1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str;
136 int rs6000_sched_restricted_insns_priority;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load;
149 /* Size of long double */
150 const char *rs6000_long_double_size_string;
151 int rs6000_long_double_type_size;
153 /* Whether -mabi=altivec has appeared */
154 int rs6000_altivec_abi;
156 /* Whether VRSAVE instructions should be generated. */
157 int rs6000_altivec_vrsave;
159 /* String from -mvrsave= option. */
160 const char *rs6000_altivec_vrsave_string;
162 /* Nonzero if we want SPE ABI extensions. */
165 /* Whether isel instructions should be generated. */
168 /* Whether SPE simd instructions should be generated. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* String from -mfloat-gprs=. */
178 const char *rs6000_float_gprs_string;
180 /* String from -misel=. */
181 const char *rs6000_isel_string;
183 /* String from -mspe=. */
184 const char *rs6000_spe_string;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0, rs6000_compare_op1;
192 int rs6000_compare_fp_p;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name = (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno = 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size = 32;
214 const char *rs6000_tls_size_string;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi;
219 /* ABI string from -mabi= option. */
220 const char *rs6000_abi_string;
222 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
226 const char *rs6000_debug_name;
227 int rs6000_debug_stack; /* debug stack applications */
228 int rs6000_debug_arg; /* debug argument handling */
230 /* Value is TRUE if register/mode pair is acceptable. */
231 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
234 static GTY(()) tree opaque_V2SI_type_node;
235 static GTY(()) tree opaque_V2SF_type_node;
236 static GTY(()) tree opaque_p_V2SI_type_node;
237 static GTY(()) tree V16QI_type_node;
238 static GTY(()) tree V2SI_type_node;
239 static GTY(()) tree V2SF_type_node;
240 static GTY(()) tree V4HI_type_node;
241 static GTY(()) tree V4SI_type_node;
242 static GTY(()) tree V4SF_type_node;
243 static GTY(()) tree V8HI_type_node;
244 static GTY(()) tree unsigned_V16QI_type_node;
245 static GTY(()) tree unsigned_V8HI_type_node;
246 static GTY(()) tree unsigned_V4SI_type_node;
247 static GTY(()) tree bool_char_type_node; /* __bool char */
248 static GTY(()) tree bool_short_type_node; /* __bool short */
249 static GTY(()) tree bool_int_type_node; /* __bool int */
250 static GTY(()) tree pixel_type_node; /* __pixel */
251 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
252 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
253 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
254 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
256 int rs6000_warn_altivec_long = 1; /* On by default. */
257 const char *rs6000_warn_altivec_long_switch;
259 const char *rs6000_traceback_name;
261 traceback_default = 0,
267 /* Flag to say the TOC is initialized */
269 char toc_label_name[10];
271 /* Alias set for saves and restores from the rs6000 stack. */
272 static GTY(()) int rs6000_sr_alias_set;
274 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
279 int rs6000_default_long_calls;
280 const char *rs6000_longcall_switch;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string;
285 int rs6000_alignment_flags;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
298 /* Target cpu costs. */
300 struct processor_costs {
301 const int mulsi; /* cost of SImode multiplication. */
302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
313 const struct processor_costs *rs6000_cost;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost = {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost = {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost = {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost = {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost = {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost = {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost = {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost = {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost = {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost = {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost = {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost = {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost = {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost = {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost = {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost = {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost = {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost = {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree, tree);
604 static rtx rs6000_generate_compare (enum rtx_code);
605 static void rs6000_maybe_dead (rtx);
606 static void rs6000_emit_stack_tie (void);
607 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
608 static rtx spe_synthesize_frame_save (rtx);
609 static bool spe_func_has_64bit_regs_p (void);
610 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
612 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
613 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
614 static unsigned rs6000_hash_constant (rtx);
615 static unsigned toc_hash_function (const void *);
616 static int toc_hash_eq (const void *, const void *);
617 static int constant_pool_expr_1 (rtx, int *, int *);
618 static bool constant_pool_expr_p (rtx);
619 static bool legitimate_small_data_p (enum machine_mode, rtx);
620 static bool legitimate_indexed_address_p (rtx, int);
621 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
622 static struct machine_function * rs6000_init_machine_status (void);
623 static bool rs6000_assemble_integer (rtx, unsigned int, int);
624 #ifdef HAVE_GAS_HIDDEN
625 static void rs6000_assemble_visibility (tree, int);
627 static int rs6000_ra_ever_killed (void);
628 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
629 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
630 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
631 static const char *rs6000_mangle_fundamental_type (tree);
632 extern const struct attribute_spec rs6000_attribute_table[];
633 static void rs6000_set_default_type_attributes (tree);
634 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
635 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
636 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
638 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
639 static bool rs6000_return_in_memory (tree, tree);
640 static void rs6000_file_start (void);
642 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
643 static void rs6000_elf_asm_out_constructor (rtx, int);
644 static void rs6000_elf_asm_out_destructor (rtx, int);
645 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
646 static void rs6000_elf_unique_section (tree, int);
647 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
648 unsigned HOST_WIDE_INT);
649 static void rs6000_elf_encode_section_info (tree, rtx, int)
651 static bool rs6000_elf_in_small_data_p (tree);
654 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
655 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
656 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
657 static void rs6000_xcoff_unique_section (tree, int);
658 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
659 unsigned HOST_WIDE_INT);
660 static const char * rs6000_xcoff_strip_name_encoding (const char *);
661 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
662 static void rs6000_xcoff_file_start (void);
663 static void rs6000_xcoff_file_end (void);
666 static bool rs6000_binds_local_p (tree);
668 static int rs6000_variable_issue (FILE *, int, rtx, int);
669 static bool rs6000_rtx_costs (rtx, int, int, int *);
670 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
671 static bool is_microcoded_insn (rtx);
672 static int is_dispatch_slot_restricted (rtx);
673 static bool is_cracked_insn (rtx);
674 static bool is_branch_slot_insn (rtx);
675 static int rs6000_adjust_priority (rtx, int);
676 static int rs6000_issue_rate (void);
677 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
678 static rtx get_next_active_insn (rtx, rtx);
679 static bool insn_terminates_group_p (rtx , enum group_termination);
680 static bool is_costly_group (rtx *, rtx);
681 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
682 static int redefine_groups (FILE *, int, rtx, rtx);
683 static int pad_groups (FILE *, int, rtx, rtx);
684 static void rs6000_sched_finish (FILE *, int);
685 static int rs6000_use_sched_lookahead (void);
686 static tree rs6000_builtin_mask_for_load (void);
688 static void rs6000_init_builtins (void);
689 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
690 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
691 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
692 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
693 static void altivec_init_builtins (void);
694 static void rs6000_common_init_builtins (void);
695 static void rs6000_init_libfuncs (void);
697 static void enable_mask_for_builtins (struct builtin_description *, int,
698 enum rs6000_builtins,
699 enum rs6000_builtins);
700 static tree build_opaque_vector_type (tree, int);
701 static void spe_init_builtins (void);
702 static rtx spe_expand_builtin (tree, rtx, bool *);
703 static rtx spe_expand_stv_builtin (enum insn_code, tree);
704 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
705 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
706 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
707 static rs6000_stack_t *rs6000_stack_info (void);
708 static void debug_stack_info (rs6000_stack_t *);
710 static rtx altivec_expand_builtin (tree, rtx, bool *);
711 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
712 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
713 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
714 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
715 static rtx altivec_expand_predicate_builtin (enum insn_code,
716 const char *, tree, rtx);
717 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
718 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
719 static void rs6000_parse_abi_options (void);
720 static void rs6000_parse_alignment_option (void);
721 static void rs6000_parse_tls_size_option (void);
722 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
723 static void rs6000_parse_float_gprs_option (void);
724 static int first_altivec_reg_to_save (void);
725 static unsigned int compute_vrsave_mask (void);
726 static void compute_save_world_info (rs6000_stack_t *info_ptr);
727 static void is_altivec_return_reg (rtx, void *);
728 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
729 int easy_vector_constant (rtx, enum machine_mode);
730 static bool is_ev64_opaque_type (tree);
731 static rtx rs6000_dwarf_register_span (rtx);
732 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
733 static rtx rs6000_tls_get_addr (void);
734 static rtx rs6000_got_sym (void);
735 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
736 static const char *rs6000_get_some_local_dynamic_name (void);
737 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
738 static rtx rs6000_complex_function_value (enum machine_mode);
739 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
740 enum machine_mode, tree);
741 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
743 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
744 tree, HOST_WIDE_INT);
745 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
748 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
751 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
752 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
753 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
754 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
757 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
759 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
761 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree, tree, int);
765 static int no_previous_def (tree function_name);
766 static tree get_prev_label (tree function_name);
767 static void rs6000_darwin_file_start (void);
770 static tree rs6000_build_builtin_va_list (void);
771 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
772 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode);
774 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
776 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
778 static int get_vsel_insn (enum machine_mode);
779 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
782 const int INSN_NOT_AVAILABLE = -1;
783 static enum machine_mode rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode;
796 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
798 /* Default register names. */
799 char rs6000_reg_names[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Initialize the GCC target structure. */
858 #undef TARGET_ATTRIBUTE_TABLE
859 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
860 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
861 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
863 #undef TARGET_ASM_ALIGNED_DI_OP
864 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
866 /* Default unaligned ops are only provided for ELF. Find the ops needed
867 for non-ELF systems. */
868 #ifndef OBJECT_FORMAT_ELF
870 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
872 #undef TARGET_ASM_UNALIGNED_HI_OP
873 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
874 #undef TARGET_ASM_UNALIGNED_SI_OP
875 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
876 #undef TARGET_ASM_UNALIGNED_DI_OP
877 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
880 #undef TARGET_ASM_UNALIGNED_HI_OP
881 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
882 #undef TARGET_ASM_UNALIGNED_SI_OP
883 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
884 #undef TARGET_ASM_UNALIGNED_DI_OP
885 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
886 #undef TARGET_ASM_ALIGNED_DI_OP
887 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
891 /* This hook deals with fixups for relocatable code and DI-mode objects
893 #undef TARGET_ASM_INTEGER
894 #define TARGET_ASM_INTEGER rs6000_assemble_integer
896 #ifdef HAVE_GAS_HIDDEN
897 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
898 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
901 #undef TARGET_HAVE_TLS
902 #define TARGET_HAVE_TLS HAVE_AS_TLS
904 #undef TARGET_CANNOT_FORCE_CONST_MEM
905 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
907 #undef TARGET_ASM_FUNCTION_PROLOGUE
908 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
909 #undef TARGET_ASM_FUNCTION_EPILOGUE
910 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
912 #undef TARGET_SCHED_VARIABLE_ISSUE
913 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
915 #undef TARGET_SCHED_ISSUE_RATE
916 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
917 #undef TARGET_SCHED_ADJUST_COST
918 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
919 #undef TARGET_SCHED_ADJUST_PRIORITY
920 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
921 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
922 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
923 #undef TARGET_SCHED_FINISH
924 #define TARGET_SCHED_FINISH rs6000_sched_finish
926 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
927 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
929 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
930 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
932 #undef TARGET_INIT_BUILTINS
933 #define TARGET_INIT_BUILTINS rs6000_init_builtins
935 #undef TARGET_EXPAND_BUILTIN
936 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
938 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
939 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
941 #undef TARGET_INIT_LIBFUNCS
942 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
945 #undef TARGET_BINDS_LOCAL_P
946 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
949 #undef TARGET_ASM_OUTPUT_MI_THUNK
950 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
952 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
953 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
955 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
956 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
958 #undef TARGET_RTX_COSTS
959 #define TARGET_RTX_COSTS rs6000_rtx_costs
960 #undef TARGET_ADDRESS_COST
961 #define TARGET_ADDRESS_COST hook_int_rtx_0
963 #undef TARGET_VECTOR_OPAQUE_P
964 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
966 #undef TARGET_DWARF_REGISTER_SPAN
967 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
969 /* On rs6000, function arguments are promoted, as are function return
971 #undef TARGET_PROMOTE_FUNCTION_ARGS
972 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
973 #undef TARGET_PROMOTE_FUNCTION_RETURN
974 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
976 #undef TARGET_RETURN_IN_MEMORY
977 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
979 #undef TARGET_SETUP_INCOMING_VARARGS
980 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
982 /* Always strict argument naming on rs6000. */
983 #undef TARGET_STRICT_ARGUMENT_NAMING
984 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
985 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
986 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
987 #undef TARGET_SPLIT_COMPLEX_ARG
988 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
989 #undef TARGET_MUST_PASS_IN_STACK
990 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
991 #undef TARGET_PASS_BY_REFERENCE
992 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
993 #undef TARGET_ARG_PARTIAL_BYTES
994 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
996 #undef TARGET_BUILD_BUILTIN_VA_LIST
997 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
999 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1000 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1002 #undef TARGET_EH_RETURN_FILTER_MODE
1003 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1005 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1006 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1008 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1009 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1011 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1019 #undef TARGET_RELAXED_ORDERING
1020 #define TARGET_RELAXED_ORDERING true
1022 struct gcc_target targetm = TARGET_INITIALIZER;
1025 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1028 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1064 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1066 rs6000_init_hard_regno_mode_ok (void)
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1076 /* If not otherwise specified by a target, make 'long double' equivalent to
1079 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1083 /* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1087 rs6000_override_options (const char *default_cpu)
1090 struct rs6000_cpu_select *ptr;
1093 /* Simplifications for entries below. */
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
1103 complete description of the processor's support.
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
1113 } const processor_target_table[]
1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1115 {"403", PROCESSOR_PPC403,
1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1122 {"601", PROCESSOR_PPC601,
1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"970", PROCESSOR_POWER4,
1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1150 {"G5", PROCESSOR_POWER4,
1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1159 {"power5", PROCESSOR_POWER5,
1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1188 rs6000_init_hard_regno_mode_ok ();
1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1191 #ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1195 #ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1200 /* Don't override by the processor default if given explicitly. */
1201 set_masks &= ~target_flags_explicit;
1203 /* Identify the processor type. */
1204 rs6000_select[0].string = default_cpu;
1205 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1209 ptr = &rs6000_select[i];
1210 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1212 for (j = 0; j < ptt_size; j++)
1213 if (! strcmp (ptr->string, processor_target_table[j].name))
1215 if (ptr->set_tune_p)
1216 rs6000_cpu = processor_target_table[j].processor;
1218 if (ptr->set_arch_p)
1220 target_flags &= ~set_masks;
1221 target_flags |= (processor_target_table[j].target_enable
1228 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1235 /* If we are optimizing big endian systems for space, use the load/store
1236 multiple and string instructions. */
1237 if (BYTES_BIG_ENDIAN && optimize_size)
1238 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1240 /* Don't allow -mmultiple or -mstring on little endian systems
1241 unless the cpu is a 750, because the hardware doesn't support the
1242 instructions used in little endian mode, and causes an alignment
1243 trap. The 750 does not cause an alignment trap (except when the
1244 target is unaligned). */
1246 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1248 if (TARGET_MULTIPLE)
1250 target_flags &= ~MASK_MULTIPLE;
1251 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1252 warning ("-mmultiple is not supported on little endian systems");
1257 target_flags &= ~MASK_STRING;
1258 if ((target_flags_explicit & MASK_STRING) != 0)
1259 warning ("-mstring is not supported on little endian systems");
1263 /* Set debug flags */
1264 if (rs6000_debug_name)
1266 if (! strcmp (rs6000_debug_name, "all"))
1267 rs6000_debug_stack = rs6000_debug_arg = 1;
1268 else if (! strcmp (rs6000_debug_name, "stack"))
1269 rs6000_debug_stack = 1;
1270 else if (! strcmp (rs6000_debug_name, "arg"))
1271 rs6000_debug_arg = 1;
1273 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1276 if (rs6000_traceback_name)
1278 if (! strncmp (rs6000_traceback_name, "full", 4))
1279 rs6000_traceback = traceback_full;
1280 else if (! strncmp (rs6000_traceback_name, "part", 4))
1281 rs6000_traceback = traceback_part;
1282 else if (! strncmp (rs6000_traceback_name, "no", 2))
1283 rs6000_traceback = traceback_none;
1285 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1286 rs6000_traceback_name);
1289 /* Set size of long double */
1290 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1291 if (rs6000_long_double_size_string)
1294 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1295 if (*tail != '\0' || (size != 64 && size != 128))
1296 error ("Unknown switch -mlong-double-%s",
1297 rs6000_long_double_size_string);
1299 rs6000_long_double_type_size = size;
1302 /* Set Altivec ABI as default for powerpc64 linux. */
1303 if (TARGET_ELF && TARGET_64BIT)
1305 rs6000_altivec_abi = 1;
1306 rs6000_altivec_vrsave = 1;
1309 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1310 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1312 rs6000_darwin64_abi = 1;
1313 /* Setting to empty string is same as "-mone-byte-bool". */
1315 darwin_one_byte_bool = "";
1317 /* Default to natural alignment, for better performance. */
1318 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1327 rs6000_parse_float_gprs_option ();
1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1339 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1342 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1345 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1352 error ("AltiVec and E500 instructions cannot coexist");
1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
1361 && !strcmp (rs6000_spe_string, "no"))
1362 rs6000_long_double_type_size = 64;
1364 else if (rs6000_select[1].string != NULL)
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1371 if (rs6000_spe_string == 0)
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1377 if (rs6000_long_double_size_string == 0)
1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1397 if (*rs6000_longcall_switch != '\0')
1398 error ("invalid option %qs", base);
1399 rs6000_default_long_calls = (base[0] != 'n');
1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1408 if (*rs6000_warn_altivec_long_switch != '\0')
1409 error ("invalid option %qs", base);
1410 rs6000_warn_altivec_long = (base[0] != 'n');
1413 /* Handle -mprioritize-restricted-insns option. */
1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1420 /* Handle -msched-costly-dep option. */
1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1423 if (rs6000_sched_costly_dep_str)
1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1426 rs6000_sched_costly_dep = no_dep_costly;
1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1428 rs6000_sched_costly_dep = all_deps_costly;
1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1437 /* Handle -minsert-sched-nops option. */
1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1440 if (rs6000_sched_insert_nops_str)
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1443 rs6000_sched_insert_nops = sched_finish_none;
1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1452 #ifdef TARGET_REGNAMES
1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
1455 if (TARGET_REGNAMES)
1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1467 target_flags |= MASK_AIX_STRUCT_RET;
1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1488 /* Set branch target alignment, if not optimizing for size. */
1491 if (rs6000_sched_groups)
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1497 if (align_loops <= 0)
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1511 if (DEFAULT_ABI != ABI_AIX)
1512 targetm.calls.split_complex_arg = NULL;
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1564 case PROCESSOR_PPC620:
1565 rs6000_cost = &ppc620_cost;
1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1595 /* Implement targetm.vectorize.builtin_mask_for_load. */
1597 rs6000_builtin_mask_for_load (void)
1600 return altivec_builtin_mask_for_load;
1605 /* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
1611 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1615 else if (!strcmp (value, "yes"))
1617 else if (!strcmp (value, "no"))
1620 error ("unknown -m%s= option specified: '%s'", name, value);
1623 /* Handle -mabi= options. */
1625 rs6000_parse_abi_options (void)
1627 if (rs6000_abi_string == 0)
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
1631 rs6000_altivec_abi = 1;
1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
1636 else if (! strcmp (rs6000_abi_string, "spe"))
1639 rs6000_altivec_abi = 0;
1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1663 /* Handle -mfloat-gprs= options. */
1665 rs6000_parse_float_gprs_option (void)
1667 if (rs6000_float_gprs_string == 0)
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1677 error ("invalid option for -mfloat-gprs");
1680 /* Handle -malign-XXXXXX options. */
1682 rs6000_parse_alignment_option (void)
1684 if (rs6000_alignment_string == 0)
1686 else if (! strcmp (rs6000_alignment_string, "power"))
1688 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1689 some C library functions, so warn about it. The flag may be
1690 useful for performance studies from time to time though, so
1691 don't disable it entirely. */
1692 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1693 warning ("-malign-power is not supported for 64-bit Darwin;"
1694 " it is incompatible with the installed C and C++ libraries");
1695 rs6000_alignment_flags = MASK_ALIGN_POWER;
1697 else if (! strcmp (rs6000_alignment_string, "natural"))
1698 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1700 error ("unknown -malign-XXXXX option specified: '%s'",
1701 rs6000_alignment_string);
1704 /* Validate and record the size specified with the -mtls-size option. */
1707 rs6000_parse_tls_size_option (void)
1709 if (rs6000_tls_size_string == 0)
1711 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1712 rs6000_tls_size = 16;
1713 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1714 rs6000_tls_size = 32;
1715 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1716 rs6000_tls_size = 64;
1718 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1722 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1726 /* Do anything needed at the start of the asm file. */
1729 rs6000_file_start (void)
1733 const char *start = buffer;
1734 struct rs6000_cpu_select *ptr;
1735 const char *default_cpu = TARGET_CPU_DEFAULT;
1736 FILE *file = asm_out_file;
1738 default_file_start ();
1740 #ifdef TARGET_BI_ARCH
1741 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1745 if (flag_verbose_asm)
1747 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1748 rs6000_select[0].string = default_cpu;
1750 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1752 ptr = &rs6000_select[i];
1753 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1755 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1760 #ifdef USING_ELFOS_H
1761 switch (rs6000_sdata)
1763 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1764 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1765 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1766 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1769 if (rs6000_sdata && g_switch_value)
1771 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1781 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1789 /* Return nonzero if this function is known to have a null epilogue. */
1792 direct_return (void)
1794 if (reload_completed)
1796 rs6000_stack_t *info = rs6000_stack_info ();
1798 if (info->first_gp_reg_save == 32
1799 && info->first_fp_reg_save == 64
1800 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1801 && ! info->lr_save_p
1802 && ! info->cr_save_p
1803 && info->vrsave_mask == 0
1811 /* Return the number of instructions it takes to form a constant in an
1812 integer register. */
1815 num_insns_constant_wide (HOST_WIDE_INT value)
1817 /* signed constant loadable with {cal|addi} */
1818 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1821 /* constant loadable with {cau|addis} */
1822 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1825 #if HOST_BITS_PER_WIDE_INT == 64
1826 else if (TARGET_POWERPC64)
1828 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1829 HOST_WIDE_INT high = value >> 31;
1831 if (high == 0 || high == -1)
1837 return num_insns_constant_wide (high) + 1;
1839 return (num_insns_constant_wide (high)
1840 + num_insns_constant_wide (low) + 1);
1849 num_insns_constant (rtx op, enum machine_mode mode)
1851 if (GET_CODE (op) == CONST_INT)
1853 #if HOST_BITS_PER_WIDE_INT == 64
1854 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1855 && mask64_operand (op, mode))
1859 return num_insns_constant_wide (INTVAL (op));
1862 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1867 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1869 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1872 else if (GET_CODE (op) == CONST_DOUBLE)
1878 int endian = (WORDS_BIG_ENDIAN == 0);
1880 if (mode == VOIDmode || mode == DImode)
1882 high = CONST_DOUBLE_HIGH (op);
1883 low = CONST_DOUBLE_LOW (op);
1887 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1890 low = l[1 - endian];
1894 return (num_insns_constant_wide (low)
1895 + num_insns_constant_wide (high));
1899 if (high == 0 && low >= 0)
1900 return num_insns_constant_wide (low);
1902 else if (high == -1 && low < 0)
1903 return num_insns_constant_wide (low);
1905 else if (mask64_operand (op, mode))
1909 return num_insns_constant_wide (high) + 1;
1912 return (num_insns_constant_wide (high)
1913 + num_insns_constant_wide (low) + 1);
1921 /* Returns the constant for the splat instruction, if exists. */
1924 easy_vector_splat_const (int cst, enum machine_mode mode)
1929 if (EASY_VECTOR_15 (cst)
1930 || EASY_VECTOR_15_ADD_SELF (cst))
1932 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1938 if (EASY_VECTOR_15 (cst)
1939 || EASY_VECTOR_15_ADD_SELF (cst))
1941 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1947 if (EASY_VECTOR_15 (cst)
1948 || EASY_VECTOR_15_ADD_SELF (cst))
1956 /* Return nonzero if all elements of a vector have the same value. */
1959 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1963 units = CONST_VECTOR_NUNITS (op);
1965 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1966 for (i = 1; i < units; ++i)
1967 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1969 if (i == units && easy_vector_splat_const (cst, mode))
1974 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1977 gen_easy_vector_constant_add_self (rtx op)
1981 units = GET_MODE_NUNITS (GET_MODE (op));
1982 v = rtvec_alloc (units);
1984 for (i = 0; i < units; i++)
1986 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1987 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1991 output_vec_const_move (rtx *operands)
1994 enum machine_mode mode;
2000 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2001 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2002 mode = GET_MODE (dest);
2006 if (zero_constant (vec, mode))
2007 return "vxor %0,%0,%0";
2008 else if (easy_vector_constant (vec, mode))
2010 operands[1] = GEN_INT (cst);
2014 if (EASY_VECTOR_15 (cst))
2016 operands[1] = GEN_INT (cst);
2017 return "vspltisw %0,%1";
2019 else if (EASY_VECTOR_15_ADD_SELF (cst))
2025 if (EASY_VECTOR_15 (cst))
2027 operands[1] = GEN_INT (cst);
2028 return "vspltish %0,%1";
2030 else if (EASY_VECTOR_15_ADD_SELF (cst))
2036 if (EASY_VECTOR_15 (cst))
2038 operands[1] = GEN_INT (cst);
2039 return "vspltisb %0,%1";
2041 else if (EASY_VECTOR_15_ADD_SELF (cst))
2054 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2055 pattern of V1DI, V4HI, and V2SF.
2057 FIXME: We should probably return # and add post reload
2058 splitters for these, but this way is so easy ;-). */
2059 operands[1] = GEN_INT (cst);
2060 operands[2] = GEN_INT (cst2);
2062 return "li %0,%1\n\tevmergelo %0,%0,%0";
2064 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2071 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2074 if (GET_CODE (op) == CONST_INT)
2076 HOST_WIDE_INT c, lsb;
2081 /* Disallow all zeros. */
2085 /* We can use a single rlwinm insn if no upper bits of C are set
2086 AND there are zero, one or two transitions in the _whole_ of
2088 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2090 /* We don't change the number of transitions by inverting,
2091 so make sure we start with the LS bit zero. */
2095 /* Find the first transition. */
2098 /* Invert to look for a second transition. */
2101 /* Erase first transition. */
2104 /* Find the second transition. */
2107 /* Invert to look for a third transition. */
2110 /* Erase second transition. */
2113 if (one_ok && !(allow_one || c))
2116 /* Find the third transition (if any). */
2119 /* Match if all the bits above are 1's (or c is zero). */
2125 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2126 implement ANDing by the mask IN. */
2128 build_mask64_2_operands (rtx in, rtx *out)
2130 #if HOST_BITS_PER_WIDE_INT >= 64
2131 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2134 if (GET_CODE (in) != CONST_INT)
2140 /* Assume c initially something like 0x00fff000000fffff. The idea
2141 is to rotate the word so that the middle ^^^^^^ group of zeros
2142 is at the MS end and can be cleared with an rldicl mask. We then
2143 rotate back and clear off the MS ^^ group of zeros with a
2145 c = ~c; /* c == 0xff000ffffff00000 */
2146 lsb = c & -c; /* lsb == 0x0000000000100000 */
2147 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2148 c = ~c; /* c == 0x00fff000000fffff */
2149 c &= -lsb; /* c == 0x00fff00000000000 */
2150 lsb = c & -c; /* lsb == 0x0000100000000000 */
2151 c = ~c; /* c == 0xff000fffffffffff */
2152 c &= -lsb; /* c == 0xff00000000000000 */
2154 while ((lsb >>= 1) != 0)
2155 shift++; /* shift == 44 on exit from loop */
2156 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2157 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2158 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2162 /* Assume c initially something like 0xff000f0000000000. The idea
2163 is to rotate the word so that the ^^^ middle group of zeros
2164 is at the LS end and can be cleared with an rldicr mask. We then
2165 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2167 lsb = c & -c; /* lsb == 0x0000010000000000 */
2168 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2169 c = ~c; /* c == 0x00fff0ffffffffff */
2170 c &= -lsb; /* c == 0x00fff00000000000 */
2171 lsb = c & -c; /* lsb == 0x0000100000000000 */
2172 c = ~c; /* c == 0xff000fffffffffff */
2173 c &= -lsb; /* c == 0xff00000000000000 */
2175 while ((lsb >>= 1) != 0)
2176 shift++; /* shift == 44 on exit from loop */
2177 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2178 m1 >>= shift; /* m1 == 0x0000000000000fff */
2179 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2182 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2183 masks will be all 1's. We are guaranteed more than one transition. */
2184 out[0] = GEN_INT (64 - shift);
2185 out[1] = GEN_INT (m1);
2186 out[2] = GEN_INT (shift);
2187 out[3] = GEN_INT (m2);
2195 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2198 invalid_e500_subreg (rtx op, enum machine_mode mode)
2200 /* Reject (subreg:SI (reg:DF)). */
2201 if (GET_CODE (op) == SUBREG
2203 && REG_P (SUBREG_REG (op))
2204 && GET_MODE (SUBREG_REG (op)) == DFmode)
2207 /* Reject (subreg:DF (reg:DI)). */
2208 if (GET_CODE (op) == SUBREG
2210 && REG_P (SUBREG_REG (op))
2211 && GET_MODE (SUBREG_REG (op)) == DImode)
2217 /* Darwin, AIX increases natural record alignment to doubleword if the first
2218 field is an FP double while the FP fields remain word aligned. */
2221 rs6000_special_round_type_align (tree type, int computed, int specified)
2223 tree field = TYPE_FIELDS (type);
2225 /* Skip all non field decls */
2226 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2227 field = TREE_CHAIN (field);
2229 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2230 return MAX (computed, specified);
2232 return MAX (MAX (computed, specified), 64);
2235 /* Return 1 for an operand in small memory on V.4/eabi. */
2238 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2239 enum machine_mode mode ATTRIBUTE_UNUSED)
2244 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2247 if (DEFAULT_ABI != ABI_V4)
2250 if (GET_CODE (op) == SYMBOL_REF)
2253 else if (GET_CODE (op) != CONST
2254 || GET_CODE (XEXP (op, 0)) != PLUS
2255 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2256 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2261 rtx sum = XEXP (op, 0);
2262 HOST_WIDE_INT summand;
2264 /* We have to be careful here, because it is the referenced address
2265 that must be 32k from _SDA_BASE_, not just the symbol. */
2266 summand = INTVAL (XEXP (sum, 1));
2267 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2270 sym_ref = XEXP (sum, 0);
2273 return SYMBOL_REF_SMALL_P (sym_ref);
2279 /* Return true if either operand is a general purpose register. */
2282 gpr_or_gpr_p (rtx op0, rtx op1)
2284 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2285 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2289 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2292 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2294 switch (GET_CODE (op))
2297 if (RS6000_SYMBOL_REF_TLS_P (op))
2299 else if (CONSTANT_POOL_ADDRESS_P (op))
2301 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2309 else if (! strcmp (XSTR (op, 0), toc_label_name))
2318 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2319 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2321 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2330 constant_pool_expr_p (rtx op)
2334 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2338 toc_relative_expr_p (rtx op)
2342 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2346 legitimate_constant_pool_address_p (rtx x)
2349 && GET_CODE (x) == PLUS
2350 && GET_CODE (XEXP (x, 0)) == REG
2351 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2352 && constant_pool_expr_p (XEXP (x, 1)));
2356 legitimate_small_data_p (enum machine_mode mode, rtx x)
2358 return (DEFAULT_ABI == ABI_V4
2359 && !flag_pic && !TARGET_TOC
2360 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2361 && small_data_operand (x, mode));
2364 /* SPE offset addressing is limited to 5-bits worth of double words. */
2365 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2368 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2370 unsigned HOST_WIDE_INT offset, extra;
2372 if (GET_CODE (x) != PLUS)
2374 if (GET_CODE (XEXP (x, 0)) != REG)
2376 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2378 if (legitimate_constant_pool_address_p (x))
2380 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2383 offset = INTVAL (XEXP (x, 1));
2391 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2392 which leaves the only valid constant offset of zero, which by
2393 canonicalization rules is also invalid. */
2400 /* SPE vector modes. */
2401 return SPE_CONST_OFFSET_OK (offset);
2404 if (TARGET_E500_DOUBLE)
2405 return SPE_CONST_OFFSET_OK (offset);
2408 /* On e500v2, we may have:
2410 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2412 Which gets addressed with evldd instructions. */
2413 if (TARGET_E500_DOUBLE)
2414 return SPE_CONST_OFFSET_OK (offset);
2416 if (mode == DFmode || !TARGET_POWERPC64)
2418 else if (offset & 3)
2424 if (mode == TFmode || !TARGET_POWERPC64)
2426 else if (offset & 3)
2437 return (offset < 0x10000) && (offset + extra < 0x10000);
2441 legitimate_indexed_address_p (rtx x, int strict)
2445 if (GET_CODE (x) != PLUS)
2451 if (!REG_P (op0) || !REG_P (op1))
2454 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2455 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2456 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2457 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2461 legitimate_indirect_address_p (rtx x, int strict)
2463 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2467 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2469 if (!TARGET_MACHO || !flag_pic
2470 || mode != SImode || GET_CODE (x) != MEM)
2474 if (GET_CODE (x) != LO_SUM)
2476 if (GET_CODE (XEXP (x, 0)) != REG)
2478 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2482 return CONSTANT_P (x);
2486 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2488 if (GET_CODE (x) != LO_SUM)
2490 if (GET_CODE (XEXP (x, 0)) != REG)
2492 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2494 /* Restrict addressing for DI because of our SUBREG hackery. */
2495 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2499 if (TARGET_ELF || TARGET_MACHO)
2501 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2505 if (GET_MODE_NUNITS (mode) != 1)
2507 if (GET_MODE_BITSIZE (mode) > 64
2508 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2509 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2512 return CONSTANT_P (x);
2519 /* Try machine-dependent ways of modifying an illegitimate address
2520 to be legitimate. If we find one, return the new, valid address.
2521 This is used from only one place: `memory_address' in explow.c.
2523 OLDX is the address as it was before break_out_memory_refs was
2524 called. In some cases it is useful to look at this to decide what
2527 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2529 It is always safe for this function to do nothing. It exists to
2530 recognize opportunities to optimize the output.
2532 On RS/6000, first check for the sum of a register with a constant
2533 integer that is out of range. If so, generate code to add the
2534 constant with the low-order 16 bits masked to the register and force
2535 this result into another register (this can be done with `cau').
2536 Then generate an address of REG+(CONST&0xffff), allowing for the
2537 possibility of bit 16 being a one.
2539 Then check for the sum of a register and something not constant, try to
2540 load the other things into a register and return the sum. */
2543 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2544 enum machine_mode mode)
2546 if (GET_CODE (x) == SYMBOL_REF)
2548 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2550 return rs6000_legitimize_tls_address (x, model);
2553 if (GET_CODE (x) == PLUS
2554 && GET_CODE (XEXP (x, 0)) == REG
2555 && GET_CODE (XEXP (x, 1)) == CONST_INT
2556 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2558 HOST_WIDE_INT high_int, low_int;
2560 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2561 high_int = INTVAL (XEXP (x, 1)) - low_int;
2562 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2563 GEN_INT (high_int)), 0);
2564 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2566 else if (GET_CODE (x) == PLUS
2567 && GET_CODE (XEXP (x, 0)) == REG
2568 && GET_CODE (XEXP (x, 1)) != CONST_INT
2569 && GET_MODE_NUNITS (mode) == 1
2570 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2572 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2574 && (TARGET_POWERPC64 || mode != DImode)
2577 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2578 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2580 else if (ALTIVEC_VECTOR_MODE (mode))
2584 /* Make sure both operands are registers. */
2585 if (GET_CODE (x) == PLUS)
2586 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2587 force_reg (Pmode, XEXP (x, 1)));
2589 reg = force_reg (Pmode, x);
2592 else if (SPE_VECTOR_MODE (mode)
2593 || (TARGET_E500_DOUBLE && (mode == DFmode
2594 || mode == DImode)))
2598 /* We accept [reg + reg] and [reg + OFFSET]. */
2600 if (GET_CODE (x) == PLUS)
2602 rtx op1 = XEXP (x, 0);
2603 rtx op2 = XEXP (x, 1);
2605 op1 = force_reg (Pmode, op1);
2607 if (GET_CODE (op2) != REG
2608 && (GET_CODE (op2) != CONST_INT
2609 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2610 op2 = force_reg (Pmode, op2);
2612 return gen_rtx_PLUS (Pmode, op1, op2);
2615 return force_reg (Pmode, x);
2621 && GET_CODE (x) != CONST_INT
2622 && GET_CODE (x) != CONST_DOUBLE
2624 && GET_MODE_NUNITS (mode) == 1
2625 && (GET_MODE_BITSIZE (mode) <= 32
2626 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2628 rtx reg = gen_reg_rtx (Pmode);
2629 emit_insn (gen_elf_high (reg, x));
2630 return gen_rtx_LO_SUM (Pmode, reg, x);
2632 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2635 && ! MACHO_DYNAMIC_NO_PIC_P
2637 && GET_CODE (x) != CONST_INT
2638 && GET_CODE (x) != CONST_DOUBLE
2640 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2644 rtx reg = gen_reg_rtx (Pmode);
2645 emit_insn (gen_macho_high (reg, x));
2646 return gen_rtx_LO_SUM (Pmode, reg, x);
2649 && constant_pool_expr_p (x)
2650 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2652 return create_TOC_reference (x);
2658 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2659 We need to emit DTP-relative relocations. */
2662 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2667 fputs ("\t.long\t", file);
2670 fputs (DOUBLE_INT_ASM_OP, file);
2675 output_addr_const (file, x);
2676 fputs ("@dtprel+0x8000", file);
2679 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2681 static GTY(()) rtx rs6000_tls_symbol;
2683 rs6000_tls_get_addr (void)
2685 if (!rs6000_tls_symbol)
2686 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2688 return rs6000_tls_symbol;
2691 /* Construct the SYMBOL_REF for TLS GOT references. */
2693 static GTY(()) rtx rs6000_got_symbol;
2695 rs6000_got_sym (void)
2697 if (!rs6000_got_symbol)
2699 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2700 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2701 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2704 return rs6000_got_symbol;
2707 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2708 this (thread-local) address. */
2711 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2715 dest = gen_reg_rtx (Pmode);
2716 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2722 tlsreg = gen_rtx_REG (Pmode, 13);
2723 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2727 tlsreg = gen_rtx_REG (Pmode, 2);
2728 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2732 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2736 tmp = gen_reg_rtx (Pmode);
2739 tlsreg = gen_rtx_REG (Pmode, 13);
2740 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2744 tlsreg = gen_rtx_REG (Pmode, 2);
2745 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2749 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2751 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2756 rtx r3, got, tga, tmp1, tmp2, eqv;
2759 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2763 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2766 rtx gsym = rs6000_got_sym ();
2767 got = gen_reg_rtx (Pmode);
2769 rs6000_emit_move (got, gsym, Pmode);
2772 rtx tempLR, tmp3, mem;
2775 tempLR = gen_reg_rtx (Pmode);
2776 tmp1 = gen_reg_rtx (Pmode);
2777 tmp2 = gen_reg_rtx (Pmode);
2778 tmp3 = gen_reg_rtx (Pmode);
2779 mem = gen_const_mem (Pmode, tmp1);
2781 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
2782 emit_move_insn (tmp1, tempLR);
2783 emit_move_insn (tmp2, mem);
2784 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2785 last = emit_move_insn (got, tmp3);
2786 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2788 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2790 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2796 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2798 r3 = gen_rtx_REG (Pmode, 3);
2800 insn = gen_tls_gd_64 (r3, got, addr);
2802 insn = gen_tls_gd_32 (r3, got, addr);
2805 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2806 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2807 insn = emit_call_insn (insn);
2808 CONST_OR_PURE_CALL_P (insn) = 1;
2809 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2810 insn = get_insns ();
2812 emit_libcall_block (insn, dest, r3, addr);
2814 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2816 r3 = gen_rtx_REG (Pmode, 3);
2818 insn = gen_tls_ld_64 (r3, got);
2820 insn = gen_tls_ld_32 (r3, got);
2823 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2824 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2825 insn = emit_call_insn (insn);
2826 CONST_OR_PURE_CALL_P (insn) = 1;
2827 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2828 insn = get_insns ();
2830 tmp1 = gen_reg_rtx (Pmode);
2831 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2833 emit_libcall_block (insn, tmp1, r3, eqv);
2834 if (rs6000_tls_size == 16)
2837 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2839 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2841 else if (rs6000_tls_size == 32)
2843 tmp2 = gen_reg_rtx (Pmode);
2845 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2847 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2850 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2852 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2856 tmp2 = gen_reg_rtx (Pmode);
2858 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2860 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2862 insn = gen_rtx_SET (Pmode, dest,
2863 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2869 /* IE, or 64 bit offset LE. */
2870 tmp2 = gen_reg_rtx (Pmode);
2872 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2874 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2877 insn = gen_tls_tls_64 (dest, tmp2, addr);
2879 insn = gen_tls_tls_32 (dest, tmp2, addr);
2887 /* Return 1 if X contains a thread-local symbol. */
2890 rs6000_tls_referenced_p (rtx x)
2892 if (! TARGET_HAVE_TLS)
2895 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2898 /* Return 1 if *X is a thread-local symbol. This is the same as
2899 rs6000_tls_symbol_ref except for the type of the unused argument. */
2902 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2904 return RS6000_SYMBOL_REF_TLS_P (*x);
2907 /* The convention appears to be to define this wherever it is used.
2908 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2909 is now used here. */
2910 #ifndef REG_MODE_OK_FOR_BASE_P
2911 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2914 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2915 replace the input X, or the original X if no replacement is called for.
2916 The output parameter *WIN is 1 if the calling macro should goto WIN,
2919 For RS/6000, we wish to handle large displacements off a base
2920 register by splitting the addend across an addiu/addis and the mem insn.
2921 This cuts number of extra insns needed from 3 to 1.
2923 On Darwin, we use this to generate code for floating point constants.
2924 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2925 The Darwin code is inside #if TARGET_MACHO because only then is
2926 machopic_function_base_name() defined. */
2928 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2929 int opnum, int type,
2930 int ind_levels ATTRIBUTE_UNUSED, int *win)
2932 /* We must recognize output that we have already generated ourselves. */
2933 if (GET_CODE (x) == PLUS
2934 && GET_CODE (XEXP (x, 0)) == PLUS
2935 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2936 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2937 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2939 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2940 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2941 opnum, (enum reload_type)type);
2947 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2948 && GET_CODE (x) == LO_SUM
2949 && GET_CODE (XEXP (x, 0)) == PLUS
2950 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2951 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2952 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2953 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2954 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
2955 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
2956 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
2958 /* Result of previous invocation of this function on Darwin
2959 floating point constant. */
2960 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2961 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
2962 opnum, (enum reload_type)type);
2968 /* Force ld/std non-word aligned offset into base register by wrapping
2970 if (GET_CODE (x) == PLUS
2971 && GET_CODE (XEXP (x, 0)) == REG
2972 && REGNO (XEXP (x, 0)) < 32
2973 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2974 && GET_CODE (XEXP (x, 1)) == CONST_INT
2975 && (INTVAL (XEXP (x, 1)) & 3) != 0
2976 && !ALTIVEC_VECTOR_MODE (mode)
2977 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
2978 && TARGET_POWERPC64)
2980 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
2981 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2982 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2983 opnum, (enum reload_type) type);
2988 if (GET_CODE (x) == PLUS
2989 && GET_CODE (XEXP (x, 0)) == REG
2990 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2991 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
2992 && GET_CODE (XEXP (x, 1)) == CONST_INT
2993 && !SPE_VECTOR_MODE (mode)
2994 && !(TARGET_E500_DOUBLE && (mode == DFmode
2996 && !ALTIVEC_VECTOR_MODE (mode))
2998 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
2999 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3001 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3003 /* Check for 32-bit overflow. */
3004 if (high + low != val)
3010 /* Reload the high part into a base reg; leave the low part
3011 in the mem directly. */
3013 x = gen_rtx_PLUS (GET_MODE (x),
3014 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3018 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3019 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3020 opnum, (enum reload_type)type);
3026 if (GET_CODE (x) == SYMBOL_REF
3027 && DEFAULT_ABI == ABI_DARWIN
3028 && !ALTIVEC_VECTOR_MODE (mode)
3029 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3030 /* Don't do this for TFmode, since the result isn't offsettable.
3031 The same goes for DImode without 64-bit gprs. */
3033 && (mode != DImode || TARGET_POWERPC64))
3037 rtx offset = gen_rtx_CONST (Pmode,
3038 gen_rtx_MINUS (Pmode, x,
3039 machopic_function_base_sym ()));
3040 x = gen_rtx_LO_SUM (GET_MODE (x),
3041 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3042 gen_rtx_HIGH (Pmode, offset)), offset);
3045 x = gen_rtx_LO_SUM (GET_MODE (x),
3046 gen_rtx_HIGH (Pmode, x), x);
3048 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3049 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3050 opnum, (enum reload_type)type);
3057 && constant_pool_expr_p (x)
3058 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3060 (x) = create_TOC_reference (x);
3068 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3069 that is a valid memory address for an instruction.
3070 The MODE argument is the machine mode for the MEM expression
3071 that wants to use this address.
3073 On the RS/6000, there are four valid address: a SYMBOL_REF that
3074 refers to a constant pool entry of an address (or the sum of it
3075 plus a constant), a short (16-bit signed) constant plus a register,
3076 the sum of two registers, or a register indirect, possibly with an
3077 auto-increment. For DFmode and DImode with a constant plus register,
3078 we must ensure that both words are addressable or PowerPC64 with offset
3081 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3082 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3083 adjacent memory cells are accessed by adding word-sized offsets
3084 during assembly output. */
3086 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3088 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3090 && ALTIVEC_VECTOR_MODE (mode)
3091 && GET_CODE (x) == AND
3092 && GET_CODE (XEXP (x, 1)) == CONST_INT
3093 && INTVAL (XEXP (x, 1)) == -16)
3096 if (RS6000_SYMBOL_REF_TLS_P (x))
3098 if (legitimate_indirect_address_p (x, reg_ok_strict))
3100 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3101 && !ALTIVEC_VECTOR_MODE (mode)
3102 && !SPE_VECTOR_MODE (mode)
3103 /* Restrict addressing for DI because of our SUBREG hackery. */
3104 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3106 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3108 if (legitimate_small_data_p (mode, x))
3110 if (legitimate_constant_pool_address_p (x))
3112 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3114 && GET_CODE (x) == PLUS
3115 && GET_CODE (XEXP (x, 0)) == REG
3116 && (XEXP (x, 0) == virtual_stack_vars_rtx
3117 || XEXP (x, 0) == arg_pointer_rtx)
3118 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3120 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3124 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3126 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3127 && (TARGET_POWERPC64 || mode != DImode)
3128 && legitimate_indexed_address_p (x, reg_ok_strict))
3130 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3135 /* Go to LABEL if ADDR (a legitimate address expression)
3136 has an effect that depends on the machine mode it is used for.
3138 On the RS/6000 this is true of all integral offsets (since AltiVec
3139 modes don't allow them) or is a pre-increment or decrement.
3141 ??? Except that due to conceptual problems in offsettable_address_p
3142 we can't really report the problems of integral offsets. So leave
3143 this assuming that the adjustable offset must be valid for the
3144 sub-words of a TFmode operand, which is what we had before. */
3147 rs6000_mode_dependent_address (rtx addr)
3149 switch (GET_CODE (addr))
3152 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3154 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3155 return val + 12 + 0x8000 >= 0x10000;
3164 return TARGET_UPDATE;
3173 /* Return number of consecutive hard regs needed starting at reg REGNO
3174 to hold something of mode MODE.
3175 This is ordinarily the length in words of a value of mode MODE
3176 but can be less for certain modes in special long registers.
3178 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3179 scalar instructions. The upper 32 bits are only available to the
3182 POWER and PowerPC GPRs hold 32 bits worth;
3183 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3186 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3188 if (FP_REGNO_P (regno))
3189 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3191 if (TARGET_E500_DOUBLE && mode == DFmode)
3194 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3195 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3197 if (ALTIVEC_REGNO_P (regno))
3199 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3201 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3204 /* Change register usage conditional on target flags. */
3206 rs6000_conditional_register_usage (void)
3210 /* Set MQ register fixed (already call_used) if not POWER
3211 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3216 /* 64-bit AIX reserves GPR13 for thread-private data. */
3218 fixed_regs[13] = call_used_regs[13]
3219 = call_really_used_regs[13] = 1;
3221 /* Conditionally disable FPRs. */
3222 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3223 for (i = 32; i < 64; i++)
3224 fixed_regs[i] = call_used_regs[i]
3225 = call_really_used_regs[i] = 1;
3227 if (DEFAULT_ABI == ABI_V4
3228 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3230 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3232 if (DEFAULT_ABI == ABI_V4
3233 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3235 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3236 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3237 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3239 if (DEFAULT_ABI == ABI_DARWIN
3240 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3241 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3242 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3243 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3244 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3246 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3247 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3248 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3251 global_regs[VSCR_REGNO] = 1;
3255 global_regs[SPEFSCR_REGNO] = 1;
3256 fixed_regs[FIXED_SCRATCH]
3257 = call_used_regs[FIXED_SCRATCH]
3258 = call_really_used_regs[FIXED_SCRATCH] = 1;
3261 if (! TARGET_ALTIVEC)
3263 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3264 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3265 call_really_used_regs[VRSAVE_REGNO] = 1;
3268 if (TARGET_ALTIVEC_ABI)
3269 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3270 call_used_regs[i] = call_really_used_regs[i] = 1;
3273 /* Try to output insns to set TARGET equal to the constant C if it can
3274 be done in less than N insns. Do all computations in MODE.
3275 Returns the place where the output has been placed if it can be
3276 done and the insns have been emitted. If it would take more than N
3277 insns, zero is returned and no insns and emitted. */
3280 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3281 rtx source, int n ATTRIBUTE_UNUSED)
3283 rtx result, insn, set;
3284 HOST_WIDE_INT c0, c1;
3286 if (mode == QImode || mode == HImode)
3289 dest = gen_reg_rtx (mode);
3290 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3293 else if (mode == SImode)
3295 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3297 emit_insn (gen_rtx_SET (VOIDmode, result,
3298 GEN_INT (INTVAL (source)
3299 & (~ (HOST_WIDE_INT) 0xffff))));
3300 emit_insn (gen_rtx_SET (VOIDmode, dest,
3301 gen_rtx_IOR (SImode, result,
3302 GEN_INT (INTVAL (source) & 0xffff))));
3305 else if (mode == DImode)
3307 if (GET_CODE (source) == CONST_INT)
3309 c0 = INTVAL (source);
3312 else if (GET_CODE (source) == CONST_DOUBLE)
3314 #if HOST_BITS_PER_WIDE_INT >= 64
3315 c0 = CONST_DOUBLE_LOW (source);
3318 c0 = CONST_DOUBLE_LOW (source);
3319 c1 = CONST_DOUBLE_HIGH (source);
3325 result = rs6000_emit_set_long_const (dest, c0, c1);
3330 insn = get_last_insn ();
3331 set = single_set (insn);
3332 if (! CONSTANT_P (SET_SRC (set)))
3333 set_unique_reg_note (insn, REG_EQUAL, source);
3338 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3339 fall back to a straight forward decomposition. We do this to avoid
3340 exponential run times encountered when looking for longer sequences
3341 with rs6000_emit_set_const. */
3343 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3345 if (!TARGET_POWERPC64)
3347 rtx operand1, operand2;
3349 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3351 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3353 emit_move_insn (operand1, GEN_INT (c1));
3354 emit_move_insn (operand2, GEN_INT (c2));
3358 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3361 ud2 = (c1 & 0xffff0000) >> 16;
3362 #if HOST_BITS_PER_WIDE_INT >= 64
3366 ud4 = (c2 & 0xffff0000) >> 16;
3368 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3369 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3372 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3374 emit_move_insn (dest, GEN_INT (ud1));
3377 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3378 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3381 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3384 emit_move_insn (dest, GEN_INT (ud2 << 16));
3386 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3388 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3389 || (ud4 == 0 && ! (ud3 & 0x8000)))
3392 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3395 emit_move_insn (dest, GEN_INT (ud3 << 16));
3398 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3399 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3401 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3406 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3409 emit_move_insn (dest, GEN_INT (ud4 << 16));
3412 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3414 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3416 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3417 GEN_INT (ud2 << 16)));
3419 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3425 /* Helper for the following. Get rid of [r+r] memory refs
3426 in cases where it won't work (TImode, TFmode). */
3429 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3431 if (GET_CODE (operands[0]) == MEM
3432 && GET_CODE (XEXP (operands[0], 0)) != REG
3433 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3434 && ! reload_in_progress)
3436 = replace_equiv_address (operands[0],
3437 copy_addr_to_reg (XEXP (operands[0], 0)));
3439 if (GET_CODE (operands[1]) == MEM
3440 && GET_CODE (XEXP (operands[1], 0)) != REG
3441 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3442 && ! reload_in_progress)
3444 = replace_equiv_address (operands[1],
3445 copy_addr_to_reg (XEXP (operands[1], 0)));
3448 /* Emit a move from SOURCE to DEST in mode MODE. */
3450 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3454 operands[1] = source;
3456 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3457 if (GET_CODE (operands[1]) == CONST_DOUBLE
3458 && ! FLOAT_MODE_P (mode)
3459 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3461 /* FIXME. This should never happen. */
3462 /* Since it seems that it does, do the safe thing and convert
3464 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3466 if (GET_CODE (operands[1]) == CONST_DOUBLE
3467 && ! FLOAT_MODE_P (mode)
3468 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3469 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3470 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3471 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3474 /* Check if GCC is setting up a block move that will end up using FP
3475 registers as temporaries. We must make sure this is acceptable. */
3476 if (GET_CODE (operands[0]) == MEM
3477 && GET_CODE (operands[1]) == MEM
3479 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3480 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3481 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3482 ? 32 : MEM_ALIGN (operands[0])))
3483 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3485 : MEM_ALIGN (operands[1]))))
3486 && ! MEM_VOLATILE_P (operands [0])
3487 && ! MEM_VOLATILE_P (operands [1]))
3489 emit_move_insn (adjust_address (operands[0], SImode, 0),
3490 adjust_address (operands[1], SImode, 0));
3491 emit_move_insn (adjust_address (operands[0], SImode, 4),
3492 adjust_address (operands[1], SImode, 4));
3496 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3497 && !gpc_reg_operand (operands[1], mode))
3498 operands[1] = force_reg (mode, operands[1]);
3500 if (mode == SFmode && ! TARGET_POWERPC
3501 && TARGET_HARD_FLOAT && TARGET_FPRS
3502 && GET_CODE (operands[0]) == MEM)
3506 if (reload_in_progress || reload_completed)
3507 regnum = true_regnum (operands[1]);
3508 else if (GET_CODE (operands[1]) == REG)
3509 regnum = REGNO (operands[1]);
3513 /* If operands[1] is a register, on POWER it may have
3514 double-precision data in it, so truncate it to single
3516 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3519 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3520 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3521 operands[1] = newreg;
3525 /* Recognize the case where operand[1] is a reference to thread-local
3526 data and load its address to a register. */
3527 if (GET_CODE (operands[1]) == SYMBOL_REF)
3529 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3531 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3534 /* Handle the case where reload calls us with an invalid address. */
3535 if (reload_in_progress && mode == Pmode
3536 && (! general_operand (operands[1], mode)
3537 || ! nonimmediate_operand (operands[0], mode)))
3540 /* 128-bit constant floating-point values on Darwin should really be
3541 loaded as two parts. */
3542 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3543 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3544 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3546 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3547 know how to get a DFmode SUBREG of a TFmode. */
3548 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3549 simplify_gen_subreg (DImode, operands[1], mode, 0),
3551 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3552 GET_MODE_SIZE (DImode)),
3553 simplify_gen_subreg (DImode, operands[1], mode,
3554 GET_MODE_SIZE (DImode)),
3559 /* FIXME: In the long term, this switch statement should go away
3560 and be replaced by a sequence of tests based on things like
3566 if (CONSTANT_P (operands[1])
3567 && GET_CODE (operands[1]) != CONST_INT)
3568 operands[1] = force_const_mem (mode, operands[1]);
3572 rs6000_eliminate_indexed_memrefs (operands);
3577 if (CONSTANT_P (operands[1])
3578 && ! easy_fp_constant (operands[1], mode))
3579 operands[1] = force_const_mem (mode, operands[1]);
3590 if (CONSTANT_P (operands[1])
3591 && !easy_vector_constant (operands[1], mode))
3592 operands[1] = force_const_mem (mode, operands[1]);
3597 /* Use default pattern for address of ELF small data */
3600 && DEFAULT_ABI == ABI_V4
3601 && (GET_CODE (operands[1]) == SYMBOL_REF
3602 || GET_CODE (operands[1]) == CONST)
3603 && small_data_operand (operands[1], mode))
3605 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3609 if (DEFAULT_ABI == ABI_V4
3610 && mode == Pmode && mode == SImode
3611 && flag_pic == 1 && got_operand (operands[1], mode))
3613 emit_insn (gen_movsi_got (operands[0], operands[1]));
3617 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3621 && CONSTANT_P (operands[1])
3622 && GET_CODE (operands[1]) != HIGH
3623 && GET_CODE (operands[1]) != CONST_INT)
3625 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3627 /* If this is a function address on -mcall-aixdesc,
3628 convert it to the address of the descriptor. */
3629 if (DEFAULT_ABI == ABI_AIX
3630 && GET_CODE (operands[1]) == SYMBOL_REF
3631 && XSTR (operands[1], 0)[0] == '.')
3633 const char *name = XSTR (operands[1], 0);
3635 while (*name == '.')
3637 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3638 CONSTANT_POOL_ADDRESS_P (new_ref)
3639 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3640 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3641 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3642 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3643 operands[1] = new_ref;
3646 if (DEFAULT_ABI == ABI_DARWIN)
3649 if (MACHO_DYNAMIC_NO_PIC_P)
3651 /* Take care of any required data indirection. */
3652 operands[1] = rs6000_machopic_legitimize_pic_address (
3653 operands[1], mode, operands[0]);
3654 if (operands[0] != operands[1])
3655 emit_insn (gen_rtx_SET (VOIDmode,
3656 operands[0], operands[1]));
3660 emit_insn (gen_macho_high (target, operands[1]));
3661 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3665 emit_insn (gen_elf_high (target, operands[1]));
3666 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3670 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3671 and we have put it in the TOC, we just need to make a TOC-relative
3674 && GET_CODE (operands[1]) == SYMBOL_REF
3675 && constant_pool_expr_p (operands[1])
3676 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3677 get_pool_mode (operands[1])))
3679 operands[1] = create_TOC_reference (operands[1]);
3681 else if (mode == Pmode
3682 && CONSTANT_P (operands[1])
3683 && ((GET_CODE (operands[1]) != CONST_INT
3684 && ! easy_fp_constant (operands[1], mode))
3685 || (GET_CODE (operands[1]) == CONST_INT
3686 && num_insns_constant (operands[1], mode) > 2)
3687 || (GET_CODE (operands[0]) == REG
3688 && FP_REGNO_P (REGNO (operands[0]))))
3689 && GET_CODE (operands[1]) != HIGH
3690 && ! legitimate_constant_pool_address_p (operands[1])
3691 && ! toc_relative_expr_p (operands[1]))
3693 /* Emit a USE operation so that the constant isn't deleted if
3694 expensive optimizations are turned on because nobody
3695 references it. This should only be done for operands that
3696 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3697 This should not be done for operands that contain LABEL_REFs.
3698 For now, we just handle the obvious case. */
3699 if (GET_CODE (operands[1]) != LABEL_REF)
3700 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3703 /* Darwin uses a special PIC legitimizer. */
3704 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3707 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3709 if (operands[0] != operands[1])
3710 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3715 /* If we are to limit the number of things we put in the TOC and
3716 this is a symbol plus a constant we can add in one insn,
3717 just put the symbol in the TOC and add the constant. Don't do
3718 this if reload is in progress. */
3719 if (GET_CODE (operands[1]) == CONST
3720 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3721 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3722 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3723 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3724 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3725 && ! side_effects_p (operands[0]))
3728 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3729 rtx other = XEXP (XEXP (operands[1], 0), 1);
3731 sym = force_reg (mode, sym);
3733 emit_insn (gen_addsi3 (operands[0], sym, other));
3735 emit_insn (gen_adddi3 (operands[0], sym, other));
3739 operands[1] = force_const_mem (mode, operands[1]);
3742 && constant_pool_expr_p (XEXP (operands[1], 0))
3743 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3744 get_pool_constant (XEXP (operands[1], 0)),
3745 get_pool_mode (XEXP (operands[1], 0))))
3748 = gen_const_mem (mode,
3749 create_TOC_reference (XEXP (operands[1], 0)));
3750 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3756 rs6000_eliminate_indexed_memrefs (operands);
3760 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3762 gen_rtx_SET (VOIDmode,
3763 operands[0], operands[1]),
3764 gen_rtx_CLOBBER (VOIDmode,
3765 gen_rtx_SCRATCH (SImode)))));
3774 /* Above, we may have called force_const_mem which may have returned
3775 an invalid address. If we can, fix this up; otherwise, reload will
3776 have to deal with it. */
3777 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3778 operands[1] = validize_mem (operands[1]);
3781 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3784 /* Nonzero if we can use a floating-point register to pass this arg. */
3785 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3786 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3787 && (CUM)->fregno <= FP_ARG_MAX_REG \
3788 && TARGET_HARD_FLOAT && TARGET_FPRS)
3790 /* Nonzero if we can use an AltiVec register to pass this arg. */
3791 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3792 (ALTIVEC_VECTOR_MODE (MODE) \
3793 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3794 && TARGET_ALTIVEC_ABI \
3797 /* Return a nonzero value to say to return the function value in
3798 memory, just as large structures are always returned. TYPE will be
3799 the data type of the value, and FNTYPE will be the type of the
3800 function doing the returning, or @code{NULL} for libcalls.
3802 The AIX ABI for the RS/6000 specifies that all structures are
3803 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3804 specifies that structures <= 8 bytes are returned in r3/r4, but a
3805 draft put them in memory, and GCC used to implement the draft
3806 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3807 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3808 compatibility can change DRAFT_V4_STRUCT_RET to override the
3809 default, and -m switches get the final word. See
3810 rs6000_override_options for more details.
3812 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3813 long double support is enabled. These values are returned in memory.
3815 int_size_in_bytes returns -1 for variable size objects, which go in
3816 memory always. The cast to unsigned makes -1 > 8. */
3819 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3821 /* In the darwin64 abi, try to use registers for larger structs
3823 if (rs6000_darwin64_abi
3824 && TREE_CODE (type) == RECORD_TYPE
3825 && int_size_in_bytes (type) > 0)
3827 CUMULATIVE_ARGS valcum;
3831 valcum.fregno = FP_ARG_MIN_REG;
3832 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3833 /* Do a trial code generation as if this were going to be passed
3834 as an argument; if any part goes in memory, we return NULL. */
3835 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3838 /* Otherwise fall through to more conventional ABI rules. */
3841 if (AGGREGATE_TYPE_P (type)
3842 && (TARGET_AIX_STRUCT_RET
3843 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3846 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3847 modes only exist for GCC vector types if -maltivec. */
3848 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3849 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3852 /* Return synthetic vectors in memory. */
3853 if (TREE_CODE (type) == VECTOR_TYPE
3854 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
3856 static bool warned_for_return_big_vectors = false;
3857 if (!warned_for_return_big_vectors)
3859 warning ("GCC vector returned by reference: "
3860 "non-standard ABI extension with no compatibility guarantee");
3861 warned_for_return_big_vectors = true;
3866 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3872 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3873 for a call to a function whose data type is FNTYPE.
3874 For a library call, FNTYPE is 0.
3876 For incoming args we set the number of arguments in the prototype large
3877 so we never return a PARALLEL. */
3880 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3881 rtx libname ATTRIBUTE_UNUSED, int incoming,
3882 int libcall, int n_named_args)
3884 static CUMULATIVE_ARGS zero_cumulative;
3886 *cum = zero_cumulative;
3888 cum->fregno = FP_ARG_MIN_REG;
3889 cum->vregno = ALTIVEC_ARG_MIN_REG;
3890 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3891 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3892 ? CALL_LIBCALL : CALL_NORMAL);
3893 cum->sysv_gregno = GP_ARG_MIN_REG;
3894 cum->stdarg = fntype
3895 && (TYPE_ARG_TYPES (fntype) != 0
3896 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3897 != void_type_node));
3899 cum->nargs_prototype = 0;
3900 if (incoming || cum->prototype)
3901 cum->nargs_prototype = n_named_args;
3903 /* Check for a longcall attribute. */
3904 if ((!fntype && rs6000_default_long_calls)
3906 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3907 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3908 cum->call_cookie |= CALL_LONG;
3910 if (TARGET_DEBUG_ARG)
3912 fprintf (stderr, "\ninit_cumulative_args:");
3915 tree ret_type = TREE_TYPE (fntype);
3916 fprintf (stderr, " ret code = %s,",
3917 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3920 if (cum->call_cookie & CALL_LONG)
3921 fprintf (stderr, " longcall,");
3923 fprintf (stderr, " proto = %d, nargs = %d\n",
3924 cum->prototype, cum->nargs_prototype);
3929 && TARGET_ALTIVEC_ABI
3930 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3932 error ("Cannot return value in vector register because"
3933 " altivec instructions are disabled, use -maltivec"
3934 " to enable them.");
3938 /* Return true if TYPE must be passed on the stack and not in registers. */
3941 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3943 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3944 return must_pass_in_stack_var_size (mode, type);
3946 return must_pass_in_stack_var_size_or_pad (mode, type);
3949 /* If defined, a C expression which determines whether, and in which
3950 direction, to pad out an argument with extra space. The value
3951 should be of type `enum direction': either `upward' to pad above
3952 the argument, `downward' to pad below, or `none' to inhibit
3955 For the AIX ABI structs are always stored left shifted in their
3959 function_arg_padding (enum machine_mode mode, tree type)
3961 #ifndef AGGREGATE_PADDING_FIXED
3962 #define AGGREGATE_PADDING_FIXED 0
3964 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
3965 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
3968 if (!AGGREGATE_PADDING_FIXED)
3970 /* GCC used to pass structures of the same size as integer types as
3971 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
3972 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
3973 passed padded downward, except that -mstrict-align further
3974 muddied the water in that multi-component structures of 2 and 4
3975 bytes in size were passed padded upward.
3977 The following arranges for best compatibility with previous
3978 versions of gcc, but removes the -mstrict-align dependency. */
3979 if (BYTES_BIG_ENDIAN)
3981 HOST_WIDE_INT size = 0;
3983 if (mode == BLKmode)
3985 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
3986 size = int_size_in_bytes (type);
3989 size = GET_MODE_SIZE (mode);
3991 if (size == 1 || size == 2 || size == 4)
3997 if (AGGREGATES_PAD_UPWARD_ALWAYS)
3999 if (type != 0 && AGGREGATE_TYPE_P (type))
4003 /* Fall back to the default. */
4004 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4007 /* If defined, a C expression that gives the alignment boundary, in bits,
4008 of an argument with the specified mode and type. If it is not defined,
4009 PARM_BOUNDARY is used for all arguments.
4011 V.4 wants long longs to be double word aligned.
4012 Doubleword align SPE vectors.
4013 Quadword align Altivec vectors.
4014 Quadword align large synthetic vector types. */
4017 function_arg_boundary (enum machine_mode mode, tree type)
4019 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4021 else if (SPE_VECTOR_MODE (mode)
4022 || (type && TREE_CODE (type) == VECTOR_TYPE
4023 && int_size_in_bytes (type) >= 8
4024 && int_size_in_bytes (type) < 16))
4026 else if (ALTIVEC_VECTOR_MODE (mode)
4027 || (type && TREE_CODE (type) == VECTOR_TYPE
4028 && int_size_in_bytes (type) >= 16))
4030 else if (rs6000_darwin64_abi && mode == BLKmode
4031 && type && TYPE_ALIGN (type) > 64)
4034 return PARM_BOUNDARY;
4037 /* For a function parm of MODE and TYPE, return the starting word in
4038 the parameter area. NWORDS of the parameter area are already used. */
4041 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4044 unsigned int parm_offset;
4046 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4047 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4048 return nwords + (-(parm_offset + nwords) & align);
4051 /* Compute the size (in words) of a function argument. */
4053 static unsigned long
4054 rs6000_arg_size (enum machine_mode mode, tree type)
4058 if (mode != BLKmode)
4059 size = GET_MODE_SIZE (mode);
4061 size = int_size_in_bytes (type);
4064 return (size + 3) >> 2;
4066 return (size + 7) >> 3;
4069 /* Use this to flush pending int fields. */
4072 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4073 HOST_WIDE_INT bitpos)
4075 unsigned int startbit, endbit;
4076 int intregs, intoffset;
4077 enum machine_mode mode;
4079 if (cum->intoffset == -1)
4082 intoffset = cum->intoffset;
4083 cum->intoffset = -1;
4085 if (intoffset % BITS_PER_WORD != 0)
4087 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4089 if (mode == BLKmode)
4091 /* We couldn't find an appropriate mode, which happens,
4092 e.g., in packed structs when there are 3 bytes to load.
4093 Back intoffset back to the beginning of the word in this
4095 intoffset = intoffset & -BITS_PER_WORD;
4099 startbit = intoffset & -BITS_PER_WORD;
4100 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4101 intregs = (endbit - startbit) / BITS_PER_WORD;
4102 cum->words += intregs;
4105 /* The darwin64 ABI calls for us to recurse down through structs,
4106 looking for elements passed in registers. Unfortunately, we have
4107 to track int register count here also because of misalignments
4108 in powerpc alignment mode. */
4111 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4113 HOST_WIDE_INT startbitpos)
4117 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4118 if (TREE_CODE (f) == FIELD_DECL)
4120 HOST_WIDE_INT bitpos = startbitpos;
4121 tree ftype = TREE_TYPE (f);
4122 enum machine_mode mode = TYPE_MODE (ftype);
4124 if (DECL_SIZE (f) != 0
4125 && host_integerp (bit_position (f), 1))
4126 bitpos += int_bit_position (f);
4128 /* ??? FIXME: else assume zero offset. */
4130 if (TREE_CODE (ftype) == RECORD_TYPE)
4131 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4132 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4134 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4135 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4136 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4138 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4140 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4144 else if (cum->intoffset == -1)
4145 cum->intoffset = bitpos;
4149 /* Update the data in CUM to advance over an argument
4150 of mode MODE and data type TYPE.
4151 (TYPE is null for libcalls where that information may not be available.)
4153 Note that for args passed by reference, function_arg will be called
4154 with MODE and TYPE set to that of the pointer to the arg, not the arg
4158 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4159 tree type, int named, int depth)
4163 /* Only tick off an argument if we're not recursing. */
4165 cum->nargs_prototype--;
4167 if (TARGET_ALTIVEC_ABI
4168 && (ALTIVEC_VECTOR_MODE (mode)
4169 || (type && TREE_CODE (type) == VECTOR_TYPE
4170 && int_size_in_bytes (type) == 16)))
4174 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4177 if (!TARGET_ALTIVEC)
4178 error ("Cannot pass argument in vector register because"
4179 " altivec instructions are disabled, use -maltivec"
4180 " to enable them.");
4182 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4183 even if it is going to be passed in a vector register.
4184 Darwin does the same for variable-argument functions. */
4185 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4186 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4196 /* Vector parameters must be 16-byte aligned. This places
4197 them at 2 mod 4 in terms of words in 32-bit mode, since
4198 the parameter save area starts at offset 24 from the
4199 stack. In 64-bit mode, they just have to start on an
4200 even word, since the parameter save area is 16-byte
4201 aligned. Space for GPRs is reserved even if the argument
4202 will be passed in memory. */
4204 align = (2 - cum->words) & 3;
4206 align = cum->words & 1;
4207 cum->words += align + rs6000_arg_size (mode, type);
4209 if (TARGET_DEBUG_ARG)
4211 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4213 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4214 cum->nargs_prototype, cum->prototype,
4215 GET_MODE_NAME (mode));
4219 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4221 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4224 else if (rs6000_darwin64_abi
4226 && TREE_CODE (type) == RECORD_TYPE
4227 && (size = int_size_in_bytes (type)) > 0)
4229 /* Variable sized types have size == -1 and are
4230 treated as if consisting entirely of ints.
4231 Pad to 16 byte boundary if needed. */
4232 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4233 && (cum->words % 2) != 0)
4235 /* For varargs, we can just go up by the size of the struct. */
4237 cum->words += (size + 7) / 8;
4240 /* It is tempting to say int register count just goes up by
4241 sizeof(type)/8, but this is wrong in a case such as
4242 { int; double; int; } [powerpc alignment]. We have to
4243 grovel through the fields for these too. */
4245 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4246 rs6000_darwin64_record_arg_advance_flush (cum,
4247 size * BITS_PER_UNIT);
4250 else if (DEFAULT_ABI == ABI_V4)
4252 if (TARGET_HARD_FLOAT && TARGET_FPRS
4253 && (mode == SFmode || mode == DFmode))
4255 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4260 cum->words += cum->words & 1;
4261 cum->words += rs6000_arg_size (mode, type);
4266 int n_words = rs6000_arg_size (mode, type);
4267 int gregno = cum->sysv_gregno;
4269 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4270 (r7,r8) or (r9,r10). As does any other 2 word item such
4271 as complex int due to a historical mistake. */
4273 gregno += (1 - gregno) & 1;
4275 /* Multi-reg args are not split between registers and stack. */
4276 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4278 /* Long long and SPE vectors are aligned on the stack.
4279 So are other 2 word items such as complex int due to
4280 a historical mistake. */
4282 cum->words += cum->words & 1;
4283 cum->words += n_words;
4286 /* Note: continuing to accumulate gregno past when we've started
4287 spilling to the stack indicates the fact that we've started
4288 spilling to the stack to expand_builtin_saveregs. */
4289 cum->sysv_gregno = gregno + n_words;
4292 if (TARGET_DEBUG_ARG)
4294 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4295 cum->words, cum->fregno);
4296 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4297 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4298 fprintf (stderr, "mode = %4s, named = %d\n",
4299 GET_MODE_NAME (mode), named);
4304 int n_words = rs6000_arg_size (mode, type);
4305 int start_words = cum->words;
4306 int align_words = rs6000_parm_start (mode, type, start_words);
4308 cum->words = align_words + n_words;
4310 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4311 && TARGET_HARD_FLOAT && TARGET_FPRS)
4312 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4314 if (TARGET_DEBUG_ARG)
4316 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4317 cum->words, cum->fregno);
4318 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4319 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4320 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4321 named, align_words - start_words, depth);
4327 spe_build_register_parallel (enum machine_mode mode, int gregno)
4333 r1 = gen_rtx_REG (DImode, gregno);
4334 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4335 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4337 else if (mode == DCmode)
4339 r1 = gen_rtx_REG (DImode, gregno);
4340 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4341 r3 = gen_rtx_REG (DImode, gregno + 2);
4342 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4343 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4349 /* Determine where to put a SIMD argument on the SPE. */
4351 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4354 int gregno = cum->sysv_gregno;
4356 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4357 are passed and returned in a pair of GPRs for ABI compatibility. */
4358 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4360 int n_words = rs6000_arg_size (mode, type);
4362 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4364 gregno += (1 - gregno) & 1;
4366 /* Multi-reg args are not split between registers and stack. */
4367 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4370 return spe_build_register_parallel (mode, gregno);
4374 int n_words = rs6000_arg_size (mode, type);
4376 /* SPE vectors are put in odd registers. */
4377 if (n_words == 2 && (gregno & 1) == 0)
4380 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4383 enum machine_mode m = SImode;
4385 r1 = gen_rtx_REG (m, gregno);
4386 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4387 r2 = gen_rtx_REG (m, gregno + 1);
4388 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4389 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4396 if (gregno <= GP_ARG_MAX_REG)
4397 return gen_rtx_REG (mode, gregno);
4403 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4404 structure between cum->intoffset and bitpos to integer registers. */
4407 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4408 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4410 enum machine_mode mode;
4412 unsigned int startbit, endbit;
4413 int this_regno, intregs, intoffset;
4416 if (cum->intoffset == -1)
4419 intoffset = cum->intoffset;
4420 cum->intoffset = -1;
4422 /* If this is the trailing part of a word, try to only load that
4423 much into the register. Otherwise load the whole register. Note
4424 that in the latter case we may pick up unwanted bits. It's not a
4425 problem at the moment but may wish to revisit. */
4427 if (intoffset % BITS_PER_WORD != 0)
4429 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4431 if (mode == BLKmode)
4433 /* We couldn't find an appropriate mode, which happens,
4434 e.g., in packed structs when there are 3 bytes to load.
4435 Back intoffset back to the beginning of the word in this
4437 intoffset = intoffset & -BITS_PER_WORD;
4444 startbit = intoffset & -BITS_PER_WORD;
4445 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4446 intregs = (endbit - startbit) / BITS_PER_WORD;
4447 this_regno = cum->words + intoffset / BITS_PER_WORD;
4449 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4452 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4456 intoffset /= BITS_PER_UNIT;
4459 regno = GP_ARG_MIN_REG + this_regno;
4460 reg = gen_rtx_REG (mode, regno);
4462 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4465 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4469 while (intregs > 0);
4472 /* Recursive workhorse for the following. */
4475 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4476 HOST_WIDE_INT startbitpos, rtx rvec[],
4481 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4482 if (TREE_CODE (f) == FIELD_DECL)
4484 HOST_WIDE_INT bitpos = startbitpos;
4485 tree ftype = TREE_TYPE (f);
4486 enum machine_mode mode = TYPE_MODE (ftype);
4488 if (DECL_SIZE (f) != 0
4489 && host_integerp (bit_position (f), 1))
4490 bitpos += int_bit_position (f);
4492 /* ??? FIXME: else assume zero offset. */
4494 if (TREE_CODE (ftype) == RECORD_TYPE)
4495 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4496 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4501 case SCmode: mode = SFmode; break;
4502 case DCmode: mode = DFmode; break;
4503 case TCmode: mode = TFmode; break;
4507 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4509 = gen_rtx_EXPR_LIST (VOIDmode,
4510 gen_rtx_REG (mode, cum->fregno++),
4511 GEN_INT (bitpos / BITS_PER_UNIT));
4515 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4517 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4519 = gen_rtx_EXPR_LIST (VOIDmode,
4520 gen_rtx_REG (mode, cum->vregno++),
4521 GEN_INT (bitpos / BITS_PER_UNIT));
4523 else if (cum->intoffset == -1)
4524 cum->intoffset = bitpos;
4528 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4529 the register(s) to be used for each field and subfield of a struct
4530 being passed by value, along with the offset of where the
4531 register's value may be found in the block. FP fields go in FP
4532 register, vector fields go in vector registers, and everything
4533 else goes in int registers, packed as in memory.
4535 This code is also used for function return values. RETVAL indicates
4536 whether this is the case.
4538 Much of this is taken from the Sparc V9 port, which has a similar
4539 calling convention. */
4542 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4543 int named, bool retval)
4545 rtx rvec[FIRST_PSEUDO_REGISTER];
4546 int k = 1, kbase = 1;
4547 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4548 /* This is a copy; modifications are not visible to our caller. */
4549 CUMULATIVE_ARGS copy_cum = *orig_cum;
4550 CUMULATIVE_ARGS *cum = ©_cum;
4552 /* Pad to 16 byte boundary if needed. */
4553 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4554 && (cum->words % 2) != 0)
4561 /* Put entries into rvec[] for individual FP and vector fields, and
4562 for the chunks of memory that go in int regs. Note we start at
4563 element 1; 0 is reserved for an indication of using memory, and
4564 may or may not be filled in below. */
4565 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4566 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4568 /* If any part of the struct went on the stack put all of it there.
4569 This hack is because the generic code for
4570 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4571 parts of the struct are not at the beginning. */
4575 return NULL_RTX; /* doesn't go in registers at all */
4577 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4579 if (k > 1 || cum->use_stack)
4580 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4585 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4588 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4592 rtx rvec[GP_ARG_NUM_REG + 1];
4594 if (align_words >= GP_ARG_NUM_REG)
4597 n_units = rs6000_arg_size (mode, type);
4599 /* Optimize the simple case where the arg fits in one gpr, except in
4600 the case of BLKmode due to assign_parms assuming that registers are
4601 BITS_PER_WORD wide. */
4603 || (n_units == 1 && mode != BLKmode))
4604 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4607 if (align_words + n_units > GP_ARG_NUM_REG)
4608 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4609 using a magic NULL_RTX component.
4610 FIXME: This is not strictly correct. Only some of the arg
4611 belongs in memory, not all of it. However, there isn't any way
4612 to do this currently, apart from building rtx descriptions for
4613 the pieces of memory we want stored. Due to bugs in the generic
4614 code we can't use the normal function_arg_partial_nregs scheme
4615 with the PARALLEL arg description we emit here.
4616 In any case, the code to store the whole arg to memory is often
4617 more efficient than code to store pieces, and we know that space
4618 is available in the right place for the whole arg. */
4619 /* FIXME: This should be fixed since the conversion to
4620 TARGET_ARG_PARTIAL_BYTES. */
4621 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4626 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4627 rtx off = GEN_INT (i++ * 4);
4628 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4630 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4632 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4635 /* Determine where to put an argument to a function.
4636 Value is zero to push the argument on the stack,
4637 or a hard register in which to store the argument.
4639 MODE is the argument's machine mode.
4640 TYPE is the data type of the argument (as a tree).
4641 This is null for libcalls where that information may
4643 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4644 the preceding args and about the function being called. It is
4645 not modified in this routine.
4646 NAMED is nonzero if this argument is a named parameter
4647 (otherwise it is an extra parameter matching an ellipsis).
4649 On RS/6000 the first eight words of non-FP are normally in registers
4650 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4651 Under V.4, the first 8 FP args are in registers.
4653 If this is floating-point and no prototype is specified, we use
4654 both an FP and integer register (or possibly FP reg and stack). Library
4655 functions (when CALL_LIBCALL is set) always have the proper types for args,
4656 so we can pass the FP value just in one register. emit_library_function
4657 doesn't support PARALLEL anyway.
4659 Note that for args passed by reference, function_arg will be called
4660 with MODE and TYPE set to that of the pointer to the arg, not the arg
4664 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4665 tree type, int named)
4667 enum rs6000_abi abi = DEFAULT_ABI;
4669 /* Return a marker to indicate whether CR1 needs to set or clear the
4670 bit that V.4 uses to say fp args were passed in registers.
4671 Assume that we don't need the marker for software floating point,
4672 or compiler generated library calls. */
4673 if (mode == VOIDmode)
4676 && cum->nargs_prototype < 0
4677 && (cum->call_cookie & CALL_LIBCALL) == 0
4678 && (cum->prototype || TARGET_NO_PROTOTYPE))
4680 /* For the SPE, we need to crxor CR6 always. */
4682 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4683 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4684 return GEN_INT (cum->call_cookie
4685 | ((cum->fregno == FP_ARG_MIN_REG)
4686 ? CALL_V4_SET_FP_ARGS
4687 : CALL_V4_CLEAR_FP_ARGS));
4690 return GEN_INT (cum->call_cookie);
4693 if (rs6000_darwin64_abi && mode == BLKmode
4694 && TREE_CODE (type) == RECORD_TYPE)
4696 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4697 if (rslt != NULL_RTX)
4699 /* Else fall through to usual handling. */
4702 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4703 if (TARGET_64BIT && ! cum->prototype)
4705 /* Vector parameters get passed in vector register
4706 and also in GPRs or memory, in absence of prototype. */
4709 align_words = (cum->words + 1) & ~1;
4711 if (align_words >= GP_ARG_NUM_REG)
4717 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4719 return gen_rtx_PARALLEL (mode,
4721 gen_rtx_EXPR_LIST (VOIDmode,
4723 gen_rtx_EXPR_LIST (VOIDmode,
4724 gen_rtx_REG (mode, cum->vregno),
4728 return gen_rtx_REG (mode, cum->vregno);
4729 else if (TARGET_ALTIVEC_ABI
4730 && (ALTIVEC_VECTOR_MODE (mode)
4731 || (type && TREE_CODE (type) == VECTOR_TYPE
4732 && int_size_in_bytes (type) == 16)))
4734 if (named || abi == ABI_V4)
4738 /* Vector parameters to varargs functions under AIX or Darwin
4739 get passed in memory and possibly also in GPRs. */
4740 int align, align_words, n_words;
4741 enum machine_mode part_mode;
4743 /* Vector parameters must be 16-byte aligned. This places them at
4744 2 mod 4 in terms of words in 32-bit mode, since the parameter
4745 save area starts at offset 24 from the stack. In 64-bit mode,
4746 they just have to start on an even word, since the parameter
4747 save area is 16-byte aligned. */
4749 align = (2 - cum->words) & 3;
4751 align = cum->words & 1;
4752 align_words = cum->words + align;
4754 /* Out of registers? Memory, then. */
4755 if (align_words >= GP_ARG_NUM_REG)
4758 if (TARGET_32BIT && TARGET_POWERPC64)
4759 return rs6000_mixed_function_arg (mode, type, align_words);
4761 /* The vector value goes in GPRs. Only the part of the
4762 value in GPRs is reported here. */
4764 n_words = rs6000_arg_size (mode, type);
4765 if (align_words + n_words > GP_ARG_NUM_REG)
4766 /* Fortunately, there are only two possibilities, the value
4767 is either wholly in GPRs or half in GPRs and half not. */
4770 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4773 else if (TARGET_SPE_ABI && TARGET_SPE
4774 && (SPE_VECTOR_MODE (mode)
4775 || (TARGET_E500_DOUBLE && (mode == DFmode
4776 || mode == DCmode))))
4777 return rs6000_spe_function_arg (cum, mode, type);
4779 else if (abi == ABI_V4)
4781 if (TARGET_HARD_FLOAT && TARGET_FPRS
4782 && (mode == SFmode || mode == DFmode))
4784 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4785 return gen_rtx_REG (mode, cum->fregno);
4791 int n_words = rs6000_arg_size (mode, type);
4792 int gregno = cum->sysv_gregno;
4794 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4795 (r7,r8) or (r9,r10). As does any other 2 word item such
4796 as complex int due to a historical mistake. */
4798 gregno += (1 - gregno) & 1;
4800 /* Multi-reg args are not split between registers and stack. */
4801 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4804 if (TARGET_32BIT && TARGET_POWERPC64)
4805 return rs6000_mixed_function_arg (mode, type,
4806 gregno - GP_ARG_MIN_REG);
4807 return gen_rtx_REG (mode, gregno);
4812 int align_words = rs6000_parm_start (mode, type, cum->words);
4814 if (USE_FP_FOR_ARG_P (cum, mode, type))
4816 rtx rvec[GP_ARG_NUM_REG + 1];
4820 enum machine_mode fmode = mode;
4821 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4823 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4825 /* Currently, we only ever need one reg here because complex
4826 doubles are split. */
4827 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
4830 /* Long double split over regs and memory. */
4834 /* Do we also need to pass this arg in the parameter save
4837 && (cum->nargs_prototype <= 0
4838 || (DEFAULT_ABI == ABI_AIX
4840 && align_words >= GP_ARG_NUM_REG)));
4842 if (!needs_psave && mode == fmode)
4843 return gen_rtx_REG (fmode, cum->fregno);
4848 /* Describe the part that goes in gprs or the stack.
4849 This piece must come first, before the fprs. */
4850 if (align_words < GP_ARG_NUM_REG)
4852 unsigned long n_words = rs6000_arg_size (mode, type);
4854 if (align_words + n_words > GP_ARG_NUM_REG
4855 || (TARGET_32BIT && TARGET_POWERPC64))
4857 /* If this is partially on the stack, then we only
4858 include the portion actually in registers here. */
4859 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4862 if (align_words + n_words > GP_ARG_NUM_REG
4863 && (TARGET_32BIT && TARGET_POWERPC64))
4864 /* Not all of the arg fits in gprs. Say that it
4865 goes in memory too, using a magic NULL_RTX
4866 component. Also see comment in
4867 rs6000_mixed_function_arg for why the normal
4868 function_arg_partial_nregs scheme doesn't work
4870 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4874 r = gen_rtx_REG (rmode,
4875 GP_ARG_MIN_REG + align_words);
4876 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
4877 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4879 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4883 /* The whole arg fits in gprs. */
4884 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4885 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4889 /* It's entirely in memory. */
4890 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4893 /* Describe where this piece goes in the fprs. */
4894 r = gen_rtx_REG (fmode, cum->fregno);
4895 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4897 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4899 else if (align_words < GP_ARG_NUM_REG)
4901 if (TARGET_32BIT && TARGET_POWERPC64)
4902 return rs6000_mixed_function_arg (mode, type, align_words);
4904 if (mode == BLKmode)
4907 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4914 /* For an arg passed partly in registers and partly in memory, this is
4915 the number of bytes passed in registers. For args passed entirely in
4916 registers or entirely in memory, zero. When an arg is described by a
4917 PARALLEL, perhaps using more than one register type, this function
4918 returns the number of bytes used by the first element of the PARALLEL. */
4921 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4922 tree type, bool named)
4927 if (DEFAULT_ABI == ABI_V4)
4930 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4931 && cum->nargs_prototype >= 0)
4934 /* In this complicated case we just disable the partial_nregs code. */
4935 if (rs6000_darwin64_abi && mode == BLKmode
4936 && TREE_CODE (type) == RECORD_TYPE
4937 && int_size_in_bytes (type) > 0)
4940 align_words = rs6000_parm_start (mode, type, cum->words);
4942 if (USE_FP_FOR_ARG_P (cum, mode, type)
4943 /* If we are passing this arg in the fixed parameter save area
4944 (gprs or memory) as well as fprs, then this function should
4945 return the number of bytes passed in the parameter save area
4946 rather than bytes passed in fprs. */
4948 && (cum->nargs_prototype <= 0
4949 || (DEFAULT_ABI == ABI_AIX
4951 && align_words >= GP_ARG_NUM_REG))))
4953 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4954 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
4955 else if (cum->nargs_prototype >= 0)
4959 if (align_words < GP_ARG_NUM_REG
4960 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
4961 ret = GP_ARG_NUM_REG - align_words;
4963 ret *= (TARGET_32BIT ? 4 : 8);
4965 if (ret != 0 && TARGET_DEBUG_ARG)
4966 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
4971 /* A C expression that indicates when an argument must be passed by
4972 reference. If nonzero for an argument, a copy of that argument is
4973 made in memory and a pointer to the argument is passed instead of
4974 the argument itself. The pointer is passed in whatever way is
4975 appropriate for passing a pointer to that type.
4977 Under V.4, aggregates and long double are passed by reference.
4979 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
4980 reference unless the AltiVec vector extension ABI is in force.
4982 As an extension to all ABIs, variable sized types are passed by
4986 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
4987 enum machine_mode mode, tree type,
4988 bool named ATTRIBUTE_UNUSED)
4990 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
4992 if (TARGET_DEBUG_ARG)
4993 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5000 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5002 if (TARGET_DEBUG_ARG)
5003 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5007 if (int_size_in_bytes (type) < 0)
5009 if (TARGET_DEBUG_ARG)
5010 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5014 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5015 modes only exist for GCC vector types if -maltivec. */
5016 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5018 if (TARGET_DEBUG_ARG)
5019 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5023 /* Pass synthetic vectors in memory. */
5024 if (TREE_CODE (type) == VECTOR_TYPE
5025 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5027 static bool warned_for_pass_big_vectors = false;
5028 if (TARGET_DEBUG_ARG)
5029 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5030 if (!warned_for_pass_big_vectors)
5032 warning ("GCC vector passed by reference: "
5033 "non-standard ABI extension with no compatibility guarantee");
5034 warned_for_pass_big_vectors = true;
5043 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5046 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5051 for (i = 0; i < nregs; i++)
5053 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5054 if (reload_completed)
5056 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5059 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5060 i * GET_MODE_SIZE (reg_mode));
5063 tem = replace_equiv_address (tem, XEXP (tem, 0));
5065 if (tem == NULL_RTX)
5068 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5072 /* Perform any needed actions needed for a function that is receiving a
5073 variable number of arguments.
5077 MODE and TYPE are the mode and type of the current parameter.
5079 PRETEND_SIZE is a variable that should be set to the amount of stack
5080 that must be pushed by the prolog to pretend that our caller pushed
5083 Normally, this macro will push all remaining incoming registers on the
5084 stack and set PRETEND_SIZE to the length of the registers pushed. */
5087 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5088 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5091 CUMULATIVE_ARGS next_cum;
5092 int reg_size = TARGET_32BIT ? 4 : 8;
5093 rtx save_area = NULL_RTX, mem;
5094 int first_reg_offset, set;
5096 /* Skip the last named argument. */
5098 function_arg_advance (&next_cum, mode, type, 1, 0);
5100 if (DEFAULT_ABI == ABI_V4)
5103 save_area = plus_constant (virtual_stack_vars_rtx,
5104 - RS6000_VARARGS_SIZE);
5106 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5110 first_reg_offset = next_cum.words;
5111 save_area = virtual_incoming_args_rtx;
5113 if (targetm.calls.must_pass_in_stack (mode, type))
5114 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5117 set = get_varargs_alias_set ();
5118 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5120 mem = gen_rtx_MEM (BLKmode,
5121 plus_constant (save_area,
5122 first_reg_offset * reg_size)),
5123 set_mem_alias_set (mem, set);
5124 set_mem_align (mem, BITS_PER_WORD);
5126 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5127 GP_ARG_NUM_REG - first_reg_offset);
5130 /* Save FP registers if needed. */
5131 if (DEFAULT_ABI == ABI_V4
5132 && TARGET_HARD_FLOAT && TARGET_FPRS
5134 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5136 int fregno = next_cum.fregno;
5137 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5138 rtx lab = gen_label_rtx ();
5139 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5142 (gen_rtx_SET (VOIDmode,
5144 gen_rtx_IF_THEN_ELSE (VOIDmode,
5145 gen_rtx_NE (VOIDmode, cr1,
5147 gen_rtx_LABEL_REF (VOIDmode, lab),
5150 while (fregno <= FP_ARG_V4_MAX_REG)
5152 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5153 set_mem_alias_set (mem, set);
5154 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5155 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5164 /* Create the va_list data type. */
5167 rs6000_build_builtin_va_list (void)
5169 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5171 /* For AIX, prefer 'char *' because that's what the system
5172 header files like. */
5173 if (DEFAULT_ABI != ABI_V4)
5174 return build_pointer_type (char_type_node);
5176 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5177 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5179 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5180 unsigned_char_type_node);
5181 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5182 unsigned_char_type_node);
5183 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5185 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5186 short_unsigned_type_node);
5187 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5189 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5192 DECL_FIELD_CONTEXT (f_gpr) = record;
5193 DECL_FIELD_CONTEXT (f_fpr) = record;
5194 DECL_FIELD_CONTEXT (f_res) = record;
5195 DECL_FIELD_CONTEXT (f_ovf) = record;
5196 DECL_FIELD_CONTEXT (f_sav) = record;
5198 TREE_CHAIN (record) = type_decl;
5199 TYPE_NAME (record) = type_decl;
5200 TYPE_FIELDS (record) = f_gpr;
5201 TREE_CHAIN (f_gpr) = f_fpr;
5202 TREE_CHAIN (f_fpr) = f_res;
5203 TREE_CHAIN (f_res) = f_ovf;
5204 TREE_CHAIN (f_ovf) = f_sav;
5206 layout_type (record);
5208 /* The correct type is an array type of one element. */
5209 return build_array_type (record, build_index_type (size_zero_node));
5212 /* Implement va_start. */
5215 rs6000_va_start (tree valist, rtx nextarg)
5217 HOST_WIDE_INT words, n_gpr, n_fpr;
5218 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5219 tree gpr, fpr, ovf, sav, t;
5221 /* Only SVR4 needs something special. */
5222 if (DEFAULT_ABI != ABI_V4)
5224 std_expand_builtin_va_start (valist, nextarg);
5228 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5229 f_fpr = TREE_CHAIN (f_gpr);
5230 f_res = TREE_CHAIN (f_fpr);
5231 f_ovf = TREE_CHAIN (f_res);
5232 f_sav = TREE_CHAIN (f_ovf);
5234 valist = build_va_arg_indirect_ref (valist);
5235 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5236 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5237 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5238 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5240 /* Count number of gp and fp argument registers used. */
5241 words = current_function_args_info.words;
5242 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5244 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5247 if (TARGET_DEBUG_ARG)
5248 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5249 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5250 words, n_gpr, n_fpr);
5252 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5253 build_int_cst (NULL_TREE, n_gpr));
5254 TREE_SIDE_EFFECTS (t) = 1;
5255 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5257 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5258 build_int_cst (NULL_TREE, n_fpr));
5259 TREE_SIDE_EFFECTS (t) = 1;
5260 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5262 /* Find the overflow area. */
5263 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5265 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5266 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5267 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5268 TREE_SIDE_EFFECTS (t) = 1;
5269 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5271 /* Find the register save area. */
5272 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5273 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5274 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5275 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5276 TREE_SIDE_EFFECTS (t) = 1;
5277 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5280 /* Implement va_arg. */
5283 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5285 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5286 tree gpr, fpr, ovf, sav, reg, t, u;
5287 int size, rsize, n_reg, sav_ofs, sav_scale;
5288 tree lab_false, lab_over, addr;
5290 tree ptrtype = build_pointer_type (type);
5292 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5294 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5295 return build_va_arg_indirect_ref (t);
5298 if (DEFAULT_ABI != ABI_V4)
5300 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5302 tree elem_type = TREE_TYPE (type);
5303 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5304 int elem_size = GET_MODE_SIZE (elem_mode);
5306 if (elem_size < UNITS_PER_WORD)
5308 tree real_part, imag_part;
5309 tree post = NULL_TREE;
5311 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5313 /* Copy the value into a temporary, lest the formal temporary
5314 be reused out from under us. */
5315 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5316 append_to_statement_list (post, pre_p);
5318 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5321 return build (COMPLEX_EXPR, type, real_part, imag_part);
5325 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5328 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5329 f_fpr = TREE_CHAIN (f_gpr);
5330 f_res = TREE_CHAIN (f_fpr);
5331 f_ovf = TREE_CHAIN (f_res);
5332 f_sav = TREE_CHAIN (f_ovf);
5334 valist = build_va_arg_indirect_ref (valist);
5335 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5336 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5337 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5338 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5340 size = int_size_in_bytes (type);
5341 rsize = (size + 3) / 4;
5344 if (TARGET_HARD_FLOAT && TARGET_FPRS
5345 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5347 /* FP args go in FP registers, if present. */
5352 if (TYPE_MODE (type) == DFmode)
5357 /* Otherwise into GP registers. */
5366 /* Pull the value out of the saved registers.... */
5369 addr = create_tmp_var (ptr_type_node, "addr");
5370 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5372 /* AltiVec vectors never go in registers when -mabi=altivec. */
5373 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5377 lab_false = create_artificial_label ();
5378 lab_over = create_artificial_label ();
5380 /* Long long and SPE vectors are aligned in the registers.
5381 As are any other 2 gpr item such as complex int due to a
5382 historical mistake. */
5386 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5387 size_int (n_reg - 1));
5388 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5391 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5392 t = build2 (GE_EXPR, boolean_type_node, u, t);
5393 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5394 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5395 gimplify_and_add (t, pre_p);
5399 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5401 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5402 u = build1 (CONVERT_EXPR, integer_type_node, u);
5403 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5404 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5406 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5407 gimplify_and_add (t, pre_p);
5409 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5410 gimplify_and_add (t, pre_p);
5412 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5413 append_to_statement_list (t, pre_p);
5417 /* Ensure that we don't find any more args in regs.
5418 Alignment has taken care of the n_reg == 2 case. */
5419 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5420 gimplify_and_add (t, pre_p);
5424 /* ... otherwise out of the overflow area. */
5426 /* Care for on-stack alignment if needed. */
5430 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5431 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5432 build_int_cst (NULL_TREE, -align));
5434 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5436 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5437 gimplify_and_add (u, pre_p);
5439 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5440 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5441 gimplify_and_add (t, pre_p);
5445 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5446 append_to_statement_list (t, pre_p);
5449 addr = fold_convert (ptrtype, addr);
5450 return build_va_arg_indirect_ref (addr);
5455 #define def_builtin(MASK, NAME, TYPE, CODE) \
5457 if ((MASK) & target_flags) \
5458 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5462 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5464 static const struct builtin_description bdesc_3arg[] =
5466 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5467 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5468 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5469 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5470 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5471 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5472 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5473 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5474 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5475 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5476 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5477 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5478 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5479 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5480 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5481 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5482 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5483 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5484 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5485 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5486 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5487 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5488 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5491 /* DST operations: void foo (void *, const int, const char). */
5493 static const struct builtin_description bdesc_dst[] =
5495 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5496 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5497 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5498 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5501 /* Simple binary operations: VECc = foo (VECa, VECb). */
5503 static struct builtin_description bdesc_2arg[] =
5505 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5506 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5507 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5508 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5509 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5510 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5511 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5512 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5514 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5515 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5516 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5517 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5520 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5521 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5522 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5523 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5524 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5525 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5526 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5527 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5528 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5529 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5530 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5532 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5533 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5534 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5535 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5536 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5537 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5538 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5539 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5540 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5541 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5542 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5543 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5544 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5545 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5546 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5547 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5548 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5549 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5550 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5551 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5552 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5553 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5554 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5555 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5556 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5557 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5558 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5559 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5560 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5561 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5562 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5563 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5570 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5575 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5576 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5578 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5579 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5580 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5581 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5582 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5584 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5585 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5586 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5587 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5588 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5589 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5590 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5591 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5592 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5593 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5594 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5595 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5596 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5597 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5598 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5599 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5600 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5601 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5602 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5603 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5604 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5606 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5614 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5615 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5617 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5619 /* Place holder, leave as first spe builtin. */
5620 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5621 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5622 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5623 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5624 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5625 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5626 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5627 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5628 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5629 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5630 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5631 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5632 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5633 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5634 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5635 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5636 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5637 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5638 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5639 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5640 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5641 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5642 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5643 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5644 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5645 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5646 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5647 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5648 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5649 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5650 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5651 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5652 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5653 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5654 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5655 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5656 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5657 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5658 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5659 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5660 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5661 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5662 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5663 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5664 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5665 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5666 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5667 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5668 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5669 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5670 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5671 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5672 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5673 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5674 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5675 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5676 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5677 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5678 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5679 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5680 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5681 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5682 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5683 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5684 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5685 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5686 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5687 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5688 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5689 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5690 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5691 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5692 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5693 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5694 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5695 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5696 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5697 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5698 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5699 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5700 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5701 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5702 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5703 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5704 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5705 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5706 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5707 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5708 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5709 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5710 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5711 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5712 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5713 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5714 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5715 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5716 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5717 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5718 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5719 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5720 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5721 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5722 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5723 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5724 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5725 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5726 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5727 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5728 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5730 /* SPE binary operations expecting a 5-bit unsigned literal. */
5731 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5733 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5734 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5735 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5736 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5737 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5738 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5739 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5740 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5741 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5742 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5743 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5744 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5745 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5746 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5747 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5748 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5749 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5750 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5751 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5752 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5753 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5754 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5755 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5756 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5757 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5758 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5760 /* Place-holder. Leave as last binary SPE builtin. */
5761 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5764 /* AltiVec predicates. */
5766 struct builtin_description_predicates
5768 const unsigned int mask;
5769 const enum insn_code icode;
5771 const char *const name;
5772 const enum rs6000_builtins code;
5775 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5777 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5778 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5779 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5780 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5781 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5782 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5783 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5784 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5785 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5786 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5787 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5788 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5789 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5792 /* SPE predicates. */
5793 static struct builtin_description bdesc_spe_predicates[] =
5795 /* Place-holder. Leave as first. */
5796 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5797 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5798 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5799 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5800 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5801 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5802 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5803 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5804 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5805 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5806 /* Place-holder. Leave as last. */
5807 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5810 /* SPE evsel predicates. */
5811 static struct builtin_description bdesc_spe_evsel[] =
5813 /* Place-holder. Leave as first. */
5814 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5815 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5816 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5817 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5818 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5819 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5820 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5821 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5822 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5823 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5824 /* Place-holder. Leave as last. */
5825 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5828 /* ABS* operations. */
5830 static const struct builtin_description bdesc_abs[] =
5832 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5833 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5834 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5835 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5836 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5837 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5838 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5841 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5844 static struct builtin_description bdesc_1arg[] =
5846 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5847 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5848 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5849 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5850 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5851 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5852 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5853 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5854 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5855 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5856 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5857 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5858 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5859 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5860 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5861 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5862 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5864 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5865 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5866 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5867 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5868 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5869 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5870 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5871 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5872 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5873 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5874 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5875 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5876 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5877 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5878 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5879 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5880 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5881 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5882 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5883 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5884 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5885 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5886 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5887 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5888 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5889 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5890 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5891 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5892 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5893 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5895 /* Place-holder. Leave as last unary SPE builtin. */
5896 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5900 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5903 tree arg0 = TREE_VALUE (arglist);
5904 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5905 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5906 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5908 if (icode == CODE_FOR_nothing)
5909 /* Builtin not supported on this processor. */
5912 /* If we got invalid arguments bail out before generating bad rtl. */
5913 if (arg0 == error_mark_node)
5916 if (icode == CODE_FOR_altivec_vspltisb
5917 || icode == CODE_FOR_altivec_vspltish
5918 || icode == CODE_FOR_altivec_vspltisw
5919 || icode == CODE_FOR_spe_evsplatfi
5920 || icode == CODE_FOR_spe_evsplati)
5922 /* Only allow 5-bit *signed* literals. */
5923 if (GET_CODE (op0) != CONST_INT
5924 || INTVAL (op0) > 0x1f
5925 || INTVAL (op0) < -0x1f)
5927 error ("argument 1 must be a 5-bit signed literal");
5933 || GET_MODE (target) != tmode
5934 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5935 target = gen_reg_rtx (tmode);
5937 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5938 op0 = copy_to_mode_reg (mode0, op0);
5940 pat = GEN_FCN (icode) (target, op0);
5949 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5951 rtx pat, scratch1, scratch2;
5952 tree arg0 = TREE_VALUE (arglist);
5953 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5954 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5955 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5957 /* If we have invalid arguments, bail out before generating bad rtl. */
5958 if (arg0 == error_mark_node)
5962 || GET_MODE (target) != tmode
5963 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5964 target = gen_reg_rtx (tmode);
5966 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5967 op0 = copy_to_mode_reg (mode0, op0);
5969 scratch1 = gen_reg_rtx (mode0);
5970 scratch2 = gen_reg_rtx (mode0);
5972 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
5981 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
5984 tree arg0 = TREE_VALUE (arglist);
5985 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
5986 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5987 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
5988 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5989 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5990 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
5992 if (icode == CODE_FOR_nothing)
5993 /* Builtin not supported on this processor. */
5996 /* If we got invalid arguments bail out before generating bad rtl. */
5997 if (arg0 == error_mark_node || arg1 == error_mark_node)
6000 if (icode == CODE_FOR_altivec_vcfux
6001 || icode == CODE_FOR_altivec_vcfsx
6002 || icode == CODE_FOR_altivec_vctsxs
6003 || icode == CODE_FOR_altivec_vctuxs
6004 || icode == CODE_FOR_altivec_vspltb
6005 || icode == CODE_FOR_altivec_vsplth
6006 || icode == CODE_FOR_altivec_vspltw
6007 || icode == CODE_FOR_spe_evaddiw
6008 || icode == CODE_FOR_spe_evldd
6009 || icode == CODE_FOR_spe_evldh
6010 || icode == CODE_FOR_spe_evldw
6011 || icode == CODE_FOR_spe_evlhhesplat
6012 || icode == CODE_FOR_spe_evlhhossplat
6013 || icode == CODE_FOR_spe_evlhhousplat
6014 || icode == CODE_FOR_spe_evlwhe
6015 || icode == CODE_FOR_spe_evlwhos
6016 || icode == CODE_FOR_spe_evlwhou
6017 || icode == CODE_FOR_spe_evlwhsplat
6018 || icode == CODE_FOR_spe_evlwwsplat
6019 || icode == CODE_FOR_spe_evrlwi
6020 || icode == CODE_FOR_spe_evslwi
6021 || icode == CODE_FOR_spe_evsrwis
6022 || icode == CODE_FOR_spe_evsubifw
6023 || icode == CODE_FOR_spe_evsrwiu)
6025 /* Only allow 5-bit unsigned literals. */
6027 if (TREE_CODE (arg1) != INTEGER_CST
6028 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6030 error ("argument 2 must be a 5-bit unsigned literal");
6036 || GET_MODE (target) != tmode
6037 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6038 target = gen_reg_rtx (tmode);
6040 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6041 op0 = copy_to_mode_reg (mode0, op0);
6042 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6043 op1 = copy_to_mode_reg (mode1, op1);
6045 pat = GEN_FCN (icode) (target, op0, op1);
6054 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6055 tree arglist, rtx target)
6058 tree cr6_form = TREE_VALUE (arglist);
6059 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6060 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6061 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6062 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6063 enum machine_mode tmode = SImode;
6064 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6065 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6068 if (TREE_CODE (cr6_form) != INTEGER_CST)
6070 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6074 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6079 /* If we have invalid arguments, bail out before generating bad rtl. */
6080 if (arg0 == error_mark_node || arg1 == error_mark_node)
6084 || GET_MODE (target) != tmode
6085 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6086 target = gen_reg_rtx (tmode);
6088 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6089 op0 = copy_to_mode_reg (mode0, op0);
6090 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6091 op1 = copy_to_mode_reg (mode1, op1);
6093 scratch = gen_reg_rtx (mode0);
6095 pat = GEN_FCN (icode) (scratch, op0, op1,
6096 gen_rtx_SYMBOL_REF (Pmode, opcode));
6101 /* The vec_any* and vec_all* predicates use the same opcodes for two
6102 different operations, but the bits in CR6 will be different
6103 depending on what information we want. So we have to play tricks
6104 with CR6 to get the right bits out.
6106 If you think this is disgusting, look at the specs for the
6107 AltiVec predicates. */
6109 switch (cr6_form_int)
6112 emit_insn (gen_cr6_test_for_zero (target));
6115 emit_insn (gen_cr6_test_for_zero_reverse (target));
6118 emit_insn (gen_cr6_test_for_lt (target));
6121 emit_insn (gen_cr6_test_for_lt_reverse (target));
6124 error ("argument 1 of __builtin_altivec_predicate is out of range");
6132 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6135 tree arg0 = TREE_VALUE (arglist);
6136 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6137 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6138 enum machine_mode mode0 = Pmode;
6139 enum machine_mode mode1 = Pmode;
6140 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6141 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6143 if (icode == CODE_FOR_nothing)
6144 /* Builtin not supported on this processor. */
6147 /* If we got invalid arguments bail out before generating bad rtl. */
6148 if (arg0 == error_mark_node || arg1 == error_mark_node)
6152 || GET_MODE (target) != tmode
6153 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6154 target = gen_reg_rtx (tmode);
6156 op1 = copy_to_mode_reg (mode1, op1);
6158 if (op0 == const0_rtx)
6160 addr = gen_rtx_MEM (tmode, op1);
6164 op0 = copy_to_mode_reg (mode0, op0);
6165 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6168 pat = GEN_FCN (icode) (target, addr);
6178 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6180 tree arg0 = TREE_VALUE (arglist);
6181 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6182 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6183 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6184 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6185 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6187 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6188 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6189 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6191 /* Invalid arguments. Bail before doing anything stoopid! */
6192 if (arg0 == error_mark_node
6193 || arg1 == error_mark_node
6194 || arg2 == error_mark_node)
6197 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6198 op0 = copy_to_mode_reg (mode2, op0);
6199 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6200 op1 = copy_to_mode_reg (mode0, op1);
6201 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6202 op2 = copy_to_mode_reg (mode1, op2);
6204 pat = GEN_FCN (icode) (op1, op2, op0);
6211 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6213 tree arg0 = TREE_VALUE (arglist);
6214 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6215 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6216 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6217 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6218 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6220 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6221 enum machine_mode mode1 = Pmode;
6222 enum machine_mode mode2 = Pmode;
6224 /* Invalid arguments. Bail before doing anything stoopid! */
6225 if (arg0 == error_mark_node
6226 || arg1 == error_mark_node
6227 || arg2 == error_mark_node)
6230 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6231 op0 = copy_to_mode_reg (tmode, op0);
6233 op2 = copy_to_mode_reg (mode2, op2);
6235 if (op1 == const0_rtx)
6237 addr = gen_rtx_MEM (tmode, op2);
6241 op1 = copy_to_mode_reg (mode1, op1);
6242 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6245 pat = GEN_FCN (icode) (addr, op0);
6252 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6255 tree arg0 = TREE_VALUE (arglist);
6256 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6257 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6258 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6259 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6260 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6261 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6262 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6263 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6264 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6266 if (icode == CODE_FOR_nothing)
6267 /* Builtin not supported on this processor. */
6270 /* If we got invalid arguments bail out before generating bad rtl. */
6271 if (arg0 == error_mark_node
6272 || arg1 == error_mark_node
6273 || arg2 == error_mark_node)
6276 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6277 || icode == CODE_FOR_altivec_vsldoi_v4si
6278 || icode == CODE_FOR_altivec_vsldoi_v8hi
6279 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6281 /* Only allow 4-bit unsigned literals. */
6283 if (TREE_CODE (arg2) != INTEGER_CST
6284 || TREE_INT_CST_LOW (arg2) & ~0xf)
6286 error ("argument 3 must be a 4-bit unsigned literal");
6292 || GET_MODE (target) != tmode
6293 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6294 target = gen_reg_rtx (tmode);
6296 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6297 op0 = copy_to_mode_reg (mode0, op0);
6298 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6299 op1 = copy_to_mode_reg (mode1, op1);
6300 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6301 op2 = copy_to_mode_reg (mode2, op2);
6303 pat = GEN_FCN (icode) (target, op0, op1, op2);
6311 /* Expand the lvx builtins. */
6313 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6315 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6316 tree arglist = TREE_OPERAND (exp, 1);
6317 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6319 enum machine_mode tmode, mode0;
6321 enum insn_code icode;
6325 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6326 icode = CODE_FOR_altivec_lvx_v16qi;
6328 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6329 icode = CODE_FOR_altivec_lvx_v8hi;
6331 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6332 icode = CODE_FOR_altivec_lvx_v4si;
6334 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6335 icode = CODE_FOR_altivec_lvx_v4sf;
6344 arg0 = TREE_VALUE (arglist);
6345 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6346 tmode = insn_data[icode].operand[0].mode;
6347 mode0 = insn_data[icode].operand[1].mode;
6350 || GET_MODE (target) != tmode
6351 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6352 target = gen_reg_rtx (tmode);
6354 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6355 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6357 pat = GEN_FCN (icode) (target, op0);
6364 /* Expand the stvx builtins. */
6366 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6369 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6370 tree arglist = TREE_OPERAND (exp, 1);
6371 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6373 enum machine_mode mode0, mode1;
6375 enum insn_code icode;
6379 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6380 icode = CODE_FOR_altivec_stvx_v16qi;
6382 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6383 icode = CODE_FOR_altivec_stvx_v8hi;
6385 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6386 icode = CODE_FOR_altivec_stvx_v4si;
6388 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6389 icode = CODE_FOR_altivec_stvx_v4sf;
6396 arg0 = TREE_VALUE (arglist);
6397 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6398 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6399 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6400 mode0 = insn_data[icode].operand[0].mode;
6401 mode1 = insn_data[icode].operand[1].mode;
6403 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6404 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6405 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6406 op1 = copy_to_mode_reg (mode1, op1);
6408 pat = GEN_FCN (icode) (op0, op1);
6416 /* Expand the dst builtins. */
6418 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6421 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6422 tree arglist = TREE_OPERAND (exp, 1);
6423 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6424 tree arg0, arg1, arg2;
6425 enum machine_mode mode0, mode1, mode2;
6426 rtx pat, op0, op1, op2;
6427 struct builtin_description *d;
6432 /* Handle DST variants. */
6433 d = (struct builtin_description *) bdesc_dst;
6434 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6435 if (d->code == fcode)
6437 arg0 = TREE_VALUE (arglist);
6438 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6439 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6440 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6441 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6442 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6443 mode0 = insn_data[d->icode].operand[0].mode;
6444 mode1 = insn_data[d->icode].operand[1].mode;
6445 mode2 = insn_data[d->icode].operand[2].mode;
6447 /* Invalid arguments, bail out before generating bad rtl. */
6448 if (arg0 == error_mark_node
6449 || arg1 == error_mark_node
6450 || arg2 == error_mark_node)
6455 if (TREE_CODE (arg2) != INTEGER_CST
6456 || TREE_INT_CST_LOW (arg2) & ~0x3)
6458 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6462 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6463 op0 = copy_to_mode_reg (Pmode, op0);
6464 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6465 op1 = copy_to_mode_reg (mode1, op1);
6467 pat = GEN_FCN (d->icode) (op0, op1, op2);
6477 /* Expand the builtin in EXP and store the result in TARGET. Store
6478 true in *EXPANDEDP if we found a builtin to expand. */
6480 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6482 struct builtin_description *d;
6483 struct builtin_description_predicates *dp;
6485 enum insn_code icode;
6486 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6487 tree arglist = TREE_OPERAND (exp, 1);
6490 enum machine_mode tmode, mode0;
6491 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6493 target = altivec_expand_ld_builtin (exp, target, expandedp);
6497 target = altivec_expand_st_builtin (exp, target, expandedp);
6501 target = altivec_expand_dst_builtin (exp, target, expandedp);
6509 case ALTIVEC_BUILTIN_STVX:
6510 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6511 case ALTIVEC_BUILTIN_STVEBX:
6512 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6513 case ALTIVEC_BUILTIN_STVEHX:
6514 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6515 case ALTIVEC_BUILTIN_STVEWX:
6516 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6517 case ALTIVEC_BUILTIN_STVXL:
6518 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6520 case ALTIVEC_BUILTIN_MFVSCR:
6521 icode = CODE_FOR_altivec_mfvscr;
6522 tmode = insn_data[icode].operand[0].mode;
6525 || GET_MODE (target) != tmode
6526 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6527 target = gen_reg_rtx (tmode);
6529 pat = GEN_FCN (icode) (target);
6535 case ALTIVEC_BUILTIN_MTVSCR:
6536 icode = CODE_FOR_altivec_mtvscr;
6537 arg0 = TREE_VALUE (arglist);
6538 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6539 mode0 = insn_data[icode].operand[0].mode;
6541 /* If we got invalid arguments bail out before generating bad rtl. */
6542 if (arg0 == error_mark_node)
6545 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6546 op0 = copy_to_mode_reg (mode0, op0);
6548 pat = GEN_FCN (icode) (op0);
6553 case ALTIVEC_BUILTIN_DSSALL:
6554 emit_insn (gen_altivec_dssall ());
6557 case ALTIVEC_BUILTIN_DSS:
6558 icode = CODE_FOR_altivec_dss;
6559 arg0 = TREE_VALUE (arglist);
6561 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6562 mode0 = insn_data[icode].operand[0].mode;
6564 /* If we got invalid arguments bail out before generating bad rtl. */
6565 if (arg0 == error_mark_node)
6568 if (TREE_CODE (arg0) != INTEGER_CST
6569 || TREE_INT_CST_LOW (arg0) & ~0x3)
6571 error ("argument to dss must be a 2-bit unsigned literal");
6575 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6576 op0 = copy_to_mode_reg (mode0, op0);
6578 emit_insn (gen_altivec_dss (op0));
6581 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6582 arg0 = TREE_VALUE (arglist);
6583 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6584 || TREE_CODE (arg0) == ARRAY_REF)
6585 arg0 = TREE_OPERAND (arg0, 0);
6586 error ("invalid parameter combination for %qs AltiVec intrinsic",
6587 TREE_STRING_POINTER (arg0));
6592 /* Expand abs* operations. */
6593 d = (struct builtin_description *) bdesc_abs;
6594 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6595 if (d->code == fcode)
6596 return altivec_expand_abs_builtin (d->icode, arglist, target);
6598 /* Expand the AltiVec predicates. */
6599 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6600 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6601 if (dp->code == fcode)
6602 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6605 /* LV* are funky. We initialized them differently. */
6608 case ALTIVEC_BUILTIN_LVSL:
6609 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6611 case ALTIVEC_BUILTIN_LVSR:
6612 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6614 case ALTIVEC_BUILTIN_LVEBX:
6615 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6617 case ALTIVEC_BUILTIN_LVEHX:
6618 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6620 case ALTIVEC_BUILTIN_LVEWX:
6621 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6623 case ALTIVEC_BUILTIN_LVXL:
6624 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6626 case ALTIVEC_BUILTIN_LVX:
6627 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6638 /* Binops that need to be initialized manually, but can be expanded
6639 automagically by rs6000_expand_binop_builtin. */
6640 static struct builtin_description bdesc_2arg_spe[] =
6642 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6643 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6644 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6645 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6646 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6647 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6648 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6649 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6650 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6651 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6652 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6653 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6654 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6655 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6656 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6657 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6658 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6659 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6660 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6661 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6662 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6663 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6666 /* Expand the builtin in EXP and store the result in TARGET. Store
6667 true in *EXPANDEDP if we found a builtin to expand.
6669 This expands the SPE builtins that are not simple unary and binary
6672 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6674 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6675 tree arglist = TREE_OPERAND (exp, 1);
6677 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6678 enum insn_code icode;
6679 enum machine_mode tmode, mode0;
6681 struct builtin_description *d;
6686 /* Syntax check for a 5-bit unsigned immediate. */
6689 case SPE_BUILTIN_EVSTDD:
6690 case SPE_BUILTIN_EVSTDH:
6691 case SPE_BUILTIN_EVSTDW:
6692 case SPE_BUILTIN_EVSTWHE:
6693 case SPE_BUILTIN_EVSTWHO:
6694 case SPE_BUILTIN_EVSTWWE:
6695 case SPE_BUILTIN_EVSTWWO:
6696 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6697 if (TREE_CODE (arg1) != INTEGER_CST
6698 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6700 error ("argument 2 must be a 5-bit unsigned literal");
6708 /* The evsplat*i instructions are not quite generic. */
6711 case SPE_BUILTIN_EVSPLATFI:
6712 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6714 case SPE_BUILTIN_EVSPLATI:
6715 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6721 d = (struct builtin_description *) bdesc_2arg_spe;
6722 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6723 if (d->code == fcode)
6724 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6726 d = (struct builtin_description *) bdesc_spe_predicates;
6727 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6728 if (d->code == fcode)
6729 return spe_expand_predicate_builtin (d->icode, arglist, target);
6731 d = (struct builtin_description *) bdesc_spe_evsel;
6732 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6733 if (d->code == fcode)
6734 return spe_expand_evsel_builtin (d->icode, arglist, target);
6738 case SPE_BUILTIN_EVSTDDX:
6739 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6740 case SPE_BUILTIN_EVSTDHX:
6741 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6742 case SPE_BUILTIN_EVSTDWX:
6743 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6744 case SPE_BUILTIN_EVSTWHEX:
6745 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6746 case SPE_BUILTIN_EVSTWHOX:
6747 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6748 case SPE_BUILTIN_EVSTWWEX:
6749 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6750 case SPE_BUILTIN_EVSTWWOX:
6751 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6752 case SPE_BUILTIN_EVSTDD:
6753 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6754 case SPE_BUILTIN_EVSTDH:
6755 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6756 case SPE_BUILTIN_EVSTDW:
6757 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6758 case SPE_BUILTIN_EVSTWHE:
6759 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6760 case SPE_BUILTIN_EVSTWHO:
6761 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6762 case SPE_BUILTIN_EVSTWWE:
6763 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6764 case SPE_BUILTIN_EVSTWWO:
6765 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6766 case SPE_BUILTIN_MFSPEFSCR:
6767 icode = CODE_FOR_spe_mfspefscr;
6768 tmode = insn_data[icode].operand[0].mode;
6771 || GET_MODE (target) != tmode
6772 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6773 target = gen_reg_rtx (tmode);
6775 pat = GEN_FCN (icode) (target);
6780 case SPE_BUILTIN_MTSPEFSCR:
6781 icode = CODE_FOR_spe_mtspefscr;
6782 arg0 = TREE_VALUE (arglist);
6783 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6784 mode0 = insn_data[icode].operand[0].mode;
6786 if (arg0 == error_mark_node)
6789 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6790 op0 = copy_to_mode_reg (mode0, op0);
6792 pat = GEN_FCN (icode) (op0);
6805 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6807 rtx pat, scratch, tmp;
6808 tree form = TREE_VALUE (arglist);
6809 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6810 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6811 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6812 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6813 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6814 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6818 if (TREE_CODE (form) != INTEGER_CST)
6820 error ("argument 1 of __builtin_spe_predicate must be a constant");
6824 form_int = TREE_INT_CST_LOW (form);
6829 if (arg0 == error_mark_node || arg1 == error_mark_node)
6833 || GET_MODE (target) != SImode
6834 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6835 target = gen_reg_rtx (SImode);
6837 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6838 op0 = copy_to_mode_reg (mode0, op0);
6839 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6840 op1 = copy_to_mode_reg (mode1, op1);
6842 scratch = gen_reg_rtx (CCmode);
6844 pat = GEN_FCN (icode) (scratch, op0, op1);
6849 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6850 _lower_. We use one compare, but look in different bits of the
6851 CR for each variant.
6853 There are 2 elements in each SPE simd type (upper/lower). The CR
6854 bits are set as follows:
6856 BIT0 | BIT 1 | BIT 2 | BIT 3
6857 U | L | (U | L) | (U & L)
6859 So, for an "all" relationship, BIT 3 would be set.
6860 For an "any" relationship, BIT 2 would be set. Etc.
6862 Following traditional nomenclature, these bits map to:
6864 BIT0 | BIT 1 | BIT 2 | BIT 3
6867 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6872 /* All variant. OV bit. */
6874 /* We need to get to the OV bit, which is the ORDERED bit. We
6875 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6876 that's ugly and will trigger a validate_condition_mode abort.
6877 So let's just use another pattern. */
6878 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6880 /* Any variant. EQ bit. */
6884 /* Upper variant. LT bit. */
6888 /* Lower variant. GT bit. */
6893 error ("argument 1 of __builtin_spe_predicate is out of range");
6897 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6898 emit_move_insn (target, tmp);
6903 /* The evsel builtins look like this:
6905 e = __builtin_spe_evsel_OP (a, b, c, d);
6909 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6910 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6914 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6917 tree arg0 = TREE_VALUE (arglist);
6918 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6919 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6920 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6921 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6922 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6923 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6924 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6925 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6926 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6931 if (arg0 == error_mark_node || arg1 == error_mark_node
6932 || arg2 == error_mark_node || arg3 == error_mark_node)
6936 || GET_MODE (target) != mode0
6937 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6938 target = gen_reg_rtx (mode0);
6940 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6941 op0 = copy_to_mode_reg (mode0, op0);
6942 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6943 op1 = copy_to_mode_reg (mode0, op1);
6944 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6945 op2 = copy_to_mode_reg (mode0, op2);
6946 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6947 op3 = copy_to_mode_reg (mode0, op3);
6949 /* Generate the compare. */
6950 scratch = gen_reg_rtx (CCmode);
6951 pat = GEN_FCN (icode) (scratch, op0, op1);
6956 if (mode0 == V2SImode)
6957 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
6959 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
6964 /* Expand an expression EXP that calls a built-in function,
6965 with result going to TARGET if that's convenient
6966 (and in mode MODE if that's convenient).
6967 SUBTARGET may be used as the target for computing one of EXP's operands.
6968 IGNORE is nonzero if the value is to be ignored. */
6971 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
6972 enum machine_mode mode ATTRIBUTE_UNUSED,
6973 int ignore ATTRIBUTE_UNUSED)
6975 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6976 tree arglist = TREE_OPERAND (exp, 1);
6977 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6978 struct builtin_description *d;
6983 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
6984 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
6986 int icode = (int) CODE_FOR_altivec_lvsr;
6987 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6988 enum machine_mode mode = insn_data[icode].operand[1].mode;
6992 if (!TARGET_ALTIVEC)
6995 arg = TREE_VALUE (arglist);
6996 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
6998 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
6999 addr = memory_address (mode, op);
7000 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7004 /* For the load case need to negate the address. */
7005 op = gen_reg_rtx (GET_MODE (addr));
7006 emit_insn (gen_rtx_SET (VOIDmode, op,
7007 gen_rtx_NEG (GET_MODE (addr), addr)));
7009 op = gen_rtx_MEM (mode, op);
7012 || GET_MODE (target) != tmode
7013 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7014 target = gen_reg_rtx (tmode);
7016 /*pat = gen_altivec_lvsr (target, op);*/
7017 pat = GEN_FCN (icode) (target, op);
7027 ret = altivec_expand_builtin (exp, target, &success);
7034 ret = spe_expand_builtin (exp, target, &success);
7040 if (TARGET_ALTIVEC || TARGET_SPE)
7042 /* Handle simple unary operations. */
7043 d = (struct builtin_description *) bdesc_1arg;
7044 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7045 if (d->code == fcode)
7046 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7048 /* Handle simple binary operations. */
7049 d = (struct builtin_description *) bdesc_2arg;
7050 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7051 if (d->code == fcode)
7052 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7054 /* Handle simple ternary operations. */
7055 d = (struct builtin_description *) bdesc_3arg;
7056 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7057 if (d->code == fcode)
7058 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7066 build_opaque_vector_type (tree node, int nunits)
7068 node = copy_node (node);
7069 TYPE_MAIN_VARIANT (node) = node;
7070 return build_vector_type (node, nunits);
7074 rs6000_init_builtins (void)
7076 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7077 V2SF_type_node = build_vector_type (float_type_node, 2);
7078 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7079 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7080 V4SF_type_node = build_vector_type (float_type_node, 4);
7081 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7082 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7084 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7085 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7086 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7088 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7089 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7090 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7092 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7093 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7094 'vector unsigned short'. */
7096 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7097 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7098 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7099 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7101 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7102 get_identifier ("__bool char"),
7103 bool_char_type_node));
7104 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7105 get_identifier ("__bool short"),
7106 bool_short_type_node));
7107 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7108 get_identifier ("__bool int"),
7109 bool_int_type_node));
7110 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7111 get_identifier ("__pixel"),
7114 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7115 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7116 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7117 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7119 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7120 get_identifier ("__vector unsigned char"),
7121 unsigned_V16QI_type_node));
7122 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7123 get_identifier ("__vector signed char"),
7125 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7126 get_identifier ("__vector __bool char"),
7127 bool_V16QI_type_node));
7129 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7130 get_identifier ("__vector unsigned short"),
7131 unsigned_V8HI_type_node));
7132 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7133 get_identifier ("__vector signed short"),
7135 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7136 get_identifier ("__vector __bool short"),
7137 bool_V8HI_type_node));
7139 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7140 get_identifier ("__vector unsigned int"),
7141 unsigned_V4SI_type_node));
7142 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7143 get_identifier ("__vector signed int"),
7145 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7146 get_identifier ("__vector __bool int"),
7147 bool_V4SI_type_node));
7149 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7150 get_identifier ("__vector float"),
7152 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7153 get_identifier ("__vector __pixel"),
7154 pixel_V8HI_type_node));
7157 spe_init_builtins ();
7159 altivec_init_builtins ();
7160 if (TARGET_ALTIVEC || TARGET_SPE)
7161 rs6000_common_init_builtins ();
7164 /* Search through a set of builtins and enable the mask bits.
7165 DESC is an array of builtins.
7166 SIZE is the total number of builtins.
7167 START is the builtin enum at which to start.
7168 END is the builtin enum at which to end. */
7170 enable_mask_for_builtins (struct builtin_description *desc, int size,
7171 enum rs6000_builtins start,
7172 enum rs6000_builtins end)
7176 for (i = 0; i < size; ++i)
7177 if (desc[i].code == start)
7183 for (; i < size; ++i)
7185 /* Flip all the bits on. */
7186 desc[i].mask = target_flags;
7187 if (desc[i].code == end)
7193 spe_init_builtins (void)
7195 tree endlink = void_list_node;
7196 tree puint_type_node = build_pointer_type (unsigned_type_node);
7197 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7198 struct builtin_description *d;
7201 tree v2si_ftype_4_v2si
7202 = build_function_type
7203 (opaque_V2SI_type_node,
7204 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7205 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7206 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7207 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7210 tree v2sf_ftype_4_v2sf
7211 = build_function_type
7212 (opaque_V2SF_type_node,
7213 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7214 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7215 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7216 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7219 tree int_ftype_int_v2si_v2si
7220 = build_function_type
7222 tree_cons (NULL_TREE, integer_type_node,
7223 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7224 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7227 tree int_ftype_int_v2sf_v2sf
7228 = build_function_type
7230 tree_cons (NULL_TREE, integer_type_node,
7231 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7232 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7235 tree void_ftype_v2si_puint_int
7236 = build_function_type (void_type_node,
7237 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7238 tree_cons (NULL_TREE, puint_type_node,
7239 tree_cons (NULL_TREE,
7243 tree void_ftype_v2si_puint_char
7244 = build_function_type (void_type_node,
7245 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7246 tree_cons (NULL_TREE, puint_type_node,
7247 tree_cons (NULL_TREE,
7251 tree void_ftype_v2si_pv2si_int
7252 = build_function_type (void_type_node,
7253 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7254 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7255 tree_cons (NULL_TREE,
7259 tree void_ftype_v2si_pv2si_char
7260 = build_function_type (void_type_node,
7261 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7262 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7263 tree_cons (NULL_TREE,
7268 = build_function_type (void_type_node,
7269 tree_cons (NULL_TREE, integer_type_node, endlink));
7272 = build_function_type (integer_type_node, endlink);
7274 tree v2si_ftype_pv2si_int
7275 = build_function_type (opaque_V2SI_type_node,
7276 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7277 tree_cons (NULL_TREE, integer_type_node,
7280 tree v2si_ftype_puint_int
7281 = build_function_type (opaque_V2SI_type_node,
7282 tree_cons (NULL_TREE, puint_type_node,
7283 tree_cons (NULL_TREE, integer_type_node,
7286 tree v2si_ftype_pushort_int
7287 = build_function_type (opaque_V2SI_type_node,
7288 tree_cons (NULL_TREE, pushort_type_node,
7289 tree_cons (NULL_TREE, integer_type_node,
7292 tree v2si_ftype_signed_char
7293 = build_function_type (opaque_V2SI_type_node,
7294 tree_cons (NULL_TREE, signed_char_type_node,
7297 /* The initialization of the simple binary and unary builtins is
7298 done in rs6000_common_init_builtins, but we have to enable the
7299 mask bits here manually because we have run out of `target_flags'
7300 bits. We really need to redesign this mask business. */
7302 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7303 ARRAY_SIZE (bdesc_2arg),
7306 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7307 ARRAY_SIZE (bdesc_1arg),
7309 SPE_BUILTIN_EVSUBFUSIAAW);
7310 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7311 ARRAY_SIZE (bdesc_spe_predicates),
7312 SPE_BUILTIN_EVCMPEQ,
7313 SPE_BUILTIN_EVFSTSTLT);
7314 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7315 ARRAY_SIZE (bdesc_spe_evsel),
7316 SPE_BUILTIN_EVSEL_CMPGTS,
7317 SPE_BUILTIN_EVSEL_FSTSTEQ);
7319 (*lang_hooks.decls.pushdecl)
7320 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7321 opaque_V2SI_type_node));
7323 /* Initialize irregular SPE builtins. */
7325 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7326 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7327 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7328 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7329 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7330 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7331 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7332 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7333 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7334 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7335 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7336 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7337 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7338 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7339 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7340 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7341 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7342 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7345 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7346 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7347 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7348 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7349 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7350 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7351 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7352 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7353 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7354 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7355 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7356 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7357 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7358 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7359 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7360 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7361 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7362 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7363 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7364 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7365 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7366 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7369 d = (struct builtin_description *) bdesc_spe_predicates;
7370 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7374 switch (insn_data[d->icode].operand[1].mode)
7377 type = int_ftype_int_v2si_v2si;
7380 type = int_ftype_int_v2sf_v2sf;
7386 def_builtin (d->mask, d->name, type, d->code);
7389 /* Evsel predicates. */
7390 d = (struct builtin_description *) bdesc_spe_evsel;
7391 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7395 switch (insn_data[d->icode].operand[1].mode)
7398 type = v2si_ftype_4_v2si;
7401 type = v2sf_ftype_4_v2sf;
7407 def_builtin (d->mask, d->name, type, d->code);
7412 altivec_init_builtins (void)
7414 struct builtin_description *d;
7415 struct builtin_description_predicates *dp;
7417 tree pfloat_type_node = build_pointer_type (float_type_node);
7418 tree pint_type_node = build_pointer_type (integer_type_node);
7419 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7420 tree pchar_type_node = build_pointer_type (char_type_node);
7422 tree pvoid_type_node = build_pointer_type (void_type_node);
7424 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7425 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7426 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7427 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7429 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7431 tree int_ftype_int_v4si_v4si
7432 = build_function_type_list (integer_type_node,
7433 integer_type_node, V4SI_type_node,
7434 V4SI_type_node, NULL_TREE);
7435 tree v4sf_ftype_pcfloat
7436 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7437 tree void_ftype_pfloat_v4sf
7438 = build_function_type_list (void_type_node,
7439 pfloat_type_node, V4SF_type_node, NULL_TREE);
7440 tree v4si_ftype_pcint
7441 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7442 tree void_ftype_pint_v4si
7443 = build_function_type_list (void_type_node,
7444 pint_type_node, V4SI_type_node, NULL_TREE);
7445 tree v8hi_ftype_pcshort
7446 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7447 tree void_ftype_pshort_v8hi
7448 = build_function_type_list (void_type_node,
7449 pshort_type_node, V8HI_type_node, NULL_TREE);
7450 tree v16qi_ftype_pcchar
7451 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7452 tree void_ftype_pchar_v16qi
7453 = build_function_type_list (void_type_node,
7454 pchar_type_node, V16QI_type_node, NULL_TREE);
7455 tree void_ftype_v4si
7456 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7457 tree v8hi_ftype_void
7458 = build_function_type (V8HI_type_node, void_list_node);
7459 tree void_ftype_void
7460 = build_function_type (void_type_node, void_list_node);
7462 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7464 tree v16qi_ftype_long_pcvoid
7465 = build_function_type_list (V16QI_type_node,
7466 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7467 tree v8hi_ftype_long_pcvoid
7468 = build_function_type_list (V8HI_type_node,
7469 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7470 tree v4si_ftype_long_pcvoid
7471 = build_function_type_list (V4SI_type_node,
7472 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7474 tree void_ftype_v4si_long_pvoid
7475 = build_function_type_list (void_type_node,
7476 V4SI_type_node, long_integer_type_node,
7477 pvoid_type_node, NULL_TREE);
7478 tree void_ftype_v16qi_long_pvoid
7479 = build_function_type_list (void_type_node,
7480 V16QI_type_node, long_integer_type_node,
7481 pvoid_type_node, NULL_TREE);
7482 tree void_ftype_v8hi_long_pvoid
7483 = build_function_type_list (void_type_node,
7484 V8HI_type_node, long_integer_type_node,
7485 pvoid_type_node, NULL_TREE);
7486 tree int_ftype_int_v8hi_v8hi
7487 = build_function_type_list (integer_type_node,
7488 integer_type_node, V8HI_type_node,
7489 V8HI_type_node, NULL_TREE);
7490 tree int_ftype_int_v16qi_v16qi
7491 = build_function_type_list (integer_type_node,
7492 integer_type_node, V16QI_type_node,
7493 V16QI_type_node, NULL_TREE);
7494 tree int_ftype_int_v4sf_v4sf
7495 = build_function_type_list (integer_type_node,
7496 integer_type_node, V4SF_type_node,
7497 V4SF_type_node, NULL_TREE);
7498 tree v4si_ftype_v4si
7499 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7500 tree v8hi_ftype_v8hi
7501 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7502 tree v16qi_ftype_v16qi
7503 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7504 tree v4sf_ftype_v4sf
7505 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7506 tree void_ftype_pcvoid_int_int
7507 = build_function_type_list (void_type_node,
7508 pcvoid_type_node, integer_type_node,
7509 integer_type_node, NULL_TREE);
7510 tree int_ftype_pcchar
7511 = build_function_type_list (integer_type_node,
7512 pcchar_type_node, NULL_TREE);
7514 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7515 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7516 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7517 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7518 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7519 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7520 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7521 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7522 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7523 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7524 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7525 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7526 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7527 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7528 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7529 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7530 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7531 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7532 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7533 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7534 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7535 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7536 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7537 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7538 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7539 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7540 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7541 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7542 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7543 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7544 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7545 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7547 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7548 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7549 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7551 /* Add the DST variants. */
7552 d = (struct builtin_description *) bdesc_dst;
7553 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7554 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7556 /* Initialize the predicates. */
7557 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7558 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7560 enum machine_mode mode1;
7563 mode1 = insn_data[dp->icode].operand[1].mode;
7568 type = int_ftype_int_v4si_v4si;
7571 type = int_ftype_int_v8hi_v8hi;
7574 type = int_ftype_int_v16qi_v16qi;
7577 type = int_ftype_int_v4sf_v4sf;
7583 def_builtin (dp->mask, dp->name, type, dp->code);
7586 /* Initialize the abs* operators. */
7587 d = (struct builtin_description *) bdesc_abs;
7588 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7590 enum machine_mode mode0;
7593 mode0 = insn_data[d->icode].operand[0].mode;
7598 type = v4si_ftype_v4si;
7601 type = v8hi_ftype_v8hi;
7604 type = v16qi_ftype_v16qi;
7607 type = v4sf_ftype_v4sf;
7613 def_builtin (d->mask, d->name, type, d->code);
7620 /* Initialize target builtin that implements
7621 targetm.vectorize.builtin_mask_for_load. */
7623 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7624 v16qi_ftype_long_pcvoid,
7625 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7627 tree_cons (get_identifier ("const"),
7628 NULL_TREE, NULL_TREE));
7629 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7630 altivec_builtin_mask_for_load = decl;
7635 rs6000_common_init_builtins (void)
7637 struct builtin_description *d;
7640 tree v4sf_ftype_v4sf_v4sf_v16qi
7641 = build_function_type_list (V4SF_type_node,
7642 V4SF_type_node, V4SF_type_node,
7643 V16QI_type_node, NULL_TREE);
7644 tree v4si_ftype_v4si_v4si_v16qi
7645 = build_function_type_list (V4SI_type_node,
7646 V4SI_type_node, V4SI_type_node,
7647 V16QI_type_node, NULL_TREE);
7648 tree v8hi_ftype_v8hi_v8hi_v16qi
7649 = build_function_type_list (V8HI_type_node,
7650 V8HI_type_node, V8HI_type_node,
7651 V16QI_type_node, NULL_TREE);
7652 tree v16qi_ftype_v16qi_v16qi_v16qi
7653 = build_function_type_list (V16QI_type_node,
7654 V16QI_type_node, V16QI_type_node,
7655 V16QI_type_node, NULL_TREE);
7657 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7659 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7660 tree v16qi_ftype_int
7661 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7662 tree v8hi_ftype_v16qi
7663 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7664 tree v4sf_ftype_v4sf
7665 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7667 tree v2si_ftype_v2si_v2si
7668 = build_function_type_list (opaque_V2SI_type_node,
7669 opaque_V2SI_type_node,
7670 opaque_V2SI_type_node, NULL_TREE);
7672 tree v2sf_ftype_v2sf_v2sf
7673 = build_function_type_list (opaque_V2SF_type_node,
7674 opaque_V2SF_type_node,
7675 opaque_V2SF_type_node, NULL_TREE);
7677 tree v2si_ftype_int_int
7678 = build_function_type_list (opaque_V2SI_type_node,
7679 integer_type_node, integer_type_node,
7682 tree v2si_ftype_v2si
7683 = build_function_type_list (opaque_V2SI_type_node,
7684 opaque_V2SI_type_node, NULL_TREE);
7686 tree v2sf_ftype_v2sf
7687 = build_function_type_list (opaque_V2SF_type_node,
7688 opaque_V2SF_type_node, NULL_TREE);
7690 tree v2sf_ftype_v2si
7691 = build_function_type_list (opaque_V2SF_type_node,
7692 opaque_V2SI_type_node, NULL_TREE);
7694 tree v2si_ftype_v2sf
7695 = build_function_type_list (opaque_V2SI_type_node,
7696 opaque_V2SF_type_node, NULL_TREE);
7698 tree v2si_ftype_v2si_char
7699 = build_function_type_list (opaque_V2SI_type_node,
7700 opaque_V2SI_type_node,
7701 char_type_node, NULL_TREE);
7703 tree v2si_ftype_int_char
7704 = build_function_type_list (opaque_V2SI_type_node,
7705 integer_type_node, char_type_node, NULL_TREE);
7707 tree v2si_ftype_char
7708 = build_function_type_list (opaque_V2SI_type_node,
7709 char_type_node, NULL_TREE);
7711 tree int_ftype_int_int
7712 = build_function_type_list (integer_type_node,
7713 integer_type_node, integer_type_node,
7716 tree v4si_ftype_v4si_v4si
7717 = build_function_type_list (V4SI_type_node,
7718 V4SI_type_node, V4SI_type_node, NULL_TREE);
7719 tree v4sf_ftype_v4si_int
7720 = build_function_type_list (V4SF_type_node,
7721 V4SI_type_node, integer_type_node, NULL_TREE);
7722 tree v4si_ftype_v4sf_int
7723 = build_function_type_list (V4SI_type_node,
7724 V4SF_type_node, integer_type_node, NULL_TREE);
7725 tree v4si_ftype_v4si_int
7726 = build_function_type_list (V4SI_type_node,
7727 V4SI_type_node, integer_type_node, NULL_TREE);
7728 tree v8hi_ftype_v8hi_int
7729 = build_function_type_list (V8HI_type_node,
7730 V8HI_type_node, integer_type_node, NULL_TREE);
7731 tree v16qi_ftype_v16qi_int
7732 = build_function_type_list (V16QI_type_node,
7733 V16QI_type_node, integer_type_node, NULL_TREE);
7734 tree v16qi_ftype_v16qi_v16qi_int
7735 = build_function_type_list (V16QI_type_node,
7736 V16QI_type_node, V16QI_type_node,
7737 integer_type_node, NULL_TREE);
7738 tree v8hi_ftype_v8hi_v8hi_int
7739 = build_function_type_list (V8HI_type_node,
7740 V8HI_type_node, V8HI_type_node,
7741 integer_type_node, NULL_TREE);
7742 tree v4si_ftype_v4si_v4si_int
7743 = build_function_type_list (V4SI_type_node,
7744 V4SI_type_node, V4SI_type_node,
7745 integer_type_node, NULL_TREE);
7746 tree v4sf_ftype_v4sf_v4sf_int
7747 = build_function_type_list (V4SF_type_node,
7748 V4SF_type_node, V4SF_type_node,
7749 integer_type_node, NULL_TREE);
7750 tree v4sf_ftype_v4sf_v4sf
7751 = build_function_type_list (V4SF_type_node,
7752 V4SF_type_node, V4SF_type_node, NULL_TREE);
7753 tree v4sf_ftype_v4sf_v4sf_v4si
7754 = build_function_type_list (V4SF_type_node,
7755 V4SF_type_node, V4SF_type_node,
7756 V4SI_type_node, NULL_TREE);
7757 tree v4sf_ftype_v4sf_v4sf_v4sf
7758 = build_function_type_list (V4SF_type_node,
7759 V4SF_type_node, V4SF_type_node,
7760 V4SF_type_node, NULL_TREE);
7761 tree v4si_ftype_v4si_v4si_v4si
7762 = build_function_type_list (V4SI_type_node,
7763 V4SI_type_node, V4SI_type_node,
7764 V4SI_type_node, NULL_TREE);
7765 tree v8hi_ftype_v8hi_v8hi
7766 = build_function_type_list (V8HI_type_node,
7767 V8HI_type_node, V8HI_type_node, NULL_TREE);
7768 tree v8hi_ftype_v8hi_v8hi_v8hi
7769 = build_function_type_list (V8HI_type_node,
7770 V8HI_type_node, V8HI_type_node,
7771 V8HI_type_node, NULL_TREE);
7772 tree v4si_ftype_v8hi_v8hi_v4si
7773 = build_function_type_list (V4SI_type_node,
7774 V8HI_type_node, V8HI_type_node,
7775 V4SI_type_node, NULL_TREE);
7776 tree v4si_ftype_v16qi_v16qi_v4si
7777 = build_function_type_list (V4SI_type_node,
7778 V16QI_type_node, V16QI_type_node,
7779 V4SI_type_node, NULL_TREE);
7780 tree v16qi_ftype_v16qi_v16qi
7781 = build_function_type_list (V16QI_type_node,
7782 V16QI_type_node, V16QI_type_node, NULL_TREE);
7783 tree v4si_ftype_v4sf_v4sf
7784 = build_function_type_list (V4SI_type_node,
7785 V4SF_type_node, V4SF_type_node, NULL_TREE);
7786 tree v8hi_ftype_v16qi_v16qi
7787 = build_function_type_list (V8HI_type_node,
7788 V16QI_type_node, V16QI_type_node, NULL_TREE);
7789 tree v4si_ftype_v8hi_v8hi
7790 = build_function_type_list (V4SI_type_node,
7791 V8HI_type_node, V8HI_type_node, NULL_TREE);
7792 tree v8hi_ftype_v4si_v4si
7793 = build_function_type_list (V8HI_type_node,
7794 V4SI_type_node, V4SI_type_node, NULL_TREE);
7795 tree v16qi_ftype_v8hi_v8hi
7796 = build_function_type_list (V16QI_type_node,
7797 V8HI_type_node, V8HI_type_node, NULL_TREE);
7798 tree v4si_ftype_v16qi_v4si
7799 = build_function_type_list (V4SI_type_node,
7800 V16QI_type_node, V4SI_type_node, NULL_TREE);
7801 tree v4si_ftype_v16qi_v16qi
7802 = build_function_type_list (V4SI_type_node,
7803 V16QI_type_node, V16QI_type_node, NULL_TREE);
7804 tree v4si_ftype_v8hi_v4si
7805 = build_function_type_list (V4SI_type_node,
7806 V8HI_type_node, V4SI_type_node, NULL_TREE);
7807 tree v4si_ftype_v8hi
7808 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7809 tree int_ftype_v4si_v4si
7810 = build_function_type_list (integer_type_node,
7811 V4SI_type_node, V4SI_type_node, NULL_TREE);
7812 tree int_ftype_v4sf_v4sf
7813 = build_function_type_list (integer_type_node,
7814 V4SF_type_node, V4SF_type_node, NULL_TREE);
7815 tree int_ftype_v16qi_v16qi
7816 = build_function_type_list (integer_type_node,
7817 V16QI_type_node, V16QI_type_node, NULL_TREE);
7818 tree int_ftype_v8hi_v8hi
7819 = build_function_type_list (integer_type_node,
7820 V8HI_type_node, V8HI_type_node, NULL_TREE);
7822 /* Add the simple ternary operators. */
7823 d = (struct builtin_description *) bdesc_3arg;
7824 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7827 enum machine_mode mode0, mode1, mode2, mode3;
7830 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7833 mode0 = insn_data[d->icode].operand[0].mode;
7834 mode1 = insn_data[d->icode].operand[1].mode;
7835 mode2 = insn_data[d->icode].operand[2].mode;
7836 mode3 = insn_data[d->icode].operand[3].mode;
7838 /* When all four are of the same mode. */
7839 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7844 type = v4si_ftype_v4si_v4si_v4si;
7847 type = v4sf_ftype_v4sf_v4sf_v4sf;
7850 type = v8hi_ftype_v8hi_v8hi_v8hi;
7853 type = v16qi_ftype_v16qi_v16qi_v16qi;
7859 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7864 type = v4si_ftype_v4si_v4si_v16qi;
7867 type = v4sf_ftype_v4sf_v4sf_v16qi;
7870 type = v8hi_ftype_v8hi_v8hi_v16qi;
7873 type = v16qi_ftype_v16qi_v16qi_v16qi;
7879 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7880 && mode3 == V4SImode)
7881 type = v4si_ftype_v16qi_v16qi_v4si;
7882 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7883 && mode3 == V4SImode)
7884 type = v4si_ftype_v8hi_v8hi_v4si;
7885 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7886 && mode3 == V4SImode)
7887 type = v4sf_ftype_v4sf_v4sf_v4si;
7889 /* vchar, vchar, vchar, 4 bit literal. */
7890 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7892 type = v16qi_ftype_v16qi_v16qi_int;
7894 /* vshort, vshort, vshort, 4 bit literal. */
7895 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7897 type = v8hi_ftype_v8hi_v8hi_int;
7899 /* vint, vint, vint, 4 bit literal. */
7900 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7902 type = v4si_ftype_v4si_v4si_int;
7904 /* vfloat, vfloat, vfloat, 4 bit literal. */
7905 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7907 type = v4sf_ftype_v4sf_v4sf_int;
7912 def_builtin (d->mask, d->name, type, d->code);
7915 /* Add the simple binary operators. */
7916 d = (struct builtin_description *) bdesc_2arg;
7917 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7919 enum machine_mode mode0, mode1, mode2;
7922 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7925 mode0 = insn_data[d->icode].operand[0].mode;
7926 mode1 = insn_data[d->icode].operand[1].mode;
7927 mode2 = insn_data[d->icode].operand[2].mode;
7929 /* When all three operands are of the same mode. */
7930 if (mode0 == mode1 && mode1 == mode2)
7935 type = v4sf_ftype_v4sf_v4sf;
7938 type = v4si_ftype_v4si_v4si;
7941 type = v16qi_ftype_v16qi_v16qi;
7944 type = v8hi_ftype_v8hi_v8hi;
7947 type = v2si_ftype_v2si_v2si;
7950 type = v2sf_ftype_v2sf_v2sf;
7953 type = int_ftype_int_int;
7960 /* A few other combos we really don't want to do manually. */
7962 /* vint, vfloat, vfloat. */
7963 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
7964 type = v4si_ftype_v4sf_v4sf;
7966 /* vshort, vchar, vchar. */
7967 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
7968 type = v8hi_ftype_v16qi_v16qi;
7970 /* vint, vshort, vshort. */
7971 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
7972 type = v4si_ftype_v8hi_v8hi;
7974 /* vshort, vint, vint. */
7975 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
7976 type = v8hi_ftype_v4si_v4si;
7978 /* vchar, vshort, vshort. */
7979 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
7980 type = v16qi_ftype_v8hi_v8hi;
7982 /* vint, vchar, vint. */
7983 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
7984 type = v4si_ftype_v16qi_v4si;
7986 /* vint, vchar, vchar. */
7987 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
7988 type = v4si_ftype_v16qi_v16qi;
7990 /* vint, vshort, vint. */
7991 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
7992 type = v4si_ftype_v8hi_v4si;
7994 /* vint, vint, 5 bit literal. */
7995 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
7996 type = v4si_ftype_v4si_int;
7998 /* vshort, vshort, 5 bit literal. */
7999 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8000 type = v8hi_ftype_v8hi_int;
8002 /* vchar, vchar, 5 bit literal. */
8003 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8004 type = v16qi_ftype_v16qi_int;
8006 /* vfloat, vint, 5 bit literal. */
8007 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8008 type = v4sf_ftype_v4si_int;
8010 /* vint, vfloat, 5 bit literal. */
8011 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8012 type = v4si_ftype_v4sf_int;
8014 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8015 type = v2si_ftype_int_int;
8017 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8018 type = v2si_ftype_v2si_char;
8020 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8021 type = v2si_ftype_int_char;
8024 else if (mode0 == SImode)
8029 type = int_ftype_v4si_v4si;
8032 type = int_ftype_v4sf_v4sf;
8035 type = int_ftype_v16qi_v16qi;
8038 type = int_ftype_v8hi_v8hi;
8048 def_builtin (d->mask, d->name, type, d->code);
8051 /* Add the simple unary operators. */
8052 d = (struct builtin_description *) bdesc_1arg;
8053 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8055 enum machine_mode mode0, mode1;
8058 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8061 mode0 = insn_data[d->icode].operand[0].mode;
8062 mode1 = insn_data[d->icode].operand[1].mode;
8064 if (mode0 == V4SImode && mode1 == QImode)
8065 type = v4si_ftype_int;
8066 else if (mode0 == V8HImode && mode1 == QImode)
8067 type = v8hi_ftype_int;
8068 else if (mode0 == V16QImode && mode1 == QImode)
8069 type = v16qi_ftype_int;
8070 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8071 type = v4sf_ftype_v4sf;
8072 else if (mode0 == V8HImode && mode1 == V16QImode)
8073 type = v8hi_ftype_v16qi;
8074 else if (mode0 == V4SImode && mode1 == V8HImode)
8075 type = v4si_ftype_v8hi;
8076 else if (mode0 == V2SImode && mode1 == V2SImode)
8077 type = v2si_ftype_v2si;
8078 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8079 type = v2sf_ftype_v2sf;
8080 else if (mode0 == V2SFmode && mode1 == V2SImode)
8081 type = v2sf_ftype_v2si;
8082 else if (mode0 == V2SImode && mode1 == V2SFmode)
8083 type = v2si_ftype_v2sf;
8084 else if (mode0 == V2SImode && mode1 == QImode)
8085 type = v2si_ftype_char;
8089 def_builtin (d->mask, d->name, type, d->code);
8094 rs6000_init_libfuncs (void)
8096 if (!TARGET_HARD_FLOAT)
8099 if (DEFAULT_ABI != ABI_V4)
8101 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8103 /* AIX library routines for float->int conversion. */
8104 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8105 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8106 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8107 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8110 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8111 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8112 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8113 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8114 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8118 /* 32-bit SVR4 quad floating point routines. */
8120 set_optab_libfunc (add_optab, TFmode, "_q_add");
8121 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8122 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8123 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8124 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8125 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8126 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8128 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8129 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8130 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8131 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8132 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8133 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8135 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8136 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8137 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8138 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8139 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8140 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8141 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8146 /* Expand a block clear operation, and return 1 if successful. Return 0
8147 if we should let the compiler generate normal code.
8149 operands[0] is the destination
8150 operands[1] is the length
8151 operands[2] is the alignment */
8154 expand_block_clear (rtx operands[])
8156 rtx orig_dest = operands[0];
8157 rtx bytes_rtx = operands[1];
8158 rtx align_rtx = operands[2];
8159 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8160 HOST_WIDE_INT align;
8161 HOST_WIDE_INT bytes;
8166 /* If this is not a fixed size move, just call memcpy */
8170 /* If this is not a fixed size alignment, abort */
8171 if (GET_CODE (align_rtx) != CONST_INT)
8173 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8175 /* Anything to clear? */
8176 bytes = INTVAL (bytes_rtx);
8180 /* Use the builtin memset after a point, to avoid huge code bloat.
8181 When optimize_size, avoid any significant code bloat; calling
8182 memset is about 4 instructions, so allow for one instruction to
8183 load zero and three to do clearing. */
8184 if (TARGET_ALTIVEC && align >= 128)
8186 else if (TARGET_POWERPC64 && align >= 32)
8191 if (optimize_size && bytes > 3 * clear_step)
8193 if (! optimize_size && bytes > 8 * clear_step)
8196 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8198 enum machine_mode mode = BLKmode;
8201 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8206 else if (bytes >= 8 && TARGET_POWERPC64
8207 /* 64-bit loads and stores require word-aligned
8209 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8214 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8215 { /* move 4 bytes */
8219 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8220 { /* move 2 bytes */
8224 else /* move 1 byte at a time */
8230 dest = adjust_address (orig_dest, mode, offset);
8232 emit_move_insn (dest, CONST0_RTX (mode));
8239 /* Expand a block move operation, and return 1 if successful. Return 0
8240 if we should let the compiler generate normal code.
8242 operands[0] is the destination
8243 operands[1] is the source
8244 operands[2] is the length
8245 operands[3] is the alignment */
8247 #define MAX_MOVE_REG 4
8250 expand_block_move (rtx operands[])
8252 rtx orig_dest = operands[0];
8253 rtx orig_src = operands[1];
8254 rtx bytes_rtx = operands[2];
8255 rtx align_rtx = operands[3];
8256 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8261 rtx stores[MAX_MOVE_REG];
8264 /* If this is not a fixed size move, just call memcpy */
8268 /* If this is not a fixed size alignment, abort */
8269 if (GET_CODE (align_rtx) != CONST_INT)
8271 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8273 /* Anything to move? */
8274 bytes = INTVAL (bytes_rtx);
8278 /* store_one_arg depends on expand_block_move to handle at least the size of
8279 reg_parm_stack_space. */
8280 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8283 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8286 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8287 rtx (*mov) (rtx, rtx);
8289 enum machine_mode mode = BLKmode;
8292 /* Altivec first, since it will be faster than a string move
8293 when it applies, and usually not significantly larger. */
8294 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8298 gen_func.mov = gen_movv4si;
8300 else if (TARGET_STRING
8301 && bytes > 24 /* move up to 32 bytes at a time */
8309 && ! fixed_regs[12])
8311 move_bytes = (bytes > 32) ? 32 : bytes;
8312 gen_func.movmemsi = gen_movmemsi_8reg;
8314 else if (TARGET_STRING
8315 && bytes > 16 /* move up to 24 bytes at a time */
8321 && ! fixed_regs[10])
8323 move_bytes = (bytes > 24) ? 24 : bytes;
8324 gen_func.movmemsi = gen_movmemsi_6reg;
8326 else if (TARGET_STRING
8327 && bytes > 8 /* move up to 16 bytes at a time */
8333 move_bytes = (bytes > 16) ? 16 : bytes;
8334 gen_func.movmemsi = gen_movmemsi_4reg;
8336 else if (bytes >= 8 && TARGET_POWERPC64
8337 /* 64-bit loads and stores require word-aligned
8339 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8343 gen_func.mov = gen_movdi;
8345 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8346 { /* move up to 8 bytes at a time */
8347 move_bytes = (bytes > 8) ? 8 : bytes;
8348 gen_func.movmemsi = gen_movmemsi_2reg;
8350 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8351 { /* move 4 bytes */
8354 gen_func.mov = gen_movsi;
8356 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8357 { /* move 2 bytes */
8360 gen_func.mov = gen_movhi;
8362 else if (TARGET_STRING && bytes > 1)
8363 { /* move up to 4 bytes at a time */
8364 move_bytes = (bytes > 4) ? 4 : bytes;
8365 gen_func.movmemsi = gen_movmemsi_1reg;
8367 else /* move 1 byte at a time */
8371 gen_func.mov = gen_movqi;
8374 src = adjust_address (orig_src, mode, offset);
8375 dest = adjust_address (orig_dest, mode, offset);
8377 if (mode != BLKmode)
8379 rtx tmp_reg = gen_reg_rtx (mode);
8381 emit_insn ((*gen_func.mov) (tmp_reg, src));
8382 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8385 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8388 for (i = 0; i < num_reg; i++)
8389 emit_insn (stores[i]);
8393 if (mode == BLKmode)
8395 /* Move the address into scratch registers. The movmemsi
8396 patterns require zero offset. */
8397 if (!REG_P (XEXP (src, 0)))
8399 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8400 src = replace_equiv_address (src, src_reg);
8402 set_mem_size (src, GEN_INT (move_bytes));
8404 if (!REG_P (XEXP (dest, 0)))
8406 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8407 dest = replace_equiv_address (dest, dest_reg);
8409 set_mem_size (dest, GEN_INT (move_bytes));
8411 emit_insn ((*gen_func.movmemsi) (dest, src,
8412 GEN_INT (move_bytes & 31),
8421 /* Return a string to perform a load_multiple operation.
8422 operands[0] is the vector.
8423 operands[1] is the source address.
8424 operands[2] is the first destination register. */
8427 rs6000_output_load_multiple (rtx operands[3])
8429 /* We have to handle the case where the pseudo used to contain the address
8430 is assigned to one of the output registers. */
8432 int words = XVECLEN (operands[0], 0);
8435 if (XVECLEN (operands[0], 0) == 1)
8436 return "{l|lwz} %2,0(%1)";
8438 for (i = 0; i < words; i++)
8439 if (refers_to_regno_p (REGNO (operands[2]) + i,
8440 REGNO (operands[2]) + i + 1, operands[1], 0))
8444 xop[0] = GEN_INT (4 * (words-1));
8445 xop[1] = operands[1];
8446 xop[2] = operands[2];
8447 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8452 xop[0] = GEN_INT (4 * (words-1));
8453 xop[1] = operands[1];
8454 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8455 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8460 for (j = 0; j < words; j++)
8463 xop[0] = GEN_INT (j * 4);
8464 xop[1] = operands[1];
8465 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8466 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8468 xop[0] = GEN_INT (i * 4);
8469 xop[1] = operands[1];
8470 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8475 return "{lsi|lswi} %2,%1,%N0";
8479 /* A validation routine: say whether CODE, a condition code, and MODE
8480 match. The other alternatives either don't make sense or should
8481 never be generated. */
8484 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8486 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8487 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8488 || GET_MODE_CLASS (mode) != MODE_CC)
8491 /* These don't make sense. */
8492 if ((code == GT || code == LT || code == GE || code == LE)
8493 && mode == CCUNSmode)
8496 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8497 && mode != CCUNSmode)
8500 if (mode != CCFPmode
8501 && (code == ORDERED || code == UNORDERED
8502 || code == UNEQ || code == LTGT
8503 || code == UNGT || code == UNLT
8504 || code == UNGE || code == UNLE))
8507 /* These should never be generated except for
8508 flag_finite_math_only. */
8509 if (mode == CCFPmode
8510 && ! flag_finite_math_only
8511 && (code == LE || code == GE
8512 || code == UNEQ || code == LTGT
8513 || code == UNGT || code == UNLT))
8516 /* These are invalid; the information is not there. */
8517 if (mode == CCEQmode
8518 && code != EQ && code != NE)
8523 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8524 mask required to convert the result of a rotate insn into a shift
8525 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8528 includes_lshift_p (rtx shiftop, rtx andop)
8530 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8532 shift_mask <<= INTVAL (shiftop);
8534 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8537 /* Similar, but for right shift. */
8540 includes_rshift_p (rtx shiftop, rtx andop)
8542 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8544 shift_mask >>= INTVAL (shiftop);
8546 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8549 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8550 to perform a left shift. It must have exactly SHIFTOP least
8551 significant 0's, then one or more 1's, then zero or more 0's. */
8554 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8556 if (GET_CODE (andop) == CONST_INT)
8558 HOST_WIDE_INT c, lsb, shift_mask;
8561 if (c == 0 || c == ~0)
8565 shift_mask <<= INTVAL (shiftop);
8567 /* Find the least significant one bit. */
8570 /* It must coincide with the LSB of the shift mask. */
8571 if (-lsb != shift_mask)
8574 /* Invert to look for the next transition (if any). */
8577 /* Remove the low group of ones (originally low group of zeros). */
8580 /* Again find the lsb, and check we have all 1's above. */
8584 else if (GET_CODE (andop) == CONST_DOUBLE
8585 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8587 HOST_WIDE_INT low, high, lsb;
8588 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8590 low = CONST_DOUBLE_LOW (andop);
8591 if (HOST_BITS_PER_WIDE_INT < 64)
8592 high = CONST_DOUBLE_HIGH (andop);
8594 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8595 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8598 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8600 shift_mask_high = ~0;
8601 if (INTVAL (shiftop) > 32)
8602 shift_mask_high <<= INTVAL (shiftop) - 32;
8606 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8613 return high == -lsb;
8616 shift_mask_low = ~0;
8617 shift_mask_low <<= INTVAL (shiftop);
8621 if (-lsb != shift_mask_low)
8624 if (HOST_BITS_PER_WIDE_INT < 64)
8629 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8632 return high == -lsb;
8636 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8642 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8643 to perform a left shift. It must have SHIFTOP or more least
8644 significant 0's, with the remainder of the word 1's. */
8647 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8649 if (GET_CODE (andop) == CONST_INT)
8651 HOST_WIDE_INT c, lsb, shift_mask;
8654 shift_mask <<= INTVAL (shiftop);
8657 /* Find the least significant one bit. */
8660 /* It must be covered by the shift mask.
8661 This test also rejects c == 0. */
8662 if ((lsb & shift_mask) == 0)
8665 /* Check we have all 1's above the transition, and reject all 1's. */
8666 return c == -lsb && lsb != 1;
8668 else if (GET_CODE (andop) == CONST_DOUBLE
8669 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8671 HOST_WIDE_INT low, lsb, shift_mask_low;
8673 low = CONST_DOUBLE_LOW (andop);
8675 if (HOST_BITS_PER_WIDE_INT < 64)
8677 HOST_WIDE_INT high, shift_mask_high;
8679 high = CONST_DOUBLE_HIGH (andop);
8683 shift_mask_high = ~0;
8684 if (INTVAL (shiftop) > 32)
8685 shift_mask_high <<= INTVAL (shiftop) - 32;
8689 if ((lsb & shift_mask_high) == 0)
8692 return high == -lsb;
8698 shift_mask_low = ~0;
8699 shift_mask_low <<= INTVAL (shiftop);
8703 if ((lsb & shift_mask_low) == 0)
8706 return low == -lsb && lsb != 1;
8712 /* Return 1 if operands will generate a valid arguments to rlwimi
8713 instruction for insert with right shift in 64-bit mode. The mask may
8714 not start on the first bit or stop on the last bit because wrap-around
8715 effects of instruction do not correspond to semantics of RTL insn. */
8718 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8720 if (INTVAL (startop) < 64
8721 && INTVAL (startop) > 32
8722 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8723 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8724 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8725 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8726 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8732 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8733 for lfq and stfq insns iff the registers are hard registers. */
8736 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8738 /* We might have been passed a SUBREG. */
8739 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8742 /* We might have been passed non floating point registers. */
8743 if (!FP_REGNO_P (REGNO (reg1))
8744 || !FP_REGNO_P (REGNO (reg2)))
8747 return (REGNO (reg1) == REGNO (reg2) - 1);
8750 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8751 addr1 and addr2 must be in consecutive memory locations
8752 (addr2 == addr1 + 8). */
8755 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
8761 /* The mems cannot be volatile. */
8762 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8765 addr1 = XEXP (mem1, 0);
8766 addr2 = XEXP (mem2, 0);
8768 /* Extract an offset (if used) from the first addr. */
8769 if (GET_CODE (addr1) == PLUS)
8771 /* If not a REG, return zero. */
8772 if (GET_CODE (XEXP (addr1, 0)) != REG)
8776 reg1 = REGNO (XEXP (addr1, 0));
8777 /* The offset must be constant! */
8778 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8780 offset1 = INTVAL (XEXP (addr1, 1));
8783 else if (GET_CODE (addr1) != REG)
8787 reg1 = REGNO (addr1);
8788 /* This was a simple (mem (reg)) expression. Offset is 0. */
8792 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8793 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8794 register as addr1. */
8795 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8797 if (GET_CODE (addr2) != PLUS)
8800 if (GET_CODE (XEXP (addr2, 0)) != REG
8801 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8804 if (reg1 != REGNO (XEXP (addr2, 0)))
8807 /* The offset for the second addr must be 8 more than the first addr. */
8808 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8811 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8816 /* Return the register class of a scratch register needed to copy IN into
8817 or out of a register in CLASS in MODE. If it can be done directly,
8818 NO_REGS is returned. */
8821 secondary_reload_class (enum reg_class class,
8822 enum machine_mode mode ATTRIBUTE_UNUSED,
8827 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8829 && MACHOPIC_INDIRECT
8833 /* We cannot copy a symbolic operand directly into anything
8834 other than BASE_REGS for TARGET_ELF. So indicate that a
8835 register from BASE_REGS is needed as an intermediate
8838 On Darwin, pic addresses require a load from memory, which
8839 needs a base register. */
8840 if (class != BASE_REGS
8841 && (GET_CODE (in) == SYMBOL_REF
8842 || GET_CODE (in) == HIGH
8843 || GET_CODE (in) == LABEL_REF
8844 || GET_CODE (in) == CONST))
8848 if (GET_CODE (in) == REG)
8851 if (regno >= FIRST_PSEUDO_REGISTER)
8853 regno = true_regnum (in);
8854 if (regno >= FIRST_PSEUDO_REGISTER)
8858 else if (GET_CODE (in) == SUBREG)
8860 regno = true_regnum (in);
8861 if (regno >= FIRST_PSEUDO_REGISTER)
8867 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8869 if (class == GENERAL_REGS || class == BASE_REGS
8870 || (regno >= 0 && INT_REGNO_P (regno)))
8873 /* Constants, memory, and FP registers can go into FP registers. */
8874 if ((regno == -1 || FP_REGNO_P (regno))
8875 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8878 /* Memory, and AltiVec registers can go into AltiVec registers. */
8879 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8880 && class == ALTIVEC_REGS)
8883 /* We can copy among the CR registers. */
8884 if ((class == CR_REGS || class == CR0_REGS)
8885 && regno >= 0 && CR_REGNO_P (regno))
8888 /* Otherwise, we need GENERAL_REGS. */
8889 return GENERAL_REGS;
8892 /* Given a comparison operation, return the bit number in CCR to test. We
8893 know this is a valid comparison.
8895 SCC_P is 1 if this is for an scc. That means that %D will have been
8896 used instead of %C, so the bits will be in different places.
8898 Return -1 if OP isn't a valid comparison for some reason. */
8901 ccr_bit (rtx op, int scc_p)
8903 enum rtx_code code = GET_CODE (op);
8904 enum machine_mode cc_mode;
8909 if (!COMPARISON_P (op))
8914 if (GET_CODE (reg) != REG
8915 || ! CR_REGNO_P (REGNO (reg)))
8918 cc_mode = GET_MODE (reg);
8919 cc_regnum = REGNO (reg);
8920 base_bit = 4 * (cc_regnum - CR0_REGNO);
8922 validate_condition_mode (code, cc_mode);
8924 /* When generating a sCOND operation, only positive conditions are
8926 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8927 && code != GTU && code != LTU)
8933 return scc_p ? base_bit + 3 : base_bit + 2;
8935 return base_bit + 2;
8936 case GT: case GTU: case UNLE:
8937 return base_bit + 1;
8938 case LT: case LTU: case UNGE:
8940 case ORDERED: case UNORDERED:
8941 return base_bit + 3;
8944 /* If scc, we will have done a cror to put the bit in the
8945 unordered position. So test that bit. For integer, this is ! LT
8946 unless this is an scc insn. */
8947 return scc_p ? base_bit + 3 : base_bit;
8950 return scc_p ? base_bit + 3 : base_bit + 1;
8957 /* Return the GOT register. */
8960 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
8962 /* The second flow pass currently (June 1999) can't update
8963 regs_ever_live without disturbing other parts of the compiler, so
8964 update it here to make the prolog/epilogue code happy. */
8965 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
8966 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
8968 current_function_uses_pic_offset_table = 1;
8970 return pic_offset_table_rtx;
8973 /* Function to init struct machine_function.
8974 This will be called, via a pointer variable,
8975 from push_function_context. */
8977 static struct machine_function *
8978 rs6000_init_machine_status (void)
8980 return ggc_alloc_cleared (sizeof (machine_function));
8983 /* These macros test for integers and extract the low-order bits. */
8985 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
8986 && GET_MODE (X) == VOIDmode)
8988 #define INT_LOWPART(X) \
8989 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
8995 unsigned long val = INT_LOWPART (op);
8997 /* If the high bit is zero, the value is the first 1 bit we find
8999 if ((val & 0x80000000) == 0)
9001 if ((val & 0xffffffff) == 0)
9005 while (((val <<= 1) & 0x80000000) == 0)
9010 /* If the high bit is set and the low bit is not, or the mask is all
9011 1's, the value is zero. */
9012 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9015 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9018 while (((val >>= 1) & 1) != 0)
9028 unsigned long val = INT_LOWPART (op);
9030 /* If the low bit is zero, the value is the first 1 bit we find from
9034 if ((val & 0xffffffff) == 0)
9038 while (((val >>= 1) & 1) == 0)
9044 /* If the low bit is set and the high bit is not, or the mask is all
9045 1's, the value is 31. */
9046 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9049 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9052 while (((val <<= 1) & 0x80000000) != 0)
9058 /* Locate some local-dynamic symbol still in use by this function
9059 so that we can print its name in some tls_ld pattern. */
9062 rs6000_get_some_local_dynamic_name (void)
9066 if (cfun->machine->some_ld_name)
9067 return cfun->machine->some_ld_name;
9069 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9071 && for_each_rtx (&PATTERN (insn),
9072 rs6000_get_some_local_dynamic_name_1, 0))
9073 return cfun->machine->some_ld_name;
9078 /* Helper function for rs6000_get_some_local_dynamic_name. */
9081 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9085 if (GET_CODE (x) == SYMBOL_REF)
9087 const char *str = XSTR (x, 0);
9088 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9090 cfun->machine->some_ld_name = str;
9098 /* Write out a function code label. */
9101 rs6000_output_function_entry (FILE *file, const char *fname)
9103 if (fname[0] != '.')
9105 switch (DEFAULT_ABI)
9114 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9123 RS6000_OUTPUT_BASENAME (file, fname);
9125 assemble_name (file, fname);
9128 /* Print an operand. Recognize special options, documented below. */
9131 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9132 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9134 #define SMALL_DATA_RELOC "sda21"
9135 #define SMALL_DATA_REG 0
9139 print_operand (FILE *file, rtx x, int code)
9143 unsigned HOST_WIDE_INT uval;
9148 /* Write out an instruction after the call which may be replaced
9149 with glue code by the loader. This depends on the AIX version. */
9150 asm_fprintf (file, RS6000_CALL_GLUE);
9153 /* %a is output_address. */
9156 /* If X is a constant integer whose low-order 5 bits are zero,
9157 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9158 in the AIX assembler where "sri" with a zero shift count
9159 writes a trash instruction. */
9160 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9167 /* If constant, low-order 16 bits of constant, unsigned.
9168 Otherwise, write normally. */
9170 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9172 print_operand (file, x, 0);
9176 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9177 for 64-bit mask direction. */
9178 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
9181 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9185 /* X is a CR register. Print the number of the GT bit of the CR. */
9186 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9187 output_operand_lossage ("invalid %%E value");
9189 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9193 /* Like 'J' but get to the EQ bit. */
9194 if (GET_CODE (x) != REG)
9197 /* Bit 1 is EQ bit. */
9198 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9200 fprintf (file, "%d", i);
9204 /* X is a CR register. Print the number of the EQ bit of the CR */
9205 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9206 output_operand_lossage ("invalid %%E value");
9208 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9212 /* X is a CR register. Print the shift count needed to move it
9213 to the high-order four bits. */
9214 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9215 output_operand_lossage ("invalid %%f value");
9217 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9221 /* Similar, but print the count for the rotate in the opposite
9223 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9224 output_operand_lossage ("invalid %%F value");
9226 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9230 /* X is a constant integer. If it is negative, print "m",
9231 otherwise print "z". This is to make an aze or ame insn. */
9232 if (GET_CODE (x) != CONST_INT)
9233 output_operand_lossage ("invalid %%G value");
9234 else if (INTVAL (x) >= 0)
9241 /* If constant, output low-order five bits. Otherwise, write
9244 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9246 print_operand (file, x, 0);
9250 /* If constant, output low-order six bits. Otherwise, write
9253 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9255 print_operand (file, x, 0);
9259 /* Print `i' if this is a constant, else nothing. */
9265 /* Write the bit number in CCR for jump. */
9268 output_operand_lossage ("invalid %%j code");
9270 fprintf (file, "%d", i);
9274 /* Similar, but add one for shift count in rlinm for scc and pass
9275 scc flag to `ccr_bit'. */
9278 output_operand_lossage ("invalid %%J code");
9280 /* If we want bit 31, write a shift count of zero, not 32. */
9281 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9285 /* X must be a constant. Write the 1's complement of the
9288 output_operand_lossage ("invalid %%k value");
9290 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9294 /* X must be a symbolic constant on ELF. Write an
9295 expression suitable for an 'addi' that adds in the low 16
9297 if (GET_CODE (x) != CONST)
9299 print_operand_address (file, x);
9304 if (GET_CODE (XEXP (x, 0)) != PLUS
9305 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9306 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9307 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9308 output_operand_lossage ("invalid %%K value");
9309 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9311 /* For GNU as, there must be a non-alphanumeric character
9312 between 'l' and the number. The '-' is added by
9313 print_operand() already. */
9314 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9316 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9320 /* %l is output_asm_label. */
9323 /* Write second word of DImode or DFmode reference. Works on register
9324 or non-indexed memory only. */
9325 if (GET_CODE (x) == REG)
9326 fputs (reg_names[REGNO (x) + 1], file);
9327 else if (GET_CODE (x) == MEM)
9329 /* Handle possible auto-increment. Since it is pre-increment and
9330 we have already done it, we can just use an offset of word. */
9331 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9332 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9333 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9336 output_address (XEXP (adjust_address_nv (x, SImode,
9340 if (small_data_operand (x, GET_MODE (x)))
9341 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9342 reg_names[SMALL_DATA_REG]);
9347 /* MB value for a mask operand. */
9348 if (! mask_operand (x, SImode))
9349 output_operand_lossage ("invalid %%m value");
9351 fprintf (file, "%d", extract_MB (x));
9355 /* ME value for a mask operand. */
9356 if (! mask_operand (x, SImode))
9357 output_operand_lossage ("invalid %%M value");
9359 fprintf (file, "%d", extract_ME (x));
9362 /* %n outputs the negative of its operand. */
9365 /* Write the number of elements in the vector times 4. */
9366 if (GET_CODE (x) != PARALLEL)
9367 output_operand_lossage ("invalid %%N value");
9369 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9373 /* Similar, but subtract 1 first. */
9374 if (GET_CODE (x) != PARALLEL)
9375 output_operand_lossage ("invalid %%O value");
9377 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9381 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9383 || INT_LOWPART (x) < 0
9384 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9385 output_operand_lossage ("invalid %%p value");
9387 fprintf (file, "%d", i);
9391 /* The operand must be an indirect memory reference. The result
9392 is the register name. */
9393 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9394 || REGNO (XEXP (x, 0)) >= 32)
9395 output_operand_lossage ("invalid %%P value");
9397 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9401 /* This outputs the logical code corresponding to a boolean
9402 expression. The expression may have one or both operands
9403 negated (if one, only the first one). For condition register
9404 logical operations, it will also treat the negated
9405 CR codes as NOTs, but not handle NOTs of them. */
9407 const char *const *t = 0;
9409 enum rtx_code code = GET_CODE (x);
9410 static const char * const tbl[3][3] = {
9411 { "and", "andc", "nor" },
9412 { "or", "orc", "nand" },
9413 { "xor", "eqv", "xor" } };
9417 else if (code == IOR)
9419 else if (code == XOR)
9422 output_operand_lossage ("invalid %%q value");
9424 if (GET_CODE (XEXP (x, 0)) != NOT)
9428 if (GET_CODE (XEXP (x, 1)) == NOT)
9446 /* X is a CR register. Print the mask for `mtcrf'. */
9447 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9448 output_operand_lossage ("invalid %%R value");
9450 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9454 /* Low 5 bits of 32 - value */
9456 output_operand_lossage ("invalid %%s value");
9458 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9462 /* PowerPC64 mask position. All 0's is excluded.
9463 CONST_INT 32-bit mask is considered sign-extended so any
9464 transition must occur within the CONST_INT, not on the boundary. */
9465 if (! mask64_operand (x, DImode))
9466 output_operand_lossage ("invalid %%S value");
9468 uval = INT_LOWPART (x);
9470 if (uval & 1) /* Clear Left */
9472 #if HOST_BITS_PER_WIDE_INT > 64
9473 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9477 else /* Clear Right */
9480 #if HOST_BITS_PER_WIDE_INT > 64
9481 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9489 fprintf (file, "%d", i);
9493 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9494 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9497 /* Bit 3 is OV bit. */
9498 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9500 /* If we want bit 31, write a shift count of zero, not 32. */
9501 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9505 /* Print the symbolic name of a branch target register. */
9506 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9507 && REGNO (x) != COUNT_REGISTER_REGNUM))
9508 output_operand_lossage ("invalid %%T value");
9509 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9510 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9512 fputs ("ctr", file);
9516 /* High-order 16 bits of constant for use in unsigned operand. */
9518 output_operand_lossage ("invalid %%u value");
9520 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9521 (INT_LOWPART (x) >> 16) & 0xffff);
9525 /* High-order 16 bits of constant for use in signed operand. */
9527 output_operand_lossage ("invalid %%v value");
9529 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9530 (INT_LOWPART (x) >> 16) & 0xffff);
9534 /* Print `u' if this has an auto-increment or auto-decrement. */
9535 if (GET_CODE (x) == MEM
9536 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9537 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9542 /* Print the trap code for this operand. */
9543 switch (GET_CODE (x))
9546 fputs ("eq", file); /* 4 */
9549 fputs ("ne", file); /* 24 */
9552 fputs ("lt", file); /* 16 */
9555 fputs ("le", file); /* 20 */
9558 fputs ("gt", file); /* 8 */
9561 fputs ("ge", file); /* 12 */
9564 fputs ("llt", file); /* 2 */
9567 fputs ("lle", file); /* 6 */
9570 fputs ("lgt", file); /* 1 */
9573 fputs ("lge", file); /* 5 */
9581 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9584 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9585 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9587 print_operand (file, x, 0);
9591 /* MB value for a PowerPC64 rldic operand. */
9592 val = (GET_CODE (x) == CONST_INT
9593 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9598 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9599 if ((val <<= 1) < 0)
9602 #if HOST_BITS_PER_WIDE_INT == 32
9603 if (GET_CODE (x) == CONST_INT && i >= 0)
9604 i += 32; /* zero-extend high-part was all 0's */
9605 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9607 val = CONST_DOUBLE_LOW (x);
9614 for ( ; i < 64; i++)
9615 if ((val <<= 1) < 0)
9620 fprintf (file, "%d", i + 1);
9624 if (GET_CODE (x) == MEM
9625 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9630 /* Like 'L', for third word of TImode */
9631 if (GET_CODE (x) == REG)
9632 fputs (reg_names[REGNO (x) + 2], file);
9633 else if (GET_CODE (x) == MEM)
9635 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9636 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9637 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9639 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9640 if (small_data_operand (x, GET_MODE (x)))
9641 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9642 reg_names[SMALL_DATA_REG]);
9647 /* X is a SYMBOL_REF. Write out the name preceded by a
9648 period and without any trailing data in brackets. Used for function
9649 names. If we are configured for System V (or the embedded ABI) on
9650 the PowerPC, do not emit the period, since those systems do not use
9651 TOCs and the like. */
9652 if (GET_CODE (x) != SYMBOL_REF)
9655 /* Mark the decl as referenced so that cgraph will output the
9657 if (SYMBOL_REF_DECL (x))
9658 mark_decl_referenced (SYMBOL_REF_DECL (x));
9660 /* For macho, check to see if we need a stub. */
9663 const char *name = XSTR (x, 0);
9665 if (MACHOPIC_INDIRECT
9666 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9667 name = machopic_indirection_name (x, /*stub_p=*/true);
9669 assemble_name (file, name);
9671 else if (!DOT_SYMBOLS)
9672 assemble_name (file, XSTR (x, 0));
9674 rs6000_output_function_entry (file, XSTR (x, 0));
9678 /* Like 'L', for last word of TImode. */
9679 if (GET_CODE (x) == REG)
9680 fputs (reg_names[REGNO (x) + 3], file);
9681 else if (GET_CODE (x) == MEM)
9683 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9684 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9685 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9687 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9688 if (small_data_operand (x, GET_MODE (x)))
9689 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9690 reg_names[SMALL_DATA_REG]);
9694 /* Print AltiVec or SPE memory operand. */
9699 if (GET_CODE (x) != MEM)
9707 if (GET_CODE (tmp) == REG)
9709 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9712 /* Handle [reg+UIMM]. */
9713 else if (GET_CODE (tmp) == PLUS &&
9714 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9718 if (GET_CODE (XEXP (tmp, 0)) != REG)
9721 x = INTVAL (XEXP (tmp, 1));
9722 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9726 /* Fall through. Must be [reg+reg]. */
9729 && GET_CODE (tmp) == AND
9730 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9731 && INTVAL (XEXP (tmp, 1)) == -16)
9732 tmp = XEXP (tmp, 0);
9733 if (GET_CODE (tmp) == REG)
9734 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9735 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9737 if (REGNO (XEXP (tmp, 0)) == 0)
9738 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9739 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9741 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9742 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9750 if (GET_CODE (x) == REG)
9751 fprintf (file, "%s", reg_names[REGNO (x)]);
9752 else if (GET_CODE (x) == MEM)
9754 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9755 know the width from the mode. */
9756 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9757 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9758 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9759 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9760 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9761 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9763 output_address (XEXP (x, 0));
9766 output_addr_const (file, x);
9770 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9774 output_operand_lossage ("invalid %%xn code");
9778 /* Print the address of an operand. */
9781 print_operand_address (FILE *file, rtx x)
9783 if (GET_CODE (x) == REG)
9784 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9785 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9786 || GET_CODE (x) == LABEL_REF)
9788 output_addr_const (file, x);
9789 if (small_data_operand (x, GET_MODE (x)))
9790 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9791 reg_names[SMALL_DATA_REG]);
9792 else if (TARGET_TOC)
9795 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9797 if (REGNO (XEXP (x, 0)) == 0)
9798 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9799 reg_names[ REGNO (XEXP (x, 0)) ]);
9801 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9802 reg_names[ REGNO (XEXP (x, 1)) ]);
9804 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9805 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9806 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9808 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9809 && CONSTANT_P (XEXP (x, 1)))
9811 output_addr_const (file, XEXP (x, 1));
9812 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9816 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9817 && CONSTANT_P (XEXP (x, 1)))
9819 fprintf (file, "lo16(");
9820 output_addr_const (file, XEXP (x, 1));
9821 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9824 else if (legitimate_constant_pool_address_p (x))
9826 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9828 rtx contains_minus = XEXP (x, 1);
9832 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9833 turn it into (sym) for output_addr_const. */
9834 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9835 contains_minus = XEXP (contains_minus, 0);
9837 minus = XEXP (contains_minus, 0);
9838 symref = XEXP (minus, 0);
9839 XEXP (contains_minus, 0) = symref;
9844 name = XSTR (symref, 0);
9845 newname = alloca (strlen (name) + sizeof ("@toc"));
9846 strcpy (newname, name);
9847 strcat (newname, "@toc");
9848 XSTR (symref, 0) = newname;
9850 output_addr_const (file, XEXP (x, 1));
9852 XSTR (symref, 0) = name;
9853 XEXP (contains_minus, 0) = minus;
9856 output_addr_const (file, XEXP (x, 1));
9858 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9864 /* Target hook for assembling integer objects. The PowerPC version has
9865 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9866 is defined. It also needs to handle DI-mode objects on 64-bit
9870 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9872 #ifdef RELOCATABLE_NEEDS_FIXUP
9873 /* Special handling for SI values. */
9874 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
9876 extern int in_toc_section (void);
9877 static int recurse = 0;
9879 /* For -mrelocatable, we mark all addresses that need to be fixed up
9880 in the .fixup section. */
9881 if (TARGET_RELOCATABLE
9882 && !in_toc_section ()
9883 && !in_text_section ()
9884 && !in_unlikely_text_section ()
9886 && GET_CODE (x) != CONST_INT
9887 && GET_CODE (x) != CONST_DOUBLE
9893 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9895 ASM_OUTPUT_LABEL (asm_out_file, buf);
9896 fprintf (asm_out_file, "\t.long\t(");
9897 output_addr_const (asm_out_file, x);
9898 fprintf (asm_out_file, ")@fixup\n");
9899 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9900 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9901 fprintf (asm_out_file, "\t.long\t");
9902 assemble_name (asm_out_file, buf);
9903 fprintf (asm_out_file, "\n\t.previous\n");
9907 /* Remove initial .'s to turn a -mcall-aixdesc function
9908 address into the address of the descriptor, not the function
9910 else if (GET_CODE (x) == SYMBOL_REF
9911 && XSTR (x, 0)[0] == '.'
9912 && DEFAULT_ABI == ABI_AIX)
9914 const char *name = XSTR (x, 0);
9915 while (*name == '.')
9918 fprintf (asm_out_file, "\t.long\t%s\n", name);
9922 #endif /* RELOCATABLE_NEEDS_FIXUP */
9923 return default_assemble_integer (x, size, aligned_p);
9926 #ifdef HAVE_GAS_HIDDEN
9927 /* Emit an assembler directive to set symbol visibility for DECL to
9931 rs6000_assemble_visibility (tree decl, int vis)
9933 /* Functions need to have their entry point symbol visibility set as
9934 well as their descriptor symbol visibility. */
9935 if (DEFAULT_ABI == ABI_AIX
9937 && TREE_CODE (decl) == FUNCTION_DECL)
9939 static const char * const visibility_types[] = {
9940 NULL, "internal", "hidden", "protected"
9943 const char *name, *type;
9945 name = ((* targetm.strip_name_encoding)
9946 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9947 type = visibility_types[vis];
9949 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9950 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9953 default_assemble_visibility (decl, vis);
9958 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
9960 /* Reversal of FP compares takes care -- an ordered compare
9961 becomes an unordered compare and vice versa. */
9962 if (mode == CCFPmode
9963 && (!flag_finite_math_only
9964 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
9965 || code == UNEQ || code == LTGT))
9966 return reverse_condition_maybe_unordered (code);
9968 return reverse_condition (code);
9971 /* Generate a compare for CODE. Return a brand-new rtx that
9972 represents the result of the compare. */
9975 rs6000_generate_compare (enum rtx_code code)
9977 enum machine_mode comp_mode;
9980 if (rs6000_compare_fp_p)
9981 comp_mode = CCFPmode;
9982 else if (code == GTU || code == LTU
9983 || code == GEU || code == LEU)
9984 comp_mode = CCUNSmode;
9985 else if ((code == EQ || code == NE)
9986 && GET_CODE (rs6000_compare_op0) == SUBREG
9987 && GET_CODE (rs6000_compare_op1) == SUBREG
9988 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
9989 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
9990 /* These are unsigned values, perhaps there will be a later
9991 ordering compare that can be shared with this one.
9992 Unfortunately we cannot detect the signedness of the operands
9994 comp_mode = CCUNSmode;
9998 /* First, the compare. */
9999 compare_result = gen_reg_rtx (comp_mode);
10001 /* SPE FP compare instructions on the GPRs. Yuck! */
10002 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10003 && rs6000_compare_fp_p)
10005 rtx cmp, or_result, compare_result2;
10006 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10008 if (op_mode == VOIDmode)
10009 op_mode = GET_MODE (rs6000_compare_op1);
10011 /* Note: The E500 comparison instructions set the GT bit (x +
10012 1), on success. This explains the mess. */
10016 case EQ: case UNEQ: case NE: case LTGT:
10017 if (op_mode == SFmode)
10018 cmp = flag_unsafe_math_optimizations
10019 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10020 rs6000_compare_op1)
10021 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10022 rs6000_compare_op1);
10023 else if (op_mode == DFmode)
10024 cmp = flag_unsafe_math_optimizations
10025 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10026 rs6000_compare_op1)
10027 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10028 rs6000_compare_op1);
10031 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10032 if (op_mode == SFmode)
10033 cmp = flag_unsafe_math_optimizations
10034 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10035 rs6000_compare_op1)
10036 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10037 rs6000_compare_op1);
10038 else if (op_mode == DFmode)
10039 cmp = flag_unsafe_math_optimizations
10040 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10041 rs6000_compare_op1)
10042 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10043 rs6000_compare_op1);
10046 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10047 if (op_mode == SFmode)
10048 cmp = flag_unsafe_math_optimizations
10049 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10050 rs6000_compare_op1)
10051 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10052 rs6000_compare_op1);
10053 else if (op_mode == DFmode)
10054 cmp = flag_unsafe_math_optimizations
10055 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10056 rs6000_compare_op1)
10057 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10058 rs6000_compare_op1);
10065 /* Synthesize LE and GE from LT/GT || EQ. */
10066 if (code == LE || code == GE || code == LEU || code == GEU)
10072 case LE: code = LT; break;
10073 case GE: code = GT; break;
10074 case LEU: code = LT; break;
10075 case GEU: code = GT; break;
10079 compare_result2 = gen_reg_rtx (CCFPmode);
10082 if (op_mode == SFmode)
10083 cmp = flag_unsafe_math_optimizations
10084 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10085 rs6000_compare_op1)
10086 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10087 rs6000_compare_op1);
10088 else if (op_mode == DFmode)
10089 cmp = flag_unsafe_math_optimizations
10090 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10091 rs6000_compare_op1)
10092 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10093 rs6000_compare_op1);
10097 /* OR them together. */
10098 or_result = gen_reg_rtx (CCFPmode);
10099 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10101 compare_result = or_result;
10106 if (code == NE || code == LTGT)
10116 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10117 CLOBBERs to match cmptf_internal2 pattern. */
10118 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10119 && GET_MODE (rs6000_compare_op0) == TFmode
10120 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10121 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10122 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10124 gen_rtx_SET (VOIDmode,
10126 gen_rtx_COMPARE (comp_mode,
10127 rs6000_compare_op0,
10128 rs6000_compare_op1)),
10129 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10130 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10131 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10132 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10133 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10134 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10135 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10136 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10138 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10139 gen_rtx_COMPARE (comp_mode,
10140 rs6000_compare_op0,
10141 rs6000_compare_op1)));
10144 /* Some kinds of FP comparisons need an OR operation;
10145 under flag_finite_math_only we don't bother. */
10146 if (rs6000_compare_fp_p
10147 && !flag_finite_math_only
10148 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10149 && (code == LE || code == GE
10150 || code == UNEQ || code == LTGT
10151 || code == UNGT || code == UNLT))
10153 enum rtx_code or1, or2;
10154 rtx or1_rtx, or2_rtx, compare2_rtx;
10155 rtx or_result = gen_reg_rtx (CCEQmode);
10159 case LE: or1 = LT; or2 = EQ; break;
10160 case GE: or1 = GT; or2 = EQ; break;
10161 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10162 case LTGT: or1 = LT; or2 = GT; break;
10163 case UNGT: or1 = UNORDERED; or2 = GT; break;
10164 case UNLT: or1 = UNORDERED; or2 = LT; break;
10167 validate_condition_mode (or1, comp_mode);
10168 validate_condition_mode (or2, comp_mode);
10169 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10170 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10171 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10172 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10174 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10176 compare_result = or_result;
10180 validate_condition_mode (code, GET_MODE (compare_result));
10182 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10186 /* Emit the RTL for an sCOND pattern. */
10189 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10192 enum machine_mode op_mode;
10193 enum rtx_code cond_code;
10195 condition_rtx = rs6000_generate_compare (code);
10196 cond_code = GET_CODE (condition_rtx);
10198 if (TARGET_E500 && rs6000_compare_fp_p
10199 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10203 PUT_MODE (condition_rtx, SImode);
10204 t = XEXP (condition_rtx, 0);
10206 if (cond_code != NE && cond_code != EQ)
10209 if (cond_code == NE)
10210 emit_insn (gen_e500_flip_gt_bit (t, t));
10212 emit_insn (gen_move_from_CR_gt_bit (result, t));
10216 if (cond_code == NE
10217 || cond_code == GE || cond_code == LE
10218 || cond_code == GEU || cond_code == LEU
10219 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10221 rtx not_result = gen_reg_rtx (CCEQmode);
10222 rtx not_op, rev_cond_rtx;
10223 enum machine_mode cc_mode;
10225 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10227 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10228 SImode, XEXP (condition_rtx, 0), const0_rtx);
10229 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10230 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10231 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10234 op_mode = GET_MODE (rs6000_compare_op0);
10235 if (op_mode == VOIDmode)
10236 op_mode = GET_MODE (rs6000_compare_op1);
10238 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10240 PUT_MODE (condition_rtx, DImode);
10241 convert_move (result, condition_rtx, 0);
10245 PUT_MODE (condition_rtx, SImode);
10246 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10250 /* Emit a branch of kind CODE to location LOC. */
10253 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10255 rtx condition_rtx, loc_ref;
10257 condition_rtx = rs6000_generate_compare (code);
10258 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10259 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10260 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10261 loc_ref, pc_rtx)));
10264 /* Return the string to output a conditional branch to LABEL, which is
10265 the operand number of the label, or -1 if the branch is really a
10266 conditional return.
10268 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10269 condition code register and its mode specifies what kind of
10270 comparison we made.
10272 REVERSED is nonzero if we should reverse the sense of the comparison.
10274 INSN is the insn. */
10277 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10279 static char string[64];
10280 enum rtx_code code = GET_CODE (op);
10281 rtx cc_reg = XEXP (op, 0);
10282 enum machine_mode mode = GET_MODE (cc_reg);
10283 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10284 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10285 int really_reversed = reversed ^ need_longbranch;
10291 validate_condition_mode (code, mode);
10293 /* Work out which way this really branches. We could use
10294 reverse_condition_maybe_unordered here always but this
10295 makes the resulting assembler clearer. */
10296 if (really_reversed)
10298 /* Reversal of FP compares takes care -- an ordered compare
10299 becomes an unordered compare and vice versa. */
10300 if (mode == CCFPmode)
10301 code = reverse_condition_maybe_unordered (code);
10303 code = reverse_condition (code);
10306 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10308 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10311 /* Opposite of GT. */
10313 else if (code == NE)
10321 /* Not all of these are actually distinct opcodes, but
10322 we distinguish them for clarity of the resulting assembler. */
10323 case NE: case LTGT:
10324 ccode = "ne"; break;
10325 case EQ: case UNEQ:
10326 ccode = "eq"; break;
10328 ccode = "ge"; break;
10329 case GT: case GTU: case UNGT:
10330 ccode = "gt"; break;
10332 ccode = "le"; break;
10333 case LT: case LTU: case UNLT:
10334 ccode = "lt"; break;
10335 case UNORDERED: ccode = "un"; break;
10336 case ORDERED: ccode = "nu"; break;
10337 case UNGE: ccode = "nl"; break;
10338 case UNLE: ccode = "ng"; break;
10343 /* Maybe we have a guess as to how likely the branch is.
10344 The old mnemonics don't have a way to specify this information. */
10346 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10347 if (note != NULL_RTX)
10349 /* PROB is the difference from 50%. */
10350 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10352 /* Only hint for highly probable/improbable branches on newer
10353 cpus as static prediction overrides processor dynamic
10354 prediction. For older cpus we may as well always hint, but
10355 assume not taken for branches that are very close to 50% as a
10356 mispredicted taken branch is more expensive than a
10357 mispredicted not-taken branch. */
10358 if (rs6000_always_hint
10359 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10361 if (abs (prob) > REG_BR_PROB_BASE / 20
10362 && ((prob > 0) ^ need_longbranch))
10370 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10372 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10374 /* We need to escape any '%' characters in the reg_names string.
10375 Assume they'd only be the first character.... */
10376 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10378 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10382 /* If the branch distance was too far, we may have to use an
10383 unconditional branch to go the distance. */
10384 if (need_longbranch)
10385 s += sprintf (s, ",$+8\n\tb %s", label);
10387 s += sprintf (s, ",%s", label);
10393 /* Return the string to flip the GT bit on a CR. */
10395 output_e500_flip_gt_bit (rtx dst, rtx src)
10397 static char string[64];
10400 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10401 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10405 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10406 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
10408 sprintf (string, "crnot %d,%d", a, b);
10412 /* Return insn index for the vector compare instruction for given CODE,
10413 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10417 get_vec_cmp_insn (enum rtx_code code,
10418 enum machine_mode dest_mode,
10419 enum machine_mode op_mode)
10421 if (!TARGET_ALTIVEC)
10422 return INSN_NOT_AVAILABLE;
10427 if (dest_mode == V16QImode && op_mode == V16QImode)
10428 return UNSPEC_VCMPEQUB;
10429 if (dest_mode == V8HImode && op_mode == V8HImode)
10430 return UNSPEC_VCMPEQUH;
10431 if (dest_mode == V4SImode && op_mode == V4SImode)
10432 return UNSPEC_VCMPEQUW;
10433 if (dest_mode == V4SImode && op_mode == V4SFmode)
10434 return UNSPEC_VCMPEQFP;
10437 if (dest_mode == V4SImode && op_mode == V4SFmode)
10438 return UNSPEC_VCMPGEFP;
10440 if (dest_mode == V16QImode && op_mode == V16QImode)
10441 return UNSPEC_VCMPGTSB;
10442 if (dest_mode == V8HImode && op_mode == V8HImode)
10443 return UNSPEC_VCMPGTSH;
10444 if (dest_mode == V4SImode && op_mode == V4SImode)
10445 return UNSPEC_VCMPGTSW;
10446 if (dest_mode == V4SImode && op_mode == V4SFmode)
10447 return UNSPEC_VCMPGTFP;
10450 if (dest_mode == V16QImode && op_mode == V16QImode)
10451 return UNSPEC_VCMPGTUB;
10452 if (dest_mode == V8HImode && op_mode == V8HImode)
10453 return UNSPEC_VCMPGTUH;
10454 if (dest_mode == V4SImode && op_mode == V4SImode)
10455 return UNSPEC_VCMPGTUW;
10460 return INSN_NOT_AVAILABLE;
10463 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10464 DMODE is expected destination mode. This is a recursive function. */
10467 rs6000_emit_vector_compare (enum rtx_code rcode,
10469 enum machine_mode dmode)
10473 enum machine_mode dest_mode;
10474 enum machine_mode op_mode = GET_MODE (op1);
10476 #ifdef ENABLE_CHECKING
10477 if (!TARGET_ALTIVEC)
10480 if (GET_MODE (op0) != GET_MODE (op1))
10484 /* Floating point vector compare instructions uses destination V4SImode.
10485 Move destination to appropriate mode later. */
10486 if (dmode == V4SFmode)
10487 dest_mode = V4SImode;
10491 mask = gen_reg_rtx (dest_mode);
10492 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10494 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10496 bool swap_operands = false;
10497 bool try_again = false;
10502 swap_operands = true;
10507 swap_operands = true;
10511 /* Treat A != B as ~(A==B). */
10513 enum insn_code nor_code;
10514 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10517 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10518 if (nor_code == CODE_FOR_nothing)
10520 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10522 if (dmode != dest_mode)
10524 rtx temp = gen_reg_rtx (dest_mode);
10525 convert_move (temp, mask, 0);
10535 /* Try GT/GTU/LT/LTU OR EQ */
10538 enum insn_code ior_code;
10539 enum rtx_code new_code;
10543 else if (rcode == GEU)
10545 else if (rcode == LE)
10547 else if (rcode == LEU)
10552 c_rtx = rs6000_emit_vector_compare (new_code,
10553 op0, op1, dest_mode);
10554 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10557 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10558 if (ior_code == CODE_FOR_nothing)
10560 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10561 if (dmode != dest_mode)
10563 rtx temp = gen_reg_rtx (dest_mode);
10564 convert_move (temp, mask, 0);
10576 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10577 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10578 /* You only get two chances. */
10591 emit_insn (gen_rtx_fmt_ee (SET,
10594 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10595 gen_rtvec (2, op0, op1),
10597 if (dmode != dest_mode)
10599 rtx temp = gen_reg_rtx (dest_mode);
10600 convert_move (temp, mask, 0);
10606 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10607 valid insn doesn exist for given mode. */
10610 get_vsel_insn (enum machine_mode mode)
10615 return UNSPEC_VSEL4SI;
10618 return UNSPEC_VSEL4SF;
10621 return UNSPEC_VSEL8HI;
10624 return UNSPEC_VSEL16QI;
10627 return INSN_NOT_AVAILABLE;
10630 return INSN_NOT_AVAILABLE;
10633 /* Emit vector select insn where DEST is destination using
10634 operands OP1, OP2 and MASK. */
10637 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10640 enum machine_mode dest_mode = GET_MODE (dest);
10641 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10643 temp = gen_reg_rtx (dest_mode);
10645 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10646 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10647 gen_rtvec (3, op1, op2, mask),
10650 emit_move_insn (dest, temp);
10654 /* Emit vector conditional expression.
10655 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10656 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10659 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10660 rtx cond, rtx cc_op0, rtx cc_op1)
10662 enum machine_mode dest_mode = GET_MODE (dest);
10663 enum rtx_code rcode = GET_CODE (cond);
10666 if (!TARGET_ALTIVEC)
10669 /* Get the vector mask for the given relational operations. */
10670 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10672 rs6000_emit_vector_select (dest, op1, op2, mask);
10677 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10678 operands of the last comparison is nonzero/true, FALSE_COND if it
10679 is zero/false. Return 0 if the hardware has no such operation. */
10682 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10684 enum rtx_code code = GET_CODE (op);
10685 rtx op0 = rs6000_compare_op0;
10686 rtx op1 = rs6000_compare_op1;
10687 REAL_VALUE_TYPE c1;
10688 enum machine_mode compare_mode = GET_MODE (op0);
10689 enum machine_mode result_mode = GET_MODE (dest);
10691 bool is_against_zero;
10693 /* These modes should always match. */
10694 if (GET_MODE (op1) != compare_mode
10695 /* In the isel case however, we can use a compare immediate, so
10696 op1 may be a small constant. */
10697 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10699 if (GET_MODE (true_cond) != result_mode)
10701 if (GET_MODE (false_cond) != result_mode)
10704 /* First, work out if the hardware can do this at all, or
10705 if it's too slow.... */
10706 if (! rs6000_compare_fp_p)
10709 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10712 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10713 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10716 is_against_zero = op1 == CONST0_RTX (compare_mode);
10718 /* A floating-point subtract might overflow, underflow, or produce
10719 an inexact result, thus changing the floating-point flags, so it
10720 can't be generated if we care about that. It's safe if one side
10721 of the construct is zero, since then no subtract will be
10723 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10724 && flag_trapping_math && ! is_against_zero)
10727 /* Eliminate half of the comparisons by switching operands, this
10728 makes the remaining code simpler. */
10729 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10730 || code == LTGT || code == LT || code == UNLE)
10732 code = reverse_condition_maybe_unordered (code);
10734 true_cond = false_cond;
10738 /* UNEQ and LTGT take four instructions for a comparison with zero,
10739 it'll probably be faster to use a branch here too. */
10740 if (code == UNEQ && HONOR_NANS (compare_mode))
10743 if (GET_CODE (op1) == CONST_DOUBLE)
10744 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10746 /* We're going to try to implement comparisons by performing
10747 a subtract, then comparing against zero. Unfortunately,
10748 Inf - Inf is NaN which is not zero, and so if we don't
10749 know that the operand is finite and the comparison
10750 would treat EQ different to UNORDERED, we can't do it. */
10751 if (HONOR_INFINITIES (compare_mode)
10752 && code != GT && code != UNGE
10753 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10754 /* Constructs of the form (a OP b ? a : b) are safe. */
10755 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10756 || (! rtx_equal_p (op0, true_cond)
10757 && ! rtx_equal_p (op1, true_cond))))
10760 /* At this point we know we can use fsel. */
10762 /* Reduce the comparison to a comparison against zero. */
10763 if (! is_against_zero)
10765 temp = gen_reg_rtx (compare_mode);
10766 emit_insn (gen_rtx_SET (VOIDmode, temp,
10767 gen_rtx_MINUS (compare_mode, op0, op1)));
10769 op1 = CONST0_RTX (compare_mode);
10772 /* If we don't care about NaNs we can reduce some of the comparisons
10773 down to faster ones. */
10774 if (! HONOR_NANS (compare_mode))
10780 true_cond = false_cond;
10793 /* Now, reduce everything down to a GE. */
10800 temp = gen_reg_rtx (compare_mode);
10801 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10806 temp = gen_reg_rtx (compare_mode);
10807 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10812 temp = gen_reg_rtx (compare_mode);
10813 emit_insn (gen_rtx_SET (VOIDmode, temp,
10814 gen_rtx_NEG (compare_mode,
10815 gen_rtx_ABS (compare_mode, op0))));
10820 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10821 temp = gen_reg_rtx (result_mode);
10822 emit_insn (gen_rtx_SET (VOIDmode, temp,
10823 gen_rtx_IF_THEN_ELSE (result_mode,
10824 gen_rtx_GE (VOIDmode,
10826 true_cond, false_cond)));
10827 false_cond = true_cond;
10830 temp = gen_reg_rtx (compare_mode);
10831 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10836 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10837 temp = gen_reg_rtx (result_mode);
10838 emit_insn (gen_rtx_SET (VOIDmode, temp,
10839 gen_rtx_IF_THEN_ELSE (result_mode,
10840 gen_rtx_GE (VOIDmode,
10842 true_cond, false_cond)));
10843 true_cond = false_cond;
10846 temp = gen_reg_rtx (compare_mode);
10847 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10855 emit_insn (gen_rtx_SET (VOIDmode, dest,
10856 gen_rtx_IF_THEN_ELSE (result_mode,
10857 gen_rtx_GE (VOIDmode,
10859 true_cond, false_cond)));
10863 /* Same as above, but for ints (isel). */
10866 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10868 rtx condition_rtx, cr;
10870 /* All isel implementations thus far are 32-bits. */
10871 if (GET_MODE (rs6000_compare_op0) != SImode)
10874 /* We still have to do the compare, because isel doesn't do a
10875 compare, it just looks at the CRx bits set by a previous compare
10877 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10878 cr = XEXP (condition_rtx, 0);
10880 if (GET_MODE (cr) == CCmode)
10881 emit_insn (gen_isel_signed (dest, condition_rtx,
10882 true_cond, false_cond, cr));
10884 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10885 true_cond, false_cond, cr));
10891 output_isel (rtx *operands)
10893 enum rtx_code code;
10895 code = GET_CODE (operands[1]);
10896 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10898 PUT_CODE (operands[1], reverse_condition (code));
10899 return "isel %0,%3,%2,%j1";
10902 return "isel %0,%2,%3,%j1";
10906 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10908 enum machine_mode mode = GET_MODE (op0);
10912 if (code == SMAX || code == SMIN)
10917 if (code == SMAX || code == UMAX)
10918 target = emit_conditional_move (dest, c, op0, op1, mode,
10919 op0, op1, mode, 0);
10921 target = emit_conditional_move (dest, c, op0, op1, mode,
10922 op1, op0, mode, 0);
10923 if (target == NULL_RTX)
10925 if (target != dest)
10926 emit_move_insn (dest, target);
10929 /* Emit instructions to move SRC to DST. Called by splitters for
10930 multi-register moves. It will emit at most one instruction for
10931 each register that is accessed; that is, it won't emit li/lis pairs
10932 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10936 rs6000_split_multireg_move (rtx dst, rtx src)
10938 /* The register number of the first register being moved. */
10940 /* The mode that is to be moved. */
10941 enum machine_mode mode;
10942 /* The mode that the move is being done in, and its size. */
10943 enum machine_mode reg_mode;
10945 /* The number of registers that will be moved. */
10948 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10949 mode = GET_MODE (dst);
10950 nregs = HARD_REGNO_NREGS (reg, mode);
10951 if (FP_REGNO_P (reg))
10953 else if (ALTIVEC_REGNO_P (reg))
10954 reg_mode = V16QImode;
10956 reg_mode = word_mode;
10957 reg_mode_size = GET_MODE_SIZE (reg_mode);
10959 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
10962 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
10964 /* Move register range backwards, if we might have destructive
10967 for (i = nregs - 1; i >= 0; i--)
10968 emit_insn (gen_rtx_SET (VOIDmode,
10969 simplify_gen_subreg (reg_mode, dst, mode,
10970 i * reg_mode_size),
10971 simplify_gen_subreg (reg_mode, src, mode,
10972 i * reg_mode_size)));
10978 bool used_update = false;
10980 if (MEM_P (src) && INT_REGNO_P (reg))
10984 if (GET_CODE (XEXP (src, 0)) == PRE_INC
10985 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
10988 breg = XEXP (XEXP (src, 0), 0);
10989 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
10990 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
10991 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
10992 emit_insn (TARGET_32BIT
10993 ? gen_addsi3 (breg, breg, delta_rtx)
10994 : gen_adddi3 (breg, breg, delta_rtx));
10995 src = gen_rtx_MEM (mode, breg);
10997 else if (! offsettable_memref_p (src))
10999 rtx newsrc, basereg;
11000 basereg = gen_rtx_REG (Pmode, reg);
11001 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11002 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11003 MEM_COPY_ATTRIBUTES (newsrc, src);
11007 breg = XEXP (src, 0);
11008 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11009 breg = XEXP (breg, 0);
11011 /* If the base register we are using to address memory is
11012 also a destination reg, then change that register last. */
11014 && REGNO (breg) >= REGNO (dst)
11015 && REGNO (breg) < REGNO (dst) + nregs)
11016 j = REGNO (breg) - REGNO (dst);
11019 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11023 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11024 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11027 breg = XEXP (XEXP (dst, 0), 0);
11028 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11029 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11030 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11032 /* We have to update the breg before doing the store.
11033 Use store with update, if available. */
11037 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11038 emit_insn (TARGET_32BIT
11039 ? (TARGET_POWERPC64
11040 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11041 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11042 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11043 used_update = true;
11046 emit_insn (TARGET_32BIT
11047 ? gen_addsi3 (breg, breg, delta_rtx)
11048 : gen_adddi3 (breg, breg, delta_rtx));
11049 dst = gen_rtx_MEM (mode, breg);
11051 else if (! offsettable_memref_p (dst))
11055 for (i = 0; i < nregs; i++)
11057 /* Calculate index to next subword. */
11062 /* If compiler already emitted move of first word by
11063 store with update, no need to do anything. */
11064 if (j == 0 && used_update)
11067 emit_insn (gen_rtx_SET (VOIDmode,
11068 simplify_gen_subreg (reg_mode, dst, mode,
11069 j * reg_mode_size),
11070 simplify_gen_subreg (reg_mode, src, mode,
11071 j * reg_mode_size)));
11077 /* This page contains routines that are used to determine what the
11078 function prologue and epilogue code will do and write them out. */
11080 /* Return the first fixed-point register that is required to be
11081 saved. 32 if none. */
11084 first_reg_to_save (void)
11088 /* Find lowest numbered live register. */
11089 for (first_reg = 13; first_reg <= 31; first_reg++)
11090 if (regs_ever_live[first_reg]
11091 && (! call_used_regs[first_reg]
11092 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11093 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11094 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11095 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11100 && current_function_uses_pic_offset_table
11101 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11102 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11108 /* Similar, for FP regs. */
11111 first_fp_reg_to_save (void)
11115 /* Find lowest numbered live register. */
11116 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11117 if (regs_ever_live[first_reg])
11123 /* Similar, for AltiVec regs. */
11126 first_altivec_reg_to_save (void)
11130 /* Stack frame remains as is unless we are in AltiVec ABI. */
11131 if (! TARGET_ALTIVEC_ABI)
11132 return LAST_ALTIVEC_REGNO + 1;
11134 /* Find lowest numbered live register. */
11135 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11136 if (regs_ever_live[i])
11142 /* Return a 32-bit mask of the AltiVec registers we need to set in
11143 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11144 the 32-bit word is 0. */
11146 static unsigned int
11147 compute_vrsave_mask (void)
11149 unsigned int i, mask = 0;
11151 /* First, find out if we use _any_ altivec registers. */
11152 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11153 if (regs_ever_live[i])
11154 mask |= ALTIVEC_REG_BIT (i);
11159 /* Next, remove the argument registers from the set. These must
11160 be in the VRSAVE mask set by the caller, so we don't need to add
11161 them in again. More importantly, the mask we compute here is
11162 used to generate CLOBBERs in the set_vrsave insn, and we do not
11163 wish the argument registers to die. */
11164 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11165 mask &= ~ALTIVEC_REG_BIT (i);
11167 /* Similarly, remove the return value from the set. */
11170 diddle_return_value (is_altivec_return_reg, &yes);
11172 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11178 /* For a very restricted set of circumstances, we can cut down the
11179 size of prologues/epilogues by calling our own save/restore-the-world
11183 compute_save_world_info (rs6000_stack_t *info_ptr)
11185 info_ptr->world_save_p = 1;
11186 info_ptr->world_save_p
11187 = (WORLD_SAVE_P (info_ptr)
11188 && DEFAULT_ABI == ABI_DARWIN
11189 && ! (current_function_calls_setjmp && flag_exceptions)
11190 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11191 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11192 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11193 && info_ptr->cr_save_p);
11195 /* This will not work in conjunction with sibcalls. Make sure there
11196 are none. (This check is expensive, but seldom executed.) */
11197 if (WORLD_SAVE_P (info_ptr))
11200 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11201 if ( GET_CODE (insn) == CALL_INSN
11202 && SIBLING_CALL_P (insn))
11204 info_ptr->world_save_p = 0;
11209 if (WORLD_SAVE_P (info_ptr))
11211 /* Even if we're not touching VRsave, make sure there's room on the
11212 stack for it, if it looks like we're calling SAVE_WORLD, which
11213 will attempt to save it. */
11214 info_ptr->vrsave_size = 4;
11216 /* "Save" the VRsave register too if we're saving the world. */
11217 if (info_ptr->vrsave_mask == 0)
11218 info_ptr->vrsave_mask = compute_vrsave_mask ();
11220 /* Because the Darwin register save/restore routines only handle
11221 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11222 check and abort if there's something worng. */
11223 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
11224 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11232 is_altivec_return_reg (rtx reg, void *xyes)
11234 bool *yes = (bool *) xyes;
11235 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11240 /* Calculate the stack information for the current function. This is
11241 complicated by having two separate calling sequences, the AIX calling
11242 sequence and the V.4 calling sequence.
11244 AIX (and Darwin/Mac OS X) stack frames look like:
11246 SP----> +---------------------------------------+
11247 | back chain to caller | 0 0
11248 +---------------------------------------+
11249 | saved CR | 4 8 (8-11)
11250 +---------------------------------------+
11252 +---------------------------------------+
11253 | reserved for compilers | 12 24
11254 +---------------------------------------+
11255 | reserved for binders | 16 32
11256 +---------------------------------------+
11257 | saved TOC pointer | 20 40
11258 +---------------------------------------+
11259 | Parameter save area (P) | 24 48
11260 +---------------------------------------+
11261 | Alloca space (A) | 24+P etc.
11262 +---------------------------------------+
11263 | Local variable space (L) | 24+P+A
11264 +---------------------------------------+
11265 | Float/int conversion temporary (X) | 24+P+A+L
11266 +---------------------------------------+
11267 | Save area for AltiVec registers (W) | 24+P+A+L+X
11268 +---------------------------------------+
11269 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11270 +---------------------------------------+
11271 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11272 +---------------------------------------+
11273 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11274 +---------------------------------------+
11275 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11276 +---------------------------------------+
11277 old SP->| back chain to caller's caller |
11278 +---------------------------------------+
11280 The required alignment for AIX configurations is two words (i.e., 8
11284 V.4 stack frames look like:
11286 SP----> +---------------------------------------+
11287 | back chain to caller | 0
11288 +---------------------------------------+
11289 | caller's saved LR | 4
11290 +---------------------------------------+
11291 | Parameter save area (P) | 8
11292 +---------------------------------------+
11293 | Alloca space (A) | 8+P
11294 +---------------------------------------+
11295 | Varargs save area (V) | 8+P+A
11296 +---------------------------------------+
11297 | Local variable space (L) | 8+P+A+V
11298 +---------------------------------------+
11299 | Float/int conversion temporary (X) | 8+P+A+V+L
11300 +---------------------------------------+
11301 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11302 +---------------------------------------+
11303 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11304 +---------------------------------------+
11305 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11306 +---------------------------------------+
11307 | SPE: area for 64-bit GP registers |
11308 +---------------------------------------+
11309 | SPE alignment padding |
11310 +---------------------------------------+
11311 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11312 +---------------------------------------+
11313 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11314 +---------------------------------------+
11315 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11316 +---------------------------------------+
11317 old SP->| back chain to caller's caller |
11318 +---------------------------------------+
11320 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11321 given. (But note below and in sysv4.h that we require only 8 and
11322 may round up the size of our stack frame anyways. The historical
11323 reason is early versions of powerpc-linux which didn't properly
11324 align the stack at program startup. A happy side-effect is that
11325 -mno-eabi libraries can be used with -meabi programs.)
11327 The EABI configuration defaults to the V.4 layout. However,
11328 the stack alignment requirements may differ. If -mno-eabi is not
11329 given, the required stack alignment is 8 bytes; if -mno-eabi is
11330 given, the required alignment is 16 bytes. (But see V.4 comment
11333 #ifndef ABI_STACK_BOUNDARY
11334 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11337 static rs6000_stack_t *
11338 rs6000_stack_info (void)
11340 static rs6000_stack_t info, zero_info;
11341 rs6000_stack_t *info_ptr = &info;
11342 int reg_size = TARGET_32BIT ? 4 : 8;
11345 HOST_WIDE_INT non_fixed_size;
11347 /* Zero all fields portably. */
11352 /* Cache value so we don't rescan instruction chain over and over. */
11353 if (cfun->machine->insn_chain_scanned_p == 0)
11354 cfun->machine->insn_chain_scanned_p
11355 = spe_func_has_64bit_regs_p () + 1;
11356 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
11359 /* Select which calling sequence. */
11360 info_ptr->abi = DEFAULT_ABI;
11362 /* Calculate which registers need to be saved & save area size. */
11363 info_ptr->first_gp_reg_save = first_reg_to_save ();
11364 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11365 even if it currently looks like we won't. */
11366 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
11367 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11368 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
11369 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11370 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
11372 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
11374 /* For the SPE, we have an additional upper 32-bits on each GPR.
11375 Ideally we should save the entire 64-bits only when the upper
11376 half is used in SIMD instructions. Since we only record
11377 registers live (not the size they are used in), this proves
11378 difficult because we'd have to traverse the instruction chain at
11379 the right time, taking reload into account. This is a real pain,
11380 so we opt to save the GPRs in 64-bits always if but one register
11381 gets used in 64-bits. Otherwise, all the registers in the frame
11382 get saved in 32-bits.
11384 So... since when we save all GPRs (except the SP) in 64-bits, the
11385 traditional GP save area will be empty. */
11386 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11387 info_ptr->gp_size = 0;
11389 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11390 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11392 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11393 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11394 - info_ptr->first_altivec_reg_save);
11396 /* Does this function call anything? */
11397 info_ptr->calls_p = (! current_function_is_leaf
11398 || cfun->machine->ra_needs_full_frame);
11400 /* Determine if we need to save the link register. */
11401 if (rs6000_ra_ever_killed ()
11402 || (DEFAULT_ABI == ABI_AIX
11403 && current_function_profile
11404 && !TARGET_PROFILE_KERNEL)
11405 #ifdef TARGET_RELOCATABLE
11406 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11408 || (info_ptr->first_fp_reg_save != 64
11409 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
11410 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
11411 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
11412 || (DEFAULT_ABI == ABI_DARWIN
11414 && current_function_uses_pic_offset_table)
11415 || info_ptr->calls_p)
11417 info_ptr->lr_save_p = 1;
11418 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
11421 /* Determine if we need to save the condition code registers. */
11422 if (regs_ever_live[CR2_REGNO]
11423 || regs_ever_live[CR3_REGNO]
11424 || regs_ever_live[CR4_REGNO])
11426 info_ptr->cr_save_p = 1;
11427 if (DEFAULT_ABI == ABI_V4)
11428 info_ptr->cr_size = reg_size;
11431 /* If the current function calls __builtin_eh_return, then we need
11432 to allocate stack space for registers that will hold data for
11433 the exception handler. */
11434 if (current_function_calls_eh_return)
11437 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11440 /* SPE saves EH registers in 64-bits. */
11441 ehrd_size = i * (TARGET_SPE_ABI
11442 && info_ptr->spe_64bit_regs_used != 0
11443 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
11448 /* Determine various sizes. */
11449 info_ptr->reg_size = reg_size;
11450 info_ptr->fixed_size = RS6000_SAVE_AREA;
11451 info_ptr->varargs_size = RS6000_VARARGS_AREA;
11452 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
11453 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
11454 TARGET_ALTIVEC ? 16 : 8);
11456 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11457 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11459 info_ptr->spe_gp_size = 0;
11461 if (TARGET_ALTIVEC_ABI)
11462 info_ptr->vrsave_mask = compute_vrsave_mask ();
11464 info_ptr->vrsave_mask = 0;
11466 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11467 info_ptr->vrsave_size = 4;
11469 info_ptr->vrsave_size = 0;
11471 compute_save_world_info (info_ptr);
11473 /* Calculate the offsets. */
11474 switch (DEFAULT_ABI)
11482 info_ptr->fp_save_offset = - info_ptr->fp_size;
11483 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11485 if (TARGET_ALTIVEC_ABI)
11487 info_ptr->vrsave_save_offset
11488 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11490 /* Align stack so vector save area is on a quadword boundary. */
11491 if (info_ptr->altivec_size != 0)
11492 info_ptr->altivec_padding_size
11493 = 16 - (-info_ptr->vrsave_save_offset % 16);
11495 info_ptr->altivec_padding_size = 0;
11497 info_ptr->altivec_save_offset
11498 = info_ptr->vrsave_save_offset
11499 - info_ptr->altivec_padding_size
11500 - info_ptr->altivec_size;
11502 /* Adjust for AltiVec case. */
11503 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11506 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
11507 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11508 info_ptr->lr_save_offset = 2*reg_size;
11512 info_ptr->fp_save_offset = - info_ptr->fp_size;
11513 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11514 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
11516 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11518 /* Align stack so SPE GPR save area is aligned on a
11519 double-word boundary. */
11520 if (info_ptr->spe_gp_size != 0)
11521 info_ptr->spe_padding_size
11522 = 8 - (-info_ptr->cr_save_offset % 8);
11524 info_ptr->spe_padding_size = 0;
11526 info_ptr->spe_gp_save_offset
11527 = info_ptr->cr_save_offset
11528 - info_ptr->spe_padding_size
11529 - info_ptr->spe_gp_size;
11531 /* Adjust for SPE case. */
11532 info_ptr->toc_save_offset
11533 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11535 else if (TARGET_ALTIVEC_ABI)
11537 info_ptr->vrsave_save_offset
11538 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11540 /* Align stack so vector save area is on a quadword boundary. */
11541 if (info_ptr->altivec_size != 0)
11542 info_ptr->altivec_padding_size
11543 = 16 - (-info_ptr->vrsave_save_offset % 16);
11545 info_ptr->altivec_padding_size = 0;
11547 info_ptr->altivec_save_offset
11548 = info_ptr->vrsave_save_offset
11549 - info_ptr->altivec_padding_size
11550 - info_ptr->altivec_size;
11552 /* Adjust for AltiVec case. */
11553 info_ptr->toc_save_offset
11554 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11557 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
11558 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
11559 info_ptr->lr_save_offset = reg_size;
11563 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
11564 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11565 + info_ptr->gp_size
11566 + info_ptr->altivec_size
11567 + info_ptr->altivec_padding_size
11568 + info_ptr->spe_gp_size
11569 + info_ptr->spe_padding_size
11571 + info_ptr->cr_size
11572 + info_ptr->lr_size
11573 + info_ptr->vrsave_size
11574 + info_ptr->toc_size,
11577 non_fixed_size = (info_ptr->vars_size
11578 + info_ptr->parm_size
11579 + info_ptr->save_size
11580 + info_ptr->varargs_size);
11582 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11583 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11585 /* Determine if we need to allocate any stack frame:
11587 For AIX we need to push the stack if a frame pointer is needed
11588 (because the stack might be dynamically adjusted), if we are
11589 debugging, if we make calls, or if the sum of fp_save, gp_save,
11590 and local variables are more than the space needed to save all
11591 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11592 + 18*8 = 288 (GPR13 reserved).
11594 For V.4 we don't have the stack cushion that AIX uses, but assume
11595 that the debugger can handle stackless frames. */
11597 if (info_ptr->calls_p)
11598 info_ptr->push_p = 1;
11600 else if (DEFAULT_ABI == ABI_V4)
11601 info_ptr->push_p = non_fixed_size != 0;
11603 else if (frame_pointer_needed)
11604 info_ptr->push_p = 1;
11606 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11607 info_ptr->push_p = 1;
11610 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11612 /* Zero offsets if we're not saving those registers. */
11613 if (info_ptr->fp_size == 0)
11614 info_ptr->fp_save_offset = 0;
11616 if (info_ptr->gp_size == 0)
11617 info_ptr->gp_save_offset = 0;
11619 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11620 info_ptr->altivec_save_offset = 0;
11622 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11623 info_ptr->vrsave_save_offset = 0;
11625 if (! TARGET_SPE_ABI
11626 || info_ptr->spe_64bit_regs_used == 0
11627 || info_ptr->spe_gp_size == 0)
11628 info_ptr->spe_gp_save_offset = 0;
11630 if (! info_ptr->lr_save_p)
11631 info_ptr->lr_save_offset = 0;
11633 if (! info_ptr->cr_save_p)
11634 info_ptr->cr_save_offset = 0;
11636 if (! info_ptr->toc_save_p)
11637 info_ptr->toc_save_offset = 0;
11642 /* Return true if the current function uses any GPRs in 64-bit SIMD
11646 spe_func_has_64bit_regs_p (void)
11650 /* Functions that save and restore all the call-saved registers will
11651 need to save/restore the registers in 64-bits. */
11652 if (current_function_calls_eh_return
11653 || current_function_calls_setjmp
11654 || current_function_has_nonlocal_goto)
11657 insns = get_insns ();
11659 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11665 /* FIXME: This should be implemented with attributes...
11667 (set_attr "spe64" "true")....then,
11668 if (get_spe64(insn)) return true;
11670 It's the only reliable way to do the stuff below. */
11672 i = PATTERN (insn);
11673 if (GET_CODE (i) == SET)
11675 enum machine_mode mode = GET_MODE (SET_SRC (i));
11677 if (SPE_VECTOR_MODE (mode))
11679 if (TARGET_E500_DOUBLE && mode == DFmode)
11689 debug_stack_info (rs6000_stack_t *info)
11691 const char *abi_string;
11694 info = rs6000_stack_info ();
11696 fprintf (stderr, "\nStack information for function %s:\n",
11697 ((current_function_decl && DECL_NAME (current_function_decl))
11698 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11703 default: abi_string = "Unknown"; break;
11704 case ABI_NONE: abi_string = "NONE"; break;
11705 case ABI_AIX: abi_string = "AIX"; break;
11706 case ABI_DARWIN: abi_string = "Darwin"; break;
11707 case ABI_V4: abi_string = "V.4"; break;
11710 fprintf (stderr, "\tABI = %5s\n", abi_string);
11712 if (TARGET_ALTIVEC_ABI)
11713 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11715 if (TARGET_SPE_ABI)
11716 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11718 if (info->first_gp_reg_save != 32)
11719 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11721 if (info->first_fp_reg_save != 64)
11722 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
11724 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11725 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11726 info->first_altivec_reg_save);
11728 if (info->lr_save_p)
11729 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
11731 if (info->cr_save_p)
11732 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11734 if (info->toc_save_p)
11735 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11737 if (info->vrsave_mask)
11738 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11741 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11744 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11746 if (info->gp_save_offset)
11747 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11749 if (info->fp_save_offset)
11750 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11752 if (info->altivec_save_offset)
11753 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11754 info->altivec_save_offset);
11756 if (info->spe_gp_save_offset)
11757 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11758 info->spe_gp_save_offset);
11760 if (info->vrsave_save_offset)
11761 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11762 info->vrsave_save_offset);
11764 if (info->lr_save_offset)
11765 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11767 if (info->cr_save_offset)
11768 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11770 if (info->toc_save_offset)
11771 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11773 if (info->varargs_save_offset)
11774 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11776 if (info->total_size)
11777 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11780 if (info->varargs_size)
11781 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11783 if (info->vars_size)
11784 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11787 if (info->parm_size)
11788 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11790 if (info->fixed_size)
11791 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11794 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11796 if (info->spe_gp_size)
11797 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11800 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11802 if (info->altivec_size)
11803 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11805 if (info->vrsave_size)
11806 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11808 if (info->altivec_padding_size)
11809 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11810 info->altivec_padding_size);
11812 if (info->spe_padding_size)
11813 fprintf (stderr, "\tspe_padding_size = %5d\n",
11814 info->spe_padding_size);
11817 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
11820 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11822 if (info->toc_size)
11823 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11825 if (info->save_size)
11826 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11828 if (info->reg_size != 4)
11829 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11831 fprintf (stderr, "\n");
11835 rs6000_return_addr (int count, rtx frame)
11837 /* Currently we don't optimize very well between prolog and body
11838 code and for PIC code the code can be actually quite bad, so
11839 don't try to be too clever here. */
11840 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11842 cfun->machine->ra_needs_full_frame = 1;
11849 plus_constant (copy_to_reg
11850 (gen_rtx_MEM (Pmode,
11851 memory_address (Pmode, frame))),
11852 RETURN_ADDRESS_OFFSET)));
11855 cfun->machine->ra_need_lr = 1;
11856 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11859 /* Say whether a function is a candidate for sibcall handling or not.
11860 We do not allow indirect calls to be optimized into sibling calls.
11861 Also, we can't do it if there are any vector parameters; there's
11862 nowhere to put the VRsave code so it works; note that functions with
11863 vector parameters are required to have a prototype, so the argument
11864 type info must be available here. (The tail recursion case can work
11865 with vector parameters, but there's no way to distinguish here.) */
11867 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11872 if (TARGET_ALTIVEC_VRSAVE)
11874 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11875 type; type = TREE_CHAIN (type))
11877 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11881 if (DEFAULT_ABI == ABI_DARWIN
11882 || (*targetm.binds_local_p) (decl))
11884 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11886 if (!lookup_attribute ("longcall", attr_list)
11887 || lookup_attribute ("shortcall", attr_list))
11895 rs6000_ra_ever_killed (void)
11901 if (current_function_is_thunk)
11904 /* regs_ever_live has LR marked as used if any sibcalls are present,
11905 but this should not force saving and restoring in the
11906 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
11907 clobbers LR, so that is inappropriate. */
11909 /* Also, the prologue can generate a store into LR that
11910 doesn't really count, like this:
11913 bcl to set PIC register
11917 When we're called from the epilogue, we need to avoid counting
11918 this as a store. */
11920 push_topmost_sequence ();
11921 top = get_insns ();
11922 pop_topmost_sequence ();
11923 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11925 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11929 if (FIND_REG_INC_NOTE (insn, reg))
11931 else if (GET_CODE (insn) == CALL_INSN
11932 && !SIBLING_CALL_P (insn))
11934 else if (set_of (reg, insn) != NULL_RTX
11935 && !prologue_epilogue_contains (insn))
11942 /* Add a REG_MAYBE_DEAD note to the insn. */
11944 rs6000_maybe_dead (rtx insn)
11946 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11951 /* Emit instructions needed to load the TOC register.
11952 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11953 a constant pool; or for SVR4 -fpic. */
11956 rs6000_emit_load_toc_table (int fromprolog)
11959 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
11961 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
11963 rtx temp = (fromprolog
11964 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11965 : gen_reg_rtx (Pmode));
11966 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
11968 rs6000_maybe_dead (insn);
11969 insn = emit_move_insn (dest, temp);
11971 rs6000_maybe_dead (insn);
11973 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
11976 rtx tempLR = (fromprolog
11977 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
11978 : gen_reg_rtx (Pmode));
11979 rtx temp0 = (fromprolog
11980 ? gen_rtx_REG (Pmode, 0)
11981 : gen_reg_rtx (Pmode));
11987 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
11988 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11990 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
11991 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
11993 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
11995 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
11996 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12004 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12005 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
12006 emit_move_insn (dest, tempLR);
12007 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12009 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12011 rs6000_maybe_dead (insn);
12013 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12015 /* This is for AIX code running in non-PIC ELF32. */
12018 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12019 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12021 insn = emit_insn (gen_elf_high (dest, realsym));
12023 rs6000_maybe_dead (insn);
12024 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12026 rs6000_maybe_dead (insn);
12028 else if (DEFAULT_ABI == ABI_AIX)
12031 insn = emit_insn (gen_load_toc_aix_si (dest));
12033 insn = emit_insn (gen_load_toc_aix_di (dest));
12035 rs6000_maybe_dead (insn);
12041 /* Emit instructions to restore the link register after determining where
12042 its value has been stored. */
12045 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12047 rs6000_stack_t *info = rs6000_stack_info ();
12050 operands[0] = source;
12051 operands[1] = scratch;
12053 if (info->lr_save_p)
12055 rtx frame_rtx = stack_pointer_rtx;
12056 HOST_WIDE_INT sp_offset = 0;
12059 if (frame_pointer_needed
12060 || current_function_calls_alloca
12061 || info->total_size > 32767)
12063 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12064 frame_rtx = operands[1];
12066 else if (info->push_p)
12067 sp_offset = info->total_size;
12069 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12070 tmp = gen_rtx_MEM (Pmode, tmp);
12071 emit_move_insn (tmp, operands[0]);
12074 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12077 static GTY(()) int set = -1;
12080 get_TOC_alias_set (void)
12083 set = new_alias_set ();
12087 /* This returns nonzero if the current function uses the TOC. This is
12088 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12089 is generated by the ABI_V4 load_toc_* patterns. */
12096 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12099 rtx pat = PATTERN (insn);
12102 if (GET_CODE (pat) == PARALLEL)
12103 for (i = 0; i < XVECLEN (pat, 0); i++)
12105 rtx sub = XVECEXP (pat, 0, i);
12106 if (GET_CODE (sub) == USE)
12108 sub = XEXP (sub, 0);
12109 if (GET_CODE (sub) == UNSPEC
12110 && XINT (sub, 1) == UNSPEC_TOC)
12120 create_TOC_reference (rtx symbol)
12122 return gen_rtx_PLUS (Pmode,
12123 gen_rtx_REG (Pmode, TOC_REGISTER),
12124 gen_rtx_CONST (Pmode,
12125 gen_rtx_MINUS (Pmode, symbol,
12126 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12129 /* If _Unwind_* has been called from within the same module,
12130 toc register is not guaranteed to be saved to 40(1) on function
12131 entry. Save it there in that case. */
12134 rs6000_aix_emit_builtin_unwind_init (void)
12137 rtx stack_top = gen_reg_rtx (Pmode);
12138 rtx opcode_addr = gen_reg_rtx (Pmode);
12139 rtx opcode = gen_reg_rtx (SImode);
12140 rtx tocompare = gen_reg_rtx (SImode);
12141 rtx no_toc_save_needed = gen_label_rtx ();
12143 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12144 emit_move_insn (stack_top, mem);
12146 mem = gen_rtx_MEM (Pmode,
12147 gen_rtx_PLUS (Pmode, stack_top,
12148 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12149 emit_move_insn (opcode_addr, mem);
12150 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12151 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12152 : 0xE8410028, SImode));
12154 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12155 SImode, NULL_RTX, NULL_RTX,
12156 no_toc_save_needed);
12158 mem = gen_rtx_MEM (Pmode,
12159 gen_rtx_PLUS (Pmode, stack_top,
12160 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12161 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12162 emit_label (no_toc_save_needed);
12165 /* This ties together stack memory (MEM with an alias set of
12166 rs6000_sr_alias_set) and the change to the stack pointer. */
12169 rs6000_emit_stack_tie (void)
12171 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12173 set_mem_alias_set (mem, rs6000_sr_alias_set);
12174 emit_insn (gen_stack_tie (mem));
12177 /* Emit the correct code for allocating stack space, as insns.
12178 If COPY_R12, make sure a copy of the old frame is left in r12.
12179 The generated code may use hard register 0 as a temporary. */
12182 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12185 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12186 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12187 rtx todec = gen_int_mode (-size, Pmode);
12189 if (INTVAL (todec) != -size)
12191 warning ("stack frame too large");
12192 emit_insn (gen_trap ());
12196 if (current_function_limit_stack)
12198 if (REG_P (stack_limit_rtx)
12199 && REGNO (stack_limit_rtx) > 1
12200 && REGNO (stack_limit_rtx) <= 31)
12202 emit_insn (TARGET_32BIT
12203 ? gen_addsi3 (tmp_reg,
12206 : gen_adddi3 (tmp_reg,
12210 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12213 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12215 && DEFAULT_ABI == ABI_V4)
12217 rtx toload = gen_rtx_CONST (VOIDmode,
12218 gen_rtx_PLUS (Pmode,
12222 emit_insn (gen_elf_high (tmp_reg, toload));
12223 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12224 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12228 warning ("stack limit expression is not supported");
12231 if (copy_r12 || ! TARGET_UPDATE)
12232 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12238 /* Need a note here so that try_split doesn't get confused. */
12239 if (get_last_insn () == NULL_RTX)
12240 emit_note (NOTE_INSN_DELETED);
12241 insn = emit_move_insn (tmp_reg, todec);
12242 try_split (PATTERN (insn), insn, 0);
12246 insn = emit_insn (TARGET_32BIT
12247 ? gen_movsi_update (stack_reg, stack_reg,
12249 : gen_movdi_di_update (stack_reg, stack_reg,
12250 todec, stack_reg));
12254 insn = emit_insn (TARGET_32BIT
12255 ? gen_addsi3 (stack_reg, stack_reg, todec)
12256 : gen_adddi3 (stack_reg, stack_reg, todec));
12257 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12258 gen_rtx_REG (Pmode, 12));
12261 RTX_FRAME_RELATED_P (insn) = 1;
12263 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12264 gen_rtx_SET (VOIDmode, stack_reg,
12265 gen_rtx_PLUS (Pmode, stack_reg,
12270 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12271 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12272 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12273 deduce these equivalences by itself so it wasn't necessary to hold
12274 its hand so much. */
12277 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
12278 rtx reg2, rtx rreg)
12282 /* copy_rtx will not make unique copies of registers, so we need to
12283 ensure we don't have unwanted sharing here. */
12285 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12288 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12290 real = copy_rtx (PATTERN (insn));
12292 if (reg2 != NULL_RTX)
12293 real = replace_rtx (real, reg2, rreg);
12295 real = replace_rtx (real, reg,
12296 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12297 STACK_POINTER_REGNUM),
12300 /* We expect that 'real' is either a SET or a PARALLEL containing
12301 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12302 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12304 if (GET_CODE (real) == SET)
12308 temp = simplify_rtx (SET_SRC (set));
12310 SET_SRC (set) = temp;
12311 temp = simplify_rtx (SET_DEST (set));
12313 SET_DEST (set) = temp;
12314 if (GET_CODE (SET_DEST (set)) == MEM)
12316 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12318 XEXP (SET_DEST (set), 0) = temp;
12321 else if (GET_CODE (real) == PARALLEL)
12324 for (i = 0; i < XVECLEN (real, 0); i++)
12325 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12327 rtx set = XVECEXP (real, 0, i);
12329 temp = simplify_rtx (SET_SRC (set));
12331 SET_SRC (set) = temp;
12332 temp = simplify_rtx (SET_DEST (set));
12334 SET_DEST (set) = temp;
12335 if (GET_CODE (SET_DEST (set)) == MEM)
12337 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12339 XEXP (SET_DEST (set), 0) = temp;
12341 RTX_FRAME_RELATED_P (set) = 1;
12348 real = spe_synthesize_frame_save (real);
12350 RTX_FRAME_RELATED_P (insn) = 1;
12351 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12356 /* Given an SPE frame note, return a PARALLEL of SETs with the
12357 original note, plus a synthetic register save. */
12360 spe_synthesize_frame_save (rtx real)
12362 rtx synth, offset, reg, real2;
12364 if (GET_CODE (real) != SET
12365 || GET_MODE (SET_SRC (real)) != V2SImode)
12368 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12369 frame related note. The parallel contains a set of the register
12370 being saved, and another set to a synthetic register (n+1200).
12371 This is so we can differentiate between 64-bit and 32-bit saves.
12372 Words cannot describe this nastiness. */
12374 if (GET_CODE (SET_DEST (real)) != MEM
12375 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12376 || GET_CODE (SET_SRC (real)) != REG)
12380 (set (mem (plus (reg x) (const y)))
12383 (set (mem (plus (reg x) (const y+4)))
12387 real2 = copy_rtx (real);
12388 PUT_MODE (SET_DEST (real2), SImode);
12389 reg = SET_SRC (real2);
12390 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12391 synth = copy_rtx (real2);
12393 if (BYTES_BIG_ENDIAN)
12395 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12396 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12399 reg = SET_SRC (synth);
12401 synth = replace_rtx (synth, reg,
12402 gen_rtx_REG (SImode, REGNO (reg) + 1200));
12404 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12405 synth = replace_rtx (synth, offset,
12406 GEN_INT (INTVAL (offset)
12407 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12409 RTX_FRAME_RELATED_P (synth) = 1;
12410 RTX_FRAME_RELATED_P (real2) = 1;
12411 if (BYTES_BIG_ENDIAN)
12412 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12414 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12419 /* Returns an insn that has a vrsave set operation with the
12420 appropriate CLOBBERs. */
12423 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
12426 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
12427 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12430 = gen_rtx_SET (VOIDmode,
12432 gen_rtx_UNSPEC_VOLATILE (SImode,
12433 gen_rtvec (2, reg, vrsave),
12438 /* We need to clobber the registers in the mask so the scheduler
12439 does not move sets to VRSAVE before sets of AltiVec registers.
12441 However, if the function receives nonlocal gotos, reload will set
12442 all call saved registers live. We will end up with:
12444 (set (reg 999) (mem))
12445 (parallel [ (set (reg vrsave) (unspec blah))
12446 (clobber (reg 999))])
12448 The clobber will cause the store into reg 999 to be dead, and
12449 flow will attempt to delete an epilogue insn. In this case, we
12450 need an unspec use/set of the register. */
12452 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12453 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12455 if (!epiloguep || call_used_regs [i])
12456 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12457 gen_rtx_REG (V4SImode, i));
12460 rtx reg = gen_rtx_REG (V4SImode, i);
12463 = gen_rtx_SET (VOIDmode,
12465 gen_rtx_UNSPEC (V4SImode,
12466 gen_rtvec (1, reg), 27));
12470 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12472 for (i = 0; i < nclobs; ++i)
12473 XVECEXP (insn, 0, i) = clobs[i];
12478 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12479 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12482 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
12483 unsigned int regno, int offset, HOST_WIDE_INT total_size)
12485 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12486 rtx replacea, replaceb;
12488 int_rtx = GEN_INT (offset);
12490 /* Some cases that need register indexed addressing. */
12491 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12492 || (TARGET_E500_DOUBLE && mode == DFmode)
12494 && SPE_VECTOR_MODE (mode)
12495 && !SPE_CONST_OFFSET_OK (offset)))
12497 /* Whomever calls us must make sure r11 is available in the
12498 flow path of instructions in the prologue. */
12499 offset_rtx = gen_rtx_REG (Pmode, 11);
12500 emit_move_insn (offset_rtx, int_rtx);
12502 replacea = offset_rtx;
12503 replaceb = int_rtx;
12507 offset_rtx = int_rtx;
12508 replacea = NULL_RTX;
12509 replaceb = NULL_RTX;
12512 reg = gen_rtx_REG (mode, regno);
12513 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12514 mem = gen_rtx_MEM (mode, addr);
12515 set_mem_alias_set (mem, rs6000_sr_alias_set);
12517 insn = emit_move_insn (mem, reg);
12519 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12522 /* Emit an offset memory reference suitable for a frame store, while
12523 converting to a valid addressing mode. */
12526 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12528 rtx int_rtx, offset_rtx;
12530 int_rtx = GEN_INT (offset);
12532 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12533 || (TARGET_E500_DOUBLE && mode == DFmode))
12535 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12536 emit_move_insn (offset_rtx, int_rtx);
12539 offset_rtx = int_rtx;
12541 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12544 #ifndef TARGET_FIX_AND_CONTINUE
12545 #define TARGET_FIX_AND_CONTINUE 0
12548 /* Emit function prologue as insns. */
12551 rs6000_emit_prologue (void)
12553 rs6000_stack_t *info = rs6000_stack_info ();
12554 enum machine_mode reg_mode = Pmode;
12555 int reg_size = TARGET_32BIT ? 4 : 8;
12556 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12557 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12558 rtx frame_reg_rtx = sp_reg_rtx;
12559 rtx cr_save_rtx = NULL_RTX;
12561 int saving_FPRs_inline;
12562 int using_store_multiple;
12563 HOST_WIDE_INT sp_offset = 0;
12565 if (TARGET_FIX_AND_CONTINUE)
12567 /* gdb on darwin arranges to forward a function from the old
12568 address by modifying the first 4 instructions of the function
12569 to branch to the overriding function. This is necessary to
12570 permit function pointers that point to the old function to
12571 actually forward to the new function. */
12572 emit_insn (gen_nop ());
12573 emit_insn (gen_nop ());
12574 emit_insn (gen_nop ());
12575 emit_insn (gen_nop ());
12578 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12580 reg_mode = V2SImode;
12584 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12585 && (!TARGET_SPE_ABI
12586 || info->spe_64bit_regs_used == 0)
12587 && info->first_gp_reg_save < 31);
12588 saving_FPRs_inline = (info->first_fp_reg_save == 64
12589 || FP_SAVE_INLINE (info->first_fp_reg_save)
12590 || current_function_calls_eh_return
12591 || cfun->machine->ra_need_lr);
12593 /* For V.4, update stack before we do any saving and set back pointer. */
12595 && (DEFAULT_ABI == ABI_V4
12596 || current_function_calls_eh_return))
12598 if (info->total_size < 32767)
12599 sp_offset = info->total_size;
12601 frame_reg_rtx = frame_ptr_rtx;
12602 rs6000_emit_allocate_stack (info->total_size,
12603 (frame_reg_rtx != sp_reg_rtx
12604 && (info->cr_save_p
12606 || info->first_fp_reg_save < 64
12607 || info->first_gp_reg_save < 32
12609 if (frame_reg_rtx != sp_reg_rtx)
12610 rs6000_emit_stack_tie ();
12613 /* Handle world saves specially here. */
12614 if (WORLD_SAVE_P (info))
12620 /* save_world expects lr in r0. */
12621 if (info->lr_save_p)
12623 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12624 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12625 RTX_FRAME_RELATED_P (insn) = 1;
12628 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12629 assumptions about the offsets of various bits of the stack
12630 frame. Abort if things aren't what they should be. */
12631 if (info->gp_save_offset != -220
12632 || info->fp_save_offset != -144
12633 || info->lr_save_offset != 8
12634 || info->cr_save_offset != 4
12636 || !info->lr_save_p
12637 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12638 || (info->vrsave_save_offset != -224
12639 || info->altivec_save_offset != (-224 -16 -192)))
12642 treg = gen_rtx_REG (SImode, 11);
12643 emit_move_insn (treg, GEN_INT (-info->total_size));
12645 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12646 in R11. It also clobbers R12, so beware! */
12648 /* Preserve CR2 for save_world prologues */
12650 sz += 32 - info->first_gp_reg_save;
12651 sz += 64 - info->first_fp_reg_save;
12652 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12653 p = rtvec_alloc (sz);
12655 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
12656 gen_rtx_REG (Pmode,
12657 LINK_REGISTER_REGNUM));
12658 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
12659 gen_rtx_SYMBOL_REF (Pmode,
12661 /* We do floats first so that the instruction pattern matches
12663 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12665 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12666 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12667 GEN_INT (info->fp_save_offset
12668 + sp_offset + 8 * i));
12669 rtx mem = gen_rtx_MEM (DFmode, addr);
12670 set_mem_alias_set (mem, rs6000_sr_alias_set);
12672 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12674 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
12676 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12677 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12678 GEN_INT (info->altivec_save_offset
12679 + sp_offset + 16 * i));
12680 rtx mem = gen_rtx_MEM (V4SImode, addr);
12681 set_mem_alias_set (mem, rs6000_sr_alias_set);
12683 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12685 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12687 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12688 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12689 GEN_INT (info->gp_save_offset
12690 + sp_offset + reg_size * i));
12691 rtx mem = gen_rtx_MEM (reg_mode, addr);
12692 set_mem_alias_set (mem, rs6000_sr_alias_set);
12694 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12698 /* CR register traditionally saved as CR2. */
12699 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12700 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12701 GEN_INT (info->cr_save_offset
12703 rtx mem = gen_rtx_MEM (reg_mode, addr);
12704 set_mem_alias_set (mem, rs6000_sr_alias_set);
12706 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12708 /* Prevent any attempt to delete the setting of r0 and treg! */
12709 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12710 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12711 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12713 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12714 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12715 NULL_RTX, NULL_RTX);
12717 if (current_function_calls_eh_return)
12722 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12723 if (regno == INVALID_REGNUM)
12725 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12726 info->ehrd_offset + sp_offset
12727 + reg_size * (int) i,
12733 /* Save AltiVec registers if needed. */
12734 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12738 /* There should be a non inline version of this, for when we
12739 are saving lots of vector registers. */
12740 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12741 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12743 rtx areg, savereg, mem;
12746 offset = info->altivec_save_offset + sp_offset
12747 + 16 * (i - info->first_altivec_reg_save);
12749 savereg = gen_rtx_REG (V4SImode, i);
12751 areg = gen_rtx_REG (Pmode, 0);
12752 emit_move_insn (areg, GEN_INT (offset));
12754 /* AltiVec addressing mode is [reg+reg]. */
12755 mem = gen_rtx_MEM (V4SImode,
12756 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12758 set_mem_alias_set (mem, rs6000_sr_alias_set);
12760 insn = emit_move_insn (mem, savereg);
12762 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12763 areg, GEN_INT (offset));
12767 /* VRSAVE is a bit vector representing which AltiVec registers
12768 are used. The OS uses this to determine which vector
12769 registers to save on a context switch. We need to save
12770 VRSAVE on the stack frame, add whatever AltiVec registers we
12771 used in this function, and do the corresponding magic in the
12774 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12775 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
12777 rtx reg, mem, vrsave;
12780 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12781 as frame_reg_rtx and r11 as the static chain pointer for
12782 nested functions. */
12783 reg = gen_rtx_REG (SImode, 0);
12784 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12786 emit_insn (gen_get_vrsave_internal (reg));
12788 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12791 offset = info->vrsave_save_offset + sp_offset;
12793 = gen_rtx_MEM (SImode,
12794 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12795 set_mem_alias_set (mem, rs6000_sr_alias_set);
12796 insn = emit_move_insn (mem, reg);
12798 /* Include the registers in the mask. */
12799 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12801 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12804 /* If we use the link register, get it into r0. */
12805 if (!WORLD_SAVE_P (info) && info->lr_save_p)
12807 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12808 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12809 RTX_FRAME_RELATED_P (insn) = 1;
12812 /* If we need to save CR, put it into r12. */
12813 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12817 cr_save_rtx = gen_rtx_REG (SImode, 12);
12818 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12819 RTX_FRAME_RELATED_P (insn) = 1;
12820 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12821 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12822 But that's OK. All we have to do is specify that _one_ condition
12823 code register is saved in this stack slot. The thrower's epilogue
12824 will then restore all the call-saved registers.
12825 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12826 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12827 gen_rtx_REG (SImode, CR2_REGNO));
12828 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12833 /* Do any required saving of fpr's. If only one or two to save, do
12834 it ourselves. Otherwise, call function. */
12835 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
12838 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12839 if ((regs_ever_live[info->first_fp_reg_save+i]
12840 && ! call_used_regs[info->first_fp_reg_save+i]))
12841 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12842 info->first_fp_reg_save + i,
12843 info->fp_save_offset + sp_offset + 8 * i,
12846 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
12850 const char *alloc_rname;
12852 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12854 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12855 gen_rtx_REG (Pmode,
12856 LINK_REGISTER_REGNUM));
12857 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12858 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12859 alloc_rname = ggc_strdup (rname);
12860 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12861 gen_rtx_SYMBOL_REF (Pmode,
12863 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12865 rtx addr, reg, mem;
12866 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12867 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12868 GEN_INT (info->fp_save_offset
12869 + sp_offset + 8*i));
12870 mem = gen_rtx_MEM (DFmode, addr);
12871 set_mem_alias_set (mem, rs6000_sr_alias_set);
12873 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12875 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12876 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12877 NULL_RTX, NULL_RTX);
12880 /* Save GPRs. This is done as a PARALLEL if we are using
12881 the store-multiple instructions. */
12882 if (!WORLD_SAVE_P (info) && using_store_multiple)
12886 p = rtvec_alloc (32 - info->first_gp_reg_save);
12887 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12889 rtx addr, reg, mem;
12890 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12891 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12892 GEN_INT (info->gp_save_offset
12895 mem = gen_rtx_MEM (reg_mode, addr);
12896 set_mem_alias_set (mem, rs6000_sr_alias_set);
12898 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12900 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12901 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12902 NULL_RTX, NULL_RTX);
12904 else if (!WORLD_SAVE_P (info))
12907 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12908 if ((regs_ever_live[info->first_gp_reg_save+i]
12909 && (! call_used_regs[info->first_gp_reg_save+i]
12910 || (i+info->first_gp_reg_save
12911 == RS6000_PIC_OFFSET_TABLE_REGNUM
12912 && TARGET_TOC && TARGET_MINIMAL_TOC)))
12913 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12914 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12915 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12917 rtx addr, reg, mem;
12918 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12920 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12922 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12925 if (!SPE_CONST_OFFSET_OK (offset))
12927 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12928 emit_move_insn (b, GEN_INT (offset));
12931 b = GEN_INT (offset);
12933 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12934 mem = gen_rtx_MEM (V2SImode, addr);
12935 set_mem_alias_set (mem, rs6000_sr_alias_set);
12936 insn = emit_move_insn (mem, reg);
12938 if (GET_CODE (b) == CONST_INT)
12939 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12940 NULL_RTX, NULL_RTX);
12942 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12943 b, GEN_INT (offset));
12947 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12948 GEN_INT (info->gp_save_offset
12951 mem = gen_rtx_MEM (reg_mode, addr);
12952 set_mem_alias_set (mem, rs6000_sr_alias_set);
12954 insn = emit_move_insn (mem, reg);
12955 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12956 NULL_RTX, NULL_RTX);
12961 /* ??? There's no need to emit actual instructions here, but it's the
12962 easiest way to get the frame unwind information emitted. */
12963 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
12965 unsigned int i, regno;
12967 /* In AIX ABI we need to pretend we save r2 here. */
12970 rtx addr, reg, mem;
12972 reg = gen_rtx_REG (reg_mode, 2);
12973 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12974 GEN_INT (sp_offset + 5 * reg_size));
12975 mem = gen_rtx_MEM (reg_mode, addr);
12976 set_mem_alias_set (mem, rs6000_sr_alias_set);
12978 insn = emit_move_insn (mem, reg);
12979 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12980 NULL_RTX, NULL_RTX);
12981 PATTERN (insn) = gen_blockage ();
12986 regno = EH_RETURN_DATA_REGNO (i);
12987 if (regno == INVALID_REGNUM)
12990 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12991 info->ehrd_offset + sp_offset
12992 + reg_size * (int) i,
12997 /* Save lr if we used it. */
12998 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13000 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13001 GEN_INT (info->lr_save_offset + sp_offset));
13002 rtx reg = gen_rtx_REG (Pmode, 0);
13003 rtx mem = gen_rtx_MEM (Pmode, addr);
13004 /* This should not be of rs6000_sr_alias_set, because of
13005 __builtin_return_address. */
13007 insn = emit_move_insn (mem, reg);
13008 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13009 NULL_RTX, NULL_RTX);
13012 /* Save CR if we use any that must be preserved. */
13013 if (!WORLD_SAVE_P (info) && info->cr_save_p)
13015 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13016 GEN_INT (info->cr_save_offset + sp_offset));
13017 rtx mem = gen_rtx_MEM (SImode, addr);
13018 /* See the large comment above about why CR2_REGNO is used. */
13019 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13021 set_mem_alias_set (mem, rs6000_sr_alias_set);
13023 /* If r12 was used to hold the original sp, copy cr into r0 now
13025 if (REGNO (frame_reg_rtx) == 12)
13029 cr_save_rtx = gen_rtx_REG (SImode, 0);
13030 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13031 RTX_FRAME_RELATED_P (insn) = 1;
13032 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13033 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13038 insn = emit_move_insn (mem, cr_save_rtx);
13040 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13041 NULL_RTX, NULL_RTX);
13044 /* Update stack and set back pointer unless this is V.4,
13045 for which it was done previously. */
13046 if (!WORLD_SAVE_P (info) && info->push_p
13047 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13048 rs6000_emit_allocate_stack (info->total_size, FALSE);
13050 /* Set frame pointer, if needed. */
13051 if (frame_pointer_needed)
13053 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13055 RTX_FRAME_RELATED_P (insn) = 1;
13058 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13059 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13060 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13061 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13063 /* If emit_load_toc_table will use the link register, we need to save
13064 it. We use R12 for this purpose because emit_load_toc_table
13065 can use register 0. This allows us to use a plain 'blr' to return
13066 from the procedure more often. */
13067 int save_LR_around_toc_setup = (TARGET_ELF
13068 && DEFAULT_ABI != ABI_AIX
13070 && ! info->lr_save_p
13071 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13072 if (save_LR_around_toc_setup)
13074 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13076 insn = emit_move_insn (frame_ptr_rtx, lr);
13077 rs6000_maybe_dead (insn);
13078 RTX_FRAME_RELATED_P (insn) = 1;
13080 rs6000_emit_load_toc_table (TRUE);
13082 insn = emit_move_insn (lr, frame_ptr_rtx);
13083 rs6000_maybe_dead (insn);
13084 RTX_FRAME_RELATED_P (insn) = 1;
13087 rs6000_emit_load_toc_table (TRUE);
13091 if (DEFAULT_ABI == ABI_DARWIN
13092 && flag_pic && current_function_uses_pic_offset_table)
13094 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13095 rtx src = machopic_function_base_sym ();
13097 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13099 insn = emit_move_insn (gen_rtx_REG (Pmode,
13100 RS6000_PIC_OFFSET_TABLE_REGNUM),
13102 rs6000_maybe_dead (insn);
13107 /* Write function prologue. */
13110 rs6000_output_function_prologue (FILE *file,
13111 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13113 rs6000_stack_t *info = rs6000_stack_info ();
13115 if (TARGET_DEBUG_STACK)
13116 debug_stack_info (info);
13118 /* Write .extern for any function we will call to save and restore
13120 if (info->first_fp_reg_save < 64
13121 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13122 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13123 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13124 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13125 RESTORE_FP_SUFFIX);
13127 /* Write .extern for AIX common mode routines, if needed. */
13128 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13130 fputs ("\t.extern __mulh\n", file);
13131 fputs ("\t.extern __mull\n", file);
13132 fputs ("\t.extern __divss\n", file);
13133 fputs ("\t.extern __divus\n", file);
13134 fputs ("\t.extern __quoss\n", file);
13135 fputs ("\t.extern __quous\n", file);
13136 common_mode_defined = 1;
13139 if (! HAVE_prologue)
13143 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13144 the "toplevel" insn chain. */
13145 emit_note (NOTE_INSN_DELETED);
13146 rs6000_emit_prologue ();
13147 emit_note (NOTE_INSN_DELETED);
13149 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13153 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13155 INSN_ADDRESSES_NEW (insn, addr);
13160 if (TARGET_DEBUG_STACK)
13161 debug_rtx_list (get_insns (), 100);
13162 final (get_insns (), file, FALSE);
13166 rs6000_pic_labelno++;
13169 /* Emit function epilogue as insns.
13171 At present, dwarf2out_frame_debug_expr doesn't understand
13172 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13173 anywhere in the epilogue. Most of the insns below would in any case
13174 need special notes to explain where r11 is in relation to the stack. */
13177 rs6000_emit_epilogue (int sibcall)
13179 rs6000_stack_t *info;
13180 int restoring_FPRs_inline;
13181 int using_load_multiple;
13182 int using_mfcr_multiple;
13183 int use_backchain_to_restore_sp;
13185 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13186 rtx frame_reg_rtx = sp_reg_rtx;
13187 enum machine_mode reg_mode = Pmode;
13188 int reg_size = TARGET_32BIT ? 4 : 8;
13191 info = rs6000_stack_info ();
13193 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13195 reg_mode = V2SImode;
13199 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13200 && (!TARGET_SPE_ABI
13201 || info->spe_64bit_regs_used == 0)
13202 && info->first_gp_reg_save < 31);
13203 restoring_FPRs_inline = (sibcall
13204 || current_function_calls_eh_return
13205 || info->first_fp_reg_save == 64
13206 || FP_SAVE_INLINE (info->first_fp_reg_save));
13207 use_backchain_to_restore_sp = (frame_pointer_needed
13208 || current_function_calls_alloca
13209 || info->total_size > 32767);
13210 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13211 || rs6000_cpu == PROCESSOR_PPC603
13212 || rs6000_cpu == PROCESSOR_PPC750
13215 if (WORLD_SAVE_P (info))
13219 const char *alloc_rname;
13222 /* eh_rest_world_r10 will return to the location saved in the LR
13223 stack slot (which is not likely to be our caller.)
13224 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13225 rest_world is similar, except any R10 parameter is ignored.
13226 The exception-handling stuff that was here in 2.95 is no
13227 longer necessary. */
13231 + 32 - info->first_gp_reg_save
13232 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13233 + 63 + 1 - info->first_fp_reg_save);
13235 strcpy (rname, ((current_function_calls_eh_return) ?
13236 "*eh_rest_world_r10" : "*rest_world"));
13237 alloc_rname = ggc_strdup (rname);
13240 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13241 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13242 gen_rtx_REG (Pmode,
13243 LINK_REGISTER_REGNUM));
13245 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13246 /* The instruction pattern requires a clobber here;
13247 it is shared with the restVEC helper. */
13249 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
13252 /* CR register traditionally saved as CR2. */
13253 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13254 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13255 GEN_INT (info->cr_save_offset));
13256 rtx mem = gen_rtx_MEM (reg_mode, addr);
13257 set_mem_alias_set (mem, rs6000_sr_alias_set);
13259 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13262 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13264 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13265 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13266 GEN_INT (info->gp_save_offset
13268 rtx mem = gen_rtx_MEM (reg_mode, addr);
13269 set_mem_alias_set (mem, rs6000_sr_alias_set);
13271 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13273 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13275 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13276 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13277 GEN_INT (info->altivec_save_offset
13279 rtx mem = gen_rtx_MEM (V4SImode, addr);
13280 set_mem_alias_set (mem, rs6000_sr_alias_set);
13282 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13284 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
13286 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13287 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13288 GEN_INT (info->fp_save_offset
13290 rtx mem = gen_rtx_MEM (DFmode, addr);
13291 set_mem_alias_set (mem, rs6000_sr_alias_set);
13293 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13296 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
13298 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
13300 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
13302 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
13304 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
13305 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13310 /* If we have a frame pointer, a call to alloca, or a large stack
13311 frame, restore the old stack pointer using the backchain. Otherwise,
13312 we know what size to update it with. */
13313 if (use_backchain_to_restore_sp)
13315 /* Under V.4, don't reset the stack pointer until after we're done
13316 loading the saved registers. */
13317 if (DEFAULT_ABI == ABI_V4)
13318 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
13320 emit_move_insn (frame_reg_rtx,
13321 gen_rtx_MEM (Pmode, sp_reg_rtx));
13324 else if (info->push_p)
13326 if (DEFAULT_ABI == ABI_V4
13327 || current_function_calls_eh_return)
13328 sp_offset = info->total_size;
13331 emit_insn (TARGET_32BIT
13332 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13333 GEN_INT (info->total_size))
13334 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13335 GEN_INT (info->total_size)));
13339 /* Restore AltiVec registers if needed. */
13340 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13344 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13345 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13347 rtx addr, areg, mem;
13349 areg = gen_rtx_REG (Pmode, 0);
13351 (areg, GEN_INT (info->altivec_save_offset
13353 + 16 * (i - info->first_altivec_reg_save)));
13355 /* AltiVec addressing mode is [reg+reg]. */
13356 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13357 mem = gen_rtx_MEM (V4SImode, addr);
13358 set_mem_alias_set (mem, rs6000_sr_alias_set);
13360 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13364 /* Restore VRSAVE if needed. */
13365 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13366 && info->vrsave_mask != 0)
13368 rtx addr, mem, reg;
13370 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13371 GEN_INT (info->vrsave_save_offset + sp_offset));
13372 mem = gen_rtx_MEM (SImode, addr);
13373 set_mem_alias_set (mem, rs6000_sr_alias_set);
13374 reg = gen_rtx_REG (SImode, 12);
13375 emit_move_insn (reg, mem);
13377 emit_insn (generate_set_vrsave (reg, info, 1));
13380 /* Get the old lr if we saved it. */
13381 if (info->lr_save_p)
13383 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13384 info->lr_save_offset + sp_offset);
13386 set_mem_alias_set (mem, rs6000_sr_alias_set);
13388 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
13391 /* Get the old cr if we saved it. */
13392 if (info->cr_save_p)
13394 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13395 GEN_INT (info->cr_save_offset + sp_offset));
13396 rtx mem = gen_rtx_MEM (SImode, addr);
13398 set_mem_alias_set (mem, rs6000_sr_alias_set);
13400 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13403 /* Set LR here to try to overlap restores below. */
13404 if (info->lr_save_p)
13405 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13406 gen_rtx_REG (Pmode, 0));
13408 /* Load exception handler data registers, if needed. */
13409 if (current_function_calls_eh_return)
13411 unsigned int i, regno;
13415 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13416 GEN_INT (sp_offset + 5 * reg_size));
13417 rtx mem = gen_rtx_MEM (reg_mode, addr);
13419 set_mem_alias_set (mem, rs6000_sr_alias_set);
13421 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13428 regno = EH_RETURN_DATA_REGNO (i);
13429 if (regno == INVALID_REGNUM)
13432 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13433 info->ehrd_offset + sp_offset
13434 + reg_size * (int) i);
13435 set_mem_alias_set (mem, rs6000_sr_alias_set);
13437 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13441 /* Restore GPRs. This is done as a PARALLEL if we are using
13442 the load-multiple instructions. */
13443 if (using_load_multiple)
13446 p = rtvec_alloc (32 - info->first_gp_reg_save);
13447 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13449 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13450 GEN_INT (info->gp_save_offset
13453 rtx mem = gen_rtx_MEM (reg_mode, addr);
13455 set_mem_alias_set (mem, rs6000_sr_alias_set);
13458 gen_rtx_SET (VOIDmode,
13459 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13462 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13465 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13466 if ((regs_ever_live[info->first_gp_reg_save+i]
13467 && (! call_used_regs[info->first_gp_reg_save+i]
13468 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13469 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13470 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13471 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13472 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13474 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13475 GEN_INT (info->gp_save_offset
13478 rtx mem = gen_rtx_MEM (reg_mode, addr);
13480 /* Restore 64-bit quantities for SPE. */
13481 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13483 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13486 if (!SPE_CONST_OFFSET_OK (offset))
13488 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13489 emit_move_insn (b, GEN_INT (offset));
13492 b = GEN_INT (offset);
13494 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13495 mem = gen_rtx_MEM (V2SImode, addr);
13498 set_mem_alias_set (mem, rs6000_sr_alias_set);
13500 emit_move_insn (gen_rtx_REG (reg_mode,
13501 info->first_gp_reg_save + i), mem);
13504 /* Restore fpr's if we need to do it without calling a function. */
13505 if (restoring_FPRs_inline)
13506 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13507 if ((regs_ever_live[info->first_fp_reg_save+i]
13508 && ! call_used_regs[info->first_fp_reg_save+i]))
13511 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13512 GEN_INT (info->fp_save_offset
13515 mem = gen_rtx_MEM (DFmode, addr);
13516 set_mem_alias_set (mem, rs6000_sr_alias_set);
13518 emit_move_insn (gen_rtx_REG (DFmode,
13519 info->first_fp_reg_save + i),
13523 /* If we saved cr, restore it here. Just those that were used. */
13524 if (info->cr_save_p)
13526 rtx r12_rtx = gen_rtx_REG (SImode, 12);
13529 if (using_mfcr_multiple)
13531 for (i = 0; i < 8; i++)
13532 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13538 if (using_mfcr_multiple && count > 1)
13543 p = rtvec_alloc (count);
13546 for (i = 0; i < 8; i++)
13547 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13549 rtvec r = rtvec_alloc (2);
13550 RTVEC_ELT (r, 0) = r12_rtx;
13551 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
13552 RTVEC_ELT (p, ndx) =
13553 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
13554 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
13557 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13562 for (i = 0; i < 8; i++)
13563 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13565 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
13571 /* If this is V.4, unwind the stack pointer after all of the loads
13572 have been done. We need to emit a block here so that sched
13573 doesn't decide to move the sp change before the register restores
13574 (which may not have any obvious dependency on the stack). This
13575 doesn't hurt performance, because there is no scheduling that can
13576 be done after this point. */
13577 if (DEFAULT_ABI == ABI_V4
13578 || current_function_calls_eh_return)
13580 if (frame_reg_rtx != sp_reg_rtx)
13581 rs6000_emit_stack_tie ();
13583 if (use_backchain_to_restore_sp)
13585 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
13587 else if (sp_offset != 0)
13589 emit_insn (TARGET_32BIT
13590 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13591 GEN_INT (sp_offset))
13592 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13593 GEN_INT (sp_offset)));
13597 if (current_function_calls_eh_return)
13599 rtx sa = EH_RETURN_STACKADJ_RTX;
13600 emit_insn (TARGET_32BIT
13601 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13602 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13608 if (! restoring_FPRs_inline)
13609 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13611 p = rtvec_alloc (2);
13613 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
13614 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13615 gen_rtx_REG (Pmode,
13616 LINK_REGISTER_REGNUM));
13618 /* If we have to restore more than two FP registers, branch to the
13619 restore function. It will return to our caller. */
13620 if (! restoring_FPRs_inline)
13624 const char *alloc_rname;
13626 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
13627 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
13628 alloc_rname = ggc_strdup (rname);
13629 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13630 gen_rtx_SYMBOL_REF (Pmode,
13633 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13636 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13637 GEN_INT (info->fp_save_offset + 8*i));
13638 mem = gen_rtx_MEM (DFmode, addr);
13639 set_mem_alias_set (mem, rs6000_sr_alias_set);
13641 RTVEC_ELT (p, i+3) =
13642 gen_rtx_SET (VOIDmode,
13643 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13648 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13652 /* Write function epilogue. */
13655 rs6000_output_function_epilogue (FILE *file,
13656 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13658 rs6000_stack_t *info = rs6000_stack_info ();
13660 if (! HAVE_epilogue)
13662 rtx insn = get_last_insn ();
13663 /* If the last insn was a BARRIER, we don't have to write anything except
13664 the trace table. */
13665 if (GET_CODE (insn) == NOTE)
13666 insn = prev_nonnote_insn (insn);
13667 if (insn == 0 || GET_CODE (insn) != BARRIER)
13669 /* This is slightly ugly, but at least we don't have two
13670 copies of the epilogue-emitting code. */
13673 /* A NOTE_INSN_DELETED is supposed to be at the start
13674 and end of the "toplevel" insn chain. */
13675 emit_note (NOTE_INSN_DELETED);
13676 rs6000_emit_epilogue (FALSE);
13677 emit_note (NOTE_INSN_DELETED);
13679 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13683 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13685 INSN_ADDRESSES_NEW (insn, addr);
13690 if (TARGET_DEBUG_STACK)
13691 debug_rtx_list (get_insns (), 100);
13692 final (get_insns (), file, FALSE);
13698 macho_branch_islands ();
13699 /* Mach-O doesn't support labels at the end of objects, so if
13700 it looks like we might want one, insert a NOP. */
13702 rtx insn = get_last_insn ();
13705 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13706 insn = PREV_INSN (insn);
13710 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13711 fputs ("\tnop\n", file);
13715 /* Output a traceback table here. See /usr/include/sys/debug.h for info
13718 We don't output a traceback table if -finhibit-size-directive was
13719 used. The documentation for -finhibit-size-directive reads
13720 ``don't output a @code{.size} assembler directive, or anything
13721 else that would cause trouble if the function is split in the
13722 middle, and the two halves are placed at locations far apart in
13723 memory.'' The traceback table has this property, since it
13724 includes the offset from the start of the function to the
13725 traceback table itself.
13727 System V.4 Powerpc's (and the embedded ABI derived from it) use a
13728 different traceback table. */
13729 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13730 && rs6000_traceback != traceback_none)
13732 const char *fname = NULL;
13733 const char *language_string = lang_hooks.name;
13734 int fixed_parms = 0, float_parms = 0, parm_info = 0;
13736 int optional_tbtab;
13738 if (rs6000_traceback == traceback_full)
13739 optional_tbtab = 1;
13740 else if (rs6000_traceback == traceback_part)
13741 optional_tbtab = 0;
13743 optional_tbtab = !optimize_size && !TARGET_ELF;
13745 if (optional_tbtab)
13747 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13748 while (*fname == '.') /* V.4 encodes . in the name */
13751 /* Need label immediately before tbtab, so we can compute
13752 its offset from the function start. */
13753 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13754 ASM_OUTPUT_LABEL (file, fname);
13757 /* The .tbtab pseudo-op can only be used for the first eight
13758 expressions, since it can't handle the possibly variable
13759 length fields that follow. However, if you omit the optional
13760 fields, the assembler outputs zeros for all optional fields
13761 anyways, giving each variable length field is minimum length
13762 (as defined in sys/debug.h). Thus we can not use the .tbtab
13763 pseudo-op at all. */
13765 /* An all-zero word flags the start of the tbtab, for debuggers
13766 that have to find it by searching forward from the entry
13767 point or from the current pc. */
13768 fputs ("\t.long 0\n", file);
13770 /* Tbtab format type. Use format type 0. */
13771 fputs ("\t.byte 0,", file);
13773 /* Language type. Unfortunately, there does not seem to be any
13774 official way to discover the language being compiled, so we
13775 use language_string.
13776 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13777 Java is 13. Objective-C is 14. */
13778 if (! strcmp (language_string, "GNU C"))
13780 else if (! strcmp (language_string, "GNU F77")
13781 || ! strcmp (language_string, "GNU F95"))
13783 else if (! strcmp (language_string, "GNU Pascal"))
13785 else if (! strcmp (language_string, "GNU Ada"))
13787 else if (! strcmp (language_string, "GNU C++"))
13789 else if (! strcmp (language_string, "GNU Java"))
13791 else if (! strcmp (language_string, "GNU Objective-C"))
13795 fprintf (file, "%d,", i);
13797 /* 8 single bit fields: global linkage (not set for C extern linkage,
13798 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13799 from start of procedure stored in tbtab, internal function, function
13800 has controlled storage, function has no toc, function uses fp,
13801 function logs/aborts fp operations. */
13802 /* Assume that fp operations are used if any fp reg must be saved. */
13803 fprintf (file, "%d,",
13804 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
13806 /* 6 bitfields: function is interrupt handler, name present in
13807 proc table, function calls alloca, on condition directives
13808 (controls stack walks, 3 bits), saves condition reg, saves
13810 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13811 set up as a frame pointer, even when there is no alloca call. */
13812 fprintf (file, "%d,",
13813 ((optional_tbtab << 6)
13814 | ((optional_tbtab & frame_pointer_needed) << 5)
13815 | (info->cr_save_p << 1)
13816 | (info->lr_save_p)));
13818 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
13820 fprintf (file, "%d,",
13821 (info->push_p << 7) | (64 - info->first_fp_reg_save));
13823 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13824 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13826 if (optional_tbtab)
13828 /* Compute the parameter info from the function decl argument
13831 int next_parm_info_bit = 31;
13833 for (decl = DECL_ARGUMENTS (current_function_decl);
13834 decl; decl = TREE_CHAIN (decl))
13836 rtx parameter = DECL_INCOMING_RTL (decl);
13837 enum machine_mode mode = GET_MODE (parameter);
13839 if (GET_CODE (parameter) == REG)
13841 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13847 if (mode == SFmode)
13849 else if (mode == DFmode || mode == TFmode)
13854 /* If only one bit will fit, don't or in this entry. */
13855 if (next_parm_info_bit > 0)
13856 parm_info |= (bits << (next_parm_info_bit - 1));
13857 next_parm_info_bit -= 2;
13861 fixed_parms += ((GET_MODE_SIZE (mode)
13862 + (UNITS_PER_WORD - 1))
13864 next_parm_info_bit -= 1;
13870 /* Number of fixed point parameters. */
13871 /* This is actually the number of words of fixed point parameters; thus
13872 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13873 fprintf (file, "%d,", fixed_parms);
13875 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13877 /* This is actually the number of fp registers that hold parameters;
13878 and thus the maximum value is 13. */
13879 /* Set parameters on stack bit if parameters are not in their original
13880 registers, regardless of whether they are on the stack? Xlc
13881 seems to set the bit when not optimizing. */
13882 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13884 if (! optional_tbtab)
13887 /* Optional fields follow. Some are variable length. */
13889 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13890 11 double float. */
13891 /* There is an entry for each parameter in a register, in the order that
13892 they occur in the parameter list. Any intervening arguments on the
13893 stack are ignored. If the list overflows a long (max possible length
13894 34 bits) then completely leave off all elements that don't fit. */
13895 /* Only emit this long if there was at least one parameter. */
13896 if (fixed_parms || float_parms)
13897 fprintf (file, "\t.long %d\n", parm_info);
13899 /* Offset from start of code to tb table. */
13900 fputs ("\t.long ", file);
13901 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13903 RS6000_OUTPUT_BASENAME (file, fname);
13905 assemble_name (file, fname);
13907 rs6000_output_function_entry (file, fname);
13910 /* Interrupt handler mask. */
13911 /* Omit this long, since we never set the interrupt handler bit
13914 /* Number of CTL (controlled storage) anchors. */
13915 /* Omit this long, since the has_ctl bit is never set above. */
13917 /* Displacement into stack of each CTL anchor. */
13918 /* Omit this list of longs, because there are no CTL anchors. */
13920 /* Length of function name. */
13923 fprintf (file, "\t.short %d\n", (int) strlen (fname));
13925 /* Function name. */
13926 assemble_string (fname, strlen (fname));
13928 /* Register for alloca automatic storage; this is always reg 31.
13929 Only emit this if the alloca bit was set above. */
13930 if (frame_pointer_needed)
13931 fputs ("\t.byte 31\n", file);
13933 fputs ("\t.align 2\n", file);
13937 /* A C compound statement that outputs the assembler code for a thunk
13938 function, used to implement C++ virtual function calls with
13939 multiple inheritance. The thunk acts as a wrapper around a virtual
13940 function, adjusting the implicit object parameter before handing
13941 control off to the real function.
13943 First, emit code to add the integer DELTA to the location that
13944 contains the incoming first argument. Assume that this argument
13945 contains a pointer, and is the one used to pass the `this' pointer
13946 in C++. This is the incoming argument *before* the function
13947 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13948 values of all other incoming arguments.
13950 After the addition, emit code to jump to FUNCTION, which is a
13951 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
13952 not touch the return address. Hence returning from FUNCTION will
13953 return to whoever called the current `thunk'.
13955 The effect must be as if FUNCTION had been called directly with the
13956 adjusted first argument. This macro is responsible for emitting
13957 all of the code for a thunk function; output_function_prologue()
13958 and output_function_epilogue() are not invoked.
13960 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
13961 been extracted from it.) It might possibly be useful on some
13962 targets, but probably not.
13964 If you do not define this macro, the target-independent code in the
13965 C++ frontend will generate a less efficient heavyweight thunk that
13966 calls FUNCTION instead of jumping to it. The generic approach does
13967 not support varargs. */
13970 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
13971 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
13974 rtx this, insn, funexp;
13976 reload_completed = 1;
13977 epilogue_completed = 1;
13978 no_new_pseudos = 1;
13979 reset_block_changes ();
13981 /* Mark the end of the (empty) prologue. */
13982 emit_note (NOTE_INSN_PROLOGUE_END);
13984 /* Find the "this" pointer. If the function returns a structure,
13985 the structure return pointer is in r3. */
13986 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
13987 this = gen_rtx_REG (Pmode, 4);
13989 this = gen_rtx_REG (Pmode, 3);
13991 /* Apply the constant offset, if required. */
13994 rtx delta_rtx = GEN_INT (delta);
13995 emit_insn (TARGET_32BIT
13996 ? gen_addsi3 (this, this, delta_rtx)
13997 : gen_adddi3 (this, this, delta_rtx));
14000 /* Apply the offset from the vtable, if required. */
14003 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14004 rtx tmp = gen_rtx_REG (Pmode, 12);
14006 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14007 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14009 emit_insn (TARGET_32BIT
14010 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14011 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14012 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14016 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14018 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14020 emit_insn (TARGET_32BIT
14021 ? gen_addsi3 (this, this, tmp)
14022 : gen_adddi3 (this, this, tmp));
14025 /* Generate a tail call to the target function. */
14026 if (!TREE_USED (function))
14028 assemble_external (function);
14029 TREE_USED (function) = 1;
14031 funexp = XEXP (DECL_RTL (function), 0);
14032 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14035 if (MACHOPIC_INDIRECT)
14036 funexp = machopic_indirect_call_target (funexp);
14039 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14040 generate sibcall RTL explicitly to avoid constraint abort. */
14041 insn = emit_call_insn (
14042 gen_rtx_PARALLEL (VOIDmode,
14044 gen_rtx_CALL (VOIDmode,
14045 funexp, const0_rtx),
14046 gen_rtx_USE (VOIDmode, const0_rtx),
14047 gen_rtx_USE (VOIDmode,
14048 gen_rtx_REG (SImode,
14049 LINK_REGISTER_REGNUM)),
14050 gen_rtx_RETURN (VOIDmode))));
14051 SIBLING_CALL_P (insn) = 1;
14054 /* Run just enough of rest_of_compilation to get the insns emitted.
14055 There's not really enough bulk here to make other passes such as
14056 instruction scheduling worth while. Note that use_thunk calls
14057 assemble_start_function and assemble_end_function. */
14058 insn = get_insns ();
14059 insn_locators_initialize ();
14060 shorten_branches (insn);
14061 final_start_function (insn, file, 1);
14062 final (insn, file, 1);
14063 final_end_function ();
14065 reload_completed = 0;
14066 epilogue_completed = 0;
14067 no_new_pseudos = 0;
14070 /* A quick summary of the various types of 'constant-pool tables'
14073 Target Flags Name One table per
14074 AIX (none) AIX TOC object file
14075 AIX -mfull-toc AIX TOC object file
14076 AIX -mminimal-toc AIX minimal TOC translation unit
14077 SVR4/EABI (none) SVR4 SDATA object file
14078 SVR4/EABI -fpic SVR4 pic object file
14079 SVR4/EABI -fPIC SVR4 PIC translation unit
14080 SVR4/EABI -mrelocatable EABI TOC function
14081 SVR4/EABI -maix AIX TOC object file
14082 SVR4/EABI -maix -mminimal-toc
14083 AIX minimal TOC translation unit
14085 Name Reg. Set by entries contains:
14086 made by addrs? fp? sum?
14088 AIX TOC 2 crt0 as Y option option
14089 AIX minimal TOC 30 prolog gcc Y Y option
14090 SVR4 SDATA 13 crt0 gcc N Y N
14091 SVR4 pic 30 prolog ld Y not yet N
14092 SVR4 PIC 30 prolog gcc Y option option
14093 EABI TOC 30 prolog gcc Y option option
14097 /* Hash functions for the hash table. */
14100 rs6000_hash_constant (rtx k)
14102 enum rtx_code code = GET_CODE (k);
14103 enum machine_mode mode = GET_MODE (k);
14104 unsigned result = (code << 3) ^ mode;
14105 const char *format;
14108 format = GET_RTX_FORMAT (code);
14109 flen = strlen (format);
14115 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14118 if (mode != VOIDmode)
14119 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14131 for (; fidx < flen; fidx++)
14132 switch (format[fidx])
14137 const char *str = XSTR (k, fidx);
14138 len = strlen (str);
14139 result = result * 613 + len;
14140 for (i = 0; i < len; i++)
14141 result = result * 613 + (unsigned) str[i];
14146 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14150 result = result * 613 + (unsigned) XINT (k, fidx);
14153 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14154 result = result * 613 + (unsigned) XWINT (k, fidx);
14158 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
14159 result = result * 613 + (unsigned) (XWINT (k, fidx)
14173 toc_hash_function (const void *hash_entry)
14175 const struct toc_hash_struct *thc =
14176 (const struct toc_hash_struct *) hash_entry;
14177 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14180 /* Compare H1 and H2 for equivalence. */
14183 toc_hash_eq (const void *h1, const void *h2)
14185 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14186 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14188 if (((const struct toc_hash_struct *) h1)->key_mode
14189 != ((const struct toc_hash_struct *) h2)->key_mode)
14192 return rtx_equal_p (r1, r2);
14195 /* These are the names given by the C++ front-end to vtables, and
14196 vtable-like objects. Ideally, this logic should not be here;
14197 instead, there should be some programmatic way of inquiring as
14198 to whether or not an object is a vtable. */
14200 #define VTABLE_NAME_P(NAME) \
14201 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
14202 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14203 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14204 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14205 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14208 rs6000_output_symbol_ref (FILE *file, rtx x)
14210 /* Currently C++ toc references to vtables can be emitted before it
14211 is decided whether the vtable is public or private. If this is
14212 the case, then the linker will eventually complain that there is
14213 a reference to an unknown section. Thus, for vtables only,
14214 we emit the TOC reference to reference the symbol and not the
14216 const char *name = XSTR (x, 0);
14218 if (VTABLE_NAME_P (name))
14220 RS6000_OUTPUT_BASENAME (file, name);
14223 assemble_name (file, name);
14226 /* Output a TOC entry. We derive the entry name from what is being
14230 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14233 const char *name = buf;
14234 const char *real_name;
14241 /* When the linker won't eliminate them, don't output duplicate
14242 TOC entries (this happens on AIX if there is any kind of TOC,
14243 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14245 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
14247 struct toc_hash_struct *h;
14250 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14251 time because GGC is not initialized at that point. */
14252 if (toc_hash_table == NULL)
14253 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
14254 toc_hash_eq, NULL);
14256 h = ggc_alloc (sizeof (*h));
14258 h->key_mode = mode;
14259 h->labelno = labelno;
14261 found = htab_find_slot (toc_hash_table, h, 1);
14262 if (*found == NULL)
14264 else /* This is indeed a duplicate.
14265 Set this label equal to that label. */
14267 fputs ("\t.set ", file);
14268 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14269 fprintf (file, "%d,", labelno);
14270 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14271 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
14277 /* If we're going to put a double constant in the TOC, make sure it's
14278 aligned properly when strict alignment is on. */
14279 if (GET_CODE (x) == CONST_DOUBLE
14280 && STRICT_ALIGNMENT
14281 && GET_MODE_BITSIZE (mode) >= 64
14282 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14283 ASM_OUTPUT_ALIGN (file, 3);
14286 (*targetm.asm_out.internal_label) (file, "LC", labelno);
14288 /* Handle FP constants specially. Note that if we have a minimal
14289 TOC, things we put here aren't actually in the TOC, so we can allow
14291 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14293 REAL_VALUE_TYPE rv;
14296 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14297 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14301 if (TARGET_MINIMAL_TOC)
14302 fputs (DOUBLE_INT_ASM_OP, file);
14304 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14305 k[0] & 0xffffffff, k[1] & 0xffffffff,
14306 k[2] & 0xffffffff, k[3] & 0xffffffff);
14307 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14308 k[0] & 0xffffffff, k[1] & 0xffffffff,
14309 k[2] & 0xffffffff, k[3] & 0xffffffff);
14314 if (TARGET_MINIMAL_TOC)
14315 fputs ("\t.long ", file);
14317 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14318 k[0] & 0xffffffff, k[1] & 0xffffffff,
14319 k[2] & 0xffffffff, k[3] & 0xffffffff);
14320 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14321 k[0] & 0xffffffff, k[1] & 0xffffffff,
14322 k[2] & 0xffffffff, k[3] & 0xffffffff);
14326 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14328 REAL_VALUE_TYPE rv;
14331 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14332 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
14336 if (TARGET_MINIMAL_TOC)
14337 fputs (DOUBLE_INT_ASM_OP, file);
14339 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14340 k[0] & 0xffffffff, k[1] & 0xffffffff);
14341 fprintf (file, "0x%lx%08lx\n",
14342 k[0] & 0xffffffff, k[1] & 0xffffffff);
14347 if (TARGET_MINIMAL_TOC)
14348 fputs ("\t.long ", file);
14350 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14351 k[0] & 0xffffffff, k[1] & 0xffffffff);
14352 fprintf (file, "0x%lx,0x%lx\n",
14353 k[0] & 0xffffffff, k[1] & 0xffffffff);
14357 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14359 REAL_VALUE_TYPE rv;
14362 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14363 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14367 if (TARGET_MINIMAL_TOC)
14368 fputs (DOUBLE_INT_ASM_OP, file);
14370 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14371 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
14376 if (TARGET_MINIMAL_TOC)
14377 fputs ("\t.long ", file);
14379 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14380 fprintf (file, "0x%lx\n", l & 0xffffffff);
14384 else if (GET_MODE (x) == VOIDmode
14385 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
14387 unsigned HOST_WIDE_INT low;
14388 HOST_WIDE_INT high;
14390 if (GET_CODE (x) == CONST_DOUBLE)
14392 low = CONST_DOUBLE_LOW (x);
14393 high = CONST_DOUBLE_HIGH (x);
14396 #if HOST_BITS_PER_WIDE_INT == 32
14399 high = (low & 0x80000000) ? ~0 : 0;
14403 low = INTVAL (x) & 0xffffffff;
14404 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
14408 /* TOC entries are always Pmode-sized, but since this
14409 is a bigendian machine then if we're putting smaller
14410 integer constants in the TOC we have to pad them.
14411 (This is still a win over putting the constants in
14412 a separate constant pool, because then we'd have
14413 to have both a TOC entry _and_ the actual constant.)
14415 For a 32-bit target, CONST_INT values are loaded and shifted
14416 entirely within `low' and can be stored in one TOC entry. */
14418 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
14419 abort ();/* It would be easy to make this work, but it doesn't now. */
14421 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
14423 #if HOST_BITS_PER_WIDE_INT == 32
14424 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14425 POINTER_SIZE, &low, &high, 0);
14428 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14429 high = (HOST_WIDE_INT) low >> 32;
14436 if (TARGET_MINIMAL_TOC)
14437 fputs (DOUBLE_INT_ASM_OP, file);
14439 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14440 (long) high & 0xffffffff, (long) low & 0xffffffff);
14441 fprintf (file, "0x%lx%08lx\n",
14442 (long) high & 0xffffffff, (long) low & 0xffffffff);
14447 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14449 if (TARGET_MINIMAL_TOC)
14450 fputs ("\t.long ", file);
14452 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14453 (long) high & 0xffffffff, (long) low & 0xffffffff);
14454 fprintf (file, "0x%lx,0x%lx\n",
14455 (long) high & 0xffffffff, (long) low & 0xffffffff);
14459 if (TARGET_MINIMAL_TOC)
14460 fputs ("\t.long ", file);
14462 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14463 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
14469 if (GET_CODE (x) == CONST)
14471 if (GET_CODE (XEXP (x, 0)) != PLUS)
14474 base = XEXP (XEXP (x, 0), 0);
14475 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14478 if (GET_CODE (base) == SYMBOL_REF)
14479 name = XSTR (base, 0);
14480 else if (GET_CODE (base) == LABEL_REF)
14481 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14482 else if (GET_CODE (base) == CODE_LABEL)
14483 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14487 real_name = (*targetm.strip_name_encoding) (name);
14488 if (TARGET_MINIMAL_TOC)
14489 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
14492 fprintf (file, "\t.tc %s", real_name);
14495 fprintf (file, ".N%d", - offset);
14497 fprintf (file, ".P%d", offset);
14499 fputs ("[TC],", file);
14502 /* Currently C++ toc references to vtables can be emitted before it
14503 is decided whether the vtable is public or private. If this is
14504 the case, then the linker will eventually complain that there is
14505 a TOC reference to an unknown section. Thus, for vtables only,
14506 we emit the TOC reference to reference the symbol and not the
14508 if (VTABLE_NAME_P (name))
14510 RS6000_OUTPUT_BASENAME (file, name);
14512 fprintf (file, "%d", offset);
14513 else if (offset > 0)
14514 fprintf (file, "+%d", offset);
14517 output_addr_const (file, x);
14521 /* Output an assembler pseudo-op to write an ASCII string of N characters
14522 starting at P to FILE.
14524 On the RS/6000, we have to do this using the .byte operation and
14525 write out special characters outside the quoted string.
14526 Also, the assembler is broken; very long strings are truncated,
14527 so we must artificially break them up early. */
14530 output_ascii (FILE *file, const char *p, int n)
14533 int i, count_string;
14534 const char *for_string = "\t.byte \"";
14535 const char *for_decimal = "\t.byte ";
14536 const char *to_close = NULL;
14539 for (i = 0; i < n; i++)
14542 if (c >= ' ' && c < 0177)
14545 fputs (for_string, file);
14548 /* Write two quotes to get one. */
14556 for_decimal = "\"\n\t.byte ";
14560 if (count_string >= 512)
14562 fputs (to_close, file);
14564 for_string = "\t.byte \"";
14565 for_decimal = "\t.byte ";
14573 fputs (for_decimal, file);
14574 fprintf (file, "%d", c);
14576 for_string = "\n\t.byte \"";
14577 for_decimal = ", ";
14583 /* Now close the string if we have written one. Then end the line. */
14585 fputs (to_close, file);
14588 /* Generate a unique section name for FILENAME for a section type
14589 represented by SECTION_DESC. Output goes into BUF.
14591 SECTION_DESC can be any string, as long as it is different for each
14592 possible section type.
14594 We name the section in the same manner as xlc. The name begins with an
14595 underscore followed by the filename (after stripping any leading directory
14596 names) with the last period replaced by the string SECTION_DESC. If
14597 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14601 rs6000_gen_section_name (char **buf, const char *filename,
14602 const char *section_desc)
14604 const char *q, *after_last_slash, *last_period = 0;
14608 after_last_slash = filename;
14609 for (q = filename; *q; q++)
14612 after_last_slash = q + 1;
14613 else if (*q == '.')
14617 len = strlen (after_last_slash) + strlen (section_desc) + 2;
14618 *buf = (char *) xmalloc (len);
14623 for (q = after_last_slash; *q; q++)
14625 if (q == last_period)
14627 strcpy (p, section_desc);
14628 p += strlen (section_desc);
14632 else if (ISALNUM (*q))
14636 if (last_period == 0)
14637 strcpy (p, section_desc);
14642 /* Emit profile function. */
14645 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
14647 if (TARGET_PROFILE_KERNEL)
14650 if (DEFAULT_ABI == ABI_AIX)
14652 #ifndef NO_PROFILE_COUNTERS
14653 # define NO_PROFILE_COUNTERS 0
14655 if (NO_PROFILE_COUNTERS)
14656 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14660 const char *label_name;
14663 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14664 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14665 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
14667 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14671 else if (DEFAULT_ABI == ABI_DARWIN)
14673 const char *mcount_name = RS6000_MCOUNT;
14674 int caller_addr_regno = LINK_REGISTER_REGNUM;
14676 /* Be conservative and always set this, at least for now. */
14677 current_function_uses_pic_offset_table = 1;
14680 /* For PIC code, set up a stub and collect the caller's address
14681 from r0, which is where the prologue puts it. */
14682 if (MACHOPIC_INDIRECT
14683 && current_function_uses_pic_offset_table)
14684 caller_addr_regno = 0;
14686 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14688 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14692 /* Write function profiler code. */
14695 output_function_profiler (FILE *file, int labelno)
14700 switch (DEFAULT_ABI)
14709 warning ("no profiling of 64-bit code for this ABI");
14712 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14713 fprintf (file, "\tmflr %s\n", reg_names[0]);
14716 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
14717 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14718 reg_names[0], save_lr, reg_names[1]);
14719 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
14720 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
14721 assemble_name (file, buf);
14722 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
14724 else if (flag_pic > 1)
14726 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14727 reg_names[0], save_lr, reg_names[1]);
14728 /* Now, we need to get the address of the label. */
14729 fputs ("\tbl 1f\n\t.long ", file);
14730 assemble_name (file, buf);
14731 fputs ("-.\n1:", file);
14732 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
14733 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
14734 reg_names[0], reg_names[11]);
14735 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14736 reg_names[0], reg_names[0], reg_names[11]);
14740 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
14741 assemble_name (file, buf);
14742 fputs ("@ha\n", file);
14743 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14744 reg_names[0], save_lr, reg_names[1]);
14745 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
14746 assemble_name (file, buf);
14747 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
14750 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
14751 fprintf (file, "\tbl %s%s\n",
14752 RS6000_MCOUNT, flag_pic ? "@plt" : "");
14757 if (!TARGET_PROFILE_KERNEL)
14759 /* Don't do anything, done in output_profile_hook (). */
14766 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14767 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14769 if (cfun->static_chain_decl != NULL)
14771 asm_fprintf (file, "\tstd %s,24(%s)\n",
14772 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14773 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14774 asm_fprintf (file, "\tld %s,24(%s)\n",
14775 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14778 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14785 /* Power4 load update and store update instructions are cracked into a
14786 load or store and an integer insn which are executed in the same cycle.
14787 Branches have their own dispatch slot which does not count against the
14788 GCC issue rate, but it changes the program flow so there are no other
14789 instructions to issue in this cycle. */
14792 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14793 int verbose ATTRIBUTE_UNUSED,
14794 rtx insn, int more)
14796 if (GET_CODE (PATTERN (insn)) == USE
14797 || GET_CODE (PATTERN (insn)) == CLOBBER)
14800 if (rs6000_sched_groups)
14802 if (is_microcoded_insn (insn))
14804 else if (is_cracked_insn (insn))
14805 return more > 2 ? more - 2 : 0;
14811 /* Adjust the cost of a scheduling dependency. Return the new cost of
14812 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14815 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
14817 if (! recog_memoized (insn))
14820 if (REG_NOTE_KIND (link) != 0)
14823 if (REG_NOTE_KIND (link) == 0)
14825 /* Data dependency; DEP_INSN writes a register that INSN reads
14826 some cycles later. */
14828 /* Separate a load from a narrower, dependent store. */
14829 if (rs6000_sched_groups
14830 && GET_CODE (PATTERN (insn)) == SET
14831 && GET_CODE (PATTERN (dep_insn)) == SET
14832 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14833 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14834 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14835 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14838 switch (get_attr_type (insn))
14841 /* Tell the first scheduling pass about the latency between
14842 a mtctr and bctr (and mtlr and br/blr). The first
14843 scheduling pass will not know about this latency since
14844 the mtctr instruction, which has the latency associated
14845 to it, will be generated by reload. */
14846 return TARGET_POWER ? 5 : 4;
14848 /* Leave some extra cycles between a compare and its
14849 dependent branch, to inhibit expensive mispredicts. */
14850 if ((rs6000_cpu_attr == CPU_PPC603
14851 || rs6000_cpu_attr == CPU_PPC604
14852 || rs6000_cpu_attr == CPU_PPC604E
14853 || rs6000_cpu_attr == CPU_PPC620
14854 || rs6000_cpu_attr == CPU_PPC630
14855 || rs6000_cpu_attr == CPU_PPC750
14856 || rs6000_cpu_attr == CPU_PPC7400
14857 || rs6000_cpu_attr == CPU_PPC7450
14858 || rs6000_cpu_attr == CPU_POWER4
14859 || rs6000_cpu_attr == CPU_POWER5)
14860 && recog_memoized (dep_insn)
14861 && (INSN_CODE (dep_insn) >= 0)
14862 && (get_attr_type (dep_insn) == TYPE_CMP
14863 || get_attr_type (dep_insn) == TYPE_COMPARE
14864 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
14865 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14866 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14867 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14868 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14869 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14874 /* Fall out to return default cost. */
14880 /* The function returns a true if INSN is microcoded.
14881 Return false otherwise. */
14884 is_microcoded_insn (rtx insn)
14886 if (!insn || !INSN_P (insn)
14887 || GET_CODE (PATTERN (insn)) == USE
14888 || GET_CODE (PATTERN (insn)) == CLOBBER)
14891 if (rs6000_sched_groups)
14893 enum attr_type type = get_attr_type (insn);
14894 if (type == TYPE_LOAD_EXT_U
14895 || type == TYPE_LOAD_EXT_UX
14896 || type == TYPE_LOAD_UX
14897 || type == TYPE_STORE_UX
14898 || type == TYPE_MFCR)
14905 /* The function returns a nonzero value if INSN can be scheduled only
14906 as the first insn in a dispatch group ("dispatch-slot restricted").
14907 In this case, the returned value indicates how many dispatch slots
14908 the insn occupies (at the beginning of the group).
14909 Return 0 otherwise. */
14912 is_dispatch_slot_restricted (rtx insn)
14914 enum attr_type type;
14916 if (!rs6000_sched_groups)
14920 || insn == NULL_RTX
14921 || GET_CODE (insn) == NOTE
14922 || GET_CODE (PATTERN (insn)) == USE
14923 || GET_CODE (PATTERN (insn)) == CLOBBER)
14926 type = get_attr_type (insn);
14933 case TYPE_DELAYED_CR:
14934 case TYPE_CR_LOGICAL:
14942 if (rs6000_cpu == PROCESSOR_POWER5
14943 && is_cracked_insn (insn))
14949 /* The function returns true if INSN is cracked into 2 instructions
14950 by the processor (and therefore occupies 2 issue slots). */
14953 is_cracked_insn (rtx insn)
14955 if (!insn || !INSN_P (insn)
14956 || GET_CODE (PATTERN (insn)) == USE
14957 || GET_CODE (PATTERN (insn)) == CLOBBER)
14960 if (rs6000_sched_groups)
14962 enum attr_type type = get_attr_type (insn);
14963 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
14964 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
14965 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
14966 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
14967 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
14968 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
14969 || type == TYPE_IDIV || type == TYPE_LDIV
14970 || type == TYPE_INSERT_WORD)
14977 /* The function returns true if INSN can be issued only from
14978 the branch slot. */
14981 is_branch_slot_insn (rtx insn)
14983 if (!insn || !INSN_P (insn)
14984 || GET_CODE (PATTERN (insn)) == USE
14985 || GET_CODE (PATTERN (insn)) == CLOBBER)
14988 if (rs6000_sched_groups)
14990 enum attr_type type = get_attr_type (insn);
14991 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
14999 /* A C statement (sans semicolon) to update the integer scheduling
15000 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15001 INSN earlier, reduce the priority to execute INSN later. Do not
15002 define this macro if you do not need to adjust the scheduling
15003 priorities of insns. */
15006 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15008 /* On machines (like the 750) which have asymmetric integer units,
15009 where one integer unit can do multiply and divides and the other
15010 can't, reduce the priority of multiply/divide so it is scheduled
15011 before other integer operations. */
15014 if (! INSN_P (insn))
15017 if (GET_CODE (PATTERN (insn)) == USE)
15020 switch (rs6000_cpu_attr) {
15022 switch (get_attr_type (insn))
15029 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15030 priority, priority);
15031 if (priority >= 0 && priority < 0x01000000)
15038 if (is_dispatch_slot_restricted (insn)
15039 && reload_completed
15040 && current_sched_info->sched_max_insns_priority
15041 && rs6000_sched_restricted_insns_priority)
15044 /* Prioritize insns that can be dispatched only in the first
15046 if (rs6000_sched_restricted_insns_priority == 1)
15047 /* Attach highest priority to insn. This means that in
15048 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15049 precede 'priority' (critical path) considerations. */
15050 return current_sched_info->sched_max_insns_priority;
15051 else if (rs6000_sched_restricted_insns_priority == 2)
15052 /* Increase priority of insn by a minimal amount. This means that in
15053 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15054 considerations precede dispatch-slot restriction considerations. */
15055 return (priority + 1);
15061 /* Return how many instructions the machine can issue per cycle. */
15064 rs6000_issue_rate (void)
15066 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15067 if (!reload_completed)
15070 switch (rs6000_cpu_attr) {
15071 case CPU_RIOS1: /* ? */
15073 case CPU_PPC601: /* ? */
15096 /* Return how many instructions to look ahead for better insn
15100 rs6000_use_sched_lookahead (void)
15102 if (rs6000_cpu_attr == CPU_PPC8540)
15107 /* Determine is PAT refers to memory. */
15110 is_mem_ref (rtx pat)
15116 if (GET_CODE (pat) == MEM)
15119 /* Recursively process the pattern. */
15120 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15122 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15125 ret |= is_mem_ref (XEXP (pat, i));
15126 else if (fmt[i] == 'E')
15127 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15128 ret |= is_mem_ref (XVECEXP (pat, i, j));
15134 /* Determine if PAT is a PATTERN of a load insn. */
15137 is_load_insn1 (rtx pat)
15139 if (!pat || pat == NULL_RTX)
15142 if (GET_CODE (pat) == SET)
15143 return is_mem_ref (SET_SRC (pat));
15145 if (GET_CODE (pat) == PARALLEL)
15149 for (i = 0; i < XVECLEN (pat, 0); i++)
15150 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15157 /* Determine if INSN loads from memory. */
15160 is_load_insn (rtx insn)
15162 if (!insn || !INSN_P (insn))
15165 if (GET_CODE (insn) == CALL_INSN)
15168 return is_load_insn1 (PATTERN (insn));
15171 /* Determine if PAT is a PATTERN of a store insn. */
15174 is_store_insn1 (rtx pat)
15176 if (!pat || pat == NULL_RTX)
15179 if (GET_CODE (pat) == SET)
15180 return is_mem_ref (SET_DEST (pat));
15182 if (GET_CODE (pat) == PARALLEL)
15186 for (i = 0; i < XVECLEN (pat, 0); i++)
15187 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15194 /* Determine if INSN stores to memory. */
15197 is_store_insn (rtx insn)
15199 if (!insn || !INSN_P (insn))
15202 return is_store_insn1 (PATTERN (insn));
15205 /* Returns whether the dependence between INSN and NEXT is considered
15206 costly by the given target. */
15209 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15212 /* If the flag is not enabled - no dependence is considered costly;
15213 allow all dependent insns in the same group.
15214 This is the most aggressive option. */
15215 if (rs6000_sched_costly_dep == no_dep_costly)
15218 /* If the flag is set to 1 - a dependence is always considered costly;
15219 do not allow dependent instructions in the same group.
15220 This is the most conservative option. */
15221 if (rs6000_sched_costly_dep == all_deps_costly)
15224 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15225 && is_load_insn (next)
15226 && is_store_insn (insn))
15227 /* Prevent load after store in the same group. */
15230 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
15231 && is_load_insn (next)
15232 && is_store_insn (insn)
15233 && (!link || (int) REG_NOTE_KIND (link) == 0))
15234 /* Prevent load after store in the same group if it is a true
15238 /* The flag is set to X; dependences with latency >= X are considered costly,
15239 and will not be scheduled in the same group. */
15240 if (rs6000_sched_costly_dep <= max_dep_latency
15241 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15247 /* Return the next insn after INSN that is found before TAIL is reached,
15248 skipping any "non-active" insns - insns that will not actually occupy
15249 an issue slot. Return NULL_RTX if such an insn is not found. */
15252 get_next_active_insn (rtx insn, rtx tail)
15256 if (!insn || insn == tail)
15259 next_insn = NEXT_INSN (insn);
15262 && next_insn != tail
15263 && (GET_CODE (next_insn) == NOTE
15264 || GET_CODE (PATTERN (next_insn)) == USE
15265 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15267 next_insn = NEXT_INSN (next_insn);
15270 if (!next_insn || next_insn == tail)
15276 /* Return whether the presence of INSN causes a dispatch group termination
15277 of group WHICH_GROUP.
15279 If WHICH_GROUP == current_group, this function will return true if INSN
15280 causes the termination of the current group (i.e, the dispatch group to
15281 which INSN belongs). This means that INSN will be the last insn in the
15282 group it belongs to.
15284 If WHICH_GROUP == previous_group, this function will return true if INSN
15285 causes the termination of the previous group (i.e, the dispatch group that
15286 precedes the group to which INSN belongs). This means that INSN will be
15287 the first insn in the group it belongs to). */
15290 insn_terminates_group_p (rtx insn, enum group_termination which_group)
15292 enum attr_type type;
15297 type = get_attr_type (insn);
15299 if (is_microcoded_insn (insn))
15302 if (which_group == current_group)
15304 if (is_branch_slot_insn (insn))
15308 else if (which_group == previous_group)
15310 if (is_dispatch_slot_restricted (insn))
15318 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15319 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15322 is_costly_group (rtx *group_insns, rtx next_insn)
15327 int issue_rate = rs6000_issue_rate ();
15329 for (i = 0; i < issue_rate; i++)
15331 rtx insn = group_insns[i];
15334 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
15336 rtx next = XEXP (link, 0);
15337 if (next == next_insn)
15339 cost = insn_cost (insn, link, next_insn);
15340 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15349 /* Utility of the function redefine_groups.
15350 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15351 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15352 to keep it "far" (in a separate group) from GROUP_INSNS, following
15353 one of the following schemes, depending on the value of the flag
15354 -minsert_sched_nops = X:
15355 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15356 in order to force NEXT_INSN into a separate group.
15357 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15358 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15359 insertion (has a group just ended, how many vacant issue slots remain in the
15360 last group, and how many dispatch groups were encountered so far). */
15363 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15364 rtx next_insn, bool *group_end, int can_issue_more,
15369 int issue_rate = rs6000_issue_rate ();
15370 bool end = *group_end;
15373 if (next_insn == NULL_RTX)
15374 return can_issue_more;
15376 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15377 return can_issue_more;
15379 force = is_costly_group (group_insns, next_insn);
15381 return can_issue_more;
15383 if (sched_verbose > 6)
15384 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
15385 *group_count ,can_issue_more);
15387 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15390 can_issue_more = 0;
15392 /* Since only a branch can be issued in the last issue_slot, it is
15393 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15394 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15395 in this case the last nop will start a new group and the branch
15396 will be forced to the new group. */
15397 if (can_issue_more && !is_branch_slot_insn (next_insn))
15400 while (can_issue_more > 0)
15403 emit_insn_before (nop, next_insn);
15411 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15413 int n_nops = rs6000_sched_insert_nops;
15415 /* Nops can't be issued from the branch slot, so the effective
15416 issue_rate for nops is 'issue_rate - 1'. */
15417 if (can_issue_more == 0)
15418 can_issue_more = issue_rate;
15420 if (can_issue_more == 0)
15422 can_issue_more = issue_rate - 1;
15425 for (i = 0; i < issue_rate; i++)
15427 group_insns[i] = 0;
15434 emit_insn_before (nop, next_insn);
15435 if (can_issue_more == issue_rate - 1) /* new group begins */
15438 if (can_issue_more == 0)
15440 can_issue_more = issue_rate - 1;
15443 for (i = 0; i < issue_rate; i++)
15445 group_insns[i] = 0;
15451 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15454 /* Is next_insn going to start a new group? */
15457 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15458 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15459 || (can_issue_more < issue_rate &&
15460 insn_terminates_group_p (next_insn, previous_group)));
15461 if (*group_end && end)
15464 if (sched_verbose > 6)
15465 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15466 *group_count, can_issue_more);
15467 return can_issue_more;
15470 return can_issue_more;
15473 /* This function tries to synch the dispatch groups that the compiler "sees"
15474 with the dispatch groups that the processor dispatcher is expected to
15475 form in practice. It tries to achieve this synchronization by forcing the
15476 estimated processor grouping on the compiler (as opposed to the function
15477 'pad_goups' which tries to force the scheduler's grouping on the processor).
15479 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15480 examines the (estimated) dispatch groups that will be formed by the processor
15481 dispatcher. It marks these group boundaries to reflect the estimated
15482 processor grouping, overriding the grouping that the scheduler had marked.
15483 Depending on the value of the flag '-minsert-sched-nops' this function can
15484 force certain insns into separate groups or force a certain distance between
15485 them by inserting nops, for example, if there exists a "costly dependence"
15488 The function estimates the group boundaries that the processor will form as
15489 folllows: It keeps track of how many vacant issue slots are available after
15490 each insn. A subsequent insn will start a new group if one of the following
15492 - no more vacant issue slots remain in the current dispatch group.
15493 - only the last issue slot, which is the branch slot, is vacant, but the next
15494 insn is not a branch.
15495 - only the last 2 or less issue slots, including the branch slot, are vacant,
15496 which means that a cracked insn (which occupies two issue slots) can't be
15497 issued in this group.
15498 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15499 start a new group. */
15502 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15504 rtx insn, next_insn;
15506 int can_issue_more;
15509 int group_count = 0;
15513 issue_rate = rs6000_issue_rate ();
15514 group_insns = alloca (issue_rate * sizeof (rtx));
15515 for (i = 0; i < issue_rate; i++)
15517 group_insns[i] = 0;
15519 can_issue_more = issue_rate;
15521 insn = get_next_active_insn (prev_head_insn, tail);
15524 while (insn != NULL_RTX)
15526 slot = (issue_rate - can_issue_more);
15527 group_insns[slot] = insn;
15529 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15530 if (insn_terminates_group_p (insn, current_group))
15531 can_issue_more = 0;
15533 next_insn = get_next_active_insn (insn, tail);
15534 if (next_insn == NULL_RTX)
15535 return group_count + 1;
15537 /* Is next_insn going to start a new group? */
15539 = (can_issue_more == 0
15540 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15541 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15542 || (can_issue_more < issue_rate &&
15543 insn_terminates_group_p (next_insn, previous_group)));
15545 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
15546 next_insn, &group_end, can_issue_more,
15552 can_issue_more = 0;
15553 for (i = 0; i < issue_rate; i++)
15555 group_insns[i] = 0;
15559 if (GET_MODE (next_insn) == TImode && can_issue_more)
15560 PUT_MODE (next_insn, VOIDmode);
15561 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
15562 PUT_MODE (next_insn, TImode);
15565 if (can_issue_more == 0)
15566 can_issue_more = issue_rate;
15569 return group_count;
15572 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15573 dispatch group boundaries that the scheduler had marked. Pad with nops
15574 any dispatch groups which have vacant issue slots, in order to force the
15575 scheduler's grouping on the processor dispatcher. The function
15576 returns the number of dispatch groups found. */
15579 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15581 rtx insn, next_insn;
15584 int can_issue_more;
15586 int group_count = 0;
15588 /* Initialize issue_rate. */
15589 issue_rate = rs6000_issue_rate ();
15590 can_issue_more = issue_rate;
15592 insn = get_next_active_insn (prev_head_insn, tail);
15593 next_insn = get_next_active_insn (insn, tail);
15595 while (insn != NULL_RTX)
15598 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15600 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15602 if (next_insn == NULL_RTX)
15607 /* If the scheduler had marked group termination at this location
15608 (between insn and next_indn), and neither insn nor next_insn will
15609 force group termination, pad the group with nops to force group
15612 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15613 && !insn_terminates_group_p (insn, current_group)
15614 && !insn_terminates_group_p (next_insn, previous_group))
15616 if (!is_branch_slot_insn (next_insn))
15619 while (can_issue_more)
15622 emit_insn_before (nop, next_insn);
15627 can_issue_more = issue_rate;
15632 next_insn = get_next_active_insn (insn, tail);
15635 return group_count;
15638 /* The following function is called at the end of scheduling BB.
15639 After reload, it inserts nops at insn group bundling. */
15642 rs6000_sched_finish (FILE *dump, int sched_verbose)
15647 fprintf (dump, "=== Finishing schedule.\n");
15649 if (reload_completed && rs6000_sched_groups)
15651 if (rs6000_sched_insert_nops == sched_finish_none)
15654 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
15655 n_groups = pad_groups (dump, sched_verbose,
15656 current_sched_info->prev_head,
15657 current_sched_info->next_tail);
15659 n_groups = redefine_groups (dump, sched_verbose,
15660 current_sched_info->prev_head,
15661 current_sched_info->next_tail);
15663 if (sched_verbose >= 6)
15665 fprintf (dump, "ngroups = %d\n", n_groups);
15666 print_rtl (dump, current_sched_info->prev_head);
15667 fprintf (dump, "Done finish_sched\n");
15672 /* Length in units of the trampoline for entering a nested function. */
15675 rs6000_trampoline_size (void)
15679 switch (DEFAULT_ABI)
15685 ret = (TARGET_32BIT) ? 12 : 24;
15690 ret = (TARGET_32BIT) ? 40 : 48;
15697 /* Emit RTL insns to initialize the variable parts of a trampoline.
15698 FNADDR is an RTX for the address of the function's pure code.
15699 CXT is an RTX for the static chain value for the function. */
15702 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
15704 enum machine_mode pmode = Pmode;
15705 int regsize = (TARGET_32BIT) ? 4 : 8;
15706 rtx ctx_reg = force_reg (pmode, cxt);
15708 switch (DEFAULT_ABI)
15713 /* Macros to shorten the code expansions below. */
15714 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
15715 #define MEM_PLUS(addr,offset) \
15716 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
15718 /* Under AIX, just build the 3 word function descriptor */
15721 rtx fn_reg = gen_reg_rtx (pmode);
15722 rtx toc_reg = gen_reg_rtx (pmode);
15723 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
15724 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
15725 emit_move_insn (MEM_DEREF (addr), fn_reg);
15726 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15727 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15731 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15734 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
15735 FALSE, VOIDmode, 4,
15737 GEN_INT (rs6000_trampoline_size ()), SImode,
15747 /* Table of valid machine attributes. */
15749 const struct attribute_spec rs6000_attribute_table[] =
15751 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
15752 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
15753 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15754 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15755 #ifdef SUBTARGET_ATTRIBUTE_TABLE
15756 SUBTARGET_ATTRIBUTE_TABLE,
15758 { NULL, 0, 0, false, false, false, NULL }
15761 /* Handle the "altivec" attribute. The attribute may have
15762 arguments as follows:
15764 __attribute__((altivec(vector__)))
15765 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15766 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15768 and may appear more than once (e.g., 'vector bool char') in a
15769 given declaration. */
15772 rs6000_handle_altivec_attribute (tree *node,
15773 tree name ATTRIBUTE_UNUSED,
15775 int flags ATTRIBUTE_UNUSED,
15776 bool *no_add_attrs)
15778 tree type = *node, result = NULL_TREE;
15779 enum machine_mode mode;
15782 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15783 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15784 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
15787 while (POINTER_TYPE_P (type)
15788 || TREE_CODE (type) == FUNCTION_TYPE
15789 || TREE_CODE (type) == METHOD_TYPE
15790 || TREE_CODE (type) == ARRAY_TYPE)
15791 type = TREE_TYPE (type);
15793 mode = TYPE_MODE (type);
15795 /* Check for invalid AltiVec type qualifiers. */
15796 if (type == long_unsigned_type_node || type == long_integer_type_node)
15799 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15800 else if (rs6000_warn_altivec_long)
15801 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15803 else if (type == long_long_unsigned_type_node
15804 || type == long_long_integer_type_node)
15805 error ("use of %<long long%> in AltiVec types is invalid");
15806 else if (type == double_type_node)
15807 error ("use of %<double%> in AltiVec types is invalid");
15808 else if (type == long_double_type_node)
15809 error ("use of %<long double%> in AltiVec types is invalid");
15810 else if (type == boolean_type_node)
15811 error ("use of boolean types in AltiVec types is invalid");
15812 else if (TREE_CODE (type) == COMPLEX_TYPE)
15813 error ("use of %<complex%> in AltiVec types is invalid");
15815 switch (altivec_type)
15818 unsigned_p = TYPE_UNSIGNED (type);
15822 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15825 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15828 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15830 case SFmode: result = V4SF_type_node; break;
15831 /* If the user says 'vector int bool', we may be handed the 'bool'
15832 attribute _before_ the 'vector' attribute, and so select the
15833 proper type in the 'b' case below. */
15834 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15842 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15843 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15844 case QImode: case V16QImode: result = bool_V16QI_type_node;
15851 case V8HImode: result = pixel_V8HI_type_node;
15857 if (result && result != type && TYPE_READONLY (type))
15858 result = build_qualified_type (result, TYPE_QUAL_CONST);
15860 *no_add_attrs = true; /* No need to hang on to the attribute. */
15863 *node = reconstruct_complex_type (*node, result);
15868 /* AltiVec defines four built-in scalar types that serve as vector
15869 elements; we must teach the compiler how to mangle them. */
15871 static const char *
15872 rs6000_mangle_fundamental_type (tree type)
15874 if (type == bool_char_type_node) return "U6__boolc";
15875 if (type == bool_short_type_node) return "U6__bools";
15876 if (type == pixel_type_node) return "u7__pixel";
15877 if (type == bool_int_type_node) return "U6__booli";
15879 /* For all other types, use normal C++ mangling. */
15883 /* Handle a "longcall" or "shortcall" attribute; arguments as in
15884 struct attribute_spec.handler. */
15887 rs6000_handle_longcall_attribute (tree *node, tree name,
15888 tree args ATTRIBUTE_UNUSED,
15889 int flags ATTRIBUTE_UNUSED,
15890 bool *no_add_attrs)
15892 if (TREE_CODE (*node) != FUNCTION_TYPE
15893 && TREE_CODE (*node) != FIELD_DECL
15894 && TREE_CODE (*node) != TYPE_DECL)
15896 warning ("%qs attribute only applies to functions",
15897 IDENTIFIER_POINTER (name));
15898 *no_add_attrs = true;
15904 /* Set longcall attributes on all functions declared when
15905 rs6000_default_long_calls is true. */
15907 rs6000_set_default_type_attributes (tree type)
15909 if (rs6000_default_long_calls
15910 && (TREE_CODE (type) == FUNCTION_TYPE
15911 || TREE_CODE (type) == METHOD_TYPE))
15912 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15914 TYPE_ATTRIBUTES (type));
15917 /* Return a reference suitable for calling a function with the
15918 longcall attribute. */
15921 rs6000_longcall_ref (rtx call_ref)
15923 const char *call_name;
15926 if (GET_CODE (call_ref) != SYMBOL_REF)
15929 /* System V adds '.' to the internal name, so skip them. */
15930 call_name = XSTR (call_ref, 0);
15931 if (*call_name == '.')
15933 while (*call_name == '.')
15936 node = get_identifier (call_name);
15937 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15940 return force_reg (Pmode, call_ref);
15943 #ifdef USING_ELFOS_H
15945 /* A C statement or statements to switch to the appropriate section
15946 for output of RTX in mode MODE. You can assume that RTX is some
15947 kind of constant in RTL. The argument MODE is redundant except in
15948 the case of a `const_int' rtx. Select the section by calling
15949 `text_section' or one of the alternatives for other sections.
15951 Do not define this macro if you put all constants in the read-only
15955 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
15956 unsigned HOST_WIDE_INT align)
15958 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
15961 default_elf_select_rtx_section (mode, x, align);
15964 /* A C statement or statements to switch to the appropriate
15965 section for output of DECL. DECL is either a `VAR_DECL' node
15966 or a constant of some sort. RELOC indicates whether forming
15967 the initial value of DECL requires link-time relocations. */
15970 rs6000_elf_select_section (tree decl, int reloc,
15971 unsigned HOST_WIDE_INT align)
15973 /* Pretend that we're always building for a shared library when
15974 ABI_AIX, because otherwise we end up with dynamic relocations
15975 in read-only sections. This happens for function pointers,
15976 references to vtables in typeinfo, and probably other cases. */
15977 default_elf_select_section_1 (decl, reloc, align,
15978 flag_pic || DEFAULT_ABI == ABI_AIX);
15981 /* A C statement to build up a unique section name, expressed as a
15982 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
15983 RELOC indicates whether the initial value of EXP requires
15984 link-time relocations. If you do not define this macro, GCC will use
15985 the symbol name prefixed by `.' as the section name. Note - this
15986 macro can now be called for uninitialized data items as well as
15987 initialized data and functions. */
15990 rs6000_elf_unique_section (tree decl, int reloc)
15992 /* As above, pretend that we're always building for a shared library
15993 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
15994 default_unique_section_1 (decl, reloc,
15995 flag_pic || DEFAULT_ABI == ABI_AIX);
15998 /* For a SYMBOL_REF, set generic flags and then perform some
15999 target-specific processing.
16001 When the AIX ABI is requested on a non-AIX system, replace the
16002 function name with the real name (with a leading .) rather than the
16003 function descriptor name. This saves a lot of overriding code to
16004 read the prefixes. */
16007 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16009 default_encode_section_info (decl, rtl, first);
16012 && TREE_CODE (decl) == FUNCTION_DECL
16014 && DEFAULT_ABI == ABI_AIX)
16016 rtx sym_ref = XEXP (rtl, 0);
16017 size_t len = strlen (XSTR (sym_ref, 0));
16018 char *str = alloca (len + 2);
16020 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16021 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16026 rs6000_elf_in_small_data_p (tree decl)
16028 if (rs6000_sdata == SDATA_NONE)
16031 /* We want to merge strings, so we never consider them small data. */
16032 if (TREE_CODE (decl) == STRING_CST)
16035 /* Functions are never in the small data area. */
16036 if (TREE_CODE (decl) == FUNCTION_DECL)
16039 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16041 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16042 if (strcmp (section, ".sdata") == 0
16043 || strcmp (section, ".sdata2") == 0
16044 || strcmp (section, ".sbss") == 0
16045 || strcmp (section, ".sbss2") == 0
16046 || strcmp (section, ".PPC.EMB.sdata0") == 0
16047 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16052 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16055 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16056 /* If it's not public, and we're not going to reference it there,
16057 there's no need to put it in the small data section. */
16058 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16065 #endif /* USING_ELFOS_H */
16068 /* Return a REG that occurs in ADDR with coefficient 1.
16069 ADDR can be effectively incremented by incrementing REG.
16071 r0 is special and we must not select it as an address
16072 register by this routine since our caller will try to
16073 increment the returned register via an "la" instruction. */
16076 find_addr_reg (rtx addr)
16078 while (GET_CODE (addr) == PLUS)
16080 if (GET_CODE (XEXP (addr, 0)) == REG
16081 && REGNO (XEXP (addr, 0)) != 0)
16082 addr = XEXP (addr, 0);
16083 else if (GET_CODE (XEXP (addr, 1)) == REG
16084 && REGNO (XEXP (addr, 1)) != 0)
16085 addr = XEXP (addr, 1);
16086 else if (CONSTANT_P (XEXP (addr, 0)))
16087 addr = XEXP (addr, 1);
16088 else if (CONSTANT_P (XEXP (addr, 1)))
16089 addr = XEXP (addr, 0);
16093 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16099 rs6000_fatal_bad_address (rtx op)
16101 fatal_insn ("bad address", op);
16106 static tree branch_island_list = 0;
16108 /* Remember to generate a branch island for far calls to the given
16112 add_compiler_branch_island (tree label_name, tree function_name,
16115 tree branch_island = build_tree_list (function_name, label_name);
16116 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16117 TREE_CHAIN (branch_island) = branch_island_list;
16118 branch_island_list = branch_island;
16121 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16122 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16123 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16124 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16126 /* Generate far-jump branch islands for everything on the
16127 branch_island_list. Invoked immediately after the last instruction
16128 of the epilogue has been emitted; the branch-islands must be
16129 appended to, and contiguous with, the function body. Mach-O stubs
16130 are generated in machopic_output_stub(). */
16133 macho_branch_islands (void)
16136 tree branch_island;
16138 for (branch_island = branch_island_list;
16140 branch_island = TREE_CHAIN (branch_island))
16142 const char *label =
16143 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16145 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16146 char name_buf[512];
16147 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16148 if (name[0] == '*' || name[0] == '&')
16149 strcpy (name_buf, name+1);
16153 strcpy (name_buf+1, name);
16155 strcpy (tmp_buf, "\n");
16156 strcat (tmp_buf, label);
16157 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16158 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16159 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16160 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16163 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16164 strcat (tmp_buf, label);
16165 strcat (tmp_buf, "_pic\n");
16166 strcat (tmp_buf, label);
16167 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16169 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16170 strcat (tmp_buf, name_buf);
16171 strcat (tmp_buf, " - ");
16172 strcat (tmp_buf, label);
16173 strcat (tmp_buf, "_pic)\n");
16175 strcat (tmp_buf, "\tmtlr r0\n");
16177 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16178 strcat (tmp_buf, name_buf);
16179 strcat (tmp_buf, " - ");
16180 strcat (tmp_buf, label);
16181 strcat (tmp_buf, "_pic)\n");
16183 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16187 strcat (tmp_buf, ":\nlis r12,hi16(");
16188 strcat (tmp_buf, name_buf);
16189 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16190 strcat (tmp_buf, name_buf);
16191 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16193 output_asm_insn (tmp_buf, 0);
16194 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16195 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16196 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16197 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16200 branch_island_list = 0;
16203 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16204 already there or not. */
16207 no_previous_def (tree function_name)
16209 tree branch_island;
16210 for (branch_island = branch_island_list;
16212 branch_island = TREE_CHAIN (branch_island))
16213 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16218 /* GET_PREV_LABEL gets the label name from the previous definition of
16222 get_prev_label (tree function_name)
16224 tree branch_island;
16225 for (branch_island = branch_island_list;
16227 branch_island = TREE_CHAIN (branch_island))
16228 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16229 return BRANCH_ISLAND_LABEL_NAME (branch_island);
16233 /* INSN is either a function call or a millicode call. It may have an
16234 unconditional jump in its delay slot.
16236 CALL_DEST is the routine we are calling. */
16239 output_call (rtx insn, rtx *operands, int dest_operand_number,
16240 int cookie_operand_number)
16242 static char buf[256];
16243 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16244 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
16247 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
16249 if (no_previous_def (funname))
16251 int line_number = 0;
16252 rtx label_rtx = gen_label_rtx ();
16253 char *label_buf, temp_buf[256];
16254 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16255 CODE_LABEL_NUMBER (label_rtx));
16256 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16257 labelname = get_identifier (label_buf);
16258 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16260 line_number = NOTE_LINE_NUMBER (insn);
16261 add_compiler_branch_island (labelname, funname, line_number);
16264 labelname = get_prev_label (funname);
16266 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16267 instruction will reach 'foo', otherwise link as 'bl L42'".
16268 "L42" should be a 'branch island', that will do a far jump to
16269 'foo'. Branch islands are generated in
16270 macho_branch_islands(). */
16271 sprintf (buf, "jbsr %%z%d,%.246s",
16272 dest_operand_number, IDENTIFIER_POINTER (labelname));
16275 sprintf (buf, "bl %%z%d", dest_operand_number);
16279 /* Generate PIC and indirect symbol stubs. */
16282 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16284 unsigned int length;
16285 char *symbol_name, *lazy_ptr_name;
16286 char *local_label_0;
16287 static int label = 0;
16289 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16290 symb = (*targetm.strip_name_encoding) (symb);
16293 length = strlen (symb);
16294 symbol_name = alloca (length + 32);
16295 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16297 lazy_ptr_name = alloca (length + 32);
16298 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16301 machopic_picsymbol_stub1_section ();
16303 machopic_symbol_stub1_section ();
16307 fprintf (file, "\t.align 5\n");
16309 fprintf (file, "%s:\n", stub);
16310 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16313 local_label_0 = alloca (sizeof ("\"L0000000000$spb\""));
16314 sprintf (local_label_0, "\"L%011d$spb\"", label);
16316 fprintf (file, "\tmflr r0\n");
16317 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16318 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16319 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16320 lazy_ptr_name, local_label_0);
16321 fprintf (file, "\tmtlr r0\n");
16322 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16323 (TARGET_64BIT ? "ldu" : "lwzu"),
16324 lazy_ptr_name, local_label_0);
16325 fprintf (file, "\tmtctr r12\n");
16326 fprintf (file, "\tbctr\n");
16330 fprintf (file, "\t.align 4\n");
16332 fprintf (file, "%s:\n", stub);
16333 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16335 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
16336 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16337 (TARGET_64BIT ? "ldu" : "lwzu"),
16339 fprintf (file, "\tmtctr r12\n");
16340 fprintf (file, "\tbctr\n");
16343 machopic_lazy_symbol_ptr_section ();
16344 fprintf (file, "%s:\n", lazy_ptr_name);
16345 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16346 fprintf (file, "%sdyld_stub_binding_helper\n",
16347 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
16350 /* Legitimize PIC addresses. If the address is already
16351 position-independent, we return ORIG. Newly generated
16352 position-independent addresses go into a reg. This is REG if non
16353 zero, otherwise we allocate register(s) as necessary. */
16355 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
16358 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
16363 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16364 reg = gen_reg_rtx (Pmode);
16366 if (GET_CODE (orig) == CONST)
16368 if (GET_CODE (XEXP (orig, 0)) == PLUS
16369 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16372 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16374 /* Use a different reg for the intermediate value, as
16375 it will be marked UNCHANGING. */
16376 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16379 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16382 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16388 if (GET_CODE (offset) == CONST_INT)
16390 if (SMALL_INT (offset))
16391 return plus_constant (base, INTVAL (offset));
16392 else if (! reload_in_progress && ! reload_completed)
16393 offset = force_reg (Pmode, offset);
16396 rtx mem = force_const_mem (Pmode, orig);
16397 return machopic_legitimize_pic_address (mem, Pmode, reg);
16400 return gen_rtx_PLUS (Pmode, base, offset);
16403 /* Fall back on generic machopic code. */
16404 return machopic_legitimize_pic_address (orig, mode, reg);
16407 /* This is just a placeholder to make linking work without having to
16408 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16409 ever needed for Darwin (not too likely!) this would have to get a
16410 real definition. */
16417 /* Output a .machine directive for the Darwin assembler, and call
16418 the generic start_file routine. */
16421 rs6000_darwin_file_start (void)
16423 static const struct
16429 { "ppc64", "ppc64", MASK_64BIT },
16430 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16431 { "power4", "ppc970", 0 },
16432 { "G5", "ppc970", 0 },
16433 { "7450", "ppc7450", 0 },
16434 { "7400", "ppc7400", MASK_ALTIVEC },
16435 { "G4", "ppc7400", 0 },
16436 { "750", "ppc750", 0 },
16437 { "740", "ppc750", 0 },
16438 { "G3", "ppc750", 0 },
16439 { "604e", "ppc604e", 0 },
16440 { "604", "ppc604", 0 },
16441 { "603e", "ppc603", 0 },
16442 { "603", "ppc603", 0 },
16443 { "601", "ppc601", 0 },
16444 { NULL, "ppc", 0 } };
16445 const char *cpu_id = "";
16448 rs6000_file_start ();
16450 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16451 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16452 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16453 && rs6000_select[i].string[0] != '\0')
16454 cpu_id = rs6000_select[i].string;
16456 /* Look through the mapping array. Pick the first name that either
16457 matches the argument, has a bit set in IF_SET that is also set
16458 in the target flags, or has a NULL name. */
16461 while (mapping[i].arg != NULL
16462 && strcmp (mapping[i].arg, cpu_id) != 0
16463 && (mapping[i].if_set & target_flags) == 0)
16466 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16469 #endif /* TARGET_MACHO */
16472 static unsigned int
16473 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
16475 return default_section_type_flags_1 (decl, name, reloc,
16476 flag_pic || DEFAULT_ABI == ABI_AIX);
16479 /* Record an element in the table of global constructors. SYMBOL is
16480 a SYMBOL_REF of the function to be called; PRIORITY is a number
16481 between 0 and MAX_INIT_PRIORITY.
16483 This differs from default_named_section_asm_out_constructor in
16484 that we have special handling for -mrelocatable. */
16487 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
16489 const char *section = ".ctors";
16492 if (priority != DEFAULT_INIT_PRIORITY)
16494 sprintf (buf, ".ctors.%.5u",
16495 /* Invert the numbering so the linker puts us in the proper
16496 order; constructors are run from right to left, and the
16497 linker sorts in increasing order. */
16498 MAX_INIT_PRIORITY - priority);
16502 named_section_flags (section, SECTION_WRITE);
16503 assemble_align (POINTER_SIZE);
16505 if (TARGET_RELOCATABLE)
16507 fputs ("\t.long (", asm_out_file);
16508 output_addr_const (asm_out_file, symbol);
16509 fputs (")@fixup\n", asm_out_file);
16512 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16516 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
16518 const char *section = ".dtors";
16521 if (priority != DEFAULT_INIT_PRIORITY)
16523 sprintf (buf, ".dtors.%.5u",
16524 /* Invert the numbering so the linker puts us in the proper
16525 order; constructors are run from right to left, and the
16526 linker sorts in increasing order. */
16527 MAX_INIT_PRIORITY - priority);
16531 named_section_flags (section, SECTION_WRITE);
16532 assemble_align (POINTER_SIZE);
16534 if (TARGET_RELOCATABLE)
16536 fputs ("\t.long (", asm_out_file);
16537 output_addr_const (asm_out_file, symbol);
16538 fputs (")@fixup\n", asm_out_file);
16541 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16545 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
16549 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16550 ASM_OUTPUT_LABEL (file, name);
16551 fputs (DOUBLE_INT_ASM_OP, file);
16552 rs6000_output_function_entry (file, name);
16553 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16556 fputs ("\t.size\t", file);
16557 assemble_name (file, name);
16558 fputs (",24\n\t.type\t.", file);
16559 assemble_name (file, name);
16560 fputs (",@function\n", file);
16561 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16563 fputs ("\t.globl\t.", file);
16564 assemble_name (file, name);
16569 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16570 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16571 rs6000_output_function_entry (file, name);
16572 fputs (":\n", file);
16576 if (TARGET_RELOCATABLE
16577 && (get_pool_size () != 0 || current_function_profile)
16582 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16584 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16585 fprintf (file, "\t.long ");
16586 assemble_name (file, buf);
16588 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16589 assemble_name (file, buf);
16593 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16594 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16596 if (DEFAULT_ABI == ABI_AIX)
16598 const char *desc_name, *orig_name;
16600 orig_name = (*targetm.strip_name_encoding) (name);
16601 desc_name = orig_name;
16602 while (*desc_name == '.')
16605 if (TREE_PUBLIC (decl))
16606 fprintf (file, "\t.globl %s\n", desc_name);
16608 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16609 fprintf (file, "%s:\n", desc_name);
16610 fprintf (file, "\t.long %s\n", orig_name);
16611 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16612 if (DEFAULT_ABI == ABI_AIX)
16613 fputs ("\t.long 0\n", file);
16614 fprintf (file, "\t.previous\n");
16616 ASM_OUTPUT_LABEL (file, name);
16622 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
16624 fputs (GLOBAL_ASM_OP, stream);
16625 RS6000_OUTPUT_BASENAME (stream, name);
16626 putc ('\n', stream);
16630 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16631 tree decl ATTRIBUTE_UNUSED)
16634 static const char * const suffix[3] = { "PR", "RO", "RW" };
16636 if (flags & SECTION_CODE)
16638 else if (flags & SECTION_WRITE)
16643 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
16644 (flags & SECTION_CODE) ? "." : "",
16645 name, suffix[smclass], flags & SECTION_ENTSIZE);
16649 rs6000_xcoff_select_section (tree decl, int reloc,
16650 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16652 if (decl_readonly_section_1 (decl, reloc, 1))
16654 if (TREE_PUBLIC (decl))
16655 read_only_data_section ();
16657 read_only_private_data_section ();
16661 if (TREE_PUBLIC (decl))
16664 private_data_section ();
16669 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
16673 /* Use select_section for private and uninitialized data. */
16674 if (!TREE_PUBLIC (decl)
16675 || DECL_COMMON (decl)
16676 || DECL_INITIAL (decl) == NULL_TREE
16677 || DECL_INITIAL (decl) == error_mark_node
16678 || (flag_zero_initialized_in_bss
16679 && initializer_zerop (DECL_INITIAL (decl))))
16682 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16683 name = (*targetm.strip_name_encoding) (name);
16684 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
16687 /* Select section for constant in constant pool.
16689 On RS/6000, all constants are in the private read-only data area.
16690 However, if this is being placed in the TOC it must be output as a
16694 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
16695 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16697 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16700 read_only_private_data_section ();
16703 /* Remove any trailing [DS] or the like from the symbol name. */
16705 static const char *
16706 rs6000_xcoff_strip_name_encoding (const char *name)
16711 len = strlen (name);
16712 if (name[len - 1] == ']')
16713 return ggc_alloc_string (name, len - 4);
16718 /* Section attributes. AIX is always PIC. */
16720 static unsigned int
16721 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
16723 unsigned int align;
16724 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16726 /* Align to at least UNIT size. */
16727 if (flags & SECTION_CODE)
16728 align = MIN_UNITS_PER_WORD;
16730 /* Increase alignment of large objects if not already stricter. */
16731 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16732 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16733 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16735 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
16738 /* Output at beginning of assembler file.
16740 Initialize the section names for the RS/6000 at this point.
16742 Specify filename, including full path, to assembler.
16744 We want to go into the TOC section so at least one .toc will be emitted.
16745 Also, in order to output proper .bs/.es pairs, we need at least one static
16746 [RW] section emitted.
16748 Finally, declare mcount when profiling to make the assembler happy. */
16751 rs6000_xcoff_file_start (void)
16753 rs6000_gen_section_name (&xcoff_bss_section_name,
16754 main_input_filename, ".bss_");
16755 rs6000_gen_section_name (&xcoff_private_data_section_name,
16756 main_input_filename, ".rw_");
16757 rs6000_gen_section_name (&xcoff_read_only_section_name,
16758 main_input_filename, ".ro_");
16760 fputs ("\t.file\t", asm_out_file);
16761 output_quoted_string (asm_out_file, main_input_filename);
16762 fputc ('\n', asm_out_file);
16763 if (write_symbols != NO_DEBUG)
16764 private_data_section ();
16767 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16768 rs6000_file_start ();
16771 /* Output at end of assembler file.
16772 On the RS/6000, referencing data should automatically pull in text. */
16775 rs6000_xcoff_file_end (void)
16778 fputs ("_section_.text:\n", asm_out_file);
16780 fputs (TARGET_32BIT
16781 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16784 #endif /* TARGET_XCOFF */
16787 /* Cross-module name binding. Darwin does not support overriding
16788 functions at dynamic-link time. */
16791 rs6000_binds_local_p (tree decl)
16793 return default_binds_local_p_1 (decl, 0);
16797 /* Compute a (partial) cost for rtx X. Return true if the complete
16798 cost has been computed, and false if subexpressions should be
16799 scanned. In either case, *TOTAL contains the cost result. */
16802 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
16804 enum machine_mode mode = GET_MODE (x);
16808 /* On the RS/6000, if it is valid in the insn, it is free. */
16810 if (((outer_code == SET
16811 || outer_code == PLUS
16812 || outer_code == MINUS)
16813 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16814 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
16815 || (outer_code == AND
16816 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16817 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16818 mode == SImode ? 'L' : 'J'))
16819 || mask_operand (x, VOIDmode)))
16820 || ((outer_code == IOR || outer_code == XOR)
16821 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16822 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16823 mode == SImode ? 'L' : 'J'))))
16824 || outer_code == ASHIFT
16825 || outer_code == ASHIFTRT
16826 || outer_code == LSHIFTRT
16827 || outer_code == ROTATE
16828 || outer_code == ROTATERT
16829 || outer_code == ZERO_EXTRACT
16830 || (outer_code == MULT
16831 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16832 || ((outer_code == DIV || outer_code == UDIV
16833 || outer_code == MOD || outer_code == UMOD)
16834 && exact_log2 (INTVAL (x)) >= 0)
16835 || (outer_code == COMPARE
16836 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16837 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16838 || (outer_code == EQ
16839 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16840 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16841 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16842 mode == SImode ? 'L' : 'J'))))
16843 || (outer_code == GTU
16844 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16845 || (outer_code == LTU
16846 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
16851 else if ((outer_code == PLUS
16852 && reg_or_add_cint64_operand (x, VOIDmode))
16853 || (outer_code == MINUS
16854 && reg_or_sub_cint64_operand (x, VOIDmode))
16855 || ((outer_code == SET
16856 || outer_code == IOR
16857 || outer_code == XOR)
16859 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16861 *total = COSTS_N_INSNS (1);
16868 && ((outer_code == AND
16869 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16870 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
16871 || mask64_operand (x, DImode)))
16872 || ((outer_code == IOR || outer_code == XOR)
16873 && CONST_DOUBLE_HIGH (x) == 0
16874 && (CONST_DOUBLE_LOW (x)
16875 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16880 else if (mode == DImode
16881 && (outer_code == SET
16882 || outer_code == IOR
16883 || outer_code == XOR)
16884 && CONST_DOUBLE_HIGH (x) == 0)
16886 *total = COSTS_N_INSNS (1);
16895 /* When optimizing for size, MEM should be slightly more expensive
16896 than generating address, e.g., (plus (reg) (const)).
16897 L1 cache latency is about two instructions. */
16898 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
16906 if (mode == DFmode)
16908 if (GET_CODE (XEXP (x, 0)) == MULT)
16910 /* FNMA accounted in outer NEG. */
16911 if (outer_code == NEG)
16912 *total = rs6000_cost->dmul - rs6000_cost->fp;
16914 *total = rs6000_cost->dmul;
16917 *total = rs6000_cost->fp;
16919 else if (mode == SFmode)
16921 /* FNMA accounted in outer NEG. */
16922 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16925 *total = rs6000_cost->fp;
16927 else if (GET_CODE (XEXP (x, 0)) == MULT)
16929 /* The rs6000 doesn't have shift-and-add instructions. */
16930 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16931 *total += COSTS_N_INSNS (1);
16934 *total = COSTS_N_INSNS (1);
16938 if (mode == DFmode)
16940 if (GET_CODE (XEXP (x, 0)) == MULT)
16942 /* FNMA accounted in outer NEG. */
16943 if (outer_code == NEG)
16946 *total = rs6000_cost->dmul;
16949 *total = rs6000_cost->fp;
16951 else if (mode == SFmode)
16953 /* FNMA accounted in outer NEG. */
16954 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16957 *total = rs6000_cost->fp;
16959 else if (GET_CODE (XEXP (x, 0)) == MULT)
16961 /* The rs6000 doesn't have shift-and-sub instructions. */
16962 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
16963 *total += COSTS_N_INSNS (1);
16966 *total = COSTS_N_INSNS (1);
16970 if (GET_CODE (XEXP (x, 1)) == CONST_INT
16971 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
16973 if (INTVAL (XEXP (x, 1)) >= -256
16974 && INTVAL (XEXP (x, 1)) <= 255)
16975 *total = rs6000_cost->mulsi_const9;
16977 *total = rs6000_cost->mulsi_const;
16979 /* FMA accounted in outer PLUS/MINUS. */
16980 else if ((mode == DFmode || mode == SFmode)
16981 && (outer_code == PLUS || outer_code == MINUS))
16983 else if (mode == DFmode)
16984 *total = rs6000_cost->dmul;
16985 else if (mode == SFmode)
16986 *total = rs6000_cost->fp;
16987 else if (mode == DImode)
16988 *total = rs6000_cost->muldi;
16990 *total = rs6000_cost->mulsi;
16995 if (FLOAT_MODE_P (mode))
16997 *total = mode == DFmode ? rs6000_cost->ddiv
16998 : rs6000_cost->sdiv;
17005 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17006 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17008 if (code == DIV || code == MOD)
17010 *total = COSTS_N_INSNS (2);
17013 *total = COSTS_N_INSNS (1);
17017 if (GET_MODE (XEXP (x, 1)) == DImode)
17018 *total = rs6000_cost->divdi;
17020 *total = rs6000_cost->divsi;
17022 /* Add in shift and subtract for MOD. */
17023 if (code == MOD || code == UMOD)
17024 *total += COSTS_N_INSNS (2);
17028 *total = COSTS_N_INSNS (4);
17032 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17043 *total = COSTS_N_INSNS (1);
17051 /* Handle mul_highpart. */
17052 if (outer_code == TRUNCATE
17053 && GET_CODE (XEXP (x, 0)) == MULT)
17055 if (mode == DImode)
17056 *total = rs6000_cost->muldi;
17058 *total = rs6000_cost->mulsi;
17061 else if (outer_code == AND)
17064 *total = COSTS_N_INSNS (1);
17069 if (GET_CODE (XEXP (x, 0)) == MEM)
17072 *total = COSTS_N_INSNS (1);
17078 if (!FLOAT_MODE_P (mode))
17080 *total = COSTS_N_INSNS (1);
17086 case UNSIGNED_FLOAT:
17090 case FLOAT_TRUNCATE:
17091 *total = rs6000_cost->fp;
17095 switch (XINT (x, 1))
17098 *total = rs6000_cost->fp;
17110 *total = COSTS_N_INSNS (1);
17113 else if (FLOAT_MODE_P (mode)
17114 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17116 *total = rs6000_cost->fp;
17124 /* Carry bit requires mode == Pmode.
17125 NEG or PLUS already counted so only add one. */
17127 && (outer_code == NEG || outer_code == PLUS))
17129 *total = COSTS_N_INSNS (1);
17132 if (outer_code == SET)
17134 if (XEXP (x, 1) == const0_rtx)
17136 *total = COSTS_N_INSNS (2);
17139 else if (mode == Pmode)
17141 *total = COSTS_N_INSNS (3);
17150 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17152 *total = COSTS_N_INSNS (2);
17156 if (outer_code == COMPARE)
17170 /* A C expression returning the cost of moving data from a register of class
17171 CLASS1 to one of CLASS2. */
17174 rs6000_register_move_cost (enum machine_mode mode,
17175 enum reg_class from, enum reg_class to)
17177 /* Moves from/to GENERAL_REGS. */
17178 if (reg_classes_intersect_p (to, GENERAL_REGS)
17179 || reg_classes_intersect_p (from, GENERAL_REGS))
17181 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17184 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17185 return (rs6000_memory_move_cost (mode, from, 0)
17186 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17188 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17190 else if (from == CR_REGS)
17194 /* A move will cost one instruction per GPR moved. */
17195 return 2 * HARD_REGNO_NREGS (0, mode);
17198 /* Moving between two similar registers is just one instruction. */
17199 else if (reg_classes_intersect_p (to, from))
17200 return mode == TFmode ? 4 : 2;
17202 /* Everything else has to go through GENERAL_REGS. */
17204 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17205 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17208 /* A C expressions returning the cost of moving data of MODE from a register to
17212 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17213 int in ATTRIBUTE_UNUSED)
17215 if (reg_classes_intersect_p (class, GENERAL_REGS))
17216 return 4 * HARD_REGNO_NREGS (0, mode);
17217 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17218 return 4 * HARD_REGNO_NREGS (32, mode);
17219 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17220 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17222 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17225 /* Return an RTX representing where to find the function value of a
17226 function returning MODE. */
17228 rs6000_complex_function_value (enum machine_mode mode)
17230 unsigned int regno;
17232 enum machine_mode inner = GET_MODE_INNER (mode);
17233 unsigned int inner_bytes = GET_MODE_SIZE (inner);
17235 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17236 regno = FP_ARG_RETURN;
17239 regno = GP_ARG_RETURN;
17241 /* 32-bit is OK since it'll go in r3/r4. */
17242 if (TARGET_32BIT && inner_bytes >= 4)
17243 return gen_rtx_REG (mode, regno);
17246 if (inner_bytes >= 8)
17247 return gen_rtx_REG (mode, regno);
17249 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17251 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
17252 GEN_INT (inner_bytes));
17253 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17256 /* Define how to find the value returned by a function.
17257 VALTYPE is the data type of the value (as a tree).
17258 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17259 otherwise, FUNC is 0.
17261 On the SPE, both FPs and vectors are returned in r3.
17263 On RS/6000 an integer value is in r3 and a floating-point value is in
17264 fp1, unless -msoft-float. */
17267 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17269 enum machine_mode mode;
17270 unsigned int regno;
17272 /* Special handling for structs in darwin64. */
17273 if (rs6000_darwin64_abi
17274 && TYPE_MODE (valtype) == BLKmode
17275 && TREE_CODE (valtype) == RECORD_TYPE
17276 && int_size_in_bytes (valtype) > 0)
17278 CUMULATIVE_ARGS valcum;
17282 valcum.fregno = FP_ARG_MIN_REG;
17283 valcum.vregno = ALTIVEC_ARG_MIN_REG;
17284 /* Do a trial code generation as if this were going to be passed as
17285 an argument; if any part goes in memory, we return NULL. */
17286 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
17289 /* Otherwise fall through to standard ABI rules. */
17292 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17294 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17295 return gen_rtx_PARALLEL (DImode,
17297 gen_rtx_EXPR_LIST (VOIDmode,
17298 gen_rtx_REG (SImode, GP_ARG_RETURN),
17300 gen_rtx_EXPR_LIST (VOIDmode,
17301 gen_rtx_REG (SImode,
17302 GP_ARG_RETURN + 1),
17306 if ((INTEGRAL_TYPE_P (valtype)
17307 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17308 || POINTER_TYPE_P (valtype))
17309 mode = TARGET_32BIT ? SImode : DImode;
17311 mode = TYPE_MODE (valtype);
17313 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
17314 regno = FP_ARG_RETURN;
17315 else if (TREE_CODE (valtype) == COMPLEX_TYPE
17316 && targetm.calls.split_complex_arg)
17317 return rs6000_complex_function_value (mode);
17318 else if (TREE_CODE (valtype) == VECTOR_TYPE
17319 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
17320 && ALTIVEC_VECTOR_MODE (mode))
17321 regno = ALTIVEC_ARG_RETURN;
17322 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17323 && (mode == DFmode || mode == DCmode))
17324 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17326 regno = GP_ARG_RETURN;
17328 return gen_rtx_REG (mode, regno);
17331 /* Define how to find the value returned by a library function
17332 assuming the value has mode MODE. */
17334 rs6000_libcall_value (enum machine_mode mode)
17336 unsigned int regno;
17338 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17340 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17341 return gen_rtx_PARALLEL (DImode,
17343 gen_rtx_EXPR_LIST (VOIDmode,
17344 gen_rtx_REG (SImode, GP_ARG_RETURN),
17346 gen_rtx_EXPR_LIST (VOIDmode,
17347 gen_rtx_REG (SImode,
17348 GP_ARG_RETURN + 1),
17352 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17353 && TARGET_HARD_FLOAT && TARGET_FPRS)
17354 regno = FP_ARG_RETURN;
17355 else if (ALTIVEC_VECTOR_MODE (mode)
17356 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
17357 regno = ALTIVEC_ARG_RETURN;
17358 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
17359 return rs6000_complex_function_value (mode);
17360 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17361 && (mode == DFmode || mode == DCmode))
17362 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17364 regno = GP_ARG_RETURN;
17366 return gen_rtx_REG (mode, regno);
17369 /* Define the offset between two registers, FROM to be eliminated and its
17370 replacement TO, at the start of a routine. */
17372 rs6000_initial_elimination_offset (int from, int to)
17374 rs6000_stack_t *info = rs6000_stack_info ();
17375 HOST_WIDE_INT offset;
17377 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17378 offset = info->push_p ? 0 : -info->total_size;
17379 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17380 offset = info->total_size;
17381 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17382 offset = info->push_p ? info->total_size : 0;
17383 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17391 /* Return true if TYPE is of type __ev64_opaque__. */
17394 is_ev64_opaque_type (tree type)
17397 && (type == opaque_V2SI_type_node
17398 || type == opaque_V2SF_type_node
17399 || type == opaque_p_V2SI_type_node));
17403 rs6000_dwarf_register_span (rtx reg)
17408 && (SPE_VECTOR_MODE (GET_MODE (reg))
17409 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17414 regno = REGNO (reg);
17416 /* The duality of the SPE register size wreaks all kinds of havoc.
17417 This is a way of distinguishing r0 in 32-bits from r0 in
17420 gen_rtx_PARALLEL (VOIDmode,
17423 gen_rtx_REG (SImode, regno + 1200),
17424 gen_rtx_REG (SImode, regno))
17426 gen_rtx_REG (SImode, regno),
17427 gen_rtx_REG (SImode, regno + 1200)));
17430 /* Map internal gcc register numbers to DWARF2 register numbers. */
17433 rs6000_dbx_register_number (unsigned int regno)
17435 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17437 if (regno == MQ_REGNO)
17439 if (regno == LINK_REGISTER_REGNUM)
17441 if (regno == COUNT_REGISTER_REGNUM)
17443 if (CR_REGNO_P (regno))
17444 return regno - CR0_REGNO + 86;
17445 if (regno == XER_REGNO)
17447 if (ALTIVEC_REGNO_P (regno))
17448 return regno - FIRST_ALTIVEC_REGNO + 1124;
17449 if (regno == VRSAVE_REGNO)
17451 if (regno == VSCR_REGNO)
17453 if (regno == SPE_ACC_REGNO)
17455 if (regno == SPEFSCR_REGNO)
17457 /* SPE high reg number. We get these values of regno from
17458 rs6000_dwarf_register_span. */
17459 if (regno >= 1200 && regno < 1232)
17465 /* target hook eh_return_filter_mode */
17466 static enum machine_mode
17467 rs6000_eh_return_filter_mode (void)
17469 return TARGET_32BIT ? SImode : word_mode;
17472 /* Target hook for vector_mode_supported_p. */
17474 rs6000_vector_mode_supported_p (enum machine_mode mode)
17477 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17480 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17487 /* Target hook for invalid_arg_for_unprototyped_fn. */
17488 static const char *
17489 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
17491 return (!rs6000_darwin64_abi
17493 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
17494 && (funcdecl == NULL_TREE
17495 || (TREE_CODE (funcdecl) == FUNCTION_DECL
17496 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
17497 ? N_("AltiVec argument passed to unprototyped function")
17501 #include "gt-rs6000.h"