1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int lr_size; /* size to hold LR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 int toc_size; /* size to hold TOC if not in save_size */
111 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
112 int spe_64bit_regs_used;
115 /* A C structure for machine-specific, per-function data.
116 This is added to the cfun structure. */
117 typedef struct machine_function GTY(())
119 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
120 int ra_needs_full_frame;
121 /* Some local-dynamic symbol. */
122 const char *some_ld_name;
123 /* Whether the instruction chain has been scanned already. */
124 int insn_chain_scanned_p;
125 /* Flags if __builtin_return_address (0) was used. */
127 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
128 varargs save area. */
129 HOST_WIDE_INT varargs_save_offset;
132 /* Target cpu type */
134 enum processor_type rs6000_cpu;
135 struct rs6000_cpu_select rs6000_select[3] =
137 /* switch name, tune arch */
138 { (const char *)0, "--with-cpu=", 1, 1 },
139 { (const char *)0, "-mcpu=", 1, 1 },
140 { (const char *)0, "-mtune=", 1, 0 },
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Support for -msched-costly-dep option. */
150 const char *rs6000_sched_costly_dep_str;
151 enum rs6000_dependence_cost rs6000_sched_costly_dep;
153 /* Support for -minsert-sched-nops option. */
154 const char *rs6000_sched_insert_nops_str;
155 enum rs6000_nop_insertion rs6000_sched_insert_nops;
157 /* Support targetm.vectorize.builtin_mask_for_load. */
158 static GTY(()) tree altivec_builtin_mask_for_load;
160 /* Size of long double */
161 int rs6000_long_double_type_size;
163 /* Whether -mabi=altivec has appeared */
164 int rs6000_altivec_abi;
166 /* Nonzero if we want SPE ABI extensions. */
169 /* Nonzero if floating point operations are done in the GPRs. */
170 int rs6000_float_gprs = 0;
172 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
173 int rs6000_darwin64_abi;
175 /* Set to nonzero once AIX common-mode calls have been defined. */
176 static GTY(()) int common_mode_defined;
178 /* Save information from a "cmpxx" operation until the branch or scc is
180 rtx rs6000_compare_op0, rs6000_compare_op1;
181 int rs6000_compare_fp_p;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 int rs6000_pic_labelno;
188 /* Which abi to adhere to */
189 const char *rs6000_abi_name;
191 /* Semantics of the small data area */
192 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
194 /* Which small data model to use */
195 const char *rs6000_sdata_name = (char *)0;
197 /* Counter for labels which are to be placed in .fixup. */
198 int fixuplabelno = 0;
201 /* Bit size of immediate TLS offsets and string from which it is decoded. */
202 int rs6000_tls_size = 32;
203 const char *rs6000_tls_size_string;
205 /* ABI enumeration available for subtarget to use. */
206 enum rs6000_abi rs6000_current_abi;
208 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
212 const char *rs6000_debug_name;
213 int rs6000_debug_stack; /* debug stack applications */
214 int rs6000_debug_arg; /* debug argument handling */
216 /* Value is TRUE if register/mode pair is acceptable. */
217 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
219 /* Built in types. */
221 tree rs6000_builtin_types[RS6000_BTI_MAX];
222 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
224 const char *rs6000_traceback_name;
226 traceback_default = 0,
232 /* Flag to say the TOC is initialized */
234 char toc_label_name[10];
236 /* Alias set for saves and restores from the rs6000 stack. */
237 static GTY(()) int rs6000_sr_alias_set;
239 /* Control alignment for fields within structures. */
240 /* String from -malign-XXXXX. */
241 int rs6000_alignment_flags;
243 /* True for any options that were explicitly set. */
245 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
246 bool alignment; /* True if -malign- was used. */
247 bool abi; /* True if -mabi= was used. */
248 bool spe; /* True if -mspe= was used. */
249 bool float_gprs; /* True if -mfloat-gprs= was used. */
250 bool isel; /* True if -misel was used. */
251 bool long_double; /* True if -mlong-double- was used. */
252 } rs6000_explicit_options;
254 struct builtin_description
256 /* mask is not const because we're going to alter it below. This
257 nonsense will go away when we rewrite the -march infrastructure
258 to give us more target flag bits. */
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Target cpu costs. */
267 struct processor_costs {
268 const int mulsi; /* cost of SImode multiplication. */
269 const int mulsi_const; /* cost of SImode multiplication by constant. */
270 const int mulsi_const9; /* cost of SImode mult by short constant. */
271 const int muldi; /* cost of DImode multiplication. */
272 const int divsi; /* cost of SImode division. */
273 const int divdi; /* cost of DImode division. */
274 const int fp; /* cost of simple SFmode and DFmode insns. */
275 const int dmul; /* cost of DFmode multiplication (and fmadd). */
276 const int sdiv; /* cost of SFmode division (fdivs). */
277 const int ddiv; /* cost of DFmode division (fdiv). */
280 const struct processor_costs *rs6000_cost;
282 /* Processor costs (relative to an add) */
284 /* Instruction size costs on 32bit processors. */
286 struct processor_costs size32_cost = {
287 COSTS_N_INSNS (1), /* mulsi */
288 COSTS_N_INSNS (1), /* mulsi_const */
289 COSTS_N_INSNS (1), /* mulsi_const9 */
290 COSTS_N_INSNS (1), /* muldi */
291 COSTS_N_INSNS (1), /* divsi */
292 COSTS_N_INSNS (1), /* divdi */
293 COSTS_N_INSNS (1), /* fp */
294 COSTS_N_INSNS (1), /* dmul */
295 COSTS_N_INSNS (1), /* sdiv */
296 COSTS_N_INSNS (1), /* ddiv */
299 /* Instruction size costs on 64bit processors. */
301 struct processor_costs size64_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction costs on RIOS1 processors. */
316 struct processor_costs rios1_cost = {
317 COSTS_N_INSNS (5), /* mulsi */
318 COSTS_N_INSNS (4), /* mulsi_const */
319 COSTS_N_INSNS (3), /* mulsi_const9 */
320 COSTS_N_INSNS (5), /* muldi */
321 COSTS_N_INSNS (19), /* divsi */
322 COSTS_N_INSNS (19), /* divdi */
323 COSTS_N_INSNS (2), /* fp */
324 COSTS_N_INSNS (2), /* dmul */
325 COSTS_N_INSNS (19), /* sdiv */
326 COSTS_N_INSNS (19), /* ddiv */
329 /* Instruction costs on RIOS2 processors. */
331 struct processor_costs rios2_cost = {
332 COSTS_N_INSNS (2), /* mulsi */
333 COSTS_N_INSNS (2), /* mulsi_const */
334 COSTS_N_INSNS (2), /* mulsi_const9 */
335 COSTS_N_INSNS (2), /* muldi */
336 COSTS_N_INSNS (13), /* divsi */
337 COSTS_N_INSNS (13), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (17), /* sdiv */
341 COSTS_N_INSNS (17), /* ddiv */
344 /* Instruction costs on RS64A processors. */
346 struct processor_costs rs64a_cost = {
347 COSTS_N_INSNS (20), /* mulsi */
348 COSTS_N_INSNS (12), /* mulsi_const */
349 COSTS_N_INSNS (8), /* mulsi_const9 */
350 COSTS_N_INSNS (34), /* muldi */
351 COSTS_N_INSNS (65), /* divsi */
352 COSTS_N_INSNS (67), /* divdi */
353 COSTS_N_INSNS (4), /* fp */
354 COSTS_N_INSNS (4), /* dmul */
355 COSTS_N_INSNS (31), /* sdiv */
356 COSTS_N_INSNS (31), /* ddiv */
359 /* Instruction costs on MPCCORE processors. */
361 struct processor_costs mpccore_cost = {
362 COSTS_N_INSNS (2), /* mulsi */
363 COSTS_N_INSNS (2), /* mulsi_const */
364 COSTS_N_INSNS (2), /* mulsi_const9 */
365 COSTS_N_INSNS (2), /* muldi */
366 COSTS_N_INSNS (6), /* divsi */
367 COSTS_N_INSNS (6), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (5), /* dmul */
370 COSTS_N_INSNS (10), /* sdiv */
371 COSTS_N_INSNS (17), /* ddiv */
374 /* Instruction costs on PPC403 processors. */
376 struct processor_costs ppc403_cost = {
377 COSTS_N_INSNS (4), /* mulsi */
378 COSTS_N_INSNS (4), /* mulsi_const */
379 COSTS_N_INSNS (4), /* mulsi_const9 */
380 COSTS_N_INSNS (4), /* muldi */
381 COSTS_N_INSNS (33), /* divsi */
382 COSTS_N_INSNS (33), /* divdi */
383 COSTS_N_INSNS (11), /* fp */
384 COSTS_N_INSNS (11), /* dmul */
385 COSTS_N_INSNS (11), /* sdiv */
386 COSTS_N_INSNS (11), /* ddiv */
389 /* Instruction costs on PPC405 processors. */
391 struct processor_costs ppc405_cost = {
392 COSTS_N_INSNS (5), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (3), /* mulsi_const9 */
395 COSTS_N_INSNS (5), /* muldi */
396 COSTS_N_INSNS (35), /* divsi */
397 COSTS_N_INSNS (35), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC440 processors. */
406 struct processor_costs ppc440_cost = {
407 COSTS_N_INSNS (3), /* mulsi */
408 COSTS_N_INSNS (2), /* mulsi_const */
409 COSTS_N_INSNS (2), /* mulsi_const9 */
410 COSTS_N_INSNS (3), /* muldi */
411 COSTS_N_INSNS (34), /* divsi */
412 COSTS_N_INSNS (34), /* divdi */
413 COSTS_N_INSNS (5), /* fp */
414 COSTS_N_INSNS (5), /* dmul */
415 COSTS_N_INSNS (19), /* sdiv */
416 COSTS_N_INSNS (33), /* ddiv */
419 /* Instruction costs on PPC601 processors. */
421 struct processor_costs ppc601_cost = {
422 COSTS_N_INSNS (5), /* mulsi */
423 COSTS_N_INSNS (5), /* mulsi_const */
424 COSTS_N_INSNS (5), /* mulsi_const9 */
425 COSTS_N_INSNS (5), /* muldi */
426 COSTS_N_INSNS (36), /* divsi */
427 COSTS_N_INSNS (36), /* divdi */
428 COSTS_N_INSNS (4), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (17), /* sdiv */
431 COSTS_N_INSNS (31), /* ddiv */
434 /* Instruction costs on PPC603 processors. */
436 struct processor_costs ppc603_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (3), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (37), /* divsi */
442 COSTS_N_INSNS (37), /* divdi */
443 COSTS_N_INSNS (3), /* fp */
444 COSTS_N_INSNS (4), /* dmul */
445 COSTS_N_INSNS (18), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
449 /* Instruction costs on PPC604 processors. */
451 struct processor_costs ppc604_cost = {
452 COSTS_N_INSNS (4), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (4), /* mulsi_const9 */
455 COSTS_N_INSNS (4), /* muldi */
456 COSTS_N_INSNS (20), /* divsi */
457 COSTS_N_INSNS (20), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (3), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (32), /* ddiv */
464 /* Instruction costs on PPC604e processors. */
466 struct processor_costs ppc604e_cost = {
467 COSTS_N_INSNS (2), /* mulsi */
468 COSTS_N_INSNS (2), /* mulsi_const */
469 COSTS_N_INSNS (2), /* mulsi_const9 */
470 COSTS_N_INSNS (2), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC620 processors. */
481 struct processor_costs ppc620_cost = {
482 COSTS_N_INSNS (5), /* mulsi */
483 COSTS_N_INSNS (4), /* mulsi_const */
484 COSTS_N_INSNS (3), /* mulsi_const9 */
485 COSTS_N_INSNS (7), /* muldi */
486 COSTS_N_INSNS (21), /* divsi */
487 COSTS_N_INSNS (37), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC630 processors. */
496 struct processor_costs ppc630_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (17), /* sdiv */
506 COSTS_N_INSNS (21), /* ddiv */
509 /* Instruction costs on PPC750 and PPC7400 processors. */
511 struct processor_costs ppc750_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (3), /* mulsi_const */
514 COSTS_N_INSNS (2), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (17), /* divsi */
517 COSTS_N_INSNS (17), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
524 /* Instruction costs on PPC7450 processors. */
526 struct processor_costs ppc7450_cost = {
527 COSTS_N_INSNS (4), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (3), /* mulsi_const9 */
530 COSTS_N_INSNS (4), /* muldi */
531 COSTS_N_INSNS (23), /* divsi */
532 COSTS_N_INSNS (23), /* divdi */
533 COSTS_N_INSNS (5), /* fp */
534 COSTS_N_INSNS (5), /* dmul */
535 COSTS_N_INSNS (21), /* sdiv */
536 COSTS_N_INSNS (35), /* ddiv */
539 /* Instruction costs on PPC8540 processors. */
541 struct processor_costs ppc8540_cost = {
542 COSTS_N_INSNS (4), /* mulsi */
543 COSTS_N_INSNS (4), /* mulsi_const */
544 COSTS_N_INSNS (4), /* mulsi_const9 */
545 COSTS_N_INSNS (4), /* muldi */
546 COSTS_N_INSNS (19), /* divsi */
547 COSTS_N_INSNS (19), /* divdi */
548 COSTS_N_INSNS (4), /* fp */
549 COSTS_N_INSNS (4), /* dmul */
550 COSTS_N_INSNS (29), /* sdiv */
551 COSTS_N_INSNS (29), /* ddiv */
554 /* Instruction costs on POWER4 and POWER5 processors. */
556 struct processor_costs power4_cost = {
557 COSTS_N_INSNS (3), /* mulsi */
558 COSTS_N_INSNS (2), /* mulsi_const */
559 COSTS_N_INSNS (2), /* mulsi_const9 */
560 COSTS_N_INSNS (4), /* muldi */
561 COSTS_N_INSNS (18), /* divsi */
562 COSTS_N_INSNS (34), /* divdi */
563 COSTS_N_INSNS (3), /* fp */
564 COSTS_N_INSNS (3), /* dmul */
565 COSTS_N_INSNS (17), /* sdiv */
566 COSTS_N_INSNS (17), /* ddiv */
570 static bool rs6000_function_ok_for_sibcall (tree, tree);
571 static const char *rs6000_invalid_within_doloop (rtx);
572 static rtx rs6000_generate_compare (enum rtx_code);
573 static void rs6000_maybe_dead (rtx);
574 static void rs6000_emit_stack_tie (void);
575 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
576 static rtx spe_synthesize_frame_save (rtx);
577 static bool spe_func_has_64bit_regs_p (void);
578 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
580 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
581 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
582 static unsigned rs6000_hash_constant (rtx);
583 static unsigned toc_hash_function (const void *);
584 static int toc_hash_eq (const void *, const void *);
585 static int constant_pool_expr_1 (rtx, int *, int *);
586 static bool constant_pool_expr_p (rtx);
587 static bool legitimate_indexed_address_p (rtx, int);
588 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
589 static struct machine_function * rs6000_init_machine_status (void);
590 static bool rs6000_assemble_integer (rtx, unsigned int, int);
591 static bool no_global_regs_above (int);
592 #ifdef HAVE_GAS_HIDDEN
593 static void rs6000_assemble_visibility (tree, int);
595 static int rs6000_ra_ever_killed (void);
596 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
597 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
598 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
599 static const char *rs6000_mangle_fundamental_type (tree);
600 extern const struct attribute_spec rs6000_attribute_table[];
601 static void rs6000_set_default_type_attributes (tree);
602 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
603 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
604 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
606 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
607 static bool rs6000_return_in_memory (tree, tree);
608 static void rs6000_file_start (void);
610 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
611 static void rs6000_elf_asm_out_constructor (rtx, int);
612 static void rs6000_elf_asm_out_destructor (rtx, int);
613 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
614 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
615 static void rs6000_elf_unique_section (tree, int);
616 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
617 unsigned HOST_WIDE_INT);
618 static void rs6000_elf_encode_section_info (tree, rtx, int)
620 static bool rs6000_elf_in_small_data_p (tree);
623 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
624 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
625 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
626 static void rs6000_xcoff_unique_section (tree, int);
627 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
628 unsigned HOST_WIDE_INT);
629 static const char * rs6000_xcoff_strip_name_encoding (const char *);
630 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
631 static void rs6000_xcoff_file_start (void);
632 static void rs6000_xcoff_file_end (void);
634 static int rs6000_variable_issue (FILE *, int, rtx, int);
635 static bool rs6000_rtx_costs (rtx, int, int, int *);
636 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
637 static bool is_microcoded_insn (rtx);
638 static int is_dispatch_slot_restricted (rtx);
639 static bool is_cracked_insn (rtx);
640 static bool is_branch_slot_insn (rtx);
641 static int rs6000_adjust_priority (rtx, int);
642 static int rs6000_issue_rate (void);
643 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
644 static rtx get_next_active_insn (rtx, rtx);
645 static bool insn_terminates_group_p (rtx , enum group_termination);
646 static bool is_costly_group (rtx *, rtx);
647 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
648 static int redefine_groups (FILE *, int, rtx, rtx);
649 static int pad_groups (FILE *, int, rtx, rtx);
650 static void rs6000_sched_finish (FILE *, int);
651 static int rs6000_use_sched_lookahead (void);
652 static tree rs6000_builtin_mask_for_load (void);
654 static void def_builtin (int, const char *, tree, int);
655 static void rs6000_init_builtins (void);
656 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
657 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
658 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
659 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
660 static void altivec_init_builtins (void);
661 static void rs6000_common_init_builtins (void);
662 static void rs6000_init_libfuncs (void);
664 static void enable_mask_for_builtins (struct builtin_description *, int,
665 enum rs6000_builtins,
666 enum rs6000_builtins);
667 static tree build_opaque_vector_type (tree, int);
668 static void spe_init_builtins (void);
669 static rtx spe_expand_builtin (tree, rtx, bool *);
670 static rtx spe_expand_stv_builtin (enum insn_code, tree);
671 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
672 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
673 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
674 static rs6000_stack_t *rs6000_stack_info (void);
675 static void debug_stack_info (rs6000_stack_t *);
677 static rtx altivec_expand_builtin (tree, rtx, bool *);
678 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
679 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
680 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
681 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
682 static rtx altivec_expand_predicate_builtin (enum insn_code,
683 const char *, tree, rtx);
684 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
685 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
686 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
687 static rtx altivec_expand_vec_set_builtin (tree);
688 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
689 static int get_element_number (tree, tree);
690 static bool rs6000_handle_option (size_t, const char *, int);
691 static void rs6000_parse_tls_size_option (void);
692 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
693 static int first_altivec_reg_to_save (void);
694 static unsigned int compute_vrsave_mask (void);
695 static void compute_save_world_info (rs6000_stack_t *info_ptr);
696 static void is_altivec_return_reg (rtx, void *);
697 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
698 int easy_vector_constant (rtx, enum machine_mode);
699 static bool rs6000_is_opaque_type (tree);
700 static rtx rs6000_dwarf_register_span (rtx);
701 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
702 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
703 static rtx rs6000_tls_get_addr (void);
704 static rtx rs6000_got_sym (void);
705 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
706 static const char *rs6000_get_some_local_dynamic_name (void);
707 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
708 static rtx rs6000_complex_function_value (enum machine_mode);
709 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
710 enum machine_mode, tree);
711 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
713 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
714 tree, HOST_WIDE_INT);
715 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
718 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
721 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
722 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
723 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
724 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
725 enum machine_mode, tree,
727 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
729 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
731 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
733 static void macho_branch_islands (void);
734 static void add_compiler_branch_island (tree, tree, int);
735 static int no_previous_def (tree function_name);
736 static tree get_prev_label (tree function_name);
737 static void rs6000_darwin_file_start (void);
740 static tree rs6000_build_builtin_va_list (void);
741 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
742 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
743 static bool rs6000_vector_mode_supported_p (enum machine_mode);
744 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
746 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
748 static int get_vsel_insn (enum machine_mode);
749 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
750 static tree rs6000_stack_protect_fail (void);
752 const int INSN_NOT_AVAILABLE = -1;
753 static enum machine_mode rs6000_eh_return_filter_mode (void);
755 /* Hash table stuff for keeping track of TOC entries. */
757 struct toc_hash_struct GTY(())
759 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
760 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
762 enum machine_mode key_mode;
766 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
768 /* Default register names. */
769 char rs6000_reg_names[][8] =
771 "0", "1", "2", "3", "4", "5", "6", "7",
772 "8", "9", "10", "11", "12", "13", "14", "15",
773 "16", "17", "18", "19", "20", "21", "22", "23",
774 "24", "25", "26", "27", "28", "29", "30", "31",
775 "0", "1", "2", "3", "4", "5", "6", "7",
776 "8", "9", "10", "11", "12", "13", "14", "15",
777 "16", "17", "18", "19", "20", "21", "22", "23",
778 "24", "25", "26", "27", "28", "29", "30", "31",
779 "mq", "lr", "ctr","ap",
780 "0", "1", "2", "3", "4", "5", "6", "7",
782 /* AltiVec registers. */
783 "0", "1", "2", "3", "4", "5", "6", "7",
784 "8", "9", "10", "11", "12", "13", "14", "15",
785 "16", "17", "18", "19", "20", "21", "22", "23",
786 "24", "25", "26", "27", "28", "29", "30", "31",
789 "spe_acc", "spefscr",
790 /* Soft frame pointer. */
794 #ifdef TARGET_REGNAMES
795 static const char alt_reg_names[][8] =
797 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
798 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
799 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
800 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
801 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
802 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
803 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
804 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
805 "mq", "lr", "ctr", "ap",
806 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
808 /* AltiVec registers. */
809 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
810 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
811 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
812 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
815 "spe_acc", "spefscr",
816 /* Soft frame pointer. */
821 #ifndef MASK_STRICT_ALIGN
822 #define MASK_STRICT_ALIGN 0
824 #ifndef TARGET_PROFILE_KERNEL
825 #define TARGET_PROFILE_KERNEL 0
828 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
829 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
831 /* Initialize the GCC target structure. */
832 #undef TARGET_ATTRIBUTE_TABLE
833 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
834 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
835 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
837 #undef TARGET_ASM_ALIGNED_DI_OP
838 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
840 /* Default unaligned ops are only provided for ELF. Find the ops needed
841 for non-ELF systems. */
842 #ifndef OBJECT_FORMAT_ELF
844 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
846 #undef TARGET_ASM_UNALIGNED_HI_OP
847 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
848 #undef TARGET_ASM_UNALIGNED_SI_OP
849 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
850 #undef TARGET_ASM_UNALIGNED_DI_OP
851 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
854 #undef TARGET_ASM_UNALIGNED_HI_OP
855 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
856 #undef TARGET_ASM_UNALIGNED_SI_OP
857 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
858 #undef TARGET_ASM_UNALIGNED_DI_OP
859 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
860 #undef TARGET_ASM_ALIGNED_DI_OP
861 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
865 /* This hook deals with fixups for relocatable code and DI-mode objects
867 #undef TARGET_ASM_INTEGER
868 #define TARGET_ASM_INTEGER rs6000_assemble_integer
870 #ifdef HAVE_GAS_HIDDEN
871 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
872 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
875 #undef TARGET_HAVE_TLS
876 #define TARGET_HAVE_TLS HAVE_AS_TLS
878 #undef TARGET_CANNOT_FORCE_CONST_MEM
879 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
881 #undef TARGET_ASM_FUNCTION_PROLOGUE
882 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
883 #undef TARGET_ASM_FUNCTION_EPILOGUE
884 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
886 #undef TARGET_SCHED_VARIABLE_ISSUE
887 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
889 #undef TARGET_SCHED_ISSUE_RATE
890 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
891 #undef TARGET_SCHED_ADJUST_COST
892 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
893 #undef TARGET_SCHED_ADJUST_PRIORITY
894 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
895 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
896 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
897 #undef TARGET_SCHED_FINISH
898 #define TARGET_SCHED_FINISH rs6000_sched_finish
900 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
901 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
903 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
904 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
906 #undef TARGET_INIT_BUILTINS
907 #define TARGET_INIT_BUILTINS rs6000_init_builtins
909 #undef TARGET_EXPAND_BUILTIN
910 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
912 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
913 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
915 #undef TARGET_INIT_LIBFUNCS
916 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
919 #undef TARGET_BINDS_LOCAL_P
920 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
923 #undef TARGET_ASM_OUTPUT_MI_THUNK
924 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
926 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
927 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
929 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
930 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
932 #undef TARGET_INVALID_WITHIN_DOLOOP
933 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
935 #undef TARGET_RTX_COSTS
936 #define TARGET_RTX_COSTS rs6000_rtx_costs
937 #undef TARGET_ADDRESS_COST
938 #define TARGET_ADDRESS_COST hook_int_rtx_0
940 #undef TARGET_VECTOR_OPAQUE_P
941 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
943 #undef TARGET_DWARF_REGISTER_SPAN
944 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
946 /* On rs6000, function arguments are promoted, as are function return
948 #undef TARGET_PROMOTE_FUNCTION_ARGS
949 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
950 #undef TARGET_PROMOTE_FUNCTION_RETURN
951 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
953 #undef TARGET_RETURN_IN_MEMORY
954 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
956 #undef TARGET_SETUP_INCOMING_VARARGS
957 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
959 /* Always strict argument naming on rs6000. */
960 #undef TARGET_STRICT_ARGUMENT_NAMING
961 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
962 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
963 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
964 #undef TARGET_SPLIT_COMPLEX_ARG
965 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
966 #undef TARGET_MUST_PASS_IN_STACK
967 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
968 #undef TARGET_PASS_BY_REFERENCE
969 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
970 #undef TARGET_ARG_PARTIAL_BYTES
971 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
973 #undef TARGET_BUILD_BUILTIN_VA_LIST
974 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
976 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
977 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
979 #undef TARGET_EH_RETURN_FILTER_MODE
980 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
982 #undef TARGET_VECTOR_MODE_SUPPORTED_P
983 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
985 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
986 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
988 #undef TARGET_HANDLE_OPTION
989 #define TARGET_HANDLE_OPTION rs6000_handle_option
991 #undef TARGET_DEFAULT_TARGET_FLAGS
992 #define TARGET_DEFAULT_TARGET_FLAGS \
993 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
995 #undef TARGET_STACK_PROTECT_FAIL
996 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
998 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
999 The PowerPC architecture requires only weak consistency among
1000 processors--that is, memory accesses between processors need not be
1001 sequentially consistent and memory accesses among processors can occur
1002 in any order. The ability to order memory accesses weakly provides
1003 opportunities for more efficient use of the system bus. Unless a
1004 dependency exists, the 604e allows read operations to precede store
1006 #undef TARGET_RELAXED_ORDERING
1007 #define TARGET_RELAXED_ORDERING true
1010 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1011 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1014 struct gcc_target targetm = TARGET_INITIALIZER;
1017 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1020 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1022 /* The GPRs can hold any mode, but values bigger than one register
1023 cannot go past R31. */
1024 if (INT_REGNO_P (regno))
1025 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1027 /* The float registers can only hold floating modes and DImode. */
1028 if (FP_REGNO_P (regno))
1030 (GET_MODE_CLASS (mode) == MODE_FLOAT
1031 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1032 || (GET_MODE_CLASS (mode) == MODE_INT
1033 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1035 /* The CR register can only hold CC modes. */
1036 if (CR_REGNO_P (regno))
1037 return GET_MODE_CLASS (mode) == MODE_CC;
1039 if (XER_REGNO_P (regno))
1040 return mode == PSImode;
1042 /* AltiVec only in AldyVec registers. */
1043 if (ALTIVEC_REGNO_P (regno))
1044 return ALTIVEC_VECTOR_MODE (mode);
1046 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1047 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1050 /* We cannot put TImode anywhere except general register and it must be
1051 able to fit within the register set. */
1053 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1056 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1058 rs6000_init_hard_regno_mode_ok (void)
1062 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1063 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1064 if (rs6000_hard_regno_mode_ok (r, m))
1065 rs6000_hard_regno_mode_ok_p[m][r] = true;
1068 /* If not otherwise specified by a target, make 'long double' equivalent to
1071 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1072 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1075 /* Override command line options. Mostly we process the processor
1076 type and sometimes adjust other TARGET_ options. */
1079 rs6000_override_options (const char *default_cpu)
1082 struct rs6000_cpu_select *ptr;
1085 /* Simplifications for entries below. */
1088 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1089 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1092 /* This table occasionally claims that a processor does not support
1093 a particular feature even though it does, but the feature is slower
1094 than the alternative. Thus, it shouldn't be relied on as a
1095 complete description of the processor's support.
1097 Please keep this list in order, and don't forget to update the
1098 documentation in invoke.texi when adding a new processor or
1102 const char *const name; /* Canonical processor name. */
1103 const enum processor_type processor; /* Processor type enum value. */
1104 const int target_enable; /* Target flags to enable. */
1105 } const processor_target_table[]
1106 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1107 {"403", PROCESSOR_PPC403,
1108 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1109 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1110 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1111 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1112 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1113 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1114 {"601", PROCESSOR_PPC601,
1115 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1116 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1117 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1118 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1120 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"620", PROCESSOR_PPC620,
1122 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1123 {"630", PROCESSOR_PPC630,
1124 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1125 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1127 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1128 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1130 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1131 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1132 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1133 /* 8548 has a dummy entry for now. */
1134 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1135 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1136 {"970", PROCESSOR_POWER4,
1137 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1138 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1139 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1141 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1142 {"G5", PROCESSOR_POWER4,
1143 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1144 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1145 {"power2", PROCESSOR_POWER,
1146 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1147 {"power3", PROCESSOR_PPC630,
1148 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1149 {"power4", PROCESSOR_POWER4,
1150 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1151 {"power5", PROCESSOR_POWER5,
1152 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1153 | MASK_MFCRF | MASK_POPCNTB},
1154 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1155 {"powerpc64", PROCESSOR_POWERPC64,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1158 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1159 {"rios2", PROCESSOR_RIOS2,
1160 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1161 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1162 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1163 {"rs64", PROCESSOR_RS64A,
1164 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1167 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1169 /* Some OSs don't support saving the high part of 64-bit registers on
1170 context switch. Other OSs don't support saving Altivec registers.
1171 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1172 settings; if the user wants either, the user must explicitly specify
1173 them and we won't interfere with the user's specification. */
1176 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1177 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1178 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1182 rs6000_init_hard_regno_mode_ok ();
1184 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1185 #ifdef OS_MISSING_POWERPC64
1186 if (OS_MISSING_POWERPC64)
1187 set_masks &= ~MASK_POWERPC64;
1189 #ifdef OS_MISSING_ALTIVEC
1190 if (OS_MISSING_ALTIVEC)
1191 set_masks &= ~MASK_ALTIVEC;
1194 /* Don't override by the processor default if given explicitly. */
1195 set_masks &= ~target_flags_explicit;
1197 /* Identify the processor type. */
1198 rs6000_select[0].string = default_cpu;
1199 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1201 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1203 ptr = &rs6000_select[i];
1204 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1206 for (j = 0; j < ptt_size; j++)
1207 if (! strcmp (ptr->string, processor_target_table[j].name))
1209 if (ptr->set_tune_p)
1210 rs6000_cpu = processor_target_table[j].processor;
1212 if (ptr->set_arch_p)
1214 target_flags &= ~set_masks;
1215 target_flags |= (processor_target_table[j].target_enable
1222 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1229 /* If we are optimizing big endian systems for space, use the load/store
1230 multiple and string instructions. */
1231 if (BYTES_BIG_ENDIAN && optimize_size)
1232 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1234 /* Don't allow -mmultiple or -mstring on little endian systems
1235 unless the cpu is a 750, because the hardware doesn't support the
1236 instructions used in little endian mode, and causes an alignment
1237 trap. The 750 does not cause an alignment trap (except when the
1238 target is unaligned). */
1240 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1242 if (TARGET_MULTIPLE)
1244 target_flags &= ~MASK_MULTIPLE;
1245 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1246 warning (0, "-mmultiple is not supported on little endian systems");
1251 target_flags &= ~MASK_STRING;
1252 if ((target_flags_explicit & MASK_STRING) != 0)
1253 warning (0, "-mstring is not supported on little endian systems");
1257 /* Set debug flags */
1258 if (rs6000_debug_name)
1260 if (! strcmp (rs6000_debug_name, "all"))
1261 rs6000_debug_stack = rs6000_debug_arg = 1;
1262 else if (! strcmp (rs6000_debug_name, "stack"))
1263 rs6000_debug_stack = 1;
1264 else if (! strcmp (rs6000_debug_name, "arg"))
1265 rs6000_debug_arg = 1;
1267 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1270 if (rs6000_traceback_name)
1272 if (! strncmp (rs6000_traceback_name, "full", 4))
1273 rs6000_traceback = traceback_full;
1274 else if (! strncmp (rs6000_traceback_name, "part", 4))
1275 rs6000_traceback = traceback_part;
1276 else if (! strncmp (rs6000_traceback_name, "no", 2))
1277 rs6000_traceback = traceback_none;
1279 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1280 rs6000_traceback_name);
1283 if (!rs6000_explicit_options.long_double)
1284 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1286 /* Set Altivec ABI as default for powerpc64 linux. */
1287 if (TARGET_ELF && TARGET_64BIT)
1289 rs6000_altivec_abi = 1;
1290 TARGET_ALTIVEC_VRSAVE = 1;
1293 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1294 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1296 rs6000_darwin64_abi = 1;
1298 darwin_one_byte_bool = 1;
1300 /* Default to natural alignment, for better performance. */
1301 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1304 /* Handle -mtls-size option. */
1305 rs6000_parse_tls_size_option ();
1307 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1308 SUBTARGET_OVERRIDE_OPTIONS;
1310 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1311 SUBSUBTARGET_OVERRIDE_OPTIONS;
1313 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1314 SUB3TARGET_OVERRIDE_OPTIONS;
1320 error ("AltiVec and E500 instructions cannot coexist");
1322 /* The e500 does not have string instructions, and we set
1323 MASK_STRING above when optimizing for size. */
1324 if ((target_flags & MASK_STRING) != 0)
1325 target_flags = target_flags & ~MASK_STRING;
1327 else if (rs6000_select[1].string != NULL)
1329 /* For the powerpc-eabispe configuration, we set all these by
1330 default, so let's unset them if we manually set another
1331 CPU that is not the E500. */
1332 if (!rs6000_explicit_options.abi)
1334 if (!rs6000_explicit_options.spe)
1336 if (!rs6000_explicit_options.float_gprs)
1337 rs6000_float_gprs = 0;
1338 if (!rs6000_explicit_options.isel)
1340 if (!rs6000_explicit_options.long_double)
1341 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1344 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1345 && rs6000_cpu != PROCESSOR_POWER5);
1346 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1347 || rs6000_cpu == PROCESSOR_POWER5);
1349 rs6000_sched_restricted_insns_priority
1350 = (rs6000_sched_groups ? 1 : 0);
1352 /* Handle -msched-costly-dep option. */
1353 rs6000_sched_costly_dep
1354 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1356 if (rs6000_sched_costly_dep_str)
1358 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1359 rs6000_sched_costly_dep = no_dep_costly;
1360 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1361 rs6000_sched_costly_dep = all_deps_costly;
1362 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1363 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1364 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1365 rs6000_sched_costly_dep = store_to_load_dep_costly;
1367 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1370 /* Handle -minsert-sched-nops option. */
1371 rs6000_sched_insert_nops
1372 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1374 if (rs6000_sched_insert_nops_str)
1376 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1377 rs6000_sched_insert_nops = sched_finish_none;
1378 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1379 rs6000_sched_insert_nops = sched_finish_pad_groups;
1380 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1381 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1383 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1386 #ifdef TARGET_REGNAMES
1387 /* If the user desires alternate register names, copy in the
1388 alternate names now. */
1389 if (TARGET_REGNAMES)
1390 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1393 /* Set aix_struct_return last, after the ABI is determined.
1394 If -maix-struct-return or -msvr4-struct-return was explicitly
1395 used, don't override with the ABI default. */
1396 if (!rs6000_explicit_options.aix_struct_ret)
1397 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1399 if (TARGET_LONG_DOUBLE_128
1400 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1401 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1403 /* Allocate an alias set for register saves & restores from stack. */
1404 rs6000_sr_alias_set = new_alias_set ();
1407 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1409 /* We can only guarantee the availability of DI pseudo-ops when
1410 assembling for 64-bit targets. */
1413 targetm.asm_out.aligned_op.di = NULL;
1414 targetm.asm_out.unaligned_op.di = NULL;
1417 /* Set branch target alignment, if not optimizing for size. */
1420 if (rs6000_sched_groups)
1422 if (align_functions <= 0)
1423 align_functions = 16;
1424 if (align_jumps <= 0)
1426 if (align_loops <= 0)
1429 if (align_jumps_max_skip <= 0)
1430 align_jumps_max_skip = 15;
1431 if (align_loops_max_skip <= 0)
1432 align_loops_max_skip = 15;
1435 /* Arrange to save and restore machine status around nested functions. */
1436 init_machine_status = rs6000_init_machine_status;
1438 /* We should always be splitting complex arguments, but we can't break
1439 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1440 if (DEFAULT_ABI != ABI_AIX)
1441 targetm.calls.split_complex_arg = NULL;
1443 /* Initialize rs6000_cost with the appropriate target costs. */
1445 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1449 case PROCESSOR_RIOS1:
1450 rs6000_cost = &rios1_cost;
1453 case PROCESSOR_RIOS2:
1454 rs6000_cost = &rios2_cost;
1457 case PROCESSOR_RS64A:
1458 rs6000_cost = &rs64a_cost;
1461 case PROCESSOR_MPCCORE:
1462 rs6000_cost = &mpccore_cost;
1465 case PROCESSOR_PPC403:
1466 rs6000_cost = &ppc403_cost;
1469 case PROCESSOR_PPC405:
1470 rs6000_cost = &ppc405_cost;
1473 case PROCESSOR_PPC440:
1474 rs6000_cost = &ppc440_cost;
1477 case PROCESSOR_PPC601:
1478 rs6000_cost = &ppc601_cost;
1481 case PROCESSOR_PPC603:
1482 rs6000_cost = &ppc603_cost;
1485 case PROCESSOR_PPC604:
1486 rs6000_cost = &ppc604_cost;
1489 case PROCESSOR_PPC604e:
1490 rs6000_cost = &ppc604e_cost;
1493 case PROCESSOR_PPC620:
1494 rs6000_cost = &ppc620_cost;
1497 case PROCESSOR_PPC630:
1498 rs6000_cost = &ppc630_cost;
1501 case PROCESSOR_PPC750:
1502 case PROCESSOR_PPC7400:
1503 rs6000_cost = &ppc750_cost;
1506 case PROCESSOR_PPC7450:
1507 rs6000_cost = &ppc7450_cost;
1510 case PROCESSOR_PPC8540:
1511 rs6000_cost = &ppc8540_cost;
1514 case PROCESSOR_POWER4:
1515 case PROCESSOR_POWER5:
1516 rs6000_cost = &power4_cost;
1524 /* Implement targetm.vectorize.builtin_mask_for_load. */
1526 rs6000_builtin_mask_for_load (void)
1529 return altivec_builtin_mask_for_load;
1534 /* Handle generic options of the form -mfoo=yes/no.
1535 NAME is the option name.
1536 VALUE is the option value.
1537 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1538 whether the option value is 'yes' or 'no' respectively. */
1540 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1544 else if (!strcmp (value, "yes"))
1546 else if (!strcmp (value, "no"))
1549 error ("unknown -m%s= option specified: '%s'", name, value);
1552 /* Validate and record the size specified with the -mtls-size option. */
1555 rs6000_parse_tls_size_option (void)
1557 if (rs6000_tls_size_string == 0)
1559 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1560 rs6000_tls_size = 16;
1561 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1562 rs6000_tls_size = 32;
1563 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1564 rs6000_tls_size = 64;
1566 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1570 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1572 if (DEFAULT_ABI == ABI_DARWIN)
1573 /* The Darwin libraries never set errno, so we might as well
1574 avoid calling them when that's the only reason we would. */
1575 flag_errno_math = 0;
1578 /* Implement TARGET_HANDLE_OPTION. */
1581 rs6000_handle_option (size_t code, const char *arg, int value)
1586 target_flags &= ~(MASK_POWER | MASK_POWER2
1587 | MASK_MULTIPLE | MASK_STRING);
1588 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1589 | MASK_MULTIPLE | MASK_STRING);
1591 case OPT_mno_powerpc:
1592 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1593 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1594 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1595 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1598 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1599 | MASK_NO_SUM_IN_TOC);
1600 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1601 | MASK_NO_SUM_IN_TOC);
1602 #ifdef TARGET_USES_SYSV4_OPT
1603 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1604 just the same as -mminimal-toc. */
1605 target_flags |= MASK_MINIMAL_TOC;
1606 target_flags_explicit |= MASK_MINIMAL_TOC;
1610 #ifdef TARGET_USES_SYSV4_OPT
1612 /* Make -mtoc behave like -mminimal-toc. */
1613 target_flags |= MASK_MINIMAL_TOC;
1614 target_flags_explicit |= MASK_MINIMAL_TOC;
1618 #ifdef TARGET_USES_AIX64_OPT
1623 target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT;
1624 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC
1628 #ifdef TARGET_USES_AIX64_OPT
1633 target_flags &= ~MASK_POWERPC64;
1634 target_flags_explicit |= MASK_POWERPC64;
1637 case OPT_minsert_sched_nops_:
1638 rs6000_sched_insert_nops_str = arg;
1641 case OPT_mminimal_toc:
1644 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1645 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1652 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1653 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1660 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1661 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1665 case OPT_mpowerpc_gpopt:
1666 case OPT_mpowerpc_gfxopt:
1669 target_flags |= MASK_POWERPC;
1670 target_flags_explicit |= MASK_POWERPC;
1674 case OPT_maix_struct_return:
1675 case OPT_msvr4_struct_return:
1676 rs6000_explicit_options.aix_struct_ret = true;
1680 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1684 rs6000_explicit_options.isel = true;
1685 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1689 rs6000_explicit_options.spe = true;
1690 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1691 /* No SPE means 64-bit long doubles, even if an E500. */
1693 rs6000_long_double_type_size = 64;
1697 rs6000_debug_name = arg;
1700 #ifdef TARGET_USES_SYSV4_OPT
1702 rs6000_abi_name = arg;
1706 rs6000_sdata_name = arg;
1709 case OPT_mtls_size_:
1710 rs6000_tls_size_string = arg;
1713 case OPT_mrelocatable:
1716 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1717 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1721 case OPT_mrelocatable_lib:
1724 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1725 | MASK_NO_FP_IN_TOC;
1726 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1727 | MASK_NO_FP_IN_TOC;
1731 target_flags &= ~MASK_RELOCATABLE;
1732 target_flags_explicit |= MASK_RELOCATABLE;
1738 rs6000_explicit_options.abi = true;
1739 if (!strcmp (arg, "altivec"))
1741 rs6000_altivec_abi = 1;
1744 else if (! strcmp (arg, "no-altivec"))
1745 rs6000_altivec_abi = 0;
1746 else if (! strcmp (arg, "spe"))
1749 rs6000_altivec_abi = 0;
1750 if (!TARGET_SPE_ABI)
1751 error ("not configured for ABI: '%s'", arg);
1753 else if (! strcmp (arg, "no-spe"))
1756 /* These are here for testing during development only, do not
1757 document in the manual please. */
1758 else if (! strcmp (arg, "d64"))
1760 rs6000_darwin64_abi = 1;
1761 warning (0, "Using darwin64 ABI");
1763 else if (! strcmp (arg, "d32"))
1765 rs6000_darwin64_abi = 0;
1766 warning (0, "Using old darwin ABI");
1771 error ("unknown ABI specified: '%s'", arg);
1777 rs6000_select[1].string = arg;
1781 rs6000_select[2].string = arg;
1784 case OPT_mtraceback_:
1785 rs6000_traceback_name = arg;
1788 case OPT_mfloat_gprs_:
1789 rs6000_explicit_options.float_gprs = true;
1790 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1791 rs6000_float_gprs = 1;
1792 else if (! strcmp (arg, "double"))
1793 rs6000_float_gprs = 2;
1794 else if (! strcmp (arg, "no"))
1795 rs6000_float_gprs = 0;
1798 error ("invalid option for -mfloat-gprs: '%s'", arg);
1803 case OPT_mlong_double_:
1804 rs6000_explicit_options.long_double = true;
1805 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1806 if (value != 64 && value != 128)
1808 error ("Unknown switch -mlong-double-%s", arg);
1809 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1813 rs6000_long_double_type_size = value;
1816 case OPT_msched_costly_dep_:
1817 rs6000_sched_costly_dep_str = arg;
1821 rs6000_explicit_options.alignment = true;
1822 if (! strcmp (arg, "power"))
1824 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1825 some C library functions, so warn about it. The flag may be
1826 useful for performance studies from time to time though, so
1827 don't disable it entirely. */
1828 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1829 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1830 " it is incompatible with the installed C and C++ libraries");
1831 rs6000_alignment_flags = MASK_ALIGN_POWER;
1833 else if (! strcmp (arg, "natural"))
1834 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1837 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1845 /* Do anything needed at the start of the asm file. */
1848 rs6000_file_start (void)
1852 const char *start = buffer;
1853 struct rs6000_cpu_select *ptr;
1854 const char *default_cpu = TARGET_CPU_DEFAULT;
1855 FILE *file = asm_out_file;
1857 default_file_start ();
1859 #ifdef TARGET_BI_ARCH
1860 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1864 if (flag_verbose_asm)
1866 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1867 rs6000_select[0].string = default_cpu;
1869 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1871 ptr = &rs6000_select[i];
1872 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1874 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1879 if (PPC405_ERRATUM77)
1881 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1885 #ifdef USING_ELFOS_H
1886 switch (rs6000_sdata)
1888 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1889 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1890 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1891 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1894 if (rs6000_sdata && g_switch_value)
1896 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1906 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1914 /* Return nonzero if this function is known to have a null epilogue. */
1917 direct_return (void)
1919 if (reload_completed)
1921 rs6000_stack_t *info = rs6000_stack_info ();
1923 if (info->first_gp_reg_save == 32
1924 && info->first_fp_reg_save == 64
1925 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1926 && ! info->lr_save_p
1927 && ! info->cr_save_p
1928 && info->vrsave_mask == 0
1936 /* Return the number of instructions it takes to form a constant in an
1937 integer register. */
1940 num_insns_constant_wide (HOST_WIDE_INT value)
1942 /* signed constant loadable with {cal|addi} */
1943 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1946 /* constant loadable with {cau|addis} */
1947 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1950 #if HOST_BITS_PER_WIDE_INT == 64
1951 else if (TARGET_POWERPC64)
1953 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1954 HOST_WIDE_INT high = value >> 31;
1956 if (high == 0 || high == -1)
1962 return num_insns_constant_wide (high) + 1;
1964 return (num_insns_constant_wide (high)
1965 + num_insns_constant_wide (low) + 1);
1974 num_insns_constant (rtx op, enum machine_mode mode)
1976 HOST_WIDE_INT low, high;
1978 switch (GET_CODE (op))
1981 #if HOST_BITS_PER_WIDE_INT == 64
1982 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1983 && mask64_operand (op, mode))
1987 return num_insns_constant_wide (INTVAL (op));
1995 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1996 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1997 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2000 if (mode == VOIDmode || mode == DImode)
2002 high = CONST_DOUBLE_HIGH (op);
2003 low = CONST_DOUBLE_LOW (op);
2010 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2011 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2012 high = l[WORDS_BIG_ENDIAN == 0];
2013 low = l[WORDS_BIG_ENDIAN != 0];
2017 return (num_insns_constant_wide (low)
2018 + num_insns_constant_wide (high));
2021 if ((high == 0 && low >= 0)
2022 || (high == -1 && low < 0))
2023 return num_insns_constant_wide (low);
2025 else if (mask64_operand (op, mode))
2029 return num_insns_constant_wide (high) + 1;
2032 return (num_insns_constant_wide (high)
2033 + num_insns_constant_wide (low) + 1);
2041 /* Returns the constant for the splat instruction, if exists. */
2044 easy_vector_splat_const (int cst, enum machine_mode mode)
2049 if (EASY_VECTOR_15 (cst)
2050 || EASY_VECTOR_15_ADD_SELF (cst))
2052 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2058 if (EASY_VECTOR_15 (cst)
2059 || EASY_VECTOR_15_ADD_SELF (cst))
2061 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2067 if (EASY_VECTOR_15 (cst)
2068 || EASY_VECTOR_15_ADD_SELF (cst))
2076 /* Return nonzero if all elements of a vector have the same value. */
2079 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2083 units = CONST_VECTOR_NUNITS (op);
2085 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2086 for (i = 1; i < units; ++i)
2087 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2089 if (i == units && easy_vector_splat_const (cst, mode))
2094 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2097 gen_easy_vector_constant_add_self (rtx op)
2101 units = GET_MODE_NUNITS (GET_MODE (op));
2102 v = rtvec_alloc (units);
2104 for (i = 0; i < units; i++)
2106 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2107 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2111 output_vec_const_move (rtx *operands)
2114 enum machine_mode mode;
2120 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2121 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2122 mode = GET_MODE (dest);
2126 if (zero_constant (vec, mode))
2127 return "vxor %0,%0,%0";
2129 gcc_assert (easy_vector_constant (vec, mode));
2131 operands[1] = GEN_INT (cst);
2135 if (EASY_VECTOR_15 (cst))
2137 operands[1] = GEN_INT (cst);
2138 return "vspltisw %0,%1";
2140 else if (EASY_VECTOR_15_ADD_SELF (cst))
2146 if (EASY_VECTOR_15 (cst))
2148 operands[1] = GEN_INT (cst);
2149 return "vspltish %0,%1";
2151 else if (EASY_VECTOR_15_ADD_SELF (cst))
2157 if (EASY_VECTOR_15 (cst))
2159 operands[1] = GEN_INT (cst);
2160 return "vspltisb %0,%1";
2162 else if (EASY_VECTOR_15_ADD_SELF (cst))
2170 gcc_assert (TARGET_SPE);
2172 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2173 pattern of V1DI, V4HI, and V2SF.
2175 FIXME: We should probably return # and add post reload
2176 splitters for these, but this way is so easy ;-). */
2177 operands[1] = GEN_INT (cst);
2178 operands[2] = GEN_INT (cst2);
2180 return "li %0,%1\n\tevmergelo %0,%0,%0";
2182 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2185 /* Initialize vector TARGET to VALS. */
2188 rs6000_expand_vector_init (rtx target, rtx vals)
2190 enum machine_mode mode = GET_MODE (target);
2191 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2192 int n_elts = GET_MODE_NUNITS (mode);
2193 int n_var = 0, one_var = -1;
2194 bool all_same = true, all_const_zero = true;
2198 for (i = 0; i < n_elts; ++i)
2200 x = XVECEXP (vals, 0, i);
2201 if (!CONSTANT_P (x))
2202 ++n_var, one_var = i;
2203 else if (x != CONST0_RTX (inner_mode))
2204 all_const_zero = false;
2206 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2212 if (mode != V4SFmode && all_const_zero)
2214 /* Zero register. */
2215 emit_insn (gen_rtx_SET (VOIDmode, target,
2216 gen_rtx_XOR (mode, target, target)));
2219 else if (mode != V4SFmode && easy_vector_same (vals, mode))
2221 /* Splat immediate. */
2222 x = gen_rtx_VEC_DUPLICATE (mode, CONST_VECTOR_ELT (vals, 0));
2223 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2227 ; /* Splat vector element. */
2230 /* Load from constant pool. */
2231 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2236 /* Store value to stack temp. Load vector element. Splat. */
2239 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2240 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2241 XVECEXP (vals, 0, 0));
2242 x = gen_rtx_UNSPEC (VOIDmode,
2243 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2244 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2246 gen_rtx_SET (VOIDmode,
2249 x = gen_rtx_VEC_SELECT (inner_mode, target,
2250 gen_rtx_PARALLEL (VOIDmode,
2251 gen_rtvec (1, const0_rtx)));
2252 emit_insn (gen_rtx_SET (VOIDmode, target,
2253 gen_rtx_VEC_DUPLICATE (mode, x)));
2257 /* One field is non-constant. Load constant then overwrite
2261 rtx copy = copy_rtx (vals);
2263 /* Load constant part of vector, substitute neighboring value for
2265 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2266 rs6000_expand_vector_init (target, copy);
2268 /* Insert variable. */
2269 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2273 /* Construct the vector in memory one field at a time
2274 and load the whole vector. */
2275 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2276 for (i = 0; i < n_elts; i++)
2277 emit_move_insn (adjust_address_nv (mem, inner_mode,
2278 i * GET_MODE_SIZE (inner_mode)),
2279 XVECEXP (vals, 0, i));
2280 emit_move_insn (target, mem);
2283 /* Set field ELT of TARGET to VAL. */
2286 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2288 enum machine_mode mode = GET_MODE (target);
2289 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2290 rtx reg = gen_reg_rtx (mode);
2292 int width = GET_MODE_SIZE (inner_mode);
2295 /* Load single variable value. */
2296 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2297 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2298 x = gen_rtx_UNSPEC (VOIDmode,
2299 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2300 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2302 gen_rtx_SET (VOIDmode,
2306 /* Linear sequence. */
2307 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2308 for (i = 0; i < 16; ++i)
2309 XVECEXP (mask, 0, i) = GEN_INT (i);
2311 /* Set permute mask to insert element into target. */
2312 for (i = 0; i < width; ++i)
2313 XVECEXP (mask, 0, elt*width + i)
2314 = GEN_INT (i + 0x10);
2315 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2316 x = gen_rtx_UNSPEC (mode,
2317 gen_rtvec (3, target, reg,
2318 force_reg (V16QImode, x)),
2320 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2323 /* Extract field ELT from VEC into TARGET. */
2326 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2328 enum machine_mode mode = GET_MODE (vec);
2329 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2332 /* Allocate mode-sized buffer. */
2333 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2335 /* Add offset to field within buffer matching vector element. */
2336 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2338 /* Store single field into mode-sized buffer. */
2339 x = gen_rtx_UNSPEC (VOIDmode,
2340 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2341 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2343 gen_rtx_SET (VOIDmode,
2346 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2349 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2350 implement ANDing by the mask IN. */
2352 build_mask64_2_operands (rtx in, rtx *out)
2354 #if HOST_BITS_PER_WIDE_INT >= 64
2355 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2358 gcc_assert (GET_CODE (in) == CONST_INT);
2363 /* Assume c initially something like 0x00fff000000fffff. The idea
2364 is to rotate the word so that the middle ^^^^^^ group of zeros
2365 is at the MS end and can be cleared with an rldicl mask. We then
2366 rotate back and clear off the MS ^^ group of zeros with a
2368 c = ~c; /* c == 0xff000ffffff00000 */
2369 lsb = c & -c; /* lsb == 0x0000000000100000 */
2370 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2371 c = ~c; /* c == 0x00fff000000fffff */
2372 c &= -lsb; /* c == 0x00fff00000000000 */
2373 lsb = c & -c; /* lsb == 0x0000100000000000 */
2374 c = ~c; /* c == 0xff000fffffffffff */
2375 c &= -lsb; /* c == 0xff00000000000000 */
2377 while ((lsb >>= 1) != 0)
2378 shift++; /* shift == 44 on exit from loop */
2379 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2380 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2381 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2385 /* Assume c initially something like 0xff000f0000000000. The idea
2386 is to rotate the word so that the ^^^ middle group of zeros
2387 is at the LS end and can be cleared with an rldicr mask. We then
2388 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2390 lsb = c & -c; /* lsb == 0x0000010000000000 */
2391 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2392 c = ~c; /* c == 0x00fff0ffffffffff */
2393 c &= -lsb; /* c == 0x00fff00000000000 */
2394 lsb = c & -c; /* lsb == 0x0000100000000000 */
2395 c = ~c; /* c == 0xff000fffffffffff */
2396 c &= -lsb; /* c == 0xff00000000000000 */
2398 while ((lsb >>= 1) != 0)
2399 shift++; /* shift == 44 on exit from loop */
2400 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2401 m1 >>= shift; /* m1 == 0x0000000000000fff */
2402 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2405 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2406 masks will be all 1's. We are guaranteed more than one transition. */
2407 out[0] = GEN_INT (64 - shift);
2408 out[1] = GEN_INT (m1);
2409 out[2] = GEN_INT (shift);
2410 out[3] = GEN_INT (m2);
2418 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2421 invalid_e500_subreg (rtx op, enum machine_mode mode)
2423 /* Reject (subreg:SI (reg:DF)). */
2424 if (GET_CODE (op) == SUBREG
2426 && REG_P (SUBREG_REG (op))
2427 && GET_MODE (SUBREG_REG (op)) == DFmode)
2430 /* Reject (subreg:DF (reg:DI)). */
2431 if (GET_CODE (op) == SUBREG
2433 && REG_P (SUBREG_REG (op))
2434 && GET_MODE (SUBREG_REG (op)) == DImode)
2440 /* Darwin, AIX increases natural record alignment to doubleword if the first
2441 field is an FP double while the FP fields remain word aligned. */
2444 rs6000_special_round_type_align (tree type, int computed, int specified)
2446 tree field = TYPE_FIELDS (type);
2448 /* Skip all non field decls */
2449 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2450 field = TREE_CHAIN (field);
2452 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2453 return MAX (computed, specified);
2455 return MAX (MAX (computed, specified), 64);
2458 /* Return 1 for an operand in small memory on V.4/eabi. */
2461 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2462 enum machine_mode mode ATTRIBUTE_UNUSED)
2467 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2470 if (DEFAULT_ABI != ABI_V4)
2473 if (GET_CODE (op) == SYMBOL_REF)
2476 else if (GET_CODE (op) != CONST
2477 || GET_CODE (XEXP (op, 0)) != PLUS
2478 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2479 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2484 rtx sum = XEXP (op, 0);
2485 HOST_WIDE_INT summand;
2487 /* We have to be careful here, because it is the referenced address
2488 that must be 32k from _SDA_BASE_, not just the symbol. */
2489 summand = INTVAL (XEXP (sum, 1));
2490 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2493 sym_ref = XEXP (sum, 0);
2496 return SYMBOL_REF_SMALL_P (sym_ref);
2502 /* Return true if either operand is a general purpose register. */
2505 gpr_or_gpr_p (rtx op0, rtx op1)
2507 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2508 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2512 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2515 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2517 switch (GET_CODE (op))
2520 if (RS6000_SYMBOL_REF_TLS_P (op))
2522 else if (CONSTANT_POOL_ADDRESS_P (op))
2524 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2532 else if (! strcmp (XSTR (op, 0), toc_label_name))
2541 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2542 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2544 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2553 constant_pool_expr_p (rtx op)
2557 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2561 toc_relative_expr_p (rtx op)
2565 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2569 legitimate_constant_pool_address_p (rtx x)
2572 && GET_CODE (x) == PLUS
2573 && GET_CODE (XEXP (x, 0)) == REG
2574 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2575 && constant_pool_expr_p (XEXP (x, 1)));
2579 rs6000_legitimate_small_data_p (enum machine_mode mode, rtx x)
2581 return (DEFAULT_ABI == ABI_V4
2582 && !flag_pic && !TARGET_TOC
2583 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2584 && small_data_operand (x, mode));
2587 /* SPE offset addressing is limited to 5-bits worth of double words. */
2588 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2591 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2593 unsigned HOST_WIDE_INT offset, extra;
2595 if (GET_CODE (x) != PLUS)
2597 if (GET_CODE (XEXP (x, 0)) != REG)
2599 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2601 if (legitimate_constant_pool_address_p (x))
2603 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2606 offset = INTVAL (XEXP (x, 1));
2614 /* AltiVec vector modes. Only reg+reg addressing is valid and
2615 constant offset zero should not occur due to canonicalization.
2616 Allow any offset when not strict before reload. */
2623 /* SPE vector modes. */
2624 return SPE_CONST_OFFSET_OK (offset);
2627 if (TARGET_E500_DOUBLE)
2628 return SPE_CONST_OFFSET_OK (offset);
2631 /* On e500v2, we may have:
2633 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2635 Which gets addressed with evldd instructions. */
2636 if (TARGET_E500_DOUBLE)
2637 return SPE_CONST_OFFSET_OK (offset);
2639 if (mode == DFmode || !TARGET_POWERPC64)
2641 else if (offset & 3)
2647 if (mode == TFmode || !TARGET_POWERPC64)
2649 else if (offset & 3)
2660 return (offset < 0x10000) && (offset + extra < 0x10000);
2664 legitimate_indexed_address_p (rtx x, int strict)
2668 if (GET_CODE (x) != PLUS)
2674 if (!REG_P (op0) || !REG_P (op1))
2677 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2678 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2679 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2680 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2684 legitimate_indirect_address_p (rtx x, int strict)
2686 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2690 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2692 if (!TARGET_MACHO || !flag_pic
2693 || mode != SImode || GET_CODE (x) != MEM)
2697 if (GET_CODE (x) != LO_SUM)
2699 if (GET_CODE (XEXP (x, 0)) != REG)
2701 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2705 return CONSTANT_P (x);
2709 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2711 if (GET_CODE (x) != LO_SUM)
2713 if (GET_CODE (XEXP (x, 0)) != REG)
2715 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2717 /* Restrict addressing for DI because of our SUBREG hackery. */
2718 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2722 if (TARGET_ELF || TARGET_MACHO)
2724 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2728 if (GET_MODE_NUNITS (mode) != 1)
2730 if (GET_MODE_BITSIZE (mode) > 64
2731 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2732 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2735 return CONSTANT_P (x);
2742 /* Try machine-dependent ways of modifying an illegitimate address
2743 to be legitimate. If we find one, return the new, valid address.
2744 This is used from only one place: `memory_address' in explow.c.
2746 OLDX is the address as it was before break_out_memory_refs was
2747 called. In some cases it is useful to look at this to decide what
2750 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2752 It is always safe for this function to do nothing. It exists to
2753 recognize opportunities to optimize the output.
2755 On RS/6000, first check for the sum of a register with a constant
2756 integer that is out of range. If so, generate code to add the
2757 constant with the low-order 16 bits masked to the register and force
2758 this result into another register (this can be done with `cau').
2759 Then generate an address of REG+(CONST&0xffff), allowing for the
2760 possibility of bit 16 being a one.
2762 Then check for the sum of a register and something not constant, try to
2763 load the other things into a register and return the sum. */
2766 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2767 enum machine_mode mode)
2769 if (GET_CODE (x) == SYMBOL_REF)
2771 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2773 return rs6000_legitimize_tls_address (x, model);
2776 if (GET_CODE (x) == PLUS
2777 && GET_CODE (XEXP (x, 0)) == REG
2778 && GET_CODE (XEXP (x, 1)) == CONST_INT
2779 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2781 HOST_WIDE_INT high_int, low_int;
2783 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2784 high_int = INTVAL (XEXP (x, 1)) - low_int;
2785 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2786 GEN_INT (high_int)), 0);
2787 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2789 else if (GET_CODE (x) == PLUS
2790 && GET_CODE (XEXP (x, 0)) == REG
2791 && GET_CODE (XEXP (x, 1)) != CONST_INT
2792 && GET_MODE_NUNITS (mode) == 1
2793 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2795 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2797 && (TARGET_POWERPC64 || mode != DImode)
2800 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2801 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2803 else if (ALTIVEC_VECTOR_MODE (mode))
2807 /* Make sure both operands are registers. */
2808 if (GET_CODE (x) == PLUS)
2809 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2810 force_reg (Pmode, XEXP (x, 1)));
2812 reg = force_reg (Pmode, x);
2815 else if (SPE_VECTOR_MODE (mode)
2816 || (TARGET_E500_DOUBLE && (mode == DFmode
2817 || mode == DImode)))
2821 /* We accept [reg + reg] and [reg + OFFSET]. */
2823 if (GET_CODE (x) == PLUS)
2825 rtx op1 = XEXP (x, 0);
2826 rtx op2 = XEXP (x, 1);
2828 op1 = force_reg (Pmode, op1);
2830 if (GET_CODE (op2) != REG
2831 && (GET_CODE (op2) != CONST_INT
2832 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2833 op2 = force_reg (Pmode, op2);
2835 return gen_rtx_PLUS (Pmode, op1, op2);
2838 return force_reg (Pmode, x);
2844 && GET_CODE (x) != CONST_INT
2845 && GET_CODE (x) != CONST_DOUBLE
2847 && GET_MODE_NUNITS (mode) == 1
2848 && (GET_MODE_BITSIZE (mode) <= 32
2849 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2851 rtx reg = gen_reg_rtx (Pmode);
2852 emit_insn (gen_elf_high (reg, x));
2853 return gen_rtx_LO_SUM (Pmode, reg, x);
2855 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2858 && ! MACHO_DYNAMIC_NO_PIC_P
2860 && GET_CODE (x) != CONST_INT
2861 && GET_CODE (x) != CONST_DOUBLE
2863 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2867 rtx reg = gen_reg_rtx (Pmode);
2868 emit_insn (gen_macho_high (reg, x));
2869 return gen_rtx_LO_SUM (Pmode, reg, x);
2872 && constant_pool_expr_p (x)
2873 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2875 return create_TOC_reference (x);
2881 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2882 We need to emit DTP-relative relocations. */
2885 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2890 fputs ("\t.long\t", file);
2893 fputs (DOUBLE_INT_ASM_OP, file);
2898 output_addr_const (file, x);
2899 fputs ("@dtprel+0x8000", file);
2902 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2904 static GTY(()) rtx rs6000_tls_symbol;
2906 rs6000_tls_get_addr (void)
2908 if (!rs6000_tls_symbol)
2909 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2911 return rs6000_tls_symbol;
2914 /* Construct the SYMBOL_REF for TLS GOT references. */
2916 static GTY(()) rtx rs6000_got_symbol;
2918 rs6000_got_sym (void)
2920 if (!rs6000_got_symbol)
2922 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2923 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2924 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2927 return rs6000_got_symbol;
2930 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2931 this (thread-local) address. */
2934 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2938 dest = gen_reg_rtx (Pmode);
2939 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2945 tlsreg = gen_rtx_REG (Pmode, 13);
2946 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2950 tlsreg = gen_rtx_REG (Pmode, 2);
2951 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2955 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2959 tmp = gen_reg_rtx (Pmode);
2962 tlsreg = gen_rtx_REG (Pmode, 13);
2963 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2967 tlsreg = gen_rtx_REG (Pmode, 2);
2968 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2972 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2974 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2979 rtx r3, got, tga, tmp1, tmp2, eqv;
2981 /* We currently use relocations like @got@tlsgd for tls, which
2982 means the linker will handle allocation of tls entries, placing
2983 them in the .got section. So use a pointer to the .got section,
2984 not one to secondary TOC sections used by 64-bit -mminimal-toc,
2985 or to secondary GOT sections used by 32-bit -fPIC. */
2987 got = gen_rtx_REG (Pmode, 2);
2991 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2994 rtx gsym = rs6000_got_sym ();
2995 got = gen_reg_rtx (Pmode);
2997 rs6000_emit_move (got, gsym, Pmode);
3000 rtx tempLR, tmp3, mem;
3003 tempLR = gen_reg_rtx (Pmode);
3004 tmp1 = gen_reg_rtx (Pmode);
3005 tmp2 = gen_reg_rtx (Pmode);
3006 tmp3 = gen_reg_rtx (Pmode);
3007 mem = gen_const_mem (Pmode, tmp1);
3009 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3010 emit_move_insn (tmp1, tempLR);
3011 emit_move_insn (tmp2, mem);
3012 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3013 last = emit_move_insn (got, tmp3);
3014 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3016 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3018 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3024 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3026 r3 = gen_rtx_REG (Pmode, 3);
3028 insn = gen_tls_gd_64 (r3, got, addr);
3030 insn = gen_tls_gd_32 (r3, got, addr);
3033 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3034 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3035 insn = emit_call_insn (insn);
3036 CONST_OR_PURE_CALL_P (insn) = 1;
3037 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3038 insn = get_insns ();
3040 emit_libcall_block (insn, dest, r3, addr);
3042 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3044 r3 = gen_rtx_REG (Pmode, 3);
3046 insn = gen_tls_ld_64 (r3, got);
3048 insn = gen_tls_ld_32 (r3, got);
3051 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3052 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3053 insn = emit_call_insn (insn);
3054 CONST_OR_PURE_CALL_P (insn) = 1;
3055 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3056 insn = get_insns ();
3058 tmp1 = gen_reg_rtx (Pmode);
3059 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3061 emit_libcall_block (insn, tmp1, r3, eqv);
3062 if (rs6000_tls_size == 16)
3065 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3067 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3069 else if (rs6000_tls_size == 32)
3071 tmp2 = gen_reg_rtx (Pmode);
3073 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3075 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3078 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3080 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3084 tmp2 = gen_reg_rtx (Pmode);
3086 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3088 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3090 insn = gen_rtx_SET (Pmode, dest,
3091 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3097 /* IE, or 64 bit offset LE. */
3098 tmp2 = gen_reg_rtx (Pmode);
3100 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3102 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3105 insn = gen_tls_tls_64 (dest, tmp2, addr);
3107 insn = gen_tls_tls_32 (dest, tmp2, addr);
3115 /* Return 1 if X contains a thread-local symbol. */
3118 rs6000_tls_referenced_p (rtx x)
3120 if (! TARGET_HAVE_TLS)
3123 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3126 /* Return 1 if *X is a thread-local symbol. This is the same as
3127 rs6000_tls_symbol_ref except for the type of the unused argument. */
3130 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3132 return RS6000_SYMBOL_REF_TLS_P (*x);
3135 /* The convention appears to be to define this wherever it is used.
3136 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3137 is now used here. */
3138 #ifndef REG_MODE_OK_FOR_BASE_P
3139 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3142 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3143 replace the input X, or the original X if no replacement is called for.
3144 The output parameter *WIN is 1 if the calling macro should goto WIN,
3147 For RS/6000, we wish to handle large displacements off a base
3148 register by splitting the addend across an addiu/addis and the mem insn.
3149 This cuts number of extra insns needed from 3 to 1.
3151 On Darwin, we use this to generate code for floating point constants.
3152 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3153 The Darwin code is inside #if TARGET_MACHO because only then is
3154 machopic_function_base_name() defined. */
3156 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3157 int opnum, int type,
3158 int ind_levels ATTRIBUTE_UNUSED, int *win)
3160 /* We must recognize output that we have already generated ourselves. */
3161 if (GET_CODE (x) == PLUS
3162 && GET_CODE (XEXP (x, 0)) == PLUS
3163 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3164 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3165 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3167 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3168 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3169 opnum, (enum reload_type)type);
3175 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3176 && GET_CODE (x) == LO_SUM
3177 && GET_CODE (XEXP (x, 0)) == PLUS
3178 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3179 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3180 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3181 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3182 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3183 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3184 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3186 /* Result of previous invocation of this function on Darwin
3187 floating point constant. */
3188 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3189 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3190 opnum, (enum reload_type)type);
3196 /* Force ld/std non-word aligned offset into base register by wrapping
3198 if (GET_CODE (x) == PLUS
3199 && GET_CODE (XEXP (x, 0)) == REG
3200 && REGNO (XEXP (x, 0)) < 32
3201 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3202 && GET_CODE (XEXP (x, 1)) == CONST_INT
3203 && (INTVAL (XEXP (x, 1)) & 3) != 0
3204 && !ALTIVEC_VECTOR_MODE (mode)
3205 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3206 && TARGET_POWERPC64)
3208 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3209 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3210 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3211 opnum, (enum reload_type) type);
3216 if (GET_CODE (x) == PLUS
3217 && GET_CODE (XEXP (x, 0)) == REG
3218 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3219 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3220 && GET_CODE (XEXP (x, 1)) == CONST_INT
3221 && !SPE_VECTOR_MODE (mode)
3222 && !(TARGET_E500_DOUBLE && (mode == DFmode
3224 && !ALTIVEC_VECTOR_MODE (mode))
3226 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3227 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3229 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3231 /* Check for 32-bit overflow. */
3232 if (high + low != val)
3238 /* Reload the high part into a base reg; leave the low part
3239 in the mem directly. */
3241 x = gen_rtx_PLUS (GET_MODE (x),
3242 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3246 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3247 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3248 opnum, (enum reload_type)type);
3253 if (GET_CODE (x) == SYMBOL_REF
3254 && !ALTIVEC_VECTOR_MODE (mode)
3256 && DEFAULT_ABI == ABI_DARWIN
3257 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3259 && DEFAULT_ABI == ABI_V4
3262 /* Don't do this for TFmode, since the result isn't offsettable.
3263 The same goes for DImode without 64-bit gprs. */
3265 && (mode != DImode || TARGET_POWERPC64))
3270 rtx offset = gen_rtx_CONST (Pmode,
3271 gen_rtx_MINUS (Pmode, x,
3272 machopic_function_base_sym ()));
3273 x = gen_rtx_LO_SUM (GET_MODE (x),
3274 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3275 gen_rtx_HIGH (Pmode, offset)), offset);
3279 x = gen_rtx_LO_SUM (GET_MODE (x),
3280 gen_rtx_HIGH (Pmode, x), x);
3282 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3283 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3284 opnum, (enum reload_type)type);
3289 /* Reload an offset address wrapped by an AND that represents the
3290 masking of the lower bits. Strip the outer AND and let reload
3291 convert the offset address into an indirect address. */
3293 && ALTIVEC_VECTOR_MODE (mode)
3294 && GET_CODE (x) == AND
3295 && GET_CODE (XEXP (x, 0)) == PLUS
3296 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3297 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3298 && GET_CODE (XEXP (x, 1)) == CONST_INT
3299 && INTVAL (XEXP (x, 1)) == -16)
3307 && constant_pool_expr_p (x)
3308 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3310 (x) = create_TOC_reference (x);
3318 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3319 that is a valid memory address for an instruction.
3320 The MODE argument is the machine mode for the MEM expression
3321 that wants to use this address.
3323 On the RS/6000, there are four valid address: a SYMBOL_REF that
3324 refers to a constant pool entry of an address (or the sum of it
3325 plus a constant), a short (16-bit signed) constant plus a register,
3326 the sum of two registers, or a register indirect, possibly with an
3327 auto-increment. For DFmode and DImode with a constant plus register,
3328 we must ensure that both words are addressable or PowerPC64 with offset
3331 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3332 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3333 adjacent memory cells are accessed by adding word-sized offsets
3334 during assembly output. */
3336 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3338 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3340 && ALTIVEC_VECTOR_MODE (mode)
3341 && GET_CODE (x) == AND
3342 && GET_CODE (XEXP (x, 1)) == CONST_INT
3343 && INTVAL (XEXP (x, 1)) == -16)
3346 if (RS6000_SYMBOL_REF_TLS_P (x))
3348 if (legitimate_indirect_address_p (x, reg_ok_strict))
3350 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3351 && !ALTIVEC_VECTOR_MODE (mode)
3352 && !SPE_VECTOR_MODE (mode)
3353 /* Restrict addressing for DI because of our SUBREG hackery. */
3354 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3356 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3358 if (rs6000_legitimate_small_data_p (mode, x))
3360 if (legitimate_constant_pool_address_p (x))
3362 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3364 && GET_CODE (x) == PLUS
3365 && GET_CODE (XEXP (x, 0)) == REG
3366 && (XEXP (x, 0) == virtual_stack_vars_rtx
3367 || XEXP (x, 0) == arg_pointer_rtx)
3368 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3370 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3374 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3376 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3377 && (TARGET_POWERPC64 || mode != DImode)
3378 && legitimate_indexed_address_p (x, reg_ok_strict))
3380 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3385 /* Go to LABEL if ADDR (a legitimate address expression)
3386 has an effect that depends on the machine mode it is used for.
3388 On the RS/6000 this is true of all integral offsets (since AltiVec
3389 modes don't allow them) or is a pre-increment or decrement.
3391 ??? Except that due to conceptual problems in offsettable_address_p
3392 we can't really report the problems of integral offsets. So leave
3393 this assuming that the adjustable offset must be valid for the
3394 sub-words of a TFmode operand, which is what we had before. */
3397 rs6000_mode_dependent_address (rtx addr)
3399 switch (GET_CODE (addr))
3402 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3404 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3405 return val + 12 + 0x8000 >= 0x10000;
3414 return TARGET_UPDATE;
3423 /* Return number of consecutive hard regs needed starting at reg REGNO
3424 to hold something of mode MODE.
3425 This is ordinarily the length in words of a value of mode MODE
3426 but can be less for certain modes in special long registers.
3428 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3429 scalar instructions. The upper 32 bits are only available to the
3432 POWER and PowerPC GPRs hold 32 bits worth;
3433 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3436 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3438 if (FP_REGNO_P (regno))
3439 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3441 if (TARGET_E500_DOUBLE && mode == DFmode)
3444 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3445 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3447 if (ALTIVEC_REGNO_P (regno))
3449 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3451 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3454 /* Change register usage conditional on target flags. */
3456 rs6000_conditional_register_usage (void)
3460 /* Set MQ register fixed (already call_used) if not POWER
3461 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3466 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3468 fixed_regs[13] = call_used_regs[13]
3469 = call_really_used_regs[13] = 1;
3471 /* Conditionally disable FPRs. */
3472 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3473 for (i = 32; i < 64; i++)
3474 fixed_regs[i] = call_used_regs[i]
3475 = call_really_used_regs[i] = 1;
3477 /* The TOC register is not killed across calls in a way that is
3478 visible to the compiler. */
3479 if (DEFAULT_ABI == ABI_AIX)
3480 call_really_used_regs[2] = 0;
3482 if (DEFAULT_ABI == ABI_V4
3483 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3485 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3487 if (DEFAULT_ABI == ABI_V4
3488 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3490 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3491 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3492 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3494 if (DEFAULT_ABI == ABI_DARWIN
3495 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3496 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3497 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3498 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3500 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3501 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3502 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3505 global_regs[VSCR_REGNO] = 1;
3509 global_regs[SPEFSCR_REGNO] = 1;
3510 fixed_regs[FIXED_SCRATCH]
3511 = call_used_regs[FIXED_SCRATCH]
3512 = call_really_used_regs[FIXED_SCRATCH] = 1;
3515 if (! TARGET_ALTIVEC)
3517 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3518 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3519 call_really_used_regs[VRSAVE_REGNO] = 1;
3522 if (TARGET_ALTIVEC_ABI)
3523 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3524 call_used_regs[i] = call_really_used_regs[i] = 1;
3527 /* Try to output insns to set TARGET equal to the constant C if it can
3528 be done in less than N insns. Do all computations in MODE.
3529 Returns the place where the output has been placed if it can be
3530 done and the insns have been emitted. If it would take more than N
3531 insns, zero is returned and no insns and emitted. */
3534 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3535 rtx source, int n ATTRIBUTE_UNUSED)
3537 rtx result, insn, set;
3538 HOST_WIDE_INT c0, c1;
3545 dest = gen_reg_rtx (mode);
3546 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3550 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3552 emit_insn (gen_rtx_SET (VOIDmode, result,
3553 GEN_INT (INTVAL (source)
3554 & (~ (HOST_WIDE_INT) 0xffff))));
3555 emit_insn (gen_rtx_SET (VOIDmode, dest,
3556 gen_rtx_IOR (SImode, result,
3557 GEN_INT (INTVAL (source) & 0xffff))));
3562 switch (GET_CODE (source))
3565 c0 = INTVAL (source);
3570 #if HOST_BITS_PER_WIDE_INT >= 64
3571 c0 = CONST_DOUBLE_LOW (source);
3574 c0 = CONST_DOUBLE_LOW (source);
3575 c1 = CONST_DOUBLE_HIGH (source);
3583 result = rs6000_emit_set_long_const (dest, c0, c1);
3590 insn = get_last_insn ();
3591 set = single_set (insn);
3592 if (! CONSTANT_P (SET_SRC (set)))
3593 set_unique_reg_note (insn, REG_EQUAL, source);
3598 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3599 fall back to a straight forward decomposition. We do this to avoid
3600 exponential run times encountered when looking for longer sequences
3601 with rs6000_emit_set_const. */
3603 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3605 if (!TARGET_POWERPC64)
3607 rtx operand1, operand2;
3609 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3611 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3613 emit_move_insn (operand1, GEN_INT (c1));
3614 emit_move_insn (operand2, GEN_INT (c2));
3618 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3621 ud2 = (c1 & 0xffff0000) >> 16;
3622 #if HOST_BITS_PER_WIDE_INT >= 64
3626 ud4 = (c2 & 0xffff0000) >> 16;
3628 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3629 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3632 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3634 emit_move_insn (dest, GEN_INT (ud1));
3637 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3638 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3641 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3644 emit_move_insn (dest, GEN_INT (ud2 << 16));
3646 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3648 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3649 || (ud4 == 0 && ! (ud3 & 0x8000)))
3652 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3655 emit_move_insn (dest, GEN_INT (ud3 << 16));
3658 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3659 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3661 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3666 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3669 emit_move_insn (dest, GEN_INT (ud4 << 16));
3672 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3674 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3676 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3677 GEN_INT (ud2 << 16)));
3679 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3685 /* Helper for the following. Get rid of [r+r] memory refs
3686 in cases where it won't work (TImode, TFmode). */
3689 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3691 if (GET_CODE (operands[0]) == MEM
3692 && GET_CODE (XEXP (operands[0], 0)) != REG
3693 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3694 && ! reload_in_progress)
3696 = replace_equiv_address (operands[0],
3697 copy_addr_to_reg (XEXP (operands[0], 0)));
3699 if (GET_CODE (operands[1]) == MEM
3700 && GET_CODE (XEXP (operands[1], 0)) != REG
3701 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3702 && ! reload_in_progress)
3704 = replace_equiv_address (operands[1],
3705 copy_addr_to_reg (XEXP (operands[1], 0)));
3708 /* Emit a move from SOURCE to DEST in mode MODE. */
3710 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3714 operands[1] = source;
3716 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3717 if (GET_CODE (operands[1]) == CONST_DOUBLE
3718 && ! FLOAT_MODE_P (mode)
3719 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3721 /* FIXME. This should never happen. */
3722 /* Since it seems that it does, do the safe thing and convert
3724 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3726 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3727 || FLOAT_MODE_P (mode)
3728 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3729 || CONST_DOUBLE_LOW (operands[1]) < 0)
3730 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3731 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3733 /* Check if GCC is setting up a block move that will end up using FP
3734 registers as temporaries. We must make sure this is acceptable. */
3735 if (GET_CODE (operands[0]) == MEM
3736 && GET_CODE (operands[1]) == MEM
3738 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3739 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3740 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3741 ? 32 : MEM_ALIGN (operands[0])))
3742 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3744 : MEM_ALIGN (operands[1]))))
3745 && ! MEM_VOLATILE_P (operands [0])
3746 && ! MEM_VOLATILE_P (operands [1]))
3748 emit_move_insn (adjust_address (operands[0], SImode, 0),
3749 adjust_address (operands[1], SImode, 0));
3750 emit_move_insn (adjust_address (operands[0], SImode, 4),
3751 adjust_address (operands[1], SImode, 4));
3755 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3756 && !gpc_reg_operand (operands[1], mode))
3757 operands[1] = force_reg (mode, operands[1]);
3759 if (mode == SFmode && ! TARGET_POWERPC
3760 && TARGET_HARD_FLOAT && TARGET_FPRS
3761 && GET_CODE (operands[0]) == MEM)
3765 if (reload_in_progress || reload_completed)
3766 regnum = true_regnum (operands[1]);
3767 else if (GET_CODE (operands[1]) == REG)
3768 regnum = REGNO (operands[1]);
3772 /* If operands[1] is a register, on POWER it may have
3773 double-precision data in it, so truncate it to single
3775 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3778 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3779 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3780 operands[1] = newreg;
3784 /* Recognize the case where operand[1] is a reference to thread-local
3785 data and load its address to a register. */
3786 if (rs6000_tls_referenced_p (operands[1]))
3788 enum tls_model model;
3789 rtx tmp = operands[1];
3792 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3794 addend = XEXP (XEXP (tmp, 0), 1);
3795 tmp = XEXP (XEXP (tmp, 0), 0);
3798 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3799 model = SYMBOL_REF_TLS_MODEL (tmp);
3800 gcc_assert (model != 0);
3802 tmp = rs6000_legitimize_tls_address (tmp, model);
3805 tmp = gen_rtx_PLUS (mode, tmp, addend);
3806 tmp = force_operand (tmp, operands[0]);
3811 /* Handle the case where reload calls us with an invalid address. */
3812 if (reload_in_progress && mode == Pmode
3813 && (! general_operand (operands[1], mode)
3814 || ! nonimmediate_operand (operands[0], mode)))
3817 /* 128-bit constant floating-point values on Darwin should really be
3818 loaded as two parts. */
3819 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3820 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3821 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3823 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3824 know how to get a DFmode SUBREG of a TFmode. */
3825 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3826 simplify_gen_subreg (DImode, operands[1], mode, 0),
3828 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3829 GET_MODE_SIZE (DImode)),
3830 simplify_gen_subreg (DImode, operands[1], mode,
3831 GET_MODE_SIZE (DImode)),
3836 /* FIXME: In the long term, this switch statement should go away
3837 and be replaced by a sequence of tests based on things like
3843 if (CONSTANT_P (operands[1])
3844 && GET_CODE (operands[1]) != CONST_INT)
3845 operands[1] = force_const_mem (mode, operands[1]);
3849 rs6000_eliminate_indexed_memrefs (operands);
3854 if (CONSTANT_P (operands[1])
3855 && ! easy_fp_constant (operands[1], mode))
3856 operands[1] = force_const_mem (mode, operands[1]);
3867 if (CONSTANT_P (operands[1])
3868 && !easy_vector_constant (operands[1], mode))
3869 operands[1] = force_const_mem (mode, operands[1]);
3874 /* Use default pattern for address of ELF small data */
3877 && DEFAULT_ABI == ABI_V4
3878 && (GET_CODE (operands[1]) == SYMBOL_REF
3879 || GET_CODE (operands[1]) == CONST)
3880 && small_data_operand (operands[1], mode))
3882 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3886 if (DEFAULT_ABI == ABI_V4
3887 && mode == Pmode && mode == SImode
3888 && flag_pic == 1 && got_operand (operands[1], mode))
3890 emit_insn (gen_movsi_got (operands[0], operands[1]));
3894 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3898 && CONSTANT_P (operands[1])
3899 && GET_CODE (operands[1]) != HIGH
3900 && GET_CODE (operands[1]) != CONST_INT)
3902 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3904 /* If this is a function address on -mcall-aixdesc,
3905 convert it to the address of the descriptor. */
3906 if (DEFAULT_ABI == ABI_AIX
3907 && GET_CODE (operands[1]) == SYMBOL_REF
3908 && XSTR (operands[1], 0)[0] == '.')
3910 const char *name = XSTR (operands[1], 0);
3912 while (*name == '.')
3914 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3915 CONSTANT_POOL_ADDRESS_P (new_ref)
3916 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3917 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3918 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3919 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3920 operands[1] = new_ref;
3923 if (DEFAULT_ABI == ABI_DARWIN)
3926 if (MACHO_DYNAMIC_NO_PIC_P)
3928 /* Take care of any required data indirection. */
3929 operands[1] = rs6000_machopic_legitimize_pic_address (
3930 operands[1], mode, operands[0]);
3931 if (operands[0] != operands[1])
3932 emit_insn (gen_rtx_SET (VOIDmode,
3933 operands[0], operands[1]));
3937 emit_insn (gen_macho_high (target, operands[1]));
3938 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3942 emit_insn (gen_elf_high (target, operands[1]));
3943 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3947 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3948 and we have put it in the TOC, we just need to make a TOC-relative
3951 && GET_CODE (operands[1]) == SYMBOL_REF
3952 && constant_pool_expr_p (operands[1])
3953 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3954 get_pool_mode (operands[1])))
3956 operands[1] = create_TOC_reference (operands[1]);
3958 else if (mode == Pmode
3959 && CONSTANT_P (operands[1])
3960 && ((GET_CODE (operands[1]) != CONST_INT
3961 && ! easy_fp_constant (operands[1], mode))
3962 || (GET_CODE (operands[1]) == CONST_INT
3963 && num_insns_constant (operands[1], mode) > 2)
3964 || (GET_CODE (operands[0]) == REG
3965 && FP_REGNO_P (REGNO (operands[0]))))
3966 && GET_CODE (operands[1]) != HIGH
3967 && ! legitimate_constant_pool_address_p (operands[1])
3968 && ! toc_relative_expr_p (operands[1]))
3970 /* Emit a USE operation so that the constant isn't deleted if
3971 expensive optimizations are turned on because nobody
3972 references it. This should only be done for operands that
3973 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3974 This should not be done for operands that contain LABEL_REFs.
3975 For now, we just handle the obvious case. */
3976 if (GET_CODE (operands[1]) != LABEL_REF)
3977 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3980 /* Darwin uses a special PIC legitimizer. */
3981 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3984 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3986 if (operands[0] != operands[1])
3987 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3992 /* If we are to limit the number of things we put in the TOC and
3993 this is a symbol plus a constant we can add in one insn,
3994 just put the symbol in the TOC and add the constant. Don't do
3995 this if reload is in progress. */
3996 if (GET_CODE (operands[1]) == CONST
3997 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3998 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3999 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4000 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4001 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4002 && ! side_effects_p (operands[0]))
4005 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4006 rtx other = XEXP (XEXP (operands[1], 0), 1);
4008 sym = force_reg (mode, sym);
4010 emit_insn (gen_addsi3 (operands[0], sym, other));
4012 emit_insn (gen_adddi3 (operands[0], sym, other));
4016 operands[1] = force_const_mem (mode, operands[1]);
4019 && constant_pool_expr_p (XEXP (operands[1], 0))
4020 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4021 get_pool_constant (XEXP (operands[1], 0)),
4022 get_pool_mode (XEXP (operands[1], 0))))
4025 = gen_const_mem (mode,
4026 create_TOC_reference (XEXP (operands[1], 0)));
4027 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4033 rs6000_eliminate_indexed_memrefs (operands);
4037 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4039 gen_rtx_SET (VOIDmode,
4040 operands[0], operands[1]),
4041 gen_rtx_CLOBBER (VOIDmode,
4042 gen_rtx_SCRATCH (SImode)))));
4051 /* Above, we may have called force_const_mem which may have returned
4052 an invalid address. If we can, fix this up; otherwise, reload will
4053 have to deal with it. */
4054 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4055 operands[1] = validize_mem (operands[1]);
4058 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4061 /* Nonzero if we can use a floating-point register to pass this arg. */
4062 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4063 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4064 && (CUM)->fregno <= FP_ARG_MAX_REG \
4065 && TARGET_HARD_FLOAT && TARGET_FPRS)
4067 /* Nonzero if we can use an AltiVec register to pass this arg. */
4068 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4069 (ALTIVEC_VECTOR_MODE (MODE) \
4070 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4071 && TARGET_ALTIVEC_ABI \
4074 /* Return a nonzero value to say to return the function value in
4075 memory, just as large structures are always returned. TYPE will be
4076 the data type of the value, and FNTYPE will be the type of the
4077 function doing the returning, or @code{NULL} for libcalls.
4079 The AIX ABI for the RS/6000 specifies that all structures are
4080 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4081 specifies that structures <= 8 bytes are returned in r3/r4, but a
4082 draft put them in memory, and GCC used to implement the draft
4083 instead of the final standard. Therefore, aix_struct_return
4084 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4085 compatibility can change DRAFT_V4_STRUCT_RET to override the
4086 default, and -m switches get the final word. See
4087 rs6000_override_options for more details.
4089 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4090 long double support is enabled. These values are returned in memory.
4092 int_size_in_bytes returns -1 for variable size objects, which go in
4093 memory always. The cast to unsigned makes -1 > 8. */
4096 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4098 /* In the darwin64 abi, try to use registers for larger structs
4100 if (rs6000_darwin64_abi
4101 && TREE_CODE (type) == RECORD_TYPE
4102 && int_size_in_bytes (type) > 0)
4104 CUMULATIVE_ARGS valcum;
4108 valcum.fregno = FP_ARG_MIN_REG;
4109 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4110 /* Do a trial code generation as if this were going to be passed
4111 as an argument; if any part goes in memory, we return NULL. */
4112 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4115 /* Otherwise fall through to more conventional ABI rules. */
4118 if (AGGREGATE_TYPE_P (type)
4119 && (aix_struct_return
4120 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4123 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4124 modes only exist for GCC vector types if -maltivec. */
4125 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4126 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4129 /* Return synthetic vectors in memory. */
4130 if (TREE_CODE (type) == VECTOR_TYPE
4131 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4133 static bool warned_for_return_big_vectors = false;
4134 if (!warned_for_return_big_vectors)
4136 warning (0, "GCC vector returned by reference: "
4137 "non-standard ABI extension with no compatibility guarantee");
4138 warned_for_return_big_vectors = true;
4143 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4149 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4150 for a call to a function whose data type is FNTYPE.
4151 For a library call, FNTYPE is 0.
4153 For incoming args we set the number of arguments in the prototype large
4154 so we never return a PARALLEL. */
4157 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4158 rtx libname ATTRIBUTE_UNUSED, int incoming,
4159 int libcall, int n_named_args)
4161 static CUMULATIVE_ARGS zero_cumulative;
4163 *cum = zero_cumulative;
4165 cum->fregno = FP_ARG_MIN_REG;
4166 cum->vregno = ALTIVEC_ARG_MIN_REG;
4167 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4168 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4169 ? CALL_LIBCALL : CALL_NORMAL);
4170 cum->sysv_gregno = GP_ARG_MIN_REG;
4171 cum->stdarg = fntype
4172 && (TYPE_ARG_TYPES (fntype) != 0
4173 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4174 != void_type_node));
4176 cum->nargs_prototype = 0;
4177 if (incoming || cum->prototype)
4178 cum->nargs_prototype = n_named_args;
4180 /* Check for a longcall attribute. */
4181 if ((!fntype && rs6000_default_long_calls)
4183 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4184 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4185 cum->call_cookie |= CALL_LONG;
4187 if (TARGET_DEBUG_ARG)
4189 fprintf (stderr, "\ninit_cumulative_args:");
4192 tree ret_type = TREE_TYPE (fntype);
4193 fprintf (stderr, " ret code = %s,",
4194 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4197 if (cum->call_cookie & CALL_LONG)
4198 fprintf (stderr, " longcall,");
4200 fprintf (stderr, " proto = %d, nargs = %d\n",
4201 cum->prototype, cum->nargs_prototype);
4206 && TARGET_ALTIVEC_ABI
4207 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4209 error ("cannot return value in vector register because"
4210 " altivec instructions are disabled, use -maltivec"
4215 /* Return true if TYPE must be passed on the stack and not in registers. */
4218 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4220 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4221 return must_pass_in_stack_var_size (mode, type);
4223 return must_pass_in_stack_var_size_or_pad (mode, type);
4226 /* If defined, a C expression which determines whether, and in which
4227 direction, to pad out an argument with extra space. The value
4228 should be of type `enum direction': either `upward' to pad above
4229 the argument, `downward' to pad below, or `none' to inhibit
4232 For the AIX ABI structs are always stored left shifted in their
4236 function_arg_padding (enum machine_mode mode, tree type)
4238 #ifndef AGGREGATE_PADDING_FIXED
4239 #define AGGREGATE_PADDING_FIXED 0
4241 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4242 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4245 if (!AGGREGATE_PADDING_FIXED)
4247 /* GCC used to pass structures of the same size as integer types as
4248 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4249 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4250 passed padded downward, except that -mstrict-align further
4251 muddied the water in that multi-component structures of 2 and 4
4252 bytes in size were passed padded upward.
4254 The following arranges for best compatibility with previous
4255 versions of gcc, but removes the -mstrict-align dependency. */
4256 if (BYTES_BIG_ENDIAN)
4258 HOST_WIDE_INT size = 0;
4260 if (mode == BLKmode)
4262 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4263 size = int_size_in_bytes (type);
4266 size = GET_MODE_SIZE (mode);
4268 if (size == 1 || size == 2 || size == 4)
4274 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4276 if (type != 0 && AGGREGATE_TYPE_P (type))
4280 /* Fall back to the default. */
4281 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4284 /* If defined, a C expression that gives the alignment boundary, in bits,
4285 of an argument with the specified mode and type. If it is not defined,
4286 PARM_BOUNDARY is used for all arguments.
4288 V.4 wants long longs to be double word aligned.
4289 Doubleword align SPE vectors.
4290 Quadword align Altivec vectors.
4291 Quadword align large synthetic vector types. */
4294 function_arg_boundary (enum machine_mode mode, tree type)
4296 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4298 else if (SPE_VECTOR_MODE (mode)
4299 || (type && TREE_CODE (type) == VECTOR_TYPE
4300 && int_size_in_bytes (type) >= 8
4301 && int_size_in_bytes (type) < 16))
4303 else if (ALTIVEC_VECTOR_MODE (mode)
4304 || (type && TREE_CODE (type) == VECTOR_TYPE
4305 && int_size_in_bytes (type) >= 16))
4307 else if (rs6000_darwin64_abi && mode == BLKmode
4308 && type && TYPE_ALIGN (type) > 64)
4311 return PARM_BOUNDARY;
4314 /* For a function parm of MODE and TYPE, return the starting word in
4315 the parameter area. NWORDS of the parameter area are already used. */
4318 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4321 unsigned int parm_offset;
4323 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4324 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4325 return nwords + (-(parm_offset + nwords) & align);
4328 /* Compute the size (in words) of a function argument. */
4330 static unsigned long
4331 rs6000_arg_size (enum machine_mode mode, tree type)
4335 if (mode != BLKmode)
4336 size = GET_MODE_SIZE (mode);
4338 size = int_size_in_bytes (type);
4341 return (size + 3) >> 2;
4343 return (size + 7) >> 3;
4346 /* Use this to flush pending int fields. */
4349 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4350 HOST_WIDE_INT bitpos)
4352 unsigned int startbit, endbit;
4353 int intregs, intoffset;
4354 enum machine_mode mode;
4356 if (cum->intoffset == -1)
4359 intoffset = cum->intoffset;
4360 cum->intoffset = -1;
4362 if (intoffset % BITS_PER_WORD != 0)
4364 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4366 if (mode == BLKmode)
4368 /* We couldn't find an appropriate mode, which happens,
4369 e.g., in packed structs when there are 3 bytes to load.
4370 Back intoffset back to the beginning of the word in this
4372 intoffset = intoffset & -BITS_PER_WORD;
4376 startbit = intoffset & -BITS_PER_WORD;
4377 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4378 intregs = (endbit - startbit) / BITS_PER_WORD;
4379 cum->words += intregs;
4382 /* The darwin64 ABI calls for us to recurse down through structs,
4383 looking for elements passed in registers. Unfortunately, we have
4384 to track int register count here also because of misalignments
4385 in powerpc alignment mode. */
4388 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4390 HOST_WIDE_INT startbitpos)
4394 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4395 if (TREE_CODE (f) == FIELD_DECL)
4397 HOST_WIDE_INT bitpos = startbitpos;
4398 tree ftype = TREE_TYPE (f);
4399 enum machine_mode mode = TYPE_MODE (ftype);
4401 if (DECL_SIZE (f) != 0
4402 && host_integerp (bit_position (f), 1))
4403 bitpos += int_bit_position (f);
4405 /* ??? FIXME: else assume zero offset. */
4407 if (TREE_CODE (ftype) == RECORD_TYPE)
4408 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4409 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4411 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4412 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4413 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4415 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4417 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4421 else if (cum->intoffset == -1)
4422 cum->intoffset = bitpos;
4426 /* Update the data in CUM to advance over an argument
4427 of mode MODE and data type TYPE.
4428 (TYPE is null for libcalls where that information may not be available.)
4430 Note that for args passed by reference, function_arg will be called
4431 with MODE and TYPE set to that of the pointer to the arg, not the arg
4435 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4436 tree type, int named, int depth)
4440 /* Only tick off an argument if we're not recursing. */
4442 cum->nargs_prototype--;
4444 if (TARGET_ALTIVEC_ABI
4445 && (ALTIVEC_VECTOR_MODE (mode)
4446 || (type && TREE_CODE (type) == VECTOR_TYPE
4447 && int_size_in_bytes (type) == 16)))
4451 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4454 if (!TARGET_ALTIVEC)
4455 error ("cannot pass argument in vector register because"
4456 " altivec instructions are disabled, use -maltivec"
4459 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4460 even if it is going to be passed in a vector register.
4461 Darwin does the same for variable-argument functions. */
4462 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4463 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4473 /* Vector parameters must be 16-byte aligned. This places
4474 them at 2 mod 4 in terms of words in 32-bit mode, since
4475 the parameter save area starts at offset 24 from the
4476 stack. In 64-bit mode, they just have to start on an
4477 even word, since the parameter save area is 16-byte
4478 aligned. Space for GPRs is reserved even if the argument
4479 will be passed in memory. */
4481 align = (2 - cum->words) & 3;
4483 align = cum->words & 1;
4484 cum->words += align + rs6000_arg_size (mode, type);
4486 if (TARGET_DEBUG_ARG)
4488 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4490 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4491 cum->nargs_prototype, cum->prototype,
4492 GET_MODE_NAME (mode));
4496 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4498 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4501 else if (rs6000_darwin64_abi
4503 && TREE_CODE (type) == RECORD_TYPE
4504 && (size = int_size_in_bytes (type)) > 0)
4506 /* Variable sized types have size == -1 and are
4507 treated as if consisting entirely of ints.
4508 Pad to 16 byte boundary if needed. */
4509 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4510 && (cum->words % 2) != 0)
4512 /* For varargs, we can just go up by the size of the struct. */
4514 cum->words += (size + 7) / 8;
4517 /* It is tempting to say int register count just goes up by
4518 sizeof(type)/8, but this is wrong in a case such as
4519 { int; double; int; } [powerpc alignment]. We have to
4520 grovel through the fields for these too. */
4522 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4523 rs6000_darwin64_record_arg_advance_flush (cum,
4524 size * BITS_PER_UNIT);
4527 else if (DEFAULT_ABI == ABI_V4)
4529 if (TARGET_HARD_FLOAT && TARGET_FPRS
4530 && (mode == SFmode || mode == DFmode))
4532 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4537 cum->words += cum->words & 1;
4538 cum->words += rs6000_arg_size (mode, type);
4543 int n_words = rs6000_arg_size (mode, type);
4544 int gregno = cum->sysv_gregno;
4546 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4547 (r7,r8) or (r9,r10). As does any other 2 word item such
4548 as complex int due to a historical mistake. */
4550 gregno += (1 - gregno) & 1;
4552 /* Multi-reg args are not split between registers and stack. */
4553 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4555 /* Long long and SPE vectors are aligned on the stack.
4556 So are other 2 word items such as complex int due to
4557 a historical mistake. */
4559 cum->words += cum->words & 1;
4560 cum->words += n_words;
4563 /* Note: continuing to accumulate gregno past when we've started
4564 spilling to the stack indicates the fact that we've started
4565 spilling to the stack to expand_builtin_saveregs. */
4566 cum->sysv_gregno = gregno + n_words;
4569 if (TARGET_DEBUG_ARG)
4571 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4572 cum->words, cum->fregno);
4573 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4574 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4575 fprintf (stderr, "mode = %4s, named = %d\n",
4576 GET_MODE_NAME (mode), named);
4581 int n_words = rs6000_arg_size (mode, type);
4582 int start_words = cum->words;
4583 int align_words = rs6000_parm_start (mode, type, start_words);
4585 cum->words = align_words + n_words;
4587 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4588 && TARGET_HARD_FLOAT && TARGET_FPRS)
4589 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4591 if (TARGET_DEBUG_ARG)
4593 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4594 cum->words, cum->fregno);
4595 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4596 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4597 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4598 named, align_words - start_words, depth);
4604 spe_build_register_parallel (enum machine_mode mode, int gregno)
4611 r1 = gen_rtx_REG (DImode, gregno);
4612 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4613 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4616 r1 = gen_rtx_REG (DImode, gregno);
4617 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4618 r3 = gen_rtx_REG (DImode, gregno + 2);
4619 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4620 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4627 /* Determine where to put a SIMD argument on the SPE. */
4629 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4632 int gregno = cum->sysv_gregno;
4634 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4635 are passed and returned in a pair of GPRs for ABI compatibility. */
4636 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4638 int n_words = rs6000_arg_size (mode, type);
4640 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4642 gregno += (1 - gregno) & 1;
4644 /* Multi-reg args are not split between registers and stack. */
4645 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4648 return spe_build_register_parallel (mode, gregno);
4652 int n_words = rs6000_arg_size (mode, type);
4654 /* SPE vectors are put in odd registers. */
4655 if (n_words == 2 && (gregno & 1) == 0)
4658 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4661 enum machine_mode m = SImode;
4663 r1 = gen_rtx_REG (m, gregno);
4664 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4665 r2 = gen_rtx_REG (m, gregno + 1);
4666 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4667 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4674 if (gregno <= GP_ARG_MAX_REG)
4675 return gen_rtx_REG (mode, gregno);
4681 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4682 structure between cum->intoffset and bitpos to integer registers. */
4685 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4686 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4688 enum machine_mode mode;
4690 unsigned int startbit, endbit;
4691 int this_regno, intregs, intoffset;
4694 if (cum->intoffset == -1)
4697 intoffset = cum->intoffset;
4698 cum->intoffset = -1;
4700 /* If this is the trailing part of a word, try to only load that
4701 much into the register. Otherwise load the whole register. Note
4702 that in the latter case we may pick up unwanted bits. It's not a
4703 problem at the moment but may wish to revisit. */
4705 if (intoffset % BITS_PER_WORD != 0)
4707 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4709 if (mode == BLKmode)
4711 /* We couldn't find an appropriate mode, which happens,
4712 e.g., in packed structs when there are 3 bytes to load.
4713 Back intoffset back to the beginning of the word in this
4715 intoffset = intoffset & -BITS_PER_WORD;
4722 startbit = intoffset & -BITS_PER_WORD;
4723 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4724 intregs = (endbit - startbit) / BITS_PER_WORD;
4725 this_regno = cum->words + intoffset / BITS_PER_WORD;
4727 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4730 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4734 intoffset /= BITS_PER_UNIT;
4737 regno = GP_ARG_MIN_REG + this_regno;
4738 reg = gen_rtx_REG (mode, regno);
4740 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4743 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4747 while (intregs > 0);
4750 /* Recursive workhorse for the following. */
4753 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4754 HOST_WIDE_INT startbitpos, rtx rvec[],
4759 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4760 if (TREE_CODE (f) == FIELD_DECL)
4762 HOST_WIDE_INT bitpos = startbitpos;
4763 tree ftype = TREE_TYPE (f);
4764 enum machine_mode mode = TYPE_MODE (ftype);
4766 if (DECL_SIZE (f) != 0
4767 && host_integerp (bit_position (f), 1))
4768 bitpos += int_bit_position (f);
4770 /* ??? FIXME: else assume zero offset. */
4772 if (TREE_CODE (ftype) == RECORD_TYPE)
4773 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4774 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4779 case SCmode: mode = SFmode; break;
4780 case DCmode: mode = DFmode; break;
4781 case TCmode: mode = TFmode; break;
4785 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4787 = gen_rtx_EXPR_LIST (VOIDmode,
4788 gen_rtx_REG (mode, cum->fregno++),
4789 GEN_INT (bitpos / BITS_PER_UNIT));
4793 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4795 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4797 = gen_rtx_EXPR_LIST (VOIDmode,
4798 gen_rtx_REG (mode, cum->vregno++),
4799 GEN_INT (bitpos / BITS_PER_UNIT));
4801 else if (cum->intoffset == -1)
4802 cum->intoffset = bitpos;
4806 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4807 the register(s) to be used for each field and subfield of a struct
4808 being passed by value, along with the offset of where the
4809 register's value may be found in the block. FP fields go in FP
4810 register, vector fields go in vector registers, and everything
4811 else goes in int registers, packed as in memory.
4813 This code is also used for function return values. RETVAL indicates
4814 whether this is the case.
4816 Much of this is taken from the SPARC V9 port, which has a similar
4817 calling convention. */
4820 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4821 int named, bool retval)
4823 rtx rvec[FIRST_PSEUDO_REGISTER];
4824 int k = 1, kbase = 1;
4825 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4826 /* This is a copy; modifications are not visible to our caller. */
4827 CUMULATIVE_ARGS copy_cum = *orig_cum;
4828 CUMULATIVE_ARGS *cum = ©_cum;
4830 /* Pad to 16 byte boundary if needed. */
4831 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4832 && (cum->words % 2) != 0)
4839 /* Put entries into rvec[] for individual FP and vector fields, and
4840 for the chunks of memory that go in int regs. Note we start at
4841 element 1; 0 is reserved for an indication of using memory, and
4842 may or may not be filled in below. */
4843 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4844 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4846 /* If any part of the struct went on the stack put all of it there.
4847 This hack is because the generic code for
4848 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4849 parts of the struct are not at the beginning. */
4853 return NULL_RTX; /* doesn't go in registers at all */
4855 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4857 if (k > 1 || cum->use_stack)
4858 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4863 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4866 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4870 rtx rvec[GP_ARG_NUM_REG + 1];
4872 if (align_words >= GP_ARG_NUM_REG)
4875 n_units = rs6000_arg_size (mode, type);
4877 /* Optimize the simple case where the arg fits in one gpr, except in
4878 the case of BLKmode due to assign_parms assuming that registers are
4879 BITS_PER_WORD wide. */
4881 || (n_units == 1 && mode != BLKmode))
4882 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4885 if (align_words + n_units > GP_ARG_NUM_REG)
4886 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4887 using a magic NULL_RTX component.
4888 FIXME: This is not strictly correct. Only some of the arg
4889 belongs in memory, not all of it. However, there isn't any way
4890 to do this currently, apart from building rtx descriptions for
4891 the pieces of memory we want stored. Due to bugs in the generic
4892 code we can't use the normal function_arg_partial_nregs scheme
4893 with the PARALLEL arg description we emit here.
4894 In any case, the code to store the whole arg to memory is often
4895 more efficient than code to store pieces, and we know that space
4896 is available in the right place for the whole arg. */
4897 /* FIXME: This should be fixed since the conversion to
4898 TARGET_ARG_PARTIAL_BYTES. */
4899 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4904 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4905 rtx off = GEN_INT (i++ * 4);
4906 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4908 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4910 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4913 /* Determine where to put an argument to a function.
4914 Value is zero to push the argument on the stack,
4915 or a hard register in which to store the argument.
4917 MODE is the argument's machine mode.
4918 TYPE is the data type of the argument (as a tree).
4919 This is null for libcalls where that information may
4921 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4922 the preceding args and about the function being called. It is
4923 not modified in this routine.
4924 NAMED is nonzero if this argument is a named parameter
4925 (otherwise it is an extra parameter matching an ellipsis).
4927 On RS/6000 the first eight words of non-FP are normally in registers
4928 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4929 Under V.4, the first 8 FP args are in registers.
4931 If this is floating-point and no prototype is specified, we use
4932 both an FP and integer register (or possibly FP reg and stack). Library
4933 functions (when CALL_LIBCALL is set) always have the proper types for args,
4934 so we can pass the FP value just in one register. emit_library_function
4935 doesn't support PARALLEL anyway.
4937 Note that for args passed by reference, function_arg will be called
4938 with MODE and TYPE set to that of the pointer to the arg, not the arg
4942 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4943 tree type, int named)
4945 enum rs6000_abi abi = DEFAULT_ABI;
4947 /* Return a marker to indicate whether CR1 needs to set or clear the
4948 bit that V.4 uses to say fp args were passed in registers.
4949 Assume that we don't need the marker for software floating point,
4950 or compiler generated library calls. */
4951 if (mode == VOIDmode)
4954 && (cum->call_cookie & CALL_LIBCALL) == 0
4956 || (cum->nargs_prototype < 0
4957 && (cum->prototype || TARGET_NO_PROTOTYPE))))
4959 /* For the SPE, we need to crxor CR6 always. */
4961 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4962 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4963 return GEN_INT (cum->call_cookie
4964 | ((cum->fregno == FP_ARG_MIN_REG)
4965 ? CALL_V4_SET_FP_ARGS
4966 : CALL_V4_CLEAR_FP_ARGS));
4969 return GEN_INT (cum->call_cookie);
4972 if (rs6000_darwin64_abi && mode == BLKmode
4973 && TREE_CODE (type) == RECORD_TYPE)
4975 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4976 if (rslt != NULL_RTX)
4978 /* Else fall through to usual handling. */
4981 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4982 if (TARGET_64BIT && ! cum->prototype)
4984 /* Vector parameters get passed in vector register
4985 and also in GPRs or memory, in absence of prototype. */
4988 align_words = (cum->words + 1) & ~1;
4990 if (align_words >= GP_ARG_NUM_REG)
4996 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4998 return gen_rtx_PARALLEL (mode,
5000 gen_rtx_EXPR_LIST (VOIDmode,
5002 gen_rtx_EXPR_LIST (VOIDmode,
5003 gen_rtx_REG (mode, cum->vregno),
5007 return gen_rtx_REG (mode, cum->vregno);
5008 else if (TARGET_ALTIVEC_ABI
5009 && (ALTIVEC_VECTOR_MODE (mode)
5010 || (type && TREE_CODE (type) == VECTOR_TYPE
5011 && int_size_in_bytes (type) == 16)))
5013 if (named || abi == ABI_V4)
5017 /* Vector parameters to varargs functions under AIX or Darwin
5018 get passed in memory and possibly also in GPRs. */
5019 int align, align_words, n_words;
5020 enum machine_mode part_mode;
5022 /* Vector parameters must be 16-byte aligned. This places them at
5023 2 mod 4 in terms of words in 32-bit mode, since the parameter
5024 save area starts at offset 24 from the stack. In 64-bit mode,
5025 they just have to start on an even word, since the parameter
5026 save area is 16-byte aligned. */
5028 align = (2 - cum->words) & 3;
5030 align = cum->words & 1;
5031 align_words = cum->words + align;
5033 /* Out of registers? Memory, then. */
5034 if (align_words >= GP_ARG_NUM_REG)
5037 if (TARGET_32BIT && TARGET_POWERPC64)
5038 return rs6000_mixed_function_arg (mode, type, align_words);
5040 /* The vector value goes in GPRs. Only the part of the
5041 value in GPRs is reported here. */
5043 n_words = rs6000_arg_size (mode, type);
5044 if (align_words + n_words > GP_ARG_NUM_REG)
5045 /* Fortunately, there are only two possibilities, the value
5046 is either wholly in GPRs or half in GPRs and half not. */
5049 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5052 else if (TARGET_SPE_ABI && TARGET_SPE
5053 && (SPE_VECTOR_MODE (mode)
5054 || (TARGET_E500_DOUBLE && (mode == DFmode
5055 || mode == DCmode))))
5056 return rs6000_spe_function_arg (cum, mode, type);
5058 else if (abi == ABI_V4)
5060 if (TARGET_HARD_FLOAT && TARGET_FPRS
5061 && (mode == SFmode || mode == DFmode))
5063 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5064 return gen_rtx_REG (mode, cum->fregno);
5070 int n_words = rs6000_arg_size (mode, type);
5071 int gregno = cum->sysv_gregno;
5073 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5074 (r7,r8) or (r9,r10). As does any other 2 word item such
5075 as complex int due to a historical mistake. */
5077 gregno += (1 - gregno) & 1;
5079 /* Multi-reg args are not split between registers and stack. */
5080 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5083 if (TARGET_32BIT && TARGET_POWERPC64)
5084 return rs6000_mixed_function_arg (mode, type,
5085 gregno - GP_ARG_MIN_REG);
5086 return gen_rtx_REG (mode, gregno);
5091 int align_words = rs6000_parm_start (mode, type, cum->words);
5093 if (USE_FP_FOR_ARG_P (cum, mode, type))
5095 rtx rvec[GP_ARG_NUM_REG + 1];
5099 enum machine_mode fmode = mode;
5100 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5102 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5104 /* Currently, we only ever need one reg here because complex
5105 doubles are split. */
5106 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5108 /* Long double split over regs and memory. */
5112 /* Do we also need to pass this arg in the parameter save
5115 && (cum->nargs_prototype <= 0
5116 || (DEFAULT_ABI == ABI_AIX
5118 && align_words >= GP_ARG_NUM_REG)));
5120 if (!needs_psave && mode == fmode)
5121 return gen_rtx_REG (fmode, cum->fregno);
5126 /* Describe the part that goes in gprs or the stack.
5127 This piece must come first, before the fprs. */
5128 if (align_words < GP_ARG_NUM_REG)
5130 unsigned long n_words = rs6000_arg_size (mode, type);
5132 if (align_words + n_words > GP_ARG_NUM_REG
5133 || (TARGET_32BIT && TARGET_POWERPC64))
5135 /* If this is partially on the stack, then we only
5136 include the portion actually in registers here. */
5137 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5140 if (align_words + n_words > GP_ARG_NUM_REG
5141 && (TARGET_32BIT && TARGET_POWERPC64))
5142 /* Not all of the arg fits in gprs. Say that it
5143 goes in memory too, using a magic NULL_RTX
5144 component. Also see comment in
5145 rs6000_mixed_function_arg for why the normal
5146 function_arg_partial_nregs scheme doesn't work
5148 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5152 r = gen_rtx_REG (rmode,
5153 GP_ARG_MIN_REG + align_words);
5154 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5155 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5157 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5161 /* The whole arg fits in gprs. */
5162 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5163 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5167 /* It's entirely in memory. */
5168 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5171 /* Describe where this piece goes in the fprs. */
5172 r = gen_rtx_REG (fmode, cum->fregno);
5173 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5175 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5177 else if (align_words < GP_ARG_NUM_REG)
5179 if (TARGET_32BIT && TARGET_POWERPC64)
5180 return rs6000_mixed_function_arg (mode, type, align_words);
5182 if (mode == BLKmode)
5185 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5192 /* For an arg passed partly in registers and partly in memory, this is
5193 the number of bytes passed in registers. For args passed entirely in
5194 registers or entirely in memory, zero. When an arg is described by a
5195 PARALLEL, perhaps using more than one register type, this function
5196 returns the number of bytes used by the first element of the PARALLEL. */
5199 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5200 tree type, bool named)
5205 if (DEFAULT_ABI == ABI_V4)
5208 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5209 && cum->nargs_prototype >= 0)
5212 /* In this complicated case we just disable the partial_nregs code. */
5213 if (rs6000_darwin64_abi && mode == BLKmode
5214 && TREE_CODE (type) == RECORD_TYPE
5215 && int_size_in_bytes (type) > 0)
5218 align_words = rs6000_parm_start (mode, type, cum->words);
5220 if (USE_FP_FOR_ARG_P (cum, mode, type)
5221 /* If we are passing this arg in the fixed parameter save area
5222 (gprs or memory) as well as fprs, then this function should
5223 return the number of bytes passed in the parameter save area
5224 rather than bytes passed in fprs. */
5226 && (cum->nargs_prototype <= 0
5227 || (DEFAULT_ABI == ABI_AIX
5229 && align_words >= GP_ARG_NUM_REG))))
5231 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5232 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5233 else if (cum->nargs_prototype >= 0)
5237 if (align_words < GP_ARG_NUM_REG
5238 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5239 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5241 if (ret != 0 && TARGET_DEBUG_ARG)
5242 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5247 /* A C expression that indicates when an argument must be passed by
5248 reference. If nonzero for an argument, a copy of that argument is
5249 made in memory and a pointer to the argument is passed instead of
5250 the argument itself. The pointer is passed in whatever way is
5251 appropriate for passing a pointer to that type.
5253 Under V.4, aggregates and long double are passed by reference.
5255 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5256 reference unless the AltiVec vector extension ABI is in force.
5258 As an extension to all ABIs, variable sized types are passed by
5262 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5263 enum machine_mode mode, tree type,
5264 bool named ATTRIBUTE_UNUSED)
5266 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5268 if (TARGET_DEBUG_ARG)
5269 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5276 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5278 if (TARGET_DEBUG_ARG)
5279 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5283 if (int_size_in_bytes (type) < 0)
5285 if (TARGET_DEBUG_ARG)
5286 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5290 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5291 modes only exist for GCC vector types if -maltivec. */
5292 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5294 if (TARGET_DEBUG_ARG)
5295 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5299 /* Pass synthetic vectors in memory. */
5300 if (TREE_CODE (type) == VECTOR_TYPE
5301 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5303 static bool warned_for_pass_big_vectors = false;
5304 if (TARGET_DEBUG_ARG)
5305 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5306 if (!warned_for_pass_big_vectors)
5308 warning (0, "GCC vector passed by reference: "
5309 "non-standard ABI extension with no compatibility guarantee");
5310 warned_for_pass_big_vectors = true;
5319 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5322 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5327 for (i = 0; i < nregs; i++)
5329 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5330 if (reload_completed)
5332 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5335 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5336 i * GET_MODE_SIZE (reg_mode));
5339 tem = replace_equiv_address (tem, XEXP (tem, 0));
5343 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5347 /* Perform any needed actions needed for a function that is receiving a
5348 variable number of arguments.
5352 MODE and TYPE are the mode and type of the current parameter.
5354 PRETEND_SIZE is a variable that should be set to the amount of stack
5355 that must be pushed by the prolog to pretend that our caller pushed
5358 Normally, this macro will push all remaining incoming registers on the
5359 stack and set PRETEND_SIZE to the length of the registers pushed. */
5362 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5363 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5366 CUMULATIVE_ARGS next_cum;
5367 int reg_size = TARGET_32BIT ? 4 : 8;
5368 rtx save_area = NULL_RTX, mem;
5369 int first_reg_offset, set;
5371 /* Skip the last named argument. */
5373 function_arg_advance (&next_cum, mode, type, 1, 0);
5375 if (DEFAULT_ABI == ABI_V4)
5377 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5381 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5382 HOST_WIDE_INT offset = 0;
5384 /* Try to optimize the size of the varargs save area.
5385 The ABI requires that ap.reg_save_area is doubleword
5386 aligned, but we don't need to allocate space for all
5387 the bytes, only those to which we actually will save
5389 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5390 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5391 if (TARGET_HARD_FLOAT && TARGET_FPRS
5392 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5393 && cfun->va_list_fpr_size)
5396 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5397 * UNITS_PER_FP_WORD;
5398 if (cfun->va_list_fpr_size
5399 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5400 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5402 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5403 * UNITS_PER_FP_WORD;
5407 offset = -((first_reg_offset * reg_size) & ~7);
5408 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5410 gpr_reg_num = cfun->va_list_gpr_size;
5411 if (reg_size == 4 && (first_reg_offset & 1))
5414 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5417 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5419 - (int) (GP_ARG_NUM_REG * reg_size);
5421 if (gpr_size + fpr_size)
5424 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5425 gcc_assert (GET_CODE (reg_save_area) == MEM);
5426 reg_save_area = XEXP (reg_save_area, 0);
5427 if (GET_CODE (reg_save_area) == PLUS)
5429 gcc_assert (XEXP (reg_save_area, 0)
5430 == virtual_stack_vars_rtx);
5431 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5432 offset += INTVAL (XEXP (reg_save_area, 1));
5435 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5438 cfun->machine->varargs_save_offset = offset;
5439 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5444 first_reg_offset = next_cum.words;
5445 save_area = virtual_incoming_args_rtx;
5447 if (targetm.calls.must_pass_in_stack (mode, type))
5448 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5451 set = get_varargs_alias_set ();
5452 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5453 && cfun->va_list_gpr_size)
5455 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5457 if (va_list_gpr_counter_field)
5459 /* V4 va_list_gpr_size counts number of registers needed. */
5460 if (nregs > cfun->va_list_gpr_size)
5461 nregs = cfun->va_list_gpr_size;
5465 /* char * va_list instead counts number of bytes needed. */
5466 if (nregs > cfun->va_list_gpr_size / reg_size)
5467 nregs = cfun->va_list_gpr_size / reg_size;
5470 mem = gen_rtx_MEM (BLKmode,
5471 plus_constant (save_area,
5472 first_reg_offset * reg_size));
5473 MEM_NOTRAP_P (mem) = 1;
5474 set_mem_alias_set (mem, set);
5475 set_mem_align (mem, BITS_PER_WORD);
5477 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5481 /* Save FP registers if needed. */
5482 if (DEFAULT_ABI == ABI_V4
5483 && TARGET_HARD_FLOAT && TARGET_FPRS
5485 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5486 && cfun->va_list_fpr_size)
5488 int fregno = next_cum.fregno, nregs;
5489 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5490 rtx lab = gen_label_rtx ();
5491 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5492 * UNITS_PER_FP_WORD);
5495 (gen_rtx_SET (VOIDmode,
5497 gen_rtx_IF_THEN_ELSE (VOIDmode,
5498 gen_rtx_NE (VOIDmode, cr1,
5500 gen_rtx_LABEL_REF (VOIDmode, lab),
5504 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5505 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5507 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5508 MEM_NOTRAP_P (mem) = 1;
5509 set_mem_alias_set (mem, set);
5510 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5511 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5518 /* Create the va_list data type. */
5521 rs6000_build_builtin_va_list (void)
5523 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5525 /* For AIX, prefer 'char *' because that's what the system
5526 header files like. */
5527 if (DEFAULT_ABI != ABI_V4)
5528 return build_pointer_type (char_type_node);
5530 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5531 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5533 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5534 unsigned_char_type_node);
5535 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5536 unsigned_char_type_node);
5537 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5539 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5540 short_unsigned_type_node);
5541 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5543 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5546 va_list_gpr_counter_field = f_gpr;
5547 va_list_fpr_counter_field = f_fpr;
5549 DECL_FIELD_CONTEXT (f_gpr) = record;
5550 DECL_FIELD_CONTEXT (f_fpr) = record;
5551 DECL_FIELD_CONTEXT (f_res) = record;
5552 DECL_FIELD_CONTEXT (f_ovf) = record;
5553 DECL_FIELD_CONTEXT (f_sav) = record;
5555 TREE_CHAIN (record) = type_decl;
5556 TYPE_NAME (record) = type_decl;
5557 TYPE_FIELDS (record) = f_gpr;
5558 TREE_CHAIN (f_gpr) = f_fpr;
5559 TREE_CHAIN (f_fpr) = f_res;
5560 TREE_CHAIN (f_res) = f_ovf;
5561 TREE_CHAIN (f_ovf) = f_sav;
5563 layout_type (record);
5565 /* The correct type is an array type of one element. */
5566 return build_array_type (record, build_index_type (size_zero_node));
5569 /* Implement va_start. */
5572 rs6000_va_start (tree valist, rtx nextarg)
5574 HOST_WIDE_INT words, n_gpr, n_fpr;
5575 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5576 tree gpr, fpr, ovf, sav, t;
5578 /* Only SVR4 needs something special. */
5579 if (DEFAULT_ABI != ABI_V4)
5581 std_expand_builtin_va_start (valist, nextarg);
5585 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5586 f_fpr = TREE_CHAIN (f_gpr);
5587 f_res = TREE_CHAIN (f_fpr);
5588 f_ovf = TREE_CHAIN (f_res);
5589 f_sav = TREE_CHAIN (f_ovf);
5591 valist = build_va_arg_indirect_ref (valist);
5592 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5593 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5594 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5595 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5597 /* Count number of gp and fp argument registers used. */
5598 words = current_function_args_info.words;
5599 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5601 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5604 if (TARGET_DEBUG_ARG)
5605 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5606 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5607 words, n_gpr, n_fpr);
5609 if (cfun->va_list_gpr_size)
5611 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5612 build_int_cst (NULL_TREE, n_gpr));
5613 TREE_SIDE_EFFECTS (t) = 1;
5614 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5617 if (cfun->va_list_fpr_size)
5619 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5620 build_int_cst (NULL_TREE, n_fpr));
5621 TREE_SIDE_EFFECTS (t) = 1;
5622 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5625 /* Find the overflow area. */
5626 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5628 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5629 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5630 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5631 TREE_SIDE_EFFECTS (t) = 1;
5632 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5634 /* If there were no va_arg invocations, don't set up the register
5636 if (!cfun->va_list_gpr_size
5637 && !cfun->va_list_fpr_size
5638 && n_gpr < GP_ARG_NUM_REG
5639 && n_fpr < FP_ARG_V4_MAX_REG)
5642 /* Find the register save area. */
5643 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5644 if (cfun->machine->varargs_save_offset)
5645 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5646 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5647 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5648 TREE_SIDE_EFFECTS (t) = 1;
5649 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5652 /* Implement va_arg. */
5655 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5657 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5658 tree gpr, fpr, ovf, sav, reg, t, u;
5659 int size, rsize, n_reg, sav_ofs, sav_scale;
5660 tree lab_false, lab_over, addr;
5662 tree ptrtype = build_pointer_type (type);
5664 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5666 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5667 return build_va_arg_indirect_ref (t);
5670 if (DEFAULT_ABI != ABI_V4)
5672 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5674 tree elem_type = TREE_TYPE (type);
5675 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5676 int elem_size = GET_MODE_SIZE (elem_mode);
5678 if (elem_size < UNITS_PER_WORD)
5680 tree real_part, imag_part;
5681 tree post = NULL_TREE;
5683 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5685 /* Copy the value into a temporary, lest the formal temporary
5686 be reused out from under us. */
5687 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5688 append_to_statement_list (post, pre_p);
5690 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5693 return build (COMPLEX_EXPR, type, real_part, imag_part);
5697 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5700 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5701 f_fpr = TREE_CHAIN (f_gpr);
5702 f_res = TREE_CHAIN (f_fpr);
5703 f_ovf = TREE_CHAIN (f_res);
5704 f_sav = TREE_CHAIN (f_ovf);
5706 valist = build_va_arg_indirect_ref (valist);
5707 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5708 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5709 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5710 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5712 size = int_size_in_bytes (type);
5713 rsize = (size + 3) / 4;
5716 if (TARGET_HARD_FLOAT && TARGET_FPRS
5717 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5719 /* FP args go in FP registers, if present. */
5724 if (TYPE_MODE (type) == DFmode)
5729 /* Otherwise into GP registers. */
5738 /* Pull the value out of the saved registers.... */
5741 addr = create_tmp_var (ptr_type_node, "addr");
5742 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5744 /* AltiVec vectors never go in registers when -mabi=altivec. */
5745 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5749 lab_false = create_artificial_label ();
5750 lab_over = create_artificial_label ();
5752 /* Long long and SPE vectors are aligned in the registers.
5753 As are any other 2 gpr item such as complex int due to a
5754 historical mistake. */
5758 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5759 size_int (n_reg - 1));
5760 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5763 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5764 t = build2 (GE_EXPR, boolean_type_node, u, t);
5765 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5766 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5767 gimplify_and_add (t, pre_p);
5771 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5773 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5774 u = build1 (CONVERT_EXPR, integer_type_node, u);
5775 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5776 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5778 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5779 gimplify_and_add (t, pre_p);
5781 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5782 gimplify_and_add (t, pre_p);
5784 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5785 append_to_statement_list (t, pre_p);
5789 /* Ensure that we don't find any more args in regs.
5790 Alignment has taken care of the n_reg == 2 case. */
5791 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5792 gimplify_and_add (t, pre_p);
5796 /* ... otherwise out of the overflow area. */
5798 /* Care for on-stack alignment if needed. */
5802 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5803 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5804 build_int_cst (NULL_TREE, -align));
5806 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5808 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5809 gimplify_and_add (u, pre_p);
5811 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5812 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5813 gimplify_and_add (t, pre_p);
5817 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5818 append_to_statement_list (t, pre_p);
5821 addr = fold_convert (ptrtype, addr);
5822 return build_va_arg_indirect_ref (addr);
5828 def_builtin (int mask, const char *name, tree type, int code)
5830 if (mask & target_flags)
5832 if (rs6000_builtin_decls[code])
5835 rs6000_builtin_decls[code] =
5836 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5841 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5843 static const struct builtin_description bdesc_3arg[] =
5845 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5846 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5847 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5848 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5849 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5850 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5851 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5852 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5853 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5854 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5855 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5856 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5857 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5858 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5859 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5860 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5861 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5862 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5863 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5864 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5865 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5866 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5867 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5886 /* DST operations: void foo (void *, const int, const char). */
5888 static const struct builtin_description bdesc_dst[] =
5890 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5891 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5892 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5901 /* Simple binary operations: VECc = foo (VECa, VECb). */
5903 static struct builtin_description bdesc_2arg[] =
5905 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5906 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5907 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5908 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5909 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5910 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5911 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5912 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5913 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5914 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5915 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5916 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5917 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5918 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5919 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5920 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5921 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5922 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5923 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5924 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5925 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5926 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5927 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5928 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5929 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5930 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5931 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5932 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5933 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5937 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5938 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5939 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5940 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5941 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5942 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5943 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5944 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5945 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5946 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5947 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5948 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5949 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5950 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5951 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5952 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5953 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5954 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5955 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5956 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5957 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5958 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5959 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5960 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5961 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5962 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5963 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5964 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5965 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5966 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5967 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5968 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5969 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5970 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5971 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5972 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5973 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5974 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5975 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5976 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5977 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5978 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5979 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5980 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5981 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5984 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5985 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5986 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5987 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5988 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5989 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5990 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5993 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5994 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5995 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5996 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5997 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5998 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5999 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6000 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6001 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6002 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6003 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6004 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6013 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6014 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6017 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6019 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6020 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6021 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6022 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6023 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6024 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6025 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6026 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6027 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6028 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6029 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6030 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6031 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6032 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6033 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6034 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6035 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6036 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6037 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6038 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6039 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6040 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6041 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6042 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6043 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6044 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6045 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6046 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6047 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6048 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6049 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6050 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6051 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6052 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6053 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6054 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6058 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6059 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6060 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6061 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6062 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6063 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6064 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6065 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6066 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6067 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6068 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6069 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6070 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6073 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6074 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6075 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6076 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6077 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6078 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6079 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6080 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6081 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6082 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6083 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6084 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6085 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6086 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6087 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6088 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6089 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6090 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6091 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6092 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6093 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6094 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6095 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6096 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6097 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6098 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6099 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6100 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6101 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6102 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6103 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6104 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6105 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6147 /* Place holder, leave as first spe builtin. */
6148 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6149 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6150 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6151 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6152 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6153 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6154 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6155 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6156 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6157 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6158 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6159 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6160 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6161 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6162 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6163 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6164 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6165 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6166 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6167 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6168 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6169 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6170 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6171 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6172 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6173 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6174 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6175 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6176 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6177 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6178 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6179 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6180 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6181 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6182 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6183 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6184 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6185 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6186 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6187 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6188 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6189 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6190 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6191 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6192 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6193 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6194 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6195 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6196 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6197 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6198 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6199 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6200 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6201 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6202 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6203 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6204 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6205 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6206 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6207 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6208 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6209 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6210 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6211 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6212 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6213 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6214 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6215 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6216 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6217 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6218 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6219 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6220 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6221 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6222 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6223 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6224 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6225 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6226 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6227 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6228 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6229 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6230 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6231 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6232 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6233 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6234 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6235 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6236 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6237 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6238 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6239 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6240 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6241 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6242 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6243 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6244 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6245 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6246 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6247 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6248 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6249 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6250 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6251 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6252 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6253 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6254 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6255 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6256 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6258 /* SPE binary operations expecting a 5-bit unsigned literal. */
6259 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6261 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6262 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6263 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6264 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6265 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6266 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6267 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6268 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6269 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6270 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6271 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6272 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6273 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6274 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6275 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6276 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6277 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6278 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6279 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6280 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6281 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6282 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6283 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6284 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6285 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6286 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6288 /* Place-holder. Leave as last binary SPE builtin. */
6289 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6292 /* AltiVec predicates. */
6294 struct builtin_description_predicates
6296 const unsigned int mask;
6297 const enum insn_code icode;
6299 const char *const name;
6300 const enum rs6000_builtins code;
6303 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6305 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6306 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6307 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6308 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6309 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6310 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6311 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6312 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6313 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6314 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6315 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6316 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6317 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6319 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6320 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6321 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6324 /* SPE predicates. */
6325 static struct builtin_description bdesc_spe_predicates[] =
6327 /* Place-holder. Leave as first. */
6328 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6329 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6330 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6331 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6332 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6333 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6334 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6335 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6336 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6337 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6338 /* Place-holder. Leave as last. */
6339 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6342 /* SPE evsel predicates. */
6343 static struct builtin_description bdesc_spe_evsel[] =
6345 /* Place-holder. Leave as first. */
6346 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6347 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6348 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6349 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6350 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6351 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6352 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6353 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6354 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6355 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6356 /* Place-holder. Leave as last. */
6357 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6360 /* ABS* operations. */
6362 static const struct builtin_description bdesc_abs[] =
6364 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6365 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6366 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6367 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6368 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6369 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6370 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6373 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6376 static struct builtin_description bdesc_1arg[] =
6378 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6379 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6380 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6381 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6382 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6383 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6384 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6385 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6386 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6387 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6388 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6389 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6390 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6391 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6392 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6393 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6394 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6396 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6397 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6398 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6399 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6400 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6401 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6402 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6403 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6404 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6405 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6406 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6407 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6408 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6409 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6410 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6411 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6412 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6413 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6414 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6416 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6417 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6418 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6419 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6420 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6421 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6422 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6423 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6424 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6425 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6426 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6427 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6428 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6429 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6430 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6431 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6432 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6433 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6434 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6435 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6436 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6437 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6438 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6439 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6440 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6441 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6442 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6443 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6444 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6445 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6447 /* Place-holder. Leave as last unary SPE builtin. */
6448 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6452 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6455 tree arg0 = TREE_VALUE (arglist);
6456 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6457 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6458 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6460 if (icode == CODE_FOR_nothing)
6461 /* Builtin not supported on this processor. */
6464 /* If we got invalid arguments bail out before generating bad rtl. */
6465 if (arg0 == error_mark_node)
6468 if (icode == CODE_FOR_altivec_vspltisb
6469 || icode == CODE_FOR_altivec_vspltish
6470 || icode == CODE_FOR_altivec_vspltisw
6471 || icode == CODE_FOR_spe_evsplatfi
6472 || icode == CODE_FOR_spe_evsplati)
6474 /* Only allow 5-bit *signed* literals. */
6475 if (GET_CODE (op0) != CONST_INT
6476 || INTVAL (op0) > 15
6477 || INTVAL (op0) < -16)
6479 error ("argument 1 must be a 5-bit signed literal");
6485 || GET_MODE (target) != tmode
6486 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6487 target = gen_reg_rtx (tmode);
6489 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6490 op0 = copy_to_mode_reg (mode0, op0);
6492 pat = GEN_FCN (icode) (target, op0);
6501 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6503 rtx pat, scratch1, scratch2;
6504 tree arg0 = TREE_VALUE (arglist);
6505 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6506 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6507 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6509 /* If we have invalid arguments, bail out before generating bad rtl. */
6510 if (arg0 == error_mark_node)
6514 || GET_MODE (target) != tmode
6515 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6516 target = gen_reg_rtx (tmode);
6518 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6519 op0 = copy_to_mode_reg (mode0, op0);
6521 scratch1 = gen_reg_rtx (mode0);
6522 scratch2 = gen_reg_rtx (mode0);
6524 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6533 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6536 tree arg0 = TREE_VALUE (arglist);
6537 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6538 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6539 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6540 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6541 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6542 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6544 if (icode == CODE_FOR_nothing)
6545 /* Builtin not supported on this processor. */
6548 /* If we got invalid arguments bail out before generating bad rtl. */
6549 if (arg0 == error_mark_node || arg1 == error_mark_node)
6552 if (icode == CODE_FOR_altivec_vcfux
6553 || icode == CODE_FOR_altivec_vcfsx
6554 || icode == CODE_FOR_altivec_vctsxs
6555 || icode == CODE_FOR_altivec_vctuxs
6556 || icode == CODE_FOR_altivec_vspltb
6557 || icode == CODE_FOR_altivec_vsplth
6558 || icode == CODE_FOR_altivec_vspltw
6559 || icode == CODE_FOR_spe_evaddiw
6560 || icode == CODE_FOR_spe_evldd
6561 || icode == CODE_FOR_spe_evldh
6562 || icode == CODE_FOR_spe_evldw
6563 || icode == CODE_FOR_spe_evlhhesplat
6564 || icode == CODE_FOR_spe_evlhhossplat
6565 || icode == CODE_FOR_spe_evlhhousplat
6566 || icode == CODE_FOR_spe_evlwhe
6567 || icode == CODE_FOR_spe_evlwhos
6568 || icode == CODE_FOR_spe_evlwhou
6569 || icode == CODE_FOR_spe_evlwhsplat
6570 || icode == CODE_FOR_spe_evlwwsplat
6571 || icode == CODE_FOR_spe_evrlwi
6572 || icode == CODE_FOR_spe_evslwi
6573 || icode == CODE_FOR_spe_evsrwis
6574 || icode == CODE_FOR_spe_evsubifw
6575 || icode == CODE_FOR_spe_evsrwiu)
6577 /* Only allow 5-bit unsigned literals. */
6579 if (TREE_CODE (arg1) != INTEGER_CST
6580 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6582 error ("argument 2 must be a 5-bit unsigned literal");
6588 || GET_MODE (target) != tmode
6589 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6590 target = gen_reg_rtx (tmode);
6592 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6593 op0 = copy_to_mode_reg (mode0, op0);
6594 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6595 op1 = copy_to_mode_reg (mode1, op1);
6597 pat = GEN_FCN (icode) (target, op0, op1);
6606 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6607 tree arglist, rtx target)
6610 tree cr6_form = TREE_VALUE (arglist);
6611 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6612 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6613 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6614 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6615 enum machine_mode tmode = SImode;
6616 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6617 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6620 if (TREE_CODE (cr6_form) != INTEGER_CST)
6622 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6626 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6628 gcc_assert (mode0 == mode1);
6630 /* If we have invalid arguments, bail out before generating bad rtl. */
6631 if (arg0 == error_mark_node || arg1 == error_mark_node)
6635 || GET_MODE (target) != tmode
6636 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6637 target = gen_reg_rtx (tmode);
6639 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6640 op0 = copy_to_mode_reg (mode0, op0);
6641 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6642 op1 = copy_to_mode_reg (mode1, op1);
6644 scratch = gen_reg_rtx (mode0);
6646 pat = GEN_FCN (icode) (scratch, op0, op1,
6647 gen_rtx_SYMBOL_REF (Pmode, opcode));
6652 /* The vec_any* and vec_all* predicates use the same opcodes for two
6653 different operations, but the bits in CR6 will be different
6654 depending on what information we want. So we have to play tricks
6655 with CR6 to get the right bits out.
6657 If you think this is disgusting, look at the specs for the
6658 AltiVec predicates. */
6660 switch (cr6_form_int)
6663 emit_insn (gen_cr6_test_for_zero (target));
6666 emit_insn (gen_cr6_test_for_zero_reverse (target));
6669 emit_insn (gen_cr6_test_for_lt (target));
6672 emit_insn (gen_cr6_test_for_lt_reverse (target));
6675 error ("argument 1 of __builtin_altivec_predicate is out of range");
6683 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6686 tree arg0 = TREE_VALUE (arglist);
6687 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6688 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6689 enum machine_mode mode0 = Pmode;
6690 enum machine_mode mode1 = Pmode;
6691 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6692 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6694 if (icode == CODE_FOR_nothing)
6695 /* Builtin not supported on this processor. */
6698 /* If we got invalid arguments bail out before generating bad rtl. */
6699 if (arg0 == error_mark_node || arg1 == error_mark_node)
6703 || GET_MODE (target) != tmode
6704 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6705 target = gen_reg_rtx (tmode);
6707 op1 = copy_to_mode_reg (mode1, op1);
6709 if (op0 == const0_rtx)
6711 addr = gen_rtx_MEM (tmode, op1);
6715 op0 = copy_to_mode_reg (mode0, op0);
6716 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6719 pat = GEN_FCN (icode) (target, addr);
6729 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6731 tree arg0 = TREE_VALUE (arglist);
6732 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6733 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6734 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6735 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6736 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6738 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6739 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6740 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6742 /* Invalid arguments. Bail before doing anything stoopid! */
6743 if (arg0 == error_mark_node
6744 || arg1 == error_mark_node
6745 || arg2 == error_mark_node)
6748 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6749 op0 = copy_to_mode_reg (mode2, op0);
6750 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6751 op1 = copy_to_mode_reg (mode0, op1);
6752 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6753 op2 = copy_to_mode_reg (mode1, op2);
6755 pat = GEN_FCN (icode) (op1, op2, op0);
6762 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6764 tree arg0 = TREE_VALUE (arglist);
6765 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6766 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6767 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6768 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6769 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6771 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6772 enum machine_mode mode1 = Pmode;
6773 enum machine_mode mode2 = Pmode;
6775 /* Invalid arguments. Bail before doing anything stoopid! */
6776 if (arg0 == error_mark_node
6777 || arg1 == error_mark_node
6778 || arg2 == error_mark_node)
6781 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6782 op0 = copy_to_mode_reg (tmode, op0);
6784 op2 = copy_to_mode_reg (mode2, op2);
6786 if (op1 == const0_rtx)
6788 addr = gen_rtx_MEM (tmode, op2);
6792 op1 = copy_to_mode_reg (mode1, op1);
6793 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6796 pat = GEN_FCN (icode) (addr, op0);
6803 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6806 tree arg0 = TREE_VALUE (arglist);
6807 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6808 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6809 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6810 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6811 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6812 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6813 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6814 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6815 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6817 if (icode == CODE_FOR_nothing)
6818 /* Builtin not supported on this processor. */
6821 /* If we got invalid arguments bail out before generating bad rtl. */
6822 if (arg0 == error_mark_node
6823 || arg1 == error_mark_node
6824 || arg2 == error_mark_node)
6827 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6828 || icode == CODE_FOR_altivec_vsldoi_v4si
6829 || icode == CODE_FOR_altivec_vsldoi_v8hi
6830 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6832 /* Only allow 4-bit unsigned literals. */
6834 if (TREE_CODE (arg2) != INTEGER_CST
6835 || TREE_INT_CST_LOW (arg2) & ~0xf)
6837 error ("argument 3 must be a 4-bit unsigned literal");
6843 || GET_MODE (target) != tmode
6844 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6845 target = gen_reg_rtx (tmode);
6847 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6848 op0 = copy_to_mode_reg (mode0, op0);
6849 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6850 op1 = copy_to_mode_reg (mode1, op1);
6851 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6852 op2 = copy_to_mode_reg (mode2, op2);
6854 pat = GEN_FCN (icode) (target, op0, op1, op2);
6862 /* Expand the lvx builtins. */
6864 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6866 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6867 tree arglist = TREE_OPERAND (exp, 1);
6868 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6870 enum machine_mode tmode, mode0;
6872 enum insn_code icode;
6876 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6877 icode = CODE_FOR_altivec_lvx_v16qi;
6879 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6880 icode = CODE_FOR_altivec_lvx_v8hi;
6882 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6883 icode = CODE_FOR_altivec_lvx_v4si;
6885 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6886 icode = CODE_FOR_altivec_lvx_v4sf;
6895 arg0 = TREE_VALUE (arglist);
6896 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6897 tmode = insn_data[icode].operand[0].mode;
6898 mode0 = insn_data[icode].operand[1].mode;
6901 || GET_MODE (target) != tmode
6902 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6903 target = gen_reg_rtx (tmode);
6905 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6906 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6908 pat = GEN_FCN (icode) (target, op0);
6915 /* Expand the stvx builtins. */
6917 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6920 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6921 tree arglist = TREE_OPERAND (exp, 1);
6922 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6924 enum machine_mode mode0, mode1;
6926 enum insn_code icode;
6930 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6931 icode = CODE_FOR_altivec_stvx_v16qi;
6933 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6934 icode = CODE_FOR_altivec_stvx_v8hi;
6936 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6937 icode = CODE_FOR_altivec_stvx_v4si;
6939 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6940 icode = CODE_FOR_altivec_stvx_v4sf;
6947 arg0 = TREE_VALUE (arglist);
6948 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6949 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6950 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6951 mode0 = insn_data[icode].operand[0].mode;
6952 mode1 = insn_data[icode].operand[1].mode;
6954 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6955 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6956 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6957 op1 = copy_to_mode_reg (mode1, op1);
6959 pat = GEN_FCN (icode) (op0, op1);
6967 /* Expand the dst builtins. */
6969 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6972 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6973 tree arglist = TREE_OPERAND (exp, 1);
6974 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6975 tree arg0, arg1, arg2;
6976 enum machine_mode mode0, mode1, mode2;
6977 rtx pat, op0, op1, op2;
6978 struct builtin_description *d;
6983 /* Handle DST variants. */
6984 d = (struct builtin_description *) bdesc_dst;
6985 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6986 if (d->code == fcode)
6988 arg0 = TREE_VALUE (arglist);
6989 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6990 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6991 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6992 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6993 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6994 mode0 = insn_data[d->icode].operand[0].mode;
6995 mode1 = insn_data[d->icode].operand[1].mode;
6996 mode2 = insn_data[d->icode].operand[2].mode;
6998 /* Invalid arguments, bail out before generating bad rtl. */
6999 if (arg0 == error_mark_node
7000 || arg1 == error_mark_node
7001 || arg2 == error_mark_node)
7006 if (TREE_CODE (arg2) != INTEGER_CST
7007 || TREE_INT_CST_LOW (arg2) & ~0x3)
7009 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7013 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7014 op0 = copy_to_mode_reg (Pmode, op0);
7015 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7016 op1 = copy_to_mode_reg (mode1, op1);
7018 pat = GEN_FCN (d->icode) (op0, op1, op2);
7028 /* Expand vec_init builtin. */
7030 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7032 enum machine_mode tmode = TYPE_MODE (type);
7033 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7034 int i, n_elt = GET_MODE_NUNITS (tmode);
7035 rtvec v = rtvec_alloc (n_elt);
7037 gcc_assert (VECTOR_MODE_P (tmode));
7039 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7041 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
7042 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7045 gcc_assert (arglist == NULL);
7047 if (!target || !register_operand (target, tmode))
7048 target = gen_reg_rtx (tmode);
7050 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7054 /* Return the integer constant in ARG. Constrain it to be in the range
7055 of the subparts of VEC_TYPE; issue an error if not. */
7058 get_element_number (tree vec_type, tree arg)
7060 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7062 if (!host_integerp (arg, 1)
7063 || (elt = tree_low_cst (arg, 1), elt > max))
7065 error ("selector must be an integer constant in the range 0..%wi", max);
7072 /* Expand vec_set builtin. */
7074 altivec_expand_vec_set_builtin (tree arglist)
7076 enum machine_mode tmode, mode1;
7077 tree arg0, arg1, arg2;
7081 arg0 = TREE_VALUE (arglist);
7082 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7083 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7085 tmode = TYPE_MODE (TREE_TYPE (arg0));
7086 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7087 gcc_assert (VECTOR_MODE_P (tmode));
7089 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7090 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7091 elt = get_element_number (TREE_TYPE (arg0), arg2);
7093 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7094 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7096 op0 = force_reg (tmode, op0);
7097 op1 = force_reg (mode1, op1);
7099 rs6000_expand_vector_set (op0, op1, elt);
7104 /* Expand vec_ext builtin. */
7106 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7108 enum machine_mode tmode, mode0;
7113 arg0 = TREE_VALUE (arglist);
7114 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7116 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7117 elt = get_element_number (TREE_TYPE (arg0), arg1);
7119 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7120 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7121 gcc_assert (VECTOR_MODE_P (mode0));
7123 op0 = force_reg (mode0, op0);
7125 if (optimize || !target || !register_operand (target, tmode))
7126 target = gen_reg_rtx (tmode);
7128 rs6000_expand_vector_extract (target, op0, elt);
7133 /* Expand the builtin in EXP and store the result in TARGET. Store
7134 true in *EXPANDEDP if we found a builtin to expand. */
7136 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7138 struct builtin_description *d;
7139 struct builtin_description_predicates *dp;
7141 enum insn_code icode;
7142 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7143 tree arglist = TREE_OPERAND (exp, 1);
7146 enum machine_mode tmode, mode0;
7147 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7149 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7150 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7153 error ("unresolved overload for Altivec builtin %qF", fndecl);
7157 target = altivec_expand_ld_builtin (exp, target, expandedp);
7161 target = altivec_expand_st_builtin (exp, target, expandedp);
7165 target = altivec_expand_dst_builtin (exp, target, expandedp);
7173 case ALTIVEC_BUILTIN_STVX:
7174 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7175 case ALTIVEC_BUILTIN_STVEBX:
7176 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7177 case ALTIVEC_BUILTIN_STVEHX:
7178 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7179 case ALTIVEC_BUILTIN_STVEWX:
7180 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7181 case ALTIVEC_BUILTIN_STVXL:
7182 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7184 case ALTIVEC_BUILTIN_MFVSCR:
7185 icode = CODE_FOR_altivec_mfvscr;
7186 tmode = insn_data[icode].operand[0].mode;
7189 || GET_MODE (target) != tmode
7190 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7191 target = gen_reg_rtx (tmode);
7193 pat = GEN_FCN (icode) (target);
7199 case ALTIVEC_BUILTIN_MTVSCR:
7200 icode = CODE_FOR_altivec_mtvscr;
7201 arg0 = TREE_VALUE (arglist);
7202 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7203 mode0 = insn_data[icode].operand[0].mode;
7205 /* If we got invalid arguments bail out before generating bad rtl. */
7206 if (arg0 == error_mark_node)
7209 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7210 op0 = copy_to_mode_reg (mode0, op0);
7212 pat = GEN_FCN (icode) (op0);
7217 case ALTIVEC_BUILTIN_DSSALL:
7218 emit_insn (gen_altivec_dssall ());
7221 case ALTIVEC_BUILTIN_DSS:
7222 icode = CODE_FOR_altivec_dss;
7223 arg0 = TREE_VALUE (arglist);
7225 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7226 mode0 = insn_data[icode].operand[0].mode;
7228 /* If we got invalid arguments bail out before generating bad rtl. */
7229 if (arg0 == error_mark_node)
7232 if (TREE_CODE (arg0) != INTEGER_CST
7233 || TREE_INT_CST_LOW (arg0) & ~0x3)
7235 error ("argument to dss must be a 2-bit unsigned literal");
7239 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7240 op0 = copy_to_mode_reg (mode0, op0);
7242 emit_insn (gen_altivec_dss (op0));
7245 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7246 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7247 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7248 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7249 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7251 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7252 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7253 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7254 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7255 return altivec_expand_vec_set_builtin (arglist);
7257 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7258 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7259 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7260 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7261 return altivec_expand_vec_ext_builtin (arglist, target);
7268 /* Expand abs* operations. */
7269 d = (struct builtin_description *) bdesc_abs;
7270 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7271 if (d->code == fcode)
7272 return altivec_expand_abs_builtin (d->icode, arglist, target);
7274 /* Expand the AltiVec predicates. */
7275 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7276 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7277 if (dp->code == fcode)
7278 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7281 /* LV* are funky. We initialized them differently. */
7284 case ALTIVEC_BUILTIN_LVSL:
7285 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7287 case ALTIVEC_BUILTIN_LVSR:
7288 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7290 case ALTIVEC_BUILTIN_LVEBX:
7291 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7293 case ALTIVEC_BUILTIN_LVEHX:
7294 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7296 case ALTIVEC_BUILTIN_LVEWX:
7297 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7299 case ALTIVEC_BUILTIN_LVXL:
7300 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7302 case ALTIVEC_BUILTIN_LVX:
7303 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7314 /* Binops that need to be initialized manually, but can be expanded
7315 automagically by rs6000_expand_binop_builtin. */
7316 static struct builtin_description bdesc_2arg_spe[] =
7318 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7319 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7320 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7321 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7322 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7323 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7324 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7325 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7326 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7327 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7328 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7329 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7330 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7331 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7332 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7333 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7334 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7335 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7336 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7337 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7338 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7339 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7342 /* Expand the builtin in EXP and store the result in TARGET. Store
7343 true in *EXPANDEDP if we found a builtin to expand.
7345 This expands the SPE builtins that are not simple unary and binary
7348 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7350 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7351 tree arglist = TREE_OPERAND (exp, 1);
7353 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7354 enum insn_code icode;
7355 enum machine_mode tmode, mode0;
7357 struct builtin_description *d;
7362 /* Syntax check for a 5-bit unsigned immediate. */
7365 case SPE_BUILTIN_EVSTDD:
7366 case SPE_BUILTIN_EVSTDH:
7367 case SPE_BUILTIN_EVSTDW:
7368 case SPE_BUILTIN_EVSTWHE:
7369 case SPE_BUILTIN_EVSTWHO:
7370 case SPE_BUILTIN_EVSTWWE:
7371 case SPE_BUILTIN_EVSTWWO:
7372 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7373 if (TREE_CODE (arg1) != INTEGER_CST
7374 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7376 error ("argument 2 must be a 5-bit unsigned literal");
7384 /* The evsplat*i instructions are not quite generic. */
7387 case SPE_BUILTIN_EVSPLATFI:
7388 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7390 case SPE_BUILTIN_EVSPLATI:
7391 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7397 d = (struct builtin_description *) bdesc_2arg_spe;
7398 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7399 if (d->code == fcode)
7400 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7402 d = (struct builtin_description *) bdesc_spe_predicates;
7403 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7404 if (d->code == fcode)
7405 return spe_expand_predicate_builtin (d->icode, arglist, target);
7407 d = (struct builtin_description *) bdesc_spe_evsel;
7408 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7409 if (d->code == fcode)
7410 return spe_expand_evsel_builtin (d->icode, arglist, target);
7414 case SPE_BUILTIN_EVSTDDX:
7415 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7416 case SPE_BUILTIN_EVSTDHX:
7417 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7418 case SPE_BUILTIN_EVSTDWX:
7419 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7420 case SPE_BUILTIN_EVSTWHEX:
7421 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7422 case SPE_BUILTIN_EVSTWHOX:
7423 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7424 case SPE_BUILTIN_EVSTWWEX:
7425 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7426 case SPE_BUILTIN_EVSTWWOX:
7427 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7428 case SPE_BUILTIN_EVSTDD:
7429 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7430 case SPE_BUILTIN_EVSTDH:
7431 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7432 case SPE_BUILTIN_EVSTDW:
7433 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7434 case SPE_BUILTIN_EVSTWHE:
7435 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7436 case SPE_BUILTIN_EVSTWHO:
7437 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7438 case SPE_BUILTIN_EVSTWWE:
7439 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7440 case SPE_BUILTIN_EVSTWWO:
7441 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7442 case SPE_BUILTIN_MFSPEFSCR:
7443 icode = CODE_FOR_spe_mfspefscr;
7444 tmode = insn_data[icode].operand[0].mode;
7447 || GET_MODE (target) != tmode
7448 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7449 target = gen_reg_rtx (tmode);
7451 pat = GEN_FCN (icode) (target);
7456 case SPE_BUILTIN_MTSPEFSCR:
7457 icode = CODE_FOR_spe_mtspefscr;
7458 arg0 = TREE_VALUE (arglist);
7459 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7460 mode0 = insn_data[icode].operand[0].mode;
7462 if (arg0 == error_mark_node)
7465 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7466 op0 = copy_to_mode_reg (mode0, op0);
7468 pat = GEN_FCN (icode) (op0);
7481 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7483 rtx pat, scratch, tmp;
7484 tree form = TREE_VALUE (arglist);
7485 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7486 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7487 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7488 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7489 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7490 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7494 if (TREE_CODE (form) != INTEGER_CST)
7496 error ("argument 1 of __builtin_spe_predicate must be a constant");
7500 form_int = TREE_INT_CST_LOW (form);
7502 gcc_assert (mode0 == mode1);
7504 if (arg0 == error_mark_node || arg1 == error_mark_node)
7508 || GET_MODE (target) != SImode
7509 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7510 target = gen_reg_rtx (SImode);
7512 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7513 op0 = copy_to_mode_reg (mode0, op0);
7514 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7515 op1 = copy_to_mode_reg (mode1, op1);
7517 scratch = gen_reg_rtx (CCmode);
7519 pat = GEN_FCN (icode) (scratch, op0, op1);
7524 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7525 _lower_. We use one compare, but look in different bits of the
7526 CR for each variant.
7528 There are 2 elements in each SPE simd type (upper/lower). The CR
7529 bits are set as follows:
7531 BIT0 | BIT 1 | BIT 2 | BIT 3
7532 U | L | (U | L) | (U & L)
7534 So, for an "all" relationship, BIT 3 would be set.
7535 For an "any" relationship, BIT 2 would be set. Etc.
7537 Following traditional nomenclature, these bits map to:
7539 BIT0 | BIT 1 | BIT 2 | BIT 3
7542 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7547 /* All variant. OV bit. */
7549 /* We need to get to the OV bit, which is the ORDERED bit. We
7550 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7551 that's ugly and will make validate_condition_mode die.
7552 So let's just use another pattern. */
7553 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7555 /* Any variant. EQ bit. */
7559 /* Upper variant. LT bit. */
7563 /* Lower variant. GT bit. */
7568 error ("argument 1 of __builtin_spe_predicate is out of range");
7572 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7573 emit_move_insn (target, tmp);
7578 /* The evsel builtins look like this:
7580 e = __builtin_spe_evsel_OP (a, b, c, d);
7584 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7585 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7589 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7592 tree arg0 = TREE_VALUE (arglist);
7593 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7594 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7595 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7596 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7597 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7598 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7599 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7600 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7601 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7603 gcc_assert (mode0 == mode1);
7605 if (arg0 == error_mark_node || arg1 == error_mark_node
7606 || arg2 == error_mark_node || arg3 == error_mark_node)
7610 || GET_MODE (target) != mode0
7611 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7612 target = gen_reg_rtx (mode0);
7614 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7615 op0 = copy_to_mode_reg (mode0, op0);
7616 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7617 op1 = copy_to_mode_reg (mode0, op1);
7618 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7619 op2 = copy_to_mode_reg (mode0, op2);
7620 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7621 op3 = copy_to_mode_reg (mode0, op3);
7623 /* Generate the compare. */
7624 scratch = gen_reg_rtx (CCmode);
7625 pat = GEN_FCN (icode) (scratch, op0, op1);
7630 if (mode0 == V2SImode)
7631 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7633 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7638 /* Expand an expression EXP that calls a built-in function,
7639 with result going to TARGET if that's convenient
7640 (and in mode MODE if that's convenient).
7641 SUBTARGET may be used as the target for computing one of EXP's operands.
7642 IGNORE is nonzero if the value is to be ignored. */
7645 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7646 enum machine_mode mode ATTRIBUTE_UNUSED,
7647 int ignore ATTRIBUTE_UNUSED)
7649 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7650 tree arglist = TREE_OPERAND (exp, 1);
7651 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7652 struct builtin_description *d;
7657 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7658 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7660 int icode = (int) CODE_FOR_altivec_lvsr;
7661 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7662 enum machine_mode mode = insn_data[icode].operand[1].mode;
7666 gcc_assert (TARGET_ALTIVEC);
7668 arg = TREE_VALUE (arglist);
7669 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7670 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7671 addr = memory_address (mode, op);
7672 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7676 /* For the load case need to negate the address. */
7677 op = gen_reg_rtx (GET_MODE (addr));
7678 emit_insn (gen_rtx_SET (VOIDmode, op,
7679 gen_rtx_NEG (GET_MODE (addr), addr)));
7681 op = gen_rtx_MEM (mode, op);
7684 || GET_MODE (target) != tmode
7685 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7686 target = gen_reg_rtx (tmode);
7688 /*pat = gen_altivec_lvsr (target, op);*/
7689 pat = GEN_FCN (icode) (target, op);
7699 ret = altivec_expand_builtin (exp, target, &success);
7706 ret = spe_expand_builtin (exp, target, &success);
7712 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7714 /* Handle simple unary operations. */
7715 d = (struct builtin_description *) bdesc_1arg;
7716 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7717 if (d->code == fcode)
7718 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7720 /* Handle simple binary operations. */
7721 d = (struct builtin_description *) bdesc_2arg;
7722 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7723 if (d->code == fcode)
7724 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7726 /* Handle simple ternary operations. */
7727 d = (struct builtin_description *) bdesc_3arg;
7728 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7729 if (d->code == fcode)
7730 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7736 build_opaque_vector_type (tree node, int nunits)
7738 node = copy_node (node);
7739 TYPE_MAIN_VARIANT (node) = node;
7740 return build_vector_type (node, nunits);
7744 rs6000_init_builtins (void)
7746 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7747 V2SF_type_node = build_vector_type (float_type_node, 2);
7748 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7749 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7750 V4SF_type_node = build_vector_type (float_type_node, 4);
7751 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7752 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7754 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7755 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7756 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7758 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7759 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7760 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7761 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7763 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7764 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7765 'vector unsigned short'. */
7767 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7768 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7769 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7770 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7772 long_integer_type_internal_node = long_integer_type_node;
7773 long_unsigned_type_internal_node = long_unsigned_type_node;
7774 intQI_type_internal_node = intQI_type_node;
7775 uintQI_type_internal_node = unsigned_intQI_type_node;
7776 intHI_type_internal_node = intHI_type_node;
7777 uintHI_type_internal_node = unsigned_intHI_type_node;
7778 intSI_type_internal_node = intSI_type_node;
7779 uintSI_type_internal_node = unsigned_intSI_type_node;
7780 float_type_internal_node = float_type_node;
7781 void_type_internal_node = void_type_node;
7783 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7784 get_identifier ("__bool char"),
7785 bool_char_type_node));
7786 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7787 get_identifier ("__bool short"),
7788 bool_short_type_node));
7789 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7790 get_identifier ("__bool int"),
7791 bool_int_type_node));
7792 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7793 get_identifier ("__pixel"),
7796 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7797 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7798 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7799 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7801 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7802 get_identifier ("__vector unsigned char"),
7803 unsigned_V16QI_type_node));
7804 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7805 get_identifier ("__vector signed char"),
7807 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7808 get_identifier ("__vector __bool char"),
7809 bool_V16QI_type_node));
7811 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7812 get_identifier ("__vector unsigned short"),
7813 unsigned_V8HI_type_node));
7814 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7815 get_identifier ("__vector signed short"),
7817 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7818 get_identifier ("__vector __bool short"),
7819 bool_V8HI_type_node));
7821 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7822 get_identifier ("__vector unsigned int"),
7823 unsigned_V4SI_type_node));
7824 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7825 get_identifier ("__vector signed int"),
7827 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7828 get_identifier ("__vector __bool int"),
7829 bool_V4SI_type_node));
7831 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7832 get_identifier ("__vector float"),
7834 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7835 get_identifier ("__vector __pixel"),
7836 pixel_V8HI_type_node));
7839 spe_init_builtins ();
7841 altivec_init_builtins ();
7842 if (TARGET_ALTIVEC || TARGET_SPE)
7843 rs6000_common_init_builtins ();
7846 /* Search through a set of builtins and enable the mask bits.
7847 DESC is an array of builtins.
7848 SIZE is the total number of builtins.
7849 START is the builtin enum at which to start.
7850 END is the builtin enum at which to end. */
7852 enable_mask_for_builtins (struct builtin_description *desc, int size,
7853 enum rs6000_builtins start,
7854 enum rs6000_builtins end)
7858 for (i = 0; i < size; ++i)
7859 if (desc[i].code == start)
7865 for (; i < size; ++i)
7867 /* Flip all the bits on. */
7868 desc[i].mask = target_flags;
7869 if (desc[i].code == end)
7875 spe_init_builtins (void)
7877 tree endlink = void_list_node;
7878 tree puint_type_node = build_pointer_type (unsigned_type_node);
7879 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7880 struct builtin_description *d;
7883 tree v2si_ftype_4_v2si
7884 = build_function_type
7885 (opaque_V2SI_type_node,
7886 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7887 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7888 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7889 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7892 tree v2sf_ftype_4_v2sf
7893 = build_function_type
7894 (opaque_V2SF_type_node,
7895 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7896 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7897 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7898 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7901 tree int_ftype_int_v2si_v2si
7902 = build_function_type
7904 tree_cons (NULL_TREE, integer_type_node,
7905 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7906 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7909 tree int_ftype_int_v2sf_v2sf
7910 = build_function_type
7912 tree_cons (NULL_TREE, integer_type_node,
7913 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7914 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7917 tree void_ftype_v2si_puint_int
7918 = build_function_type (void_type_node,
7919 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7920 tree_cons (NULL_TREE, puint_type_node,
7921 tree_cons (NULL_TREE,
7925 tree void_ftype_v2si_puint_char
7926 = build_function_type (void_type_node,
7927 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7928 tree_cons (NULL_TREE, puint_type_node,
7929 tree_cons (NULL_TREE,
7933 tree void_ftype_v2si_pv2si_int
7934 = build_function_type (void_type_node,
7935 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7936 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7937 tree_cons (NULL_TREE,
7941 tree void_ftype_v2si_pv2si_char
7942 = build_function_type (void_type_node,
7943 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7944 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7945 tree_cons (NULL_TREE,
7950 = build_function_type (void_type_node,
7951 tree_cons (NULL_TREE, integer_type_node, endlink));
7954 = build_function_type (integer_type_node, endlink);
7956 tree v2si_ftype_pv2si_int
7957 = build_function_type (opaque_V2SI_type_node,
7958 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7959 tree_cons (NULL_TREE, integer_type_node,
7962 tree v2si_ftype_puint_int
7963 = build_function_type (opaque_V2SI_type_node,
7964 tree_cons (NULL_TREE, puint_type_node,
7965 tree_cons (NULL_TREE, integer_type_node,
7968 tree v2si_ftype_pushort_int
7969 = build_function_type (opaque_V2SI_type_node,
7970 tree_cons (NULL_TREE, pushort_type_node,
7971 tree_cons (NULL_TREE, integer_type_node,
7974 tree v2si_ftype_signed_char
7975 = build_function_type (opaque_V2SI_type_node,
7976 tree_cons (NULL_TREE, signed_char_type_node,
7979 /* The initialization of the simple binary and unary builtins is
7980 done in rs6000_common_init_builtins, but we have to enable the
7981 mask bits here manually because we have run out of `target_flags'
7982 bits. We really need to redesign this mask business. */
7984 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7985 ARRAY_SIZE (bdesc_2arg),
7988 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7989 ARRAY_SIZE (bdesc_1arg),
7991 SPE_BUILTIN_EVSUBFUSIAAW);
7992 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7993 ARRAY_SIZE (bdesc_spe_predicates),
7994 SPE_BUILTIN_EVCMPEQ,
7995 SPE_BUILTIN_EVFSTSTLT);
7996 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7997 ARRAY_SIZE (bdesc_spe_evsel),
7998 SPE_BUILTIN_EVSEL_CMPGTS,
7999 SPE_BUILTIN_EVSEL_FSTSTEQ);
8001 (*lang_hooks.decls.pushdecl)
8002 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8003 opaque_V2SI_type_node));
8005 /* Initialize irregular SPE builtins. */
8007 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8008 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8009 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8010 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8011 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8012 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8013 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8014 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8015 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8016 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8017 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8018 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8019 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8020 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8021 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8022 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8023 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8024 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8027 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8028 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8029 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8030 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8031 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8032 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8033 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8034 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8035 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8036 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8037 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8038 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8039 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8040 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8041 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8042 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8043 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8044 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8045 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8046 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8047 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8048 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8051 d = (struct builtin_description *) bdesc_spe_predicates;
8052 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8056 switch (insn_data[d->icode].operand[1].mode)
8059 type = int_ftype_int_v2si_v2si;
8062 type = int_ftype_int_v2sf_v2sf;
8068 def_builtin (d->mask, d->name, type, d->code);
8071 /* Evsel predicates. */
8072 d = (struct builtin_description *) bdesc_spe_evsel;
8073 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8077 switch (insn_data[d->icode].operand[1].mode)
8080 type = v2si_ftype_4_v2si;
8083 type = v2sf_ftype_4_v2sf;
8089 def_builtin (d->mask, d->name, type, d->code);
8094 altivec_init_builtins (void)
8096 struct builtin_description *d;
8097 struct builtin_description_predicates *dp;
8101 tree pfloat_type_node = build_pointer_type (float_type_node);
8102 tree pint_type_node = build_pointer_type (integer_type_node);
8103 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8104 tree pchar_type_node = build_pointer_type (char_type_node);
8106 tree pvoid_type_node = build_pointer_type (void_type_node);
8108 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8109 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8110 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8111 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8113 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8115 tree int_ftype_opaque
8116 = build_function_type_list (integer_type_node,
8117 opaque_V4SI_type_node, NULL_TREE);
8119 tree opaque_ftype_opaque_int
8120 = build_function_type_list (opaque_V4SI_type_node,
8121 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8122 tree opaque_ftype_opaque_opaque_int
8123 = build_function_type_list (opaque_V4SI_type_node,
8124 opaque_V4SI_type_node, opaque_V4SI_type_node,
8125 integer_type_node, NULL_TREE);
8126 tree int_ftype_int_opaque_opaque
8127 = build_function_type_list (integer_type_node,
8128 integer_type_node, opaque_V4SI_type_node,
8129 opaque_V4SI_type_node, NULL_TREE);
8130 tree int_ftype_int_v4si_v4si
8131 = build_function_type_list (integer_type_node,
8132 integer_type_node, V4SI_type_node,
8133 V4SI_type_node, NULL_TREE);
8134 tree v4sf_ftype_pcfloat
8135 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8136 tree void_ftype_pfloat_v4sf
8137 = build_function_type_list (void_type_node,
8138 pfloat_type_node, V4SF_type_node, NULL_TREE);
8139 tree v4si_ftype_pcint
8140 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8141 tree void_ftype_pint_v4si
8142 = build_function_type_list (void_type_node,
8143 pint_type_node, V4SI_type_node, NULL_TREE);
8144 tree v8hi_ftype_pcshort
8145 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8146 tree void_ftype_pshort_v8hi
8147 = build_function_type_list (void_type_node,
8148 pshort_type_node, V8HI_type_node, NULL_TREE);
8149 tree v16qi_ftype_pcchar
8150 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8151 tree void_ftype_pchar_v16qi
8152 = build_function_type_list (void_type_node,
8153 pchar_type_node, V16QI_type_node, NULL_TREE);
8154 tree void_ftype_v4si
8155 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8156 tree v8hi_ftype_void
8157 = build_function_type (V8HI_type_node, void_list_node);
8158 tree void_ftype_void
8159 = build_function_type (void_type_node, void_list_node);
8161 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8163 tree opaque_ftype_long_pcvoid
8164 = build_function_type_list (opaque_V4SI_type_node,
8165 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8166 tree v16qi_ftype_long_pcvoid
8167 = build_function_type_list (V16QI_type_node,
8168 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8169 tree v8hi_ftype_long_pcvoid
8170 = build_function_type_list (V8HI_type_node,
8171 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8172 tree v4si_ftype_long_pcvoid
8173 = build_function_type_list (V4SI_type_node,
8174 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8176 tree void_ftype_opaque_long_pvoid
8177 = build_function_type_list (void_type_node,
8178 opaque_V4SI_type_node, long_integer_type_node,
8179 pvoid_type_node, NULL_TREE);
8180 tree void_ftype_v4si_long_pvoid
8181 = build_function_type_list (void_type_node,
8182 V4SI_type_node, long_integer_type_node,
8183 pvoid_type_node, NULL_TREE);
8184 tree void_ftype_v16qi_long_pvoid
8185 = build_function_type_list (void_type_node,
8186 V16QI_type_node, long_integer_type_node,
8187 pvoid_type_node, NULL_TREE);
8188 tree void_ftype_v8hi_long_pvoid
8189 = build_function_type_list (void_type_node,
8190 V8HI_type_node, long_integer_type_node,
8191 pvoid_type_node, NULL_TREE);
8192 tree int_ftype_int_v8hi_v8hi
8193 = build_function_type_list (integer_type_node,
8194 integer_type_node, V8HI_type_node,
8195 V8HI_type_node, NULL_TREE);
8196 tree int_ftype_int_v16qi_v16qi
8197 = build_function_type_list (integer_type_node,
8198 integer_type_node, V16QI_type_node,
8199 V16QI_type_node, NULL_TREE);
8200 tree int_ftype_int_v4sf_v4sf
8201 = build_function_type_list (integer_type_node,
8202 integer_type_node, V4SF_type_node,
8203 V4SF_type_node, NULL_TREE);
8204 tree v4si_ftype_v4si
8205 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8206 tree v8hi_ftype_v8hi
8207 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8208 tree v16qi_ftype_v16qi
8209 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8210 tree v4sf_ftype_v4sf
8211 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8212 tree void_ftype_pcvoid_int_int
8213 = build_function_type_list (void_type_node,
8214 pcvoid_type_node, integer_type_node,
8215 integer_type_node, NULL_TREE);
8217 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8218 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8219 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8220 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8221 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8222 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8223 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8224 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8225 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8226 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8227 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8228 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8229 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8230 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8231 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8232 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8233 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8234 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8235 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8236 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8237 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8238 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8239 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8240 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8241 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8242 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8243 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8244 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8245 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8246 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8247 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8248 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8249 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8250 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8251 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8252 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8253 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8254 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8255 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8256 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8257 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8258 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8259 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8260 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8261 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8262 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8264 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8266 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8267 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8268 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8269 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8270 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8271 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8272 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8273 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8274 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8275 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8277 /* Add the DST variants. */
8278 d = (struct builtin_description *) bdesc_dst;
8279 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8280 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8282 /* Initialize the predicates. */
8283 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8284 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8286 enum machine_mode mode1;
8288 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8289 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8294 mode1 = insn_data[dp->icode].operand[1].mode;
8299 type = int_ftype_int_opaque_opaque;
8302 type = int_ftype_int_v4si_v4si;
8305 type = int_ftype_int_v8hi_v8hi;
8308 type = int_ftype_int_v16qi_v16qi;
8311 type = int_ftype_int_v4sf_v4sf;
8317 def_builtin (dp->mask, dp->name, type, dp->code);
8320 /* Initialize the abs* operators. */
8321 d = (struct builtin_description *) bdesc_abs;
8322 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8324 enum machine_mode mode0;
8327 mode0 = insn_data[d->icode].operand[0].mode;
8332 type = v4si_ftype_v4si;
8335 type = v8hi_ftype_v8hi;
8338 type = v16qi_ftype_v16qi;
8341 type = v4sf_ftype_v4sf;
8347 def_builtin (d->mask, d->name, type, d->code);
8354 /* Initialize target builtin that implements
8355 targetm.vectorize.builtin_mask_for_load. */
8357 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8358 v16qi_ftype_long_pcvoid,
8359 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8361 tree_cons (get_identifier ("const"),
8362 NULL_TREE, NULL_TREE));
8363 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8364 altivec_builtin_mask_for_load = decl;
8367 /* Access to the vec_init patterns. */
8368 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8369 integer_type_node, integer_type_node,
8370 integer_type_node, NULL_TREE);
8371 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8372 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8374 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8375 short_integer_type_node,
8376 short_integer_type_node,
8377 short_integer_type_node,
8378 short_integer_type_node,
8379 short_integer_type_node,
8380 short_integer_type_node,
8381 short_integer_type_node, NULL_TREE);
8382 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8383 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8385 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8386 char_type_node, char_type_node,
8387 char_type_node, char_type_node,
8388 char_type_node, char_type_node,
8389 char_type_node, char_type_node,
8390 char_type_node, char_type_node,
8391 char_type_node, char_type_node,
8392 char_type_node, char_type_node,
8393 char_type_node, NULL_TREE);
8394 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8395 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8397 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8398 float_type_node, float_type_node,
8399 float_type_node, NULL_TREE);
8400 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8401 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8403 /* Access to the vec_set patterns. */
8404 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8406 integer_type_node, NULL_TREE);
8407 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8408 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8410 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8412 integer_type_node, NULL_TREE);
8413 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8414 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8416 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8418 integer_type_node, NULL_TREE);
8419 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8420 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8422 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8424 integer_type_node, NULL_TREE);
8425 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8426 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8428 /* Access to the vec_extract patterns. */
8429 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8430 integer_type_node, NULL_TREE);
8431 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8432 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8434 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8435 integer_type_node, NULL_TREE);
8436 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8437 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8439 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8440 integer_type_node, NULL_TREE);
8441 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8442 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8444 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8445 integer_type_node, NULL_TREE);
8446 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8447 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8451 rs6000_common_init_builtins (void)
8453 struct builtin_description *d;
8456 tree v4sf_ftype_v4sf_v4sf_v16qi
8457 = build_function_type_list (V4SF_type_node,
8458 V4SF_type_node, V4SF_type_node,
8459 V16QI_type_node, NULL_TREE);
8460 tree v4si_ftype_v4si_v4si_v16qi
8461 = build_function_type_list (V4SI_type_node,
8462 V4SI_type_node, V4SI_type_node,
8463 V16QI_type_node, NULL_TREE);
8464 tree v8hi_ftype_v8hi_v8hi_v16qi
8465 = build_function_type_list (V8HI_type_node,
8466 V8HI_type_node, V8HI_type_node,
8467 V16QI_type_node, NULL_TREE);
8468 tree v16qi_ftype_v16qi_v16qi_v16qi
8469 = build_function_type_list (V16QI_type_node,
8470 V16QI_type_node, V16QI_type_node,
8471 V16QI_type_node, NULL_TREE);
8473 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8475 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8476 tree v16qi_ftype_int
8477 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8478 tree v8hi_ftype_v16qi
8479 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8480 tree v4sf_ftype_v4sf
8481 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8483 tree v2si_ftype_v2si_v2si
8484 = build_function_type_list (opaque_V2SI_type_node,
8485 opaque_V2SI_type_node,
8486 opaque_V2SI_type_node, NULL_TREE);
8488 tree v2sf_ftype_v2sf_v2sf
8489 = build_function_type_list (opaque_V2SF_type_node,
8490 opaque_V2SF_type_node,
8491 opaque_V2SF_type_node, NULL_TREE);
8493 tree v2si_ftype_int_int
8494 = build_function_type_list (opaque_V2SI_type_node,
8495 integer_type_node, integer_type_node,
8498 tree opaque_ftype_opaque
8499 = build_function_type_list (opaque_V4SI_type_node,
8500 opaque_V4SI_type_node, NULL_TREE);
8502 tree v2si_ftype_v2si
8503 = build_function_type_list (opaque_V2SI_type_node,
8504 opaque_V2SI_type_node, NULL_TREE);
8506 tree v2sf_ftype_v2sf
8507 = build_function_type_list (opaque_V2SF_type_node,
8508 opaque_V2SF_type_node, NULL_TREE);
8510 tree v2sf_ftype_v2si
8511 = build_function_type_list (opaque_V2SF_type_node,
8512 opaque_V2SI_type_node, NULL_TREE);
8514 tree v2si_ftype_v2sf
8515 = build_function_type_list (opaque_V2SI_type_node,
8516 opaque_V2SF_type_node, NULL_TREE);
8518 tree v2si_ftype_v2si_char
8519 = build_function_type_list (opaque_V2SI_type_node,
8520 opaque_V2SI_type_node,
8521 char_type_node, NULL_TREE);
8523 tree v2si_ftype_int_char
8524 = build_function_type_list (opaque_V2SI_type_node,
8525 integer_type_node, char_type_node, NULL_TREE);
8527 tree v2si_ftype_char
8528 = build_function_type_list (opaque_V2SI_type_node,
8529 char_type_node, NULL_TREE);
8531 tree int_ftype_int_int
8532 = build_function_type_list (integer_type_node,
8533 integer_type_node, integer_type_node,
8536 tree opaque_ftype_opaque_opaque
8537 = build_function_type_list (opaque_V4SI_type_node,
8538 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8539 tree v4si_ftype_v4si_v4si
8540 = build_function_type_list (V4SI_type_node,
8541 V4SI_type_node, V4SI_type_node, NULL_TREE);
8542 tree v4sf_ftype_v4si_int
8543 = build_function_type_list (V4SF_type_node,
8544 V4SI_type_node, integer_type_node, NULL_TREE);
8545 tree v4si_ftype_v4sf_int
8546 = build_function_type_list (V4SI_type_node,
8547 V4SF_type_node, integer_type_node, NULL_TREE);
8548 tree v4si_ftype_v4si_int
8549 = build_function_type_list (V4SI_type_node,
8550 V4SI_type_node, integer_type_node, NULL_TREE);
8551 tree v8hi_ftype_v8hi_int
8552 = build_function_type_list (V8HI_type_node,
8553 V8HI_type_node, integer_type_node, NULL_TREE);
8554 tree v16qi_ftype_v16qi_int
8555 = build_function_type_list (V16QI_type_node,
8556 V16QI_type_node, integer_type_node, NULL_TREE);
8557 tree v16qi_ftype_v16qi_v16qi_int
8558 = build_function_type_list (V16QI_type_node,
8559 V16QI_type_node, V16QI_type_node,
8560 integer_type_node, NULL_TREE);
8561 tree v8hi_ftype_v8hi_v8hi_int
8562 = build_function_type_list (V8HI_type_node,
8563 V8HI_type_node, V8HI_type_node,
8564 integer_type_node, NULL_TREE);
8565 tree v4si_ftype_v4si_v4si_int
8566 = build_function_type_list (V4SI_type_node,
8567 V4SI_type_node, V4SI_type_node,
8568 integer_type_node, NULL_TREE);
8569 tree v4sf_ftype_v4sf_v4sf_int
8570 = build_function_type_list (V4SF_type_node,
8571 V4SF_type_node, V4SF_type_node,
8572 integer_type_node, NULL_TREE);
8573 tree v4sf_ftype_v4sf_v4sf
8574 = build_function_type_list (V4SF_type_node,
8575 V4SF_type_node, V4SF_type_node, NULL_TREE);
8576 tree opaque_ftype_opaque_opaque_opaque
8577 = build_function_type_list (opaque_V4SI_type_node,
8578 opaque_V4SI_type_node, opaque_V4SI_type_node,
8579 opaque_V4SI_type_node, NULL_TREE);
8580 tree v4sf_ftype_v4sf_v4sf_v4si
8581 = build_function_type_list (V4SF_type_node,
8582 V4SF_type_node, V4SF_type_node,
8583 V4SI_type_node, NULL_TREE);
8584 tree v4sf_ftype_v4sf_v4sf_v4sf
8585 = build_function_type_list (V4SF_type_node,
8586 V4SF_type_node, V4SF_type_node,
8587 V4SF_type_node, NULL_TREE);
8588 tree v4si_ftype_v4si_v4si_v4si
8589 = build_function_type_list (V4SI_type_node,
8590 V4SI_type_node, V4SI_type_node,
8591 V4SI_type_node, NULL_TREE);
8592 tree v8hi_ftype_v8hi_v8hi
8593 = build_function_type_list (V8HI_type_node,
8594 V8HI_type_node, V8HI_type_node, NULL_TREE);
8595 tree v8hi_ftype_v8hi_v8hi_v8hi
8596 = build_function_type_list (V8HI_type_node,
8597 V8HI_type_node, V8HI_type_node,
8598 V8HI_type_node, NULL_TREE);
8599 tree v4si_ftype_v8hi_v8hi_v4si
8600 = build_function_type_list (V4SI_type_node,
8601 V8HI_type_node, V8HI_type_node,
8602 V4SI_type_node, NULL_TREE);
8603 tree v4si_ftype_v16qi_v16qi_v4si
8604 = build_function_type_list (V4SI_type_node,
8605 V16QI_type_node, V16QI_type_node,
8606 V4SI_type_node, NULL_TREE);
8607 tree v16qi_ftype_v16qi_v16qi
8608 = build_function_type_list (V16QI_type_node,
8609 V16QI_type_node, V16QI_type_node, NULL_TREE);
8610 tree v4si_ftype_v4sf_v4sf
8611 = build_function_type_list (V4SI_type_node,
8612 V4SF_type_node, V4SF_type_node, NULL_TREE);
8613 tree v8hi_ftype_v16qi_v16qi
8614 = build_function_type_list (V8HI_type_node,
8615 V16QI_type_node, V16QI_type_node, NULL_TREE);
8616 tree v4si_ftype_v8hi_v8hi
8617 = build_function_type_list (V4SI_type_node,
8618 V8HI_type_node, V8HI_type_node, NULL_TREE);
8619 tree v8hi_ftype_v4si_v4si
8620 = build_function_type_list (V8HI_type_node,
8621 V4SI_type_node, V4SI_type_node, NULL_TREE);
8622 tree v16qi_ftype_v8hi_v8hi
8623 = build_function_type_list (V16QI_type_node,
8624 V8HI_type_node, V8HI_type_node, NULL_TREE);
8625 tree v4si_ftype_v16qi_v4si
8626 = build_function_type_list (V4SI_type_node,
8627 V16QI_type_node, V4SI_type_node, NULL_TREE);
8628 tree v4si_ftype_v16qi_v16qi
8629 = build_function_type_list (V4SI_type_node,
8630 V16QI_type_node, V16QI_type_node, NULL_TREE);
8631 tree v4si_ftype_v8hi_v4si
8632 = build_function_type_list (V4SI_type_node,
8633 V8HI_type_node, V4SI_type_node, NULL_TREE);
8634 tree v4si_ftype_v8hi
8635 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8636 tree int_ftype_v4si_v4si
8637 = build_function_type_list (integer_type_node,
8638 V4SI_type_node, V4SI_type_node, NULL_TREE);
8639 tree int_ftype_v4sf_v4sf
8640 = build_function_type_list (integer_type_node,
8641 V4SF_type_node, V4SF_type_node, NULL_TREE);
8642 tree int_ftype_v16qi_v16qi
8643 = build_function_type_list (integer_type_node,
8644 V16QI_type_node, V16QI_type_node, NULL_TREE);
8645 tree int_ftype_v8hi_v8hi
8646 = build_function_type_list (integer_type_node,
8647 V8HI_type_node, V8HI_type_node, NULL_TREE);
8649 /* Add the simple ternary operators. */
8650 d = (struct builtin_description *) bdesc_3arg;
8651 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8653 enum machine_mode mode0, mode1, mode2, mode3;
8655 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8656 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8667 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8670 mode0 = insn_data[d->icode].operand[0].mode;
8671 mode1 = insn_data[d->icode].operand[1].mode;
8672 mode2 = insn_data[d->icode].operand[2].mode;
8673 mode3 = insn_data[d->icode].operand[3].mode;
8676 /* When all four are of the same mode. */
8677 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8682 type = opaque_ftype_opaque_opaque_opaque;
8685 type = v4si_ftype_v4si_v4si_v4si;
8688 type = v4sf_ftype_v4sf_v4sf_v4sf;
8691 type = v8hi_ftype_v8hi_v8hi_v8hi;
8694 type = v16qi_ftype_v16qi_v16qi_v16qi;
8700 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8705 type = v4si_ftype_v4si_v4si_v16qi;
8708 type = v4sf_ftype_v4sf_v4sf_v16qi;
8711 type = v8hi_ftype_v8hi_v8hi_v16qi;
8714 type = v16qi_ftype_v16qi_v16qi_v16qi;
8720 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8721 && mode3 == V4SImode)
8722 type = v4si_ftype_v16qi_v16qi_v4si;
8723 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8724 && mode3 == V4SImode)
8725 type = v4si_ftype_v8hi_v8hi_v4si;
8726 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8727 && mode3 == V4SImode)
8728 type = v4sf_ftype_v4sf_v4sf_v4si;
8730 /* vchar, vchar, vchar, 4 bit literal. */
8731 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8733 type = v16qi_ftype_v16qi_v16qi_int;
8735 /* vshort, vshort, vshort, 4 bit literal. */
8736 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8738 type = v8hi_ftype_v8hi_v8hi_int;
8740 /* vint, vint, vint, 4 bit literal. */
8741 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8743 type = v4si_ftype_v4si_v4si_int;
8745 /* vfloat, vfloat, vfloat, 4 bit literal. */
8746 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8748 type = v4sf_ftype_v4sf_v4sf_int;
8753 def_builtin (d->mask, d->name, type, d->code);
8756 /* Add the simple binary operators. */
8757 d = (struct builtin_description *) bdesc_2arg;
8758 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8760 enum machine_mode mode0, mode1, mode2;
8762 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8763 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8773 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8776 mode0 = insn_data[d->icode].operand[0].mode;
8777 mode1 = insn_data[d->icode].operand[1].mode;
8778 mode2 = insn_data[d->icode].operand[2].mode;
8781 /* When all three operands are of the same mode. */
8782 if (mode0 == mode1 && mode1 == mode2)
8787 type = opaque_ftype_opaque_opaque;
8790 type = v4sf_ftype_v4sf_v4sf;
8793 type = v4si_ftype_v4si_v4si;
8796 type = v16qi_ftype_v16qi_v16qi;
8799 type = v8hi_ftype_v8hi_v8hi;
8802 type = v2si_ftype_v2si_v2si;
8805 type = v2sf_ftype_v2sf_v2sf;
8808 type = int_ftype_int_int;
8815 /* A few other combos we really don't want to do manually. */
8817 /* vint, vfloat, vfloat. */
8818 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8819 type = v4si_ftype_v4sf_v4sf;
8821 /* vshort, vchar, vchar. */
8822 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8823 type = v8hi_ftype_v16qi_v16qi;
8825 /* vint, vshort, vshort. */
8826 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8827 type = v4si_ftype_v8hi_v8hi;
8829 /* vshort, vint, vint. */
8830 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8831 type = v8hi_ftype_v4si_v4si;
8833 /* vchar, vshort, vshort. */
8834 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8835 type = v16qi_ftype_v8hi_v8hi;
8837 /* vint, vchar, vint. */
8838 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8839 type = v4si_ftype_v16qi_v4si;
8841 /* vint, vchar, vchar. */
8842 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8843 type = v4si_ftype_v16qi_v16qi;
8845 /* vint, vshort, vint. */
8846 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8847 type = v4si_ftype_v8hi_v4si;
8849 /* vint, vint, 5 bit literal. */
8850 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8851 type = v4si_ftype_v4si_int;
8853 /* vshort, vshort, 5 bit literal. */
8854 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8855 type = v8hi_ftype_v8hi_int;
8857 /* vchar, vchar, 5 bit literal. */
8858 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8859 type = v16qi_ftype_v16qi_int;
8861 /* vfloat, vint, 5 bit literal. */
8862 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8863 type = v4sf_ftype_v4si_int;
8865 /* vint, vfloat, 5 bit literal. */
8866 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8867 type = v4si_ftype_v4sf_int;
8869 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8870 type = v2si_ftype_int_int;
8872 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8873 type = v2si_ftype_v2si_char;
8875 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8876 type = v2si_ftype_int_char;
8881 gcc_assert (mode0 == SImode);
8885 type = int_ftype_v4si_v4si;
8888 type = int_ftype_v4sf_v4sf;
8891 type = int_ftype_v16qi_v16qi;
8894 type = int_ftype_v8hi_v8hi;
8901 def_builtin (d->mask, d->name, type, d->code);
8904 /* Add the simple unary operators. */
8905 d = (struct builtin_description *) bdesc_1arg;
8906 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8908 enum machine_mode mode0, mode1;
8910 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8911 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8920 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8923 mode0 = insn_data[d->icode].operand[0].mode;
8924 mode1 = insn_data[d->icode].operand[1].mode;
8927 if (mode0 == V4SImode && mode1 == QImode)
8928 type = v4si_ftype_int;
8929 else if (mode0 == V8HImode && mode1 == QImode)
8930 type = v8hi_ftype_int;
8931 else if (mode0 == V16QImode && mode1 == QImode)
8932 type = v16qi_ftype_int;
8933 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8934 type = opaque_ftype_opaque;
8935 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8936 type = v4sf_ftype_v4sf;
8937 else if (mode0 == V8HImode && mode1 == V16QImode)
8938 type = v8hi_ftype_v16qi;
8939 else if (mode0 == V4SImode && mode1 == V8HImode)
8940 type = v4si_ftype_v8hi;
8941 else if (mode0 == V2SImode && mode1 == V2SImode)
8942 type = v2si_ftype_v2si;
8943 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8944 type = v2sf_ftype_v2sf;
8945 else if (mode0 == V2SFmode && mode1 == V2SImode)
8946 type = v2sf_ftype_v2si;
8947 else if (mode0 == V2SImode && mode1 == V2SFmode)
8948 type = v2si_ftype_v2sf;
8949 else if (mode0 == V2SImode && mode1 == QImode)
8950 type = v2si_ftype_char;
8954 def_builtin (d->mask, d->name, type, d->code);
8959 rs6000_init_libfuncs (void)
8961 if (!TARGET_HARD_FLOAT)
8964 if (DEFAULT_ABI != ABI_V4)
8966 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8968 /* AIX library routines for float->int conversion. */
8969 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8970 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8971 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8972 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8975 /* AIX/Darwin/64-bit Linux quad floating point routines. */
8976 if (!TARGET_XL_COMPAT)
8978 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8979 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8980 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8981 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8985 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8986 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8987 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8988 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8993 /* 32-bit SVR4 quad floating point routines. */
8995 set_optab_libfunc (add_optab, TFmode, "_q_add");
8996 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8997 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8998 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8999 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9000 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9001 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9003 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9004 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9005 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9006 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9007 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9008 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9010 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9011 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9012 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9013 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9014 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9015 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9016 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9021 /* Expand a block clear operation, and return 1 if successful. Return 0
9022 if we should let the compiler generate normal code.
9024 operands[0] is the destination
9025 operands[1] is the length
9026 operands[3] is the alignment */
9029 expand_block_clear (rtx operands[])
9031 rtx orig_dest = operands[0];
9032 rtx bytes_rtx = operands[1];
9033 rtx align_rtx = operands[3];
9034 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9035 HOST_WIDE_INT align;
9036 HOST_WIDE_INT bytes;
9041 /* If this is not a fixed size move, just call memcpy */
9045 /* This must be a fixed size alignment */
9046 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9047 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9049 /* Anything to clear? */
9050 bytes = INTVAL (bytes_rtx);
9054 /* Use the builtin memset after a point, to avoid huge code bloat.
9055 When optimize_size, avoid any significant code bloat; calling
9056 memset is about 4 instructions, so allow for one instruction to
9057 load zero and three to do clearing. */
9058 if (TARGET_ALTIVEC && align >= 128)
9060 else if (TARGET_POWERPC64 && align >= 32)
9065 if (optimize_size && bytes > 3 * clear_step)
9067 if (! optimize_size && bytes > 8 * clear_step)
9070 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9072 enum machine_mode mode = BLKmode;
9075 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9080 else if (bytes >= 8 && TARGET_POWERPC64
9081 /* 64-bit loads and stores require word-aligned
9083 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9088 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9089 { /* move 4 bytes */
9093 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9094 { /* move 2 bytes */
9098 else /* move 1 byte at a time */
9104 dest = adjust_address (orig_dest, mode, offset);
9106 emit_move_insn (dest, CONST0_RTX (mode));
9113 /* Expand a block move operation, and return 1 if successful. Return 0
9114 if we should let the compiler generate normal code.
9116 operands[0] is the destination
9117 operands[1] is the source
9118 operands[2] is the length
9119 operands[3] is the alignment */
9121 #define MAX_MOVE_REG 4
9124 expand_block_move (rtx operands[])
9126 rtx orig_dest = operands[0];
9127 rtx orig_src = operands[1];
9128 rtx bytes_rtx = operands[2];
9129 rtx align_rtx = operands[3];
9130 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9135 rtx stores[MAX_MOVE_REG];
9138 /* If this is not a fixed size move, just call memcpy */
9142 /* This must be a fixed size alignment */
9143 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9144 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9146 /* Anything to move? */
9147 bytes = INTVAL (bytes_rtx);
9151 /* store_one_arg depends on expand_block_move to handle at least the size of
9152 reg_parm_stack_space. */
9153 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9156 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9159 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9160 rtx (*mov) (rtx, rtx);
9162 enum machine_mode mode = BLKmode;
9165 /* Altivec first, since it will be faster than a string move
9166 when it applies, and usually not significantly larger. */
9167 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9171 gen_func.mov = gen_movv4si;
9173 else if (TARGET_STRING
9174 && bytes > 24 /* move up to 32 bytes at a time */
9182 && ! fixed_regs[12])
9184 move_bytes = (bytes > 32) ? 32 : bytes;
9185 gen_func.movmemsi = gen_movmemsi_8reg;
9187 else if (TARGET_STRING
9188 && bytes > 16 /* move up to 24 bytes at a time */
9194 && ! fixed_regs[10])
9196 move_bytes = (bytes > 24) ? 24 : bytes;
9197 gen_func.movmemsi = gen_movmemsi_6reg;
9199 else if (TARGET_STRING
9200 && bytes > 8 /* move up to 16 bytes at a time */
9206 move_bytes = (bytes > 16) ? 16 : bytes;
9207 gen_func.movmemsi = gen_movmemsi_4reg;
9209 else if (bytes >= 8 && TARGET_POWERPC64
9210 /* 64-bit loads and stores require word-aligned
9212 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9216 gen_func.mov = gen_movdi;
9218 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9219 { /* move up to 8 bytes at a time */
9220 move_bytes = (bytes > 8) ? 8 : bytes;
9221 gen_func.movmemsi = gen_movmemsi_2reg;
9223 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9224 { /* move 4 bytes */
9227 gen_func.mov = gen_movsi;
9229 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9230 { /* move 2 bytes */
9233 gen_func.mov = gen_movhi;
9235 else if (TARGET_STRING && bytes > 1)
9236 { /* move up to 4 bytes at a time */
9237 move_bytes = (bytes > 4) ? 4 : bytes;
9238 gen_func.movmemsi = gen_movmemsi_1reg;
9240 else /* move 1 byte at a time */
9244 gen_func.mov = gen_movqi;
9247 src = adjust_address (orig_src, mode, offset);
9248 dest = adjust_address (orig_dest, mode, offset);
9250 if (mode != BLKmode)
9252 rtx tmp_reg = gen_reg_rtx (mode);
9254 emit_insn ((*gen_func.mov) (tmp_reg, src));
9255 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9258 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9261 for (i = 0; i < num_reg; i++)
9262 emit_insn (stores[i]);
9266 if (mode == BLKmode)
9268 /* Move the address into scratch registers. The movmemsi
9269 patterns require zero offset. */
9270 if (!REG_P (XEXP (src, 0)))
9272 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9273 src = replace_equiv_address (src, src_reg);
9275 set_mem_size (src, GEN_INT (move_bytes));
9277 if (!REG_P (XEXP (dest, 0)))
9279 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9280 dest = replace_equiv_address (dest, dest_reg);
9282 set_mem_size (dest, GEN_INT (move_bytes));
9284 emit_insn ((*gen_func.movmemsi) (dest, src,
9285 GEN_INT (move_bytes & 31),
9294 /* Return a string to perform a load_multiple operation.
9295 operands[0] is the vector.
9296 operands[1] is the source address.
9297 operands[2] is the first destination register. */
9300 rs6000_output_load_multiple (rtx operands[3])
9302 /* We have to handle the case where the pseudo used to contain the address
9303 is assigned to one of the output registers. */
9305 int words = XVECLEN (operands[0], 0);
9308 if (XVECLEN (operands[0], 0) == 1)
9309 return "{l|lwz} %2,0(%1)";
9311 for (i = 0; i < words; i++)
9312 if (refers_to_regno_p (REGNO (operands[2]) + i,
9313 REGNO (operands[2]) + i + 1, operands[1], 0))
9317 xop[0] = GEN_INT (4 * (words-1));
9318 xop[1] = operands[1];
9319 xop[2] = operands[2];
9320 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9325 xop[0] = GEN_INT (4 * (words-1));
9326 xop[1] = operands[1];
9327 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9328 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9333 for (j = 0; j < words; j++)
9336 xop[0] = GEN_INT (j * 4);
9337 xop[1] = operands[1];
9338 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9339 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9341 xop[0] = GEN_INT (i * 4);
9342 xop[1] = operands[1];
9343 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9348 return "{lsi|lswi} %2,%1,%N0";
9352 /* A validation routine: say whether CODE, a condition code, and MODE
9353 match. The other alternatives either don't make sense or should
9354 never be generated. */
9357 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9359 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9360 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9361 && GET_MODE_CLASS (mode) == MODE_CC);
9363 /* These don't make sense. */
9364 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9365 || mode != CCUNSmode);
9367 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9368 || mode == CCUNSmode);
9370 gcc_assert (mode == CCFPmode
9371 || (code != ORDERED && code != UNORDERED
9372 && code != UNEQ && code != LTGT
9373 && code != UNGT && code != UNLT
9374 && code != UNGE && code != UNLE));
9376 /* These should never be generated except for
9377 flag_finite_math_only. */
9378 gcc_assert (mode != CCFPmode
9379 || flag_finite_math_only
9380 || (code != LE && code != GE
9381 && code != UNEQ && code != LTGT
9382 && code != UNGT && code != UNLT));
9384 /* These are invalid; the information is not there. */
9385 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9389 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9390 mask required to convert the result of a rotate insn into a shift
9391 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9394 includes_lshift_p (rtx shiftop, rtx andop)
9396 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9398 shift_mask <<= INTVAL (shiftop);
9400 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9403 /* Similar, but for right shift. */
9406 includes_rshift_p (rtx shiftop, rtx andop)
9408 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9410 shift_mask >>= INTVAL (shiftop);
9412 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9415 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9416 to perform a left shift. It must have exactly SHIFTOP least
9417 significant 0's, then one or more 1's, then zero or more 0's. */
9420 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9422 if (GET_CODE (andop) == CONST_INT)
9424 HOST_WIDE_INT c, lsb, shift_mask;
9427 if (c == 0 || c == ~0)
9431 shift_mask <<= INTVAL (shiftop);
9433 /* Find the least significant one bit. */
9436 /* It must coincide with the LSB of the shift mask. */
9437 if (-lsb != shift_mask)
9440 /* Invert to look for the next transition (if any). */
9443 /* Remove the low group of ones (originally low group of zeros). */
9446 /* Again find the lsb, and check we have all 1's above. */
9450 else if (GET_CODE (andop) == CONST_DOUBLE
9451 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9453 HOST_WIDE_INT low, high, lsb;
9454 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9456 low = CONST_DOUBLE_LOW (andop);
9457 if (HOST_BITS_PER_WIDE_INT < 64)
9458 high = CONST_DOUBLE_HIGH (andop);
9460 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9461 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9464 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9466 shift_mask_high = ~0;
9467 if (INTVAL (shiftop) > 32)
9468 shift_mask_high <<= INTVAL (shiftop) - 32;
9472 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9479 return high == -lsb;
9482 shift_mask_low = ~0;
9483 shift_mask_low <<= INTVAL (shiftop);
9487 if (-lsb != shift_mask_low)
9490 if (HOST_BITS_PER_WIDE_INT < 64)
9495 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9498 return high == -lsb;
9502 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9508 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9509 to perform a left shift. It must have SHIFTOP or more least
9510 significant 0's, with the remainder of the word 1's. */
9513 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9515 if (GET_CODE (andop) == CONST_INT)
9517 HOST_WIDE_INT c, lsb, shift_mask;
9520 shift_mask <<= INTVAL (shiftop);
9523 /* Find the least significant one bit. */
9526 /* It must be covered by the shift mask.
9527 This test also rejects c == 0. */
9528 if ((lsb & shift_mask) == 0)
9531 /* Check we have all 1's above the transition, and reject all 1's. */
9532 return c == -lsb && lsb != 1;
9534 else if (GET_CODE (andop) == CONST_DOUBLE
9535 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9537 HOST_WIDE_INT low, lsb, shift_mask_low;
9539 low = CONST_DOUBLE_LOW (andop);
9541 if (HOST_BITS_PER_WIDE_INT < 64)
9543 HOST_WIDE_INT high, shift_mask_high;
9545 high = CONST_DOUBLE_HIGH (andop);
9549 shift_mask_high = ~0;
9550 if (INTVAL (shiftop) > 32)
9551 shift_mask_high <<= INTVAL (shiftop) - 32;
9555 if ((lsb & shift_mask_high) == 0)
9558 return high == -lsb;
9564 shift_mask_low = ~0;
9565 shift_mask_low <<= INTVAL (shiftop);
9569 if ((lsb & shift_mask_low) == 0)
9572 return low == -lsb && lsb != 1;
9578 /* Return 1 if operands will generate a valid arguments to rlwimi
9579 instruction for insert with right shift in 64-bit mode. The mask may
9580 not start on the first bit or stop on the last bit because wrap-around
9581 effects of instruction do not correspond to semantics of RTL insn. */
9584 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9586 if (INTVAL (startop) < 64
9587 && INTVAL (startop) > 32
9588 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9589 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9590 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9591 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9592 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9598 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9599 for lfq and stfq insns iff the registers are hard registers. */
9602 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9604 /* We might have been passed a SUBREG. */
9605 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9608 /* We might have been passed non floating point registers. */
9609 if (!FP_REGNO_P (REGNO (reg1))
9610 || !FP_REGNO_P (REGNO (reg2)))
9613 return (REGNO (reg1) == REGNO (reg2) - 1);
9616 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9617 addr1 and addr2 must be in consecutive memory locations
9618 (addr2 == addr1 + 8). */
9621 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9624 unsigned int reg1, reg2;
9625 int offset1, offset2;
9627 /* The mems cannot be volatile. */
9628 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9631 addr1 = XEXP (mem1, 0);
9632 addr2 = XEXP (mem2, 0);
9634 /* Extract an offset (if used) from the first addr. */
9635 if (GET_CODE (addr1) == PLUS)
9637 /* If not a REG, return zero. */
9638 if (GET_CODE (XEXP (addr1, 0)) != REG)
9642 reg1 = REGNO (XEXP (addr1, 0));
9643 /* The offset must be constant! */
9644 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9646 offset1 = INTVAL (XEXP (addr1, 1));
9649 else if (GET_CODE (addr1) != REG)
9653 reg1 = REGNO (addr1);
9654 /* This was a simple (mem (reg)) expression. Offset is 0. */
9658 /* And now for the second addr. */
9659 if (GET_CODE (addr2) == PLUS)
9661 /* If not a REG, return zero. */
9662 if (GET_CODE (XEXP (addr2, 0)) != REG)
9666 reg2 = REGNO (XEXP (addr2, 0));
9667 /* The offset must be constant. */
9668 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9670 offset2 = INTVAL (XEXP (addr2, 1));
9673 else if (GET_CODE (addr2) != REG)
9677 reg2 = REGNO (addr2);
9678 /* This was a simple (mem (reg)) expression. Offset is 0. */
9682 /* Both of these must have the same base register. */
9686 /* The offset for the second addr must be 8 more than the first addr. */
9687 if (offset2 != offset1 + 8)
9690 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9695 /* Return the register class of a scratch register needed to copy IN into
9696 or out of a register in CLASS in MODE. If it can be done directly,
9697 NO_REGS is returned. */
9700 secondary_reload_class (enum reg_class class,
9701 enum machine_mode mode ATTRIBUTE_UNUSED,
9706 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9708 && MACHOPIC_INDIRECT
9712 /* We cannot copy a symbolic operand directly into anything
9713 other than BASE_REGS for TARGET_ELF. So indicate that a
9714 register from BASE_REGS is needed as an intermediate
9717 On Darwin, pic addresses require a load from memory, which
9718 needs a base register. */
9719 if (class != BASE_REGS
9720 && (GET_CODE (in) == SYMBOL_REF
9721 || GET_CODE (in) == HIGH
9722 || GET_CODE (in) == LABEL_REF
9723 || GET_CODE (in) == CONST))
9727 if (GET_CODE (in) == REG)
9730 if (regno >= FIRST_PSEUDO_REGISTER)
9732 regno = true_regnum (in);
9733 if (regno >= FIRST_PSEUDO_REGISTER)
9737 else if (GET_CODE (in) == SUBREG)
9739 regno = true_regnum (in);
9740 if (regno >= FIRST_PSEUDO_REGISTER)
9746 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9748 if (class == GENERAL_REGS || class == BASE_REGS
9749 || (regno >= 0 && INT_REGNO_P (regno)))
9752 /* Constants, memory, and FP registers can go into FP registers. */
9753 if ((regno == -1 || FP_REGNO_P (regno))
9754 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9757 /* Memory, and AltiVec registers can go into AltiVec registers. */
9758 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9759 && class == ALTIVEC_REGS)
9762 /* We can copy among the CR registers. */
9763 if ((class == CR_REGS || class == CR0_REGS)
9764 && regno >= 0 && CR_REGNO_P (regno))
9767 /* Otherwise, we need GENERAL_REGS. */
9768 return GENERAL_REGS;
9771 /* Given a comparison operation, return the bit number in CCR to test. We
9772 know this is a valid comparison.
9774 SCC_P is 1 if this is for an scc. That means that %D will have been
9775 used instead of %C, so the bits will be in different places.
9777 Return -1 if OP isn't a valid comparison for some reason. */
9780 ccr_bit (rtx op, int scc_p)
9782 enum rtx_code code = GET_CODE (op);
9783 enum machine_mode cc_mode;
9788 if (!COMPARISON_P (op))
9793 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9795 cc_mode = GET_MODE (reg);
9796 cc_regnum = REGNO (reg);
9797 base_bit = 4 * (cc_regnum - CR0_REGNO);
9799 validate_condition_mode (code, cc_mode);
9801 /* When generating a sCOND operation, only positive conditions are
9804 || code == EQ || code == GT || code == LT || code == UNORDERED
9805 || code == GTU || code == LTU);
9810 return scc_p ? base_bit + 3 : base_bit + 2;
9812 return base_bit + 2;
9813 case GT: case GTU: case UNLE:
9814 return base_bit + 1;
9815 case LT: case LTU: case UNGE:
9817 case ORDERED: case UNORDERED:
9818 return base_bit + 3;
9821 /* If scc, we will have done a cror to put the bit in the
9822 unordered position. So test that bit. For integer, this is ! LT
9823 unless this is an scc insn. */
9824 return scc_p ? base_bit + 3 : base_bit;
9827 return scc_p ? base_bit + 3 : base_bit + 1;
9834 /* Return the GOT register. */
9837 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9839 /* The second flow pass currently (June 1999) can't update
9840 regs_ever_live without disturbing other parts of the compiler, so
9841 update it here to make the prolog/epilogue code happy. */
9842 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9843 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9845 current_function_uses_pic_offset_table = 1;
9847 return pic_offset_table_rtx;
9850 /* Function to init struct machine_function.
9851 This will be called, via a pointer variable,
9852 from push_function_context. */
9854 static struct machine_function *
9855 rs6000_init_machine_status (void)
9857 return ggc_alloc_cleared (sizeof (machine_function));
9860 /* These macros test for integers and extract the low-order bits. */
9862 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9863 && GET_MODE (X) == VOIDmode)
9865 #define INT_LOWPART(X) \
9866 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9872 unsigned long val = INT_LOWPART (op);
9874 /* If the high bit is zero, the value is the first 1 bit we find
9876 if ((val & 0x80000000) == 0)
9878 gcc_assert (val & 0xffffffff);
9881 while (((val <<= 1) & 0x80000000) == 0)
9886 /* If the high bit is set and the low bit is not, or the mask is all
9887 1's, the value is zero. */
9888 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9891 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9894 while (((val >>= 1) & 1) != 0)
9904 unsigned long val = INT_LOWPART (op);
9906 /* If the low bit is zero, the value is the first 1 bit we find from
9910 gcc_assert (val & 0xffffffff);
9913 while (((val >>= 1) & 1) == 0)
9919 /* If the low bit is set and the high bit is not, or the mask is all
9920 1's, the value is 31. */
9921 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9924 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9927 while (((val <<= 1) & 0x80000000) != 0)
9933 /* Locate some local-dynamic symbol still in use by this function
9934 so that we can print its name in some tls_ld pattern. */
9937 rs6000_get_some_local_dynamic_name (void)
9941 if (cfun->machine->some_ld_name)
9942 return cfun->machine->some_ld_name;
9944 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9946 && for_each_rtx (&PATTERN (insn),
9947 rs6000_get_some_local_dynamic_name_1, 0))
9948 return cfun->machine->some_ld_name;
9953 /* Helper function for rs6000_get_some_local_dynamic_name. */
9956 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9960 if (GET_CODE (x) == SYMBOL_REF)
9962 const char *str = XSTR (x, 0);
9963 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9965 cfun->machine->some_ld_name = str;
9973 /* Write out a function code label. */
9976 rs6000_output_function_entry (FILE *file, const char *fname)
9978 if (fname[0] != '.')
9980 switch (DEFAULT_ABI)
9989 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9998 RS6000_OUTPUT_BASENAME (file, fname);
10000 assemble_name (file, fname);
10003 /* Print an operand. Recognize special options, documented below. */
10006 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10007 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10009 #define SMALL_DATA_RELOC "sda21"
10010 #define SMALL_DATA_REG 0
10014 print_operand (FILE *file, rtx x, int code)
10018 unsigned HOST_WIDE_INT uval;
10023 /* Write out an instruction after the call which may be replaced
10024 with glue code by the loader. This depends on the AIX version. */
10025 asm_fprintf (file, RS6000_CALL_GLUE);
10028 /* %a is output_address. */
10031 /* If X is a constant integer whose low-order 5 bits are zero,
10032 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10033 in the AIX assembler where "sri" with a zero shift count
10034 writes a trash instruction. */
10035 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10042 /* If constant, low-order 16 bits of constant, unsigned.
10043 Otherwise, write normally. */
10045 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10047 print_operand (file, x, 0);
10051 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10052 for 64-bit mask direction. */
10053 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10056 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10060 /* X is a CR register. Print the number of the GT bit of the CR. */
10061 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10062 output_operand_lossage ("invalid %%E value");
10064 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10068 /* Like 'J' but get to the EQ bit. */
10069 gcc_assert (GET_CODE (x) == REG);
10071 /* Bit 1 is EQ bit. */
10072 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10074 fprintf (file, "%d", i);
10078 /* X is a CR register. Print the number of the EQ bit of the CR */
10079 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10080 output_operand_lossage ("invalid %%E value");
10082 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10086 /* X is a CR register. Print the shift count needed to move it
10087 to the high-order four bits. */
10088 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10089 output_operand_lossage ("invalid %%f value");
10091 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10095 /* Similar, but print the count for the rotate in the opposite
10097 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10098 output_operand_lossage ("invalid %%F value");
10100 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10104 /* X is a constant integer. If it is negative, print "m",
10105 otherwise print "z". This is to make an aze or ame insn. */
10106 if (GET_CODE (x) != CONST_INT)
10107 output_operand_lossage ("invalid %%G value");
10108 else if (INTVAL (x) >= 0)
10115 /* If constant, output low-order five bits. Otherwise, write
10118 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10120 print_operand (file, x, 0);
10124 /* If constant, output low-order six bits. Otherwise, write
10127 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10129 print_operand (file, x, 0);
10133 /* Print `i' if this is a constant, else nothing. */
10139 /* Write the bit number in CCR for jump. */
10140 i = ccr_bit (x, 0);
10142 output_operand_lossage ("invalid %%j code");
10144 fprintf (file, "%d", i);
10148 /* Similar, but add one for shift count in rlinm for scc and pass
10149 scc flag to `ccr_bit'. */
10150 i = ccr_bit (x, 1);
10152 output_operand_lossage ("invalid %%J code");
10154 /* If we want bit 31, write a shift count of zero, not 32. */
10155 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10159 /* X must be a constant. Write the 1's complement of the
10162 output_operand_lossage ("invalid %%k value");
10164 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10168 /* X must be a symbolic constant on ELF. Write an
10169 expression suitable for an 'addi' that adds in the low 16
10170 bits of the MEM. */
10171 if (GET_CODE (x) != CONST)
10173 print_operand_address (file, x);
10174 fputs ("@l", file);
10178 if (GET_CODE (XEXP (x, 0)) != PLUS
10179 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10180 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10181 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10182 output_operand_lossage ("invalid %%K value");
10183 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10184 fputs ("@l", file);
10185 /* For GNU as, there must be a non-alphanumeric character
10186 between 'l' and the number. The '-' is added by
10187 print_operand() already. */
10188 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10190 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10194 /* %l is output_asm_label. */
10197 /* Write second word of DImode or DFmode reference. Works on register
10198 or non-indexed memory only. */
10199 if (GET_CODE (x) == REG)
10200 fputs (reg_names[REGNO (x) + 1], file);
10201 else if (GET_CODE (x) == MEM)
10203 /* Handle possible auto-increment. Since it is pre-increment and
10204 we have already done it, we can just use an offset of word. */
10205 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10206 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10207 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10210 output_address (XEXP (adjust_address_nv (x, SImode,
10214 if (small_data_operand (x, GET_MODE (x)))
10215 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10216 reg_names[SMALL_DATA_REG]);
10221 /* MB value for a mask operand. */
10222 if (! mask_operand (x, SImode))
10223 output_operand_lossage ("invalid %%m value");
10225 fprintf (file, "%d", extract_MB (x));
10229 /* ME value for a mask operand. */
10230 if (! mask_operand (x, SImode))
10231 output_operand_lossage ("invalid %%M value");
10233 fprintf (file, "%d", extract_ME (x));
10236 /* %n outputs the negative of its operand. */
10239 /* Write the number of elements in the vector times 4. */
10240 if (GET_CODE (x) != PARALLEL)
10241 output_operand_lossage ("invalid %%N value");
10243 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10247 /* Similar, but subtract 1 first. */
10248 if (GET_CODE (x) != PARALLEL)
10249 output_operand_lossage ("invalid %%O value");
10251 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10255 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10257 || INT_LOWPART (x) < 0
10258 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10259 output_operand_lossage ("invalid %%p value");
10261 fprintf (file, "%d", i);
10265 /* The operand must be an indirect memory reference. The result
10266 is the register name. */
10267 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10268 || REGNO (XEXP (x, 0)) >= 32)
10269 output_operand_lossage ("invalid %%P value");
10271 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10275 /* This outputs the logical code corresponding to a boolean
10276 expression. The expression may have one or both operands
10277 negated (if one, only the first one). For condition register
10278 logical operations, it will also treat the negated
10279 CR codes as NOTs, but not handle NOTs of them. */
10281 const char *const *t = 0;
10283 enum rtx_code code = GET_CODE (x);
10284 static const char * const tbl[3][3] = {
10285 { "and", "andc", "nor" },
10286 { "or", "orc", "nand" },
10287 { "xor", "eqv", "xor" } };
10291 else if (code == IOR)
10293 else if (code == XOR)
10296 output_operand_lossage ("invalid %%q value");
10298 if (GET_CODE (XEXP (x, 0)) != NOT)
10302 if (GET_CODE (XEXP (x, 1)) == NOT)
10320 /* X is a CR register. Print the mask for `mtcrf'. */
10321 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10322 output_operand_lossage ("invalid %%R value");
10324 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10328 /* Low 5 bits of 32 - value */
10330 output_operand_lossage ("invalid %%s value");
10332 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10336 /* PowerPC64 mask position. All 0's is excluded.
10337 CONST_INT 32-bit mask is considered sign-extended so any
10338 transition must occur within the CONST_INT, not on the boundary. */
10339 if (! mask64_operand (x, DImode))
10340 output_operand_lossage ("invalid %%S value");
10342 uval = INT_LOWPART (x);
10344 if (uval & 1) /* Clear Left */
10346 #if HOST_BITS_PER_WIDE_INT > 64
10347 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10351 else /* Clear Right */
10354 #if HOST_BITS_PER_WIDE_INT > 64
10355 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10361 gcc_assert (i >= 0);
10362 fprintf (file, "%d", i);
10366 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10367 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10369 /* Bit 3 is OV bit. */
10370 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10372 /* If we want bit 31, write a shift count of zero, not 32. */
10373 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10377 /* Print the symbolic name of a branch target register. */
10378 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10379 && REGNO (x) != COUNT_REGISTER_REGNUM))
10380 output_operand_lossage ("invalid %%T value");
10381 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10382 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10384 fputs ("ctr", file);
10388 /* High-order 16 bits of constant for use in unsigned operand. */
10390 output_operand_lossage ("invalid %%u value");
10392 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10393 (INT_LOWPART (x) >> 16) & 0xffff);
10397 /* High-order 16 bits of constant for use in signed operand. */
10399 output_operand_lossage ("invalid %%v value");
10401 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10402 (INT_LOWPART (x) >> 16) & 0xffff);
10406 /* Print `u' if this has an auto-increment or auto-decrement. */
10407 if (GET_CODE (x) == MEM
10408 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10409 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10414 /* Print the trap code for this operand. */
10415 switch (GET_CODE (x))
10418 fputs ("eq", file); /* 4 */
10421 fputs ("ne", file); /* 24 */
10424 fputs ("lt", file); /* 16 */
10427 fputs ("le", file); /* 20 */
10430 fputs ("gt", file); /* 8 */
10433 fputs ("ge", file); /* 12 */
10436 fputs ("llt", file); /* 2 */
10439 fputs ("lle", file); /* 6 */
10442 fputs ("lgt", file); /* 1 */
10445 fputs ("lge", file); /* 5 */
10448 gcc_unreachable ();
10453 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10456 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10457 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10459 print_operand (file, x, 0);
10463 /* MB value for a PowerPC64 rldic operand. */
10464 val = (GET_CODE (x) == CONST_INT
10465 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10470 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10471 if ((val <<= 1) < 0)
10474 #if HOST_BITS_PER_WIDE_INT == 32
10475 if (GET_CODE (x) == CONST_INT && i >= 0)
10476 i += 32; /* zero-extend high-part was all 0's */
10477 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10479 val = CONST_DOUBLE_LOW (x);
10485 for ( ; i < 64; i++)
10486 if ((val <<= 1) < 0)
10491 fprintf (file, "%d", i + 1);
10495 if (GET_CODE (x) == MEM
10496 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10501 /* Like 'L', for third word of TImode */
10502 if (GET_CODE (x) == REG)
10503 fputs (reg_names[REGNO (x) + 2], file);
10504 else if (GET_CODE (x) == MEM)
10506 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10507 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10508 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10510 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10511 if (small_data_operand (x, GET_MODE (x)))
10512 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10513 reg_names[SMALL_DATA_REG]);
10518 /* X is a SYMBOL_REF. Write out the name preceded by a
10519 period and without any trailing data in brackets. Used for function
10520 names. If we are configured for System V (or the embedded ABI) on
10521 the PowerPC, do not emit the period, since those systems do not use
10522 TOCs and the like. */
10523 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10525 /* Mark the decl as referenced so that cgraph will output the
10527 if (SYMBOL_REF_DECL (x))
10528 mark_decl_referenced (SYMBOL_REF_DECL (x));
10530 /* For macho, check to see if we need a stub. */
10533 const char *name = XSTR (x, 0);
10535 if (MACHOPIC_INDIRECT
10536 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10537 name = machopic_indirection_name (x, /*stub_p=*/true);
10539 assemble_name (file, name);
10541 else if (!DOT_SYMBOLS)
10542 assemble_name (file, XSTR (x, 0));
10544 rs6000_output_function_entry (file, XSTR (x, 0));
10548 /* Like 'L', for last word of TImode. */
10549 if (GET_CODE (x) == REG)
10550 fputs (reg_names[REGNO (x) + 3], file);
10551 else if (GET_CODE (x) == MEM)
10553 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10554 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10555 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10557 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10558 if (small_data_operand (x, GET_MODE (x)))
10559 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10560 reg_names[SMALL_DATA_REG]);
10564 /* Print AltiVec or SPE memory operand. */
10569 gcc_assert (GET_CODE (x) == MEM);
10575 /* Handle [reg]. */
10576 if (GET_CODE (tmp) == REG)
10578 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10581 /* Handle [reg+UIMM]. */
10582 else if (GET_CODE (tmp) == PLUS &&
10583 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10587 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10589 x = INTVAL (XEXP (tmp, 1));
10590 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10594 /* Fall through. Must be [reg+reg]. */
10597 && GET_CODE (tmp) == AND
10598 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10599 && INTVAL (XEXP (tmp, 1)) == -16)
10600 tmp = XEXP (tmp, 0);
10601 if (GET_CODE (tmp) == REG)
10602 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10605 gcc_assert (GET_CODE (tmp) == PLUS
10606 && GET_CODE (XEXP (tmp, 1)) == REG);
10608 if (REGNO (XEXP (tmp, 0)) == 0)
10609 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10610 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10612 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10613 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10619 if (GET_CODE (x) == REG)
10620 fprintf (file, "%s", reg_names[REGNO (x)]);
10621 else if (GET_CODE (x) == MEM)
10623 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10624 know the width from the mode. */
10625 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10626 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10627 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10628 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10629 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10630 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10632 output_address (XEXP (x, 0));
10635 output_addr_const (file, x);
10639 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10643 output_operand_lossage ("invalid %%xn code");
10647 /* Print the address of an operand. */
10650 print_operand_address (FILE *file, rtx x)
10652 if (GET_CODE (x) == REG)
10653 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10654 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10655 || GET_CODE (x) == LABEL_REF)
10657 output_addr_const (file, x);
10658 if (small_data_operand (x, GET_MODE (x)))
10659 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10660 reg_names[SMALL_DATA_REG]);
10662 gcc_assert (!TARGET_TOC);
10664 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10666 if (REGNO (XEXP (x, 0)) == 0)
10667 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10668 reg_names[ REGNO (XEXP (x, 0)) ]);
10670 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10671 reg_names[ REGNO (XEXP (x, 1)) ]);
10673 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10674 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10675 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10677 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10678 && CONSTANT_P (XEXP (x, 1)))
10680 output_addr_const (file, XEXP (x, 1));
10681 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10685 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10686 && CONSTANT_P (XEXP (x, 1)))
10688 fprintf (file, "lo16(");
10689 output_addr_const (file, XEXP (x, 1));
10690 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10693 else if (legitimate_constant_pool_address_p (x))
10695 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10697 rtx contains_minus = XEXP (x, 1);
10701 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10702 turn it into (sym) for output_addr_const. */
10703 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10704 contains_minus = XEXP (contains_minus, 0);
10706 minus = XEXP (contains_minus, 0);
10707 symref = XEXP (minus, 0);
10708 XEXP (contains_minus, 0) = symref;
10713 name = XSTR (symref, 0);
10714 newname = alloca (strlen (name) + sizeof ("@toc"));
10715 strcpy (newname, name);
10716 strcat (newname, "@toc");
10717 XSTR (symref, 0) = newname;
10719 output_addr_const (file, XEXP (x, 1));
10721 XSTR (symref, 0) = name;
10722 XEXP (contains_minus, 0) = minus;
10725 output_addr_const (file, XEXP (x, 1));
10727 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10730 gcc_unreachable ();
10733 /* Target hook for assembling integer objects. The PowerPC version has
10734 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10735 is defined. It also needs to handle DI-mode objects on 64-bit
10739 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10741 #ifdef RELOCATABLE_NEEDS_FIXUP
10742 /* Special handling for SI values. */
10743 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10745 extern int in_toc_section (void);
10746 static int recurse = 0;
10748 /* For -mrelocatable, we mark all addresses that need to be fixed up
10749 in the .fixup section. */
10750 if (TARGET_RELOCATABLE
10751 && !in_toc_section ()
10752 && !in_text_section ()
10753 && !in_unlikely_text_section ()
10755 && GET_CODE (x) != CONST_INT
10756 && GET_CODE (x) != CONST_DOUBLE
10762 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10764 ASM_OUTPUT_LABEL (asm_out_file, buf);
10765 fprintf (asm_out_file, "\t.long\t(");
10766 output_addr_const (asm_out_file, x);
10767 fprintf (asm_out_file, ")@fixup\n");
10768 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10769 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10770 fprintf (asm_out_file, "\t.long\t");
10771 assemble_name (asm_out_file, buf);
10772 fprintf (asm_out_file, "\n\t.previous\n");
10776 /* Remove initial .'s to turn a -mcall-aixdesc function
10777 address into the address of the descriptor, not the function
10779 else if (GET_CODE (x) == SYMBOL_REF
10780 && XSTR (x, 0)[0] == '.'
10781 && DEFAULT_ABI == ABI_AIX)
10783 const char *name = XSTR (x, 0);
10784 while (*name == '.')
10787 fprintf (asm_out_file, "\t.long\t%s\n", name);
10791 #endif /* RELOCATABLE_NEEDS_FIXUP */
10792 return default_assemble_integer (x, size, aligned_p);
10795 #ifdef HAVE_GAS_HIDDEN
10796 /* Emit an assembler directive to set symbol visibility for DECL to
10797 VISIBILITY_TYPE. */
10800 rs6000_assemble_visibility (tree decl, int vis)
10802 /* Functions need to have their entry point symbol visibility set as
10803 well as their descriptor symbol visibility. */
10804 if (DEFAULT_ABI == ABI_AIX
10806 && TREE_CODE (decl) == FUNCTION_DECL)
10808 static const char * const visibility_types[] = {
10809 NULL, "internal", "hidden", "protected"
10812 const char *name, *type;
10814 name = ((* targetm.strip_name_encoding)
10815 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10816 type = visibility_types[vis];
10818 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10819 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10822 default_assemble_visibility (decl, vis);
10827 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10829 /* Reversal of FP compares takes care -- an ordered compare
10830 becomes an unordered compare and vice versa. */
10831 if (mode == CCFPmode
10832 && (!flag_finite_math_only
10833 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10834 || code == UNEQ || code == LTGT))
10835 return reverse_condition_maybe_unordered (code);
10837 return reverse_condition (code);
10840 /* Generate a compare for CODE. Return a brand-new rtx that
10841 represents the result of the compare. */
10844 rs6000_generate_compare (enum rtx_code code)
10846 enum machine_mode comp_mode;
10847 rtx compare_result;
10849 if (rs6000_compare_fp_p)
10850 comp_mode = CCFPmode;
10851 else if (code == GTU || code == LTU
10852 || code == GEU || code == LEU)
10853 comp_mode = CCUNSmode;
10854 else if ((code == EQ || code == NE)
10855 && GET_CODE (rs6000_compare_op0) == SUBREG
10856 && GET_CODE (rs6000_compare_op1) == SUBREG
10857 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10858 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10859 /* These are unsigned values, perhaps there will be a later
10860 ordering compare that can be shared with this one.
10861 Unfortunately we cannot detect the signedness of the operands
10862 for non-subregs. */
10863 comp_mode = CCUNSmode;
10865 comp_mode = CCmode;
10867 /* First, the compare. */
10868 compare_result = gen_reg_rtx (comp_mode);
10870 /* SPE FP compare instructions on the GPRs. Yuck! */
10871 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10872 && rs6000_compare_fp_p)
10874 rtx cmp, or_result, compare_result2;
10875 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10877 if (op_mode == VOIDmode)
10878 op_mode = GET_MODE (rs6000_compare_op1);
10880 /* Note: The E500 comparison instructions set the GT bit (x +
10881 1), on success. This explains the mess. */
10885 case EQ: case UNEQ: case NE: case LTGT:
10889 cmp = flag_unsafe_math_optimizations
10890 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10891 rs6000_compare_op1)
10892 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10893 rs6000_compare_op1);
10897 cmp = flag_unsafe_math_optimizations
10898 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10899 rs6000_compare_op1)
10900 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10901 rs6000_compare_op1);
10905 gcc_unreachable ();
10909 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10913 cmp = flag_unsafe_math_optimizations
10914 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10915 rs6000_compare_op1)
10916 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10917 rs6000_compare_op1);
10921 cmp = flag_unsafe_math_optimizations
10922 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10923 rs6000_compare_op1)
10924 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10925 rs6000_compare_op1);
10929 gcc_unreachable ();
10933 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10937 cmp = flag_unsafe_math_optimizations
10938 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10939 rs6000_compare_op1)
10940 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10941 rs6000_compare_op1);
10945 cmp = flag_unsafe_math_optimizations
10946 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10947 rs6000_compare_op1)
10948 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10949 rs6000_compare_op1);
10953 gcc_unreachable ();
10957 gcc_unreachable ();
10960 /* Synthesize LE and GE from LT/GT || EQ. */
10961 if (code == LE || code == GE || code == LEU || code == GEU)
10967 case LE: code = LT; break;
10968 case GE: code = GT; break;
10969 case LEU: code = LT; break;
10970 case GEU: code = GT; break;
10971 default: gcc_unreachable ();
10974 compare_result2 = gen_reg_rtx (CCFPmode);
10980 cmp = flag_unsafe_math_optimizations
10981 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10982 rs6000_compare_op1)
10983 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10984 rs6000_compare_op1);
10988 cmp = flag_unsafe_math_optimizations
10989 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10990 rs6000_compare_op1)
10991 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10992 rs6000_compare_op1);
10996 gcc_unreachable ();
11000 /* OR them together. */
11001 or_result = gen_reg_rtx (CCFPmode);
11002 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11004 compare_result = or_result;
11009 if (code == NE || code == LTGT)
11019 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11020 CLOBBERs to match cmptf_internal2 pattern. */
11021 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11022 && GET_MODE (rs6000_compare_op0) == TFmode
11023 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11024 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11025 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11027 gen_rtx_SET (VOIDmode,
11029 gen_rtx_COMPARE (comp_mode,
11030 rs6000_compare_op0,
11031 rs6000_compare_op1)),
11032 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11033 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11034 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11035 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11036 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11037 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11038 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11039 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11040 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11041 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11043 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11044 comp_mode = CCEQmode;
11045 compare_result = gen_reg_rtx (CCEQmode);
11047 emit_insn (gen_stack_protect_testdi (compare_result,
11048 rs6000_compare_op0, op1));
11050 emit_insn (gen_stack_protect_testsi (compare_result,
11051 rs6000_compare_op0, op1));
11054 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11055 gen_rtx_COMPARE (comp_mode,
11056 rs6000_compare_op0,
11057 rs6000_compare_op1)));
11060 /* Some kinds of FP comparisons need an OR operation;
11061 under flag_finite_math_only we don't bother. */
11062 if (rs6000_compare_fp_p
11063 && !flag_finite_math_only
11064 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11065 && (code == LE || code == GE
11066 || code == UNEQ || code == LTGT
11067 || code == UNGT || code == UNLT))
11069 enum rtx_code or1, or2;
11070 rtx or1_rtx, or2_rtx, compare2_rtx;
11071 rtx or_result = gen_reg_rtx (CCEQmode);
11075 case LE: or1 = LT; or2 = EQ; break;
11076 case GE: or1 = GT; or2 = EQ; break;
11077 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11078 case LTGT: or1 = LT; or2 = GT; break;
11079 case UNGT: or1 = UNORDERED; or2 = GT; break;
11080 case UNLT: or1 = UNORDERED; or2 = LT; break;
11081 default: gcc_unreachable ();
11083 validate_condition_mode (or1, comp_mode);
11084 validate_condition_mode (or2, comp_mode);
11085 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11086 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11087 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11088 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11090 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11092 compare_result = or_result;
11096 validate_condition_mode (code, GET_MODE (compare_result));
11098 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11102 /* Emit the RTL for an sCOND pattern. */
11105 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11108 enum machine_mode op_mode;
11109 enum rtx_code cond_code;
11111 condition_rtx = rs6000_generate_compare (code);
11112 cond_code = GET_CODE (condition_rtx);
11114 if (TARGET_E500 && rs6000_compare_fp_p
11115 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11119 PUT_MODE (condition_rtx, SImode);
11120 t = XEXP (condition_rtx, 0);
11122 gcc_assert (cond_code == NE || cond_code == EQ);
11124 if (cond_code == NE)
11125 emit_insn (gen_e500_flip_gt_bit (t, t));
11127 emit_insn (gen_move_from_CR_gt_bit (result, t));
11131 if (cond_code == NE
11132 || cond_code == GE || cond_code == LE
11133 || cond_code == GEU || cond_code == LEU
11134 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11136 rtx not_result = gen_reg_rtx (CCEQmode);
11137 rtx not_op, rev_cond_rtx;
11138 enum machine_mode cc_mode;
11140 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11142 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11143 SImode, XEXP (condition_rtx, 0), const0_rtx);
11144 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11145 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11146 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11149 op_mode = GET_MODE (rs6000_compare_op0);
11150 if (op_mode == VOIDmode)
11151 op_mode = GET_MODE (rs6000_compare_op1);
11153 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11155 PUT_MODE (condition_rtx, DImode);
11156 convert_move (result, condition_rtx, 0);
11160 PUT_MODE (condition_rtx, SImode);
11161 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11165 /* Emit a branch of kind CODE to location LOC. */
11168 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11170 rtx condition_rtx, loc_ref;
11172 condition_rtx = rs6000_generate_compare (code);
11173 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11174 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11175 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11176 loc_ref, pc_rtx)));
11179 /* Return the string to output a conditional branch to LABEL, which is
11180 the operand number of the label, or -1 if the branch is really a
11181 conditional return.
11183 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11184 condition code register and its mode specifies what kind of
11185 comparison we made.
11187 REVERSED is nonzero if we should reverse the sense of the comparison.
11189 INSN is the insn. */
11192 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11194 static char string[64];
11195 enum rtx_code code = GET_CODE (op);
11196 rtx cc_reg = XEXP (op, 0);
11197 enum machine_mode mode = GET_MODE (cc_reg);
11198 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11199 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11200 int really_reversed = reversed ^ need_longbranch;
11206 validate_condition_mode (code, mode);
11208 /* Work out which way this really branches. We could use
11209 reverse_condition_maybe_unordered here always but this
11210 makes the resulting assembler clearer. */
11211 if (really_reversed)
11213 /* Reversal of FP compares takes care -- an ordered compare
11214 becomes an unordered compare and vice versa. */
11215 if (mode == CCFPmode)
11216 code = reverse_condition_maybe_unordered (code);
11218 code = reverse_condition (code);
11221 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11223 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11228 /* Opposite of GT. */
11237 gcc_unreachable ();
11243 /* Not all of these are actually distinct opcodes, but
11244 we distinguish them for clarity of the resulting assembler. */
11245 case NE: case LTGT:
11246 ccode = "ne"; break;
11247 case EQ: case UNEQ:
11248 ccode = "eq"; break;
11250 ccode = "ge"; break;
11251 case GT: case GTU: case UNGT:
11252 ccode = "gt"; break;
11254 ccode = "le"; break;
11255 case LT: case LTU: case UNLT:
11256 ccode = "lt"; break;
11257 case UNORDERED: ccode = "un"; break;
11258 case ORDERED: ccode = "nu"; break;
11259 case UNGE: ccode = "nl"; break;
11260 case UNLE: ccode = "ng"; break;
11262 gcc_unreachable ();
11265 /* Maybe we have a guess as to how likely the branch is.
11266 The old mnemonics don't have a way to specify this information. */
11268 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11269 if (note != NULL_RTX)
11271 /* PROB is the difference from 50%. */
11272 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11274 /* Only hint for highly probable/improbable branches on newer
11275 cpus as static prediction overrides processor dynamic
11276 prediction. For older cpus we may as well always hint, but
11277 assume not taken for branches that are very close to 50% as a
11278 mispredicted taken branch is more expensive than a
11279 mispredicted not-taken branch. */
11280 if (rs6000_always_hint
11281 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11283 if (abs (prob) > REG_BR_PROB_BASE / 20
11284 && ((prob > 0) ^ need_longbranch))
11292 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11294 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11296 /* We need to escape any '%' characters in the reg_names string.
11297 Assume they'd only be the first character.... */
11298 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11300 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11304 /* If the branch distance was too far, we may have to use an
11305 unconditional branch to go the distance. */
11306 if (need_longbranch)
11307 s += sprintf (s, ",$+8\n\tb %s", label);
11309 s += sprintf (s, ",%s", label);
11315 /* Return the string to flip the GT bit on a CR. */
11317 output_e500_flip_gt_bit (rtx dst, rtx src)
11319 static char string[64];
11322 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11323 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11326 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11327 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11329 sprintf (string, "crnot %d,%d", a, b);
11333 /* Return insn index for the vector compare instruction for given CODE,
11334 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11338 get_vec_cmp_insn (enum rtx_code code,
11339 enum machine_mode dest_mode,
11340 enum machine_mode op_mode)
11342 if (!TARGET_ALTIVEC)
11343 return INSN_NOT_AVAILABLE;
11348 if (dest_mode == V16QImode && op_mode == V16QImode)
11349 return UNSPEC_VCMPEQUB;
11350 if (dest_mode == V8HImode && op_mode == V8HImode)
11351 return UNSPEC_VCMPEQUH;
11352 if (dest_mode == V4SImode && op_mode == V4SImode)
11353 return UNSPEC_VCMPEQUW;
11354 if (dest_mode == V4SImode && op_mode == V4SFmode)
11355 return UNSPEC_VCMPEQFP;
11358 if (dest_mode == V4SImode && op_mode == V4SFmode)
11359 return UNSPEC_VCMPGEFP;
11361 if (dest_mode == V16QImode && op_mode == V16QImode)
11362 return UNSPEC_VCMPGTSB;
11363 if (dest_mode == V8HImode && op_mode == V8HImode)
11364 return UNSPEC_VCMPGTSH;
11365 if (dest_mode == V4SImode && op_mode == V4SImode)
11366 return UNSPEC_VCMPGTSW;
11367 if (dest_mode == V4SImode && op_mode == V4SFmode)
11368 return UNSPEC_VCMPGTFP;
11371 if (dest_mode == V16QImode && op_mode == V16QImode)
11372 return UNSPEC_VCMPGTUB;
11373 if (dest_mode == V8HImode && op_mode == V8HImode)
11374 return UNSPEC_VCMPGTUH;
11375 if (dest_mode == V4SImode && op_mode == V4SImode)
11376 return UNSPEC_VCMPGTUW;
11381 return INSN_NOT_AVAILABLE;
11384 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11385 DMODE is expected destination mode. This is a recursive function. */
11388 rs6000_emit_vector_compare (enum rtx_code rcode,
11390 enum machine_mode dmode)
11394 enum machine_mode dest_mode;
11395 enum machine_mode op_mode = GET_MODE (op1);
11397 gcc_assert (TARGET_ALTIVEC);
11398 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11400 /* Floating point vector compare instructions uses destination V4SImode.
11401 Move destination to appropriate mode later. */
11402 if (dmode == V4SFmode)
11403 dest_mode = V4SImode;
11407 mask = gen_reg_rtx (dest_mode);
11408 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11410 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11412 bool swap_operands = false;
11413 bool try_again = false;
11418 swap_operands = true;
11423 swap_operands = true;
11427 /* Treat A != B as ~(A==B). */
11429 enum insn_code nor_code;
11430 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11433 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11434 gcc_assert (nor_code != CODE_FOR_nothing);
11435 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11437 if (dmode != dest_mode)
11439 rtx temp = gen_reg_rtx (dest_mode);
11440 convert_move (temp, mask, 0);
11450 /* Try GT/GTU/LT/LTU OR EQ */
11453 enum insn_code ior_code;
11454 enum rtx_code new_code;
11475 gcc_unreachable ();
11478 c_rtx = rs6000_emit_vector_compare (new_code,
11479 op0, op1, dest_mode);
11480 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11483 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11484 gcc_assert (ior_code != CODE_FOR_nothing);
11485 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11486 if (dmode != dest_mode)
11488 rtx temp = gen_reg_rtx (dest_mode);
11489 convert_move (temp, mask, 0);
11496 gcc_unreachable ();
11501 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11502 /* You only get two chances. */
11503 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11515 emit_insn (gen_rtx_SET (VOIDmode, mask,
11516 gen_rtx_UNSPEC (dest_mode,
11517 gen_rtvec (2, op0, op1),
11519 if (dmode != dest_mode)
11521 rtx temp = gen_reg_rtx (dest_mode);
11522 convert_move (temp, mask, 0);
11528 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11529 valid insn doesn exist for given mode. */
11532 get_vsel_insn (enum machine_mode mode)
11537 return UNSPEC_VSEL4SI;
11540 return UNSPEC_VSEL4SF;
11543 return UNSPEC_VSEL8HI;
11546 return UNSPEC_VSEL16QI;
11549 return INSN_NOT_AVAILABLE;
11552 return INSN_NOT_AVAILABLE;
11555 /* Emit vector select insn where DEST is destination using
11556 operands OP1, OP2 and MASK. */
11559 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11562 enum machine_mode dest_mode = GET_MODE (dest);
11563 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11565 temp = gen_reg_rtx (dest_mode);
11567 /* For each vector element, select op1 when mask is 1 otherwise
11569 t = gen_rtx_SET (VOIDmode, temp,
11570 gen_rtx_UNSPEC (dest_mode,
11571 gen_rtvec (3, op2, op1, mask),
11574 emit_move_insn (dest, temp);
11578 /* Emit vector conditional expression.
11579 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11580 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11583 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11584 rtx cond, rtx cc_op0, rtx cc_op1)
11586 enum machine_mode dest_mode = GET_MODE (dest);
11587 enum rtx_code rcode = GET_CODE (cond);
11590 if (!TARGET_ALTIVEC)
11593 /* Get the vector mask for the given relational operations. */
11594 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11596 rs6000_emit_vector_select (dest, op1, op2, mask);
11601 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11602 operands of the last comparison is nonzero/true, FALSE_COND if it
11603 is zero/false. Return 0 if the hardware has no such operation. */
11606 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11608 enum rtx_code code = GET_CODE (op);
11609 rtx op0 = rs6000_compare_op0;
11610 rtx op1 = rs6000_compare_op1;
11611 REAL_VALUE_TYPE c1;
11612 enum machine_mode compare_mode = GET_MODE (op0);
11613 enum machine_mode result_mode = GET_MODE (dest);
11615 bool is_against_zero;
11617 /* These modes should always match. */
11618 if (GET_MODE (op1) != compare_mode
11619 /* In the isel case however, we can use a compare immediate, so
11620 op1 may be a small constant. */
11621 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11623 if (GET_MODE (true_cond) != result_mode)
11625 if (GET_MODE (false_cond) != result_mode)
11628 /* First, work out if the hardware can do this at all, or
11629 if it's too slow.... */
11630 if (! rs6000_compare_fp_p)
11633 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11636 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11637 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11640 is_against_zero = op1 == CONST0_RTX (compare_mode);
11642 /* A floating-point subtract might overflow, underflow, or produce
11643 an inexact result, thus changing the floating-point flags, so it
11644 can't be generated if we care about that. It's safe if one side
11645 of the construct is zero, since then no subtract will be
11647 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11648 && flag_trapping_math && ! is_against_zero)
11651 /* Eliminate half of the comparisons by switching operands, this
11652 makes the remaining code simpler. */
11653 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11654 || code == LTGT || code == LT || code == UNLE)
11656 code = reverse_condition_maybe_unordered (code);
11658 true_cond = false_cond;
11662 /* UNEQ and LTGT take four instructions for a comparison with zero,
11663 it'll probably be faster to use a branch here too. */
11664 if (code == UNEQ && HONOR_NANS (compare_mode))
11667 if (GET_CODE (op1) == CONST_DOUBLE)
11668 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11670 /* We're going to try to implement comparisons by performing
11671 a subtract, then comparing against zero. Unfortunately,
11672 Inf - Inf is NaN which is not zero, and so if we don't
11673 know that the operand is finite and the comparison
11674 would treat EQ different to UNORDERED, we can't do it. */
11675 if (HONOR_INFINITIES (compare_mode)
11676 && code != GT && code != UNGE
11677 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11678 /* Constructs of the form (a OP b ? a : b) are safe. */
11679 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11680 || (! rtx_equal_p (op0, true_cond)
11681 && ! rtx_equal_p (op1, true_cond))))
11684 /* At this point we know we can use fsel. */
11686 /* Reduce the comparison to a comparison against zero. */
11687 if (! is_against_zero)
11689 temp = gen_reg_rtx (compare_mode);
11690 emit_insn (gen_rtx_SET (VOIDmode, temp,
11691 gen_rtx_MINUS (compare_mode, op0, op1)));
11693 op1 = CONST0_RTX (compare_mode);
11696 /* If we don't care about NaNs we can reduce some of the comparisons
11697 down to faster ones. */
11698 if (! HONOR_NANS (compare_mode))
11704 true_cond = false_cond;
11717 /* Now, reduce everything down to a GE. */
11724 temp = gen_reg_rtx (compare_mode);
11725 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11730 temp = gen_reg_rtx (compare_mode);
11731 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11736 temp = gen_reg_rtx (compare_mode);
11737 emit_insn (gen_rtx_SET (VOIDmode, temp,
11738 gen_rtx_NEG (compare_mode,
11739 gen_rtx_ABS (compare_mode, op0))));
11744 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11745 temp = gen_reg_rtx (result_mode);
11746 emit_insn (gen_rtx_SET (VOIDmode, temp,
11747 gen_rtx_IF_THEN_ELSE (result_mode,
11748 gen_rtx_GE (VOIDmode,
11750 true_cond, false_cond)));
11751 false_cond = true_cond;
11754 temp = gen_reg_rtx (compare_mode);
11755 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11760 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11761 temp = gen_reg_rtx (result_mode);
11762 emit_insn (gen_rtx_SET (VOIDmode, temp,
11763 gen_rtx_IF_THEN_ELSE (result_mode,
11764 gen_rtx_GE (VOIDmode,
11766 true_cond, false_cond)));
11767 true_cond = false_cond;
11770 temp = gen_reg_rtx (compare_mode);
11771 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11776 gcc_unreachable ();
11779 emit_insn (gen_rtx_SET (VOIDmode, dest,
11780 gen_rtx_IF_THEN_ELSE (result_mode,
11781 gen_rtx_GE (VOIDmode,
11783 true_cond, false_cond)));
11787 /* Same as above, but for ints (isel). */
11790 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11792 rtx condition_rtx, cr;
11794 /* All isel implementations thus far are 32-bits. */
11795 if (GET_MODE (rs6000_compare_op0) != SImode)
11798 /* We still have to do the compare, because isel doesn't do a
11799 compare, it just looks at the CRx bits set by a previous compare
11801 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11802 cr = XEXP (condition_rtx, 0);
11804 if (GET_MODE (cr) == CCmode)
11805 emit_insn (gen_isel_signed (dest, condition_rtx,
11806 true_cond, false_cond, cr));
11808 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11809 true_cond, false_cond, cr));
11815 output_isel (rtx *operands)
11817 enum rtx_code code;
11819 code = GET_CODE (operands[1]);
11820 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11822 PUT_CODE (operands[1], reverse_condition (code));
11823 return "isel %0,%3,%2,%j1";
11826 return "isel %0,%2,%3,%j1";
11830 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11832 enum machine_mode mode = GET_MODE (op0);
11836 if (code == SMAX || code == SMIN)
11841 if (code == SMAX || code == UMAX)
11842 target = emit_conditional_move (dest, c, op0, op1, mode,
11843 op0, op1, mode, 0);
11845 target = emit_conditional_move (dest, c, op0, op1, mode,
11846 op1, op0, mode, 0);
11847 gcc_assert (target);
11848 if (target != dest)
11849 emit_move_insn (dest, target);
11852 /* Emit instructions to perform a load-reserved/store-conditional operation.
11853 The operation performed is an atomic
11854 (set M (CODE:MODE M OP))
11855 If not NULL, BEFORE is atomically set to M before the operation, and
11856 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11857 If SYNC_P then a memory barrier is emitted before the operation.
11858 Either OP or M may be wrapped in a NOT operation. */
11861 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11862 rtx m, rtx op, rtx before_param, rtx after_param,
11865 enum machine_mode used_mode;
11866 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11869 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11870 rtx shift = NULL_RTX;
11873 emit_insn (gen_memory_barrier ());
11875 if (GET_CODE (m) == NOT)
11876 used_m = XEXP (m, 0);
11880 /* If this is smaller than SImode, we'll have to use SImode with
11882 if (mode == QImode || mode == HImode)
11886 if (MEM_ALIGN (used_m) >= 32)
11889 if (BYTES_BIG_ENDIAN)
11890 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11892 shift = GEN_INT (ishift);
11896 rtx addrSI, aligned_addr;
11897 int shift_mask = mode == QImode ? 0x18 : 0x10;
11899 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11900 XEXP (used_m, 0)));
11901 shift = gen_reg_rtx (SImode);
11903 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11904 GEN_INT (shift_mask)));
11905 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11907 aligned_addr = expand_binop (Pmode, and_optab,
11909 GEN_INT (-4), NULL_RTX,
11910 1, OPTAB_LIB_WIDEN);
11911 used_m = change_address (used_m, SImode, aligned_addr);
11912 set_mem_align (used_m, 32);
11913 /* It's safe to keep the old alias set of USED_M, because
11914 the operation is atomic and only affects the original
11916 if (GET_CODE (m) == NOT)
11917 m = gen_rtx_NOT (SImode, used_m);
11922 if (GET_CODE (op) == NOT)
11924 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11925 oldop = gen_rtx_NOT (SImode, oldop);
11928 oldop = lowpart_subreg (SImode, op, mode);
11934 newop = expand_binop (SImode, and_optab,
11935 oldop, GEN_INT (imask), NULL_RTX,
11936 1, OPTAB_LIB_WIDEN);
11937 emit_insn (gen_ashlsi3 (newop, newop, shift));
11941 newop = expand_binop (SImode, ior_optab,
11942 oldop, GEN_INT (~imask), NULL_RTX,
11943 1, OPTAB_LIB_WIDEN);
11944 emit_insn (gen_rotlsi3 (newop, newop, shift));
11952 newop = expand_binop (SImode, and_optab,
11953 oldop, GEN_INT (imask), NULL_RTX,
11954 1, OPTAB_LIB_WIDEN);
11955 emit_insn (gen_ashlsi3 (newop, newop, shift));
11957 mask = gen_reg_rtx (SImode);
11958 emit_move_insn (mask, GEN_INT (imask));
11959 emit_insn (gen_ashlsi3 (mask, mask, shift));
11962 newop = gen_rtx_PLUS (SImode, m, newop);
11964 newop = gen_rtx_MINUS (SImode, m, newop);
11965 newop = gen_rtx_AND (SImode, newop, mask);
11966 newop = gen_rtx_IOR (SImode, newop,
11967 gen_rtx_AND (SImode,
11968 gen_rtx_NOT (SImode, mask),
11974 gcc_unreachable ();
11977 if (GET_CODE (m) == NOT)
11981 mask = gen_reg_rtx (SImode);
11982 emit_move_insn (mask, GEN_INT (imask));
11983 emit_insn (gen_ashlsi3 (mask, mask, shift));
11985 xorm = gen_rtx_XOR (SImode, used_m, mask);
11986 /* Depending on the value of 'op', the XOR or the operation might
11987 be able to be simplified away. */
11988 newop = simplify_gen_binary (code, SImode, xorm, newop);
11991 used_mode = SImode;
11992 before = gen_reg_rtx (used_mode);
11993 after = gen_reg_rtx (used_mode);
11998 before = before_param;
11999 after = after_param;
12001 if (before == NULL_RTX)
12002 before = gen_reg_rtx (used_mode);
12003 if (after == NULL_RTX)
12004 after = gen_reg_rtx (used_mode);
12007 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12008 && used_mode != mode)
12009 the_op = op; /* Computed above. */
12010 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12011 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12013 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12015 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12016 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12017 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12018 gen_rtx_UNSPEC (used_mode,
12019 gen_rtvec (1, the_op),
12021 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12023 if ((code == PLUS || code == MINUS) && used_mode != mode)
12024 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12025 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12027 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12028 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12030 /* Shift and mask the return values properly. */
12031 if (used_mode != mode && before_param)
12033 emit_insn (gen_lshrsi3 (before, before, shift));
12034 convert_move (before_param, before, 1);
12037 if (used_mode != mode && after_param)
12039 emit_insn (gen_lshrsi3 (after, after, shift));
12040 convert_move (after_param, after, 1);
12043 /* The previous sequence will end with a branch that's dependent on
12044 the conditional store, so placing an isync will ensure that no
12045 other instructions (especially, no load or store instructions)
12046 can start before the atomic operation completes. */
12048 emit_insn (gen_isync ());
12051 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12052 COND is true. Mark the jump as unlikely to be taken. */
12055 emit_unlikely_jump (rtx cond, rtx label)
12057 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12060 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12061 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12062 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12065 /* A subroutine of the atomic operation splitters. Emit a load-locked
12066 instruction in MODE. */
12069 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12071 rtx (*fn) (rtx, rtx) = NULL;
12072 if (mode == SImode)
12073 fn = gen_load_locked_si;
12074 else if (mode == DImode)
12075 fn = gen_load_locked_di;
12076 emit_insn (fn (reg, mem));
12079 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12080 instruction in MODE. */
12083 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12085 rtx (*fn) (rtx, rtx, rtx) = NULL;
12086 if (mode == SImode)
12087 fn = gen_store_conditional_si;
12088 else if (mode == DImode)
12089 fn = gen_store_conditional_di;
12091 /* Emit sync before stwcx. to address PPC405 Erratum. */
12092 if (PPC405_ERRATUM77)
12093 emit_insn (gen_memory_barrier ());
12095 emit_insn (fn (res, mem, val));
12098 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12099 to perform. MEM is the memory on which to operate. VAL is the second
12100 operand of the binary operator. BEFORE and AFTER are optional locations to
12101 return the value of MEM either before of after the operation. SCRATCH is
12102 a scratch register. */
12105 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12106 rtx before, rtx after, rtx scratch)
12108 enum machine_mode mode = GET_MODE (mem);
12109 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12111 emit_insn (gen_memory_barrier ());
12113 label = gen_label_rtx ();
12114 emit_label (label);
12115 label = gen_rtx_LABEL_REF (VOIDmode, label);
12117 if (before == NULL_RTX)
12119 emit_load_locked (mode, before, mem);
12122 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12123 else if (code == AND)
12124 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12126 x = gen_rtx_fmt_ee (code, mode, before, val);
12128 if (after != NULL_RTX)
12129 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12130 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12132 emit_store_conditional (mode, cond, mem, scratch);
12134 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12135 emit_unlikely_jump (x, label);
12137 emit_insn (gen_isync ());
12140 /* Expand an atomic compare and swap operation. MEM is the memory on which
12141 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12142 value to be stored. SCRATCH is a scratch GPR. */
12145 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12148 enum machine_mode mode = GET_MODE (mem);
12149 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12151 emit_insn (gen_memory_barrier ());
12153 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12154 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12155 emit_label (XEXP (label1, 0));
12157 emit_load_locked (mode, retval, mem);
12159 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12160 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12162 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12163 emit_unlikely_jump (x, label2);
12165 emit_move_insn (scratch, newval);
12166 emit_store_conditional (mode, cond, mem, scratch);
12168 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12169 emit_unlikely_jump (x, label1);
12171 emit_insn (gen_isync ());
12172 emit_label (XEXP (label2, 0));
12175 /* Expand an atomic test and set operation. MEM is the memory on which
12176 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12179 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12181 enum machine_mode mode = GET_MODE (mem);
12182 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12184 emit_insn (gen_memory_barrier ());
12186 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12187 emit_label (XEXP (label, 0));
12189 emit_load_locked (mode, retval, mem);
12190 emit_move_insn (scratch, val);
12191 emit_store_conditional (mode, cond, mem, scratch);
12193 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12194 emit_unlikely_jump (x, label);
12196 emit_insn (gen_isync ());
12199 /* Emit instructions to move SRC to DST. Called by splitters for
12200 multi-register moves. It will emit at most one instruction for
12201 each register that is accessed; that is, it won't emit li/lis pairs
12202 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12206 rs6000_split_multireg_move (rtx dst, rtx src)
12208 /* The register number of the first register being moved. */
12210 /* The mode that is to be moved. */
12211 enum machine_mode mode;
12212 /* The mode that the move is being done in, and its size. */
12213 enum machine_mode reg_mode;
12215 /* The number of registers that will be moved. */
12218 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12219 mode = GET_MODE (dst);
12220 nregs = hard_regno_nregs[reg][mode];
12221 if (FP_REGNO_P (reg))
12223 else if (ALTIVEC_REGNO_P (reg))
12224 reg_mode = V16QImode;
12226 reg_mode = word_mode;
12227 reg_mode_size = GET_MODE_SIZE (reg_mode);
12229 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12231 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12233 /* Move register range backwards, if we might have destructive
12236 for (i = nregs - 1; i >= 0; i--)
12237 emit_insn (gen_rtx_SET (VOIDmode,
12238 simplify_gen_subreg (reg_mode, dst, mode,
12239 i * reg_mode_size),
12240 simplify_gen_subreg (reg_mode, src, mode,
12241 i * reg_mode_size)));
12247 bool used_update = false;
12249 if (MEM_P (src) && INT_REGNO_P (reg))
12253 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12254 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12257 breg = XEXP (XEXP (src, 0), 0);
12258 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12259 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12260 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12261 emit_insn (TARGET_32BIT
12262 ? gen_addsi3 (breg, breg, delta_rtx)
12263 : gen_adddi3 (breg, breg, delta_rtx));
12264 src = replace_equiv_address (src, breg);
12266 else if (! offsettable_memref_p (src))
12269 basereg = gen_rtx_REG (Pmode, reg);
12270 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12271 src = replace_equiv_address (src, basereg);
12274 breg = XEXP (src, 0);
12275 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12276 breg = XEXP (breg, 0);
12278 /* If the base register we are using to address memory is
12279 also a destination reg, then change that register last. */
12281 && REGNO (breg) >= REGNO (dst)
12282 && REGNO (breg) < REGNO (dst) + nregs)
12283 j = REGNO (breg) - REGNO (dst);
12286 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12290 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12291 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12294 breg = XEXP (XEXP (dst, 0), 0);
12295 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12296 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12297 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12299 /* We have to update the breg before doing the store.
12300 Use store with update, if available. */
12304 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12305 emit_insn (TARGET_32BIT
12306 ? (TARGET_POWERPC64
12307 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12308 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12309 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12310 used_update = true;
12313 emit_insn (TARGET_32BIT
12314 ? gen_addsi3 (breg, breg, delta_rtx)
12315 : gen_adddi3 (breg, breg, delta_rtx));
12316 dst = replace_equiv_address (dst, breg);
12319 gcc_assert (offsettable_memref_p (dst));
12322 for (i = 0; i < nregs; i++)
12324 /* Calculate index to next subword. */
12329 /* If compiler already emitted move of first word by
12330 store with update, no need to do anything. */
12331 if (j == 0 && used_update)
12334 emit_insn (gen_rtx_SET (VOIDmode,
12335 simplify_gen_subreg (reg_mode, dst, mode,
12336 j * reg_mode_size),
12337 simplify_gen_subreg (reg_mode, src, mode,
12338 j * reg_mode_size)));
12344 /* This page contains routines that are used to determine what the
12345 function prologue and epilogue code will do and write them out. */
12347 /* Return the first fixed-point register that is required to be
12348 saved. 32 if none. */
12351 first_reg_to_save (void)
12355 /* Find lowest numbered live register. */
12356 for (first_reg = 13; first_reg <= 31; first_reg++)
12357 if (regs_ever_live[first_reg]
12358 && (! call_used_regs[first_reg]
12359 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12360 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12361 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12362 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12367 && current_function_uses_pic_offset_table
12368 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12369 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12375 /* Similar, for FP regs. */
12378 first_fp_reg_to_save (void)
12382 /* Find lowest numbered live register. */
12383 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12384 if (regs_ever_live[first_reg])
12390 /* Similar, for AltiVec regs. */
12393 first_altivec_reg_to_save (void)
12397 /* Stack frame remains as is unless we are in AltiVec ABI. */
12398 if (! TARGET_ALTIVEC_ABI)
12399 return LAST_ALTIVEC_REGNO + 1;
12401 /* Find lowest numbered live register. */
12402 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12403 if (regs_ever_live[i])
12409 /* Return a 32-bit mask of the AltiVec registers we need to set in
12410 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12411 the 32-bit word is 0. */
12413 static unsigned int
12414 compute_vrsave_mask (void)
12416 unsigned int i, mask = 0;
12418 /* First, find out if we use _any_ altivec registers. */
12419 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12420 if (regs_ever_live[i])
12421 mask |= ALTIVEC_REG_BIT (i);
12426 /* Next, remove the argument registers from the set. These must
12427 be in the VRSAVE mask set by the caller, so we don't need to add
12428 them in again. More importantly, the mask we compute here is
12429 used to generate CLOBBERs in the set_vrsave insn, and we do not
12430 wish the argument registers to die. */
12431 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12432 mask &= ~ALTIVEC_REG_BIT (i);
12434 /* Similarly, remove the return value from the set. */
12437 diddle_return_value (is_altivec_return_reg, &yes);
12439 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12445 /* For a very restricted set of circumstances, we can cut down the
12446 size of prologues/epilogues by calling our own save/restore-the-world
12450 compute_save_world_info (rs6000_stack_t *info_ptr)
12452 info_ptr->world_save_p = 1;
12453 info_ptr->world_save_p
12454 = (WORLD_SAVE_P (info_ptr)
12455 && DEFAULT_ABI == ABI_DARWIN
12456 && ! (current_function_calls_setjmp && flag_exceptions)
12457 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12458 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12459 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12460 && info_ptr->cr_save_p);
12462 /* This will not work in conjunction with sibcalls. Make sure there
12463 are none. (This check is expensive, but seldom executed.) */
12464 if (WORLD_SAVE_P (info_ptr))
12467 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12468 if ( GET_CODE (insn) == CALL_INSN
12469 && SIBLING_CALL_P (insn))
12471 info_ptr->world_save_p = 0;
12476 if (WORLD_SAVE_P (info_ptr))
12478 /* Even if we're not touching VRsave, make sure there's room on the
12479 stack for it, if it looks like we're calling SAVE_WORLD, which
12480 will attempt to save it. */
12481 info_ptr->vrsave_size = 4;
12483 /* "Save" the VRsave register too if we're saving the world. */
12484 if (info_ptr->vrsave_mask == 0)
12485 info_ptr->vrsave_mask = compute_vrsave_mask ();
12487 /* Because the Darwin register save/restore routines only handle
12488 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12490 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12491 && (info_ptr->first_altivec_reg_save
12492 >= FIRST_SAVED_ALTIVEC_REGNO));
12499 is_altivec_return_reg (rtx reg, void *xyes)
12501 bool *yes = (bool *) xyes;
12502 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12507 /* Calculate the stack information for the current function. This is
12508 complicated by having two separate calling sequences, the AIX calling
12509 sequence and the V.4 calling sequence.
12511 AIX (and Darwin/Mac OS X) stack frames look like:
12513 SP----> +---------------------------------------+
12514 | back chain to caller | 0 0
12515 +---------------------------------------+
12516 | saved CR | 4 8 (8-11)
12517 +---------------------------------------+
12519 +---------------------------------------+
12520 | reserved for compilers | 12 24
12521 +---------------------------------------+
12522 | reserved for binders | 16 32
12523 +---------------------------------------+
12524 | saved TOC pointer | 20 40
12525 +---------------------------------------+
12526 | Parameter save area (P) | 24 48
12527 +---------------------------------------+
12528 | Alloca space (A) | 24+P etc.
12529 +---------------------------------------+
12530 | Local variable space (L) | 24+P+A
12531 +---------------------------------------+
12532 | Float/int conversion temporary (X) | 24+P+A+L
12533 +---------------------------------------+
12534 | Save area for AltiVec registers (W) | 24+P+A+L+X
12535 +---------------------------------------+
12536 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12537 +---------------------------------------+
12538 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12539 +---------------------------------------+
12540 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12541 +---------------------------------------+
12542 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12543 +---------------------------------------+
12544 old SP->| back chain to caller's caller |
12545 +---------------------------------------+
12547 The required alignment for AIX configurations is two words (i.e., 8
12551 V.4 stack frames look like:
12553 SP----> +---------------------------------------+
12554 | back chain to caller | 0
12555 +---------------------------------------+
12556 | caller's saved LR | 4
12557 +---------------------------------------+
12558 | Parameter save area (P) | 8
12559 +---------------------------------------+
12560 | Alloca space (A) | 8+P
12561 +---------------------------------------+
12562 | Varargs save area (V) | 8+P+A
12563 +---------------------------------------+
12564 | Local variable space (L) | 8+P+A+V
12565 +---------------------------------------+
12566 | Float/int conversion temporary (X) | 8+P+A+V+L
12567 +---------------------------------------+
12568 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12569 +---------------------------------------+
12570 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12571 +---------------------------------------+
12572 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12573 +---------------------------------------+
12574 | SPE: area for 64-bit GP registers |
12575 +---------------------------------------+
12576 | SPE alignment padding |
12577 +---------------------------------------+
12578 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12579 +---------------------------------------+
12580 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12581 +---------------------------------------+
12582 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12583 +---------------------------------------+
12584 old SP->| back chain to caller's caller |
12585 +---------------------------------------+
12587 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12588 given. (But note below and in sysv4.h that we require only 8 and
12589 may round up the size of our stack frame anyways. The historical
12590 reason is early versions of powerpc-linux which didn't properly
12591 align the stack at program startup. A happy side-effect is that
12592 -mno-eabi libraries can be used with -meabi programs.)
12594 The EABI configuration defaults to the V.4 layout. However,
12595 the stack alignment requirements may differ. If -mno-eabi is not
12596 given, the required stack alignment is 8 bytes; if -mno-eabi is
12597 given, the required alignment is 16 bytes. (But see V.4 comment
12600 #ifndef ABI_STACK_BOUNDARY
12601 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12604 static rs6000_stack_t *
12605 rs6000_stack_info (void)
12607 static rs6000_stack_t info, zero_info;
12608 rs6000_stack_t *info_ptr = &info;
12609 int reg_size = TARGET_32BIT ? 4 : 8;
12612 HOST_WIDE_INT non_fixed_size;
12614 /* Zero all fields portably. */
12619 /* Cache value so we don't rescan instruction chain over and over. */
12620 if (cfun->machine->insn_chain_scanned_p == 0)
12621 cfun->machine->insn_chain_scanned_p
12622 = spe_func_has_64bit_regs_p () + 1;
12623 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12626 /* Select which calling sequence. */
12627 info_ptr->abi = DEFAULT_ABI;
12629 /* Calculate which registers need to be saved & save area size. */
12630 info_ptr->first_gp_reg_save = first_reg_to_save ();
12631 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12632 even if it currently looks like we won't. */
12633 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12634 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12635 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12636 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12637 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12639 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12641 /* For the SPE, we have an additional upper 32-bits on each GPR.
12642 Ideally we should save the entire 64-bits only when the upper
12643 half is used in SIMD instructions. Since we only record
12644 registers live (not the size they are used in), this proves
12645 difficult because we'd have to traverse the instruction chain at
12646 the right time, taking reload into account. This is a real pain,
12647 so we opt to save the GPRs in 64-bits always if but one register
12648 gets used in 64-bits. Otherwise, all the registers in the frame
12649 get saved in 32-bits.
12651 So... since when we save all GPRs (except the SP) in 64-bits, the
12652 traditional GP save area will be empty. */
12653 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12654 info_ptr->gp_size = 0;
12656 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12657 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12659 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12660 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12661 - info_ptr->first_altivec_reg_save);
12663 /* Does this function call anything? */
12664 info_ptr->calls_p = (! current_function_is_leaf
12665 || cfun->machine->ra_needs_full_frame);
12667 /* Determine if we need to save the link register. */
12668 if (rs6000_ra_ever_killed ()
12669 || (DEFAULT_ABI == ABI_AIX
12670 && current_function_profile
12671 && !TARGET_PROFILE_KERNEL)
12672 #ifdef TARGET_RELOCATABLE
12673 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12675 || (info_ptr->first_fp_reg_save != 64
12676 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12677 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12678 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12679 || info_ptr->calls_p)
12681 info_ptr->lr_save_p = 1;
12682 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12685 /* Determine if we need to save the condition code registers. */
12686 if (regs_ever_live[CR2_REGNO]
12687 || regs_ever_live[CR3_REGNO]
12688 || regs_ever_live[CR4_REGNO])
12690 info_ptr->cr_save_p = 1;
12691 if (DEFAULT_ABI == ABI_V4)
12692 info_ptr->cr_size = reg_size;
12695 /* If the current function calls __builtin_eh_return, then we need
12696 to allocate stack space for registers that will hold data for
12697 the exception handler. */
12698 if (current_function_calls_eh_return)
12701 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12704 /* SPE saves EH registers in 64-bits. */
12705 ehrd_size = i * (TARGET_SPE_ABI
12706 && info_ptr->spe_64bit_regs_used != 0
12707 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12712 /* Determine various sizes. */
12713 info_ptr->reg_size = reg_size;
12714 info_ptr->fixed_size = RS6000_SAVE_AREA;
12715 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12716 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12717 TARGET_ALTIVEC ? 16 : 8);
12718 if (FRAME_GROWS_DOWNWARD)
12719 info_ptr->vars_size
12720 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12721 + info_ptr->parm_size,
12722 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12723 - (info_ptr->fixed_size + info_ptr->vars_size
12724 + info_ptr->parm_size);
12726 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12727 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12729 info_ptr->spe_gp_size = 0;
12731 if (TARGET_ALTIVEC_ABI)
12732 info_ptr->vrsave_mask = compute_vrsave_mask ();
12734 info_ptr->vrsave_mask = 0;
12736 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12737 info_ptr->vrsave_size = 4;
12739 info_ptr->vrsave_size = 0;
12741 compute_save_world_info (info_ptr);
12743 /* Calculate the offsets. */
12744 switch (DEFAULT_ABI)
12748 gcc_unreachable ();
12752 info_ptr->fp_save_offset = - info_ptr->fp_size;
12753 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12755 if (TARGET_ALTIVEC_ABI)
12757 info_ptr->vrsave_save_offset
12758 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12760 /* Align stack so vector save area is on a quadword boundary. */
12761 if (info_ptr->altivec_size != 0)
12762 info_ptr->altivec_padding_size
12763 = 16 - (-info_ptr->vrsave_save_offset % 16);
12765 info_ptr->altivec_padding_size = 0;
12767 info_ptr->altivec_save_offset
12768 = info_ptr->vrsave_save_offset
12769 - info_ptr->altivec_padding_size
12770 - info_ptr->altivec_size;
12772 /* Adjust for AltiVec case. */
12773 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12776 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12777 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12778 info_ptr->lr_save_offset = 2*reg_size;
12782 info_ptr->fp_save_offset = - info_ptr->fp_size;
12783 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12784 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12786 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12788 /* Align stack so SPE GPR save area is aligned on a
12789 double-word boundary. */
12790 if (info_ptr->spe_gp_size != 0)
12791 info_ptr->spe_padding_size
12792 = 8 - (-info_ptr->cr_save_offset % 8);
12794 info_ptr->spe_padding_size = 0;
12796 info_ptr->spe_gp_save_offset
12797 = info_ptr->cr_save_offset
12798 - info_ptr->spe_padding_size
12799 - info_ptr->spe_gp_size;
12801 /* Adjust for SPE case. */
12802 info_ptr->toc_save_offset
12803 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12805 else if (TARGET_ALTIVEC_ABI)
12807 info_ptr->vrsave_save_offset
12808 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12810 /* Align stack so vector save area is on a quadword boundary. */
12811 if (info_ptr->altivec_size != 0)
12812 info_ptr->altivec_padding_size
12813 = 16 - (-info_ptr->vrsave_save_offset % 16);
12815 info_ptr->altivec_padding_size = 0;
12817 info_ptr->altivec_save_offset
12818 = info_ptr->vrsave_save_offset
12819 - info_ptr->altivec_padding_size
12820 - info_ptr->altivec_size;
12822 /* Adjust for AltiVec case. */
12823 info_ptr->toc_save_offset
12824 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12827 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12828 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12829 info_ptr->lr_save_offset = reg_size;
12833 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12834 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12835 + info_ptr->gp_size
12836 + info_ptr->altivec_size
12837 + info_ptr->altivec_padding_size
12838 + info_ptr->spe_gp_size
12839 + info_ptr->spe_padding_size
12841 + info_ptr->cr_size
12842 + info_ptr->lr_size
12843 + info_ptr->vrsave_size
12844 + info_ptr->toc_size,
12847 non_fixed_size = (info_ptr->vars_size
12848 + info_ptr->parm_size
12849 + info_ptr->save_size);
12851 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12852 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12854 /* Determine if we need to allocate any stack frame:
12856 For AIX we need to push the stack if a frame pointer is needed
12857 (because the stack might be dynamically adjusted), if we are
12858 debugging, if we make calls, or if the sum of fp_save, gp_save,
12859 and local variables are more than the space needed to save all
12860 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12861 + 18*8 = 288 (GPR13 reserved).
12863 For V.4 we don't have the stack cushion that AIX uses, but assume
12864 that the debugger can handle stackless frames. */
12866 if (info_ptr->calls_p)
12867 info_ptr->push_p = 1;
12869 else if (DEFAULT_ABI == ABI_V4)
12870 info_ptr->push_p = non_fixed_size != 0;
12872 else if (frame_pointer_needed)
12873 info_ptr->push_p = 1;
12875 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12876 info_ptr->push_p = 1;
12879 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12881 /* Zero offsets if we're not saving those registers. */
12882 if (info_ptr->fp_size == 0)
12883 info_ptr->fp_save_offset = 0;
12885 if (info_ptr->gp_size == 0)
12886 info_ptr->gp_save_offset = 0;
12888 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12889 info_ptr->altivec_save_offset = 0;
12891 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12892 info_ptr->vrsave_save_offset = 0;
12894 if (! TARGET_SPE_ABI
12895 || info_ptr->spe_64bit_regs_used == 0
12896 || info_ptr->spe_gp_size == 0)
12897 info_ptr->spe_gp_save_offset = 0;
12899 if (! info_ptr->lr_save_p)
12900 info_ptr->lr_save_offset = 0;
12902 if (! info_ptr->cr_save_p)
12903 info_ptr->cr_save_offset = 0;
12905 if (! info_ptr->toc_save_p)
12906 info_ptr->toc_save_offset = 0;
12911 /* Return true if the current function uses any GPRs in 64-bit SIMD
12915 spe_func_has_64bit_regs_p (void)
12919 /* Functions that save and restore all the call-saved registers will
12920 need to save/restore the registers in 64-bits. */
12921 if (current_function_calls_eh_return
12922 || current_function_calls_setjmp
12923 || current_function_has_nonlocal_goto)
12926 insns = get_insns ();
12928 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12934 /* FIXME: This should be implemented with attributes...
12936 (set_attr "spe64" "true")....then,
12937 if (get_spe64(insn)) return true;
12939 It's the only reliable way to do the stuff below. */
12941 i = PATTERN (insn);
12942 if (GET_CODE (i) == SET)
12944 enum machine_mode mode = GET_MODE (SET_SRC (i));
12946 if (SPE_VECTOR_MODE (mode))
12948 if (TARGET_E500_DOUBLE && mode == DFmode)
12958 debug_stack_info (rs6000_stack_t *info)
12960 const char *abi_string;
12963 info = rs6000_stack_info ();
12965 fprintf (stderr, "\nStack information for function %s:\n",
12966 ((current_function_decl && DECL_NAME (current_function_decl))
12967 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12972 default: abi_string = "Unknown"; break;
12973 case ABI_NONE: abi_string = "NONE"; break;
12974 case ABI_AIX: abi_string = "AIX"; break;
12975 case ABI_DARWIN: abi_string = "Darwin"; break;
12976 case ABI_V4: abi_string = "V.4"; break;
12979 fprintf (stderr, "\tABI = %5s\n", abi_string);
12981 if (TARGET_ALTIVEC_ABI)
12982 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12984 if (TARGET_SPE_ABI)
12985 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12987 if (info->first_gp_reg_save != 32)
12988 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12990 if (info->first_fp_reg_save != 64)
12991 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12993 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12994 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12995 info->first_altivec_reg_save);
12997 if (info->lr_save_p)
12998 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13000 if (info->cr_save_p)
13001 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13003 if (info->toc_save_p)
13004 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
13006 if (info->vrsave_mask)
13007 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13010 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13013 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13015 if (info->gp_save_offset)
13016 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13018 if (info->fp_save_offset)
13019 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13021 if (info->altivec_save_offset)
13022 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13023 info->altivec_save_offset);
13025 if (info->spe_gp_save_offset)
13026 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13027 info->spe_gp_save_offset);
13029 if (info->vrsave_save_offset)
13030 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13031 info->vrsave_save_offset);
13033 if (info->lr_save_offset)
13034 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13036 if (info->cr_save_offset)
13037 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13039 if (info->toc_save_offset)
13040 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
13042 if (info->varargs_save_offset)
13043 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13045 if (info->total_size)
13046 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13049 if (info->vars_size)
13050 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13053 if (info->parm_size)
13054 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13056 if (info->fixed_size)
13057 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13060 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13062 if (info->spe_gp_size)
13063 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13066 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13068 if (info->altivec_size)
13069 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13071 if (info->vrsave_size)
13072 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13074 if (info->altivec_padding_size)
13075 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13076 info->altivec_padding_size);
13078 if (info->spe_padding_size)
13079 fprintf (stderr, "\tspe_padding_size = %5d\n",
13080 info->spe_padding_size);
13083 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13086 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13088 if (info->toc_size)
13089 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13091 if (info->save_size)
13092 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13094 if (info->reg_size != 4)
13095 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13097 fprintf (stderr, "\n");
13101 rs6000_return_addr (int count, rtx frame)
13103 /* Currently we don't optimize very well between prolog and body
13104 code and for PIC code the code can be actually quite bad, so
13105 don't try to be too clever here. */
13106 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13108 cfun->machine->ra_needs_full_frame = 1;
13115 plus_constant (copy_to_reg
13116 (gen_rtx_MEM (Pmode,
13117 memory_address (Pmode, frame))),
13118 RETURN_ADDRESS_OFFSET)));
13121 cfun->machine->ra_need_lr = 1;
13122 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13125 /* Say whether a function is a candidate for sibcall handling or not.
13126 We do not allow indirect calls to be optimized into sibling calls.
13127 Also, we can't do it if there are any vector parameters; there's
13128 nowhere to put the VRsave code so it works; note that functions with
13129 vector parameters are required to have a prototype, so the argument
13130 type info must be available here. (The tail recursion case can work
13131 with vector parameters, but there's no way to distinguish here.) */
13133 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13138 if (TARGET_ALTIVEC_VRSAVE)
13140 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13141 type; type = TREE_CHAIN (type))
13143 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13147 if (DEFAULT_ABI == ABI_DARWIN
13148 || (*targetm.binds_local_p) (decl))
13150 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13152 if (!lookup_attribute ("longcall", attr_list)
13153 || lookup_attribute ("shortcall", attr_list))
13160 /* NULL if INSN insn is valid within a low-overhead loop.
13161 Otherwise return why doloop cannot be applied.
13162 PowerPC uses the COUNT register for branch on table instructions. */
13164 static const char *
13165 rs6000_invalid_within_doloop (rtx insn)
13168 return "Function call in the loop.";
13171 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13172 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13173 return "Computed branch in the loop.";
13179 rs6000_ra_ever_killed (void)
13185 if (current_function_is_thunk)
13188 /* regs_ever_live has LR marked as used if any sibcalls are present,
13189 but this should not force saving and restoring in the
13190 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13191 clobbers LR, so that is inappropriate. */
13193 /* Also, the prologue can generate a store into LR that
13194 doesn't really count, like this:
13197 bcl to set PIC register
13201 When we're called from the epilogue, we need to avoid counting
13202 this as a store. */
13204 push_topmost_sequence ();
13205 top = get_insns ();
13206 pop_topmost_sequence ();
13207 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13209 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13213 if (FIND_REG_INC_NOTE (insn, reg))
13215 else if (GET_CODE (insn) == CALL_INSN
13216 && !SIBLING_CALL_P (insn))
13218 else if (set_of (reg, insn) != NULL_RTX
13219 && !prologue_epilogue_contains (insn))
13226 /* Add a REG_MAYBE_DEAD note to the insn. */
13228 rs6000_maybe_dead (rtx insn)
13230 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13235 /* Emit instructions needed to load the TOC register.
13236 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13237 a constant pool; or for SVR4 -fpic. */
13240 rs6000_emit_load_toc_table (int fromprolog)
13243 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13245 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13248 rtx lab, tmp1, tmp2, got, tempLR;
13250 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13251 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13253 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13255 got = rs6000_got_sym ();
13256 tmp1 = tmp2 = dest;
13259 tmp1 = gen_reg_rtx (Pmode);
13260 tmp2 = gen_reg_rtx (Pmode);
13262 tempLR = (fromprolog
13263 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13264 : gen_reg_rtx (Pmode));
13265 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13267 rs6000_maybe_dead (insn);
13268 insn = emit_move_insn (tmp1, tempLR);
13270 rs6000_maybe_dead (insn);
13271 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13273 rs6000_maybe_dead (insn);
13274 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13276 rs6000_maybe_dead (insn);
13278 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13280 rtx tempLR = (fromprolog
13281 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13282 : gen_reg_rtx (Pmode));
13284 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13286 rs6000_maybe_dead (insn);
13287 insn = emit_move_insn (dest, tempLR);
13289 rs6000_maybe_dead (insn);
13291 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13294 rtx tempLR = (fromprolog
13295 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13296 : gen_reg_rtx (Pmode));
13297 rtx temp0 = (fromprolog
13298 ? gen_rtx_REG (Pmode, 0)
13299 : gen_reg_rtx (Pmode));
13305 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13306 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13308 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13309 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13311 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13313 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13314 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13322 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13323 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13324 emit_move_insn (dest, tempLR);
13325 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13327 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13329 rs6000_maybe_dead (insn);
13331 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13333 /* This is for AIX code running in non-PIC ELF32. */
13336 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13337 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13339 insn = emit_insn (gen_elf_high (dest, realsym));
13341 rs6000_maybe_dead (insn);
13342 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13344 rs6000_maybe_dead (insn);
13348 gcc_assert (DEFAULT_ABI == ABI_AIX);
13351 insn = emit_insn (gen_load_toc_aix_si (dest));
13353 insn = emit_insn (gen_load_toc_aix_di (dest));
13355 rs6000_maybe_dead (insn);
13359 /* Emit instructions to restore the link register after determining where
13360 its value has been stored. */
13363 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13365 rs6000_stack_t *info = rs6000_stack_info ();
13368 operands[0] = source;
13369 operands[1] = scratch;
13371 if (info->lr_save_p)
13373 rtx frame_rtx = stack_pointer_rtx;
13374 HOST_WIDE_INT sp_offset = 0;
13377 if (frame_pointer_needed
13378 || current_function_calls_alloca
13379 || info->total_size > 32767)
13381 tmp = gen_rtx_MEM (Pmode, frame_rtx);
13382 MEM_NOTRAP_P (tmp) = 1;
13383 set_mem_alias_set (tmp, rs6000_sr_alias_set);
13384 emit_move_insn (operands[1], tmp);
13385 frame_rtx = operands[1];
13387 else if (info->push_p)
13388 sp_offset = info->total_size;
13390 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13391 tmp = gen_rtx_MEM (Pmode, tmp);
13392 MEM_NOTRAP_P (tmp) = 1;
13393 set_mem_alias_set (tmp, rs6000_sr_alias_set);
13394 emit_move_insn (tmp, operands[0]);
13397 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13400 static GTY(()) int set = -1;
13403 get_TOC_alias_set (void)
13406 set = new_alias_set ();
13410 /* This returns nonzero if the current function uses the TOC. This is
13411 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13412 is generated by the ABI_V4 load_toc_* patterns. */
13419 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13422 rtx pat = PATTERN (insn);
13425 if (GET_CODE (pat) == PARALLEL)
13426 for (i = 0; i < XVECLEN (pat, 0); i++)
13428 rtx sub = XVECEXP (pat, 0, i);
13429 if (GET_CODE (sub) == USE)
13431 sub = XEXP (sub, 0);
13432 if (GET_CODE (sub) == UNSPEC
13433 && XINT (sub, 1) == UNSPEC_TOC)
13443 create_TOC_reference (rtx symbol)
13445 return gen_rtx_PLUS (Pmode,
13446 gen_rtx_REG (Pmode, TOC_REGISTER),
13447 gen_rtx_CONST (Pmode,
13448 gen_rtx_MINUS (Pmode, symbol,
13449 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13452 /* If _Unwind_* has been called from within the same module,
13453 toc register is not guaranteed to be saved to 40(1) on function
13454 entry. Save it there in that case. */
13457 rs6000_aix_emit_builtin_unwind_init (void)
13460 rtx stack_top = gen_reg_rtx (Pmode);
13461 rtx opcode_addr = gen_reg_rtx (Pmode);
13462 rtx opcode = gen_reg_rtx (SImode);
13463 rtx tocompare = gen_reg_rtx (SImode);
13464 rtx no_toc_save_needed = gen_label_rtx ();
13466 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13467 emit_move_insn (stack_top, mem);
13469 mem = gen_frame_mem (Pmode,
13470 gen_rtx_PLUS (Pmode, stack_top,
13471 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13472 emit_move_insn (opcode_addr, mem);
13473 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13474 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13475 : 0xE8410028, SImode));
13477 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13478 SImode, NULL_RTX, NULL_RTX,
13479 no_toc_save_needed);
13481 mem = gen_frame_mem (Pmode,
13482 gen_rtx_PLUS (Pmode, stack_top,
13483 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13484 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13485 emit_label (no_toc_save_needed);
13488 /* This ties together stack memory (MEM with an alias set of
13489 rs6000_sr_alias_set) and the change to the stack pointer. */
13492 rs6000_emit_stack_tie (void)
13494 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13496 set_mem_alias_set (mem, rs6000_sr_alias_set);
13497 emit_insn (gen_stack_tie (mem));
13500 /* Emit the correct code for allocating stack space, as insns.
13501 If COPY_R12, make sure a copy of the old frame is left in r12.
13502 The generated code may use hard register 0 as a temporary. */
13505 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13508 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13509 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13510 rtx todec = gen_int_mode (-size, Pmode);
13512 if (INTVAL (todec) != -size)
13514 warning (0, "stack frame too large");
13515 emit_insn (gen_trap ());
13519 if (current_function_limit_stack)
13521 if (REG_P (stack_limit_rtx)
13522 && REGNO (stack_limit_rtx) > 1
13523 && REGNO (stack_limit_rtx) <= 31)
13525 emit_insn (TARGET_32BIT
13526 ? gen_addsi3 (tmp_reg,
13529 : gen_adddi3 (tmp_reg,
13533 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13536 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13538 && DEFAULT_ABI == ABI_V4)
13540 rtx toload = gen_rtx_CONST (VOIDmode,
13541 gen_rtx_PLUS (Pmode,
13545 emit_insn (gen_elf_high (tmp_reg, toload));
13546 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13547 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13551 warning (0, "stack limit expression is not supported");
13554 if (copy_r12 || ! TARGET_UPDATE)
13555 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13561 /* Need a note here so that try_split doesn't get confused. */
13562 if (get_last_insn () == NULL_RTX)
13563 emit_note (NOTE_INSN_DELETED);
13564 insn = emit_move_insn (tmp_reg, todec);
13565 try_split (PATTERN (insn), insn, 0);
13569 insn = emit_insn (TARGET_32BIT
13570 ? gen_movsi_update (stack_reg, stack_reg,
13572 : gen_movdi_di_update (stack_reg, stack_reg,
13573 todec, stack_reg));
13577 insn = emit_insn (TARGET_32BIT
13578 ? gen_addsi3 (stack_reg, stack_reg, todec)
13579 : gen_adddi3 (stack_reg, stack_reg, todec));
13580 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13581 gen_rtx_REG (Pmode, 12));
13584 RTX_FRAME_RELATED_P (insn) = 1;
13586 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13587 gen_rtx_SET (VOIDmode, stack_reg,
13588 gen_rtx_PLUS (Pmode, stack_reg,
13593 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13594 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13595 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13596 deduce these equivalences by itself so it wasn't necessary to hold
13597 its hand so much. */
13600 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13601 rtx reg2, rtx rreg)
13605 /* copy_rtx will not make unique copies of registers, so we need to
13606 ensure we don't have unwanted sharing here. */
13608 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13611 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13613 real = copy_rtx (PATTERN (insn));
13615 if (reg2 != NULL_RTX)
13616 real = replace_rtx (real, reg2, rreg);
13618 real = replace_rtx (real, reg,
13619 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13620 STACK_POINTER_REGNUM),
13623 /* We expect that 'real' is either a SET or a PARALLEL containing
13624 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13625 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13627 if (GET_CODE (real) == SET)
13631 temp = simplify_rtx (SET_SRC (set));
13633 SET_SRC (set) = temp;
13634 temp = simplify_rtx (SET_DEST (set));
13636 SET_DEST (set) = temp;
13637 if (GET_CODE (SET_DEST (set)) == MEM)
13639 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13641 XEXP (SET_DEST (set), 0) = temp;
13648 gcc_assert (GET_CODE (real) == PARALLEL);
13649 for (i = 0; i < XVECLEN (real, 0); i++)
13650 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13652 rtx set = XVECEXP (real, 0, i);
13654 temp = simplify_rtx (SET_SRC (set));
13656 SET_SRC (set) = temp;
13657 temp = simplify_rtx (SET_DEST (set));
13659 SET_DEST (set) = temp;
13660 if (GET_CODE (SET_DEST (set)) == MEM)
13662 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13664 XEXP (SET_DEST (set), 0) = temp;
13666 RTX_FRAME_RELATED_P (set) = 1;
13671 real = spe_synthesize_frame_save (real);
13673 RTX_FRAME_RELATED_P (insn) = 1;
13674 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13679 /* Given an SPE frame note, return a PARALLEL of SETs with the
13680 original note, plus a synthetic register save. */
13683 spe_synthesize_frame_save (rtx real)
13685 rtx synth, offset, reg, real2;
13687 if (GET_CODE (real) != SET
13688 || GET_MODE (SET_SRC (real)) != V2SImode)
13691 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13692 frame related note. The parallel contains a set of the register
13693 being saved, and another set to a synthetic register (n+1200).
13694 This is so we can differentiate between 64-bit and 32-bit saves.
13695 Words cannot describe this nastiness. */
13697 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13698 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13699 && GET_CODE (SET_SRC (real)) == REG);
13702 (set (mem (plus (reg x) (const y)))
13705 (set (mem (plus (reg x) (const y+4)))
13709 real2 = copy_rtx (real);
13710 PUT_MODE (SET_DEST (real2), SImode);
13711 reg = SET_SRC (real2);
13712 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13713 synth = copy_rtx (real2);
13715 if (BYTES_BIG_ENDIAN)
13717 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13718 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13721 reg = SET_SRC (synth);
13723 synth = replace_rtx (synth, reg,
13724 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13726 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13727 synth = replace_rtx (synth, offset,
13728 GEN_INT (INTVAL (offset)
13729 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13731 RTX_FRAME_RELATED_P (synth) = 1;
13732 RTX_FRAME_RELATED_P (real2) = 1;
13733 if (BYTES_BIG_ENDIAN)
13734 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13736 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13741 /* Returns an insn that has a vrsave set operation with the
13742 appropriate CLOBBERs. */
13745 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13748 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13749 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13752 = gen_rtx_SET (VOIDmode,
13754 gen_rtx_UNSPEC_VOLATILE (SImode,
13755 gen_rtvec (2, reg, vrsave),
13756 UNSPECV_SET_VRSAVE));
13760 /* We need to clobber the registers in the mask so the scheduler
13761 does not move sets to VRSAVE before sets of AltiVec registers.
13763 However, if the function receives nonlocal gotos, reload will set
13764 all call saved registers live. We will end up with:
13766 (set (reg 999) (mem))
13767 (parallel [ (set (reg vrsave) (unspec blah))
13768 (clobber (reg 999))])
13770 The clobber will cause the store into reg 999 to be dead, and
13771 flow will attempt to delete an epilogue insn. In this case, we
13772 need an unspec use/set of the register. */
13774 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13775 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13777 if (!epiloguep || call_used_regs [i])
13778 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13779 gen_rtx_REG (V4SImode, i));
13782 rtx reg = gen_rtx_REG (V4SImode, i);
13785 = gen_rtx_SET (VOIDmode,
13787 gen_rtx_UNSPEC (V4SImode,
13788 gen_rtvec (1, reg), 27));
13792 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13794 for (i = 0; i < nclobs; ++i)
13795 XVECEXP (insn, 0, i) = clobs[i];
13800 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13801 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13804 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13805 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13807 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13808 rtx replacea, replaceb;
13810 int_rtx = GEN_INT (offset);
13812 /* Some cases that need register indexed addressing. */
13813 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13814 || (TARGET_E500_DOUBLE && mode == DFmode)
13816 && SPE_VECTOR_MODE (mode)
13817 && !SPE_CONST_OFFSET_OK (offset)))
13819 /* Whomever calls us must make sure r11 is available in the
13820 flow path of instructions in the prologue. */
13821 offset_rtx = gen_rtx_REG (Pmode, 11);
13822 emit_move_insn (offset_rtx, int_rtx);
13824 replacea = offset_rtx;
13825 replaceb = int_rtx;
13829 offset_rtx = int_rtx;
13830 replacea = NULL_RTX;
13831 replaceb = NULL_RTX;
13834 reg = gen_rtx_REG (mode, regno);
13835 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13836 mem = gen_rtx_MEM (mode, addr);
13837 set_mem_alias_set (mem, rs6000_sr_alias_set);
13839 insn = emit_move_insn (mem, reg);
13841 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13844 /* Emit an offset memory reference suitable for a frame store, while
13845 converting to a valid addressing mode. */
13848 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13850 rtx int_rtx, offset_rtx;
13852 int_rtx = GEN_INT (offset);
13854 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13855 || (TARGET_E500_DOUBLE && mode == DFmode))
13857 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13858 emit_move_insn (offset_rtx, int_rtx);
13861 offset_rtx = int_rtx;
13863 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13866 /* Look for user-defined global regs. We should not save and restore these,
13867 and cannot use stmw/lmw if there are any in its range. */
13870 no_global_regs_above (int first_greg)
13873 for (i = 0; i < 32 - first_greg; i++)
13874 if (global_regs[first_greg + i])
13879 #ifndef TARGET_FIX_AND_CONTINUE
13880 #define TARGET_FIX_AND_CONTINUE 0
13883 /* Emit function prologue as insns. */
13886 rs6000_emit_prologue (void)
13888 rs6000_stack_t *info = rs6000_stack_info ();
13889 enum machine_mode reg_mode = Pmode;
13890 int reg_size = TARGET_32BIT ? 4 : 8;
13891 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13892 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13893 rtx frame_reg_rtx = sp_reg_rtx;
13894 rtx cr_save_rtx = NULL_RTX;
13896 int saving_FPRs_inline;
13897 int using_store_multiple;
13898 HOST_WIDE_INT sp_offset = 0;
13900 if (TARGET_FIX_AND_CONTINUE)
13902 /* gdb on darwin arranges to forward a function from the old
13903 address by modifying the first 5 instructions of the function
13904 to branch to the overriding function. This is necessary to
13905 permit function pointers that point to the old function to
13906 actually forward to the new function. */
13907 emit_insn (gen_nop ());
13908 emit_insn (gen_nop ());
13909 emit_insn (gen_nop ());
13910 emit_insn (gen_nop ());
13911 emit_insn (gen_nop ());
13914 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13916 reg_mode = V2SImode;
13920 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13921 && (!TARGET_SPE_ABI
13922 || info->spe_64bit_regs_used == 0)
13923 && info->first_gp_reg_save < 31
13924 && no_global_regs_above (info->first_gp_reg_save));
13925 saving_FPRs_inline = (info->first_fp_reg_save == 64
13926 || FP_SAVE_INLINE (info->first_fp_reg_save)
13927 || current_function_calls_eh_return
13928 || cfun->machine->ra_need_lr);
13930 /* For V.4, update stack before we do any saving and set back pointer. */
13932 && (DEFAULT_ABI == ABI_V4
13933 || current_function_calls_eh_return))
13935 if (info->total_size < 32767)
13936 sp_offset = info->total_size;
13938 frame_reg_rtx = frame_ptr_rtx;
13939 rs6000_emit_allocate_stack (info->total_size,
13940 (frame_reg_rtx != sp_reg_rtx
13941 && (info->cr_save_p
13943 || info->first_fp_reg_save < 64
13944 || info->first_gp_reg_save < 32
13946 if (frame_reg_rtx != sp_reg_rtx)
13947 rs6000_emit_stack_tie ();
13950 /* Handle world saves specially here. */
13951 if (WORLD_SAVE_P (info))
13957 /* save_world expects lr in r0. */
13958 if (info->lr_save_p)
13960 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13961 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13962 RTX_FRAME_RELATED_P (insn) = 1;
13965 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13966 assumptions about the offsets of various bits of the stack
13968 gcc_assert (info->gp_save_offset == -220
13969 && info->fp_save_offset == -144
13970 && info->lr_save_offset == 8
13971 && info->cr_save_offset == 4
13974 && (!current_function_calls_eh_return
13975 || info->ehrd_offset == -432)
13976 && info->vrsave_save_offset == -224
13977 && info->altivec_save_offset == (-224 -16 -192));
13979 treg = gen_rtx_REG (SImode, 11);
13980 emit_move_insn (treg, GEN_INT (-info->total_size));
13982 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13983 in R11. It also clobbers R12, so beware! */
13985 /* Preserve CR2 for save_world prologues */
13987 sz += 32 - info->first_gp_reg_save;
13988 sz += 64 - info->first_fp_reg_save;
13989 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13990 p = rtvec_alloc (sz);
13992 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13993 gen_rtx_REG (Pmode,
13994 LINK_REGISTER_REGNUM));
13995 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13996 gen_rtx_SYMBOL_REF (Pmode,
13998 /* We do floats first so that the instruction pattern matches
14000 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14002 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14003 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14004 GEN_INT (info->fp_save_offset
14005 + sp_offset + 8 * i));
14006 rtx mem = gen_rtx_MEM (DFmode, addr);
14007 set_mem_alias_set (mem, rs6000_sr_alias_set);
14009 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14011 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14013 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14014 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14015 GEN_INT (info->altivec_save_offset
14016 + sp_offset + 16 * i));
14017 rtx mem = gen_rtx_MEM (V4SImode, addr);
14018 set_mem_alias_set (mem, rs6000_sr_alias_set);
14020 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14022 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14024 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14025 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14026 GEN_INT (info->gp_save_offset
14027 + sp_offset + reg_size * i));
14028 rtx mem = gen_rtx_MEM (reg_mode, addr);
14029 set_mem_alias_set (mem, rs6000_sr_alias_set);
14031 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14035 /* CR register traditionally saved as CR2. */
14036 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14037 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14038 GEN_INT (info->cr_save_offset
14040 rtx mem = gen_rtx_MEM (reg_mode, addr);
14041 set_mem_alias_set (mem, rs6000_sr_alias_set);
14043 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14045 /* Prevent any attempt to delete the setting of r0 and treg! */
14046 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14047 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14048 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14050 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14051 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14052 NULL_RTX, NULL_RTX);
14054 if (current_function_calls_eh_return)
14059 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14060 if (regno == INVALID_REGNUM)
14062 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14063 info->ehrd_offset + sp_offset
14064 + reg_size * (int) i,
14070 /* Save AltiVec registers if needed. */
14071 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14075 /* There should be a non inline version of this, for when we
14076 are saving lots of vector registers. */
14077 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14078 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14080 rtx areg, savereg, mem;
14083 offset = info->altivec_save_offset + sp_offset
14084 + 16 * (i - info->first_altivec_reg_save);
14086 savereg = gen_rtx_REG (V4SImode, i);
14088 areg = gen_rtx_REG (Pmode, 0);
14089 emit_move_insn (areg, GEN_INT (offset));
14091 /* AltiVec addressing mode is [reg+reg]. */
14092 mem = gen_rtx_MEM (V4SImode,
14093 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14095 set_mem_alias_set (mem, rs6000_sr_alias_set);
14097 insn = emit_move_insn (mem, savereg);
14099 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14100 areg, GEN_INT (offset));
14104 /* VRSAVE is a bit vector representing which AltiVec registers
14105 are used. The OS uses this to determine which vector
14106 registers to save on a context switch. We need to save
14107 VRSAVE on the stack frame, add whatever AltiVec registers we
14108 used in this function, and do the corresponding magic in the
14111 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14112 && info->vrsave_mask != 0)
14114 rtx reg, mem, vrsave;
14117 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14118 as frame_reg_rtx and r11 as the static chain pointer for
14119 nested functions. */
14120 reg = gen_rtx_REG (SImode, 0);
14121 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14123 emit_insn (gen_get_vrsave_internal (reg));
14125 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14127 if (!WORLD_SAVE_P (info))
14130 offset = info->vrsave_save_offset + sp_offset;
14132 = gen_rtx_MEM (SImode,
14133 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14134 set_mem_alias_set (mem, rs6000_sr_alias_set);
14135 insn = emit_move_insn (mem, reg);
14138 /* Include the registers in the mask. */
14139 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14141 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14144 /* If we use the link register, get it into r0. */
14145 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14147 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14148 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14149 RTX_FRAME_RELATED_P (insn) = 1;
14152 /* If we need to save CR, put it into r12. */
14153 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14157 cr_save_rtx = gen_rtx_REG (SImode, 12);
14158 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14159 RTX_FRAME_RELATED_P (insn) = 1;
14160 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14161 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14162 But that's OK. All we have to do is specify that _one_ condition
14163 code register is saved in this stack slot. The thrower's epilogue
14164 will then restore all the call-saved registers.
14165 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14166 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14167 gen_rtx_REG (SImode, CR2_REGNO));
14168 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14173 /* Do any required saving of fpr's. If only one or two to save, do
14174 it ourselves. Otherwise, call function. */
14175 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14178 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14179 if ((regs_ever_live[info->first_fp_reg_save+i]
14180 && ! call_used_regs[info->first_fp_reg_save+i]))
14181 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14182 info->first_fp_reg_save + i,
14183 info->fp_save_offset + sp_offset + 8 * i,
14186 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14190 const char *alloc_rname;
14192 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14194 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14195 gen_rtx_REG (Pmode,
14196 LINK_REGISTER_REGNUM));
14197 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14198 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14199 alloc_rname = ggc_strdup (rname);
14200 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14201 gen_rtx_SYMBOL_REF (Pmode,
14203 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14205 rtx addr, reg, mem;
14206 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14207 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14208 GEN_INT (info->fp_save_offset
14209 + sp_offset + 8*i));
14210 mem = gen_rtx_MEM (DFmode, addr);
14211 set_mem_alias_set (mem, rs6000_sr_alias_set);
14213 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14215 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14216 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14217 NULL_RTX, NULL_RTX);
14220 /* Save GPRs. This is done as a PARALLEL if we are using
14221 the store-multiple instructions. */
14222 if (!WORLD_SAVE_P (info) && using_store_multiple)
14226 p = rtvec_alloc (32 - info->first_gp_reg_save);
14227 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14229 rtx addr, reg, mem;
14230 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14231 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14232 GEN_INT (info->gp_save_offset
14235 mem = gen_rtx_MEM (reg_mode, addr);
14236 set_mem_alias_set (mem, rs6000_sr_alias_set);
14238 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14240 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14241 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14242 NULL_RTX, NULL_RTX);
14244 else if (!WORLD_SAVE_P (info))
14247 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14248 if ((regs_ever_live[info->first_gp_reg_save + i]
14249 && (!call_used_regs[info->first_gp_reg_save + i]
14250 || (i + info->first_gp_reg_save
14251 == RS6000_PIC_OFFSET_TABLE_REGNUM
14252 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14253 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14254 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14255 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14257 rtx addr, reg, mem;
14258 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14260 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14262 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14265 if (!SPE_CONST_OFFSET_OK (offset))
14267 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14268 emit_move_insn (b, GEN_INT (offset));
14271 b = GEN_INT (offset);
14273 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14274 mem = gen_rtx_MEM (V2SImode, addr);
14275 set_mem_alias_set (mem, rs6000_sr_alias_set);
14276 insn = emit_move_insn (mem, reg);
14278 if (GET_CODE (b) == CONST_INT)
14279 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14280 NULL_RTX, NULL_RTX);
14282 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14283 b, GEN_INT (offset));
14287 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14288 GEN_INT (info->gp_save_offset
14291 mem = gen_rtx_MEM (reg_mode, addr);
14292 set_mem_alias_set (mem, rs6000_sr_alias_set);
14294 insn = emit_move_insn (mem, reg);
14295 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14296 NULL_RTX, NULL_RTX);
14301 /* ??? There's no need to emit actual instructions here, but it's the
14302 easiest way to get the frame unwind information emitted. */
14303 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14305 unsigned int i, regno;
14307 /* In AIX ABI we need to pretend we save r2 here. */
14310 rtx addr, reg, mem;
14312 reg = gen_rtx_REG (reg_mode, 2);
14313 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14314 GEN_INT (sp_offset + 5 * reg_size));
14315 mem = gen_rtx_MEM (reg_mode, addr);
14316 set_mem_alias_set (mem, rs6000_sr_alias_set);
14318 insn = emit_move_insn (mem, reg);
14319 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14320 NULL_RTX, NULL_RTX);
14321 PATTERN (insn) = gen_blockage ();
14326 regno = EH_RETURN_DATA_REGNO (i);
14327 if (regno == INVALID_REGNUM)
14330 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14331 info->ehrd_offset + sp_offset
14332 + reg_size * (int) i,
14337 /* Save lr if we used it. */
14338 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14340 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14341 GEN_INT (info->lr_save_offset + sp_offset));
14342 rtx reg = gen_rtx_REG (Pmode, 0);
14343 rtx mem = gen_rtx_MEM (Pmode, addr);
14344 /* This should not be of rs6000_sr_alias_set, because of
14345 __builtin_return_address. */
14347 insn = emit_move_insn (mem, reg);
14348 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14349 NULL_RTX, NULL_RTX);
14352 /* Save CR if we use any that must be preserved. */
14353 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14355 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14356 GEN_INT (info->cr_save_offset + sp_offset));
14357 rtx mem = gen_rtx_MEM (SImode, addr);
14358 /* See the large comment above about why CR2_REGNO is used. */
14359 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14361 set_mem_alias_set (mem, rs6000_sr_alias_set);
14363 /* If r12 was used to hold the original sp, copy cr into r0 now
14365 if (REGNO (frame_reg_rtx) == 12)
14369 cr_save_rtx = gen_rtx_REG (SImode, 0);
14370 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14371 RTX_FRAME_RELATED_P (insn) = 1;
14372 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14373 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14378 insn = emit_move_insn (mem, cr_save_rtx);
14380 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14381 NULL_RTX, NULL_RTX);
14384 /* Update stack and set back pointer unless this is V.4,
14385 for which it was done previously. */
14386 if (!WORLD_SAVE_P (info) && info->push_p
14387 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14388 rs6000_emit_allocate_stack (info->total_size, FALSE);
14390 /* Set frame pointer, if needed. */
14391 if (frame_pointer_needed)
14393 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14395 RTX_FRAME_RELATED_P (insn) = 1;
14398 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14399 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14400 || (DEFAULT_ABI == ABI_V4
14401 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14402 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14404 /* If emit_load_toc_table will use the link register, we need to save
14405 it. We use R12 for this purpose because emit_load_toc_table
14406 can use register 0. This allows us to use a plain 'blr' to return
14407 from the procedure more often. */
14408 int save_LR_around_toc_setup = (TARGET_ELF
14409 && DEFAULT_ABI != ABI_AIX
14411 && ! info->lr_save_p
14412 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14413 if (save_LR_around_toc_setup)
14415 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14417 insn = emit_move_insn (frame_ptr_rtx, lr);
14418 rs6000_maybe_dead (insn);
14419 RTX_FRAME_RELATED_P (insn) = 1;
14421 rs6000_emit_load_toc_table (TRUE);
14423 insn = emit_move_insn (lr, frame_ptr_rtx);
14424 rs6000_maybe_dead (insn);
14425 RTX_FRAME_RELATED_P (insn) = 1;
14428 rs6000_emit_load_toc_table (TRUE);
14432 if (DEFAULT_ABI == ABI_DARWIN
14433 && flag_pic && current_function_uses_pic_offset_table)
14435 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14436 rtx src = machopic_function_base_sym ();
14438 /* Save and restore LR locally around this call (in R0). */
14439 if (!info->lr_save_p)
14440 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14442 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14444 insn = emit_move_insn (gen_rtx_REG (Pmode,
14445 RS6000_PIC_OFFSET_TABLE_REGNUM),
14447 rs6000_maybe_dead (insn);
14449 if (!info->lr_save_p)
14450 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14455 /* Write function prologue. */
14458 rs6000_output_function_prologue (FILE *file,
14459 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14461 rs6000_stack_t *info = rs6000_stack_info ();
14463 if (TARGET_DEBUG_STACK)
14464 debug_stack_info (info);
14466 /* Write .extern for any function we will call to save and restore
14468 if (info->first_fp_reg_save < 64
14469 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14470 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14471 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14472 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14473 RESTORE_FP_SUFFIX);
14475 /* Write .extern for AIX common mode routines, if needed. */
14476 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14478 fputs ("\t.extern __mulh\n", file);
14479 fputs ("\t.extern __mull\n", file);
14480 fputs ("\t.extern __divss\n", file);
14481 fputs ("\t.extern __divus\n", file);
14482 fputs ("\t.extern __quoss\n", file);
14483 fputs ("\t.extern __quous\n", file);
14484 common_mode_defined = 1;
14487 if (! HAVE_prologue)
14491 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14492 the "toplevel" insn chain. */
14493 emit_note (NOTE_INSN_DELETED);
14494 rs6000_emit_prologue ();
14495 emit_note (NOTE_INSN_DELETED);
14497 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14501 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14503 INSN_ADDRESSES_NEW (insn, addr);
14508 if (TARGET_DEBUG_STACK)
14509 debug_rtx_list (get_insns (), 100);
14510 final (get_insns (), file, FALSE);
14514 rs6000_pic_labelno++;
14517 /* Emit function epilogue as insns.
14519 At present, dwarf2out_frame_debug_expr doesn't understand
14520 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14521 anywhere in the epilogue. Most of the insns below would in any case
14522 need special notes to explain where r11 is in relation to the stack. */
14525 rs6000_emit_epilogue (int sibcall)
14527 rs6000_stack_t *info;
14528 int restoring_FPRs_inline;
14529 int using_load_multiple;
14530 int using_mfcr_multiple;
14531 int use_backchain_to_restore_sp;
14533 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14534 rtx frame_reg_rtx = sp_reg_rtx;
14535 enum machine_mode reg_mode = Pmode;
14536 int reg_size = TARGET_32BIT ? 4 : 8;
14539 info = rs6000_stack_info ();
14541 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14543 reg_mode = V2SImode;
14547 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14548 && (!TARGET_SPE_ABI
14549 || info->spe_64bit_regs_used == 0)
14550 && info->first_gp_reg_save < 31
14551 && no_global_regs_above (info->first_gp_reg_save));
14552 restoring_FPRs_inline = (sibcall
14553 || current_function_calls_eh_return
14554 || info->first_fp_reg_save == 64
14555 || FP_SAVE_INLINE (info->first_fp_reg_save));
14556 use_backchain_to_restore_sp = (frame_pointer_needed
14557 || current_function_calls_alloca
14558 || info->total_size > 32767);
14559 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14560 || rs6000_cpu == PROCESSOR_PPC603
14561 || rs6000_cpu == PROCESSOR_PPC750
14564 if (WORLD_SAVE_P (info))
14568 const char *alloc_rname;
14571 /* eh_rest_world_r10 will return to the location saved in the LR
14572 stack slot (which is not likely to be our caller.)
14573 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14574 rest_world is similar, except any R10 parameter is ignored.
14575 The exception-handling stuff that was here in 2.95 is no
14576 longer necessary. */
14580 + 32 - info->first_gp_reg_save
14581 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14582 + 63 + 1 - info->first_fp_reg_save);
14584 strcpy (rname, ((current_function_calls_eh_return) ?
14585 "*eh_rest_world_r10" : "*rest_world"));
14586 alloc_rname = ggc_strdup (rname);
14589 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14590 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14591 gen_rtx_REG (Pmode,
14592 LINK_REGISTER_REGNUM));
14594 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14595 /* The instruction pattern requires a clobber here;
14596 it is shared with the restVEC helper. */
14598 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14601 /* CR register traditionally saved as CR2. */
14602 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14603 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14604 GEN_INT (info->cr_save_offset));
14605 rtx mem = gen_rtx_MEM (reg_mode, addr);
14606 set_mem_alias_set (mem, rs6000_sr_alias_set);
14608 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14611 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14613 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14614 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14615 GEN_INT (info->gp_save_offset
14617 rtx mem = gen_rtx_MEM (reg_mode, addr);
14618 set_mem_alias_set (mem, rs6000_sr_alias_set);
14620 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14622 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14624 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14625 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14626 GEN_INT (info->altivec_save_offset
14628 rtx mem = gen_rtx_MEM (V4SImode, addr);
14629 set_mem_alias_set (mem, rs6000_sr_alias_set);
14631 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14633 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14635 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14636 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14637 GEN_INT (info->fp_save_offset
14639 rtx mem = gen_rtx_MEM (DFmode, addr);
14640 set_mem_alias_set (mem, rs6000_sr_alias_set);
14642 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14645 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14647 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14649 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14651 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14653 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14654 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14659 /* If we have a frame pointer, a call to alloca, or a large stack
14660 frame, restore the old stack pointer using the backchain. Otherwise,
14661 we know what size to update it with. */
14662 if (use_backchain_to_restore_sp)
14664 /* Under V.4, don't reset the stack pointer until after we're done
14665 loading the saved registers. */
14666 if (DEFAULT_ABI == ABI_V4)
14667 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14669 emit_move_insn (frame_reg_rtx,
14670 gen_rtx_MEM (Pmode, sp_reg_rtx));
14673 else if (info->push_p)
14675 if (DEFAULT_ABI == ABI_V4
14676 || current_function_calls_eh_return)
14677 sp_offset = info->total_size;
14680 emit_insn (TARGET_32BIT
14681 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14682 GEN_INT (info->total_size))
14683 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14684 GEN_INT (info->total_size)));
14688 /* Restore AltiVec registers if needed. */
14689 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14693 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14694 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14696 rtx addr, areg, mem;
14698 areg = gen_rtx_REG (Pmode, 0);
14700 (areg, GEN_INT (info->altivec_save_offset
14702 + 16 * (i - info->first_altivec_reg_save)));
14704 /* AltiVec addressing mode is [reg+reg]. */
14705 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14706 mem = gen_rtx_MEM (V4SImode, addr);
14707 set_mem_alias_set (mem, rs6000_sr_alias_set);
14709 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14713 /* Restore VRSAVE if needed. */
14714 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14715 && info->vrsave_mask != 0)
14717 rtx addr, mem, reg;
14719 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14720 GEN_INT (info->vrsave_save_offset + sp_offset));
14721 mem = gen_rtx_MEM (SImode, addr);
14722 set_mem_alias_set (mem, rs6000_sr_alias_set);
14723 reg = gen_rtx_REG (SImode, 12);
14724 emit_move_insn (reg, mem);
14726 emit_insn (generate_set_vrsave (reg, info, 1));
14729 /* Get the old lr if we saved it. */
14730 if (info->lr_save_p)
14732 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14733 info->lr_save_offset + sp_offset);
14735 set_mem_alias_set (mem, rs6000_sr_alias_set);
14737 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14740 /* Get the old cr if we saved it. */
14741 if (info->cr_save_p)
14743 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14744 GEN_INT (info->cr_save_offset + sp_offset));
14745 rtx mem = gen_rtx_MEM (SImode, addr);
14747 set_mem_alias_set (mem, rs6000_sr_alias_set);
14749 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14752 /* Set LR here to try to overlap restores below. */
14753 if (info->lr_save_p)
14754 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14755 gen_rtx_REG (Pmode, 0));
14757 /* Load exception handler data registers, if needed. */
14758 if (current_function_calls_eh_return)
14760 unsigned int i, regno;
14764 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14765 GEN_INT (sp_offset + 5 * reg_size));
14766 rtx mem = gen_rtx_MEM (reg_mode, addr);
14768 set_mem_alias_set (mem, rs6000_sr_alias_set);
14770 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14777 regno = EH_RETURN_DATA_REGNO (i);
14778 if (regno == INVALID_REGNUM)
14781 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14782 info->ehrd_offset + sp_offset
14783 + reg_size * (int) i);
14784 set_mem_alias_set (mem, rs6000_sr_alias_set);
14786 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14790 /* Restore GPRs. This is done as a PARALLEL if we are using
14791 the load-multiple instructions. */
14792 if (using_load_multiple)
14795 p = rtvec_alloc (32 - info->first_gp_reg_save);
14796 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14798 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14799 GEN_INT (info->gp_save_offset
14802 rtx mem = gen_rtx_MEM (reg_mode, addr);
14804 set_mem_alias_set (mem, rs6000_sr_alias_set);
14807 gen_rtx_SET (VOIDmode,
14808 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14811 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14814 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14815 if ((regs_ever_live[info->first_gp_reg_save + i]
14816 && (!call_used_regs[info->first_gp_reg_save + i]
14817 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14818 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14819 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14820 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14821 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14823 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14824 GEN_INT (info->gp_save_offset
14827 rtx mem = gen_rtx_MEM (reg_mode, addr);
14829 /* Restore 64-bit quantities for SPE. */
14830 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14832 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14835 if (!SPE_CONST_OFFSET_OK (offset))
14837 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14838 emit_move_insn (b, GEN_INT (offset));
14841 b = GEN_INT (offset);
14843 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14844 mem = gen_rtx_MEM (V2SImode, addr);
14847 set_mem_alias_set (mem, rs6000_sr_alias_set);
14849 emit_move_insn (gen_rtx_REG (reg_mode,
14850 info->first_gp_reg_save + i), mem);
14853 /* Restore fpr's if we need to do it without calling a function. */
14854 if (restoring_FPRs_inline)
14855 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14856 if ((regs_ever_live[info->first_fp_reg_save+i]
14857 && ! call_used_regs[info->first_fp_reg_save+i]))
14860 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14861 GEN_INT (info->fp_save_offset
14864 mem = gen_rtx_MEM (DFmode, addr);
14865 set_mem_alias_set (mem, rs6000_sr_alias_set);
14867 emit_move_insn (gen_rtx_REG (DFmode,
14868 info->first_fp_reg_save + i),
14872 /* If we saved cr, restore it here. Just those that were used. */
14873 if (info->cr_save_p)
14875 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14878 if (using_mfcr_multiple)
14880 for (i = 0; i < 8; i++)
14881 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14883 gcc_assert (count);
14886 if (using_mfcr_multiple && count > 1)
14891 p = rtvec_alloc (count);
14894 for (i = 0; i < 8; i++)
14895 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14897 rtvec r = rtvec_alloc (2);
14898 RTVEC_ELT (r, 0) = r12_rtx;
14899 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14900 RTVEC_ELT (p, ndx) =
14901 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14902 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14905 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14906 gcc_assert (ndx == count);
14909 for (i = 0; i < 8; i++)
14910 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14912 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14918 /* If this is V.4, unwind the stack pointer after all of the loads
14919 have been done. We need to emit a block here so that sched
14920 doesn't decide to move the sp change before the register restores
14921 (which may not have any obvious dependency on the stack). This
14922 doesn't hurt performance, because there is no scheduling that can
14923 be done after this point. */
14924 if (DEFAULT_ABI == ABI_V4
14925 || current_function_calls_eh_return)
14927 if (frame_reg_rtx != sp_reg_rtx)
14928 rs6000_emit_stack_tie ();
14930 if (use_backchain_to_restore_sp)
14932 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14934 else if (sp_offset != 0)
14936 emit_insn (TARGET_32BIT
14937 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14938 GEN_INT (sp_offset))
14939 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14940 GEN_INT (sp_offset)));
14944 if (current_function_calls_eh_return)
14946 rtx sa = EH_RETURN_STACKADJ_RTX;
14947 emit_insn (TARGET_32BIT
14948 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14949 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14955 if (! restoring_FPRs_inline)
14956 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14958 p = rtvec_alloc (2);
14960 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14961 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14962 gen_rtx_REG (Pmode,
14963 LINK_REGISTER_REGNUM));
14965 /* If we have to restore more than two FP registers, branch to the
14966 restore function. It will return to our caller. */
14967 if (! restoring_FPRs_inline)
14971 const char *alloc_rname;
14973 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14974 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14975 alloc_rname = ggc_strdup (rname);
14976 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14977 gen_rtx_SYMBOL_REF (Pmode,
14980 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14983 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14984 GEN_INT (info->fp_save_offset + 8*i));
14985 mem = gen_rtx_MEM (DFmode, addr);
14986 set_mem_alias_set (mem, rs6000_sr_alias_set);
14988 RTVEC_ELT (p, i+3) =
14989 gen_rtx_SET (VOIDmode,
14990 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14995 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14999 /* Write function epilogue. */
15002 rs6000_output_function_epilogue (FILE *file,
15003 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15005 rs6000_stack_t *info = rs6000_stack_info ();
15007 if (! HAVE_epilogue)
15009 rtx insn = get_last_insn ();
15010 /* If the last insn was a BARRIER, we don't have to write anything except
15011 the trace table. */
15012 if (GET_CODE (insn) == NOTE)
15013 insn = prev_nonnote_insn (insn);
15014 if (insn == 0 || GET_CODE (insn) != BARRIER)
15016 /* This is slightly ugly, but at least we don't have two
15017 copies of the epilogue-emitting code. */
15020 /* A NOTE_INSN_DELETED is supposed to be at the start
15021 and end of the "toplevel" insn chain. */
15022 emit_note (NOTE_INSN_DELETED);
15023 rs6000_emit_epilogue (FALSE);
15024 emit_note (NOTE_INSN_DELETED);
15026 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15030 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15032 INSN_ADDRESSES_NEW (insn, addr);
15037 if (TARGET_DEBUG_STACK)
15038 debug_rtx_list (get_insns (), 100);
15039 final (get_insns (), file, FALSE);
15045 macho_branch_islands ();
15046 /* Mach-O doesn't support labels at the end of objects, so if
15047 it looks like we might want one, insert a NOP. */
15049 rtx insn = get_last_insn ();
15052 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15053 insn = PREV_INSN (insn);
15057 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15058 fputs ("\tnop\n", file);
15062 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15065 We don't output a traceback table if -finhibit-size-directive was
15066 used. The documentation for -finhibit-size-directive reads
15067 ``don't output a @code{.size} assembler directive, or anything
15068 else that would cause trouble if the function is split in the
15069 middle, and the two halves are placed at locations far apart in
15070 memory.'' The traceback table has this property, since it
15071 includes the offset from the start of the function to the
15072 traceback table itself.
15074 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15075 different traceback table. */
15076 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15077 && rs6000_traceback != traceback_none)
15079 const char *fname = NULL;
15080 const char *language_string = lang_hooks.name;
15081 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15083 int optional_tbtab;
15085 if (rs6000_traceback == traceback_full)
15086 optional_tbtab = 1;
15087 else if (rs6000_traceback == traceback_part)
15088 optional_tbtab = 0;
15090 optional_tbtab = !optimize_size && !TARGET_ELF;
15092 if (optional_tbtab)
15094 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15095 while (*fname == '.') /* V.4 encodes . in the name */
15098 /* Need label immediately before tbtab, so we can compute
15099 its offset from the function start. */
15100 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15101 ASM_OUTPUT_LABEL (file, fname);
15104 /* The .tbtab pseudo-op can only be used for the first eight
15105 expressions, since it can't handle the possibly variable
15106 length fields that follow. However, if you omit the optional
15107 fields, the assembler outputs zeros for all optional fields
15108 anyways, giving each variable length field is minimum length
15109 (as defined in sys/debug.h). Thus we can not use the .tbtab
15110 pseudo-op at all. */
15112 /* An all-zero word flags the start of the tbtab, for debuggers
15113 that have to find it by searching forward from the entry
15114 point or from the current pc. */
15115 fputs ("\t.long 0\n", file);
15117 /* Tbtab format type. Use format type 0. */
15118 fputs ("\t.byte 0,", file);
15120 /* Language type. Unfortunately, there does not seem to be any
15121 official way to discover the language being compiled, so we
15122 use language_string.
15123 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15124 Java is 13. Objective-C is 14. */
15125 if (! strcmp (language_string, "GNU C"))
15127 else if (! strcmp (language_string, "GNU F77")
15128 || ! strcmp (language_string, "GNU F95"))
15130 else if (! strcmp (language_string, "GNU Pascal"))
15132 else if (! strcmp (language_string, "GNU Ada"))
15134 else if (! strcmp (language_string, "GNU C++"))
15136 else if (! strcmp (language_string, "GNU Java"))
15138 else if (! strcmp (language_string, "GNU Objective-C"))
15141 gcc_unreachable ();
15142 fprintf (file, "%d,", i);
15144 /* 8 single bit fields: global linkage (not set for C extern linkage,
15145 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15146 from start of procedure stored in tbtab, internal function, function
15147 has controlled storage, function has no toc, function uses fp,
15148 function logs/aborts fp operations. */
15149 /* Assume that fp operations are used if any fp reg must be saved. */
15150 fprintf (file, "%d,",
15151 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15153 /* 6 bitfields: function is interrupt handler, name present in
15154 proc table, function calls alloca, on condition directives
15155 (controls stack walks, 3 bits), saves condition reg, saves
15157 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15158 set up as a frame pointer, even when there is no alloca call. */
15159 fprintf (file, "%d,",
15160 ((optional_tbtab << 6)
15161 | ((optional_tbtab & frame_pointer_needed) << 5)
15162 | (info->cr_save_p << 1)
15163 | (info->lr_save_p)));
15165 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15167 fprintf (file, "%d,",
15168 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15170 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15171 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15173 if (optional_tbtab)
15175 /* Compute the parameter info from the function decl argument
15178 int next_parm_info_bit = 31;
15180 for (decl = DECL_ARGUMENTS (current_function_decl);
15181 decl; decl = TREE_CHAIN (decl))
15183 rtx parameter = DECL_INCOMING_RTL (decl);
15184 enum machine_mode mode = GET_MODE (parameter);
15186 if (GET_CODE (parameter) == REG)
15188 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15206 gcc_unreachable ();
15209 /* If only one bit will fit, don't or in this entry. */
15210 if (next_parm_info_bit > 0)
15211 parm_info |= (bits << (next_parm_info_bit - 1));
15212 next_parm_info_bit -= 2;
15216 fixed_parms += ((GET_MODE_SIZE (mode)
15217 + (UNITS_PER_WORD - 1))
15219 next_parm_info_bit -= 1;
15225 /* Number of fixed point parameters. */
15226 /* This is actually the number of words of fixed point parameters; thus
15227 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15228 fprintf (file, "%d,", fixed_parms);
15230 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15232 /* This is actually the number of fp registers that hold parameters;
15233 and thus the maximum value is 13. */
15234 /* Set parameters on stack bit if parameters are not in their original
15235 registers, regardless of whether they are on the stack? Xlc
15236 seems to set the bit when not optimizing. */
15237 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15239 if (! optional_tbtab)
15242 /* Optional fields follow. Some are variable length. */
15244 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15245 11 double float. */
15246 /* There is an entry for each parameter in a register, in the order that
15247 they occur in the parameter list. Any intervening arguments on the
15248 stack are ignored. If the list overflows a long (max possible length
15249 34 bits) then completely leave off all elements that don't fit. */
15250 /* Only emit this long if there was at least one parameter. */
15251 if (fixed_parms || float_parms)
15252 fprintf (file, "\t.long %d\n", parm_info);
15254 /* Offset from start of code to tb table. */
15255 fputs ("\t.long ", file);
15256 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15258 RS6000_OUTPUT_BASENAME (file, fname);
15260 assemble_name (file, fname);
15262 rs6000_output_function_entry (file, fname);
15265 /* Interrupt handler mask. */
15266 /* Omit this long, since we never set the interrupt handler bit
15269 /* Number of CTL (controlled storage) anchors. */
15270 /* Omit this long, since the has_ctl bit is never set above. */
15272 /* Displacement into stack of each CTL anchor. */
15273 /* Omit this list of longs, because there are no CTL anchors. */
15275 /* Length of function name. */
15278 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15280 /* Function name. */
15281 assemble_string (fname, strlen (fname));
15283 /* Register for alloca automatic storage; this is always reg 31.
15284 Only emit this if the alloca bit was set above. */
15285 if (frame_pointer_needed)
15286 fputs ("\t.byte 31\n", file);
15288 fputs ("\t.align 2\n", file);
15292 /* A C compound statement that outputs the assembler code for a thunk
15293 function, used to implement C++ virtual function calls with
15294 multiple inheritance. The thunk acts as a wrapper around a virtual
15295 function, adjusting the implicit object parameter before handing
15296 control off to the real function.
15298 First, emit code to add the integer DELTA to the location that
15299 contains the incoming first argument. Assume that this argument
15300 contains a pointer, and is the one used to pass the `this' pointer
15301 in C++. This is the incoming argument *before* the function
15302 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15303 values of all other incoming arguments.
15305 After the addition, emit code to jump to FUNCTION, which is a
15306 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15307 not touch the return address. Hence returning from FUNCTION will
15308 return to whoever called the current `thunk'.
15310 The effect must be as if FUNCTION had been called directly with the
15311 adjusted first argument. This macro is responsible for emitting
15312 all of the code for a thunk function; output_function_prologue()
15313 and output_function_epilogue() are not invoked.
15315 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15316 been extracted from it.) It might possibly be useful on some
15317 targets, but probably not.
15319 If you do not define this macro, the target-independent code in the
15320 C++ frontend will generate a less efficient heavyweight thunk that
15321 calls FUNCTION instead of jumping to it. The generic approach does
15322 not support varargs. */
15325 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15326 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15329 rtx this, insn, funexp;
15331 reload_completed = 1;
15332 epilogue_completed = 1;
15333 no_new_pseudos = 1;
15334 reset_block_changes ();
15336 /* Mark the end of the (empty) prologue. */
15337 emit_note (NOTE_INSN_PROLOGUE_END);
15339 /* Find the "this" pointer. If the function returns a structure,
15340 the structure return pointer is in r3. */
15341 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15342 this = gen_rtx_REG (Pmode, 4);
15344 this = gen_rtx_REG (Pmode, 3);
15346 /* Apply the constant offset, if required. */
15349 rtx delta_rtx = GEN_INT (delta);
15350 emit_insn (TARGET_32BIT
15351 ? gen_addsi3 (this, this, delta_rtx)
15352 : gen_adddi3 (this, this, delta_rtx));
15355 /* Apply the offset from the vtable, if required. */
15358 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15359 rtx tmp = gen_rtx_REG (Pmode, 12);
15361 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15362 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15364 emit_insn (TARGET_32BIT
15365 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15366 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15367 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15371 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15373 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15375 emit_insn (TARGET_32BIT
15376 ? gen_addsi3 (this, this, tmp)
15377 : gen_adddi3 (this, this, tmp));
15380 /* Generate a tail call to the target function. */
15381 if (!TREE_USED (function))
15383 assemble_external (function);
15384 TREE_USED (function) = 1;
15386 funexp = XEXP (DECL_RTL (function), 0);
15387 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15390 if (MACHOPIC_INDIRECT)
15391 funexp = machopic_indirect_call_target (funexp);
15394 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15395 generate sibcall RTL explicitly. */
15396 insn = emit_call_insn (
15397 gen_rtx_PARALLEL (VOIDmode,
15399 gen_rtx_CALL (VOIDmode,
15400 funexp, const0_rtx),
15401 gen_rtx_USE (VOIDmode, const0_rtx),
15402 gen_rtx_USE (VOIDmode,
15403 gen_rtx_REG (SImode,
15404 LINK_REGISTER_REGNUM)),
15405 gen_rtx_RETURN (VOIDmode))));
15406 SIBLING_CALL_P (insn) = 1;
15409 /* Run just enough of rest_of_compilation to get the insns emitted.
15410 There's not really enough bulk here to make other passes such as
15411 instruction scheduling worth while. Note that use_thunk calls
15412 assemble_start_function and assemble_end_function. */
15413 insn = get_insns ();
15414 insn_locators_initialize ();
15415 shorten_branches (insn);
15416 final_start_function (insn, file, 1);
15417 final (insn, file, 1);
15418 final_end_function ();
15420 reload_completed = 0;
15421 epilogue_completed = 0;
15422 no_new_pseudos = 0;
15425 /* A quick summary of the various types of 'constant-pool tables'
15428 Target Flags Name One table per
15429 AIX (none) AIX TOC object file
15430 AIX -mfull-toc AIX TOC object file
15431 AIX -mminimal-toc AIX minimal TOC translation unit
15432 SVR4/EABI (none) SVR4 SDATA object file
15433 SVR4/EABI -fpic SVR4 pic object file
15434 SVR4/EABI -fPIC SVR4 PIC translation unit
15435 SVR4/EABI -mrelocatable EABI TOC function
15436 SVR4/EABI -maix AIX TOC object file
15437 SVR4/EABI -maix -mminimal-toc
15438 AIX minimal TOC translation unit
15440 Name Reg. Set by entries contains:
15441 made by addrs? fp? sum?
15443 AIX TOC 2 crt0 as Y option option
15444 AIX minimal TOC 30 prolog gcc Y Y option
15445 SVR4 SDATA 13 crt0 gcc N Y N
15446 SVR4 pic 30 prolog ld Y not yet N
15447 SVR4 PIC 30 prolog gcc Y option option
15448 EABI TOC 30 prolog gcc Y option option
15452 /* Hash functions for the hash table. */
15455 rs6000_hash_constant (rtx k)
15457 enum rtx_code code = GET_CODE (k);
15458 enum machine_mode mode = GET_MODE (k);
15459 unsigned result = (code << 3) ^ mode;
15460 const char *format;
15463 format = GET_RTX_FORMAT (code);
15464 flen = strlen (format);
15470 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15473 if (mode != VOIDmode)
15474 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15486 for (; fidx < flen; fidx++)
15487 switch (format[fidx])
15492 const char *str = XSTR (k, fidx);
15493 len = strlen (str);
15494 result = result * 613 + len;
15495 for (i = 0; i < len; i++)
15496 result = result * 613 + (unsigned) str[i];
15501 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15505 result = result * 613 + (unsigned) XINT (k, fidx);
15508 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15509 result = result * 613 + (unsigned) XWINT (k, fidx);
15513 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15514 result = result * 613 + (unsigned) (XWINT (k, fidx)
15521 gcc_unreachable ();
15528 toc_hash_function (const void *hash_entry)
15530 const struct toc_hash_struct *thc =
15531 (const struct toc_hash_struct *) hash_entry;
15532 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15535 /* Compare H1 and H2 for equivalence. */
15538 toc_hash_eq (const void *h1, const void *h2)
15540 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15541 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15543 if (((const struct toc_hash_struct *) h1)->key_mode
15544 != ((const struct toc_hash_struct *) h2)->key_mode)
15547 return rtx_equal_p (r1, r2);
15550 /* These are the names given by the C++ front-end to vtables, and
15551 vtable-like objects. Ideally, this logic should not be here;
15552 instead, there should be some programmatic way of inquiring as
15553 to whether or not an object is a vtable. */
15555 #define VTABLE_NAME_P(NAME) \
15556 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15557 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15558 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15559 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15560 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15563 rs6000_output_symbol_ref (FILE *file, rtx x)
15565 /* Currently C++ toc references to vtables can be emitted before it
15566 is decided whether the vtable is public or private. If this is
15567 the case, then the linker will eventually complain that there is
15568 a reference to an unknown section. Thus, for vtables only,
15569 we emit the TOC reference to reference the symbol and not the
15571 const char *name = XSTR (x, 0);
15573 if (VTABLE_NAME_P (name))
15575 RS6000_OUTPUT_BASENAME (file, name);
15578 assemble_name (file, name);
15581 /* Output a TOC entry. We derive the entry name from what is being
15585 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15588 const char *name = buf;
15589 const char *real_name;
15593 gcc_assert (!TARGET_NO_TOC);
15595 /* When the linker won't eliminate them, don't output duplicate
15596 TOC entries (this happens on AIX if there is any kind of TOC,
15597 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15599 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15601 struct toc_hash_struct *h;
15604 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15605 time because GGC is not initialized at that point. */
15606 if (toc_hash_table == NULL)
15607 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15608 toc_hash_eq, NULL);
15610 h = ggc_alloc (sizeof (*h));
15612 h->key_mode = mode;
15613 h->labelno = labelno;
15615 found = htab_find_slot (toc_hash_table, h, 1);
15616 if (*found == NULL)
15618 else /* This is indeed a duplicate.
15619 Set this label equal to that label. */
15621 fputs ("\t.set ", file);
15622 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15623 fprintf (file, "%d,", labelno);
15624 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15625 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15631 /* If we're going to put a double constant in the TOC, make sure it's
15632 aligned properly when strict alignment is on. */
15633 if (GET_CODE (x) == CONST_DOUBLE
15634 && STRICT_ALIGNMENT
15635 && GET_MODE_BITSIZE (mode) >= 64
15636 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15637 ASM_OUTPUT_ALIGN (file, 3);
15640 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15642 /* Handle FP constants specially. Note that if we have a minimal
15643 TOC, things we put here aren't actually in the TOC, so we can allow
15645 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15647 REAL_VALUE_TYPE rv;
15650 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15651 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15655 if (TARGET_MINIMAL_TOC)
15656 fputs (DOUBLE_INT_ASM_OP, file);
15658 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15659 k[0] & 0xffffffff, k[1] & 0xffffffff,
15660 k[2] & 0xffffffff, k[3] & 0xffffffff);
15661 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15662 k[0] & 0xffffffff, k[1] & 0xffffffff,
15663 k[2] & 0xffffffff, k[3] & 0xffffffff);
15668 if (TARGET_MINIMAL_TOC)
15669 fputs ("\t.long ", file);
15671 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15672 k[0] & 0xffffffff, k[1] & 0xffffffff,
15673 k[2] & 0xffffffff, k[3] & 0xffffffff);
15674 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15675 k[0] & 0xffffffff, k[1] & 0xffffffff,
15676 k[2] & 0xffffffff, k[3] & 0xffffffff);
15680 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15682 REAL_VALUE_TYPE rv;
15685 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15686 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15690 if (TARGET_MINIMAL_TOC)
15691 fputs (DOUBLE_INT_ASM_OP, file);
15693 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15694 k[0] & 0xffffffff, k[1] & 0xffffffff);
15695 fprintf (file, "0x%lx%08lx\n",
15696 k[0] & 0xffffffff, k[1] & 0xffffffff);
15701 if (TARGET_MINIMAL_TOC)
15702 fputs ("\t.long ", file);
15704 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15705 k[0] & 0xffffffff, k[1] & 0xffffffff);
15706 fprintf (file, "0x%lx,0x%lx\n",
15707 k[0] & 0xffffffff, k[1] & 0xffffffff);
15711 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15713 REAL_VALUE_TYPE rv;
15716 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15717 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15721 if (TARGET_MINIMAL_TOC)
15722 fputs (DOUBLE_INT_ASM_OP, file);
15724 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15725 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15730 if (TARGET_MINIMAL_TOC)
15731 fputs ("\t.long ", file);
15733 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15734 fprintf (file, "0x%lx\n", l & 0xffffffff);
15738 else if (GET_MODE (x) == VOIDmode
15739 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15741 unsigned HOST_WIDE_INT low;
15742 HOST_WIDE_INT high;
15744 if (GET_CODE (x) == CONST_DOUBLE)
15746 low = CONST_DOUBLE_LOW (x);
15747 high = CONST_DOUBLE_HIGH (x);
15750 #if HOST_BITS_PER_WIDE_INT == 32
15753 high = (low & 0x80000000) ? ~0 : 0;
15757 low = INTVAL (x) & 0xffffffff;
15758 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15762 /* TOC entries are always Pmode-sized, but since this
15763 is a bigendian machine then if we're putting smaller
15764 integer constants in the TOC we have to pad them.
15765 (This is still a win over putting the constants in
15766 a separate constant pool, because then we'd have
15767 to have both a TOC entry _and_ the actual constant.)
15769 For a 32-bit target, CONST_INT values are loaded and shifted
15770 entirely within `low' and can be stored in one TOC entry. */
15772 /* It would be easy to make this work, but it doesn't now. */
15773 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15775 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15777 #if HOST_BITS_PER_WIDE_INT == 32
15778 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15779 POINTER_SIZE, &low, &high, 0);
15782 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15783 high = (HOST_WIDE_INT) low >> 32;
15790 if (TARGET_MINIMAL_TOC)
15791 fputs (DOUBLE_INT_ASM_OP, file);
15793 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15794 (long) high & 0xffffffff, (long) low & 0xffffffff);
15795 fprintf (file, "0x%lx%08lx\n",
15796 (long) high & 0xffffffff, (long) low & 0xffffffff);
15801 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15803 if (TARGET_MINIMAL_TOC)
15804 fputs ("\t.long ", file);
15806 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15807 (long) high & 0xffffffff, (long) low & 0xffffffff);
15808 fprintf (file, "0x%lx,0x%lx\n",
15809 (long) high & 0xffffffff, (long) low & 0xffffffff);
15813 if (TARGET_MINIMAL_TOC)
15814 fputs ("\t.long ", file);
15816 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15817 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15823 if (GET_CODE (x) == CONST)
15825 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15827 base = XEXP (XEXP (x, 0), 0);
15828 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15831 switch (GET_CODE (base))
15834 name = XSTR (base, 0);
15838 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15839 CODE_LABEL_NUMBER (XEXP (base, 0)));
15843 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15847 gcc_unreachable ();
15850 real_name = (*targetm.strip_name_encoding) (name);
15851 if (TARGET_MINIMAL_TOC)
15852 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15855 fprintf (file, "\t.tc %s", real_name);
15858 fprintf (file, ".N%d", - offset);
15860 fprintf (file, ".P%d", offset);
15862 fputs ("[TC],", file);
15865 /* Currently C++ toc references to vtables can be emitted before it
15866 is decided whether the vtable is public or private. If this is
15867 the case, then the linker will eventually complain that there is
15868 a TOC reference to an unknown section. Thus, for vtables only,
15869 we emit the TOC reference to reference the symbol and not the
15871 if (VTABLE_NAME_P (name))
15873 RS6000_OUTPUT_BASENAME (file, name);
15875 fprintf (file, "%d", offset);
15876 else if (offset > 0)
15877 fprintf (file, "+%d", offset);
15880 output_addr_const (file, x);
15884 /* Output an assembler pseudo-op to write an ASCII string of N characters
15885 starting at P to FILE.
15887 On the RS/6000, we have to do this using the .byte operation and
15888 write out special characters outside the quoted string.
15889 Also, the assembler is broken; very long strings are truncated,
15890 so we must artificially break them up early. */
15893 output_ascii (FILE *file, const char *p, int n)
15896 int i, count_string;
15897 const char *for_string = "\t.byte \"";
15898 const char *for_decimal = "\t.byte ";
15899 const char *to_close = NULL;
15902 for (i = 0; i < n; i++)
15905 if (c >= ' ' && c < 0177)
15908 fputs (for_string, file);
15911 /* Write two quotes to get one. */
15919 for_decimal = "\"\n\t.byte ";
15923 if (count_string >= 512)
15925 fputs (to_close, file);
15927 for_string = "\t.byte \"";
15928 for_decimal = "\t.byte ";
15936 fputs (for_decimal, file);
15937 fprintf (file, "%d", c);
15939 for_string = "\n\t.byte \"";
15940 for_decimal = ", ";
15946 /* Now close the string if we have written one. Then end the line. */
15948 fputs (to_close, file);
15951 /* Generate a unique section name for FILENAME for a section type
15952 represented by SECTION_DESC. Output goes into BUF.
15954 SECTION_DESC can be any string, as long as it is different for each
15955 possible section type.
15957 We name the section in the same manner as xlc. The name begins with an
15958 underscore followed by the filename (after stripping any leading directory
15959 names) with the last period replaced by the string SECTION_DESC. If
15960 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15964 rs6000_gen_section_name (char **buf, const char *filename,
15965 const char *section_desc)
15967 const char *q, *after_last_slash, *last_period = 0;
15971 after_last_slash = filename;
15972 for (q = filename; *q; q++)
15975 after_last_slash = q + 1;
15976 else if (*q == '.')
15980 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15981 *buf = (char *) xmalloc (len);
15986 for (q = after_last_slash; *q; q++)
15988 if (q == last_period)
15990 strcpy (p, section_desc);
15991 p += strlen (section_desc);
15995 else if (ISALNUM (*q))
15999 if (last_period == 0)
16000 strcpy (p, section_desc);
16005 /* Emit profile function. */
16008 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16010 /* Non-standard profiling for kernels, which just saves LR then calls
16011 _mcount without worrying about arg saves. The idea is to change
16012 the function prologue as little as possible as it isn't easy to
16013 account for arg save/restore code added just for _mcount. */
16014 if (TARGET_PROFILE_KERNEL)
16017 if (DEFAULT_ABI == ABI_AIX)
16019 #ifndef NO_PROFILE_COUNTERS
16020 # define NO_PROFILE_COUNTERS 0
16022 if (NO_PROFILE_COUNTERS)
16023 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16027 const char *label_name;
16030 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16031 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16032 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16034 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16038 else if (DEFAULT_ABI == ABI_DARWIN)
16040 const char *mcount_name = RS6000_MCOUNT;
16041 int caller_addr_regno = LINK_REGISTER_REGNUM;
16043 /* Be conservative and always set this, at least for now. */
16044 current_function_uses_pic_offset_table = 1;
16047 /* For PIC code, set up a stub and collect the caller's address
16048 from r0, which is where the prologue puts it. */
16049 if (MACHOPIC_INDIRECT
16050 && current_function_uses_pic_offset_table)
16051 caller_addr_regno = 0;
16053 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16055 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16059 /* Write function profiler code. */
16062 output_function_profiler (FILE *file, int labelno)
16066 switch (DEFAULT_ABI)
16069 gcc_unreachable ();
16074 warning (0, "no profiling of 64-bit code for this ABI");
16077 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16078 fprintf (file, "\tmflr %s\n", reg_names[0]);
16079 if (NO_PROFILE_COUNTERS)
16081 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16082 reg_names[0], reg_names[1]);
16084 else if (TARGET_SECURE_PLT && flag_pic)
16086 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16087 reg_names[0], reg_names[1]);
16088 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16089 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16090 reg_names[12], reg_names[12]);
16091 assemble_name (file, buf);
16092 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16093 assemble_name (file, buf);
16094 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16096 else if (flag_pic == 1)
16098 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16099 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16100 reg_names[0], reg_names[1]);
16101 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16102 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16103 assemble_name (file, buf);
16104 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16106 else if (flag_pic > 1)
16108 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16109 reg_names[0], reg_names[1]);
16110 /* Now, we need to get the address of the label. */
16111 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16112 assemble_name (file, buf);
16113 fputs ("-.\n1:", file);
16114 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16115 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16116 reg_names[0], reg_names[11]);
16117 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16118 reg_names[0], reg_names[0], reg_names[11]);
16122 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16123 assemble_name (file, buf);
16124 fputs ("@ha\n", file);
16125 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16126 reg_names[0], reg_names[1]);
16127 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16128 assemble_name (file, buf);
16129 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16132 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16133 fprintf (file, "\tbl %s%s\n",
16134 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16139 if (!TARGET_PROFILE_KERNEL)
16141 /* Don't do anything, done in output_profile_hook (). */
16145 gcc_assert (!TARGET_32BIT);
16147 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16148 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16150 if (cfun->static_chain_decl != NULL)
16152 asm_fprintf (file, "\tstd %s,24(%s)\n",
16153 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16154 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16155 asm_fprintf (file, "\tld %s,24(%s)\n",
16156 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16159 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16166 /* Power4 load update and store update instructions are cracked into a
16167 load or store and an integer insn which are executed in the same cycle.
16168 Branches have their own dispatch slot which does not count against the
16169 GCC issue rate, but it changes the program flow so there are no other
16170 instructions to issue in this cycle. */
16173 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16174 int verbose ATTRIBUTE_UNUSED,
16175 rtx insn, int more)
16177 if (GET_CODE (PATTERN (insn)) == USE
16178 || GET_CODE (PATTERN (insn)) == CLOBBER)
16181 if (rs6000_sched_groups)
16183 if (is_microcoded_insn (insn))
16185 else if (is_cracked_insn (insn))
16186 return more > 2 ? more - 2 : 0;
16192 /* Adjust the cost of a scheduling dependency. Return the new cost of
16193 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16196 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16198 if (! recog_memoized (insn))
16201 if (REG_NOTE_KIND (link) != 0)
16204 if (REG_NOTE_KIND (link) == 0)
16206 /* Data dependency; DEP_INSN writes a register that INSN reads
16207 some cycles later. */
16209 /* Separate a load from a narrower, dependent store. */
16210 if (rs6000_sched_groups
16211 && GET_CODE (PATTERN (insn)) == SET
16212 && GET_CODE (PATTERN (dep_insn)) == SET
16213 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16214 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16215 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16216 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16219 switch (get_attr_type (insn))
16222 /* Tell the first scheduling pass about the latency between
16223 a mtctr and bctr (and mtlr and br/blr). The first
16224 scheduling pass will not know about this latency since
16225 the mtctr instruction, which has the latency associated
16226 to it, will be generated by reload. */
16227 return TARGET_POWER ? 5 : 4;
16229 /* Leave some extra cycles between a compare and its
16230 dependent branch, to inhibit expensive mispredicts. */
16231 if ((rs6000_cpu_attr == CPU_PPC603
16232 || rs6000_cpu_attr == CPU_PPC604
16233 || rs6000_cpu_attr == CPU_PPC604E
16234 || rs6000_cpu_attr == CPU_PPC620
16235 || rs6000_cpu_attr == CPU_PPC630
16236 || rs6000_cpu_attr == CPU_PPC750
16237 || rs6000_cpu_attr == CPU_PPC7400
16238 || rs6000_cpu_attr == CPU_PPC7450
16239 || rs6000_cpu_attr == CPU_POWER4
16240 || rs6000_cpu_attr == CPU_POWER5)
16241 && recog_memoized (dep_insn)
16242 && (INSN_CODE (dep_insn) >= 0)
16243 && (get_attr_type (dep_insn) == TYPE_CMP
16244 || get_attr_type (dep_insn) == TYPE_COMPARE
16245 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16246 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16247 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16248 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16249 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16250 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16255 /* Fall out to return default cost. */
16261 /* The function returns a true if INSN is microcoded.
16262 Return false otherwise. */
16265 is_microcoded_insn (rtx insn)
16267 if (!insn || !INSN_P (insn)
16268 || GET_CODE (PATTERN (insn)) == USE
16269 || GET_CODE (PATTERN (insn)) == CLOBBER)
16272 if (rs6000_sched_groups)
16274 enum attr_type type = get_attr_type (insn);
16275 if (type == TYPE_LOAD_EXT_U
16276 || type == TYPE_LOAD_EXT_UX
16277 || type == TYPE_LOAD_UX
16278 || type == TYPE_STORE_UX
16279 || type == TYPE_MFCR)
16286 /* The function returns a nonzero value if INSN can be scheduled only
16287 as the first insn in a dispatch group ("dispatch-slot restricted").
16288 In this case, the returned value indicates how many dispatch slots
16289 the insn occupies (at the beginning of the group).
16290 Return 0 otherwise. */
16293 is_dispatch_slot_restricted (rtx insn)
16295 enum attr_type type;
16297 if (!rs6000_sched_groups)
16301 || insn == NULL_RTX
16302 || GET_CODE (insn) == NOTE
16303 || GET_CODE (PATTERN (insn)) == USE
16304 || GET_CODE (PATTERN (insn)) == CLOBBER)
16307 type = get_attr_type (insn);
16314 case TYPE_DELAYED_CR:
16315 case TYPE_CR_LOGICAL:
16328 if (rs6000_cpu == PROCESSOR_POWER5
16329 && is_cracked_insn (insn))
16335 /* The function returns true if INSN is cracked into 2 instructions
16336 by the processor (and therefore occupies 2 issue slots). */
16339 is_cracked_insn (rtx insn)
16341 if (!insn || !INSN_P (insn)
16342 || GET_CODE (PATTERN (insn)) == USE
16343 || GET_CODE (PATTERN (insn)) == CLOBBER)
16346 if (rs6000_sched_groups)
16348 enum attr_type type = get_attr_type (insn);
16349 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16350 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16351 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16352 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16353 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16354 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16355 || type == TYPE_IDIV || type == TYPE_LDIV
16356 || type == TYPE_INSERT_WORD)
16363 /* The function returns true if INSN can be issued only from
16364 the branch slot. */
16367 is_branch_slot_insn (rtx insn)
16369 if (!insn || !INSN_P (insn)
16370 || GET_CODE (PATTERN (insn)) == USE
16371 || GET_CODE (PATTERN (insn)) == CLOBBER)
16374 if (rs6000_sched_groups)
16376 enum attr_type type = get_attr_type (insn);
16377 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16385 /* A C statement (sans semicolon) to update the integer scheduling
16386 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16387 INSN earlier, reduce the priority to execute INSN later. Do not
16388 define this macro if you do not need to adjust the scheduling
16389 priorities of insns. */
16392 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16394 /* On machines (like the 750) which have asymmetric integer units,
16395 where one integer unit can do multiply and divides and the other
16396 can't, reduce the priority of multiply/divide so it is scheduled
16397 before other integer operations. */
16400 if (! INSN_P (insn))
16403 if (GET_CODE (PATTERN (insn)) == USE)
16406 switch (rs6000_cpu_attr) {
16408 switch (get_attr_type (insn))
16415 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16416 priority, priority);
16417 if (priority >= 0 && priority < 0x01000000)
16424 if (is_dispatch_slot_restricted (insn)
16425 && reload_completed
16426 && current_sched_info->sched_max_insns_priority
16427 && rs6000_sched_restricted_insns_priority)
16430 /* Prioritize insns that can be dispatched only in the first
16432 if (rs6000_sched_restricted_insns_priority == 1)
16433 /* Attach highest priority to insn. This means that in
16434 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16435 precede 'priority' (critical path) considerations. */
16436 return current_sched_info->sched_max_insns_priority;
16437 else if (rs6000_sched_restricted_insns_priority == 2)
16438 /* Increase priority of insn by a minimal amount. This means that in
16439 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16440 considerations precede dispatch-slot restriction considerations. */
16441 return (priority + 1);
16447 /* Return how many instructions the machine can issue per cycle. */
16450 rs6000_issue_rate (void)
16452 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16453 if (!reload_completed)
16456 switch (rs6000_cpu_attr) {
16457 case CPU_RIOS1: /* ? */
16459 case CPU_PPC601: /* ? */
16482 /* Return how many instructions to look ahead for better insn
16486 rs6000_use_sched_lookahead (void)
16488 if (rs6000_cpu_attr == CPU_PPC8540)
16493 /* Determine is PAT refers to memory. */
16496 is_mem_ref (rtx pat)
16502 if (GET_CODE (pat) == MEM)
16505 /* Recursively process the pattern. */
16506 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16508 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16511 ret |= is_mem_ref (XEXP (pat, i));
16512 else if (fmt[i] == 'E')
16513 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16514 ret |= is_mem_ref (XVECEXP (pat, i, j));
16520 /* Determine if PAT is a PATTERN of a load insn. */
16523 is_load_insn1 (rtx pat)
16525 if (!pat || pat == NULL_RTX)
16528 if (GET_CODE (pat) == SET)
16529 return is_mem_ref (SET_SRC (pat));
16531 if (GET_CODE (pat) == PARALLEL)
16535 for (i = 0; i < XVECLEN (pat, 0); i++)
16536 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16543 /* Determine if INSN loads from memory. */
16546 is_load_insn (rtx insn)
16548 if (!insn || !INSN_P (insn))
16551 if (GET_CODE (insn) == CALL_INSN)
16554 return is_load_insn1 (PATTERN (insn));
16557 /* Determine if PAT is a PATTERN of a store insn. */
16560 is_store_insn1 (rtx pat)
16562 if (!pat || pat == NULL_RTX)
16565 if (GET_CODE (pat) == SET)
16566 return is_mem_ref (SET_DEST (pat));
16568 if (GET_CODE (pat) == PARALLEL)
16572 for (i = 0; i < XVECLEN (pat, 0); i++)
16573 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16580 /* Determine if INSN stores to memory. */
16583 is_store_insn (rtx insn)
16585 if (!insn || !INSN_P (insn))
16588 return is_store_insn1 (PATTERN (insn));
16591 /* Returns whether the dependence between INSN and NEXT is considered
16592 costly by the given target. */
16595 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16598 /* If the flag is not enabled - no dependence is considered costly;
16599 allow all dependent insns in the same group.
16600 This is the most aggressive option. */
16601 if (rs6000_sched_costly_dep == no_dep_costly)
16604 /* If the flag is set to 1 - a dependence is always considered costly;
16605 do not allow dependent instructions in the same group.
16606 This is the most conservative option. */
16607 if (rs6000_sched_costly_dep == all_deps_costly)
16610 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16611 && is_load_insn (next)
16612 && is_store_insn (insn))
16613 /* Prevent load after store in the same group. */
16616 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16617 && is_load_insn (next)
16618 && is_store_insn (insn)
16619 && (!link || (int) REG_NOTE_KIND (link) == 0))
16620 /* Prevent load after store in the same group if it is a true
16624 /* The flag is set to X; dependences with latency >= X are considered costly,
16625 and will not be scheduled in the same group. */
16626 if (rs6000_sched_costly_dep <= max_dep_latency
16627 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16633 /* Return the next insn after INSN that is found before TAIL is reached,
16634 skipping any "non-active" insns - insns that will not actually occupy
16635 an issue slot. Return NULL_RTX if such an insn is not found. */
16638 get_next_active_insn (rtx insn, rtx tail)
16640 if (insn == NULL_RTX || insn == tail)
16645 insn = NEXT_INSN (insn);
16646 if (insn == NULL_RTX || insn == tail)
16651 || (NONJUMP_INSN_P (insn)
16652 && GET_CODE (PATTERN (insn)) != USE
16653 && GET_CODE (PATTERN (insn)) != CLOBBER
16654 && INSN_CODE (insn) != CODE_FOR_stack_tie))
16660 /* Return whether the presence of INSN causes a dispatch group termination
16661 of group WHICH_GROUP.
16663 If WHICH_GROUP == current_group, this function will return true if INSN
16664 causes the termination of the current group (i.e, the dispatch group to
16665 which INSN belongs). This means that INSN will be the last insn in the
16666 group it belongs to.
16668 If WHICH_GROUP == previous_group, this function will return true if INSN
16669 causes the termination of the previous group (i.e, the dispatch group that
16670 precedes the group to which INSN belongs). This means that INSN will be
16671 the first insn in the group it belongs to). */
16674 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16676 enum attr_type type;
16681 type = get_attr_type (insn);
16683 if (is_microcoded_insn (insn))
16686 if (which_group == current_group)
16688 if (is_branch_slot_insn (insn))
16692 else if (which_group == previous_group)
16694 if (is_dispatch_slot_restricted (insn))
16702 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16703 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16706 is_costly_group (rtx *group_insns, rtx next_insn)
16711 int issue_rate = rs6000_issue_rate ();
16713 for (i = 0; i < issue_rate; i++)
16715 rtx insn = group_insns[i];
16718 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16720 rtx next = XEXP (link, 0);
16721 if (next == next_insn)
16723 cost = insn_cost (insn, link, next_insn);
16724 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16733 /* Utility of the function redefine_groups.
16734 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16735 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16736 to keep it "far" (in a separate group) from GROUP_INSNS, following
16737 one of the following schemes, depending on the value of the flag
16738 -minsert_sched_nops = X:
16739 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16740 in order to force NEXT_INSN into a separate group.
16741 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16742 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16743 insertion (has a group just ended, how many vacant issue slots remain in the
16744 last group, and how many dispatch groups were encountered so far). */
16747 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16748 rtx next_insn, bool *group_end, int can_issue_more,
16753 int issue_rate = rs6000_issue_rate ();
16754 bool end = *group_end;
16757 if (next_insn == NULL_RTX)
16758 return can_issue_more;
16760 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16761 return can_issue_more;
16763 force = is_costly_group (group_insns, next_insn);
16765 return can_issue_more;
16767 if (sched_verbose > 6)
16768 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16769 *group_count ,can_issue_more);
16771 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16774 can_issue_more = 0;
16776 /* Since only a branch can be issued in the last issue_slot, it is
16777 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16778 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16779 in this case the last nop will start a new group and the branch
16780 will be forced to the new group. */
16781 if (can_issue_more && !is_branch_slot_insn (next_insn))
16784 while (can_issue_more > 0)
16787 emit_insn_before (nop, next_insn);
16795 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16797 int n_nops = rs6000_sched_insert_nops;
16799 /* Nops can't be issued from the branch slot, so the effective
16800 issue_rate for nops is 'issue_rate - 1'. */
16801 if (can_issue_more == 0)
16802 can_issue_more = issue_rate;
16804 if (can_issue_more == 0)
16806 can_issue_more = issue_rate - 1;
16809 for (i = 0; i < issue_rate; i++)
16811 group_insns[i] = 0;
16818 emit_insn_before (nop, next_insn);
16819 if (can_issue_more == issue_rate - 1) /* new group begins */
16822 if (can_issue_more == 0)
16824 can_issue_more = issue_rate - 1;
16827 for (i = 0; i < issue_rate; i++)
16829 group_insns[i] = 0;
16835 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16838 /* Is next_insn going to start a new group? */
16841 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16842 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16843 || (can_issue_more < issue_rate &&
16844 insn_terminates_group_p (next_insn, previous_group)));
16845 if (*group_end && end)
16848 if (sched_verbose > 6)
16849 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16850 *group_count, can_issue_more);
16851 return can_issue_more;
16854 return can_issue_more;
16857 /* This function tries to synch the dispatch groups that the compiler "sees"
16858 with the dispatch groups that the processor dispatcher is expected to
16859 form in practice. It tries to achieve this synchronization by forcing the
16860 estimated processor grouping on the compiler (as opposed to the function
16861 'pad_goups' which tries to force the scheduler's grouping on the processor).
16863 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16864 examines the (estimated) dispatch groups that will be formed by the processor
16865 dispatcher. It marks these group boundaries to reflect the estimated
16866 processor grouping, overriding the grouping that the scheduler had marked.
16867 Depending on the value of the flag '-minsert-sched-nops' this function can
16868 force certain insns into separate groups or force a certain distance between
16869 them by inserting nops, for example, if there exists a "costly dependence"
16872 The function estimates the group boundaries that the processor will form as
16873 follows: It keeps track of how many vacant issue slots are available after
16874 each insn. A subsequent insn will start a new group if one of the following
16876 - no more vacant issue slots remain in the current dispatch group.
16877 - only the last issue slot, which is the branch slot, is vacant, but the next
16878 insn is not a branch.
16879 - only the last 2 or less issue slots, including the branch slot, are vacant,
16880 which means that a cracked insn (which occupies two issue slots) can't be
16881 issued in this group.
16882 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16883 start a new group. */
16886 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16888 rtx insn, next_insn;
16890 int can_issue_more;
16893 int group_count = 0;
16897 issue_rate = rs6000_issue_rate ();
16898 group_insns = alloca (issue_rate * sizeof (rtx));
16899 for (i = 0; i < issue_rate; i++)
16901 group_insns[i] = 0;
16903 can_issue_more = issue_rate;
16905 insn = get_next_active_insn (prev_head_insn, tail);
16908 while (insn != NULL_RTX)
16910 slot = (issue_rate - can_issue_more);
16911 group_insns[slot] = insn;
16913 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16914 if (insn_terminates_group_p (insn, current_group))
16915 can_issue_more = 0;
16917 next_insn = get_next_active_insn (insn, tail);
16918 if (next_insn == NULL_RTX)
16919 return group_count + 1;
16921 /* Is next_insn going to start a new group? */
16923 = (can_issue_more == 0
16924 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16925 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16926 || (can_issue_more < issue_rate &&
16927 insn_terminates_group_p (next_insn, previous_group)));
16929 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16930 next_insn, &group_end, can_issue_more,
16936 can_issue_more = 0;
16937 for (i = 0; i < issue_rate; i++)
16939 group_insns[i] = 0;
16943 if (GET_MODE (next_insn) == TImode && can_issue_more)
16944 PUT_MODE (next_insn, VOIDmode);
16945 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16946 PUT_MODE (next_insn, TImode);
16949 if (can_issue_more == 0)
16950 can_issue_more = issue_rate;
16953 return group_count;
16956 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16957 dispatch group boundaries that the scheduler had marked. Pad with nops
16958 any dispatch groups which have vacant issue slots, in order to force the
16959 scheduler's grouping on the processor dispatcher. The function
16960 returns the number of dispatch groups found. */
16963 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16965 rtx insn, next_insn;
16968 int can_issue_more;
16970 int group_count = 0;
16972 /* Initialize issue_rate. */
16973 issue_rate = rs6000_issue_rate ();
16974 can_issue_more = issue_rate;
16976 insn = get_next_active_insn (prev_head_insn, tail);
16977 next_insn = get_next_active_insn (insn, tail);
16979 while (insn != NULL_RTX)
16982 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16984 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16986 if (next_insn == NULL_RTX)
16991 /* If the scheduler had marked group termination at this location
16992 (between insn and next_indn), and neither insn nor next_insn will
16993 force group termination, pad the group with nops to force group
16996 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16997 && !insn_terminates_group_p (insn, current_group)
16998 && !insn_terminates_group_p (next_insn, previous_group))
17000 if (!is_branch_slot_insn (next_insn))
17003 while (can_issue_more)
17006 emit_insn_before (nop, next_insn);
17011 can_issue_more = issue_rate;
17016 next_insn = get_next_active_insn (insn, tail);
17019 return group_count;
17022 /* The following function is called at the end of scheduling BB.
17023 After reload, it inserts nops at insn group bundling. */
17026 rs6000_sched_finish (FILE *dump, int sched_verbose)
17031 fprintf (dump, "=== Finishing schedule.\n");
17033 if (reload_completed && rs6000_sched_groups)
17035 if (rs6000_sched_insert_nops == sched_finish_none)
17038 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17039 n_groups = pad_groups (dump, sched_verbose,
17040 current_sched_info->prev_head,
17041 current_sched_info->next_tail);
17043 n_groups = redefine_groups (dump, sched_verbose,
17044 current_sched_info->prev_head,
17045 current_sched_info->next_tail);
17047 if (sched_verbose >= 6)
17049 fprintf (dump, "ngroups = %d\n", n_groups);
17050 print_rtl (dump, current_sched_info->prev_head);
17051 fprintf (dump, "Done finish_sched\n");
17056 /* Length in units of the trampoline for entering a nested function. */
17059 rs6000_trampoline_size (void)
17063 switch (DEFAULT_ABI)
17066 gcc_unreachable ();
17069 ret = (TARGET_32BIT) ? 12 : 24;
17074 ret = (TARGET_32BIT) ? 40 : 48;
17081 /* Emit RTL insns to initialize the variable parts of a trampoline.
17082 FNADDR is an RTX for the address of the function's pure code.
17083 CXT is an RTX for the static chain value for the function. */
17086 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17088 enum machine_mode pmode = Pmode;
17089 int regsize = (TARGET_32BIT) ? 4 : 8;
17090 rtx ctx_reg = force_reg (pmode, cxt);
17092 switch (DEFAULT_ABI)
17095 gcc_unreachable ();
17097 /* Macros to shorten the code expansions below. */
17098 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17099 #define MEM_PLUS(addr,offset) \
17100 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17102 /* Under AIX, just build the 3 word function descriptor */
17105 rtx fn_reg = gen_reg_rtx (pmode);
17106 rtx toc_reg = gen_reg_rtx (pmode);
17107 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17108 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17109 emit_move_insn (MEM_DEREF (addr), fn_reg);
17110 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17111 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17115 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17118 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17119 FALSE, VOIDmode, 4,
17121 GEN_INT (rs6000_trampoline_size ()), SImode,
17131 /* Table of valid machine attributes. */
17133 const struct attribute_spec rs6000_attribute_table[] =
17135 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17136 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17137 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17138 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17139 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17140 SUBTARGET_ATTRIBUTE_TABLE,
17142 { NULL, 0, 0, false, false, false, NULL }
17145 /* Handle the "altivec" attribute. The attribute may have
17146 arguments as follows:
17148 __attribute__((altivec(vector__)))
17149 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17150 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17152 and may appear more than once (e.g., 'vector bool char') in a
17153 given declaration. */
17156 rs6000_handle_altivec_attribute (tree *node,
17157 tree name ATTRIBUTE_UNUSED,
17159 int flags ATTRIBUTE_UNUSED,
17160 bool *no_add_attrs)
17162 tree type = *node, result = NULL_TREE;
17163 enum machine_mode mode;
17166 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17167 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17168 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17171 while (POINTER_TYPE_P (type)
17172 || TREE_CODE (type) == FUNCTION_TYPE
17173 || TREE_CODE (type) == METHOD_TYPE
17174 || TREE_CODE (type) == ARRAY_TYPE)
17175 type = TREE_TYPE (type);
17177 mode = TYPE_MODE (type);
17179 /* Check for invalid AltiVec type qualifiers. */
17180 if (type == long_unsigned_type_node || type == long_integer_type_node)
17183 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17184 else if (rs6000_warn_altivec_long)
17185 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17187 else if (type == long_long_unsigned_type_node
17188 || type == long_long_integer_type_node)
17189 error ("use of %<long long%> in AltiVec types is invalid");
17190 else if (type == double_type_node)
17191 error ("use of %<double%> in AltiVec types is invalid");
17192 else if (type == long_double_type_node)
17193 error ("use of %<long double%> in AltiVec types is invalid");
17194 else if (type == boolean_type_node)
17195 error ("use of boolean types in AltiVec types is invalid");
17196 else if (TREE_CODE (type) == COMPLEX_TYPE)
17197 error ("use of %<complex%> in AltiVec types is invalid");
17199 switch (altivec_type)
17202 unsigned_p = TYPE_UNSIGNED (type);
17206 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17209 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17212 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17214 case SFmode: result = V4SF_type_node; break;
17215 /* If the user says 'vector int bool', we may be handed the 'bool'
17216 attribute _before_ the 'vector' attribute, and so select the
17217 proper type in the 'b' case below. */
17218 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17226 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17227 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17228 case QImode: case V16QImode: result = bool_V16QI_type_node;
17235 case V8HImode: result = pixel_V8HI_type_node;
17241 if (result && result != type && TYPE_READONLY (type))
17242 result = build_qualified_type (result, TYPE_QUAL_CONST);
17244 *no_add_attrs = true; /* No need to hang on to the attribute. */
17247 *node = reconstruct_complex_type (*node, result);
17252 /* AltiVec defines four built-in scalar types that serve as vector
17253 elements; we must teach the compiler how to mangle them. */
17255 static const char *
17256 rs6000_mangle_fundamental_type (tree type)
17258 if (type == bool_char_type_node) return "U6__boolc";
17259 if (type == bool_short_type_node) return "U6__bools";
17260 if (type == pixel_type_node) return "u7__pixel";
17261 if (type == bool_int_type_node) return "U6__booli";
17263 /* For all other types, use normal C++ mangling. */
17267 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17268 struct attribute_spec.handler. */
17271 rs6000_handle_longcall_attribute (tree *node, tree name,
17272 tree args ATTRIBUTE_UNUSED,
17273 int flags ATTRIBUTE_UNUSED,
17274 bool *no_add_attrs)
17276 if (TREE_CODE (*node) != FUNCTION_TYPE
17277 && TREE_CODE (*node) != FIELD_DECL
17278 && TREE_CODE (*node) != TYPE_DECL)
17280 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17281 IDENTIFIER_POINTER (name));
17282 *no_add_attrs = true;
17288 /* Set longcall attributes on all functions declared when
17289 rs6000_default_long_calls is true. */
17291 rs6000_set_default_type_attributes (tree type)
17293 if (rs6000_default_long_calls
17294 && (TREE_CODE (type) == FUNCTION_TYPE
17295 || TREE_CODE (type) == METHOD_TYPE))
17296 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17298 TYPE_ATTRIBUTES (type));
17301 /* Return a reference suitable for calling a function with the
17302 longcall attribute. */
17305 rs6000_longcall_ref (rtx call_ref)
17307 const char *call_name;
17310 if (GET_CODE (call_ref) != SYMBOL_REF)
17313 /* System V adds '.' to the internal name, so skip them. */
17314 call_name = XSTR (call_ref, 0);
17315 if (*call_name == '.')
17317 while (*call_name == '.')
17320 node = get_identifier (call_name);
17321 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17324 return force_reg (Pmode, call_ref);
17327 #ifdef USING_ELFOS_H
17329 /* A C statement or statements to switch to the appropriate section
17330 for output of RTX in mode MODE. You can assume that RTX is some
17331 kind of constant in RTL. The argument MODE is redundant except in
17332 the case of a `const_int' rtx. Select the section by calling
17333 `text_section' or one of the alternatives for other sections.
17335 Do not define this macro if you put all constants in the read-only
17339 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17340 unsigned HOST_WIDE_INT align)
17342 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17345 default_elf_select_rtx_section (mode, x, align);
17348 /* A C statement or statements to switch to the appropriate
17349 section for output of DECL. DECL is either a `VAR_DECL' node
17350 or a constant of some sort. RELOC indicates whether forming
17351 the initial value of DECL requires link-time relocations. */
17354 rs6000_elf_select_section (tree decl, int reloc,
17355 unsigned HOST_WIDE_INT align)
17357 /* Pretend that we're always building for a shared library when
17358 ABI_AIX, because otherwise we end up with dynamic relocations
17359 in read-only sections. This happens for function pointers,
17360 references to vtables in typeinfo, and probably other cases. */
17361 default_elf_select_section_1 (decl, reloc, align,
17362 flag_pic || DEFAULT_ABI == ABI_AIX);
17365 /* A C statement to build up a unique section name, expressed as a
17366 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17367 RELOC indicates whether the initial value of EXP requires
17368 link-time relocations. If you do not define this macro, GCC will use
17369 the symbol name prefixed by `.' as the section name. Note - this
17370 macro can now be called for uninitialized data items as well as
17371 initialized data and functions. */
17374 rs6000_elf_unique_section (tree decl, int reloc)
17376 /* As above, pretend that we're always building for a shared library
17377 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17378 default_unique_section_1 (decl, reloc,
17379 flag_pic || DEFAULT_ABI == ABI_AIX);
17382 /* For a SYMBOL_REF, set generic flags and then perform some
17383 target-specific processing.
17385 When the AIX ABI is requested on a non-AIX system, replace the
17386 function name with the real name (with a leading .) rather than the
17387 function descriptor name. This saves a lot of overriding code to
17388 read the prefixes. */
17391 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17393 default_encode_section_info (decl, rtl, first);
17396 && TREE_CODE (decl) == FUNCTION_DECL
17398 && DEFAULT_ABI == ABI_AIX)
17400 rtx sym_ref = XEXP (rtl, 0);
17401 size_t len = strlen (XSTR (sym_ref, 0));
17402 char *str = alloca (len + 2);
17404 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17405 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17410 rs6000_elf_in_small_data_p (tree decl)
17412 if (rs6000_sdata == SDATA_NONE)
17415 /* We want to merge strings, so we never consider them small data. */
17416 if (TREE_CODE (decl) == STRING_CST)
17419 /* Functions are never in the small data area. */
17420 if (TREE_CODE (decl) == FUNCTION_DECL)
17423 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17425 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17426 if (strcmp (section, ".sdata") == 0
17427 || strcmp (section, ".sdata2") == 0
17428 || strcmp (section, ".sbss") == 0
17429 || strcmp (section, ".sbss2") == 0
17430 || strcmp (section, ".PPC.EMB.sdata0") == 0
17431 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17436 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17439 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17440 /* If it's not public, and we're not going to reference it there,
17441 there's no need to put it in the small data section. */
17442 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17449 #endif /* USING_ELFOS_H */
17452 /* Return a REG that occurs in ADDR with coefficient 1.
17453 ADDR can be effectively incremented by incrementing REG.
17455 r0 is special and we must not select it as an address
17456 register by this routine since our caller will try to
17457 increment the returned register via an "la" instruction. */
17460 find_addr_reg (rtx addr)
17462 while (GET_CODE (addr) == PLUS)
17464 if (GET_CODE (XEXP (addr, 0)) == REG
17465 && REGNO (XEXP (addr, 0)) != 0)
17466 addr = XEXP (addr, 0);
17467 else if (GET_CODE (XEXP (addr, 1)) == REG
17468 && REGNO (XEXP (addr, 1)) != 0)
17469 addr = XEXP (addr, 1);
17470 else if (CONSTANT_P (XEXP (addr, 0)))
17471 addr = XEXP (addr, 1);
17472 else if (CONSTANT_P (XEXP (addr, 1)))
17473 addr = XEXP (addr, 0);
17475 gcc_unreachable ();
17477 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17482 rs6000_fatal_bad_address (rtx op)
17484 fatal_insn ("bad address", op);
17489 static tree branch_island_list = 0;
17491 /* Remember to generate a branch island for far calls to the given
17495 add_compiler_branch_island (tree label_name, tree function_name,
17498 tree branch_island = build_tree_list (function_name, label_name);
17499 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17500 TREE_CHAIN (branch_island) = branch_island_list;
17501 branch_island_list = branch_island;
17504 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17505 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17506 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17507 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17509 /* Generate far-jump branch islands for everything on the
17510 branch_island_list. Invoked immediately after the last instruction
17511 of the epilogue has been emitted; the branch-islands must be
17512 appended to, and contiguous with, the function body. Mach-O stubs
17513 are generated in machopic_output_stub(). */
17516 macho_branch_islands (void)
17519 tree branch_island;
17521 for (branch_island = branch_island_list;
17523 branch_island = TREE_CHAIN (branch_island))
17525 const char *label =
17526 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17528 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17529 char name_buf[512];
17530 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17531 if (name[0] == '*' || name[0] == '&')
17532 strcpy (name_buf, name+1);
17536 strcpy (name_buf+1, name);
17538 strcpy (tmp_buf, "\n");
17539 strcat (tmp_buf, label);
17540 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17541 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17542 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17543 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17546 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17547 strcat (tmp_buf, label);
17548 strcat (tmp_buf, "_pic\n");
17549 strcat (tmp_buf, label);
17550 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17552 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17553 strcat (tmp_buf, name_buf);
17554 strcat (tmp_buf, " - ");
17555 strcat (tmp_buf, label);
17556 strcat (tmp_buf, "_pic)\n");
17558 strcat (tmp_buf, "\tmtlr r0\n");
17560 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17561 strcat (tmp_buf, name_buf);
17562 strcat (tmp_buf, " - ");
17563 strcat (tmp_buf, label);
17564 strcat (tmp_buf, "_pic)\n");
17566 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17570 strcat (tmp_buf, ":\nlis r12,hi16(");
17571 strcat (tmp_buf, name_buf);
17572 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17573 strcat (tmp_buf, name_buf);
17574 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17576 output_asm_insn (tmp_buf, 0);
17577 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17578 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17579 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17580 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17583 branch_island_list = 0;
17586 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17587 already there or not. */
17590 no_previous_def (tree function_name)
17592 tree branch_island;
17593 for (branch_island = branch_island_list;
17595 branch_island = TREE_CHAIN (branch_island))
17596 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17601 /* GET_PREV_LABEL gets the label name from the previous definition of
17605 get_prev_label (tree function_name)
17607 tree branch_island;
17608 for (branch_island = branch_island_list;
17610 branch_island = TREE_CHAIN (branch_island))
17611 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17612 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17616 /* INSN is either a function call or a millicode call. It may have an
17617 unconditional jump in its delay slot.
17619 CALL_DEST is the routine we are calling. */
17622 output_call (rtx insn, rtx *operands, int dest_operand_number,
17623 int cookie_operand_number)
17625 static char buf[256];
17626 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17627 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17630 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17632 if (no_previous_def (funname))
17634 int line_number = 0;
17635 rtx label_rtx = gen_label_rtx ();
17636 char *label_buf, temp_buf[256];
17637 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17638 CODE_LABEL_NUMBER (label_rtx));
17639 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17640 labelname = get_identifier (label_buf);
17641 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17643 line_number = NOTE_LINE_NUMBER (insn);
17644 add_compiler_branch_island (labelname, funname, line_number);
17647 labelname = get_prev_label (funname);
17649 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17650 instruction will reach 'foo', otherwise link as 'bl L42'".
17651 "L42" should be a 'branch island', that will do a far jump to
17652 'foo'. Branch islands are generated in
17653 macho_branch_islands(). */
17654 sprintf (buf, "jbsr %%z%d,%.246s",
17655 dest_operand_number, IDENTIFIER_POINTER (labelname));
17658 sprintf (buf, "bl %%z%d", dest_operand_number);
17662 /* Generate PIC and indirect symbol stubs. */
17665 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17667 unsigned int length;
17668 char *symbol_name, *lazy_ptr_name;
17669 char *local_label_0;
17670 static int label = 0;
17672 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17673 symb = (*targetm.strip_name_encoding) (symb);
17676 length = strlen (symb);
17677 symbol_name = alloca (length + 32);
17678 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17680 lazy_ptr_name = alloca (length + 32);
17681 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17684 machopic_picsymbol_stub1_section ();
17686 machopic_symbol_stub1_section ();
17690 fprintf (file, "\t.align 5\n");
17692 fprintf (file, "%s:\n", stub);
17693 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17696 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17697 sprintf (local_label_0, "\"L%011d$spb\"", label);
17699 fprintf (file, "\tmflr r0\n");
17700 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17701 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17702 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17703 lazy_ptr_name, local_label_0);
17704 fprintf (file, "\tmtlr r0\n");
17705 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17706 (TARGET_64BIT ? "ldu" : "lwzu"),
17707 lazy_ptr_name, local_label_0);
17708 fprintf (file, "\tmtctr r12\n");
17709 fprintf (file, "\tbctr\n");
17713 fprintf (file, "\t.align 4\n");
17715 fprintf (file, "%s:\n", stub);
17716 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17718 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17719 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17720 (TARGET_64BIT ? "ldu" : "lwzu"),
17722 fprintf (file, "\tmtctr r12\n");
17723 fprintf (file, "\tbctr\n");
17726 machopic_lazy_symbol_ptr_section ();
17727 fprintf (file, "%s:\n", lazy_ptr_name);
17728 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17729 fprintf (file, "%sdyld_stub_binding_helper\n",
17730 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17733 /* Legitimize PIC addresses. If the address is already
17734 position-independent, we return ORIG. Newly generated
17735 position-independent addresses go into a reg. This is REG if non
17736 zero, otherwise we allocate register(s) as necessary. */
17738 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17741 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17746 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17747 reg = gen_reg_rtx (Pmode);
17749 if (GET_CODE (orig) == CONST)
17753 if (GET_CODE (XEXP (orig, 0)) == PLUS
17754 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17757 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17759 /* Use a different reg for the intermediate value, as
17760 it will be marked UNCHANGING. */
17761 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17762 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17765 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17768 if (GET_CODE (offset) == CONST_INT)
17770 if (SMALL_INT (offset))
17771 return plus_constant (base, INTVAL (offset));
17772 else if (! reload_in_progress && ! reload_completed)
17773 offset = force_reg (Pmode, offset);
17776 rtx mem = force_const_mem (Pmode, orig);
17777 return machopic_legitimize_pic_address (mem, Pmode, reg);
17780 return gen_rtx_PLUS (Pmode, base, offset);
17783 /* Fall back on generic machopic code. */
17784 return machopic_legitimize_pic_address (orig, mode, reg);
17787 /* This is just a placeholder to make linking work without having to
17788 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17789 ever needed for Darwin (not too likely!) this would have to get a
17790 real definition. */
17797 /* Output a .machine directive for the Darwin assembler, and call
17798 the generic start_file routine. */
17801 rs6000_darwin_file_start (void)
17803 static const struct
17809 { "ppc64", "ppc64", MASK_64BIT },
17810 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17811 { "power4", "ppc970", 0 },
17812 { "G5", "ppc970", 0 },
17813 { "7450", "ppc7450", 0 },
17814 { "7400", "ppc7400", MASK_ALTIVEC },
17815 { "G4", "ppc7400", 0 },
17816 { "750", "ppc750", 0 },
17817 { "740", "ppc750", 0 },
17818 { "G3", "ppc750", 0 },
17819 { "604e", "ppc604e", 0 },
17820 { "604", "ppc604", 0 },
17821 { "603e", "ppc603", 0 },
17822 { "603", "ppc603", 0 },
17823 { "601", "ppc601", 0 },
17824 { NULL, "ppc", 0 } };
17825 const char *cpu_id = "";
17828 rs6000_file_start ();
17830 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17831 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17832 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17833 && rs6000_select[i].string[0] != '\0')
17834 cpu_id = rs6000_select[i].string;
17836 /* Look through the mapping array. Pick the first name that either
17837 matches the argument, has a bit set in IF_SET that is also set
17838 in the target flags, or has a NULL name. */
17841 while (mapping[i].arg != NULL
17842 && strcmp (mapping[i].arg, cpu_id) != 0
17843 && (mapping[i].if_set & target_flags) == 0)
17846 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17849 #endif /* TARGET_MACHO */
17852 static unsigned int
17853 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17855 return default_section_type_flags_1 (decl, name, reloc,
17856 flag_pic || DEFAULT_ABI == ABI_AIX);
17859 /* Record an element in the table of global constructors. SYMBOL is
17860 a SYMBOL_REF of the function to be called; PRIORITY is a number
17861 between 0 and MAX_INIT_PRIORITY.
17863 This differs from default_named_section_asm_out_constructor in
17864 that we have special handling for -mrelocatable. */
17867 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17869 const char *section = ".ctors";
17872 if (priority != DEFAULT_INIT_PRIORITY)
17874 sprintf (buf, ".ctors.%.5u",
17875 /* Invert the numbering so the linker puts us in the proper
17876 order; constructors are run from right to left, and the
17877 linker sorts in increasing order. */
17878 MAX_INIT_PRIORITY - priority);
17882 named_section_flags (section, SECTION_WRITE);
17883 assemble_align (POINTER_SIZE);
17885 if (TARGET_RELOCATABLE)
17887 fputs ("\t.long (", asm_out_file);
17888 output_addr_const (asm_out_file, symbol);
17889 fputs (")@fixup\n", asm_out_file);
17892 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17896 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17898 const char *section = ".dtors";
17901 if (priority != DEFAULT_INIT_PRIORITY)
17903 sprintf (buf, ".dtors.%.5u",
17904 /* Invert the numbering so the linker puts us in the proper
17905 order; constructors are run from right to left, and the
17906 linker sorts in increasing order. */
17907 MAX_INIT_PRIORITY - priority);
17911 named_section_flags (section, SECTION_WRITE);
17912 assemble_align (POINTER_SIZE);
17914 if (TARGET_RELOCATABLE)
17916 fputs ("\t.long (", asm_out_file);
17917 output_addr_const (asm_out_file, symbol);
17918 fputs (")@fixup\n", asm_out_file);
17921 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17925 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17929 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17930 ASM_OUTPUT_LABEL (file, name);
17931 fputs (DOUBLE_INT_ASM_OP, file);
17932 rs6000_output_function_entry (file, name);
17933 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17936 fputs ("\t.size\t", file);
17937 assemble_name (file, name);
17938 fputs (",24\n\t.type\t.", file);
17939 assemble_name (file, name);
17940 fputs (",@function\n", file);
17941 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17943 fputs ("\t.globl\t.", file);
17944 assemble_name (file, name);
17949 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17950 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17951 rs6000_output_function_entry (file, name);
17952 fputs (":\n", file);
17956 if (TARGET_RELOCATABLE
17957 && !TARGET_SECURE_PLT
17958 && (get_pool_size () != 0 || current_function_profile)
17963 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17965 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17966 fprintf (file, "\t.long ");
17967 assemble_name (file, buf);
17969 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17970 assemble_name (file, buf);
17974 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17975 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17977 if (DEFAULT_ABI == ABI_AIX)
17979 const char *desc_name, *orig_name;
17981 orig_name = (*targetm.strip_name_encoding) (name);
17982 desc_name = orig_name;
17983 while (*desc_name == '.')
17986 if (TREE_PUBLIC (decl))
17987 fprintf (file, "\t.globl %s\n", desc_name);
17989 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17990 fprintf (file, "%s:\n", desc_name);
17991 fprintf (file, "\t.long %s\n", orig_name);
17992 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17993 if (DEFAULT_ABI == ABI_AIX)
17994 fputs ("\t.long 0\n", file);
17995 fprintf (file, "\t.previous\n");
17997 ASM_OUTPUT_LABEL (file, name);
18001 rs6000_elf_end_indicate_exec_stack (void)
18004 file_end_indicate_exec_stack ();
18010 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18012 fputs (GLOBAL_ASM_OP, stream);
18013 RS6000_OUTPUT_BASENAME (stream, name);
18014 putc ('\n', stream);
18018 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18019 tree decl ATTRIBUTE_UNUSED)
18022 static const char * const suffix[3] = { "PR", "RO", "RW" };
18024 if (flags & SECTION_CODE)
18026 else if (flags & SECTION_WRITE)
18031 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18032 (flags & SECTION_CODE) ? "." : "",
18033 name, suffix[smclass], flags & SECTION_ENTSIZE);
18037 rs6000_xcoff_select_section (tree decl, int reloc,
18038 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18040 if (decl_readonly_section_1 (decl, reloc, 1))
18042 if (TREE_PUBLIC (decl))
18043 read_only_data_section ();
18045 read_only_private_data_section ();
18049 if (TREE_PUBLIC (decl))
18052 private_data_section ();
18057 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18061 /* Use select_section for private and uninitialized data. */
18062 if (!TREE_PUBLIC (decl)
18063 || DECL_COMMON (decl)
18064 || DECL_INITIAL (decl) == NULL_TREE
18065 || DECL_INITIAL (decl) == error_mark_node
18066 || (flag_zero_initialized_in_bss
18067 && initializer_zerop (DECL_INITIAL (decl))))
18070 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18071 name = (*targetm.strip_name_encoding) (name);
18072 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18075 /* Select section for constant in constant pool.
18077 On RS/6000, all constants are in the private read-only data area.
18078 However, if this is being placed in the TOC it must be output as a
18082 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18083 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18085 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18088 read_only_private_data_section ();
18091 /* Remove any trailing [DS] or the like from the symbol name. */
18093 static const char *
18094 rs6000_xcoff_strip_name_encoding (const char *name)
18099 len = strlen (name);
18100 if (name[len - 1] == ']')
18101 return ggc_alloc_string (name, len - 4);
18106 /* Section attributes. AIX is always PIC. */
18108 static unsigned int
18109 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18111 unsigned int align;
18112 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18114 /* Align to at least UNIT size. */
18115 if (flags & SECTION_CODE)
18116 align = MIN_UNITS_PER_WORD;
18118 /* Increase alignment of large objects if not already stricter. */
18119 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18120 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18121 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18123 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18126 /* Output at beginning of assembler file.
18128 Initialize the section names for the RS/6000 at this point.
18130 Specify filename, including full path, to assembler.
18132 We want to go into the TOC section so at least one .toc will be emitted.
18133 Also, in order to output proper .bs/.es pairs, we need at least one static
18134 [RW] section emitted.
18136 Finally, declare mcount when profiling to make the assembler happy. */
18139 rs6000_xcoff_file_start (void)
18141 rs6000_gen_section_name (&xcoff_bss_section_name,
18142 main_input_filename, ".bss_");
18143 rs6000_gen_section_name (&xcoff_private_data_section_name,
18144 main_input_filename, ".rw_");
18145 rs6000_gen_section_name (&xcoff_read_only_section_name,
18146 main_input_filename, ".ro_");
18148 fputs ("\t.file\t", asm_out_file);
18149 output_quoted_string (asm_out_file, main_input_filename);
18150 fputc ('\n', asm_out_file);
18151 if (write_symbols != NO_DEBUG)
18152 private_data_section ();
18155 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18156 rs6000_file_start ();
18159 /* Output at end of assembler file.
18160 On the RS/6000, referencing data should automatically pull in text. */
18163 rs6000_xcoff_file_end (void)
18166 fputs ("_section_.text:\n", asm_out_file);
18168 fputs (TARGET_32BIT
18169 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18172 #endif /* TARGET_XCOFF */
18174 /* Compute a (partial) cost for rtx X. Return true if the complete
18175 cost has been computed, and false if subexpressions should be
18176 scanned. In either case, *TOTAL contains the cost result. */
18179 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18181 enum machine_mode mode = GET_MODE (x);
18185 /* On the RS/6000, if it is valid in the insn, it is free. */
18187 if (((outer_code == SET
18188 || outer_code == PLUS
18189 || outer_code == MINUS)
18190 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18191 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18192 || (outer_code == AND
18193 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18194 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18195 mode == SImode ? 'L' : 'J'))
18196 || mask_operand (x, mode)
18198 && mask64_operand (x, DImode))))
18199 || ((outer_code == IOR || outer_code == XOR)
18200 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18201 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18202 mode == SImode ? 'L' : 'J'))))
18203 || outer_code == ASHIFT
18204 || outer_code == ASHIFTRT
18205 || outer_code == LSHIFTRT
18206 || outer_code == ROTATE
18207 || outer_code == ROTATERT
18208 || outer_code == ZERO_EXTRACT
18209 || (outer_code == MULT
18210 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18211 || ((outer_code == DIV || outer_code == UDIV
18212 || outer_code == MOD || outer_code == UMOD)
18213 && exact_log2 (INTVAL (x)) >= 0)
18214 || (outer_code == COMPARE
18215 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18216 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18217 || (outer_code == EQ
18218 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18219 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18220 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18221 mode == SImode ? 'L' : 'J'))))
18222 || (outer_code == GTU
18223 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18224 || (outer_code == LTU
18225 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18230 else if ((outer_code == PLUS
18231 && reg_or_add_cint_operand (x, VOIDmode))
18232 || (outer_code == MINUS
18233 && reg_or_sub_cint_operand (x, VOIDmode))
18234 || ((outer_code == SET
18235 || outer_code == IOR
18236 || outer_code == XOR)
18238 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18240 *total = COSTS_N_INSNS (1);
18247 && ((outer_code == AND
18248 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18249 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18250 || mask_operand (x, DImode)
18251 || mask64_operand (x, DImode)))
18252 || ((outer_code == IOR || outer_code == XOR)
18253 && CONST_DOUBLE_HIGH (x) == 0
18254 && (CONST_DOUBLE_LOW (x)
18255 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18260 else if (mode == DImode
18261 && (outer_code == SET
18262 || outer_code == IOR
18263 || outer_code == XOR)
18264 && CONST_DOUBLE_HIGH (x) == 0)
18266 *total = COSTS_N_INSNS (1);
18275 /* When optimizing for size, MEM should be slightly more expensive
18276 than generating address, e.g., (plus (reg) (const)).
18277 L1 cache latency is about two instructions. */
18278 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18286 if (mode == DFmode)
18288 if (GET_CODE (XEXP (x, 0)) == MULT)
18290 /* FNMA accounted in outer NEG. */
18291 if (outer_code == NEG)
18292 *total = rs6000_cost->dmul - rs6000_cost->fp;
18294 *total = rs6000_cost->dmul;
18297 *total = rs6000_cost->fp;
18299 else if (mode == SFmode)
18301 /* FNMA accounted in outer NEG. */
18302 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18305 *total = rs6000_cost->fp;
18308 *total = COSTS_N_INSNS (1);
18312 if (mode == DFmode)
18314 if (GET_CODE (XEXP (x, 0)) == MULT)
18316 /* FNMA accounted in outer NEG. */
18317 if (outer_code == NEG)
18320 *total = rs6000_cost->dmul;
18323 *total = rs6000_cost->fp;
18325 else if (mode == SFmode)
18327 /* FNMA accounted in outer NEG. */
18328 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18331 *total = rs6000_cost->fp;
18334 *total = COSTS_N_INSNS (1);
18338 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18339 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18341 if (INTVAL (XEXP (x, 1)) >= -256
18342 && INTVAL (XEXP (x, 1)) <= 255)
18343 *total = rs6000_cost->mulsi_const9;
18345 *total = rs6000_cost->mulsi_const;
18347 /* FMA accounted in outer PLUS/MINUS. */
18348 else if ((mode == DFmode || mode == SFmode)
18349 && (outer_code == PLUS || outer_code == MINUS))
18351 else if (mode == DFmode)
18352 *total = rs6000_cost->dmul;
18353 else if (mode == SFmode)
18354 *total = rs6000_cost->fp;
18355 else if (mode == DImode)
18356 *total = rs6000_cost->muldi;
18358 *total = rs6000_cost->mulsi;
18363 if (FLOAT_MODE_P (mode))
18365 *total = mode == DFmode ? rs6000_cost->ddiv
18366 : rs6000_cost->sdiv;
18373 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18374 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18376 if (code == DIV || code == MOD)
18378 *total = COSTS_N_INSNS (2);
18381 *total = COSTS_N_INSNS (1);
18385 if (GET_MODE (XEXP (x, 1)) == DImode)
18386 *total = rs6000_cost->divdi;
18388 *total = rs6000_cost->divsi;
18390 /* Add in shift and subtract for MOD. */
18391 if (code == MOD || code == UMOD)
18392 *total += COSTS_N_INSNS (2);
18396 *total = COSTS_N_INSNS (4);
18400 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18411 *total = COSTS_N_INSNS (1);
18419 /* Handle mul_highpart. */
18420 if (outer_code == TRUNCATE
18421 && GET_CODE (XEXP (x, 0)) == MULT)
18423 if (mode == DImode)
18424 *total = rs6000_cost->muldi;
18426 *total = rs6000_cost->mulsi;
18429 else if (outer_code == AND)
18432 *total = COSTS_N_INSNS (1);
18437 if (GET_CODE (XEXP (x, 0)) == MEM)
18440 *total = COSTS_N_INSNS (1);
18446 if (!FLOAT_MODE_P (mode))
18448 *total = COSTS_N_INSNS (1);
18454 case UNSIGNED_FLOAT:
18457 case FLOAT_TRUNCATE:
18458 *total = rs6000_cost->fp;
18462 if (mode == DFmode)
18465 *total = rs6000_cost->fp;
18469 switch (XINT (x, 1))
18472 *total = rs6000_cost->fp;
18484 *total = COSTS_N_INSNS (1);
18487 else if (FLOAT_MODE_P (mode)
18488 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18490 *total = rs6000_cost->fp;
18498 /* Carry bit requires mode == Pmode.
18499 NEG or PLUS already counted so only add one. */
18501 && (outer_code == NEG || outer_code == PLUS))
18503 *total = COSTS_N_INSNS (1);
18506 if (outer_code == SET)
18508 if (XEXP (x, 1) == const0_rtx)
18510 *total = COSTS_N_INSNS (2);
18513 else if (mode == Pmode)
18515 *total = COSTS_N_INSNS (3);
18524 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18526 *total = COSTS_N_INSNS (2);
18530 if (outer_code == COMPARE)
18544 /* A C expression returning the cost of moving data from a register of class
18545 CLASS1 to one of CLASS2. */
18548 rs6000_register_move_cost (enum machine_mode mode,
18549 enum reg_class from, enum reg_class to)
18551 /* Moves from/to GENERAL_REGS. */
18552 if (reg_classes_intersect_p (to, GENERAL_REGS)
18553 || reg_classes_intersect_p (from, GENERAL_REGS))
18555 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18558 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18559 return (rs6000_memory_move_cost (mode, from, 0)
18560 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18562 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18564 else if (from == CR_REGS)
18568 /* A move will cost one instruction per GPR moved. */
18569 return 2 * hard_regno_nregs[0][mode];
18572 /* Moving between two similar registers is just one instruction. */
18573 else if (reg_classes_intersect_p (to, from))
18574 return mode == TFmode ? 4 : 2;
18576 /* Everything else has to go through GENERAL_REGS. */
18578 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18579 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18582 /* A C expressions returning the cost of moving data of MODE from a register to
18586 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18587 int in ATTRIBUTE_UNUSED)
18589 if (reg_classes_intersect_p (class, GENERAL_REGS))
18590 return 4 * hard_regno_nregs[0][mode];
18591 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18592 return 4 * hard_regno_nregs[32][mode];
18593 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18594 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18596 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18599 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18600 Assumes no trapping math and finite arguments. */
18603 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18605 rtx x0, e0, e1, y1, u0, v0, one;
18607 x0 = gen_reg_rtx (SFmode);
18608 e0 = gen_reg_rtx (SFmode);
18609 e1 = gen_reg_rtx (SFmode);
18610 y1 = gen_reg_rtx (SFmode);
18611 u0 = gen_reg_rtx (SFmode);
18612 v0 = gen_reg_rtx (SFmode);
18613 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18615 /* x0 = 1./d estimate */
18616 emit_insn (gen_rtx_SET (VOIDmode, x0,
18617 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18619 /* e0 = 1. - d * x0 */
18620 emit_insn (gen_rtx_SET (VOIDmode, e0,
18621 gen_rtx_MINUS (SFmode, one,
18622 gen_rtx_MULT (SFmode, d, x0))));
18623 /* e1 = e0 + e0 * e0 */
18624 emit_insn (gen_rtx_SET (VOIDmode, e1,
18625 gen_rtx_PLUS (SFmode,
18626 gen_rtx_MULT (SFmode, e0, e0), e0)));
18627 /* y1 = x0 + e1 * x0 */
18628 emit_insn (gen_rtx_SET (VOIDmode, y1,
18629 gen_rtx_PLUS (SFmode,
18630 gen_rtx_MULT (SFmode, e1, x0), x0)));
18632 emit_insn (gen_rtx_SET (VOIDmode, u0,
18633 gen_rtx_MULT (SFmode, n, y1)));
18634 /* v0 = n - d * u0 */
18635 emit_insn (gen_rtx_SET (VOIDmode, v0,
18636 gen_rtx_MINUS (SFmode, n,
18637 gen_rtx_MULT (SFmode, d, u0))));
18638 /* res = u0 + v0 * y1 */
18639 emit_insn (gen_rtx_SET (VOIDmode, res,
18640 gen_rtx_PLUS (SFmode,
18641 gen_rtx_MULT (SFmode, v0, y1), u0)));
18644 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18645 Assumes no trapping math and finite arguments. */
18648 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18650 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18652 x0 = gen_reg_rtx (DFmode);
18653 e0 = gen_reg_rtx (DFmode);
18654 e1 = gen_reg_rtx (DFmode);
18655 e2 = gen_reg_rtx (DFmode);
18656 y1 = gen_reg_rtx (DFmode);
18657 y2 = gen_reg_rtx (DFmode);
18658 y3 = gen_reg_rtx (DFmode);
18659 u0 = gen_reg_rtx (DFmode);
18660 v0 = gen_reg_rtx (DFmode);
18661 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18663 /* x0 = 1./d estimate */
18664 emit_insn (gen_rtx_SET (VOIDmode, x0,
18665 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18667 /* e0 = 1. - d * x0 */
18668 emit_insn (gen_rtx_SET (VOIDmode, e0,
18669 gen_rtx_MINUS (DFmode, one,
18670 gen_rtx_MULT (SFmode, d, x0))));
18671 /* y1 = x0 + e0 * x0 */
18672 emit_insn (gen_rtx_SET (VOIDmode, y1,
18673 gen_rtx_PLUS (DFmode,
18674 gen_rtx_MULT (DFmode, e0, x0), x0)));
18676 emit_insn (gen_rtx_SET (VOIDmode, e1,
18677 gen_rtx_MULT (DFmode, e0, e0)));
18678 /* y2 = y1 + e1 * y1 */
18679 emit_insn (gen_rtx_SET (VOIDmode, y2,
18680 gen_rtx_PLUS (DFmode,
18681 gen_rtx_MULT (DFmode, e1, y1), y1)));
18683 emit_insn (gen_rtx_SET (VOIDmode, e2,
18684 gen_rtx_MULT (DFmode, e1, e1)));
18685 /* y3 = y2 + e2 * y2 */
18686 emit_insn (gen_rtx_SET (VOIDmode, y3,
18687 gen_rtx_PLUS (DFmode,
18688 gen_rtx_MULT (DFmode, e2, y2), y2)));
18690 emit_insn (gen_rtx_SET (VOIDmode, u0,
18691 gen_rtx_MULT (DFmode, n, y3)));
18692 /* v0 = n - d * u0 */
18693 emit_insn (gen_rtx_SET (VOIDmode, v0,
18694 gen_rtx_MINUS (DFmode, n,
18695 gen_rtx_MULT (DFmode, d, u0))));
18696 /* res = u0 + v0 * y3 */
18697 emit_insn (gen_rtx_SET (VOIDmode, res,
18698 gen_rtx_PLUS (DFmode,
18699 gen_rtx_MULT (DFmode, v0, y3), u0)));
18702 /* Return an RTX representing where to find the function value of a
18703 function returning MODE. */
18705 rs6000_complex_function_value (enum machine_mode mode)
18707 unsigned int regno;
18709 enum machine_mode inner = GET_MODE_INNER (mode);
18710 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18712 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18713 regno = FP_ARG_RETURN;
18716 regno = GP_ARG_RETURN;
18718 /* 32-bit is OK since it'll go in r3/r4. */
18719 if (TARGET_32BIT && inner_bytes >= 4)
18720 return gen_rtx_REG (mode, regno);
18723 if (inner_bytes >= 8)
18724 return gen_rtx_REG (mode, regno);
18726 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18728 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18729 GEN_INT (inner_bytes));
18730 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18733 /* Define how to find the value returned by a function.
18734 VALTYPE is the data type of the value (as a tree).
18735 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18736 otherwise, FUNC is 0.
18738 On the SPE, both FPs and vectors are returned in r3.
18740 On RS/6000 an integer value is in r3 and a floating-point value is in
18741 fp1, unless -msoft-float. */
18744 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18746 enum machine_mode mode;
18747 unsigned int regno;
18749 /* Special handling for structs in darwin64. */
18750 if (rs6000_darwin64_abi
18751 && TYPE_MODE (valtype) == BLKmode
18752 && TREE_CODE (valtype) == RECORD_TYPE
18753 && int_size_in_bytes (valtype) > 0)
18755 CUMULATIVE_ARGS valcum;
18759 valcum.fregno = FP_ARG_MIN_REG;
18760 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18761 /* Do a trial code generation as if this were going to be passed as
18762 an argument; if any part goes in memory, we return NULL. */
18763 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18766 /* Otherwise fall through to standard ABI rules. */
18769 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18771 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18772 return gen_rtx_PARALLEL (DImode,
18774 gen_rtx_EXPR_LIST (VOIDmode,
18775 gen_rtx_REG (SImode, GP_ARG_RETURN),
18777 gen_rtx_EXPR_LIST (VOIDmode,
18778 gen_rtx_REG (SImode,
18779 GP_ARG_RETURN + 1),
18782 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
18784 return gen_rtx_PARALLEL (DCmode,
18786 gen_rtx_EXPR_LIST (VOIDmode,
18787 gen_rtx_REG (SImode, GP_ARG_RETURN),
18789 gen_rtx_EXPR_LIST (VOIDmode,
18790 gen_rtx_REG (SImode,
18791 GP_ARG_RETURN + 1),
18793 gen_rtx_EXPR_LIST (VOIDmode,
18794 gen_rtx_REG (SImode,
18795 GP_ARG_RETURN + 2),
18797 gen_rtx_EXPR_LIST (VOIDmode,
18798 gen_rtx_REG (SImode,
18799 GP_ARG_RETURN + 3),
18802 if ((INTEGRAL_TYPE_P (valtype)
18803 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18804 || POINTER_TYPE_P (valtype))
18805 mode = TARGET_32BIT ? SImode : DImode;
18807 mode = TYPE_MODE (valtype);
18809 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18810 regno = FP_ARG_RETURN;
18811 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18812 && targetm.calls.split_complex_arg)
18813 return rs6000_complex_function_value (mode);
18814 else if (TREE_CODE (valtype) == VECTOR_TYPE
18815 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18816 && ALTIVEC_VECTOR_MODE (mode))
18817 regno = ALTIVEC_ARG_RETURN;
18818 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18819 && (mode == DFmode || mode == DCmode))
18820 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18822 regno = GP_ARG_RETURN;
18824 return gen_rtx_REG (mode, regno);
18827 /* Define how to find the value returned by a library function
18828 assuming the value has mode MODE. */
18830 rs6000_libcall_value (enum machine_mode mode)
18832 unsigned int regno;
18834 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18836 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18837 return gen_rtx_PARALLEL (DImode,
18839 gen_rtx_EXPR_LIST (VOIDmode,
18840 gen_rtx_REG (SImode, GP_ARG_RETURN),
18842 gen_rtx_EXPR_LIST (VOIDmode,
18843 gen_rtx_REG (SImode,
18844 GP_ARG_RETURN + 1),
18848 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18849 && TARGET_HARD_FLOAT && TARGET_FPRS)
18850 regno = FP_ARG_RETURN;
18851 else if (ALTIVEC_VECTOR_MODE (mode)
18852 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18853 regno = ALTIVEC_ARG_RETURN;
18854 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18855 return rs6000_complex_function_value (mode);
18856 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18857 && (mode == DFmode || mode == DCmode))
18858 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18860 regno = GP_ARG_RETURN;
18862 return gen_rtx_REG (mode, regno);
18865 /* Define the offset between two registers, FROM to be eliminated and its
18866 replacement TO, at the start of a routine. */
18868 rs6000_initial_elimination_offset (int from, int to)
18870 rs6000_stack_t *info = rs6000_stack_info ();
18871 HOST_WIDE_INT offset;
18873 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18874 offset = info->push_p ? 0 : -info->total_size;
18875 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18877 offset = info->push_p ? 0 : -info->total_size;
18878 if (FRAME_GROWS_DOWNWARD)
18879 offset += info->fixed_size + info->vars_size + info->parm_size;
18881 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18882 offset = FRAME_GROWS_DOWNWARD
18883 ? info->fixed_size + info->vars_size + info->parm_size
18885 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18886 offset = info->total_size;
18887 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18888 offset = info->push_p ? info->total_size : 0;
18889 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18892 gcc_unreachable ();
18897 /* Return true if TYPE is a SPE or AltiVec opaque type. */
18900 rs6000_is_opaque_type (tree type)
18902 return (type == opaque_V2SI_type_node
18903 || type == opaque_V2SF_type_node
18904 || type == opaque_p_V2SI_type_node
18905 || type == opaque_V4SI_type_node);
18909 rs6000_dwarf_register_span (rtx reg)
18914 && (SPE_VECTOR_MODE (GET_MODE (reg))
18915 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18920 regno = REGNO (reg);
18922 /* The duality of the SPE register size wreaks all kinds of havoc.
18923 This is a way of distinguishing r0 in 32-bits from r0 in
18926 gen_rtx_PARALLEL (VOIDmode,
18929 gen_rtx_REG (SImode, regno + 1200),
18930 gen_rtx_REG (SImode, regno))
18932 gen_rtx_REG (SImode, regno),
18933 gen_rtx_REG (SImode, regno + 1200)));
18936 /* Map internal gcc register numbers to DWARF2 register numbers. */
18939 rs6000_dbx_register_number (unsigned int regno)
18941 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18943 if (regno == MQ_REGNO)
18945 if (regno == LINK_REGISTER_REGNUM)
18947 if (regno == COUNT_REGISTER_REGNUM)
18949 if (CR_REGNO_P (regno))
18950 return regno - CR0_REGNO + 86;
18951 if (regno == XER_REGNO)
18953 if (ALTIVEC_REGNO_P (regno))
18954 return regno - FIRST_ALTIVEC_REGNO + 1124;
18955 if (regno == VRSAVE_REGNO)
18957 if (regno == VSCR_REGNO)
18959 if (regno == SPE_ACC_REGNO)
18961 if (regno == SPEFSCR_REGNO)
18963 /* SPE high reg number. We get these values of regno from
18964 rs6000_dwarf_register_span. */
18965 gcc_assert (regno >= 1200 && regno < 1232);
18969 /* target hook eh_return_filter_mode */
18970 static enum machine_mode
18971 rs6000_eh_return_filter_mode (void)
18973 return TARGET_32BIT ? SImode : word_mode;
18976 /* Target hook for vector_mode_supported_p. */
18978 rs6000_vector_mode_supported_p (enum machine_mode mode)
18981 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18984 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18991 /* Target hook for invalid_arg_for_unprototyped_fn. */
18992 static const char *
18993 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
18995 return (!rs6000_darwin64_abi
18997 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
18998 && (funcdecl == NULL_TREE
18999 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19000 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19001 ? N_("AltiVec argument passed to unprototyped function")
19005 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19006 setup by using __stack_chk_fail_local hidden function instead of
19007 calling __stack_chk_fail directly. Otherwise it is better to call
19008 __stack_chk_fail directly. */
19011 rs6000_stack_protect_fail (void)
19013 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19014 ? default_hidden_stack_protect_fail ()
19015 : default_external_stack_protect_fail ();
19018 #include "gt-rs6000.h"