1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
57 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
60 #include "gstab.h" /* for N_SLINE */
63 #ifndef TARGET_NO_PROTOTYPE
64 #define TARGET_NO_PROTOTYPE 0
67 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15)
68 #define EASY_VECTOR_15_ADD_SELF(n) ((n) >= 0x10 && (n) <= 0x1e && !((n) & 1))
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int toc_save_p; /* true if the TOC needs to be saved */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int toc_save_offset; /* offset to save the TOC pointer */
95 int varargs_save_offset; /* offset to save the varargs registers */
96 int ehrd_offset; /* offset to EH return data */
97 int reg_size; /* register size (4 or 8) */
98 int varargs_size; /* size to hold V.4 args passed in regs */
99 HOST_WIDE_INT vars_size; /* variable save area size */
100 int parm_size; /* outgoing parameter size */
101 int save_size; /* save area size */
102 int fixed_size; /* fixed size of stack frame */
103 int gp_size; /* size of saved GP registers */
104 int fp_size; /* size of saved FP registers */
105 int altivec_size; /* size of saved AltiVec registers */
106 int cr_size; /* size to hold CR if not in save_size */
107 int lr_size; /* size to hold LR if not in save_size */
108 int vrsave_size; /* size to hold VRSAVE if not in save_size */
109 int altivec_padding_size; /* size of altivec alignment padding if
111 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
112 int spe_padding_size;
113 int toc_size; /* size to hold TOC if not in save_size */
114 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
115 int spe_64bit_regs_used;
118 /* Target cpu type */
120 enum processor_type rs6000_cpu;
121 struct rs6000_cpu_select rs6000_select[3] =
123 /* switch name, tune arch */
124 { (const char *)0, "--with-cpu=", 1, 1 },
125 { (const char *)0, "-mcpu=", 1, 1 },
126 { (const char *)0, "-mtune=", 1, 0 },
129 /* Always emit branch hint bits. */
130 static GTY(()) bool rs6000_always_hint;
132 /* Schedule instructions for group formation. */
133 static GTY(()) bool rs6000_sched_groups;
135 /* Support adjust_priority scheduler hook
136 and -mprioritize-restricted-insns= option. */
137 const char *rs6000_sched_restricted_insns_priority_str;
138 int rs6000_sched_restricted_insns_priority;
140 /* Support for -msched-costly-dep option. */
141 const char *rs6000_sched_costly_dep_str;
142 enum rs6000_dependence_cost rs6000_sched_costly_dep;
144 /* Support for -minsert-sched-nops option. */
145 const char *rs6000_sched_insert_nops_str;
146 enum rs6000_nop_insertion rs6000_sched_insert_nops;
148 /* Support targetm.vectorize.builtin_mask_for_load. */
149 static GTY(()) tree altivec_builtin_mask_for_load;
151 /* Size of long double */
152 const char *rs6000_long_double_size_string;
153 int rs6000_long_double_type_size;
155 /* Whether -mabi=altivec has appeared */
156 int rs6000_altivec_abi;
158 /* Whether VRSAVE instructions should be generated. */
159 int rs6000_altivec_vrsave;
161 /* String from -mvrsave= option. */
162 const char *rs6000_altivec_vrsave_string;
164 /* Nonzero if we want SPE ABI extensions. */
167 /* Whether isel instructions should be generated. */
170 /* Whether SPE simd instructions should be generated. */
173 /* Nonzero if floating point operations are done in the GPRs. */
174 int rs6000_float_gprs = 0;
176 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
177 int rs6000_darwin64_abi;
179 /* String from -mfloat-gprs=. */
180 const char *rs6000_float_gprs_string;
182 /* String from -misel=. */
183 const char *rs6000_isel_string;
185 /* String from -mspe=. */
186 const char *rs6000_spe_string;
188 /* Set to nonzero once AIX common-mode calls have been defined. */
189 static GTY(()) int common_mode_defined;
191 /* Save information from a "cmpxx" operation until the branch or scc is
193 rtx rs6000_compare_op0, rs6000_compare_op1;
194 int rs6000_compare_fp_p;
196 /* Label number of label created for -mrelocatable, to call to so we can
197 get the address of the GOT section */
198 int rs6000_pic_labelno;
201 /* Which abi to adhere to */
202 const char *rs6000_abi_name;
204 /* Semantics of the small data area */
205 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
207 /* Which small data model to use */
208 const char *rs6000_sdata_name = (char *)0;
210 /* Counter for labels which are to be placed in .fixup. */
211 int fixuplabelno = 0;
214 /* Bit size of immediate TLS offsets and string from which it is decoded. */
215 int rs6000_tls_size = 32;
216 const char *rs6000_tls_size_string;
218 /* ABI enumeration available for subtarget to use. */
219 enum rs6000_abi rs6000_current_abi;
221 /* ABI string from -mabi= option. */
222 const char *rs6000_abi_string;
224 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
228 const char *rs6000_debug_name;
229 int rs6000_debug_stack; /* debug stack applications */
230 int rs6000_debug_arg; /* debug argument handling */
232 /* Value is TRUE if register/mode pair is accepatable. */
233 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
236 static GTY(()) tree opaque_V2SI_type_node;
237 static GTY(()) tree opaque_V2SF_type_node;
238 static GTY(()) tree opaque_p_V2SI_type_node;
239 static GTY(()) tree V16QI_type_node;
240 static GTY(()) tree V2SI_type_node;
241 static GTY(()) tree V2SF_type_node;
242 static GTY(()) tree V4HI_type_node;
243 static GTY(()) tree V4SI_type_node;
244 static GTY(()) tree V4SF_type_node;
245 static GTY(()) tree V8HI_type_node;
246 static GTY(()) tree unsigned_V16QI_type_node;
247 static GTY(()) tree unsigned_V8HI_type_node;
248 static GTY(()) tree unsigned_V4SI_type_node;
249 static GTY(()) tree bool_char_type_node; /* __bool char */
250 static GTY(()) tree bool_short_type_node; /* __bool short */
251 static GTY(()) tree bool_int_type_node; /* __bool int */
252 static GTY(()) tree pixel_type_node; /* __pixel */
253 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
254 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
255 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
256 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
258 int rs6000_warn_altivec_long = 1; /* On by default. */
259 const char *rs6000_warn_altivec_long_switch;
261 const char *rs6000_traceback_name;
263 traceback_default = 0,
269 /* Flag to say the TOC is initialized */
271 char toc_label_name[10];
273 /* Alias set for saves and restores from the rs6000 stack. */
274 static GTY(()) int rs6000_sr_alias_set;
276 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
277 The only place that looks at this is rs6000_set_default_type_attributes;
278 everywhere else should rely on the presence or absence of a longcall
279 attribute on the function declaration. Exception: init_cumulative_args
280 looks at it too, for libcalls. */
281 int rs6000_default_long_calls;
282 const char *rs6000_longcall_switch;
284 /* Control alignment for fields within structures. */
285 /* String from -malign-XXXXX. */
286 const char *rs6000_alignment_string;
287 int rs6000_alignment_flags;
289 struct builtin_description
291 /* mask is not const because we're going to alter it below. This
292 nonsense will go away when we rewrite the -march infrastructure
293 to give us more target flag bits. */
295 const enum insn_code icode;
296 const char *const name;
297 const enum rs6000_builtins code;
300 /* Target cpu costs. */
302 struct processor_costs {
303 const int mulsi; /* cost of SImode multiplication. */
304 const int mulsi_const; /* cost of SImode multiplication by constant. */
305 const int mulsi_const9; /* cost of SImode mult by short constant. */
306 const int muldi; /* cost of DImode multiplication. */
307 const int divsi; /* cost of SImode division. */
308 const int divdi; /* cost of DImode division. */
309 const int fp; /* cost of simple SFmode and DFmode insns. */
310 const int dmul; /* cost of DFmode multiplication (and fmadd). */
311 const int sdiv; /* cost of SFmode division (fdivs). */
312 const int ddiv; /* cost of DFmode division (fdiv). */
315 const struct processor_costs *rs6000_cost;
317 /* Processor costs (relative to an add) */
319 /* Instruction size costs on 32bit processors. */
321 struct processor_costs size32_cost = {
322 COSTS_N_INSNS (1), /* mulsi */
323 COSTS_N_INSNS (1), /* mulsi_const */
324 COSTS_N_INSNS (1), /* mulsi_const9 */
325 COSTS_N_INSNS (1), /* muldi */
326 COSTS_N_INSNS (1), /* divsi */
327 COSTS_N_INSNS (1), /* divdi */
328 COSTS_N_INSNS (1), /* fp */
329 COSTS_N_INSNS (1), /* dmul */
330 COSTS_N_INSNS (1), /* sdiv */
331 COSTS_N_INSNS (1), /* ddiv */
334 /* Instruction size costs on 64bit processors. */
336 struct processor_costs size64_cost = {
337 COSTS_N_INSNS (1), /* mulsi */
338 COSTS_N_INSNS (1), /* mulsi_const */
339 COSTS_N_INSNS (1), /* mulsi_const9 */
340 COSTS_N_INSNS (1), /* muldi */
341 COSTS_N_INSNS (1), /* divsi */
342 COSTS_N_INSNS (1), /* divdi */
343 COSTS_N_INSNS (1), /* fp */
344 COSTS_N_INSNS (1), /* dmul */
345 COSTS_N_INSNS (1), /* sdiv */
346 COSTS_N_INSNS (1), /* ddiv */
349 /* Instruction costs on RIOS1 processors. */
351 struct processor_costs rios1_cost = {
352 COSTS_N_INSNS (5), /* mulsi */
353 COSTS_N_INSNS (4), /* mulsi_const */
354 COSTS_N_INSNS (3), /* mulsi_const9 */
355 COSTS_N_INSNS (5), /* muldi */
356 COSTS_N_INSNS (19), /* divsi */
357 COSTS_N_INSNS (19), /* divdi */
358 COSTS_N_INSNS (2), /* fp */
359 COSTS_N_INSNS (2), /* dmul */
360 COSTS_N_INSNS (19), /* sdiv */
361 COSTS_N_INSNS (19), /* ddiv */
364 /* Instruction costs on RIOS2 processors. */
366 struct processor_costs rios2_cost = {
367 COSTS_N_INSNS (2), /* mulsi */
368 COSTS_N_INSNS (2), /* mulsi_const */
369 COSTS_N_INSNS (2), /* mulsi_const9 */
370 COSTS_N_INSNS (2), /* muldi */
371 COSTS_N_INSNS (13), /* divsi */
372 COSTS_N_INSNS (13), /* divdi */
373 COSTS_N_INSNS (2), /* fp */
374 COSTS_N_INSNS (2), /* dmul */
375 COSTS_N_INSNS (17), /* sdiv */
376 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
394 /* Instruction costs on MPCCORE processors. */
396 struct processor_costs mpccore_cost = {
397 COSTS_N_INSNS (2), /* mulsi */
398 COSTS_N_INSNS (2), /* mulsi_const */
399 COSTS_N_INSNS (2), /* mulsi_const9 */
400 COSTS_N_INSNS (2), /* muldi */
401 COSTS_N_INSNS (6), /* divsi */
402 COSTS_N_INSNS (6), /* divdi */
403 COSTS_N_INSNS (4), /* fp */
404 COSTS_N_INSNS (5), /* dmul */
405 COSTS_N_INSNS (10), /* sdiv */
406 COSTS_N_INSNS (17), /* ddiv */
409 /* Instruction costs on PPC403 processors. */
411 struct processor_costs ppc403_cost = {
412 COSTS_N_INSNS (4), /* mulsi */
413 COSTS_N_INSNS (4), /* mulsi_const */
414 COSTS_N_INSNS (4), /* mulsi_const9 */
415 COSTS_N_INSNS (4), /* muldi */
416 COSTS_N_INSNS (33), /* divsi */
417 COSTS_N_INSNS (33), /* divdi */
418 COSTS_N_INSNS (11), /* fp */
419 COSTS_N_INSNS (11), /* dmul */
420 COSTS_N_INSNS (11), /* sdiv */
421 COSTS_N_INSNS (11), /* ddiv */
424 /* Instruction costs on PPC405 processors. */
426 struct processor_costs ppc405_cost = {
427 COSTS_N_INSNS (5), /* mulsi */
428 COSTS_N_INSNS (4), /* mulsi_const */
429 COSTS_N_INSNS (3), /* mulsi_const9 */
430 COSTS_N_INSNS (5), /* muldi */
431 COSTS_N_INSNS (35), /* divsi */
432 COSTS_N_INSNS (35), /* divdi */
433 COSTS_N_INSNS (11), /* fp */
434 COSTS_N_INSNS (11), /* dmul */
435 COSTS_N_INSNS (11), /* sdiv */
436 COSTS_N_INSNS (11), /* ddiv */
439 /* Instruction costs on PPC440 processors. */
441 struct processor_costs ppc440_cost = {
442 COSTS_N_INSNS (3), /* mulsi */
443 COSTS_N_INSNS (2), /* mulsi_const */
444 COSTS_N_INSNS (2), /* mulsi_const9 */
445 COSTS_N_INSNS (3), /* muldi */
446 COSTS_N_INSNS (34), /* divsi */
447 COSTS_N_INSNS (34), /* divdi */
448 COSTS_N_INSNS (5), /* fp */
449 COSTS_N_INSNS (5), /* dmul */
450 COSTS_N_INSNS (19), /* sdiv */
451 COSTS_N_INSNS (33), /* ddiv */
454 /* Instruction costs on PPC601 processors. */
456 struct processor_costs ppc601_cost = {
457 COSTS_N_INSNS (5), /* mulsi */
458 COSTS_N_INSNS (5), /* mulsi_const */
459 COSTS_N_INSNS (5), /* mulsi_const9 */
460 COSTS_N_INSNS (5), /* muldi */
461 COSTS_N_INSNS (36), /* divsi */
462 COSTS_N_INSNS (36), /* divdi */
463 COSTS_N_INSNS (4), /* fp */
464 COSTS_N_INSNS (5), /* dmul */
465 COSTS_N_INSNS (17), /* sdiv */
466 COSTS_N_INSNS (31), /* ddiv */
469 /* Instruction costs on PPC603 processors. */
471 struct processor_costs ppc603_cost = {
472 COSTS_N_INSNS (5), /* mulsi */
473 COSTS_N_INSNS (3), /* mulsi_const */
474 COSTS_N_INSNS (2), /* mulsi_const9 */
475 COSTS_N_INSNS (5), /* muldi */
476 COSTS_N_INSNS (37), /* divsi */
477 COSTS_N_INSNS (37), /* divdi */
478 COSTS_N_INSNS (3), /* fp */
479 COSTS_N_INSNS (4), /* dmul */
480 COSTS_N_INSNS (18), /* sdiv */
481 COSTS_N_INSNS (33), /* ddiv */
484 /* Instruction costs on PPC604 processors. */
486 struct processor_costs ppc604_cost = {
487 COSTS_N_INSNS (4), /* mulsi */
488 COSTS_N_INSNS (4), /* mulsi_const */
489 COSTS_N_INSNS (4), /* mulsi_const9 */
490 COSTS_N_INSNS (4), /* muldi */
491 COSTS_N_INSNS (20), /* divsi */
492 COSTS_N_INSNS (20), /* divdi */
493 COSTS_N_INSNS (3), /* fp */
494 COSTS_N_INSNS (3), /* dmul */
495 COSTS_N_INSNS (18), /* sdiv */
496 COSTS_N_INSNS (32), /* ddiv */
499 /* Instruction costs on PPC604e processors. */
501 struct processor_costs ppc604e_cost = {
502 COSTS_N_INSNS (2), /* mulsi */
503 COSTS_N_INSNS (2), /* mulsi_const */
504 COSTS_N_INSNS (2), /* mulsi_const9 */
505 COSTS_N_INSNS (2), /* muldi */
506 COSTS_N_INSNS (20), /* divsi */
507 COSTS_N_INSNS (20), /* divdi */
508 COSTS_N_INSNS (3), /* fp */
509 COSTS_N_INSNS (3), /* dmul */
510 COSTS_N_INSNS (18), /* sdiv */
511 COSTS_N_INSNS (32), /* ddiv */
514 /* Instruction costs on PPC620 processors. */
516 struct processor_costs ppc620_cost = {
517 COSTS_N_INSNS (5), /* mulsi */
518 COSTS_N_INSNS (4), /* mulsi_const */
519 COSTS_N_INSNS (3), /* mulsi_const9 */
520 COSTS_N_INSNS (7), /* muldi */
521 COSTS_N_INSNS (21), /* divsi */
522 COSTS_N_INSNS (37), /* divdi */
523 COSTS_N_INSNS (3), /* fp */
524 COSTS_N_INSNS (3), /* dmul */
525 COSTS_N_INSNS (18), /* sdiv */
526 COSTS_N_INSNS (32), /* ddiv */
529 /* Instruction costs on PPC630 processors. */
531 struct processor_costs ppc630_cost = {
532 COSTS_N_INSNS (5), /* mulsi */
533 COSTS_N_INSNS (4), /* mulsi_const */
534 COSTS_N_INSNS (3), /* mulsi_const9 */
535 COSTS_N_INSNS (7), /* muldi */
536 COSTS_N_INSNS (21), /* divsi */
537 COSTS_N_INSNS (37), /* divdi */
538 COSTS_N_INSNS (3), /* fp */
539 COSTS_N_INSNS (3), /* dmul */
540 COSTS_N_INSNS (17), /* sdiv */
541 COSTS_N_INSNS (21), /* ddiv */
544 /* Instruction costs on PPC750 and PPC7400 processors. */
546 struct processor_costs ppc750_cost = {
547 COSTS_N_INSNS (5), /* mulsi */
548 COSTS_N_INSNS (3), /* mulsi_const */
549 COSTS_N_INSNS (2), /* mulsi_const9 */
550 COSTS_N_INSNS (5), /* muldi */
551 COSTS_N_INSNS (17), /* divsi */
552 COSTS_N_INSNS (17), /* divdi */
553 COSTS_N_INSNS (3), /* fp */
554 COSTS_N_INSNS (3), /* dmul */
555 COSTS_N_INSNS (17), /* sdiv */
556 COSTS_N_INSNS (31), /* ddiv */
559 /* Instruction costs on PPC7450 processors. */
561 struct processor_costs ppc7450_cost = {
562 COSTS_N_INSNS (4), /* mulsi */
563 COSTS_N_INSNS (3), /* mulsi_const */
564 COSTS_N_INSNS (3), /* mulsi_const9 */
565 COSTS_N_INSNS (4), /* muldi */
566 COSTS_N_INSNS (23), /* divsi */
567 COSTS_N_INSNS (23), /* divdi */
568 COSTS_N_INSNS (5), /* fp */
569 COSTS_N_INSNS (5), /* dmul */
570 COSTS_N_INSNS (21), /* sdiv */
571 COSTS_N_INSNS (35), /* ddiv */
574 /* Instruction costs on PPC8540 processors. */
576 struct processor_costs ppc8540_cost = {
577 COSTS_N_INSNS (4), /* mulsi */
578 COSTS_N_INSNS (4), /* mulsi_const */
579 COSTS_N_INSNS (4), /* mulsi_const9 */
580 COSTS_N_INSNS (4), /* muldi */
581 COSTS_N_INSNS (19), /* divsi */
582 COSTS_N_INSNS (19), /* divdi */
583 COSTS_N_INSNS (4), /* fp */
584 COSTS_N_INSNS (4), /* dmul */
585 COSTS_N_INSNS (29), /* sdiv */
586 COSTS_N_INSNS (29), /* ddiv */
589 /* Instruction costs on POWER4 and POWER5 processors. */
591 struct processor_costs power4_cost = {
592 COSTS_N_INSNS (3), /* mulsi */
593 COSTS_N_INSNS (2), /* mulsi_const */
594 COSTS_N_INSNS (2), /* mulsi_const9 */
595 COSTS_N_INSNS (4), /* muldi */
596 COSTS_N_INSNS (18), /* divsi */
597 COSTS_N_INSNS (34), /* divdi */
598 COSTS_N_INSNS (3), /* fp */
599 COSTS_N_INSNS (3), /* dmul */
600 COSTS_N_INSNS (17), /* sdiv */
601 COSTS_N_INSNS (17), /* ddiv */
605 static bool rs6000_function_ok_for_sibcall (tree, tree);
606 static int num_insns_constant_wide (HOST_WIDE_INT);
607 static void validate_condition_mode (enum rtx_code, enum machine_mode);
608 static rtx rs6000_generate_compare (enum rtx_code);
609 static void rs6000_maybe_dead (rtx);
610 static void rs6000_emit_stack_tie (void);
611 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
612 static rtx spe_synthesize_frame_save (rtx);
613 static bool spe_func_has_64bit_regs_p (void);
614 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
616 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
617 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
618 static unsigned rs6000_hash_constant (rtx);
619 static unsigned toc_hash_function (const void *);
620 static int toc_hash_eq (const void *, const void *);
621 static int constant_pool_expr_1 (rtx, int *, int *);
622 static bool constant_pool_expr_p (rtx);
623 static bool toc_relative_expr_p (rtx);
624 static bool legitimate_small_data_p (enum machine_mode, rtx);
625 static bool legitimate_indexed_address_p (rtx, int);
626 static bool legitimate_indirect_address_p (rtx, int);
627 static bool macho_lo_sum_memory_operand (rtx x, enum machine_mode mode);
628 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
629 static struct machine_function * rs6000_init_machine_status (void);
630 static bool rs6000_assemble_integer (rtx, unsigned int, int);
631 #ifdef HAVE_GAS_HIDDEN
632 static void rs6000_assemble_visibility (tree, int);
634 static int rs6000_ra_ever_killed (void);
635 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
636 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
637 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
638 static const char *rs6000_mangle_fundamental_type (tree);
639 extern const struct attribute_spec rs6000_attribute_table[];
640 static void rs6000_set_default_type_attributes (tree);
641 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
642 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
643 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
645 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
646 static bool rs6000_return_in_memory (tree, tree);
647 static void rs6000_file_start (void);
649 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
650 static void rs6000_elf_asm_out_constructor (rtx, int);
651 static void rs6000_elf_asm_out_destructor (rtx, int);
652 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
653 static void rs6000_elf_unique_section (tree, int);
654 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
655 unsigned HOST_WIDE_INT);
656 static void rs6000_elf_encode_section_info (tree, rtx, int)
658 static bool rs6000_elf_in_small_data_p (tree);
661 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
662 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
663 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
664 static void rs6000_xcoff_unique_section (tree, int);
665 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
666 unsigned HOST_WIDE_INT);
667 static const char * rs6000_xcoff_strip_name_encoding (const char *);
668 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
669 static void rs6000_xcoff_file_start (void);
670 static void rs6000_xcoff_file_end (void);
673 static bool rs6000_binds_local_p (tree);
675 static int rs6000_variable_issue (FILE *, int, rtx, int);
676 static bool rs6000_rtx_costs (rtx, int, int, int *);
677 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
678 static bool is_microcoded_insn (rtx);
679 static int is_dispatch_slot_restricted (rtx);
680 static bool is_cracked_insn (rtx);
681 static bool is_branch_slot_insn (rtx);
682 static int rs6000_adjust_priority (rtx, int);
683 static int rs6000_issue_rate (void);
684 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
685 static rtx get_next_active_insn (rtx, rtx);
686 static bool insn_terminates_group_p (rtx , enum group_termination);
687 static bool is_costly_group (rtx *, rtx);
688 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
689 static int redefine_groups (FILE *, int, rtx, rtx);
690 static int pad_groups (FILE *, int, rtx, rtx);
691 static void rs6000_sched_finish (FILE *, int);
692 static int rs6000_use_sched_lookahead (void);
693 static tree rs6000_builtin_mask_for_load (void);
695 static void rs6000_init_builtins (void);
696 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
697 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
698 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
699 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
700 static void altivec_init_builtins (void);
701 static void rs6000_common_init_builtins (void);
702 static void rs6000_init_libfuncs (void);
704 static void enable_mask_for_builtins (struct builtin_description *, int,
705 enum rs6000_builtins,
706 enum rs6000_builtins);
707 static tree build_opaque_vector_type (tree, int);
708 static void spe_init_builtins (void);
709 static rtx spe_expand_builtin (tree, rtx, bool *);
710 static rtx spe_expand_stv_builtin (enum insn_code, tree);
711 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
712 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
713 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
714 static rs6000_stack_t *rs6000_stack_info (void);
715 static void debug_stack_info (rs6000_stack_t *);
717 static rtx altivec_expand_builtin (tree, rtx, bool *);
718 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
719 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
720 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
721 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
722 static rtx altivec_expand_predicate_builtin (enum insn_code,
723 const char *, tree, rtx);
724 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
725 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
726 static void rs6000_parse_abi_options (void);
727 static void rs6000_parse_alignment_option (void);
728 static void rs6000_parse_tls_size_option (void);
729 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
730 static void rs6000_parse_float_gprs_option (void);
731 static int first_altivec_reg_to_save (void);
732 static unsigned int compute_vrsave_mask (void);
733 static void compute_save_world_info(rs6000_stack_t *info_ptr);
734 static void is_altivec_return_reg (rtx, void *);
735 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
736 int easy_vector_constant (rtx, enum machine_mode);
737 static int easy_vector_same (rtx, enum machine_mode);
738 static int easy_vector_splat_const (int, enum machine_mode);
739 static bool is_ev64_opaque_type (tree);
740 static rtx rs6000_dwarf_register_span (rtx);
741 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
742 static rtx rs6000_tls_get_addr (void);
743 static rtx rs6000_got_sym (void);
744 static inline int rs6000_tls_symbol_ref_1 (rtx *, void *);
745 static const char *rs6000_get_some_local_dynamic_name (void);
746 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
747 static rtx rs6000_complex_function_value (enum machine_mode);
748 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
749 enum machine_mode, tree);
750 static rtx rs6000_darwin64_function_arg (CUMULATIVE_ARGS *,
751 enum machine_mode, tree, int);
752 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
753 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
754 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
757 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
759 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
762 static void macho_branch_islands (void);
763 static void add_compiler_branch_island (tree, tree, int);
764 static int no_previous_def (tree function_name);
765 static tree get_prev_label (tree function_name);
766 static void rs6000_darwin_file_start (void);
769 static tree rs6000_build_builtin_va_list (void);
770 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
771 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
772 static bool rs6000_vector_mode_supported_p (enum machine_mode);
773 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
775 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
777 static int get_vsel_insn (enum machine_mode);
778 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
781 const int INSN_NOT_AVAILABLE = -1;
782 static enum machine_mode rs6000_eh_return_filter_mode (void);
784 /* Hash table stuff for keeping track of TOC entries. */
786 struct toc_hash_struct GTY(())
788 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
789 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
791 enum machine_mode key_mode;
795 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
797 /* Default register names. */
798 char rs6000_reg_names[][8] =
800 "0", "1", "2", "3", "4", "5", "6", "7",
801 "8", "9", "10", "11", "12", "13", "14", "15",
802 "16", "17", "18", "19", "20", "21", "22", "23",
803 "24", "25", "26", "27", "28", "29", "30", "31",
804 "0", "1", "2", "3", "4", "5", "6", "7",
805 "8", "9", "10", "11", "12", "13", "14", "15",
806 "16", "17", "18", "19", "20", "21", "22", "23",
807 "24", "25", "26", "27", "28", "29", "30", "31",
808 "mq", "lr", "ctr","ap",
809 "0", "1", "2", "3", "4", "5", "6", "7",
811 /* AltiVec registers. */
812 "0", "1", "2", "3", "4", "5", "6", "7",
813 "8", "9", "10", "11", "12", "13", "14", "15",
814 "16", "17", "18", "19", "20", "21", "22", "23",
815 "24", "25", "26", "27", "28", "29", "30", "31",
821 #ifdef TARGET_REGNAMES
822 static const char alt_reg_names[][8] =
824 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
825 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
826 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
827 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
828 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
829 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
830 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
831 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
832 "mq", "lr", "ctr", "ap",
833 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
835 /* AltiVec registers. */
836 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
837 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
838 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
839 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
846 #ifndef MASK_STRICT_ALIGN
847 #define MASK_STRICT_ALIGN 0
849 #ifndef TARGET_PROFILE_KERNEL
850 #define TARGET_PROFILE_KERNEL 0
853 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
854 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
856 /* Return 1 for a symbol ref for a thread-local storage symbol. */
857 #define RS6000_SYMBOL_REF_TLS_P(RTX) \
858 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
860 /* Initialize the GCC target structure. */
861 #undef TARGET_ATTRIBUTE_TABLE
862 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
863 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
864 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
866 #undef TARGET_ASM_ALIGNED_DI_OP
867 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
869 /* Default unaligned ops are only provided for ELF. Find the ops needed
870 for non-ELF systems. */
871 #ifndef OBJECT_FORMAT_ELF
873 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
875 #undef TARGET_ASM_UNALIGNED_HI_OP
876 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
877 #undef TARGET_ASM_UNALIGNED_SI_OP
878 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
879 #undef TARGET_ASM_UNALIGNED_DI_OP
880 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
883 #undef TARGET_ASM_UNALIGNED_HI_OP
884 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
885 #undef TARGET_ASM_UNALIGNED_SI_OP
886 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
887 #undef TARGET_ASM_UNALIGNED_DI_OP
888 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
889 #undef TARGET_ASM_ALIGNED_DI_OP
890 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
894 /* This hook deals with fixups for relocatable code and DI-mode objects
896 #undef TARGET_ASM_INTEGER
897 #define TARGET_ASM_INTEGER rs6000_assemble_integer
899 #ifdef HAVE_GAS_HIDDEN
900 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
901 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
904 #undef TARGET_HAVE_TLS
905 #define TARGET_HAVE_TLS HAVE_AS_TLS
907 #undef TARGET_CANNOT_FORCE_CONST_MEM
908 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
910 #undef TARGET_ASM_FUNCTION_PROLOGUE
911 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
912 #undef TARGET_ASM_FUNCTION_EPILOGUE
913 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
915 #undef TARGET_SCHED_VARIABLE_ISSUE
916 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
918 #undef TARGET_SCHED_ISSUE_RATE
919 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
920 #undef TARGET_SCHED_ADJUST_COST
921 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
922 #undef TARGET_SCHED_ADJUST_PRIORITY
923 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
924 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
925 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
926 #undef TARGET_SCHED_FINISH
927 #define TARGET_SCHED_FINISH rs6000_sched_finish
929 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
930 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
932 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
933 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
935 #undef TARGET_INIT_BUILTINS
936 #define TARGET_INIT_BUILTINS rs6000_init_builtins
938 #undef TARGET_EXPAND_BUILTIN
939 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
941 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
942 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
944 #undef TARGET_INIT_LIBFUNCS
945 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
948 #undef TARGET_BINDS_LOCAL_P
949 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
952 #undef TARGET_ASM_OUTPUT_MI_THUNK
953 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
955 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
956 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
958 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
959 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
961 #undef TARGET_RTX_COSTS
962 #define TARGET_RTX_COSTS rs6000_rtx_costs
963 #undef TARGET_ADDRESS_COST
964 #define TARGET_ADDRESS_COST hook_int_rtx_0
966 #undef TARGET_VECTOR_OPAQUE_P
967 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
969 #undef TARGET_DWARF_REGISTER_SPAN
970 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
972 /* On rs6000, function arguments are promoted, as are function return
974 #undef TARGET_PROMOTE_FUNCTION_ARGS
975 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
976 #undef TARGET_PROMOTE_FUNCTION_RETURN
977 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
979 #undef TARGET_RETURN_IN_MEMORY
980 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
982 #undef TARGET_SETUP_INCOMING_VARARGS
983 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
985 /* Always strict argument naming on rs6000. */
986 #undef TARGET_STRICT_ARGUMENT_NAMING
987 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
988 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
989 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
990 #undef TARGET_SPLIT_COMPLEX_ARG
991 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
992 #undef TARGET_MUST_PASS_IN_STACK
993 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
994 #undef TARGET_PASS_BY_REFERENCE
995 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
996 #undef TARGET_ARG_PARTIAL_BYTES
997 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
999 #undef TARGET_BUILD_BUILTIN_VA_LIST
1000 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1002 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1003 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1005 #undef TARGET_EH_RETURN_FILTER_MODE
1006 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1008 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1009 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1011 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1019 #undef TARGET_RELAXED_ORDERING
1020 #define TARGET_RELAXED_ORDERING true
1022 struct gcc_target targetm = TARGET_INITIALIZER;
1025 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1028 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1064 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1066 rs6000_init_hard_regno_mode_ok (void)
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1076 /* If not otherwise specified by a target, make 'long double' equivalent to
1079 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1083 /* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1087 rs6000_override_options (const char *default_cpu)
1090 struct rs6000_cpu_select *ptr;
1093 /* Simplifications for entries below. */
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
1103 complete description of the processor's support.
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
1113 } const processor_target_table[]
1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1115 {"403", PROCESSOR_PPC403,
1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1122 {"601", PROCESSOR_PPC601,
1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"970", PROCESSOR_POWER4,
1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1150 {"G5", PROCESSOR_POWER4,
1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1159 {"power5", PROCESSOR_POWER5,
1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1188 rs6000_init_hard_regno_mode_ok ();
1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1191 #ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1195 #ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1200 /* Don't override these by the processor default if given explicitly. */
1201 set_masks &= ~(target_flags_explicit
1202 & (MASK_MULTIPLE | MASK_STRING | MASK_SOFT_FLOAT));
1204 /* Identify the processor type. */
1205 rs6000_select[0].string = default_cpu;
1206 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1208 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1210 ptr = &rs6000_select[i];
1211 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1213 for (j = 0; j < ptt_size; j++)
1214 if (! strcmp (ptr->string, processor_target_table[j].name))
1216 if (ptr->set_tune_p)
1217 rs6000_cpu = processor_target_table[j].processor;
1219 if (ptr->set_arch_p)
1221 target_flags &= ~set_masks;
1222 target_flags |= (processor_target_table[j].target_enable
1229 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1236 /* If we are optimizing big endian systems for space, use the load/store
1237 multiple and string instructions. */
1238 if (BYTES_BIG_ENDIAN && optimize_size)
1239 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1241 /* Don't allow -mmultiple or -mstring on little endian systems
1242 unless the cpu is a 750, because the hardware doesn't support the
1243 instructions used in little endian mode, and causes an alignment
1244 trap. The 750 does not cause an alignment trap (except when the
1245 target is unaligned). */
1247 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1249 if (TARGET_MULTIPLE)
1251 target_flags &= ~MASK_MULTIPLE;
1252 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1253 warning ("-mmultiple is not supported on little endian systems");
1258 target_flags &= ~MASK_STRING;
1259 if ((target_flags_explicit & MASK_STRING) != 0)
1260 warning ("-mstring is not supported on little endian systems");
1264 /* Set debug flags */
1265 if (rs6000_debug_name)
1267 if (! strcmp (rs6000_debug_name, "all"))
1268 rs6000_debug_stack = rs6000_debug_arg = 1;
1269 else if (! strcmp (rs6000_debug_name, "stack"))
1270 rs6000_debug_stack = 1;
1271 else if (! strcmp (rs6000_debug_name, "arg"))
1272 rs6000_debug_arg = 1;
1274 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1277 if (rs6000_traceback_name)
1279 if (! strncmp (rs6000_traceback_name, "full", 4))
1280 rs6000_traceback = traceback_full;
1281 else if (! strncmp (rs6000_traceback_name, "part", 4))
1282 rs6000_traceback = traceback_part;
1283 else if (! strncmp (rs6000_traceback_name, "no", 2))
1284 rs6000_traceback = traceback_none;
1286 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1287 rs6000_traceback_name);
1290 /* Set size of long double */
1291 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1292 if (rs6000_long_double_size_string)
1295 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1296 if (*tail != '\0' || (size != 64 && size != 128))
1297 error ("Unknown switch -mlong-double-%s",
1298 rs6000_long_double_size_string);
1300 rs6000_long_double_type_size = size;
1303 /* Set Altivec ABI as default for powerpc64 linux. */
1304 if (TARGET_ELF && TARGET_64BIT)
1306 rs6000_altivec_abi = 1;
1307 rs6000_altivec_vrsave = 1;
1310 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1311 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1313 rs6000_darwin64_abi = 1;
1314 /* Setting to empty string is same as "-mone-byte-bool". */
1316 darwin_one_byte_bool = "";
1320 /* Handle -mabi= options. */
1321 rs6000_parse_abi_options ();
1323 /* Handle -malign-XXXXX option. */
1324 rs6000_parse_alignment_option ();
1326 rs6000_parse_float_gprs_option ();
1328 /* Handle generic -mFOO=YES/NO options. */
1329 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1330 &rs6000_altivec_vrsave);
1331 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1333 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1335 /* Handle -mtls-size option. */
1336 rs6000_parse_tls_size_option ();
1338 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1339 SUBTARGET_OVERRIDE_OPTIONS;
1341 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1342 SUBSUBTARGET_OVERRIDE_OPTIONS;
1344 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1345 SUB3TARGET_OVERRIDE_OPTIONS;
1351 error ("AltiVec and E500 instructions cannot coexist");
1353 /* The e500 does not have string instructions, and we set
1354 MASK_STRING above when optimizing for size. */
1355 if ((target_flags & MASK_STRING) != 0)
1356 target_flags = target_flags & ~MASK_STRING;
1358 /* No SPE means 64-bit long doubles, even if an E500. */
1359 if (rs6000_spe_string != 0
1360 && !strcmp (rs6000_spe_string, "no"))
1361 rs6000_long_double_type_size = 64;
1363 else if (rs6000_select[1].string != NULL)
1365 /* For the powerpc-eabispe configuration, we set all these by
1366 default, so let's unset them if we manually set another
1367 CPU that is not the E500. */
1368 if (rs6000_abi_string == 0)
1370 if (rs6000_spe_string == 0)
1372 if (rs6000_float_gprs_string == 0)
1373 rs6000_float_gprs = 0;
1374 if (rs6000_isel_string == 0)
1376 if (rs6000_long_double_size_string == 0)
1377 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1380 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1381 && rs6000_cpu != PROCESSOR_POWER5);
1382 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1383 || rs6000_cpu == PROCESSOR_POWER5);
1385 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1386 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1387 bits in target_flags so TARGET_SWITCHES cannot be used.
1388 Assumption here is that rs6000_longcall_switch points into the
1389 text of the complete option, rather than being a copy, so we can
1390 scan back for the presence or absence of the no- modifier. */
1391 if (rs6000_longcall_switch)
1393 const char *base = rs6000_longcall_switch;
1394 while (base[-1] != 'm') base--;
1396 if (*rs6000_longcall_switch != '\0')
1397 error ("invalid option %qs", base);
1398 rs6000_default_long_calls = (base[0] != 'n');
1401 /* Handle -m(no-)warn-altivec-long similarly. */
1402 if (rs6000_warn_altivec_long_switch)
1404 const char *base = rs6000_warn_altivec_long_switch;
1405 while (base[-1] != 'm') base--;
1407 if (*rs6000_warn_altivec_long_switch != '\0')
1408 error ("invalid option %qs", base);
1409 rs6000_warn_altivec_long = (base[0] != 'n');
1412 /* Handle -mprioritize-restricted-insns option. */
1413 rs6000_sched_restricted_insns_priority
1414 = (rs6000_sched_groups ? 1 : 0);
1415 if (rs6000_sched_restricted_insns_priority_str)
1416 rs6000_sched_restricted_insns_priority =
1417 atoi (rs6000_sched_restricted_insns_priority_str);
1419 /* Handle -msched-costly-dep option. */
1420 rs6000_sched_costly_dep
1421 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1422 if (rs6000_sched_costly_dep_str)
1424 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1425 rs6000_sched_costly_dep = no_dep_costly;
1426 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1427 rs6000_sched_costly_dep = all_deps_costly;
1428 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1429 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1430 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1431 rs6000_sched_costly_dep = store_to_load_dep_costly;
1433 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1436 /* Handle -minsert-sched-nops option. */
1437 rs6000_sched_insert_nops
1438 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1439 if (rs6000_sched_insert_nops_str)
1441 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1442 rs6000_sched_insert_nops = sched_finish_none;
1443 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1444 rs6000_sched_insert_nops = sched_finish_pad_groups;
1445 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1446 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1448 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1451 #ifdef TARGET_REGNAMES
1452 /* If the user desires alternate register names, copy in the
1453 alternate names now. */
1454 if (TARGET_REGNAMES)
1455 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1458 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1459 If -maix-struct-return or -msvr4-struct-return was explicitly
1460 used, don't override with the ABI default. */
1461 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1463 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1464 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1466 target_flags |= MASK_AIX_STRUCT_RET;
1469 if (TARGET_LONG_DOUBLE_128
1470 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1471 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1473 /* Allocate an alias set for register saves & restores from stack. */
1474 rs6000_sr_alias_set = new_alias_set ();
1477 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1479 /* We can only guarantee the availability of DI pseudo-ops when
1480 assembling for 64-bit targets. */
1483 targetm.asm_out.aligned_op.di = NULL;
1484 targetm.asm_out.unaligned_op.di = NULL;
1487 /* Set branch target alignment, if not optimizing for size. */
1490 if (rs6000_sched_groups)
1492 if (align_functions <= 0)
1493 align_functions = 16;
1494 if (align_jumps <= 0)
1496 if (align_loops <= 0)
1499 if (align_jumps_max_skip <= 0)
1500 align_jumps_max_skip = 15;
1501 if (align_loops_max_skip <= 0)
1502 align_loops_max_skip = 15;
1505 /* Arrange to save and restore machine status around nested functions. */
1506 init_machine_status = rs6000_init_machine_status;
1508 /* We should always be splitting complex arguments, but we can't break
1509 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1510 if (DEFAULT_ABI != ABI_AIX)
1511 targetm.calls.split_complex_arg = NULL;
1513 /* Initialize rs6000_cost with the appropriate target costs. */
1515 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1519 case PROCESSOR_RIOS1:
1520 rs6000_cost = &rios1_cost;
1523 case PROCESSOR_RIOS2:
1524 rs6000_cost = &rios2_cost;
1527 case PROCESSOR_RS64A:
1528 rs6000_cost = &rs64a_cost;
1531 case PROCESSOR_MPCCORE:
1532 rs6000_cost = &mpccore_cost;
1535 case PROCESSOR_PPC403:
1536 rs6000_cost = &ppc403_cost;
1539 case PROCESSOR_PPC405:
1540 rs6000_cost = &ppc405_cost;
1543 case PROCESSOR_PPC440:
1544 rs6000_cost = &ppc440_cost;
1547 case PROCESSOR_PPC601:
1548 rs6000_cost = &ppc601_cost;
1551 case PROCESSOR_PPC603:
1552 rs6000_cost = &ppc603_cost;
1555 case PROCESSOR_PPC604:
1556 rs6000_cost = &ppc604_cost;
1559 case PROCESSOR_PPC604e:
1560 rs6000_cost = &ppc604e_cost;
1563 case PROCESSOR_PPC620:
1564 rs6000_cost = &ppc620_cost;
1567 case PROCESSOR_PPC630:
1568 rs6000_cost = &ppc630_cost;
1571 case PROCESSOR_PPC750:
1572 case PROCESSOR_PPC7400:
1573 rs6000_cost = &ppc750_cost;
1576 case PROCESSOR_PPC7450:
1577 rs6000_cost = &ppc7450_cost;
1580 case PROCESSOR_PPC8540:
1581 rs6000_cost = &ppc8540_cost;
1584 case PROCESSOR_POWER4:
1585 case PROCESSOR_POWER5:
1586 rs6000_cost = &power4_cost;
1594 /* Implement targetm.vectorize.builtin_mask_for_load. */
1596 rs6000_builtin_mask_for_load (void)
1599 return altivec_builtin_mask_for_load;
1604 /* Handle generic options of the form -mfoo=yes/no.
1605 NAME is the option name.
1606 VALUE is the option value.
1607 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1608 whether the option value is 'yes' or 'no' respectively. */
1610 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1614 else if (!strcmp (value, "yes"))
1616 else if (!strcmp (value, "no"))
1619 error ("unknown -m%s= option specified: '%s'", name, value);
1622 /* Handle -mabi= options. */
1624 rs6000_parse_abi_options (void)
1626 if (rs6000_abi_string == 0)
1628 else if (! strcmp (rs6000_abi_string, "altivec"))
1630 rs6000_altivec_abi = 1;
1633 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1634 rs6000_altivec_abi = 0;
1635 else if (! strcmp (rs6000_abi_string, "spe"))
1638 rs6000_altivec_abi = 0;
1639 if (!TARGET_SPE_ABI)
1640 error ("not configured for ABI: '%s'", rs6000_abi_string);
1643 /* These are here for testing during development only, do not
1644 document in the manual please. */
1645 else if (! strcmp (rs6000_abi_string, "d64"))
1647 rs6000_darwin64_abi = 1;
1648 warning ("Using darwin64 ABI");
1650 else if (! strcmp (rs6000_abi_string, "d32"))
1652 rs6000_darwin64_abi = 0;
1653 warning ("Using old darwin ABI");
1656 else if (! strcmp (rs6000_abi_string, "no-spe"))
1659 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1662 /* Handle -mfloat-gprs= options. */
1664 rs6000_parse_float_gprs_option (void)
1666 if (rs6000_float_gprs_string == 0)
1668 else if (! strcmp (rs6000_float_gprs_string, "yes")
1669 || ! strcmp (rs6000_float_gprs_string, "single"))
1670 rs6000_float_gprs = 1;
1671 else if (! strcmp (rs6000_float_gprs_string, "double"))
1672 rs6000_float_gprs = 2;
1673 else if (! strcmp (rs6000_float_gprs_string, "no"))
1674 rs6000_float_gprs = 0;
1676 error ("invalid option for -mfloat-gprs");
1679 /* Handle -malign-XXXXXX options. */
1681 rs6000_parse_alignment_option (void)
1683 if (rs6000_alignment_string == 0)
1685 else if (! strcmp (rs6000_alignment_string, "power"))
1686 rs6000_alignment_flags = MASK_ALIGN_POWER;
1687 else if (! strcmp (rs6000_alignment_string, "natural"))
1688 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1690 error ("unknown -malign-XXXXX option specified: '%s'",
1691 rs6000_alignment_string);
1694 /* Validate and record the size specified with the -mtls-size option. */
1697 rs6000_parse_tls_size_option (void)
1699 if (rs6000_tls_size_string == 0)
1701 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1702 rs6000_tls_size = 16;
1703 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1704 rs6000_tls_size = 32;
1705 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1706 rs6000_tls_size = 64;
1708 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1712 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1716 /* Do anything needed at the start of the asm file. */
1719 rs6000_file_start (void)
1723 const char *start = buffer;
1724 struct rs6000_cpu_select *ptr;
1725 const char *default_cpu = TARGET_CPU_DEFAULT;
1726 FILE *file = asm_out_file;
1728 default_file_start ();
1730 #ifdef TARGET_BI_ARCH
1731 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1735 if (flag_verbose_asm)
1737 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1738 rs6000_select[0].string = default_cpu;
1740 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1742 ptr = &rs6000_select[i];
1743 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1745 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1750 #ifdef USING_ELFOS_H
1751 switch (rs6000_sdata)
1753 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1754 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1755 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1756 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1759 if (rs6000_sdata && g_switch_value)
1761 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1773 /* Return nonzero if this function is known to have a null epilogue. */
1776 direct_return (void)
1778 if (reload_completed)
1780 rs6000_stack_t *info = rs6000_stack_info ();
1782 if (info->first_gp_reg_save == 32
1783 && info->first_fp_reg_save == 64
1784 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1785 && ! info->lr_save_p
1786 && ! info->cr_save_p
1787 && info->vrsave_mask == 0
1795 /* Returns 1 always. */
1798 any_operand (rtx op ATTRIBUTE_UNUSED,
1799 enum machine_mode mode ATTRIBUTE_UNUSED)
1804 /* Returns 1 always. */
1807 any_parallel_operand (rtx op ATTRIBUTE_UNUSED,
1808 enum machine_mode mode ATTRIBUTE_UNUSED)
1813 /* Returns 1 if op is the count register. */
1816 count_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1818 if (GET_CODE (op) != REG)
1821 if (REGNO (op) == COUNT_REGISTER_REGNUM)
1824 if (REGNO (op) > FIRST_PSEUDO_REGISTER)
1830 /* Returns 1 if op is an altivec register. */
1833 altivec_register_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1835 return (register_operand (op, mode)
1836 && (GET_CODE (op) != REG
1837 || REGNO (op) > FIRST_PSEUDO_REGISTER
1838 || ALTIVEC_REGNO_P (REGNO (op))));
1842 xer_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1844 if (GET_CODE (op) != REG)
1847 if (XER_REGNO_P (REGNO (op)))
1853 /* Return 1 if OP is a signed 8-bit constant. Int multiplication
1854 by such constants completes more quickly. */
1857 s8bit_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1859 return (GET_CODE (op) == CONST_INT
1860 && (INTVAL (op) >= -128 && INTVAL (op) <= 127));
1863 /* Return 1 if OP is a constant that can fit in a D field. */
1866 short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1868 return (GET_CODE (op) == CONST_INT
1869 && CONST_OK_FOR_LETTER_P (INTVAL (op), 'I'));
1872 /* Similar for an unsigned D field. */
1875 u_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1877 return (GET_CODE (op) == CONST_INT
1878 && CONST_OK_FOR_LETTER_P (INTVAL (op) & GET_MODE_MASK (mode), 'K'));
1881 /* Return 1 if OP is a CONST_INT that cannot fit in a signed D field. */
1884 non_short_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1886 return (GET_CODE (op) == CONST_INT
1887 && (unsigned HOST_WIDE_INT) (INTVAL (op) + 0x8000) >= 0x10000);
1890 /* Returns 1 if OP is a CONST_INT that is a positive value
1891 and an exact power of 2. */
1894 exact_log2_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1896 return (GET_CODE (op) == CONST_INT
1898 && exact_log2 (INTVAL (op)) >= 0);
1901 /* Returns 1 if OP is a register that is not special (i.e., not MQ,
1905 gpc_reg_operand (rtx op, enum machine_mode mode)
1907 return (register_operand (op, mode)
1908 && (GET_CODE (op) != REG
1909 || (REGNO (op) >= ARG_POINTER_REGNUM
1910 && !XER_REGNO_P (REGNO (op)))
1911 || REGNO (op) < MQ_REGNO));
1914 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1918 cc_reg_operand (rtx op, enum machine_mode mode)
1920 return (register_operand (op, mode)
1921 && (GET_CODE (op) != REG
1922 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1923 || CR_REGNO_P (REGNO (op))));
1926 /* Returns 1 if OP is either a pseudo-register or a register denoting a
1927 CR field that isn't CR0. */
1930 cc_reg_not_cr0_operand (rtx op, enum machine_mode mode)
1932 return (register_operand (op, mode)
1933 && (GET_CODE (op) != REG
1934 || REGNO (op) >= FIRST_PSEUDO_REGISTER
1935 || CR_REGNO_NOT_CR0_P (REGNO (op))));
1938 /* Returns 1 if OP is either a constant integer valid for a D-field or
1939 a non-special register. If a register, it must be in the proper
1940 mode unless MODE is VOIDmode. */
1943 reg_or_short_operand (rtx op, enum machine_mode mode)
1945 return short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1948 /* Similar, except check if the negation of the constant would be
1949 valid for a D-field. Don't allow a constant zero, since all the
1950 patterns that call this predicate use "addic r1,r2,-constant" on
1951 a constant value to set a carry when r2 is greater or equal to
1952 "constant". That doesn't work for zero. */
1955 reg_or_neg_short_operand (rtx op, enum machine_mode mode)
1957 if (GET_CODE (op) == CONST_INT)
1958 return CONST_OK_FOR_LETTER_P (INTVAL (op), 'P') && INTVAL (op) != 0;
1960 return gpc_reg_operand (op, mode);
1963 /* Returns 1 if OP is either a constant integer valid for a DS-field or
1964 a non-special register. If a register, it must be in the proper
1965 mode unless MODE is VOIDmode. */
1968 reg_or_aligned_short_operand (rtx op, enum machine_mode mode)
1970 if (gpc_reg_operand (op, mode))
1972 else if (short_cint_operand (op, mode) && !(INTVAL (op) & 3))
1979 /* Return 1 if the operand is either a register or an integer whose
1980 high-order 16 bits are zero. */
1983 reg_or_u_short_operand (rtx op, enum machine_mode mode)
1985 return u_short_cint_operand (op, mode) || gpc_reg_operand (op, mode);
1988 /* Return 1 is the operand is either a non-special register or ANY
1989 constant integer. */
1992 reg_or_cint_operand (rtx op, enum machine_mode mode)
1994 return (GET_CODE (op) == CONST_INT || gpc_reg_operand (op, mode));
1997 /* Return 1 is the operand is either a non-special register or ANY
1998 32-bit signed constant integer. */
2001 reg_or_arith_cint_operand (rtx op, enum machine_mode mode)
2003 return (gpc_reg_operand (op, mode)
2004 || (GET_CODE (op) == CONST_INT
2005 #if HOST_BITS_PER_WIDE_INT != 32
2006 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80000000)
2007 < (unsigned HOST_WIDE_INT) 0x100000000ll)
2012 /* Return 1 is the operand is either a non-special register or a 32-bit
2013 signed constant integer valid for 64-bit addition. */
2016 reg_or_add_cint64_operand (rtx op, enum machine_mode mode)
2018 return (gpc_reg_operand (op, mode)
2019 || (GET_CODE (op) == CONST_INT
2020 #if HOST_BITS_PER_WIDE_INT == 32
2021 && INTVAL (op) < 0x7fff8000
2023 && ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
2029 /* Return 1 is the operand is either a non-special register or a 32-bit
2030 signed constant integer valid for 64-bit subtraction. */
2033 reg_or_sub_cint64_operand (rtx op, enum machine_mode mode)
2035 return (gpc_reg_operand (op, mode)
2036 || (GET_CODE (op) == CONST_INT
2037 #if HOST_BITS_PER_WIDE_INT == 32
2038 && (- INTVAL (op)) < 0x7fff8000
2040 && ((unsigned HOST_WIDE_INT) ((- INTVAL (op)) + 0x80008000)
2046 /* Return 1 is the operand is either a non-special register or ANY
2047 32-bit unsigned constant integer. */
2050 reg_or_logical_cint_operand (rtx op, enum machine_mode mode)
2052 if (GET_CODE (op) == CONST_INT)
2054 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
2056 if (GET_MODE_BITSIZE (mode) <= 32)
2059 if (INTVAL (op) < 0)
2063 return ((INTVAL (op) & GET_MODE_MASK (mode)
2064 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0);
2066 else if (GET_CODE (op) == CONST_DOUBLE)
2068 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2072 return CONST_DOUBLE_HIGH (op) == 0;
2075 return gpc_reg_operand (op, mode);
2078 /* Return 1 if the operand is an operand that can be loaded via the GOT. */
2081 got_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2083 return (GET_CODE (op) == SYMBOL_REF
2084 || GET_CODE (op) == CONST
2085 || GET_CODE (op) == LABEL_REF);
2088 /* Return 1 if the operand is a simple references that can be loaded via
2089 the GOT (labels involving addition aren't allowed). */
2092 got_no_const_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2094 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF);
2097 /* Return the number of instructions it takes to form a constant in an
2098 integer register. */
2101 num_insns_constant_wide (HOST_WIDE_INT value)
2103 /* signed constant loadable with {cal|addi} */
2104 if (CONST_OK_FOR_LETTER_P (value, 'I'))
2107 /* constant loadable with {cau|addis} */
2108 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
2111 #if HOST_BITS_PER_WIDE_INT == 64
2112 else if (TARGET_POWERPC64)
2114 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2115 HOST_WIDE_INT high = value >> 31;
2117 if (high == 0 || high == -1)
2123 return num_insns_constant_wide (high) + 1;
2125 return (num_insns_constant_wide (high)
2126 + num_insns_constant_wide (low) + 1);
2135 num_insns_constant (rtx op, enum machine_mode mode)
2137 if (GET_CODE (op) == CONST_INT)
2139 #if HOST_BITS_PER_WIDE_INT == 64
2140 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2141 && mask64_operand (op, mode))
2145 return num_insns_constant_wide (INTVAL (op));
2148 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
2153 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2154 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2155 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2158 else if (GET_CODE (op) == CONST_DOUBLE)
2164 int endian = (WORDS_BIG_ENDIAN == 0);
2166 if (mode == VOIDmode || mode == DImode)
2168 high = CONST_DOUBLE_HIGH (op);
2169 low = CONST_DOUBLE_LOW (op);
2173 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2174 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2176 low = l[1 - endian];
2180 return (num_insns_constant_wide (low)
2181 + num_insns_constant_wide (high));
2185 if (high == 0 && low >= 0)
2186 return num_insns_constant_wide (low);
2188 else if (high == -1 && low < 0)
2189 return num_insns_constant_wide (low);
2191 else if (mask64_operand (op, mode))
2195 return num_insns_constant_wide (high) + 1;
2198 return (num_insns_constant_wide (high)
2199 + num_insns_constant_wide (low) + 1);
2207 /* Return 1 if the operand is a CONST_DOUBLE and it can be put into a
2208 register with one instruction per word. We only do this if we can
2209 safely read CONST_DOUBLE_{LOW,HIGH}. */
2212 easy_fp_constant (rtx op, enum machine_mode mode)
2214 if (GET_CODE (op) != CONST_DOUBLE
2215 || GET_MODE (op) != mode
2216 || (GET_MODE_CLASS (mode) != MODE_FLOAT && mode != DImode))
2219 /* Consider all constants with -msoft-float to be easy. */
2220 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE)
2224 /* If we are using V.4 style PIC, consider all constants to be hard. */
2225 if (flag_pic && DEFAULT_ABI == ABI_V4)
2228 #ifdef TARGET_RELOCATABLE
2229 /* Similarly if we are using -mrelocatable, consider all constants
2231 if (TARGET_RELOCATABLE)
2240 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2241 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
2243 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2244 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
2245 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
2246 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
2249 else if (mode == DFmode)
2254 if (TARGET_E500_DOUBLE)
2257 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2258 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
2260 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
2261 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
2264 else if (mode == SFmode)
2269 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2270 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2272 return num_insns_constant_wide (l) == 1;
2275 else if (mode == DImode)
2276 return ((TARGET_POWERPC64
2277 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
2278 || (num_insns_constant (op, DImode) <= 2));
2280 else if (mode == SImode)
2286 /* Returns the constant for the splat instruction, if exists. */
2289 easy_vector_splat_const (int cst, enum machine_mode mode)
2294 if (EASY_VECTOR_15 (cst)
2295 || EASY_VECTOR_15_ADD_SELF (cst))
2297 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2303 if (EASY_VECTOR_15 (cst)
2304 || EASY_VECTOR_15_ADD_SELF (cst))
2306 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2312 if (EASY_VECTOR_15 (cst)
2313 || EASY_VECTOR_15_ADD_SELF (cst))
2322 /* Return nonzero if all elements of a vector have the same value. */
2325 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2329 units = CONST_VECTOR_NUNITS (op);
2331 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2332 for (i = 1; i < units; ++i)
2333 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2335 if (i == units && easy_vector_splat_const (cst, mode))
2340 /* Return 1 if the operand is a CONST_INT and can be put into a
2341 register without using memory. */
2344 easy_vector_constant (rtx op, enum machine_mode mode)
2348 if (GET_CODE (op) != CONST_VECTOR
2353 if (zero_constant (op, mode)
2354 && ((TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
2355 || (TARGET_SPE && SPE_VECTOR_MODE (mode))))
2358 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
2361 if (TARGET_SPE && mode == V1DImode)
2364 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2365 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
2367 /* Limit SPE vectors to 15 bits signed. These we can generate with:
2369 evmergelo r0, r0, r0
2372 I don't know how efficient it would be to allow bigger constants,
2373 considering we'll have an extra 'ori' for every 'li'. I doubt 5
2374 instructions is better than a 64-bit memory load, but I don't
2375 have the e500 timing specs. */
2376 if (TARGET_SPE && mode == V2SImode
2377 && cst >= -0x7fff && cst <= 0x7fff
2378 && cst2 >= -0x7fff && cst2 <= 0x7fff)
2382 && easy_vector_same (op, mode))
2384 cst = easy_vector_splat_const (cst, mode);
2385 if (EASY_VECTOR_15_ADD_SELF (cst)
2386 || EASY_VECTOR_15 (cst))
2392 /* Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF. */
2395 easy_vector_constant_add_self (rtx op, enum machine_mode mode)
2399 && GET_CODE (op) == CONST_VECTOR
2400 && easy_vector_same (op, mode))
2402 cst = easy_vector_splat_const (INTVAL (CONST_VECTOR_ELT (op, 0)), mode);
2403 if (EASY_VECTOR_15_ADD_SELF (cst))
2409 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2412 gen_easy_vector_constant_add_self (rtx op)
2416 units = GET_MODE_NUNITS (GET_MODE (op));
2417 v = rtvec_alloc (units);
2419 for (i = 0; i < units; i++)
2421 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2422 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2426 output_vec_const_move (rtx *operands)
2429 enum machine_mode mode;
2435 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2436 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2437 mode = GET_MODE (dest);
2441 if (zero_constant (vec, mode))
2442 return "vxor %0,%0,%0";
2443 else if (easy_vector_constant (vec, mode))
2445 operands[1] = GEN_INT (cst);
2449 if (EASY_VECTOR_15 (cst))
2451 operands[1] = GEN_INT (cst);
2452 return "vspltisw %0,%1";
2454 else if (EASY_VECTOR_15_ADD_SELF (cst))
2460 if (EASY_VECTOR_15 (cst))
2462 operands[1] = GEN_INT (cst);
2463 return "vspltish %0,%1";
2465 else if (EASY_VECTOR_15_ADD_SELF (cst))
2471 if (EASY_VECTOR_15 (cst))
2473 operands[1] = GEN_INT (cst);
2474 return "vspltisb %0,%1";
2476 else if (EASY_VECTOR_15_ADD_SELF (cst))
2489 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2490 pattern of V1DI, V4HI, and V2SF.
2492 FIXME: We should probably return # and add post reload
2493 splitters for these, but this way is so easy ;-). */
2494 operands[1] = GEN_INT (cst);
2495 operands[2] = GEN_INT (cst2);
2497 return "li %0,%1\n\tevmergelo %0,%0,%0";
2499 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2505 /* Return 1 if the operand is the constant 0. This works for scalars
2506 as well as vectors. */
2508 zero_constant (rtx op, enum machine_mode mode)
2510 return op == CONST0_RTX (mode);
2513 /* Return 1 if the operand is 0.0. */
2515 zero_fp_constant (rtx op, enum machine_mode mode)
2517 return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
2520 /* Return 1 if the operand is in volatile memory. Note that during
2521 the RTL generation phase, memory_operand does not return TRUE for
2522 volatile memory references. So this function allows us to
2523 recognize volatile references where its safe. */
2526 volatile_mem_operand (rtx op, enum machine_mode mode)
2528 if (GET_CODE (op) != MEM)
2531 if (!MEM_VOLATILE_P (op))
2534 if (mode != GET_MODE (op))
2537 if (reload_completed)
2538 return memory_operand (op, mode);
2540 if (reload_in_progress)
2541 return strict_memory_address_p (mode, XEXP (op, 0));
2543 return memory_address_p (mode, XEXP (op, 0));
2546 /* Return 1 if the operand is an offsettable memory operand. */
2549 offsettable_mem_operand (rtx op, enum machine_mode mode)
2551 return ((GET_CODE (op) == MEM)
2552 && offsettable_address_p (reload_completed || reload_in_progress,
2553 mode, XEXP (op, 0)));
2556 /* Return 1 if the operand is either an easy FP constant (see above) or
2560 mem_or_easy_const_operand (rtx op, enum machine_mode mode)
2562 return memory_operand (op, mode) || easy_fp_constant (op, mode);
2565 /* Return 1 if the operand is either a non-special register or an item
2566 that can be used as the operand of a `mode' add insn. */
2569 add_operand (rtx op, enum machine_mode mode)
2571 if (GET_CODE (op) == CONST_INT)
2572 return (CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2573 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2575 return gpc_reg_operand (op, mode);
2578 /* Return 1 if OP is a constant but not a valid add_operand. */
2581 non_add_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2583 return (GET_CODE (op) == CONST_INT
2584 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
2585 && !CONST_OK_FOR_LETTER_P (INTVAL (op), 'L'));
2588 /* Return 1 if the operand is a non-special register or a constant that
2589 can be used as the operand of an OR or XOR insn on the RS/6000. */
2592 logical_operand (rtx op, enum machine_mode mode)
2594 HOST_WIDE_INT opl, oph;
2596 if (gpc_reg_operand (op, mode))
2599 if (GET_CODE (op) == CONST_INT)
2601 opl = INTVAL (op) & GET_MODE_MASK (mode);
2603 #if HOST_BITS_PER_WIDE_INT <= 32
2604 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
2608 else if (GET_CODE (op) == CONST_DOUBLE)
2610 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
2613 opl = CONST_DOUBLE_LOW (op);
2614 oph = CONST_DOUBLE_HIGH (op);
2621 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
2622 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
2625 /* Return 1 if C is a constant that is not a logical operand (as
2626 above), but could be split into one. */
2629 non_logical_cint_operand (rtx op, enum machine_mode mode)
2631 return ((GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE)
2632 && ! logical_operand (op, mode)
2633 && reg_or_logical_cint_operand (op, mode));
2636 /* Return 1 if C is a constant that can be encoded in a 32-bit mask on the
2637 RS/6000. It is if there are no more than two 1->0 or 0->1 transitions.
2638 Reject all ones and all zeros, since these should have been optimized
2639 away and confuse the making of MB and ME. */
2642 mask_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2644 HOST_WIDE_INT c, lsb;
2646 if (GET_CODE (op) != CONST_INT)
2651 /* Fail in 64-bit mode if the mask wraps around because the upper
2652 32-bits of the mask will all be 1s, contrary to GCC's internal view. */
2653 if (TARGET_POWERPC64 && (c & 0x80000001) == 0x80000001)
2656 /* We don't change the number of transitions by inverting,
2657 so make sure we start with the LS bit zero. */
2661 /* Reject all zeros or all ones. */
2665 /* Find the first transition. */
2668 /* Invert to look for a second transition. */
2671 /* Erase first transition. */
2674 /* Find the second transition (if any). */
2677 /* Match if all the bits above are 1's (or c is zero). */
2681 /* Return 1 for the PowerPC64 rlwinm corner case. */
2684 mask_operand_wrap (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2686 HOST_WIDE_INT c, lsb;
2688 if (GET_CODE (op) != CONST_INT)
2693 if ((c & 0x80000001) != 0x80000001)
2707 /* Return 1 if the operand is a constant that is a PowerPC64 mask.
2708 It is if there are no more than one 1->0 or 0->1 transitions.
2709 Reject all zeros, since zero should have been optimized away and
2710 confuses the making of MB and ME. */
2713 mask64_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2715 if (GET_CODE (op) == CONST_INT)
2717 HOST_WIDE_INT c, lsb;
2721 /* Reject all zeros. */
2725 /* We don't change the number of transitions by inverting,
2726 so make sure we start with the LS bit zero. */
2730 /* Find the transition, and check that all bits above are 1's. */
2733 /* Match if all the bits above are 1's (or c is zero). */
2740 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2743 if (GET_CODE (op) == CONST_INT)
2745 HOST_WIDE_INT c, lsb;
2750 /* Disallow all zeros. */
2754 /* We can use a single rlwinm insn if no upper bits of C are set
2755 AND there are zero, one or two transitions in the _whole_ of
2757 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2759 /* We don't change the number of transitions by inverting,
2760 so make sure we start with the LS bit zero. */
2764 /* Find the first transition. */
2767 /* Invert to look for a second transition. */
2770 /* Erase first transition. */
2773 /* Find the second transition. */
2776 /* Invert to look for a third transition. */
2779 /* Erase second transition. */
2782 if (one_ok && !(allow_one || c))
2785 /* Find the third transition (if any). */
2788 /* Match if all the bits above are 1's (or c is zero). */
2794 /* Like mask64_operand, but allow up to three transitions. This
2795 predicate is used by insn patterns that generate two rldicl or
2796 rldicr machine insns. */
2797 int mask64_2_operand (rtx op, enum machine_mode mode)
2799 return mask64_1or2_operand (op, mode, false);
2802 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2803 implement ANDing by the mask IN. */
2805 build_mask64_2_operands (rtx in, rtx *out)
2807 #if HOST_BITS_PER_WIDE_INT >= 64
2808 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2811 if (GET_CODE (in) != CONST_INT)
2817 /* Assume c initially something like 0x00fff000000fffff. The idea
2818 is to rotate the word so that the middle ^^^^^^ group of zeros
2819 is at the MS end and can be cleared with an rldicl mask. We then
2820 rotate back and clear off the MS ^^ group of zeros with a
2822 c = ~c; /* c == 0xff000ffffff00000 */
2823 lsb = c & -c; /* lsb == 0x0000000000100000 */
2824 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2825 c = ~c; /* c == 0x00fff000000fffff */
2826 c &= -lsb; /* c == 0x00fff00000000000 */
2827 lsb = c & -c; /* lsb == 0x0000100000000000 */
2828 c = ~c; /* c == 0xff000fffffffffff */
2829 c &= -lsb; /* c == 0xff00000000000000 */
2831 while ((lsb >>= 1) != 0)
2832 shift++; /* shift == 44 on exit from loop */
2833 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2834 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2835 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2839 /* Assume c initially something like 0xff000f0000000000. The idea
2840 is to rotate the word so that the ^^^ middle group of zeros
2841 is at the LS end and can be cleared with an rldicr mask. We then
2842 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2844 lsb = c & -c; /* lsb == 0x0000010000000000 */
2845 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2846 c = ~c; /* c == 0x00fff0ffffffffff */
2847 c &= -lsb; /* c == 0x00fff00000000000 */
2848 lsb = c & -c; /* lsb == 0x0000100000000000 */
2849 c = ~c; /* c == 0xff000fffffffffff */
2850 c &= -lsb; /* c == 0xff00000000000000 */
2852 while ((lsb >>= 1) != 0)
2853 shift++; /* shift == 44 on exit from loop */
2854 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2855 m1 >>= shift; /* m1 == 0x0000000000000fff */
2856 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2859 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2860 masks will be all 1's. We are guaranteed more than one transition. */
2861 out[0] = GEN_INT (64 - shift);
2862 out[1] = GEN_INT (m1);
2863 out[2] = GEN_INT (shift);
2864 out[3] = GEN_INT (m2);
2872 /* Return 1 if the operand is either a non-special register or a constant
2873 that can be used as the operand of a PowerPC64 logical AND insn. */
2876 and64_operand (rtx op, enum machine_mode mode)
2878 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2879 return (gpc_reg_operand (op, mode) || mask64_operand (op, mode));
2881 return (logical_operand (op, mode) || mask64_operand (op, mode));
2884 /* Like the above, but also match constants that can be implemented
2885 with two rldicl or rldicr insns. */
2888 and64_2_operand (rtx op, enum machine_mode mode)
2890 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2891 return gpc_reg_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2893 return logical_operand (op, mode) || mask64_1or2_operand (op, mode, true);
2896 /* Return 1 if the operand is either a non-special register or a
2897 constant that can be used as the operand of an RS/6000 logical AND insn. */
2900 and_operand (rtx op, enum machine_mode mode)
2902 if (fixed_regs[CR0_REGNO]) /* CR0 not available, don't do andi./andis. */
2903 return (gpc_reg_operand (op, mode) || mask_operand (op, mode));
2905 return (logical_operand (op, mode) || mask_operand (op, mode));
2908 /* Return 1 if the operand is a general register or memory operand. */
2911 reg_or_mem_operand (rtx op, enum machine_mode mode)
2913 return (gpc_reg_operand (op, mode)
2914 || memory_operand (op, mode)
2915 || macho_lo_sum_memory_operand (op, mode)
2916 || volatile_mem_operand (op, mode));
2919 /* Return 1 if the operand is a general register or memory operand without
2920 pre_inc or pre_dec which produces invalid form of PowerPC lwa
2924 lwa_operand (rtx op, enum machine_mode mode)
2928 if (reload_completed && GET_CODE (inner) == SUBREG)
2929 inner = SUBREG_REG (inner);
2931 return gpc_reg_operand (inner, mode)
2932 || (memory_operand (inner, mode)
2933 && GET_CODE (XEXP (inner, 0)) != PRE_INC
2934 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
2935 && (GET_CODE (XEXP (inner, 0)) != PLUS
2936 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
2937 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
2940 /* Return 1 if the operand, used inside a MEM, is a SYMBOL_REF. */
2943 symbol_ref_operand (rtx op, enum machine_mode mode)
2945 if (mode != VOIDmode && GET_MODE (op) != mode)
2948 return (GET_CODE (op) == SYMBOL_REF
2949 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op)));
2952 /* Return 1 if the operand, used inside a MEM, is a valid first argument
2953 to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR. */
2956 call_operand (rtx op, enum machine_mode mode)
2958 if (mode != VOIDmode && GET_MODE (op) != mode)
2961 return (GET_CODE (op) == SYMBOL_REF
2962 || (GET_CODE (op) == REG
2963 && (REGNO (op) == LINK_REGISTER_REGNUM
2964 || REGNO (op) == COUNT_REGISTER_REGNUM
2965 || REGNO (op) >= FIRST_PSEUDO_REGISTER)));
2968 /* Return 1 if the operand is a SYMBOL_REF for a function known to be in
2972 current_file_function_operand (rtx op,
2973 enum machine_mode mode ATTRIBUTE_UNUSED)
2975 return (GET_CODE (op) == SYMBOL_REF
2976 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
2977 && (SYMBOL_REF_LOCAL_P (op)
2978 || (DECL_RTL_SET_P (current_function_decl)
2979 && op == XEXP (DECL_RTL (current_function_decl), 0))));
2982 /* Return 1 if this operand is a valid input for a move insn. */
2985 input_operand (rtx op, enum machine_mode mode)
2987 /* Memory is always valid. */
2988 if (memory_operand (op, mode))
2991 /* For floating-point, easy constants are valid. */
2992 if (GET_MODE_CLASS (mode) == MODE_FLOAT
2994 && easy_fp_constant (op, mode))
2997 /* Allow any integer constant. */
2998 if (GET_MODE_CLASS (mode) == MODE_INT
2999 && (GET_CODE (op) == CONST_INT
3000 || GET_CODE (op) == CONST_DOUBLE))
3003 /* Allow easy vector constants. */
3004 if (GET_CODE (op) == CONST_VECTOR
3005 && easy_vector_constant (op, mode))
3008 /* For floating-point or multi-word mode, the only remaining valid type
3010 if (GET_MODE_CLASS (mode) == MODE_FLOAT
3011 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
3012 return register_operand (op, mode);
3014 /* The only cases left are integral modes one word or smaller (we
3015 do not get called for MODE_CC values). These can be in any
3017 if (register_operand (op, mode))
3020 /* A SYMBOL_REF referring to the TOC is valid. */
3021 if (legitimate_constant_pool_address_p (op))
3024 /* A constant pool expression (relative to the TOC) is valid */
3025 if (toc_relative_expr_p (op))
3028 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
3030 if (DEFAULT_ABI == ABI_V4
3031 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
3032 && small_data_operand (op, Pmode))
3039 /* Darwin, AIX increases natural record alignment to doubleword if the first
3040 field is an FP double while the FP fields remain word aligned. */
3043 rs6000_special_round_type_align (tree type, int computed, int specified)
3045 tree field = TYPE_FIELDS (type);
3047 /* Skip all non field decls */
3048 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3049 field = TREE_CHAIN (field);
3051 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
3052 return MAX (computed, specified);
3054 return MAX (MAX (computed, specified), 64);
3057 /* Return 1 for an operand in small memory on V.4/eabi. */
3060 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3061 enum machine_mode mode ATTRIBUTE_UNUSED)
3066 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3069 if (DEFAULT_ABI != ABI_V4)
3072 if (GET_CODE (op) == SYMBOL_REF)
3075 else if (GET_CODE (op) != CONST
3076 || GET_CODE (XEXP (op, 0)) != PLUS
3077 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3078 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3083 rtx sum = XEXP (op, 0);
3084 HOST_WIDE_INT summand;
3086 /* We have to be careful here, because it is the referenced address
3087 that must be 32k from _SDA_BASE_, not just the symbol. */
3088 summand = INTVAL (XEXP (sum, 1));
3089 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3092 sym_ref = XEXP (sum, 0);
3095 return SYMBOL_REF_SMALL_P (sym_ref);
3101 /* Return true, if operand is a memory operand and has a
3102 displacement divisible by 4. */
3105 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
3110 if (!memory_operand (op, mode))
3113 addr = XEXP (op, 0);
3114 if (GET_CODE (addr) == PLUS
3115 && GET_CODE (XEXP (addr, 0)) == REG
3116 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
3117 off = INTVAL (XEXP (addr, 1));
3119 return (off % 4) == 0;
3122 /* Return true if either operand is a general purpose register. */
3125 gpr_or_gpr_p (rtx op0, rtx op1)
3127 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3128 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3132 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3135 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3137 switch (GET_CODE(op))
3140 if (RS6000_SYMBOL_REF_TLS_P (op))
3142 else if (CONSTANT_POOL_ADDRESS_P (op))
3144 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3152 else if (! strcmp (XSTR (op, 0), toc_label_name))
3161 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3162 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3164 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3173 constant_pool_expr_p (rtx op)
3177 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3181 toc_relative_expr_p (rtx op)
3185 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3189 legitimate_constant_pool_address_p (rtx x)
3192 && GET_CODE (x) == PLUS
3193 && GET_CODE (XEXP (x, 0)) == REG
3194 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3195 && constant_pool_expr_p (XEXP (x, 1)));
3199 legitimate_small_data_p (enum machine_mode mode, rtx x)
3201 return (DEFAULT_ABI == ABI_V4
3202 && !flag_pic && !TARGET_TOC
3203 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3204 && small_data_operand (x, mode));
3207 /* SPE offset addressing is limited to 5-bits worth of double words. */
3208 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3211 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3213 unsigned HOST_WIDE_INT offset, extra;
3215 if (GET_CODE (x) != PLUS)
3217 if (GET_CODE (XEXP (x, 0)) != REG)
3219 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3221 if (legitimate_constant_pool_address_p (x))
3223 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3226 offset = INTVAL (XEXP (x, 1));
3234 /* AltiVec vector modes. Only reg+reg addressing is valid here,
3235 which leaves the only valid constant offset of zero, which by
3236 canonicalization rules is also invalid. */
3243 /* SPE vector modes. */
3244 return SPE_CONST_OFFSET_OK (offset);
3247 if (TARGET_E500_DOUBLE)
3248 return SPE_CONST_OFFSET_OK (offset);
3251 if (mode == DFmode || !TARGET_POWERPC64)
3253 else if (offset & 3)
3259 if (mode == TFmode || !TARGET_POWERPC64)
3261 else if (offset & 3)
3272 return (offset < 0x10000) && (offset + extra < 0x10000);
3276 legitimate_indexed_address_p (rtx x, int strict)
3280 if (GET_CODE (x) != PLUS)
3286 if (!REG_P (op0) || !REG_P (op1))
3289 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
3290 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3291 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3292 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
3296 legitimate_indirect_address_p (rtx x, int strict)
3298 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3302 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3304 if (!TARGET_MACHO || !flag_pic
3305 || mode != SImode || GET_CODE(x) != MEM)
3309 if (GET_CODE (x) != LO_SUM)
3311 if (GET_CODE (XEXP (x, 0)) != REG)
3313 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3317 return CONSTANT_P (x);
3321 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3323 if (GET_CODE (x) != LO_SUM)
3325 if (GET_CODE (XEXP (x, 0)) != REG)
3327 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3329 if (TARGET_E500_DOUBLE && mode == DFmode)
3333 if (TARGET_ELF || TARGET_MACHO)
3335 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3339 if (GET_MODE_NUNITS (mode) != 1)
3341 if (GET_MODE_BITSIZE (mode) > 64
3342 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3343 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3346 return CONSTANT_P (x);
3353 /* Try machine-dependent ways of modifying an illegitimate address
3354 to be legitimate. If we find one, return the new, valid address.
3355 This is used from only one place: `memory_address' in explow.c.
3357 OLDX is the address as it was before break_out_memory_refs was
3358 called. In some cases it is useful to look at this to decide what
3361 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3363 It is always safe for this function to do nothing. It exists to
3364 recognize opportunities to optimize the output.
3366 On RS/6000, first check for the sum of a register with a constant
3367 integer that is out of range. If so, generate code to add the
3368 constant with the low-order 16 bits masked to the register and force
3369 this result into another register (this can be done with `cau').
3370 Then generate an address of REG+(CONST&0xffff), allowing for the
3371 possibility of bit 16 being a one.
3373 Then check for the sum of a register and something not constant, try to
3374 load the other things into a register and return the sum. */
3377 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3378 enum machine_mode mode)
3380 if (GET_CODE (x) == SYMBOL_REF)
3382 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3384 return rs6000_legitimize_tls_address (x, model);
3387 if (GET_CODE (x) == PLUS
3388 && GET_CODE (XEXP (x, 0)) == REG
3389 && GET_CODE (XEXP (x, 1)) == CONST_INT
3390 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3392 HOST_WIDE_INT high_int, low_int;
3394 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3395 high_int = INTVAL (XEXP (x, 1)) - low_int;
3396 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3397 GEN_INT (high_int)), 0);
3398 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3400 else if (GET_CODE (x) == PLUS
3401 && GET_CODE (XEXP (x, 0)) == REG
3402 && GET_CODE (XEXP (x, 1)) != CONST_INT
3403 && GET_MODE_NUNITS (mode) == 1
3404 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3406 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3407 && (TARGET_POWERPC64 || mode != DImode)
3410 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3411 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3413 else if (ALTIVEC_VECTOR_MODE (mode))
3417 /* Make sure both operands are registers. */
3418 if (GET_CODE (x) == PLUS)
3419 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3420 force_reg (Pmode, XEXP (x, 1)));
3422 reg = force_reg (Pmode, x);
3425 else if (SPE_VECTOR_MODE (mode)
3426 || (TARGET_E500_DOUBLE && mode == DFmode))
3428 /* We accept [reg + reg] and [reg + OFFSET]. */
3430 if (GET_CODE (x) == PLUS)
3432 rtx op1 = XEXP (x, 0);
3433 rtx op2 = XEXP (x, 1);
3435 op1 = force_reg (Pmode, op1);
3437 if (GET_CODE (op2) != REG
3438 && (GET_CODE (op2) != CONST_INT
3439 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3440 op2 = force_reg (Pmode, op2);
3442 return gen_rtx_PLUS (Pmode, op1, op2);
3445 return force_reg (Pmode, x);
3451 && GET_CODE (x) != CONST_INT
3452 && GET_CODE (x) != CONST_DOUBLE
3454 && GET_MODE_NUNITS (mode) == 1
3455 && (GET_MODE_BITSIZE (mode) <= 32
3456 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3458 rtx reg = gen_reg_rtx (Pmode);
3459 emit_insn (gen_elf_high (reg, x));
3460 return gen_rtx_LO_SUM (Pmode, reg, x);
3462 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3465 && ! MACHO_DYNAMIC_NO_PIC_P
3467 && GET_CODE (x) != CONST_INT
3468 && GET_CODE (x) != CONST_DOUBLE
3470 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3474 rtx reg = gen_reg_rtx (Pmode);
3475 emit_insn (gen_macho_high (reg, x));
3476 return gen_rtx_LO_SUM (Pmode, reg, x);
3479 && constant_pool_expr_p (x)
3480 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3482 return create_TOC_reference (x);
3488 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
3489 We need to emit DTP-relative relocations. */
3492 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3497 fputs ("\t.long\t", file);
3500 fputs (DOUBLE_INT_ASM_OP, file);
3505 output_addr_const (file, x);
3506 fputs ("@dtprel+0x8000", file);
3509 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3511 static GTY(()) rtx rs6000_tls_symbol;
3513 rs6000_tls_get_addr (void)
3515 if (!rs6000_tls_symbol)
3516 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3518 return rs6000_tls_symbol;
3521 /* Construct the SYMBOL_REF for TLS GOT references. */
3523 static GTY(()) rtx rs6000_got_symbol;
3525 rs6000_got_sym (void)
3527 if (!rs6000_got_symbol)
3529 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3530 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3531 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3534 return rs6000_got_symbol;
3537 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3538 this (thread-local) address. */
3541 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3545 dest = gen_reg_rtx (Pmode);
3546 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3552 tlsreg = gen_rtx_REG (Pmode, 13);
3553 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3557 tlsreg = gen_rtx_REG (Pmode, 2);
3558 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3562 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3566 tmp = gen_reg_rtx (Pmode);
3569 tlsreg = gen_rtx_REG (Pmode, 13);
3570 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3574 tlsreg = gen_rtx_REG (Pmode, 2);
3575 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3579 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3581 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3586 rtx r3, got, tga, tmp1, tmp2, eqv;
3589 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3593 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3596 rtx gsym = rs6000_got_sym ();
3597 got = gen_reg_rtx (Pmode);
3599 rs6000_emit_move (got, gsym, Pmode);
3603 static int tls_got_labelno = 0;
3604 rtx tempLR, lab, tmp3, mem;
3607 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
3608 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
3609 tempLR = gen_reg_rtx (Pmode);
3610 tmp1 = gen_reg_rtx (Pmode);
3611 tmp2 = gen_reg_rtx (Pmode);
3612 tmp3 = gen_reg_rtx (Pmode);
3613 mem = gen_const_mem (Pmode, tmp1);
3615 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
3617 emit_move_insn (tmp1, tempLR);
3618 emit_move_insn (tmp2, mem);
3619 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3620 last = emit_move_insn (got, tmp3);
3621 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3623 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3625 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3631 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3633 r3 = gen_rtx_REG (Pmode, 3);
3635 insn = gen_tls_gd_64 (r3, got, addr);
3637 insn = gen_tls_gd_32 (r3, got, addr);
3640 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3641 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3642 insn = emit_call_insn (insn);
3643 CONST_OR_PURE_CALL_P (insn) = 1;
3644 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3645 insn = get_insns ();
3647 emit_libcall_block (insn, dest, r3, addr);
3649 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3651 r3 = gen_rtx_REG (Pmode, 3);
3653 insn = gen_tls_ld_64 (r3, got);
3655 insn = gen_tls_ld_32 (r3, got);
3658 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3659 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3660 insn = emit_call_insn (insn);
3661 CONST_OR_PURE_CALL_P (insn) = 1;
3662 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3663 insn = get_insns ();
3665 tmp1 = gen_reg_rtx (Pmode);
3666 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3668 emit_libcall_block (insn, tmp1, r3, eqv);
3669 if (rs6000_tls_size == 16)
3672 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3674 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3676 else if (rs6000_tls_size == 32)
3678 tmp2 = gen_reg_rtx (Pmode);
3680 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3682 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3685 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3687 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3691 tmp2 = gen_reg_rtx (Pmode);
3693 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3695 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3697 insn = gen_rtx_SET (Pmode, dest,
3698 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3704 /* IE, or 64 bit offset LE. */
3705 tmp2 = gen_reg_rtx (Pmode);
3707 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3709 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3712 insn = gen_tls_tls_64 (dest, tmp2, addr);
3714 insn = gen_tls_tls_32 (dest, tmp2, addr);
3722 /* Return 1 if X is a SYMBOL_REF for a TLS symbol. This is used in
3723 instruction definitions. */
3726 rs6000_tls_symbol_ref (rtx x, enum machine_mode mode ATTRIBUTE_UNUSED)
3728 return RS6000_SYMBOL_REF_TLS_P (x);
3731 /* Return 1 if X contains a thread-local symbol. */
3734 rs6000_tls_referenced_p (rtx x)
3736 if (! TARGET_HAVE_TLS)
3739 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3742 /* Return 1 if *X is a thread-local symbol. This is the same as
3743 rs6000_tls_symbol_ref except for the type of the unused argument. */
3746 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3748 return RS6000_SYMBOL_REF_TLS_P (*x);
3751 /* The convention appears to be to define this wherever it is used.
3752 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3753 is now used here. */
3754 #ifndef REG_MODE_OK_FOR_BASE_P
3755 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3758 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3759 replace the input X, or the original X if no replacement is called for.
3760 The output parameter *WIN is 1 if the calling macro should goto WIN,
3763 For RS/6000, we wish to handle large displacements off a base
3764 register by splitting the addend across an addiu/addis and the mem insn.
3765 This cuts number of extra insns needed from 3 to 1.
3767 On Darwin, we use this to generate code for floating point constants.
3768 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3769 The Darwin code is inside #if TARGET_MACHO because only then is
3770 machopic_function_base_name() defined. */
3772 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3773 int opnum, int type,
3774 int ind_levels ATTRIBUTE_UNUSED, int *win)
3776 /* We must recognize output that we have already generated ourselves. */
3777 if (GET_CODE (x) == PLUS
3778 && GET_CODE (XEXP (x, 0)) == PLUS
3779 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3780 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3781 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3783 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3784 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3785 opnum, (enum reload_type)type);
3791 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3792 && GET_CODE (x) == LO_SUM
3793 && GET_CODE (XEXP (x, 0)) == PLUS
3794 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3795 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3796 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3797 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3798 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3799 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3800 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3802 /* Result of previous invocation of this function on Darwin
3803 floating point constant. */
3804 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3805 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3806 opnum, (enum reload_type)type);
3812 /* Force ld/std non-word aligned offset into base register by wrapping
3814 if (GET_CODE (x) == PLUS
3815 && GET_CODE (XEXP (x, 0)) == REG
3816 && REGNO (XEXP (x, 0)) < 32
3817 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3818 && GET_CODE (XEXP (x, 1)) == CONST_INT
3819 && (INTVAL (XEXP (x, 1)) & 3) != 0
3820 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3821 && TARGET_POWERPC64)
3823 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3824 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3825 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3826 opnum, (enum reload_type) type);
3831 if (GET_CODE (x) == PLUS
3832 && GET_CODE (XEXP (x, 0)) == REG
3833 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3834 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3835 && GET_CODE (XEXP (x, 1)) == CONST_INT
3836 && !SPE_VECTOR_MODE (mode)
3837 && !(TARGET_E500_DOUBLE && mode == DFmode)
3838 && !ALTIVEC_VECTOR_MODE (mode))
3840 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3841 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3843 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3845 /* Check for 32-bit overflow. */
3846 if (high + low != val)
3852 /* Reload the high part into a base reg; leave the low part
3853 in the mem directly. */
3855 x = gen_rtx_PLUS (GET_MODE (x),
3856 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3860 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3861 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3862 opnum, (enum reload_type)type);
3868 if (GET_CODE (x) == SYMBOL_REF
3869 && DEFAULT_ABI == ABI_DARWIN
3870 && !ALTIVEC_VECTOR_MODE (mode)
3871 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3872 /* Don't do this for TFmode, since the result isn't offsettable.
3873 The same goes for DImode without 64-bit gprs. */
3875 && (mode != DImode || TARGET_POWERPC64))
3879 rtx offset = gen_rtx_CONST (Pmode,
3880 gen_rtx_MINUS (Pmode, x,
3881 machopic_function_base_sym ()));
3882 x = gen_rtx_LO_SUM (GET_MODE (x),
3883 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3884 gen_rtx_HIGH (Pmode, offset)), offset);
3887 x = gen_rtx_LO_SUM (GET_MODE (x),
3888 gen_rtx_HIGH (Pmode, x), x);
3890 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3891 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3892 opnum, (enum reload_type)type);
3899 && constant_pool_expr_p (x)
3900 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3902 (x) = create_TOC_reference (x);
3910 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3911 that is a valid memory address for an instruction.
3912 The MODE argument is the machine mode for the MEM expression
3913 that wants to use this address.
3915 On the RS/6000, there are four valid address: a SYMBOL_REF that
3916 refers to a constant pool entry of an address (or the sum of it
3917 plus a constant), a short (16-bit signed) constant plus a register,
3918 the sum of two registers, or a register indirect, possibly with an
3919 auto-increment. For DFmode and DImode with a constant plus register,
3920 we must ensure that both words are addressable or PowerPC64 with offset
3923 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3924 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3925 adjacent memory cells are accessed by adding word-sized offsets
3926 during assembly output. */
3928 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3930 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3932 && ALTIVEC_VECTOR_MODE (mode)
3933 && GET_CODE (x) == AND
3934 && GET_CODE (XEXP (x, 1)) == CONST_INT
3935 && INTVAL (XEXP (x, 1)) == -16)
3938 if (RS6000_SYMBOL_REF_TLS_P (x))
3940 if (legitimate_indirect_address_p (x, reg_ok_strict))
3942 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3943 && !ALTIVEC_VECTOR_MODE (mode)
3944 && !SPE_VECTOR_MODE (mode)
3945 && !(TARGET_E500_DOUBLE && mode == DFmode)
3947 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3949 if (legitimate_small_data_p (mode, x))
3951 if (legitimate_constant_pool_address_p (x))
3953 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3955 && GET_CODE (x) == PLUS
3956 && GET_CODE (XEXP (x, 0)) == REG
3957 && (XEXP (x, 0) == virtual_stack_vars_rtx
3958 || XEXP (x, 0) == arg_pointer_rtx)
3959 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3961 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3965 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3967 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3968 && (TARGET_POWERPC64 || mode != DImode)
3969 && legitimate_indexed_address_p (x, reg_ok_strict))
3971 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3976 /* Go to LABEL if ADDR (a legitimate address expression)
3977 has an effect that depends on the machine mode it is used for.
3979 On the RS/6000 this is true of all integral offsets (since AltiVec
3980 modes don't allow them) or is a pre-increment or decrement.
3982 ??? Except that due to conceptual problems in offsettable_address_p
3983 we can't really report the problems of integral offsets. So leave
3984 this assuming that the adjustable offset must be valid for the
3985 sub-words of a TFmode operand, which is what we had before. */
3988 rs6000_mode_dependent_address (rtx addr)
3990 switch (GET_CODE (addr))
3993 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3995 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3996 return val + 12 + 0x8000 >= 0x10000;
4005 return TARGET_UPDATE;
4014 /* Return number of consecutive hard regs needed starting at reg REGNO
4015 to hold something of mode MODE.
4016 This is ordinarily the length in words of a value of mode MODE
4017 but can be less for certain modes in special long registers.
4019 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4020 scalar instructions. The upper 32 bits are only available to the
4023 POWER and PowerPC GPRs hold 32 bits worth;
4024 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4027 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4029 if (FP_REGNO_P (regno))
4030 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4032 if (TARGET_E500_DOUBLE && mode == DFmode)
4035 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4036 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4038 if (ALTIVEC_REGNO_P (regno))
4040 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4042 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4045 /* Change register usage conditional on target flags. */
4047 rs6000_conditional_register_usage (void)
4051 /* Set MQ register fixed (already call_used) if not POWER
4052 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4057 /* 64-bit AIX reserves GPR13 for thread-private data. */
4059 fixed_regs[13] = call_used_regs[13]
4060 = call_really_used_regs[13] = 1;
4062 /* Conditionally disable FPRs. */
4063 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4064 for (i = 32; i < 64; i++)
4065 fixed_regs[i] = call_used_regs[i]
4066 = call_really_used_regs[i] = 1;
4068 if (DEFAULT_ABI == ABI_V4
4069 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4071 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4073 if (DEFAULT_ABI == ABI_V4
4074 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4076 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4077 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4078 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4080 if (DEFAULT_ABI == ABI_DARWIN
4081 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4082 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4083 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4084 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4085 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4087 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4088 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4089 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4092 global_regs[VSCR_REGNO] = 1;
4096 global_regs[SPEFSCR_REGNO] = 1;
4097 fixed_regs[FIXED_SCRATCH]
4098 = call_used_regs[FIXED_SCRATCH]
4099 = call_really_used_regs[FIXED_SCRATCH] = 1;
4102 if (! TARGET_ALTIVEC)
4104 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4105 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4106 call_really_used_regs[VRSAVE_REGNO] = 1;
4109 if (TARGET_ALTIVEC_ABI)
4110 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4111 call_used_regs[i] = call_really_used_regs[i] = 1;
4114 /* Try to output insns to set TARGET equal to the constant C if it can
4115 be done in less than N insns. Do all computations in MODE.
4116 Returns the place where the output has been placed if it can be
4117 done and the insns have been emitted. If it would take more than N
4118 insns, zero is returned and no insns and emitted. */
4121 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4122 rtx source, int n ATTRIBUTE_UNUSED)
4124 rtx result, insn, set;
4125 HOST_WIDE_INT c0, c1;
4127 if (mode == QImode || mode == HImode)
4130 dest = gen_reg_rtx (mode);
4131 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4134 else if (mode == SImode)
4136 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
4138 emit_insn (gen_rtx_SET (VOIDmode, result,
4139 GEN_INT (INTVAL (source)
4140 & (~ (HOST_WIDE_INT) 0xffff))));
4141 emit_insn (gen_rtx_SET (VOIDmode, dest,
4142 gen_rtx_IOR (SImode, result,
4143 GEN_INT (INTVAL (source) & 0xffff))));
4146 else if (mode == DImode)
4148 if (GET_CODE (source) == CONST_INT)
4150 c0 = INTVAL (source);
4153 else if (GET_CODE (source) == CONST_DOUBLE)
4155 #if HOST_BITS_PER_WIDE_INT >= 64
4156 c0 = CONST_DOUBLE_LOW (source);
4159 c0 = CONST_DOUBLE_LOW (source);
4160 c1 = CONST_DOUBLE_HIGH (source);
4166 result = rs6000_emit_set_long_const (dest, c0, c1);
4171 insn = get_last_insn ();
4172 set = single_set (insn);
4173 if (! CONSTANT_P (SET_SRC (set)))
4174 set_unique_reg_note (insn, REG_EQUAL, source);
4179 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4180 fall back to a straight forward decomposition. We do this to avoid
4181 exponential run times encountered when looking for longer sequences
4182 with rs6000_emit_set_const. */
4184 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4186 if (!TARGET_POWERPC64)
4188 rtx operand1, operand2;
4190 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4192 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4194 emit_move_insn (operand1, GEN_INT (c1));
4195 emit_move_insn (operand2, GEN_INT (c2));
4199 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4202 ud2 = (c1 & 0xffff0000) >> 16;
4203 #if HOST_BITS_PER_WIDE_INT >= 64
4207 ud4 = (c2 & 0xffff0000) >> 16;
4209 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4210 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4213 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4215 emit_move_insn (dest, GEN_INT (ud1));
4218 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4219 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4222 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4225 emit_move_insn (dest, GEN_INT (ud2 << 16));
4227 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4229 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4230 || (ud4 == 0 && ! (ud3 & 0x8000)))
4233 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4236 emit_move_insn (dest, GEN_INT (ud3 << 16));
4239 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4240 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4242 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4247 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4250 emit_move_insn (dest, GEN_INT (ud4 << 16));
4253 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4255 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4257 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4258 GEN_INT (ud2 << 16)));
4260 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4266 /* Helper for the following. Get rid of [r+r] memory refs
4267 in cases where it won't work (TImode, TFmode). */
4270 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4272 if (GET_CODE (operands[0]) == MEM
4273 && GET_CODE (XEXP (operands[0], 0)) != REG
4274 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4275 && ! reload_in_progress)
4277 = replace_equiv_address (operands[0],
4278 copy_addr_to_reg (XEXP (operands[0], 0)));
4280 if (GET_CODE (operands[1]) == MEM
4281 && GET_CODE (XEXP (operands[1], 0)) != REG
4282 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4283 && ! reload_in_progress)
4285 = replace_equiv_address (operands[1],
4286 copy_addr_to_reg (XEXP (operands[1], 0)));
4289 /* Emit a move from SOURCE to DEST in mode MODE. */
4291 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4295 operands[1] = source;
4297 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4298 if (GET_CODE (operands[1]) == CONST_DOUBLE
4299 && ! FLOAT_MODE_P (mode)
4300 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4302 /* FIXME. This should never happen. */
4303 /* Since it seems that it does, do the safe thing and convert
4305 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4307 if (GET_CODE (operands[1]) == CONST_DOUBLE
4308 && ! FLOAT_MODE_P (mode)
4309 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
4310 && CONST_DOUBLE_LOW (operands[1]) >= 0)
4311 || (CONST_DOUBLE_HIGH (operands[1]) == -1
4312 && CONST_DOUBLE_LOW (operands[1]) < 0)))
4315 /* Check if GCC is setting up a block move that will end up using FP
4316 registers as temporaries. We must make sure this is acceptable. */
4317 if (GET_CODE (operands[0]) == MEM
4318 && GET_CODE (operands[1]) == MEM
4320 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4321 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4322 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4323 ? 32 : MEM_ALIGN (operands[0])))
4324 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4326 : MEM_ALIGN (operands[1]))))
4327 && ! MEM_VOLATILE_P (operands [0])
4328 && ! MEM_VOLATILE_P (operands [1]))
4330 emit_move_insn (adjust_address (operands[0], SImode, 0),
4331 adjust_address (operands[1], SImode, 0));
4332 emit_move_insn (adjust_address (operands[0], SImode, 4),
4333 adjust_address (operands[1], SImode, 4));
4337 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4338 && !gpc_reg_operand (operands[1], mode))
4339 operands[1] = force_reg (mode, operands[1]);
4341 if (mode == SFmode && ! TARGET_POWERPC
4342 && TARGET_HARD_FLOAT && TARGET_FPRS
4343 && GET_CODE (operands[0]) == MEM)
4347 if (reload_in_progress || reload_completed)
4348 regnum = true_regnum (operands[1]);
4349 else if (GET_CODE (operands[1]) == REG)
4350 regnum = REGNO (operands[1]);
4354 /* If operands[1] is a register, on POWER it may have
4355 double-precision data in it, so truncate it to single
4357 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4360 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4361 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4362 operands[1] = newreg;
4366 /* Recognize the case where operand[1] is a reference to thread-local
4367 data and load its address to a register. */
4368 if (GET_CODE (operands[1]) == SYMBOL_REF)
4370 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
4372 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
4375 /* Handle the case where reload calls us with an invalid address. */
4376 if (reload_in_progress && mode == Pmode
4377 && (! general_operand (operands[1], mode)
4378 || ! nonimmediate_operand (operands[0], mode)))
4381 /* 128-bit constant floating-point values on Darwin should really be
4382 loaded as two parts. */
4383 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
4384 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
4385 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4387 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4388 know how to get a DFmode SUBREG of a TFmode. */
4389 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4390 simplify_gen_subreg (DImode, operands[1], mode, 0),
4392 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4393 GET_MODE_SIZE (DImode)),
4394 simplify_gen_subreg (DImode, operands[1], mode,
4395 GET_MODE_SIZE (DImode)),
4400 /* FIXME: In the long term, this switch statement should go away
4401 and be replaced by a sequence of tests based on things like
4407 if (CONSTANT_P (operands[1])
4408 && GET_CODE (operands[1]) != CONST_INT)
4409 operands[1] = force_const_mem (mode, operands[1]);
4413 rs6000_eliminate_indexed_memrefs (operands);
4418 if (CONSTANT_P (operands[1])
4419 && ! easy_fp_constant (operands[1], mode))
4420 operands[1] = force_const_mem (mode, operands[1]);
4431 if (CONSTANT_P (operands[1])
4432 && !easy_vector_constant (operands[1], mode))
4433 operands[1] = force_const_mem (mode, operands[1]);
4438 /* Use default pattern for address of ELF small data */
4441 && DEFAULT_ABI == ABI_V4
4442 && (GET_CODE (operands[1]) == SYMBOL_REF
4443 || GET_CODE (operands[1]) == CONST)
4444 && small_data_operand (operands[1], mode))
4446 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4450 if (DEFAULT_ABI == ABI_V4
4451 && mode == Pmode && mode == SImode
4452 && flag_pic == 1 && got_operand (operands[1], mode))
4454 emit_insn (gen_movsi_got (operands[0], operands[1]));
4458 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4462 && CONSTANT_P (operands[1])
4463 && GET_CODE (operands[1]) != HIGH
4464 && GET_CODE (operands[1]) != CONST_INT)
4466 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4468 /* If this is a function address on -mcall-aixdesc,
4469 convert it to the address of the descriptor. */
4470 if (DEFAULT_ABI == ABI_AIX
4471 && GET_CODE (operands[1]) == SYMBOL_REF
4472 && XSTR (operands[1], 0)[0] == '.')
4474 const char *name = XSTR (operands[1], 0);
4476 while (*name == '.')
4478 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4479 CONSTANT_POOL_ADDRESS_P (new_ref)
4480 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4481 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4482 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4483 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
4484 operands[1] = new_ref;
4487 if (DEFAULT_ABI == ABI_DARWIN)
4490 if (MACHO_DYNAMIC_NO_PIC_P)
4492 /* Take care of any required data indirection. */
4493 operands[1] = rs6000_machopic_legitimize_pic_address (
4494 operands[1], mode, operands[0]);
4495 if (operands[0] != operands[1])
4496 emit_insn (gen_rtx_SET (VOIDmode,
4497 operands[0], operands[1]));
4501 emit_insn (gen_macho_high (target, operands[1]));
4502 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4506 emit_insn (gen_elf_high (target, operands[1]));
4507 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4511 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4512 and we have put it in the TOC, we just need to make a TOC-relative
4515 && GET_CODE (operands[1]) == SYMBOL_REF
4516 && constant_pool_expr_p (operands[1])
4517 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4518 get_pool_mode (operands[1])))
4520 operands[1] = create_TOC_reference (operands[1]);
4522 else if (mode == Pmode
4523 && CONSTANT_P (operands[1])
4524 && ((GET_CODE (operands[1]) != CONST_INT
4525 && ! easy_fp_constant (operands[1], mode))
4526 || (GET_CODE (operands[1]) == CONST_INT
4527 && num_insns_constant (operands[1], mode) > 2)
4528 || (GET_CODE (operands[0]) == REG
4529 && FP_REGNO_P (REGNO (operands[0]))))
4530 && GET_CODE (operands[1]) != HIGH
4531 && ! legitimate_constant_pool_address_p (operands[1])
4532 && ! toc_relative_expr_p (operands[1]))
4534 /* Emit a USE operation so that the constant isn't deleted if
4535 expensive optimizations are turned on because nobody
4536 references it. This should only be done for operands that
4537 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4538 This should not be done for operands that contain LABEL_REFs.
4539 For now, we just handle the obvious case. */
4540 if (GET_CODE (operands[1]) != LABEL_REF)
4541 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4544 /* Darwin uses a special PIC legitimizer. */
4545 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4548 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4550 if (operands[0] != operands[1])
4551 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4556 /* If we are to limit the number of things we put in the TOC and
4557 this is a symbol plus a constant we can add in one insn,
4558 just put the symbol in the TOC and add the constant. Don't do
4559 this if reload is in progress. */
4560 if (GET_CODE (operands[1]) == CONST
4561 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4562 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4563 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4564 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4565 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4566 && ! side_effects_p (operands[0]))
4569 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4570 rtx other = XEXP (XEXP (operands[1], 0), 1);
4572 sym = force_reg (mode, sym);
4574 emit_insn (gen_addsi3 (operands[0], sym, other));
4576 emit_insn (gen_adddi3 (operands[0], sym, other));
4580 operands[1] = force_const_mem (mode, operands[1]);
4583 && constant_pool_expr_p (XEXP (operands[1], 0))
4584 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4585 get_pool_constant (XEXP (operands[1], 0)),
4586 get_pool_mode (XEXP (operands[1], 0))))
4589 = gen_const_mem (mode,
4590 create_TOC_reference (XEXP (operands[1], 0)));
4591 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4597 rs6000_eliminate_indexed_memrefs (operands);
4601 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4603 gen_rtx_SET (VOIDmode,
4604 operands[0], operands[1]),
4605 gen_rtx_CLOBBER (VOIDmode,
4606 gen_rtx_SCRATCH (SImode)))));
4615 /* Above, we may have called force_const_mem which may have returned
4616 an invalid address. If we can, fix this up; otherwise, reload will
4617 have to deal with it. */
4618 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4619 operands[1] = validize_mem (operands[1]);
4622 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4625 /* Nonzero if we can use a floating-point register to pass this arg. */
4626 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4627 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4628 && (CUM)->fregno <= FP_ARG_MAX_REG \
4629 && TARGET_HARD_FLOAT && TARGET_FPRS)
4631 /* Nonzero if we can use an AltiVec register to pass this arg. */
4632 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4633 (ALTIVEC_VECTOR_MODE (MODE) \
4634 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4635 && TARGET_ALTIVEC_ABI \
4638 /* Return a nonzero value to say to return the function value in
4639 memory, just as large structures are always returned. TYPE will be
4640 the data type of the value, and FNTYPE will be the type of the
4641 function doing the returning, or @code{NULL} for libcalls.
4643 The AIX ABI for the RS/6000 specifies that all structures are
4644 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4645 specifies that structures <= 8 bytes are returned in r3/r4, but a
4646 draft put them in memory, and GCC used to implement the draft
4647 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
4648 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4649 compatibility can change DRAFT_V4_STRUCT_RET to override the
4650 default, and -m switches get the final word. See
4651 rs6000_override_options for more details.
4653 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4654 long double support is enabled. These values are returned in memory.
4656 int_size_in_bytes returns -1 for variable size objects, which go in
4657 memory always. The cast to unsigned makes -1 > 8. */
4660 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4662 /* In the darwin64 abi, try to use registers for larger structs
4664 if (AGGREGATE_TYPE_P (type)
4665 && rs6000_darwin64_abi
4666 && TREE_CODE (type) == RECORD_TYPE
4667 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) <= 32)
4668 && ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 0))
4671 if (AGGREGATE_TYPE_P (type)
4672 && (TARGET_AIX_STRUCT_RET
4673 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4676 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4677 modes only exist for GCC vector types if -maltivec. */
4678 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4679 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4682 /* Return synthetic vectors in memory. */
4683 if (TREE_CODE (type) == VECTOR_TYPE
4684 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4686 static bool warned_for_return_big_vectors = false;
4687 if (!warned_for_return_big_vectors)
4689 warning ("GCC vector returned by reference: "
4690 "non-standard ABI extension with no compatibility guarantee");
4691 warned_for_return_big_vectors = true;
4696 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4702 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4703 for a call to a function whose data type is FNTYPE.
4704 For a library call, FNTYPE is 0.
4706 For incoming args we set the number of arguments in the prototype large
4707 so we never return a PARALLEL. */
4710 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4711 rtx libname ATTRIBUTE_UNUSED, int incoming,
4712 int libcall, int n_named_args)
4714 static CUMULATIVE_ARGS zero_cumulative;
4716 *cum = zero_cumulative;
4718 cum->fregno = FP_ARG_MIN_REG;
4719 cum->vregno = ALTIVEC_ARG_MIN_REG;
4720 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4721 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4722 ? CALL_LIBCALL : CALL_NORMAL);
4723 cum->sysv_gregno = GP_ARG_MIN_REG;
4724 cum->stdarg = fntype
4725 && (TYPE_ARG_TYPES (fntype) != 0
4726 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4727 != void_type_node));
4729 cum->nargs_prototype = 0;
4730 if (incoming || cum->prototype)
4731 cum->nargs_prototype = n_named_args;
4733 /* Check for a longcall attribute. */
4734 if ((!fntype && rs6000_default_long_calls)
4736 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4737 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4738 cum->call_cookie |= CALL_LONG;
4740 if (TARGET_DEBUG_ARG)
4742 fprintf (stderr, "\ninit_cumulative_args:");
4745 tree ret_type = TREE_TYPE (fntype);
4746 fprintf (stderr, " ret code = %s,",
4747 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4750 if (cum->call_cookie & CALL_LONG)
4751 fprintf (stderr, " longcall,");
4753 fprintf (stderr, " proto = %d, nargs = %d\n",
4754 cum->prototype, cum->nargs_prototype);
4759 && TARGET_ALTIVEC_ABI
4760 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4762 error ("Cannot return value in vector register because"
4763 " altivec instructions are disabled, use -maltivec"
4764 " to enable them.");
4768 /* Return true if TYPE must be passed on the stack and not in registers. */
4771 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4773 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4774 return must_pass_in_stack_var_size (mode, type);
4776 return must_pass_in_stack_var_size_or_pad (mode, type);
4779 /* If defined, a C expression which determines whether, and in which
4780 direction, to pad out an argument with extra space. The value
4781 should be of type `enum direction': either `upward' to pad above
4782 the argument, `downward' to pad below, or `none' to inhibit
4785 For the AIX ABI structs are always stored left shifted in their
4789 function_arg_padding (enum machine_mode mode, tree type)
4791 #ifndef AGGREGATE_PADDING_FIXED
4792 #define AGGREGATE_PADDING_FIXED 0
4794 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4795 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4798 if (!AGGREGATE_PADDING_FIXED)
4800 /* GCC used to pass structures of the same size as integer types as
4801 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4802 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4803 passed padded downward, except that -mstrict-align further
4804 muddied the water in that multi-component structures of 2 and 4
4805 bytes in size were passed padded upward.
4807 The following arranges for best compatibility with previous
4808 versions of gcc, but removes the -mstrict-align dependency. */
4809 if (BYTES_BIG_ENDIAN)
4811 HOST_WIDE_INT size = 0;
4813 if (mode == BLKmode)
4815 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4816 size = int_size_in_bytes (type);
4819 size = GET_MODE_SIZE (mode);
4821 if (size == 1 || size == 2 || size == 4)
4827 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4829 if (type != 0 && AGGREGATE_TYPE_P (type))
4833 /* Fall back to the default. */
4834 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4837 /* If defined, a C expression that gives the alignment boundary, in bits,
4838 of an argument with the specified mode and type. If it is not defined,
4839 PARM_BOUNDARY is used for all arguments.
4841 V.4 wants long longs to be double word aligned.
4842 Doubleword align SPE vectors.
4843 Quadword align Altivec vectors.
4844 Quadword align large synthetic vector types. */
4847 function_arg_boundary (enum machine_mode mode, tree type)
4849 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4851 else if (SPE_VECTOR_MODE (mode)
4852 || (type && TREE_CODE (type) == VECTOR_TYPE
4853 && int_size_in_bytes (type) >= 8
4854 && int_size_in_bytes (type) < 16))
4856 else if (ALTIVEC_VECTOR_MODE (mode)
4857 || (type && TREE_CODE (type) == VECTOR_TYPE
4858 && int_size_in_bytes (type) >= 16))
4861 return PARM_BOUNDARY;
4864 /* Compute the size (in words) of a function argument. */
4866 static unsigned long
4867 rs6000_arg_size (enum machine_mode mode, tree type)
4871 if (mode != BLKmode)
4872 size = GET_MODE_SIZE (mode);
4874 size = int_size_in_bytes (type);
4877 return (size + 3) >> 2;
4879 return (size + 7) >> 3;
4882 /* The darwin64 ABI calls for us to recurse down through structs,
4883 applying the same rules to struct elements as if a reference to
4884 each were being passed directly. */
4887 darwin64_function_arg_advance (CUMULATIVE_ARGS *cum, tree type,
4888 int named, int depth)
4893 switch (TREE_CODE (type))
4896 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4897 if (TREE_CODE (f) == FIELD_DECL)
4899 ftype = TREE_TYPE (f);
4900 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4906 tot = int_size_in_bytes (type);
4909 ftype = TREE_TYPE (type);
4910 tot /= int_size_in_bytes (ftype);
4912 for (i = 0; i < tot; ++i)
4914 function_arg_advance (cum, TYPE_MODE (ftype), ftype,
4924 /* Update the data in CUM to advance over an argument
4925 of mode MODE and data type TYPE.
4926 (TYPE is null for libcalls where that information may not be available.)
4928 Note that for args passed by reference, function_arg will be called
4929 with MODE and TYPE set to that of the pointer to the arg, not the arg
4933 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4934 tree type, int named, int depth)
4936 /* Only tick off an argument if we're not recursing. */
4938 cum->nargs_prototype--;
4940 if (TARGET_ALTIVEC_ABI
4941 && (ALTIVEC_VECTOR_MODE (mode)
4942 || (type && TREE_CODE (type) == VECTOR_TYPE
4943 && int_size_in_bytes (type) == 16)))
4947 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4950 if (!TARGET_ALTIVEC)
4951 error ("Cannot pass argument in vector register because"
4952 " altivec instructions are disabled, use -maltivec"
4953 " to enable them.");
4955 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4956 even if it is going to be passed in a vector register.
4957 Darwin does the same for variable-argument functions. */
4958 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4959 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4969 /* Vector parameters must be 16-byte aligned. This places
4970 them at 2 mod 4 in terms of words in 32-bit mode, since
4971 the parameter save area starts at offset 24 from the
4972 stack. In 64-bit mode, they just have to start on an
4973 even word, since the parameter save area is 16-byte
4974 aligned. Space for GPRs is reserved even if the argument
4975 will be passed in memory. */
4977 align = (2 - cum->words) & 3;
4979 align = cum->words & 1;
4980 cum->words += align + rs6000_arg_size (mode, type);
4982 if (TARGET_DEBUG_ARG)
4984 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4986 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4987 cum->nargs_prototype, cum->prototype,
4988 GET_MODE_NAME (mode));
4992 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4994 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4997 else if (rs6000_darwin64_abi
4999 && (TREE_CODE (type) == RECORD_TYPE
5000 || TREE_CODE (type) == ARRAY_TYPE))
5001 darwin64_function_arg_advance (cum, type, named, depth);
5003 else if (DEFAULT_ABI == ABI_V4)
5005 if (TARGET_HARD_FLOAT && TARGET_FPRS
5006 && (mode == SFmode || mode == DFmode))
5008 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5013 cum->words += cum->words & 1;
5014 cum->words += rs6000_arg_size (mode, type);
5019 int n_words = rs6000_arg_size (mode, type);
5020 int gregno = cum->sysv_gregno;
5022 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5023 (r7,r8) or (r9,r10). As does any other 2 word item such
5024 as complex int due to a historical mistake. */
5026 gregno += (1 - gregno) & 1;
5028 /* Multi-reg args are not split between registers and stack. */
5029 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5031 /* Long long and SPE vectors are aligned on the stack.
5032 So are other 2 word items such as complex int due to
5033 a historical mistake. */
5035 cum->words += cum->words & 1;
5036 cum->words += n_words;
5039 /* Note: continuing to accumulate gregno past when we've started
5040 spilling to the stack indicates the fact that we've started
5041 spilling to the stack to expand_builtin_saveregs. */
5042 cum->sysv_gregno = gregno + n_words;
5045 if (TARGET_DEBUG_ARG)
5047 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5048 cum->words, cum->fregno);
5049 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5050 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5051 fprintf (stderr, "mode = %4s, named = %d\n",
5052 GET_MODE_NAME (mode), named);
5057 int n_words = rs6000_arg_size (mode, type);
5058 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5060 /* The simple alignment calculation here works because
5061 function_arg_boundary / PARM_BOUNDARY will only be 1 or 2.
5062 If we ever want to handle alignments larger than 8 bytes for
5063 32-bit or 16 bytes for 64-bit, then we'll need to take into
5064 account the offset to the start of the parm save area. */
5065 align &= cum->words;
5066 cum->words += align + n_words;
5068 if (GET_MODE_CLASS (mode) == MODE_FLOAT
5069 && TARGET_HARD_FLOAT && TARGET_FPRS)
5070 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5072 if (TARGET_DEBUG_ARG)
5074 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5075 cum->words, cum->fregno);
5076 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5077 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5078 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5079 named, align, depth);
5085 spe_build_register_parallel (enum machine_mode mode, int gregno)
5088 enum machine_mode inner = SImode;
5092 r1 = gen_rtx_REG (inner, gregno);
5093 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5094 r2 = gen_rtx_REG (inner, gregno + 1);
5095 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5096 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5098 else if (mode == DCmode)
5100 r1 = gen_rtx_REG (inner, gregno);
5101 r1 = gen_rtx_EXPR_LIST (SImode, r1, const0_rtx);
5102 r2 = gen_rtx_REG (inner, gregno + 1);
5103 r2 = gen_rtx_EXPR_LIST (SImode, r2, GEN_INT (4));
5104 r3 = gen_rtx_REG (inner, gregno + 2);
5105 r3 = gen_rtx_EXPR_LIST (SImode, r3, GEN_INT (8));
5106 r4 = gen_rtx_REG (inner, gregno + 3);
5107 r4 = gen_rtx_EXPR_LIST (SImode, r4, GEN_INT (12));
5108 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r2, r3, r4));
5115 /* Determine where to put a SIMD argument on the SPE. */
5117 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5120 int gregno = cum->sysv_gregno;
5122 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5123 are passed and returned in a pair of GPRs for ABI compatibility. */
5124 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
5126 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5127 gregno += (1 - gregno) & 1;
5129 /* We do not split between registers and stack. */
5130 if (gregno + 1 > GP_ARG_MAX_REG)
5133 return spe_build_register_parallel (mode, gregno);
5137 int n_words = rs6000_arg_size (mode, type);
5139 /* SPE vectors are put in odd registers. */
5140 if (n_words == 2 && (gregno & 1) == 0)
5143 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5146 enum machine_mode m = SImode;
5148 r1 = gen_rtx_REG (m, gregno);
5149 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5150 r2 = gen_rtx_REG (m, gregno + 1);
5151 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5152 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5159 if (gregno <= GP_ARG_MAX_REG)
5160 return gen_rtx_REG (mode, gregno);
5166 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5167 the register(s) to be used for each field and subfield of a struct
5168 being passed by value, along with the offset of where the
5169 register's value may be found in the block. */
5172 rs6000_darwin64_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5173 tree type, int named)
5175 tree f, ftype, offset;
5176 rtx rvec[FIRST_PSEUDO_REGISTER], sub, suboff, roffset;
5177 int k = 0, i, j, bytepos, subbytepos, tot;
5178 CUMULATIVE_ARGS saved_cum = *cum;
5179 enum machine_mode submode;
5181 switch (TREE_CODE (type))
5184 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5185 if (TREE_CODE (f) == FIELD_DECL)
5187 ftype = TREE_TYPE (f);
5188 offset = DECL_FIELD_OFFSET (f);
5189 bytepos = int_bit_position (f) / BITS_PER_UNIT;
5190 /* Force substructs to be handled as BLKmode even if
5191 they're small enough to be recorded as DImode, so we
5192 drill through to non-record fields. */
5193 submode = TYPE_MODE (ftype);
5194 if (TREE_CODE (ftype) == RECORD_TYPE)
5196 sub = function_arg (cum, submode, ftype, named);
5197 if (sub == NULL_RTX)
5199 if (GET_CODE (sub) == PARALLEL)
5201 for (i = 0; i < XVECLEN (sub, 0); i++)
5203 rtx subsub = XVECEXP (sub, 0, i);
5204 suboff = XEXP (subsub, 1);
5205 subbytepos = INTVAL (suboff);
5206 subbytepos += bytepos;
5207 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5208 subsub = XEXP (subsub, 0);
5209 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5214 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5215 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5217 /* Now do an arg advance to get all the cumulative arg
5218 stuff set correctly for the next subfield. Note that it
5219 has no lasting effect, because it is being done on a
5220 temporary copy of the cumulative arg data. */
5221 function_arg_advance (cum, submode, ftype, named, 1);
5226 tot = rs6000_arg_size (mode, type);
5231 for (j = 0; j < tot; ++j)
5233 sub = gen_rtx_REG ((TARGET_64BIT ? DImode : SImode), GP_ARG_MIN_REG + cum->words++);
5234 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5235 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5236 if (cum->words >= GP_ARG_NUM_REG)
5238 bytepos += (TARGET_64BIT ? 8 : 4);
5243 tot = int_size_in_bytes (type);
5246 ftype = TREE_TYPE (type);
5247 tot /= int_size_in_bytes (ftype);
5250 for (j = 0; j < tot; ++j)
5252 /* Force substructs to be handled as BLKmode even if
5253 they're small enough to be recorded as DImode, so we
5254 drill through to non-record fields. */
5255 submode = TYPE_MODE (ftype);
5256 if (TREE_CODE (ftype) == RECORD_TYPE)
5258 sub = function_arg (cum, submode, ftype, named);
5259 if (sub == NULL_RTX)
5261 if (GET_CODE (sub) == PARALLEL)
5263 for (i = 0; i < XVECLEN (sub, 0); i++)
5265 rtx subsub = XVECEXP (sub, 0, i);
5267 suboff = XEXP (subsub, 1);
5268 subbytepos = INTVAL (suboff);
5269 subbytepos += bytepos;
5270 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
5271 subsub = XEXP (subsub, 0);
5272 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
5277 roffset = gen_rtx_CONST_INT (SImode, bytepos);
5278 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
5280 /* Now do an arg advance to get all the cumulative arg
5281 stuff set correctly for the next subfield. Note that it
5282 has no lasting effect, because it is being done on a
5283 temporary copy of the cumulative arg data. */
5284 function_arg_advance (cum, submode, ftype, named, 1);
5285 bytepos += int_size_in_bytes (ftype);
5295 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5300 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5303 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5307 rtx rvec[GP_ARG_NUM_REG + 1];
5309 if (align_words >= GP_ARG_NUM_REG)
5312 n_units = rs6000_arg_size (mode, type);
5314 /* Optimize the simple case where the arg fits in one gpr, except in
5315 the case of BLKmode due to assign_parms assuming that registers are
5316 BITS_PER_WORD wide. */
5318 || (n_units == 1 && mode != BLKmode))
5319 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5322 if (align_words + n_units > GP_ARG_NUM_REG)
5323 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5324 using a magic NULL_RTX component.
5325 FIXME: This is not strictly correct. Only some of the arg
5326 belongs in memory, not all of it. However, there isn't any way
5327 to do this currently, apart from building rtx descriptions for
5328 the pieces of memory we want stored. Due to bugs in the generic
5329 code we can't use the normal function_arg_partial_nregs scheme
5330 with the PARALLEL arg description we emit here.
5331 In any case, the code to store the whole arg to memory is often
5332 more efficient than code to store pieces, and we know that space
5333 is available in the right place for the whole arg. */
5334 /* FIXME: This should be fixed since the conversion to
5335 TARGET_ARG_PARTIAL_BYTES. */
5336 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5341 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5342 rtx off = GEN_INT (i++ * 4);
5343 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5345 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5347 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5350 /* Determine where to put an argument to a function.
5351 Value is zero to push the argument on the stack,
5352 or a hard register in which to store the argument.
5354 MODE is the argument's machine mode.
5355 TYPE is the data type of the argument (as a tree).
5356 This is null for libcalls where that information may
5358 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5359 the preceding args and about the function being called.
5360 NAMED is nonzero if this argument is a named parameter
5361 (otherwise it is an extra parameter matching an ellipsis).
5363 On RS/6000 the first eight words of non-FP are normally in registers
5364 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5365 Under V.4, the first 8 FP args are in registers.
5367 If this is floating-point and no prototype is specified, we use
5368 both an FP and integer register (or possibly FP reg and stack). Library
5369 functions (when CALL_LIBCALL is set) always have the proper types for args,
5370 so we can pass the FP value just in one register. emit_library_function
5371 doesn't support PARALLEL anyway.
5373 Note that for args passed by reference, function_arg will be called
5374 with MODE and TYPE set to that of the pointer to the arg, not the arg
5378 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5379 tree type, int named)
5381 enum rs6000_abi abi = DEFAULT_ABI;
5383 /* Return a marker to indicate whether CR1 needs to set or clear the
5384 bit that V.4 uses to say fp args were passed in registers.
5385 Assume that we don't need the marker for software floating point,
5386 or compiler generated library calls. */
5387 if (mode == VOIDmode)
5390 && cum->nargs_prototype < 0
5391 && (cum->call_cookie & CALL_LIBCALL) == 0
5392 && (cum->prototype || TARGET_NO_PROTOTYPE))
5394 /* For the SPE, we need to crxor CR6 always. */
5396 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5397 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5398 return GEN_INT (cum->call_cookie
5399 | ((cum->fregno == FP_ARG_MIN_REG)
5400 ? CALL_V4_SET_FP_ARGS
5401 : CALL_V4_CLEAR_FP_ARGS));
5404 return GEN_INT (cum->call_cookie);
5408 && rs6000_darwin64_abi
5409 && (TREE_CODE (type) == RECORD_TYPE
5410 || TREE_CODE (type) == UNION_TYPE
5411 || TREE_CODE (type) == ARRAY_TYPE))
5413 rtx rslt = rs6000_darwin64_function_arg (cum, mode, type, named);
5414 if (rslt != NULL_RTX)
5416 /* Else fall through to usual handling. */
5419 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5420 if (TARGET_64BIT && ! cum->prototype)
5422 /* Vector parameters get passed in vector register
5423 and also in GPRs or memory, in absence of prototype. */
5426 align_words = (cum->words + 1) & ~1;
5428 if (align_words >= GP_ARG_NUM_REG)
5434 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5436 return gen_rtx_PARALLEL (mode,
5438 gen_rtx_EXPR_LIST (VOIDmode,
5440 gen_rtx_EXPR_LIST (VOIDmode,
5441 gen_rtx_REG (mode, cum->vregno),
5445 return gen_rtx_REG (mode, cum->vregno);
5446 else if (TARGET_ALTIVEC_ABI
5447 && (ALTIVEC_VECTOR_MODE (mode)
5448 || (type && TREE_CODE (type) == VECTOR_TYPE
5449 && int_size_in_bytes (type) == 16)))
5451 if (named || abi == ABI_V4)
5455 /* Vector parameters to varargs functions under AIX or Darwin
5456 get passed in memory and possibly also in GPRs. */
5457 int align, align_words, n_words;
5458 enum machine_mode part_mode;
5460 /* Vector parameters must be 16-byte aligned. This places them at
5461 2 mod 4 in terms of words in 32-bit mode, since the parameter
5462 save area starts at offset 24 from the stack. In 64-bit mode,
5463 they just have to start on an even word, since the parameter
5464 save area is 16-byte aligned. */
5466 align = (2 - cum->words) & 3;
5468 align = cum->words & 1;
5469 align_words = cum->words + align;
5471 /* Out of registers? Memory, then. */
5472 if (align_words >= GP_ARG_NUM_REG)
5475 if (TARGET_32BIT && TARGET_POWERPC64)
5476 return rs6000_mixed_function_arg (mode, type, align_words);
5478 /* The vector value goes in GPRs. Only the part of the
5479 value in GPRs is reported here. */
5481 n_words = rs6000_arg_size (mode, type);
5482 if (align_words + n_words > GP_ARG_NUM_REG)
5483 /* Fortunately, there are only two possibilities, the value
5484 is either wholly in GPRs or half in GPRs and half not. */
5487 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5490 else if (TARGET_SPE_ABI && TARGET_SPE
5491 && (SPE_VECTOR_MODE (mode)
5492 || (TARGET_E500_DOUBLE && (mode == DFmode
5493 || mode == DCmode))))
5494 return rs6000_spe_function_arg (cum, mode, type);
5496 else if (abi == ABI_V4)
5498 if (TARGET_HARD_FLOAT && TARGET_FPRS
5499 && (mode == SFmode || mode == DFmode))
5501 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5502 return gen_rtx_REG (mode, cum->fregno);
5508 int n_words = rs6000_arg_size (mode, type);
5509 int gregno = cum->sysv_gregno;
5511 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5512 (r7,r8) or (r9,r10). As does any other 2 word item such
5513 as complex int due to a historical mistake. */
5515 gregno += (1 - gregno) & 1;
5517 /* Multi-reg args are not split between registers and stack. */
5518 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5521 if (TARGET_32BIT && TARGET_POWERPC64)
5522 return rs6000_mixed_function_arg (mode, type,
5523 gregno - GP_ARG_MIN_REG);
5524 return gen_rtx_REG (mode, gregno);
5529 int align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5530 int align_words = cum->words + (cum->words & align);
5532 if (USE_FP_FOR_ARG_P (cum, mode, type))
5534 rtx rvec[GP_ARG_NUM_REG + 1];
5538 enum machine_mode fmode = mode;
5539 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5541 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5543 /* Currently, we only ever need one reg here because complex
5544 doubles are split. */
5545 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
5548 /* Long double split over regs and memory. */
5552 /* Do we also need to pass this arg in the parameter save
5555 && (cum->nargs_prototype <= 0
5556 || (DEFAULT_ABI == ABI_AIX
5558 && align_words >= GP_ARG_NUM_REG)));
5560 if (!needs_psave && mode == fmode)
5561 return gen_rtx_REG (fmode, cum->fregno);
5566 /* Describe the part that goes in gprs or the stack.
5567 This piece must come first, before the fprs. */
5568 if (align_words < GP_ARG_NUM_REG)
5570 unsigned long n_words = rs6000_arg_size (mode, type);
5572 if (align_words + n_words > GP_ARG_NUM_REG
5573 || (TARGET_32BIT && TARGET_POWERPC64))
5575 /* If this is partially on the stack, then we only
5576 include the portion actually in registers here. */
5577 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5580 if (align_words + n_words > GP_ARG_NUM_REG
5581 && (TARGET_32BIT && TARGET_POWERPC64))
5582 /* Not all of the arg fits in gprs. Say that it
5583 goes in memory too, using a magic NULL_RTX
5584 component. Also see comment in
5585 rs6000_mixed_function_arg for why the normal
5586 function_arg_partial_nregs scheme doesn't work
5588 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5592 r = gen_rtx_REG (rmode,
5593 GP_ARG_MIN_REG + align_words);
5594 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5595 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5597 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5601 /* The whole arg fits in gprs. */
5602 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5603 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5607 /* It's entirely in memory. */
5608 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5611 /* Describe where this piece goes in the fprs. */
5612 r = gen_rtx_REG (fmode, cum->fregno);
5613 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5615 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5617 else if (align_words < GP_ARG_NUM_REG)
5619 if (TARGET_32BIT && TARGET_POWERPC64)
5620 return rs6000_mixed_function_arg (mode, type, align_words);
5622 if (mode == BLKmode)
5625 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5632 /* For an arg passed partly in registers and partly in memory, this is
5633 the number of registers used. For args passed entirely in registers
5634 or entirely in memory, zero. When an arg is described by a PARALLEL,
5635 perhaps using more than one register type, this function returns the
5636 number of bytes of registers used by the PARALLEL. */
5639 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5640 tree type, bool named)
5647 if (DEFAULT_ABI == ABI_V4)
5650 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5651 && cum->nargs_prototype >= 0)
5654 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5655 parm_offset = TARGET_32BIT ? 2 : 0;
5656 align_words = cum->words + ((parm_offset - cum->words) & align);
5658 if (USE_FP_FOR_ARG_P (cum, mode, type)
5659 /* If we are passing this arg in gprs as well, then this function
5660 should return the number of gprs (or memory) partially passed,
5661 *not* the number of fprs. */
5663 && (cum->nargs_prototype <= 0
5664 || (DEFAULT_ABI == ABI_AIX
5666 && align_words >= GP_ARG_NUM_REG))))
5668 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5669 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
5670 else if (cum->nargs_prototype >= 0)
5674 if (align_words < GP_ARG_NUM_REG
5675 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5676 ret = GP_ARG_NUM_REG - align_words;
5678 ret *= (TARGET_32BIT ? 4 : 8);
5680 if (ret != 0 && TARGET_DEBUG_ARG)
5681 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5686 /* A C expression that indicates when an argument must be passed by
5687 reference. If nonzero for an argument, a copy of that argument is
5688 made in memory and a pointer to the argument is passed instead of
5689 the argument itself. The pointer is passed in whatever way is
5690 appropriate for passing a pointer to that type.
5692 Under V.4, aggregates and long double are passed by reference.
5694 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5695 reference unless the AltiVec vector extension ABI is in force.
5697 As an extension to all ABIs, variable sized types are passed by
5701 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5702 enum machine_mode mode, tree type,
5703 bool named ATTRIBUTE_UNUSED)
5705 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5707 if (TARGET_DEBUG_ARG)
5708 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5715 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5717 if (TARGET_DEBUG_ARG)
5718 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5722 if (int_size_in_bytes (type) < 0)
5724 if (TARGET_DEBUG_ARG)
5725 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5729 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5730 modes only exist for GCC vector types if -maltivec. */
5731 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5733 if (TARGET_DEBUG_ARG)
5734 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5738 /* Pass synthetic vectors in memory. */
5739 if (TREE_CODE (type) == VECTOR_TYPE
5740 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5742 static bool warned_for_pass_big_vectors = false;
5743 if (TARGET_DEBUG_ARG)
5744 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5745 if (!warned_for_pass_big_vectors)
5747 warning ("GCC vector passed by reference: "
5748 "non-standard ABI extension with no compatibility guarantee");
5749 warned_for_pass_big_vectors = true;
5758 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5761 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5766 for (i = 0; i < nregs; i++)
5768 rtx tem = adjust_address_nv (x, reg_mode, i*GET_MODE_SIZE(reg_mode));
5769 if (reload_completed)
5771 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5774 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5775 i * GET_MODE_SIZE(reg_mode));
5778 tem = replace_equiv_address (tem, XEXP (tem, 0));
5780 if (tem == NULL_RTX)
5783 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5787 /* Perform any needed actions needed for a function that is receiving a
5788 variable number of arguments.
5792 MODE and TYPE are the mode and type of the current parameter.
5794 PRETEND_SIZE is a variable that should be set to the amount of stack
5795 that must be pushed by the prolog to pretend that our caller pushed
5798 Normally, this macro will push all remaining incoming registers on the
5799 stack and set PRETEND_SIZE to the length of the registers pushed. */
5802 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5803 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5806 CUMULATIVE_ARGS next_cum;
5807 int reg_size = TARGET_32BIT ? 4 : 8;
5808 rtx save_area = NULL_RTX, mem;
5809 int first_reg_offset, set;
5811 /* Skip the last named argument. */
5813 function_arg_advance (&next_cum, mode, type, 1, 0);
5815 if (DEFAULT_ABI == ABI_V4)
5818 save_area = plus_constant (virtual_stack_vars_rtx,
5819 - RS6000_VARARGS_SIZE);
5821 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5825 first_reg_offset = next_cum.words;
5826 save_area = virtual_incoming_args_rtx;
5828 if (targetm.calls.must_pass_in_stack (mode, type))
5829 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5832 set = get_varargs_alias_set ();
5833 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5835 mem = gen_rtx_MEM (BLKmode,
5836 plus_constant (save_area,
5837 first_reg_offset * reg_size)),
5838 set_mem_alias_set (mem, set);
5839 set_mem_align (mem, BITS_PER_WORD);
5841 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5842 GP_ARG_NUM_REG - first_reg_offset);
5845 /* Save FP registers if needed. */
5846 if (DEFAULT_ABI == ABI_V4
5847 && TARGET_HARD_FLOAT && TARGET_FPRS
5849 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5851 int fregno = next_cum.fregno;
5852 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5853 rtx lab = gen_label_rtx ();
5854 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5857 (gen_rtx_SET (VOIDmode,
5859 gen_rtx_IF_THEN_ELSE (VOIDmode,
5860 gen_rtx_NE (VOIDmode, cr1,
5862 gen_rtx_LABEL_REF (VOIDmode, lab),
5865 while (fregno <= FP_ARG_V4_MAX_REG)
5867 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5868 set_mem_alias_set (mem, set);
5869 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5870 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5879 /* Create the va_list data type. */
5882 rs6000_build_builtin_va_list (void)
5884 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5886 /* For AIX, prefer 'char *' because that's what the system
5887 header files like. */
5888 if (DEFAULT_ABI != ABI_V4)
5889 return build_pointer_type (char_type_node);
5891 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5892 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5894 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5895 unsigned_char_type_node);
5896 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5897 unsigned_char_type_node);
5898 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5900 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5901 short_unsigned_type_node);
5902 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5904 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5907 DECL_FIELD_CONTEXT (f_gpr) = record;
5908 DECL_FIELD_CONTEXT (f_fpr) = record;
5909 DECL_FIELD_CONTEXT (f_res) = record;
5910 DECL_FIELD_CONTEXT (f_ovf) = record;
5911 DECL_FIELD_CONTEXT (f_sav) = record;
5913 TREE_CHAIN (record) = type_decl;
5914 TYPE_NAME (record) = type_decl;
5915 TYPE_FIELDS (record) = f_gpr;
5916 TREE_CHAIN (f_gpr) = f_fpr;
5917 TREE_CHAIN (f_fpr) = f_res;
5918 TREE_CHAIN (f_res) = f_ovf;
5919 TREE_CHAIN (f_ovf) = f_sav;
5921 layout_type (record);
5923 /* The correct type is an array type of one element. */
5924 return build_array_type (record, build_index_type (size_zero_node));
5927 /* Implement va_start. */
5930 rs6000_va_start (tree valist, rtx nextarg)
5932 HOST_WIDE_INT words, n_gpr, n_fpr;
5933 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5934 tree gpr, fpr, ovf, sav, t;
5936 /* Only SVR4 needs something special. */
5937 if (DEFAULT_ABI != ABI_V4)
5939 std_expand_builtin_va_start (valist, nextarg);
5943 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5944 f_fpr = TREE_CHAIN (f_gpr);
5945 f_res = TREE_CHAIN (f_fpr);
5946 f_ovf = TREE_CHAIN (f_res);
5947 f_sav = TREE_CHAIN (f_ovf);
5949 valist = build_va_arg_indirect_ref (valist);
5950 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5951 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5952 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5953 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5955 /* Count number of gp and fp argument registers used. */
5956 words = current_function_args_info.words;
5957 n_gpr = current_function_args_info.sysv_gregno - GP_ARG_MIN_REG;
5958 n_fpr = current_function_args_info.fregno - FP_ARG_MIN_REG;
5960 if (TARGET_DEBUG_ARG)
5961 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5962 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5963 words, n_gpr, n_fpr);
5965 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5966 build_int_cst (NULL_TREE, n_gpr));
5967 TREE_SIDE_EFFECTS (t) = 1;
5968 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5970 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5971 build_int_cst (NULL_TREE, n_fpr));
5972 TREE_SIDE_EFFECTS (t) = 1;
5973 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5975 /* Find the overflow area. */
5976 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5978 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5979 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5980 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5981 TREE_SIDE_EFFECTS (t) = 1;
5982 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5984 /* Find the register save area. */
5985 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5986 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5987 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5988 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5989 TREE_SIDE_EFFECTS (t) = 1;
5990 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5993 /* Implement va_arg. */
5996 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5998 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5999 tree gpr, fpr, ovf, sav, reg, t, u;
6000 int size, rsize, n_reg, sav_ofs, sav_scale;
6001 tree lab_false, lab_over, addr;
6003 tree ptrtype = build_pointer_type (type);
6005 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6007 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6008 return build_va_arg_indirect_ref (t);
6011 if (DEFAULT_ABI != ABI_V4)
6013 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6015 tree elem_type = TREE_TYPE (type);
6016 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6017 int elem_size = GET_MODE_SIZE (elem_mode);
6019 if (elem_size < UNITS_PER_WORD)
6021 tree real_part, imag_part;
6022 tree post = NULL_TREE;
6024 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6026 /* Copy the value into a temporary, lest the formal temporary
6027 be reused out from under us. */
6028 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6029 append_to_statement_list (post, pre_p);
6031 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6034 return build (COMPLEX_EXPR, type, real_part, imag_part);
6038 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6041 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6042 f_fpr = TREE_CHAIN (f_gpr);
6043 f_res = TREE_CHAIN (f_fpr);
6044 f_ovf = TREE_CHAIN (f_res);
6045 f_sav = TREE_CHAIN (f_ovf);
6047 valist = build_va_arg_indirect_ref (valist);
6048 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6049 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6050 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6051 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6053 size = int_size_in_bytes (type);
6054 rsize = (size + 3) / 4;
6057 if (TARGET_HARD_FLOAT && TARGET_FPRS
6058 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
6060 /* FP args go in FP registers, if present. */
6065 if (TYPE_MODE (type) == DFmode)
6070 /* Otherwise into GP registers. */
6079 /* Pull the value out of the saved registers.... */
6082 addr = create_tmp_var (ptr_type_node, "addr");
6083 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6085 /* AltiVec vectors never go in registers when -mabi=altivec. */
6086 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6090 lab_false = create_artificial_label ();
6091 lab_over = create_artificial_label ();
6093 /* Long long and SPE vectors are aligned in the registers.
6094 As are any other 2 gpr item such as complex int due to a
6095 historical mistake. */
6099 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6100 size_int (n_reg - 1));
6101 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6104 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6105 t = build2 (GE_EXPR, boolean_type_node, u, t);
6106 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6107 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6108 gimplify_and_add (t, pre_p);
6112 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6114 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6115 u = build1 (CONVERT_EXPR, integer_type_node, u);
6116 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6117 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6119 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6120 gimplify_and_add (t, pre_p);
6122 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6123 gimplify_and_add (t, pre_p);
6125 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6126 append_to_statement_list (t, pre_p);
6130 /* Ensure that we don't find any more args in regs.
6131 Alignment has taken care of the n_reg == 2 case. */
6132 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6133 gimplify_and_add (t, pre_p);
6137 /* ... otherwise out of the overflow area. */
6139 /* Care for on-stack alignment if needed. */
6143 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6144 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6145 build_int_cst (NULL_TREE, -align));
6147 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6149 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6150 gimplify_and_add (u, pre_p);
6152 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6153 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6154 gimplify_and_add (t, pre_p);
6158 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6159 append_to_statement_list (t, pre_p);
6162 addr = fold_convert (ptrtype, addr);
6163 return build_va_arg_indirect_ref (addr);
6168 #define def_builtin(MASK, NAME, TYPE, CODE) \
6170 if ((MASK) & target_flags) \
6171 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
6175 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6177 static const struct builtin_description bdesc_3arg[] =
6179 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6180 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6181 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6182 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6183 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6184 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6185 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6186 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6187 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6188 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6189 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6190 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6191 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6192 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6193 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6194 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6195 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6196 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6197 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6198 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6199 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6200 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6201 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6204 /* DST operations: void foo (void *, const int, const char). */
6206 static const struct builtin_description bdesc_dst[] =
6208 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6209 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6210 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6211 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
6214 /* Simple binary operations: VECc = foo (VECa, VECb). */
6216 static struct builtin_description bdesc_2arg[] =
6218 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6219 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6220 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6221 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6222 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6223 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6224 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6225 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6226 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6227 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6228 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6229 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6230 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6231 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6232 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6233 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6234 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6235 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6236 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6237 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6238 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6239 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6240 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6241 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6242 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6243 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6244 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6245 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6246 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6247 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6248 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6249 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6250 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6251 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6252 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6253 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6254 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6255 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6256 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6257 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6258 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6259 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6260 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6261 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6262 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6263 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6264 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6265 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6266 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6267 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6268 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6269 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6270 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6271 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6272 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6273 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6274 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6275 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6276 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6277 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6278 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6279 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6280 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6281 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6282 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6283 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6284 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6285 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6286 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6287 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
6288 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6289 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
6290 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6291 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6292 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6293 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6294 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6295 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6296 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6297 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6298 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6299 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6300 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6301 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6302 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6303 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6304 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6305 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6306 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6307 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6308 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6309 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6310 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6311 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6312 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6313 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6314 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6315 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6316 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6317 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6318 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6319 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6320 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6321 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6322 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6323 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6324 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6325 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6326 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6327 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6328 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6329 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6330 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6332 /* Place holder, leave as first spe builtin. */
6333 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6334 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6335 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6336 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6337 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6338 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6339 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6340 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6341 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6342 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6343 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6344 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6345 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6346 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6347 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6348 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6349 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6350 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6351 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6352 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6353 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6354 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6355 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6356 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6357 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6358 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6359 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6360 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6361 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6362 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6363 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6364 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6365 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6366 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6367 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6368 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6369 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6370 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6371 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6372 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6373 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6374 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6375 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6376 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6377 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6378 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6379 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6380 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6381 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6382 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6383 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6384 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6385 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6386 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6387 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6388 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6389 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6390 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6391 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6392 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6393 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6394 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6395 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6396 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6397 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6398 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6399 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6400 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6401 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6402 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6403 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6404 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6405 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6406 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6407 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6408 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6409 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6410 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6411 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6412 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6413 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6414 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6415 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6416 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6417 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6418 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6419 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6420 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6421 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6422 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6423 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6424 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6425 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6426 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6427 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6428 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6429 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6430 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6431 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6432 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6433 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6434 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6435 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6436 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6437 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6438 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6439 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6440 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6441 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6443 /* SPE binary operations expecting a 5-bit unsigned literal. */
6444 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6446 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6447 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6448 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6449 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6450 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6451 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6452 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6453 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6454 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6455 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6456 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6457 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6458 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6459 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6460 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6461 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6462 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6463 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6464 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6465 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6466 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6467 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6468 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6469 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6470 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6471 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6473 /* Place-holder. Leave as last binary SPE builtin. */
6474 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
6477 /* AltiVec predicates. */
6479 struct builtin_description_predicates
6481 const unsigned int mask;
6482 const enum insn_code icode;
6484 const char *const name;
6485 const enum rs6000_builtins code;
6488 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6490 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6491 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6492 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6493 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6494 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6495 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6496 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6497 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6498 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6499 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6500 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6501 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6502 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
6505 /* SPE predicates. */
6506 static struct builtin_description bdesc_spe_predicates[] =
6508 /* Place-holder. Leave as first. */
6509 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6510 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6511 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6512 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6513 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6514 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6515 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6516 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6517 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6518 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6519 /* Place-holder. Leave as last. */
6520 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6523 /* SPE evsel predicates. */
6524 static struct builtin_description bdesc_spe_evsel[] =
6526 /* Place-holder. Leave as first. */
6527 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6528 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6529 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6530 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6531 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6532 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6533 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6534 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6535 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6536 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6537 /* Place-holder. Leave as last. */
6538 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6541 /* ABS* operations. */
6543 static const struct builtin_description bdesc_abs[] =
6545 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6546 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6547 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6548 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6549 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6550 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6551 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6554 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6557 static struct builtin_description bdesc_1arg[] =
6559 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6560 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6561 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6562 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6563 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6564 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6565 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6566 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6567 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6568 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6569 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6570 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6571 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6572 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6573 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6574 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6575 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6577 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6578 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6579 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6580 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6581 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6582 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6583 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6584 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6585 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6586 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6587 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6588 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6589 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6590 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6591 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6592 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6593 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6594 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6595 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6596 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6597 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6598 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6599 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6600 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6601 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6602 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6603 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6604 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6605 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6606 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6608 /* Place-holder. Leave as last unary SPE builtin. */
6609 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
6613 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6616 tree arg0 = TREE_VALUE (arglist);
6617 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6618 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6619 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6621 if (icode == CODE_FOR_nothing)
6622 /* Builtin not supported on this processor. */
6625 /* If we got invalid arguments bail out before generating bad rtl. */
6626 if (arg0 == error_mark_node)
6629 if (icode == CODE_FOR_altivec_vspltisb
6630 || icode == CODE_FOR_altivec_vspltish
6631 || icode == CODE_FOR_altivec_vspltisw
6632 || icode == CODE_FOR_spe_evsplatfi
6633 || icode == CODE_FOR_spe_evsplati)
6635 /* Only allow 5-bit *signed* literals. */
6636 if (GET_CODE (op0) != CONST_INT
6637 || INTVAL (op0) > 0x1f
6638 || INTVAL (op0) < -0x1f)
6640 error ("argument 1 must be a 5-bit signed literal");
6646 || GET_MODE (target) != tmode
6647 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6648 target = gen_reg_rtx (tmode);
6650 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6651 op0 = copy_to_mode_reg (mode0, op0);
6653 pat = GEN_FCN (icode) (target, op0);
6662 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6664 rtx pat, scratch1, scratch2;
6665 tree arg0 = TREE_VALUE (arglist);
6666 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6667 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6668 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6670 /* If we have invalid arguments, bail out before generating bad rtl. */
6671 if (arg0 == error_mark_node)
6675 || GET_MODE (target) != tmode
6676 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6677 target = gen_reg_rtx (tmode);
6679 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6680 op0 = copy_to_mode_reg (mode0, op0);
6682 scratch1 = gen_reg_rtx (mode0);
6683 scratch2 = gen_reg_rtx (mode0);
6685 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6694 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6697 tree arg0 = TREE_VALUE (arglist);
6698 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6699 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6700 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6701 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6702 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6703 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6705 if (icode == CODE_FOR_nothing)
6706 /* Builtin not supported on this processor. */
6709 /* If we got invalid arguments bail out before generating bad rtl. */
6710 if (arg0 == error_mark_node || arg1 == error_mark_node)
6713 if (icode == CODE_FOR_altivec_vcfux
6714 || icode == CODE_FOR_altivec_vcfsx
6715 || icode == CODE_FOR_altivec_vctsxs
6716 || icode == CODE_FOR_altivec_vctuxs
6717 || icode == CODE_FOR_altivec_vspltb
6718 || icode == CODE_FOR_altivec_vsplth
6719 || icode == CODE_FOR_altivec_vspltw
6720 || icode == CODE_FOR_spe_evaddiw
6721 || icode == CODE_FOR_spe_evldd
6722 || icode == CODE_FOR_spe_evldh
6723 || icode == CODE_FOR_spe_evldw
6724 || icode == CODE_FOR_spe_evlhhesplat
6725 || icode == CODE_FOR_spe_evlhhossplat
6726 || icode == CODE_FOR_spe_evlhhousplat
6727 || icode == CODE_FOR_spe_evlwhe
6728 || icode == CODE_FOR_spe_evlwhos
6729 || icode == CODE_FOR_spe_evlwhou
6730 || icode == CODE_FOR_spe_evlwhsplat
6731 || icode == CODE_FOR_spe_evlwwsplat
6732 || icode == CODE_FOR_spe_evrlwi
6733 || icode == CODE_FOR_spe_evslwi
6734 || icode == CODE_FOR_spe_evsrwis
6735 || icode == CODE_FOR_spe_evsubifw
6736 || icode == CODE_FOR_spe_evsrwiu)
6738 /* Only allow 5-bit unsigned literals. */
6740 if (TREE_CODE (arg1) != INTEGER_CST
6741 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6743 error ("argument 2 must be a 5-bit unsigned literal");
6749 || GET_MODE (target) != tmode
6750 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6751 target = gen_reg_rtx (tmode);
6753 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6754 op0 = copy_to_mode_reg (mode0, op0);
6755 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6756 op1 = copy_to_mode_reg (mode1, op1);
6758 pat = GEN_FCN (icode) (target, op0, op1);
6767 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6768 tree arglist, rtx target)
6771 tree cr6_form = TREE_VALUE (arglist);
6772 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6773 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6774 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6775 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6776 enum machine_mode tmode = SImode;
6777 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6778 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6781 if (TREE_CODE (cr6_form) != INTEGER_CST)
6783 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6787 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6792 /* If we have invalid arguments, bail out before generating bad rtl. */
6793 if (arg0 == error_mark_node || arg1 == error_mark_node)
6797 || GET_MODE (target) != tmode
6798 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6799 target = gen_reg_rtx (tmode);
6801 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6802 op0 = copy_to_mode_reg (mode0, op0);
6803 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6804 op1 = copy_to_mode_reg (mode1, op1);
6806 scratch = gen_reg_rtx (mode0);
6808 pat = GEN_FCN (icode) (scratch, op0, op1,
6809 gen_rtx_SYMBOL_REF (Pmode, opcode));
6814 /* The vec_any* and vec_all* predicates use the same opcodes for two
6815 different operations, but the bits in CR6 will be different
6816 depending on what information we want. So we have to play tricks
6817 with CR6 to get the right bits out.
6819 If you think this is disgusting, look at the specs for the
6820 AltiVec predicates. */
6822 switch (cr6_form_int)
6825 emit_insn (gen_cr6_test_for_zero (target));
6828 emit_insn (gen_cr6_test_for_zero_reverse (target));
6831 emit_insn (gen_cr6_test_for_lt (target));
6834 emit_insn (gen_cr6_test_for_lt_reverse (target));
6837 error ("argument 1 of __builtin_altivec_predicate is out of range");
6845 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6848 tree arg0 = TREE_VALUE (arglist);
6849 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6850 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6851 enum machine_mode mode0 = Pmode;
6852 enum machine_mode mode1 = Pmode;
6853 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6854 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6856 if (icode == CODE_FOR_nothing)
6857 /* Builtin not supported on this processor. */
6860 /* If we got invalid arguments bail out before generating bad rtl. */
6861 if (arg0 == error_mark_node || arg1 == error_mark_node)
6865 || GET_MODE (target) != tmode
6866 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6867 target = gen_reg_rtx (tmode);
6869 op1 = copy_to_mode_reg (mode1, op1);
6871 if (op0 == const0_rtx)
6873 addr = gen_rtx_MEM (tmode, op1);
6877 op0 = copy_to_mode_reg (mode0, op0);
6878 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6881 pat = GEN_FCN (icode) (target, addr);
6891 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6893 tree arg0 = TREE_VALUE (arglist);
6894 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6895 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6896 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6897 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6898 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6900 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6901 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6902 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6904 /* Invalid arguments. Bail before doing anything stoopid! */
6905 if (arg0 == error_mark_node
6906 || arg1 == error_mark_node
6907 || arg2 == error_mark_node)
6910 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6911 op0 = copy_to_mode_reg (mode2, op0);
6912 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6913 op1 = copy_to_mode_reg (mode0, op1);
6914 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6915 op2 = copy_to_mode_reg (mode1, op2);
6917 pat = GEN_FCN (icode) (op1, op2, op0);
6924 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6926 tree arg0 = TREE_VALUE (arglist);
6927 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6928 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6929 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6930 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6931 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6933 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6934 enum machine_mode mode1 = Pmode;
6935 enum machine_mode mode2 = Pmode;
6937 /* Invalid arguments. Bail before doing anything stoopid! */
6938 if (arg0 == error_mark_node
6939 || arg1 == error_mark_node
6940 || arg2 == error_mark_node)
6943 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6944 op0 = copy_to_mode_reg (tmode, op0);
6946 op2 = copy_to_mode_reg (mode2, op2);
6948 if (op1 == const0_rtx)
6950 addr = gen_rtx_MEM (tmode, op2);
6954 op1 = copy_to_mode_reg (mode1, op1);
6955 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6958 pat = GEN_FCN (icode) (addr, op0);
6965 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6968 tree arg0 = TREE_VALUE (arglist);
6969 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6970 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6971 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6972 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6973 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6974 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6975 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6976 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6977 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6979 if (icode == CODE_FOR_nothing)
6980 /* Builtin not supported on this processor. */
6983 /* If we got invalid arguments bail out before generating bad rtl. */
6984 if (arg0 == error_mark_node
6985 || arg1 == error_mark_node
6986 || arg2 == error_mark_node)
6989 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6990 || icode == CODE_FOR_altivec_vsldoi_v4si
6991 || icode == CODE_FOR_altivec_vsldoi_v8hi
6992 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6994 /* Only allow 4-bit unsigned literals. */
6996 if (TREE_CODE (arg2) != INTEGER_CST
6997 || TREE_INT_CST_LOW (arg2) & ~0xf)
6999 error ("argument 3 must be a 4-bit unsigned literal");
7005 || GET_MODE (target) != tmode
7006 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7007 target = gen_reg_rtx (tmode);
7009 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7010 op0 = copy_to_mode_reg (mode0, op0);
7011 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7012 op1 = copy_to_mode_reg (mode1, op1);
7013 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7014 op2 = copy_to_mode_reg (mode2, op2);
7016 pat = GEN_FCN (icode) (target, op0, op1, op2);
7024 /* Expand the lvx builtins. */
7026 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7028 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7029 tree arglist = TREE_OPERAND (exp, 1);
7030 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7032 enum machine_mode tmode, mode0;
7034 enum insn_code icode;
7038 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7039 icode = CODE_FOR_altivec_lvx_v16qi;
7041 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7042 icode = CODE_FOR_altivec_lvx_v8hi;
7044 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7045 icode = CODE_FOR_altivec_lvx_v4si;
7047 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7048 icode = CODE_FOR_altivec_lvx_v4sf;
7057 arg0 = TREE_VALUE (arglist);
7058 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7059 tmode = insn_data[icode].operand[0].mode;
7060 mode0 = insn_data[icode].operand[1].mode;
7063 || GET_MODE (target) != tmode
7064 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7065 target = gen_reg_rtx (tmode);
7067 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7068 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7070 pat = GEN_FCN (icode) (target, op0);
7077 /* Expand the stvx builtins. */
7079 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7082 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7083 tree arglist = TREE_OPERAND (exp, 1);
7084 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7086 enum machine_mode mode0, mode1;
7088 enum insn_code icode;
7092 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7093 icode = CODE_FOR_altivec_stvx_v16qi;
7095 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7096 icode = CODE_FOR_altivec_stvx_v8hi;
7098 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7099 icode = CODE_FOR_altivec_stvx_v4si;
7101 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7102 icode = CODE_FOR_altivec_stvx_v4sf;
7109 arg0 = TREE_VALUE (arglist);
7110 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7111 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7112 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7113 mode0 = insn_data[icode].operand[0].mode;
7114 mode1 = insn_data[icode].operand[1].mode;
7116 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7117 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7118 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7119 op1 = copy_to_mode_reg (mode1, op1);
7121 pat = GEN_FCN (icode) (op0, op1);
7129 /* Expand the dst builtins. */
7131 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7134 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7135 tree arglist = TREE_OPERAND (exp, 1);
7136 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7137 tree arg0, arg1, arg2;
7138 enum machine_mode mode0, mode1, mode2;
7139 rtx pat, op0, op1, op2;
7140 struct builtin_description *d;
7145 /* Handle DST variants. */
7146 d = (struct builtin_description *) bdesc_dst;
7147 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7148 if (d->code == fcode)
7150 arg0 = TREE_VALUE (arglist);
7151 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7152 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7153 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7154 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7155 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7156 mode0 = insn_data[d->icode].operand[0].mode;
7157 mode1 = insn_data[d->icode].operand[1].mode;
7158 mode2 = insn_data[d->icode].operand[2].mode;
7160 /* Invalid arguments, bail out before generating bad rtl. */
7161 if (arg0 == error_mark_node
7162 || arg1 == error_mark_node
7163 || arg2 == error_mark_node)
7168 if (TREE_CODE (arg2) != INTEGER_CST
7169 || TREE_INT_CST_LOW (arg2) & ~0x3)
7171 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7175 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7176 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7177 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7178 op1 = copy_to_mode_reg (mode1, op1);
7180 pat = GEN_FCN (d->icode) (op0, op1, op2);
7190 /* Expand the builtin in EXP and store the result in TARGET. Store
7191 true in *EXPANDEDP if we found a builtin to expand. */
7193 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7195 struct builtin_description *d;
7196 struct builtin_description_predicates *dp;
7198 enum insn_code icode;
7199 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7200 tree arglist = TREE_OPERAND (exp, 1);
7203 enum machine_mode tmode, mode0;
7204 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7206 target = altivec_expand_ld_builtin (exp, target, expandedp);
7210 target = altivec_expand_st_builtin (exp, target, expandedp);
7214 target = altivec_expand_dst_builtin (exp, target, expandedp);
7222 case ALTIVEC_BUILTIN_STVX:
7223 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7224 case ALTIVEC_BUILTIN_STVEBX:
7225 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7226 case ALTIVEC_BUILTIN_STVEHX:
7227 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7228 case ALTIVEC_BUILTIN_STVEWX:
7229 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7230 case ALTIVEC_BUILTIN_STVXL:
7231 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7233 case ALTIVEC_BUILTIN_MFVSCR:
7234 icode = CODE_FOR_altivec_mfvscr;
7235 tmode = insn_data[icode].operand[0].mode;
7238 || GET_MODE (target) != tmode
7239 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7240 target = gen_reg_rtx (tmode);
7242 pat = GEN_FCN (icode) (target);
7248 case ALTIVEC_BUILTIN_MTVSCR:
7249 icode = CODE_FOR_altivec_mtvscr;
7250 arg0 = TREE_VALUE (arglist);
7251 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7252 mode0 = insn_data[icode].operand[0].mode;
7254 /* If we got invalid arguments bail out before generating bad rtl. */
7255 if (arg0 == error_mark_node)
7258 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7259 op0 = copy_to_mode_reg (mode0, op0);
7261 pat = GEN_FCN (icode) (op0);
7266 case ALTIVEC_BUILTIN_DSSALL:
7267 emit_insn (gen_altivec_dssall ());
7270 case ALTIVEC_BUILTIN_DSS:
7271 icode = CODE_FOR_altivec_dss;
7272 arg0 = TREE_VALUE (arglist);
7274 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7275 mode0 = insn_data[icode].operand[0].mode;
7277 /* If we got invalid arguments bail out before generating bad rtl. */
7278 if (arg0 == error_mark_node)
7281 if (TREE_CODE (arg0) != INTEGER_CST
7282 || TREE_INT_CST_LOW (arg0) & ~0x3)
7284 error ("argument to dss must be a 2-bit unsigned literal");
7288 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7289 op0 = copy_to_mode_reg (mode0, op0);
7291 emit_insn (gen_altivec_dss (op0));
7294 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
7295 arg0 = TREE_VALUE (arglist);
7296 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
7297 || TREE_CODE (arg0) == ARRAY_REF)
7298 arg0 = TREE_OPERAND (arg0, 0);
7299 error ("invalid parameter combination for %qs AltiVec intrinsic",
7300 TREE_STRING_POINTER (arg0));
7305 /* Expand abs* operations. */
7306 d = (struct builtin_description *) bdesc_abs;
7307 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7308 if (d->code == fcode)
7309 return altivec_expand_abs_builtin (d->icode, arglist, target);
7311 /* Expand the AltiVec predicates. */
7312 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7313 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7314 if (dp->code == fcode)
7315 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7318 /* LV* are funky. We initialized them differently. */
7321 case ALTIVEC_BUILTIN_LVSL:
7322 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7324 case ALTIVEC_BUILTIN_LVSR:
7325 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7327 case ALTIVEC_BUILTIN_LVEBX:
7328 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7330 case ALTIVEC_BUILTIN_LVEHX:
7331 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7333 case ALTIVEC_BUILTIN_LVEWX:
7334 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7336 case ALTIVEC_BUILTIN_LVXL:
7337 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7339 case ALTIVEC_BUILTIN_LVX:
7340 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7351 /* Binops that need to be initialized manually, but can be expanded
7352 automagically by rs6000_expand_binop_builtin. */
7353 static struct builtin_description bdesc_2arg_spe[] =
7355 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7356 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7357 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7358 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7359 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7360 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7361 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7362 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7363 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7364 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7365 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7366 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7367 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7368 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7369 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7370 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7371 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7372 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7373 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7374 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7375 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7376 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7379 /* Expand the builtin in EXP and store the result in TARGET. Store
7380 true in *EXPANDEDP if we found a builtin to expand.
7382 This expands the SPE builtins that are not simple unary and binary
7385 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7387 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7388 tree arglist = TREE_OPERAND (exp, 1);
7390 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7391 enum insn_code icode;
7392 enum machine_mode tmode, mode0;
7394 struct builtin_description *d;
7399 /* Syntax check for a 5-bit unsigned immediate. */
7402 case SPE_BUILTIN_EVSTDD:
7403 case SPE_BUILTIN_EVSTDH:
7404 case SPE_BUILTIN_EVSTDW:
7405 case SPE_BUILTIN_EVSTWHE:
7406 case SPE_BUILTIN_EVSTWHO:
7407 case SPE_BUILTIN_EVSTWWE:
7408 case SPE_BUILTIN_EVSTWWO:
7409 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7410 if (TREE_CODE (arg1) != INTEGER_CST
7411 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7413 error ("argument 2 must be a 5-bit unsigned literal");
7421 /* The evsplat*i instructions are not quite generic. */
7424 case SPE_BUILTIN_EVSPLATFI:
7425 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7427 case SPE_BUILTIN_EVSPLATI:
7428 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7434 d = (struct builtin_description *) bdesc_2arg_spe;
7435 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7436 if (d->code == fcode)
7437 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7439 d = (struct builtin_description *) bdesc_spe_predicates;
7440 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7441 if (d->code == fcode)
7442 return spe_expand_predicate_builtin (d->icode, arglist, target);
7444 d = (struct builtin_description *) bdesc_spe_evsel;
7445 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7446 if (d->code == fcode)
7447 return spe_expand_evsel_builtin (d->icode, arglist, target);
7451 case SPE_BUILTIN_EVSTDDX:
7452 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7453 case SPE_BUILTIN_EVSTDHX:
7454 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7455 case SPE_BUILTIN_EVSTDWX:
7456 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7457 case SPE_BUILTIN_EVSTWHEX:
7458 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7459 case SPE_BUILTIN_EVSTWHOX:
7460 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7461 case SPE_BUILTIN_EVSTWWEX:
7462 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7463 case SPE_BUILTIN_EVSTWWOX:
7464 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7465 case SPE_BUILTIN_EVSTDD:
7466 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7467 case SPE_BUILTIN_EVSTDH:
7468 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7469 case SPE_BUILTIN_EVSTDW:
7470 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7471 case SPE_BUILTIN_EVSTWHE:
7472 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7473 case SPE_BUILTIN_EVSTWHO:
7474 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7475 case SPE_BUILTIN_EVSTWWE:
7476 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7477 case SPE_BUILTIN_EVSTWWO:
7478 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7479 case SPE_BUILTIN_MFSPEFSCR:
7480 icode = CODE_FOR_spe_mfspefscr;
7481 tmode = insn_data[icode].operand[0].mode;
7484 || GET_MODE (target) != tmode
7485 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7486 target = gen_reg_rtx (tmode);
7488 pat = GEN_FCN (icode) (target);
7493 case SPE_BUILTIN_MTSPEFSCR:
7494 icode = CODE_FOR_spe_mtspefscr;
7495 arg0 = TREE_VALUE (arglist);
7496 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7497 mode0 = insn_data[icode].operand[0].mode;
7499 if (arg0 == error_mark_node)
7502 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7503 op0 = copy_to_mode_reg (mode0, op0);
7505 pat = GEN_FCN (icode) (op0);
7518 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7520 rtx pat, scratch, tmp;
7521 tree form = TREE_VALUE (arglist);
7522 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7523 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7524 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7525 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7526 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7527 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7531 if (TREE_CODE (form) != INTEGER_CST)
7533 error ("argument 1 of __builtin_spe_predicate must be a constant");
7537 form_int = TREE_INT_CST_LOW (form);
7542 if (arg0 == error_mark_node || arg1 == error_mark_node)
7546 || GET_MODE (target) != SImode
7547 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7548 target = gen_reg_rtx (SImode);
7550 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7551 op0 = copy_to_mode_reg (mode0, op0);
7552 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7553 op1 = copy_to_mode_reg (mode1, op1);
7555 scratch = gen_reg_rtx (CCmode);
7557 pat = GEN_FCN (icode) (scratch, op0, op1);
7562 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7563 _lower_. We use one compare, but look in different bits of the
7564 CR for each variant.
7566 There are 2 elements in each SPE simd type (upper/lower). The CR
7567 bits are set as follows:
7569 BIT0 | BIT 1 | BIT 2 | BIT 3
7570 U | L | (U | L) | (U & L)
7572 So, for an "all" relationship, BIT 3 would be set.
7573 For an "any" relationship, BIT 2 would be set. Etc.
7575 Following traditional nomenclature, these bits map to:
7577 BIT0 | BIT 1 | BIT 2 | BIT 3
7580 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7585 /* All variant. OV bit. */
7587 /* We need to get to the OV bit, which is the ORDERED bit. We
7588 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7589 that's ugly and will trigger a validate_condition_mode abort.
7590 So let's just use another pattern. */
7591 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7593 /* Any variant. EQ bit. */
7597 /* Upper variant. LT bit. */
7601 /* Lower variant. GT bit. */
7606 error ("argument 1 of __builtin_spe_predicate is out of range");
7610 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7611 emit_move_insn (target, tmp);
7616 /* The evsel builtins look like this:
7618 e = __builtin_spe_evsel_OP (a, b, c, d);
7622 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7623 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7627 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7630 tree arg0 = TREE_VALUE (arglist);
7631 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7632 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7633 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7634 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7635 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7636 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7637 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7638 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7639 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7644 if (arg0 == error_mark_node || arg1 == error_mark_node
7645 || arg2 == error_mark_node || arg3 == error_mark_node)
7649 || GET_MODE (target) != mode0
7650 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7651 target = gen_reg_rtx (mode0);
7653 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7654 op0 = copy_to_mode_reg (mode0, op0);
7655 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7656 op1 = copy_to_mode_reg (mode0, op1);
7657 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7658 op2 = copy_to_mode_reg (mode0, op2);
7659 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7660 op3 = copy_to_mode_reg (mode0, op3);
7662 /* Generate the compare. */
7663 scratch = gen_reg_rtx (CCmode);
7664 pat = GEN_FCN (icode) (scratch, op0, op1);
7669 if (mode0 == V2SImode)
7670 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7672 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7677 /* Expand an expression EXP that calls a built-in function,
7678 with result going to TARGET if that's convenient
7679 (and in mode MODE if that's convenient).
7680 SUBTARGET may be used as the target for computing one of EXP's operands.
7681 IGNORE is nonzero if the value is to be ignored. */
7684 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7685 enum machine_mode mode ATTRIBUTE_UNUSED,
7686 int ignore ATTRIBUTE_UNUSED)
7688 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7689 tree arglist = TREE_OPERAND (exp, 1);
7690 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7691 struct builtin_description *d;
7696 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7697 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7699 int icode = (int) CODE_FOR_altivec_lvsr;
7700 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7701 enum machine_mode mode = insn_data[icode].operand[1].mode;
7705 if (!TARGET_ALTIVEC)
7708 arg = TREE_VALUE (arglist);
7709 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7711 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7712 addr = memory_address (mode, op);
7713 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7717 /* For the load case need to negate the address. */
7718 op = gen_reg_rtx (GET_MODE (addr));
7719 emit_insn (gen_rtx_SET (VOIDmode, op,
7720 gen_rtx_NEG (GET_MODE (addr), addr)));
7722 op = gen_rtx_MEM (mode, op);
7725 || GET_MODE (target) != tmode
7726 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7727 target = gen_reg_rtx (tmode);
7729 /*pat = gen_altivec_lvsr (target, op);*/
7730 pat = GEN_FCN (icode) (target, op);
7740 ret = altivec_expand_builtin (exp, target, &success);
7747 ret = spe_expand_builtin (exp, target, &success);
7753 if (TARGET_ALTIVEC || TARGET_SPE)
7755 /* Handle simple unary operations. */
7756 d = (struct builtin_description *) bdesc_1arg;
7757 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7758 if (d->code == fcode)
7759 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7761 /* Handle simple binary operations. */
7762 d = (struct builtin_description *) bdesc_2arg;
7763 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7764 if (d->code == fcode)
7765 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7767 /* Handle simple ternary operations. */
7768 d = (struct builtin_description *) bdesc_3arg;
7769 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7770 if (d->code == fcode)
7771 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7779 build_opaque_vector_type (tree node, int nunits)
7781 node = copy_node (node);
7782 TYPE_MAIN_VARIANT (node) = node;
7783 return build_vector_type (node, nunits);
7787 rs6000_init_builtins (void)
7789 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7790 V2SF_type_node = build_vector_type (float_type_node, 2);
7791 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7792 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7793 V4SF_type_node = build_vector_type (float_type_node, 4);
7794 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7795 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7797 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7798 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7799 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7801 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7802 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7803 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7805 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7806 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7807 'vector unsigned short'. */
7809 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7810 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7811 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7812 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7814 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7815 get_identifier ("__bool char"),
7816 bool_char_type_node));
7817 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7818 get_identifier ("__bool short"),
7819 bool_short_type_node));
7820 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7821 get_identifier ("__bool int"),
7822 bool_int_type_node));
7823 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7824 get_identifier ("__pixel"),
7827 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7828 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7829 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7830 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7832 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7833 get_identifier ("__vector unsigned char"),
7834 unsigned_V16QI_type_node));
7835 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7836 get_identifier ("__vector signed char"),
7838 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7839 get_identifier ("__vector __bool char"),
7840 bool_V16QI_type_node));
7842 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7843 get_identifier ("__vector unsigned short"),
7844 unsigned_V8HI_type_node));
7845 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7846 get_identifier ("__vector signed short"),
7848 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7849 get_identifier ("__vector __bool short"),
7850 bool_V8HI_type_node));
7852 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7853 get_identifier ("__vector unsigned int"),
7854 unsigned_V4SI_type_node));
7855 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7856 get_identifier ("__vector signed int"),
7858 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7859 get_identifier ("__vector __bool int"),
7860 bool_V4SI_type_node));
7862 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7863 get_identifier ("__vector float"),
7865 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7866 get_identifier ("__vector __pixel"),
7867 pixel_V8HI_type_node));
7870 spe_init_builtins ();
7872 altivec_init_builtins ();
7873 if (TARGET_ALTIVEC || TARGET_SPE)
7874 rs6000_common_init_builtins ();
7877 /* Search through a set of builtins and enable the mask bits.
7878 DESC is an array of builtins.
7879 SIZE is the total number of builtins.
7880 START is the builtin enum at which to start.
7881 END is the builtin enum at which to end. */
7883 enable_mask_for_builtins (struct builtin_description *desc, int size,
7884 enum rs6000_builtins start,
7885 enum rs6000_builtins end)
7889 for (i = 0; i < size; ++i)
7890 if (desc[i].code == start)
7896 for (; i < size; ++i)
7898 /* Flip all the bits on. */
7899 desc[i].mask = target_flags;
7900 if (desc[i].code == end)
7906 spe_init_builtins (void)
7908 tree endlink = void_list_node;
7909 tree puint_type_node = build_pointer_type (unsigned_type_node);
7910 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7911 struct builtin_description *d;
7914 tree v2si_ftype_4_v2si
7915 = build_function_type
7916 (opaque_V2SI_type_node,
7917 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7918 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7919 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7920 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7923 tree v2sf_ftype_4_v2sf
7924 = build_function_type
7925 (opaque_V2SF_type_node,
7926 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7927 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7928 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7929 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7932 tree int_ftype_int_v2si_v2si
7933 = build_function_type
7935 tree_cons (NULL_TREE, integer_type_node,
7936 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7937 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7940 tree int_ftype_int_v2sf_v2sf
7941 = build_function_type
7943 tree_cons (NULL_TREE, integer_type_node,
7944 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7945 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7948 tree void_ftype_v2si_puint_int
7949 = build_function_type (void_type_node,
7950 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7951 tree_cons (NULL_TREE, puint_type_node,
7952 tree_cons (NULL_TREE,
7956 tree void_ftype_v2si_puint_char
7957 = build_function_type (void_type_node,
7958 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7959 tree_cons (NULL_TREE, puint_type_node,
7960 tree_cons (NULL_TREE,
7964 tree void_ftype_v2si_pv2si_int
7965 = build_function_type (void_type_node,
7966 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7967 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7968 tree_cons (NULL_TREE,
7972 tree void_ftype_v2si_pv2si_char
7973 = build_function_type (void_type_node,
7974 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7975 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7976 tree_cons (NULL_TREE,
7981 = build_function_type (void_type_node,
7982 tree_cons (NULL_TREE, integer_type_node, endlink));
7985 = build_function_type (integer_type_node, endlink);
7987 tree v2si_ftype_pv2si_int
7988 = build_function_type (opaque_V2SI_type_node,
7989 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7990 tree_cons (NULL_TREE, integer_type_node,
7993 tree v2si_ftype_puint_int
7994 = build_function_type (opaque_V2SI_type_node,
7995 tree_cons (NULL_TREE, puint_type_node,
7996 tree_cons (NULL_TREE, integer_type_node,
7999 tree v2si_ftype_pushort_int
8000 = build_function_type (opaque_V2SI_type_node,
8001 tree_cons (NULL_TREE, pushort_type_node,
8002 tree_cons (NULL_TREE, integer_type_node,
8005 tree v2si_ftype_signed_char
8006 = build_function_type (opaque_V2SI_type_node,
8007 tree_cons (NULL_TREE, signed_char_type_node,
8010 /* The initialization of the simple binary and unary builtins is
8011 done in rs6000_common_init_builtins, but we have to enable the
8012 mask bits here manually because we have run out of `target_flags'
8013 bits. We really need to redesign this mask business. */
8015 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8016 ARRAY_SIZE (bdesc_2arg),
8019 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8020 ARRAY_SIZE (bdesc_1arg),
8022 SPE_BUILTIN_EVSUBFUSIAAW);
8023 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8024 ARRAY_SIZE (bdesc_spe_predicates),
8025 SPE_BUILTIN_EVCMPEQ,
8026 SPE_BUILTIN_EVFSTSTLT);
8027 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8028 ARRAY_SIZE (bdesc_spe_evsel),
8029 SPE_BUILTIN_EVSEL_CMPGTS,
8030 SPE_BUILTIN_EVSEL_FSTSTEQ);
8032 (*lang_hooks.decls.pushdecl)
8033 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8034 opaque_V2SI_type_node));
8036 /* Initialize irregular SPE builtins. */
8038 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8039 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8040 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8041 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8042 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8043 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8044 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8045 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8046 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8047 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8048 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8049 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8050 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8051 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8052 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8053 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8054 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8055 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8058 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8059 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8060 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8061 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8062 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8063 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8064 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8065 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8066 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8067 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8068 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8069 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8070 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8071 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8072 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8073 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8074 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8075 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8076 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8077 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8078 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8079 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8082 d = (struct builtin_description *) bdesc_spe_predicates;
8083 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8087 switch (insn_data[d->icode].operand[1].mode)
8090 type = int_ftype_int_v2si_v2si;
8093 type = int_ftype_int_v2sf_v2sf;
8099 def_builtin (d->mask, d->name, type, d->code);
8102 /* Evsel predicates. */
8103 d = (struct builtin_description *) bdesc_spe_evsel;
8104 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8108 switch (insn_data[d->icode].operand[1].mode)
8111 type = v2si_ftype_4_v2si;
8114 type = v2sf_ftype_4_v2sf;
8120 def_builtin (d->mask, d->name, type, d->code);
8125 altivec_init_builtins (void)
8127 struct builtin_description *d;
8128 struct builtin_description_predicates *dp;
8130 tree pfloat_type_node = build_pointer_type (float_type_node);
8131 tree pint_type_node = build_pointer_type (integer_type_node);
8132 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8133 tree pchar_type_node = build_pointer_type (char_type_node);
8135 tree pvoid_type_node = build_pointer_type (void_type_node);
8137 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8138 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8139 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8140 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8142 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8144 tree int_ftype_int_v4si_v4si
8145 = build_function_type_list (integer_type_node,
8146 integer_type_node, V4SI_type_node,
8147 V4SI_type_node, NULL_TREE);
8148 tree v4sf_ftype_pcfloat
8149 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8150 tree void_ftype_pfloat_v4sf
8151 = build_function_type_list (void_type_node,
8152 pfloat_type_node, V4SF_type_node, NULL_TREE);
8153 tree v4si_ftype_pcint
8154 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8155 tree void_ftype_pint_v4si
8156 = build_function_type_list (void_type_node,
8157 pint_type_node, V4SI_type_node, NULL_TREE);
8158 tree v8hi_ftype_pcshort
8159 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8160 tree void_ftype_pshort_v8hi
8161 = build_function_type_list (void_type_node,
8162 pshort_type_node, V8HI_type_node, NULL_TREE);
8163 tree v16qi_ftype_pcchar
8164 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8165 tree void_ftype_pchar_v16qi
8166 = build_function_type_list (void_type_node,
8167 pchar_type_node, V16QI_type_node, NULL_TREE);
8168 tree void_ftype_v4si
8169 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8170 tree v8hi_ftype_void
8171 = build_function_type (V8HI_type_node, void_list_node);
8172 tree void_ftype_void
8173 = build_function_type (void_type_node, void_list_node);
8175 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8177 tree v16qi_ftype_long_pcvoid
8178 = build_function_type_list (V16QI_type_node,
8179 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8180 tree v8hi_ftype_long_pcvoid
8181 = build_function_type_list (V8HI_type_node,
8182 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8183 tree v4si_ftype_long_pcvoid
8184 = build_function_type_list (V4SI_type_node,
8185 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8187 tree void_ftype_v4si_long_pvoid
8188 = build_function_type_list (void_type_node,
8189 V4SI_type_node, long_integer_type_node,
8190 pvoid_type_node, NULL_TREE);
8191 tree void_ftype_v16qi_long_pvoid
8192 = build_function_type_list (void_type_node,
8193 V16QI_type_node, long_integer_type_node,
8194 pvoid_type_node, NULL_TREE);
8195 tree void_ftype_v8hi_long_pvoid
8196 = build_function_type_list (void_type_node,
8197 V8HI_type_node, long_integer_type_node,
8198 pvoid_type_node, NULL_TREE);
8199 tree int_ftype_int_v8hi_v8hi
8200 = build_function_type_list (integer_type_node,
8201 integer_type_node, V8HI_type_node,
8202 V8HI_type_node, NULL_TREE);
8203 tree int_ftype_int_v16qi_v16qi
8204 = build_function_type_list (integer_type_node,
8205 integer_type_node, V16QI_type_node,
8206 V16QI_type_node, NULL_TREE);
8207 tree int_ftype_int_v4sf_v4sf
8208 = build_function_type_list (integer_type_node,
8209 integer_type_node, V4SF_type_node,
8210 V4SF_type_node, NULL_TREE);
8211 tree v4si_ftype_v4si
8212 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8213 tree v8hi_ftype_v8hi
8214 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8215 tree v16qi_ftype_v16qi
8216 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8217 tree v4sf_ftype_v4sf
8218 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8219 tree void_ftype_pcvoid_int_int
8220 = build_function_type_list (void_type_node,
8221 pcvoid_type_node, integer_type_node,
8222 integer_type_node, NULL_TREE);
8223 tree int_ftype_pcchar
8224 = build_function_type_list (integer_type_node,
8225 pcchar_type_node, NULL_TREE);
8227 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8228 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8229 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8230 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8231 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8232 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8233 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8234 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8235 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8236 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8237 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8238 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8239 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8240 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8241 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8242 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8243 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8244 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8245 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8246 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8247 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8248 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8249 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8250 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8251 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8252 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8253 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8254 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8255 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8256 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8257 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8258 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8260 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
8261 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
8262 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
8264 /* Add the DST variants. */
8265 d = (struct builtin_description *) bdesc_dst;
8266 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8267 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8269 /* Initialize the predicates. */
8270 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8271 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8273 enum machine_mode mode1;
8276 mode1 = insn_data[dp->icode].operand[1].mode;
8281 type = int_ftype_int_v4si_v4si;
8284 type = int_ftype_int_v8hi_v8hi;
8287 type = int_ftype_int_v16qi_v16qi;
8290 type = int_ftype_int_v4sf_v4sf;
8296 def_builtin (dp->mask, dp->name, type, dp->code);
8299 /* Initialize the abs* operators. */
8300 d = (struct builtin_description *) bdesc_abs;
8301 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8303 enum machine_mode mode0;
8306 mode0 = insn_data[d->icode].operand[0].mode;
8311 type = v4si_ftype_v4si;
8314 type = v8hi_ftype_v8hi;
8317 type = v16qi_ftype_v16qi;
8320 type = v4sf_ftype_v4sf;
8326 def_builtin (d->mask, d->name, type, d->code);
8333 /* Initialize target builtin that implements
8334 targetm.vectorize.builtin_mask_for_load. */
8336 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8337 v16qi_ftype_long_pcvoid,
8338 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8339 BUILT_IN_MD, NULL, NULL_TREE);
8340 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8341 altivec_builtin_mask_for_load = decl;
8346 rs6000_common_init_builtins (void)
8348 struct builtin_description *d;
8351 tree v4sf_ftype_v4sf_v4sf_v16qi
8352 = build_function_type_list (V4SF_type_node,
8353 V4SF_type_node, V4SF_type_node,
8354 V16QI_type_node, NULL_TREE);
8355 tree v4si_ftype_v4si_v4si_v16qi
8356 = build_function_type_list (V4SI_type_node,
8357 V4SI_type_node, V4SI_type_node,
8358 V16QI_type_node, NULL_TREE);
8359 tree v8hi_ftype_v8hi_v8hi_v16qi
8360 = build_function_type_list (V8HI_type_node,
8361 V8HI_type_node, V8HI_type_node,
8362 V16QI_type_node, NULL_TREE);
8363 tree v16qi_ftype_v16qi_v16qi_v16qi
8364 = build_function_type_list (V16QI_type_node,
8365 V16QI_type_node, V16QI_type_node,
8366 V16QI_type_node, NULL_TREE);
8368 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8370 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8371 tree v16qi_ftype_int
8372 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8373 tree v8hi_ftype_v16qi
8374 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8375 tree v4sf_ftype_v4sf
8376 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8378 tree v2si_ftype_v2si_v2si
8379 = build_function_type_list (opaque_V2SI_type_node,
8380 opaque_V2SI_type_node,
8381 opaque_V2SI_type_node, NULL_TREE);
8383 tree v2sf_ftype_v2sf_v2sf
8384 = build_function_type_list (opaque_V2SF_type_node,
8385 opaque_V2SF_type_node,
8386 opaque_V2SF_type_node, NULL_TREE);
8388 tree v2si_ftype_int_int
8389 = build_function_type_list (opaque_V2SI_type_node,
8390 integer_type_node, integer_type_node,
8393 tree v2si_ftype_v2si
8394 = build_function_type_list (opaque_V2SI_type_node,
8395 opaque_V2SI_type_node, NULL_TREE);
8397 tree v2sf_ftype_v2sf
8398 = build_function_type_list (opaque_V2SF_type_node,
8399 opaque_V2SF_type_node, NULL_TREE);
8401 tree v2sf_ftype_v2si
8402 = build_function_type_list (opaque_V2SF_type_node,
8403 opaque_V2SI_type_node, NULL_TREE);
8405 tree v2si_ftype_v2sf
8406 = build_function_type_list (opaque_V2SI_type_node,
8407 opaque_V2SF_type_node, NULL_TREE);
8409 tree v2si_ftype_v2si_char
8410 = build_function_type_list (opaque_V2SI_type_node,
8411 opaque_V2SI_type_node,
8412 char_type_node, NULL_TREE);
8414 tree v2si_ftype_int_char
8415 = build_function_type_list (opaque_V2SI_type_node,
8416 integer_type_node, char_type_node, NULL_TREE);
8418 tree v2si_ftype_char
8419 = build_function_type_list (opaque_V2SI_type_node,
8420 char_type_node, NULL_TREE);
8422 tree int_ftype_int_int
8423 = build_function_type_list (integer_type_node,
8424 integer_type_node, integer_type_node,
8427 tree v4si_ftype_v4si_v4si
8428 = build_function_type_list (V4SI_type_node,
8429 V4SI_type_node, V4SI_type_node, NULL_TREE);
8430 tree v4sf_ftype_v4si_int
8431 = build_function_type_list (V4SF_type_node,
8432 V4SI_type_node, integer_type_node, NULL_TREE);
8433 tree v4si_ftype_v4sf_int
8434 = build_function_type_list (V4SI_type_node,
8435 V4SF_type_node, integer_type_node, NULL_TREE);
8436 tree v4si_ftype_v4si_int
8437 = build_function_type_list (V4SI_type_node,
8438 V4SI_type_node, integer_type_node, NULL_TREE);
8439 tree v8hi_ftype_v8hi_int
8440 = build_function_type_list (V8HI_type_node,
8441 V8HI_type_node, integer_type_node, NULL_TREE);
8442 tree v16qi_ftype_v16qi_int
8443 = build_function_type_list (V16QI_type_node,
8444 V16QI_type_node, integer_type_node, NULL_TREE);
8445 tree v16qi_ftype_v16qi_v16qi_int
8446 = build_function_type_list (V16QI_type_node,
8447 V16QI_type_node, V16QI_type_node,
8448 integer_type_node, NULL_TREE);
8449 tree v8hi_ftype_v8hi_v8hi_int
8450 = build_function_type_list (V8HI_type_node,
8451 V8HI_type_node, V8HI_type_node,
8452 integer_type_node, NULL_TREE);
8453 tree v4si_ftype_v4si_v4si_int
8454 = build_function_type_list (V4SI_type_node,
8455 V4SI_type_node, V4SI_type_node,
8456 integer_type_node, NULL_TREE);
8457 tree v4sf_ftype_v4sf_v4sf_int
8458 = build_function_type_list (V4SF_type_node,
8459 V4SF_type_node, V4SF_type_node,
8460 integer_type_node, NULL_TREE);
8461 tree v4sf_ftype_v4sf_v4sf
8462 = build_function_type_list (V4SF_type_node,
8463 V4SF_type_node, V4SF_type_node, NULL_TREE);
8464 tree v4sf_ftype_v4sf_v4sf_v4si
8465 = build_function_type_list (V4SF_type_node,
8466 V4SF_type_node, V4SF_type_node,
8467 V4SI_type_node, NULL_TREE);
8468 tree v4sf_ftype_v4sf_v4sf_v4sf
8469 = build_function_type_list (V4SF_type_node,
8470 V4SF_type_node, V4SF_type_node,
8471 V4SF_type_node, NULL_TREE);
8472 tree v4si_ftype_v4si_v4si_v4si
8473 = build_function_type_list (V4SI_type_node,
8474 V4SI_type_node, V4SI_type_node,
8475 V4SI_type_node, NULL_TREE);
8476 tree v8hi_ftype_v8hi_v8hi
8477 = build_function_type_list (V8HI_type_node,
8478 V8HI_type_node, V8HI_type_node, NULL_TREE);
8479 tree v8hi_ftype_v8hi_v8hi_v8hi
8480 = build_function_type_list (V8HI_type_node,
8481 V8HI_type_node, V8HI_type_node,
8482 V8HI_type_node, NULL_TREE);
8483 tree v4si_ftype_v8hi_v8hi_v4si
8484 = build_function_type_list (V4SI_type_node,
8485 V8HI_type_node, V8HI_type_node,
8486 V4SI_type_node, NULL_TREE);
8487 tree v4si_ftype_v16qi_v16qi_v4si
8488 = build_function_type_list (V4SI_type_node,
8489 V16QI_type_node, V16QI_type_node,
8490 V4SI_type_node, NULL_TREE);
8491 tree v16qi_ftype_v16qi_v16qi
8492 = build_function_type_list (V16QI_type_node,
8493 V16QI_type_node, V16QI_type_node, NULL_TREE);
8494 tree v4si_ftype_v4sf_v4sf
8495 = build_function_type_list (V4SI_type_node,
8496 V4SF_type_node, V4SF_type_node, NULL_TREE);
8497 tree v8hi_ftype_v16qi_v16qi
8498 = build_function_type_list (V8HI_type_node,
8499 V16QI_type_node, V16QI_type_node, NULL_TREE);
8500 tree v4si_ftype_v8hi_v8hi
8501 = build_function_type_list (V4SI_type_node,
8502 V8HI_type_node, V8HI_type_node, NULL_TREE);
8503 tree v8hi_ftype_v4si_v4si
8504 = build_function_type_list (V8HI_type_node,
8505 V4SI_type_node, V4SI_type_node, NULL_TREE);
8506 tree v16qi_ftype_v8hi_v8hi
8507 = build_function_type_list (V16QI_type_node,
8508 V8HI_type_node, V8HI_type_node, NULL_TREE);
8509 tree v4si_ftype_v16qi_v4si
8510 = build_function_type_list (V4SI_type_node,
8511 V16QI_type_node, V4SI_type_node, NULL_TREE);
8512 tree v4si_ftype_v16qi_v16qi
8513 = build_function_type_list (V4SI_type_node,
8514 V16QI_type_node, V16QI_type_node, NULL_TREE);
8515 tree v4si_ftype_v8hi_v4si
8516 = build_function_type_list (V4SI_type_node,
8517 V8HI_type_node, V4SI_type_node, NULL_TREE);
8518 tree v4si_ftype_v8hi
8519 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8520 tree int_ftype_v4si_v4si
8521 = build_function_type_list (integer_type_node,
8522 V4SI_type_node, V4SI_type_node, NULL_TREE);
8523 tree int_ftype_v4sf_v4sf
8524 = build_function_type_list (integer_type_node,
8525 V4SF_type_node, V4SF_type_node, NULL_TREE);
8526 tree int_ftype_v16qi_v16qi
8527 = build_function_type_list (integer_type_node,
8528 V16QI_type_node, V16QI_type_node, NULL_TREE);
8529 tree int_ftype_v8hi_v8hi
8530 = build_function_type_list (integer_type_node,
8531 V8HI_type_node, V8HI_type_node, NULL_TREE);
8533 /* Add the simple ternary operators. */
8534 d = (struct builtin_description *) bdesc_3arg;
8535 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8538 enum machine_mode mode0, mode1, mode2, mode3;
8541 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8544 mode0 = insn_data[d->icode].operand[0].mode;
8545 mode1 = insn_data[d->icode].operand[1].mode;
8546 mode2 = insn_data[d->icode].operand[2].mode;
8547 mode3 = insn_data[d->icode].operand[3].mode;
8549 /* When all four are of the same mode. */
8550 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8555 type = v4si_ftype_v4si_v4si_v4si;
8558 type = v4sf_ftype_v4sf_v4sf_v4sf;
8561 type = v8hi_ftype_v8hi_v8hi_v8hi;
8564 type = v16qi_ftype_v16qi_v16qi_v16qi;
8570 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8575 type = v4si_ftype_v4si_v4si_v16qi;
8578 type = v4sf_ftype_v4sf_v4sf_v16qi;
8581 type = v8hi_ftype_v8hi_v8hi_v16qi;
8584 type = v16qi_ftype_v16qi_v16qi_v16qi;
8590 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8591 && mode3 == V4SImode)
8592 type = v4si_ftype_v16qi_v16qi_v4si;
8593 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8594 && mode3 == V4SImode)
8595 type = v4si_ftype_v8hi_v8hi_v4si;
8596 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8597 && mode3 == V4SImode)
8598 type = v4sf_ftype_v4sf_v4sf_v4si;
8600 /* vchar, vchar, vchar, 4 bit literal. */
8601 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8603 type = v16qi_ftype_v16qi_v16qi_int;
8605 /* vshort, vshort, vshort, 4 bit literal. */
8606 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8608 type = v8hi_ftype_v8hi_v8hi_int;
8610 /* vint, vint, vint, 4 bit literal. */
8611 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8613 type = v4si_ftype_v4si_v4si_int;
8615 /* vfloat, vfloat, vfloat, 4 bit literal. */
8616 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8618 type = v4sf_ftype_v4sf_v4sf_int;
8623 def_builtin (d->mask, d->name, type, d->code);
8626 /* Add the simple binary operators. */
8627 d = (struct builtin_description *) bdesc_2arg;
8628 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8630 enum machine_mode mode0, mode1, mode2;
8633 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8636 mode0 = insn_data[d->icode].operand[0].mode;
8637 mode1 = insn_data[d->icode].operand[1].mode;
8638 mode2 = insn_data[d->icode].operand[2].mode;
8640 /* When all three operands are of the same mode. */
8641 if (mode0 == mode1 && mode1 == mode2)
8646 type = v4sf_ftype_v4sf_v4sf;
8649 type = v4si_ftype_v4si_v4si;
8652 type = v16qi_ftype_v16qi_v16qi;
8655 type = v8hi_ftype_v8hi_v8hi;
8658 type = v2si_ftype_v2si_v2si;
8661 type = v2sf_ftype_v2sf_v2sf;
8664 type = int_ftype_int_int;
8671 /* A few other combos we really don't want to do manually. */
8673 /* vint, vfloat, vfloat. */
8674 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8675 type = v4si_ftype_v4sf_v4sf;
8677 /* vshort, vchar, vchar. */
8678 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8679 type = v8hi_ftype_v16qi_v16qi;
8681 /* vint, vshort, vshort. */
8682 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8683 type = v4si_ftype_v8hi_v8hi;
8685 /* vshort, vint, vint. */
8686 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8687 type = v8hi_ftype_v4si_v4si;
8689 /* vchar, vshort, vshort. */
8690 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8691 type = v16qi_ftype_v8hi_v8hi;
8693 /* vint, vchar, vint. */
8694 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8695 type = v4si_ftype_v16qi_v4si;
8697 /* vint, vchar, vchar. */
8698 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8699 type = v4si_ftype_v16qi_v16qi;
8701 /* vint, vshort, vint. */
8702 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8703 type = v4si_ftype_v8hi_v4si;
8705 /* vint, vint, 5 bit literal. */
8706 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8707 type = v4si_ftype_v4si_int;
8709 /* vshort, vshort, 5 bit literal. */
8710 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8711 type = v8hi_ftype_v8hi_int;
8713 /* vchar, vchar, 5 bit literal. */
8714 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8715 type = v16qi_ftype_v16qi_int;
8717 /* vfloat, vint, 5 bit literal. */
8718 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8719 type = v4sf_ftype_v4si_int;
8721 /* vint, vfloat, 5 bit literal. */
8722 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8723 type = v4si_ftype_v4sf_int;
8725 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8726 type = v2si_ftype_int_int;
8728 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8729 type = v2si_ftype_v2si_char;
8731 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8732 type = v2si_ftype_int_char;
8735 else if (mode0 == SImode)
8740 type = int_ftype_v4si_v4si;
8743 type = int_ftype_v4sf_v4sf;
8746 type = int_ftype_v16qi_v16qi;
8749 type = int_ftype_v8hi_v8hi;
8759 def_builtin (d->mask, d->name, type, d->code);
8762 /* Add the simple unary operators. */
8763 d = (struct builtin_description *) bdesc_1arg;
8764 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8766 enum machine_mode mode0, mode1;
8769 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8772 mode0 = insn_data[d->icode].operand[0].mode;
8773 mode1 = insn_data[d->icode].operand[1].mode;
8775 if (mode0 == V4SImode && mode1 == QImode)
8776 type = v4si_ftype_int;
8777 else if (mode0 == V8HImode && mode1 == QImode)
8778 type = v8hi_ftype_int;
8779 else if (mode0 == V16QImode && mode1 == QImode)
8780 type = v16qi_ftype_int;
8781 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8782 type = v4sf_ftype_v4sf;
8783 else if (mode0 == V8HImode && mode1 == V16QImode)
8784 type = v8hi_ftype_v16qi;
8785 else if (mode0 == V4SImode && mode1 == V8HImode)
8786 type = v4si_ftype_v8hi;
8787 else if (mode0 == V2SImode && mode1 == V2SImode)
8788 type = v2si_ftype_v2si;
8789 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8790 type = v2sf_ftype_v2sf;
8791 else if (mode0 == V2SFmode && mode1 == V2SImode)
8792 type = v2sf_ftype_v2si;
8793 else if (mode0 == V2SImode && mode1 == V2SFmode)
8794 type = v2si_ftype_v2sf;
8795 else if (mode0 == V2SImode && mode1 == QImode)
8796 type = v2si_ftype_char;
8800 def_builtin (d->mask, d->name, type, d->code);
8805 rs6000_init_libfuncs (void)
8807 if (!TARGET_HARD_FLOAT)
8810 if (DEFAULT_ABI != ABI_V4)
8812 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8814 /* AIX library routines for float->int conversion. */
8815 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8816 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8817 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8818 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8821 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8822 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
8823 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
8824 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
8825 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
8829 /* 32-bit SVR4 quad floating point routines. */
8831 set_optab_libfunc (add_optab, TFmode, "_q_add");
8832 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8833 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8834 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8835 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8836 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8837 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8839 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8840 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8841 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8842 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8843 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8844 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8846 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8847 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8848 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8849 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8850 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8851 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8852 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8857 /* Expand a block clear operation, and return 1 if successful. Return 0
8858 if we should let the compiler generate normal code.
8860 operands[0] is the destination
8861 operands[1] is the length
8862 operands[2] is the alignment */
8865 expand_block_clear (rtx operands[])
8867 rtx orig_dest = operands[0];
8868 rtx bytes_rtx = operands[1];
8869 rtx align_rtx = operands[2];
8870 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8871 HOST_WIDE_INT align;
8872 HOST_WIDE_INT bytes;
8877 /* If this is not a fixed size move, just call memcpy */
8881 /* If this is not a fixed size alignment, abort */
8882 if (GET_CODE (align_rtx) != CONST_INT)
8884 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8886 /* Anything to clear? */
8887 bytes = INTVAL (bytes_rtx);
8891 /* Use the builtin memset after a point, to avoid huge code bloat.
8892 When optimize_size, avoid any significant code bloat; calling
8893 memset is about 4 instructions, so allow for one instruction to
8894 load zero and three to do clearing. */
8895 if (TARGET_ALTIVEC && align >= 128)
8897 else if (TARGET_POWERPC64 && align >= 32)
8902 if (optimize_size && bytes > 3 * clear_step)
8904 if (! optimize_size && bytes > 8 * clear_step)
8907 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8909 enum machine_mode mode = BLKmode;
8912 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8917 else if (bytes >= 8 && TARGET_POWERPC64
8918 /* 64-bit loads and stores require word-aligned
8920 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8925 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8926 { /* move 4 bytes */
8930 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8931 { /* move 2 bytes */
8935 else /* move 1 byte at a time */
8941 dest = adjust_address (orig_dest, mode, offset);
8943 emit_move_insn (dest, CONST0_RTX (mode));
8950 /* Expand a block move operation, and return 1 if successful. Return 0
8951 if we should let the compiler generate normal code.
8953 operands[0] is the destination
8954 operands[1] is the source
8955 operands[2] is the length
8956 operands[3] is the alignment */
8958 #define MAX_MOVE_REG 4
8961 expand_block_move (rtx operands[])
8963 rtx orig_dest = operands[0];
8964 rtx orig_src = operands[1];
8965 rtx bytes_rtx = operands[2];
8966 rtx align_rtx = operands[3];
8967 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8972 rtx stores[MAX_MOVE_REG];
8975 /* If this is not a fixed size move, just call memcpy */
8979 /* If this is not a fixed size alignment, abort */
8980 if (GET_CODE (align_rtx) != CONST_INT)
8982 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8984 /* Anything to move? */
8985 bytes = INTVAL (bytes_rtx);
8989 /* store_one_arg depends on expand_block_move to handle at least the size of
8990 reg_parm_stack_space. */
8991 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8994 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8997 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8998 rtx (*mov) (rtx, rtx);
9000 enum machine_mode mode = BLKmode;
9003 /* Altivec first, since it will be faster than a string move
9004 when it applies, and usually not significantly larger. */
9005 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9009 gen_func.mov = gen_movv4si;
9011 else if (TARGET_STRING
9012 && bytes > 24 /* move up to 32 bytes at a time */
9020 && ! fixed_regs[12])
9022 move_bytes = (bytes > 32) ? 32 : bytes;
9023 gen_func.movmemsi = gen_movmemsi_8reg;
9025 else if (TARGET_STRING
9026 && bytes > 16 /* move up to 24 bytes at a time */
9032 && ! fixed_regs[10])
9034 move_bytes = (bytes > 24) ? 24 : bytes;
9035 gen_func.movmemsi = gen_movmemsi_6reg;
9037 else if (TARGET_STRING
9038 && bytes > 8 /* move up to 16 bytes at a time */
9044 move_bytes = (bytes > 16) ? 16 : bytes;
9045 gen_func.movmemsi = gen_movmemsi_4reg;
9047 else if (bytes >= 8 && TARGET_POWERPC64
9048 /* 64-bit loads and stores require word-aligned
9050 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9054 gen_func.mov = gen_movdi;
9056 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9057 { /* move up to 8 bytes at a time */
9058 move_bytes = (bytes > 8) ? 8 : bytes;
9059 gen_func.movmemsi = gen_movmemsi_2reg;
9061 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9062 { /* move 4 bytes */
9065 gen_func.mov = gen_movsi;
9067 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9068 { /* move 2 bytes */
9071 gen_func.mov = gen_movhi;
9073 else if (TARGET_STRING && bytes > 1)
9074 { /* move up to 4 bytes at a time */
9075 move_bytes = (bytes > 4) ? 4 : bytes;
9076 gen_func.movmemsi = gen_movmemsi_1reg;
9078 else /* move 1 byte at a time */
9082 gen_func.mov = gen_movqi;
9085 src = adjust_address (orig_src, mode, offset);
9086 dest = adjust_address (orig_dest, mode, offset);
9088 if (mode != BLKmode)
9090 rtx tmp_reg = gen_reg_rtx (mode);
9092 emit_insn ((*gen_func.mov) (tmp_reg, src));
9093 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9096 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9099 for (i = 0; i < num_reg; i++)
9100 emit_insn (stores[i]);
9104 if (mode == BLKmode)
9106 /* Move the address into scratch registers. The movmemsi
9107 patterns require zero offset. */
9108 if (!REG_P (XEXP (src, 0)))
9110 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9111 src = replace_equiv_address (src, src_reg);
9113 set_mem_size (src, GEN_INT (move_bytes));
9115 if (!REG_P (XEXP (dest, 0)))
9117 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9118 dest = replace_equiv_address (dest, dest_reg);
9120 set_mem_size (dest, GEN_INT (move_bytes));
9122 emit_insn ((*gen_func.movmemsi) (dest, src,
9123 GEN_INT (move_bytes & 31),
9132 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9133 known to be a PARALLEL. */
9135 save_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9140 int count = XVECLEN (op, 0);
9146 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9147 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9150 for (i=1; i <= 18; i++)
9152 elt = XVECEXP (op, 0, index++);
9153 if (GET_CODE (elt) != SET
9154 || GET_CODE (SET_DEST (elt)) != MEM
9155 || ! memory_operand (SET_DEST (elt), DFmode)
9156 || GET_CODE (SET_SRC (elt)) != REG
9157 || GET_MODE (SET_SRC (elt)) != DFmode)
9161 for (i=1; i <= 12; i++)
9163 elt = XVECEXP (op, 0, index++);
9164 if (GET_CODE (elt) != SET
9165 || GET_CODE (SET_DEST (elt)) != MEM
9166 || GET_CODE (SET_SRC (elt)) != REG
9167 || GET_MODE (SET_SRC (elt)) != V4SImode)
9171 for (i=1; i <= 19; i++)
9173 elt = XVECEXP (op, 0, index++);
9174 if (GET_CODE (elt) != SET
9175 || GET_CODE (SET_DEST (elt)) != MEM
9176 || ! memory_operand (SET_DEST (elt), Pmode)
9177 || GET_CODE (SET_SRC (elt)) != REG
9178 || GET_MODE (SET_SRC (elt)) != Pmode)
9182 elt = XVECEXP (op, 0, index++);
9183 if (GET_CODE (elt) != SET
9184 || GET_CODE (SET_DEST (elt)) != MEM
9185 || ! memory_operand (SET_DEST (elt), Pmode)
9186 || GET_CODE (SET_SRC (elt)) != REG
9187 || REGNO (SET_SRC (elt)) != CR2_REGNO
9188 || GET_MODE (SET_SRC (elt)) != Pmode)
9191 if (GET_CODE (XVECEXP (op, 0, index++)) != USE
9192 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9193 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9198 /* Return 1 if OP is suitable for a save_world call in prologue. It is
9199 known to be a PARALLEL. */
9201 restore_world_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9206 int count = XVECLEN (op, 0);
9212 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
9213 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9214 || GET_CODE (XVECEXP (op, 0, index++)) != USE
9215 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
9218 elt = XVECEXP (op, 0, index++);
9219 if (GET_CODE (elt) != SET
9220 || GET_CODE (SET_SRC (elt)) != MEM
9221 || ! memory_operand (SET_SRC (elt), Pmode)
9222 || GET_CODE (SET_DEST (elt)) != REG
9223 || REGNO (SET_DEST (elt)) != CR2_REGNO
9224 || GET_MODE (SET_DEST (elt)) != Pmode)
9227 for (i=1; i <= 19; i++)
9229 elt = XVECEXP (op, 0, index++);
9230 if (GET_CODE (elt) != SET
9231 || GET_CODE (SET_SRC (elt)) != MEM
9232 || ! memory_operand (SET_SRC (elt), Pmode)
9233 || GET_CODE (SET_DEST (elt)) != REG
9234 || GET_MODE (SET_DEST (elt)) != Pmode)
9238 for (i=1; i <= 12; i++)
9240 elt = XVECEXP (op, 0, index++);
9241 if (GET_CODE (elt) != SET
9242 || GET_CODE (SET_SRC (elt)) != MEM
9243 || GET_CODE (SET_DEST (elt)) != REG
9244 || GET_MODE (SET_DEST (elt)) != V4SImode)
9248 for (i=1; i <= 18; i++)
9250 elt = XVECEXP (op, 0, index++);
9251 if (GET_CODE (elt) != SET
9252 || GET_CODE (SET_SRC (elt)) != MEM
9253 || ! memory_operand (SET_SRC (elt), DFmode)
9254 || GET_CODE (SET_DEST (elt)) != REG
9255 || GET_MODE (SET_DEST (elt)) != DFmode)
9259 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9260 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9261 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9262 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
9263 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
9269 /* Return 1 if OP is a load multiple operation. It is known to be a
9270 PARALLEL and the first section will be tested. */
9273 load_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9275 int count = XVECLEN (op, 0);
9276 unsigned int dest_regno;
9280 /* Perform a quick check so we don't blow up below. */
9282 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9283 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9284 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9287 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9288 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9290 for (i = 1; i < count; i++)
9292 rtx elt = XVECEXP (op, 0, i);
9294 if (GET_CODE (elt) != SET
9295 || GET_CODE (SET_DEST (elt)) != REG
9296 || GET_MODE (SET_DEST (elt)) != SImode
9297 || REGNO (SET_DEST (elt)) != dest_regno + i
9298 || GET_CODE (SET_SRC (elt)) != MEM
9299 || GET_MODE (SET_SRC (elt)) != SImode
9300 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
9301 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
9302 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
9303 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
9310 /* Similar, but tests for store multiple. Here, the second vector element
9311 is a CLOBBER. It will be tested later. */
9314 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9316 int count = XVECLEN (op, 0) - 1;
9317 unsigned int src_regno;
9321 /* Perform a quick check so we don't blow up below. */
9323 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9324 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9325 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9328 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9329 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9331 for (i = 1; i < count; i++)
9333 rtx elt = XVECEXP (op, 0, i + 1);
9335 if (GET_CODE (elt) != SET
9336 || GET_CODE (SET_SRC (elt)) != REG
9337 || GET_MODE (SET_SRC (elt)) != SImode
9338 || REGNO (SET_SRC (elt)) != src_regno + i
9339 || GET_CODE (SET_DEST (elt)) != MEM
9340 || GET_MODE (SET_DEST (elt)) != SImode
9341 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
9342 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
9343 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
9344 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
9351 /* Return a string to perform a load_multiple operation.
9352 operands[0] is the vector.
9353 operands[1] is the source address.
9354 operands[2] is the first destination register. */
9357 rs6000_output_load_multiple (rtx operands[3])
9359 /* We have to handle the case where the pseudo used to contain the address
9360 is assigned to one of the output registers. */
9362 int words = XVECLEN (operands[0], 0);
9365 if (XVECLEN (operands[0], 0) == 1)
9366 return "{l|lwz} %2,0(%1)";
9368 for (i = 0; i < words; i++)
9369 if (refers_to_regno_p (REGNO (operands[2]) + i,
9370 REGNO (operands[2]) + i + 1, operands[1], 0))
9374 xop[0] = GEN_INT (4 * (words-1));
9375 xop[1] = operands[1];
9376 xop[2] = operands[2];
9377 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9382 xop[0] = GEN_INT (4 * (words-1));
9383 xop[1] = operands[1];
9384 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9385 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9390 for (j = 0; j < words; j++)
9393 xop[0] = GEN_INT (j * 4);
9394 xop[1] = operands[1];
9395 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9396 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9398 xop[0] = GEN_INT (i * 4);
9399 xop[1] = operands[1];
9400 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9405 return "{lsi|lswi} %2,%1,%N0";
9408 /* Return 1 for a parallel vrsave operation. */
9411 vrsave_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9413 int count = XVECLEN (op, 0);
9414 unsigned int dest_regno, src_regno;
9418 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9419 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9420 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE)
9423 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9424 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9426 if (dest_regno != VRSAVE_REGNO
9427 && src_regno != VRSAVE_REGNO)
9430 for (i = 1; i < count; i++)
9432 rtx elt = XVECEXP (op, 0, i);
9434 if (GET_CODE (elt) != CLOBBER
9435 && GET_CODE (elt) != SET)
9442 /* Return 1 for an PARALLEL suitable for mfcr. */
9445 mfcr_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9447 int count = XVECLEN (op, 0);
9450 /* Perform a quick check so we don't blow up below. */
9452 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9453 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9454 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9457 for (i = 0; i < count; i++)
9459 rtx exp = XVECEXP (op, 0, i);
9464 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
9466 if (GET_CODE (src_reg) != REG
9467 || GET_MODE (src_reg) != CCmode
9468 || ! CR_REGNO_P (REGNO (src_reg)))
9471 if (GET_CODE (exp) != SET
9472 || GET_CODE (SET_DEST (exp)) != REG
9473 || GET_MODE (SET_DEST (exp)) != SImode
9474 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
9476 unspec = SET_SRC (exp);
9477 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
9479 if (GET_CODE (unspec) != UNSPEC
9480 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
9481 || XVECLEN (unspec, 0) != 2
9482 || XVECEXP (unspec, 0, 0) != src_reg
9483 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9484 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9490 /* Return 1 for an PARALLEL suitable for mtcrf. */
9493 mtcrf_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9495 int count = XVECLEN (op, 0);
9499 /* Perform a quick check so we don't blow up below. */
9501 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9502 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
9503 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
9505 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
9507 if (GET_CODE (src_reg) != REG
9508 || GET_MODE (src_reg) != SImode
9509 || ! INT_REGNO_P (REGNO (src_reg)))
9512 for (i = 0; i < count; i++)
9514 rtx exp = XVECEXP (op, 0, i);
9518 if (GET_CODE (exp) != SET
9519 || GET_CODE (SET_DEST (exp)) != REG
9520 || GET_MODE (SET_DEST (exp)) != CCmode
9521 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
9523 unspec = SET_SRC (exp);
9524 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
9526 if (GET_CODE (unspec) != UNSPEC
9527 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
9528 || XVECLEN (unspec, 0) != 2
9529 || XVECEXP (unspec, 0, 0) != src_reg
9530 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
9531 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
9537 /* Return 1 for an PARALLEL suitable for lmw. */
9540 lmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9542 int count = XVECLEN (op, 0);
9543 unsigned int dest_regno;
9545 unsigned int base_regno;
9546 HOST_WIDE_INT offset;
9549 /* Perform a quick check so we don't blow up below. */
9551 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9552 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
9553 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
9556 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
9557 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
9560 || count != 32 - (int) dest_regno)
9563 if (legitimate_indirect_address_p (src_addr, 0))
9566 base_regno = REGNO (src_addr);
9567 if (base_regno == 0)
9570 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
9572 offset = INTVAL (XEXP (src_addr, 1));
9573 base_regno = REGNO (XEXP (src_addr, 0));
9578 for (i = 0; i < count; i++)
9580 rtx elt = XVECEXP (op, 0, i);
9583 HOST_WIDE_INT newoffset;
9585 if (GET_CODE (elt) != SET
9586 || GET_CODE (SET_DEST (elt)) != REG
9587 || GET_MODE (SET_DEST (elt)) != SImode
9588 || REGNO (SET_DEST (elt)) != dest_regno + i
9589 || GET_CODE (SET_SRC (elt)) != MEM
9590 || GET_MODE (SET_SRC (elt)) != SImode)
9592 newaddr = XEXP (SET_SRC (elt), 0);
9593 if (legitimate_indirect_address_p (newaddr, 0))
9598 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9600 addr_reg = XEXP (newaddr, 0);
9601 newoffset = INTVAL (XEXP (newaddr, 1));
9605 if (REGNO (addr_reg) != base_regno
9606 || newoffset != offset + 4 * i)
9613 /* Return 1 for an PARALLEL suitable for stmw. */
9616 stmw_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9618 int count = XVECLEN (op, 0);
9619 unsigned int src_regno;
9621 unsigned int base_regno;
9622 HOST_WIDE_INT offset;
9625 /* Perform a quick check so we don't blow up below. */
9627 || GET_CODE (XVECEXP (op, 0, 0)) != SET
9628 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
9629 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
9632 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
9633 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
9636 || count != 32 - (int) src_regno)
9639 if (legitimate_indirect_address_p (dest_addr, 0))
9642 base_regno = REGNO (dest_addr);
9643 if (base_regno == 0)
9646 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
9648 offset = INTVAL (XEXP (dest_addr, 1));
9649 base_regno = REGNO (XEXP (dest_addr, 0));
9654 for (i = 0; i < count; i++)
9656 rtx elt = XVECEXP (op, 0, i);
9659 HOST_WIDE_INT newoffset;
9661 if (GET_CODE (elt) != SET
9662 || GET_CODE (SET_SRC (elt)) != REG
9663 || GET_MODE (SET_SRC (elt)) != SImode
9664 || REGNO (SET_SRC (elt)) != src_regno + i
9665 || GET_CODE (SET_DEST (elt)) != MEM
9666 || GET_MODE (SET_DEST (elt)) != SImode)
9668 newaddr = XEXP (SET_DEST (elt), 0);
9669 if (legitimate_indirect_address_p (newaddr, 0))
9674 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
9676 addr_reg = XEXP (newaddr, 0);
9677 newoffset = INTVAL (XEXP (newaddr, 1));
9681 if (REGNO (addr_reg) != base_regno
9682 || newoffset != offset + 4 * i)
9689 /* A validation routine: say whether CODE, a condition code, and MODE
9690 match. The other alternatives either don't make sense or should
9691 never be generated. */
9694 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9696 if ((GET_RTX_CLASS (code) != RTX_COMPARE
9697 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
9698 || GET_MODE_CLASS (mode) != MODE_CC)
9701 /* These don't make sense. */
9702 if ((code == GT || code == LT || code == GE || code == LE)
9703 && mode == CCUNSmode)
9706 if ((code == GTU || code == LTU || code == GEU || code == LEU)
9707 && mode != CCUNSmode)
9710 if (mode != CCFPmode
9711 && (code == ORDERED || code == UNORDERED
9712 || code == UNEQ || code == LTGT
9713 || code == UNGT || code == UNLT
9714 || code == UNGE || code == UNLE))
9717 /* These should never be generated except for
9718 flag_finite_math_only. */
9719 if (mode == CCFPmode
9720 && ! flag_finite_math_only
9721 && (code == LE || code == GE
9722 || code == UNEQ || code == LTGT
9723 || code == UNGT || code == UNLT))
9726 /* These are invalid; the information is not there. */
9727 if (mode == CCEQmode
9728 && code != EQ && code != NE)
9732 /* Return 1 if OP is a comparison operation that is valid for a branch insn.
9733 We only check the opcode against the mode of the CC value here. */
9736 branch_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9738 enum rtx_code code = GET_CODE (op);
9739 enum machine_mode cc_mode;
9741 if (!COMPARISON_P (op))
9744 cc_mode = GET_MODE (XEXP (op, 0));
9745 if (GET_MODE_CLASS (cc_mode) != MODE_CC)
9748 validate_condition_mode (code, cc_mode);
9753 /* Return 1 if OP is a comparison operation that is valid for a branch
9754 insn and which is true if the corresponding bit in the CC register
9758 branch_positive_comparison_operator (rtx op, enum machine_mode mode)
9762 if (! branch_comparison_operator (op, mode))
9765 code = GET_CODE (op);
9766 return (code == EQ || code == LT || code == GT
9767 || code == LTU || code == GTU
9768 || code == UNORDERED);
9771 /* Return 1 if OP is a comparison operation that is valid for an scc
9772 insn: it must be a positive comparison. */
9775 scc_comparison_operator (rtx op, enum machine_mode mode)
9777 return branch_positive_comparison_operator (op, mode);
9781 trap_comparison_operator (rtx op, enum machine_mode mode)
9783 if (mode != VOIDmode && mode != GET_MODE (op))
9785 return COMPARISON_P (op);
9789 boolean_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9791 enum rtx_code code = GET_CODE (op);
9792 return (code == AND || code == IOR || code == XOR);
9796 boolean_or_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9798 enum rtx_code code = GET_CODE (op);
9799 return (code == IOR || code == XOR);
9803 min_max_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
9805 enum rtx_code code = GET_CODE (op);
9806 return (code == SMIN || code == SMAX || code == UMIN || code == UMAX);
9809 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9810 mask required to convert the result of a rotate insn into a shift
9811 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9814 includes_lshift_p (rtx shiftop, rtx andop)
9816 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9818 shift_mask <<= INTVAL (shiftop);
9820 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9823 /* Similar, but for right shift. */
9826 includes_rshift_p (rtx shiftop, rtx andop)
9828 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9830 shift_mask >>= INTVAL (shiftop);
9832 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9835 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9836 to perform a left shift. It must have exactly SHIFTOP least
9837 significant 0's, then one or more 1's, then zero or more 0's. */
9840 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9842 if (GET_CODE (andop) == CONST_INT)
9844 HOST_WIDE_INT c, lsb, shift_mask;
9847 if (c == 0 || c == ~0)
9851 shift_mask <<= INTVAL (shiftop);
9853 /* Find the least significant one bit. */
9856 /* It must coincide with the LSB of the shift mask. */
9857 if (-lsb != shift_mask)
9860 /* Invert to look for the next transition (if any). */
9863 /* Remove the low group of ones (originally low group of zeros). */
9866 /* Again find the lsb, and check we have all 1's above. */
9870 else if (GET_CODE (andop) == CONST_DOUBLE
9871 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9873 HOST_WIDE_INT low, high, lsb;
9874 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9876 low = CONST_DOUBLE_LOW (andop);
9877 if (HOST_BITS_PER_WIDE_INT < 64)
9878 high = CONST_DOUBLE_HIGH (andop);
9880 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9881 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9884 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9886 shift_mask_high = ~0;
9887 if (INTVAL (shiftop) > 32)
9888 shift_mask_high <<= INTVAL (shiftop) - 32;
9892 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9899 return high == -lsb;
9902 shift_mask_low = ~0;
9903 shift_mask_low <<= INTVAL (shiftop);
9907 if (-lsb != shift_mask_low)
9910 if (HOST_BITS_PER_WIDE_INT < 64)
9915 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9918 return high == -lsb;
9922 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9928 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9929 to perform a left shift. It must have SHIFTOP or more least
9930 significant 0's, with the remainder of the word 1's. */
9933 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9935 if (GET_CODE (andop) == CONST_INT)
9937 HOST_WIDE_INT c, lsb, shift_mask;
9940 shift_mask <<= INTVAL (shiftop);
9943 /* Find the least significant one bit. */
9946 /* It must be covered by the shift mask.
9947 This test also rejects c == 0. */
9948 if ((lsb & shift_mask) == 0)
9951 /* Check we have all 1's above the transition, and reject all 1's. */
9952 return c == -lsb && lsb != 1;
9954 else if (GET_CODE (andop) == CONST_DOUBLE
9955 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9957 HOST_WIDE_INT low, lsb, shift_mask_low;
9959 low = CONST_DOUBLE_LOW (andop);
9961 if (HOST_BITS_PER_WIDE_INT < 64)
9963 HOST_WIDE_INT high, shift_mask_high;
9965 high = CONST_DOUBLE_HIGH (andop);
9969 shift_mask_high = ~0;
9970 if (INTVAL (shiftop) > 32)
9971 shift_mask_high <<= INTVAL (shiftop) - 32;
9975 if ((lsb & shift_mask_high) == 0)
9978 return high == -lsb;
9984 shift_mask_low = ~0;
9985 shift_mask_low <<= INTVAL (shiftop);
9989 if ((lsb & shift_mask_low) == 0)
9992 return low == -lsb && lsb != 1;
9998 /* Return 1 if operands will generate a valid arguments to rlwimi
9999 instruction for insert with right shift in 64-bit mode. The mask may
10000 not start on the first bit or stop on the last bit because wrap-around
10001 effects of instruction do not correspond to semantics of RTL insn. */
10004 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10006 if (INTVAL (startop) < 64
10007 && INTVAL (startop) > 32
10008 && (INTVAL (sizeop) + INTVAL (startop) < 64)
10009 && (INTVAL (sizeop) + INTVAL (startop) > 33)
10010 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
10011 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
10012 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10018 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10019 for lfq and stfq insns iff the registers are hard registers. */
10022 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10024 /* We might have been passed a SUBREG. */
10025 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10028 /* We might have been passed non floating point registers. */
10029 if (!FP_REGNO_P (REGNO (reg1))
10030 || !FP_REGNO_P (REGNO (reg2)))
10033 return (REGNO (reg1) == REGNO (reg2) - 1);
10036 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10037 addr1 and addr2 must be in consecutive memory locations
10038 (addr2 == addr1 + 8). */
10041 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10047 /* The mems cannot be volatile. */
10048 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10051 addr1 = XEXP (mem1, 0);
10052 addr2 = XEXP (mem2, 0);
10054 /* Extract an offset (if used) from the first addr. */
10055 if (GET_CODE (addr1) == PLUS)
10057 /* If not a REG, return zero. */
10058 if (GET_CODE (XEXP (addr1, 0)) != REG)
10062 reg1 = REGNO (XEXP (addr1, 0));
10063 /* The offset must be constant! */
10064 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10066 offset1 = INTVAL (XEXP (addr1, 1));
10069 else if (GET_CODE (addr1) != REG)
10073 reg1 = REGNO (addr1);
10074 /* This was a simple (mem (reg)) expression. Offset is 0. */
10078 /* Make sure the second address is a (mem (plus (reg) (const_int)))
10079 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
10080 register as addr1. */
10081 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
10083 if (GET_CODE (addr2) != PLUS)
10086 if (GET_CODE (XEXP (addr2, 0)) != REG
10087 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10090 if (reg1 != REGNO (XEXP (addr2, 0)))
10093 /* The offset for the second addr must be 8 more than the first addr. */
10094 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
10097 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10102 /* Return the register class of a scratch register needed to copy IN into
10103 or out of a register in CLASS in MODE. If it can be done directly,
10104 NO_REGS is returned. */
10107 secondary_reload_class (enum reg_class class,
10108 enum machine_mode mode ATTRIBUTE_UNUSED,
10113 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10115 && MACHOPIC_INDIRECT
10119 /* We cannot copy a symbolic operand directly into anything
10120 other than BASE_REGS for TARGET_ELF. So indicate that a
10121 register from BASE_REGS is needed as an intermediate
10124 On Darwin, pic addresses require a load from memory, which
10125 needs a base register. */
10126 if (class != BASE_REGS
10127 && (GET_CODE (in) == SYMBOL_REF
10128 || GET_CODE (in) == HIGH
10129 || GET_CODE (in) == LABEL_REF
10130 || GET_CODE (in) == CONST))
10134 if (GET_CODE (in) == REG)
10136 regno = REGNO (in);
10137 if (regno >= FIRST_PSEUDO_REGISTER)
10139 regno = true_regnum (in);
10140 if (regno >= FIRST_PSEUDO_REGISTER)
10144 else if (GET_CODE (in) == SUBREG)
10146 regno = true_regnum (in);
10147 if (regno >= FIRST_PSEUDO_REGISTER)
10153 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10155 if (class == GENERAL_REGS || class == BASE_REGS
10156 || (regno >= 0 && INT_REGNO_P (regno)))
10159 /* Constants, memory, and FP registers can go into FP registers. */
10160 if ((regno == -1 || FP_REGNO_P (regno))
10161 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10164 /* Memory, and AltiVec registers can go into AltiVec registers. */
10165 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10166 && class == ALTIVEC_REGS)
10169 /* We can copy among the CR registers. */
10170 if ((class == CR_REGS || class == CR0_REGS)
10171 && regno >= 0 && CR_REGNO_P (regno))
10174 /* Otherwise, we need GENERAL_REGS. */
10175 return GENERAL_REGS;
10178 /* Given a comparison operation, return the bit number in CCR to test. We
10179 know this is a valid comparison.
10181 SCC_P is 1 if this is for an scc. That means that %D will have been
10182 used instead of %C, so the bits will be in different places.
10184 Return -1 if OP isn't a valid comparison for some reason. */
10187 ccr_bit (rtx op, int scc_p)
10189 enum rtx_code code = GET_CODE (op);
10190 enum machine_mode cc_mode;
10195 if (!COMPARISON_P (op))
10198 reg = XEXP (op, 0);
10200 if (GET_CODE (reg) != REG
10201 || ! CR_REGNO_P (REGNO (reg)))
10204 cc_mode = GET_MODE (reg);
10205 cc_regnum = REGNO (reg);
10206 base_bit = 4 * (cc_regnum - CR0_REGNO);
10208 validate_condition_mode (code, cc_mode);
10210 /* When generating a sCOND operation, only positive conditions are
10212 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
10213 && code != GTU && code != LTU)
10219 return scc_p ? base_bit + 3 : base_bit + 2;
10221 return base_bit + 2;
10222 case GT: case GTU: case UNLE:
10223 return base_bit + 1;
10224 case LT: case LTU: case UNGE:
10226 case ORDERED: case UNORDERED:
10227 return base_bit + 3;
10230 /* If scc, we will have done a cror to put the bit in the
10231 unordered position. So test that bit. For integer, this is ! LT
10232 unless this is an scc insn. */
10233 return scc_p ? base_bit + 3 : base_bit;
10236 return scc_p ? base_bit + 3 : base_bit + 1;
10243 /* Return the GOT register. */
10246 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10248 /* The second flow pass currently (June 1999) can't update
10249 regs_ever_live without disturbing other parts of the compiler, so
10250 update it here to make the prolog/epilogue code happy. */
10251 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10252 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10254 current_function_uses_pic_offset_table = 1;
10256 return pic_offset_table_rtx;
10259 /* Function to init struct machine_function.
10260 This will be called, via a pointer variable,
10261 from push_function_context. */
10263 static struct machine_function *
10264 rs6000_init_machine_status (void)
10266 return ggc_alloc_cleared (sizeof (machine_function));
10269 /* These macros test for integers and extract the low-order bits. */
10271 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10272 && GET_MODE (X) == VOIDmode)
10274 #define INT_LOWPART(X) \
10275 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10278 extract_MB (rtx op)
10281 unsigned long val = INT_LOWPART (op);
10283 /* If the high bit is zero, the value is the first 1 bit we find
10285 if ((val & 0x80000000) == 0)
10287 if ((val & 0xffffffff) == 0)
10291 while (((val <<= 1) & 0x80000000) == 0)
10296 /* If the high bit is set and the low bit is not, or the mask is all
10297 1's, the value is zero. */
10298 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10301 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10304 while (((val >>= 1) & 1) != 0)
10311 extract_ME (rtx op)
10314 unsigned long val = INT_LOWPART (op);
10316 /* If the low bit is zero, the value is the first 1 bit we find from
10318 if ((val & 1) == 0)
10320 if ((val & 0xffffffff) == 0)
10324 while (((val >>= 1) & 1) == 0)
10330 /* If the low bit is set and the high bit is not, or the mask is all
10331 1's, the value is 31. */
10332 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10335 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10338 while (((val <<= 1) & 0x80000000) != 0)
10344 /* Locate some local-dynamic symbol still in use by this function
10345 so that we can print its name in some tls_ld pattern. */
10347 static const char *
10348 rs6000_get_some_local_dynamic_name (void)
10352 if (cfun->machine->some_ld_name)
10353 return cfun->machine->some_ld_name;
10355 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10357 && for_each_rtx (&PATTERN (insn),
10358 rs6000_get_some_local_dynamic_name_1, 0))
10359 return cfun->machine->some_ld_name;
10364 /* Helper function for rs6000_get_some_local_dynamic_name. */
10367 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10371 if (GET_CODE (x) == SYMBOL_REF)
10373 const char *str = XSTR (x, 0);
10374 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10376 cfun->machine->some_ld_name = str;
10384 /* Write out a function code label. */
10387 rs6000_output_function_entry (FILE *file, const char *fname)
10389 if (fname[0] != '.')
10391 switch (DEFAULT_ABI)
10400 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10409 RS6000_OUTPUT_BASENAME (file, fname);
10411 assemble_name (file, fname);
10414 /* Print an operand. Recognize special options, documented below. */
10417 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10418 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10420 #define SMALL_DATA_RELOC "sda21"
10421 #define SMALL_DATA_REG 0
10425 print_operand (FILE *file, rtx x, int code)
10429 unsigned HOST_WIDE_INT uval;
10434 /* Write out an instruction after the call which may be replaced
10435 with glue code by the loader. This depends on the AIX version. */
10436 asm_fprintf (file, RS6000_CALL_GLUE);
10439 /* %a is output_address. */
10442 /* If X is a constant integer whose low-order 5 bits are zero,
10443 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10444 in the AIX assembler where "sri" with a zero shift count
10445 writes a trash instruction. */
10446 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10453 /* If constant, low-order 16 bits of constant, unsigned.
10454 Otherwise, write normally. */
10456 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10458 print_operand (file, x, 0);
10462 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10463 for 64-bit mask direction. */
10464 putc (((INT_LOWPART(x) & 1) == 0 ? 'r' : 'l'), file);
10467 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10471 /* X is a CR register. Print the number of the GT bit of the CR. */
10472 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10473 output_operand_lossage ("invalid %%E value");
10475 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10479 /* Like 'J' but get to the EQ bit. */
10480 if (GET_CODE (x) != REG)
10483 /* Bit 1 is EQ bit. */
10484 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10486 /* If we want bit 31, write a shift count of zero, not 32. */
10487 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10491 /* X is a CR register. Print the number of the EQ bit of the CR */
10492 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10493 output_operand_lossage ("invalid %%E value");
10495 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10499 /* X is a CR register. Print the shift count needed to move it
10500 to the high-order four bits. */
10501 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10502 output_operand_lossage ("invalid %%f value");
10504 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10508 /* Similar, but print the count for the rotate in the opposite
10510 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10511 output_operand_lossage ("invalid %%F value");
10513 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10517 /* X is a constant integer. If it is negative, print "m",
10518 otherwise print "z". This is to make an aze or ame insn. */
10519 if (GET_CODE (x) != CONST_INT)
10520 output_operand_lossage ("invalid %%G value");
10521 else if (INTVAL (x) >= 0)
10528 /* If constant, output low-order five bits. Otherwise, write
10531 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10533 print_operand (file, x, 0);
10537 /* If constant, output low-order six bits. Otherwise, write
10540 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10542 print_operand (file, x, 0);
10546 /* Print `i' if this is a constant, else nothing. */
10552 /* Write the bit number in CCR for jump. */
10553 i = ccr_bit (x, 0);
10555 output_operand_lossage ("invalid %%j code");
10557 fprintf (file, "%d", i);
10561 /* Similar, but add one for shift count in rlinm for scc and pass
10562 scc flag to `ccr_bit'. */
10563 i = ccr_bit (x, 1);
10565 output_operand_lossage ("invalid %%J code");
10567 /* If we want bit 31, write a shift count of zero, not 32. */
10568 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10572 /* X must be a constant. Write the 1's complement of the
10575 output_operand_lossage ("invalid %%k value");
10577 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10581 /* X must be a symbolic constant on ELF. Write an
10582 expression suitable for an 'addi' that adds in the low 16
10583 bits of the MEM. */
10584 if (GET_CODE (x) != CONST)
10586 print_operand_address (file, x);
10587 fputs ("@l", file);
10591 if (GET_CODE (XEXP (x, 0)) != PLUS
10592 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10593 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10594 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10595 output_operand_lossage ("invalid %%K value");
10596 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10597 fputs ("@l", file);
10598 /* For GNU as, there must be a non-alphanumeric character
10599 between 'l' and the number. The '-' is added by
10600 print_operand() already. */
10601 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10603 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10607 /* %l is output_asm_label. */
10610 /* Write second word of DImode or DFmode reference. Works on register
10611 or non-indexed memory only. */
10612 if (GET_CODE (x) == REG)
10613 fputs (reg_names[REGNO (x) + 1], file);
10614 else if (GET_CODE (x) == MEM)
10616 /* Handle possible auto-increment. Since it is pre-increment and
10617 we have already done it, we can just use an offset of word. */
10618 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10619 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10620 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10623 output_address (XEXP (adjust_address_nv (x, SImode,
10627 if (small_data_operand (x, GET_MODE (x)))
10628 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10629 reg_names[SMALL_DATA_REG]);
10634 /* MB value for a mask operand. */
10635 if (! mask_operand (x, SImode))
10636 output_operand_lossage ("invalid %%m value");
10638 fprintf (file, "%d", extract_MB (x));
10642 /* ME value for a mask operand. */
10643 if (! mask_operand (x, SImode))
10644 output_operand_lossage ("invalid %%M value");
10646 fprintf (file, "%d", extract_ME (x));
10649 /* %n outputs the negative of its operand. */
10652 /* Write the number of elements in the vector times 4. */
10653 if (GET_CODE (x) != PARALLEL)
10654 output_operand_lossage ("invalid %%N value");
10656 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10660 /* Similar, but subtract 1 first. */
10661 if (GET_CODE (x) != PARALLEL)
10662 output_operand_lossage ("invalid %%O value");
10664 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10668 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10670 || INT_LOWPART (x) < 0
10671 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10672 output_operand_lossage ("invalid %%p value");
10674 fprintf (file, "%d", i);
10678 /* The operand must be an indirect memory reference. The result
10679 is the register name. */
10680 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10681 || REGNO (XEXP (x, 0)) >= 32)
10682 output_operand_lossage ("invalid %%P value");
10684 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10688 /* This outputs the logical code corresponding to a boolean
10689 expression. The expression may have one or both operands
10690 negated (if one, only the first one). For condition register
10691 logical operations, it will also treat the negated
10692 CR codes as NOTs, but not handle NOTs of them. */
10694 const char *const *t = 0;
10696 enum rtx_code code = GET_CODE (x);
10697 static const char * const tbl[3][3] = {
10698 { "and", "andc", "nor" },
10699 { "or", "orc", "nand" },
10700 { "xor", "eqv", "xor" } };
10704 else if (code == IOR)
10706 else if (code == XOR)
10709 output_operand_lossage ("invalid %%q value");
10711 if (GET_CODE (XEXP (x, 0)) != NOT)
10715 if (GET_CODE (XEXP (x, 1)) == NOT)
10733 /* X is a CR register. Print the mask for `mtcrf'. */
10734 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10735 output_operand_lossage ("invalid %%R value");
10737 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10741 /* Low 5 bits of 32 - value */
10743 output_operand_lossage ("invalid %%s value");
10745 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10749 /* PowerPC64 mask position. All 0's is excluded.
10750 CONST_INT 32-bit mask is considered sign-extended so any
10751 transition must occur within the CONST_INT, not on the boundary. */
10752 if (! mask64_operand (x, DImode))
10753 output_operand_lossage ("invalid %%S value");
10755 uval = INT_LOWPART (x);
10757 if (uval & 1) /* Clear Left */
10759 #if HOST_BITS_PER_WIDE_INT > 64
10760 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10764 else /* Clear Right */
10767 #if HOST_BITS_PER_WIDE_INT > 64
10768 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10776 fprintf (file, "%d", i);
10780 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10781 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
10784 /* Bit 3 is OV bit. */
10785 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10787 /* If we want bit 31, write a shift count of zero, not 32. */
10788 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10792 /* Print the symbolic name of a branch target register. */
10793 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10794 && REGNO (x) != COUNT_REGISTER_REGNUM))
10795 output_operand_lossage ("invalid %%T value");
10796 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10797 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10799 fputs ("ctr", file);
10803 /* High-order 16 bits of constant for use in unsigned operand. */
10805 output_operand_lossage ("invalid %%u value");
10807 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10808 (INT_LOWPART (x) >> 16) & 0xffff);
10812 /* High-order 16 bits of constant for use in signed operand. */
10814 output_operand_lossage ("invalid %%v value");
10816 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10817 (INT_LOWPART (x) >> 16) & 0xffff);
10821 /* Print `u' if this has an auto-increment or auto-decrement. */
10822 if (GET_CODE (x) == MEM
10823 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10824 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10829 /* Print the trap code for this operand. */
10830 switch (GET_CODE (x))
10833 fputs ("eq", file); /* 4 */
10836 fputs ("ne", file); /* 24 */
10839 fputs ("lt", file); /* 16 */
10842 fputs ("le", file); /* 20 */
10845 fputs ("gt", file); /* 8 */
10848 fputs ("ge", file); /* 12 */
10851 fputs ("llt", file); /* 2 */
10854 fputs ("lle", file); /* 6 */
10857 fputs ("lgt", file); /* 1 */
10860 fputs ("lge", file); /* 5 */
10868 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10871 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10872 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10874 print_operand (file, x, 0);
10878 /* MB value for a PowerPC64 rldic operand. */
10879 val = (GET_CODE (x) == CONST_INT
10880 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10885 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10886 if ((val <<= 1) < 0)
10889 #if HOST_BITS_PER_WIDE_INT == 32
10890 if (GET_CODE (x) == CONST_INT && i >= 0)
10891 i += 32; /* zero-extend high-part was all 0's */
10892 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10894 val = CONST_DOUBLE_LOW (x);
10901 for ( ; i < 64; i++)
10902 if ((val <<= 1) < 0)
10907 fprintf (file, "%d", i + 1);
10911 if (GET_CODE (x) == MEM
10912 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10917 /* Like 'L', for third word of TImode */
10918 if (GET_CODE (x) == REG)
10919 fputs (reg_names[REGNO (x) + 2], file);
10920 else if (GET_CODE (x) == MEM)
10922 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10923 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10924 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10926 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10927 if (small_data_operand (x, GET_MODE (x)))
10928 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10929 reg_names[SMALL_DATA_REG]);
10934 /* X is a SYMBOL_REF. Write out the name preceded by a
10935 period and without any trailing data in brackets. Used for function
10936 names. If we are configured for System V (or the embedded ABI) on
10937 the PowerPC, do not emit the period, since those systems do not use
10938 TOCs and the like. */
10939 if (GET_CODE (x) != SYMBOL_REF)
10942 /* Mark the decl as referenced so that cgraph will output the
10944 if (SYMBOL_REF_DECL (x))
10945 mark_decl_referenced (SYMBOL_REF_DECL (x));
10947 /* For macho, check to see if we need a stub. */
10950 const char *name = XSTR (x, 0);
10952 if (MACHOPIC_INDIRECT
10953 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10954 name = machopic_indirection_name (x, /*stub_p=*/true);
10956 assemble_name (file, name);
10958 else if (!DOT_SYMBOLS)
10959 assemble_name (file, XSTR (x, 0));
10961 rs6000_output_function_entry (file, XSTR (x, 0));
10965 /* Like 'L', for last word of TImode. */
10966 if (GET_CODE (x) == REG)
10967 fputs (reg_names[REGNO (x) + 3], file);
10968 else if (GET_CODE (x) == MEM)
10970 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10971 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10972 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10974 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10975 if (small_data_operand (x, GET_MODE (x)))
10976 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10977 reg_names[SMALL_DATA_REG]);
10981 /* Print AltiVec or SPE memory operand. */
10986 if (GET_CODE (x) != MEM)
10993 /* Handle [reg]. */
10994 if (GET_CODE (tmp) == REG)
10996 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10999 /* Handle [reg+UIMM]. */
11000 else if (GET_CODE (tmp) == PLUS &&
11001 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11005 if (GET_CODE (XEXP (tmp, 0)) != REG)
11008 x = INTVAL (XEXP (tmp, 1));
11009 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11013 /* Fall through. Must be [reg+reg]. */
11016 && GET_CODE (tmp) == AND
11017 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11018 && INTVAL (XEXP (tmp, 1)) == -16)
11019 tmp = XEXP (tmp, 0);
11020 if (GET_CODE (tmp) == REG)
11021 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11022 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
11024 if (REGNO (XEXP (tmp, 0)) == 0)
11025 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11026 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11028 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11029 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11037 if (GET_CODE (x) == REG)
11038 fprintf (file, "%s", reg_names[REGNO (x)]);
11039 else if (GET_CODE (x) == MEM)
11041 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11042 know the width from the mode. */
11043 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11044 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11045 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11046 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11047 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11048 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11050 output_address (XEXP (x, 0));
11053 output_addr_const (file, x);
11057 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11061 output_operand_lossage ("invalid %%xn code");
11065 /* Print the address of an operand. */
11068 print_operand_address (FILE *file, rtx x)
11070 if (GET_CODE (x) == REG)
11071 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11072 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11073 || GET_CODE (x) == LABEL_REF)
11075 output_addr_const (file, x);
11076 if (small_data_operand (x, GET_MODE (x)))
11077 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11078 reg_names[SMALL_DATA_REG]);
11079 else if (TARGET_TOC)
11082 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11084 if (REGNO (XEXP (x, 0)) == 0)
11085 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11086 reg_names[ REGNO (XEXP (x, 0)) ]);
11088 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11089 reg_names[ REGNO (XEXP (x, 1)) ]);
11091 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11092 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11093 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11095 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11096 && CONSTANT_P (XEXP (x, 1)))
11098 output_addr_const (file, XEXP (x, 1));
11099 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11103 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11104 && CONSTANT_P (XEXP (x, 1)))
11106 fprintf (file, "lo16(");
11107 output_addr_const (file, XEXP (x, 1));
11108 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11111 else if (legitimate_constant_pool_address_p (x))
11113 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11115 rtx contains_minus = XEXP (x, 1);
11119 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11120 turn it into (sym) for output_addr_const. */
11121 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11122 contains_minus = XEXP (contains_minus, 0);
11124 minus = XEXP (contains_minus, 0);
11125 symref = XEXP (minus, 0);
11126 XEXP (contains_minus, 0) = symref;
11131 name = XSTR (symref, 0);
11132 newname = alloca (strlen (name) + sizeof ("@toc"));
11133 strcpy (newname, name);
11134 strcat (newname, "@toc");
11135 XSTR (symref, 0) = newname;
11137 output_addr_const (file, XEXP (x, 1));
11139 XSTR (symref, 0) = name;
11140 XEXP (contains_minus, 0) = minus;
11143 output_addr_const (file, XEXP (x, 1));
11145 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11151 /* Target hook for assembling integer objects. The PowerPC version has
11152 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11153 is defined. It also needs to handle DI-mode objects on 64-bit
11157 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11159 #ifdef RELOCATABLE_NEEDS_FIXUP
11160 /* Special handling for SI values. */
11161 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11163 extern int in_toc_section (void);
11164 static int recurse = 0;
11166 /* For -mrelocatable, we mark all addresses that need to be fixed up
11167 in the .fixup section. */
11168 if (TARGET_RELOCATABLE
11169 && !in_toc_section ()
11170 && !in_text_section ()
11171 && !in_unlikely_text_section ()
11173 && GET_CODE (x) != CONST_INT
11174 && GET_CODE (x) != CONST_DOUBLE
11180 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11182 ASM_OUTPUT_LABEL (asm_out_file, buf);
11183 fprintf (asm_out_file, "\t.long\t(");
11184 output_addr_const (asm_out_file, x);
11185 fprintf (asm_out_file, ")@fixup\n");
11186 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11187 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11188 fprintf (asm_out_file, "\t.long\t");
11189 assemble_name (asm_out_file, buf);
11190 fprintf (asm_out_file, "\n\t.previous\n");
11194 /* Remove initial .'s to turn a -mcall-aixdesc function
11195 address into the address of the descriptor, not the function
11197 else if (GET_CODE (x) == SYMBOL_REF
11198 && XSTR (x, 0)[0] == '.'
11199 && DEFAULT_ABI == ABI_AIX)
11201 const char *name = XSTR (x, 0);
11202 while (*name == '.')
11205 fprintf (asm_out_file, "\t.long\t%s\n", name);
11209 #endif /* RELOCATABLE_NEEDS_FIXUP */
11210 return default_assemble_integer (x, size, aligned_p);
11213 #ifdef HAVE_GAS_HIDDEN
11214 /* Emit an assembler directive to set symbol visibility for DECL to
11215 VISIBILITY_TYPE. */
11218 rs6000_assemble_visibility (tree decl, int vis)
11220 /* Functions need to have their entry point symbol visibility set as
11221 well as their descriptor symbol visibility. */
11222 if (DEFAULT_ABI == ABI_AIX
11224 && TREE_CODE (decl) == FUNCTION_DECL)
11226 static const char * const visibility_types[] = {
11227 NULL, "internal", "hidden", "protected"
11230 const char *name, *type;
11232 name = ((* targetm.strip_name_encoding)
11233 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11234 type = visibility_types[vis];
11236 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11237 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11240 default_assemble_visibility (decl, vis);
11245 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11247 /* Reversal of FP compares takes care -- an ordered compare
11248 becomes an unordered compare and vice versa. */
11249 if (mode == CCFPmode
11250 && (!flag_finite_math_only
11251 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11252 || code == UNEQ || code == LTGT))
11253 return reverse_condition_maybe_unordered (code);
11255 return reverse_condition (code);
11258 /* Generate a compare for CODE. Return a brand-new rtx that
11259 represents the result of the compare. */
11262 rs6000_generate_compare (enum rtx_code code)
11264 enum machine_mode comp_mode;
11265 rtx compare_result;
11267 if (rs6000_compare_fp_p)
11268 comp_mode = CCFPmode;
11269 else if (code == GTU || code == LTU
11270 || code == GEU || code == LEU)
11271 comp_mode = CCUNSmode;
11272 else if ((code == EQ || code == NE)
11273 && GET_CODE (rs6000_compare_op0) == SUBREG
11274 && GET_CODE (rs6000_compare_op1) == SUBREG
11275 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11276 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11277 /* These are unsigned values, perhaps there will be a later
11278 ordering compare that can be shared with this one.
11279 Unfortunately we cannot detect the signedness of the operands
11280 for non-subregs. */
11281 comp_mode = CCUNSmode;
11283 comp_mode = CCmode;
11285 /* First, the compare. */
11286 compare_result = gen_reg_rtx (comp_mode);
11288 /* SPE FP compare instructions on the GPRs. Yuck! */
11289 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11290 && rs6000_compare_fp_p)
11292 rtx cmp, or1, or2, or_result, compare_result2;
11293 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11295 if (op_mode == VOIDmode)
11296 op_mode = GET_MODE (rs6000_compare_op1);
11298 /* Note: The E500 comparison instructions set the GT bit (x +
11299 1), on success. This explains the mess. */
11303 case EQ: case UNEQ: case NE: case LTGT:
11304 if (op_mode == SFmode)
11305 cmp = flag_finite_math_only
11306 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11307 rs6000_compare_op1)
11308 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11309 rs6000_compare_op1);
11310 else if (op_mode == DFmode)
11311 cmp = flag_finite_math_only
11312 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11313 rs6000_compare_op1)
11314 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11315 rs6000_compare_op1);
11318 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11319 if (op_mode == SFmode)
11320 cmp = flag_finite_math_only
11321 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11322 rs6000_compare_op1)
11323 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11324 rs6000_compare_op1);
11325 else if (op_mode == DFmode)
11326 cmp = flag_finite_math_only
11327 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11328 rs6000_compare_op1)
11329 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11330 rs6000_compare_op1);
11333 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11334 if (op_mode == SFmode)
11335 cmp = flag_finite_math_only
11336 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11337 rs6000_compare_op1)
11338 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11339 rs6000_compare_op1);
11340 else if (op_mode == DFmode)
11341 cmp = flag_finite_math_only
11342 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11343 rs6000_compare_op1)
11344 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11345 rs6000_compare_op1);
11352 /* Synthesize LE and GE from LT/GT || EQ. */
11353 if (code == LE || code == GE || code == LEU || code == GEU)
11359 case LE: code = LT; break;
11360 case GE: code = GT; break;
11361 case LEU: code = LT; break;
11362 case GEU: code = GT; break;
11366 or1 = gen_reg_rtx (SImode);
11367 or2 = gen_reg_rtx (SImode);
11368 or_result = gen_reg_rtx (CCEQmode);
11369 compare_result2 = gen_reg_rtx (CCFPmode);
11372 if (op_mode == SFmode)
11373 cmp = flag_finite_math_only
11374 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11375 rs6000_compare_op1)
11376 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11377 rs6000_compare_op1);
11378 else if (op_mode == DFmode)
11379 cmp = flag_finite_math_only
11380 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11381 rs6000_compare_op1)
11382 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11383 rs6000_compare_op1);
11387 or1 = gen_rtx_GT (SImode, compare_result, const0_rtx);
11388 or2 = gen_rtx_GT (SImode, compare_result2, const0_rtx);
11390 /* OR them together. */
11391 cmp = gen_rtx_SET (VOIDmode, or_result,
11392 gen_rtx_COMPARE (CCEQmode,
11393 gen_rtx_IOR (SImode, or1, or2),
11395 compare_result = or_result;
11400 if (code == NE || code == LTGT)
11409 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11410 gen_rtx_COMPARE (comp_mode,
11411 rs6000_compare_op0,
11412 rs6000_compare_op1)));
11414 /* Some kinds of FP comparisons need an OR operation;
11415 under flag_finite_math_only we don't bother. */
11416 if (rs6000_compare_fp_p
11417 && ! flag_finite_math_only
11418 && ! (TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11419 && (code == LE || code == GE
11420 || code == UNEQ || code == LTGT
11421 || code == UNGT || code == UNLT))
11423 enum rtx_code or1, or2;
11424 rtx or1_rtx, or2_rtx, compare2_rtx;
11425 rtx or_result = gen_reg_rtx (CCEQmode);
11429 case LE: or1 = LT; or2 = EQ; break;
11430 case GE: or1 = GT; or2 = EQ; break;
11431 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11432 case LTGT: or1 = LT; or2 = GT; break;
11433 case UNGT: or1 = UNORDERED; or2 = GT; break;
11434 case UNLT: or1 = UNORDERED; or2 = LT; break;
11437 validate_condition_mode (or1, comp_mode);
11438 validate_condition_mode (or2, comp_mode);
11439 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11440 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11441 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11442 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11444 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11446 compare_result = or_result;
11450 validate_condition_mode (code, GET_MODE (compare_result));
11452 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11456 /* Emit the RTL for an sCOND pattern. */
11459 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11462 enum machine_mode op_mode;
11463 enum rtx_code cond_code;
11465 condition_rtx = rs6000_generate_compare (code);
11466 cond_code = GET_CODE (condition_rtx);
11468 if (TARGET_E500 && rs6000_compare_fp_p
11469 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11473 PUT_MODE (condition_rtx, SImode);
11474 t = XEXP (condition_rtx, 0);
11476 if (cond_code != NE && cond_code != EQ)
11479 if (cond_code == NE)
11480 emit_insn (gen_e500_flip_eq_bit (t, t));
11482 emit_insn (gen_move_from_CR_eq_bit (result, t));
11486 if (cond_code == NE
11487 || cond_code == GE || cond_code == LE
11488 || cond_code == GEU || cond_code == LEU
11489 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11491 rtx not_result = gen_reg_rtx (CCEQmode);
11492 rtx not_op, rev_cond_rtx;
11493 enum machine_mode cc_mode;
11495 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11497 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11498 SImode, XEXP (condition_rtx, 0), const0_rtx);
11499 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11500 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11501 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11504 op_mode = GET_MODE (rs6000_compare_op0);
11505 if (op_mode == VOIDmode)
11506 op_mode = GET_MODE (rs6000_compare_op1);
11508 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11510 PUT_MODE (condition_rtx, DImode);
11511 convert_move (result, condition_rtx, 0);
11515 PUT_MODE (condition_rtx, SImode);
11516 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11520 /* Emit a branch of kind CODE to location LOC. */
11523 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11525 rtx condition_rtx, loc_ref;
11527 condition_rtx = rs6000_generate_compare (code);
11528 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11529 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11530 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11531 loc_ref, pc_rtx)));
11534 /* Return the string to output a conditional branch to LABEL, which is
11535 the operand number of the label, or -1 if the branch is really a
11536 conditional return.
11538 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11539 condition code register and its mode specifies what kind of
11540 comparison we made.
11542 REVERSED is nonzero if we should reverse the sense of the comparison.
11544 INSN is the insn. */
11547 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11549 static char string[64];
11550 enum rtx_code code = GET_CODE (op);
11551 rtx cc_reg = XEXP (op, 0);
11552 enum machine_mode mode = GET_MODE (cc_reg);
11553 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11554 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11555 int really_reversed = reversed ^ need_longbranch;
11561 validate_condition_mode (code, mode);
11563 /* Work out which way this really branches. We could use
11564 reverse_condition_maybe_unordered here always but this
11565 makes the resulting assembler clearer. */
11566 if (really_reversed)
11568 /* Reversal of FP compares takes care -- an ordered compare
11569 becomes an unordered compare and vice versa. */
11570 if (mode == CCFPmode)
11571 code = reverse_condition_maybe_unordered (code);
11573 code = reverse_condition (code);
11576 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11578 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11581 /* Opposite of GT. */
11583 else if (code == NE)
11591 /* Not all of these are actually distinct opcodes, but
11592 we distinguish them for clarity of the resulting assembler. */
11593 case NE: case LTGT:
11594 ccode = "ne"; break;
11595 case EQ: case UNEQ:
11596 ccode = "eq"; break;
11598 ccode = "ge"; break;
11599 case GT: case GTU: case UNGT:
11600 ccode = "gt"; break;
11602 ccode = "le"; break;
11603 case LT: case LTU: case UNLT:
11604 ccode = "lt"; break;
11605 case UNORDERED: ccode = "un"; break;
11606 case ORDERED: ccode = "nu"; break;
11607 case UNGE: ccode = "nl"; break;
11608 case UNLE: ccode = "ng"; break;
11613 /* Maybe we have a guess as to how likely the branch is.
11614 The old mnemonics don't have a way to specify this information. */
11616 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11617 if (note != NULL_RTX)
11619 /* PROB is the difference from 50%. */
11620 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11622 /* Only hint for highly probable/improbable branches on newer
11623 cpus as static prediction overrides processor dynamic
11624 prediction. For older cpus we may as well always hint, but
11625 assume not taken for branches that are very close to 50% as a
11626 mispredicted taken branch is more expensive than a
11627 mispredicted not-taken branch. */
11628 if (rs6000_always_hint
11629 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11631 if (abs (prob) > REG_BR_PROB_BASE / 20
11632 && ((prob > 0) ^ need_longbranch))
11640 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11642 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11644 /* We need to escape any '%' characters in the reg_names string.
11645 Assume they'd only be the first character.... */
11646 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11648 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11652 /* If the branch distance was too far, we may have to use an
11653 unconditional branch to go the distance. */
11654 if (need_longbranch)
11655 s += sprintf (s, ",$+8\n\tb %s", label);
11657 s += sprintf (s, ",%s", label);
11663 /* Return the string to flip the EQ bit on a CR. */
11665 output_e500_flip_eq_bit (rtx dst, rtx src)
11667 static char string[64];
11670 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
11671 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
11675 a = 4 * (REGNO (dst) - CR0_REGNO) + 2;
11676 b = 4 * (REGNO (src) - CR0_REGNO) + 2;
11678 sprintf (string, "crnot %d,%d", a, b);
11682 /* Return insn index for the vector compare instruction for given CODE,
11683 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11687 get_vec_cmp_insn (enum rtx_code code,
11688 enum machine_mode dest_mode,
11689 enum machine_mode op_mode)
11691 if (!TARGET_ALTIVEC)
11692 return INSN_NOT_AVAILABLE;
11697 if (dest_mode == V16QImode && op_mode == V16QImode)
11698 return UNSPEC_VCMPEQUB;
11699 if (dest_mode == V8HImode && op_mode == V8HImode)
11700 return UNSPEC_VCMPEQUH;
11701 if (dest_mode == V4SImode && op_mode == V4SImode)
11702 return UNSPEC_VCMPEQUW;
11703 if (dest_mode == V4SImode && op_mode == V4SFmode)
11704 return UNSPEC_VCMPEQFP;
11707 if (dest_mode == V4SImode && op_mode == V4SFmode)
11708 return UNSPEC_VCMPGEFP;
11710 if (dest_mode == V16QImode && op_mode == V16QImode)
11711 return UNSPEC_VCMPGTSB;
11712 if (dest_mode == V8HImode && op_mode == V8HImode)
11713 return UNSPEC_VCMPGTSH;
11714 if (dest_mode == V4SImode && op_mode == V4SImode)
11715 return UNSPEC_VCMPGTSW;
11716 if (dest_mode == V4SImode && op_mode == V4SFmode)
11717 return UNSPEC_VCMPGTFP;
11720 if (dest_mode == V16QImode && op_mode == V16QImode)
11721 return UNSPEC_VCMPGTUB;
11722 if (dest_mode == V8HImode && op_mode == V8HImode)
11723 return UNSPEC_VCMPGTUH;
11724 if (dest_mode == V4SImode && op_mode == V4SImode)
11725 return UNSPEC_VCMPGTUW;
11730 return INSN_NOT_AVAILABLE;
11733 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11734 DMODE is expected destination mode. This is a recursive function. */
11737 rs6000_emit_vector_compare (enum rtx_code rcode,
11739 enum machine_mode dmode)
11743 enum machine_mode dest_mode;
11744 enum machine_mode op_mode = GET_MODE (op1);
11746 #ifdef ENABLE_CHECKING
11747 if (!TARGET_ALTIVEC)
11750 if (GET_MODE (op0) != GET_MODE (op1))
11754 /* Floating point vector compare instructions uses destination V4SImode.
11755 Move destination to appropriate mode later. */
11756 if (dmode == V4SFmode)
11757 dest_mode = V4SImode;
11761 mask = gen_reg_rtx (dest_mode);
11762 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11764 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11766 bool swap_operands = false;
11767 bool try_again = false;
11772 swap_operands = true;
11777 swap_operands = true;
11781 /* Treat A != B as ~(A==B). */
11783 enum insn_code nor_code;
11784 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11787 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11788 if (nor_code == CODE_FOR_nothing)
11790 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11792 if (dmode != dest_mode)
11794 rtx temp = gen_reg_rtx (dest_mode);
11795 convert_move (temp, mask, 0);
11805 /* Try GT/GTU/LT/LTU OR EQ */
11808 enum insn_code ior_code;
11809 enum rtx_code new_code;
11813 else if (rcode == GEU)
11815 else if (rcode == LE)
11817 else if (rcode == LEU)
11822 c_rtx = rs6000_emit_vector_compare (new_code,
11823 op0, op1, dest_mode);
11824 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11827 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11828 if (ior_code == CODE_FOR_nothing)
11830 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11831 if (dmode != dest_mode)
11833 rtx temp = gen_reg_rtx (dest_mode);
11834 convert_move (temp, mask, 0);
11846 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11847 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11848 /* You only get two chances. */
11861 emit_insn (gen_rtx_fmt_ee (SET,
11864 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11865 gen_rtvec (2, op0, op1),
11867 if (dmode != dest_mode)
11869 rtx temp = gen_reg_rtx (dest_mode);
11870 convert_move (temp, mask, 0);
11876 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11877 valid insn doesn exist for given mode. */
11880 get_vsel_insn (enum machine_mode mode)
11885 return UNSPEC_VSEL4SI;
11888 return UNSPEC_VSEL4SF;
11891 return UNSPEC_VSEL8HI;
11894 return UNSPEC_VSEL16QI;
11897 return INSN_NOT_AVAILABLE;
11900 return INSN_NOT_AVAILABLE;
11903 /* Emit vector select insn where DEST is destination using
11904 operands OP1, OP2 and MASK. */
11907 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11910 enum machine_mode dest_mode = GET_MODE (dest);
11911 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11913 temp = gen_reg_rtx (dest_mode);
11915 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
11916 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
11917 gen_rtvec (3, op1, op2, mask),
11920 emit_move_insn (dest, temp);
11924 /* Emit vector conditional expression.
11925 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11926 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11929 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11930 rtx cond, rtx cc_op0, rtx cc_op1)
11932 enum machine_mode dest_mode = GET_MODE (dest);
11933 enum rtx_code rcode = GET_CODE (cond);
11936 if (!TARGET_ALTIVEC)
11939 /* Get the vector mask for the given relational operations. */
11940 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11942 rs6000_emit_vector_select (dest, op1, op2, mask);
11947 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11948 operands of the last comparison is nonzero/true, FALSE_COND if it
11949 is zero/false. Return 0 if the hardware has no such operation. */
11952 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11954 enum rtx_code code = GET_CODE (op);
11955 rtx op0 = rs6000_compare_op0;
11956 rtx op1 = rs6000_compare_op1;
11957 REAL_VALUE_TYPE c1;
11958 enum machine_mode compare_mode = GET_MODE (op0);
11959 enum machine_mode result_mode = GET_MODE (dest);
11961 bool is_against_zero;
11963 /* These modes should always match. */
11964 if (GET_MODE (op1) != compare_mode
11965 /* In the isel case however, we can use a compare immediate, so
11966 op1 may be a small constant. */
11967 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11969 if (GET_MODE (true_cond) != result_mode)
11971 if (GET_MODE (false_cond) != result_mode)
11974 /* First, work out if the hardware can do this at all, or
11975 if it's too slow.... */
11976 if (! rs6000_compare_fp_p)
11979 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11982 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11983 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11986 is_against_zero = op1 == CONST0_RTX (compare_mode);
11988 /* A floating-point subtract might overflow, underflow, or produce
11989 an inexact result, thus changing the floating-point flags, so it
11990 can't be generated if we care about that. It's safe if one side
11991 of the construct is zero, since then no subtract will be
11993 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11994 && flag_trapping_math && ! is_against_zero)
11997 /* Eliminate half of the comparisons by switching operands, this
11998 makes the remaining code simpler. */
11999 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12000 || code == LTGT || code == LT || code == UNLE)
12002 code = reverse_condition_maybe_unordered (code);
12004 true_cond = false_cond;
12008 /* UNEQ and LTGT take four instructions for a comparison with zero,
12009 it'll probably be faster to use a branch here too. */
12010 if (code == UNEQ && HONOR_NANS (compare_mode))
12013 if (GET_CODE (op1) == CONST_DOUBLE)
12014 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12016 /* We're going to try to implement comparisons by performing
12017 a subtract, then comparing against zero. Unfortunately,
12018 Inf - Inf is NaN which is not zero, and so if we don't
12019 know that the operand is finite and the comparison
12020 would treat EQ different to UNORDERED, we can't do it. */
12021 if (HONOR_INFINITIES (compare_mode)
12022 && code != GT && code != UNGE
12023 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12024 /* Constructs of the form (a OP b ? a : b) are safe. */
12025 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12026 || (! rtx_equal_p (op0, true_cond)
12027 && ! rtx_equal_p (op1, true_cond))))
12030 /* At this point we know we can use fsel. */
12032 /* Reduce the comparison to a comparison against zero. */
12033 if (! is_against_zero)
12035 temp = gen_reg_rtx (compare_mode);
12036 emit_insn (gen_rtx_SET (VOIDmode, temp,
12037 gen_rtx_MINUS (compare_mode, op0, op1)));
12039 op1 = CONST0_RTX (compare_mode);
12042 /* If we don't care about NaNs we can reduce some of the comparisons
12043 down to faster ones. */
12044 if (! HONOR_NANS (compare_mode))
12050 true_cond = false_cond;
12063 /* Now, reduce everything down to a GE. */
12070 temp = gen_reg_rtx (compare_mode);
12071 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12076 temp = gen_reg_rtx (compare_mode);
12077 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12082 temp = gen_reg_rtx (compare_mode);
12083 emit_insn (gen_rtx_SET (VOIDmode, temp,
12084 gen_rtx_NEG (compare_mode,
12085 gen_rtx_ABS (compare_mode, op0))));
12090 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12091 temp = gen_reg_rtx (result_mode);
12092 emit_insn (gen_rtx_SET (VOIDmode, temp,
12093 gen_rtx_IF_THEN_ELSE (result_mode,
12094 gen_rtx_GE (VOIDmode,
12096 true_cond, false_cond)));
12097 false_cond = true_cond;
12100 temp = gen_reg_rtx (compare_mode);
12101 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12106 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12107 temp = gen_reg_rtx (result_mode);
12108 emit_insn (gen_rtx_SET (VOIDmode, temp,
12109 gen_rtx_IF_THEN_ELSE (result_mode,
12110 gen_rtx_GE (VOIDmode,
12112 true_cond, false_cond)));
12113 true_cond = false_cond;
12116 temp = gen_reg_rtx (compare_mode);
12117 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12125 emit_insn (gen_rtx_SET (VOIDmode, dest,
12126 gen_rtx_IF_THEN_ELSE (result_mode,
12127 gen_rtx_GE (VOIDmode,
12129 true_cond, false_cond)));
12133 /* Same as above, but for ints (isel). */
12136 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12138 rtx condition_rtx, cr;
12140 /* All isel implementations thus far are 32-bits. */
12141 if (GET_MODE (rs6000_compare_op0) != SImode)
12144 /* We still have to do the compare, because isel doesn't do a
12145 compare, it just looks at the CRx bits set by a previous compare
12147 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12148 cr = XEXP (condition_rtx, 0);
12150 if (GET_MODE (cr) == CCmode)
12151 emit_insn (gen_isel_signed (dest, condition_rtx,
12152 true_cond, false_cond, cr));
12154 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12155 true_cond, false_cond, cr));
12161 output_isel (rtx *operands)
12163 enum rtx_code code;
12165 code = GET_CODE (operands[1]);
12166 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12168 PUT_CODE (operands[1], reverse_condition (code));
12169 return "isel %0,%3,%2,%j1";
12172 return "isel %0,%2,%3,%j1";
12176 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12178 enum machine_mode mode = GET_MODE (op0);
12182 if (code == SMAX || code == SMIN)
12187 if (code == SMAX || code == UMAX)
12188 target = emit_conditional_move (dest, c, op0, op1, mode,
12189 op0, op1, mode, 0);
12191 target = emit_conditional_move (dest, c, op0, op1, mode,
12192 op1, op0, mode, 0);
12193 if (target == NULL_RTX)
12195 if (target != dest)
12196 emit_move_insn (dest, target);
12199 /* Emit instructions to move SRC to DST. Called by splitters for
12200 multi-register moves. It will emit at most one instruction for
12201 each register that is accessed; that is, it won't emit li/lis pairs
12202 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12206 rs6000_split_multireg_move (rtx dst, rtx src)
12208 /* The register number of the first register being moved. */
12210 /* The mode that is to be moved. */
12211 enum machine_mode mode;
12212 /* The mode that the move is being done in, and its size. */
12213 enum machine_mode reg_mode;
12215 /* The number of registers that will be moved. */
12218 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12219 mode = GET_MODE (dst);
12220 nregs = HARD_REGNO_NREGS (reg, mode);
12221 if (FP_REGNO_P (reg))
12223 else if (ALTIVEC_REGNO_P (reg))
12224 reg_mode = V16QImode;
12226 reg_mode = word_mode;
12227 reg_mode_size = GET_MODE_SIZE (reg_mode);
12229 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
12232 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12234 /* Move register range backwards, if we might have destructive
12237 for (i = nregs - 1; i >= 0; i--)
12238 emit_insn (gen_rtx_SET (VOIDmode,
12239 simplify_gen_subreg (reg_mode, dst, mode,
12240 i * reg_mode_size),
12241 simplify_gen_subreg (reg_mode, src, mode,
12242 i * reg_mode_size)));
12248 bool used_update = false;
12250 if (MEM_P (src) && INT_REGNO_P (reg))
12254 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12255 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12258 breg = XEXP (XEXP (src, 0), 0);
12259 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12260 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12261 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12262 emit_insn (TARGET_32BIT
12263 ? gen_addsi3 (breg, breg, delta_rtx)
12264 : gen_adddi3 (breg, breg, delta_rtx));
12265 src = gen_rtx_MEM (mode, breg);
12267 else if (! offsettable_memref_p (src))
12269 rtx newsrc, basereg;
12270 basereg = gen_rtx_REG (Pmode, reg);
12271 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12272 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
12273 MEM_COPY_ATTRIBUTES (newsrc, src);
12277 breg = XEXP (src, 0);
12278 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12279 breg = XEXP (breg, 0);
12281 /* If the base register we are using to address memory is
12282 also a destination reg, then change that register last. */
12284 && REGNO (breg) >= REGNO (dst)
12285 && REGNO (breg) < REGNO (dst) + nregs)
12286 j = REGNO (breg) - REGNO (dst);
12289 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12293 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12294 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12297 breg = XEXP (XEXP (dst, 0), 0);
12298 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12299 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12300 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12302 /* We have to update the breg before doing the store.
12303 Use store with update, if available. */
12307 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12308 emit_insn (TARGET_32BIT
12309 ? (TARGET_POWERPC64
12310 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12311 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12312 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12313 used_update = true;
12316 emit_insn (TARGET_32BIT
12317 ? gen_addsi3 (breg, breg, delta_rtx)
12318 : gen_adddi3 (breg, breg, delta_rtx));
12319 dst = gen_rtx_MEM (mode, breg);
12321 else if (! offsettable_memref_p (dst))
12325 for (i = 0; i < nregs; i++)
12327 /* Calculate index to next subword. */
12332 /* If compiler already emitted move of first word by
12333 store with update, no need to do anything. */
12334 if (j == 0 && used_update)
12337 emit_insn (gen_rtx_SET (VOIDmode,
12338 simplify_gen_subreg (reg_mode, dst, mode,
12339 j * reg_mode_size),
12340 simplify_gen_subreg (reg_mode, src, mode,
12341 j * reg_mode_size)));
12347 /* This page contains routines that are used to determine what the
12348 function prologue and epilogue code will do and write them out. */
12350 /* Return the first fixed-point register that is required to be
12351 saved. 32 if none. */
12354 first_reg_to_save (void)
12358 /* Find lowest numbered live register. */
12359 for (first_reg = 13; first_reg <= 31; first_reg++)
12360 if (regs_ever_live[first_reg]
12361 && (! call_used_regs[first_reg]
12362 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12363 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12364 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12365 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12370 && current_function_uses_pic_offset_table
12371 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12372 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12378 /* Similar, for FP regs. */
12381 first_fp_reg_to_save (void)
12385 /* Find lowest numbered live register. */
12386 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12387 if (regs_ever_live[first_reg])
12393 /* Similar, for AltiVec regs. */
12396 first_altivec_reg_to_save (void)
12400 /* Stack frame remains as is unless we are in AltiVec ABI. */
12401 if (! TARGET_ALTIVEC_ABI)
12402 return LAST_ALTIVEC_REGNO + 1;
12404 /* Find lowest numbered live register. */
12405 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12406 if (regs_ever_live[i])
12412 /* Return a 32-bit mask of the AltiVec registers we need to set in
12413 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12414 the 32-bit word is 0. */
12416 static unsigned int
12417 compute_vrsave_mask (void)
12419 unsigned int i, mask = 0;
12421 /* First, find out if we use _any_ altivec registers. */
12422 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12423 if (regs_ever_live[i])
12424 mask |= ALTIVEC_REG_BIT (i);
12429 /* Next, remove the argument registers from the set. These must
12430 be in the VRSAVE mask set by the caller, so we don't need to add
12431 them in again. More importantly, the mask we compute here is
12432 used to generate CLOBBERs in the set_vrsave insn, and we do not
12433 wish the argument registers to die. */
12434 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12435 mask &= ~ALTIVEC_REG_BIT (i);
12437 /* Similarly, remove the return value from the set. */
12440 diddle_return_value (is_altivec_return_reg, &yes);
12442 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12448 /* For a very restricted set of circumstances, we can cut down the
12449 size of prologues/epilogues by calling our own save/restore-the-world
12453 compute_save_world_info (rs6000_stack_t *info_ptr)
12455 info_ptr->world_save_p = 1;
12456 info_ptr->world_save_p
12457 = (WORLD_SAVE_P (info_ptr)
12458 && DEFAULT_ABI == ABI_DARWIN
12459 && ! (current_function_calls_setjmp && flag_exceptions)
12460 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12461 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12462 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12463 && info_ptr->cr_save_p);
12465 /* This will not work in conjunction with sibcalls. Make sure there
12466 are none. (This check is expensive, but seldom executed.) */
12467 if (WORLD_SAVE_P (info_ptr))
12470 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12471 if ( GET_CODE (insn) == CALL_INSN
12472 && SIBLING_CALL_P (insn))
12474 info_ptr->world_save_p = 0;
12479 if (WORLD_SAVE_P (info_ptr))
12481 /* Even if we're not touching VRsave, make sure there's room on the
12482 stack for it, if it looks like we're calling SAVE_WORLD, which
12483 will attempt to save it. */
12484 info_ptr->vrsave_size = 4;
12486 /* "Save" the VRsave register too if we're saving the world. */
12487 if (info_ptr->vrsave_mask == 0)
12488 info_ptr->vrsave_mask = compute_vrsave_mask ();
12490 /* Because the Darwin register save/restore routines only handle
12491 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12492 check and abort if there's something worng. */
12493 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
12494 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
12502 is_altivec_return_reg (rtx reg, void *xyes)
12504 bool *yes = (bool *) xyes;
12505 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12510 /* Calculate the stack information for the current function. This is
12511 complicated by having two separate calling sequences, the AIX calling
12512 sequence and the V.4 calling sequence.
12514 AIX (and Darwin/Mac OS X) stack frames look like:
12516 SP----> +---------------------------------------+
12517 | back chain to caller | 0 0
12518 +---------------------------------------+
12519 | saved CR | 4 8 (8-11)
12520 +---------------------------------------+
12522 +---------------------------------------+
12523 | reserved for compilers | 12 24
12524 +---------------------------------------+
12525 | reserved for binders | 16 32
12526 +---------------------------------------+
12527 | saved TOC pointer | 20 40
12528 +---------------------------------------+
12529 | Parameter save area (P) | 24 48
12530 +---------------------------------------+
12531 | Alloca space (A) | 24+P etc.
12532 +---------------------------------------+
12533 | Local variable space (L) | 24+P+A
12534 +---------------------------------------+
12535 | Float/int conversion temporary (X) | 24+P+A+L
12536 +---------------------------------------+
12537 | Save area for AltiVec registers (W) | 24+P+A+L+X
12538 +---------------------------------------+
12539 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12540 +---------------------------------------+
12541 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12542 +---------------------------------------+
12543 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12544 +---------------------------------------+
12545 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12546 +---------------------------------------+
12547 old SP->| back chain to caller's caller |
12548 +---------------------------------------+
12550 The required alignment for AIX configurations is two words (i.e., 8
12554 V.4 stack frames look like:
12556 SP----> +---------------------------------------+
12557 | back chain to caller | 0
12558 +---------------------------------------+
12559 | caller's saved LR | 4
12560 +---------------------------------------+
12561 | Parameter save area (P) | 8
12562 +---------------------------------------+
12563 | Alloca space (A) | 8+P
12564 +---------------------------------------+
12565 | Varargs save area (V) | 8+P+A
12566 +---------------------------------------+
12567 | Local variable space (L) | 8+P+A+V
12568 +---------------------------------------+
12569 | Float/int conversion temporary (X) | 8+P+A+V+L
12570 +---------------------------------------+
12571 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12572 +---------------------------------------+
12573 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12574 +---------------------------------------+
12575 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12576 +---------------------------------------+
12577 | SPE: area for 64-bit GP registers |
12578 +---------------------------------------+
12579 | SPE alignment padding |
12580 +---------------------------------------+
12581 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12582 +---------------------------------------+
12583 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12584 +---------------------------------------+
12585 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12586 +---------------------------------------+
12587 old SP->| back chain to caller's caller |
12588 +---------------------------------------+
12590 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12591 given. (But note below and in sysv4.h that we require only 8 and
12592 may round up the size of our stack frame anyways. The historical
12593 reason is early versions of powerpc-linux which didn't properly
12594 align the stack at program startup. A happy side-effect is that
12595 -mno-eabi libraries can be used with -meabi programs.)
12597 The EABI configuration defaults to the V.4 layout. However,
12598 the stack alignment requirements may differ. If -mno-eabi is not
12599 given, the required stack alignment is 8 bytes; if -mno-eabi is
12600 given, the required alignment is 16 bytes. (But see V.4 comment
12603 #ifndef ABI_STACK_BOUNDARY
12604 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12607 static rs6000_stack_t *
12608 rs6000_stack_info (void)
12610 static rs6000_stack_t info, zero_info;
12611 rs6000_stack_t *info_ptr = &info;
12612 int reg_size = TARGET_32BIT ? 4 : 8;
12615 HOST_WIDE_INT non_fixed_size;
12617 /* Zero all fields portably. */
12622 /* Cache value so we don't rescan instruction chain over and over. */
12623 if (cfun->machine->insn_chain_scanned_p == 0)
12625 cfun->machine->insn_chain_scanned_p = 1;
12626 info_ptr->spe_64bit_regs_used = (int) spe_func_has_64bit_regs_p ();
12630 /* Select which calling sequence. */
12631 info_ptr->abi = DEFAULT_ABI;
12633 /* Calculate which registers need to be saved & save area size. */
12634 info_ptr->first_gp_reg_save = first_reg_to_save ();
12635 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12636 even if it currently looks like we won't. */
12637 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12638 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12639 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12640 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12641 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12643 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12645 /* For the SPE, we have an additional upper 32-bits on each GPR.
12646 Ideally we should save the entire 64-bits only when the upper
12647 half is used in SIMD instructions. Since we only record
12648 registers live (not the size they are used in), this proves
12649 difficult because we'd have to traverse the instruction chain at
12650 the right time, taking reload into account. This is a real pain,
12651 so we opt to save the GPRs in 64-bits always if but one register
12652 gets used in 64-bits. Otherwise, all the registers in the frame
12653 get saved in 32-bits.
12655 So... since when we save all GPRs (except the SP) in 64-bits, the
12656 traditional GP save area will be empty. */
12657 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12658 info_ptr->gp_size = 0;
12660 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12661 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12663 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12664 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12665 - info_ptr->first_altivec_reg_save);
12667 /* Does this function call anything? */
12668 info_ptr->calls_p = (! current_function_is_leaf
12669 || cfun->machine->ra_needs_full_frame);
12671 /* Determine if we need to save the link register. */
12672 if (rs6000_ra_ever_killed ()
12673 || (DEFAULT_ABI == ABI_AIX
12674 && current_function_profile
12675 && !TARGET_PROFILE_KERNEL)
12676 #ifdef TARGET_RELOCATABLE
12677 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12679 || (info_ptr->first_fp_reg_save != 64
12680 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12681 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12682 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12683 || (DEFAULT_ABI == ABI_DARWIN
12685 && current_function_uses_pic_offset_table)
12686 || info_ptr->calls_p)
12688 info_ptr->lr_save_p = 1;
12689 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12692 /* Determine if we need to save the condition code registers. */
12693 if (regs_ever_live[CR2_REGNO]
12694 || regs_ever_live[CR3_REGNO]
12695 || regs_ever_live[CR4_REGNO])
12697 info_ptr->cr_save_p = 1;
12698 if (DEFAULT_ABI == ABI_V4)
12699 info_ptr->cr_size = reg_size;
12702 /* If the current function calls __builtin_eh_return, then we need
12703 to allocate stack space for registers that will hold data for
12704 the exception handler. */
12705 if (current_function_calls_eh_return)
12708 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12711 /* SPE saves EH registers in 64-bits. */
12712 ehrd_size = i * (TARGET_SPE_ABI
12713 && info_ptr->spe_64bit_regs_used != 0
12714 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12719 /* Determine various sizes. */
12720 info_ptr->reg_size = reg_size;
12721 info_ptr->fixed_size = RS6000_SAVE_AREA;
12722 info_ptr->varargs_size = RS6000_VARARGS_AREA;
12723 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12724 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12725 TARGET_ALTIVEC ? 16 : 8);
12727 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12728 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12730 info_ptr->spe_gp_size = 0;
12732 if (TARGET_ALTIVEC_ABI)
12733 info_ptr->vrsave_mask = compute_vrsave_mask ();
12735 info_ptr->vrsave_mask = 0;
12737 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12738 info_ptr->vrsave_size = 4;
12740 info_ptr->vrsave_size = 0;
12742 compute_save_world_info (info_ptr);
12744 /* Calculate the offsets. */
12745 switch (DEFAULT_ABI)
12753 info_ptr->fp_save_offset = - info_ptr->fp_size;
12754 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12756 if (TARGET_ALTIVEC_ABI)
12758 info_ptr->vrsave_save_offset
12759 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12761 /* Align stack so vector save area is on a quadword boundary. */
12762 if (info_ptr->altivec_size != 0)
12763 info_ptr->altivec_padding_size
12764 = 16 - (-info_ptr->vrsave_save_offset % 16);
12766 info_ptr->altivec_padding_size = 0;
12768 info_ptr->altivec_save_offset
12769 = info_ptr->vrsave_save_offset
12770 - info_ptr->altivec_padding_size
12771 - info_ptr->altivec_size;
12773 /* Adjust for AltiVec case. */
12774 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12777 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12778 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12779 info_ptr->lr_save_offset = 2*reg_size;
12783 info_ptr->fp_save_offset = - info_ptr->fp_size;
12784 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12785 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12787 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12789 /* Align stack so SPE GPR save area is aligned on a
12790 double-word boundary. */
12791 if (info_ptr->spe_gp_size != 0)
12792 info_ptr->spe_padding_size
12793 = 8 - (-info_ptr->cr_save_offset % 8);
12795 info_ptr->spe_padding_size = 0;
12797 info_ptr->spe_gp_save_offset
12798 = info_ptr->cr_save_offset
12799 - info_ptr->spe_padding_size
12800 - info_ptr->spe_gp_size;
12802 /* Adjust for SPE case. */
12803 info_ptr->toc_save_offset
12804 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12806 else if (TARGET_ALTIVEC_ABI)
12808 info_ptr->vrsave_save_offset
12809 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12811 /* Align stack so vector save area is on a quadword boundary. */
12812 if (info_ptr->altivec_size != 0)
12813 info_ptr->altivec_padding_size
12814 = 16 - (-info_ptr->vrsave_save_offset % 16);
12816 info_ptr->altivec_padding_size = 0;
12818 info_ptr->altivec_save_offset
12819 = info_ptr->vrsave_save_offset
12820 - info_ptr->altivec_padding_size
12821 - info_ptr->altivec_size;
12823 /* Adjust for AltiVec case. */
12824 info_ptr->toc_save_offset
12825 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12828 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12829 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12830 info_ptr->lr_save_offset = reg_size;
12834 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12835 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12836 + info_ptr->gp_size
12837 + info_ptr->altivec_size
12838 + info_ptr->altivec_padding_size
12839 + info_ptr->spe_gp_size
12840 + info_ptr->spe_padding_size
12842 + info_ptr->cr_size
12843 + info_ptr->lr_size
12844 + info_ptr->vrsave_size
12845 + info_ptr->toc_size,
12848 non_fixed_size = (info_ptr->vars_size
12849 + info_ptr->parm_size
12850 + info_ptr->save_size
12851 + info_ptr->varargs_size);
12853 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12854 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12856 /* Determine if we need to allocate any stack frame:
12858 For AIX we need to push the stack if a frame pointer is needed
12859 (because the stack might be dynamically adjusted), if we are
12860 debugging, if we make calls, or if the sum of fp_save, gp_save,
12861 and local variables are more than the space needed to save all
12862 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12863 + 18*8 = 288 (GPR13 reserved).
12865 For V.4 we don't have the stack cushion that AIX uses, but assume
12866 that the debugger can handle stackless frames. */
12868 if (info_ptr->calls_p)
12869 info_ptr->push_p = 1;
12871 else if (DEFAULT_ABI == ABI_V4)
12872 info_ptr->push_p = non_fixed_size != 0;
12874 else if (frame_pointer_needed)
12875 info_ptr->push_p = 1;
12877 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12878 info_ptr->push_p = 1;
12881 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12883 /* Zero offsets if we're not saving those registers. */
12884 if (info_ptr->fp_size == 0)
12885 info_ptr->fp_save_offset = 0;
12887 if (info_ptr->gp_size == 0)
12888 info_ptr->gp_save_offset = 0;
12890 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12891 info_ptr->altivec_save_offset = 0;
12893 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12894 info_ptr->vrsave_save_offset = 0;
12896 if (! TARGET_SPE_ABI
12897 || info_ptr->spe_64bit_regs_used == 0
12898 || info_ptr->spe_gp_size == 0)
12899 info_ptr->spe_gp_save_offset = 0;
12901 if (! info_ptr->lr_save_p)
12902 info_ptr->lr_save_offset = 0;
12904 if (! info_ptr->cr_save_p)
12905 info_ptr->cr_save_offset = 0;
12907 if (! info_ptr->toc_save_p)
12908 info_ptr->toc_save_offset = 0;
12913 /* Return true if the current function uses any GPRs in 64-bit SIMD
12917 spe_func_has_64bit_regs_p (void)
12921 /* Functions that save and restore all the call-saved registers will
12922 need to save/restore the registers in 64-bits. */
12923 if (current_function_calls_eh_return
12924 || current_function_calls_setjmp
12925 || current_function_has_nonlocal_goto)
12928 insns = get_insns ();
12930 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12936 i = PATTERN (insn);
12937 if (GET_CODE (i) == SET)
12939 enum machine_mode mode = GET_MODE (SET_SRC (i));
12941 if (SPE_VECTOR_MODE (mode))
12943 if (TARGET_E500_DOUBLE && mode == DFmode)
12953 debug_stack_info (rs6000_stack_t *info)
12955 const char *abi_string;
12958 info = rs6000_stack_info ();
12960 fprintf (stderr, "\nStack information for function %s:\n",
12961 ((current_function_decl && DECL_NAME (current_function_decl))
12962 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
12967 default: abi_string = "Unknown"; break;
12968 case ABI_NONE: abi_string = "NONE"; break;
12969 case ABI_AIX: abi_string = "AIX"; break;
12970 case ABI_DARWIN: abi_string = "Darwin"; break;
12971 case ABI_V4: abi_string = "V.4"; break;
12974 fprintf (stderr, "\tABI = %5s\n", abi_string);
12976 if (TARGET_ALTIVEC_ABI)
12977 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
12979 if (TARGET_SPE_ABI)
12980 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
12982 if (info->first_gp_reg_save != 32)
12983 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
12985 if (info->first_fp_reg_save != 64)
12986 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
12988 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
12989 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
12990 info->first_altivec_reg_save);
12992 if (info->lr_save_p)
12993 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
12995 if (info->cr_save_p)
12996 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
12998 if (info->toc_save_p)
12999 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
13001 if (info->vrsave_mask)
13002 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13005 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13008 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13010 if (info->gp_save_offset)
13011 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13013 if (info->fp_save_offset)
13014 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13016 if (info->altivec_save_offset)
13017 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13018 info->altivec_save_offset);
13020 if (info->spe_gp_save_offset)
13021 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13022 info->spe_gp_save_offset);
13024 if (info->vrsave_save_offset)
13025 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13026 info->vrsave_save_offset);
13028 if (info->lr_save_offset)
13029 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13031 if (info->cr_save_offset)
13032 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13034 if (info->toc_save_offset)
13035 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
13037 if (info->varargs_save_offset)
13038 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13040 if (info->total_size)
13041 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13044 if (info->varargs_size)
13045 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
13047 if (info->vars_size)
13048 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13051 if (info->parm_size)
13052 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13054 if (info->fixed_size)
13055 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13058 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13060 if (info->spe_gp_size)
13061 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13064 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13066 if (info->altivec_size)
13067 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13069 if (info->vrsave_size)
13070 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13072 if (info->altivec_padding_size)
13073 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13074 info->altivec_padding_size);
13076 if (info->spe_padding_size)
13077 fprintf (stderr, "\tspe_padding_size = %5d\n",
13078 info->spe_padding_size);
13081 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13084 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13086 if (info->toc_size)
13087 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13089 if (info->save_size)
13090 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13092 if (info->reg_size != 4)
13093 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13095 fprintf (stderr, "\n");
13099 rs6000_return_addr (int count, rtx frame)
13101 /* Currently we don't optimize very well between prolog and body
13102 code and for PIC code the code can be actually quite bad, so
13103 don't try to be too clever here. */
13104 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13106 cfun->machine->ra_needs_full_frame = 1;
13113 plus_constant (copy_to_reg
13114 (gen_rtx_MEM (Pmode,
13115 memory_address (Pmode, frame))),
13116 RETURN_ADDRESS_OFFSET)));
13119 cfun->machine->ra_need_lr = 1;
13120 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13123 /* Say whether a function is a candidate for sibcall handling or not.
13124 We do not allow indirect calls to be optimized into sibling calls.
13125 Also, we can't do it if there are any vector parameters; there's
13126 nowhere to put the VRsave code so it works; note that functions with
13127 vector parameters are required to have a prototype, so the argument
13128 type info must be available here. (The tail recursion case can work
13129 with vector parameters, but there's no way to distinguish here.) */
13131 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13136 if (TARGET_ALTIVEC_VRSAVE)
13138 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13139 type; type = TREE_CHAIN (type))
13141 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13145 if (DEFAULT_ABI == ABI_DARWIN
13146 || (*targetm.binds_local_p) (decl))
13148 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13150 if (!lookup_attribute ("longcall", attr_list)
13151 || lookup_attribute ("shortcall", attr_list))
13159 rs6000_ra_ever_killed (void)
13165 if (current_function_is_thunk)
13168 /* regs_ever_live has LR marked as used if any sibcalls are present,
13169 but this should not force saving and restoring in the
13170 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13171 clobbers LR, so that is inappropriate. */
13173 /* Also, the prologue can generate a store into LR that
13174 doesn't really count, like this:
13177 bcl to set PIC register
13181 When we're called from the epilogue, we need to avoid counting
13182 this as a store. */
13184 push_topmost_sequence ();
13185 top = get_insns ();
13186 pop_topmost_sequence ();
13187 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13189 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13193 if (FIND_REG_INC_NOTE (insn, reg))
13195 else if (GET_CODE (insn) == CALL_INSN
13196 && !SIBLING_CALL_P (insn))
13198 else if (set_of (reg, insn) != NULL_RTX
13199 && !prologue_epilogue_contains (insn))
13206 /* Add a REG_MAYBE_DEAD note to the insn. */
13208 rs6000_maybe_dead (rtx insn)
13210 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13215 /* Emit instructions needed to load the TOC register.
13216 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13217 a constant pool; or for SVR4 -fpic. */
13220 rs6000_emit_load_toc_table (int fromprolog)
13223 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13225 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13227 rtx temp = (fromprolog
13228 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13229 : gen_reg_rtx (Pmode));
13230 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
13232 rs6000_maybe_dead (insn);
13233 insn = emit_move_insn (dest, temp);
13235 rs6000_maybe_dead (insn);
13237 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13240 rtx tempLR = (fromprolog
13241 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13242 : gen_reg_rtx (Pmode));
13243 rtx temp0 = (fromprolog
13244 ? gen_rtx_REG (Pmode, 0)
13245 : gen_reg_rtx (Pmode));
13248 /* possibly create the toc section */
13249 if (! toc_initialized)
13252 function_section (current_function_decl);
13259 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13260 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13262 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13263 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13265 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13267 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13268 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13275 static int reload_toc_labelno = 0;
13277 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13279 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
13280 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13282 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
13283 emit_move_insn (dest, tempLR);
13284 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13286 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13288 rs6000_maybe_dead (insn);
13290 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13292 /* This is for AIX code running in non-PIC ELF32. */
13295 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13296 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13298 insn = emit_insn (gen_elf_high (dest, realsym));
13300 rs6000_maybe_dead (insn);
13301 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13303 rs6000_maybe_dead (insn);
13305 else if (DEFAULT_ABI == ABI_AIX)
13308 insn = emit_insn (gen_load_toc_aix_si (dest));
13310 insn = emit_insn (gen_load_toc_aix_di (dest));
13312 rs6000_maybe_dead (insn);
13318 /* Emit instructions to restore the link register after determining where
13319 its value has been stored. */
13322 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13324 rs6000_stack_t *info = rs6000_stack_info ();
13327 operands[0] = source;
13328 operands[1] = scratch;
13330 if (info->lr_save_p)
13332 rtx frame_rtx = stack_pointer_rtx;
13333 HOST_WIDE_INT sp_offset = 0;
13336 if (frame_pointer_needed
13337 || current_function_calls_alloca
13338 || info->total_size > 32767)
13340 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13341 frame_rtx = operands[1];
13343 else if (info->push_p)
13344 sp_offset = info->total_size;
13346 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13347 tmp = gen_rtx_MEM (Pmode, tmp);
13348 emit_move_insn (tmp, operands[0]);
13351 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13354 static GTY(()) int set = -1;
13357 get_TOC_alias_set (void)
13360 set = new_alias_set ();
13364 /* This returns nonzero if the current function uses the TOC. This is
13365 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13366 is generated by the ABI_V4 load_toc_* patterns. */
13373 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13376 rtx pat = PATTERN (insn);
13379 if (GET_CODE (pat) == PARALLEL)
13380 for (i = 0; i < XVECLEN (pat, 0); i++)
13382 rtx sub = XVECEXP (pat, 0, i);
13383 if (GET_CODE (sub) == USE)
13385 sub = XEXP (sub, 0);
13386 if (GET_CODE (sub) == UNSPEC
13387 && XINT (sub, 1) == UNSPEC_TOC)
13397 create_TOC_reference (rtx symbol)
13399 return gen_rtx_PLUS (Pmode,
13400 gen_rtx_REG (Pmode, TOC_REGISTER),
13401 gen_rtx_CONST (Pmode,
13402 gen_rtx_MINUS (Pmode, symbol,
13403 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13406 /* If _Unwind_* has been called from within the same module,
13407 toc register is not guaranteed to be saved to 40(1) on function
13408 entry. Save it there in that case. */
13411 rs6000_aix_emit_builtin_unwind_init (void)
13414 rtx stack_top = gen_reg_rtx (Pmode);
13415 rtx opcode_addr = gen_reg_rtx (Pmode);
13416 rtx opcode = gen_reg_rtx (SImode);
13417 rtx tocompare = gen_reg_rtx (SImode);
13418 rtx no_toc_save_needed = gen_label_rtx ();
13420 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13421 emit_move_insn (stack_top, mem);
13423 mem = gen_rtx_MEM (Pmode,
13424 gen_rtx_PLUS (Pmode, stack_top,
13425 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13426 emit_move_insn (opcode_addr, mem);
13427 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13428 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13429 : 0xE8410028, SImode));
13431 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13432 SImode, NULL_RTX, NULL_RTX,
13433 no_toc_save_needed);
13435 mem = gen_rtx_MEM (Pmode,
13436 gen_rtx_PLUS (Pmode, stack_top,
13437 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13438 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13439 emit_label (no_toc_save_needed);
13442 /* This ties together stack memory (MEM with an alias set of
13443 rs6000_sr_alias_set) and the change to the stack pointer. */
13446 rs6000_emit_stack_tie (void)
13448 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13450 set_mem_alias_set (mem, rs6000_sr_alias_set);
13451 emit_insn (gen_stack_tie (mem));
13454 /* Emit the correct code for allocating stack space, as insns.
13455 If COPY_R12, make sure a copy of the old frame is left in r12.
13456 The generated code may use hard register 0 as a temporary. */
13459 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13462 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13463 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13464 rtx todec = gen_int_mode (-size, Pmode);
13466 if (INTVAL (todec) != -size)
13468 warning("stack frame too large");
13469 emit_insn (gen_trap ());
13473 if (current_function_limit_stack)
13475 if (REG_P (stack_limit_rtx)
13476 && REGNO (stack_limit_rtx) > 1
13477 && REGNO (stack_limit_rtx) <= 31)
13479 emit_insn (TARGET_32BIT
13480 ? gen_addsi3 (tmp_reg,
13483 : gen_adddi3 (tmp_reg,
13487 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13490 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13492 && DEFAULT_ABI == ABI_V4)
13494 rtx toload = gen_rtx_CONST (VOIDmode,
13495 gen_rtx_PLUS (Pmode,
13499 emit_insn (gen_elf_high (tmp_reg, toload));
13500 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13501 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13505 warning ("stack limit expression is not supported");
13508 if (copy_r12 || ! TARGET_UPDATE)
13509 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13515 /* Need a note here so that try_split doesn't get confused. */
13516 if (get_last_insn() == NULL_RTX)
13517 emit_note (NOTE_INSN_DELETED);
13518 insn = emit_move_insn (tmp_reg, todec);
13519 try_split (PATTERN (insn), insn, 0);
13523 insn = emit_insn (TARGET_32BIT
13524 ? gen_movsi_update (stack_reg, stack_reg,
13526 : gen_movdi_di_update (stack_reg, stack_reg,
13527 todec, stack_reg));
13531 insn = emit_insn (TARGET_32BIT
13532 ? gen_addsi3 (stack_reg, stack_reg, todec)
13533 : gen_adddi3 (stack_reg, stack_reg, todec));
13534 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13535 gen_rtx_REG (Pmode, 12));
13538 RTX_FRAME_RELATED_P (insn) = 1;
13540 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13541 gen_rtx_SET (VOIDmode, stack_reg,
13542 gen_rtx_PLUS (Pmode, stack_reg,
13547 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13548 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13549 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13550 deduce these equivalences by itself so it wasn't necessary to hold
13551 its hand so much. */
13554 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13555 rtx reg2, rtx rreg)
13559 /* copy_rtx will not make unique copies of registers, so we need to
13560 ensure we don't have unwanted sharing here. */
13562 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13565 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13567 real = copy_rtx (PATTERN (insn));
13569 if (reg2 != NULL_RTX)
13570 real = replace_rtx (real, reg2, rreg);
13572 real = replace_rtx (real, reg,
13573 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13574 STACK_POINTER_REGNUM),
13577 /* We expect that 'real' is either a SET or a PARALLEL containing
13578 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13579 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13581 if (GET_CODE (real) == SET)
13585 temp = simplify_rtx (SET_SRC (set));
13587 SET_SRC (set) = temp;
13588 temp = simplify_rtx (SET_DEST (set));
13590 SET_DEST (set) = temp;
13591 if (GET_CODE (SET_DEST (set)) == MEM)
13593 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13595 XEXP (SET_DEST (set), 0) = temp;
13598 else if (GET_CODE (real) == PARALLEL)
13601 for (i = 0; i < XVECLEN (real, 0); i++)
13602 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13604 rtx set = XVECEXP (real, 0, i);
13606 temp = simplify_rtx (SET_SRC (set));
13608 SET_SRC (set) = temp;
13609 temp = simplify_rtx (SET_DEST (set));
13611 SET_DEST (set) = temp;
13612 if (GET_CODE (SET_DEST (set)) == MEM)
13614 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13616 XEXP (SET_DEST (set), 0) = temp;
13618 RTX_FRAME_RELATED_P (set) = 1;
13625 real = spe_synthesize_frame_save (real);
13627 RTX_FRAME_RELATED_P (insn) = 1;
13628 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13633 /* Given an SPE frame note, return a PARALLEL of SETs with the
13634 original note, plus a synthetic register save. */
13637 spe_synthesize_frame_save (rtx real)
13639 rtx synth, offset, reg, real2;
13641 if (GET_CODE (real) != SET
13642 || GET_MODE (SET_SRC (real)) != V2SImode)
13645 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13646 frame related note. The parallel contains a set of the register
13647 being saved, and another set to a synthetic register (n+1200).
13648 This is so we can differentiate between 64-bit and 32-bit saves.
13649 Words cannot describe this nastiness. */
13651 if (GET_CODE (SET_DEST (real)) != MEM
13652 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
13653 || GET_CODE (SET_SRC (real)) != REG)
13657 (set (mem (plus (reg x) (const y)))
13660 (set (mem (plus (reg x) (const y+4)))
13664 real2 = copy_rtx (real);
13665 PUT_MODE (SET_DEST (real2), SImode);
13666 reg = SET_SRC (real2);
13667 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13668 synth = copy_rtx (real2);
13670 if (BYTES_BIG_ENDIAN)
13672 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13673 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13676 reg = SET_SRC (synth);
13678 synth = replace_rtx (synth, reg,
13679 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13681 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13682 synth = replace_rtx (synth, offset,
13683 GEN_INT (INTVAL (offset)
13684 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13686 RTX_FRAME_RELATED_P (synth) = 1;
13687 RTX_FRAME_RELATED_P (real2) = 1;
13688 if (BYTES_BIG_ENDIAN)
13689 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13691 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13696 /* Returns an insn that has a vrsave set operation with the
13697 appropriate CLOBBERs. */
13700 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13703 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13704 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13707 = gen_rtx_SET (VOIDmode,
13709 gen_rtx_UNSPEC_VOLATILE (SImode,
13710 gen_rtvec (2, reg, vrsave),
13715 /* We need to clobber the registers in the mask so the scheduler
13716 does not move sets to VRSAVE before sets of AltiVec registers.
13718 However, if the function receives nonlocal gotos, reload will set
13719 all call saved registers live. We will end up with:
13721 (set (reg 999) (mem))
13722 (parallel [ (set (reg vrsave) (unspec blah))
13723 (clobber (reg 999))])
13725 The clobber will cause the store into reg 999 to be dead, and
13726 flow will attempt to delete an epilogue insn. In this case, we
13727 need an unspec use/set of the register. */
13729 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13730 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13732 if (!epiloguep || call_used_regs [i])
13733 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13734 gen_rtx_REG (V4SImode, i));
13737 rtx reg = gen_rtx_REG (V4SImode, i);
13740 = gen_rtx_SET (VOIDmode,
13742 gen_rtx_UNSPEC (V4SImode,
13743 gen_rtvec (1, reg), 27));
13747 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13749 for (i = 0; i < nclobs; ++i)
13750 XVECEXP (insn, 0, i) = clobs[i];
13755 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13756 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13759 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13760 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13762 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13763 rtx replacea, replaceb;
13765 int_rtx = GEN_INT (offset);
13767 /* Some cases that need register indexed addressing. */
13768 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13769 || (TARGET_E500_DOUBLE && mode == DFmode)
13771 && SPE_VECTOR_MODE (mode)
13772 && !SPE_CONST_OFFSET_OK (offset)))
13774 /* Whomever calls us must make sure r11 is available in the
13775 flow path of instructions in the prologue. */
13776 offset_rtx = gen_rtx_REG (Pmode, 11);
13777 emit_move_insn (offset_rtx, int_rtx);
13779 replacea = offset_rtx;
13780 replaceb = int_rtx;
13784 offset_rtx = int_rtx;
13785 replacea = NULL_RTX;
13786 replaceb = NULL_RTX;
13789 reg = gen_rtx_REG (mode, regno);
13790 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13791 mem = gen_rtx_MEM (mode, addr);
13792 set_mem_alias_set (mem, rs6000_sr_alias_set);
13794 insn = emit_move_insn (mem, reg);
13796 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13799 /* Emit an offset memory reference suitable for a frame store, while
13800 converting to a valid addressing mode. */
13803 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13805 rtx int_rtx, offset_rtx;
13807 int_rtx = GEN_INT (offset);
13809 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13810 || (TARGET_E500_DOUBLE && mode == DFmode))
13812 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13813 emit_move_insn (offset_rtx, int_rtx);
13816 offset_rtx = int_rtx;
13818 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13821 #ifndef TARGET_FIX_AND_CONTINUE
13822 #define TARGET_FIX_AND_CONTINUE 0
13825 /* Emit function prologue as insns. */
13828 rs6000_emit_prologue (void)
13830 rs6000_stack_t *info = rs6000_stack_info ();
13831 enum machine_mode reg_mode = Pmode;
13832 int reg_size = TARGET_32BIT ? 4 : 8;
13833 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13834 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13835 rtx frame_reg_rtx = sp_reg_rtx;
13836 rtx cr_save_rtx = NULL_RTX;
13838 int saving_FPRs_inline;
13839 int using_store_multiple;
13840 HOST_WIDE_INT sp_offset = 0;
13842 if (TARGET_FIX_AND_CONTINUE)
13844 /* gdb on darwin arranges to forward a function from the old
13845 address by modifying the first 4 instructions of the function
13846 to branch to the overriding function. This is necessary to
13847 permit function pointers that point to the old function to
13848 actually forward to the new function. */
13849 emit_insn (gen_nop ());
13850 emit_insn (gen_nop ());
13851 emit_insn (gen_nop ());
13852 emit_insn (gen_nop ());
13855 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13857 reg_mode = V2SImode;
13861 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13862 && (!TARGET_SPE_ABI
13863 || info->spe_64bit_regs_used == 0)
13864 && info->first_gp_reg_save < 31);
13865 saving_FPRs_inline = (info->first_fp_reg_save == 64
13866 || FP_SAVE_INLINE (info->first_fp_reg_save)
13867 || current_function_calls_eh_return
13868 || cfun->machine->ra_need_lr);
13870 /* For V.4, update stack before we do any saving and set back pointer. */
13872 && (DEFAULT_ABI == ABI_V4
13873 || current_function_calls_eh_return))
13875 if (info->total_size < 32767)
13876 sp_offset = info->total_size;
13878 frame_reg_rtx = frame_ptr_rtx;
13879 rs6000_emit_allocate_stack (info->total_size,
13880 (frame_reg_rtx != sp_reg_rtx
13881 && (info->cr_save_p
13883 || info->first_fp_reg_save < 64
13884 || info->first_gp_reg_save < 32
13886 if (frame_reg_rtx != sp_reg_rtx)
13887 rs6000_emit_stack_tie ();
13890 /* Handle world saves specially here. */
13891 if (WORLD_SAVE_P (info))
13897 /* save_world expects lr in r0. */
13898 if (info->lr_save_p)
13900 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
13901 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
13902 RTX_FRAME_RELATED_P (insn) = 1;
13905 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
13906 assumptions about the offsets of various bits of the stack
13907 frame. Abort if things aren't what they should be. */
13908 if (info->gp_save_offset != -220
13909 || info->fp_save_offset != -144
13910 || info->lr_save_offset != 8
13911 || info->cr_save_offset != 4
13913 || !info->lr_save_p
13914 || (current_function_calls_eh_return && info->ehrd_offset != -432)
13915 || (info->vrsave_save_offset != -224
13916 || info->altivec_save_offset != (-224 -16 -192)))
13919 treg = gen_rtx_REG (SImode, 11);
13920 emit_move_insn (treg, GEN_INT (-info->total_size));
13922 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
13923 in R11. It also clobbers R12, so beware! */
13925 /* Preserve CR2 for save_world prologues */
13927 sz += 32 - info->first_gp_reg_save;
13928 sz += 64 - info->first_fp_reg_save;
13929 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
13930 p = rtvec_alloc (sz);
13932 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
13933 gen_rtx_REG (Pmode,
13934 LINK_REGISTER_REGNUM));
13935 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13936 gen_rtx_SYMBOL_REF (Pmode,
13938 /* We do floats first so that the instruction pattern matches
13940 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13942 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13943 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13944 GEN_INT (info->fp_save_offset
13945 + sp_offset + 8 * i));
13946 rtx mem = gen_rtx_MEM (DFmode, addr);
13947 set_mem_alias_set (mem, rs6000_sr_alias_set);
13949 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13951 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13953 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13954 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13955 GEN_INT (info->altivec_save_offset
13956 + sp_offset + 16 * i));
13957 rtx mem = gen_rtx_MEM (V4SImode, addr);
13958 set_mem_alias_set (mem, rs6000_sr_alias_set);
13960 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13962 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13964 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13965 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13966 GEN_INT (info->gp_save_offset
13967 + sp_offset + reg_size * i));
13968 rtx mem = gen_rtx_MEM (reg_mode, addr);
13969 set_mem_alias_set (mem, rs6000_sr_alias_set);
13971 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13975 /* CR register traditionally saved as CR2. */
13976 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13977 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13978 GEN_INT (info->cr_save_offset
13980 rtx mem = gen_rtx_MEM (reg_mode, addr);
13981 set_mem_alias_set (mem, rs6000_sr_alias_set);
13983 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
13985 /* Prevent any attempt to delete the setting of r0 and treg! */
13986 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
13987 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
13988 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
13990 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13991 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13992 NULL_RTX, NULL_RTX);
13994 if (current_function_calls_eh_return)
13999 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14000 if (regno == INVALID_REGNUM)
14002 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14003 info->ehrd_offset + sp_offset
14004 + reg_size * (int) i,
14010 /* Save AltiVec registers if needed. */
14011 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14015 /* There should be a non inline version of this, for when we
14016 are saving lots of vector registers. */
14017 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14018 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14020 rtx areg, savereg, mem;
14023 offset = info->altivec_save_offset + sp_offset
14024 + 16 * (i - info->first_altivec_reg_save);
14026 savereg = gen_rtx_REG (V4SImode, i);
14028 areg = gen_rtx_REG (Pmode, 0);
14029 emit_move_insn (areg, GEN_INT (offset));
14031 /* AltiVec addressing mode is [reg+reg]. */
14032 mem = gen_rtx_MEM (V4SImode,
14033 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14035 set_mem_alias_set (mem, rs6000_sr_alias_set);
14037 insn = emit_move_insn (mem, savereg);
14039 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14040 areg, GEN_INT (offset));
14044 /* VRSAVE is a bit vector representing which AltiVec registers
14045 are used. The OS uses this to determine which vector
14046 registers to save on a context switch. We need to save
14047 VRSAVE on the stack frame, add whatever AltiVec registers we
14048 used in this function, and do the corresponding magic in the
14051 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14052 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
14054 rtx reg, mem, vrsave;
14057 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14058 as frame_reg_rtx and r11 as the static chain pointer for
14059 nested functions. */
14060 reg = gen_rtx_REG (SImode, 0);
14061 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14063 emit_insn (gen_get_vrsave_internal (reg));
14065 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14068 offset = info->vrsave_save_offset + sp_offset;
14070 = gen_rtx_MEM (SImode,
14071 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14072 set_mem_alias_set (mem, rs6000_sr_alias_set);
14073 insn = emit_move_insn (mem, reg);
14075 /* Include the registers in the mask. */
14076 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14078 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14081 /* If we use the link register, get it into r0. */
14082 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14084 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14085 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14086 RTX_FRAME_RELATED_P (insn) = 1;
14089 /* If we need to save CR, put it into r12. */
14090 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14094 cr_save_rtx = gen_rtx_REG (SImode, 12);
14095 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14096 RTX_FRAME_RELATED_P (insn) = 1;
14097 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14098 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14099 But that's OK. All we have to do is specify that _one_ condition
14100 code register is saved in this stack slot. The thrower's epilogue
14101 will then restore all the call-saved registers.
14102 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14103 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14104 gen_rtx_REG (SImode, CR2_REGNO));
14105 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14110 /* Do any required saving of fpr's. If only one or two to save, do
14111 it ourselves. Otherwise, call function. */
14112 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14115 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14116 if ((regs_ever_live[info->first_fp_reg_save+i]
14117 && ! call_used_regs[info->first_fp_reg_save+i]))
14118 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14119 info->first_fp_reg_save + i,
14120 info->fp_save_offset + sp_offset + 8 * i,
14123 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14127 const char *alloc_rname;
14129 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14131 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14132 gen_rtx_REG (Pmode,
14133 LINK_REGISTER_REGNUM));
14134 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14135 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14136 alloc_rname = ggc_strdup (rname);
14137 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14138 gen_rtx_SYMBOL_REF (Pmode,
14140 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14142 rtx addr, reg, mem;
14143 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14144 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14145 GEN_INT (info->fp_save_offset
14146 + sp_offset + 8*i));
14147 mem = gen_rtx_MEM (DFmode, addr);
14148 set_mem_alias_set (mem, rs6000_sr_alias_set);
14150 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14152 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14153 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14154 NULL_RTX, NULL_RTX);
14157 /* Save GPRs. This is done as a PARALLEL if we are using
14158 the store-multiple instructions. */
14159 if (!WORLD_SAVE_P (info) && using_store_multiple)
14163 p = rtvec_alloc (32 - info->first_gp_reg_save);
14164 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14166 rtx addr, reg, mem;
14167 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14168 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14169 GEN_INT (info->gp_save_offset
14172 mem = gen_rtx_MEM (reg_mode, addr);
14173 set_mem_alias_set (mem, rs6000_sr_alias_set);
14175 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14177 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14178 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14179 NULL_RTX, NULL_RTX);
14181 else if (!WORLD_SAVE_P (info))
14184 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14185 if ((regs_ever_live[info->first_gp_reg_save+i]
14186 && (! call_used_regs[info->first_gp_reg_save+i]
14187 || (i+info->first_gp_reg_save
14188 == RS6000_PIC_OFFSET_TABLE_REGNUM
14189 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14190 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14191 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14192 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14194 rtx addr, reg, mem;
14195 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14197 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14199 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14202 if (!SPE_CONST_OFFSET_OK (offset))
14204 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14205 emit_move_insn (b, GEN_INT (offset));
14208 b = GEN_INT (offset);
14210 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14211 mem = gen_rtx_MEM (V2SImode, addr);
14212 set_mem_alias_set (mem, rs6000_sr_alias_set);
14213 insn = emit_move_insn (mem, reg);
14215 if (GET_CODE (b) == CONST_INT)
14216 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14217 NULL_RTX, NULL_RTX);
14219 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14220 b, GEN_INT (offset));
14224 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14225 GEN_INT (info->gp_save_offset
14228 mem = gen_rtx_MEM (reg_mode, addr);
14229 set_mem_alias_set (mem, rs6000_sr_alias_set);
14231 insn = emit_move_insn (mem, reg);
14232 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14233 NULL_RTX, NULL_RTX);
14238 /* ??? There's no need to emit actual instructions here, but it's the
14239 easiest way to get the frame unwind information emitted. */
14240 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14242 unsigned int i, regno;
14244 /* In AIX ABI we need to pretend we save r2 here. */
14247 rtx addr, reg, mem;
14249 reg = gen_rtx_REG (reg_mode, 2);
14250 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14251 GEN_INT (sp_offset + 5 * reg_size));
14252 mem = gen_rtx_MEM (reg_mode, addr);
14253 set_mem_alias_set (mem, rs6000_sr_alias_set);
14255 insn = emit_move_insn (mem, reg);
14256 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14257 NULL_RTX, NULL_RTX);
14258 PATTERN (insn) = gen_blockage ();
14263 regno = EH_RETURN_DATA_REGNO (i);
14264 if (regno == INVALID_REGNUM)
14267 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14268 info->ehrd_offset + sp_offset
14269 + reg_size * (int) i,
14274 /* Save lr if we used it. */
14275 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14277 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14278 GEN_INT (info->lr_save_offset + sp_offset));
14279 rtx reg = gen_rtx_REG (Pmode, 0);
14280 rtx mem = gen_rtx_MEM (Pmode, addr);
14281 /* This should not be of rs6000_sr_alias_set, because of
14282 __builtin_return_address. */
14284 insn = emit_move_insn (mem, reg);
14285 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14286 NULL_RTX, NULL_RTX);
14289 /* Save CR if we use any that must be preserved. */
14290 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14292 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14293 GEN_INT (info->cr_save_offset + sp_offset));
14294 rtx mem = gen_rtx_MEM (SImode, addr);
14295 /* See the large comment above about why CR2_REGNO is used. */
14296 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14298 set_mem_alias_set (mem, rs6000_sr_alias_set);
14300 /* If r12 was used to hold the original sp, copy cr into r0 now
14302 if (REGNO (frame_reg_rtx) == 12)
14306 cr_save_rtx = gen_rtx_REG (SImode, 0);
14307 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14308 RTX_FRAME_RELATED_P (insn) = 1;
14309 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14310 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14315 insn = emit_move_insn (mem, cr_save_rtx);
14317 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14318 NULL_RTX, NULL_RTX);
14321 /* Update stack and set back pointer unless this is V.4,
14322 for which it was done previously. */
14323 if (!WORLD_SAVE_P (info) && info->push_p
14324 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14325 rs6000_emit_allocate_stack (info->total_size, FALSE);
14327 /* Set frame pointer, if needed. */
14328 if (frame_pointer_needed)
14330 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
14332 RTX_FRAME_RELATED_P (insn) = 1;
14335 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14336 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14337 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
14338 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14340 /* If emit_load_toc_table will use the link register, we need to save
14341 it. We use R12 for this purpose because emit_load_toc_table
14342 can use register 0. This allows us to use a plain 'blr' to return
14343 from the procedure more often. */
14344 int save_LR_around_toc_setup = (TARGET_ELF
14345 && DEFAULT_ABI != ABI_AIX
14347 && ! info->lr_save_p
14348 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14349 if (save_LR_around_toc_setup)
14351 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14353 insn = emit_move_insn (frame_ptr_rtx, lr);
14354 rs6000_maybe_dead (insn);
14355 RTX_FRAME_RELATED_P (insn) = 1;
14357 rs6000_emit_load_toc_table (TRUE);
14359 insn = emit_move_insn (lr, frame_ptr_rtx);
14360 rs6000_maybe_dead (insn);
14361 RTX_FRAME_RELATED_P (insn) = 1;
14364 rs6000_emit_load_toc_table (TRUE);
14368 if (DEFAULT_ABI == ABI_DARWIN
14369 && flag_pic && current_function_uses_pic_offset_table)
14371 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14372 rtx src = machopic_function_base_sym ();
14374 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14376 insn = emit_move_insn (gen_rtx_REG (Pmode,
14377 RS6000_PIC_OFFSET_TABLE_REGNUM),
14379 rs6000_maybe_dead (insn);
14384 /* Write function prologue. */
14387 rs6000_output_function_prologue (FILE *file,
14388 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14390 rs6000_stack_t *info = rs6000_stack_info ();
14392 if (TARGET_DEBUG_STACK)
14393 debug_stack_info (info);
14395 /* Write .extern for any function we will call to save and restore
14397 if (info->first_fp_reg_save < 64
14398 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14399 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14400 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14401 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14402 RESTORE_FP_SUFFIX);
14404 /* Write .extern for AIX common mode routines, if needed. */
14405 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14407 fputs ("\t.extern __mulh\n", file);
14408 fputs ("\t.extern __mull\n", file);
14409 fputs ("\t.extern __divss\n", file);
14410 fputs ("\t.extern __divus\n", file);
14411 fputs ("\t.extern __quoss\n", file);
14412 fputs ("\t.extern __quous\n", file);
14413 common_mode_defined = 1;
14416 if (! HAVE_prologue)
14420 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14421 the "toplevel" insn chain. */
14422 emit_note (NOTE_INSN_DELETED);
14423 rs6000_emit_prologue ();
14424 emit_note (NOTE_INSN_DELETED);
14426 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14430 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14432 INSN_ADDRESSES_NEW (insn, addr);
14437 if (TARGET_DEBUG_STACK)
14438 debug_rtx_list (get_insns (), 100);
14439 final (get_insns (), file, FALSE, FALSE);
14443 rs6000_pic_labelno++;
14446 /* Emit function epilogue as insns.
14448 At present, dwarf2out_frame_debug_expr doesn't understand
14449 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14450 anywhere in the epilogue. Most of the insns below would in any case
14451 need special notes to explain where r11 is in relation to the stack. */
14454 rs6000_emit_epilogue (int sibcall)
14456 rs6000_stack_t *info;
14457 int restoring_FPRs_inline;
14458 int using_load_multiple;
14459 int using_mfcr_multiple;
14460 int use_backchain_to_restore_sp;
14462 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14463 rtx frame_reg_rtx = sp_reg_rtx;
14464 enum machine_mode reg_mode = Pmode;
14465 int reg_size = TARGET_32BIT ? 4 : 8;
14468 info = rs6000_stack_info ();
14470 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14472 reg_mode = V2SImode;
14476 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14477 && (!TARGET_SPE_ABI
14478 || info->spe_64bit_regs_used == 0)
14479 && info->first_gp_reg_save < 31);
14480 restoring_FPRs_inline = (sibcall
14481 || current_function_calls_eh_return
14482 || info->first_fp_reg_save == 64
14483 || FP_SAVE_INLINE (info->first_fp_reg_save));
14484 use_backchain_to_restore_sp = (frame_pointer_needed
14485 || current_function_calls_alloca
14486 || info->total_size > 32767);
14487 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14488 || rs6000_cpu == PROCESSOR_PPC603
14489 || rs6000_cpu == PROCESSOR_PPC750
14492 if (WORLD_SAVE_P (info))
14496 const char *alloc_rname;
14499 /* eh_rest_world_r10 will return to the location saved in the LR
14500 stack slot (which is not likely to be our caller.)
14501 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14502 rest_world is similar, except any R10 parameter is ignored.
14503 The exception-handling stuff that was here in 2.95 is no
14504 longer necessary. */
14508 + 32 - info->first_gp_reg_save
14509 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14510 + 63 + 1 - info->first_fp_reg_save);
14512 strcpy (rname, ((current_function_calls_eh_return) ?
14513 "*eh_rest_world_r10" : "*rest_world"));
14514 alloc_rname = ggc_strdup (rname);
14517 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14518 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14519 gen_rtx_REG (Pmode,
14520 LINK_REGISTER_REGNUM));
14522 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14523 /* The instruction pattern requires a clobber here;
14524 it is shared with the restVEC helper. */
14526 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14529 /* CR register traditionally saved as CR2. */
14530 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14531 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14532 GEN_INT (info->cr_save_offset));
14533 rtx mem = gen_rtx_MEM (reg_mode, addr);
14534 set_mem_alias_set (mem, rs6000_sr_alias_set);
14536 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14539 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14541 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14542 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14543 GEN_INT (info->gp_save_offset
14545 rtx mem = gen_rtx_MEM (reg_mode, addr);
14546 set_mem_alias_set (mem, rs6000_sr_alias_set);
14548 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14550 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14552 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14553 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14554 GEN_INT (info->altivec_save_offset
14556 rtx mem = gen_rtx_MEM (V4SImode, addr);
14557 set_mem_alias_set (mem, rs6000_sr_alias_set);
14559 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14561 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14563 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14564 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14565 GEN_INT (info->fp_save_offset
14567 rtx mem = gen_rtx_MEM (DFmode, addr);
14568 set_mem_alias_set (mem, rs6000_sr_alias_set);
14570 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14573 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14575 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14577 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14579 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14581 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14582 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14587 /* If we have a frame pointer, a call to alloca, or a large stack
14588 frame, restore the old stack pointer using the backchain. Otherwise,
14589 we know what size to update it with. */
14590 if (use_backchain_to_restore_sp)
14592 /* Under V.4, don't reset the stack pointer until after we're done
14593 loading the saved registers. */
14594 if (DEFAULT_ABI == ABI_V4)
14595 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14597 emit_move_insn (frame_reg_rtx,
14598 gen_rtx_MEM (Pmode, sp_reg_rtx));
14601 else if (info->push_p)
14603 if (DEFAULT_ABI == ABI_V4
14604 || current_function_calls_eh_return)
14605 sp_offset = info->total_size;
14608 emit_insn (TARGET_32BIT
14609 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14610 GEN_INT (info->total_size))
14611 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14612 GEN_INT (info->total_size)));
14616 /* Restore AltiVec registers if needed. */
14617 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14621 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14622 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14624 rtx addr, areg, mem;
14626 areg = gen_rtx_REG (Pmode, 0);
14628 (areg, GEN_INT (info->altivec_save_offset
14630 + 16 * (i - info->first_altivec_reg_save)));
14632 /* AltiVec addressing mode is [reg+reg]. */
14633 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14634 mem = gen_rtx_MEM (V4SImode, addr);
14635 set_mem_alias_set (mem, rs6000_sr_alias_set);
14637 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14641 /* Restore VRSAVE if needed. */
14642 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14643 && info->vrsave_mask != 0)
14645 rtx addr, mem, reg;
14647 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14648 GEN_INT (info->vrsave_save_offset + sp_offset));
14649 mem = gen_rtx_MEM (SImode, addr);
14650 set_mem_alias_set (mem, rs6000_sr_alias_set);
14651 reg = gen_rtx_REG (SImode, 12);
14652 emit_move_insn (reg, mem);
14654 emit_insn (generate_set_vrsave (reg, info, 1));
14657 /* Get the old lr if we saved it. */
14658 if (info->lr_save_p)
14660 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14661 info->lr_save_offset + sp_offset);
14663 set_mem_alias_set (mem, rs6000_sr_alias_set);
14665 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14668 /* Get the old cr if we saved it. */
14669 if (info->cr_save_p)
14671 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14672 GEN_INT (info->cr_save_offset + sp_offset));
14673 rtx mem = gen_rtx_MEM (SImode, addr);
14675 set_mem_alias_set (mem, rs6000_sr_alias_set);
14677 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14680 /* Set LR here to try to overlap restores below. */
14681 if (info->lr_save_p)
14682 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14683 gen_rtx_REG (Pmode, 0));
14685 /* Load exception handler data registers, if needed. */
14686 if (current_function_calls_eh_return)
14688 unsigned int i, regno;
14692 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14693 GEN_INT (sp_offset + 5 * reg_size));
14694 rtx mem = gen_rtx_MEM (reg_mode, addr);
14696 set_mem_alias_set (mem, rs6000_sr_alias_set);
14698 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14705 regno = EH_RETURN_DATA_REGNO (i);
14706 if (regno == INVALID_REGNUM)
14709 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14710 info->ehrd_offset + sp_offset
14711 + reg_size * (int) i);
14712 set_mem_alias_set (mem, rs6000_sr_alias_set);
14714 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14718 /* Restore GPRs. This is done as a PARALLEL if we are using
14719 the load-multiple instructions. */
14720 if (using_load_multiple)
14723 p = rtvec_alloc (32 - info->first_gp_reg_save);
14724 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14726 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14727 GEN_INT (info->gp_save_offset
14730 rtx mem = gen_rtx_MEM (reg_mode, addr);
14732 set_mem_alias_set (mem, rs6000_sr_alias_set);
14735 gen_rtx_SET (VOIDmode,
14736 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14739 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14742 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14743 if ((regs_ever_live[info->first_gp_reg_save+i]
14744 && (! call_used_regs[info->first_gp_reg_save+i]
14745 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14746 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14747 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14748 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14749 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14751 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14752 GEN_INT (info->gp_save_offset
14755 rtx mem = gen_rtx_MEM (reg_mode, addr);
14757 /* Restore 64-bit quantities for SPE. */
14758 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14760 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14763 if (!SPE_CONST_OFFSET_OK (offset))
14765 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14766 emit_move_insn (b, GEN_INT (offset));
14769 b = GEN_INT (offset);
14771 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14772 mem = gen_rtx_MEM (V2SImode, addr);
14775 set_mem_alias_set (mem, rs6000_sr_alias_set);
14777 emit_move_insn (gen_rtx_REG (reg_mode,
14778 info->first_gp_reg_save + i), mem);
14781 /* Restore fpr's if we need to do it without calling a function. */
14782 if (restoring_FPRs_inline)
14783 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14784 if ((regs_ever_live[info->first_fp_reg_save+i]
14785 && ! call_used_regs[info->first_fp_reg_save+i]))
14788 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14789 GEN_INT (info->fp_save_offset
14792 mem = gen_rtx_MEM (DFmode, addr);
14793 set_mem_alias_set (mem, rs6000_sr_alias_set);
14795 emit_move_insn (gen_rtx_REG (DFmode,
14796 info->first_fp_reg_save + i),
14800 /* If we saved cr, restore it here. Just those that were used. */
14801 if (info->cr_save_p)
14803 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14806 if (using_mfcr_multiple)
14808 for (i = 0; i < 8; i++)
14809 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14815 if (using_mfcr_multiple && count > 1)
14820 p = rtvec_alloc (count);
14823 for (i = 0; i < 8; i++)
14824 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14826 rtvec r = rtvec_alloc (2);
14827 RTVEC_ELT (r, 0) = r12_rtx;
14828 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14829 RTVEC_ELT (p, ndx) =
14830 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14831 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14834 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14839 for (i = 0; i < 8; i++)
14840 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14842 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14848 /* If this is V.4, unwind the stack pointer after all of the loads
14849 have been done. We need to emit a block here so that sched
14850 doesn't decide to move the sp change before the register restores
14851 (which may not have any obvious dependency on the stack). This
14852 doesn't hurt performance, because there is no scheduling that can
14853 be done after this point. */
14854 if (DEFAULT_ABI == ABI_V4
14855 || current_function_calls_eh_return)
14857 if (frame_reg_rtx != sp_reg_rtx)
14858 rs6000_emit_stack_tie ();
14860 if (use_backchain_to_restore_sp)
14862 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14864 else if (sp_offset != 0)
14866 emit_insn (TARGET_32BIT
14867 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14868 GEN_INT (sp_offset))
14869 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14870 GEN_INT (sp_offset)));
14874 if (current_function_calls_eh_return)
14876 rtx sa = EH_RETURN_STACKADJ_RTX;
14877 emit_insn (TARGET_32BIT
14878 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14879 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14885 if (! restoring_FPRs_inline)
14886 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14888 p = rtvec_alloc (2);
14890 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
14891 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14892 gen_rtx_REG (Pmode,
14893 LINK_REGISTER_REGNUM));
14895 /* If we have to restore more than two FP registers, branch to the
14896 restore function. It will return to our caller. */
14897 if (! restoring_FPRs_inline)
14901 const char *alloc_rname;
14903 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
14904 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
14905 alloc_rname = ggc_strdup (rname);
14906 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
14907 gen_rtx_SYMBOL_REF (Pmode,
14910 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14913 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
14914 GEN_INT (info->fp_save_offset + 8*i));
14915 mem = gen_rtx_MEM (DFmode, addr);
14916 set_mem_alias_set (mem, rs6000_sr_alias_set);
14918 RTVEC_ELT (p, i+3) =
14919 gen_rtx_SET (VOIDmode,
14920 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
14925 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14929 /* Write function epilogue. */
14932 rs6000_output_function_epilogue (FILE *file,
14933 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14935 rs6000_stack_t *info = rs6000_stack_info ();
14937 if (! HAVE_epilogue)
14939 rtx insn = get_last_insn ();
14940 /* If the last insn was a BARRIER, we don't have to write anything except
14941 the trace table. */
14942 if (GET_CODE (insn) == NOTE)
14943 insn = prev_nonnote_insn (insn);
14944 if (insn == 0 || GET_CODE (insn) != BARRIER)
14946 /* This is slightly ugly, but at least we don't have two
14947 copies of the epilogue-emitting code. */
14950 /* A NOTE_INSN_DELETED is supposed to be at the start
14951 and end of the "toplevel" insn chain. */
14952 emit_note (NOTE_INSN_DELETED);
14953 rs6000_emit_epilogue (FALSE);
14954 emit_note (NOTE_INSN_DELETED);
14956 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14960 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14962 INSN_ADDRESSES_NEW (insn, addr);
14967 if (TARGET_DEBUG_STACK)
14968 debug_rtx_list (get_insns (), 100);
14969 final (get_insns (), file, FALSE, FALSE);
14975 macho_branch_islands ();
14976 /* Mach-O doesn't support labels at the end of objects, so if
14977 it looks like we might want one, insert a NOP. */
14979 rtx insn = get_last_insn ();
14982 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
14983 insn = PREV_INSN (insn);
14987 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
14988 fputs ("\tnop\n", file);
14992 /* Output a traceback table here. See /usr/include/sys/debug.h for info
14995 We don't output a traceback table if -finhibit-size-directive was
14996 used. The documentation for -finhibit-size-directive reads
14997 ``don't output a @code{.size} assembler directive, or anything
14998 else that would cause trouble if the function is split in the
14999 middle, and the two halves are placed at locations far apart in
15000 memory.'' The traceback table has this property, since it
15001 includes the offset from the start of the function to the
15002 traceback table itself.
15004 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15005 different traceback table. */
15006 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15007 && rs6000_traceback != traceback_none)
15009 const char *fname = NULL;
15010 const char *language_string = lang_hooks.name;
15011 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15013 int optional_tbtab;
15015 if (rs6000_traceback == traceback_full)
15016 optional_tbtab = 1;
15017 else if (rs6000_traceback == traceback_part)
15018 optional_tbtab = 0;
15020 optional_tbtab = !optimize_size && !TARGET_ELF;
15022 if (optional_tbtab)
15024 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15025 while (*fname == '.') /* V.4 encodes . in the name */
15028 /* Need label immediately before tbtab, so we can compute
15029 its offset from the function start. */
15030 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15031 ASM_OUTPUT_LABEL (file, fname);
15034 /* The .tbtab pseudo-op can only be used for the first eight
15035 expressions, since it can't handle the possibly variable
15036 length fields that follow. However, if you omit the optional
15037 fields, the assembler outputs zeros for all optional fields
15038 anyways, giving each variable length field is minimum length
15039 (as defined in sys/debug.h). Thus we can not use the .tbtab
15040 pseudo-op at all. */
15042 /* An all-zero word flags the start of the tbtab, for debuggers
15043 that have to find it by searching forward from the entry
15044 point or from the current pc. */
15045 fputs ("\t.long 0\n", file);
15047 /* Tbtab format type. Use format type 0. */
15048 fputs ("\t.byte 0,", file);
15050 /* Language type. Unfortunately, there does not seem to be any
15051 official way to discover the language being compiled, so we
15052 use language_string.
15053 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15054 Java is 13. Objective-C is 14. */
15055 if (! strcmp (language_string, "GNU C"))
15057 else if (! strcmp (language_string, "GNU F77")
15058 || ! strcmp (language_string, "GNU F95"))
15060 else if (! strcmp (language_string, "GNU Pascal"))
15062 else if (! strcmp (language_string, "GNU Ada"))
15064 else if (! strcmp (language_string, "GNU C++"))
15066 else if (! strcmp (language_string, "GNU Java"))
15068 else if (! strcmp (language_string, "GNU Objective-C"))
15072 fprintf (file, "%d,", i);
15074 /* 8 single bit fields: global linkage (not set for C extern linkage,
15075 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15076 from start of procedure stored in tbtab, internal function, function
15077 has controlled storage, function has no toc, function uses fp,
15078 function logs/aborts fp operations. */
15079 /* Assume that fp operations are used if any fp reg must be saved. */
15080 fprintf (file, "%d,",
15081 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15083 /* 6 bitfields: function is interrupt handler, name present in
15084 proc table, function calls alloca, on condition directives
15085 (controls stack walks, 3 bits), saves condition reg, saves
15087 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15088 set up as a frame pointer, even when there is no alloca call. */
15089 fprintf (file, "%d,",
15090 ((optional_tbtab << 6)
15091 | ((optional_tbtab & frame_pointer_needed) << 5)
15092 | (info->cr_save_p << 1)
15093 | (info->lr_save_p)));
15095 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15097 fprintf (file, "%d,",
15098 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15100 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15101 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15103 if (optional_tbtab)
15105 /* Compute the parameter info from the function decl argument
15108 int next_parm_info_bit = 31;
15110 for (decl = DECL_ARGUMENTS (current_function_decl);
15111 decl; decl = TREE_CHAIN (decl))
15113 rtx parameter = DECL_INCOMING_RTL (decl);
15114 enum machine_mode mode = GET_MODE (parameter);
15116 if (GET_CODE (parameter) == REG)
15118 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15124 if (mode == SFmode)
15126 else if (mode == DFmode || mode == TFmode)
15131 /* If only one bit will fit, don't or in this entry. */
15132 if (next_parm_info_bit > 0)
15133 parm_info |= (bits << (next_parm_info_bit - 1));
15134 next_parm_info_bit -= 2;
15138 fixed_parms += ((GET_MODE_SIZE (mode)
15139 + (UNITS_PER_WORD - 1))
15141 next_parm_info_bit -= 1;
15147 /* Number of fixed point parameters. */
15148 /* This is actually the number of words of fixed point parameters; thus
15149 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15150 fprintf (file, "%d,", fixed_parms);
15152 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15154 /* This is actually the number of fp registers that hold parameters;
15155 and thus the maximum value is 13. */
15156 /* Set parameters on stack bit if parameters are not in their original
15157 registers, regardless of whether they are on the stack? Xlc
15158 seems to set the bit when not optimizing. */
15159 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15161 if (! optional_tbtab)
15164 /* Optional fields follow. Some are variable length. */
15166 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15167 11 double float. */
15168 /* There is an entry for each parameter in a register, in the order that
15169 they occur in the parameter list. Any intervening arguments on the
15170 stack are ignored. If the list overflows a long (max possible length
15171 34 bits) then completely leave off all elements that don't fit. */
15172 /* Only emit this long if there was at least one parameter. */
15173 if (fixed_parms || float_parms)
15174 fprintf (file, "\t.long %d\n", parm_info);
15176 /* Offset from start of code to tb table. */
15177 fputs ("\t.long ", file);
15178 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15180 RS6000_OUTPUT_BASENAME (file, fname);
15182 assemble_name (file, fname);
15184 rs6000_output_function_entry (file, fname);
15187 /* Interrupt handler mask. */
15188 /* Omit this long, since we never set the interrupt handler bit
15191 /* Number of CTL (controlled storage) anchors. */
15192 /* Omit this long, since the has_ctl bit is never set above. */
15194 /* Displacement into stack of each CTL anchor. */
15195 /* Omit this list of longs, because there are no CTL anchors. */
15197 /* Length of function name. */
15200 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15202 /* Function name. */
15203 assemble_string (fname, strlen (fname));
15205 /* Register for alloca automatic storage; this is always reg 31.
15206 Only emit this if the alloca bit was set above. */
15207 if (frame_pointer_needed)
15208 fputs ("\t.byte 31\n", file);
15210 fputs ("\t.align 2\n", file);
15214 /* A C compound statement that outputs the assembler code for a thunk
15215 function, used to implement C++ virtual function calls with
15216 multiple inheritance. The thunk acts as a wrapper around a virtual
15217 function, adjusting the implicit object parameter before handing
15218 control off to the real function.
15220 First, emit code to add the integer DELTA to the location that
15221 contains the incoming first argument. Assume that this argument
15222 contains a pointer, and is the one used to pass the `this' pointer
15223 in C++. This is the incoming argument *before* the function
15224 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15225 values of all other incoming arguments.
15227 After the addition, emit code to jump to FUNCTION, which is a
15228 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15229 not touch the return address. Hence returning from FUNCTION will
15230 return to whoever called the current `thunk'.
15232 The effect must be as if FUNCTION had been called directly with the
15233 adjusted first argument. This macro is responsible for emitting
15234 all of the code for a thunk function; output_function_prologue()
15235 and output_function_epilogue() are not invoked.
15237 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15238 been extracted from it.) It might possibly be useful on some
15239 targets, but probably not.
15241 If you do not define this macro, the target-independent code in the
15242 C++ frontend will generate a less efficient heavyweight thunk that
15243 calls FUNCTION instead of jumping to it. The generic approach does
15244 not support varargs. */
15247 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15248 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15251 rtx this, insn, funexp;
15253 reload_completed = 1;
15254 epilogue_completed = 1;
15255 no_new_pseudos = 1;
15256 reset_block_changes ();
15258 /* Mark the end of the (empty) prologue. */
15259 emit_note (NOTE_INSN_PROLOGUE_END);
15261 /* Find the "this" pointer. If the function returns a structure,
15262 the structure return pointer is in r3. */
15263 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15264 this = gen_rtx_REG (Pmode, 4);
15266 this = gen_rtx_REG (Pmode, 3);
15268 /* Apply the constant offset, if required. */
15271 rtx delta_rtx = GEN_INT (delta);
15272 emit_insn (TARGET_32BIT
15273 ? gen_addsi3 (this, this, delta_rtx)
15274 : gen_adddi3 (this, this, delta_rtx));
15277 /* Apply the offset from the vtable, if required. */
15280 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15281 rtx tmp = gen_rtx_REG (Pmode, 12);
15283 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15284 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15286 emit_insn (TARGET_32BIT
15287 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15288 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15289 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15293 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15295 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15297 emit_insn (TARGET_32BIT
15298 ? gen_addsi3 (this, this, tmp)
15299 : gen_adddi3 (this, this, tmp));
15302 /* Generate a tail call to the target function. */
15303 if (!TREE_USED (function))
15305 assemble_external (function);
15306 TREE_USED (function) = 1;
15308 funexp = XEXP (DECL_RTL (function), 0);
15309 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15312 if (MACHOPIC_INDIRECT)
15313 funexp = machopic_indirect_call_target (funexp);
15316 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15317 generate sibcall RTL explicitly to avoid constraint abort. */
15318 insn = emit_call_insn (
15319 gen_rtx_PARALLEL (VOIDmode,
15321 gen_rtx_CALL (VOIDmode,
15322 funexp, const0_rtx),
15323 gen_rtx_USE (VOIDmode, const0_rtx),
15324 gen_rtx_USE (VOIDmode,
15325 gen_rtx_REG (SImode,
15326 LINK_REGISTER_REGNUM)),
15327 gen_rtx_RETURN (VOIDmode))));
15328 SIBLING_CALL_P (insn) = 1;
15331 /* Run just enough of rest_of_compilation to get the insns emitted.
15332 There's not really enough bulk here to make other passes such as
15333 instruction scheduling worth while. Note that use_thunk calls
15334 assemble_start_function and assemble_end_function. */
15335 insn = get_insns ();
15336 insn_locators_initialize ();
15337 shorten_branches (insn);
15338 final_start_function (insn, file, 1);
15339 final (insn, file, 1, 0);
15340 final_end_function ();
15342 reload_completed = 0;
15343 epilogue_completed = 0;
15344 no_new_pseudos = 0;
15347 /* A quick summary of the various types of 'constant-pool tables'
15350 Target Flags Name One table per
15351 AIX (none) AIX TOC object file
15352 AIX -mfull-toc AIX TOC object file
15353 AIX -mminimal-toc AIX minimal TOC translation unit
15354 SVR4/EABI (none) SVR4 SDATA object file
15355 SVR4/EABI -fpic SVR4 pic object file
15356 SVR4/EABI -fPIC SVR4 PIC translation unit
15357 SVR4/EABI -mrelocatable EABI TOC function
15358 SVR4/EABI -maix AIX TOC object file
15359 SVR4/EABI -maix -mminimal-toc
15360 AIX minimal TOC translation unit
15362 Name Reg. Set by entries contains:
15363 made by addrs? fp? sum?
15365 AIX TOC 2 crt0 as Y option option
15366 AIX minimal TOC 30 prolog gcc Y Y option
15367 SVR4 SDATA 13 crt0 gcc N Y N
15368 SVR4 pic 30 prolog ld Y not yet N
15369 SVR4 PIC 30 prolog gcc Y option option
15370 EABI TOC 30 prolog gcc Y option option
15374 /* Hash functions for the hash table. */
15377 rs6000_hash_constant (rtx k)
15379 enum rtx_code code = GET_CODE (k);
15380 enum machine_mode mode = GET_MODE (k);
15381 unsigned result = (code << 3) ^ mode;
15382 const char *format;
15385 format = GET_RTX_FORMAT (code);
15386 flen = strlen (format);
15392 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15395 if (mode != VOIDmode)
15396 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15408 for (; fidx < flen; fidx++)
15409 switch (format[fidx])
15414 const char *str = XSTR (k, fidx);
15415 len = strlen (str);
15416 result = result * 613 + len;
15417 for (i = 0; i < len; i++)
15418 result = result * 613 + (unsigned) str[i];
15423 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15427 result = result * 613 + (unsigned) XINT (k, fidx);
15430 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15431 result = result * 613 + (unsigned) XWINT (k, fidx);
15435 for (i = 0; i < sizeof(HOST_WIDE_INT)/sizeof(unsigned); i++)
15436 result = result * 613 + (unsigned) (XWINT (k, fidx)
15450 toc_hash_function (const void *hash_entry)
15452 const struct toc_hash_struct *thc =
15453 (const struct toc_hash_struct *) hash_entry;
15454 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15457 /* Compare H1 and H2 for equivalence. */
15460 toc_hash_eq (const void *h1, const void *h2)
15462 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15463 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15465 if (((const struct toc_hash_struct *) h1)->key_mode
15466 != ((const struct toc_hash_struct *) h2)->key_mode)
15469 return rtx_equal_p (r1, r2);
15472 /* These are the names given by the C++ front-end to vtables, and
15473 vtable-like objects. Ideally, this logic should not be here;
15474 instead, there should be some programmatic way of inquiring as
15475 to whether or not an object is a vtable. */
15477 #define VTABLE_NAME_P(NAME) \
15478 (strncmp ("_vt.", name, strlen("_vt.")) == 0 \
15479 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15480 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15481 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15482 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15485 rs6000_output_symbol_ref (FILE *file, rtx x)
15487 /* Currently C++ toc references to vtables can be emitted before it
15488 is decided whether the vtable is public or private. If this is
15489 the case, then the linker will eventually complain that there is
15490 a reference to an unknown section. Thus, for vtables only,
15491 we emit the TOC reference to reference the symbol and not the
15493 const char *name = XSTR (x, 0);
15495 if (VTABLE_NAME_P (name))
15497 RS6000_OUTPUT_BASENAME (file, name);
15500 assemble_name (file, name);
15503 /* Output a TOC entry. We derive the entry name from what is being
15507 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15510 const char *name = buf;
15511 const char *real_name;
15518 /* When the linker won't eliminate them, don't output duplicate
15519 TOC entries (this happens on AIX if there is any kind of TOC,
15520 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15522 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15524 struct toc_hash_struct *h;
15527 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15528 time because GGC is not initialized at that point. */
15529 if (toc_hash_table == NULL)
15530 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15531 toc_hash_eq, NULL);
15533 h = ggc_alloc (sizeof (*h));
15535 h->key_mode = mode;
15536 h->labelno = labelno;
15538 found = htab_find_slot (toc_hash_table, h, 1);
15539 if (*found == NULL)
15541 else /* This is indeed a duplicate.
15542 Set this label equal to that label. */
15544 fputs ("\t.set ", file);
15545 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15546 fprintf (file, "%d,", labelno);
15547 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15548 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15554 /* If we're going to put a double constant in the TOC, make sure it's
15555 aligned properly when strict alignment is on. */
15556 if (GET_CODE (x) == CONST_DOUBLE
15557 && STRICT_ALIGNMENT
15558 && GET_MODE_BITSIZE (mode) >= 64
15559 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15560 ASM_OUTPUT_ALIGN (file, 3);
15563 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15565 /* Handle FP constants specially. Note that if we have a minimal
15566 TOC, things we put here aren't actually in the TOC, so we can allow
15568 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15570 REAL_VALUE_TYPE rv;
15573 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15574 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15578 if (TARGET_MINIMAL_TOC)
15579 fputs (DOUBLE_INT_ASM_OP, file);
15581 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15582 k[0] & 0xffffffff, k[1] & 0xffffffff,
15583 k[2] & 0xffffffff, k[3] & 0xffffffff);
15584 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15585 k[0] & 0xffffffff, k[1] & 0xffffffff,
15586 k[2] & 0xffffffff, k[3] & 0xffffffff);
15591 if (TARGET_MINIMAL_TOC)
15592 fputs ("\t.long ", file);
15594 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15595 k[0] & 0xffffffff, k[1] & 0xffffffff,
15596 k[2] & 0xffffffff, k[3] & 0xffffffff);
15597 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15598 k[0] & 0xffffffff, k[1] & 0xffffffff,
15599 k[2] & 0xffffffff, k[3] & 0xffffffff);
15603 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15605 REAL_VALUE_TYPE rv;
15608 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15609 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15613 if (TARGET_MINIMAL_TOC)
15614 fputs (DOUBLE_INT_ASM_OP, file);
15616 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15617 k[0] & 0xffffffff, k[1] & 0xffffffff);
15618 fprintf (file, "0x%lx%08lx\n",
15619 k[0] & 0xffffffff, k[1] & 0xffffffff);
15624 if (TARGET_MINIMAL_TOC)
15625 fputs ("\t.long ", file);
15627 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15628 k[0] & 0xffffffff, k[1] & 0xffffffff);
15629 fprintf (file, "0x%lx,0x%lx\n",
15630 k[0] & 0xffffffff, k[1] & 0xffffffff);
15634 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15636 REAL_VALUE_TYPE rv;
15639 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15640 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15644 if (TARGET_MINIMAL_TOC)
15645 fputs (DOUBLE_INT_ASM_OP, file);
15647 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15648 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15653 if (TARGET_MINIMAL_TOC)
15654 fputs ("\t.long ", file);
15656 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15657 fprintf (file, "0x%lx\n", l & 0xffffffff);
15661 else if (GET_MODE (x) == VOIDmode
15662 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15664 unsigned HOST_WIDE_INT low;
15665 HOST_WIDE_INT high;
15667 if (GET_CODE (x) == CONST_DOUBLE)
15669 low = CONST_DOUBLE_LOW (x);
15670 high = CONST_DOUBLE_HIGH (x);
15673 #if HOST_BITS_PER_WIDE_INT == 32
15676 high = (low & 0x80000000) ? ~0 : 0;
15680 low = INTVAL (x) & 0xffffffff;
15681 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15685 /* TOC entries are always Pmode-sized, but since this
15686 is a bigendian machine then if we're putting smaller
15687 integer constants in the TOC we have to pad them.
15688 (This is still a win over putting the constants in
15689 a separate constant pool, because then we'd have
15690 to have both a TOC entry _and_ the actual constant.)
15692 For a 32-bit target, CONST_INT values are loaded and shifted
15693 entirely within `low' and can be stored in one TOC entry. */
15695 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
15696 abort ();/* It would be easy to make this work, but it doesn't now. */
15698 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15700 #if HOST_BITS_PER_WIDE_INT == 32
15701 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15702 POINTER_SIZE, &low, &high, 0);
15705 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15706 high = (HOST_WIDE_INT) low >> 32;
15713 if (TARGET_MINIMAL_TOC)
15714 fputs (DOUBLE_INT_ASM_OP, file);
15716 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15717 (long) high & 0xffffffff, (long) low & 0xffffffff);
15718 fprintf (file, "0x%lx%08lx\n",
15719 (long) high & 0xffffffff, (long) low & 0xffffffff);
15724 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15726 if (TARGET_MINIMAL_TOC)
15727 fputs ("\t.long ", file);
15729 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15730 (long) high & 0xffffffff, (long) low & 0xffffffff);
15731 fprintf (file, "0x%lx,0x%lx\n",
15732 (long) high & 0xffffffff, (long) low & 0xffffffff);
15736 if (TARGET_MINIMAL_TOC)
15737 fputs ("\t.long ", file);
15739 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15740 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15746 if (GET_CODE (x) == CONST)
15748 if (GET_CODE (XEXP (x, 0)) != PLUS)
15751 base = XEXP (XEXP (x, 0), 0);
15752 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15755 if (GET_CODE (base) == SYMBOL_REF)
15756 name = XSTR (base, 0);
15757 else if (GET_CODE (base) == LABEL_REF)
15758 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
15759 else if (GET_CODE (base) == CODE_LABEL)
15760 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15764 real_name = (*targetm.strip_name_encoding) (name);
15765 if (TARGET_MINIMAL_TOC)
15766 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15769 fprintf (file, "\t.tc %s", real_name);
15772 fprintf (file, ".N%d", - offset);
15774 fprintf (file, ".P%d", offset);
15776 fputs ("[TC],", file);
15779 /* Currently C++ toc references to vtables can be emitted before it
15780 is decided whether the vtable is public or private. If this is
15781 the case, then the linker will eventually complain that there is
15782 a TOC reference to an unknown section. Thus, for vtables only,
15783 we emit the TOC reference to reference the symbol and not the
15785 if (VTABLE_NAME_P (name))
15787 RS6000_OUTPUT_BASENAME (file, name);
15789 fprintf (file, "%d", offset);
15790 else if (offset > 0)
15791 fprintf (file, "+%d", offset);
15794 output_addr_const (file, x);
15798 /* Output an assembler pseudo-op to write an ASCII string of N characters
15799 starting at P to FILE.
15801 On the RS/6000, we have to do this using the .byte operation and
15802 write out special characters outside the quoted string.
15803 Also, the assembler is broken; very long strings are truncated,
15804 so we must artificially break them up early. */
15807 output_ascii (FILE *file, const char *p, int n)
15810 int i, count_string;
15811 const char *for_string = "\t.byte \"";
15812 const char *for_decimal = "\t.byte ";
15813 const char *to_close = NULL;
15816 for (i = 0; i < n; i++)
15819 if (c >= ' ' && c < 0177)
15822 fputs (for_string, file);
15825 /* Write two quotes to get one. */
15833 for_decimal = "\"\n\t.byte ";
15837 if (count_string >= 512)
15839 fputs (to_close, file);
15841 for_string = "\t.byte \"";
15842 for_decimal = "\t.byte ";
15850 fputs (for_decimal, file);
15851 fprintf (file, "%d", c);
15853 for_string = "\n\t.byte \"";
15854 for_decimal = ", ";
15860 /* Now close the string if we have written one. Then end the line. */
15862 fputs (to_close, file);
15865 /* Generate a unique section name for FILENAME for a section type
15866 represented by SECTION_DESC. Output goes into BUF.
15868 SECTION_DESC can be any string, as long as it is different for each
15869 possible section type.
15871 We name the section in the same manner as xlc. The name begins with an
15872 underscore followed by the filename (after stripping any leading directory
15873 names) with the last period replaced by the string SECTION_DESC. If
15874 FILENAME does not contain a period, SECTION_DESC is appended to the end of
15878 rs6000_gen_section_name (char **buf, const char *filename,
15879 const char *section_desc)
15881 const char *q, *after_last_slash, *last_period = 0;
15885 after_last_slash = filename;
15886 for (q = filename; *q; q++)
15889 after_last_slash = q + 1;
15890 else if (*q == '.')
15894 len = strlen (after_last_slash) + strlen (section_desc) + 2;
15895 *buf = (char *) xmalloc (len);
15900 for (q = after_last_slash; *q; q++)
15902 if (q == last_period)
15904 strcpy (p, section_desc);
15905 p += strlen (section_desc);
15909 else if (ISALNUM (*q))
15913 if (last_period == 0)
15914 strcpy (p, section_desc);
15919 /* Emit profile function. */
15922 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
15924 if (TARGET_PROFILE_KERNEL)
15927 if (DEFAULT_ABI == ABI_AIX)
15929 #ifndef NO_PROFILE_COUNTERS
15930 # define NO_PROFILE_COUNTERS 0
15932 if (NO_PROFILE_COUNTERS)
15933 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
15937 const char *label_name;
15940 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15941 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
15942 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
15944 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
15948 else if (DEFAULT_ABI == ABI_DARWIN)
15950 const char *mcount_name = RS6000_MCOUNT;
15951 int caller_addr_regno = LINK_REGISTER_REGNUM;
15953 /* Be conservative and always set this, at least for now. */
15954 current_function_uses_pic_offset_table = 1;
15957 /* For PIC code, set up a stub and collect the caller's address
15958 from r0, which is where the prologue puts it. */
15959 if (MACHOPIC_INDIRECT
15960 && current_function_uses_pic_offset_table)
15961 caller_addr_regno = 0;
15963 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
15965 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
15969 /* Write function profiler code. */
15972 output_function_profiler (FILE *file, int labelno)
15977 switch (DEFAULT_ABI)
15986 warning ("no profiling of 64-bit code for this ABI");
15989 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
15990 fprintf (file, "\tmflr %s\n", reg_names[0]);
15993 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
15994 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
15995 reg_names[0], save_lr, reg_names[1]);
15996 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
15997 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
15998 assemble_name (file, buf);
15999 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16001 else if (flag_pic > 1)
16003 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
16004 reg_names[0], save_lr, reg_names[1]);
16005 /* Now, we need to get the address of the label. */
16006 fputs ("\tbl 1f\n\t.long ", file);
16007 assemble_name (file, buf);
16008 fputs ("-.\n1:", file);
16009 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16010 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16011 reg_names[0], reg_names[11]);
16012 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16013 reg_names[0], reg_names[0], reg_names[11]);
16017 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16018 assemble_name (file, buf);
16019 fputs ("@ha\n", file);
16020 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
16021 reg_names[0], save_lr, reg_names[1]);
16022 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16023 assemble_name (file, buf);
16024 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16027 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16028 fprintf (file, "\tbl %s%s\n",
16029 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16034 if (!TARGET_PROFILE_KERNEL)
16036 /* Don't do anything, done in output_profile_hook (). */
16043 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16044 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16046 if (cfun->static_chain_decl != NULL)
16048 asm_fprintf (file, "\tstd %s,24(%s)\n",
16049 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16050 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16051 asm_fprintf (file, "\tld %s,24(%s)\n",
16052 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16055 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16062 /* Power4 load update and store update instructions are cracked into a
16063 load or store and an integer insn which are executed in the same cycle.
16064 Branches have their own dispatch slot which does not count against the
16065 GCC issue rate, but it changes the program flow so there are no other
16066 instructions to issue in this cycle. */
16069 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16070 int verbose ATTRIBUTE_UNUSED,
16071 rtx insn, int more)
16073 if (GET_CODE (PATTERN (insn)) == USE
16074 || GET_CODE (PATTERN (insn)) == CLOBBER)
16077 if (rs6000_sched_groups)
16079 if (is_microcoded_insn (insn))
16081 else if (is_cracked_insn (insn))
16082 return more > 2 ? more - 2 : 0;
16088 /* Adjust the cost of a scheduling dependency. Return the new cost of
16089 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16092 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16094 if (! recog_memoized (insn))
16097 if (REG_NOTE_KIND (link) != 0)
16100 if (REG_NOTE_KIND (link) == 0)
16102 /* Data dependency; DEP_INSN writes a register that INSN reads
16103 some cycles later. */
16105 /* Separate a load from a narrower, dependent store. */
16106 if (rs6000_sched_groups
16107 && GET_CODE (PATTERN (insn)) == SET
16108 && GET_CODE (PATTERN (dep_insn)) == SET
16109 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16110 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16111 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16112 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16115 switch (get_attr_type (insn))
16118 /* Tell the first scheduling pass about the latency between
16119 a mtctr and bctr (and mtlr and br/blr). The first
16120 scheduling pass will not know about this latency since
16121 the mtctr instruction, which has the latency associated
16122 to it, will be generated by reload. */
16123 return TARGET_POWER ? 5 : 4;
16125 /* Leave some extra cycles between a compare and its
16126 dependent branch, to inhibit expensive mispredicts. */
16127 if ((rs6000_cpu_attr == CPU_PPC603
16128 || rs6000_cpu_attr == CPU_PPC604
16129 || rs6000_cpu_attr == CPU_PPC604E
16130 || rs6000_cpu_attr == CPU_PPC620
16131 || rs6000_cpu_attr == CPU_PPC630
16132 || rs6000_cpu_attr == CPU_PPC750
16133 || rs6000_cpu_attr == CPU_PPC7400
16134 || rs6000_cpu_attr == CPU_PPC7450
16135 || rs6000_cpu_attr == CPU_POWER4
16136 || rs6000_cpu_attr == CPU_POWER5)
16137 && recog_memoized (dep_insn)
16138 && (INSN_CODE (dep_insn) >= 0)
16139 && (get_attr_type (dep_insn) == TYPE_CMP
16140 || get_attr_type (dep_insn) == TYPE_COMPARE
16141 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16142 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16143 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16144 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16145 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16146 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16151 /* Fall out to return default cost. */
16157 /* The function returns a true if INSN is microcoded.
16158 Return false otherwise. */
16161 is_microcoded_insn (rtx insn)
16163 if (!insn || !INSN_P (insn)
16164 || GET_CODE (PATTERN (insn)) == USE
16165 || GET_CODE (PATTERN (insn)) == CLOBBER)
16168 if (rs6000_sched_groups)
16170 enum attr_type type = get_attr_type (insn);
16171 if (type == TYPE_LOAD_EXT_U
16172 || type == TYPE_LOAD_EXT_UX
16173 || type == TYPE_LOAD_UX
16174 || type == TYPE_STORE_UX
16175 || type == TYPE_MFCR)
16182 /* The function returns a nonzero value if INSN can be scheduled only
16183 as the first insn in a dispatch group ("dispatch-slot restricted").
16184 In this case, the returned value indicates how many dispatch slots
16185 the insn occupies (at the beginning of the group).
16186 Return 0 otherwise. */
16189 is_dispatch_slot_restricted (rtx insn)
16191 enum attr_type type;
16193 if (!rs6000_sched_groups)
16197 || insn == NULL_RTX
16198 || GET_CODE (insn) == NOTE
16199 || GET_CODE (PATTERN (insn)) == USE
16200 || GET_CODE (PATTERN (insn)) == CLOBBER)
16203 type = get_attr_type (insn);
16210 case TYPE_DELAYED_CR:
16211 case TYPE_CR_LOGICAL:
16219 if (rs6000_cpu == PROCESSOR_POWER5
16220 && is_cracked_insn (insn))
16226 /* The function returns true if INSN is cracked into 2 instructions
16227 by the processor (and therefore occupies 2 issue slots). */
16230 is_cracked_insn (rtx insn)
16232 if (!insn || !INSN_P (insn)
16233 || GET_CODE (PATTERN (insn)) == USE
16234 || GET_CODE (PATTERN (insn)) == CLOBBER)
16237 if (rs6000_sched_groups)
16239 enum attr_type type = get_attr_type (insn);
16240 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16241 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16242 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16243 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16244 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16245 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16246 || type == TYPE_IDIV || type == TYPE_LDIV
16247 || type == TYPE_INSERT_WORD)
16254 /* The function returns true if INSN can be issued only from
16255 the branch slot. */
16258 is_branch_slot_insn (rtx insn)
16260 if (!insn || !INSN_P (insn)
16261 || GET_CODE (PATTERN (insn)) == USE
16262 || GET_CODE (PATTERN (insn)) == CLOBBER)
16265 if (rs6000_sched_groups)
16267 enum attr_type type = get_attr_type (insn);
16268 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16276 /* A C statement (sans semicolon) to update the integer scheduling
16277 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16278 INSN earlier, reduce the priority to execute INSN later. Do not
16279 define this macro if you do not need to adjust the scheduling
16280 priorities of insns. */
16283 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16285 /* On machines (like the 750) which have asymmetric integer units,
16286 where one integer unit can do multiply and divides and the other
16287 can't, reduce the priority of multiply/divide so it is scheduled
16288 before other integer operations. */
16291 if (! INSN_P (insn))
16294 if (GET_CODE (PATTERN (insn)) == USE)
16297 switch (rs6000_cpu_attr) {
16299 switch (get_attr_type (insn))
16306 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16307 priority, priority);
16308 if (priority >= 0 && priority < 0x01000000)
16315 if (is_dispatch_slot_restricted (insn)
16316 && reload_completed
16317 && current_sched_info->sched_max_insns_priority
16318 && rs6000_sched_restricted_insns_priority)
16321 /* Prioritize insns that can be dispatched only in the first
16323 if (rs6000_sched_restricted_insns_priority == 1)
16324 /* Attach highest priority to insn. This means that in
16325 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16326 precede 'priority' (critical path) considerations. */
16327 return current_sched_info->sched_max_insns_priority;
16328 else if (rs6000_sched_restricted_insns_priority == 2)
16329 /* Increase priority of insn by a minimal amount. This means that in
16330 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16331 considerations precede dispatch-slot restriction considerations. */
16332 return (priority + 1);
16338 /* Return how many instructions the machine can issue per cycle. */
16341 rs6000_issue_rate (void)
16343 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16344 if (!reload_completed)
16347 switch (rs6000_cpu_attr) {
16348 case CPU_RIOS1: /* ? */
16350 case CPU_PPC601: /* ? */
16373 /* Return how many instructions to look ahead for better insn
16377 rs6000_use_sched_lookahead (void)
16379 if (rs6000_cpu_attr == CPU_PPC8540)
16384 /* Determine is PAT refers to memory. */
16387 is_mem_ref (rtx pat)
16393 if (GET_CODE (pat) == MEM)
16396 /* Recursively process the pattern. */
16397 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16399 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16402 ret |= is_mem_ref (XEXP (pat, i));
16403 else if (fmt[i] == 'E')
16404 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16405 ret |= is_mem_ref (XVECEXP (pat, i, j));
16411 /* Determine if PAT is a PATTERN of a load insn. */
16414 is_load_insn1 (rtx pat)
16416 if (!pat || pat == NULL_RTX)
16419 if (GET_CODE (pat) == SET)
16420 return is_mem_ref (SET_SRC (pat));
16422 if (GET_CODE (pat) == PARALLEL)
16426 for (i = 0; i < XVECLEN (pat, 0); i++)
16427 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16434 /* Determine if INSN loads from memory. */
16437 is_load_insn (rtx insn)
16439 if (!insn || !INSN_P (insn))
16442 if (GET_CODE (insn) == CALL_INSN)
16445 return is_load_insn1 (PATTERN (insn));
16448 /* Determine if PAT is a PATTERN of a store insn. */
16451 is_store_insn1 (rtx pat)
16453 if (!pat || pat == NULL_RTX)
16456 if (GET_CODE (pat) == SET)
16457 return is_mem_ref (SET_DEST (pat));
16459 if (GET_CODE (pat) == PARALLEL)
16463 for (i = 0; i < XVECLEN (pat, 0); i++)
16464 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16471 /* Determine if INSN stores to memory. */
16474 is_store_insn (rtx insn)
16476 if (!insn || !INSN_P (insn))
16479 return is_store_insn1 (PATTERN (insn));
16482 /* Returns whether the dependence between INSN and NEXT is considered
16483 costly by the given target. */
16486 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16489 /* If the flag is not enbled - no dependence is considered costly;
16490 allow all dependent insns in the same group.
16491 This is the most aggressive option. */
16492 if (rs6000_sched_costly_dep == no_dep_costly)
16495 /* If the flag is set to 1 - a dependence is always considered costly;
16496 do not allow dependent instructions in the same group.
16497 This is the most conservative option. */
16498 if (rs6000_sched_costly_dep == all_deps_costly)
16501 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16502 && is_load_insn (next)
16503 && is_store_insn (insn))
16504 /* Prevent load after store in the same group. */
16507 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16508 && is_load_insn (next)
16509 && is_store_insn (insn)
16510 && (!link || (int) REG_NOTE_KIND (link) == 0))
16511 /* Prevent load after store in the same group if it is a true
16515 /* The flag is set to X; dependences with latency >= X are considered costly,
16516 and will not be scheduled in the same group. */
16517 if (rs6000_sched_costly_dep <= max_dep_latency
16518 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16524 /* Return the next insn after INSN that is found before TAIL is reached,
16525 skipping any "non-active" insns - insns that will not actually occupy
16526 an issue slot. Return NULL_RTX if such an insn is not found. */
16529 get_next_active_insn (rtx insn, rtx tail)
16533 if (!insn || insn == tail)
16536 next_insn = NEXT_INSN (insn);
16539 && next_insn != tail
16540 && (GET_CODE(next_insn) == NOTE
16541 || GET_CODE (PATTERN (next_insn)) == USE
16542 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16544 next_insn = NEXT_INSN (next_insn);
16547 if (!next_insn || next_insn == tail)
16553 /* Return whether the presence of INSN causes a dispatch group termination
16554 of group WHICH_GROUP.
16556 If WHICH_GROUP == current_group, this function will return true if INSN
16557 causes the termination of the current group (i.e, the dispatch group to
16558 which INSN belongs). This means that INSN will be the last insn in the
16559 group it belongs to.
16561 If WHICH_GROUP == previous_group, this function will return true if INSN
16562 causes the termination of the previous group (i.e, the dispatch group that
16563 precedes the group to which INSN belongs). This means that INSN will be
16564 the first insn in the group it belongs to). */
16567 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16569 enum attr_type type;
16574 type = get_attr_type (insn);
16576 if (is_microcoded_insn (insn))
16579 if (which_group == current_group)
16581 if (is_branch_slot_insn (insn))
16585 else if (which_group == previous_group)
16587 if (is_dispatch_slot_restricted (insn))
16595 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16596 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16599 is_costly_group (rtx *group_insns, rtx next_insn)
16604 int issue_rate = rs6000_issue_rate ();
16606 for (i = 0; i < issue_rate; i++)
16608 rtx insn = group_insns[i];
16611 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16613 rtx next = XEXP (link, 0);
16614 if (next == next_insn)
16616 cost = insn_cost (insn, link, next_insn);
16617 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16626 /* Utility of the function redefine_groups.
16627 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16628 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16629 to keep it "far" (in a separate group) from GROUP_INSNS, following
16630 one of the following schemes, depending on the value of the flag
16631 -minsert_sched_nops = X:
16632 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16633 in order to force NEXT_INSN into a separate group.
16634 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16635 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16636 insertion (has a group just ended, how many vacant issue slots remain in the
16637 last group, and how many dispatch groups were encountered so far). */
16640 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16641 rtx next_insn, bool *group_end, int can_issue_more,
16646 int issue_rate = rs6000_issue_rate ();
16647 bool end = *group_end;
16650 if (next_insn == NULL_RTX)
16651 return can_issue_more;
16653 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16654 return can_issue_more;
16656 force = is_costly_group (group_insns, next_insn);
16658 return can_issue_more;
16660 if (sched_verbose > 6)
16661 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16662 *group_count ,can_issue_more);
16664 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16667 can_issue_more = 0;
16669 /* Since only a branch can be issued in the last issue_slot, it is
16670 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16671 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16672 in this case the last nop will start a new group and the branch
16673 will be forced to the new group. */
16674 if (can_issue_more && !is_branch_slot_insn (next_insn))
16677 while (can_issue_more > 0)
16680 emit_insn_before (nop, next_insn);
16688 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16690 int n_nops = rs6000_sched_insert_nops;
16692 /* Nops can't be issued from the branch slot, so the effective
16693 issue_rate for nops is 'issue_rate - 1'. */
16694 if (can_issue_more == 0)
16695 can_issue_more = issue_rate;
16697 if (can_issue_more == 0)
16699 can_issue_more = issue_rate - 1;
16702 for (i = 0; i < issue_rate; i++)
16704 group_insns[i] = 0;
16711 emit_insn_before (nop, next_insn);
16712 if (can_issue_more == issue_rate - 1) /* new group begins */
16715 if (can_issue_more == 0)
16717 can_issue_more = issue_rate - 1;
16720 for (i = 0; i < issue_rate; i++)
16722 group_insns[i] = 0;
16728 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16731 /* Is next_insn going to start a new group? */
16734 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16735 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16736 || (can_issue_more < issue_rate &&
16737 insn_terminates_group_p (next_insn, previous_group)));
16738 if (*group_end && end)
16741 if (sched_verbose > 6)
16742 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16743 *group_count, can_issue_more);
16744 return can_issue_more;
16747 return can_issue_more;
16750 /* This function tries to synch the dispatch groups that the compiler "sees"
16751 with the dispatch groups that the processor dispatcher is expected to
16752 form in practice. It tries to achieve this synchronization by forcing the
16753 estimated processor grouping on the compiler (as opposed to the function
16754 'pad_goups' which tries to force the scheduler's grouping on the processor).
16756 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16757 examines the (estimated) dispatch groups that will be formed by the processor
16758 dispatcher. It marks these group boundaries to reflect the estimated
16759 processor grouping, overriding the grouping that the scheduler had marked.
16760 Depending on the value of the flag '-minsert-sched-nops' this function can
16761 force certain insns into separate groups or force a certain distance between
16762 them by inserting nops, for example, if there exists a "costly dependence"
16765 The function estimates the group boundaries that the processor will form as
16766 folllows: It keeps track of how many vacant issue slots are available after
16767 each insn. A subsequent insn will start a new group if one of the following
16769 - no more vacant issue slots remain in the current dispatch group.
16770 - only the last issue slot, which is the branch slot, is vacant, but the next
16771 insn is not a branch.
16772 - only the last 2 or less issue slots, including the branch slot, are vacant,
16773 which means that a cracked insn (which occupies two issue slots) can't be
16774 issued in this group.
16775 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16776 start a new group. */
16779 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16781 rtx insn, next_insn;
16783 int can_issue_more;
16786 int group_count = 0;
16790 issue_rate = rs6000_issue_rate ();
16791 group_insns = alloca (issue_rate * sizeof (rtx));
16792 for (i = 0; i < issue_rate; i++)
16794 group_insns[i] = 0;
16796 can_issue_more = issue_rate;
16798 insn = get_next_active_insn (prev_head_insn, tail);
16801 while (insn != NULL_RTX)
16803 slot = (issue_rate - can_issue_more);
16804 group_insns[slot] = insn;
16806 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16807 if (insn_terminates_group_p (insn, current_group))
16808 can_issue_more = 0;
16810 next_insn = get_next_active_insn (insn, tail);
16811 if (next_insn == NULL_RTX)
16812 return group_count + 1;
16814 /* Is next_insn going to start a new group? */
16816 = (can_issue_more == 0
16817 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16818 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16819 || (can_issue_more < issue_rate &&
16820 insn_terminates_group_p (next_insn, previous_group)));
16822 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16823 next_insn, &group_end, can_issue_more,
16829 can_issue_more = 0;
16830 for (i = 0; i < issue_rate; i++)
16832 group_insns[i] = 0;
16836 if (GET_MODE (next_insn) == TImode && can_issue_more)
16837 PUT_MODE(next_insn, VOIDmode);
16838 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16839 PUT_MODE (next_insn, TImode);
16842 if (can_issue_more == 0)
16843 can_issue_more = issue_rate;
16846 return group_count;
16849 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16850 dispatch group boundaries that the scheduler had marked. Pad with nops
16851 any dispatch groups which have vacant issue slots, in order to force the
16852 scheduler's grouping on the processor dispatcher. The function
16853 returns the number of dispatch groups found. */
16856 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16858 rtx insn, next_insn;
16861 int can_issue_more;
16863 int group_count = 0;
16865 /* Initialize issue_rate. */
16866 issue_rate = rs6000_issue_rate ();
16867 can_issue_more = issue_rate;
16869 insn = get_next_active_insn (prev_head_insn, tail);
16870 next_insn = get_next_active_insn (insn, tail);
16872 while (insn != NULL_RTX)
16875 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16877 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
16879 if (next_insn == NULL_RTX)
16884 /* If the scheduler had marked group termination at this location
16885 (between insn and next_indn), and neither insn nor next_insn will
16886 force group termination, pad the group with nops to force group
16889 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
16890 && !insn_terminates_group_p (insn, current_group)
16891 && !insn_terminates_group_p (next_insn, previous_group))
16893 if (!is_branch_slot_insn(next_insn))
16896 while (can_issue_more)
16899 emit_insn_before (nop, next_insn);
16904 can_issue_more = issue_rate;
16909 next_insn = get_next_active_insn (insn, tail);
16912 return group_count;
16915 /* The following function is called at the end of scheduling BB.
16916 After reload, it inserts nops at insn group bundling. */
16919 rs6000_sched_finish (FILE *dump, int sched_verbose)
16924 fprintf (dump, "=== Finishing schedule.\n");
16926 if (reload_completed && rs6000_sched_groups)
16928 if (rs6000_sched_insert_nops == sched_finish_none)
16931 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
16932 n_groups = pad_groups (dump, sched_verbose,
16933 current_sched_info->prev_head,
16934 current_sched_info->next_tail);
16936 n_groups = redefine_groups (dump, sched_verbose,
16937 current_sched_info->prev_head,
16938 current_sched_info->next_tail);
16940 if (sched_verbose >= 6)
16942 fprintf (dump, "ngroups = %d\n", n_groups);
16943 print_rtl (dump, current_sched_info->prev_head);
16944 fprintf (dump, "Done finish_sched\n");
16949 /* Length in units of the trampoline for entering a nested function. */
16952 rs6000_trampoline_size (void)
16956 switch (DEFAULT_ABI)
16962 ret = (TARGET_32BIT) ? 12 : 24;
16967 ret = (TARGET_32BIT) ? 40 : 48;
16974 /* Emit RTL insns to initialize the variable parts of a trampoline.
16975 FNADDR is an RTX for the address of the function's pure code.
16976 CXT is an RTX for the static chain value for the function. */
16979 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
16981 enum machine_mode pmode = Pmode;
16982 int regsize = (TARGET_32BIT) ? 4 : 8;
16983 rtx ctx_reg = force_reg (pmode, cxt);
16985 switch (DEFAULT_ABI)
16990 /* Macros to shorten the code expansions below. */
16991 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
16992 #define MEM_PLUS(addr,offset) \
16993 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
16995 /* Under AIX, just build the 3 word function descriptor */
16998 rtx fn_reg = gen_reg_rtx (pmode);
16999 rtx toc_reg = gen_reg_rtx (pmode);
17000 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17001 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17002 emit_move_insn (MEM_DEREF (addr), fn_reg);
17003 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17004 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17008 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17011 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17012 FALSE, VOIDmode, 4,
17014 GEN_INT (rs6000_trampoline_size ()), SImode,
17024 /* Table of valid machine attributes. */
17026 const struct attribute_spec rs6000_attribute_table[] =
17028 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17029 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17030 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17031 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17032 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17033 SUBTARGET_ATTRIBUTE_TABLE,
17035 { NULL, 0, 0, false, false, false, NULL }
17038 /* Handle the "altivec" attribute. The attribute may have
17039 arguments as follows:
17041 __attribute__((altivec(vector__)))
17042 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17043 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17045 and may appear more than once (e.g., 'vector bool char') in a
17046 given declaration. */
17049 rs6000_handle_altivec_attribute (tree *node,
17050 tree name ATTRIBUTE_UNUSED,
17052 int flags ATTRIBUTE_UNUSED,
17053 bool *no_add_attrs)
17055 tree type = *node, result = NULL_TREE;
17056 enum machine_mode mode;
17059 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17060 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17061 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17064 while (POINTER_TYPE_P (type)
17065 || TREE_CODE (type) == FUNCTION_TYPE
17066 || TREE_CODE (type) == METHOD_TYPE
17067 || TREE_CODE (type) == ARRAY_TYPE)
17068 type = TREE_TYPE (type);
17070 mode = TYPE_MODE (type);
17072 /* Check for invalid AltiVec type qualifiers. */
17073 if (type == long_unsigned_type_node || type == long_integer_type_node)
17076 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17077 else if (rs6000_warn_altivec_long)
17078 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
17080 else if (type == long_long_unsigned_type_node
17081 || type == long_long_integer_type_node)
17082 error ("use of %<long long%> in AltiVec types is invalid");
17083 else if (type == double_type_node)
17084 error ("use of %<double%> in AltiVec types is invalid");
17085 else if (type == long_double_type_node)
17086 error ("use of %<long double%> in AltiVec types is invalid");
17087 else if (type == boolean_type_node)
17088 error ("use of boolean types in AltiVec types is invalid");
17089 else if (TREE_CODE (type) == COMPLEX_TYPE)
17090 error ("use of %<complex%> in AltiVec types is invalid");
17092 switch (altivec_type)
17095 unsigned_p = TYPE_UNSIGNED (type);
17099 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17102 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17105 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17107 case SFmode: result = V4SF_type_node; break;
17108 /* If the user says 'vector int bool', we may be handed the 'bool'
17109 attribute _before_ the 'vector' attribute, and so select the
17110 proper type in the 'b' case below. */
17111 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17119 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17120 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17121 case QImode: case V16QImode: result = bool_V16QI_type_node;
17128 case V8HImode: result = pixel_V8HI_type_node;
17134 if (result && result != type && TYPE_READONLY (type))
17135 result = build_qualified_type (result, TYPE_QUAL_CONST);
17137 *no_add_attrs = true; /* No need to hang on to the attribute. */
17140 *node = reconstruct_complex_type (*node, result);
17145 /* AltiVec defines four built-in scalar types that serve as vector
17146 elements; we must teach the compiler how to mangle them. */
17148 static const char *
17149 rs6000_mangle_fundamental_type (tree type)
17151 if (type == bool_char_type_node) return "U6__boolc";
17152 if (type == bool_short_type_node) return "U6__bools";
17153 if (type == pixel_type_node) return "u7__pixel";
17154 if (type == bool_int_type_node) return "U6__booli";
17156 /* For all other types, use normal C++ mangling. */
17160 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17161 struct attribute_spec.handler. */
17164 rs6000_handle_longcall_attribute (tree *node, tree name,
17165 tree args ATTRIBUTE_UNUSED,
17166 int flags ATTRIBUTE_UNUSED,
17167 bool *no_add_attrs)
17169 if (TREE_CODE (*node) != FUNCTION_TYPE
17170 && TREE_CODE (*node) != FIELD_DECL
17171 && TREE_CODE (*node) != TYPE_DECL)
17173 warning ("%qs attribute only applies to functions",
17174 IDENTIFIER_POINTER (name));
17175 *no_add_attrs = true;
17181 /* Set longcall attributes on all functions declared when
17182 rs6000_default_long_calls is true. */
17184 rs6000_set_default_type_attributes (tree type)
17186 if (rs6000_default_long_calls
17187 && (TREE_CODE (type) == FUNCTION_TYPE
17188 || TREE_CODE (type) == METHOD_TYPE))
17189 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17191 TYPE_ATTRIBUTES (type));
17194 /* Return a reference suitable for calling a function with the
17195 longcall attribute. */
17198 rs6000_longcall_ref (rtx call_ref)
17200 const char *call_name;
17203 if (GET_CODE (call_ref) != SYMBOL_REF)
17206 /* System V adds '.' to the internal name, so skip them. */
17207 call_name = XSTR (call_ref, 0);
17208 if (*call_name == '.')
17210 while (*call_name == '.')
17213 node = get_identifier (call_name);
17214 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17217 return force_reg (Pmode, call_ref);
17220 #ifdef USING_ELFOS_H
17222 /* A C statement or statements to switch to the appropriate section
17223 for output of RTX in mode MODE. You can assume that RTX is some
17224 kind of constant in RTL. The argument MODE is redundant except in
17225 the case of a `const_int' rtx. Select the section by calling
17226 `text_section' or one of the alternatives for other sections.
17228 Do not define this macro if you put all constants in the read-only
17232 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17233 unsigned HOST_WIDE_INT align)
17235 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17238 default_elf_select_rtx_section (mode, x, align);
17241 /* A C statement or statements to switch to the appropriate
17242 section for output of DECL. DECL is either a `VAR_DECL' node
17243 or a constant of some sort. RELOC indicates whether forming
17244 the initial value of DECL requires link-time relocations. */
17247 rs6000_elf_select_section (tree decl, int reloc,
17248 unsigned HOST_WIDE_INT align)
17250 /* Pretend that we're always building for a shared library when
17251 ABI_AIX, because otherwise we end up with dynamic relocations
17252 in read-only sections. This happens for function pointers,
17253 references to vtables in typeinfo, and probably other cases. */
17254 default_elf_select_section_1 (decl, reloc, align,
17255 flag_pic || DEFAULT_ABI == ABI_AIX);
17258 /* A C statement to build up a unique section name, expressed as a
17259 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17260 RELOC indicates whether the initial value of EXP requires
17261 link-time relocations. If you do not define this macro, GCC will use
17262 the symbol name prefixed by `.' as the section name. Note - this
17263 macro can now be called for uninitialized data items as well as
17264 initialized data and functions. */
17267 rs6000_elf_unique_section (tree decl, int reloc)
17269 /* As above, pretend that we're always building for a shared library
17270 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17271 default_unique_section_1 (decl, reloc,
17272 flag_pic || DEFAULT_ABI == ABI_AIX);
17275 /* For a SYMBOL_REF, set generic flags and then perform some
17276 target-specific processing.
17278 When the AIX ABI is requested on a non-AIX system, replace the
17279 function name with the real name (with a leading .) rather than the
17280 function descriptor name. This saves a lot of overriding code to
17281 read the prefixes. */
17284 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17286 default_encode_section_info (decl, rtl, first);
17289 && TREE_CODE (decl) == FUNCTION_DECL
17291 && DEFAULT_ABI == ABI_AIX)
17293 rtx sym_ref = XEXP (rtl, 0);
17294 size_t len = strlen (XSTR (sym_ref, 0));
17295 char *str = alloca (len + 2);
17297 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17298 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17303 rs6000_elf_in_small_data_p (tree decl)
17305 if (rs6000_sdata == SDATA_NONE)
17308 /* We want to merge strings, so we never consider them small data. */
17309 if (TREE_CODE (decl) == STRING_CST)
17312 /* Functions are never in the small data area. */
17313 if (TREE_CODE (decl) == FUNCTION_DECL)
17316 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17318 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17319 if (strcmp (section, ".sdata") == 0
17320 || strcmp (section, ".sdata2") == 0
17321 || strcmp (section, ".sbss") == 0
17322 || strcmp (section, ".sbss2") == 0
17323 || strcmp (section, ".PPC.EMB.sdata0") == 0
17324 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17329 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17332 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17333 /* If it's not public, and we're not going to reference it there,
17334 there's no need to put it in the small data section. */
17335 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17342 #endif /* USING_ELFOS_H */
17345 /* Return a REG that occurs in ADDR with coefficient 1.
17346 ADDR can be effectively incremented by incrementing REG.
17348 r0 is special and we must not select it as an address
17349 register by this routine since our caller will try to
17350 increment the returned register via an "la" instruction. */
17353 find_addr_reg (rtx addr)
17355 while (GET_CODE (addr) == PLUS)
17357 if (GET_CODE (XEXP (addr, 0)) == REG
17358 && REGNO (XEXP (addr, 0)) != 0)
17359 addr = XEXP (addr, 0);
17360 else if (GET_CODE (XEXP (addr, 1)) == REG
17361 && REGNO (XEXP (addr, 1)) != 0)
17362 addr = XEXP (addr, 1);
17363 else if (CONSTANT_P (XEXP (addr, 0)))
17364 addr = XEXP (addr, 1);
17365 else if (CONSTANT_P (XEXP (addr, 1)))
17366 addr = XEXP (addr, 0);
17370 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
17376 rs6000_fatal_bad_address (rtx op)
17378 fatal_insn ("bad address", op);
17383 static tree branch_island_list = 0;
17385 /* Remember to generate a branch island for far calls to the given
17389 add_compiler_branch_island (tree label_name, tree function_name,
17392 tree branch_island = build_tree_list (function_name, label_name);
17393 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17394 TREE_CHAIN (branch_island) = branch_island_list;
17395 branch_island_list = branch_island;
17398 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17399 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17400 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17401 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17403 /* Generate far-jump branch islands for everything on the
17404 branch_island_list. Invoked immediately after the last instruction
17405 of the epilogue has been emitted; the branch-islands must be
17406 appended to, and contiguous with, the function body. Mach-O stubs
17407 are generated in machopic_output_stub(). */
17410 macho_branch_islands (void)
17413 tree branch_island;
17415 for (branch_island = branch_island_list;
17417 branch_island = TREE_CHAIN (branch_island))
17419 const char *label =
17420 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17422 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17423 char name_buf[512];
17424 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17425 if (name[0] == '*' || name[0] == '&')
17426 strcpy (name_buf, name+1);
17430 strcpy (name_buf+1, name);
17432 strcpy (tmp_buf, "\n");
17433 strcat (tmp_buf, label);
17434 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17435 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17436 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17437 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17440 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17441 strcat (tmp_buf, label);
17442 strcat (tmp_buf, "_pic\n");
17443 strcat (tmp_buf, label);
17444 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17446 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17447 strcat (tmp_buf, name_buf);
17448 strcat (tmp_buf, " - ");
17449 strcat (tmp_buf, label);
17450 strcat (tmp_buf, "_pic)\n");
17452 strcat (tmp_buf, "\tmtlr r0\n");
17454 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17455 strcat (tmp_buf, name_buf);
17456 strcat (tmp_buf, " - ");
17457 strcat (tmp_buf, label);
17458 strcat (tmp_buf, "_pic)\n");
17460 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17464 strcat (tmp_buf, ":\nlis r12,hi16(");
17465 strcat (tmp_buf, name_buf);
17466 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17467 strcat (tmp_buf, name_buf);
17468 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17470 output_asm_insn (tmp_buf, 0);
17471 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17472 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17473 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17474 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17477 branch_island_list = 0;
17480 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17481 already there or not. */
17484 no_previous_def (tree function_name)
17486 tree branch_island;
17487 for (branch_island = branch_island_list;
17489 branch_island = TREE_CHAIN (branch_island))
17490 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17495 /* GET_PREV_LABEL gets the label name from the previous definition of
17499 get_prev_label (tree function_name)
17501 tree branch_island;
17502 for (branch_island = branch_island_list;
17504 branch_island = TREE_CHAIN (branch_island))
17505 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17506 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17510 /* INSN is either a function call or a millicode call. It may have an
17511 unconditional jump in its delay slot.
17513 CALL_DEST is the routine we are calling. */
17516 output_call (rtx insn, rtx *operands, int dest_operand_number,
17517 int cookie_operand_number)
17519 static char buf[256];
17520 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17521 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17524 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17526 if (no_previous_def (funname))
17528 int line_number = 0;
17529 rtx label_rtx = gen_label_rtx ();
17530 char *label_buf, temp_buf[256];
17531 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17532 CODE_LABEL_NUMBER (label_rtx));
17533 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17534 labelname = get_identifier (label_buf);
17535 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17537 line_number = NOTE_LINE_NUMBER (insn);
17538 add_compiler_branch_island (labelname, funname, line_number);
17541 labelname = get_prev_label (funname);
17543 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17544 instruction will reach 'foo', otherwise link as 'bl L42'".
17545 "L42" should be a 'branch island', that will do a far jump to
17546 'foo'. Branch islands are generated in
17547 macho_branch_islands(). */
17548 sprintf (buf, "jbsr %%z%d,%.246s",
17549 dest_operand_number, IDENTIFIER_POINTER (labelname));
17552 sprintf (buf, "bl %%z%d", dest_operand_number);
17556 /* Generate PIC and indirect symbol stubs. */
17559 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17561 unsigned int length;
17562 char *symbol_name, *lazy_ptr_name;
17563 char *local_label_0;
17564 static int label = 0;
17566 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17567 symb = (*targetm.strip_name_encoding) (symb);
17570 length = strlen (symb);
17571 symbol_name = alloca (length + 32);
17572 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17574 lazy_ptr_name = alloca (length + 32);
17575 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17578 machopic_picsymbol_stub1_section ();
17580 machopic_symbol_stub1_section ();
17584 fprintf (file, "\t.align 5\n");
17586 fprintf (file, "%s:\n", stub);
17587 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17590 local_label_0 = alloca (sizeof("\"L0000000000$spb\""));
17591 sprintf (local_label_0, "\"L%011d$spb\"", label);
17593 fprintf (file, "\tmflr r0\n");
17594 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17595 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17596 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17597 lazy_ptr_name, local_label_0);
17598 fprintf (file, "\tmtlr r0\n");
17599 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17600 (TARGET_64BIT ? "ldu" : "lwzu"),
17601 lazy_ptr_name, local_label_0);
17602 fprintf (file, "\tmtctr r12\n");
17603 fprintf (file, "\tbctr\n");
17607 fprintf (file, "\t.align 4\n");
17609 fprintf (file, "%s:\n", stub);
17610 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17612 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17613 fprintf (file, "\tlwzu r12,lo16(%s)(r11)\n", lazy_ptr_name);
17614 fprintf (file, "\tmtctr r12\n");
17615 fprintf (file, "\tbctr\n");
17618 machopic_lazy_symbol_ptr_section ();
17619 fprintf (file, "%s:\n", lazy_ptr_name);
17620 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17621 fprintf (file, "%sdyld_stub_binding_helper\n",
17622 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17625 /* Legitimize PIC addresses. If the address is already
17626 position-independent, we return ORIG. Newly generated
17627 position-independent addresses go into a reg. This is REG if non
17628 zero, otherwise we allocate register(s) as necessary. */
17630 #define SMALL_INT(X) ((unsigned) (INTVAL(X) + 0x8000) < 0x10000)
17633 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17638 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17639 reg = gen_reg_rtx (Pmode);
17641 if (GET_CODE (orig) == CONST)
17643 if (GET_CODE (XEXP (orig, 0)) == PLUS
17644 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17647 if (GET_CODE (XEXP (orig, 0)) == PLUS)
17649 /* Use a different reg for the intermediate value, as
17650 it will be marked UNCHANGING. */
17651 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17654 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17657 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17663 if (GET_CODE (offset) == CONST_INT)
17665 if (SMALL_INT (offset))
17666 return plus_constant (base, INTVAL (offset));
17667 else if (! reload_in_progress && ! reload_completed)
17668 offset = force_reg (Pmode, offset);
17671 rtx mem = force_const_mem (Pmode, orig);
17672 return machopic_legitimize_pic_address (mem, Pmode, reg);
17675 return gen_rtx_PLUS (Pmode, base, offset);
17678 /* Fall back on generic machopic code. */
17679 return machopic_legitimize_pic_address (orig, mode, reg);
17682 /* This is just a placeholder to make linking work without having to
17683 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17684 ever needed for Darwin (not too likely!) this would have to get a
17685 real definition. */
17692 /* Output a .machine directive for the Darwin assembler, and call
17693 the generic start_file routine. */
17696 rs6000_darwin_file_start (void)
17698 static const struct
17704 { "ppc64", "ppc64", MASK_64BIT },
17705 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17706 { "power4", "ppc970", 0 },
17707 { "G5", "ppc970", 0 },
17708 { "7450", "ppc7450", 0 },
17709 { "7400", "ppc7400", MASK_ALTIVEC },
17710 { "G4", "ppc7400", 0 },
17711 { "750", "ppc750", 0 },
17712 { "740", "ppc750", 0 },
17713 { "G3", "ppc750", 0 },
17714 { "604e", "ppc604e", 0 },
17715 { "604", "ppc604", 0 },
17716 { "603e", "ppc603", 0 },
17717 { "603", "ppc603", 0 },
17718 { "601", "ppc601", 0 },
17719 { NULL, "ppc", 0 } };
17720 const char *cpu_id = "";
17723 rs6000_file_start();
17725 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17726 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17727 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17728 && rs6000_select[i].string[0] != '\0')
17729 cpu_id = rs6000_select[i].string;
17731 /* Look through the mapping array. Pick the first name that either
17732 matches the argument, has a bit set in IF_SET that is also set
17733 in the target flags, or has a NULL name. */
17736 while (mapping[i].arg != NULL
17737 && strcmp (mapping[i].arg, cpu_id) != 0
17738 && (mapping[i].if_set & target_flags) == 0)
17741 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17744 #endif /* TARGET_MACHO */
17747 static unsigned int
17748 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17750 return default_section_type_flags_1 (decl, name, reloc,
17751 flag_pic || DEFAULT_ABI == ABI_AIX);
17754 /* Record an element in the table of global constructors. SYMBOL is
17755 a SYMBOL_REF of the function to be called; PRIORITY is a number
17756 between 0 and MAX_INIT_PRIORITY.
17758 This differs from default_named_section_asm_out_constructor in
17759 that we have special handling for -mrelocatable. */
17762 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17764 const char *section = ".ctors";
17767 if (priority != DEFAULT_INIT_PRIORITY)
17769 sprintf (buf, ".ctors.%.5u",
17770 /* Invert the numbering so the linker puts us in the proper
17771 order; constructors are run from right to left, and the
17772 linker sorts in increasing order. */
17773 MAX_INIT_PRIORITY - priority);
17777 named_section_flags (section, SECTION_WRITE);
17778 assemble_align (POINTER_SIZE);
17780 if (TARGET_RELOCATABLE)
17782 fputs ("\t.long (", asm_out_file);
17783 output_addr_const (asm_out_file, symbol);
17784 fputs (")@fixup\n", asm_out_file);
17787 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17791 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17793 const char *section = ".dtors";
17796 if (priority != DEFAULT_INIT_PRIORITY)
17798 sprintf (buf, ".dtors.%.5u",
17799 /* Invert the numbering so the linker puts us in the proper
17800 order; constructors are run from right to left, and the
17801 linker sorts in increasing order. */
17802 MAX_INIT_PRIORITY - priority);
17806 named_section_flags (section, SECTION_WRITE);
17807 assemble_align (POINTER_SIZE);
17809 if (TARGET_RELOCATABLE)
17811 fputs ("\t.long (", asm_out_file);
17812 output_addr_const (asm_out_file, symbol);
17813 fputs (")@fixup\n", asm_out_file);
17816 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17820 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17824 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17825 ASM_OUTPUT_LABEL (file, name);
17826 fputs (DOUBLE_INT_ASM_OP, file);
17827 rs6000_output_function_entry (file, name);
17828 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17831 fputs ("\t.size\t", file);
17832 assemble_name (file, name);
17833 fputs (",24\n\t.type\t.", file);
17834 assemble_name (file, name);
17835 fputs (",@function\n", file);
17836 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17838 fputs ("\t.globl\t.", file);
17839 assemble_name (file, name);
17844 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17845 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17846 rs6000_output_function_entry (file, name);
17847 fputs (":\n", file);
17851 if (TARGET_RELOCATABLE
17852 && (get_pool_size () != 0 || current_function_profile)
17857 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
17859 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
17860 fprintf (file, "\t.long ");
17861 assemble_name (file, buf);
17863 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
17864 assemble_name (file, buf);
17868 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17869 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17871 if (DEFAULT_ABI == ABI_AIX)
17873 const char *desc_name, *orig_name;
17875 orig_name = (*targetm.strip_name_encoding) (name);
17876 desc_name = orig_name;
17877 while (*desc_name == '.')
17880 if (TREE_PUBLIC (decl))
17881 fprintf (file, "\t.globl %s\n", desc_name);
17883 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
17884 fprintf (file, "%s:\n", desc_name);
17885 fprintf (file, "\t.long %s\n", orig_name);
17886 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
17887 if (DEFAULT_ABI == ABI_AIX)
17888 fputs ("\t.long 0\n", file);
17889 fprintf (file, "\t.previous\n");
17891 ASM_OUTPUT_LABEL (file, name);
17897 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
17899 fputs (GLOBAL_ASM_OP, stream);
17900 RS6000_OUTPUT_BASENAME (stream, name);
17901 putc ('\n', stream);
17905 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
17906 tree decl ATTRIBUTE_UNUSED)
17909 static const char * const suffix[3] = { "PR", "RO", "RW" };
17911 if (flags & SECTION_CODE)
17913 else if (flags & SECTION_WRITE)
17918 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
17919 (flags & SECTION_CODE) ? "." : "",
17920 name, suffix[smclass], flags & SECTION_ENTSIZE);
17924 rs6000_xcoff_select_section (tree decl, int reloc,
17925 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17927 if (decl_readonly_section_1 (decl, reloc, 1))
17929 if (TREE_PUBLIC (decl))
17930 read_only_data_section ();
17932 read_only_private_data_section ();
17936 if (TREE_PUBLIC (decl))
17939 private_data_section ();
17944 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
17948 /* Use select_section for private and uninitialized data. */
17949 if (!TREE_PUBLIC (decl)
17950 || DECL_COMMON (decl)
17951 || DECL_INITIAL (decl) == NULL_TREE
17952 || DECL_INITIAL (decl) == error_mark_node
17953 || (flag_zero_initialized_in_bss
17954 && initializer_zerop (DECL_INITIAL (decl))))
17957 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
17958 name = (*targetm.strip_name_encoding) (name);
17959 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
17962 /* Select section for constant in constant pool.
17964 On RS/6000, all constants are in the private read-only data area.
17965 However, if this is being placed in the TOC it must be output as a
17969 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
17970 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
17972 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17975 read_only_private_data_section ();
17978 /* Remove any trailing [DS] or the like from the symbol name. */
17980 static const char *
17981 rs6000_xcoff_strip_name_encoding (const char *name)
17986 len = strlen (name);
17987 if (name[len - 1] == ']')
17988 return ggc_alloc_string (name, len - 4);
17993 /* Section attributes. AIX is always PIC. */
17995 static unsigned int
17996 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
17998 unsigned int align;
17999 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18001 /* Align to at least UNIT size. */
18002 if (flags & SECTION_CODE)
18003 align = MIN_UNITS_PER_WORD;
18005 /* Increase alignment of large objects if not already stricter. */
18006 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18007 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18008 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18010 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18013 /* Output at beginning of assembler file.
18015 Initialize the section names for the RS/6000 at this point.
18017 Specify filename, including full path, to assembler.
18019 We want to go into the TOC section so at least one .toc will be emitted.
18020 Also, in order to output proper .bs/.es pairs, we need at least one static
18021 [RW] section emitted.
18023 Finally, declare mcount when profiling to make the assembler happy. */
18026 rs6000_xcoff_file_start (void)
18028 rs6000_gen_section_name (&xcoff_bss_section_name,
18029 main_input_filename, ".bss_");
18030 rs6000_gen_section_name (&xcoff_private_data_section_name,
18031 main_input_filename, ".rw_");
18032 rs6000_gen_section_name (&xcoff_read_only_section_name,
18033 main_input_filename, ".ro_");
18035 fputs ("\t.file\t", asm_out_file);
18036 output_quoted_string (asm_out_file, main_input_filename);
18037 fputc ('\n', asm_out_file);
18039 if (write_symbols != NO_DEBUG)
18040 private_data_section ();
18043 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18044 rs6000_file_start ();
18047 /* Output at end of assembler file.
18048 On the RS/6000, referencing data should automatically pull in text. */
18051 rs6000_xcoff_file_end (void)
18054 fputs ("_section_.text:\n", asm_out_file);
18056 fputs (TARGET_32BIT
18057 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18060 #endif /* TARGET_XCOFF */
18063 /* Cross-module name binding. Darwin does not support overriding
18064 functions at dynamic-link time. */
18067 rs6000_binds_local_p (tree decl)
18069 return default_binds_local_p_1 (decl, 0);
18073 /* Compute a (partial) cost for rtx X. Return true if the complete
18074 cost has been computed, and false if subexpressions should be
18075 scanned. In either case, *TOTAL contains the cost result. */
18078 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18080 enum machine_mode mode = GET_MODE (x);
18084 /* On the RS/6000, if it is valid in the insn, it is free. */
18086 if (((outer_code == SET
18087 || outer_code == PLUS
18088 || outer_code == MINUS)
18089 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18090 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18091 || (outer_code == AND
18092 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18093 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18094 mode == SImode ? 'L' : 'J'))
18095 || mask_operand (x, VOIDmode)))
18096 || ((outer_code == IOR || outer_code == XOR)
18097 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18098 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18099 mode == SImode ? 'L' : 'J'))))
18100 || outer_code == ASHIFT
18101 || outer_code == ASHIFTRT
18102 || outer_code == LSHIFTRT
18103 || outer_code == ROTATE
18104 || outer_code == ROTATERT
18105 || outer_code == ZERO_EXTRACT
18106 || (outer_code == MULT
18107 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18108 || ((outer_code == DIV || outer_code == UDIV
18109 || outer_code == MOD || outer_code == UMOD)
18110 && exact_log2 (INTVAL (x)) >= 0)
18111 || (outer_code == COMPARE
18112 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18113 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18114 || (outer_code == EQ
18115 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18116 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18117 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18118 mode == SImode ? 'L' : 'J'))))
18119 || (outer_code == GTU
18120 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18121 || (outer_code == LTU
18122 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18127 else if ((outer_code == PLUS
18128 && reg_or_add_cint64_operand (x, VOIDmode))
18129 || (outer_code == MINUS
18130 && reg_or_sub_cint64_operand (x, VOIDmode))
18131 || ((outer_code == SET
18132 || outer_code == IOR
18133 || outer_code == XOR)
18135 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18137 *total = COSTS_N_INSNS (1);
18144 && ((outer_code == AND
18145 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18146 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18147 || mask64_operand (x, DImode)))
18148 || ((outer_code == IOR || outer_code == XOR)
18149 && CONST_DOUBLE_HIGH (x) == 0
18150 && (CONST_DOUBLE_LOW (x)
18151 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18156 else if (mode == DImode
18157 && (outer_code == SET
18158 || outer_code == IOR
18159 || outer_code == XOR)
18160 && CONST_DOUBLE_HIGH (x) == 0)
18162 *total = COSTS_N_INSNS (1);
18171 /* When optimizing for size, MEM should be slightly more expensive
18172 than generating address, e.g., (plus (reg) (const)).
18173 L1 cache latency is about two instructions. */
18174 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18182 if (mode == DFmode)
18184 if (GET_CODE (XEXP (x, 0)) == MULT)
18186 /* FNMA accounted in outer NEG. */
18187 if (outer_code == NEG)
18188 *total = rs6000_cost->dmul - rs6000_cost->fp;
18190 *total = rs6000_cost->dmul;
18193 *total = rs6000_cost->fp;
18195 else if (mode == SFmode)
18197 /* FNMA accounted in outer NEG. */
18198 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18201 *total = rs6000_cost->fp;
18203 else if (GET_CODE (XEXP (x, 0)) == MULT)
18205 /* The rs6000 doesn't have shift-and-add instructions. */
18206 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
18207 *total += COSTS_N_INSNS (1);
18210 *total = COSTS_N_INSNS (1);
18214 if (mode == DFmode)
18216 if (GET_CODE (XEXP (x, 0)) == MULT)
18218 /* FNMA accounted in outer NEG. */
18219 if (outer_code == NEG)
18222 *total = rs6000_cost->dmul;
18225 *total = rs6000_cost->fp;
18227 else if (mode == SFmode)
18229 /* FNMA accounted in outer NEG. */
18230 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18233 *total = rs6000_cost->fp;
18235 else if (GET_CODE (XEXP (x, 0)) == MULT)
18237 /* The rs6000 doesn't have shift-and-sub instructions. */
18238 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
18239 *total += COSTS_N_INSNS (1);
18242 *total = COSTS_N_INSNS (1);
18246 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18247 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18249 if (INTVAL (XEXP (x, 1)) >= -256
18250 && INTVAL (XEXP (x, 1)) <= 255)
18251 *total = rs6000_cost->mulsi_const9;
18253 *total = rs6000_cost->mulsi_const;
18255 /* FMA accounted in outer PLUS/MINUS. */
18256 else if ((mode == DFmode || mode == SFmode)
18257 && (outer_code == PLUS || outer_code == MINUS))
18259 else if (mode == DFmode)
18260 *total = rs6000_cost->dmul;
18261 else if (mode == SFmode)
18262 *total = rs6000_cost->fp;
18263 else if (mode == DImode)
18264 *total = rs6000_cost->muldi;
18266 *total = rs6000_cost->mulsi;
18271 if (FLOAT_MODE_P (mode))
18273 *total = mode == DFmode ? rs6000_cost->ddiv
18274 : rs6000_cost->sdiv;
18281 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18282 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18284 if (code == DIV || code == MOD)
18286 *total = COSTS_N_INSNS (2);
18289 *total = COSTS_N_INSNS (1);
18293 if (GET_MODE (XEXP (x, 1)) == DImode)
18294 *total = rs6000_cost->divdi;
18296 *total = rs6000_cost->divsi;
18298 /* Add in shift and subtract for MOD. */
18299 if (code == MOD || code == UMOD)
18300 *total += COSTS_N_INSNS (2);
18304 *total = COSTS_N_INSNS (4);
18308 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18319 *total = COSTS_N_INSNS (1);
18327 /* Handle mul_highpart. */
18328 if (outer_code == TRUNCATE
18329 && GET_CODE (XEXP (x, 0)) == MULT)
18331 if (mode == DImode)
18332 *total = rs6000_cost->muldi;
18334 *total = rs6000_cost->mulsi;
18337 else if (outer_code == AND)
18340 *total = COSTS_N_INSNS (1);
18345 if (GET_CODE (XEXP (x, 0)) == MEM)
18348 *total = COSTS_N_INSNS (1);
18354 if (!FLOAT_MODE_P (mode))
18356 *total = COSTS_N_INSNS (1);
18362 case UNSIGNED_FLOAT:
18366 case FLOAT_TRUNCATE:
18367 *total = rs6000_cost->fp;
18371 switch (XINT (x, 1))
18374 *total = rs6000_cost->fp;
18386 *total = COSTS_N_INSNS (1);
18389 else if (FLOAT_MODE_P (mode)
18390 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18392 *total = rs6000_cost->fp;
18400 /* Carry bit requires mode == Pmode.
18401 NEG or PLUS already counted so only add one. */
18403 && (outer_code == NEG || outer_code == PLUS))
18405 *total = COSTS_N_INSNS (1);
18408 if (outer_code == SET)
18410 if (XEXP (x, 1) == const0_rtx)
18412 *total = COSTS_N_INSNS (2);
18415 else if (mode == Pmode)
18417 *total = COSTS_N_INSNS (3);
18426 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18428 *total = COSTS_N_INSNS (2);
18432 if (outer_code == COMPARE)
18446 /* A C expression returning the cost of moving data from a register of class
18447 CLASS1 to one of CLASS2. */
18450 rs6000_register_move_cost (enum machine_mode mode,
18451 enum reg_class from, enum reg_class to)
18453 /* Moves from/to GENERAL_REGS. */
18454 if (reg_classes_intersect_p (to, GENERAL_REGS)
18455 || reg_classes_intersect_p (from, GENERAL_REGS))
18457 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18460 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18461 return (rs6000_memory_move_cost (mode, from, 0)
18462 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18464 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18466 else if (from == CR_REGS)
18470 /* A move will cost one instruction per GPR moved. */
18471 return 2 * HARD_REGNO_NREGS (0, mode);
18474 /* Moving between two similar registers is just one instruction. */
18475 else if (reg_classes_intersect_p (to, from))
18476 return mode == TFmode ? 4 : 2;
18478 /* Everything else has to go through GENERAL_REGS. */
18480 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18481 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18484 /* A C expressions returning the cost of moving data of MODE from a register to
18488 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18489 int in ATTRIBUTE_UNUSED)
18491 if (reg_classes_intersect_p (class, GENERAL_REGS))
18492 return 4 * HARD_REGNO_NREGS (0, mode);
18493 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18494 return 4 * HARD_REGNO_NREGS (32, mode);
18495 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18496 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
18498 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18501 /* Return an RTX representing where to find the function value of a
18502 function returning MODE. */
18504 rs6000_complex_function_value (enum machine_mode mode)
18506 unsigned int regno;
18508 enum machine_mode inner = GET_MODE_INNER (mode);
18509 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18511 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18512 regno = FP_ARG_RETURN;
18515 regno = GP_ARG_RETURN;
18517 /* 32-bit is OK since it'll go in r3/r4. */
18518 if (TARGET_32BIT && inner_bytes >= 4)
18519 return gen_rtx_REG (mode, regno);
18522 if (inner_bytes >= 8)
18523 return gen_rtx_REG (mode, regno);
18525 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18527 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18528 GEN_INT (inner_bytes));
18529 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18532 /* Compose a PARALLEL for a darwin64 struct being returned by
18536 rs6000_darwin64_function_value (CUMULATIVE_ARGS *cum, tree valtype)
18539 rtx rvec[FIRST_PSEUDO_REGISTER], sub, roffset, suboff;
18540 int k = 0, bytepos, tot, elt, i, subbytepos;
18541 enum machine_mode fmode;
18543 switch (TREE_CODE (valtype))
18546 for (f = TYPE_FIELDS (valtype); f ; f = TREE_CHAIN (f))
18547 if (TREE_CODE (f) == FIELD_DECL)
18549 ftype = TREE_TYPE (f);
18550 fmode = TYPE_MODE (ftype);
18551 bytepos = int_bit_position (f) / BITS_PER_UNIT;
18552 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18554 sub = gen_rtx_REG (fmode, cum->fregno++);
18555 cum->sysv_gregno++;
18557 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18559 sub = gen_rtx_REG (fmode, cum->vregno++);
18560 cum->sysv_gregno++;
18562 else if (fmode == BLKmode
18563 && (TREE_CODE (ftype) == RECORD_TYPE
18564 || TREE_CODE (ftype) == ARRAY_TYPE))
18565 sub = rs6000_darwin64_function_value (cum, ftype);
18567 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18568 if (sub == NULL_RTX)
18570 else if (GET_CODE (sub) == PARALLEL)
18572 for (i = 0; i < XVECLEN (sub, 0); i++)
18574 rtx subsub = XVECEXP (sub, 0, i);
18576 suboff = XEXP (subsub, 1);
18577 subbytepos = INTVAL (suboff);
18578 subbytepos += bytepos;
18579 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18580 subsub = XEXP (subsub, 0);
18581 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18586 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18587 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18591 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18596 /* If passing by value won't work, give up. */
18597 if (int_size_in_bytes (valtype) <= 0)
18599 ftype = TREE_TYPE (valtype);
18600 fmode = TYPE_MODE (ftype);
18601 tot = int_size_in_bytes (valtype) / int_size_in_bytes (ftype);
18603 for (elt = 0; elt < tot; ++elt)
18605 if (USE_FP_FOR_ARG_P (cum, fmode, ftype))
18607 sub = gen_rtx_REG (fmode, cum->fregno++);
18608 cum->sysv_gregno++;
18610 else if (USE_ALTIVEC_FOR_ARG_P (cum, fmode, ftype, 1))
18612 sub = gen_rtx_REG (fmode, cum->vregno++);
18613 cum->sysv_gregno++;
18615 else if (fmode == BLKmode
18616 && (TREE_CODE (ftype) == RECORD_TYPE
18617 || TREE_CODE (ftype) == ARRAY_TYPE))
18618 sub = rs6000_darwin64_function_value (cum, ftype);
18620 sub = gen_rtx_REG (fmode, cum->sysv_gregno++);
18621 if (sub == NULL_RTX)
18623 else if (GET_CODE (sub) == PARALLEL)
18625 for (i = 0; i < XVECLEN (sub, 0); i++)
18627 rtx subsub = XVECEXP (sub, 0, i);
18629 suboff = XEXP (subsub, 1);
18630 subbytepos = INTVAL (suboff);
18631 subbytepos += bytepos;
18632 roffset = gen_rtx_CONST_INT (SImode, subbytepos);
18633 subsub = XEXP (subsub, 0);
18634 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, subsub, roffset);
18639 roffset = gen_rtx_CONST_INT (SImode, bytepos);
18640 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, sub, roffset);
18642 bytepos += int_size_in_bytes (ftype);
18645 return gen_rtx_PARALLEL (TYPE_MODE (valtype), gen_rtvec_v (k, rvec));
18654 /* Define how to find the value returned by a function.
18655 VALTYPE is the data type of the value (as a tree).
18656 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18657 otherwise, FUNC is 0.
18659 On the SPE, both FPs and vectors are returned in r3.
18661 On RS/6000 an integer value is in r3 and a floating-point value is in
18662 fp1, unless -msoft-float. */
18665 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18667 enum machine_mode mode;
18668 unsigned int regno;
18670 /* Special handling for structs in darwin64. */
18671 if (rs6000_darwin64_abi
18672 && TYPE_MODE (valtype) == BLKmode
18673 && (TREE_CODE (valtype) == RECORD_TYPE
18674 || TREE_CODE (valtype) == ARRAY_TYPE))
18676 CUMULATIVE_ARGS valcum;
18679 valcum.sysv_gregno = GP_ARG_RETURN;
18680 valcum.fregno = FP_ARG_MIN_REG;
18681 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18682 valret = rs6000_darwin64_function_value (&valcum, valtype);
18685 /* Otherwise fall through to standard ABI rules. */
18688 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18690 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18691 return gen_rtx_PARALLEL (DImode,
18693 gen_rtx_EXPR_LIST (VOIDmode,
18694 gen_rtx_REG (SImode, GP_ARG_RETURN),
18696 gen_rtx_EXPR_LIST (VOIDmode,
18697 gen_rtx_REG (SImode,
18698 GP_ARG_RETURN + 1),
18702 if ((INTEGRAL_TYPE_P (valtype)
18703 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18704 || POINTER_TYPE_P (valtype))
18705 mode = TARGET_32BIT ? SImode : DImode;
18707 mode = TYPE_MODE (valtype);
18709 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18710 regno = FP_ARG_RETURN;
18711 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18712 && targetm.calls.split_complex_arg)
18713 return rs6000_complex_function_value (mode);
18714 else if (TREE_CODE (valtype) == VECTOR_TYPE
18715 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18716 && ALTIVEC_VECTOR_MODE (mode))
18717 regno = ALTIVEC_ARG_RETURN;
18718 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18719 && (mode == DFmode || mode == DCmode))
18720 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18722 regno = GP_ARG_RETURN;
18724 return gen_rtx_REG (mode, regno);
18727 /* Define how to find the value returned by a library function
18728 assuming the value has mode MODE. */
18730 rs6000_libcall_value (enum machine_mode mode)
18732 unsigned int regno;
18734 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18736 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18737 return gen_rtx_PARALLEL (DImode,
18739 gen_rtx_EXPR_LIST (VOIDmode,
18740 gen_rtx_REG (SImode, GP_ARG_RETURN),
18742 gen_rtx_EXPR_LIST (VOIDmode,
18743 gen_rtx_REG (SImode,
18744 GP_ARG_RETURN + 1),
18748 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18749 && TARGET_HARD_FLOAT && TARGET_FPRS)
18750 regno = FP_ARG_RETURN;
18751 else if (ALTIVEC_VECTOR_MODE (mode)
18752 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18753 regno = ALTIVEC_ARG_RETURN;
18754 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18755 return rs6000_complex_function_value (mode);
18756 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18757 && (mode == DFmode || mode == DCmode))
18758 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18760 regno = GP_ARG_RETURN;
18762 return gen_rtx_REG (mode, regno);
18765 /* Define the offset between two registers, FROM to be eliminated and its
18766 replacement TO, at the start of a routine. */
18768 rs6000_initial_elimination_offset (int from, int to)
18770 rs6000_stack_t *info = rs6000_stack_info ();
18771 HOST_WIDE_INT offset;
18773 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18774 offset = info->push_p ? 0 : -info->total_size;
18775 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
18776 offset = info->total_size;
18777 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18778 offset = info->push_p ? info->total_size : 0;
18779 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18787 /* Return true if TYPE is of type __ev64_opaque__. */
18790 is_ev64_opaque_type (tree type)
18793 && (type == opaque_V2SI_type_node
18794 || type == opaque_V2SF_type_node
18795 || type == opaque_p_V2SI_type_node));
18799 rs6000_dwarf_register_span (rtx reg)
18804 && (SPE_VECTOR_MODE (GET_MODE (reg))
18805 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18810 regno = REGNO (reg);
18812 /* The duality of the SPE register size wreaks all kinds of havoc.
18813 This is a way of distinguishing r0 in 32-bits from r0 in
18816 gen_rtx_PARALLEL (VOIDmode,
18819 gen_rtx_REG (SImode, regno + 1200),
18820 gen_rtx_REG (SImode, regno))
18822 gen_rtx_REG (SImode, regno),
18823 gen_rtx_REG (SImode, regno + 1200)));
18826 /* Map internal gcc register numbers to DWARF2 register numbers. */
18829 rs6000_dbx_register_number (unsigned int regno)
18831 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18833 if (regno == MQ_REGNO)
18835 if (regno == LINK_REGISTER_REGNUM)
18837 if (regno == COUNT_REGISTER_REGNUM)
18839 if (CR_REGNO_P (regno))
18840 return regno - CR0_REGNO + 86;
18841 if (regno == XER_REGNO)
18843 if (ALTIVEC_REGNO_P (regno))
18844 return regno - FIRST_ALTIVEC_REGNO + 1124;
18845 if (regno == VRSAVE_REGNO)
18847 if (regno == VSCR_REGNO)
18849 if (regno == SPE_ACC_REGNO)
18851 if (regno == SPEFSCR_REGNO)
18853 /* SPE high reg number. We get these values of regno from
18854 rs6000_dwarf_register_span. */
18855 if (regno >= 1200 && regno < 1232)
18861 /* target hook eh_return_filter_mode */
18862 static enum machine_mode
18863 rs6000_eh_return_filter_mode (void)
18865 return TARGET_32BIT ? SImode : word_mode;
18868 /* Target hook for vector_mode_supported_p. */
18870 rs6000_vector_mode_supported_p (enum machine_mode mode)
18873 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
18876 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
18883 #include "gt-rs6000.h"