1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 59 Temple Place - Suite 330, Boston,
21 MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 int varargs_size; /* size to hold V.4 args passed in regs */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int lr_size; /* size to hold LR if not in save_size */
106 int vrsave_size; /* size to hold VRSAVE if not in save_size */
107 int altivec_padding_size; /* size of altivec alignment padding if
109 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
110 int spe_padding_size;
111 int toc_size; /* size to hold TOC if not in save_size */
112 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
113 int spe_64bit_regs_used;
116 /* Target cpu type */
118 enum processor_type rs6000_cpu;
119 struct rs6000_cpu_select rs6000_select[3] =
121 /* switch name, tune arch */
122 { (const char *)0, "--with-cpu=", 1, 1 },
123 { (const char *)0, "-mcpu=", 1, 1 },
124 { (const char *)0, "-mtune=", 1, 0 },
127 /* Always emit branch hint bits. */
128 static GTY(()) bool rs6000_always_hint;
130 /* Schedule instructions for group formation. */
131 static GTY(()) bool rs6000_sched_groups;
133 /* Support adjust_priority scheduler hook
134 and -mprioritize-restricted-insns= option. */
135 const char *rs6000_sched_restricted_insns_priority_str;
136 int rs6000_sched_restricted_insns_priority;
138 /* Support for -msched-costly-dep option. */
139 const char *rs6000_sched_costly_dep_str;
140 enum rs6000_dependence_cost rs6000_sched_costly_dep;
142 /* Support for -minsert-sched-nops option. */
143 const char *rs6000_sched_insert_nops_str;
144 enum rs6000_nop_insertion rs6000_sched_insert_nops;
146 /* Support targetm.vectorize.builtin_mask_for_load. */
147 static GTY(()) tree altivec_builtin_mask_for_load;
149 /* Size of long double */
150 const char *rs6000_long_double_size_string;
151 int rs6000_long_double_type_size;
153 /* Whether -mabi=altivec has appeared */
154 int rs6000_altivec_abi;
156 /* Whether VRSAVE instructions should be generated. */
157 int rs6000_altivec_vrsave;
159 /* String from -mvrsave= option. */
160 const char *rs6000_altivec_vrsave_string;
162 /* Nonzero if we want SPE ABI extensions. */
165 /* Whether isel instructions should be generated. */
168 /* Whether SPE simd instructions should be generated. */
171 /* Nonzero if floating point operations are done in the GPRs. */
172 int rs6000_float_gprs = 0;
174 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
175 int rs6000_darwin64_abi;
177 /* String from -mfloat-gprs=. */
178 const char *rs6000_float_gprs_string;
180 /* String from -misel=. */
181 const char *rs6000_isel_string;
183 /* String from -mspe=. */
184 const char *rs6000_spe_string;
186 /* Set to nonzero once AIX common-mode calls have been defined. */
187 static GTY(()) int common_mode_defined;
189 /* Save information from a "cmpxx" operation until the branch or scc is
191 rtx rs6000_compare_op0, rs6000_compare_op1;
192 int rs6000_compare_fp_p;
194 /* Label number of label created for -mrelocatable, to call to so we can
195 get the address of the GOT section */
196 int rs6000_pic_labelno;
199 /* Which abi to adhere to */
200 const char *rs6000_abi_name;
202 /* Semantics of the small data area */
203 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
205 /* Which small data model to use */
206 const char *rs6000_sdata_name = (char *)0;
208 /* Counter for labels which are to be placed in .fixup. */
209 int fixuplabelno = 0;
212 /* Bit size of immediate TLS offsets and string from which it is decoded. */
213 int rs6000_tls_size = 32;
214 const char *rs6000_tls_size_string;
216 /* ABI enumeration available for subtarget to use. */
217 enum rs6000_abi rs6000_current_abi;
219 /* ABI string from -mabi= option. */
220 const char *rs6000_abi_string;
222 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
226 const char *rs6000_debug_name;
227 int rs6000_debug_stack; /* debug stack applications */
228 int rs6000_debug_arg; /* debug argument handling */
230 /* Value is TRUE if register/mode pair is accepatable. */
231 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
234 static GTY(()) tree opaque_V2SI_type_node;
235 static GTY(()) tree opaque_V2SF_type_node;
236 static GTY(()) tree opaque_p_V2SI_type_node;
237 static GTY(()) tree V16QI_type_node;
238 static GTY(()) tree V2SI_type_node;
239 static GTY(()) tree V2SF_type_node;
240 static GTY(()) tree V4HI_type_node;
241 static GTY(()) tree V4SI_type_node;
242 static GTY(()) tree V4SF_type_node;
243 static GTY(()) tree V8HI_type_node;
244 static GTY(()) tree unsigned_V16QI_type_node;
245 static GTY(()) tree unsigned_V8HI_type_node;
246 static GTY(()) tree unsigned_V4SI_type_node;
247 static GTY(()) tree bool_char_type_node; /* __bool char */
248 static GTY(()) tree bool_short_type_node; /* __bool short */
249 static GTY(()) tree bool_int_type_node; /* __bool int */
250 static GTY(()) tree pixel_type_node; /* __pixel */
251 static GTY(()) tree bool_V16QI_type_node; /* __vector __bool char */
252 static GTY(()) tree bool_V8HI_type_node; /* __vector __bool short */
253 static GTY(()) tree bool_V4SI_type_node; /* __vector __bool int */
254 static GTY(()) tree pixel_V8HI_type_node; /* __vector __pixel */
256 int rs6000_warn_altivec_long = 1; /* On by default. */
257 const char *rs6000_warn_altivec_long_switch;
259 const char *rs6000_traceback_name;
261 traceback_default = 0,
267 /* Flag to say the TOC is initialized */
269 char toc_label_name[10];
271 /* Alias set for saves and restores from the rs6000 stack. */
272 static GTY(()) int rs6000_sr_alias_set;
274 /* Call distance, overridden by -mlongcall and #pragma longcall(1).
275 The only place that looks at this is rs6000_set_default_type_attributes;
276 everywhere else should rely on the presence or absence of a longcall
277 attribute on the function declaration. Exception: init_cumulative_args
278 looks at it too, for libcalls. */
279 int rs6000_default_long_calls;
280 const char *rs6000_longcall_switch;
282 /* Control alignment for fields within structures. */
283 /* String from -malign-XXXXX. */
284 const char *rs6000_alignment_string;
285 int rs6000_alignment_flags;
287 struct builtin_description
289 /* mask is not const because we're going to alter it below. This
290 nonsense will go away when we rewrite the -march infrastructure
291 to give us more target flag bits. */
293 const enum insn_code icode;
294 const char *const name;
295 const enum rs6000_builtins code;
298 /* Target cpu costs. */
300 struct processor_costs {
301 const int mulsi; /* cost of SImode multiplication. */
302 const int mulsi_const; /* cost of SImode multiplication by constant. */
303 const int mulsi_const9; /* cost of SImode mult by short constant. */
304 const int muldi; /* cost of DImode multiplication. */
305 const int divsi; /* cost of SImode division. */
306 const int divdi; /* cost of DImode division. */
307 const int fp; /* cost of simple SFmode and DFmode insns. */
308 const int dmul; /* cost of DFmode multiplication (and fmadd). */
309 const int sdiv; /* cost of SFmode division (fdivs). */
310 const int ddiv; /* cost of DFmode division (fdiv). */
313 const struct processor_costs *rs6000_cost;
315 /* Processor costs (relative to an add) */
317 /* Instruction size costs on 32bit processors. */
319 struct processor_costs size32_cost = {
320 COSTS_N_INSNS (1), /* mulsi */
321 COSTS_N_INSNS (1), /* mulsi_const */
322 COSTS_N_INSNS (1), /* mulsi_const9 */
323 COSTS_N_INSNS (1), /* muldi */
324 COSTS_N_INSNS (1), /* divsi */
325 COSTS_N_INSNS (1), /* divdi */
326 COSTS_N_INSNS (1), /* fp */
327 COSTS_N_INSNS (1), /* dmul */
328 COSTS_N_INSNS (1), /* sdiv */
329 COSTS_N_INSNS (1), /* ddiv */
332 /* Instruction size costs on 64bit processors. */
334 struct processor_costs size64_cost = {
335 COSTS_N_INSNS (1), /* mulsi */
336 COSTS_N_INSNS (1), /* mulsi_const */
337 COSTS_N_INSNS (1), /* mulsi_const9 */
338 COSTS_N_INSNS (1), /* muldi */
339 COSTS_N_INSNS (1), /* divsi */
340 COSTS_N_INSNS (1), /* divdi */
341 COSTS_N_INSNS (1), /* fp */
342 COSTS_N_INSNS (1), /* dmul */
343 COSTS_N_INSNS (1), /* sdiv */
344 COSTS_N_INSNS (1), /* ddiv */
347 /* Instruction costs on RIOS1 processors. */
349 struct processor_costs rios1_cost = {
350 COSTS_N_INSNS (5), /* mulsi */
351 COSTS_N_INSNS (4), /* mulsi_const */
352 COSTS_N_INSNS (3), /* mulsi_const9 */
353 COSTS_N_INSNS (5), /* muldi */
354 COSTS_N_INSNS (19), /* divsi */
355 COSTS_N_INSNS (19), /* divdi */
356 COSTS_N_INSNS (2), /* fp */
357 COSTS_N_INSNS (2), /* dmul */
358 COSTS_N_INSNS (19), /* sdiv */
359 COSTS_N_INSNS (19), /* ddiv */
362 /* Instruction costs on RIOS2 processors. */
364 struct processor_costs rios2_cost = {
365 COSTS_N_INSNS (2), /* mulsi */
366 COSTS_N_INSNS (2), /* mulsi_const */
367 COSTS_N_INSNS (2), /* mulsi_const9 */
368 COSTS_N_INSNS (2), /* muldi */
369 COSTS_N_INSNS (13), /* divsi */
370 COSTS_N_INSNS (13), /* divdi */
371 COSTS_N_INSNS (2), /* fp */
372 COSTS_N_INSNS (2), /* dmul */
373 COSTS_N_INSNS (17), /* sdiv */
374 COSTS_N_INSNS (17), /* ddiv */
377 /* Instruction costs on RS64A processors. */
379 struct processor_costs rs64a_cost = {
380 COSTS_N_INSNS (20), /* mulsi */
381 COSTS_N_INSNS (12), /* mulsi_const */
382 COSTS_N_INSNS (8), /* mulsi_const9 */
383 COSTS_N_INSNS (34), /* muldi */
384 COSTS_N_INSNS (65), /* divsi */
385 COSTS_N_INSNS (67), /* divdi */
386 COSTS_N_INSNS (4), /* fp */
387 COSTS_N_INSNS (4), /* dmul */
388 COSTS_N_INSNS (31), /* sdiv */
389 COSTS_N_INSNS (31), /* ddiv */
392 /* Instruction costs on MPCCORE processors. */
394 struct processor_costs mpccore_cost = {
395 COSTS_N_INSNS (2), /* mulsi */
396 COSTS_N_INSNS (2), /* mulsi_const */
397 COSTS_N_INSNS (2), /* mulsi_const9 */
398 COSTS_N_INSNS (2), /* muldi */
399 COSTS_N_INSNS (6), /* divsi */
400 COSTS_N_INSNS (6), /* divdi */
401 COSTS_N_INSNS (4), /* fp */
402 COSTS_N_INSNS (5), /* dmul */
403 COSTS_N_INSNS (10), /* sdiv */
404 COSTS_N_INSNS (17), /* ddiv */
407 /* Instruction costs on PPC403 processors. */
409 struct processor_costs ppc403_cost = {
410 COSTS_N_INSNS (4), /* mulsi */
411 COSTS_N_INSNS (4), /* mulsi_const */
412 COSTS_N_INSNS (4), /* mulsi_const9 */
413 COSTS_N_INSNS (4), /* muldi */
414 COSTS_N_INSNS (33), /* divsi */
415 COSTS_N_INSNS (33), /* divdi */
416 COSTS_N_INSNS (11), /* fp */
417 COSTS_N_INSNS (11), /* dmul */
418 COSTS_N_INSNS (11), /* sdiv */
419 COSTS_N_INSNS (11), /* ddiv */
422 /* Instruction costs on PPC405 processors. */
424 struct processor_costs ppc405_cost = {
425 COSTS_N_INSNS (5), /* mulsi */
426 COSTS_N_INSNS (4), /* mulsi_const */
427 COSTS_N_INSNS (3), /* mulsi_const9 */
428 COSTS_N_INSNS (5), /* muldi */
429 COSTS_N_INSNS (35), /* divsi */
430 COSTS_N_INSNS (35), /* divdi */
431 COSTS_N_INSNS (11), /* fp */
432 COSTS_N_INSNS (11), /* dmul */
433 COSTS_N_INSNS (11), /* sdiv */
434 COSTS_N_INSNS (11), /* ddiv */
437 /* Instruction costs on PPC440 processors. */
439 struct processor_costs ppc440_cost = {
440 COSTS_N_INSNS (3), /* mulsi */
441 COSTS_N_INSNS (2), /* mulsi_const */
442 COSTS_N_INSNS (2), /* mulsi_const9 */
443 COSTS_N_INSNS (3), /* muldi */
444 COSTS_N_INSNS (34), /* divsi */
445 COSTS_N_INSNS (34), /* divdi */
446 COSTS_N_INSNS (5), /* fp */
447 COSTS_N_INSNS (5), /* dmul */
448 COSTS_N_INSNS (19), /* sdiv */
449 COSTS_N_INSNS (33), /* ddiv */
452 /* Instruction costs on PPC601 processors. */
454 struct processor_costs ppc601_cost = {
455 COSTS_N_INSNS (5), /* mulsi */
456 COSTS_N_INSNS (5), /* mulsi_const */
457 COSTS_N_INSNS (5), /* mulsi_const9 */
458 COSTS_N_INSNS (5), /* muldi */
459 COSTS_N_INSNS (36), /* divsi */
460 COSTS_N_INSNS (36), /* divdi */
461 COSTS_N_INSNS (4), /* fp */
462 COSTS_N_INSNS (5), /* dmul */
463 COSTS_N_INSNS (17), /* sdiv */
464 COSTS_N_INSNS (31), /* ddiv */
467 /* Instruction costs on PPC603 processors. */
469 struct processor_costs ppc603_cost = {
470 COSTS_N_INSNS (5), /* mulsi */
471 COSTS_N_INSNS (3), /* mulsi_const */
472 COSTS_N_INSNS (2), /* mulsi_const9 */
473 COSTS_N_INSNS (5), /* muldi */
474 COSTS_N_INSNS (37), /* divsi */
475 COSTS_N_INSNS (37), /* divdi */
476 COSTS_N_INSNS (3), /* fp */
477 COSTS_N_INSNS (4), /* dmul */
478 COSTS_N_INSNS (18), /* sdiv */
479 COSTS_N_INSNS (33), /* ddiv */
482 /* Instruction costs on PPC604 processors. */
484 struct processor_costs ppc604_cost = {
485 COSTS_N_INSNS (4), /* mulsi */
486 COSTS_N_INSNS (4), /* mulsi_const */
487 COSTS_N_INSNS (4), /* mulsi_const9 */
488 COSTS_N_INSNS (4), /* muldi */
489 COSTS_N_INSNS (20), /* divsi */
490 COSTS_N_INSNS (20), /* divdi */
491 COSTS_N_INSNS (3), /* fp */
492 COSTS_N_INSNS (3), /* dmul */
493 COSTS_N_INSNS (18), /* sdiv */
494 COSTS_N_INSNS (32), /* ddiv */
497 /* Instruction costs on PPC604e processors. */
499 struct processor_costs ppc604e_cost = {
500 COSTS_N_INSNS (2), /* mulsi */
501 COSTS_N_INSNS (2), /* mulsi_const */
502 COSTS_N_INSNS (2), /* mulsi_const9 */
503 COSTS_N_INSNS (2), /* muldi */
504 COSTS_N_INSNS (20), /* divsi */
505 COSTS_N_INSNS (20), /* divdi */
506 COSTS_N_INSNS (3), /* fp */
507 COSTS_N_INSNS (3), /* dmul */
508 COSTS_N_INSNS (18), /* sdiv */
509 COSTS_N_INSNS (32), /* ddiv */
512 /* Instruction costs on PPC620 processors. */
514 struct processor_costs ppc620_cost = {
515 COSTS_N_INSNS (5), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (3), /* mulsi_const9 */
518 COSTS_N_INSNS (7), /* muldi */
519 COSTS_N_INSNS (21), /* divsi */
520 COSTS_N_INSNS (37), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
527 /* Instruction costs on PPC630 processors. */
529 struct processor_costs ppc630_cost = {
530 COSTS_N_INSNS (5), /* mulsi */
531 COSTS_N_INSNS (4), /* mulsi_const */
532 COSTS_N_INSNS (3), /* mulsi_const9 */
533 COSTS_N_INSNS (7), /* muldi */
534 COSTS_N_INSNS (21), /* divsi */
535 COSTS_N_INSNS (37), /* divdi */
536 COSTS_N_INSNS (3), /* fp */
537 COSTS_N_INSNS (3), /* dmul */
538 COSTS_N_INSNS (17), /* sdiv */
539 COSTS_N_INSNS (21), /* ddiv */
542 /* Instruction costs on PPC750 and PPC7400 processors. */
544 struct processor_costs ppc750_cost = {
545 COSTS_N_INSNS (5), /* mulsi */
546 COSTS_N_INSNS (3), /* mulsi_const */
547 COSTS_N_INSNS (2), /* mulsi_const9 */
548 COSTS_N_INSNS (5), /* muldi */
549 COSTS_N_INSNS (17), /* divsi */
550 COSTS_N_INSNS (17), /* divdi */
551 COSTS_N_INSNS (3), /* fp */
552 COSTS_N_INSNS (3), /* dmul */
553 COSTS_N_INSNS (17), /* sdiv */
554 COSTS_N_INSNS (31), /* ddiv */
557 /* Instruction costs on PPC7450 processors. */
559 struct processor_costs ppc7450_cost = {
560 COSTS_N_INSNS (4), /* mulsi */
561 COSTS_N_INSNS (3), /* mulsi_const */
562 COSTS_N_INSNS (3), /* mulsi_const9 */
563 COSTS_N_INSNS (4), /* muldi */
564 COSTS_N_INSNS (23), /* divsi */
565 COSTS_N_INSNS (23), /* divdi */
566 COSTS_N_INSNS (5), /* fp */
567 COSTS_N_INSNS (5), /* dmul */
568 COSTS_N_INSNS (21), /* sdiv */
569 COSTS_N_INSNS (35), /* ddiv */
572 /* Instruction costs on PPC8540 processors. */
574 struct processor_costs ppc8540_cost = {
575 COSTS_N_INSNS (4), /* mulsi */
576 COSTS_N_INSNS (4), /* mulsi_const */
577 COSTS_N_INSNS (4), /* mulsi_const9 */
578 COSTS_N_INSNS (4), /* muldi */
579 COSTS_N_INSNS (19), /* divsi */
580 COSTS_N_INSNS (19), /* divdi */
581 COSTS_N_INSNS (4), /* fp */
582 COSTS_N_INSNS (4), /* dmul */
583 COSTS_N_INSNS (29), /* sdiv */
584 COSTS_N_INSNS (29), /* ddiv */
587 /* Instruction costs on POWER4 and POWER5 processors. */
589 struct processor_costs power4_cost = {
590 COSTS_N_INSNS (3), /* mulsi */
591 COSTS_N_INSNS (2), /* mulsi_const */
592 COSTS_N_INSNS (2), /* mulsi_const9 */
593 COSTS_N_INSNS (4), /* muldi */
594 COSTS_N_INSNS (18), /* divsi */
595 COSTS_N_INSNS (34), /* divdi */
596 COSTS_N_INSNS (3), /* fp */
597 COSTS_N_INSNS (3), /* dmul */
598 COSTS_N_INSNS (17), /* sdiv */
599 COSTS_N_INSNS (17), /* ddiv */
603 static bool rs6000_function_ok_for_sibcall (tree, tree);
604 static rtx rs6000_generate_compare (enum rtx_code);
605 static void rs6000_maybe_dead (rtx);
606 static void rs6000_emit_stack_tie (void);
607 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
608 static rtx spe_synthesize_frame_save (rtx);
609 static bool spe_func_has_64bit_regs_p (void);
610 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
612 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
613 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
614 static unsigned rs6000_hash_constant (rtx);
615 static unsigned toc_hash_function (const void *);
616 static int toc_hash_eq (const void *, const void *);
617 static int constant_pool_expr_1 (rtx, int *, int *);
618 static bool constant_pool_expr_p (rtx);
619 static bool legitimate_small_data_p (enum machine_mode, rtx);
620 static bool legitimate_indexed_address_p (rtx, int);
621 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
622 static struct machine_function * rs6000_init_machine_status (void);
623 static bool rs6000_assemble_integer (rtx, unsigned int, int);
624 #ifdef HAVE_GAS_HIDDEN
625 static void rs6000_assemble_visibility (tree, int);
627 static int rs6000_ra_ever_killed (void);
628 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
629 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
630 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
631 static const char *rs6000_mangle_fundamental_type (tree);
632 extern const struct attribute_spec rs6000_attribute_table[];
633 static void rs6000_set_default_type_attributes (tree);
634 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
635 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
636 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
638 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
639 static bool rs6000_return_in_memory (tree, tree);
640 static void rs6000_file_start (void);
642 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
643 static void rs6000_elf_asm_out_constructor (rtx, int);
644 static void rs6000_elf_asm_out_destructor (rtx, int);
645 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
646 static void rs6000_elf_unique_section (tree, int);
647 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
648 unsigned HOST_WIDE_INT);
649 static void rs6000_elf_encode_section_info (tree, rtx, int)
651 static bool rs6000_elf_in_small_data_p (tree);
654 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
655 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
656 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
657 static void rs6000_xcoff_unique_section (tree, int);
658 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
659 unsigned HOST_WIDE_INT);
660 static const char * rs6000_xcoff_strip_name_encoding (const char *);
661 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
662 static void rs6000_xcoff_file_start (void);
663 static void rs6000_xcoff_file_end (void);
666 static bool rs6000_binds_local_p (tree);
668 static int rs6000_variable_issue (FILE *, int, rtx, int);
669 static bool rs6000_rtx_costs (rtx, int, int, int *);
670 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
671 static bool is_microcoded_insn (rtx);
672 static int is_dispatch_slot_restricted (rtx);
673 static bool is_cracked_insn (rtx);
674 static bool is_branch_slot_insn (rtx);
675 static int rs6000_adjust_priority (rtx, int);
676 static int rs6000_issue_rate (void);
677 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
678 static rtx get_next_active_insn (rtx, rtx);
679 static bool insn_terminates_group_p (rtx , enum group_termination);
680 static bool is_costly_group (rtx *, rtx);
681 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
682 static int redefine_groups (FILE *, int, rtx, rtx);
683 static int pad_groups (FILE *, int, rtx, rtx);
684 static void rs6000_sched_finish (FILE *, int);
685 static int rs6000_use_sched_lookahead (void);
686 static tree rs6000_builtin_mask_for_load (void);
688 static void rs6000_init_builtins (void);
689 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
690 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
691 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
692 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
693 static void altivec_init_builtins (void);
694 static void rs6000_common_init_builtins (void);
695 static void rs6000_init_libfuncs (void);
697 static void enable_mask_for_builtins (struct builtin_description *, int,
698 enum rs6000_builtins,
699 enum rs6000_builtins);
700 static tree build_opaque_vector_type (tree, int);
701 static void spe_init_builtins (void);
702 static rtx spe_expand_builtin (tree, rtx, bool *);
703 static rtx spe_expand_stv_builtin (enum insn_code, tree);
704 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
705 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
706 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
707 static rs6000_stack_t *rs6000_stack_info (void);
708 static void debug_stack_info (rs6000_stack_t *);
710 static rtx altivec_expand_builtin (tree, rtx, bool *);
711 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
712 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
713 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
714 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
715 static rtx altivec_expand_predicate_builtin (enum insn_code,
716 const char *, tree, rtx);
717 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
718 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
719 static void rs6000_parse_abi_options (void);
720 static void rs6000_parse_alignment_option (void);
721 static void rs6000_parse_tls_size_option (void);
722 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
723 static void rs6000_parse_float_gprs_option (void);
724 static int first_altivec_reg_to_save (void);
725 static unsigned int compute_vrsave_mask (void);
726 static void compute_save_world_info (rs6000_stack_t *info_ptr);
727 static void is_altivec_return_reg (rtx, void *);
728 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
729 int easy_vector_constant (rtx, enum machine_mode);
730 static bool is_ev64_opaque_type (tree);
731 static rtx rs6000_dwarf_register_span (rtx);
732 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
733 static rtx rs6000_tls_get_addr (void);
734 static rtx rs6000_got_sym (void);
735 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
736 static const char *rs6000_get_some_local_dynamic_name (void);
737 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
738 static rtx rs6000_complex_function_value (enum machine_mode);
739 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
740 enum machine_mode, tree);
741 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
743 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
744 tree, HOST_WIDE_INT);
745 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
748 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
751 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
752 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
753 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
754 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
755 enum machine_mode, tree,
757 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
759 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
761 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
763 static void macho_branch_islands (void);
764 static void add_compiler_branch_island (tree, tree, int);
765 static int no_previous_def (tree function_name);
766 static tree get_prev_label (tree function_name);
767 static void rs6000_darwin_file_start (void);
770 static tree rs6000_build_builtin_va_list (void);
771 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
772 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
773 static bool rs6000_vector_mode_supported_p (enum machine_mode);
774 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
776 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
778 static int get_vsel_insn (enum machine_mode);
779 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
782 const int INSN_NOT_AVAILABLE = -1;
783 static enum machine_mode rs6000_eh_return_filter_mode (void);
785 /* Hash table stuff for keeping track of TOC entries. */
787 struct toc_hash_struct GTY(())
789 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
790 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
792 enum machine_mode key_mode;
796 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
798 /* Default register names. */
799 char rs6000_reg_names[][8] =
801 "0", "1", "2", "3", "4", "5", "6", "7",
802 "8", "9", "10", "11", "12", "13", "14", "15",
803 "16", "17", "18", "19", "20", "21", "22", "23",
804 "24", "25", "26", "27", "28", "29", "30", "31",
805 "0", "1", "2", "3", "4", "5", "6", "7",
806 "8", "9", "10", "11", "12", "13", "14", "15",
807 "16", "17", "18", "19", "20", "21", "22", "23",
808 "24", "25", "26", "27", "28", "29", "30", "31",
809 "mq", "lr", "ctr","ap",
810 "0", "1", "2", "3", "4", "5", "6", "7",
812 /* AltiVec registers. */
813 "0", "1", "2", "3", "4", "5", "6", "7",
814 "8", "9", "10", "11", "12", "13", "14", "15",
815 "16", "17", "18", "19", "20", "21", "22", "23",
816 "24", "25", "26", "27", "28", "29", "30", "31",
822 #ifdef TARGET_REGNAMES
823 static const char alt_reg_names[][8] =
825 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
826 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
827 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
828 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
829 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
830 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
831 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
832 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
833 "mq", "lr", "ctr", "ap",
834 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
836 /* AltiVec registers. */
837 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
838 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
839 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
840 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
847 #ifndef MASK_STRICT_ALIGN
848 #define MASK_STRICT_ALIGN 0
850 #ifndef TARGET_PROFILE_KERNEL
851 #define TARGET_PROFILE_KERNEL 0
854 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
855 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
857 /* Initialize the GCC target structure. */
858 #undef TARGET_ATTRIBUTE_TABLE
859 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
860 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
861 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
863 #undef TARGET_ASM_ALIGNED_DI_OP
864 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
866 /* Default unaligned ops are only provided for ELF. Find the ops needed
867 for non-ELF systems. */
868 #ifndef OBJECT_FORMAT_ELF
870 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
872 #undef TARGET_ASM_UNALIGNED_HI_OP
873 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
874 #undef TARGET_ASM_UNALIGNED_SI_OP
875 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
876 #undef TARGET_ASM_UNALIGNED_DI_OP
877 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
880 #undef TARGET_ASM_UNALIGNED_HI_OP
881 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
882 #undef TARGET_ASM_UNALIGNED_SI_OP
883 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
884 #undef TARGET_ASM_UNALIGNED_DI_OP
885 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
886 #undef TARGET_ASM_ALIGNED_DI_OP
887 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
891 /* This hook deals with fixups for relocatable code and DI-mode objects
893 #undef TARGET_ASM_INTEGER
894 #define TARGET_ASM_INTEGER rs6000_assemble_integer
896 #ifdef HAVE_GAS_HIDDEN
897 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
898 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
901 #undef TARGET_HAVE_TLS
902 #define TARGET_HAVE_TLS HAVE_AS_TLS
904 #undef TARGET_CANNOT_FORCE_CONST_MEM
905 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
907 #undef TARGET_ASM_FUNCTION_PROLOGUE
908 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
909 #undef TARGET_ASM_FUNCTION_EPILOGUE
910 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
912 #undef TARGET_SCHED_VARIABLE_ISSUE
913 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
915 #undef TARGET_SCHED_ISSUE_RATE
916 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
917 #undef TARGET_SCHED_ADJUST_COST
918 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
919 #undef TARGET_SCHED_ADJUST_PRIORITY
920 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
921 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
922 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
923 #undef TARGET_SCHED_FINISH
924 #define TARGET_SCHED_FINISH rs6000_sched_finish
926 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
927 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
929 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
930 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
932 #undef TARGET_INIT_BUILTINS
933 #define TARGET_INIT_BUILTINS rs6000_init_builtins
935 #undef TARGET_EXPAND_BUILTIN
936 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
938 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
939 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
941 #undef TARGET_INIT_LIBFUNCS
942 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
945 #undef TARGET_BINDS_LOCAL_P
946 #define TARGET_BINDS_LOCAL_P rs6000_binds_local_p
949 #undef TARGET_ASM_OUTPUT_MI_THUNK
950 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
952 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
953 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
955 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
956 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
958 #undef TARGET_RTX_COSTS
959 #define TARGET_RTX_COSTS rs6000_rtx_costs
960 #undef TARGET_ADDRESS_COST
961 #define TARGET_ADDRESS_COST hook_int_rtx_0
963 #undef TARGET_VECTOR_OPAQUE_P
964 #define TARGET_VECTOR_OPAQUE_P is_ev64_opaque_type
966 #undef TARGET_DWARF_REGISTER_SPAN
967 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
969 /* On rs6000, function arguments are promoted, as are function return
971 #undef TARGET_PROMOTE_FUNCTION_ARGS
972 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
973 #undef TARGET_PROMOTE_FUNCTION_RETURN
974 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
976 #undef TARGET_RETURN_IN_MEMORY
977 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
979 #undef TARGET_SETUP_INCOMING_VARARGS
980 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
982 /* Always strict argument naming on rs6000. */
983 #undef TARGET_STRICT_ARGUMENT_NAMING
984 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
985 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
986 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
987 #undef TARGET_SPLIT_COMPLEX_ARG
988 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
989 #undef TARGET_MUST_PASS_IN_STACK
990 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
991 #undef TARGET_PASS_BY_REFERENCE
992 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
993 #undef TARGET_ARG_PARTIAL_BYTES
994 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
996 #undef TARGET_BUILD_BUILTIN_VA_LIST
997 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
999 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1000 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1002 #undef TARGET_EH_RETURN_FILTER_MODE
1003 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1005 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1006 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1008 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1009 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1011 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1012 The PowerPC architecture requires only weak consistency among
1013 processors--that is, memory accesses between processors need not be
1014 sequentially consistent and memory accesses among processors can occur
1015 in any order. The ability to order memory accesses weakly provides
1016 opportunities for more efficient use of the system bus. Unless a
1017 dependency exists, the 604e allows read operations to precede store
1019 #undef TARGET_RELAXED_ORDERING
1020 #define TARGET_RELAXED_ORDERING true
1022 struct gcc_target targetm = TARGET_INITIALIZER;
1025 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1028 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1030 /* The GPRs can hold any mode, but values bigger than one register
1031 cannot go past R31. */
1032 if (INT_REGNO_P (regno))
1033 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1035 /* The float registers can only hold floating modes and DImode. */
1036 if (FP_REGNO_P (regno))
1038 (GET_MODE_CLASS (mode) == MODE_FLOAT
1039 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1040 || (GET_MODE_CLASS (mode) == MODE_INT
1041 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1043 /* The CR register can only hold CC modes. */
1044 if (CR_REGNO_P (regno))
1045 return GET_MODE_CLASS (mode) == MODE_CC;
1047 if (XER_REGNO_P (regno))
1048 return mode == PSImode;
1050 /* AltiVec only in AldyVec registers. */
1051 if (ALTIVEC_REGNO_P (regno))
1052 return ALTIVEC_VECTOR_MODE (mode);
1054 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1055 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1058 /* We cannot put TImode anywhere except general register and it must be
1059 able to fit within the register set. */
1061 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1064 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1066 rs6000_init_hard_regno_mode_ok (void)
1070 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1071 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1072 if (rs6000_hard_regno_mode_ok (r, m))
1073 rs6000_hard_regno_mode_ok_p[m][r] = true;
1076 /* If not otherwise specified by a target, make 'long double' equivalent to
1079 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1080 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1083 /* Override command line options. Mostly we process the processor
1084 type and sometimes adjust other TARGET_ options. */
1087 rs6000_override_options (const char *default_cpu)
1090 struct rs6000_cpu_select *ptr;
1093 /* Simplifications for entries below. */
1096 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1097 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1100 /* This table occasionally claims that a processor does not support
1101 a particular feature even though it does, but the feature is slower
1102 than the alternative. Thus, it shouldn't be relied on as a
1103 complete description of the processor's support.
1105 Please keep this list in order, and don't forget to update the
1106 documentation in invoke.texi when adding a new processor or
1110 const char *const name; /* Canonical processor name. */
1111 const enum processor_type processor; /* Processor type enum value. */
1112 const int target_enable; /* Target flags to enable. */
1113 } const processor_target_table[]
1114 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1115 {"403", PROCESSOR_PPC403,
1116 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1117 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1118 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1119 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1120 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1121 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1122 {"601", PROCESSOR_PPC601,
1123 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1124 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1125 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1126 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1128 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1129 {"620", PROCESSOR_PPC620,
1130 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1131 {"630", PROCESSOR_PPC630,
1132 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1133 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1135 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1136 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1137 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1138 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1139 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1140 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1141 /* 8548 has a dummy entry for now. */
1142 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1143 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1144 {"970", PROCESSOR_POWER4,
1145 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1146 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1147 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1148 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1149 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1150 {"G5", PROCESSOR_POWER4,
1151 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1153 {"power2", PROCESSOR_POWER,
1154 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1155 {"power3", PROCESSOR_PPC630,
1156 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1157 {"power4", PROCESSOR_POWER4,
1158 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1159 {"power5", PROCESSOR_POWER5,
1160 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1161 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1162 {"powerpc64", PROCESSOR_POWERPC64,
1163 POWERPC_BASE_MASK | MASK_POWERPC64},
1164 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1165 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1166 {"rios2", PROCESSOR_RIOS2,
1167 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1168 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1169 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1170 {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
1173 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1175 /* Some OSs don't support saving the high part of 64-bit registers on
1176 context switch. Other OSs don't support saving Altivec registers.
1177 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1178 settings; if the user wants either, the user must explicitly specify
1179 them and we won't interfere with the user's specification. */
1182 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1183 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1184 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1188 rs6000_init_hard_regno_mode_ok ();
1190 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1191 #ifdef OS_MISSING_POWERPC64
1192 if (OS_MISSING_POWERPC64)
1193 set_masks &= ~MASK_POWERPC64;
1195 #ifdef OS_MISSING_ALTIVEC
1196 if (OS_MISSING_ALTIVEC)
1197 set_masks &= ~MASK_ALTIVEC;
1200 /* Don't override by the processor default if given explicitly. */
1201 set_masks &= ~target_flags_explicit;
1203 /* Identify the processor type. */
1204 rs6000_select[0].string = default_cpu;
1205 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1207 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1209 ptr = &rs6000_select[i];
1210 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1212 for (j = 0; j < ptt_size; j++)
1213 if (! strcmp (ptr->string, processor_target_table[j].name))
1215 if (ptr->set_tune_p)
1216 rs6000_cpu = processor_target_table[j].processor;
1218 if (ptr->set_arch_p)
1220 target_flags &= ~set_masks;
1221 target_flags |= (processor_target_table[j].target_enable
1228 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1235 /* If we are optimizing big endian systems for space, use the load/store
1236 multiple and string instructions. */
1237 if (BYTES_BIG_ENDIAN && optimize_size)
1238 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1240 /* Don't allow -mmultiple or -mstring on little endian systems
1241 unless the cpu is a 750, because the hardware doesn't support the
1242 instructions used in little endian mode, and causes an alignment
1243 trap. The 750 does not cause an alignment trap (except when the
1244 target is unaligned). */
1246 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1248 if (TARGET_MULTIPLE)
1250 target_flags &= ~MASK_MULTIPLE;
1251 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1252 warning ("-mmultiple is not supported on little endian systems");
1257 target_flags &= ~MASK_STRING;
1258 if ((target_flags_explicit & MASK_STRING) != 0)
1259 warning ("-mstring is not supported on little endian systems");
1263 /* Set debug flags */
1264 if (rs6000_debug_name)
1266 if (! strcmp (rs6000_debug_name, "all"))
1267 rs6000_debug_stack = rs6000_debug_arg = 1;
1268 else if (! strcmp (rs6000_debug_name, "stack"))
1269 rs6000_debug_stack = 1;
1270 else if (! strcmp (rs6000_debug_name, "arg"))
1271 rs6000_debug_arg = 1;
1273 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1276 if (rs6000_traceback_name)
1278 if (! strncmp (rs6000_traceback_name, "full", 4))
1279 rs6000_traceback = traceback_full;
1280 else if (! strncmp (rs6000_traceback_name, "part", 4))
1281 rs6000_traceback = traceback_part;
1282 else if (! strncmp (rs6000_traceback_name, "no", 2))
1283 rs6000_traceback = traceback_none;
1285 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1286 rs6000_traceback_name);
1289 /* Set size of long double */
1290 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1291 if (rs6000_long_double_size_string)
1294 int size = strtol (rs6000_long_double_size_string, &tail, 10);
1295 if (*tail != '\0' || (size != 64 && size != 128))
1296 error ("Unknown switch -mlong-double-%s",
1297 rs6000_long_double_size_string);
1299 rs6000_long_double_type_size = size;
1302 /* Set Altivec ABI as default for powerpc64 linux. */
1303 if (TARGET_ELF && TARGET_64BIT)
1305 rs6000_altivec_abi = 1;
1306 rs6000_altivec_vrsave = 1;
1309 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1310 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1312 rs6000_darwin64_abi = 1;
1313 /* Setting to empty string is same as "-mone-byte-bool". */
1315 darwin_one_byte_bool = "";
1317 /* Default to natural alignment, for better performance. */
1318 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1321 /* Handle -mabi= options. */
1322 rs6000_parse_abi_options ();
1324 /* Handle -malign-XXXXX option. */
1325 rs6000_parse_alignment_option ();
1327 rs6000_parse_float_gprs_option ();
1329 /* Handle generic -mFOO=YES/NO options. */
1330 rs6000_parse_yes_no_option ("vrsave", rs6000_altivec_vrsave_string,
1331 &rs6000_altivec_vrsave);
1332 rs6000_parse_yes_no_option ("isel", rs6000_isel_string,
1334 rs6000_parse_yes_no_option ("spe", rs6000_spe_string, &rs6000_spe);
1336 /* Handle -mtls-size option. */
1337 rs6000_parse_tls_size_option ();
1339 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1340 SUBTARGET_OVERRIDE_OPTIONS;
1342 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1343 SUBSUBTARGET_OVERRIDE_OPTIONS;
1345 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1346 SUB3TARGET_OVERRIDE_OPTIONS;
1352 error ("AltiVec and E500 instructions cannot coexist");
1354 /* The e500 does not have string instructions, and we set
1355 MASK_STRING above when optimizing for size. */
1356 if ((target_flags & MASK_STRING) != 0)
1357 target_flags = target_flags & ~MASK_STRING;
1359 /* No SPE means 64-bit long doubles, even if an E500. */
1360 if (rs6000_spe_string != 0
1361 && !strcmp (rs6000_spe_string, "no"))
1362 rs6000_long_double_type_size = 64;
1364 else if (rs6000_select[1].string != NULL)
1366 /* For the powerpc-eabispe configuration, we set all these by
1367 default, so let's unset them if we manually set another
1368 CPU that is not the E500. */
1369 if (rs6000_abi_string == 0)
1371 if (rs6000_spe_string == 0)
1373 if (rs6000_float_gprs_string == 0)
1374 rs6000_float_gprs = 0;
1375 if (rs6000_isel_string == 0)
1377 if (rs6000_long_double_size_string == 0)
1378 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1381 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1382 && rs6000_cpu != PROCESSOR_POWER5);
1383 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1384 || rs6000_cpu == PROCESSOR_POWER5);
1386 /* Handle -m(no-)longcall option. This is a bit of a cheap hack,
1387 using TARGET_OPTIONS to handle a toggle switch, but we're out of
1388 bits in target_flags so TARGET_SWITCHES cannot be used.
1389 Assumption here is that rs6000_longcall_switch points into the
1390 text of the complete option, rather than being a copy, so we can
1391 scan back for the presence or absence of the no- modifier. */
1392 if (rs6000_longcall_switch)
1394 const char *base = rs6000_longcall_switch;
1395 while (base[-1] != 'm') base--;
1397 if (*rs6000_longcall_switch != '\0')
1398 error ("invalid option %qs", base);
1399 rs6000_default_long_calls = (base[0] != 'n');
1402 /* Handle -m(no-)warn-altivec-long similarly. */
1403 if (rs6000_warn_altivec_long_switch)
1405 const char *base = rs6000_warn_altivec_long_switch;
1406 while (base[-1] != 'm') base--;
1408 if (*rs6000_warn_altivec_long_switch != '\0')
1409 error ("invalid option %qs", base);
1410 rs6000_warn_altivec_long = (base[0] != 'n');
1413 /* Handle -mprioritize-restricted-insns option. */
1414 rs6000_sched_restricted_insns_priority
1415 = (rs6000_sched_groups ? 1 : 0);
1416 if (rs6000_sched_restricted_insns_priority_str)
1417 rs6000_sched_restricted_insns_priority =
1418 atoi (rs6000_sched_restricted_insns_priority_str);
1420 /* Handle -msched-costly-dep option. */
1421 rs6000_sched_costly_dep
1422 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1423 if (rs6000_sched_costly_dep_str)
1425 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1426 rs6000_sched_costly_dep = no_dep_costly;
1427 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1428 rs6000_sched_costly_dep = all_deps_costly;
1429 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1430 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1431 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1432 rs6000_sched_costly_dep = store_to_load_dep_costly;
1434 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1437 /* Handle -minsert-sched-nops option. */
1438 rs6000_sched_insert_nops
1439 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1440 if (rs6000_sched_insert_nops_str)
1442 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1443 rs6000_sched_insert_nops = sched_finish_none;
1444 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1445 rs6000_sched_insert_nops = sched_finish_pad_groups;
1446 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1447 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1449 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1452 #ifdef TARGET_REGNAMES
1453 /* If the user desires alternate register names, copy in the
1454 alternate names now. */
1455 if (TARGET_REGNAMES)
1456 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1459 /* Set TARGET_AIX_STRUCT_RET last, after the ABI is determined.
1460 If -maix-struct-return or -msvr4-struct-return was explicitly
1461 used, don't override with the ABI default. */
1462 if ((target_flags_explicit & MASK_AIX_STRUCT_RET) == 0)
1464 if (DEFAULT_ABI == ABI_V4 && !DRAFT_V4_STRUCT_RET)
1465 target_flags = (target_flags & ~MASK_AIX_STRUCT_RET);
1467 target_flags |= MASK_AIX_STRUCT_RET;
1470 if (TARGET_LONG_DOUBLE_128
1471 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1472 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1474 /* Allocate an alias set for register saves & restores from stack. */
1475 rs6000_sr_alias_set = new_alias_set ();
1478 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1480 /* We can only guarantee the availability of DI pseudo-ops when
1481 assembling for 64-bit targets. */
1484 targetm.asm_out.aligned_op.di = NULL;
1485 targetm.asm_out.unaligned_op.di = NULL;
1488 /* Set branch target alignment, if not optimizing for size. */
1491 if (rs6000_sched_groups)
1493 if (align_functions <= 0)
1494 align_functions = 16;
1495 if (align_jumps <= 0)
1497 if (align_loops <= 0)
1500 if (align_jumps_max_skip <= 0)
1501 align_jumps_max_skip = 15;
1502 if (align_loops_max_skip <= 0)
1503 align_loops_max_skip = 15;
1506 /* Arrange to save and restore machine status around nested functions. */
1507 init_machine_status = rs6000_init_machine_status;
1509 /* We should always be splitting complex arguments, but we can't break
1510 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1511 if (DEFAULT_ABI != ABI_AIX)
1512 targetm.calls.split_complex_arg = NULL;
1514 /* Initialize rs6000_cost with the appropriate target costs. */
1516 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1520 case PROCESSOR_RIOS1:
1521 rs6000_cost = &rios1_cost;
1524 case PROCESSOR_RIOS2:
1525 rs6000_cost = &rios2_cost;
1528 case PROCESSOR_RS64A:
1529 rs6000_cost = &rs64a_cost;
1532 case PROCESSOR_MPCCORE:
1533 rs6000_cost = &mpccore_cost;
1536 case PROCESSOR_PPC403:
1537 rs6000_cost = &ppc403_cost;
1540 case PROCESSOR_PPC405:
1541 rs6000_cost = &ppc405_cost;
1544 case PROCESSOR_PPC440:
1545 rs6000_cost = &ppc440_cost;
1548 case PROCESSOR_PPC601:
1549 rs6000_cost = &ppc601_cost;
1552 case PROCESSOR_PPC603:
1553 rs6000_cost = &ppc603_cost;
1556 case PROCESSOR_PPC604:
1557 rs6000_cost = &ppc604_cost;
1560 case PROCESSOR_PPC604e:
1561 rs6000_cost = &ppc604e_cost;
1564 case PROCESSOR_PPC620:
1565 rs6000_cost = &ppc620_cost;
1568 case PROCESSOR_PPC630:
1569 rs6000_cost = &ppc630_cost;
1572 case PROCESSOR_PPC750:
1573 case PROCESSOR_PPC7400:
1574 rs6000_cost = &ppc750_cost;
1577 case PROCESSOR_PPC7450:
1578 rs6000_cost = &ppc7450_cost;
1581 case PROCESSOR_PPC8540:
1582 rs6000_cost = &ppc8540_cost;
1585 case PROCESSOR_POWER4:
1586 case PROCESSOR_POWER5:
1587 rs6000_cost = &power4_cost;
1595 /* Implement targetm.vectorize.builtin_mask_for_load. */
1597 rs6000_builtin_mask_for_load (void)
1600 return altivec_builtin_mask_for_load;
1605 /* Handle generic options of the form -mfoo=yes/no.
1606 NAME is the option name.
1607 VALUE is the option value.
1608 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1609 whether the option value is 'yes' or 'no' respectively. */
1611 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1615 else if (!strcmp (value, "yes"))
1617 else if (!strcmp (value, "no"))
1620 error ("unknown -m%s= option specified: '%s'", name, value);
1623 /* Handle -mabi= options. */
1625 rs6000_parse_abi_options (void)
1627 if (rs6000_abi_string == 0)
1629 else if (! strcmp (rs6000_abi_string, "altivec"))
1631 rs6000_altivec_abi = 1;
1634 else if (! strcmp (rs6000_abi_string, "no-altivec"))
1635 rs6000_altivec_abi = 0;
1636 else if (! strcmp (rs6000_abi_string, "spe"))
1639 rs6000_altivec_abi = 0;
1640 if (!TARGET_SPE_ABI)
1641 error ("not configured for ABI: '%s'", rs6000_abi_string);
1644 /* These are here for testing during development only, do not
1645 document in the manual please. */
1646 else if (! strcmp (rs6000_abi_string, "d64"))
1648 rs6000_darwin64_abi = 1;
1649 warning ("Using darwin64 ABI");
1651 else if (! strcmp (rs6000_abi_string, "d32"))
1653 rs6000_darwin64_abi = 0;
1654 warning ("Using old darwin ABI");
1657 else if (! strcmp (rs6000_abi_string, "no-spe"))
1660 error ("unknown ABI specified: '%s'", rs6000_abi_string);
1663 /* Handle -mfloat-gprs= options. */
1665 rs6000_parse_float_gprs_option (void)
1667 if (rs6000_float_gprs_string == 0)
1669 else if (! strcmp (rs6000_float_gprs_string, "yes")
1670 || ! strcmp (rs6000_float_gprs_string, "single"))
1671 rs6000_float_gprs = 1;
1672 else if (! strcmp (rs6000_float_gprs_string, "double"))
1673 rs6000_float_gprs = 2;
1674 else if (! strcmp (rs6000_float_gprs_string, "no"))
1675 rs6000_float_gprs = 0;
1677 error ("invalid option for -mfloat-gprs");
1680 /* Handle -malign-XXXXXX options. */
1682 rs6000_parse_alignment_option (void)
1684 if (rs6000_alignment_string == 0)
1686 else if (! strcmp (rs6000_alignment_string, "power"))
1688 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1689 some C library functions, so warn about it. The flag may be
1690 useful for performance studies from time to time though, so
1691 don't disable it entirely. */
1692 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1693 warning ("-malign-power is not supported for 64-bit Darwin;"
1694 " it is incompatible with the installed C and C++ libraries");
1695 rs6000_alignment_flags = MASK_ALIGN_POWER;
1697 else if (! strcmp (rs6000_alignment_string, "natural"))
1698 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1700 error ("unknown -malign-XXXXX option specified: '%s'",
1701 rs6000_alignment_string);
1704 /* Validate and record the size specified with the -mtls-size option. */
1707 rs6000_parse_tls_size_option (void)
1709 if (rs6000_tls_size_string == 0)
1711 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1712 rs6000_tls_size = 16;
1713 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1714 rs6000_tls_size = 32;
1715 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1716 rs6000_tls_size = 64;
1718 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1722 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1726 /* Do anything needed at the start of the asm file. */
1729 rs6000_file_start (void)
1733 const char *start = buffer;
1734 struct rs6000_cpu_select *ptr;
1735 const char *default_cpu = TARGET_CPU_DEFAULT;
1736 FILE *file = asm_out_file;
1738 default_file_start ();
1740 #ifdef TARGET_BI_ARCH
1741 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1745 if (flag_verbose_asm)
1747 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1748 rs6000_select[0].string = default_cpu;
1750 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1752 ptr = &rs6000_select[i];
1753 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1755 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1760 #ifdef USING_ELFOS_H
1761 switch (rs6000_sdata)
1763 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1764 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1765 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1766 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1769 if (rs6000_sdata && g_switch_value)
1771 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1781 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1789 /* Return nonzero if this function is known to have a null epilogue. */
1792 direct_return (void)
1794 if (reload_completed)
1796 rs6000_stack_t *info = rs6000_stack_info ();
1798 if (info->first_gp_reg_save == 32
1799 && info->first_fp_reg_save == 64
1800 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1801 && ! info->lr_save_p
1802 && ! info->cr_save_p
1803 && info->vrsave_mask == 0
1811 /* Return the number of instructions it takes to form a constant in an
1812 integer register. */
1815 num_insns_constant_wide (HOST_WIDE_INT value)
1817 /* signed constant loadable with {cal|addi} */
1818 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1821 /* constant loadable with {cau|addis} */
1822 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1825 #if HOST_BITS_PER_WIDE_INT == 64
1826 else if (TARGET_POWERPC64)
1828 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1829 HOST_WIDE_INT high = value >> 31;
1831 if (high == 0 || high == -1)
1837 return num_insns_constant_wide (high) + 1;
1839 return (num_insns_constant_wide (high)
1840 + num_insns_constant_wide (low) + 1);
1849 num_insns_constant (rtx op, enum machine_mode mode)
1851 if (GET_CODE (op) == CONST_INT)
1853 #if HOST_BITS_PER_WIDE_INT == 64
1854 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1855 && mask64_operand (op, mode))
1859 return num_insns_constant_wide (INTVAL (op));
1862 else if (GET_CODE (op) == CONST_DOUBLE && mode == SFmode)
1867 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1868 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1869 return num_insns_constant_wide ((HOST_WIDE_INT) l);
1872 else if (GET_CODE (op) == CONST_DOUBLE)
1878 int endian = (WORDS_BIG_ENDIAN == 0);
1880 if (mode == VOIDmode || mode == DImode)
1882 high = CONST_DOUBLE_HIGH (op);
1883 low = CONST_DOUBLE_LOW (op);
1887 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1888 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
1890 low = l[1 - endian];
1894 return (num_insns_constant_wide (low)
1895 + num_insns_constant_wide (high));
1899 if (high == 0 && low >= 0)
1900 return num_insns_constant_wide (low);
1902 else if (high == -1 && low < 0)
1903 return num_insns_constant_wide (low);
1905 else if (mask64_operand (op, mode))
1909 return num_insns_constant_wide (high) + 1;
1912 return (num_insns_constant_wide (high)
1913 + num_insns_constant_wide (low) + 1);
1921 /* Returns the constant for the splat instruction, if exists. */
1924 easy_vector_splat_const (int cst, enum machine_mode mode)
1929 if (EASY_VECTOR_15 (cst)
1930 || EASY_VECTOR_15_ADD_SELF (cst))
1932 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
1938 if (EASY_VECTOR_15 (cst)
1939 || EASY_VECTOR_15_ADD_SELF (cst))
1941 if ((cst & 0xff) != ((cst >> 8) & 0xff))
1947 if (EASY_VECTOR_15 (cst)
1948 || EASY_VECTOR_15_ADD_SELF (cst))
1956 /* Return nonzero if all elements of a vector have the same value. */
1959 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1963 units = CONST_VECTOR_NUNITS (op);
1965 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
1966 for (i = 1; i < units; ++i)
1967 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
1969 if (i == units && easy_vector_splat_const (cst, mode))
1974 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
1977 gen_easy_vector_constant_add_self (rtx op)
1981 units = GET_MODE_NUNITS (GET_MODE (op));
1982 v = rtvec_alloc (units);
1984 for (i = 0; i < units; i++)
1986 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
1987 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
1991 output_vec_const_move (rtx *operands)
1994 enum machine_mode mode;
2000 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2001 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2002 mode = GET_MODE (dest);
2006 if (zero_constant (vec, mode))
2007 return "vxor %0,%0,%0";
2008 else if (easy_vector_constant (vec, mode))
2010 operands[1] = GEN_INT (cst);
2014 if (EASY_VECTOR_15 (cst))
2016 operands[1] = GEN_INT (cst);
2017 return "vspltisw %0,%1";
2019 else if (EASY_VECTOR_15_ADD_SELF (cst))
2025 if (EASY_VECTOR_15 (cst))
2027 operands[1] = GEN_INT (cst);
2028 return "vspltish %0,%1";
2030 else if (EASY_VECTOR_15_ADD_SELF (cst))
2036 if (EASY_VECTOR_15 (cst))
2038 operands[1] = GEN_INT (cst);
2039 return "vspltisb %0,%1";
2041 else if (EASY_VECTOR_15_ADD_SELF (cst))
2054 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2055 pattern of V1DI, V4HI, and V2SF.
2057 FIXME: We should probably return # and add post reload
2058 splitters for these, but this way is so easy ;-). */
2059 operands[1] = GEN_INT (cst);
2060 operands[2] = GEN_INT (cst2);
2062 return "li %0,%1\n\tevmergelo %0,%0,%0";
2064 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2071 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2074 if (GET_CODE (op) == CONST_INT)
2076 HOST_WIDE_INT c, lsb;
2081 /* Disallow all zeros. */
2085 /* We can use a single rlwinm insn if no upper bits of C are set
2086 AND there are zero, one or two transitions in the _whole_ of
2088 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2090 /* We don't change the number of transitions by inverting,
2091 so make sure we start with the LS bit zero. */
2095 /* Find the first transition. */
2098 /* Invert to look for a second transition. */
2101 /* Erase first transition. */
2104 /* Find the second transition. */
2107 /* Invert to look for a third transition. */
2110 /* Erase second transition. */
2113 if (one_ok && !(allow_one || c))
2116 /* Find the third transition (if any). */
2119 /* Match if all the bits above are 1's (or c is zero). */
2125 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2126 implement ANDing by the mask IN. */
2128 build_mask64_2_operands (rtx in, rtx *out)
2130 #if HOST_BITS_PER_WIDE_INT >= 64
2131 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2134 if (GET_CODE (in) != CONST_INT)
2140 /* Assume c initially something like 0x00fff000000fffff. The idea
2141 is to rotate the word so that the middle ^^^^^^ group of zeros
2142 is at the MS end and can be cleared with an rldicl mask. We then
2143 rotate back and clear off the MS ^^ group of zeros with a
2145 c = ~c; /* c == 0xff000ffffff00000 */
2146 lsb = c & -c; /* lsb == 0x0000000000100000 */
2147 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2148 c = ~c; /* c == 0x00fff000000fffff */
2149 c &= -lsb; /* c == 0x00fff00000000000 */
2150 lsb = c & -c; /* lsb == 0x0000100000000000 */
2151 c = ~c; /* c == 0xff000fffffffffff */
2152 c &= -lsb; /* c == 0xff00000000000000 */
2154 while ((lsb >>= 1) != 0)
2155 shift++; /* shift == 44 on exit from loop */
2156 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2157 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2158 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2162 /* Assume c initially something like 0xff000f0000000000. The idea
2163 is to rotate the word so that the ^^^ middle group of zeros
2164 is at the LS end and can be cleared with an rldicr mask. We then
2165 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2167 lsb = c & -c; /* lsb == 0x0000010000000000 */
2168 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2169 c = ~c; /* c == 0x00fff0ffffffffff */
2170 c &= -lsb; /* c == 0x00fff00000000000 */
2171 lsb = c & -c; /* lsb == 0x0000100000000000 */
2172 c = ~c; /* c == 0xff000fffffffffff */
2173 c &= -lsb; /* c == 0xff00000000000000 */
2175 while ((lsb >>= 1) != 0)
2176 shift++; /* shift == 44 on exit from loop */
2177 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2178 m1 >>= shift; /* m1 == 0x0000000000000fff */
2179 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2182 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2183 masks will be all 1's. We are guaranteed more than one transition. */
2184 out[0] = GEN_INT (64 - shift);
2185 out[1] = GEN_INT (m1);
2186 out[2] = GEN_INT (shift);
2187 out[3] = GEN_INT (m2);
2195 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2198 invalid_e500_subreg (rtx op, enum machine_mode mode)
2200 /* Reject (subreg:SI (reg:DF)). */
2201 if (GET_CODE (op) == SUBREG
2203 && REG_P (SUBREG_REG (op))
2204 && GET_MODE (SUBREG_REG (op)) == DFmode)
2207 /* Reject (subreg:DF (reg:DI)). */
2208 if (GET_CODE (op) == SUBREG
2210 && REG_P (SUBREG_REG (op))
2211 && GET_MODE (SUBREG_REG (op)) == DImode)
2217 /* Darwin, AIX increases natural record alignment to doubleword if the first
2218 field is an FP double while the FP fields remain word aligned. */
2221 rs6000_special_round_type_align (tree type, int computed, int specified)
2223 tree field = TYPE_FIELDS (type);
2225 /* Skip all non field decls */
2226 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2227 field = TREE_CHAIN (field);
2229 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2230 return MAX (computed, specified);
2232 return MAX (MAX (computed, specified), 64);
2235 /* Return 1 for an operand in small memory on V.4/eabi. */
2238 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2239 enum machine_mode mode ATTRIBUTE_UNUSED)
2244 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2247 if (DEFAULT_ABI != ABI_V4)
2250 if (GET_CODE (op) == SYMBOL_REF)
2253 else if (GET_CODE (op) != CONST
2254 || GET_CODE (XEXP (op, 0)) != PLUS
2255 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2256 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2261 rtx sum = XEXP (op, 0);
2262 HOST_WIDE_INT summand;
2264 /* We have to be careful here, because it is the referenced address
2265 that must be 32k from _SDA_BASE_, not just the symbol. */
2266 summand = INTVAL (XEXP (sum, 1));
2267 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2270 sym_ref = XEXP (sum, 0);
2273 return SYMBOL_REF_SMALL_P (sym_ref);
2279 /* Return true, if operand is a memory operand and has a
2280 displacement divisible by 4. */
2283 word_offset_memref_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2288 if (!memory_operand (op, mode))
2291 addr = XEXP (op, 0);
2292 if (GET_CODE (addr) == PLUS
2293 && GET_CODE (XEXP (addr, 0)) == REG
2294 && GET_CODE (XEXP (addr, 1)) == CONST_INT)
2295 off = INTVAL (XEXP (addr, 1));
2297 return (off % 4) == 0;
2300 /* Return true if the operand is an indirect or indexed memory operand. */
2303 indexed_or_indirect_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2306 if (!memory_operand (op, mode))
2309 addr = XEXP (op, 0);
2310 if (GET_CODE (addr) == REG)
2312 if (GET_CODE (addr) == PLUS
2313 && GET_CODE (XEXP (addr, 0)) == REG
2314 && GET_CODE (XEXP (addr, 1)) == REG)
2319 /* Return true if either operand is a general purpose register. */
2322 gpr_or_gpr_p (rtx op0, rtx op1)
2324 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2325 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2329 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2332 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2334 switch (GET_CODE (op))
2337 if (RS6000_SYMBOL_REF_TLS_P (op))
2339 else if (CONSTANT_POOL_ADDRESS_P (op))
2341 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2349 else if (! strcmp (XSTR (op, 0), toc_label_name))
2358 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2359 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2361 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2370 constant_pool_expr_p (rtx op)
2374 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2378 toc_relative_expr_p (rtx op)
2382 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2386 legitimate_constant_pool_address_p (rtx x)
2389 && GET_CODE (x) == PLUS
2390 && GET_CODE (XEXP (x, 0)) == REG
2391 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2392 && constant_pool_expr_p (XEXP (x, 1)));
2396 legitimate_small_data_p (enum machine_mode mode, rtx x)
2398 return (DEFAULT_ABI == ABI_V4
2399 && !flag_pic && !TARGET_TOC
2400 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2401 && small_data_operand (x, mode));
2404 /* SPE offset addressing is limited to 5-bits worth of double words. */
2405 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2408 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2410 unsigned HOST_WIDE_INT offset, extra;
2412 if (GET_CODE (x) != PLUS)
2414 if (GET_CODE (XEXP (x, 0)) != REG)
2416 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2418 if (legitimate_constant_pool_address_p (x))
2420 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2423 offset = INTVAL (XEXP (x, 1));
2431 /* AltiVec vector modes. Only reg+reg addressing is valid here,
2432 which leaves the only valid constant offset of zero, which by
2433 canonicalization rules is also invalid. */
2440 /* SPE vector modes. */
2441 return SPE_CONST_OFFSET_OK (offset);
2444 if (TARGET_E500_DOUBLE)
2445 return SPE_CONST_OFFSET_OK (offset);
2448 /* On e500v2, we may have:
2450 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2452 Which gets addressed with evldd instructions. */
2453 if (TARGET_E500_DOUBLE)
2454 return SPE_CONST_OFFSET_OK (offset);
2456 if (mode == DFmode || !TARGET_POWERPC64)
2458 else if (offset & 3)
2464 if (mode == TFmode || !TARGET_POWERPC64)
2466 else if (offset & 3)
2477 return (offset < 0x10000) && (offset + extra < 0x10000);
2481 legitimate_indexed_address_p (rtx x, int strict)
2485 if (GET_CODE (x) != PLUS)
2491 if (!REG_P (op0) || !REG_P (op1))
2494 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2495 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2496 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2497 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2501 legitimate_indirect_address_p (rtx x, int strict)
2503 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2507 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2509 if (!TARGET_MACHO || !flag_pic
2510 || mode != SImode || GET_CODE (x) != MEM)
2514 if (GET_CODE (x) != LO_SUM)
2516 if (GET_CODE (XEXP (x, 0)) != REG)
2518 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2522 return CONSTANT_P (x);
2526 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2528 if (GET_CODE (x) != LO_SUM)
2530 if (GET_CODE (XEXP (x, 0)) != REG)
2532 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2534 /* Restrict addressing for DI because of our SUBREG hackery. */
2535 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2539 if (TARGET_ELF || TARGET_MACHO)
2541 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2545 if (GET_MODE_NUNITS (mode) != 1)
2547 if (GET_MODE_BITSIZE (mode) > 64
2548 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2549 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2552 return CONSTANT_P (x);
2559 /* Try machine-dependent ways of modifying an illegitimate address
2560 to be legitimate. If we find one, return the new, valid address.
2561 This is used from only one place: `memory_address' in explow.c.
2563 OLDX is the address as it was before break_out_memory_refs was
2564 called. In some cases it is useful to look at this to decide what
2567 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2569 It is always safe for this function to do nothing. It exists to
2570 recognize opportunities to optimize the output.
2572 On RS/6000, first check for the sum of a register with a constant
2573 integer that is out of range. If so, generate code to add the
2574 constant with the low-order 16 bits masked to the register and force
2575 this result into another register (this can be done with `cau').
2576 Then generate an address of REG+(CONST&0xffff), allowing for the
2577 possibility of bit 16 being a one.
2579 Then check for the sum of a register and something not constant, try to
2580 load the other things into a register and return the sum. */
2583 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2584 enum machine_mode mode)
2586 if (GET_CODE (x) == SYMBOL_REF)
2588 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2590 return rs6000_legitimize_tls_address (x, model);
2593 if (GET_CODE (x) == PLUS
2594 && GET_CODE (XEXP (x, 0)) == REG
2595 && GET_CODE (XEXP (x, 1)) == CONST_INT
2596 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2598 HOST_WIDE_INT high_int, low_int;
2600 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2601 high_int = INTVAL (XEXP (x, 1)) - low_int;
2602 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2603 GEN_INT (high_int)), 0);
2604 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2606 else if (GET_CODE (x) == PLUS
2607 && GET_CODE (XEXP (x, 0)) == REG
2608 && GET_CODE (XEXP (x, 1)) != CONST_INT
2609 && GET_MODE_NUNITS (mode) == 1
2610 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2612 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2614 && (TARGET_POWERPC64 || mode != DImode)
2617 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2618 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2620 else if (ALTIVEC_VECTOR_MODE (mode))
2624 /* Make sure both operands are registers. */
2625 if (GET_CODE (x) == PLUS)
2626 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2627 force_reg (Pmode, XEXP (x, 1)));
2629 reg = force_reg (Pmode, x);
2632 else if (SPE_VECTOR_MODE (mode)
2633 || (TARGET_E500_DOUBLE && (mode == DFmode
2634 || mode == DImode)))
2638 /* We accept [reg + reg] and [reg + OFFSET]. */
2640 if (GET_CODE (x) == PLUS)
2642 rtx op1 = XEXP (x, 0);
2643 rtx op2 = XEXP (x, 1);
2645 op1 = force_reg (Pmode, op1);
2647 if (GET_CODE (op2) != REG
2648 && (GET_CODE (op2) != CONST_INT
2649 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2650 op2 = force_reg (Pmode, op2);
2652 return gen_rtx_PLUS (Pmode, op1, op2);
2655 return force_reg (Pmode, x);
2661 && GET_CODE (x) != CONST_INT
2662 && GET_CODE (x) != CONST_DOUBLE
2664 && GET_MODE_NUNITS (mode) == 1
2665 && (GET_MODE_BITSIZE (mode) <= 32
2666 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2668 rtx reg = gen_reg_rtx (Pmode);
2669 emit_insn (gen_elf_high (reg, x));
2670 return gen_rtx_LO_SUM (Pmode, reg, x);
2672 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2675 && ! MACHO_DYNAMIC_NO_PIC_P
2677 && GET_CODE (x) != CONST_INT
2678 && GET_CODE (x) != CONST_DOUBLE
2680 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2684 rtx reg = gen_reg_rtx (Pmode);
2685 emit_insn (gen_macho_high (reg, x));
2686 return gen_rtx_LO_SUM (Pmode, reg, x);
2689 && constant_pool_expr_p (x)
2690 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2692 return create_TOC_reference (x);
2698 /* This is called from dwarf2out.c via ASM_OUTPUT_DWARF_DTPREL.
2699 We need to emit DTP-relative relocations. */
2702 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2707 fputs ("\t.long\t", file);
2710 fputs (DOUBLE_INT_ASM_OP, file);
2715 output_addr_const (file, x);
2716 fputs ("@dtprel+0x8000", file);
2719 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2721 static GTY(()) rtx rs6000_tls_symbol;
2723 rs6000_tls_get_addr (void)
2725 if (!rs6000_tls_symbol)
2726 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2728 return rs6000_tls_symbol;
2731 /* Construct the SYMBOL_REF for TLS GOT references. */
2733 static GTY(()) rtx rs6000_got_symbol;
2735 rs6000_got_sym (void)
2737 if (!rs6000_got_symbol)
2739 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2740 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2741 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2744 return rs6000_got_symbol;
2747 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2748 this (thread-local) address. */
2751 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2755 dest = gen_reg_rtx (Pmode);
2756 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
2762 tlsreg = gen_rtx_REG (Pmode, 13);
2763 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
2767 tlsreg = gen_rtx_REG (Pmode, 2);
2768 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
2772 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
2776 tmp = gen_reg_rtx (Pmode);
2779 tlsreg = gen_rtx_REG (Pmode, 13);
2780 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
2784 tlsreg = gen_rtx_REG (Pmode, 2);
2785 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
2789 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
2791 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
2796 rtx r3, got, tga, tmp1, tmp2, eqv;
2799 got = gen_rtx_REG (Pmode, TOC_REGISTER);
2803 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
2806 rtx gsym = rs6000_got_sym ();
2807 got = gen_reg_rtx (Pmode);
2809 rs6000_emit_move (got, gsym, Pmode);
2813 static int tls_got_labelno = 0;
2814 rtx tempLR, lab, tmp3, mem;
2817 ASM_GENERATE_INTERNAL_LABEL (buf, "LTLS", tls_got_labelno++);
2818 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
2819 tempLR = gen_reg_rtx (Pmode);
2820 tmp1 = gen_reg_rtx (Pmode);
2821 tmp2 = gen_reg_rtx (Pmode);
2822 tmp3 = gen_reg_rtx (Pmode);
2823 mem = gen_const_mem (Pmode, tmp1);
2825 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, lab,
2827 emit_move_insn (tmp1, tempLR);
2828 emit_move_insn (tmp2, mem);
2829 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
2830 last = emit_move_insn (got, tmp3);
2831 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
2833 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
2835 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
2841 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
2843 r3 = gen_rtx_REG (Pmode, 3);
2845 insn = gen_tls_gd_64 (r3, got, addr);
2847 insn = gen_tls_gd_32 (r3, got, addr);
2850 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2851 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2852 insn = emit_call_insn (insn);
2853 CONST_OR_PURE_CALL_P (insn) = 1;
2854 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2855 insn = get_insns ();
2857 emit_libcall_block (insn, dest, r3, addr);
2859 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
2861 r3 = gen_rtx_REG (Pmode, 3);
2863 insn = gen_tls_ld_64 (r3, got);
2865 insn = gen_tls_ld_32 (r3, got);
2868 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
2869 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
2870 insn = emit_call_insn (insn);
2871 CONST_OR_PURE_CALL_P (insn) = 1;
2872 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
2873 insn = get_insns ();
2875 tmp1 = gen_reg_rtx (Pmode);
2876 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
2878 emit_libcall_block (insn, tmp1, r3, eqv);
2879 if (rs6000_tls_size == 16)
2882 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
2884 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
2886 else if (rs6000_tls_size == 32)
2888 tmp2 = gen_reg_rtx (Pmode);
2890 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
2892 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
2895 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
2897 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
2901 tmp2 = gen_reg_rtx (Pmode);
2903 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
2905 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
2907 insn = gen_rtx_SET (Pmode, dest,
2908 gen_rtx_PLUS (Pmode, tmp2, tmp1));
2914 /* IE, or 64 bit offset LE. */
2915 tmp2 = gen_reg_rtx (Pmode);
2917 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
2919 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
2922 insn = gen_tls_tls_64 (dest, tmp2, addr);
2924 insn = gen_tls_tls_32 (dest, tmp2, addr);
2932 /* Return 1 if X contains a thread-local symbol. */
2935 rs6000_tls_referenced_p (rtx x)
2937 if (! TARGET_HAVE_TLS)
2940 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
2943 /* Return 1 if *X is a thread-local symbol. This is the same as
2944 rs6000_tls_symbol_ref except for the type of the unused argument. */
2947 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
2949 return RS6000_SYMBOL_REF_TLS_P (*x);
2952 /* The convention appears to be to define this wherever it is used.
2953 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
2954 is now used here. */
2955 #ifndef REG_MODE_OK_FOR_BASE_P
2956 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
2959 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
2960 replace the input X, or the original X if no replacement is called for.
2961 The output parameter *WIN is 1 if the calling macro should goto WIN,
2964 For RS/6000, we wish to handle large displacements off a base
2965 register by splitting the addend across an addiu/addis and the mem insn.
2966 This cuts number of extra insns needed from 3 to 1.
2968 On Darwin, we use this to generate code for floating point constants.
2969 A movsf_low is generated so we wind up with 2 instructions rather than 3.
2970 The Darwin code is inside #if TARGET_MACHO because only then is
2971 machopic_function_base_name() defined. */
2973 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
2974 int opnum, int type,
2975 int ind_levels ATTRIBUTE_UNUSED, int *win)
2977 /* We must recognize output that we have already generated ourselves. */
2978 if (GET_CODE (x) == PLUS
2979 && GET_CODE (XEXP (x, 0)) == PLUS
2980 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
2981 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2982 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2984 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
2985 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
2986 opnum, (enum reload_type)type);
2992 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
2993 && GET_CODE (x) == LO_SUM
2994 && GET_CODE (XEXP (x, 0)) == PLUS
2995 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
2996 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
2997 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
2998 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
2999 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3000 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3001 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3003 /* Result of previous invocation of this function on Darwin
3004 floating point constant. */
3005 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3006 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3007 opnum, (enum reload_type)type);
3013 /* Force ld/std non-word aligned offset into base register by wrapping
3015 if (GET_CODE (x) == PLUS
3016 && GET_CODE (XEXP (x, 0)) == REG
3017 && REGNO (XEXP (x, 0)) < 32
3018 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3019 && GET_CODE (XEXP (x, 1)) == CONST_INT
3020 && (INTVAL (XEXP (x, 1)) & 3) != 0
3021 && !ALTIVEC_VECTOR_MODE (mode)
3022 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3023 && TARGET_POWERPC64)
3025 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3026 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3027 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3028 opnum, (enum reload_type) type);
3033 if (GET_CODE (x) == PLUS
3034 && GET_CODE (XEXP (x, 0)) == REG
3035 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3036 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3037 && GET_CODE (XEXP (x, 1)) == CONST_INT
3038 && !SPE_VECTOR_MODE (mode)
3039 && !(TARGET_E500_DOUBLE && (mode == DFmode
3041 && !ALTIVEC_VECTOR_MODE (mode))
3043 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3044 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3046 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3048 /* Check for 32-bit overflow. */
3049 if (high + low != val)
3055 /* Reload the high part into a base reg; leave the low part
3056 in the mem directly. */
3058 x = gen_rtx_PLUS (GET_MODE (x),
3059 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3063 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3064 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3065 opnum, (enum reload_type)type);
3071 if (GET_CODE (x) == SYMBOL_REF
3072 && DEFAULT_ABI == ABI_DARWIN
3073 && !ALTIVEC_VECTOR_MODE (mode)
3074 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3075 /* Don't do this for TFmode, since the result isn't offsettable.
3076 The same goes for DImode without 64-bit gprs. */
3078 && (mode != DImode || TARGET_POWERPC64))
3082 rtx offset = gen_rtx_CONST (Pmode,
3083 gen_rtx_MINUS (Pmode, x,
3084 machopic_function_base_sym ()));
3085 x = gen_rtx_LO_SUM (GET_MODE (x),
3086 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3087 gen_rtx_HIGH (Pmode, offset)), offset);
3090 x = gen_rtx_LO_SUM (GET_MODE (x),
3091 gen_rtx_HIGH (Pmode, x), x);
3093 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3094 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3095 opnum, (enum reload_type)type);
3102 && constant_pool_expr_p (x)
3103 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3105 (x) = create_TOC_reference (x);
3113 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3114 that is a valid memory address for an instruction.
3115 The MODE argument is the machine mode for the MEM expression
3116 that wants to use this address.
3118 On the RS/6000, there are four valid address: a SYMBOL_REF that
3119 refers to a constant pool entry of an address (or the sum of it
3120 plus a constant), a short (16-bit signed) constant plus a register,
3121 the sum of two registers, or a register indirect, possibly with an
3122 auto-increment. For DFmode and DImode with a constant plus register,
3123 we must ensure that both words are addressable or PowerPC64 with offset
3126 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3127 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3128 adjacent memory cells are accessed by adding word-sized offsets
3129 during assembly output. */
3131 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3133 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3135 && ALTIVEC_VECTOR_MODE (mode)
3136 && GET_CODE (x) == AND
3137 && GET_CODE (XEXP (x, 1)) == CONST_INT
3138 && INTVAL (XEXP (x, 1)) == -16)
3141 if (RS6000_SYMBOL_REF_TLS_P (x))
3143 if (legitimate_indirect_address_p (x, reg_ok_strict))
3145 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3146 && !ALTIVEC_VECTOR_MODE (mode)
3147 && !SPE_VECTOR_MODE (mode)
3148 /* Restrict addressing for DI because of our SUBREG hackery. */
3149 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3151 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3153 if (legitimate_small_data_p (mode, x))
3155 if (legitimate_constant_pool_address_p (x))
3157 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3159 && GET_CODE (x) == PLUS
3160 && GET_CODE (XEXP (x, 0)) == REG
3161 && (XEXP (x, 0) == virtual_stack_vars_rtx
3162 || XEXP (x, 0) == arg_pointer_rtx)
3163 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3165 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3169 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3171 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3172 && (TARGET_POWERPC64 || mode != DImode)
3173 && legitimate_indexed_address_p (x, reg_ok_strict))
3175 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3180 /* Go to LABEL if ADDR (a legitimate address expression)
3181 has an effect that depends on the machine mode it is used for.
3183 On the RS/6000 this is true of all integral offsets (since AltiVec
3184 modes don't allow them) or is a pre-increment or decrement.
3186 ??? Except that due to conceptual problems in offsettable_address_p
3187 we can't really report the problems of integral offsets. So leave
3188 this assuming that the adjustable offset must be valid for the
3189 sub-words of a TFmode operand, which is what we had before. */
3192 rs6000_mode_dependent_address (rtx addr)
3194 switch (GET_CODE (addr))
3197 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3199 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3200 return val + 12 + 0x8000 >= 0x10000;
3209 return TARGET_UPDATE;
3218 /* Return number of consecutive hard regs needed starting at reg REGNO
3219 to hold something of mode MODE.
3220 This is ordinarily the length in words of a value of mode MODE
3221 but can be less for certain modes in special long registers.
3223 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3224 scalar instructions. The upper 32 bits are only available to the
3227 POWER and PowerPC GPRs hold 32 bits worth;
3228 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3231 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3233 if (FP_REGNO_P (regno))
3234 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3236 if (TARGET_E500_DOUBLE && mode == DFmode)
3239 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3240 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3242 if (ALTIVEC_REGNO_P (regno))
3244 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3246 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3249 /* Change register usage conditional on target flags. */
3251 rs6000_conditional_register_usage (void)
3255 /* Set MQ register fixed (already call_used) if not POWER
3256 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3261 /* 64-bit AIX reserves GPR13 for thread-private data. */
3263 fixed_regs[13] = call_used_regs[13]
3264 = call_really_used_regs[13] = 1;
3266 /* Conditionally disable FPRs. */
3267 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3268 for (i = 32; i < 64; i++)
3269 fixed_regs[i] = call_used_regs[i]
3270 = call_really_used_regs[i] = 1;
3272 if (DEFAULT_ABI == ABI_V4
3273 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3275 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3277 if (DEFAULT_ABI == ABI_V4
3278 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3280 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3281 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3282 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3284 if (DEFAULT_ABI == ABI_DARWIN
3285 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3286 global_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3287 = fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3288 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3289 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3291 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3292 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3293 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3296 global_regs[VSCR_REGNO] = 1;
3300 global_regs[SPEFSCR_REGNO] = 1;
3301 fixed_regs[FIXED_SCRATCH]
3302 = call_used_regs[FIXED_SCRATCH]
3303 = call_really_used_regs[FIXED_SCRATCH] = 1;
3306 if (! TARGET_ALTIVEC)
3308 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3309 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3310 call_really_used_regs[VRSAVE_REGNO] = 1;
3313 if (TARGET_ALTIVEC_ABI)
3314 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3315 call_used_regs[i] = call_really_used_regs[i] = 1;
3318 /* Try to output insns to set TARGET equal to the constant C if it can
3319 be done in less than N insns. Do all computations in MODE.
3320 Returns the place where the output has been placed if it can be
3321 done and the insns have been emitted. If it would take more than N
3322 insns, zero is returned and no insns and emitted. */
3325 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3326 rtx source, int n ATTRIBUTE_UNUSED)
3328 rtx result, insn, set;
3329 HOST_WIDE_INT c0, c1;
3331 if (mode == QImode || mode == HImode)
3334 dest = gen_reg_rtx (mode);
3335 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3338 else if (mode == SImode)
3340 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3342 emit_insn (gen_rtx_SET (VOIDmode, result,
3343 GEN_INT (INTVAL (source)
3344 & (~ (HOST_WIDE_INT) 0xffff))));
3345 emit_insn (gen_rtx_SET (VOIDmode, dest,
3346 gen_rtx_IOR (SImode, result,
3347 GEN_INT (INTVAL (source) & 0xffff))));
3350 else if (mode == DImode)
3352 if (GET_CODE (source) == CONST_INT)
3354 c0 = INTVAL (source);
3357 else if (GET_CODE (source) == CONST_DOUBLE)
3359 #if HOST_BITS_PER_WIDE_INT >= 64
3360 c0 = CONST_DOUBLE_LOW (source);
3363 c0 = CONST_DOUBLE_LOW (source);
3364 c1 = CONST_DOUBLE_HIGH (source);
3370 result = rs6000_emit_set_long_const (dest, c0, c1);
3375 insn = get_last_insn ();
3376 set = single_set (insn);
3377 if (! CONSTANT_P (SET_SRC (set)))
3378 set_unique_reg_note (insn, REG_EQUAL, source);
3383 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3384 fall back to a straight forward decomposition. We do this to avoid
3385 exponential run times encountered when looking for longer sequences
3386 with rs6000_emit_set_const. */
3388 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3390 if (!TARGET_POWERPC64)
3392 rtx operand1, operand2;
3394 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3396 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3398 emit_move_insn (operand1, GEN_INT (c1));
3399 emit_move_insn (operand2, GEN_INT (c2));
3403 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3406 ud2 = (c1 & 0xffff0000) >> 16;
3407 #if HOST_BITS_PER_WIDE_INT >= 64
3411 ud4 = (c2 & 0xffff0000) >> 16;
3413 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3414 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3417 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3419 emit_move_insn (dest, GEN_INT (ud1));
3422 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3423 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3426 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3429 emit_move_insn (dest, GEN_INT (ud2 << 16));
3431 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3433 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3434 || (ud4 == 0 && ! (ud3 & 0x8000)))
3437 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3440 emit_move_insn (dest, GEN_INT (ud3 << 16));
3443 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3444 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3446 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3451 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3454 emit_move_insn (dest, GEN_INT (ud4 << 16));
3457 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3459 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3461 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3462 GEN_INT (ud2 << 16)));
3464 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3470 /* Helper for the following. Get rid of [r+r] memory refs
3471 in cases where it won't work (TImode, TFmode). */
3474 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3476 if (GET_CODE (operands[0]) == MEM
3477 && GET_CODE (XEXP (operands[0], 0)) != REG
3478 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3479 && ! reload_in_progress)
3481 = replace_equiv_address (operands[0],
3482 copy_addr_to_reg (XEXP (operands[0], 0)));
3484 if (GET_CODE (operands[1]) == MEM
3485 && GET_CODE (XEXP (operands[1], 0)) != REG
3486 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3487 && ! reload_in_progress)
3489 = replace_equiv_address (operands[1],
3490 copy_addr_to_reg (XEXP (operands[1], 0)));
3493 /* Emit a move from SOURCE to DEST in mode MODE. */
3495 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3499 operands[1] = source;
3501 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3502 if (GET_CODE (operands[1]) == CONST_DOUBLE
3503 && ! FLOAT_MODE_P (mode)
3504 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3506 /* FIXME. This should never happen. */
3507 /* Since it seems that it does, do the safe thing and convert
3509 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3511 if (GET_CODE (operands[1]) == CONST_DOUBLE
3512 && ! FLOAT_MODE_P (mode)
3513 && ((CONST_DOUBLE_HIGH (operands[1]) == 0
3514 && CONST_DOUBLE_LOW (operands[1]) >= 0)
3515 || (CONST_DOUBLE_HIGH (operands[1]) == -1
3516 && CONST_DOUBLE_LOW (operands[1]) < 0)))
3519 /* Check if GCC is setting up a block move that will end up using FP
3520 registers as temporaries. We must make sure this is acceptable. */
3521 if (GET_CODE (operands[0]) == MEM
3522 && GET_CODE (operands[1]) == MEM
3524 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3525 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3526 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3527 ? 32 : MEM_ALIGN (operands[0])))
3528 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3530 : MEM_ALIGN (operands[1]))))
3531 && ! MEM_VOLATILE_P (operands [0])
3532 && ! MEM_VOLATILE_P (operands [1]))
3534 emit_move_insn (adjust_address (operands[0], SImode, 0),
3535 adjust_address (operands[1], SImode, 0));
3536 emit_move_insn (adjust_address (operands[0], SImode, 4),
3537 adjust_address (operands[1], SImode, 4));
3541 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3542 && !gpc_reg_operand (operands[1], mode))
3543 operands[1] = force_reg (mode, operands[1]);
3545 if (mode == SFmode && ! TARGET_POWERPC
3546 && TARGET_HARD_FLOAT && TARGET_FPRS
3547 && GET_CODE (operands[0]) == MEM)
3551 if (reload_in_progress || reload_completed)
3552 regnum = true_regnum (operands[1]);
3553 else if (GET_CODE (operands[1]) == REG)
3554 regnum = REGNO (operands[1]);
3558 /* If operands[1] is a register, on POWER it may have
3559 double-precision data in it, so truncate it to single
3561 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3564 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3565 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3566 operands[1] = newreg;
3570 /* Recognize the case where operand[1] is a reference to thread-local
3571 data and load its address to a register. */
3572 if (GET_CODE (operands[1]) == SYMBOL_REF)
3574 enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
3576 operands[1] = rs6000_legitimize_tls_address (operands[1], model);
3579 /* Handle the case where reload calls us with an invalid address. */
3580 if (reload_in_progress && mode == Pmode
3581 && (! general_operand (operands[1], mode)
3582 || ! nonimmediate_operand (operands[0], mode)))
3585 /* 128-bit constant floating-point values on Darwin should really be
3586 loaded as two parts. */
3587 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3588 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3589 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3591 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3592 know how to get a DFmode SUBREG of a TFmode. */
3593 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3594 simplify_gen_subreg (DImode, operands[1], mode, 0),
3596 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3597 GET_MODE_SIZE (DImode)),
3598 simplify_gen_subreg (DImode, operands[1], mode,
3599 GET_MODE_SIZE (DImode)),
3604 /* FIXME: In the long term, this switch statement should go away
3605 and be replaced by a sequence of tests based on things like
3611 if (CONSTANT_P (operands[1])
3612 && GET_CODE (operands[1]) != CONST_INT)
3613 operands[1] = force_const_mem (mode, operands[1]);
3617 rs6000_eliminate_indexed_memrefs (operands);
3622 if (CONSTANT_P (operands[1])
3623 && ! easy_fp_constant (operands[1], mode))
3624 operands[1] = force_const_mem (mode, operands[1]);
3635 if (CONSTANT_P (operands[1])
3636 && !easy_vector_constant (operands[1], mode))
3637 operands[1] = force_const_mem (mode, operands[1]);
3642 /* Use default pattern for address of ELF small data */
3645 && DEFAULT_ABI == ABI_V4
3646 && (GET_CODE (operands[1]) == SYMBOL_REF
3647 || GET_CODE (operands[1]) == CONST)
3648 && small_data_operand (operands[1], mode))
3650 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3654 if (DEFAULT_ABI == ABI_V4
3655 && mode == Pmode && mode == SImode
3656 && flag_pic == 1 && got_operand (operands[1], mode))
3658 emit_insn (gen_movsi_got (operands[0], operands[1]));
3662 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3666 && CONSTANT_P (operands[1])
3667 && GET_CODE (operands[1]) != HIGH
3668 && GET_CODE (operands[1]) != CONST_INT)
3670 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3672 /* If this is a function address on -mcall-aixdesc,
3673 convert it to the address of the descriptor. */
3674 if (DEFAULT_ABI == ABI_AIX
3675 && GET_CODE (operands[1]) == SYMBOL_REF
3676 && XSTR (operands[1], 0)[0] == '.')
3678 const char *name = XSTR (operands[1], 0);
3680 while (*name == '.')
3682 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3683 CONSTANT_POOL_ADDRESS_P (new_ref)
3684 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3685 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3686 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3687 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3688 operands[1] = new_ref;
3691 if (DEFAULT_ABI == ABI_DARWIN)
3694 if (MACHO_DYNAMIC_NO_PIC_P)
3696 /* Take care of any required data indirection. */
3697 operands[1] = rs6000_machopic_legitimize_pic_address (
3698 operands[1], mode, operands[0]);
3699 if (operands[0] != operands[1])
3700 emit_insn (gen_rtx_SET (VOIDmode,
3701 operands[0], operands[1]));
3705 emit_insn (gen_macho_high (target, operands[1]));
3706 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3710 emit_insn (gen_elf_high (target, operands[1]));
3711 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3715 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3716 and we have put it in the TOC, we just need to make a TOC-relative
3719 && GET_CODE (operands[1]) == SYMBOL_REF
3720 && constant_pool_expr_p (operands[1])
3721 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
3722 get_pool_mode (operands[1])))
3724 operands[1] = create_TOC_reference (operands[1]);
3726 else if (mode == Pmode
3727 && CONSTANT_P (operands[1])
3728 && ((GET_CODE (operands[1]) != CONST_INT
3729 && ! easy_fp_constant (operands[1], mode))
3730 || (GET_CODE (operands[1]) == CONST_INT
3731 && num_insns_constant (operands[1], mode) > 2)
3732 || (GET_CODE (operands[0]) == REG
3733 && FP_REGNO_P (REGNO (operands[0]))))
3734 && GET_CODE (operands[1]) != HIGH
3735 && ! legitimate_constant_pool_address_p (operands[1])
3736 && ! toc_relative_expr_p (operands[1]))
3738 /* Emit a USE operation so that the constant isn't deleted if
3739 expensive optimizations are turned on because nobody
3740 references it. This should only be done for operands that
3741 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
3742 This should not be done for operands that contain LABEL_REFs.
3743 For now, we just handle the obvious case. */
3744 if (GET_CODE (operands[1]) != LABEL_REF)
3745 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
3748 /* Darwin uses a special PIC legitimizer. */
3749 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
3752 rs6000_machopic_legitimize_pic_address (operands[1], mode,
3754 if (operands[0] != operands[1])
3755 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3760 /* If we are to limit the number of things we put in the TOC and
3761 this is a symbol plus a constant we can add in one insn,
3762 just put the symbol in the TOC and add the constant. Don't do
3763 this if reload is in progress. */
3764 if (GET_CODE (operands[1]) == CONST
3765 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
3766 && GET_CODE (XEXP (operands[1], 0)) == PLUS
3767 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
3768 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
3769 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
3770 && ! side_effects_p (operands[0]))
3773 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
3774 rtx other = XEXP (XEXP (operands[1], 0), 1);
3776 sym = force_reg (mode, sym);
3778 emit_insn (gen_addsi3 (operands[0], sym, other));
3780 emit_insn (gen_adddi3 (operands[0], sym, other));
3784 operands[1] = force_const_mem (mode, operands[1]);
3787 && constant_pool_expr_p (XEXP (operands[1], 0))
3788 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
3789 get_pool_constant (XEXP (operands[1], 0)),
3790 get_pool_mode (XEXP (operands[1], 0))))
3793 = gen_const_mem (mode,
3794 create_TOC_reference (XEXP (operands[1], 0)));
3795 set_mem_alias_set (operands[1], get_TOC_alias_set ());
3801 rs6000_eliminate_indexed_memrefs (operands);
3805 emit_insn (gen_rtx_PARALLEL (VOIDmode,
3807 gen_rtx_SET (VOIDmode,
3808 operands[0], operands[1]),
3809 gen_rtx_CLOBBER (VOIDmode,
3810 gen_rtx_SCRATCH (SImode)))));
3819 /* Above, we may have called force_const_mem which may have returned
3820 an invalid address. If we can, fix this up; otherwise, reload will
3821 have to deal with it. */
3822 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
3823 operands[1] = validize_mem (operands[1]);
3826 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3829 /* Nonzero if we can use a floating-point register to pass this arg. */
3830 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
3831 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
3832 && (CUM)->fregno <= FP_ARG_MAX_REG \
3833 && TARGET_HARD_FLOAT && TARGET_FPRS)
3835 /* Nonzero if we can use an AltiVec register to pass this arg. */
3836 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
3837 (ALTIVEC_VECTOR_MODE (MODE) \
3838 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
3839 && TARGET_ALTIVEC_ABI \
3842 /* Return a nonzero value to say to return the function value in
3843 memory, just as large structures are always returned. TYPE will be
3844 the data type of the value, and FNTYPE will be the type of the
3845 function doing the returning, or @code{NULL} for libcalls.
3847 The AIX ABI for the RS/6000 specifies that all structures are
3848 returned in memory. The Darwin ABI does the same. The SVR4 ABI
3849 specifies that structures <= 8 bytes are returned in r3/r4, but a
3850 draft put them in memory, and GCC used to implement the draft
3851 instead of the final standard. Therefore, TARGET_AIX_STRUCT_RET
3852 controls this instead of DEFAULT_ABI; V.4 targets needing backward
3853 compatibility can change DRAFT_V4_STRUCT_RET to override the
3854 default, and -m switches get the final word. See
3855 rs6000_override_options for more details.
3857 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
3858 long double support is enabled. These values are returned in memory.
3860 int_size_in_bytes returns -1 for variable size objects, which go in
3861 memory always. The cast to unsigned makes -1 > 8. */
3864 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
3866 /* In the darwin64 abi, try to use registers for larger structs
3868 if (rs6000_darwin64_abi
3869 && TREE_CODE (type) == RECORD_TYPE
3870 && int_size_in_bytes (type) > 0)
3872 CUMULATIVE_ARGS valcum;
3876 valcum.fregno = FP_ARG_MIN_REG;
3877 valcum.vregno = ALTIVEC_ARG_MIN_REG;
3878 /* Do a trial code generation as if this were going to be passed
3879 as an argument; if any part goes in memory, we return NULL. */
3880 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
3883 /* Otherwise fall through to more conventional ABI rules. */
3886 if (AGGREGATE_TYPE_P (type)
3887 && (TARGET_AIX_STRUCT_RET
3888 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
3891 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
3892 modes only exist for GCC vector types if -maltivec. */
3893 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
3894 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
3897 /* Return synthetic vectors in memory. */
3898 if (TREE_CODE (type) == VECTOR_TYPE
3899 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
3901 static bool warned_for_return_big_vectors = false;
3902 if (!warned_for_return_big_vectors)
3904 warning ("GCC vector returned by reference: "
3905 "non-standard ABI extension with no compatibility guarantee");
3906 warned_for_return_big_vectors = true;
3911 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
3917 /* Initialize a variable CUM of type CUMULATIVE_ARGS
3918 for a call to a function whose data type is FNTYPE.
3919 For a library call, FNTYPE is 0.
3921 For incoming args we set the number of arguments in the prototype large
3922 so we never return a PARALLEL. */
3925 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
3926 rtx libname ATTRIBUTE_UNUSED, int incoming,
3927 int libcall, int n_named_args)
3929 static CUMULATIVE_ARGS zero_cumulative;
3931 *cum = zero_cumulative;
3933 cum->fregno = FP_ARG_MIN_REG;
3934 cum->vregno = ALTIVEC_ARG_MIN_REG;
3935 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
3936 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
3937 ? CALL_LIBCALL : CALL_NORMAL);
3938 cum->sysv_gregno = GP_ARG_MIN_REG;
3939 cum->stdarg = fntype
3940 && (TYPE_ARG_TYPES (fntype) != 0
3941 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
3942 != void_type_node));
3944 cum->nargs_prototype = 0;
3945 if (incoming || cum->prototype)
3946 cum->nargs_prototype = n_named_args;
3948 /* Check for a longcall attribute. */
3949 if ((!fntype && rs6000_default_long_calls)
3951 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
3952 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
3953 cum->call_cookie |= CALL_LONG;
3955 if (TARGET_DEBUG_ARG)
3957 fprintf (stderr, "\ninit_cumulative_args:");
3960 tree ret_type = TREE_TYPE (fntype);
3961 fprintf (stderr, " ret code = %s,",
3962 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3965 if (cum->call_cookie & CALL_LONG)
3966 fprintf (stderr, " longcall,");
3968 fprintf (stderr, " proto = %d, nargs = %d\n",
3969 cum->prototype, cum->nargs_prototype);
3974 && TARGET_ALTIVEC_ABI
3975 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
3977 error ("Cannot return value in vector register because"
3978 " altivec instructions are disabled, use -maltivec"
3979 " to enable them.");
3983 /* Return true if TYPE must be passed on the stack and not in registers. */
3986 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
3988 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
3989 return must_pass_in_stack_var_size (mode, type);
3991 return must_pass_in_stack_var_size_or_pad (mode, type);
3994 /* If defined, a C expression which determines whether, and in which
3995 direction, to pad out an argument with extra space. The value
3996 should be of type `enum direction': either `upward' to pad above
3997 the argument, `downward' to pad below, or `none' to inhibit
4000 For the AIX ABI structs are always stored left shifted in their
4004 function_arg_padding (enum machine_mode mode, tree type)
4006 #ifndef AGGREGATE_PADDING_FIXED
4007 #define AGGREGATE_PADDING_FIXED 0
4009 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4010 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4013 if (!AGGREGATE_PADDING_FIXED)
4015 /* GCC used to pass structures of the same size as integer types as
4016 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4017 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4018 passed padded downward, except that -mstrict-align further
4019 muddied the water in that multi-component structures of 2 and 4
4020 bytes in size were passed padded upward.
4022 The following arranges for best compatibility with previous
4023 versions of gcc, but removes the -mstrict-align dependency. */
4024 if (BYTES_BIG_ENDIAN)
4026 HOST_WIDE_INT size = 0;
4028 if (mode == BLKmode)
4030 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4031 size = int_size_in_bytes (type);
4034 size = GET_MODE_SIZE (mode);
4036 if (size == 1 || size == 2 || size == 4)
4042 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4044 if (type != 0 && AGGREGATE_TYPE_P (type))
4048 /* Fall back to the default. */
4049 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4052 /* If defined, a C expression that gives the alignment boundary, in bits,
4053 of an argument with the specified mode and type. If it is not defined,
4054 PARM_BOUNDARY is used for all arguments.
4056 V.4 wants long longs to be double word aligned.
4057 Doubleword align SPE vectors.
4058 Quadword align Altivec vectors.
4059 Quadword align large synthetic vector types. */
4062 function_arg_boundary (enum machine_mode mode, tree type)
4064 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4066 else if (SPE_VECTOR_MODE (mode)
4067 || (type && TREE_CODE (type) == VECTOR_TYPE
4068 && int_size_in_bytes (type) >= 8
4069 && int_size_in_bytes (type) < 16))
4071 else if (ALTIVEC_VECTOR_MODE (mode)
4072 || (type && TREE_CODE (type) == VECTOR_TYPE
4073 && int_size_in_bytes (type) >= 16))
4075 else if (rs6000_darwin64_abi && mode == BLKmode
4076 && type && TYPE_ALIGN (type) > 64)
4079 return PARM_BOUNDARY;
4082 /* For a function parm of MODE and TYPE, return the starting word in
4083 the parameter area. NWORDS of the parameter area are already used. */
4086 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4089 unsigned int parm_offset;
4091 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4092 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4093 return nwords + (-(parm_offset + nwords) & align);
4096 /* Compute the size (in words) of a function argument. */
4098 static unsigned long
4099 rs6000_arg_size (enum machine_mode mode, tree type)
4103 if (mode != BLKmode)
4104 size = GET_MODE_SIZE (mode);
4106 size = int_size_in_bytes (type);
4109 return (size + 3) >> 2;
4111 return (size + 7) >> 3;
4114 /* Use this to flush pending int fields. */
4117 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4118 HOST_WIDE_INT bitpos)
4120 unsigned int startbit, endbit;
4121 int intregs, intoffset;
4122 enum machine_mode mode;
4124 if (cum->intoffset == -1)
4127 intoffset = cum->intoffset;
4128 cum->intoffset = -1;
4130 if (intoffset % BITS_PER_WORD != 0)
4132 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4134 if (mode == BLKmode)
4136 /* We couldn't find an appropriate mode, which happens,
4137 e.g., in packed structs when there are 3 bytes to load.
4138 Back intoffset back to the beginning of the word in this
4140 intoffset = intoffset & -BITS_PER_WORD;
4144 startbit = intoffset & -BITS_PER_WORD;
4145 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4146 intregs = (endbit - startbit) / BITS_PER_WORD;
4147 cum->words += intregs;
4150 /* The darwin64 ABI calls for us to recurse down through structs,
4151 looking for elements passed in registers. Unfortunately, we have
4152 to track int register count here also because of misalignments
4153 in powerpc alignment mode. */
4156 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4158 HOST_WIDE_INT startbitpos)
4162 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4163 if (TREE_CODE (f) == FIELD_DECL)
4165 HOST_WIDE_INT bitpos = startbitpos;
4166 tree ftype = TREE_TYPE (f);
4167 enum machine_mode mode = TYPE_MODE (ftype);
4169 if (DECL_SIZE (f) != 0
4170 && host_integerp (bit_position (f), 1))
4171 bitpos += int_bit_position (f);
4173 /* ??? FIXME: else assume zero offset. */
4175 if (TREE_CODE (ftype) == RECORD_TYPE)
4176 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4177 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4179 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4180 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4181 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4183 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4185 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4189 else if (cum->intoffset == -1)
4190 cum->intoffset = bitpos;
4194 /* Update the data in CUM to advance over an argument
4195 of mode MODE and data type TYPE.
4196 (TYPE is null for libcalls where that information may not be available.)
4198 Note that for args passed by reference, function_arg will be called
4199 with MODE and TYPE set to that of the pointer to the arg, not the arg
4203 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4204 tree type, int named, int depth)
4208 /* Only tick off an argument if we're not recursing. */
4210 cum->nargs_prototype--;
4212 if (TARGET_ALTIVEC_ABI
4213 && (ALTIVEC_VECTOR_MODE (mode)
4214 || (type && TREE_CODE (type) == VECTOR_TYPE
4215 && int_size_in_bytes (type) == 16)))
4219 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4222 if (!TARGET_ALTIVEC)
4223 error ("Cannot pass argument in vector register because"
4224 " altivec instructions are disabled, use -maltivec"
4225 " to enable them.");
4227 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4228 even if it is going to be passed in a vector register.
4229 Darwin does the same for variable-argument functions. */
4230 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4231 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4241 /* Vector parameters must be 16-byte aligned. This places
4242 them at 2 mod 4 in terms of words in 32-bit mode, since
4243 the parameter save area starts at offset 24 from the
4244 stack. In 64-bit mode, they just have to start on an
4245 even word, since the parameter save area is 16-byte
4246 aligned. Space for GPRs is reserved even if the argument
4247 will be passed in memory. */
4249 align = (2 - cum->words) & 3;
4251 align = cum->words & 1;
4252 cum->words += align + rs6000_arg_size (mode, type);
4254 if (TARGET_DEBUG_ARG)
4256 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4258 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4259 cum->nargs_prototype, cum->prototype,
4260 GET_MODE_NAME (mode));
4264 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4266 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4269 else if (rs6000_darwin64_abi
4271 && TREE_CODE (type) == RECORD_TYPE
4272 && (size = int_size_in_bytes (type)) > 0)
4274 /* Variable sized types have size == -1 and are
4275 treated as if consisting entirely of ints.
4276 Pad to 16 byte boundary if needed. */
4277 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4278 && (cum->words % 2) != 0)
4280 /* For varargs, we can just go up by the size of the struct. */
4282 cum->words += (size + 7) / 8;
4285 /* It is tempting to say int register count just goes up by
4286 sizeof(type)/8, but this is wrong in a case such as
4287 { int; double; int; } [powerpc alignment]. We have to
4288 grovel through the fields for these too. */
4290 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4291 rs6000_darwin64_record_arg_advance_flush (cum,
4292 size * BITS_PER_UNIT);
4295 else if (DEFAULT_ABI == ABI_V4)
4297 if (TARGET_HARD_FLOAT && TARGET_FPRS
4298 && (mode == SFmode || mode == DFmode))
4300 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4305 cum->words += cum->words & 1;
4306 cum->words += rs6000_arg_size (mode, type);
4311 int n_words = rs6000_arg_size (mode, type);
4312 int gregno = cum->sysv_gregno;
4314 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4315 (r7,r8) or (r9,r10). As does any other 2 word item such
4316 as complex int due to a historical mistake. */
4318 gregno += (1 - gregno) & 1;
4320 /* Multi-reg args are not split between registers and stack. */
4321 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4323 /* Long long and SPE vectors are aligned on the stack.
4324 So are other 2 word items such as complex int due to
4325 a historical mistake. */
4327 cum->words += cum->words & 1;
4328 cum->words += n_words;
4331 /* Note: continuing to accumulate gregno past when we've started
4332 spilling to the stack indicates the fact that we've started
4333 spilling to the stack to expand_builtin_saveregs. */
4334 cum->sysv_gregno = gregno + n_words;
4337 if (TARGET_DEBUG_ARG)
4339 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4340 cum->words, cum->fregno);
4341 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4342 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4343 fprintf (stderr, "mode = %4s, named = %d\n",
4344 GET_MODE_NAME (mode), named);
4349 int n_words = rs6000_arg_size (mode, type);
4350 int start_words = cum->words;
4351 int align_words = rs6000_parm_start (mode, type, start_words);
4353 cum->words = align_words + n_words;
4355 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4356 && TARGET_HARD_FLOAT && TARGET_FPRS)
4357 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4359 if (TARGET_DEBUG_ARG)
4361 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4362 cum->words, cum->fregno);
4363 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4364 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4365 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4366 named, align_words - start_words, depth);
4372 spe_build_register_parallel (enum machine_mode mode, int gregno)
4378 r1 = gen_rtx_REG (DImode, gregno);
4379 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4380 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4382 else if (mode == DCmode)
4384 r1 = gen_rtx_REG (DImode, gregno);
4385 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4386 r3 = gen_rtx_REG (DImode, gregno + 2);
4387 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4388 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4394 /* Determine where to put a SIMD argument on the SPE. */
4396 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4399 int gregno = cum->sysv_gregno;
4401 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4402 are passed and returned in a pair of GPRs for ABI compatibility. */
4403 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4405 int n_words = rs6000_arg_size (mode, type);
4407 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4409 gregno += (1 - gregno) & 1;
4411 /* Multi-reg args are not split between registers and stack. */
4412 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4415 return spe_build_register_parallel (mode, gregno);
4419 int n_words = rs6000_arg_size (mode, type);
4421 /* SPE vectors are put in odd registers. */
4422 if (n_words == 2 && (gregno & 1) == 0)
4425 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4428 enum machine_mode m = SImode;
4430 r1 = gen_rtx_REG (m, gregno);
4431 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4432 r2 = gen_rtx_REG (m, gregno + 1);
4433 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4434 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4441 if (gregno <= GP_ARG_MAX_REG)
4442 return gen_rtx_REG (mode, gregno);
4448 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4449 structure between cum->intoffset and bitpos to integer registers. */
4452 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4453 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4455 enum machine_mode mode;
4457 unsigned int startbit, endbit;
4458 int this_regno, intregs, intoffset;
4461 if (cum->intoffset == -1)
4464 intoffset = cum->intoffset;
4465 cum->intoffset = -1;
4467 /* If this is the trailing part of a word, try to only load that
4468 much into the register. Otherwise load the whole register. Note
4469 that in the latter case we may pick up unwanted bits. It's not a
4470 problem at the moment but may wish to revisit. */
4472 if (intoffset % BITS_PER_WORD != 0)
4474 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4476 if (mode == BLKmode)
4478 /* We couldn't find an appropriate mode, which happens,
4479 e.g., in packed structs when there are 3 bytes to load.
4480 Back intoffset back to the beginning of the word in this
4482 intoffset = intoffset & -BITS_PER_WORD;
4489 startbit = intoffset & -BITS_PER_WORD;
4490 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4491 intregs = (endbit - startbit) / BITS_PER_WORD;
4492 this_regno = cum->words + intoffset / BITS_PER_WORD;
4494 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4497 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4501 intoffset /= BITS_PER_UNIT;
4504 regno = GP_ARG_MIN_REG + this_regno;
4505 reg = gen_rtx_REG (mode, regno);
4507 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4510 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4514 while (intregs > 0);
4517 /* Recursive workhorse for the following. */
4520 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4521 HOST_WIDE_INT startbitpos, rtx rvec[],
4526 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4527 if (TREE_CODE (f) == FIELD_DECL)
4529 HOST_WIDE_INT bitpos = startbitpos;
4530 tree ftype = TREE_TYPE (f);
4531 enum machine_mode mode = TYPE_MODE (ftype);
4533 if (DECL_SIZE (f) != 0
4534 && host_integerp (bit_position (f), 1))
4535 bitpos += int_bit_position (f);
4537 /* ??? FIXME: else assume zero offset. */
4539 if (TREE_CODE (ftype) == RECORD_TYPE)
4540 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4541 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4546 case SCmode: mode = SFmode; break;
4547 case DCmode: mode = DFmode; break;
4548 case TCmode: mode = TFmode; break;
4552 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4554 = gen_rtx_EXPR_LIST (VOIDmode,
4555 gen_rtx_REG (mode, cum->fregno++),
4556 GEN_INT (bitpos / BITS_PER_UNIT));
4560 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4562 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4564 = gen_rtx_EXPR_LIST (VOIDmode,
4565 gen_rtx_REG (mode, cum->vregno++),
4566 GEN_INT (bitpos / BITS_PER_UNIT));
4568 else if (cum->intoffset == -1)
4569 cum->intoffset = bitpos;
4573 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4574 the register(s) to be used for each field and subfield of a struct
4575 being passed by value, along with the offset of where the
4576 register's value may be found in the block. FP fields go in FP
4577 register, vector fields go in vector registers, and everything
4578 else goes in int registers, packed as in memory.
4580 This code is also used for function return values. RETVAL indicates
4581 whether this is the case.
4583 Much of this is taken from the Sparc V9 port, which has a similar
4584 calling convention. */
4587 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4588 int named, bool retval)
4590 rtx rvec[FIRST_PSEUDO_REGISTER];
4591 int k = 1, kbase = 1;
4592 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4593 /* This is a copy; modifications are not visible to our caller. */
4594 CUMULATIVE_ARGS copy_cum = *orig_cum;
4595 CUMULATIVE_ARGS *cum = ©_cum;
4597 /* Pad to 16 byte boundary if needed. */
4598 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4599 && (cum->words % 2) != 0)
4606 /* Put entries into rvec[] for individual FP and vector fields, and
4607 for the chunks of memory that go in int regs. Note we start at
4608 element 1; 0 is reserved for an indication of using memory, and
4609 may or may not be filled in below. */
4610 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4611 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4613 /* If any part of the struct went on the stack put all of it there.
4614 This hack is because the generic code for
4615 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4616 parts of the struct are not at the beginning. */
4620 return NULL_RTX; /* doesn't go in registers at all */
4622 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4624 if (k > 1 || cum->use_stack)
4625 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4630 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4633 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4637 rtx rvec[GP_ARG_NUM_REG + 1];
4639 if (align_words >= GP_ARG_NUM_REG)
4642 n_units = rs6000_arg_size (mode, type);
4644 /* Optimize the simple case where the arg fits in one gpr, except in
4645 the case of BLKmode due to assign_parms assuming that registers are
4646 BITS_PER_WORD wide. */
4648 || (n_units == 1 && mode != BLKmode))
4649 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4652 if (align_words + n_units > GP_ARG_NUM_REG)
4653 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4654 using a magic NULL_RTX component.
4655 FIXME: This is not strictly correct. Only some of the arg
4656 belongs in memory, not all of it. However, there isn't any way
4657 to do this currently, apart from building rtx descriptions for
4658 the pieces of memory we want stored. Due to bugs in the generic
4659 code we can't use the normal function_arg_partial_nregs scheme
4660 with the PARALLEL arg description we emit here.
4661 In any case, the code to store the whole arg to memory is often
4662 more efficient than code to store pieces, and we know that space
4663 is available in the right place for the whole arg. */
4664 /* FIXME: This should be fixed since the conversion to
4665 TARGET_ARG_PARTIAL_BYTES. */
4666 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4671 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4672 rtx off = GEN_INT (i++ * 4);
4673 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4675 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4677 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4680 /* Determine where to put an argument to a function.
4681 Value is zero to push the argument on the stack,
4682 or a hard register in which to store the argument.
4684 MODE is the argument's machine mode.
4685 TYPE is the data type of the argument (as a tree).
4686 This is null for libcalls where that information may
4688 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4689 the preceding args and about the function being called. It is
4690 not modified in this routine.
4691 NAMED is nonzero if this argument is a named parameter
4692 (otherwise it is an extra parameter matching an ellipsis).
4694 On RS/6000 the first eight words of non-FP are normally in registers
4695 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4696 Under V.4, the first 8 FP args are in registers.
4698 If this is floating-point and no prototype is specified, we use
4699 both an FP and integer register (or possibly FP reg and stack). Library
4700 functions (when CALL_LIBCALL is set) always have the proper types for args,
4701 so we can pass the FP value just in one register. emit_library_function
4702 doesn't support PARALLEL anyway.
4704 Note that for args passed by reference, function_arg will be called
4705 with MODE and TYPE set to that of the pointer to the arg, not the arg
4709 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4710 tree type, int named)
4712 enum rs6000_abi abi = DEFAULT_ABI;
4714 /* Return a marker to indicate whether CR1 needs to set or clear the
4715 bit that V.4 uses to say fp args were passed in registers.
4716 Assume that we don't need the marker for software floating point,
4717 or compiler generated library calls. */
4718 if (mode == VOIDmode)
4721 && cum->nargs_prototype < 0
4722 && (cum->call_cookie & CALL_LIBCALL) == 0
4723 && (cum->prototype || TARGET_NO_PROTOTYPE))
4725 /* For the SPE, we need to crxor CR6 always. */
4727 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
4728 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
4729 return GEN_INT (cum->call_cookie
4730 | ((cum->fregno == FP_ARG_MIN_REG)
4731 ? CALL_V4_SET_FP_ARGS
4732 : CALL_V4_CLEAR_FP_ARGS));
4735 return GEN_INT (cum->call_cookie);
4738 if (rs6000_darwin64_abi && mode == BLKmode
4739 && TREE_CODE (type) == RECORD_TYPE)
4741 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
4742 if (rslt != NULL_RTX)
4744 /* Else fall through to usual handling. */
4747 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4748 if (TARGET_64BIT && ! cum->prototype)
4750 /* Vector parameters get passed in vector register
4751 and also in GPRs or memory, in absence of prototype. */
4754 align_words = (cum->words + 1) & ~1;
4756 if (align_words >= GP_ARG_NUM_REG)
4762 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4764 return gen_rtx_PARALLEL (mode,
4766 gen_rtx_EXPR_LIST (VOIDmode,
4768 gen_rtx_EXPR_LIST (VOIDmode,
4769 gen_rtx_REG (mode, cum->vregno),
4773 return gen_rtx_REG (mode, cum->vregno);
4774 else if (TARGET_ALTIVEC_ABI
4775 && (ALTIVEC_VECTOR_MODE (mode)
4776 || (type && TREE_CODE (type) == VECTOR_TYPE
4777 && int_size_in_bytes (type) == 16)))
4779 if (named || abi == ABI_V4)
4783 /* Vector parameters to varargs functions under AIX or Darwin
4784 get passed in memory and possibly also in GPRs. */
4785 int align, align_words, n_words;
4786 enum machine_mode part_mode;
4788 /* Vector parameters must be 16-byte aligned. This places them at
4789 2 mod 4 in terms of words in 32-bit mode, since the parameter
4790 save area starts at offset 24 from the stack. In 64-bit mode,
4791 they just have to start on an even word, since the parameter
4792 save area is 16-byte aligned. */
4794 align = (2 - cum->words) & 3;
4796 align = cum->words & 1;
4797 align_words = cum->words + align;
4799 /* Out of registers? Memory, then. */
4800 if (align_words >= GP_ARG_NUM_REG)
4803 if (TARGET_32BIT && TARGET_POWERPC64)
4804 return rs6000_mixed_function_arg (mode, type, align_words);
4806 /* The vector value goes in GPRs. Only the part of the
4807 value in GPRs is reported here. */
4809 n_words = rs6000_arg_size (mode, type);
4810 if (align_words + n_words > GP_ARG_NUM_REG)
4811 /* Fortunately, there are only two possibilities, the value
4812 is either wholly in GPRs or half in GPRs and half not. */
4815 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
4818 else if (TARGET_SPE_ABI && TARGET_SPE
4819 && (SPE_VECTOR_MODE (mode)
4820 || (TARGET_E500_DOUBLE && (mode == DFmode
4821 || mode == DCmode))))
4822 return rs6000_spe_function_arg (cum, mode, type);
4824 else if (abi == ABI_V4)
4826 if (TARGET_HARD_FLOAT && TARGET_FPRS
4827 && (mode == SFmode || mode == DFmode))
4829 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4830 return gen_rtx_REG (mode, cum->fregno);
4836 int n_words = rs6000_arg_size (mode, type);
4837 int gregno = cum->sysv_gregno;
4839 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4840 (r7,r8) or (r9,r10). As does any other 2 word item such
4841 as complex int due to a historical mistake. */
4843 gregno += (1 - gregno) & 1;
4845 /* Multi-reg args are not split between registers and stack. */
4846 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4849 if (TARGET_32BIT && TARGET_POWERPC64)
4850 return rs6000_mixed_function_arg (mode, type,
4851 gregno - GP_ARG_MIN_REG);
4852 return gen_rtx_REG (mode, gregno);
4857 int align_words = rs6000_parm_start (mode, type, cum->words);
4859 if (USE_FP_FOR_ARG_P (cum, mode, type))
4861 rtx rvec[GP_ARG_NUM_REG + 1];
4865 enum machine_mode fmode = mode;
4866 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
4868 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
4870 /* Currently, we only ever need one reg here because complex
4871 doubles are split. */
4872 if (cum->fregno != FP_ARG_MAX_REG || fmode != TFmode)
4875 /* Long double split over regs and memory. */
4879 /* Do we also need to pass this arg in the parameter save
4882 && (cum->nargs_prototype <= 0
4883 || (DEFAULT_ABI == ABI_AIX
4885 && align_words >= GP_ARG_NUM_REG)));
4887 if (!needs_psave && mode == fmode)
4888 return gen_rtx_REG (fmode, cum->fregno);
4893 /* Describe the part that goes in gprs or the stack.
4894 This piece must come first, before the fprs. */
4895 if (align_words < GP_ARG_NUM_REG)
4897 unsigned long n_words = rs6000_arg_size (mode, type);
4899 if (align_words + n_words > GP_ARG_NUM_REG
4900 || (TARGET_32BIT && TARGET_POWERPC64))
4902 /* If this is partially on the stack, then we only
4903 include the portion actually in registers here. */
4904 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
4907 if (align_words + n_words > GP_ARG_NUM_REG
4908 && (TARGET_32BIT && TARGET_POWERPC64))
4909 /* Not all of the arg fits in gprs. Say that it
4910 goes in memory too, using a magic NULL_RTX
4911 component. Also see comment in
4912 rs6000_mixed_function_arg for why the normal
4913 function_arg_partial_nregs scheme doesn't work
4915 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
4919 r = gen_rtx_REG (rmode,
4920 GP_ARG_MIN_REG + align_words);
4921 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
4922 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4924 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
4928 /* The whole arg fits in gprs. */
4929 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4930 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4934 /* It's entirely in memory. */
4935 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4938 /* Describe where this piece goes in the fprs. */
4939 r = gen_rtx_REG (fmode, cum->fregno);
4940 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
4942 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4944 else if (align_words < GP_ARG_NUM_REG)
4946 if (TARGET_32BIT && TARGET_POWERPC64)
4947 return rs6000_mixed_function_arg (mode, type, align_words);
4949 if (mode == BLKmode)
4952 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4959 /* For an arg passed partly in registers and partly in memory, this is
4960 the number of registers used. For args passed entirely in registers
4961 or entirely in memory, zero. When an arg is described by a PARALLEL,
4962 perhaps using more than one register type, this function returns the
4963 number of bytes of registers used by the PARALLEL. */
4966 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4967 tree type, bool named)
4972 if (DEFAULT_ABI == ABI_V4)
4975 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
4976 && cum->nargs_prototype >= 0)
4979 /* In this complicated case we just disable the partial_nregs code. */
4980 if (rs6000_darwin64_abi && mode == BLKmode
4981 && TREE_CODE (type) == RECORD_TYPE
4982 && int_size_in_bytes (type) > 0)
4985 align_words = rs6000_parm_start (mode, type, cum->words);
4987 if (USE_FP_FOR_ARG_P (cum, mode, type)
4988 /* If we are passing this arg in gprs as well, then this function
4989 should return the number of gprs (or memory) partially passed,
4990 *not* the number of fprs. */
4992 && (cum->nargs_prototype <= 0
4993 || (DEFAULT_ABI == ABI_AIX
4995 && align_words >= GP_ARG_NUM_REG))))
4997 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
4998 ret = FP_ARG_MAX_REG + 1 - cum->fregno;
4999 else if (cum->nargs_prototype >= 0)
5003 if (align_words < GP_ARG_NUM_REG
5004 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5005 ret = GP_ARG_NUM_REG - align_words;
5007 ret *= (TARGET_32BIT ? 4 : 8);
5009 if (ret != 0 && TARGET_DEBUG_ARG)
5010 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5015 /* A C expression that indicates when an argument must be passed by
5016 reference. If nonzero for an argument, a copy of that argument is
5017 made in memory and a pointer to the argument is passed instead of
5018 the argument itself. The pointer is passed in whatever way is
5019 appropriate for passing a pointer to that type.
5021 Under V.4, aggregates and long double are passed by reference.
5023 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5024 reference unless the AltiVec vector extension ABI is in force.
5026 As an extension to all ABIs, variable sized types are passed by
5030 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5031 enum machine_mode mode, tree type,
5032 bool named ATTRIBUTE_UNUSED)
5034 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5036 if (TARGET_DEBUG_ARG)
5037 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5044 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5046 if (TARGET_DEBUG_ARG)
5047 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5051 if (int_size_in_bytes (type) < 0)
5053 if (TARGET_DEBUG_ARG)
5054 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5058 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5059 modes only exist for GCC vector types if -maltivec. */
5060 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5062 if (TARGET_DEBUG_ARG)
5063 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5067 /* Pass synthetic vectors in memory. */
5068 if (TREE_CODE (type) == VECTOR_TYPE
5069 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5071 static bool warned_for_pass_big_vectors = false;
5072 if (TARGET_DEBUG_ARG)
5073 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5074 if (!warned_for_pass_big_vectors)
5076 warning ("GCC vector passed by reference: "
5077 "non-standard ABI extension with no compatibility guarantee");
5078 warned_for_pass_big_vectors = true;
5087 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5090 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5095 for (i = 0; i < nregs; i++)
5097 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5098 if (reload_completed)
5100 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5103 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5104 i * GET_MODE_SIZE (reg_mode));
5107 tem = replace_equiv_address (tem, XEXP (tem, 0));
5109 if (tem == NULL_RTX)
5112 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5116 /* Perform any needed actions needed for a function that is receiving a
5117 variable number of arguments.
5121 MODE and TYPE are the mode and type of the current parameter.
5123 PRETEND_SIZE is a variable that should be set to the amount of stack
5124 that must be pushed by the prolog to pretend that our caller pushed
5127 Normally, this macro will push all remaining incoming registers on the
5128 stack and set PRETEND_SIZE to the length of the registers pushed. */
5131 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5132 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5135 CUMULATIVE_ARGS next_cum;
5136 int reg_size = TARGET_32BIT ? 4 : 8;
5137 rtx save_area = NULL_RTX, mem;
5138 int first_reg_offset, set;
5140 /* Skip the last named argument. */
5142 function_arg_advance (&next_cum, mode, type, 1, 0);
5144 if (DEFAULT_ABI == ABI_V4)
5147 save_area = plus_constant (virtual_stack_vars_rtx,
5148 - RS6000_VARARGS_SIZE);
5150 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5154 first_reg_offset = next_cum.words;
5155 save_area = virtual_incoming_args_rtx;
5157 if (targetm.calls.must_pass_in_stack (mode, type))
5158 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5161 set = get_varargs_alias_set ();
5162 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG)
5164 mem = gen_rtx_MEM (BLKmode,
5165 plus_constant (save_area,
5166 first_reg_offset * reg_size)),
5167 set_mem_alias_set (mem, set);
5168 set_mem_align (mem, BITS_PER_WORD);
5170 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5171 GP_ARG_NUM_REG - first_reg_offset);
5174 /* Save FP registers if needed. */
5175 if (DEFAULT_ABI == ABI_V4
5176 && TARGET_HARD_FLOAT && TARGET_FPRS
5178 && next_cum.fregno <= FP_ARG_V4_MAX_REG)
5180 int fregno = next_cum.fregno;
5181 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5182 rtx lab = gen_label_rtx ();
5183 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG) * 8);
5186 (gen_rtx_SET (VOIDmode,
5188 gen_rtx_IF_THEN_ELSE (VOIDmode,
5189 gen_rtx_NE (VOIDmode, cr1,
5191 gen_rtx_LABEL_REF (VOIDmode, lab),
5194 while (fregno <= FP_ARG_V4_MAX_REG)
5196 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5197 set_mem_alias_set (mem, set);
5198 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5199 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5208 /* Create the va_list data type. */
5211 rs6000_build_builtin_va_list (void)
5213 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5215 /* For AIX, prefer 'char *' because that's what the system
5216 header files like. */
5217 if (DEFAULT_ABI != ABI_V4)
5218 return build_pointer_type (char_type_node);
5220 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5221 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5223 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5224 unsigned_char_type_node);
5225 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5226 unsigned_char_type_node);
5227 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5229 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5230 short_unsigned_type_node);
5231 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5233 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5236 DECL_FIELD_CONTEXT (f_gpr) = record;
5237 DECL_FIELD_CONTEXT (f_fpr) = record;
5238 DECL_FIELD_CONTEXT (f_res) = record;
5239 DECL_FIELD_CONTEXT (f_ovf) = record;
5240 DECL_FIELD_CONTEXT (f_sav) = record;
5242 TREE_CHAIN (record) = type_decl;
5243 TYPE_NAME (record) = type_decl;
5244 TYPE_FIELDS (record) = f_gpr;
5245 TREE_CHAIN (f_gpr) = f_fpr;
5246 TREE_CHAIN (f_fpr) = f_res;
5247 TREE_CHAIN (f_res) = f_ovf;
5248 TREE_CHAIN (f_ovf) = f_sav;
5250 layout_type (record);
5252 /* The correct type is an array type of one element. */
5253 return build_array_type (record, build_index_type (size_zero_node));
5256 /* Implement va_start. */
5259 rs6000_va_start (tree valist, rtx nextarg)
5261 HOST_WIDE_INT words, n_gpr, n_fpr;
5262 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5263 tree gpr, fpr, ovf, sav, t;
5265 /* Only SVR4 needs something special. */
5266 if (DEFAULT_ABI != ABI_V4)
5268 std_expand_builtin_va_start (valist, nextarg);
5272 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5273 f_fpr = TREE_CHAIN (f_gpr);
5274 f_res = TREE_CHAIN (f_fpr);
5275 f_ovf = TREE_CHAIN (f_res);
5276 f_sav = TREE_CHAIN (f_ovf);
5278 valist = build_va_arg_indirect_ref (valist);
5279 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5280 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5281 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5282 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5284 /* Count number of gp and fp argument registers used. */
5285 words = current_function_args_info.words;
5286 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5288 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5291 if (TARGET_DEBUG_ARG)
5292 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5293 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5294 words, n_gpr, n_fpr);
5296 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5297 build_int_cst (NULL_TREE, n_gpr));
5298 TREE_SIDE_EFFECTS (t) = 1;
5299 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5301 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5302 build_int_cst (NULL_TREE, n_fpr));
5303 TREE_SIDE_EFFECTS (t) = 1;
5304 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5306 /* Find the overflow area. */
5307 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5309 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5310 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5311 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5312 TREE_SIDE_EFFECTS (t) = 1;
5313 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5315 /* Find the register save area. */
5316 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5317 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5318 build_int_cst (NULL_TREE, -RS6000_VARARGS_SIZE));
5319 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5320 TREE_SIDE_EFFECTS (t) = 1;
5321 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5324 /* Implement va_arg. */
5327 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5329 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5330 tree gpr, fpr, ovf, sav, reg, t, u;
5331 int size, rsize, n_reg, sav_ofs, sav_scale;
5332 tree lab_false, lab_over, addr;
5334 tree ptrtype = build_pointer_type (type);
5336 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5338 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5339 return build_va_arg_indirect_ref (t);
5342 if (DEFAULT_ABI != ABI_V4)
5344 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5346 tree elem_type = TREE_TYPE (type);
5347 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5348 int elem_size = GET_MODE_SIZE (elem_mode);
5350 if (elem_size < UNITS_PER_WORD)
5352 tree real_part, imag_part;
5353 tree post = NULL_TREE;
5355 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5357 /* Copy the value into a temporary, lest the formal temporary
5358 be reused out from under us. */
5359 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5360 append_to_statement_list (post, pre_p);
5362 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5365 return build (COMPLEX_EXPR, type, real_part, imag_part);
5369 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5372 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5373 f_fpr = TREE_CHAIN (f_gpr);
5374 f_res = TREE_CHAIN (f_fpr);
5375 f_ovf = TREE_CHAIN (f_res);
5376 f_sav = TREE_CHAIN (f_ovf);
5378 valist = build_va_arg_indirect_ref (valist);
5379 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5380 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5381 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5382 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5384 size = int_size_in_bytes (type);
5385 rsize = (size + 3) / 4;
5388 if (TARGET_HARD_FLOAT && TARGET_FPRS
5389 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5391 /* FP args go in FP registers, if present. */
5396 if (TYPE_MODE (type) == DFmode)
5401 /* Otherwise into GP registers. */
5410 /* Pull the value out of the saved registers.... */
5413 addr = create_tmp_var (ptr_type_node, "addr");
5414 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5416 /* AltiVec vectors never go in registers when -mabi=altivec. */
5417 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5421 lab_false = create_artificial_label ();
5422 lab_over = create_artificial_label ();
5424 /* Long long and SPE vectors are aligned in the registers.
5425 As are any other 2 gpr item such as complex int due to a
5426 historical mistake. */
5430 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5431 size_int (n_reg - 1));
5432 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5435 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5436 t = build2 (GE_EXPR, boolean_type_node, u, t);
5437 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5438 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5439 gimplify_and_add (t, pre_p);
5443 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5445 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5446 u = build1 (CONVERT_EXPR, integer_type_node, u);
5447 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5448 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5450 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5451 gimplify_and_add (t, pre_p);
5453 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5454 gimplify_and_add (t, pre_p);
5456 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5457 append_to_statement_list (t, pre_p);
5461 /* Ensure that we don't find any more args in regs.
5462 Alignment has taken care of the n_reg == 2 case. */
5463 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5464 gimplify_and_add (t, pre_p);
5468 /* ... otherwise out of the overflow area. */
5470 /* Care for on-stack alignment if needed. */
5474 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5475 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5476 build_int_cst (NULL_TREE, -align));
5478 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5480 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5481 gimplify_and_add (u, pre_p);
5483 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5484 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5485 gimplify_and_add (t, pre_p);
5489 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5490 append_to_statement_list (t, pre_p);
5493 addr = fold_convert (ptrtype, addr);
5494 return build_va_arg_indirect_ref (addr);
5499 #define def_builtin(MASK, NAME, TYPE, CODE) \
5501 if ((MASK) & target_flags) \
5502 lang_hooks.builtin_function ((NAME), (TYPE), (CODE), BUILT_IN_MD, \
5506 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5508 static const struct builtin_description bdesc_3arg[] =
5510 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5511 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5512 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5513 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5514 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5515 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5516 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5517 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5518 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5519 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5520 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5521 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5522 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5523 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5524 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5525 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5526 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5527 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5528 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5529 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5530 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5531 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5532 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5535 /* DST operations: void foo (void *, const int, const char). */
5537 static const struct builtin_description bdesc_dst[] =
5539 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5540 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5541 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5542 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT }
5545 /* Simple binary operations: VECc = foo (VECa, VECb). */
5547 static struct builtin_description bdesc_2arg[] =
5549 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5550 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5551 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5552 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5553 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5554 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5555 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5556 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5557 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5558 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5559 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5560 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5561 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5562 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5563 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5564 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5565 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5566 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5567 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5568 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5569 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5570 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5571 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5572 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5573 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5574 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5575 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5576 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5577 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5578 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5579 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5580 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5581 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5582 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5583 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5584 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5585 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5586 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5587 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5588 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5589 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5590 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5591 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5592 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5593 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5594 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5595 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5596 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5597 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5598 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5599 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5600 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
5601 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
5602 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
5603 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
5604 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
5605 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
5606 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
5607 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
5608 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
5609 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
5610 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
5611 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
5612 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
5613 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
5614 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
5615 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
5616 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
5617 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
5618 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
5619 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
5620 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
5621 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
5622 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
5623 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
5624 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
5625 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
5626 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
5627 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
5628 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
5629 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
5630 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
5631 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
5632 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
5633 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
5634 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
5635 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
5636 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
5637 { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
5638 { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
5639 { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
5640 { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
5641 { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
5642 { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
5643 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
5644 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
5645 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
5646 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
5647 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
5648 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
5649 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
5650 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
5651 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
5652 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
5653 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
5654 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
5655 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
5656 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
5657 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
5658 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
5659 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
5660 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
5661 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
5663 /* Place holder, leave as first spe builtin. */
5664 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
5665 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
5666 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
5667 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
5668 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
5669 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
5670 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
5671 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
5672 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
5673 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
5674 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
5675 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
5676 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
5677 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
5678 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
5679 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
5680 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
5681 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
5682 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
5683 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
5684 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
5685 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
5686 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
5687 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
5688 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
5689 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
5690 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
5691 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
5692 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
5693 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
5694 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
5695 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
5696 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
5697 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
5698 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
5699 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
5700 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
5701 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
5702 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
5703 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
5704 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
5705 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
5706 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
5707 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
5708 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
5709 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
5710 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
5711 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
5712 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
5713 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
5714 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
5715 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
5716 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
5717 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
5718 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
5719 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
5720 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
5721 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
5722 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
5723 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
5724 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
5725 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
5726 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
5727 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
5728 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
5729 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
5730 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
5731 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
5732 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
5733 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
5734 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
5735 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
5736 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
5737 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
5738 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
5739 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
5740 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
5741 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
5742 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
5743 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
5744 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
5745 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
5746 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
5747 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
5748 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
5749 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
5750 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
5751 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
5752 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
5753 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
5754 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
5755 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
5756 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
5757 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
5758 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
5759 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
5760 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
5761 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
5762 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
5763 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
5764 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
5765 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
5766 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
5767 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
5768 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
5769 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
5770 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
5771 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
5772 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
5774 /* SPE binary operations expecting a 5-bit unsigned literal. */
5775 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
5777 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
5778 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
5779 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
5780 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
5781 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
5782 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
5783 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
5784 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
5785 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
5786 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
5787 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
5788 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
5789 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
5790 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
5791 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
5792 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
5793 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
5794 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
5795 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
5796 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
5797 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
5798 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
5799 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
5800 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
5801 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
5802 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
5804 /* Place-holder. Leave as last binary SPE builtin. */
5805 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR },
5808 /* AltiVec predicates. */
5810 struct builtin_description_predicates
5812 const unsigned int mask;
5813 const enum insn_code icode;
5815 const char *const name;
5816 const enum rs6000_builtins code;
5819 static const struct builtin_description_predicates bdesc_altivec_preds[] =
5821 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
5822 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
5823 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
5824 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
5825 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
5826 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
5827 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
5828 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
5829 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
5830 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
5831 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
5832 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
5833 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P }
5836 /* SPE predicates. */
5837 static struct builtin_description bdesc_spe_predicates[] =
5839 /* Place-holder. Leave as first. */
5840 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
5841 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
5842 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
5843 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
5844 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
5845 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
5846 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
5847 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
5848 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
5849 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
5850 /* Place-holder. Leave as last. */
5851 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
5854 /* SPE evsel predicates. */
5855 static struct builtin_description bdesc_spe_evsel[] =
5857 /* Place-holder. Leave as first. */
5858 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
5859 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
5860 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
5861 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
5862 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
5863 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
5864 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
5865 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
5866 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
5867 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
5868 /* Place-holder. Leave as last. */
5869 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
5872 /* ABS* operations. */
5874 static const struct builtin_description bdesc_abs[] =
5876 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
5877 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
5878 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
5879 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
5880 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
5881 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
5882 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
5885 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
5888 static struct builtin_description bdesc_1arg[] =
5890 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
5891 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
5892 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
5894 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
5895 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
5896 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
5897 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
5898 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
5899 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
5900 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
5901 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
5902 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
5903 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
5904 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
5905 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
5906 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
5908 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
5909 end with SPE_BUILTIN_EVSUBFUSIAAW. */
5910 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
5911 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
5912 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
5913 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
5914 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
5915 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
5916 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
5917 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
5918 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
5919 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
5920 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
5921 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
5922 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
5923 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
5924 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
5925 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
5926 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
5927 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
5928 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
5929 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
5930 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
5931 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
5932 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
5933 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
5934 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
5935 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
5936 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
5937 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
5939 /* Place-holder. Leave as last unary SPE builtin. */
5940 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
5944 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
5947 tree arg0 = TREE_VALUE (arglist);
5948 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5949 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5950 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
5952 if (icode == CODE_FOR_nothing)
5953 /* Builtin not supported on this processor. */
5956 /* If we got invalid arguments bail out before generating bad rtl. */
5957 if (arg0 == error_mark_node)
5960 if (icode == CODE_FOR_altivec_vspltisb
5961 || icode == CODE_FOR_altivec_vspltish
5962 || icode == CODE_FOR_altivec_vspltisw
5963 || icode == CODE_FOR_spe_evsplatfi
5964 || icode == CODE_FOR_spe_evsplati)
5966 /* Only allow 5-bit *signed* literals. */
5967 if (GET_CODE (op0) != CONST_INT
5968 || INTVAL (op0) > 0x1f
5969 || INTVAL (op0) < -0x1f)
5971 error ("argument 1 must be a 5-bit signed literal");
5977 || GET_MODE (target) != tmode
5978 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
5979 target = gen_reg_rtx (tmode);
5981 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
5982 op0 = copy_to_mode_reg (mode0, op0);
5984 pat = GEN_FCN (icode) (target, op0);
5993 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
5995 rtx pat, scratch1, scratch2;
5996 tree arg0 = TREE_VALUE (arglist);
5997 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
5998 enum machine_mode tmode = insn_data[icode].operand[0].mode;
5999 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6001 /* If we have invalid arguments, bail out before generating bad rtl. */
6002 if (arg0 == error_mark_node)
6006 || GET_MODE (target) != tmode
6007 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6008 target = gen_reg_rtx (tmode);
6010 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6011 op0 = copy_to_mode_reg (mode0, op0);
6013 scratch1 = gen_reg_rtx (mode0);
6014 scratch2 = gen_reg_rtx (mode0);
6016 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6025 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6028 tree arg0 = TREE_VALUE (arglist);
6029 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6030 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6031 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6032 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6033 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6034 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6036 if (icode == CODE_FOR_nothing)
6037 /* Builtin not supported on this processor. */
6040 /* If we got invalid arguments bail out before generating bad rtl. */
6041 if (arg0 == error_mark_node || arg1 == error_mark_node)
6044 if (icode == CODE_FOR_altivec_vcfux
6045 || icode == CODE_FOR_altivec_vcfsx
6046 || icode == CODE_FOR_altivec_vctsxs
6047 || icode == CODE_FOR_altivec_vctuxs
6048 || icode == CODE_FOR_altivec_vspltb
6049 || icode == CODE_FOR_altivec_vsplth
6050 || icode == CODE_FOR_altivec_vspltw
6051 || icode == CODE_FOR_spe_evaddiw
6052 || icode == CODE_FOR_spe_evldd
6053 || icode == CODE_FOR_spe_evldh
6054 || icode == CODE_FOR_spe_evldw
6055 || icode == CODE_FOR_spe_evlhhesplat
6056 || icode == CODE_FOR_spe_evlhhossplat
6057 || icode == CODE_FOR_spe_evlhhousplat
6058 || icode == CODE_FOR_spe_evlwhe
6059 || icode == CODE_FOR_spe_evlwhos
6060 || icode == CODE_FOR_spe_evlwhou
6061 || icode == CODE_FOR_spe_evlwhsplat
6062 || icode == CODE_FOR_spe_evlwwsplat
6063 || icode == CODE_FOR_spe_evrlwi
6064 || icode == CODE_FOR_spe_evslwi
6065 || icode == CODE_FOR_spe_evsrwis
6066 || icode == CODE_FOR_spe_evsubifw
6067 || icode == CODE_FOR_spe_evsrwiu)
6069 /* Only allow 5-bit unsigned literals. */
6071 if (TREE_CODE (arg1) != INTEGER_CST
6072 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6074 error ("argument 2 must be a 5-bit unsigned literal");
6080 || GET_MODE (target) != tmode
6081 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6082 target = gen_reg_rtx (tmode);
6084 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6085 op0 = copy_to_mode_reg (mode0, op0);
6086 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6087 op1 = copy_to_mode_reg (mode1, op1);
6089 pat = GEN_FCN (icode) (target, op0, op1);
6098 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6099 tree arglist, rtx target)
6102 tree cr6_form = TREE_VALUE (arglist);
6103 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6104 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6105 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6106 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6107 enum machine_mode tmode = SImode;
6108 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6109 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6112 if (TREE_CODE (cr6_form) != INTEGER_CST)
6114 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6118 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6123 /* If we have invalid arguments, bail out before generating bad rtl. */
6124 if (arg0 == error_mark_node || arg1 == error_mark_node)
6128 || GET_MODE (target) != tmode
6129 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6130 target = gen_reg_rtx (tmode);
6132 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6133 op0 = copy_to_mode_reg (mode0, op0);
6134 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6135 op1 = copy_to_mode_reg (mode1, op1);
6137 scratch = gen_reg_rtx (mode0);
6139 pat = GEN_FCN (icode) (scratch, op0, op1,
6140 gen_rtx_SYMBOL_REF (Pmode, opcode));
6145 /* The vec_any* and vec_all* predicates use the same opcodes for two
6146 different operations, but the bits in CR6 will be different
6147 depending on what information we want. So we have to play tricks
6148 with CR6 to get the right bits out.
6150 If you think this is disgusting, look at the specs for the
6151 AltiVec predicates. */
6153 switch (cr6_form_int)
6156 emit_insn (gen_cr6_test_for_zero (target));
6159 emit_insn (gen_cr6_test_for_zero_reverse (target));
6162 emit_insn (gen_cr6_test_for_lt (target));
6165 emit_insn (gen_cr6_test_for_lt_reverse (target));
6168 error ("argument 1 of __builtin_altivec_predicate is out of range");
6176 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6179 tree arg0 = TREE_VALUE (arglist);
6180 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6181 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6182 enum machine_mode mode0 = Pmode;
6183 enum machine_mode mode1 = Pmode;
6184 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6185 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6187 if (icode == CODE_FOR_nothing)
6188 /* Builtin not supported on this processor. */
6191 /* If we got invalid arguments bail out before generating bad rtl. */
6192 if (arg0 == error_mark_node || arg1 == error_mark_node)
6196 || GET_MODE (target) != tmode
6197 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6198 target = gen_reg_rtx (tmode);
6200 op1 = copy_to_mode_reg (mode1, op1);
6202 if (op0 == const0_rtx)
6204 addr = gen_rtx_MEM (tmode, op1);
6208 op0 = copy_to_mode_reg (mode0, op0);
6209 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6212 pat = GEN_FCN (icode) (target, addr);
6222 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6224 tree arg0 = TREE_VALUE (arglist);
6225 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6226 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6227 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6228 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6229 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6231 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6232 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6233 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6235 /* Invalid arguments. Bail before doing anything stoopid! */
6236 if (arg0 == error_mark_node
6237 || arg1 == error_mark_node
6238 || arg2 == error_mark_node)
6241 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6242 op0 = copy_to_mode_reg (mode2, op0);
6243 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6244 op1 = copy_to_mode_reg (mode0, op1);
6245 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6246 op2 = copy_to_mode_reg (mode1, op2);
6248 pat = GEN_FCN (icode) (op1, op2, op0);
6255 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6257 tree arg0 = TREE_VALUE (arglist);
6258 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6259 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6260 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6261 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6262 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6264 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6265 enum machine_mode mode1 = Pmode;
6266 enum machine_mode mode2 = Pmode;
6268 /* Invalid arguments. Bail before doing anything stoopid! */
6269 if (arg0 == error_mark_node
6270 || arg1 == error_mark_node
6271 || arg2 == error_mark_node)
6274 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6275 op0 = copy_to_mode_reg (tmode, op0);
6277 op2 = copy_to_mode_reg (mode2, op2);
6279 if (op1 == const0_rtx)
6281 addr = gen_rtx_MEM (tmode, op2);
6285 op1 = copy_to_mode_reg (mode1, op1);
6286 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6289 pat = GEN_FCN (icode) (addr, op0);
6296 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6299 tree arg0 = TREE_VALUE (arglist);
6300 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6301 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6302 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6303 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6304 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6305 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6306 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6307 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6308 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6310 if (icode == CODE_FOR_nothing)
6311 /* Builtin not supported on this processor. */
6314 /* If we got invalid arguments bail out before generating bad rtl. */
6315 if (arg0 == error_mark_node
6316 || arg1 == error_mark_node
6317 || arg2 == error_mark_node)
6320 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6321 || icode == CODE_FOR_altivec_vsldoi_v4si
6322 || icode == CODE_FOR_altivec_vsldoi_v8hi
6323 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6325 /* Only allow 4-bit unsigned literals. */
6327 if (TREE_CODE (arg2) != INTEGER_CST
6328 || TREE_INT_CST_LOW (arg2) & ~0xf)
6330 error ("argument 3 must be a 4-bit unsigned literal");
6336 || GET_MODE (target) != tmode
6337 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6338 target = gen_reg_rtx (tmode);
6340 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6341 op0 = copy_to_mode_reg (mode0, op0);
6342 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6343 op1 = copy_to_mode_reg (mode1, op1);
6344 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6345 op2 = copy_to_mode_reg (mode2, op2);
6347 pat = GEN_FCN (icode) (target, op0, op1, op2);
6355 /* Expand the lvx builtins. */
6357 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6359 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6360 tree arglist = TREE_OPERAND (exp, 1);
6361 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6363 enum machine_mode tmode, mode0;
6365 enum insn_code icode;
6369 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6370 icode = CODE_FOR_altivec_lvx_v16qi;
6372 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6373 icode = CODE_FOR_altivec_lvx_v8hi;
6375 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6376 icode = CODE_FOR_altivec_lvx_v4si;
6378 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6379 icode = CODE_FOR_altivec_lvx_v4sf;
6388 arg0 = TREE_VALUE (arglist);
6389 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6390 tmode = insn_data[icode].operand[0].mode;
6391 mode0 = insn_data[icode].operand[1].mode;
6394 || GET_MODE (target) != tmode
6395 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6396 target = gen_reg_rtx (tmode);
6398 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6399 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6401 pat = GEN_FCN (icode) (target, op0);
6408 /* Expand the stvx builtins. */
6410 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6413 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6414 tree arglist = TREE_OPERAND (exp, 1);
6415 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6417 enum machine_mode mode0, mode1;
6419 enum insn_code icode;
6423 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6424 icode = CODE_FOR_altivec_stvx_v16qi;
6426 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6427 icode = CODE_FOR_altivec_stvx_v8hi;
6429 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6430 icode = CODE_FOR_altivec_stvx_v4si;
6432 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6433 icode = CODE_FOR_altivec_stvx_v4sf;
6440 arg0 = TREE_VALUE (arglist);
6441 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6442 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6443 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6444 mode0 = insn_data[icode].operand[0].mode;
6445 mode1 = insn_data[icode].operand[1].mode;
6447 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6448 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6449 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6450 op1 = copy_to_mode_reg (mode1, op1);
6452 pat = GEN_FCN (icode) (op0, op1);
6460 /* Expand the dst builtins. */
6462 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6465 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6466 tree arglist = TREE_OPERAND (exp, 1);
6467 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6468 tree arg0, arg1, arg2;
6469 enum machine_mode mode0, mode1, mode2;
6470 rtx pat, op0, op1, op2;
6471 struct builtin_description *d;
6476 /* Handle DST variants. */
6477 d = (struct builtin_description *) bdesc_dst;
6478 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
6479 if (d->code == fcode)
6481 arg0 = TREE_VALUE (arglist);
6482 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6483 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6484 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6485 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6486 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6487 mode0 = insn_data[d->icode].operand[0].mode;
6488 mode1 = insn_data[d->icode].operand[1].mode;
6489 mode2 = insn_data[d->icode].operand[2].mode;
6491 /* Invalid arguments, bail out before generating bad rtl. */
6492 if (arg0 == error_mark_node
6493 || arg1 == error_mark_node
6494 || arg2 == error_mark_node)
6499 if (TREE_CODE (arg2) != INTEGER_CST
6500 || TREE_INT_CST_LOW (arg2) & ~0x3)
6502 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
6506 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
6507 op0 = copy_to_mode_reg (Pmode, op0);
6508 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
6509 op1 = copy_to_mode_reg (mode1, op1);
6511 pat = GEN_FCN (d->icode) (op0, op1, op2);
6521 /* Expand the builtin in EXP and store the result in TARGET. Store
6522 true in *EXPANDEDP if we found a builtin to expand. */
6524 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
6526 struct builtin_description *d;
6527 struct builtin_description_predicates *dp;
6529 enum insn_code icode;
6530 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6531 tree arglist = TREE_OPERAND (exp, 1);
6534 enum machine_mode tmode, mode0;
6535 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6537 target = altivec_expand_ld_builtin (exp, target, expandedp);
6541 target = altivec_expand_st_builtin (exp, target, expandedp);
6545 target = altivec_expand_dst_builtin (exp, target, expandedp);
6553 case ALTIVEC_BUILTIN_STVX:
6554 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
6555 case ALTIVEC_BUILTIN_STVEBX:
6556 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
6557 case ALTIVEC_BUILTIN_STVEHX:
6558 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
6559 case ALTIVEC_BUILTIN_STVEWX:
6560 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
6561 case ALTIVEC_BUILTIN_STVXL:
6562 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
6564 case ALTIVEC_BUILTIN_MFVSCR:
6565 icode = CODE_FOR_altivec_mfvscr;
6566 tmode = insn_data[icode].operand[0].mode;
6569 || GET_MODE (target) != tmode
6570 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6571 target = gen_reg_rtx (tmode);
6573 pat = GEN_FCN (icode) (target);
6579 case ALTIVEC_BUILTIN_MTVSCR:
6580 icode = CODE_FOR_altivec_mtvscr;
6581 arg0 = TREE_VALUE (arglist);
6582 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6583 mode0 = insn_data[icode].operand[0].mode;
6585 /* If we got invalid arguments bail out before generating bad rtl. */
6586 if (arg0 == error_mark_node)
6589 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6590 op0 = copy_to_mode_reg (mode0, op0);
6592 pat = GEN_FCN (icode) (op0);
6597 case ALTIVEC_BUILTIN_DSSALL:
6598 emit_insn (gen_altivec_dssall ());
6601 case ALTIVEC_BUILTIN_DSS:
6602 icode = CODE_FOR_altivec_dss;
6603 arg0 = TREE_VALUE (arglist);
6605 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6606 mode0 = insn_data[icode].operand[0].mode;
6608 /* If we got invalid arguments bail out before generating bad rtl. */
6609 if (arg0 == error_mark_node)
6612 if (TREE_CODE (arg0) != INTEGER_CST
6613 || TREE_INT_CST_LOW (arg0) & ~0x3)
6615 error ("argument to dss must be a 2-bit unsigned literal");
6619 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6620 op0 = copy_to_mode_reg (mode0, op0);
6622 emit_insn (gen_altivec_dss (op0));
6625 case ALTIVEC_BUILTIN_COMPILETIME_ERROR:
6626 arg0 = TREE_VALUE (arglist);
6627 while (TREE_CODE (arg0) == NOP_EXPR || TREE_CODE (arg0) == ADDR_EXPR
6628 || TREE_CODE (arg0) == ARRAY_REF)
6629 arg0 = TREE_OPERAND (arg0, 0);
6630 error ("invalid parameter combination for %qs AltiVec intrinsic",
6631 TREE_STRING_POINTER (arg0));
6636 /* Expand abs* operations. */
6637 d = (struct builtin_description *) bdesc_abs;
6638 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
6639 if (d->code == fcode)
6640 return altivec_expand_abs_builtin (d->icode, arglist, target);
6642 /* Expand the AltiVec predicates. */
6643 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
6644 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
6645 if (dp->code == fcode)
6646 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
6649 /* LV* are funky. We initialized them differently. */
6652 case ALTIVEC_BUILTIN_LVSL:
6653 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
6655 case ALTIVEC_BUILTIN_LVSR:
6656 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
6658 case ALTIVEC_BUILTIN_LVEBX:
6659 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
6661 case ALTIVEC_BUILTIN_LVEHX:
6662 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
6664 case ALTIVEC_BUILTIN_LVEWX:
6665 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
6667 case ALTIVEC_BUILTIN_LVXL:
6668 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
6670 case ALTIVEC_BUILTIN_LVX:
6671 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
6682 /* Binops that need to be initialized manually, but can be expanded
6683 automagically by rs6000_expand_binop_builtin. */
6684 static struct builtin_description bdesc_2arg_spe[] =
6686 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
6687 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
6688 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
6689 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
6690 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
6691 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
6692 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
6693 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
6694 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
6695 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
6696 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
6697 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
6698 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
6699 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
6700 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
6701 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
6702 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
6703 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
6704 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
6705 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
6706 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
6707 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
6710 /* Expand the builtin in EXP and store the result in TARGET. Store
6711 true in *EXPANDEDP if we found a builtin to expand.
6713 This expands the SPE builtins that are not simple unary and binary
6716 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
6718 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6719 tree arglist = TREE_OPERAND (exp, 1);
6721 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6722 enum insn_code icode;
6723 enum machine_mode tmode, mode0;
6725 struct builtin_description *d;
6730 /* Syntax check for a 5-bit unsigned immediate. */
6733 case SPE_BUILTIN_EVSTDD:
6734 case SPE_BUILTIN_EVSTDH:
6735 case SPE_BUILTIN_EVSTDW:
6736 case SPE_BUILTIN_EVSTWHE:
6737 case SPE_BUILTIN_EVSTWHO:
6738 case SPE_BUILTIN_EVSTWWE:
6739 case SPE_BUILTIN_EVSTWWO:
6740 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6741 if (TREE_CODE (arg1) != INTEGER_CST
6742 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6744 error ("argument 2 must be a 5-bit unsigned literal");
6752 /* The evsplat*i instructions are not quite generic. */
6755 case SPE_BUILTIN_EVSPLATFI:
6756 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
6758 case SPE_BUILTIN_EVSPLATI:
6759 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
6765 d = (struct builtin_description *) bdesc_2arg_spe;
6766 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
6767 if (d->code == fcode)
6768 return rs6000_expand_binop_builtin (d->icode, arglist, target);
6770 d = (struct builtin_description *) bdesc_spe_predicates;
6771 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
6772 if (d->code == fcode)
6773 return spe_expand_predicate_builtin (d->icode, arglist, target);
6775 d = (struct builtin_description *) bdesc_spe_evsel;
6776 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
6777 if (d->code == fcode)
6778 return spe_expand_evsel_builtin (d->icode, arglist, target);
6782 case SPE_BUILTIN_EVSTDDX:
6783 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
6784 case SPE_BUILTIN_EVSTDHX:
6785 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
6786 case SPE_BUILTIN_EVSTDWX:
6787 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
6788 case SPE_BUILTIN_EVSTWHEX:
6789 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
6790 case SPE_BUILTIN_EVSTWHOX:
6791 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
6792 case SPE_BUILTIN_EVSTWWEX:
6793 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
6794 case SPE_BUILTIN_EVSTWWOX:
6795 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
6796 case SPE_BUILTIN_EVSTDD:
6797 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
6798 case SPE_BUILTIN_EVSTDH:
6799 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
6800 case SPE_BUILTIN_EVSTDW:
6801 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
6802 case SPE_BUILTIN_EVSTWHE:
6803 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
6804 case SPE_BUILTIN_EVSTWHO:
6805 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
6806 case SPE_BUILTIN_EVSTWWE:
6807 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
6808 case SPE_BUILTIN_EVSTWWO:
6809 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
6810 case SPE_BUILTIN_MFSPEFSCR:
6811 icode = CODE_FOR_spe_mfspefscr;
6812 tmode = insn_data[icode].operand[0].mode;
6815 || GET_MODE (target) != tmode
6816 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6817 target = gen_reg_rtx (tmode);
6819 pat = GEN_FCN (icode) (target);
6824 case SPE_BUILTIN_MTSPEFSCR:
6825 icode = CODE_FOR_spe_mtspefscr;
6826 arg0 = TREE_VALUE (arglist);
6827 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6828 mode0 = insn_data[icode].operand[0].mode;
6830 if (arg0 == error_mark_node)
6833 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6834 op0 = copy_to_mode_reg (mode0, op0);
6836 pat = GEN_FCN (icode) (op0);
6849 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
6851 rtx pat, scratch, tmp;
6852 tree form = TREE_VALUE (arglist);
6853 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6854 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6855 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6856 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6857 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6858 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6862 if (TREE_CODE (form) != INTEGER_CST)
6864 error ("argument 1 of __builtin_spe_predicate must be a constant");
6868 form_int = TREE_INT_CST_LOW (form);
6873 if (arg0 == error_mark_node || arg1 == error_mark_node)
6877 || GET_MODE (target) != SImode
6878 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
6879 target = gen_reg_rtx (SImode);
6881 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6882 op0 = copy_to_mode_reg (mode0, op0);
6883 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6884 op1 = copy_to_mode_reg (mode1, op1);
6886 scratch = gen_reg_rtx (CCmode);
6888 pat = GEN_FCN (icode) (scratch, op0, op1);
6893 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
6894 _lower_. We use one compare, but look in different bits of the
6895 CR for each variant.
6897 There are 2 elements in each SPE simd type (upper/lower). The CR
6898 bits are set as follows:
6900 BIT0 | BIT 1 | BIT 2 | BIT 3
6901 U | L | (U | L) | (U & L)
6903 So, for an "all" relationship, BIT 3 would be set.
6904 For an "any" relationship, BIT 2 would be set. Etc.
6906 Following traditional nomenclature, these bits map to:
6908 BIT0 | BIT 1 | BIT 2 | BIT 3
6911 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
6916 /* All variant. OV bit. */
6918 /* We need to get to the OV bit, which is the ORDERED bit. We
6919 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
6920 that's ugly and will trigger a validate_condition_mode abort.
6921 So let's just use another pattern. */
6922 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
6924 /* Any variant. EQ bit. */
6928 /* Upper variant. LT bit. */
6932 /* Lower variant. GT bit. */
6937 error ("argument 1 of __builtin_spe_predicate is out of range");
6941 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
6942 emit_move_insn (target, tmp);
6947 /* The evsel builtins look like this:
6949 e = __builtin_spe_evsel_OP (a, b, c, d);
6953 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
6954 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
6958 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
6961 tree arg0 = TREE_VALUE (arglist);
6962 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6963 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6964 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
6965 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6966 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6967 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6968 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
6969 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6970 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6975 if (arg0 == error_mark_node || arg1 == error_mark_node
6976 || arg2 == error_mark_node || arg3 == error_mark_node)
6980 || GET_MODE (target) != mode0
6981 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
6982 target = gen_reg_rtx (mode0);
6984 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6985 op0 = copy_to_mode_reg (mode0, op0);
6986 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
6987 op1 = copy_to_mode_reg (mode0, op1);
6988 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6989 op2 = copy_to_mode_reg (mode0, op2);
6990 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
6991 op3 = copy_to_mode_reg (mode0, op3);
6993 /* Generate the compare. */
6994 scratch = gen_reg_rtx (CCmode);
6995 pat = GEN_FCN (icode) (scratch, op0, op1);
7000 if (mode0 == V2SImode)
7001 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7003 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7008 /* Expand an expression EXP that calls a built-in function,
7009 with result going to TARGET if that's convenient
7010 (and in mode MODE if that's convenient).
7011 SUBTARGET may be used as the target for computing one of EXP's operands.
7012 IGNORE is nonzero if the value is to be ignored. */
7015 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7016 enum machine_mode mode ATTRIBUTE_UNUSED,
7017 int ignore ATTRIBUTE_UNUSED)
7019 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7020 tree arglist = TREE_OPERAND (exp, 1);
7021 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7022 struct builtin_description *d;
7027 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7028 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7030 int icode = (int) CODE_FOR_altivec_lvsr;
7031 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7032 enum machine_mode mode = insn_data[icode].operand[1].mode;
7036 if (!TARGET_ALTIVEC)
7039 arg = TREE_VALUE (arglist);
7040 if (TREE_CODE (TREE_TYPE (arg)) != POINTER_TYPE)
7042 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7043 addr = memory_address (mode, op);
7044 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7048 /* For the load case need to negate the address. */
7049 op = gen_reg_rtx (GET_MODE (addr));
7050 emit_insn (gen_rtx_SET (VOIDmode, op,
7051 gen_rtx_NEG (GET_MODE (addr), addr)));
7053 op = gen_rtx_MEM (mode, op);
7056 || GET_MODE (target) != tmode
7057 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7058 target = gen_reg_rtx (tmode);
7060 /*pat = gen_altivec_lvsr (target, op);*/
7061 pat = GEN_FCN (icode) (target, op);
7071 ret = altivec_expand_builtin (exp, target, &success);
7078 ret = spe_expand_builtin (exp, target, &success);
7084 if (TARGET_ALTIVEC || TARGET_SPE)
7086 /* Handle simple unary operations. */
7087 d = (struct builtin_description *) bdesc_1arg;
7088 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7089 if (d->code == fcode)
7090 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7092 /* Handle simple binary operations. */
7093 d = (struct builtin_description *) bdesc_2arg;
7094 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7095 if (d->code == fcode)
7096 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7098 /* Handle simple ternary operations. */
7099 d = (struct builtin_description *) bdesc_3arg;
7100 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7101 if (d->code == fcode)
7102 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7110 build_opaque_vector_type (tree node, int nunits)
7112 node = copy_node (node);
7113 TYPE_MAIN_VARIANT (node) = node;
7114 return build_vector_type (node, nunits);
7118 rs6000_init_builtins (void)
7120 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7121 V2SF_type_node = build_vector_type (float_type_node, 2);
7122 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7123 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7124 V4SF_type_node = build_vector_type (float_type_node, 4);
7125 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7126 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7128 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7129 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7130 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7132 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7133 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7134 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7136 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7137 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7138 'vector unsigned short'. */
7140 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7141 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7142 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7143 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7145 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7146 get_identifier ("__bool char"),
7147 bool_char_type_node));
7148 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7149 get_identifier ("__bool short"),
7150 bool_short_type_node));
7151 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7152 get_identifier ("__bool int"),
7153 bool_int_type_node));
7154 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7155 get_identifier ("__pixel"),
7158 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7159 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7160 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7161 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7163 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7164 get_identifier ("__vector unsigned char"),
7165 unsigned_V16QI_type_node));
7166 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7167 get_identifier ("__vector signed char"),
7169 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7170 get_identifier ("__vector __bool char"),
7171 bool_V16QI_type_node));
7173 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7174 get_identifier ("__vector unsigned short"),
7175 unsigned_V8HI_type_node));
7176 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7177 get_identifier ("__vector signed short"),
7179 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7180 get_identifier ("__vector __bool short"),
7181 bool_V8HI_type_node));
7183 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7184 get_identifier ("__vector unsigned int"),
7185 unsigned_V4SI_type_node));
7186 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7187 get_identifier ("__vector signed int"),
7189 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7190 get_identifier ("__vector __bool int"),
7191 bool_V4SI_type_node));
7193 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7194 get_identifier ("__vector float"),
7196 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7197 get_identifier ("__vector __pixel"),
7198 pixel_V8HI_type_node));
7201 spe_init_builtins ();
7203 altivec_init_builtins ();
7204 if (TARGET_ALTIVEC || TARGET_SPE)
7205 rs6000_common_init_builtins ();
7208 /* Search through a set of builtins and enable the mask bits.
7209 DESC is an array of builtins.
7210 SIZE is the total number of builtins.
7211 START is the builtin enum at which to start.
7212 END is the builtin enum at which to end. */
7214 enable_mask_for_builtins (struct builtin_description *desc, int size,
7215 enum rs6000_builtins start,
7216 enum rs6000_builtins end)
7220 for (i = 0; i < size; ++i)
7221 if (desc[i].code == start)
7227 for (; i < size; ++i)
7229 /* Flip all the bits on. */
7230 desc[i].mask = target_flags;
7231 if (desc[i].code == end)
7237 spe_init_builtins (void)
7239 tree endlink = void_list_node;
7240 tree puint_type_node = build_pointer_type (unsigned_type_node);
7241 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7242 struct builtin_description *d;
7245 tree v2si_ftype_4_v2si
7246 = build_function_type
7247 (opaque_V2SI_type_node,
7248 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7249 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7250 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7251 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7254 tree v2sf_ftype_4_v2sf
7255 = build_function_type
7256 (opaque_V2SF_type_node,
7257 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7258 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7259 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7260 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7263 tree int_ftype_int_v2si_v2si
7264 = build_function_type
7266 tree_cons (NULL_TREE, integer_type_node,
7267 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7268 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7271 tree int_ftype_int_v2sf_v2sf
7272 = build_function_type
7274 tree_cons (NULL_TREE, integer_type_node,
7275 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7276 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7279 tree void_ftype_v2si_puint_int
7280 = build_function_type (void_type_node,
7281 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7282 tree_cons (NULL_TREE, puint_type_node,
7283 tree_cons (NULL_TREE,
7287 tree void_ftype_v2si_puint_char
7288 = build_function_type (void_type_node,
7289 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7290 tree_cons (NULL_TREE, puint_type_node,
7291 tree_cons (NULL_TREE,
7295 tree void_ftype_v2si_pv2si_int
7296 = build_function_type (void_type_node,
7297 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7298 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7299 tree_cons (NULL_TREE,
7303 tree void_ftype_v2si_pv2si_char
7304 = build_function_type (void_type_node,
7305 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7306 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7307 tree_cons (NULL_TREE,
7312 = build_function_type (void_type_node,
7313 tree_cons (NULL_TREE, integer_type_node, endlink));
7316 = build_function_type (integer_type_node, endlink);
7318 tree v2si_ftype_pv2si_int
7319 = build_function_type (opaque_V2SI_type_node,
7320 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7321 tree_cons (NULL_TREE, integer_type_node,
7324 tree v2si_ftype_puint_int
7325 = build_function_type (opaque_V2SI_type_node,
7326 tree_cons (NULL_TREE, puint_type_node,
7327 tree_cons (NULL_TREE, integer_type_node,
7330 tree v2si_ftype_pushort_int
7331 = build_function_type (opaque_V2SI_type_node,
7332 tree_cons (NULL_TREE, pushort_type_node,
7333 tree_cons (NULL_TREE, integer_type_node,
7336 tree v2si_ftype_signed_char
7337 = build_function_type (opaque_V2SI_type_node,
7338 tree_cons (NULL_TREE, signed_char_type_node,
7341 /* The initialization of the simple binary and unary builtins is
7342 done in rs6000_common_init_builtins, but we have to enable the
7343 mask bits here manually because we have run out of `target_flags'
7344 bits. We really need to redesign this mask business. */
7346 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
7347 ARRAY_SIZE (bdesc_2arg),
7350 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
7351 ARRAY_SIZE (bdesc_1arg),
7353 SPE_BUILTIN_EVSUBFUSIAAW);
7354 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
7355 ARRAY_SIZE (bdesc_spe_predicates),
7356 SPE_BUILTIN_EVCMPEQ,
7357 SPE_BUILTIN_EVFSTSTLT);
7358 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
7359 ARRAY_SIZE (bdesc_spe_evsel),
7360 SPE_BUILTIN_EVSEL_CMPGTS,
7361 SPE_BUILTIN_EVSEL_FSTSTEQ);
7363 (*lang_hooks.decls.pushdecl)
7364 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
7365 opaque_V2SI_type_node));
7367 /* Initialize irregular SPE builtins. */
7369 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
7370 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
7371 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
7372 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
7373 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
7374 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
7375 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
7376 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
7377 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
7378 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
7379 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
7380 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
7381 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
7382 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
7383 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
7384 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
7385 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
7386 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
7389 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
7390 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
7391 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
7392 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
7393 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
7394 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
7395 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
7396 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
7397 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
7398 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
7399 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
7400 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
7401 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
7402 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
7403 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
7404 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
7405 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
7406 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
7407 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
7408 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
7409 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
7410 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
7413 d = (struct builtin_description *) bdesc_spe_predicates;
7414 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
7418 switch (insn_data[d->icode].operand[1].mode)
7421 type = int_ftype_int_v2si_v2si;
7424 type = int_ftype_int_v2sf_v2sf;
7430 def_builtin (d->mask, d->name, type, d->code);
7433 /* Evsel predicates. */
7434 d = (struct builtin_description *) bdesc_spe_evsel;
7435 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
7439 switch (insn_data[d->icode].operand[1].mode)
7442 type = v2si_ftype_4_v2si;
7445 type = v2sf_ftype_4_v2sf;
7451 def_builtin (d->mask, d->name, type, d->code);
7456 altivec_init_builtins (void)
7458 struct builtin_description *d;
7459 struct builtin_description_predicates *dp;
7461 tree pfloat_type_node = build_pointer_type (float_type_node);
7462 tree pint_type_node = build_pointer_type (integer_type_node);
7463 tree pshort_type_node = build_pointer_type (short_integer_type_node);
7464 tree pchar_type_node = build_pointer_type (char_type_node);
7466 tree pvoid_type_node = build_pointer_type (void_type_node);
7468 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
7469 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
7470 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
7471 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
7473 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
7475 tree int_ftype_int_v4si_v4si
7476 = build_function_type_list (integer_type_node,
7477 integer_type_node, V4SI_type_node,
7478 V4SI_type_node, NULL_TREE);
7479 tree v4sf_ftype_pcfloat
7480 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
7481 tree void_ftype_pfloat_v4sf
7482 = build_function_type_list (void_type_node,
7483 pfloat_type_node, V4SF_type_node, NULL_TREE);
7484 tree v4si_ftype_pcint
7485 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
7486 tree void_ftype_pint_v4si
7487 = build_function_type_list (void_type_node,
7488 pint_type_node, V4SI_type_node, NULL_TREE);
7489 tree v8hi_ftype_pcshort
7490 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
7491 tree void_ftype_pshort_v8hi
7492 = build_function_type_list (void_type_node,
7493 pshort_type_node, V8HI_type_node, NULL_TREE);
7494 tree v16qi_ftype_pcchar
7495 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
7496 tree void_ftype_pchar_v16qi
7497 = build_function_type_list (void_type_node,
7498 pchar_type_node, V16QI_type_node, NULL_TREE);
7499 tree void_ftype_v4si
7500 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
7501 tree v8hi_ftype_void
7502 = build_function_type (V8HI_type_node, void_list_node);
7503 tree void_ftype_void
7504 = build_function_type (void_type_node, void_list_node);
7506 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
7508 tree v16qi_ftype_long_pcvoid
7509 = build_function_type_list (V16QI_type_node,
7510 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7511 tree v8hi_ftype_long_pcvoid
7512 = build_function_type_list (V8HI_type_node,
7513 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7514 tree v4si_ftype_long_pcvoid
7515 = build_function_type_list (V4SI_type_node,
7516 long_integer_type_node, pcvoid_type_node, NULL_TREE);
7518 tree void_ftype_v4si_long_pvoid
7519 = build_function_type_list (void_type_node,
7520 V4SI_type_node, long_integer_type_node,
7521 pvoid_type_node, NULL_TREE);
7522 tree void_ftype_v16qi_long_pvoid
7523 = build_function_type_list (void_type_node,
7524 V16QI_type_node, long_integer_type_node,
7525 pvoid_type_node, NULL_TREE);
7526 tree void_ftype_v8hi_long_pvoid
7527 = build_function_type_list (void_type_node,
7528 V8HI_type_node, long_integer_type_node,
7529 pvoid_type_node, NULL_TREE);
7530 tree int_ftype_int_v8hi_v8hi
7531 = build_function_type_list (integer_type_node,
7532 integer_type_node, V8HI_type_node,
7533 V8HI_type_node, NULL_TREE);
7534 tree int_ftype_int_v16qi_v16qi
7535 = build_function_type_list (integer_type_node,
7536 integer_type_node, V16QI_type_node,
7537 V16QI_type_node, NULL_TREE);
7538 tree int_ftype_int_v4sf_v4sf
7539 = build_function_type_list (integer_type_node,
7540 integer_type_node, V4SF_type_node,
7541 V4SF_type_node, NULL_TREE);
7542 tree v4si_ftype_v4si
7543 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
7544 tree v8hi_ftype_v8hi
7545 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
7546 tree v16qi_ftype_v16qi
7547 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
7548 tree v4sf_ftype_v4sf
7549 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7550 tree void_ftype_pcvoid_int_int
7551 = build_function_type_list (void_type_node,
7552 pcvoid_type_node, integer_type_node,
7553 integer_type_node, NULL_TREE);
7554 tree int_ftype_pcchar
7555 = build_function_type_list (integer_type_node,
7556 pcchar_type_node, NULL_TREE);
7558 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
7559 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
7560 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
7561 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
7562 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
7563 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
7564 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
7565 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
7566 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
7567 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
7568 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
7569 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
7570 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
7571 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
7572 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
7573 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
7574 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
7575 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
7576 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
7577 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
7578 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
7579 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
7580 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
7581 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
7582 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
7583 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
7584 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
7585 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
7586 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
7587 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
7588 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
7589 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
7591 /* See altivec.h for usage of "__builtin_altivec_compiletime_error". */
7592 def_builtin (MASK_ALTIVEC, "__builtin_altivec_compiletime_error", int_ftype_pcchar,
7593 ALTIVEC_BUILTIN_COMPILETIME_ERROR);
7595 /* Add the DST variants. */
7596 d = (struct builtin_description *) bdesc_dst;
7597 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7598 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
7600 /* Initialize the predicates. */
7601 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7602 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7604 enum machine_mode mode1;
7607 mode1 = insn_data[dp->icode].operand[1].mode;
7612 type = int_ftype_int_v4si_v4si;
7615 type = int_ftype_int_v8hi_v8hi;
7618 type = int_ftype_int_v16qi_v16qi;
7621 type = int_ftype_int_v4sf_v4sf;
7627 def_builtin (dp->mask, dp->name, type, dp->code);
7630 /* Initialize the abs* operators. */
7631 d = (struct builtin_description *) bdesc_abs;
7632 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7634 enum machine_mode mode0;
7637 mode0 = insn_data[d->icode].operand[0].mode;
7642 type = v4si_ftype_v4si;
7645 type = v8hi_ftype_v8hi;
7648 type = v16qi_ftype_v16qi;
7651 type = v4sf_ftype_v4sf;
7657 def_builtin (d->mask, d->name, type, d->code);
7664 /* Initialize target builtin that implements
7665 targetm.vectorize.builtin_mask_for_load. */
7667 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
7668 v16qi_ftype_long_pcvoid,
7669 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
7670 BUILT_IN_MD, NULL, NULL_TREE);
7671 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
7672 altivec_builtin_mask_for_load = decl;
7677 rs6000_common_init_builtins (void)
7679 struct builtin_description *d;
7682 tree v4sf_ftype_v4sf_v4sf_v16qi
7683 = build_function_type_list (V4SF_type_node,
7684 V4SF_type_node, V4SF_type_node,
7685 V16QI_type_node, NULL_TREE);
7686 tree v4si_ftype_v4si_v4si_v16qi
7687 = build_function_type_list (V4SI_type_node,
7688 V4SI_type_node, V4SI_type_node,
7689 V16QI_type_node, NULL_TREE);
7690 tree v8hi_ftype_v8hi_v8hi_v16qi
7691 = build_function_type_list (V8HI_type_node,
7692 V8HI_type_node, V8HI_type_node,
7693 V16QI_type_node, NULL_TREE);
7694 tree v16qi_ftype_v16qi_v16qi_v16qi
7695 = build_function_type_list (V16QI_type_node,
7696 V16QI_type_node, V16QI_type_node,
7697 V16QI_type_node, NULL_TREE);
7699 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
7701 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
7702 tree v16qi_ftype_int
7703 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
7704 tree v8hi_ftype_v16qi
7705 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
7706 tree v4sf_ftype_v4sf
7707 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
7709 tree v2si_ftype_v2si_v2si
7710 = build_function_type_list (opaque_V2SI_type_node,
7711 opaque_V2SI_type_node,
7712 opaque_V2SI_type_node, NULL_TREE);
7714 tree v2sf_ftype_v2sf_v2sf
7715 = build_function_type_list (opaque_V2SF_type_node,
7716 opaque_V2SF_type_node,
7717 opaque_V2SF_type_node, NULL_TREE);
7719 tree v2si_ftype_int_int
7720 = build_function_type_list (opaque_V2SI_type_node,
7721 integer_type_node, integer_type_node,
7724 tree v2si_ftype_v2si
7725 = build_function_type_list (opaque_V2SI_type_node,
7726 opaque_V2SI_type_node, NULL_TREE);
7728 tree v2sf_ftype_v2sf
7729 = build_function_type_list (opaque_V2SF_type_node,
7730 opaque_V2SF_type_node, NULL_TREE);
7732 tree v2sf_ftype_v2si
7733 = build_function_type_list (opaque_V2SF_type_node,
7734 opaque_V2SI_type_node, NULL_TREE);
7736 tree v2si_ftype_v2sf
7737 = build_function_type_list (opaque_V2SI_type_node,
7738 opaque_V2SF_type_node, NULL_TREE);
7740 tree v2si_ftype_v2si_char
7741 = build_function_type_list (opaque_V2SI_type_node,
7742 opaque_V2SI_type_node,
7743 char_type_node, NULL_TREE);
7745 tree v2si_ftype_int_char
7746 = build_function_type_list (opaque_V2SI_type_node,
7747 integer_type_node, char_type_node, NULL_TREE);
7749 tree v2si_ftype_char
7750 = build_function_type_list (opaque_V2SI_type_node,
7751 char_type_node, NULL_TREE);
7753 tree int_ftype_int_int
7754 = build_function_type_list (integer_type_node,
7755 integer_type_node, integer_type_node,
7758 tree v4si_ftype_v4si_v4si
7759 = build_function_type_list (V4SI_type_node,
7760 V4SI_type_node, V4SI_type_node, NULL_TREE);
7761 tree v4sf_ftype_v4si_int
7762 = build_function_type_list (V4SF_type_node,
7763 V4SI_type_node, integer_type_node, NULL_TREE);
7764 tree v4si_ftype_v4sf_int
7765 = build_function_type_list (V4SI_type_node,
7766 V4SF_type_node, integer_type_node, NULL_TREE);
7767 tree v4si_ftype_v4si_int
7768 = build_function_type_list (V4SI_type_node,
7769 V4SI_type_node, integer_type_node, NULL_TREE);
7770 tree v8hi_ftype_v8hi_int
7771 = build_function_type_list (V8HI_type_node,
7772 V8HI_type_node, integer_type_node, NULL_TREE);
7773 tree v16qi_ftype_v16qi_int
7774 = build_function_type_list (V16QI_type_node,
7775 V16QI_type_node, integer_type_node, NULL_TREE);
7776 tree v16qi_ftype_v16qi_v16qi_int
7777 = build_function_type_list (V16QI_type_node,
7778 V16QI_type_node, V16QI_type_node,
7779 integer_type_node, NULL_TREE);
7780 tree v8hi_ftype_v8hi_v8hi_int
7781 = build_function_type_list (V8HI_type_node,
7782 V8HI_type_node, V8HI_type_node,
7783 integer_type_node, NULL_TREE);
7784 tree v4si_ftype_v4si_v4si_int
7785 = build_function_type_list (V4SI_type_node,
7786 V4SI_type_node, V4SI_type_node,
7787 integer_type_node, NULL_TREE);
7788 tree v4sf_ftype_v4sf_v4sf_int
7789 = build_function_type_list (V4SF_type_node,
7790 V4SF_type_node, V4SF_type_node,
7791 integer_type_node, NULL_TREE);
7792 tree v4sf_ftype_v4sf_v4sf
7793 = build_function_type_list (V4SF_type_node,
7794 V4SF_type_node, V4SF_type_node, NULL_TREE);
7795 tree v4sf_ftype_v4sf_v4sf_v4si
7796 = build_function_type_list (V4SF_type_node,
7797 V4SF_type_node, V4SF_type_node,
7798 V4SI_type_node, NULL_TREE);
7799 tree v4sf_ftype_v4sf_v4sf_v4sf
7800 = build_function_type_list (V4SF_type_node,
7801 V4SF_type_node, V4SF_type_node,
7802 V4SF_type_node, NULL_TREE);
7803 tree v4si_ftype_v4si_v4si_v4si
7804 = build_function_type_list (V4SI_type_node,
7805 V4SI_type_node, V4SI_type_node,
7806 V4SI_type_node, NULL_TREE);
7807 tree v8hi_ftype_v8hi_v8hi
7808 = build_function_type_list (V8HI_type_node,
7809 V8HI_type_node, V8HI_type_node, NULL_TREE);
7810 tree v8hi_ftype_v8hi_v8hi_v8hi
7811 = build_function_type_list (V8HI_type_node,
7812 V8HI_type_node, V8HI_type_node,
7813 V8HI_type_node, NULL_TREE);
7814 tree v4si_ftype_v8hi_v8hi_v4si
7815 = build_function_type_list (V4SI_type_node,
7816 V8HI_type_node, V8HI_type_node,
7817 V4SI_type_node, NULL_TREE);
7818 tree v4si_ftype_v16qi_v16qi_v4si
7819 = build_function_type_list (V4SI_type_node,
7820 V16QI_type_node, V16QI_type_node,
7821 V4SI_type_node, NULL_TREE);
7822 tree v16qi_ftype_v16qi_v16qi
7823 = build_function_type_list (V16QI_type_node,
7824 V16QI_type_node, V16QI_type_node, NULL_TREE);
7825 tree v4si_ftype_v4sf_v4sf
7826 = build_function_type_list (V4SI_type_node,
7827 V4SF_type_node, V4SF_type_node, NULL_TREE);
7828 tree v8hi_ftype_v16qi_v16qi
7829 = build_function_type_list (V8HI_type_node,
7830 V16QI_type_node, V16QI_type_node, NULL_TREE);
7831 tree v4si_ftype_v8hi_v8hi
7832 = build_function_type_list (V4SI_type_node,
7833 V8HI_type_node, V8HI_type_node, NULL_TREE);
7834 tree v8hi_ftype_v4si_v4si
7835 = build_function_type_list (V8HI_type_node,
7836 V4SI_type_node, V4SI_type_node, NULL_TREE);
7837 tree v16qi_ftype_v8hi_v8hi
7838 = build_function_type_list (V16QI_type_node,
7839 V8HI_type_node, V8HI_type_node, NULL_TREE);
7840 tree v4si_ftype_v16qi_v4si
7841 = build_function_type_list (V4SI_type_node,
7842 V16QI_type_node, V4SI_type_node, NULL_TREE);
7843 tree v4si_ftype_v16qi_v16qi
7844 = build_function_type_list (V4SI_type_node,
7845 V16QI_type_node, V16QI_type_node, NULL_TREE);
7846 tree v4si_ftype_v8hi_v4si
7847 = build_function_type_list (V4SI_type_node,
7848 V8HI_type_node, V4SI_type_node, NULL_TREE);
7849 tree v4si_ftype_v8hi
7850 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
7851 tree int_ftype_v4si_v4si
7852 = build_function_type_list (integer_type_node,
7853 V4SI_type_node, V4SI_type_node, NULL_TREE);
7854 tree int_ftype_v4sf_v4sf
7855 = build_function_type_list (integer_type_node,
7856 V4SF_type_node, V4SF_type_node, NULL_TREE);
7857 tree int_ftype_v16qi_v16qi
7858 = build_function_type_list (integer_type_node,
7859 V16QI_type_node, V16QI_type_node, NULL_TREE);
7860 tree int_ftype_v8hi_v8hi
7861 = build_function_type_list (integer_type_node,
7862 V8HI_type_node, V8HI_type_node, NULL_TREE);
7864 /* Add the simple ternary operators. */
7865 d = (struct builtin_description *) bdesc_3arg;
7866 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7869 enum machine_mode mode0, mode1, mode2, mode3;
7872 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7875 mode0 = insn_data[d->icode].operand[0].mode;
7876 mode1 = insn_data[d->icode].operand[1].mode;
7877 mode2 = insn_data[d->icode].operand[2].mode;
7878 mode3 = insn_data[d->icode].operand[3].mode;
7880 /* When all four are of the same mode. */
7881 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
7886 type = v4si_ftype_v4si_v4si_v4si;
7889 type = v4sf_ftype_v4sf_v4sf_v4sf;
7892 type = v8hi_ftype_v8hi_v8hi_v8hi;
7895 type = v16qi_ftype_v16qi_v16qi_v16qi;
7901 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
7906 type = v4si_ftype_v4si_v4si_v16qi;
7909 type = v4sf_ftype_v4sf_v4sf_v16qi;
7912 type = v8hi_ftype_v8hi_v8hi_v16qi;
7915 type = v16qi_ftype_v16qi_v16qi_v16qi;
7921 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
7922 && mode3 == V4SImode)
7923 type = v4si_ftype_v16qi_v16qi_v4si;
7924 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
7925 && mode3 == V4SImode)
7926 type = v4si_ftype_v8hi_v8hi_v4si;
7927 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
7928 && mode3 == V4SImode)
7929 type = v4sf_ftype_v4sf_v4sf_v4si;
7931 /* vchar, vchar, vchar, 4 bit literal. */
7932 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
7934 type = v16qi_ftype_v16qi_v16qi_int;
7936 /* vshort, vshort, vshort, 4 bit literal. */
7937 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
7939 type = v8hi_ftype_v8hi_v8hi_int;
7941 /* vint, vint, vint, 4 bit literal. */
7942 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
7944 type = v4si_ftype_v4si_v4si_int;
7946 /* vfloat, vfloat, vfloat, 4 bit literal. */
7947 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
7949 type = v4sf_ftype_v4sf_v4sf_int;
7954 def_builtin (d->mask, d->name, type, d->code);
7957 /* Add the simple binary operators. */
7958 d = (struct builtin_description *) bdesc_2arg;
7959 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7961 enum machine_mode mode0, mode1, mode2;
7964 if (d->name == 0 || d->icode == CODE_FOR_nothing)
7967 mode0 = insn_data[d->icode].operand[0].mode;
7968 mode1 = insn_data[d->icode].operand[1].mode;
7969 mode2 = insn_data[d->icode].operand[2].mode;
7971 /* When all three operands are of the same mode. */
7972 if (mode0 == mode1 && mode1 == mode2)
7977 type = v4sf_ftype_v4sf_v4sf;
7980 type = v4si_ftype_v4si_v4si;
7983 type = v16qi_ftype_v16qi_v16qi;
7986 type = v8hi_ftype_v8hi_v8hi;
7989 type = v2si_ftype_v2si_v2si;
7992 type = v2sf_ftype_v2sf_v2sf;
7995 type = int_ftype_int_int;
8002 /* A few other combos we really don't want to do manually. */
8004 /* vint, vfloat, vfloat. */
8005 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8006 type = v4si_ftype_v4sf_v4sf;
8008 /* vshort, vchar, vchar. */
8009 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8010 type = v8hi_ftype_v16qi_v16qi;
8012 /* vint, vshort, vshort. */
8013 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8014 type = v4si_ftype_v8hi_v8hi;
8016 /* vshort, vint, vint. */
8017 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8018 type = v8hi_ftype_v4si_v4si;
8020 /* vchar, vshort, vshort. */
8021 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8022 type = v16qi_ftype_v8hi_v8hi;
8024 /* vint, vchar, vint. */
8025 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8026 type = v4si_ftype_v16qi_v4si;
8028 /* vint, vchar, vchar. */
8029 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8030 type = v4si_ftype_v16qi_v16qi;
8032 /* vint, vshort, vint. */
8033 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8034 type = v4si_ftype_v8hi_v4si;
8036 /* vint, vint, 5 bit literal. */
8037 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8038 type = v4si_ftype_v4si_int;
8040 /* vshort, vshort, 5 bit literal. */
8041 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8042 type = v8hi_ftype_v8hi_int;
8044 /* vchar, vchar, 5 bit literal. */
8045 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8046 type = v16qi_ftype_v16qi_int;
8048 /* vfloat, vint, 5 bit literal. */
8049 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8050 type = v4sf_ftype_v4si_int;
8052 /* vint, vfloat, 5 bit literal. */
8053 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8054 type = v4si_ftype_v4sf_int;
8056 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8057 type = v2si_ftype_int_int;
8059 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8060 type = v2si_ftype_v2si_char;
8062 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8063 type = v2si_ftype_int_char;
8066 else if (mode0 == SImode)
8071 type = int_ftype_v4si_v4si;
8074 type = int_ftype_v4sf_v4sf;
8077 type = int_ftype_v16qi_v16qi;
8080 type = int_ftype_v8hi_v8hi;
8090 def_builtin (d->mask, d->name, type, d->code);
8093 /* Add the simple unary operators. */
8094 d = (struct builtin_description *) bdesc_1arg;
8095 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8097 enum machine_mode mode0, mode1;
8100 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8103 mode0 = insn_data[d->icode].operand[0].mode;
8104 mode1 = insn_data[d->icode].operand[1].mode;
8106 if (mode0 == V4SImode && mode1 == QImode)
8107 type = v4si_ftype_int;
8108 else if (mode0 == V8HImode && mode1 == QImode)
8109 type = v8hi_ftype_int;
8110 else if (mode0 == V16QImode && mode1 == QImode)
8111 type = v16qi_ftype_int;
8112 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8113 type = v4sf_ftype_v4sf;
8114 else if (mode0 == V8HImode && mode1 == V16QImode)
8115 type = v8hi_ftype_v16qi;
8116 else if (mode0 == V4SImode && mode1 == V8HImode)
8117 type = v4si_ftype_v8hi;
8118 else if (mode0 == V2SImode && mode1 == V2SImode)
8119 type = v2si_ftype_v2si;
8120 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8121 type = v2sf_ftype_v2sf;
8122 else if (mode0 == V2SFmode && mode1 == V2SImode)
8123 type = v2sf_ftype_v2si;
8124 else if (mode0 == V2SImode && mode1 == V2SFmode)
8125 type = v2si_ftype_v2sf;
8126 else if (mode0 == V2SImode && mode1 == QImode)
8127 type = v2si_ftype_char;
8131 def_builtin (d->mask, d->name, type, d->code);
8136 rs6000_init_libfuncs (void)
8138 if (!TARGET_HARD_FLOAT)
8141 if (DEFAULT_ABI != ABI_V4)
8143 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
8145 /* AIX library routines for float->int conversion. */
8146 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
8147 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
8148 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
8149 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
8152 /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
8153 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
8154 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
8155 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
8156 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
8160 /* 32-bit SVR4 quad floating point routines. */
8162 set_optab_libfunc (add_optab, TFmode, "_q_add");
8163 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
8164 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
8165 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
8166 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
8167 if (TARGET_PPC_GPOPT || TARGET_POWER2)
8168 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
8170 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
8171 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
8172 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
8173 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
8174 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
8175 set_optab_libfunc (le_optab, TFmode, "_q_fle");
8177 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
8178 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
8179 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
8180 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
8181 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
8182 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
8183 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
8188 /* Expand a block clear operation, and return 1 if successful. Return 0
8189 if we should let the compiler generate normal code.
8191 operands[0] is the destination
8192 operands[1] is the length
8193 operands[2] is the alignment */
8196 expand_block_clear (rtx operands[])
8198 rtx orig_dest = operands[0];
8199 rtx bytes_rtx = operands[1];
8200 rtx align_rtx = operands[2];
8201 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
8202 HOST_WIDE_INT align;
8203 HOST_WIDE_INT bytes;
8208 /* If this is not a fixed size move, just call memcpy */
8212 /* If this is not a fixed size alignment, abort */
8213 if (GET_CODE (align_rtx) != CONST_INT)
8215 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8217 /* Anything to clear? */
8218 bytes = INTVAL (bytes_rtx);
8222 /* Use the builtin memset after a point, to avoid huge code bloat.
8223 When optimize_size, avoid any significant code bloat; calling
8224 memset is about 4 instructions, so allow for one instruction to
8225 load zero and three to do clearing. */
8226 if (TARGET_ALTIVEC && align >= 128)
8228 else if (TARGET_POWERPC64 && align >= 32)
8233 if (optimize_size && bytes > 3 * clear_step)
8235 if (! optimize_size && bytes > 8 * clear_step)
8238 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
8240 enum machine_mode mode = BLKmode;
8243 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
8248 else if (bytes >= 8 && TARGET_POWERPC64
8249 /* 64-bit loads and stores require word-aligned
8251 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8256 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8257 { /* move 4 bytes */
8261 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8262 { /* move 2 bytes */
8266 else /* move 1 byte at a time */
8272 dest = adjust_address (orig_dest, mode, offset);
8274 emit_move_insn (dest, CONST0_RTX (mode));
8281 /* Expand a block move operation, and return 1 if successful. Return 0
8282 if we should let the compiler generate normal code.
8284 operands[0] is the destination
8285 operands[1] is the source
8286 operands[2] is the length
8287 operands[3] is the alignment */
8289 #define MAX_MOVE_REG 4
8292 expand_block_move (rtx operands[])
8294 rtx orig_dest = operands[0];
8295 rtx orig_src = operands[1];
8296 rtx bytes_rtx = operands[2];
8297 rtx align_rtx = operands[3];
8298 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
8303 rtx stores[MAX_MOVE_REG];
8306 /* If this is not a fixed size move, just call memcpy */
8310 /* If this is not a fixed size alignment, abort */
8311 if (GET_CODE (align_rtx) != CONST_INT)
8313 align = INTVAL (align_rtx) * BITS_PER_UNIT;
8315 /* Anything to move? */
8316 bytes = INTVAL (bytes_rtx);
8320 /* store_one_arg depends on expand_block_move to handle at least the size of
8321 reg_parm_stack_space. */
8322 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
8325 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
8328 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
8329 rtx (*mov) (rtx, rtx);
8331 enum machine_mode mode = BLKmode;
8334 /* Altivec first, since it will be faster than a string move
8335 when it applies, and usually not significantly larger. */
8336 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
8340 gen_func.mov = gen_movv4si;
8342 else if (TARGET_STRING
8343 && bytes > 24 /* move up to 32 bytes at a time */
8351 && ! fixed_regs[12])
8353 move_bytes = (bytes > 32) ? 32 : bytes;
8354 gen_func.movmemsi = gen_movmemsi_8reg;
8356 else if (TARGET_STRING
8357 && bytes > 16 /* move up to 24 bytes at a time */
8363 && ! fixed_regs[10])
8365 move_bytes = (bytes > 24) ? 24 : bytes;
8366 gen_func.movmemsi = gen_movmemsi_6reg;
8368 else if (TARGET_STRING
8369 && bytes > 8 /* move up to 16 bytes at a time */
8375 move_bytes = (bytes > 16) ? 16 : bytes;
8376 gen_func.movmemsi = gen_movmemsi_4reg;
8378 else if (bytes >= 8 && TARGET_POWERPC64
8379 /* 64-bit loads and stores require word-aligned
8381 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
8385 gen_func.mov = gen_movdi;
8387 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
8388 { /* move up to 8 bytes at a time */
8389 move_bytes = (bytes > 8) ? 8 : bytes;
8390 gen_func.movmemsi = gen_movmemsi_2reg;
8392 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
8393 { /* move 4 bytes */
8396 gen_func.mov = gen_movsi;
8398 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
8399 { /* move 2 bytes */
8402 gen_func.mov = gen_movhi;
8404 else if (TARGET_STRING && bytes > 1)
8405 { /* move up to 4 bytes at a time */
8406 move_bytes = (bytes > 4) ? 4 : bytes;
8407 gen_func.movmemsi = gen_movmemsi_1reg;
8409 else /* move 1 byte at a time */
8413 gen_func.mov = gen_movqi;
8416 src = adjust_address (orig_src, mode, offset);
8417 dest = adjust_address (orig_dest, mode, offset);
8419 if (mode != BLKmode)
8421 rtx tmp_reg = gen_reg_rtx (mode);
8423 emit_insn ((*gen_func.mov) (tmp_reg, src));
8424 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
8427 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
8430 for (i = 0; i < num_reg; i++)
8431 emit_insn (stores[i]);
8435 if (mode == BLKmode)
8437 /* Move the address into scratch registers. The movmemsi
8438 patterns require zero offset. */
8439 if (!REG_P (XEXP (src, 0)))
8441 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
8442 src = replace_equiv_address (src, src_reg);
8444 set_mem_size (src, GEN_INT (move_bytes));
8446 if (!REG_P (XEXP (dest, 0)))
8448 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
8449 dest = replace_equiv_address (dest, dest_reg);
8451 set_mem_size (dest, GEN_INT (move_bytes));
8453 emit_insn ((*gen_func.movmemsi) (dest, src,
8454 GEN_INT (move_bytes & 31),
8463 /* Return a string to perform a load_multiple operation.
8464 operands[0] is the vector.
8465 operands[1] is the source address.
8466 operands[2] is the first destination register. */
8469 rs6000_output_load_multiple (rtx operands[3])
8471 /* We have to handle the case where the pseudo used to contain the address
8472 is assigned to one of the output registers. */
8474 int words = XVECLEN (operands[0], 0);
8477 if (XVECLEN (operands[0], 0) == 1)
8478 return "{l|lwz} %2,0(%1)";
8480 for (i = 0; i < words; i++)
8481 if (refers_to_regno_p (REGNO (operands[2]) + i,
8482 REGNO (operands[2]) + i + 1, operands[1], 0))
8486 xop[0] = GEN_INT (4 * (words-1));
8487 xop[1] = operands[1];
8488 xop[2] = operands[2];
8489 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
8494 xop[0] = GEN_INT (4 * (words-1));
8495 xop[1] = operands[1];
8496 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
8497 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
8502 for (j = 0; j < words; j++)
8505 xop[0] = GEN_INT (j * 4);
8506 xop[1] = operands[1];
8507 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
8508 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
8510 xop[0] = GEN_INT (i * 4);
8511 xop[1] = operands[1];
8512 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
8517 return "{lsi|lswi} %2,%1,%N0";
8521 /* A validation routine: say whether CODE, a condition code, and MODE
8522 match. The other alternatives either don't make sense or should
8523 never be generated. */
8526 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
8528 if ((GET_RTX_CLASS (code) != RTX_COMPARE
8529 && GET_RTX_CLASS (code) != RTX_COMM_COMPARE)
8530 || GET_MODE_CLASS (mode) != MODE_CC)
8533 /* These don't make sense. */
8534 if ((code == GT || code == LT || code == GE || code == LE)
8535 && mode == CCUNSmode)
8538 if ((code == GTU || code == LTU || code == GEU || code == LEU)
8539 && mode != CCUNSmode)
8542 if (mode != CCFPmode
8543 && (code == ORDERED || code == UNORDERED
8544 || code == UNEQ || code == LTGT
8545 || code == UNGT || code == UNLT
8546 || code == UNGE || code == UNLE))
8549 /* These should never be generated except for
8550 flag_finite_math_only. */
8551 if (mode == CCFPmode
8552 && ! flag_finite_math_only
8553 && (code == LE || code == GE
8554 || code == UNEQ || code == LTGT
8555 || code == UNGT || code == UNLT))
8558 /* These are invalid; the information is not there. */
8559 if (mode == CCEQmode
8560 && code != EQ && code != NE)
8565 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
8566 mask required to convert the result of a rotate insn into a shift
8567 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
8570 includes_lshift_p (rtx shiftop, rtx andop)
8572 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8574 shift_mask <<= INTVAL (shiftop);
8576 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8579 /* Similar, but for right shift. */
8582 includes_rshift_p (rtx shiftop, rtx andop)
8584 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
8586 shift_mask >>= INTVAL (shiftop);
8588 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
8591 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
8592 to perform a left shift. It must have exactly SHIFTOP least
8593 significant 0's, then one or more 1's, then zero or more 0's. */
8596 includes_rldic_lshift_p (rtx shiftop, rtx andop)
8598 if (GET_CODE (andop) == CONST_INT)
8600 HOST_WIDE_INT c, lsb, shift_mask;
8603 if (c == 0 || c == ~0)
8607 shift_mask <<= INTVAL (shiftop);
8609 /* Find the least significant one bit. */
8612 /* It must coincide with the LSB of the shift mask. */
8613 if (-lsb != shift_mask)
8616 /* Invert to look for the next transition (if any). */
8619 /* Remove the low group of ones (originally low group of zeros). */
8622 /* Again find the lsb, and check we have all 1's above. */
8626 else if (GET_CODE (andop) == CONST_DOUBLE
8627 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8629 HOST_WIDE_INT low, high, lsb;
8630 HOST_WIDE_INT shift_mask_low, shift_mask_high;
8632 low = CONST_DOUBLE_LOW (andop);
8633 if (HOST_BITS_PER_WIDE_INT < 64)
8634 high = CONST_DOUBLE_HIGH (andop);
8636 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
8637 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
8640 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8642 shift_mask_high = ~0;
8643 if (INTVAL (shiftop) > 32)
8644 shift_mask_high <<= INTVAL (shiftop) - 32;
8648 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
8655 return high == -lsb;
8658 shift_mask_low = ~0;
8659 shift_mask_low <<= INTVAL (shiftop);
8663 if (-lsb != shift_mask_low)
8666 if (HOST_BITS_PER_WIDE_INT < 64)
8671 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
8674 return high == -lsb;
8678 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
8684 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
8685 to perform a left shift. It must have SHIFTOP or more least
8686 significant 0's, with the remainder of the word 1's. */
8689 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
8691 if (GET_CODE (andop) == CONST_INT)
8693 HOST_WIDE_INT c, lsb, shift_mask;
8696 shift_mask <<= INTVAL (shiftop);
8699 /* Find the least significant one bit. */
8702 /* It must be covered by the shift mask.
8703 This test also rejects c == 0. */
8704 if ((lsb & shift_mask) == 0)
8707 /* Check we have all 1's above the transition, and reject all 1's. */
8708 return c == -lsb && lsb != 1;
8710 else if (GET_CODE (andop) == CONST_DOUBLE
8711 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
8713 HOST_WIDE_INT low, lsb, shift_mask_low;
8715 low = CONST_DOUBLE_LOW (andop);
8717 if (HOST_BITS_PER_WIDE_INT < 64)
8719 HOST_WIDE_INT high, shift_mask_high;
8721 high = CONST_DOUBLE_HIGH (andop);
8725 shift_mask_high = ~0;
8726 if (INTVAL (shiftop) > 32)
8727 shift_mask_high <<= INTVAL (shiftop) - 32;
8731 if ((lsb & shift_mask_high) == 0)
8734 return high == -lsb;
8740 shift_mask_low = ~0;
8741 shift_mask_low <<= INTVAL (shiftop);
8745 if ((lsb & shift_mask_low) == 0)
8748 return low == -lsb && lsb != 1;
8754 /* Return 1 if operands will generate a valid arguments to rlwimi
8755 instruction for insert with right shift in 64-bit mode. The mask may
8756 not start on the first bit or stop on the last bit because wrap-around
8757 effects of instruction do not correspond to semantics of RTL insn. */
8760 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
8762 if (INTVAL (startop) < 64
8763 && INTVAL (startop) > 32
8764 && (INTVAL (sizeop) + INTVAL (startop) < 64)
8765 && (INTVAL (sizeop) + INTVAL (startop) > 33)
8766 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
8767 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
8768 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
8774 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
8775 for lfq and stfq insns iff the registers are hard registers. */
8778 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
8780 /* We might have been passed a SUBREG. */
8781 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
8784 /* We might have been passed non floating point registers. */
8785 if (!FP_REGNO_P (REGNO (reg1))
8786 || !FP_REGNO_P (REGNO (reg2)))
8789 return (REGNO (reg1) == REGNO (reg2) - 1);
8792 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
8793 addr1 and addr2 must be in consecutive memory locations
8794 (addr2 == addr1 + 8). */
8797 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
8803 /* The mems cannot be volatile. */
8804 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
8807 addr1 = XEXP (mem1, 0);
8808 addr2 = XEXP (mem2, 0);
8810 /* Extract an offset (if used) from the first addr. */
8811 if (GET_CODE (addr1) == PLUS)
8813 /* If not a REG, return zero. */
8814 if (GET_CODE (XEXP (addr1, 0)) != REG)
8818 reg1 = REGNO (XEXP (addr1, 0));
8819 /* The offset must be constant! */
8820 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
8822 offset1 = INTVAL (XEXP (addr1, 1));
8825 else if (GET_CODE (addr1) != REG)
8829 reg1 = REGNO (addr1);
8830 /* This was a simple (mem (reg)) expression. Offset is 0. */
8834 /* Make sure the second address is a (mem (plus (reg) (const_int)))
8835 or if it is (mem (reg)) then make sure that offset1 is -8 and the same
8836 register as addr1. */
8837 if (offset1 == -8 && GET_CODE (addr2) == REG && reg1 == REGNO (addr2))
8839 if (GET_CODE (addr2) != PLUS)
8842 if (GET_CODE (XEXP (addr2, 0)) != REG
8843 || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
8846 if (reg1 != REGNO (XEXP (addr2, 0)))
8849 /* The offset for the second addr must be 8 more than the first addr. */
8850 if (INTVAL (XEXP (addr2, 1)) != offset1 + 8)
8853 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
8858 /* Return the register class of a scratch register needed to copy IN into
8859 or out of a register in CLASS in MODE. If it can be done directly,
8860 NO_REGS is returned. */
8863 secondary_reload_class (enum reg_class class,
8864 enum machine_mode mode ATTRIBUTE_UNUSED,
8869 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
8871 && MACHOPIC_INDIRECT
8875 /* We cannot copy a symbolic operand directly into anything
8876 other than BASE_REGS for TARGET_ELF. So indicate that a
8877 register from BASE_REGS is needed as an intermediate
8880 On Darwin, pic addresses require a load from memory, which
8881 needs a base register. */
8882 if (class != BASE_REGS
8883 && (GET_CODE (in) == SYMBOL_REF
8884 || GET_CODE (in) == HIGH
8885 || GET_CODE (in) == LABEL_REF
8886 || GET_CODE (in) == CONST))
8890 if (GET_CODE (in) == REG)
8893 if (regno >= FIRST_PSEUDO_REGISTER)
8895 regno = true_regnum (in);
8896 if (regno >= FIRST_PSEUDO_REGISTER)
8900 else if (GET_CODE (in) == SUBREG)
8902 regno = true_regnum (in);
8903 if (regno >= FIRST_PSEUDO_REGISTER)
8909 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
8911 if (class == GENERAL_REGS || class == BASE_REGS
8912 || (regno >= 0 && INT_REGNO_P (regno)))
8915 /* Constants, memory, and FP registers can go into FP registers. */
8916 if ((regno == -1 || FP_REGNO_P (regno))
8917 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
8920 /* Memory, and AltiVec registers can go into AltiVec registers. */
8921 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
8922 && class == ALTIVEC_REGS)
8925 /* We can copy among the CR registers. */
8926 if ((class == CR_REGS || class == CR0_REGS)
8927 && regno >= 0 && CR_REGNO_P (regno))
8930 /* Otherwise, we need GENERAL_REGS. */
8931 return GENERAL_REGS;
8934 /* Given a comparison operation, return the bit number in CCR to test. We
8935 know this is a valid comparison.
8937 SCC_P is 1 if this is for an scc. That means that %D will have been
8938 used instead of %C, so the bits will be in different places.
8940 Return -1 if OP isn't a valid comparison for some reason. */
8943 ccr_bit (rtx op, int scc_p)
8945 enum rtx_code code = GET_CODE (op);
8946 enum machine_mode cc_mode;
8951 if (!COMPARISON_P (op))
8956 if (GET_CODE (reg) != REG
8957 || ! CR_REGNO_P (REGNO (reg)))
8960 cc_mode = GET_MODE (reg);
8961 cc_regnum = REGNO (reg);
8962 base_bit = 4 * (cc_regnum - CR0_REGNO);
8964 validate_condition_mode (code, cc_mode);
8966 /* When generating a sCOND operation, only positive conditions are
8968 if (scc_p && code != EQ && code != GT && code != LT && code != UNORDERED
8969 && code != GTU && code != LTU)
8975 return scc_p ? base_bit + 3 : base_bit + 2;
8977 return base_bit + 2;
8978 case GT: case GTU: case UNLE:
8979 return base_bit + 1;
8980 case LT: case LTU: case UNGE:
8982 case ORDERED: case UNORDERED:
8983 return base_bit + 3;
8986 /* If scc, we will have done a cror to put the bit in the
8987 unordered position. So test that bit. For integer, this is ! LT
8988 unless this is an scc insn. */
8989 return scc_p ? base_bit + 3 : base_bit;
8992 return scc_p ? base_bit + 3 : base_bit + 1;
8999 /* Return the GOT register. */
9002 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9004 /* The second flow pass currently (June 1999) can't update
9005 regs_ever_live without disturbing other parts of the compiler, so
9006 update it here to make the prolog/epilogue code happy. */
9007 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9008 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9010 current_function_uses_pic_offset_table = 1;
9012 return pic_offset_table_rtx;
9015 /* Function to init struct machine_function.
9016 This will be called, via a pointer variable,
9017 from push_function_context. */
9019 static struct machine_function *
9020 rs6000_init_machine_status (void)
9022 return ggc_alloc_cleared (sizeof (machine_function));
9025 /* These macros test for integers and extract the low-order bits. */
9027 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9028 && GET_MODE (X) == VOIDmode)
9030 #define INT_LOWPART(X) \
9031 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9037 unsigned long val = INT_LOWPART (op);
9039 /* If the high bit is zero, the value is the first 1 bit we find
9041 if ((val & 0x80000000) == 0)
9043 if ((val & 0xffffffff) == 0)
9047 while (((val <<= 1) & 0x80000000) == 0)
9052 /* If the high bit is set and the low bit is not, or the mask is all
9053 1's, the value is zero. */
9054 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9057 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9060 while (((val >>= 1) & 1) != 0)
9070 unsigned long val = INT_LOWPART (op);
9072 /* If the low bit is zero, the value is the first 1 bit we find from
9076 if ((val & 0xffffffff) == 0)
9080 while (((val >>= 1) & 1) == 0)
9086 /* If the low bit is set and the high bit is not, or the mask is all
9087 1's, the value is 31. */
9088 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9091 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9094 while (((val <<= 1) & 0x80000000) != 0)
9100 /* Locate some local-dynamic symbol still in use by this function
9101 so that we can print its name in some tls_ld pattern. */
9104 rs6000_get_some_local_dynamic_name (void)
9108 if (cfun->machine->some_ld_name)
9109 return cfun->machine->some_ld_name;
9111 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9113 && for_each_rtx (&PATTERN (insn),
9114 rs6000_get_some_local_dynamic_name_1, 0))
9115 return cfun->machine->some_ld_name;
9120 /* Helper function for rs6000_get_some_local_dynamic_name. */
9123 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
9127 if (GET_CODE (x) == SYMBOL_REF)
9129 const char *str = XSTR (x, 0);
9130 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
9132 cfun->machine->some_ld_name = str;
9140 /* Write out a function code label. */
9143 rs6000_output_function_entry (FILE *file, const char *fname)
9145 if (fname[0] != '.')
9147 switch (DEFAULT_ABI)
9156 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
9165 RS6000_OUTPUT_BASENAME (file, fname);
9167 assemble_name (file, fname);
9170 /* Print an operand. Recognize special options, documented below. */
9173 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
9174 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
9176 #define SMALL_DATA_RELOC "sda21"
9177 #define SMALL_DATA_REG 0
9181 print_operand (FILE *file, rtx x, int code)
9185 unsigned HOST_WIDE_INT uval;
9190 /* Write out an instruction after the call which may be replaced
9191 with glue code by the loader. This depends on the AIX version. */
9192 asm_fprintf (file, RS6000_CALL_GLUE);
9195 /* %a is output_address. */
9198 /* If X is a constant integer whose low-order 5 bits are zero,
9199 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
9200 in the AIX assembler where "sri" with a zero shift count
9201 writes a trash instruction. */
9202 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
9209 /* If constant, low-order 16 bits of constant, unsigned.
9210 Otherwise, write normally. */
9212 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
9214 print_operand (file, x, 0);
9218 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
9219 for 64-bit mask direction. */
9220 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
9223 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
9227 /* X is a CR register. Print the number of the GT bit of the CR. */
9228 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9229 output_operand_lossage ("invalid %%E value");
9231 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
9235 /* Like 'J' but get to the EQ bit. */
9236 if (GET_CODE (x) != REG)
9239 /* Bit 1 is EQ bit. */
9240 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
9242 fprintf (file, "%d", i);
9246 /* X is a CR register. Print the number of the EQ bit of the CR */
9247 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9248 output_operand_lossage ("invalid %%E value");
9250 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
9254 /* X is a CR register. Print the shift count needed to move it
9255 to the high-order four bits. */
9256 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9257 output_operand_lossage ("invalid %%f value");
9259 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
9263 /* Similar, but print the count for the rotate in the opposite
9265 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9266 output_operand_lossage ("invalid %%F value");
9268 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
9272 /* X is a constant integer. If it is negative, print "m",
9273 otherwise print "z". This is to make an aze or ame insn. */
9274 if (GET_CODE (x) != CONST_INT)
9275 output_operand_lossage ("invalid %%G value");
9276 else if (INTVAL (x) >= 0)
9283 /* If constant, output low-order five bits. Otherwise, write
9286 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
9288 print_operand (file, x, 0);
9292 /* If constant, output low-order six bits. Otherwise, write
9295 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
9297 print_operand (file, x, 0);
9301 /* Print `i' if this is a constant, else nothing. */
9307 /* Write the bit number in CCR for jump. */
9310 output_operand_lossage ("invalid %%j code");
9312 fprintf (file, "%d", i);
9316 /* Similar, but add one for shift count in rlinm for scc and pass
9317 scc flag to `ccr_bit'. */
9320 output_operand_lossage ("invalid %%J code");
9322 /* If we want bit 31, write a shift count of zero, not 32. */
9323 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9327 /* X must be a constant. Write the 1's complement of the
9330 output_operand_lossage ("invalid %%k value");
9332 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
9336 /* X must be a symbolic constant on ELF. Write an
9337 expression suitable for an 'addi' that adds in the low 16
9339 if (GET_CODE (x) != CONST)
9341 print_operand_address (file, x);
9346 if (GET_CODE (XEXP (x, 0)) != PLUS
9347 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
9348 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
9349 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
9350 output_operand_lossage ("invalid %%K value");
9351 print_operand_address (file, XEXP (XEXP (x, 0), 0));
9353 /* For GNU as, there must be a non-alphanumeric character
9354 between 'l' and the number. The '-' is added by
9355 print_operand() already. */
9356 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
9358 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
9362 /* %l is output_asm_label. */
9365 /* Write second word of DImode or DFmode reference. Works on register
9366 or non-indexed memory only. */
9367 if (GET_CODE (x) == REG)
9368 fputs (reg_names[REGNO (x) + 1], file);
9369 else if (GET_CODE (x) == MEM)
9371 /* Handle possible auto-increment. Since it is pre-increment and
9372 we have already done it, we can just use an offset of word. */
9373 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9374 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9375 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
9378 output_address (XEXP (adjust_address_nv (x, SImode,
9382 if (small_data_operand (x, GET_MODE (x)))
9383 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9384 reg_names[SMALL_DATA_REG]);
9389 /* MB value for a mask operand. */
9390 if (! mask_operand (x, SImode))
9391 output_operand_lossage ("invalid %%m value");
9393 fprintf (file, "%d", extract_MB (x));
9397 /* ME value for a mask operand. */
9398 if (! mask_operand (x, SImode))
9399 output_operand_lossage ("invalid %%M value");
9401 fprintf (file, "%d", extract_ME (x));
9404 /* %n outputs the negative of its operand. */
9407 /* Write the number of elements in the vector times 4. */
9408 if (GET_CODE (x) != PARALLEL)
9409 output_operand_lossage ("invalid %%N value");
9411 fprintf (file, "%d", XVECLEN (x, 0) * 4);
9415 /* Similar, but subtract 1 first. */
9416 if (GET_CODE (x) != PARALLEL)
9417 output_operand_lossage ("invalid %%O value");
9419 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
9423 /* X is a CONST_INT that is a power of two. Output the logarithm. */
9425 || INT_LOWPART (x) < 0
9426 || (i = exact_log2 (INT_LOWPART (x))) < 0)
9427 output_operand_lossage ("invalid %%p value");
9429 fprintf (file, "%d", i);
9433 /* The operand must be an indirect memory reference. The result
9434 is the register name. */
9435 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
9436 || REGNO (XEXP (x, 0)) >= 32)
9437 output_operand_lossage ("invalid %%P value");
9439 fputs (reg_names[REGNO (XEXP (x, 0))], file);
9443 /* This outputs the logical code corresponding to a boolean
9444 expression. The expression may have one or both operands
9445 negated (if one, only the first one). For condition register
9446 logical operations, it will also treat the negated
9447 CR codes as NOTs, but not handle NOTs of them. */
9449 const char *const *t = 0;
9451 enum rtx_code code = GET_CODE (x);
9452 static const char * const tbl[3][3] = {
9453 { "and", "andc", "nor" },
9454 { "or", "orc", "nand" },
9455 { "xor", "eqv", "xor" } };
9459 else if (code == IOR)
9461 else if (code == XOR)
9464 output_operand_lossage ("invalid %%q value");
9466 if (GET_CODE (XEXP (x, 0)) != NOT)
9470 if (GET_CODE (XEXP (x, 1)) == NOT)
9488 /* X is a CR register. Print the mask for `mtcrf'. */
9489 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
9490 output_operand_lossage ("invalid %%R value");
9492 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
9496 /* Low 5 bits of 32 - value */
9498 output_operand_lossage ("invalid %%s value");
9500 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
9504 /* PowerPC64 mask position. All 0's is excluded.
9505 CONST_INT 32-bit mask is considered sign-extended so any
9506 transition must occur within the CONST_INT, not on the boundary. */
9507 if (! mask64_operand (x, DImode))
9508 output_operand_lossage ("invalid %%S value");
9510 uval = INT_LOWPART (x);
9512 if (uval & 1) /* Clear Left */
9514 #if HOST_BITS_PER_WIDE_INT > 64
9515 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9519 else /* Clear Right */
9522 #if HOST_BITS_PER_WIDE_INT > 64
9523 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
9531 fprintf (file, "%d", i);
9535 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
9536 if (GET_CODE (x) != REG || GET_MODE (x) != CCmode)
9539 /* Bit 3 is OV bit. */
9540 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
9542 /* If we want bit 31, write a shift count of zero, not 32. */
9543 fprintf (file, "%d", i == 31 ? 0 : i + 1);
9547 /* Print the symbolic name of a branch target register. */
9548 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
9549 && REGNO (x) != COUNT_REGISTER_REGNUM))
9550 output_operand_lossage ("invalid %%T value");
9551 else if (REGNO (x) == LINK_REGISTER_REGNUM)
9552 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
9554 fputs ("ctr", file);
9558 /* High-order 16 bits of constant for use in unsigned operand. */
9560 output_operand_lossage ("invalid %%u value");
9562 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9563 (INT_LOWPART (x) >> 16) & 0xffff);
9567 /* High-order 16 bits of constant for use in signed operand. */
9569 output_operand_lossage ("invalid %%v value");
9571 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
9572 (INT_LOWPART (x) >> 16) & 0xffff);
9576 /* Print `u' if this has an auto-increment or auto-decrement. */
9577 if (GET_CODE (x) == MEM
9578 && (GET_CODE (XEXP (x, 0)) == PRE_INC
9579 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
9584 /* Print the trap code for this operand. */
9585 switch (GET_CODE (x))
9588 fputs ("eq", file); /* 4 */
9591 fputs ("ne", file); /* 24 */
9594 fputs ("lt", file); /* 16 */
9597 fputs ("le", file); /* 20 */
9600 fputs ("gt", file); /* 8 */
9603 fputs ("ge", file); /* 12 */
9606 fputs ("llt", file); /* 2 */
9609 fputs ("lle", file); /* 6 */
9612 fputs ("lgt", file); /* 1 */
9615 fputs ("lge", file); /* 5 */
9623 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
9626 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
9627 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
9629 print_operand (file, x, 0);
9633 /* MB value for a PowerPC64 rldic operand. */
9634 val = (GET_CODE (x) == CONST_INT
9635 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
9640 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
9641 if ((val <<= 1) < 0)
9644 #if HOST_BITS_PER_WIDE_INT == 32
9645 if (GET_CODE (x) == CONST_INT && i >= 0)
9646 i += 32; /* zero-extend high-part was all 0's */
9647 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
9649 val = CONST_DOUBLE_LOW (x);
9656 for ( ; i < 64; i++)
9657 if ((val <<= 1) < 0)
9662 fprintf (file, "%d", i + 1);
9666 if (GET_CODE (x) == MEM
9667 && legitimate_indexed_address_p (XEXP (x, 0), 0))
9672 /* Like 'L', for third word of TImode */
9673 if (GET_CODE (x) == REG)
9674 fputs (reg_names[REGNO (x) + 2], file);
9675 else if (GET_CODE (x) == MEM)
9677 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9678 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9679 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
9681 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
9682 if (small_data_operand (x, GET_MODE (x)))
9683 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9684 reg_names[SMALL_DATA_REG]);
9689 /* X is a SYMBOL_REF. Write out the name preceded by a
9690 period and without any trailing data in brackets. Used for function
9691 names. If we are configured for System V (or the embedded ABI) on
9692 the PowerPC, do not emit the period, since those systems do not use
9693 TOCs and the like. */
9694 if (GET_CODE (x) != SYMBOL_REF)
9697 /* Mark the decl as referenced so that cgraph will output the
9699 if (SYMBOL_REF_DECL (x))
9700 mark_decl_referenced (SYMBOL_REF_DECL (x));
9702 /* For macho, check to see if we need a stub. */
9705 const char *name = XSTR (x, 0);
9707 if (MACHOPIC_INDIRECT
9708 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
9709 name = machopic_indirection_name (x, /*stub_p=*/true);
9711 assemble_name (file, name);
9713 else if (!DOT_SYMBOLS)
9714 assemble_name (file, XSTR (x, 0));
9716 rs6000_output_function_entry (file, XSTR (x, 0));
9720 /* Like 'L', for last word of TImode. */
9721 if (GET_CODE (x) == REG)
9722 fputs (reg_names[REGNO (x) + 3], file);
9723 else if (GET_CODE (x) == MEM)
9725 if (GET_CODE (XEXP (x, 0)) == PRE_INC
9726 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
9727 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
9729 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
9730 if (small_data_operand (x, GET_MODE (x)))
9731 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9732 reg_names[SMALL_DATA_REG]);
9736 /* Print AltiVec or SPE memory operand. */
9741 if (GET_CODE (x) != MEM)
9749 if (GET_CODE (tmp) == REG)
9751 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
9754 /* Handle [reg+UIMM]. */
9755 else if (GET_CODE (tmp) == PLUS &&
9756 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
9760 if (GET_CODE (XEXP (tmp, 0)) != REG)
9763 x = INTVAL (XEXP (tmp, 1));
9764 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
9768 /* Fall through. Must be [reg+reg]. */
9771 && GET_CODE (tmp) == AND
9772 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
9773 && INTVAL (XEXP (tmp, 1)) == -16)
9774 tmp = XEXP (tmp, 0);
9775 if (GET_CODE (tmp) == REG)
9776 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
9777 else if (GET_CODE (tmp) == PLUS && GET_CODE (XEXP (tmp, 1)) == REG)
9779 if (REGNO (XEXP (tmp, 0)) == 0)
9780 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
9781 reg_names[ REGNO (XEXP (tmp, 0)) ]);
9783 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
9784 reg_names[ REGNO (XEXP (tmp, 1)) ]);
9792 if (GET_CODE (x) == REG)
9793 fprintf (file, "%s", reg_names[REGNO (x)]);
9794 else if (GET_CODE (x) == MEM)
9796 /* We need to handle PRE_INC and PRE_DEC here, since we need to
9797 know the width from the mode. */
9798 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
9799 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
9800 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9801 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
9802 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
9803 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
9805 output_address (XEXP (x, 0));
9808 output_addr_const (file, x);
9812 assemble_name (file, rs6000_get_some_local_dynamic_name ());
9816 output_operand_lossage ("invalid %%xn code");
9820 /* Print the address of an operand. */
9823 print_operand_address (FILE *file, rtx x)
9825 if (GET_CODE (x) == REG)
9826 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
9827 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
9828 || GET_CODE (x) == LABEL_REF)
9830 output_addr_const (file, x);
9831 if (small_data_operand (x, GET_MODE (x)))
9832 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
9833 reg_names[SMALL_DATA_REG]);
9834 else if (TARGET_TOC)
9837 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
9839 if (REGNO (XEXP (x, 0)) == 0)
9840 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
9841 reg_names[ REGNO (XEXP (x, 0)) ]);
9843 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
9844 reg_names[ REGNO (XEXP (x, 1)) ]);
9846 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
9847 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
9848 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
9850 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9851 && CONSTANT_P (XEXP (x, 1)))
9853 output_addr_const (file, XEXP (x, 1));
9854 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9858 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
9859 && CONSTANT_P (XEXP (x, 1)))
9861 fprintf (file, "lo16(");
9862 output_addr_const (file, XEXP (x, 1));
9863 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
9866 else if (legitimate_constant_pool_address_p (x))
9868 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
9870 rtx contains_minus = XEXP (x, 1);
9874 /* Find the (minus (sym) (toc)) buried in X, and temporarily
9875 turn it into (sym) for output_addr_const. */
9876 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
9877 contains_minus = XEXP (contains_minus, 0);
9879 minus = XEXP (contains_minus, 0);
9880 symref = XEXP (minus, 0);
9881 XEXP (contains_minus, 0) = symref;
9886 name = XSTR (symref, 0);
9887 newname = alloca (strlen (name) + sizeof ("@toc"));
9888 strcpy (newname, name);
9889 strcat (newname, "@toc");
9890 XSTR (symref, 0) = newname;
9892 output_addr_const (file, XEXP (x, 1));
9894 XSTR (symref, 0) = name;
9895 XEXP (contains_minus, 0) = minus;
9898 output_addr_const (file, XEXP (x, 1));
9900 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
9906 /* Target hook for assembling integer objects. The PowerPC version has
9907 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
9908 is defined. It also needs to handle DI-mode objects on 64-bit
9912 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
9914 #ifdef RELOCATABLE_NEEDS_FIXUP
9915 /* Special handling for SI values. */
9916 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
9918 extern int in_toc_section (void);
9919 static int recurse = 0;
9921 /* For -mrelocatable, we mark all addresses that need to be fixed up
9922 in the .fixup section. */
9923 if (TARGET_RELOCATABLE
9924 && !in_toc_section ()
9925 && !in_text_section ()
9926 && !in_unlikely_text_section ()
9928 && GET_CODE (x) != CONST_INT
9929 && GET_CODE (x) != CONST_DOUBLE
9935 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
9937 ASM_OUTPUT_LABEL (asm_out_file, buf);
9938 fprintf (asm_out_file, "\t.long\t(");
9939 output_addr_const (asm_out_file, x);
9940 fprintf (asm_out_file, ")@fixup\n");
9941 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
9942 ASM_OUTPUT_ALIGN (asm_out_file, 2);
9943 fprintf (asm_out_file, "\t.long\t");
9944 assemble_name (asm_out_file, buf);
9945 fprintf (asm_out_file, "\n\t.previous\n");
9949 /* Remove initial .'s to turn a -mcall-aixdesc function
9950 address into the address of the descriptor, not the function
9952 else if (GET_CODE (x) == SYMBOL_REF
9953 && XSTR (x, 0)[0] == '.'
9954 && DEFAULT_ABI == ABI_AIX)
9956 const char *name = XSTR (x, 0);
9957 while (*name == '.')
9960 fprintf (asm_out_file, "\t.long\t%s\n", name);
9964 #endif /* RELOCATABLE_NEEDS_FIXUP */
9965 return default_assemble_integer (x, size, aligned_p);
9968 #ifdef HAVE_GAS_HIDDEN
9969 /* Emit an assembler directive to set symbol visibility for DECL to
9973 rs6000_assemble_visibility (tree decl, int vis)
9975 /* Functions need to have their entry point symbol visibility set as
9976 well as their descriptor symbol visibility. */
9977 if (DEFAULT_ABI == ABI_AIX
9979 && TREE_CODE (decl) == FUNCTION_DECL)
9981 static const char * const visibility_types[] = {
9982 NULL, "internal", "hidden", "protected"
9985 const char *name, *type;
9987 name = ((* targetm.strip_name_encoding)
9988 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
9989 type = visibility_types[vis];
9991 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
9992 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
9995 default_assemble_visibility (decl, vis);
10000 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10002 /* Reversal of FP compares takes care -- an ordered compare
10003 becomes an unordered compare and vice versa. */
10004 if (mode == CCFPmode
10005 && (!flag_finite_math_only
10006 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10007 || code == UNEQ || code == LTGT))
10008 return reverse_condition_maybe_unordered (code);
10010 return reverse_condition (code);
10013 /* Generate a compare for CODE. Return a brand-new rtx that
10014 represents the result of the compare. */
10017 rs6000_generate_compare (enum rtx_code code)
10019 enum machine_mode comp_mode;
10020 rtx compare_result;
10022 if (rs6000_compare_fp_p)
10023 comp_mode = CCFPmode;
10024 else if (code == GTU || code == LTU
10025 || code == GEU || code == LEU)
10026 comp_mode = CCUNSmode;
10027 else if ((code == EQ || code == NE)
10028 && GET_CODE (rs6000_compare_op0) == SUBREG
10029 && GET_CODE (rs6000_compare_op1) == SUBREG
10030 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10031 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10032 /* These are unsigned values, perhaps there will be a later
10033 ordering compare that can be shared with this one.
10034 Unfortunately we cannot detect the signedness of the operands
10035 for non-subregs. */
10036 comp_mode = CCUNSmode;
10038 comp_mode = CCmode;
10040 /* First, the compare. */
10041 compare_result = gen_reg_rtx (comp_mode);
10043 /* SPE FP compare instructions on the GPRs. Yuck! */
10044 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10045 && rs6000_compare_fp_p)
10047 rtx cmp, or_result, compare_result2;
10048 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10050 if (op_mode == VOIDmode)
10051 op_mode = GET_MODE (rs6000_compare_op1);
10053 /* Note: The E500 comparison instructions set the GT bit (x +
10054 1), on success. This explains the mess. */
10058 case EQ: case UNEQ: case NE: case LTGT:
10059 if (op_mode == SFmode)
10060 cmp = flag_unsafe_math_optimizations
10061 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10062 rs6000_compare_op1)
10063 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10064 rs6000_compare_op1);
10065 else if (op_mode == DFmode)
10066 cmp = flag_unsafe_math_optimizations
10067 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10068 rs6000_compare_op1)
10069 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10070 rs6000_compare_op1);
10073 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10074 if (op_mode == SFmode)
10075 cmp = flag_unsafe_math_optimizations
10076 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10077 rs6000_compare_op1)
10078 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10079 rs6000_compare_op1);
10080 else if (op_mode == DFmode)
10081 cmp = flag_unsafe_math_optimizations
10082 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10083 rs6000_compare_op1)
10084 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10085 rs6000_compare_op1);
10088 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10089 if (op_mode == SFmode)
10090 cmp = flag_unsafe_math_optimizations
10091 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10092 rs6000_compare_op1)
10093 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10094 rs6000_compare_op1);
10095 else if (op_mode == DFmode)
10096 cmp = flag_unsafe_math_optimizations
10097 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10098 rs6000_compare_op1)
10099 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10100 rs6000_compare_op1);
10107 /* Synthesize LE and GE from LT/GT || EQ. */
10108 if (code == LE || code == GE || code == LEU || code == GEU)
10114 case LE: code = LT; break;
10115 case GE: code = GT; break;
10116 case LEU: code = LT; break;
10117 case GEU: code = GT; break;
10121 compare_result2 = gen_reg_rtx (CCFPmode);
10124 if (op_mode == SFmode)
10125 cmp = flag_unsafe_math_optimizations
10126 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
10127 rs6000_compare_op1)
10128 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
10129 rs6000_compare_op1);
10130 else if (op_mode == DFmode)
10131 cmp = flag_unsafe_math_optimizations
10132 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
10133 rs6000_compare_op1)
10134 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
10135 rs6000_compare_op1);
10139 /* OR them together. */
10140 or_result = gen_reg_rtx (CCFPmode);
10141 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
10143 compare_result = or_result;
10148 if (code == NE || code == LTGT)
10158 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
10159 CLOBBERs to match cmptf_internal2 pattern. */
10160 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
10161 && GET_MODE (rs6000_compare_op0) == TFmode
10162 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
10163 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
10164 emit_insn (gen_rtx_PARALLEL (VOIDmode,
10166 gen_rtx_SET (VOIDmode,
10168 gen_rtx_COMPARE (comp_mode,
10169 rs6000_compare_op0,
10170 rs6000_compare_op1)),
10171 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10172 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10173 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10174 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10175 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10176 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10177 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
10178 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
10180 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
10181 gen_rtx_COMPARE (comp_mode,
10182 rs6000_compare_op0,
10183 rs6000_compare_op1)));
10186 /* Some kinds of FP comparisons need an OR operation;
10187 under flag_finite_math_only we don't bother. */
10188 if (rs6000_compare_fp_p
10189 && !flag_finite_math_only
10190 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
10191 && (code == LE || code == GE
10192 || code == UNEQ || code == LTGT
10193 || code == UNGT || code == UNLT))
10195 enum rtx_code or1, or2;
10196 rtx or1_rtx, or2_rtx, compare2_rtx;
10197 rtx or_result = gen_reg_rtx (CCEQmode);
10201 case LE: or1 = LT; or2 = EQ; break;
10202 case GE: or1 = GT; or2 = EQ; break;
10203 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
10204 case LTGT: or1 = LT; or2 = GT; break;
10205 case UNGT: or1 = UNORDERED; or2 = GT; break;
10206 case UNLT: or1 = UNORDERED; or2 = LT; break;
10209 validate_condition_mode (or1, comp_mode);
10210 validate_condition_mode (or2, comp_mode);
10211 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
10212 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
10213 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
10214 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
10216 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
10218 compare_result = or_result;
10222 validate_condition_mode (code, GET_MODE (compare_result));
10224 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
10228 /* Emit the RTL for an sCOND pattern. */
10231 rs6000_emit_sCOND (enum rtx_code code, rtx result)
10234 enum machine_mode op_mode;
10235 enum rtx_code cond_code;
10237 condition_rtx = rs6000_generate_compare (code);
10238 cond_code = GET_CODE (condition_rtx);
10240 if (TARGET_E500 && rs6000_compare_fp_p
10241 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10245 PUT_MODE (condition_rtx, SImode);
10246 t = XEXP (condition_rtx, 0);
10248 if (cond_code != NE && cond_code != EQ)
10251 if (cond_code == NE)
10252 emit_insn (gen_e500_flip_gt_bit (t, t));
10254 emit_insn (gen_move_from_CR_gt_bit (result, t));
10258 if (cond_code == NE
10259 || cond_code == GE || cond_code == LE
10260 || cond_code == GEU || cond_code == LEU
10261 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
10263 rtx not_result = gen_reg_rtx (CCEQmode);
10264 rtx not_op, rev_cond_rtx;
10265 enum machine_mode cc_mode;
10267 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
10269 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
10270 SImode, XEXP (condition_rtx, 0), const0_rtx);
10271 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
10272 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
10273 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
10276 op_mode = GET_MODE (rs6000_compare_op0);
10277 if (op_mode == VOIDmode)
10278 op_mode = GET_MODE (rs6000_compare_op1);
10280 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
10282 PUT_MODE (condition_rtx, DImode);
10283 convert_move (result, condition_rtx, 0);
10287 PUT_MODE (condition_rtx, SImode);
10288 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
10292 /* Emit a branch of kind CODE to location LOC. */
10295 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
10297 rtx condition_rtx, loc_ref;
10299 condition_rtx = rs6000_generate_compare (code);
10300 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
10301 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
10302 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
10303 loc_ref, pc_rtx)));
10306 /* Return the string to output a conditional branch to LABEL, which is
10307 the operand number of the label, or -1 if the branch is really a
10308 conditional return.
10310 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
10311 condition code register and its mode specifies what kind of
10312 comparison we made.
10314 REVERSED is nonzero if we should reverse the sense of the comparison.
10316 INSN is the insn. */
10319 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
10321 static char string[64];
10322 enum rtx_code code = GET_CODE (op);
10323 rtx cc_reg = XEXP (op, 0);
10324 enum machine_mode mode = GET_MODE (cc_reg);
10325 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
10326 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
10327 int really_reversed = reversed ^ need_longbranch;
10333 validate_condition_mode (code, mode);
10335 /* Work out which way this really branches. We could use
10336 reverse_condition_maybe_unordered here always but this
10337 makes the resulting assembler clearer. */
10338 if (really_reversed)
10340 /* Reversal of FP compares takes care -- an ordered compare
10341 becomes an unordered compare and vice versa. */
10342 if (mode == CCFPmode)
10343 code = reverse_condition_maybe_unordered (code);
10345 code = reverse_condition (code);
10348 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
10350 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
10353 /* Opposite of GT. */
10355 else if (code == NE)
10363 /* Not all of these are actually distinct opcodes, but
10364 we distinguish them for clarity of the resulting assembler. */
10365 case NE: case LTGT:
10366 ccode = "ne"; break;
10367 case EQ: case UNEQ:
10368 ccode = "eq"; break;
10370 ccode = "ge"; break;
10371 case GT: case GTU: case UNGT:
10372 ccode = "gt"; break;
10374 ccode = "le"; break;
10375 case LT: case LTU: case UNLT:
10376 ccode = "lt"; break;
10377 case UNORDERED: ccode = "un"; break;
10378 case ORDERED: ccode = "nu"; break;
10379 case UNGE: ccode = "nl"; break;
10380 case UNLE: ccode = "ng"; break;
10385 /* Maybe we have a guess as to how likely the branch is.
10386 The old mnemonics don't have a way to specify this information. */
10388 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
10389 if (note != NULL_RTX)
10391 /* PROB is the difference from 50%. */
10392 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
10394 /* Only hint for highly probable/improbable branches on newer
10395 cpus as static prediction overrides processor dynamic
10396 prediction. For older cpus we may as well always hint, but
10397 assume not taken for branches that are very close to 50% as a
10398 mispredicted taken branch is more expensive than a
10399 mispredicted not-taken branch. */
10400 if (rs6000_always_hint
10401 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
10403 if (abs (prob) > REG_BR_PROB_BASE / 20
10404 && ((prob > 0) ^ need_longbranch))
10412 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
10414 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
10416 /* We need to escape any '%' characters in the reg_names string.
10417 Assume they'd only be the first character.... */
10418 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
10420 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
10424 /* If the branch distance was too far, we may have to use an
10425 unconditional branch to go the distance. */
10426 if (need_longbranch)
10427 s += sprintf (s, ",$+8\n\tb %s", label);
10429 s += sprintf (s, ",%s", label);
10435 /* Return the string to flip the GT bit on a CR. */
10437 output_e500_flip_gt_bit (rtx dst, rtx src)
10439 static char string[64];
10442 if (GET_CODE (dst) != REG || ! CR_REGNO_P (REGNO (dst))
10443 || GET_CODE (src) != REG || ! CR_REGNO_P (REGNO (src)))
10447 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
10448 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
10450 sprintf (string, "crnot %d,%d", a, b);
10454 /* Return insn index for the vector compare instruction for given CODE,
10455 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
10459 get_vec_cmp_insn (enum rtx_code code,
10460 enum machine_mode dest_mode,
10461 enum machine_mode op_mode)
10463 if (!TARGET_ALTIVEC)
10464 return INSN_NOT_AVAILABLE;
10469 if (dest_mode == V16QImode && op_mode == V16QImode)
10470 return UNSPEC_VCMPEQUB;
10471 if (dest_mode == V8HImode && op_mode == V8HImode)
10472 return UNSPEC_VCMPEQUH;
10473 if (dest_mode == V4SImode && op_mode == V4SImode)
10474 return UNSPEC_VCMPEQUW;
10475 if (dest_mode == V4SImode && op_mode == V4SFmode)
10476 return UNSPEC_VCMPEQFP;
10479 if (dest_mode == V4SImode && op_mode == V4SFmode)
10480 return UNSPEC_VCMPGEFP;
10482 if (dest_mode == V16QImode && op_mode == V16QImode)
10483 return UNSPEC_VCMPGTSB;
10484 if (dest_mode == V8HImode && op_mode == V8HImode)
10485 return UNSPEC_VCMPGTSH;
10486 if (dest_mode == V4SImode && op_mode == V4SImode)
10487 return UNSPEC_VCMPGTSW;
10488 if (dest_mode == V4SImode && op_mode == V4SFmode)
10489 return UNSPEC_VCMPGTFP;
10492 if (dest_mode == V16QImode && op_mode == V16QImode)
10493 return UNSPEC_VCMPGTUB;
10494 if (dest_mode == V8HImode && op_mode == V8HImode)
10495 return UNSPEC_VCMPGTUH;
10496 if (dest_mode == V4SImode && op_mode == V4SImode)
10497 return UNSPEC_VCMPGTUW;
10502 return INSN_NOT_AVAILABLE;
10505 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
10506 DMODE is expected destination mode. This is a recursive function. */
10509 rs6000_emit_vector_compare (enum rtx_code rcode,
10511 enum machine_mode dmode)
10515 enum machine_mode dest_mode;
10516 enum machine_mode op_mode = GET_MODE (op1);
10518 #ifdef ENABLE_CHECKING
10519 if (!TARGET_ALTIVEC)
10522 if (GET_MODE (op0) != GET_MODE (op1))
10526 /* Floating point vector compare instructions uses destination V4SImode.
10527 Move destination to appropriate mode later. */
10528 if (dmode == V4SFmode)
10529 dest_mode = V4SImode;
10533 mask = gen_reg_rtx (dest_mode);
10534 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10536 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10538 bool swap_operands = false;
10539 bool try_again = false;
10544 swap_operands = true;
10549 swap_operands = true;
10553 /* Treat A != B as ~(A==B). */
10555 enum insn_code nor_code;
10556 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10559 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
10560 if (nor_code == CODE_FOR_nothing)
10562 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
10564 if (dmode != dest_mode)
10566 rtx temp = gen_reg_rtx (dest_mode);
10567 convert_move (temp, mask, 0);
10577 /* Try GT/GTU/LT/LTU OR EQ */
10580 enum insn_code ior_code;
10581 enum rtx_code new_code;
10585 else if (rcode == GEU)
10587 else if (rcode == LE)
10589 else if (rcode == LEU)
10594 c_rtx = rs6000_emit_vector_compare (new_code,
10595 op0, op1, dest_mode);
10596 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
10599 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
10600 if (ior_code == CODE_FOR_nothing)
10602 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
10603 if (dmode != dest_mode)
10605 rtx temp = gen_reg_rtx (dest_mode);
10606 convert_move (temp, mask, 0);
10618 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
10619 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
10620 /* You only get two chances. */
10633 emit_insn (gen_rtx_fmt_ee (SET,
10636 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10637 gen_rtvec (2, op0, op1),
10639 if (dmode != dest_mode)
10641 rtx temp = gen_reg_rtx (dest_mode);
10642 convert_move (temp, mask, 0);
10648 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
10649 valid insn doesn exist for given mode. */
10652 get_vsel_insn (enum machine_mode mode)
10657 return UNSPEC_VSEL4SI;
10660 return UNSPEC_VSEL4SF;
10663 return UNSPEC_VSEL8HI;
10666 return UNSPEC_VSEL16QI;
10669 return INSN_NOT_AVAILABLE;
10672 return INSN_NOT_AVAILABLE;
10675 /* Emit vector select insn where DEST is destination using
10676 operands OP1, OP2 and MASK. */
10679 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
10682 enum machine_mode dest_mode = GET_MODE (dest);
10683 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
10685 temp = gen_reg_rtx (dest_mode);
10687 t = gen_rtx_fmt_ee (SET, VOIDmode, temp,
10688 gen_rtx_fmt_Ei (UNSPEC, dest_mode,
10689 gen_rtvec (3, op1, op2, mask),
10692 emit_move_insn (dest, temp);
10696 /* Emit vector conditional expression.
10697 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
10698 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
10701 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
10702 rtx cond, rtx cc_op0, rtx cc_op1)
10704 enum machine_mode dest_mode = GET_MODE (dest);
10705 enum rtx_code rcode = GET_CODE (cond);
10708 if (!TARGET_ALTIVEC)
10711 /* Get the vector mask for the given relational operations. */
10712 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
10714 rs6000_emit_vector_select (dest, op1, op2, mask);
10719 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
10720 operands of the last comparison is nonzero/true, FALSE_COND if it
10721 is zero/false. Return 0 if the hardware has no such operation. */
10724 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10726 enum rtx_code code = GET_CODE (op);
10727 rtx op0 = rs6000_compare_op0;
10728 rtx op1 = rs6000_compare_op1;
10729 REAL_VALUE_TYPE c1;
10730 enum machine_mode compare_mode = GET_MODE (op0);
10731 enum machine_mode result_mode = GET_MODE (dest);
10733 bool is_against_zero;
10735 /* These modes should always match. */
10736 if (GET_MODE (op1) != compare_mode
10737 /* In the isel case however, we can use a compare immediate, so
10738 op1 may be a small constant. */
10739 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
10741 if (GET_MODE (true_cond) != result_mode)
10743 if (GET_MODE (false_cond) != result_mode)
10746 /* First, work out if the hardware can do this at all, or
10747 if it's too slow.... */
10748 if (! rs6000_compare_fp_p)
10751 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
10754 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
10755 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
10758 is_against_zero = op1 == CONST0_RTX (compare_mode);
10760 /* A floating-point subtract might overflow, underflow, or produce
10761 an inexact result, thus changing the floating-point flags, so it
10762 can't be generated if we care about that. It's safe if one side
10763 of the construct is zero, since then no subtract will be
10765 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
10766 && flag_trapping_math && ! is_against_zero)
10769 /* Eliminate half of the comparisons by switching operands, this
10770 makes the remaining code simpler. */
10771 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
10772 || code == LTGT || code == LT || code == UNLE)
10774 code = reverse_condition_maybe_unordered (code);
10776 true_cond = false_cond;
10780 /* UNEQ and LTGT take four instructions for a comparison with zero,
10781 it'll probably be faster to use a branch here too. */
10782 if (code == UNEQ && HONOR_NANS (compare_mode))
10785 if (GET_CODE (op1) == CONST_DOUBLE)
10786 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
10788 /* We're going to try to implement comparisons by performing
10789 a subtract, then comparing against zero. Unfortunately,
10790 Inf - Inf is NaN which is not zero, and so if we don't
10791 know that the operand is finite and the comparison
10792 would treat EQ different to UNORDERED, we can't do it. */
10793 if (HONOR_INFINITIES (compare_mode)
10794 && code != GT && code != UNGE
10795 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
10796 /* Constructs of the form (a OP b ? a : b) are safe. */
10797 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
10798 || (! rtx_equal_p (op0, true_cond)
10799 && ! rtx_equal_p (op1, true_cond))))
10802 /* At this point we know we can use fsel. */
10804 /* Reduce the comparison to a comparison against zero. */
10805 if (! is_against_zero)
10807 temp = gen_reg_rtx (compare_mode);
10808 emit_insn (gen_rtx_SET (VOIDmode, temp,
10809 gen_rtx_MINUS (compare_mode, op0, op1)));
10811 op1 = CONST0_RTX (compare_mode);
10814 /* If we don't care about NaNs we can reduce some of the comparisons
10815 down to faster ones. */
10816 if (! HONOR_NANS (compare_mode))
10822 true_cond = false_cond;
10835 /* Now, reduce everything down to a GE. */
10842 temp = gen_reg_rtx (compare_mode);
10843 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10848 temp = gen_reg_rtx (compare_mode);
10849 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
10854 temp = gen_reg_rtx (compare_mode);
10855 emit_insn (gen_rtx_SET (VOIDmode, temp,
10856 gen_rtx_NEG (compare_mode,
10857 gen_rtx_ABS (compare_mode, op0))));
10862 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
10863 temp = gen_reg_rtx (result_mode);
10864 emit_insn (gen_rtx_SET (VOIDmode, temp,
10865 gen_rtx_IF_THEN_ELSE (result_mode,
10866 gen_rtx_GE (VOIDmode,
10868 true_cond, false_cond)));
10869 false_cond = true_cond;
10872 temp = gen_reg_rtx (compare_mode);
10873 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10878 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
10879 temp = gen_reg_rtx (result_mode);
10880 emit_insn (gen_rtx_SET (VOIDmode, temp,
10881 gen_rtx_IF_THEN_ELSE (result_mode,
10882 gen_rtx_GE (VOIDmode,
10884 true_cond, false_cond)));
10885 true_cond = false_cond;
10888 temp = gen_reg_rtx (compare_mode);
10889 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
10897 emit_insn (gen_rtx_SET (VOIDmode, dest,
10898 gen_rtx_IF_THEN_ELSE (result_mode,
10899 gen_rtx_GE (VOIDmode,
10901 true_cond, false_cond)));
10905 /* Same as above, but for ints (isel). */
10908 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
10910 rtx condition_rtx, cr;
10912 /* All isel implementations thus far are 32-bits. */
10913 if (GET_MODE (rs6000_compare_op0) != SImode)
10916 /* We still have to do the compare, because isel doesn't do a
10917 compare, it just looks at the CRx bits set by a previous compare
10919 condition_rtx = rs6000_generate_compare (GET_CODE (op));
10920 cr = XEXP (condition_rtx, 0);
10922 if (GET_MODE (cr) == CCmode)
10923 emit_insn (gen_isel_signed (dest, condition_rtx,
10924 true_cond, false_cond, cr));
10926 emit_insn (gen_isel_unsigned (dest, condition_rtx,
10927 true_cond, false_cond, cr));
10933 output_isel (rtx *operands)
10935 enum rtx_code code;
10937 code = GET_CODE (operands[1]);
10938 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
10940 PUT_CODE (operands[1], reverse_condition (code));
10941 return "isel %0,%3,%2,%j1";
10944 return "isel %0,%2,%3,%j1";
10948 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
10950 enum machine_mode mode = GET_MODE (op0);
10954 if (code == SMAX || code == SMIN)
10959 if (code == SMAX || code == UMAX)
10960 target = emit_conditional_move (dest, c, op0, op1, mode,
10961 op0, op1, mode, 0);
10963 target = emit_conditional_move (dest, c, op0, op1, mode,
10964 op1, op0, mode, 0);
10965 if (target == NULL_RTX)
10967 if (target != dest)
10968 emit_move_insn (dest, target);
10971 /* Emit instructions to move SRC to DST. Called by splitters for
10972 multi-register moves. It will emit at most one instruction for
10973 each register that is accessed; that is, it won't emit li/lis pairs
10974 (or equivalent for 64-bit code). One of SRC or DST must be a hard
10978 rs6000_split_multireg_move (rtx dst, rtx src)
10980 /* The register number of the first register being moved. */
10982 /* The mode that is to be moved. */
10983 enum machine_mode mode;
10984 /* The mode that the move is being done in, and its size. */
10985 enum machine_mode reg_mode;
10987 /* The number of registers that will be moved. */
10990 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
10991 mode = GET_MODE (dst);
10992 nregs = HARD_REGNO_NREGS (reg, mode);
10993 if (FP_REGNO_P (reg))
10995 else if (ALTIVEC_REGNO_P (reg))
10996 reg_mode = V16QImode;
10998 reg_mode = word_mode;
10999 reg_mode_size = GET_MODE_SIZE (reg_mode);
11001 if (reg_mode_size * nregs != GET_MODE_SIZE (mode))
11004 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
11006 /* Move register range backwards, if we might have destructive
11009 for (i = nregs - 1; i >= 0; i--)
11010 emit_insn (gen_rtx_SET (VOIDmode,
11011 simplify_gen_subreg (reg_mode, dst, mode,
11012 i * reg_mode_size),
11013 simplify_gen_subreg (reg_mode, src, mode,
11014 i * reg_mode_size)));
11020 bool used_update = false;
11022 if (MEM_P (src) && INT_REGNO_P (reg))
11026 if (GET_CODE (XEXP (src, 0)) == PRE_INC
11027 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
11030 breg = XEXP (XEXP (src, 0), 0);
11031 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
11032 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
11033 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
11034 emit_insn (TARGET_32BIT
11035 ? gen_addsi3 (breg, breg, delta_rtx)
11036 : gen_adddi3 (breg, breg, delta_rtx));
11037 src = gen_rtx_MEM (mode, breg);
11039 else if (! offsettable_memref_p (src))
11041 rtx newsrc, basereg;
11042 basereg = gen_rtx_REG (Pmode, reg);
11043 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
11044 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
11045 MEM_COPY_ATTRIBUTES (newsrc, src);
11049 breg = XEXP (src, 0);
11050 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
11051 breg = XEXP (breg, 0);
11053 /* If the base register we are using to address memory is
11054 also a destination reg, then change that register last. */
11056 && REGNO (breg) >= REGNO (dst)
11057 && REGNO (breg) < REGNO (dst) + nregs)
11058 j = REGNO (breg) - REGNO (dst);
11061 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
11065 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
11066 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
11069 breg = XEXP (XEXP (dst, 0), 0);
11070 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
11071 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
11072 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
11074 /* We have to update the breg before doing the store.
11075 Use store with update, if available. */
11079 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
11080 emit_insn (TARGET_32BIT
11081 ? (TARGET_POWERPC64
11082 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
11083 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
11084 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
11085 used_update = true;
11088 emit_insn (TARGET_32BIT
11089 ? gen_addsi3 (breg, breg, delta_rtx)
11090 : gen_adddi3 (breg, breg, delta_rtx));
11091 dst = gen_rtx_MEM (mode, breg);
11093 else if (! offsettable_memref_p (dst))
11097 for (i = 0; i < nregs; i++)
11099 /* Calculate index to next subword. */
11104 /* If compiler already emitted move of first word by
11105 store with update, no need to do anything. */
11106 if (j == 0 && used_update)
11109 emit_insn (gen_rtx_SET (VOIDmode,
11110 simplify_gen_subreg (reg_mode, dst, mode,
11111 j * reg_mode_size),
11112 simplify_gen_subreg (reg_mode, src, mode,
11113 j * reg_mode_size)));
11119 /* This page contains routines that are used to determine what the
11120 function prologue and epilogue code will do and write them out. */
11122 /* Return the first fixed-point register that is required to be
11123 saved. 32 if none. */
11126 first_reg_to_save (void)
11130 /* Find lowest numbered live register. */
11131 for (first_reg = 13; first_reg <= 31; first_reg++)
11132 if (regs_ever_live[first_reg]
11133 && (! call_used_regs[first_reg]
11134 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
11135 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
11136 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
11137 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
11142 && current_function_uses_pic_offset_table
11143 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
11144 return RS6000_PIC_OFFSET_TABLE_REGNUM;
11150 /* Similar, for FP regs. */
11153 first_fp_reg_to_save (void)
11157 /* Find lowest numbered live register. */
11158 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
11159 if (regs_ever_live[first_reg])
11165 /* Similar, for AltiVec regs. */
11168 first_altivec_reg_to_save (void)
11172 /* Stack frame remains as is unless we are in AltiVec ABI. */
11173 if (! TARGET_ALTIVEC_ABI)
11174 return LAST_ALTIVEC_REGNO + 1;
11176 /* Find lowest numbered live register. */
11177 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
11178 if (regs_ever_live[i])
11184 /* Return a 32-bit mask of the AltiVec registers we need to set in
11185 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
11186 the 32-bit word is 0. */
11188 static unsigned int
11189 compute_vrsave_mask (void)
11191 unsigned int i, mask = 0;
11193 /* First, find out if we use _any_ altivec registers. */
11194 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
11195 if (regs_ever_live[i])
11196 mask |= ALTIVEC_REG_BIT (i);
11201 /* Next, remove the argument registers from the set. These must
11202 be in the VRSAVE mask set by the caller, so we don't need to add
11203 them in again. More importantly, the mask we compute here is
11204 used to generate CLOBBERs in the set_vrsave insn, and we do not
11205 wish the argument registers to die. */
11206 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
11207 mask &= ~ALTIVEC_REG_BIT (i);
11209 /* Similarly, remove the return value from the set. */
11212 diddle_return_value (is_altivec_return_reg, &yes);
11214 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
11220 /* For a very restricted set of circumstances, we can cut down the
11221 size of prologues/epilogues by calling our own save/restore-the-world
11225 compute_save_world_info (rs6000_stack_t *info_ptr)
11227 info_ptr->world_save_p = 1;
11228 info_ptr->world_save_p
11229 = (WORLD_SAVE_P (info_ptr)
11230 && DEFAULT_ABI == ABI_DARWIN
11231 && ! (current_function_calls_setjmp && flag_exceptions)
11232 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
11233 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
11234 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
11235 && info_ptr->cr_save_p);
11237 /* This will not work in conjunction with sibcalls. Make sure there
11238 are none. (This check is expensive, but seldom executed.) */
11239 if (WORLD_SAVE_P (info_ptr))
11242 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
11243 if ( GET_CODE (insn) == CALL_INSN
11244 && SIBLING_CALL_P (insn))
11246 info_ptr->world_save_p = 0;
11251 if (WORLD_SAVE_P (info_ptr))
11253 /* Even if we're not touching VRsave, make sure there's room on the
11254 stack for it, if it looks like we're calling SAVE_WORLD, which
11255 will attempt to save it. */
11256 info_ptr->vrsave_size = 4;
11258 /* "Save" the VRsave register too if we're saving the world. */
11259 if (info_ptr->vrsave_mask == 0)
11260 info_ptr->vrsave_mask = compute_vrsave_mask ();
11262 /* Because the Darwin register save/restore routines only handle
11263 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
11264 check and abort if there's something worng. */
11265 if (info_ptr->first_fp_reg_save < FIRST_SAVED_FP_REGNO
11266 || info_ptr->first_altivec_reg_save < FIRST_SAVED_ALTIVEC_REGNO)
11274 is_altivec_return_reg (rtx reg, void *xyes)
11276 bool *yes = (bool *) xyes;
11277 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
11282 /* Calculate the stack information for the current function. This is
11283 complicated by having two separate calling sequences, the AIX calling
11284 sequence and the V.4 calling sequence.
11286 AIX (and Darwin/Mac OS X) stack frames look like:
11288 SP----> +---------------------------------------+
11289 | back chain to caller | 0 0
11290 +---------------------------------------+
11291 | saved CR | 4 8 (8-11)
11292 +---------------------------------------+
11294 +---------------------------------------+
11295 | reserved for compilers | 12 24
11296 +---------------------------------------+
11297 | reserved for binders | 16 32
11298 +---------------------------------------+
11299 | saved TOC pointer | 20 40
11300 +---------------------------------------+
11301 | Parameter save area (P) | 24 48
11302 +---------------------------------------+
11303 | Alloca space (A) | 24+P etc.
11304 +---------------------------------------+
11305 | Local variable space (L) | 24+P+A
11306 +---------------------------------------+
11307 | Float/int conversion temporary (X) | 24+P+A+L
11308 +---------------------------------------+
11309 | Save area for AltiVec registers (W) | 24+P+A+L+X
11310 +---------------------------------------+
11311 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
11312 +---------------------------------------+
11313 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
11314 +---------------------------------------+
11315 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
11316 +---------------------------------------+
11317 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
11318 +---------------------------------------+
11319 old SP->| back chain to caller's caller |
11320 +---------------------------------------+
11322 The required alignment for AIX configurations is two words (i.e., 8
11326 V.4 stack frames look like:
11328 SP----> +---------------------------------------+
11329 | back chain to caller | 0
11330 +---------------------------------------+
11331 | caller's saved LR | 4
11332 +---------------------------------------+
11333 | Parameter save area (P) | 8
11334 +---------------------------------------+
11335 | Alloca space (A) | 8+P
11336 +---------------------------------------+
11337 | Varargs save area (V) | 8+P+A
11338 +---------------------------------------+
11339 | Local variable space (L) | 8+P+A+V
11340 +---------------------------------------+
11341 | Float/int conversion temporary (X) | 8+P+A+V+L
11342 +---------------------------------------+
11343 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
11344 +---------------------------------------+
11345 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
11346 +---------------------------------------+
11347 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
11348 +---------------------------------------+
11349 | SPE: area for 64-bit GP registers |
11350 +---------------------------------------+
11351 | SPE alignment padding |
11352 +---------------------------------------+
11353 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
11354 +---------------------------------------+
11355 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
11356 +---------------------------------------+
11357 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
11358 +---------------------------------------+
11359 old SP->| back chain to caller's caller |
11360 +---------------------------------------+
11362 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
11363 given. (But note below and in sysv4.h that we require only 8 and
11364 may round up the size of our stack frame anyways. The historical
11365 reason is early versions of powerpc-linux which didn't properly
11366 align the stack at program startup. A happy side-effect is that
11367 -mno-eabi libraries can be used with -meabi programs.)
11369 The EABI configuration defaults to the V.4 layout. However,
11370 the stack alignment requirements may differ. If -mno-eabi is not
11371 given, the required stack alignment is 8 bytes; if -mno-eabi is
11372 given, the required alignment is 16 bytes. (But see V.4 comment
11375 #ifndef ABI_STACK_BOUNDARY
11376 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
11379 static rs6000_stack_t *
11380 rs6000_stack_info (void)
11382 static rs6000_stack_t info, zero_info;
11383 rs6000_stack_t *info_ptr = &info;
11384 int reg_size = TARGET_32BIT ? 4 : 8;
11387 HOST_WIDE_INT non_fixed_size;
11389 /* Zero all fields portably. */
11394 /* Cache value so we don't rescan instruction chain over and over. */
11395 if (cfun->machine->insn_chain_scanned_p == 0)
11396 cfun->machine->insn_chain_scanned_p
11397 = spe_func_has_64bit_regs_p () + 1;
11398 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
11401 /* Select which calling sequence. */
11402 info_ptr->abi = DEFAULT_ABI;
11404 /* Calculate which registers need to be saved & save area size. */
11405 info_ptr->first_gp_reg_save = first_reg_to_save ();
11406 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
11407 even if it currently looks like we won't. */
11408 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
11409 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
11410 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
11411 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
11412 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
11414 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
11416 /* For the SPE, we have an additional upper 32-bits on each GPR.
11417 Ideally we should save the entire 64-bits only when the upper
11418 half is used in SIMD instructions. Since we only record
11419 registers live (not the size they are used in), this proves
11420 difficult because we'd have to traverse the instruction chain at
11421 the right time, taking reload into account. This is a real pain,
11422 so we opt to save the GPRs in 64-bits always if but one register
11423 gets used in 64-bits. Otherwise, all the registers in the frame
11424 get saved in 32-bits.
11426 So... since when we save all GPRs (except the SP) in 64-bits, the
11427 traditional GP save area will be empty. */
11428 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11429 info_ptr->gp_size = 0;
11431 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
11432 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
11434 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
11435 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
11436 - info_ptr->first_altivec_reg_save);
11438 /* Does this function call anything? */
11439 info_ptr->calls_p = (! current_function_is_leaf
11440 || cfun->machine->ra_needs_full_frame);
11442 /* Determine if we need to save the link register. */
11443 if (rs6000_ra_ever_killed ()
11444 || (DEFAULT_ABI == ABI_AIX
11445 && current_function_profile
11446 && !TARGET_PROFILE_KERNEL)
11447 #ifdef TARGET_RELOCATABLE
11448 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
11450 || (info_ptr->first_fp_reg_save != 64
11451 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
11452 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
11453 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
11454 || (DEFAULT_ABI == ABI_DARWIN
11456 && current_function_uses_pic_offset_table)
11457 || info_ptr->calls_p)
11459 info_ptr->lr_save_p = 1;
11460 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
11463 /* Determine if we need to save the condition code registers. */
11464 if (regs_ever_live[CR2_REGNO]
11465 || regs_ever_live[CR3_REGNO]
11466 || regs_ever_live[CR4_REGNO])
11468 info_ptr->cr_save_p = 1;
11469 if (DEFAULT_ABI == ABI_V4)
11470 info_ptr->cr_size = reg_size;
11473 /* If the current function calls __builtin_eh_return, then we need
11474 to allocate stack space for registers that will hold data for
11475 the exception handler. */
11476 if (current_function_calls_eh_return)
11479 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
11482 /* SPE saves EH registers in 64-bits. */
11483 ehrd_size = i * (TARGET_SPE_ABI
11484 && info_ptr->spe_64bit_regs_used != 0
11485 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
11490 /* Determine various sizes. */
11491 info_ptr->reg_size = reg_size;
11492 info_ptr->fixed_size = RS6000_SAVE_AREA;
11493 info_ptr->varargs_size = RS6000_VARARGS_AREA;
11494 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
11495 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
11496 TARGET_ALTIVEC ? 16 : 8);
11498 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11499 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
11501 info_ptr->spe_gp_size = 0;
11503 if (TARGET_ALTIVEC_ABI)
11504 info_ptr->vrsave_mask = compute_vrsave_mask ();
11506 info_ptr->vrsave_mask = 0;
11508 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
11509 info_ptr->vrsave_size = 4;
11511 info_ptr->vrsave_size = 0;
11513 compute_save_world_info (info_ptr);
11515 /* Calculate the offsets. */
11516 switch (DEFAULT_ABI)
11524 info_ptr->fp_save_offset = - info_ptr->fp_size;
11525 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11527 if (TARGET_ALTIVEC_ABI)
11529 info_ptr->vrsave_save_offset
11530 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
11532 /* Align stack so vector save area is on a quadword boundary. */
11533 if (info_ptr->altivec_size != 0)
11534 info_ptr->altivec_padding_size
11535 = 16 - (-info_ptr->vrsave_save_offset % 16);
11537 info_ptr->altivec_padding_size = 0;
11539 info_ptr->altivec_save_offset
11540 = info_ptr->vrsave_save_offset
11541 - info_ptr->altivec_padding_size
11542 - info_ptr->altivec_size;
11544 /* Adjust for AltiVec case. */
11545 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
11548 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
11549 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
11550 info_ptr->lr_save_offset = 2*reg_size;
11554 info_ptr->fp_save_offset = - info_ptr->fp_size;
11555 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
11556 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
11558 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
11560 /* Align stack so SPE GPR save area is aligned on a
11561 double-word boundary. */
11562 if (info_ptr->spe_gp_size != 0)
11563 info_ptr->spe_padding_size
11564 = 8 - (-info_ptr->cr_save_offset % 8);
11566 info_ptr->spe_padding_size = 0;
11568 info_ptr->spe_gp_save_offset
11569 = info_ptr->cr_save_offset
11570 - info_ptr->spe_padding_size
11571 - info_ptr->spe_gp_size;
11573 /* Adjust for SPE case. */
11574 info_ptr->toc_save_offset
11575 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
11577 else if (TARGET_ALTIVEC_ABI)
11579 info_ptr->vrsave_save_offset
11580 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
11582 /* Align stack so vector save area is on a quadword boundary. */
11583 if (info_ptr->altivec_size != 0)
11584 info_ptr->altivec_padding_size
11585 = 16 - (-info_ptr->vrsave_save_offset % 16);
11587 info_ptr->altivec_padding_size = 0;
11589 info_ptr->altivec_save_offset
11590 = info_ptr->vrsave_save_offset
11591 - info_ptr->altivec_padding_size
11592 - info_ptr->altivec_size;
11594 /* Adjust for AltiVec case. */
11595 info_ptr->toc_save_offset
11596 = info_ptr->altivec_save_offset - info_ptr->toc_size;
11599 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
11600 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
11601 info_ptr->lr_save_offset = reg_size;
11605 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
11606 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
11607 + info_ptr->gp_size
11608 + info_ptr->altivec_size
11609 + info_ptr->altivec_padding_size
11610 + info_ptr->spe_gp_size
11611 + info_ptr->spe_padding_size
11613 + info_ptr->cr_size
11614 + info_ptr->lr_size
11615 + info_ptr->vrsave_size
11616 + info_ptr->toc_size,
11619 non_fixed_size = (info_ptr->vars_size
11620 + info_ptr->parm_size
11621 + info_ptr->save_size
11622 + info_ptr->varargs_size);
11624 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
11625 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
11627 /* Determine if we need to allocate any stack frame:
11629 For AIX we need to push the stack if a frame pointer is needed
11630 (because the stack might be dynamically adjusted), if we are
11631 debugging, if we make calls, or if the sum of fp_save, gp_save,
11632 and local variables are more than the space needed to save all
11633 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
11634 + 18*8 = 288 (GPR13 reserved).
11636 For V.4 we don't have the stack cushion that AIX uses, but assume
11637 that the debugger can handle stackless frames. */
11639 if (info_ptr->calls_p)
11640 info_ptr->push_p = 1;
11642 else if (DEFAULT_ABI == ABI_V4)
11643 info_ptr->push_p = non_fixed_size != 0;
11645 else if (frame_pointer_needed)
11646 info_ptr->push_p = 1;
11648 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
11649 info_ptr->push_p = 1;
11652 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
11654 /* Zero offsets if we're not saving those registers. */
11655 if (info_ptr->fp_size == 0)
11656 info_ptr->fp_save_offset = 0;
11658 if (info_ptr->gp_size == 0)
11659 info_ptr->gp_save_offset = 0;
11661 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
11662 info_ptr->altivec_save_offset = 0;
11664 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
11665 info_ptr->vrsave_save_offset = 0;
11667 if (! TARGET_SPE_ABI
11668 || info_ptr->spe_64bit_regs_used == 0
11669 || info_ptr->spe_gp_size == 0)
11670 info_ptr->spe_gp_save_offset = 0;
11672 if (! info_ptr->lr_save_p)
11673 info_ptr->lr_save_offset = 0;
11675 if (! info_ptr->cr_save_p)
11676 info_ptr->cr_save_offset = 0;
11678 if (! info_ptr->toc_save_p)
11679 info_ptr->toc_save_offset = 0;
11684 /* Return true if the current function uses any GPRs in 64-bit SIMD
11688 spe_func_has_64bit_regs_p (void)
11692 /* Functions that save and restore all the call-saved registers will
11693 need to save/restore the registers in 64-bits. */
11694 if (current_function_calls_eh_return
11695 || current_function_calls_setjmp
11696 || current_function_has_nonlocal_goto)
11699 insns = get_insns ();
11701 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
11707 /* FIXME: This should be implemented with attributes...
11709 (set_attr "spe64" "true")....then,
11710 if (get_spe64(insn)) return true;
11712 It's the only reliable way to do the stuff below. */
11714 i = PATTERN (insn);
11715 if (GET_CODE (i) == SET)
11717 enum machine_mode mode = GET_MODE (SET_SRC (i));
11719 if (SPE_VECTOR_MODE (mode))
11721 if (TARGET_E500_DOUBLE && mode == DFmode)
11731 debug_stack_info (rs6000_stack_t *info)
11733 const char *abi_string;
11736 info = rs6000_stack_info ();
11738 fprintf (stderr, "\nStack information for function %s:\n",
11739 ((current_function_decl && DECL_NAME (current_function_decl))
11740 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
11745 default: abi_string = "Unknown"; break;
11746 case ABI_NONE: abi_string = "NONE"; break;
11747 case ABI_AIX: abi_string = "AIX"; break;
11748 case ABI_DARWIN: abi_string = "Darwin"; break;
11749 case ABI_V4: abi_string = "V.4"; break;
11752 fprintf (stderr, "\tABI = %5s\n", abi_string);
11754 if (TARGET_ALTIVEC_ABI)
11755 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
11757 if (TARGET_SPE_ABI)
11758 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
11760 if (info->first_gp_reg_save != 32)
11761 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
11763 if (info->first_fp_reg_save != 64)
11764 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
11766 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
11767 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
11768 info->first_altivec_reg_save);
11770 if (info->lr_save_p)
11771 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
11773 if (info->cr_save_p)
11774 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
11776 if (info->toc_save_p)
11777 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
11779 if (info->vrsave_mask)
11780 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
11783 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
11786 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
11788 if (info->gp_save_offset)
11789 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
11791 if (info->fp_save_offset)
11792 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
11794 if (info->altivec_save_offset)
11795 fprintf (stderr, "\taltivec_save_offset = %5d\n",
11796 info->altivec_save_offset);
11798 if (info->spe_gp_save_offset)
11799 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
11800 info->spe_gp_save_offset);
11802 if (info->vrsave_save_offset)
11803 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
11804 info->vrsave_save_offset);
11806 if (info->lr_save_offset)
11807 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
11809 if (info->cr_save_offset)
11810 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
11812 if (info->toc_save_offset)
11813 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
11815 if (info->varargs_save_offset)
11816 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
11818 if (info->total_size)
11819 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11822 if (info->varargs_size)
11823 fprintf (stderr, "\tvarargs_size = %5d\n", info->varargs_size);
11825 if (info->vars_size)
11826 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
11829 if (info->parm_size)
11830 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
11832 if (info->fixed_size)
11833 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
11836 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
11838 if (info->spe_gp_size)
11839 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
11842 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
11844 if (info->altivec_size)
11845 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
11847 if (info->vrsave_size)
11848 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
11850 if (info->altivec_padding_size)
11851 fprintf (stderr, "\taltivec_padding_size= %5d\n",
11852 info->altivec_padding_size);
11854 if (info->spe_padding_size)
11855 fprintf (stderr, "\tspe_padding_size = %5d\n",
11856 info->spe_padding_size);
11859 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
11862 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
11864 if (info->toc_size)
11865 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
11867 if (info->save_size)
11868 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
11870 if (info->reg_size != 4)
11871 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
11873 fprintf (stderr, "\n");
11877 rs6000_return_addr (int count, rtx frame)
11879 /* Currently we don't optimize very well between prolog and body
11880 code and for PIC code the code can be actually quite bad, so
11881 don't try to be too clever here. */
11882 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
11884 cfun->machine->ra_needs_full_frame = 1;
11891 plus_constant (copy_to_reg
11892 (gen_rtx_MEM (Pmode,
11893 memory_address (Pmode, frame))),
11894 RETURN_ADDRESS_OFFSET)));
11897 cfun->machine->ra_need_lr = 1;
11898 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
11901 /* Say whether a function is a candidate for sibcall handling or not.
11902 We do not allow indirect calls to be optimized into sibling calls.
11903 Also, we can't do it if there are any vector parameters; there's
11904 nowhere to put the VRsave code so it works; note that functions with
11905 vector parameters are required to have a prototype, so the argument
11906 type info must be available here. (The tail recursion case can work
11907 with vector parameters, but there's no way to distinguish here.) */
11909 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
11914 if (TARGET_ALTIVEC_VRSAVE)
11916 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
11917 type; type = TREE_CHAIN (type))
11919 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
11923 if (DEFAULT_ABI == ABI_DARWIN
11924 || (*targetm.binds_local_p) (decl))
11926 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
11928 if (!lookup_attribute ("longcall", attr_list)
11929 || lookup_attribute ("shortcall", attr_list))
11937 rs6000_ra_ever_killed (void)
11943 if (current_function_is_thunk)
11946 /* regs_ever_live has LR marked as used if any sibcalls are present,
11947 but this should not force saving and restoring in the
11948 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
11949 clobbers LR, so that is inappropriate. */
11951 /* Also, the prologue can generate a store into LR that
11952 doesn't really count, like this:
11955 bcl to set PIC register
11959 When we're called from the epilogue, we need to avoid counting
11960 this as a store. */
11962 push_topmost_sequence ();
11963 top = get_insns ();
11964 pop_topmost_sequence ();
11965 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
11967 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
11971 if (FIND_REG_INC_NOTE (insn, reg))
11973 else if (GET_CODE (insn) == CALL_INSN
11974 && !SIBLING_CALL_P (insn))
11976 else if (set_of (reg, insn) != NULL_RTX
11977 && !prologue_epilogue_contains (insn))
11984 /* Add a REG_MAYBE_DEAD note to the insn. */
11986 rs6000_maybe_dead (rtx insn)
11988 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
11993 /* Emit instructions needed to load the TOC register.
11994 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
11995 a constant pool; or for SVR4 -fpic. */
11998 rs6000_emit_load_toc_table (int fromprolog)
12001 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
12003 if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
12005 rtx temp = (fromprolog
12006 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12007 : gen_reg_rtx (Pmode));
12008 insn = emit_insn (gen_load_toc_v4_pic_si (temp));
12010 rs6000_maybe_dead (insn);
12011 insn = emit_move_insn (dest, temp);
12013 rs6000_maybe_dead (insn);
12015 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
12018 rtx tempLR = (fromprolog
12019 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
12020 : gen_reg_rtx (Pmode));
12021 rtx temp0 = (fromprolog
12022 ? gen_rtx_REG (Pmode, 0)
12023 : gen_reg_rtx (Pmode));
12030 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
12031 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12033 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
12034 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12036 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
12038 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
12039 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
12046 static int reload_toc_labelno = 0;
12048 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
12050 ASM_GENERATE_INTERNAL_LABEL (buf, "LCG", reload_toc_labelno++);
12051 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12053 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, symF, tocsym));
12054 emit_move_insn (dest, tempLR);
12055 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
12057 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
12059 rs6000_maybe_dead (insn);
12061 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
12063 /* This is for AIX code running in non-PIC ELF32. */
12066 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
12067 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
12069 insn = emit_insn (gen_elf_high (dest, realsym));
12071 rs6000_maybe_dead (insn);
12072 insn = emit_insn (gen_elf_low (dest, dest, realsym));
12074 rs6000_maybe_dead (insn);
12076 else if (DEFAULT_ABI == ABI_AIX)
12079 insn = emit_insn (gen_load_toc_aix_si (dest));
12081 insn = emit_insn (gen_load_toc_aix_di (dest));
12083 rs6000_maybe_dead (insn);
12089 /* Emit instructions to restore the link register after determining where
12090 its value has been stored. */
12093 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
12095 rs6000_stack_t *info = rs6000_stack_info ();
12098 operands[0] = source;
12099 operands[1] = scratch;
12101 if (info->lr_save_p)
12103 rtx frame_rtx = stack_pointer_rtx;
12104 HOST_WIDE_INT sp_offset = 0;
12107 if (frame_pointer_needed
12108 || current_function_calls_alloca
12109 || info->total_size > 32767)
12111 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
12112 frame_rtx = operands[1];
12114 else if (info->push_p)
12115 sp_offset = info->total_size;
12117 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
12118 tmp = gen_rtx_MEM (Pmode, tmp);
12119 emit_move_insn (tmp, operands[0]);
12122 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
12125 static GTY(()) int set = -1;
12128 get_TOC_alias_set (void)
12131 set = new_alias_set ();
12135 /* This returns nonzero if the current function uses the TOC. This is
12136 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
12137 is generated by the ABI_V4 load_toc_* patterns. */
12144 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
12147 rtx pat = PATTERN (insn);
12150 if (GET_CODE (pat) == PARALLEL)
12151 for (i = 0; i < XVECLEN (pat, 0); i++)
12153 rtx sub = XVECEXP (pat, 0, i);
12154 if (GET_CODE (sub) == USE)
12156 sub = XEXP (sub, 0);
12157 if (GET_CODE (sub) == UNSPEC
12158 && XINT (sub, 1) == UNSPEC_TOC)
12168 create_TOC_reference (rtx symbol)
12170 return gen_rtx_PLUS (Pmode,
12171 gen_rtx_REG (Pmode, TOC_REGISTER),
12172 gen_rtx_CONST (Pmode,
12173 gen_rtx_MINUS (Pmode, symbol,
12174 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
12177 /* If _Unwind_* has been called from within the same module,
12178 toc register is not guaranteed to be saved to 40(1) on function
12179 entry. Save it there in that case. */
12182 rs6000_aix_emit_builtin_unwind_init (void)
12185 rtx stack_top = gen_reg_rtx (Pmode);
12186 rtx opcode_addr = gen_reg_rtx (Pmode);
12187 rtx opcode = gen_reg_rtx (SImode);
12188 rtx tocompare = gen_reg_rtx (SImode);
12189 rtx no_toc_save_needed = gen_label_rtx ();
12191 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
12192 emit_move_insn (stack_top, mem);
12194 mem = gen_rtx_MEM (Pmode,
12195 gen_rtx_PLUS (Pmode, stack_top,
12196 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
12197 emit_move_insn (opcode_addr, mem);
12198 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
12199 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
12200 : 0xE8410028, SImode));
12202 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
12203 SImode, NULL_RTX, NULL_RTX,
12204 no_toc_save_needed);
12206 mem = gen_rtx_MEM (Pmode,
12207 gen_rtx_PLUS (Pmode, stack_top,
12208 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
12209 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
12210 emit_label (no_toc_save_needed);
12213 /* This ties together stack memory (MEM with an alias set of
12214 rs6000_sr_alias_set) and the change to the stack pointer. */
12217 rs6000_emit_stack_tie (void)
12219 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
12221 set_mem_alias_set (mem, rs6000_sr_alias_set);
12222 emit_insn (gen_stack_tie (mem));
12225 /* Emit the correct code for allocating stack space, as insns.
12226 If COPY_R12, make sure a copy of the old frame is left in r12.
12227 The generated code may use hard register 0 as a temporary. */
12230 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
12233 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12234 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
12235 rtx todec = gen_int_mode (-size, Pmode);
12237 if (INTVAL (todec) != -size)
12239 warning ("stack frame too large");
12240 emit_insn (gen_trap ());
12244 if (current_function_limit_stack)
12246 if (REG_P (stack_limit_rtx)
12247 && REGNO (stack_limit_rtx) > 1
12248 && REGNO (stack_limit_rtx) <= 31)
12250 emit_insn (TARGET_32BIT
12251 ? gen_addsi3 (tmp_reg,
12254 : gen_adddi3 (tmp_reg,
12258 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12261 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
12263 && DEFAULT_ABI == ABI_V4)
12265 rtx toload = gen_rtx_CONST (VOIDmode,
12266 gen_rtx_PLUS (Pmode,
12270 emit_insn (gen_elf_high (tmp_reg, toload));
12271 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
12272 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
12276 warning ("stack limit expression is not supported");
12279 if (copy_r12 || ! TARGET_UPDATE)
12280 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
12286 /* Need a note here so that try_split doesn't get confused. */
12287 if (get_last_insn () == NULL_RTX)
12288 emit_note (NOTE_INSN_DELETED);
12289 insn = emit_move_insn (tmp_reg, todec);
12290 try_split (PATTERN (insn), insn, 0);
12294 insn = emit_insn (TARGET_32BIT
12295 ? gen_movsi_update (stack_reg, stack_reg,
12297 : gen_movdi_di_update (stack_reg, stack_reg,
12298 todec, stack_reg));
12302 insn = emit_insn (TARGET_32BIT
12303 ? gen_addsi3 (stack_reg, stack_reg, todec)
12304 : gen_adddi3 (stack_reg, stack_reg, todec));
12305 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
12306 gen_rtx_REG (Pmode, 12));
12309 RTX_FRAME_RELATED_P (insn) = 1;
12311 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12312 gen_rtx_SET (VOIDmode, stack_reg,
12313 gen_rtx_PLUS (Pmode, stack_reg,
12318 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
12319 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
12320 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
12321 deduce these equivalences by itself so it wasn't necessary to hold
12322 its hand so much. */
12325 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
12326 rtx reg2, rtx rreg)
12330 /* copy_rtx will not make unique copies of registers, so we need to
12331 ensure we don't have unwanted sharing here. */
12333 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12336 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
12338 real = copy_rtx (PATTERN (insn));
12340 if (reg2 != NULL_RTX)
12341 real = replace_rtx (real, reg2, rreg);
12343 real = replace_rtx (real, reg,
12344 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
12345 STACK_POINTER_REGNUM),
12348 /* We expect that 'real' is either a SET or a PARALLEL containing
12349 SETs (and possibly other stuff). In a PARALLEL, all the SETs
12350 are important so they all have to be marked RTX_FRAME_RELATED_P. */
12352 if (GET_CODE (real) == SET)
12356 temp = simplify_rtx (SET_SRC (set));
12358 SET_SRC (set) = temp;
12359 temp = simplify_rtx (SET_DEST (set));
12361 SET_DEST (set) = temp;
12362 if (GET_CODE (SET_DEST (set)) == MEM)
12364 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12366 XEXP (SET_DEST (set), 0) = temp;
12369 else if (GET_CODE (real) == PARALLEL)
12372 for (i = 0; i < XVECLEN (real, 0); i++)
12373 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
12375 rtx set = XVECEXP (real, 0, i);
12377 temp = simplify_rtx (SET_SRC (set));
12379 SET_SRC (set) = temp;
12380 temp = simplify_rtx (SET_DEST (set));
12382 SET_DEST (set) = temp;
12383 if (GET_CODE (SET_DEST (set)) == MEM)
12385 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
12387 XEXP (SET_DEST (set), 0) = temp;
12389 RTX_FRAME_RELATED_P (set) = 1;
12396 real = spe_synthesize_frame_save (real);
12398 RTX_FRAME_RELATED_P (insn) = 1;
12399 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12404 /* Given an SPE frame note, return a PARALLEL of SETs with the
12405 original note, plus a synthetic register save. */
12408 spe_synthesize_frame_save (rtx real)
12410 rtx synth, offset, reg, real2;
12412 if (GET_CODE (real) != SET
12413 || GET_MODE (SET_SRC (real)) != V2SImode)
12416 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
12417 frame related note. The parallel contains a set of the register
12418 being saved, and another set to a synthetic register (n+1200).
12419 This is so we can differentiate between 64-bit and 32-bit saves.
12420 Words cannot describe this nastiness. */
12422 if (GET_CODE (SET_DEST (real)) != MEM
12423 || GET_CODE (XEXP (SET_DEST (real), 0)) != PLUS
12424 || GET_CODE (SET_SRC (real)) != REG)
12428 (set (mem (plus (reg x) (const y)))
12431 (set (mem (plus (reg x) (const y+4)))
12435 real2 = copy_rtx (real);
12436 PUT_MODE (SET_DEST (real2), SImode);
12437 reg = SET_SRC (real2);
12438 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
12439 synth = copy_rtx (real2);
12441 if (BYTES_BIG_ENDIAN)
12443 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
12444 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
12447 reg = SET_SRC (synth);
12449 synth = replace_rtx (synth, reg,
12450 gen_rtx_REG (SImode, REGNO (reg) + 1200));
12452 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
12453 synth = replace_rtx (synth, offset,
12454 GEN_INT (INTVAL (offset)
12455 + (BYTES_BIG_ENDIAN ? 0 : 4)));
12457 RTX_FRAME_RELATED_P (synth) = 1;
12458 RTX_FRAME_RELATED_P (real2) = 1;
12459 if (BYTES_BIG_ENDIAN)
12460 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
12462 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
12467 /* Returns an insn that has a vrsave set operation with the
12468 appropriate CLOBBERs. */
12471 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
12474 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
12475 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12478 = gen_rtx_SET (VOIDmode,
12480 gen_rtx_UNSPEC_VOLATILE (SImode,
12481 gen_rtvec (2, reg, vrsave),
12486 /* We need to clobber the registers in the mask so the scheduler
12487 does not move sets to VRSAVE before sets of AltiVec registers.
12489 However, if the function receives nonlocal gotos, reload will set
12490 all call saved registers live. We will end up with:
12492 (set (reg 999) (mem))
12493 (parallel [ (set (reg vrsave) (unspec blah))
12494 (clobber (reg 999))])
12496 The clobber will cause the store into reg 999 to be dead, and
12497 flow will attempt to delete an epilogue insn. In this case, we
12498 need an unspec use/set of the register. */
12500 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12501 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12503 if (!epiloguep || call_used_regs [i])
12504 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
12505 gen_rtx_REG (V4SImode, i));
12508 rtx reg = gen_rtx_REG (V4SImode, i);
12511 = gen_rtx_SET (VOIDmode,
12513 gen_rtx_UNSPEC (V4SImode,
12514 gen_rtvec (1, reg), 27));
12518 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
12520 for (i = 0; i < nclobs; ++i)
12521 XVECEXP (insn, 0, i) = clobs[i];
12526 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
12527 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
12530 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
12531 unsigned int regno, int offset, HOST_WIDE_INT total_size)
12533 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
12534 rtx replacea, replaceb;
12536 int_rtx = GEN_INT (offset);
12538 /* Some cases that need register indexed addressing. */
12539 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
12540 || (TARGET_E500_DOUBLE && mode == DFmode)
12542 && SPE_VECTOR_MODE (mode)
12543 && !SPE_CONST_OFFSET_OK (offset)))
12545 /* Whomever calls us must make sure r11 is available in the
12546 flow path of instructions in the prologue. */
12547 offset_rtx = gen_rtx_REG (Pmode, 11);
12548 emit_move_insn (offset_rtx, int_rtx);
12550 replacea = offset_rtx;
12551 replaceb = int_rtx;
12555 offset_rtx = int_rtx;
12556 replacea = NULL_RTX;
12557 replaceb = NULL_RTX;
12560 reg = gen_rtx_REG (mode, regno);
12561 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
12562 mem = gen_rtx_MEM (mode, addr);
12563 set_mem_alias_set (mem, rs6000_sr_alias_set);
12565 insn = emit_move_insn (mem, reg);
12567 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
12570 /* Emit an offset memory reference suitable for a frame store, while
12571 converting to a valid addressing mode. */
12574 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
12576 rtx int_rtx, offset_rtx;
12578 int_rtx = GEN_INT (offset);
12580 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
12581 || (TARGET_E500_DOUBLE && mode == DFmode))
12583 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12584 emit_move_insn (offset_rtx, int_rtx);
12587 offset_rtx = int_rtx;
12589 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
12592 #ifndef TARGET_FIX_AND_CONTINUE
12593 #define TARGET_FIX_AND_CONTINUE 0
12596 /* Emit function prologue as insns. */
12599 rs6000_emit_prologue (void)
12601 rs6000_stack_t *info = rs6000_stack_info ();
12602 enum machine_mode reg_mode = Pmode;
12603 int reg_size = TARGET_32BIT ? 4 : 8;
12604 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
12605 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
12606 rtx frame_reg_rtx = sp_reg_rtx;
12607 rtx cr_save_rtx = NULL_RTX;
12609 int saving_FPRs_inline;
12610 int using_store_multiple;
12611 HOST_WIDE_INT sp_offset = 0;
12613 if (TARGET_FIX_AND_CONTINUE)
12615 /* gdb on darwin arranges to forward a function from the old
12616 address by modifying the first 4 instructions of the function
12617 to branch to the overriding function. This is necessary to
12618 permit function pointers that point to the old function to
12619 actually forward to the new function. */
12620 emit_insn (gen_nop ());
12621 emit_insn (gen_nop ());
12622 emit_insn (gen_nop ());
12623 emit_insn (gen_nop ());
12626 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12628 reg_mode = V2SImode;
12632 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
12633 && (!TARGET_SPE_ABI
12634 || info->spe_64bit_regs_used == 0)
12635 && info->first_gp_reg_save < 31);
12636 saving_FPRs_inline = (info->first_fp_reg_save == 64
12637 || FP_SAVE_INLINE (info->first_fp_reg_save)
12638 || current_function_calls_eh_return
12639 || cfun->machine->ra_need_lr);
12641 /* For V.4, update stack before we do any saving and set back pointer. */
12643 && (DEFAULT_ABI == ABI_V4
12644 || current_function_calls_eh_return))
12646 if (info->total_size < 32767)
12647 sp_offset = info->total_size;
12649 frame_reg_rtx = frame_ptr_rtx;
12650 rs6000_emit_allocate_stack (info->total_size,
12651 (frame_reg_rtx != sp_reg_rtx
12652 && (info->cr_save_p
12654 || info->first_fp_reg_save < 64
12655 || info->first_gp_reg_save < 32
12657 if (frame_reg_rtx != sp_reg_rtx)
12658 rs6000_emit_stack_tie ();
12661 /* Handle world saves specially here. */
12662 if (WORLD_SAVE_P (info))
12668 /* save_world expects lr in r0. */
12669 if (info->lr_save_p)
12671 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12672 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12673 RTX_FRAME_RELATED_P (insn) = 1;
12676 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
12677 assumptions about the offsets of various bits of the stack
12678 frame. Abort if things aren't what they should be. */
12679 if (info->gp_save_offset != -220
12680 || info->fp_save_offset != -144
12681 || info->lr_save_offset != 8
12682 || info->cr_save_offset != 4
12684 || !info->lr_save_p
12685 || (current_function_calls_eh_return && info->ehrd_offset != -432)
12686 || (info->vrsave_save_offset != -224
12687 || info->altivec_save_offset != (-224 -16 -192)))
12690 treg = gen_rtx_REG (SImode, 11);
12691 emit_move_insn (treg, GEN_INT (-info->total_size));
12693 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
12694 in R11. It also clobbers R12, so beware! */
12696 /* Preserve CR2 for save_world prologues */
12698 sz += 32 - info->first_gp_reg_save;
12699 sz += 64 - info->first_fp_reg_save;
12700 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
12701 p = rtvec_alloc (sz);
12703 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
12704 gen_rtx_REG (Pmode,
12705 LINK_REGISTER_REGNUM));
12706 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
12707 gen_rtx_SYMBOL_REF (Pmode,
12709 /* We do floats first so that the instruction pattern matches
12711 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12713 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12714 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12715 GEN_INT (info->fp_save_offset
12716 + sp_offset + 8 * i));
12717 rtx mem = gen_rtx_MEM (DFmode, addr);
12718 set_mem_alias_set (mem, rs6000_sr_alias_set);
12720 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12722 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
12724 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
12725 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12726 GEN_INT (info->altivec_save_offset
12727 + sp_offset + 16 * i));
12728 rtx mem = gen_rtx_MEM (V4SImode, addr);
12729 set_mem_alias_set (mem, rs6000_sr_alias_set);
12731 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12733 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12735 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12736 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12737 GEN_INT (info->gp_save_offset
12738 + sp_offset + reg_size * i));
12739 rtx mem = gen_rtx_MEM (reg_mode, addr);
12740 set_mem_alias_set (mem, rs6000_sr_alias_set);
12742 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12746 /* CR register traditionally saved as CR2. */
12747 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
12748 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12749 GEN_INT (info->cr_save_offset
12751 rtx mem = gen_rtx_MEM (reg_mode, addr);
12752 set_mem_alias_set (mem, rs6000_sr_alias_set);
12754 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
12756 /* Prevent any attempt to delete the setting of r0 and treg! */
12757 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
12758 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
12759 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
12761 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12762 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12763 NULL_RTX, NULL_RTX);
12765 if (current_function_calls_eh_return)
12770 unsigned int regno = EH_RETURN_DATA_REGNO (i);
12771 if (regno == INVALID_REGNUM)
12773 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
12774 info->ehrd_offset + sp_offset
12775 + reg_size * (int) i,
12781 /* Save AltiVec registers if needed. */
12782 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
12786 /* There should be a non inline version of this, for when we
12787 are saving lots of vector registers. */
12788 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
12789 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
12791 rtx areg, savereg, mem;
12794 offset = info->altivec_save_offset + sp_offset
12795 + 16 * (i - info->first_altivec_reg_save);
12797 savereg = gen_rtx_REG (V4SImode, i);
12799 areg = gen_rtx_REG (Pmode, 0);
12800 emit_move_insn (areg, GEN_INT (offset));
12802 /* AltiVec addressing mode is [reg+reg]. */
12803 mem = gen_rtx_MEM (V4SImode,
12804 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
12806 set_mem_alias_set (mem, rs6000_sr_alias_set);
12808 insn = emit_move_insn (mem, savereg);
12810 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12811 areg, GEN_INT (offset));
12815 /* VRSAVE is a bit vector representing which AltiVec registers
12816 are used. The OS uses this to determine which vector
12817 registers to save on a context switch. We need to save
12818 VRSAVE on the stack frame, add whatever AltiVec registers we
12819 used in this function, and do the corresponding magic in the
12822 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
12823 && !WORLD_SAVE_P (info) && info->vrsave_mask != 0)
12825 rtx reg, mem, vrsave;
12828 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
12829 as frame_reg_rtx and r11 as the static chain pointer for
12830 nested functions. */
12831 reg = gen_rtx_REG (SImode, 0);
12832 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
12834 emit_insn (gen_get_vrsave_internal (reg));
12836 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
12839 offset = info->vrsave_save_offset + sp_offset;
12841 = gen_rtx_MEM (SImode,
12842 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
12843 set_mem_alias_set (mem, rs6000_sr_alias_set);
12844 insn = emit_move_insn (mem, reg);
12846 /* Include the registers in the mask. */
12847 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
12849 insn = emit_insn (generate_set_vrsave (reg, info, 0));
12852 /* If we use the link register, get it into r0. */
12853 if (!WORLD_SAVE_P (info) && info->lr_save_p)
12855 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
12856 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
12857 RTX_FRAME_RELATED_P (insn) = 1;
12860 /* If we need to save CR, put it into r12. */
12861 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
12865 cr_save_rtx = gen_rtx_REG (SImode, 12);
12866 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
12867 RTX_FRAME_RELATED_P (insn) = 1;
12868 /* Now, there's no way that dwarf2out_frame_debug_expr is going
12869 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
12870 But that's OK. All we have to do is specify that _one_ condition
12871 code register is saved in this stack slot. The thrower's epilogue
12872 will then restore all the call-saved registers.
12873 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
12874 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
12875 gen_rtx_REG (SImode, CR2_REGNO));
12876 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
12881 /* Do any required saving of fpr's. If only one or two to save, do
12882 it ourselves. Otherwise, call function. */
12883 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
12886 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12887 if ((regs_ever_live[info->first_fp_reg_save+i]
12888 && ! call_used_regs[info->first_fp_reg_save+i]))
12889 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
12890 info->first_fp_reg_save + i,
12891 info->fp_save_offset + sp_offset + 8 * i,
12894 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
12898 const char *alloc_rname;
12900 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
12902 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
12903 gen_rtx_REG (Pmode,
12904 LINK_REGISTER_REGNUM));
12905 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
12906 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
12907 alloc_rname = ggc_strdup (rname);
12908 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
12909 gen_rtx_SYMBOL_REF (Pmode,
12911 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
12913 rtx addr, reg, mem;
12914 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
12915 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12916 GEN_INT (info->fp_save_offset
12917 + sp_offset + 8*i));
12918 mem = gen_rtx_MEM (DFmode, addr);
12919 set_mem_alias_set (mem, rs6000_sr_alias_set);
12921 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
12923 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12924 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12925 NULL_RTX, NULL_RTX);
12928 /* Save GPRs. This is done as a PARALLEL if we are using
12929 the store-multiple instructions. */
12930 if (!WORLD_SAVE_P (info) && using_store_multiple)
12934 p = rtvec_alloc (32 - info->first_gp_reg_save);
12935 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12937 rtx addr, reg, mem;
12938 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12939 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12940 GEN_INT (info->gp_save_offset
12943 mem = gen_rtx_MEM (reg_mode, addr);
12944 set_mem_alias_set (mem, rs6000_sr_alias_set);
12946 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
12948 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
12949 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12950 NULL_RTX, NULL_RTX);
12952 else if (!WORLD_SAVE_P (info))
12955 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
12956 if ((regs_ever_live[info->first_gp_reg_save+i]
12957 && (! call_used_regs[info->first_gp_reg_save+i]
12958 || (i+info->first_gp_reg_save
12959 == RS6000_PIC_OFFSET_TABLE_REGNUM
12960 && TARGET_TOC && TARGET_MINIMAL_TOC)))
12961 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
12962 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12963 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
12965 rtx addr, reg, mem;
12966 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
12968 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
12970 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
12973 if (!SPE_CONST_OFFSET_OK (offset))
12975 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
12976 emit_move_insn (b, GEN_INT (offset));
12979 b = GEN_INT (offset);
12981 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
12982 mem = gen_rtx_MEM (V2SImode, addr);
12983 set_mem_alias_set (mem, rs6000_sr_alias_set);
12984 insn = emit_move_insn (mem, reg);
12986 if (GET_CODE (b) == CONST_INT)
12987 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12988 NULL_RTX, NULL_RTX);
12990 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
12991 b, GEN_INT (offset));
12995 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
12996 GEN_INT (info->gp_save_offset
12999 mem = gen_rtx_MEM (reg_mode, addr);
13000 set_mem_alias_set (mem, rs6000_sr_alias_set);
13002 insn = emit_move_insn (mem, reg);
13003 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13004 NULL_RTX, NULL_RTX);
13009 /* ??? There's no need to emit actual instructions here, but it's the
13010 easiest way to get the frame unwind information emitted. */
13011 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
13013 unsigned int i, regno;
13015 /* In AIX ABI we need to pretend we save r2 here. */
13018 rtx addr, reg, mem;
13020 reg = gen_rtx_REG (reg_mode, 2);
13021 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13022 GEN_INT (sp_offset + 5 * reg_size));
13023 mem = gen_rtx_MEM (reg_mode, addr);
13024 set_mem_alias_set (mem, rs6000_sr_alias_set);
13026 insn = emit_move_insn (mem, reg);
13027 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13028 NULL_RTX, NULL_RTX);
13029 PATTERN (insn) = gen_blockage ();
13034 regno = EH_RETURN_DATA_REGNO (i);
13035 if (regno == INVALID_REGNUM)
13038 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
13039 info->ehrd_offset + sp_offset
13040 + reg_size * (int) i,
13045 /* Save lr if we used it. */
13046 if (!WORLD_SAVE_P (info) && info->lr_save_p)
13048 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13049 GEN_INT (info->lr_save_offset + sp_offset));
13050 rtx reg = gen_rtx_REG (Pmode, 0);
13051 rtx mem = gen_rtx_MEM (Pmode, addr);
13052 /* This should not be of rs6000_sr_alias_set, because of
13053 __builtin_return_address. */
13055 insn = emit_move_insn (mem, reg);
13056 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13057 NULL_RTX, NULL_RTX);
13060 /* Save CR if we use any that must be preserved. */
13061 if (!WORLD_SAVE_P (info) && info->cr_save_p)
13063 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13064 GEN_INT (info->cr_save_offset + sp_offset));
13065 rtx mem = gen_rtx_MEM (SImode, addr);
13066 /* See the large comment above about why CR2_REGNO is used. */
13067 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
13069 set_mem_alias_set (mem, rs6000_sr_alias_set);
13071 /* If r12 was used to hold the original sp, copy cr into r0 now
13073 if (REGNO (frame_reg_rtx) == 12)
13077 cr_save_rtx = gen_rtx_REG (SImode, 0);
13078 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
13079 RTX_FRAME_RELATED_P (insn) = 1;
13080 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
13081 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13086 insn = emit_move_insn (mem, cr_save_rtx);
13088 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
13089 NULL_RTX, NULL_RTX);
13092 /* Update stack and set back pointer unless this is V.4,
13093 for which it was done previously. */
13094 if (!WORLD_SAVE_P (info) && info->push_p
13095 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
13096 rs6000_emit_allocate_stack (info->total_size, FALSE);
13098 /* Set frame pointer, if needed. */
13099 if (frame_pointer_needed)
13101 insn = emit_move_insn (gen_rtx_REG (Pmode, FRAME_POINTER_REGNUM),
13103 RTX_FRAME_RELATED_P (insn) = 1;
13106 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
13107 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
13108 || (DEFAULT_ABI == ABI_V4 && flag_pic == 1
13109 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
13111 /* If emit_load_toc_table will use the link register, we need to save
13112 it. We use R12 for this purpose because emit_load_toc_table
13113 can use register 0. This allows us to use a plain 'blr' to return
13114 from the procedure more often. */
13115 int save_LR_around_toc_setup = (TARGET_ELF
13116 && DEFAULT_ABI != ABI_AIX
13118 && ! info->lr_save_p
13119 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
13120 if (save_LR_around_toc_setup)
13122 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13124 insn = emit_move_insn (frame_ptr_rtx, lr);
13125 rs6000_maybe_dead (insn);
13126 RTX_FRAME_RELATED_P (insn) = 1;
13128 rs6000_emit_load_toc_table (TRUE);
13130 insn = emit_move_insn (lr, frame_ptr_rtx);
13131 rs6000_maybe_dead (insn);
13132 RTX_FRAME_RELATED_P (insn) = 1;
13135 rs6000_emit_load_toc_table (TRUE);
13139 if (DEFAULT_ABI == ABI_DARWIN
13140 && flag_pic && current_function_uses_pic_offset_table)
13142 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13143 rtx src = machopic_function_base_sym ();
13145 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
13147 insn = emit_move_insn (gen_rtx_REG (Pmode,
13148 RS6000_PIC_OFFSET_TABLE_REGNUM),
13150 rs6000_maybe_dead (insn);
13155 /* Write function prologue. */
13158 rs6000_output_function_prologue (FILE *file,
13159 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13161 rs6000_stack_t *info = rs6000_stack_info ();
13163 if (TARGET_DEBUG_STACK)
13164 debug_stack_info (info);
13166 /* Write .extern for any function we will call to save and restore
13168 if (info->first_fp_reg_save < 64
13169 && !FP_SAVE_INLINE (info->first_fp_reg_save))
13170 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
13171 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
13172 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
13173 RESTORE_FP_SUFFIX);
13175 /* Write .extern for AIX common mode routines, if needed. */
13176 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
13178 fputs ("\t.extern __mulh\n", file);
13179 fputs ("\t.extern __mull\n", file);
13180 fputs ("\t.extern __divss\n", file);
13181 fputs ("\t.extern __divus\n", file);
13182 fputs ("\t.extern __quoss\n", file);
13183 fputs ("\t.extern __quous\n", file);
13184 common_mode_defined = 1;
13187 if (! HAVE_prologue)
13191 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
13192 the "toplevel" insn chain. */
13193 emit_note (NOTE_INSN_DELETED);
13194 rs6000_emit_prologue ();
13195 emit_note (NOTE_INSN_DELETED);
13197 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13201 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13203 INSN_ADDRESSES_NEW (insn, addr);
13208 if (TARGET_DEBUG_STACK)
13209 debug_rtx_list (get_insns (), 100);
13210 final (get_insns (), file, FALSE, FALSE);
13214 rs6000_pic_labelno++;
13217 /* Emit function epilogue as insns.
13219 At present, dwarf2out_frame_debug_expr doesn't understand
13220 register restores, so we don't bother setting RTX_FRAME_RELATED_P
13221 anywhere in the epilogue. Most of the insns below would in any case
13222 need special notes to explain where r11 is in relation to the stack. */
13225 rs6000_emit_epilogue (int sibcall)
13227 rs6000_stack_t *info;
13228 int restoring_FPRs_inline;
13229 int using_load_multiple;
13230 int using_mfcr_multiple;
13231 int use_backchain_to_restore_sp;
13233 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
13234 rtx frame_reg_rtx = sp_reg_rtx;
13235 enum machine_mode reg_mode = Pmode;
13236 int reg_size = TARGET_32BIT ? 4 : 8;
13239 info = rs6000_stack_info ();
13241 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13243 reg_mode = V2SImode;
13247 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13248 && (!TARGET_SPE_ABI
13249 || info->spe_64bit_regs_used == 0)
13250 && info->first_gp_reg_save < 31);
13251 restoring_FPRs_inline = (sibcall
13252 || current_function_calls_eh_return
13253 || info->first_fp_reg_save == 64
13254 || FP_SAVE_INLINE (info->first_fp_reg_save));
13255 use_backchain_to_restore_sp = (frame_pointer_needed
13256 || current_function_calls_alloca
13257 || info->total_size > 32767);
13258 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
13259 || rs6000_cpu == PROCESSOR_PPC603
13260 || rs6000_cpu == PROCESSOR_PPC750
13263 if (WORLD_SAVE_P (info))
13267 const char *alloc_rname;
13270 /* eh_rest_world_r10 will return to the location saved in the LR
13271 stack slot (which is not likely to be our caller.)
13272 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
13273 rest_world is similar, except any R10 parameter is ignored.
13274 The exception-handling stuff that was here in 2.95 is no
13275 longer necessary. */
13279 + 32 - info->first_gp_reg_save
13280 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
13281 + 63 + 1 - info->first_fp_reg_save);
13283 strcpy (rname, ((current_function_calls_eh_return) ?
13284 "*eh_rest_world_r10" : "*rest_world"));
13285 alloc_rname = ggc_strdup (rname);
13288 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
13289 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
13290 gen_rtx_REG (Pmode,
13291 LINK_REGISTER_REGNUM));
13293 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
13294 /* The instruction pattern requires a clobber here;
13295 it is shared with the restVEC helper. */
13297 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
13300 /* CR register traditionally saved as CR2. */
13301 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
13302 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13303 GEN_INT (info->cr_save_offset));
13304 rtx mem = gen_rtx_MEM (reg_mode, addr);
13305 set_mem_alias_set (mem, rs6000_sr_alias_set);
13307 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13310 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13312 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
13313 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13314 GEN_INT (info->gp_save_offset
13316 rtx mem = gen_rtx_MEM (reg_mode, addr);
13317 set_mem_alias_set (mem, rs6000_sr_alias_set);
13319 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13321 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
13323 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
13324 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13325 GEN_INT (info->altivec_save_offset
13327 rtx mem = gen_rtx_MEM (V4SImode, addr);
13328 set_mem_alias_set (mem, rs6000_sr_alias_set);
13330 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13332 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
13334 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
13335 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13336 GEN_INT (info->fp_save_offset
13338 rtx mem = gen_rtx_MEM (DFmode, addr);
13339 set_mem_alias_set (mem, rs6000_sr_alias_set);
13341 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
13344 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
13346 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
13348 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
13350 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
13352 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
13353 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13358 /* If we have a frame pointer, a call to alloca, or a large stack
13359 frame, restore the old stack pointer using the backchain. Otherwise,
13360 we know what size to update it with. */
13361 if (use_backchain_to_restore_sp)
13363 /* Under V.4, don't reset the stack pointer until after we're done
13364 loading the saved registers. */
13365 if (DEFAULT_ABI == ABI_V4)
13366 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
13368 emit_move_insn (frame_reg_rtx,
13369 gen_rtx_MEM (Pmode, sp_reg_rtx));
13372 else if (info->push_p)
13374 if (DEFAULT_ABI == ABI_V4
13375 || current_function_calls_eh_return)
13376 sp_offset = info->total_size;
13379 emit_insn (TARGET_32BIT
13380 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13381 GEN_INT (info->total_size))
13382 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13383 GEN_INT (info->total_size)));
13387 /* Restore AltiVec registers if needed. */
13388 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
13392 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
13393 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13395 rtx addr, areg, mem;
13397 areg = gen_rtx_REG (Pmode, 0);
13399 (areg, GEN_INT (info->altivec_save_offset
13401 + 16 * (i - info->first_altivec_reg_save)));
13403 /* AltiVec addressing mode is [reg+reg]. */
13404 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
13405 mem = gen_rtx_MEM (V4SImode, addr);
13406 set_mem_alias_set (mem, rs6000_sr_alias_set);
13408 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
13412 /* Restore VRSAVE if needed. */
13413 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
13414 && info->vrsave_mask != 0)
13416 rtx addr, mem, reg;
13418 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13419 GEN_INT (info->vrsave_save_offset + sp_offset));
13420 mem = gen_rtx_MEM (SImode, addr);
13421 set_mem_alias_set (mem, rs6000_sr_alias_set);
13422 reg = gen_rtx_REG (SImode, 12);
13423 emit_move_insn (reg, mem);
13425 emit_insn (generate_set_vrsave (reg, info, 1));
13428 /* Get the old lr if we saved it. */
13429 if (info->lr_save_p)
13431 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
13432 info->lr_save_offset + sp_offset);
13434 set_mem_alias_set (mem, rs6000_sr_alias_set);
13436 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
13439 /* Get the old cr if we saved it. */
13440 if (info->cr_save_p)
13442 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13443 GEN_INT (info->cr_save_offset + sp_offset));
13444 rtx mem = gen_rtx_MEM (SImode, addr);
13446 set_mem_alias_set (mem, rs6000_sr_alias_set);
13448 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
13451 /* Set LR here to try to overlap restores below. */
13452 if (info->lr_save_p)
13453 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
13454 gen_rtx_REG (Pmode, 0));
13456 /* Load exception handler data registers, if needed. */
13457 if (current_function_calls_eh_return)
13459 unsigned int i, regno;
13463 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13464 GEN_INT (sp_offset + 5 * reg_size));
13465 rtx mem = gen_rtx_MEM (reg_mode, addr);
13467 set_mem_alias_set (mem, rs6000_sr_alias_set);
13469 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
13476 regno = EH_RETURN_DATA_REGNO (i);
13477 if (regno == INVALID_REGNUM)
13480 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
13481 info->ehrd_offset + sp_offset
13482 + reg_size * (int) i);
13483 set_mem_alias_set (mem, rs6000_sr_alias_set);
13485 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
13489 /* Restore GPRs. This is done as a PARALLEL if we are using
13490 the load-multiple instructions. */
13491 if (using_load_multiple)
13494 p = rtvec_alloc (32 - info->first_gp_reg_save);
13495 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13497 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13498 GEN_INT (info->gp_save_offset
13501 rtx mem = gen_rtx_MEM (reg_mode, addr);
13503 set_mem_alias_set (mem, rs6000_sr_alias_set);
13506 gen_rtx_SET (VOIDmode,
13507 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
13510 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13513 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
13514 if ((regs_ever_live[info->first_gp_reg_save+i]
13515 && (! call_used_regs[info->first_gp_reg_save+i]
13516 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13517 && TARGET_TOC && TARGET_MINIMAL_TOC)))
13518 || (i+info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
13519 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13520 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
13522 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13523 GEN_INT (info->gp_save_offset
13526 rtx mem = gen_rtx_MEM (reg_mode, addr);
13528 /* Restore 64-bit quantities for SPE. */
13529 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13531 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
13534 if (!SPE_CONST_OFFSET_OK (offset))
13536 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13537 emit_move_insn (b, GEN_INT (offset));
13540 b = GEN_INT (offset);
13542 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
13543 mem = gen_rtx_MEM (V2SImode, addr);
13546 set_mem_alias_set (mem, rs6000_sr_alias_set);
13548 emit_move_insn (gen_rtx_REG (reg_mode,
13549 info->first_gp_reg_save + i), mem);
13552 /* Restore fpr's if we need to do it without calling a function. */
13553 if (restoring_FPRs_inline)
13554 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13555 if ((regs_ever_live[info->first_fp_reg_save+i]
13556 && ! call_used_regs[info->first_fp_reg_save+i]))
13559 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
13560 GEN_INT (info->fp_save_offset
13563 mem = gen_rtx_MEM (DFmode, addr);
13564 set_mem_alias_set (mem, rs6000_sr_alias_set);
13566 emit_move_insn (gen_rtx_REG (DFmode,
13567 info->first_fp_reg_save + i),
13571 /* If we saved cr, restore it here. Just those that were used. */
13572 if (info->cr_save_p)
13574 rtx r12_rtx = gen_rtx_REG (SImode, 12);
13577 if (using_mfcr_multiple)
13579 for (i = 0; i < 8; i++)
13580 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13586 if (using_mfcr_multiple && count > 1)
13591 p = rtvec_alloc (count);
13594 for (i = 0; i < 8; i++)
13595 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13597 rtvec r = rtvec_alloc (2);
13598 RTVEC_ELT (r, 0) = r12_rtx;
13599 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
13600 RTVEC_ELT (p, ndx) =
13601 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
13602 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
13605 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
13610 for (i = 0; i < 8; i++)
13611 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
13613 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
13619 /* If this is V.4, unwind the stack pointer after all of the loads
13620 have been done. We need to emit a block here so that sched
13621 doesn't decide to move the sp change before the register restores
13622 (which may not have any obvious dependency on the stack). This
13623 doesn't hurt performance, because there is no scheduling that can
13624 be done after this point. */
13625 if (DEFAULT_ABI == ABI_V4
13626 || current_function_calls_eh_return)
13628 if (frame_reg_rtx != sp_reg_rtx)
13629 rs6000_emit_stack_tie ();
13631 if (use_backchain_to_restore_sp)
13633 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
13635 else if (sp_offset != 0)
13637 emit_insn (TARGET_32BIT
13638 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
13639 GEN_INT (sp_offset))
13640 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
13641 GEN_INT (sp_offset)));
13645 if (current_function_calls_eh_return)
13647 rtx sa = EH_RETURN_STACKADJ_RTX;
13648 emit_insn (TARGET_32BIT
13649 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
13650 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
13656 if (! restoring_FPRs_inline)
13657 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
13659 p = rtvec_alloc (2);
13661 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
13662 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
13663 gen_rtx_REG (Pmode,
13664 LINK_REGISTER_REGNUM));
13666 /* If we have to restore more than two FP registers, branch to the
13667 restore function. It will return to our caller. */
13668 if (! restoring_FPRs_inline)
13672 const char *alloc_rname;
13674 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
13675 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
13676 alloc_rname = ggc_strdup (rname);
13677 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
13678 gen_rtx_SYMBOL_REF (Pmode,
13681 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
13684 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
13685 GEN_INT (info->fp_save_offset + 8*i));
13686 mem = gen_rtx_MEM (DFmode, addr);
13687 set_mem_alias_set (mem, rs6000_sr_alias_set);
13689 RTVEC_ELT (p, i+3) =
13690 gen_rtx_SET (VOIDmode,
13691 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
13696 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
13700 /* Write function epilogue. */
13703 rs6000_output_function_epilogue (FILE *file,
13704 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
13706 rs6000_stack_t *info = rs6000_stack_info ();
13708 if (! HAVE_epilogue)
13710 rtx insn = get_last_insn ();
13711 /* If the last insn was a BARRIER, we don't have to write anything except
13712 the trace table. */
13713 if (GET_CODE (insn) == NOTE)
13714 insn = prev_nonnote_insn (insn);
13715 if (insn == 0 || GET_CODE (insn) != BARRIER)
13717 /* This is slightly ugly, but at least we don't have two
13718 copies of the epilogue-emitting code. */
13721 /* A NOTE_INSN_DELETED is supposed to be at the start
13722 and end of the "toplevel" insn chain. */
13723 emit_note (NOTE_INSN_DELETED);
13724 rs6000_emit_epilogue (FALSE);
13725 emit_note (NOTE_INSN_DELETED);
13727 /* Expand INSN_ADDRESSES so final() doesn't crash. */
13731 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
13733 INSN_ADDRESSES_NEW (insn, addr);
13738 if (TARGET_DEBUG_STACK)
13739 debug_rtx_list (get_insns (), 100);
13740 final (get_insns (), file, FALSE, FALSE);
13746 macho_branch_islands ();
13747 /* Mach-O doesn't support labels at the end of objects, so if
13748 it looks like we might want one, insert a NOP. */
13750 rtx insn = get_last_insn ();
13753 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
13754 insn = PREV_INSN (insn);
13758 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
13759 fputs ("\tnop\n", file);
13763 /* Output a traceback table here. See /usr/include/sys/debug.h for info
13766 We don't output a traceback table if -finhibit-size-directive was
13767 used. The documentation for -finhibit-size-directive reads
13768 ``don't output a @code{.size} assembler directive, or anything
13769 else that would cause trouble if the function is split in the
13770 middle, and the two halves are placed at locations far apart in
13771 memory.'' The traceback table has this property, since it
13772 includes the offset from the start of the function to the
13773 traceback table itself.
13775 System V.4 Powerpc's (and the embedded ABI derived from it) use a
13776 different traceback table. */
13777 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
13778 && rs6000_traceback != traceback_none)
13780 const char *fname = NULL;
13781 const char *language_string = lang_hooks.name;
13782 int fixed_parms = 0, float_parms = 0, parm_info = 0;
13784 int optional_tbtab;
13786 if (rs6000_traceback == traceback_full)
13787 optional_tbtab = 1;
13788 else if (rs6000_traceback == traceback_part)
13789 optional_tbtab = 0;
13791 optional_tbtab = !optimize_size && !TARGET_ELF;
13793 if (optional_tbtab)
13795 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
13796 while (*fname == '.') /* V.4 encodes . in the name */
13799 /* Need label immediately before tbtab, so we can compute
13800 its offset from the function start. */
13801 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13802 ASM_OUTPUT_LABEL (file, fname);
13805 /* The .tbtab pseudo-op can only be used for the first eight
13806 expressions, since it can't handle the possibly variable
13807 length fields that follow. However, if you omit the optional
13808 fields, the assembler outputs zeros for all optional fields
13809 anyways, giving each variable length field is minimum length
13810 (as defined in sys/debug.h). Thus we can not use the .tbtab
13811 pseudo-op at all. */
13813 /* An all-zero word flags the start of the tbtab, for debuggers
13814 that have to find it by searching forward from the entry
13815 point or from the current pc. */
13816 fputs ("\t.long 0\n", file);
13818 /* Tbtab format type. Use format type 0. */
13819 fputs ("\t.byte 0,", file);
13821 /* Language type. Unfortunately, there does not seem to be any
13822 official way to discover the language being compiled, so we
13823 use language_string.
13824 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
13825 Java is 13. Objective-C is 14. */
13826 if (! strcmp (language_string, "GNU C"))
13828 else if (! strcmp (language_string, "GNU F77")
13829 || ! strcmp (language_string, "GNU F95"))
13831 else if (! strcmp (language_string, "GNU Pascal"))
13833 else if (! strcmp (language_string, "GNU Ada"))
13835 else if (! strcmp (language_string, "GNU C++"))
13837 else if (! strcmp (language_string, "GNU Java"))
13839 else if (! strcmp (language_string, "GNU Objective-C"))
13843 fprintf (file, "%d,", i);
13845 /* 8 single bit fields: global linkage (not set for C extern linkage,
13846 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
13847 from start of procedure stored in tbtab, internal function, function
13848 has controlled storage, function has no toc, function uses fp,
13849 function logs/aborts fp operations. */
13850 /* Assume that fp operations are used if any fp reg must be saved. */
13851 fprintf (file, "%d,",
13852 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
13854 /* 6 bitfields: function is interrupt handler, name present in
13855 proc table, function calls alloca, on condition directives
13856 (controls stack walks, 3 bits), saves condition reg, saves
13858 /* The `function calls alloca' bit seems to be set whenever reg 31 is
13859 set up as a frame pointer, even when there is no alloca call. */
13860 fprintf (file, "%d,",
13861 ((optional_tbtab << 6)
13862 | ((optional_tbtab & frame_pointer_needed) << 5)
13863 | (info->cr_save_p << 1)
13864 | (info->lr_save_p)));
13866 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
13868 fprintf (file, "%d,",
13869 (info->push_p << 7) | (64 - info->first_fp_reg_save));
13871 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
13872 fprintf (file, "%d,", (32 - first_reg_to_save ()));
13874 if (optional_tbtab)
13876 /* Compute the parameter info from the function decl argument
13879 int next_parm_info_bit = 31;
13881 for (decl = DECL_ARGUMENTS (current_function_decl);
13882 decl; decl = TREE_CHAIN (decl))
13884 rtx parameter = DECL_INCOMING_RTL (decl);
13885 enum machine_mode mode = GET_MODE (parameter);
13887 if (GET_CODE (parameter) == REG)
13889 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
13895 if (mode == SFmode)
13897 else if (mode == DFmode || mode == TFmode)
13902 /* If only one bit will fit, don't or in this entry. */
13903 if (next_parm_info_bit > 0)
13904 parm_info |= (bits << (next_parm_info_bit - 1));
13905 next_parm_info_bit -= 2;
13909 fixed_parms += ((GET_MODE_SIZE (mode)
13910 + (UNITS_PER_WORD - 1))
13912 next_parm_info_bit -= 1;
13918 /* Number of fixed point parameters. */
13919 /* This is actually the number of words of fixed point parameters; thus
13920 an 8 byte struct counts as 2; and thus the maximum value is 8. */
13921 fprintf (file, "%d,", fixed_parms);
13923 /* 2 bitfields: number of floating point parameters (7 bits), parameters
13925 /* This is actually the number of fp registers that hold parameters;
13926 and thus the maximum value is 13. */
13927 /* Set parameters on stack bit if parameters are not in their original
13928 registers, regardless of whether they are on the stack? Xlc
13929 seems to set the bit when not optimizing. */
13930 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
13932 if (! optional_tbtab)
13935 /* Optional fields follow. Some are variable length. */
13937 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
13938 11 double float. */
13939 /* There is an entry for each parameter in a register, in the order that
13940 they occur in the parameter list. Any intervening arguments on the
13941 stack are ignored. If the list overflows a long (max possible length
13942 34 bits) then completely leave off all elements that don't fit. */
13943 /* Only emit this long if there was at least one parameter. */
13944 if (fixed_parms || float_parms)
13945 fprintf (file, "\t.long %d\n", parm_info);
13947 /* Offset from start of code to tb table. */
13948 fputs ("\t.long ", file);
13949 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
13951 RS6000_OUTPUT_BASENAME (file, fname);
13953 assemble_name (file, fname);
13955 rs6000_output_function_entry (file, fname);
13958 /* Interrupt handler mask. */
13959 /* Omit this long, since we never set the interrupt handler bit
13962 /* Number of CTL (controlled storage) anchors. */
13963 /* Omit this long, since the has_ctl bit is never set above. */
13965 /* Displacement into stack of each CTL anchor. */
13966 /* Omit this list of longs, because there are no CTL anchors. */
13968 /* Length of function name. */
13971 fprintf (file, "\t.short %d\n", (int) strlen (fname));
13973 /* Function name. */
13974 assemble_string (fname, strlen (fname));
13976 /* Register for alloca automatic storage; this is always reg 31.
13977 Only emit this if the alloca bit was set above. */
13978 if (frame_pointer_needed)
13979 fputs ("\t.byte 31\n", file);
13981 fputs ("\t.align 2\n", file);
13985 /* A C compound statement that outputs the assembler code for a thunk
13986 function, used to implement C++ virtual function calls with
13987 multiple inheritance. The thunk acts as a wrapper around a virtual
13988 function, adjusting the implicit object parameter before handing
13989 control off to the real function.
13991 First, emit code to add the integer DELTA to the location that
13992 contains the incoming first argument. Assume that this argument
13993 contains a pointer, and is the one used to pass the `this' pointer
13994 in C++. This is the incoming argument *before* the function
13995 prologue, e.g. `%o0' on a sparc. The addition must preserve the
13996 values of all other incoming arguments.
13998 After the addition, emit code to jump to FUNCTION, which is a
13999 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
14000 not touch the return address. Hence returning from FUNCTION will
14001 return to whoever called the current `thunk'.
14003 The effect must be as if FUNCTION had been called directly with the
14004 adjusted first argument. This macro is responsible for emitting
14005 all of the code for a thunk function; output_function_prologue()
14006 and output_function_epilogue() are not invoked.
14008 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
14009 been extracted from it.) It might possibly be useful on some
14010 targets, but probably not.
14012 If you do not define this macro, the target-independent code in the
14013 C++ frontend will generate a less efficient heavyweight thunk that
14014 calls FUNCTION instead of jumping to it. The generic approach does
14015 not support varargs. */
14018 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
14019 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
14022 rtx this, insn, funexp;
14024 reload_completed = 1;
14025 epilogue_completed = 1;
14026 no_new_pseudos = 1;
14027 reset_block_changes ();
14029 /* Mark the end of the (empty) prologue. */
14030 emit_note (NOTE_INSN_PROLOGUE_END);
14032 /* Find the "this" pointer. If the function returns a structure,
14033 the structure return pointer is in r3. */
14034 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
14035 this = gen_rtx_REG (Pmode, 4);
14037 this = gen_rtx_REG (Pmode, 3);
14039 /* Apply the constant offset, if required. */
14042 rtx delta_rtx = GEN_INT (delta);
14043 emit_insn (TARGET_32BIT
14044 ? gen_addsi3 (this, this, delta_rtx)
14045 : gen_adddi3 (this, this, delta_rtx));
14048 /* Apply the offset from the vtable, if required. */
14051 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
14052 rtx tmp = gen_rtx_REG (Pmode, 12);
14054 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
14055 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
14057 emit_insn (TARGET_32BIT
14058 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
14059 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
14060 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
14064 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
14066 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
14068 emit_insn (TARGET_32BIT
14069 ? gen_addsi3 (this, this, tmp)
14070 : gen_adddi3 (this, this, tmp));
14073 /* Generate a tail call to the target function. */
14074 if (!TREE_USED (function))
14076 assemble_external (function);
14077 TREE_USED (function) = 1;
14079 funexp = XEXP (DECL_RTL (function), 0);
14080 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
14083 if (MACHOPIC_INDIRECT)
14084 funexp = machopic_indirect_call_target (funexp);
14087 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
14088 generate sibcall RTL explicitly to avoid constraint abort. */
14089 insn = emit_call_insn (
14090 gen_rtx_PARALLEL (VOIDmode,
14092 gen_rtx_CALL (VOIDmode,
14093 funexp, const0_rtx),
14094 gen_rtx_USE (VOIDmode, const0_rtx),
14095 gen_rtx_USE (VOIDmode,
14096 gen_rtx_REG (SImode,
14097 LINK_REGISTER_REGNUM)),
14098 gen_rtx_RETURN (VOIDmode))));
14099 SIBLING_CALL_P (insn) = 1;
14102 /* Run just enough of rest_of_compilation to get the insns emitted.
14103 There's not really enough bulk here to make other passes such as
14104 instruction scheduling worth while. Note that use_thunk calls
14105 assemble_start_function and assemble_end_function. */
14106 insn = get_insns ();
14107 insn_locators_initialize ();
14108 shorten_branches (insn);
14109 final_start_function (insn, file, 1);
14110 final (insn, file, 1, 0);
14111 final_end_function ();
14113 reload_completed = 0;
14114 epilogue_completed = 0;
14115 no_new_pseudos = 0;
14118 /* A quick summary of the various types of 'constant-pool tables'
14121 Target Flags Name One table per
14122 AIX (none) AIX TOC object file
14123 AIX -mfull-toc AIX TOC object file
14124 AIX -mminimal-toc AIX minimal TOC translation unit
14125 SVR4/EABI (none) SVR4 SDATA object file
14126 SVR4/EABI -fpic SVR4 pic object file
14127 SVR4/EABI -fPIC SVR4 PIC translation unit
14128 SVR4/EABI -mrelocatable EABI TOC function
14129 SVR4/EABI -maix AIX TOC object file
14130 SVR4/EABI -maix -mminimal-toc
14131 AIX minimal TOC translation unit
14133 Name Reg. Set by entries contains:
14134 made by addrs? fp? sum?
14136 AIX TOC 2 crt0 as Y option option
14137 AIX minimal TOC 30 prolog gcc Y Y option
14138 SVR4 SDATA 13 crt0 gcc N Y N
14139 SVR4 pic 30 prolog ld Y not yet N
14140 SVR4 PIC 30 prolog gcc Y option option
14141 EABI TOC 30 prolog gcc Y option option
14145 /* Hash functions for the hash table. */
14148 rs6000_hash_constant (rtx k)
14150 enum rtx_code code = GET_CODE (k);
14151 enum machine_mode mode = GET_MODE (k);
14152 unsigned result = (code << 3) ^ mode;
14153 const char *format;
14156 format = GET_RTX_FORMAT (code);
14157 flen = strlen (format);
14163 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
14166 if (mode != VOIDmode)
14167 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
14179 for (; fidx < flen; fidx++)
14180 switch (format[fidx])
14185 const char *str = XSTR (k, fidx);
14186 len = strlen (str);
14187 result = result * 613 + len;
14188 for (i = 0; i < len; i++)
14189 result = result * 613 + (unsigned) str[i];
14194 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
14198 result = result * 613 + (unsigned) XINT (k, fidx);
14201 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
14202 result = result * 613 + (unsigned) XWINT (k, fidx);
14206 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
14207 result = result * 613 + (unsigned) (XWINT (k, fidx)
14221 toc_hash_function (const void *hash_entry)
14223 const struct toc_hash_struct *thc =
14224 (const struct toc_hash_struct *) hash_entry;
14225 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
14228 /* Compare H1 and H2 for equivalence. */
14231 toc_hash_eq (const void *h1, const void *h2)
14233 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
14234 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
14236 if (((const struct toc_hash_struct *) h1)->key_mode
14237 != ((const struct toc_hash_struct *) h2)->key_mode)
14240 return rtx_equal_p (r1, r2);
14243 /* These are the names given by the C++ front-end to vtables, and
14244 vtable-like objects. Ideally, this logic should not be here;
14245 instead, there should be some programmatic way of inquiring as
14246 to whether or not an object is a vtable. */
14248 #define VTABLE_NAME_P(NAME) \
14249 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
14250 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
14251 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
14252 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
14253 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
14256 rs6000_output_symbol_ref (FILE *file, rtx x)
14258 /* Currently C++ toc references to vtables can be emitted before it
14259 is decided whether the vtable is public or private. If this is
14260 the case, then the linker will eventually complain that there is
14261 a reference to an unknown section. Thus, for vtables only,
14262 we emit the TOC reference to reference the symbol and not the
14264 const char *name = XSTR (x, 0);
14266 if (VTABLE_NAME_P (name))
14268 RS6000_OUTPUT_BASENAME (file, name);
14271 assemble_name (file, name);
14274 /* Output a TOC entry. We derive the entry name from what is being
14278 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
14281 const char *name = buf;
14282 const char *real_name;
14289 /* When the linker won't eliminate them, don't output duplicate
14290 TOC entries (this happens on AIX if there is any kind of TOC,
14291 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
14293 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
14295 struct toc_hash_struct *h;
14298 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
14299 time because GGC is not initialized at that point. */
14300 if (toc_hash_table == NULL)
14301 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
14302 toc_hash_eq, NULL);
14304 h = ggc_alloc (sizeof (*h));
14306 h->key_mode = mode;
14307 h->labelno = labelno;
14309 found = htab_find_slot (toc_hash_table, h, 1);
14310 if (*found == NULL)
14312 else /* This is indeed a duplicate.
14313 Set this label equal to that label. */
14315 fputs ("\t.set ", file);
14316 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14317 fprintf (file, "%d,", labelno);
14318 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
14319 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
14325 /* If we're going to put a double constant in the TOC, make sure it's
14326 aligned properly when strict alignment is on. */
14327 if (GET_CODE (x) == CONST_DOUBLE
14328 && STRICT_ALIGNMENT
14329 && GET_MODE_BITSIZE (mode) >= 64
14330 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
14331 ASM_OUTPUT_ALIGN (file, 3);
14334 (*targetm.asm_out.internal_label) (file, "LC", labelno);
14336 /* Handle FP constants specially. Note that if we have a minimal
14337 TOC, things we put here aren't actually in the TOC, so we can allow
14339 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
14341 REAL_VALUE_TYPE rv;
14344 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14345 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
14349 if (TARGET_MINIMAL_TOC)
14350 fputs (DOUBLE_INT_ASM_OP, file);
14352 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14353 k[0] & 0xffffffff, k[1] & 0xffffffff,
14354 k[2] & 0xffffffff, k[3] & 0xffffffff);
14355 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
14356 k[0] & 0xffffffff, k[1] & 0xffffffff,
14357 k[2] & 0xffffffff, k[3] & 0xffffffff);
14362 if (TARGET_MINIMAL_TOC)
14363 fputs ("\t.long ", file);
14365 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
14366 k[0] & 0xffffffff, k[1] & 0xffffffff,
14367 k[2] & 0xffffffff, k[3] & 0xffffffff);
14368 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
14369 k[0] & 0xffffffff, k[1] & 0xffffffff,
14370 k[2] & 0xffffffff, k[3] & 0xffffffff);
14374 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
14376 REAL_VALUE_TYPE rv;
14379 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14380 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
14384 if (TARGET_MINIMAL_TOC)
14385 fputs (DOUBLE_INT_ASM_OP, file);
14387 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14388 k[0] & 0xffffffff, k[1] & 0xffffffff);
14389 fprintf (file, "0x%lx%08lx\n",
14390 k[0] & 0xffffffff, k[1] & 0xffffffff);
14395 if (TARGET_MINIMAL_TOC)
14396 fputs ("\t.long ", file);
14398 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
14399 k[0] & 0xffffffff, k[1] & 0xffffffff);
14400 fprintf (file, "0x%lx,0x%lx\n",
14401 k[0] & 0xffffffff, k[1] & 0xffffffff);
14405 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
14407 REAL_VALUE_TYPE rv;
14410 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
14411 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
14415 if (TARGET_MINIMAL_TOC)
14416 fputs (DOUBLE_INT_ASM_OP, file);
14418 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14419 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
14424 if (TARGET_MINIMAL_TOC)
14425 fputs ("\t.long ", file);
14427 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
14428 fprintf (file, "0x%lx\n", l & 0xffffffff);
14432 else if (GET_MODE (x) == VOIDmode
14433 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
14435 unsigned HOST_WIDE_INT low;
14436 HOST_WIDE_INT high;
14438 if (GET_CODE (x) == CONST_DOUBLE)
14440 low = CONST_DOUBLE_LOW (x);
14441 high = CONST_DOUBLE_HIGH (x);
14444 #if HOST_BITS_PER_WIDE_INT == 32
14447 high = (low & 0x80000000) ? ~0 : 0;
14451 low = INTVAL (x) & 0xffffffff;
14452 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
14456 /* TOC entries are always Pmode-sized, but since this
14457 is a bigendian machine then if we're putting smaller
14458 integer constants in the TOC we have to pad them.
14459 (This is still a win over putting the constants in
14460 a separate constant pool, because then we'd have
14461 to have both a TOC entry _and_ the actual constant.)
14463 For a 32-bit target, CONST_INT values are loaded and shifted
14464 entirely within `low' and can be stored in one TOC entry. */
14466 if (TARGET_64BIT && POINTER_SIZE < GET_MODE_BITSIZE (mode))
14467 abort ();/* It would be easy to make this work, but it doesn't now. */
14469 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
14471 #if HOST_BITS_PER_WIDE_INT == 32
14472 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
14473 POINTER_SIZE, &low, &high, 0);
14476 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
14477 high = (HOST_WIDE_INT) low >> 32;
14484 if (TARGET_MINIMAL_TOC)
14485 fputs (DOUBLE_INT_ASM_OP, file);
14487 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14488 (long) high & 0xffffffff, (long) low & 0xffffffff);
14489 fprintf (file, "0x%lx%08lx\n",
14490 (long) high & 0xffffffff, (long) low & 0xffffffff);
14495 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
14497 if (TARGET_MINIMAL_TOC)
14498 fputs ("\t.long ", file);
14500 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
14501 (long) high & 0xffffffff, (long) low & 0xffffffff);
14502 fprintf (file, "0x%lx,0x%lx\n",
14503 (long) high & 0xffffffff, (long) low & 0xffffffff);
14507 if (TARGET_MINIMAL_TOC)
14508 fputs ("\t.long ", file);
14510 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
14511 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
14517 if (GET_CODE (x) == CONST)
14519 if (GET_CODE (XEXP (x, 0)) != PLUS)
14522 base = XEXP (XEXP (x, 0), 0);
14523 offset = INTVAL (XEXP (XEXP (x, 0), 1));
14526 if (GET_CODE (base) == SYMBOL_REF)
14527 name = XSTR (base, 0);
14528 else if (GET_CODE (base) == LABEL_REF)
14529 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (base, 0)));
14530 else if (GET_CODE (base) == CODE_LABEL)
14531 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
14535 real_name = (*targetm.strip_name_encoding) (name);
14536 if (TARGET_MINIMAL_TOC)
14537 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
14540 fprintf (file, "\t.tc %s", real_name);
14543 fprintf (file, ".N%d", - offset);
14545 fprintf (file, ".P%d", offset);
14547 fputs ("[TC],", file);
14550 /* Currently C++ toc references to vtables can be emitted before it
14551 is decided whether the vtable is public or private. If this is
14552 the case, then the linker will eventually complain that there is
14553 a TOC reference to an unknown section. Thus, for vtables only,
14554 we emit the TOC reference to reference the symbol and not the
14556 if (VTABLE_NAME_P (name))
14558 RS6000_OUTPUT_BASENAME (file, name);
14560 fprintf (file, "%d", offset);
14561 else if (offset > 0)
14562 fprintf (file, "+%d", offset);
14565 output_addr_const (file, x);
14569 /* Output an assembler pseudo-op to write an ASCII string of N characters
14570 starting at P to FILE.
14572 On the RS/6000, we have to do this using the .byte operation and
14573 write out special characters outside the quoted string.
14574 Also, the assembler is broken; very long strings are truncated,
14575 so we must artificially break them up early. */
14578 output_ascii (FILE *file, const char *p, int n)
14581 int i, count_string;
14582 const char *for_string = "\t.byte \"";
14583 const char *for_decimal = "\t.byte ";
14584 const char *to_close = NULL;
14587 for (i = 0; i < n; i++)
14590 if (c >= ' ' && c < 0177)
14593 fputs (for_string, file);
14596 /* Write two quotes to get one. */
14604 for_decimal = "\"\n\t.byte ";
14608 if (count_string >= 512)
14610 fputs (to_close, file);
14612 for_string = "\t.byte \"";
14613 for_decimal = "\t.byte ";
14621 fputs (for_decimal, file);
14622 fprintf (file, "%d", c);
14624 for_string = "\n\t.byte \"";
14625 for_decimal = ", ";
14631 /* Now close the string if we have written one. Then end the line. */
14633 fputs (to_close, file);
14636 /* Generate a unique section name for FILENAME for a section type
14637 represented by SECTION_DESC. Output goes into BUF.
14639 SECTION_DESC can be any string, as long as it is different for each
14640 possible section type.
14642 We name the section in the same manner as xlc. The name begins with an
14643 underscore followed by the filename (after stripping any leading directory
14644 names) with the last period replaced by the string SECTION_DESC. If
14645 FILENAME does not contain a period, SECTION_DESC is appended to the end of
14649 rs6000_gen_section_name (char **buf, const char *filename,
14650 const char *section_desc)
14652 const char *q, *after_last_slash, *last_period = 0;
14656 after_last_slash = filename;
14657 for (q = filename; *q; q++)
14660 after_last_slash = q + 1;
14661 else if (*q == '.')
14665 len = strlen (after_last_slash) + strlen (section_desc) + 2;
14666 *buf = (char *) xmalloc (len);
14671 for (q = after_last_slash; *q; q++)
14673 if (q == last_period)
14675 strcpy (p, section_desc);
14676 p += strlen (section_desc);
14680 else if (ISALNUM (*q))
14684 if (last_period == 0)
14685 strcpy (p, section_desc);
14690 /* Emit profile function. */
14693 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
14695 if (TARGET_PROFILE_KERNEL)
14698 if (DEFAULT_ABI == ABI_AIX)
14700 #ifndef NO_PROFILE_COUNTERS
14701 # define NO_PROFILE_COUNTERS 0
14703 if (NO_PROFILE_COUNTERS)
14704 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
14708 const char *label_name;
14711 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14712 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
14713 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
14715 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
14719 else if (DEFAULT_ABI == ABI_DARWIN)
14721 const char *mcount_name = RS6000_MCOUNT;
14722 int caller_addr_regno = LINK_REGISTER_REGNUM;
14724 /* Be conservative and always set this, at least for now. */
14725 current_function_uses_pic_offset_table = 1;
14728 /* For PIC code, set up a stub and collect the caller's address
14729 from r0, which is where the prologue puts it. */
14730 if (MACHOPIC_INDIRECT
14731 && current_function_uses_pic_offset_table)
14732 caller_addr_regno = 0;
14734 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
14736 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
14740 /* Write function profiler code. */
14743 output_function_profiler (FILE *file, int labelno)
14748 switch (DEFAULT_ABI)
14757 warning ("no profiling of 64-bit code for this ABI");
14760 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
14761 fprintf (file, "\tmflr %s\n", reg_names[0]);
14764 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
14765 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14766 reg_names[0], save_lr, reg_names[1]);
14767 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
14768 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
14769 assemble_name (file, buf);
14770 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
14772 else if (flag_pic > 1)
14774 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14775 reg_names[0], save_lr, reg_names[1]);
14776 /* Now, we need to get the address of the label. */
14777 fputs ("\tbl 1f\n\t.long ", file);
14778 assemble_name (file, buf);
14779 fputs ("-.\n1:", file);
14780 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
14781 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
14782 reg_names[0], reg_names[11]);
14783 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
14784 reg_names[0], reg_names[0], reg_names[11]);
14788 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
14789 assemble_name (file, buf);
14790 fputs ("@ha\n", file);
14791 asm_fprintf (file, "\t{st|stw} %s,%d(%s)\n",
14792 reg_names[0], save_lr, reg_names[1]);
14793 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
14794 assemble_name (file, buf);
14795 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
14798 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
14799 fprintf (file, "\tbl %s%s\n",
14800 RS6000_MCOUNT, flag_pic ? "@plt" : "");
14805 if (!TARGET_PROFILE_KERNEL)
14807 /* Don't do anything, done in output_profile_hook (). */
14814 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
14815 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
14817 if (cfun->static_chain_decl != NULL)
14819 asm_fprintf (file, "\tstd %s,24(%s)\n",
14820 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14821 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14822 asm_fprintf (file, "\tld %s,24(%s)\n",
14823 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
14826 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
14833 /* Power4 load update and store update instructions are cracked into a
14834 load or store and an integer insn which are executed in the same cycle.
14835 Branches have their own dispatch slot which does not count against the
14836 GCC issue rate, but it changes the program flow so there are no other
14837 instructions to issue in this cycle. */
14840 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
14841 int verbose ATTRIBUTE_UNUSED,
14842 rtx insn, int more)
14844 if (GET_CODE (PATTERN (insn)) == USE
14845 || GET_CODE (PATTERN (insn)) == CLOBBER)
14848 if (rs6000_sched_groups)
14850 if (is_microcoded_insn (insn))
14852 else if (is_cracked_insn (insn))
14853 return more > 2 ? more - 2 : 0;
14859 /* Adjust the cost of a scheduling dependency. Return the new cost of
14860 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
14863 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
14865 if (! recog_memoized (insn))
14868 if (REG_NOTE_KIND (link) != 0)
14871 if (REG_NOTE_KIND (link) == 0)
14873 /* Data dependency; DEP_INSN writes a register that INSN reads
14874 some cycles later. */
14876 /* Separate a load from a narrower, dependent store. */
14877 if (rs6000_sched_groups
14878 && GET_CODE (PATTERN (insn)) == SET
14879 && GET_CODE (PATTERN (dep_insn)) == SET
14880 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
14881 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
14882 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
14883 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
14886 switch (get_attr_type (insn))
14889 /* Tell the first scheduling pass about the latency between
14890 a mtctr and bctr (and mtlr and br/blr). The first
14891 scheduling pass will not know about this latency since
14892 the mtctr instruction, which has the latency associated
14893 to it, will be generated by reload. */
14894 return TARGET_POWER ? 5 : 4;
14896 /* Leave some extra cycles between a compare and its
14897 dependent branch, to inhibit expensive mispredicts. */
14898 if ((rs6000_cpu_attr == CPU_PPC603
14899 || rs6000_cpu_attr == CPU_PPC604
14900 || rs6000_cpu_attr == CPU_PPC604E
14901 || rs6000_cpu_attr == CPU_PPC620
14902 || rs6000_cpu_attr == CPU_PPC630
14903 || rs6000_cpu_attr == CPU_PPC750
14904 || rs6000_cpu_attr == CPU_PPC7400
14905 || rs6000_cpu_attr == CPU_PPC7450
14906 || rs6000_cpu_attr == CPU_POWER4
14907 || rs6000_cpu_attr == CPU_POWER5)
14908 && recog_memoized (dep_insn)
14909 && (INSN_CODE (dep_insn) >= 0)
14910 && (get_attr_type (dep_insn) == TYPE_CMP
14911 || get_attr_type (dep_insn) == TYPE_COMPARE
14912 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
14913 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
14914 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
14915 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
14916 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
14917 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
14922 /* Fall out to return default cost. */
14928 /* The function returns a true if INSN is microcoded.
14929 Return false otherwise. */
14932 is_microcoded_insn (rtx insn)
14934 if (!insn || !INSN_P (insn)
14935 || GET_CODE (PATTERN (insn)) == USE
14936 || GET_CODE (PATTERN (insn)) == CLOBBER)
14939 if (rs6000_sched_groups)
14941 enum attr_type type = get_attr_type (insn);
14942 if (type == TYPE_LOAD_EXT_U
14943 || type == TYPE_LOAD_EXT_UX
14944 || type == TYPE_LOAD_UX
14945 || type == TYPE_STORE_UX
14946 || type == TYPE_MFCR)
14953 /* The function returns a nonzero value if INSN can be scheduled only
14954 as the first insn in a dispatch group ("dispatch-slot restricted").
14955 In this case, the returned value indicates how many dispatch slots
14956 the insn occupies (at the beginning of the group).
14957 Return 0 otherwise. */
14960 is_dispatch_slot_restricted (rtx insn)
14962 enum attr_type type;
14964 if (!rs6000_sched_groups)
14968 || insn == NULL_RTX
14969 || GET_CODE (insn) == NOTE
14970 || GET_CODE (PATTERN (insn)) == USE
14971 || GET_CODE (PATTERN (insn)) == CLOBBER)
14974 type = get_attr_type (insn);
14981 case TYPE_DELAYED_CR:
14982 case TYPE_CR_LOGICAL:
14990 if (rs6000_cpu == PROCESSOR_POWER5
14991 && is_cracked_insn (insn))
14997 /* The function returns true if INSN is cracked into 2 instructions
14998 by the processor (and therefore occupies 2 issue slots). */
15001 is_cracked_insn (rtx insn)
15003 if (!insn || !INSN_P (insn)
15004 || GET_CODE (PATTERN (insn)) == USE
15005 || GET_CODE (PATTERN (insn)) == CLOBBER)
15008 if (rs6000_sched_groups)
15010 enum attr_type type = get_attr_type (insn);
15011 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
15012 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
15013 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
15014 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
15015 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
15016 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
15017 || type == TYPE_IDIV || type == TYPE_LDIV
15018 || type == TYPE_INSERT_WORD)
15025 /* The function returns true if INSN can be issued only from
15026 the branch slot. */
15029 is_branch_slot_insn (rtx insn)
15031 if (!insn || !INSN_P (insn)
15032 || GET_CODE (PATTERN (insn)) == USE
15033 || GET_CODE (PATTERN (insn)) == CLOBBER)
15036 if (rs6000_sched_groups)
15038 enum attr_type type = get_attr_type (insn);
15039 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
15047 /* A C statement (sans semicolon) to update the integer scheduling
15048 priority INSN_PRIORITY (INSN). Increase the priority to execute the
15049 INSN earlier, reduce the priority to execute INSN later. Do not
15050 define this macro if you do not need to adjust the scheduling
15051 priorities of insns. */
15054 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
15056 /* On machines (like the 750) which have asymmetric integer units,
15057 where one integer unit can do multiply and divides and the other
15058 can't, reduce the priority of multiply/divide so it is scheduled
15059 before other integer operations. */
15062 if (! INSN_P (insn))
15065 if (GET_CODE (PATTERN (insn)) == USE)
15068 switch (rs6000_cpu_attr) {
15070 switch (get_attr_type (insn))
15077 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
15078 priority, priority);
15079 if (priority >= 0 && priority < 0x01000000)
15086 if (is_dispatch_slot_restricted (insn)
15087 && reload_completed
15088 && current_sched_info->sched_max_insns_priority
15089 && rs6000_sched_restricted_insns_priority)
15092 /* Prioritize insns that can be dispatched only in the first
15094 if (rs6000_sched_restricted_insns_priority == 1)
15095 /* Attach highest priority to insn. This means that in
15096 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
15097 precede 'priority' (critical path) considerations. */
15098 return current_sched_info->sched_max_insns_priority;
15099 else if (rs6000_sched_restricted_insns_priority == 2)
15100 /* Increase priority of insn by a minimal amount. This means that in
15101 haifa-sched.c:ready_sort(), only 'priority' (critical path)
15102 considerations precede dispatch-slot restriction considerations. */
15103 return (priority + 1);
15109 /* Return how many instructions the machine can issue per cycle. */
15112 rs6000_issue_rate (void)
15114 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
15115 if (!reload_completed)
15118 switch (rs6000_cpu_attr) {
15119 case CPU_RIOS1: /* ? */
15121 case CPU_PPC601: /* ? */
15144 /* Return how many instructions to look ahead for better insn
15148 rs6000_use_sched_lookahead (void)
15150 if (rs6000_cpu_attr == CPU_PPC8540)
15155 /* Determine is PAT refers to memory. */
15158 is_mem_ref (rtx pat)
15164 if (GET_CODE (pat) == MEM)
15167 /* Recursively process the pattern. */
15168 fmt = GET_RTX_FORMAT (GET_CODE (pat));
15170 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
15173 ret |= is_mem_ref (XEXP (pat, i));
15174 else if (fmt[i] == 'E')
15175 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
15176 ret |= is_mem_ref (XVECEXP (pat, i, j));
15182 /* Determine if PAT is a PATTERN of a load insn. */
15185 is_load_insn1 (rtx pat)
15187 if (!pat || pat == NULL_RTX)
15190 if (GET_CODE (pat) == SET)
15191 return is_mem_ref (SET_SRC (pat));
15193 if (GET_CODE (pat) == PARALLEL)
15197 for (i = 0; i < XVECLEN (pat, 0); i++)
15198 if (is_load_insn1 (XVECEXP (pat, 0, i)))
15205 /* Determine if INSN loads from memory. */
15208 is_load_insn (rtx insn)
15210 if (!insn || !INSN_P (insn))
15213 if (GET_CODE (insn) == CALL_INSN)
15216 return is_load_insn1 (PATTERN (insn));
15219 /* Determine if PAT is a PATTERN of a store insn. */
15222 is_store_insn1 (rtx pat)
15224 if (!pat || pat == NULL_RTX)
15227 if (GET_CODE (pat) == SET)
15228 return is_mem_ref (SET_DEST (pat));
15230 if (GET_CODE (pat) == PARALLEL)
15234 for (i = 0; i < XVECLEN (pat, 0); i++)
15235 if (is_store_insn1 (XVECEXP (pat, 0, i)))
15242 /* Determine if INSN stores to memory. */
15245 is_store_insn (rtx insn)
15247 if (!insn || !INSN_P (insn))
15250 return is_store_insn1 (PATTERN (insn));
15253 /* Returns whether the dependence between INSN and NEXT is considered
15254 costly by the given target. */
15257 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
15260 /* If the flag is not enbled - no dependence is considered costly;
15261 allow all dependent insns in the same group.
15262 This is the most aggressive option. */
15263 if (rs6000_sched_costly_dep == no_dep_costly)
15266 /* If the flag is set to 1 - a dependence is always considered costly;
15267 do not allow dependent instructions in the same group.
15268 This is the most conservative option. */
15269 if (rs6000_sched_costly_dep == all_deps_costly)
15272 if (rs6000_sched_costly_dep == store_to_load_dep_costly
15273 && is_load_insn (next)
15274 && is_store_insn (insn))
15275 /* Prevent load after store in the same group. */
15278 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
15279 && is_load_insn (next)
15280 && is_store_insn (insn)
15281 && (!link || (int) REG_NOTE_KIND (link) == 0))
15282 /* Prevent load after store in the same group if it is a true
15286 /* The flag is set to X; dependences with latency >= X are considered costly,
15287 and will not be scheduled in the same group. */
15288 if (rs6000_sched_costly_dep <= max_dep_latency
15289 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
15295 /* Return the next insn after INSN that is found before TAIL is reached,
15296 skipping any "non-active" insns - insns that will not actually occupy
15297 an issue slot. Return NULL_RTX if such an insn is not found. */
15300 get_next_active_insn (rtx insn, rtx tail)
15304 if (!insn || insn == tail)
15307 next_insn = NEXT_INSN (insn);
15310 && next_insn != tail
15311 && (GET_CODE (next_insn) == NOTE
15312 || GET_CODE (PATTERN (next_insn)) == USE
15313 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
15315 next_insn = NEXT_INSN (next_insn);
15318 if (!next_insn || next_insn == tail)
15324 /* Return whether the presence of INSN causes a dispatch group termination
15325 of group WHICH_GROUP.
15327 If WHICH_GROUP == current_group, this function will return true if INSN
15328 causes the termination of the current group (i.e, the dispatch group to
15329 which INSN belongs). This means that INSN will be the last insn in the
15330 group it belongs to.
15332 If WHICH_GROUP == previous_group, this function will return true if INSN
15333 causes the termination of the previous group (i.e, the dispatch group that
15334 precedes the group to which INSN belongs). This means that INSN will be
15335 the first insn in the group it belongs to). */
15338 insn_terminates_group_p (rtx insn, enum group_termination which_group)
15340 enum attr_type type;
15345 type = get_attr_type (insn);
15347 if (is_microcoded_insn (insn))
15350 if (which_group == current_group)
15352 if (is_branch_slot_insn (insn))
15356 else if (which_group == previous_group)
15358 if (is_dispatch_slot_restricted (insn))
15366 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
15367 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
15370 is_costly_group (rtx *group_insns, rtx next_insn)
15375 int issue_rate = rs6000_issue_rate ();
15377 for (i = 0; i < issue_rate; i++)
15379 rtx insn = group_insns[i];
15382 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
15384 rtx next = XEXP (link, 0);
15385 if (next == next_insn)
15387 cost = insn_cost (insn, link, next_insn);
15388 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
15397 /* Utility of the function redefine_groups.
15398 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
15399 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
15400 to keep it "far" (in a separate group) from GROUP_INSNS, following
15401 one of the following schemes, depending on the value of the flag
15402 -minsert_sched_nops = X:
15403 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
15404 in order to force NEXT_INSN into a separate group.
15405 (2) X < sched_finish_regroup_exact: insert exactly X nops.
15406 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
15407 insertion (has a group just ended, how many vacant issue slots remain in the
15408 last group, and how many dispatch groups were encountered so far). */
15411 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
15412 rtx next_insn, bool *group_end, int can_issue_more,
15417 int issue_rate = rs6000_issue_rate ();
15418 bool end = *group_end;
15421 if (next_insn == NULL_RTX)
15422 return can_issue_more;
15424 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
15425 return can_issue_more;
15427 force = is_costly_group (group_insns, next_insn);
15429 return can_issue_more;
15431 if (sched_verbose > 6)
15432 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
15433 *group_count ,can_issue_more);
15435 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
15438 can_issue_more = 0;
15440 /* Since only a branch can be issued in the last issue_slot, it is
15441 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
15442 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
15443 in this case the last nop will start a new group and the branch
15444 will be forced to the new group. */
15445 if (can_issue_more && !is_branch_slot_insn (next_insn))
15448 while (can_issue_more > 0)
15451 emit_insn_before (nop, next_insn);
15459 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
15461 int n_nops = rs6000_sched_insert_nops;
15463 /* Nops can't be issued from the branch slot, so the effective
15464 issue_rate for nops is 'issue_rate - 1'. */
15465 if (can_issue_more == 0)
15466 can_issue_more = issue_rate;
15468 if (can_issue_more == 0)
15470 can_issue_more = issue_rate - 1;
15473 for (i = 0; i < issue_rate; i++)
15475 group_insns[i] = 0;
15482 emit_insn_before (nop, next_insn);
15483 if (can_issue_more == issue_rate - 1) /* new group begins */
15486 if (can_issue_more == 0)
15488 can_issue_more = issue_rate - 1;
15491 for (i = 0; i < issue_rate; i++)
15493 group_insns[i] = 0;
15499 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
15502 /* Is next_insn going to start a new group? */
15505 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15506 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15507 || (can_issue_more < issue_rate &&
15508 insn_terminates_group_p (next_insn, previous_group)));
15509 if (*group_end && end)
15512 if (sched_verbose > 6)
15513 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
15514 *group_count, can_issue_more);
15515 return can_issue_more;
15518 return can_issue_more;
15521 /* This function tries to synch the dispatch groups that the compiler "sees"
15522 with the dispatch groups that the processor dispatcher is expected to
15523 form in practice. It tries to achieve this synchronization by forcing the
15524 estimated processor grouping on the compiler (as opposed to the function
15525 'pad_goups' which tries to force the scheduler's grouping on the processor).
15527 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
15528 examines the (estimated) dispatch groups that will be formed by the processor
15529 dispatcher. It marks these group boundaries to reflect the estimated
15530 processor grouping, overriding the grouping that the scheduler had marked.
15531 Depending on the value of the flag '-minsert-sched-nops' this function can
15532 force certain insns into separate groups or force a certain distance between
15533 them by inserting nops, for example, if there exists a "costly dependence"
15536 The function estimates the group boundaries that the processor will form as
15537 folllows: It keeps track of how many vacant issue slots are available after
15538 each insn. A subsequent insn will start a new group if one of the following
15540 - no more vacant issue slots remain in the current dispatch group.
15541 - only the last issue slot, which is the branch slot, is vacant, but the next
15542 insn is not a branch.
15543 - only the last 2 or less issue slots, including the branch slot, are vacant,
15544 which means that a cracked insn (which occupies two issue slots) can't be
15545 issued in this group.
15546 - less than 'issue_rate' slots are vacant, and the next insn always needs to
15547 start a new group. */
15550 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15552 rtx insn, next_insn;
15554 int can_issue_more;
15557 int group_count = 0;
15561 issue_rate = rs6000_issue_rate ();
15562 group_insns = alloca (issue_rate * sizeof (rtx));
15563 for (i = 0; i < issue_rate; i++)
15565 group_insns[i] = 0;
15567 can_issue_more = issue_rate;
15569 insn = get_next_active_insn (prev_head_insn, tail);
15572 while (insn != NULL_RTX)
15574 slot = (issue_rate - can_issue_more);
15575 group_insns[slot] = insn;
15577 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15578 if (insn_terminates_group_p (insn, current_group))
15579 can_issue_more = 0;
15581 next_insn = get_next_active_insn (insn, tail);
15582 if (next_insn == NULL_RTX)
15583 return group_count + 1;
15585 /* Is next_insn going to start a new group? */
15587 = (can_issue_more == 0
15588 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
15589 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
15590 || (can_issue_more < issue_rate &&
15591 insn_terminates_group_p (next_insn, previous_group)));
15593 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
15594 next_insn, &group_end, can_issue_more,
15600 can_issue_more = 0;
15601 for (i = 0; i < issue_rate; i++)
15603 group_insns[i] = 0;
15607 if (GET_MODE (next_insn) == TImode && can_issue_more)
15608 PUT_MODE (next_insn, VOIDmode);
15609 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
15610 PUT_MODE (next_insn, TImode);
15613 if (can_issue_more == 0)
15614 can_issue_more = issue_rate;
15617 return group_count;
15620 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
15621 dispatch group boundaries that the scheduler had marked. Pad with nops
15622 any dispatch groups which have vacant issue slots, in order to force the
15623 scheduler's grouping on the processor dispatcher. The function
15624 returns the number of dispatch groups found. */
15627 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
15629 rtx insn, next_insn;
15632 int can_issue_more;
15634 int group_count = 0;
15636 /* Initialize issue_rate. */
15637 issue_rate = rs6000_issue_rate ();
15638 can_issue_more = issue_rate;
15640 insn = get_next_active_insn (prev_head_insn, tail);
15641 next_insn = get_next_active_insn (insn, tail);
15643 while (insn != NULL_RTX)
15646 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
15648 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
15650 if (next_insn == NULL_RTX)
15655 /* If the scheduler had marked group termination at this location
15656 (between insn and next_indn), and neither insn nor next_insn will
15657 force group termination, pad the group with nops to force group
15660 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
15661 && !insn_terminates_group_p (insn, current_group)
15662 && !insn_terminates_group_p (next_insn, previous_group))
15664 if (!is_branch_slot_insn (next_insn))
15667 while (can_issue_more)
15670 emit_insn_before (nop, next_insn);
15675 can_issue_more = issue_rate;
15680 next_insn = get_next_active_insn (insn, tail);
15683 return group_count;
15686 /* The following function is called at the end of scheduling BB.
15687 After reload, it inserts nops at insn group bundling. */
15690 rs6000_sched_finish (FILE *dump, int sched_verbose)
15695 fprintf (dump, "=== Finishing schedule.\n");
15697 if (reload_completed && rs6000_sched_groups)
15699 if (rs6000_sched_insert_nops == sched_finish_none)
15702 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
15703 n_groups = pad_groups (dump, sched_verbose,
15704 current_sched_info->prev_head,
15705 current_sched_info->next_tail);
15707 n_groups = redefine_groups (dump, sched_verbose,
15708 current_sched_info->prev_head,
15709 current_sched_info->next_tail);
15711 if (sched_verbose >= 6)
15713 fprintf (dump, "ngroups = %d\n", n_groups);
15714 print_rtl (dump, current_sched_info->prev_head);
15715 fprintf (dump, "Done finish_sched\n");
15720 /* Length in units of the trampoline for entering a nested function. */
15723 rs6000_trampoline_size (void)
15727 switch (DEFAULT_ABI)
15733 ret = (TARGET_32BIT) ? 12 : 24;
15738 ret = (TARGET_32BIT) ? 40 : 48;
15745 /* Emit RTL insns to initialize the variable parts of a trampoline.
15746 FNADDR is an RTX for the address of the function's pure code.
15747 CXT is an RTX for the static chain value for the function. */
15750 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
15752 enum machine_mode pmode = Pmode;
15753 int regsize = (TARGET_32BIT) ? 4 : 8;
15754 rtx ctx_reg = force_reg (pmode, cxt);
15756 switch (DEFAULT_ABI)
15761 /* Macros to shorten the code expansions below. */
15762 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
15763 #define MEM_PLUS(addr,offset) \
15764 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
15766 /* Under AIX, just build the 3 word function descriptor */
15769 rtx fn_reg = gen_reg_rtx (pmode);
15770 rtx toc_reg = gen_reg_rtx (pmode);
15771 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
15772 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
15773 emit_move_insn (MEM_DEREF (addr), fn_reg);
15774 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
15775 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
15779 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
15782 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
15783 FALSE, VOIDmode, 4,
15785 GEN_INT (rs6000_trampoline_size ()), SImode,
15795 /* Table of valid machine attributes. */
15797 const struct attribute_spec rs6000_attribute_table[] =
15799 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
15800 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
15801 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15802 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
15803 #ifdef SUBTARGET_ATTRIBUTE_TABLE
15804 SUBTARGET_ATTRIBUTE_TABLE,
15806 { NULL, 0, 0, false, false, false, NULL }
15809 /* Handle the "altivec" attribute. The attribute may have
15810 arguments as follows:
15812 __attribute__((altivec(vector__)))
15813 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
15814 __attribute__((altivec(bool__))) (always followed by 'unsigned')
15816 and may appear more than once (e.g., 'vector bool char') in a
15817 given declaration. */
15820 rs6000_handle_altivec_attribute (tree *node,
15821 tree name ATTRIBUTE_UNUSED,
15823 int flags ATTRIBUTE_UNUSED,
15824 bool *no_add_attrs)
15826 tree type = *node, result = NULL_TREE;
15827 enum machine_mode mode;
15830 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
15831 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
15832 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
15835 while (POINTER_TYPE_P (type)
15836 || TREE_CODE (type) == FUNCTION_TYPE
15837 || TREE_CODE (type) == METHOD_TYPE
15838 || TREE_CODE (type) == ARRAY_TYPE)
15839 type = TREE_TYPE (type);
15841 mode = TYPE_MODE (type);
15843 /* Check for invalid AltiVec type qualifiers. */
15844 if (type == long_unsigned_type_node || type == long_integer_type_node)
15847 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
15848 else if (rs6000_warn_altivec_long)
15849 warning ("use of %<long%> in AltiVec types is deprecated; use %<int%>");
15851 else if (type == long_long_unsigned_type_node
15852 || type == long_long_integer_type_node)
15853 error ("use of %<long long%> in AltiVec types is invalid");
15854 else if (type == double_type_node)
15855 error ("use of %<double%> in AltiVec types is invalid");
15856 else if (type == long_double_type_node)
15857 error ("use of %<long double%> in AltiVec types is invalid");
15858 else if (type == boolean_type_node)
15859 error ("use of boolean types in AltiVec types is invalid");
15860 else if (TREE_CODE (type) == COMPLEX_TYPE)
15861 error ("use of %<complex%> in AltiVec types is invalid");
15863 switch (altivec_type)
15866 unsigned_p = TYPE_UNSIGNED (type);
15870 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
15873 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
15876 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
15878 case SFmode: result = V4SF_type_node; break;
15879 /* If the user says 'vector int bool', we may be handed the 'bool'
15880 attribute _before_ the 'vector' attribute, and so select the
15881 proper type in the 'b' case below. */
15882 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
15890 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
15891 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
15892 case QImode: case V16QImode: result = bool_V16QI_type_node;
15899 case V8HImode: result = pixel_V8HI_type_node;
15905 if (result && result != type && TYPE_READONLY (type))
15906 result = build_qualified_type (result, TYPE_QUAL_CONST);
15908 *no_add_attrs = true; /* No need to hang on to the attribute. */
15911 *node = reconstruct_complex_type (*node, result);
15916 /* AltiVec defines four built-in scalar types that serve as vector
15917 elements; we must teach the compiler how to mangle them. */
15919 static const char *
15920 rs6000_mangle_fundamental_type (tree type)
15922 if (type == bool_char_type_node) return "U6__boolc";
15923 if (type == bool_short_type_node) return "U6__bools";
15924 if (type == pixel_type_node) return "u7__pixel";
15925 if (type == bool_int_type_node) return "U6__booli";
15927 /* For all other types, use normal C++ mangling. */
15931 /* Handle a "longcall" or "shortcall" attribute; arguments as in
15932 struct attribute_spec.handler. */
15935 rs6000_handle_longcall_attribute (tree *node, tree name,
15936 tree args ATTRIBUTE_UNUSED,
15937 int flags ATTRIBUTE_UNUSED,
15938 bool *no_add_attrs)
15940 if (TREE_CODE (*node) != FUNCTION_TYPE
15941 && TREE_CODE (*node) != FIELD_DECL
15942 && TREE_CODE (*node) != TYPE_DECL)
15944 warning ("%qs attribute only applies to functions",
15945 IDENTIFIER_POINTER (name));
15946 *no_add_attrs = true;
15952 /* Set longcall attributes on all functions declared when
15953 rs6000_default_long_calls is true. */
15955 rs6000_set_default_type_attributes (tree type)
15957 if (rs6000_default_long_calls
15958 && (TREE_CODE (type) == FUNCTION_TYPE
15959 || TREE_CODE (type) == METHOD_TYPE))
15960 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
15962 TYPE_ATTRIBUTES (type));
15965 /* Return a reference suitable for calling a function with the
15966 longcall attribute. */
15969 rs6000_longcall_ref (rtx call_ref)
15971 const char *call_name;
15974 if (GET_CODE (call_ref) != SYMBOL_REF)
15977 /* System V adds '.' to the internal name, so skip them. */
15978 call_name = XSTR (call_ref, 0);
15979 if (*call_name == '.')
15981 while (*call_name == '.')
15984 node = get_identifier (call_name);
15985 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
15988 return force_reg (Pmode, call_ref);
15991 #ifdef USING_ELFOS_H
15993 /* A C statement or statements to switch to the appropriate section
15994 for output of RTX in mode MODE. You can assume that RTX is some
15995 kind of constant in RTL. The argument MODE is redundant except in
15996 the case of a `const_int' rtx. Select the section by calling
15997 `text_section' or one of the alternatives for other sections.
15999 Do not define this macro if you put all constants in the read-only
16003 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
16004 unsigned HOST_WIDE_INT align)
16006 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16009 default_elf_select_rtx_section (mode, x, align);
16012 /* A C statement or statements to switch to the appropriate
16013 section for output of DECL. DECL is either a `VAR_DECL' node
16014 or a constant of some sort. RELOC indicates whether forming
16015 the initial value of DECL requires link-time relocations. */
16018 rs6000_elf_select_section (tree decl, int reloc,
16019 unsigned HOST_WIDE_INT align)
16021 /* Pretend that we're always building for a shared library when
16022 ABI_AIX, because otherwise we end up with dynamic relocations
16023 in read-only sections. This happens for function pointers,
16024 references to vtables in typeinfo, and probably other cases. */
16025 default_elf_select_section_1 (decl, reloc, align,
16026 flag_pic || DEFAULT_ABI == ABI_AIX);
16029 /* A C statement to build up a unique section name, expressed as a
16030 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
16031 RELOC indicates whether the initial value of EXP requires
16032 link-time relocations. If you do not define this macro, GCC will use
16033 the symbol name prefixed by `.' as the section name. Note - this
16034 macro can now be called for uninitialized data items as well as
16035 initialized data and functions. */
16038 rs6000_elf_unique_section (tree decl, int reloc)
16040 /* As above, pretend that we're always building for a shared library
16041 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
16042 default_unique_section_1 (decl, reloc,
16043 flag_pic || DEFAULT_ABI == ABI_AIX);
16046 /* For a SYMBOL_REF, set generic flags and then perform some
16047 target-specific processing.
16049 When the AIX ABI is requested on a non-AIX system, replace the
16050 function name with the real name (with a leading .) rather than the
16051 function descriptor name. This saves a lot of overriding code to
16052 read the prefixes. */
16055 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
16057 default_encode_section_info (decl, rtl, first);
16060 && TREE_CODE (decl) == FUNCTION_DECL
16062 && DEFAULT_ABI == ABI_AIX)
16064 rtx sym_ref = XEXP (rtl, 0);
16065 size_t len = strlen (XSTR (sym_ref, 0));
16066 char *str = alloca (len + 2);
16068 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
16069 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
16074 rs6000_elf_in_small_data_p (tree decl)
16076 if (rs6000_sdata == SDATA_NONE)
16079 /* We want to merge strings, so we never consider them small data. */
16080 if (TREE_CODE (decl) == STRING_CST)
16083 /* Functions are never in the small data area. */
16084 if (TREE_CODE (decl) == FUNCTION_DECL)
16087 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
16089 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
16090 if (strcmp (section, ".sdata") == 0
16091 || strcmp (section, ".sdata2") == 0
16092 || strcmp (section, ".sbss") == 0
16093 || strcmp (section, ".sbss2") == 0
16094 || strcmp (section, ".PPC.EMB.sdata0") == 0
16095 || strcmp (section, ".PPC.EMB.sbss0") == 0)
16100 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
16103 && (unsigned HOST_WIDE_INT) size <= g_switch_value
16104 /* If it's not public, and we're not going to reference it there,
16105 there's no need to put it in the small data section. */
16106 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
16113 #endif /* USING_ELFOS_H */
16116 /* Return a REG that occurs in ADDR with coefficient 1.
16117 ADDR can be effectively incremented by incrementing REG.
16119 r0 is special and we must not select it as an address
16120 register by this routine since our caller will try to
16121 increment the returned register via an "la" instruction. */
16124 find_addr_reg (rtx addr)
16126 while (GET_CODE (addr) == PLUS)
16128 if (GET_CODE (XEXP (addr, 0)) == REG
16129 && REGNO (XEXP (addr, 0)) != 0)
16130 addr = XEXP (addr, 0);
16131 else if (GET_CODE (XEXP (addr, 1)) == REG
16132 && REGNO (XEXP (addr, 1)) != 0)
16133 addr = XEXP (addr, 1);
16134 else if (CONSTANT_P (XEXP (addr, 0)))
16135 addr = XEXP (addr, 1);
16136 else if (CONSTANT_P (XEXP (addr, 1)))
16137 addr = XEXP (addr, 0);
16141 if (GET_CODE (addr) == REG && REGNO (addr) != 0)
16147 rs6000_fatal_bad_address (rtx op)
16149 fatal_insn ("bad address", op);
16154 static tree branch_island_list = 0;
16156 /* Remember to generate a branch island for far calls to the given
16160 add_compiler_branch_island (tree label_name, tree function_name,
16163 tree branch_island = build_tree_list (function_name, label_name);
16164 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
16165 TREE_CHAIN (branch_island) = branch_island_list;
16166 branch_island_list = branch_island;
16169 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
16170 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
16171 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
16172 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
16174 /* Generate far-jump branch islands for everything on the
16175 branch_island_list. Invoked immediately after the last instruction
16176 of the epilogue has been emitted; the branch-islands must be
16177 appended to, and contiguous with, the function body. Mach-O stubs
16178 are generated in machopic_output_stub(). */
16181 macho_branch_islands (void)
16184 tree branch_island;
16186 for (branch_island = branch_island_list;
16188 branch_island = TREE_CHAIN (branch_island))
16190 const char *label =
16191 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
16193 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
16194 char name_buf[512];
16195 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
16196 if (name[0] == '*' || name[0] == '&')
16197 strcpy (name_buf, name+1);
16201 strcpy (name_buf+1, name);
16203 strcpy (tmp_buf, "\n");
16204 strcat (tmp_buf, label);
16205 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16206 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16207 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16208 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16211 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
16212 strcat (tmp_buf, label);
16213 strcat (tmp_buf, "_pic\n");
16214 strcat (tmp_buf, label);
16215 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
16217 strcat (tmp_buf, "\taddis r11,r11,ha16(");
16218 strcat (tmp_buf, name_buf);
16219 strcat (tmp_buf, " - ");
16220 strcat (tmp_buf, label);
16221 strcat (tmp_buf, "_pic)\n");
16223 strcat (tmp_buf, "\tmtlr r0\n");
16225 strcat (tmp_buf, "\taddi r12,r11,lo16(");
16226 strcat (tmp_buf, name_buf);
16227 strcat (tmp_buf, " - ");
16228 strcat (tmp_buf, label);
16229 strcat (tmp_buf, "_pic)\n");
16231 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
16235 strcat (tmp_buf, ":\nlis r12,hi16(");
16236 strcat (tmp_buf, name_buf);
16237 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
16238 strcat (tmp_buf, name_buf);
16239 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
16241 output_asm_insn (tmp_buf, 0);
16242 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
16243 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
16244 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
16245 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
16248 branch_island_list = 0;
16251 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
16252 already there or not. */
16255 no_previous_def (tree function_name)
16257 tree branch_island;
16258 for (branch_island = branch_island_list;
16260 branch_island = TREE_CHAIN (branch_island))
16261 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16266 /* GET_PREV_LABEL gets the label name from the previous definition of
16270 get_prev_label (tree function_name)
16272 tree branch_island;
16273 for (branch_island = branch_island_list;
16275 branch_island = TREE_CHAIN (branch_island))
16276 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
16277 return BRANCH_ISLAND_LABEL_NAME (branch_island);
16281 /* INSN is either a function call or a millicode call. It may have an
16282 unconditional jump in its delay slot.
16284 CALL_DEST is the routine we are calling. */
16287 output_call (rtx insn, rtx *operands, int dest_operand_number,
16288 int cookie_operand_number)
16290 static char buf[256];
16291 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
16292 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
16295 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
16297 if (no_previous_def (funname))
16299 int line_number = 0;
16300 rtx label_rtx = gen_label_rtx ();
16301 char *label_buf, temp_buf[256];
16302 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
16303 CODE_LABEL_NUMBER (label_rtx));
16304 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
16305 labelname = get_identifier (label_buf);
16306 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
16308 line_number = NOTE_LINE_NUMBER (insn);
16309 add_compiler_branch_island (labelname, funname, line_number);
16312 labelname = get_prev_label (funname);
16314 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
16315 instruction will reach 'foo', otherwise link as 'bl L42'".
16316 "L42" should be a 'branch island', that will do a far jump to
16317 'foo'. Branch islands are generated in
16318 macho_branch_islands(). */
16319 sprintf (buf, "jbsr %%z%d,%.246s",
16320 dest_operand_number, IDENTIFIER_POINTER (labelname));
16323 sprintf (buf, "bl %%z%d", dest_operand_number);
16327 /* Generate PIC and indirect symbol stubs. */
16330 machopic_output_stub (FILE *file, const char *symb, const char *stub)
16332 unsigned int length;
16333 char *symbol_name, *lazy_ptr_name;
16334 char *local_label_0;
16335 static int label = 0;
16337 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
16338 symb = (*targetm.strip_name_encoding) (symb);
16341 length = strlen (symb);
16342 symbol_name = alloca (length + 32);
16343 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
16345 lazy_ptr_name = alloca (length + 32);
16346 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
16349 machopic_picsymbol_stub1_section ();
16351 machopic_symbol_stub1_section ();
16355 fprintf (file, "\t.align 5\n");
16357 fprintf (file, "%s:\n", stub);
16358 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16361 local_label_0 = alloca (sizeof ("\"L0000000000$spb\""));
16362 sprintf (local_label_0, "\"L%011d$spb\"", label);
16364 fprintf (file, "\tmflr r0\n");
16365 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
16366 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
16367 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
16368 lazy_ptr_name, local_label_0);
16369 fprintf (file, "\tmtlr r0\n");
16370 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
16371 (TARGET_64BIT ? "ldu" : "lwzu"),
16372 lazy_ptr_name, local_label_0);
16373 fprintf (file, "\tmtctr r12\n");
16374 fprintf (file, "\tbctr\n");
16378 fprintf (file, "\t.align 4\n");
16380 fprintf (file, "%s:\n", stub);
16381 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16383 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
16384 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
16385 (TARGET_64BIT ? "ldu" : "lwzu"),
16387 fprintf (file, "\tmtctr r12\n");
16388 fprintf (file, "\tbctr\n");
16391 machopic_lazy_symbol_ptr_section ();
16392 fprintf (file, "%s:\n", lazy_ptr_name);
16393 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
16394 fprintf (file, "%sdyld_stub_binding_helper\n",
16395 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
16398 /* Legitimize PIC addresses. If the address is already
16399 position-independent, we return ORIG. Newly generated
16400 position-independent addresses go into a reg. This is REG if non
16401 zero, otherwise we allocate register(s) as necessary. */
16403 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
16406 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
16411 if (reg == NULL && ! reload_in_progress && ! reload_completed)
16412 reg = gen_reg_rtx (Pmode);
16414 if (GET_CODE (orig) == CONST)
16416 if (GET_CODE (XEXP (orig, 0)) == PLUS
16417 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
16420 if (GET_CODE (XEXP (orig, 0)) == PLUS)
16422 /* Use a different reg for the intermediate value, as
16423 it will be marked UNCHANGING. */
16424 rtx reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
16427 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
16430 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
16436 if (GET_CODE (offset) == CONST_INT)
16438 if (SMALL_INT (offset))
16439 return plus_constant (base, INTVAL (offset));
16440 else if (! reload_in_progress && ! reload_completed)
16441 offset = force_reg (Pmode, offset);
16444 rtx mem = force_const_mem (Pmode, orig);
16445 return machopic_legitimize_pic_address (mem, Pmode, reg);
16448 return gen_rtx_PLUS (Pmode, base, offset);
16451 /* Fall back on generic machopic code. */
16452 return machopic_legitimize_pic_address (orig, mode, reg);
16455 /* This is just a placeholder to make linking work without having to
16456 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
16457 ever needed for Darwin (not too likely!) this would have to get a
16458 real definition. */
16465 /* Output a .machine directive for the Darwin assembler, and call
16466 the generic start_file routine. */
16469 rs6000_darwin_file_start (void)
16471 static const struct
16477 { "ppc64", "ppc64", MASK_64BIT },
16478 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
16479 { "power4", "ppc970", 0 },
16480 { "G5", "ppc970", 0 },
16481 { "7450", "ppc7450", 0 },
16482 { "7400", "ppc7400", MASK_ALTIVEC },
16483 { "G4", "ppc7400", 0 },
16484 { "750", "ppc750", 0 },
16485 { "740", "ppc750", 0 },
16486 { "G3", "ppc750", 0 },
16487 { "604e", "ppc604e", 0 },
16488 { "604", "ppc604", 0 },
16489 { "603e", "ppc603", 0 },
16490 { "603", "ppc603", 0 },
16491 { "601", "ppc601", 0 },
16492 { NULL, "ppc", 0 } };
16493 const char *cpu_id = "";
16496 rs6000_file_start ();
16498 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
16499 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
16500 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
16501 && rs6000_select[i].string[0] != '\0')
16502 cpu_id = rs6000_select[i].string;
16504 /* Look through the mapping array. Pick the first name that either
16505 matches the argument, has a bit set in IF_SET that is also set
16506 in the target flags, or has a NULL name. */
16509 while (mapping[i].arg != NULL
16510 && strcmp (mapping[i].arg, cpu_id) != 0
16511 && (mapping[i].if_set & target_flags) == 0)
16514 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
16517 #endif /* TARGET_MACHO */
16520 static unsigned int
16521 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
16523 return default_section_type_flags_1 (decl, name, reloc,
16524 flag_pic || DEFAULT_ABI == ABI_AIX);
16527 /* Record an element in the table of global constructors. SYMBOL is
16528 a SYMBOL_REF of the function to be called; PRIORITY is a number
16529 between 0 and MAX_INIT_PRIORITY.
16531 This differs from default_named_section_asm_out_constructor in
16532 that we have special handling for -mrelocatable. */
16535 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
16537 const char *section = ".ctors";
16540 if (priority != DEFAULT_INIT_PRIORITY)
16542 sprintf (buf, ".ctors.%.5u",
16543 /* Invert the numbering so the linker puts us in the proper
16544 order; constructors are run from right to left, and the
16545 linker sorts in increasing order. */
16546 MAX_INIT_PRIORITY - priority);
16550 named_section_flags (section, SECTION_WRITE);
16551 assemble_align (POINTER_SIZE);
16553 if (TARGET_RELOCATABLE)
16555 fputs ("\t.long (", asm_out_file);
16556 output_addr_const (asm_out_file, symbol);
16557 fputs (")@fixup\n", asm_out_file);
16560 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16564 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
16566 const char *section = ".dtors";
16569 if (priority != DEFAULT_INIT_PRIORITY)
16571 sprintf (buf, ".dtors.%.5u",
16572 /* Invert the numbering so the linker puts us in the proper
16573 order; constructors are run from right to left, and the
16574 linker sorts in increasing order. */
16575 MAX_INIT_PRIORITY - priority);
16579 named_section_flags (section, SECTION_WRITE);
16580 assemble_align (POINTER_SIZE);
16582 if (TARGET_RELOCATABLE)
16584 fputs ("\t.long (", asm_out_file);
16585 output_addr_const (asm_out_file, symbol);
16586 fputs (")@fixup\n", asm_out_file);
16589 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
16593 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
16597 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
16598 ASM_OUTPUT_LABEL (file, name);
16599 fputs (DOUBLE_INT_ASM_OP, file);
16600 rs6000_output_function_entry (file, name);
16601 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
16604 fputs ("\t.size\t", file);
16605 assemble_name (file, name);
16606 fputs (",24\n\t.type\t.", file);
16607 assemble_name (file, name);
16608 fputs (",@function\n", file);
16609 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
16611 fputs ("\t.globl\t.", file);
16612 assemble_name (file, name);
16617 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16618 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16619 rs6000_output_function_entry (file, name);
16620 fputs (":\n", file);
16624 if (TARGET_RELOCATABLE
16625 && (get_pool_size () != 0 || current_function_profile)
16630 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
16632 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
16633 fprintf (file, "\t.long ");
16634 assemble_name (file, buf);
16636 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
16637 assemble_name (file, buf);
16641 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
16642 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
16644 if (DEFAULT_ABI == ABI_AIX)
16646 const char *desc_name, *orig_name;
16648 orig_name = (*targetm.strip_name_encoding) (name);
16649 desc_name = orig_name;
16650 while (*desc_name == '.')
16653 if (TREE_PUBLIC (decl))
16654 fprintf (file, "\t.globl %s\n", desc_name);
16656 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
16657 fprintf (file, "%s:\n", desc_name);
16658 fprintf (file, "\t.long %s\n", orig_name);
16659 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
16660 if (DEFAULT_ABI == ABI_AIX)
16661 fputs ("\t.long 0\n", file);
16662 fprintf (file, "\t.previous\n");
16664 ASM_OUTPUT_LABEL (file, name);
16670 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
16672 fputs (GLOBAL_ASM_OP, stream);
16673 RS6000_OUTPUT_BASENAME (stream, name);
16674 putc ('\n', stream);
16678 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
16679 tree decl ATTRIBUTE_UNUSED)
16682 static const char * const suffix[3] = { "PR", "RO", "RW" };
16684 if (flags & SECTION_CODE)
16686 else if (flags & SECTION_WRITE)
16691 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
16692 (flags & SECTION_CODE) ? "." : "",
16693 name, suffix[smclass], flags & SECTION_ENTSIZE);
16697 rs6000_xcoff_select_section (tree decl, int reloc,
16698 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16700 if (decl_readonly_section_1 (decl, reloc, 1))
16702 if (TREE_PUBLIC (decl))
16703 read_only_data_section ();
16705 read_only_private_data_section ();
16709 if (TREE_PUBLIC (decl))
16712 private_data_section ();
16717 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
16721 /* Use select_section for private and uninitialized data. */
16722 if (!TREE_PUBLIC (decl)
16723 || DECL_COMMON (decl)
16724 || DECL_INITIAL (decl) == NULL_TREE
16725 || DECL_INITIAL (decl) == error_mark_node
16726 || (flag_zero_initialized_in_bss
16727 && initializer_zerop (DECL_INITIAL (decl))))
16730 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
16731 name = (*targetm.strip_name_encoding) (name);
16732 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
16735 /* Select section for constant in constant pool.
16737 On RS/6000, all constants are in the private read-only data area.
16738 However, if this is being placed in the TOC it must be output as a
16742 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
16743 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
16745 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
16748 read_only_private_data_section ();
16751 /* Remove any trailing [DS] or the like from the symbol name. */
16753 static const char *
16754 rs6000_xcoff_strip_name_encoding (const char *name)
16759 len = strlen (name);
16760 if (name[len - 1] == ']')
16761 return ggc_alloc_string (name, len - 4);
16766 /* Section attributes. AIX is always PIC. */
16768 static unsigned int
16769 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
16771 unsigned int align;
16772 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
16774 /* Align to at least UNIT size. */
16775 if (flags & SECTION_CODE)
16776 align = MIN_UNITS_PER_WORD;
16778 /* Increase alignment of large objects if not already stricter. */
16779 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
16780 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
16781 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
16783 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
16786 /* Output at beginning of assembler file.
16788 Initialize the section names for the RS/6000 at this point.
16790 Specify filename, including full path, to assembler.
16792 We want to go into the TOC section so at least one .toc will be emitted.
16793 Also, in order to output proper .bs/.es pairs, we need at least one static
16794 [RW] section emitted.
16796 Finally, declare mcount when profiling to make the assembler happy. */
16799 rs6000_xcoff_file_start (void)
16801 rs6000_gen_section_name (&xcoff_bss_section_name,
16802 main_input_filename, ".bss_");
16803 rs6000_gen_section_name (&xcoff_private_data_section_name,
16804 main_input_filename, ".rw_");
16805 rs6000_gen_section_name (&xcoff_read_only_section_name,
16806 main_input_filename, ".ro_");
16808 fputs ("\t.file\t", asm_out_file);
16809 output_quoted_string (asm_out_file, main_input_filename);
16810 fputc ('\n', asm_out_file);
16811 if (write_symbols != NO_DEBUG)
16812 private_data_section ();
16815 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
16816 rs6000_file_start ();
16819 /* Output at end of assembler file.
16820 On the RS/6000, referencing data should automatically pull in text. */
16823 rs6000_xcoff_file_end (void)
16826 fputs ("_section_.text:\n", asm_out_file);
16828 fputs (TARGET_32BIT
16829 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
16832 #endif /* TARGET_XCOFF */
16835 /* Cross-module name binding. Darwin does not support overriding
16836 functions at dynamic-link time. */
16839 rs6000_binds_local_p (tree decl)
16841 return default_binds_local_p_1 (decl, 0);
16845 /* Compute a (partial) cost for rtx X. Return true if the complete
16846 cost has been computed, and false if subexpressions should be
16847 scanned. In either case, *TOTAL contains the cost result. */
16850 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
16852 enum machine_mode mode = GET_MODE (x);
16856 /* On the RS/6000, if it is valid in the insn, it is free. */
16858 if (((outer_code == SET
16859 || outer_code == PLUS
16860 || outer_code == MINUS)
16861 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16862 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
16863 || (outer_code == AND
16864 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16865 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16866 mode == SImode ? 'L' : 'J'))
16867 || mask_operand (x, VOIDmode)))
16868 || ((outer_code == IOR || outer_code == XOR)
16869 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16870 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16871 mode == SImode ? 'L' : 'J'))))
16872 || outer_code == ASHIFT
16873 || outer_code == ASHIFTRT
16874 || outer_code == LSHIFTRT
16875 || outer_code == ROTATE
16876 || outer_code == ROTATERT
16877 || outer_code == ZERO_EXTRACT
16878 || (outer_code == MULT
16879 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16880 || ((outer_code == DIV || outer_code == UDIV
16881 || outer_code == MOD || outer_code == UMOD)
16882 && exact_log2 (INTVAL (x)) >= 0)
16883 || (outer_code == COMPARE
16884 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16885 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
16886 || (outer_code == EQ
16887 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
16888 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16889 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
16890 mode == SImode ? 'L' : 'J'))))
16891 || (outer_code == GTU
16892 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
16893 || (outer_code == LTU
16894 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
16899 else if ((outer_code == PLUS
16900 && reg_or_add_cint64_operand (x, VOIDmode))
16901 || (outer_code == MINUS
16902 && reg_or_sub_cint64_operand (x, VOIDmode))
16903 || ((outer_code == SET
16904 || outer_code == IOR
16905 || outer_code == XOR)
16907 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
16909 *total = COSTS_N_INSNS (1);
16916 && ((outer_code == AND
16917 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
16918 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
16919 || mask64_operand (x, DImode)))
16920 || ((outer_code == IOR || outer_code == XOR)
16921 && CONST_DOUBLE_HIGH (x) == 0
16922 && (CONST_DOUBLE_LOW (x)
16923 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
16928 else if (mode == DImode
16929 && (outer_code == SET
16930 || outer_code == IOR
16931 || outer_code == XOR)
16932 && CONST_DOUBLE_HIGH (x) == 0)
16934 *total = COSTS_N_INSNS (1);
16943 /* When optimizing for size, MEM should be slightly more expensive
16944 than generating address, e.g., (plus (reg) (const)).
16945 L1 cache latency is about two instructions. */
16946 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
16954 if (mode == DFmode)
16956 if (GET_CODE (XEXP (x, 0)) == MULT)
16958 /* FNMA accounted in outer NEG. */
16959 if (outer_code == NEG)
16960 *total = rs6000_cost->dmul - rs6000_cost->fp;
16962 *total = rs6000_cost->dmul;
16965 *total = rs6000_cost->fp;
16967 else if (mode == SFmode)
16969 /* FNMA accounted in outer NEG. */
16970 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
16973 *total = rs6000_cost->fp;
16975 else if (GET_CODE (XEXP (x, 0)) == MULT)
16977 /* The rs6000 doesn't have shift-and-add instructions. */
16978 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
16979 *total += COSTS_N_INSNS (1);
16982 *total = COSTS_N_INSNS (1);
16986 if (mode == DFmode)
16988 if (GET_CODE (XEXP (x, 0)) == MULT)
16990 /* FNMA accounted in outer NEG. */
16991 if (outer_code == NEG)
16994 *total = rs6000_cost->dmul;
16997 *total = rs6000_cost->fp;
16999 else if (mode == SFmode)
17001 /* FNMA accounted in outer NEG. */
17002 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
17005 *total = rs6000_cost->fp;
17007 else if (GET_CODE (XEXP (x, 0)) == MULT)
17009 /* The rs6000 doesn't have shift-and-sub instructions. */
17010 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
17011 *total += COSTS_N_INSNS (1);
17014 *total = COSTS_N_INSNS (1);
17018 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17019 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
17021 if (INTVAL (XEXP (x, 1)) >= -256
17022 && INTVAL (XEXP (x, 1)) <= 255)
17023 *total = rs6000_cost->mulsi_const9;
17025 *total = rs6000_cost->mulsi_const;
17027 /* FMA accounted in outer PLUS/MINUS. */
17028 else if ((mode == DFmode || mode == SFmode)
17029 && (outer_code == PLUS || outer_code == MINUS))
17031 else if (mode == DFmode)
17032 *total = rs6000_cost->dmul;
17033 else if (mode == SFmode)
17034 *total = rs6000_cost->fp;
17035 else if (mode == DImode)
17036 *total = rs6000_cost->muldi;
17038 *total = rs6000_cost->mulsi;
17043 if (FLOAT_MODE_P (mode))
17045 *total = mode == DFmode ? rs6000_cost->ddiv
17046 : rs6000_cost->sdiv;
17053 if (GET_CODE (XEXP (x, 1)) == CONST_INT
17054 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
17056 if (code == DIV || code == MOD)
17058 *total = COSTS_N_INSNS (2);
17061 *total = COSTS_N_INSNS (1);
17065 if (GET_MODE (XEXP (x, 1)) == DImode)
17066 *total = rs6000_cost->divdi;
17068 *total = rs6000_cost->divsi;
17070 /* Add in shift and subtract for MOD. */
17071 if (code == MOD || code == UMOD)
17072 *total += COSTS_N_INSNS (2);
17076 *total = COSTS_N_INSNS (4);
17080 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
17091 *total = COSTS_N_INSNS (1);
17099 /* Handle mul_highpart. */
17100 if (outer_code == TRUNCATE
17101 && GET_CODE (XEXP (x, 0)) == MULT)
17103 if (mode == DImode)
17104 *total = rs6000_cost->muldi;
17106 *total = rs6000_cost->mulsi;
17109 else if (outer_code == AND)
17112 *total = COSTS_N_INSNS (1);
17117 if (GET_CODE (XEXP (x, 0)) == MEM)
17120 *total = COSTS_N_INSNS (1);
17126 if (!FLOAT_MODE_P (mode))
17128 *total = COSTS_N_INSNS (1);
17134 case UNSIGNED_FLOAT:
17138 case FLOAT_TRUNCATE:
17139 *total = rs6000_cost->fp;
17143 switch (XINT (x, 1))
17146 *total = rs6000_cost->fp;
17158 *total = COSTS_N_INSNS (1);
17161 else if (FLOAT_MODE_P (mode)
17162 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
17164 *total = rs6000_cost->fp;
17172 /* Carry bit requires mode == Pmode.
17173 NEG or PLUS already counted so only add one. */
17175 && (outer_code == NEG || outer_code == PLUS))
17177 *total = COSTS_N_INSNS (1);
17180 if (outer_code == SET)
17182 if (XEXP (x, 1) == const0_rtx)
17184 *total = COSTS_N_INSNS (2);
17187 else if (mode == Pmode)
17189 *total = COSTS_N_INSNS (3);
17198 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
17200 *total = COSTS_N_INSNS (2);
17204 if (outer_code == COMPARE)
17218 /* A C expression returning the cost of moving data from a register of class
17219 CLASS1 to one of CLASS2. */
17222 rs6000_register_move_cost (enum machine_mode mode,
17223 enum reg_class from, enum reg_class to)
17225 /* Moves from/to GENERAL_REGS. */
17226 if (reg_classes_intersect_p (to, GENERAL_REGS)
17227 || reg_classes_intersect_p (from, GENERAL_REGS))
17229 if (! reg_classes_intersect_p (to, GENERAL_REGS))
17232 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
17233 return (rs6000_memory_move_cost (mode, from, 0)
17234 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
17236 /* It's more expensive to move CR_REGS than CR0_REGS because of the
17238 else if (from == CR_REGS)
17242 /* A move will cost one instruction per GPR moved. */
17243 return 2 * HARD_REGNO_NREGS (0, mode);
17246 /* Moving between two similar registers is just one instruction. */
17247 else if (reg_classes_intersect_p (to, from))
17248 return mode == TFmode ? 4 : 2;
17250 /* Everything else has to go through GENERAL_REGS. */
17252 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
17253 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
17256 /* A C expressions returning the cost of moving data of MODE from a register to
17260 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
17261 int in ATTRIBUTE_UNUSED)
17263 if (reg_classes_intersect_p (class, GENERAL_REGS))
17264 return 4 * HARD_REGNO_NREGS (0, mode);
17265 else if (reg_classes_intersect_p (class, FLOAT_REGS))
17266 return 4 * HARD_REGNO_NREGS (32, mode);
17267 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
17268 return 4 * HARD_REGNO_NREGS (FIRST_ALTIVEC_REGNO, mode);
17270 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
17273 /* Return an RTX representing where to find the function value of a
17274 function returning MODE. */
17276 rs6000_complex_function_value (enum machine_mode mode)
17278 unsigned int regno;
17280 enum machine_mode inner = GET_MODE_INNER (mode);
17281 unsigned int inner_bytes = GET_MODE_SIZE (inner);
17283 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
17284 regno = FP_ARG_RETURN;
17287 regno = GP_ARG_RETURN;
17289 /* 32-bit is OK since it'll go in r3/r4. */
17290 if (TARGET_32BIT && inner_bytes >= 4)
17291 return gen_rtx_REG (mode, regno);
17294 if (inner_bytes >= 8)
17295 return gen_rtx_REG (mode, regno);
17297 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
17299 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
17300 GEN_INT (inner_bytes));
17301 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
17304 /* Define how to find the value returned by a function.
17305 VALTYPE is the data type of the value (as a tree).
17306 If the precise function being called is known, FUNC is its FUNCTION_DECL;
17307 otherwise, FUNC is 0.
17309 On the SPE, both FPs and vectors are returned in r3.
17311 On RS/6000 an integer value is in r3 and a floating-point value is in
17312 fp1, unless -msoft-float. */
17315 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
17317 enum machine_mode mode;
17318 unsigned int regno;
17320 /* Special handling for structs in darwin64. */
17321 if (rs6000_darwin64_abi
17322 && TYPE_MODE (valtype) == BLKmode
17323 && TREE_CODE (valtype) == RECORD_TYPE
17324 && int_size_in_bytes (valtype) > 0)
17326 CUMULATIVE_ARGS valcum;
17330 valcum.fregno = FP_ARG_MIN_REG;
17331 valcum.vregno = ALTIVEC_ARG_MIN_REG;
17332 /* Do a trial code generation as if this were going to be passed as
17333 an argument; if any part goes in memory, we return NULL. */
17334 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
17337 /* Otherwise fall through to standard ABI rules. */
17340 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
17342 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17343 return gen_rtx_PARALLEL (DImode,
17345 gen_rtx_EXPR_LIST (VOIDmode,
17346 gen_rtx_REG (SImode, GP_ARG_RETURN),
17348 gen_rtx_EXPR_LIST (VOIDmode,
17349 gen_rtx_REG (SImode,
17350 GP_ARG_RETURN + 1),
17354 if ((INTEGRAL_TYPE_P (valtype)
17355 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
17356 || POINTER_TYPE_P (valtype))
17357 mode = TARGET_32BIT ? SImode : DImode;
17359 mode = TYPE_MODE (valtype);
17361 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
17362 regno = FP_ARG_RETURN;
17363 else if (TREE_CODE (valtype) == COMPLEX_TYPE
17364 && targetm.calls.split_complex_arg)
17365 return rs6000_complex_function_value (mode);
17366 else if (TREE_CODE (valtype) == VECTOR_TYPE
17367 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
17368 && ALTIVEC_VECTOR_MODE (mode))
17369 regno = ALTIVEC_ARG_RETURN;
17370 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17371 && (mode == DFmode || mode == DCmode))
17372 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17374 regno = GP_ARG_RETURN;
17376 return gen_rtx_REG (mode, regno);
17379 /* Define how to find the value returned by a library function
17380 assuming the value has mode MODE. */
17382 rs6000_libcall_value (enum machine_mode mode)
17384 unsigned int regno;
17386 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
17388 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
17389 return gen_rtx_PARALLEL (DImode,
17391 gen_rtx_EXPR_LIST (VOIDmode,
17392 gen_rtx_REG (SImode, GP_ARG_RETURN),
17394 gen_rtx_EXPR_LIST (VOIDmode,
17395 gen_rtx_REG (SImode,
17396 GP_ARG_RETURN + 1),
17400 if (GET_MODE_CLASS (mode) == MODE_FLOAT
17401 && TARGET_HARD_FLOAT && TARGET_FPRS)
17402 regno = FP_ARG_RETURN;
17403 else if (ALTIVEC_VECTOR_MODE (mode)
17404 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
17405 regno = ALTIVEC_ARG_RETURN;
17406 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
17407 return rs6000_complex_function_value (mode);
17408 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
17409 && (mode == DFmode || mode == DCmode))
17410 return spe_build_register_parallel (mode, GP_ARG_RETURN);
17412 regno = GP_ARG_RETURN;
17414 return gen_rtx_REG (mode, regno);
17417 /* Define the offset between two registers, FROM to be eliminated and its
17418 replacement TO, at the start of a routine. */
17420 rs6000_initial_elimination_offset (int from, int to)
17422 rs6000_stack_t *info = rs6000_stack_info ();
17423 HOST_WIDE_INT offset;
17425 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17426 offset = info->push_p ? 0 : -info->total_size;
17427 else if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
17428 offset = info->total_size;
17429 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
17430 offset = info->push_p ? info->total_size : 0;
17431 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
17439 /* Return true if TYPE is of type __ev64_opaque__. */
17442 is_ev64_opaque_type (tree type)
17445 && (type == opaque_V2SI_type_node
17446 || type == opaque_V2SF_type_node
17447 || type == opaque_p_V2SI_type_node));
17451 rs6000_dwarf_register_span (rtx reg)
17456 && (SPE_VECTOR_MODE (GET_MODE (reg))
17457 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
17462 regno = REGNO (reg);
17464 /* The duality of the SPE register size wreaks all kinds of havoc.
17465 This is a way of distinguishing r0 in 32-bits from r0 in
17468 gen_rtx_PARALLEL (VOIDmode,
17471 gen_rtx_REG (SImode, regno + 1200),
17472 gen_rtx_REG (SImode, regno))
17474 gen_rtx_REG (SImode, regno),
17475 gen_rtx_REG (SImode, regno + 1200)));
17478 /* Map internal gcc register numbers to DWARF2 register numbers. */
17481 rs6000_dbx_register_number (unsigned int regno)
17483 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
17485 if (regno == MQ_REGNO)
17487 if (regno == LINK_REGISTER_REGNUM)
17489 if (regno == COUNT_REGISTER_REGNUM)
17491 if (CR_REGNO_P (regno))
17492 return regno - CR0_REGNO + 86;
17493 if (regno == XER_REGNO)
17495 if (ALTIVEC_REGNO_P (regno))
17496 return regno - FIRST_ALTIVEC_REGNO + 1124;
17497 if (regno == VRSAVE_REGNO)
17499 if (regno == VSCR_REGNO)
17501 if (regno == SPE_ACC_REGNO)
17503 if (regno == SPEFSCR_REGNO)
17505 /* SPE high reg number. We get these values of regno from
17506 rs6000_dwarf_register_span. */
17507 if (regno >= 1200 && regno < 1232)
17513 /* target hook eh_return_filter_mode */
17514 static enum machine_mode
17515 rs6000_eh_return_filter_mode (void)
17517 return TARGET_32BIT ? SImode : word_mode;
17520 /* Target hook for vector_mode_supported_p. */
17522 rs6000_vector_mode_supported_p (enum machine_mode mode)
17525 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
17528 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
17535 /* Target hook for invalid_arg_for_unprototyped_fn. */
17536 static const char *
17537 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
17539 return (!rs6000_darwin64_abi
17541 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
17542 && (funcdecl == NULL_TREE
17543 || (TREE_CODE (funcdecl) == FUNCTION_DECL
17544 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
17545 ? N_("AltiVec argument passed to unprototyped function")
17549 #include "gt-rs6000.h"