1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_maybe_dead (rtx);
620 static void rs6000_emit_stack_tie (void);
621 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
622 static rtx spe_synthesize_frame_save (rtx);
623 static bool spe_func_has_64bit_regs_p (void);
624 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
626 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
627 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
628 static unsigned rs6000_hash_constant (rtx);
629 static unsigned toc_hash_function (const void *);
630 static int toc_hash_eq (const void *, const void *);
631 static int constant_pool_expr_1 (rtx, int *, int *);
632 static bool constant_pool_expr_p (rtx);
633 static bool legitimate_small_data_p (enum machine_mode, rtx);
634 static bool legitimate_indexed_address_p (rtx, int);
635 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
636 static struct machine_function * rs6000_init_machine_status (void);
637 static bool rs6000_assemble_integer (rtx, unsigned int, int);
638 static bool no_global_regs_above (int);
639 #ifdef HAVE_GAS_HIDDEN
640 static void rs6000_assemble_visibility (tree, int);
642 static int rs6000_ra_ever_killed (void);
643 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
644 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
645 static bool rs6000_ms_bitfield_layout_p (tree);
646 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
647 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
648 static const char *rs6000_mangle_fundamental_type (tree);
649 extern const struct attribute_spec rs6000_attribute_table[];
650 static void rs6000_set_default_type_attributes (tree);
651 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
652 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
653 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
655 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
656 static bool rs6000_return_in_memory (tree, tree);
657 static void rs6000_file_start (void);
659 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
660 static void rs6000_elf_asm_out_constructor (rtx, int);
661 static void rs6000_elf_asm_out_destructor (rtx, int);
662 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
663 static void rs6000_elf_asm_init_sections (void);
664 static section *rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
665 static void rs6000_elf_unique_section (tree, int);
666 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
667 unsigned HOST_WIDE_INT);
668 static void rs6000_elf_encode_section_info (tree, rtx, int)
671 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
673 static void rs6000_xcoff_asm_output_anchor (rtx);
674 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
675 static void rs6000_xcoff_asm_init_sections (void);
676 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
677 static section *rs6000_xcoff_select_section (tree, int,
678 unsigned HOST_WIDE_INT);
679 static void rs6000_xcoff_unique_section (tree, int);
680 static section *rs6000_xcoff_select_rtx_section
681 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
682 static const char * rs6000_xcoff_strip_name_encoding (const char *);
683 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
684 static void rs6000_xcoff_file_start (void);
685 static void rs6000_xcoff_file_end (void);
687 static int rs6000_variable_issue (FILE *, int, rtx, int);
688 static bool rs6000_rtx_costs (rtx, int, int, int *);
689 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
690 static void rs6000_sched_init (FILE *, int, int);
691 static bool is_microcoded_insn (rtx);
692 static bool is_nonpipeline_insn (rtx);
693 static bool is_cracked_insn (rtx);
694 static bool is_branch_slot_insn (rtx);
695 static bool is_load_insn (rtx);
696 static rtx get_store_dest (rtx pat);
697 static bool is_store_insn (rtx);
698 static bool set_to_load_agen (rtx,rtx);
699 static bool adjacent_mem_locations (rtx,rtx);
700 static int rs6000_adjust_priority (rtx, int);
701 static int rs6000_issue_rate (void);
702 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
703 static rtx get_next_active_insn (rtx, rtx);
704 static bool insn_terminates_group_p (rtx , enum group_termination);
705 static bool insn_must_be_first_in_group (rtx);
706 static bool insn_must_be_last_in_group (rtx);
707 static bool is_costly_group (rtx *, rtx);
708 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
709 static int redefine_groups (FILE *, int, rtx, rtx);
710 static int pad_groups (FILE *, int, rtx, rtx);
711 static void rs6000_sched_finish (FILE *, int);
712 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
713 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
714 static int rs6000_use_sched_lookahead (void);
715 static int rs6000_use_sched_lookahead_guard (rtx);
716 static tree rs6000_builtin_mask_for_load (void);
717 static tree rs6000_builtin_mul_widen_even (tree);
718 static tree rs6000_builtin_mul_widen_odd (tree);
720 static void def_builtin (int, const char *, tree, int);
721 static void rs6000_init_builtins (void);
722 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
723 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
725 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
726 static void altivec_init_builtins (void);
727 static void rs6000_common_init_builtins (void);
728 static void rs6000_init_libfuncs (void);
730 static void enable_mask_for_builtins (struct builtin_description *, int,
731 enum rs6000_builtins,
732 enum rs6000_builtins);
733 static tree build_opaque_vector_type (tree, int);
734 static void spe_init_builtins (void);
735 static rtx spe_expand_builtin (tree, rtx, bool *);
736 static rtx spe_expand_stv_builtin (enum insn_code, tree);
737 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
738 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
739 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
740 static rs6000_stack_t *rs6000_stack_info (void);
741 static void debug_stack_info (rs6000_stack_t *);
743 static rtx altivec_expand_builtin (tree, rtx, bool *);
744 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
747 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
748 static rtx altivec_expand_predicate_builtin (enum insn_code,
749 const char *, tree, rtx);
750 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
751 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
752 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
753 static rtx altivec_expand_vec_set_builtin (tree);
754 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
755 static int get_element_number (tree, tree);
756 static bool rs6000_handle_option (size_t, const char *, int);
757 static void rs6000_parse_tls_size_option (void);
758 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
759 static int first_altivec_reg_to_save (void);
760 static unsigned int compute_vrsave_mask (void);
761 static void compute_save_world_info (rs6000_stack_t *info_ptr);
762 static void is_altivec_return_reg (rtx, void *);
763 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
764 int easy_vector_constant (rtx, enum machine_mode);
765 static bool rs6000_is_opaque_type (tree);
766 static rtx rs6000_dwarf_register_span (rtx);
767 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
768 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
769 static rtx rs6000_tls_get_addr (void);
770 static rtx rs6000_got_sym (void);
771 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
772 static const char *rs6000_get_some_local_dynamic_name (void);
773 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
774 static rtx rs6000_complex_function_value (enum machine_mode);
775 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
776 enum machine_mode, tree);
777 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
779 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
780 tree, HOST_WIDE_INT);
781 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
784 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
787 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
788 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
789 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
790 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
791 enum machine_mode, tree,
793 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
795 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
797 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
799 static void macho_branch_islands (void);
800 static void add_compiler_branch_island (tree, tree, int);
801 static int no_previous_def (tree function_name);
802 static tree get_prev_label (tree function_name);
803 static void rs6000_darwin_file_start (void);
806 static tree rs6000_build_builtin_va_list (void);
807 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
808 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
809 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
810 static bool rs6000_vector_mode_supported_p (enum machine_mode);
811 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
813 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
815 static int get_vsel_insn (enum machine_mode);
816 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
817 static tree rs6000_stack_protect_fail (void);
819 const int INSN_NOT_AVAILABLE = -1;
820 static enum machine_mode rs6000_eh_return_filter_mode (void);
822 /* Hash table stuff for keeping track of TOC entries. */
824 struct toc_hash_struct GTY(())
826 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
827 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
829 enum machine_mode key_mode;
833 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
835 /* Default register names. */
836 char rs6000_reg_names[][8] =
838 "0", "1", "2", "3", "4", "5", "6", "7",
839 "8", "9", "10", "11", "12", "13", "14", "15",
840 "16", "17", "18", "19", "20", "21", "22", "23",
841 "24", "25", "26", "27", "28", "29", "30", "31",
842 "0", "1", "2", "3", "4", "5", "6", "7",
843 "8", "9", "10", "11", "12", "13", "14", "15",
844 "16", "17", "18", "19", "20", "21", "22", "23",
845 "24", "25", "26", "27", "28", "29", "30", "31",
846 "mq", "lr", "ctr","ap",
847 "0", "1", "2", "3", "4", "5", "6", "7",
849 /* AltiVec registers. */
850 "0", "1", "2", "3", "4", "5", "6", "7",
851 "8", "9", "10", "11", "12", "13", "14", "15",
852 "16", "17", "18", "19", "20", "21", "22", "23",
853 "24", "25", "26", "27", "28", "29", "30", "31",
856 "spe_acc", "spefscr",
857 /* Soft frame pointer. */
861 #ifdef TARGET_REGNAMES
862 static const char alt_reg_names[][8] =
864 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
865 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
866 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
867 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
868 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
869 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
870 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
871 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
872 "mq", "lr", "ctr", "ap",
873 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
875 /* AltiVec registers. */
876 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
877 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
878 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
879 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
882 "spe_acc", "spefscr",
883 /* Soft frame pointer. */
888 #ifndef MASK_STRICT_ALIGN
889 #define MASK_STRICT_ALIGN 0
891 #ifndef TARGET_PROFILE_KERNEL
892 #define TARGET_PROFILE_KERNEL 0
895 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
896 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
898 /* Initialize the GCC target structure. */
899 #undef TARGET_ATTRIBUTE_TABLE
900 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
901 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
902 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
904 #undef TARGET_ASM_ALIGNED_DI_OP
905 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
907 /* Default unaligned ops are only provided for ELF. Find the ops needed
908 for non-ELF systems. */
909 #ifndef OBJECT_FORMAT_ELF
911 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
913 #undef TARGET_ASM_UNALIGNED_HI_OP
914 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
915 #undef TARGET_ASM_UNALIGNED_SI_OP
916 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
917 #undef TARGET_ASM_UNALIGNED_DI_OP
918 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
921 #undef TARGET_ASM_UNALIGNED_HI_OP
922 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
923 #undef TARGET_ASM_UNALIGNED_SI_OP
924 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
925 #undef TARGET_ASM_UNALIGNED_DI_OP
926 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
927 #undef TARGET_ASM_ALIGNED_DI_OP
928 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
932 /* This hook deals with fixups for relocatable code and DI-mode objects
934 #undef TARGET_ASM_INTEGER
935 #define TARGET_ASM_INTEGER rs6000_assemble_integer
937 #ifdef HAVE_GAS_HIDDEN
938 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
939 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
942 #undef TARGET_HAVE_TLS
943 #define TARGET_HAVE_TLS HAVE_AS_TLS
945 #undef TARGET_CANNOT_FORCE_CONST_MEM
946 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
948 #undef TARGET_ASM_FUNCTION_PROLOGUE
949 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
950 #undef TARGET_ASM_FUNCTION_EPILOGUE
951 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
953 #undef TARGET_SCHED_VARIABLE_ISSUE
954 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
956 #undef TARGET_SCHED_ISSUE_RATE
957 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
958 #undef TARGET_SCHED_ADJUST_COST
959 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
960 #undef TARGET_SCHED_ADJUST_PRIORITY
961 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
962 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
963 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
964 #undef TARGET_SCHED_INIT
965 #define TARGET_SCHED_INIT rs6000_sched_init
966 #undef TARGET_SCHED_FINISH
967 #define TARGET_SCHED_FINISH rs6000_sched_finish
968 #undef TARGET_SCHED_REORDER
969 #define TARGET_SCHED_REORDER rs6000_sched_reorder
970 #undef TARGET_SCHED_REORDER2
971 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
973 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
974 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
976 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
977 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
979 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
980 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
981 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
982 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
983 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
984 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
986 #undef TARGET_INIT_BUILTINS
987 #define TARGET_INIT_BUILTINS rs6000_init_builtins
989 #undef TARGET_EXPAND_BUILTIN
990 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
992 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
993 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
995 #undef TARGET_INIT_LIBFUNCS
996 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
999 #undef TARGET_BINDS_LOCAL_P
1000 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1003 #undef TARGET_MS_BITFIELD_LAYOUT_P
1004 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1006 #undef TARGET_ASM_OUTPUT_MI_THUNK
1007 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1009 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1010 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1012 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1013 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1015 #undef TARGET_INVALID_WITHIN_DOLOOP
1016 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1018 #undef TARGET_RTX_COSTS
1019 #define TARGET_RTX_COSTS rs6000_rtx_costs
1020 #undef TARGET_ADDRESS_COST
1021 #define TARGET_ADDRESS_COST hook_int_rtx_0
1023 #undef TARGET_VECTOR_OPAQUE_P
1024 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1026 #undef TARGET_DWARF_REGISTER_SPAN
1027 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1029 /* On rs6000, function arguments are promoted, as are function return
1031 #undef TARGET_PROMOTE_FUNCTION_ARGS
1032 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1033 #undef TARGET_PROMOTE_FUNCTION_RETURN
1034 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1036 #undef TARGET_RETURN_IN_MEMORY
1037 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1039 #undef TARGET_SETUP_INCOMING_VARARGS
1040 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1042 /* Always strict argument naming on rs6000. */
1043 #undef TARGET_STRICT_ARGUMENT_NAMING
1044 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1045 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1046 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1047 #undef TARGET_SPLIT_COMPLEX_ARG
1048 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1049 #undef TARGET_MUST_PASS_IN_STACK
1050 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1051 #undef TARGET_PASS_BY_REFERENCE
1052 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1053 #undef TARGET_ARG_PARTIAL_BYTES
1054 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1056 #undef TARGET_BUILD_BUILTIN_VA_LIST
1057 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1059 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1060 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1062 #undef TARGET_EH_RETURN_FILTER_MODE
1063 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1065 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1066 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1068 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1069 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1071 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1072 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1074 #undef TARGET_HANDLE_OPTION
1075 #define TARGET_HANDLE_OPTION rs6000_handle_option
1077 #undef TARGET_DEFAULT_TARGET_FLAGS
1078 #define TARGET_DEFAULT_TARGET_FLAGS \
1081 #undef TARGET_STACK_PROTECT_FAIL
1082 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1084 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1085 The PowerPC architecture requires only weak consistency among
1086 processors--that is, memory accesses between processors need not be
1087 sequentially consistent and memory accesses among processors can occur
1088 in any order. The ability to order memory accesses weakly provides
1089 opportunities for more efficient use of the system bus. Unless a
1090 dependency exists, the 604e allows read operations to precede store
1092 #undef TARGET_RELAXED_ORDERING
1093 #define TARGET_RELAXED_ORDERING true
1096 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1097 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1100 /* Use a 32-bit anchor range. This leads to sequences like:
1102 addis tmp,anchor,high
1105 where tmp itself acts as an anchor, and can be shared between
1106 accesses to the same 64k page. */
1107 #undef TARGET_MIN_ANCHOR_OFFSET
1108 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1109 #undef TARGET_MAX_ANCHOR_OFFSET
1110 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1111 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1112 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1114 struct gcc_target targetm = TARGET_INITIALIZER;
1117 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1120 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1122 /* The GPRs can hold any mode, but values bigger than one register
1123 cannot go past R31. */
1124 if (INT_REGNO_P (regno))
1125 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1127 /* The float registers can only hold floating modes and DImode.
1128 This also excludes decimal float modes. */
1129 if (FP_REGNO_P (regno))
1131 (SCALAR_FLOAT_MODE_P (mode)
1132 && !DECIMAL_FLOAT_MODE_P (mode)
1133 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1134 || (GET_MODE_CLASS (mode) == MODE_INT
1135 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1137 /* The CR register can only hold CC modes. */
1138 if (CR_REGNO_P (regno))
1139 return GET_MODE_CLASS (mode) == MODE_CC;
1141 if (XER_REGNO_P (regno))
1142 return mode == PSImode;
1144 /* AltiVec only in AldyVec registers. */
1145 if (ALTIVEC_REGNO_P (regno))
1146 return ALTIVEC_VECTOR_MODE (mode);
1148 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1149 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1152 /* We cannot put TImode anywhere except general register and it must be
1153 able to fit within the register set. */
1155 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1158 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1160 rs6000_init_hard_regno_mode_ok (void)
1164 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1165 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1166 if (rs6000_hard_regno_mode_ok (r, m))
1167 rs6000_hard_regno_mode_ok_p[m][r] = true;
1170 /* If not otherwise specified by a target, make 'long double' equivalent to
1173 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1174 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1177 /* Override command line options. Mostly we process the processor
1178 type and sometimes adjust other TARGET_ options. */
1181 rs6000_override_options (const char *default_cpu)
1184 struct rs6000_cpu_select *ptr;
1187 /* Simplifications for entries below. */
1190 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1191 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1194 /* This table occasionally claims that a processor does not support
1195 a particular feature even though it does, but the feature is slower
1196 than the alternative. Thus, it shouldn't be relied on as a
1197 complete description of the processor's support.
1199 Please keep this list in order, and don't forget to update the
1200 documentation in invoke.texi when adding a new processor or
1204 const char *const name; /* Canonical processor name. */
1205 const enum processor_type processor; /* Processor type enum value. */
1206 const int target_enable; /* Target flags to enable. */
1207 } const processor_target_table[]
1208 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1209 {"403", PROCESSOR_PPC403,
1210 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1211 {"405", PROCESSOR_PPC405,
1212 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1213 {"405fp", PROCESSOR_PPC405,
1214 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1215 {"440", PROCESSOR_PPC440,
1216 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1217 {"440fp", PROCESSOR_PPC440,
1218 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1219 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1220 {"601", PROCESSOR_PPC601,
1221 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1222 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1223 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1224 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1225 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1226 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1227 {"620", PROCESSOR_PPC620,
1228 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1229 {"630", PROCESSOR_PPC630,
1230 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1231 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1232 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1233 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1234 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1235 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1236 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1237 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1238 {"8540", PROCESSOR_PPC8540,
1239 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1240 /* 8548 has a dummy entry for now. */
1241 {"8548", PROCESSOR_PPC8540,
1242 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_STRICT_ALIGN},
1243 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1244 {"970", PROCESSOR_POWER4,
1245 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1246 {"cell", PROCESSOR_CELL,
1247 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1248 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1249 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1250 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1251 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1252 {"G5", PROCESSOR_POWER4,
1253 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1254 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1255 {"power2", PROCESSOR_POWER,
1256 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1257 {"power3", PROCESSOR_PPC630,
1258 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1259 {"power4", PROCESSOR_POWER4,
1260 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1261 {"power5", PROCESSOR_POWER5,
1262 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1263 | MASK_MFCRF | MASK_POPCNTB},
1264 {"power5+", PROCESSOR_POWER5,
1265 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1266 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1267 {"power6", PROCESSOR_POWER6,
1268 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1270 {"power6x", PROCESSOR_POWER6,
1271 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1272 | MASK_FPRND | MASK_MFPGPR},
1273 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1274 {"powerpc64", PROCESSOR_POWERPC64,
1275 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1276 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1277 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1278 {"rios2", PROCESSOR_RIOS2,
1279 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1280 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1281 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1282 {"rs64", PROCESSOR_RS64A,
1283 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1286 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1288 /* Some OSs don't support saving the high part of 64-bit registers on
1289 context switch. Other OSs don't support saving Altivec registers.
1290 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1291 settings; if the user wants either, the user must explicitly specify
1292 them and we won't interfere with the user's specification. */
1295 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1296 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1297 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1298 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1299 | MASK_DLMZB | MASK_MFPGPR)
1302 rs6000_init_hard_regno_mode_ok ();
1304 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1305 #ifdef OS_MISSING_POWERPC64
1306 if (OS_MISSING_POWERPC64)
1307 set_masks &= ~MASK_POWERPC64;
1309 #ifdef OS_MISSING_ALTIVEC
1310 if (OS_MISSING_ALTIVEC)
1311 set_masks &= ~MASK_ALTIVEC;
1314 /* Don't override by the processor default if given explicitly. */
1315 set_masks &= ~target_flags_explicit;
1317 /* Identify the processor type. */
1318 rs6000_select[0].string = default_cpu;
1319 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1321 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1323 ptr = &rs6000_select[i];
1324 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1326 for (j = 0; j < ptt_size; j++)
1327 if (! strcmp (ptr->string, processor_target_table[j].name))
1329 if (ptr->set_tune_p)
1330 rs6000_cpu = processor_target_table[j].processor;
1332 if (ptr->set_arch_p)
1334 target_flags &= ~set_masks;
1335 target_flags |= (processor_target_table[j].target_enable
1342 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1349 /* If we are optimizing big endian systems for space, use the load/store
1350 multiple and string instructions. */
1351 if (BYTES_BIG_ENDIAN && optimize_size)
1352 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1354 /* Don't allow -mmultiple or -mstring on little endian systems
1355 unless the cpu is a 750, because the hardware doesn't support the
1356 instructions used in little endian mode, and causes an alignment
1357 trap. The 750 does not cause an alignment trap (except when the
1358 target is unaligned). */
1360 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1362 if (TARGET_MULTIPLE)
1364 target_flags &= ~MASK_MULTIPLE;
1365 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1366 warning (0, "-mmultiple is not supported on little endian systems");
1371 target_flags &= ~MASK_STRING;
1372 if ((target_flags_explicit & MASK_STRING) != 0)
1373 warning (0, "-mstring is not supported on little endian systems");
1377 /* Set debug flags */
1378 if (rs6000_debug_name)
1380 if (! strcmp (rs6000_debug_name, "all"))
1381 rs6000_debug_stack = rs6000_debug_arg = 1;
1382 else if (! strcmp (rs6000_debug_name, "stack"))
1383 rs6000_debug_stack = 1;
1384 else if (! strcmp (rs6000_debug_name, "arg"))
1385 rs6000_debug_arg = 1;
1387 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1390 if (rs6000_traceback_name)
1392 if (! strncmp (rs6000_traceback_name, "full", 4))
1393 rs6000_traceback = traceback_full;
1394 else if (! strncmp (rs6000_traceback_name, "part", 4))
1395 rs6000_traceback = traceback_part;
1396 else if (! strncmp (rs6000_traceback_name, "no", 2))
1397 rs6000_traceback = traceback_none;
1399 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1400 rs6000_traceback_name);
1403 if (!rs6000_explicit_options.long_double)
1404 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1406 #ifndef POWERPC_LINUX
1407 if (!rs6000_explicit_options.ieee)
1408 rs6000_ieeequad = 1;
1411 /* Set Altivec ABI as default for powerpc64 linux. */
1412 if (TARGET_ELF && TARGET_64BIT)
1414 rs6000_altivec_abi = 1;
1415 TARGET_ALTIVEC_VRSAVE = 1;
1418 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1419 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1421 rs6000_darwin64_abi = 1;
1423 darwin_one_byte_bool = 1;
1425 /* Default to natural alignment, for better performance. */
1426 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1429 /* Place FP constants in the constant pool instead of TOC
1430 if section anchors enabled. */
1431 if (flag_section_anchors)
1432 TARGET_NO_FP_IN_TOC = 1;
1434 /* Handle -mtls-size option. */
1435 rs6000_parse_tls_size_option ();
1437 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1438 SUBTARGET_OVERRIDE_OPTIONS;
1440 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1441 SUBSUBTARGET_OVERRIDE_OPTIONS;
1443 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1444 SUB3TARGET_OVERRIDE_OPTIONS;
1450 error ("AltiVec and E500 instructions cannot coexist");
1452 /* The e500 does not have string instructions, and we set
1453 MASK_STRING above when optimizing for size. */
1454 if ((target_flags & MASK_STRING) != 0)
1455 target_flags = target_flags & ~MASK_STRING;
1457 else if (rs6000_select[1].string != NULL)
1459 /* For the powerpc-eabispe configuration, we set all these by
1460 default, so let's unset them if we manually set another
1461 CPU that is not the E500. */
1462 if (!rs6000_explicit_options.abi)
1464 if (!rs6000_explicit_options.spe)
1466 if (!rs6000_explicit_options.float_gprs)
1467 rs6000_float_gprs = 0;
1468 if (!rs6000_explicit_options.isel)
1470 if (!rs6000_explicit_options.long_double)
1471 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1474 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1475 && rs6000_cpu != PROCESSOR_POWER5
1476 && rs6000_cpu != PROCESSOR_POWER6
1477 && rs6000_cpu != PROCESSOR_CELL);
1478 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1479 || rs6000_cpu == PROCESSOR_POWER5);
1480 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1481 || rs6000_cpu == PROCESSOR_POWER5
1482 || rs6000_cpu == PROCESSOR_POWER6);
1484 rs6000_sched_restricted_insns_priority
1485 = (rs6000_sched_groups ? 1 : 0);
1487 /* Handle -msched-costly-dep option. */
1488 rs6000_sched_costly_dep
1489 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1491 if (rs6000_sched_costly_dep_str)
1493 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1494 rs6000_sched_costly_dep = no_dep_costly;
1495 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1496 rs6000_sched_costly_dep = all_deps_costly;
1497 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1498 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1499 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1500 rs6000_sched_costly_dep = store_to_load_dep_costly;
1502 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1505 /* Handle -minsert-sched-nops option. */
1506 rs6000_sched_insert_nops
1507 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1509 if (rs6000_sched_insert_nops_str)
1511 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1512 rs6000_sched_insert_nops = sched_finish_none;
1513 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1514 rs6000_sched_insert_nops = sched_finish_pad_groups;
1515 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1516 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1518 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1521 #ifdef TARGET_REGNAMES
1522 /* If the user desires alternate register names, copy in the
1523 alternate names now. */
1524 if (TARGET_REGNAMES)
1525 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1528 /* Set aix_struct_return last, after the ABI is determined.
1529 If -maix-struct-return or -msvr4-struct-return was explicitly
1530 used, don't override with the ABI default. */
1531 if (!rs6000_explicit_options.aix_struct_ret)
1532 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1534 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1535 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1538 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1540 /* We can only guarantee the availability of DI pseudo-ops when
1541 assembling for 64-bit targets. */
1544 targetm.asm_out.aligned_op.di = NULL;
1545 targetm.asm_out.unaligned_op.di = NULL;
1548 /* Set branch target alignment, if not optimizing for size. */
1551 /* Cell wants to be aligned 8byte for dual issue. */
1552 if (rs6000_cpu == PROCESSOR_CELL)
1554 if (align_functions <= 0)
1555 align_functions = 8;
1556 if (align_jumps <= 0)
1558 if (align_loops <= 0)
1561 if (rs6000_align_branch_targets)
1563 if (align_functions <= 0)
1564 align_functions = 16;
1565 if (align_jumps <= 0)
1567 if (align_loops <= 0)
1570 if (align_jumps_max_skip <= 0)
1571 align_jumps_max_skip = 15;
1572 if (align_loops_max_skip <= 0)
1573 align_loops_max_skip = 15;
1576 /* Arrange to save and restore machine status around nested functions. */
1577 init_machine_status = rs6000_init_machine_status;
1579 /* We should always be splitting complex arguments, but we can't break
1580 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1581 if (DEFAULT_ABI != ABI_AIX)
1582 targetm.calls.split_complex_arg = NULL;
1584 /* Initialize rs6000_cost with the appropriate target costs. */
1586 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1590 case PROCESSOR_RIOS1:
1591 rs6000_cost = &rios1_cost;
1594 case PROCESSOR_RIOS2:
1595 rs6000_cost = &rios2_cost;
1598 case PROCESSOR_RS64A:
1599 rs6000_cost = &rs64a_cost;
1602 case PROCESSOR_MPCCORE:
1603 rs6000_cost = &mpccore_cost;
1606 case PROCESSOR_PPC403:
1607 rs6000_cost = &ppc403_cost;
1610 case PROCESSOR_PPC405:
1611 rs6000_cost = &ppc405_cost;
1614 case PROCESSOR_PPC440:
1615 rs6000_cost = &ppc440_cost;
1618 case PROCESSOR_PPC601:
1619 rs6000_cost = &ppc601_cost;
1622 case PROCESSOR_PPC603:
1623 rs6000_cost = &ppc603_cost;
1626 case PROCESSOR_PPC604:
1627 rs6000_cost = &ppc604_cost;
1630 case PROCESSOR_PPC604e:
1631 rs6000_cost = &ppc604e_cost;
1634 case PROCESSOR_PPC620:
1635 rs6000_cost = &ppc620_cost;
1638 case PROCESSOR_PPC630:
1639 rs6000_cost = &ppc630_cost;
1642 case PROCESSOR_CELL:
1643 rs6000_cost = &ppccell_cost;
1646 case PROCESSOR_PPC750:
1647 case PROCESSOR_PPC7400:
1648 rs6000_cost = &ppc750_cost;
1651 case PROCESSOR_PPC7450:
1652 rs6000_cost = &ppc7450_cost;
1655 case PROCESSOR_PPC8540:
1656 rs6000_cost = &ppc8540_cost;
1659 case PROCESSOR_POWER4:
1660 case PROCESSOR_POWER5:
1661 rs6000_cost = &power4_cost;
1664 case PROCESSOR_POWER6:
1665 rs6000_cost = &power6_cost;
1673 /* Implement targetm.vectorize.builtin_mask_for_load. */
1675 rs6000_builtin_mask_for_load (void)
1678 return altivec_builtin_mask_for_load;
1683 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1685 rs6000_builtin_mul_widen_even (tree type)
1687 if (!TARGET_ALTIVEC)
1690 switch (TYPE_MODE (type))
1693 return TYPE_UNSIGNED (type) ?
1694 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1695 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1698 return TYPE_UNSIGNED (type) ?
1699 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1700 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1706 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1708 rs6000_builtin_mul_widen_odd (tree type)
1710 if (!TARGET_ALTIVEC)
1713 switch (TYPE_MODE (type))
1716 return TYPE_UNSIGNED (type) ?
1717 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1718 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1721 return TYPE_UNSIGNED (type) ?
1722 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1723 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1729 /* Handle generic options of the form -mfoo=yes/no.
1730 NAME is the option name.
1731 VALUE is the option value.
1732 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1733 whether the option value is 'yes' or 'no' respectively. */
1735 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1739 else if (!strcmp (value, "yes"))
1741 else if (!strcmp (value, "no"))
1744 error ("unknown -m%s= option specified: '%s'", name, value);
1747 /* Validate and record the size specified with the -mtls-size option. */
1750 rs6000_parse_tls_size_option (void)
1752 if (rs6000_tls_size_string == 0)
1754 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1755 rs6000_tls_size = 16;
1756 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1757 rs6000_tls_size = 32;
1758 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1759 rs6000_tls_size = 64;
1761 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1765 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1767 if (DEFAULT_ABI == ABI_DARWIN)
1768 /* The Darwin libraries never set errno, so we might as well
1769 avoid calling them when that's the only reason we would. */
1770 flag_errno_math = 0;
1772 /* Double growth factor to counter reduced min jump length. */
1773 set_param_value ("max-grow-copy-bb-insns", 16);
1775 /* Enable section anchors by default.
1776 Skip section anchors for Objective C and Objective C++
1777 until front-ends fixed. */
1778 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1779 flag_section_anchors = 1;
1782 /* Implement TARGET_HANDLE_OPTION. */
1785 rs6000_handle_option (size_t code, const char *arg, int value)
1790 target_flags &= ~(MASK_POWER | MASK_POWER2
1791 | MASK_MULTIPLE | MASK_STRING);
1792 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1793 | MASK_MULTIPLE | MASK_STRING);
1795 case OPT_mno_powerpc:
1796 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1797 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1798 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1799 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1802 target_flags &= ~MASK_MINIMAL_TOC;
1803 TARGET_NO_FP_IN_TOC = 0;
1804 TARGET_NO_SUM_IN_TOC = 0;
1805 target_flags_explicit |= MASK_MINIMAL_TOC;
1806 #ifdef TARGET_USES_SYSV4_OPT
1807 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1808 just the same as -mminimal-toc. */
1809 target_flags |= MASK_MINIMAL_TOC;
1810 target_flags_explicit |= MASK_MINIMAL_TOC;
1814 #ifdef TARGET_USES_SYSV4_OPT
1816 /* Make -mtoc behave like -mminimal-toc. */
1817 target_flags |= MASK_MINIMAL_TOC;
1818 target_flags_explicit |= MASK_MINIMAL_TOC;
1822 #ifdef TARGET_USES_AIX64_OPT
1827 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1828 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1829 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1832 #ifdef TARGET_USES_AIX64_OPT
1837 target_flags &= ~MASK_POWERPC64;
1838 target_flags_explicit |= MASK_POWERPC64;
1841 case OPT_minsert_sched_nops_:
1842 rs6000_sched_insert_nops_str = arg;
1845 case OPT_mminimal_toc:
1848 TARGET_NO_FP_IN_TOC = 0;
1849 TARGET_NO_SUM_IN_TOC = 0;
1856 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1857 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1864 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1865 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1869 case OPT_mpowerpc_gpopt:
1870 case OPT_mpowerpc_gfxopt:
1873 target_flags |= MASK_POWERPC;
1874 target_flags_explicit |= MASK_POWERPC;
1878 case OPT_maix_struct_return:
1879 case OPT_msvr4_struct_return:
1880 rs6000_explicit_options.aix_struct_ret = true;
1884 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1888 rs6000_explicit_options.isel = true;
1889 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1893 rs6000_explicit_options.spe = true;
1894 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1895 /* No SPE means 64-bit long doubles, even if an E500. */
1897 rs6000_long_double_type_size = 64;
1901 rs6000_debug_name = arg;
1904 #ifdef TARGET_USES_SYSV4_OPT
1906 rs6000_abi_name = arg;
1910 rs6000_sdata_name = arg;
1913 case OPT_mtls_size_:
1914 rs6000_tls_size_string = arg;
1917 case OPT_mrelocatable:
1920 target_flags |= MASK_MINIMAL_TOC;
1921 target_flags_explicit |= MASK_MINIMAL_TOC;
1922 TARGET_NO_FP_IN_TOC = 1;
1926 case OPT_mrelocatable_lib:
1929 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1930 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
1931 TARGET_NO_FP_IN_TOC = 1;
1935 target_flags &= ~MASK_RELOCATABLE;
1936 target_flags_explicit |= MASK_RELOCATABLE;
1942 if (!strcmp (arg, "altivec"))
1944 rs6000_explicit_options.abi = true;
1945 rs6000_altivec_abi = 1;
1948 else if (! strcmp (arg, "no-altivec"))
1950 /* ??? Don't set rs6000_explicit_options.abi here, to allow
1951 the default for rs6000_spe_abi to be chosen later. */
1952 rs6000_altivec_abi = 0;
1954 else if (! strcmp (arg, "spe"))
1956 rs6000_explicit_options.abi = true;
1958 rs6000_altivec_abi = 0;
1959 if (!TARGET_SPE_ABI)
1960 error ("not configured for ABI: '%s'", arg);
1962 else if (! strcmp (arg, "no-spe"))
1964 rs6000_explicit_options.abi = true;
1968 /* These are here for testing during development only, do not
1969 document in the manual please. */
1970 else if (! strcmp (arg, "d64"))
1972 rs6000_darwin64_abi = 1;
1973 warning (0, "Using darwin64 ABI");
1975 else if (! strcmp (arg, "d32"))
1977 rs6000_darwin64_abi = 0;
1978 warning (0, "Using old darwin ABI");
1981 else if (! strcmp (arg, "ibmlongdouble"))
1983 rs6000_explicit_options.ieee = true;
1984 rs6000_ieeequad = 0;
1985 warning (0, "Using IBM extended precision long double");
1987 else if (! strcmp (arg, "ieeelongdouble"))
1989 rs6000_explicit_options.ieee = true;
1990 rs6000_ieeequad = 1;
1991 warning (0, "Using IEEE extended precision long double");
1996 error ("unknown ABI specified: '%s'", arg);
2002 rs6000_select[1].string = arg;
2006 rs6000_select[2].string = arg;
2009 case OPT_mtraceback_:
2010 rs6000_traceback_name = arg;
2013 case OPT_mfloat_gprs_:
2014 rs6000_explicit_options.float_gprs = true;
2015 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2016 rs6000_float_gprs = 1;
2017 else if (! strcmp (arg, "double"))
2018 rs6000_float_gprs = 2;
2019 else if (! strcmp (arg, "no"))
2020 rs6000_float_gprs = 0;
2023 error ("invalid option for -mfloat-gprs: '%s'", arg);
2028 case OPT_mlong_double_:
2029 rs6000_explicit_options.long_double = true;
2030 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2031 if (value != 64 && value != 128)
2033 error ("Unknown switch -mlong-double-%s", arg);
2034 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2038 rs6000_long_double_type_size = value;
2041 case OPT_msched_costly_dep_:
2042 rs6000_sched_costly_dep_str = arg;
2046 rs6000_explicit_options.alignment = true;
2047 if (! strcmp (arg, "power"))
2049 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2050 some C library functions, so warn about it. The flag may be
2051 useful for performance studies from time to time though, so
2052 don't disable it entirely. */
2053 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2054 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2055 " it is incompatible with the installed C and C++ libraries");
2056 rs6000_alignment_flags = MASK_ALIGN_POWER;
2058 else if (! strcmp (arg, "natural"))
2059 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2062 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2070 /* Do anything needed at the start of the asm file. */
2073 rs6000_file_start (void)
2077 const char *start = buffer;
2078 struct rs6000_cpu_select *ptr;
2079 const char *default_cpu = TARGET_CPU_DEFAULT;
2080 FILE *file = asm_out_file;
2082 default_file_start ();
2084 #ifdef TARGET_BI_ARCH
2085 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2089 if (flag_verbose_asm)
2091 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2092 rs6000_select[0].string = default_cpu;
2094 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2096 ptr = &rs6000_select[i];
2097 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2099 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2104 if (PPC405_ERRATUM77)
2106 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2110 #ifdef USING_ELFOS_H
2111 switch (rs6000_sdata)
2113 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2114 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2115 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2116 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2119 if (rs6000_sdata && g_switch_value)
2121 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2131 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2133 switch_to_section (toc_section);
2134 switch_to_section (text_section);
2139 /* Return nonzero if this function is known to have a null epilogue. */
2142 direct_return (void)
2144 if (reload_completed)
2146 rs6000_stack_t *info = rs6000_stack_info ();
2148 if (info->first_gp_reg_save == 32
2149 && info->first_fp_reg_save == 64
2150 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2151 && ! info->lr_save_p
2152 && ! info->cr_save_p
2153 && info->vrsave_mask == 0
2161 /* Return the number of instructions it takes to form a constant in an
2162 integer register. */
2165 num_insns_constant_wide (HOST_WIDE_INT value)
2167 /* signed constant loadable with {cal|addi} */
2168 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2171 /* constant loadable with {cau|addis} */
2172 else if ((value & 0xffff) == 0
2173 && (value >> 31 == -1 || value >> 31 == 0))
2176 #if HOST_BITS_PER_WIDE_INT == 64
2177 else if (TARGET_POWERPC64)
2179 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2180 HOST_WIDE_INT high = value >> 31;
2182 if (high == 0 || high == -1)
2188 return num_insns_constant_wide (high) + 1;
2190 return (num_insns_constant_wide (high)
2191 + num_insns_constant_wide (low) + 1);
2200 num_insns_constant (rtx op, enum machine_mode mode)
2202 HOST_WIDE_INT low, high;
2204 switch (GET_CODE (op))
2207 #if HOST_BITS_PER_WIDE_INT == 64
2208 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2209 && mask64_operand (op, mode))
2213 return num_insns_constant_wide (INTVAL (op));
2221 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2222 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2223 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2226 if (mode == VOIDmode || mode == DImode)
2228 high = CONST_DOUBLE_HIGH (op);
2229 low = CONST_DOUBLE_LOW (op);
2236 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2237 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2238 high = l[WORDS_BIG_ENDIAN == 0];
2239 low = l[WORDS_BIG_ENDIAN != 0];
2243 return (num_insns_constant_wide (low)
2244 + num_insns_constant_wide (high));
2247 if ((high == 0 && low >= 0)
2248 || (high == -1 && low < 0))
2249 return num_insns_constant_wide (low);
2251 else if (mask64_operand (op, mode))
2255 return num_insns_constant_wide (high) + 1;
2258 return (num_insns_constant_wide (high)
2259 + num_insns_constant_wide (low) + 1);
2267 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2268 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2269 corresponding element of the vector, but for V4SFmode and V2SFmode,
2270 the corresponding "float" is interpreted as an SImode integer. */
2272 static HOST_WIDE_INT
2273 const_vector_elt_as_int (rtx op, unsigned int elt)
2275 rtx tmp = CONST_VECTOR_ELT (op, elt);
2276 if (GET_MODE (op) == V4SFmode
2277 || GET_MODE (op) == V2SFmode)
2278 tmp = gen_lowpart (SImode, tmp);
2279 return INTVAL (tmp);
2282 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2283 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2284 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2285 all items are set to the same value and contain COPIES replicas of the
2286 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2287 operand and the others are set to the value of the operand's msb. */
2290 vspltis_constant (rtx op, unsigned step, unsigned copies)
2292 enum machine_mode mode = GET_MODE (op);
2293 enum machine_mode inner = GET_MODE_INNER (mode);
2296 unsigned nunits = GET_MODE_NUNITS (mode);
2297 unsigned bitsize = GET_MODE_BITSIZE (inner);
2298 unsigned mask = GET_MODE_MASK (inner);
2300 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2301 HOST_WIDE_INT splat_val = val;
2302 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2304 /* Construct the value to be splatted, if possible. If not, return 0. */
2305 for (i = 2; i <= copies; i *= 2)
2307 HOST_WIDE_INT small_val;
2309 small_val = splat_val >> bitsize;
2311 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2313 splat_val = small_val;
2316 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2317 if (EASY_VECTOR_15 (splat_val))
2320 /* Also check if we can splat, and then add the result to itself. Do so if
2321 the value is positive, of if the splat instruction is using OP's mode;
2322 for splat_val < 0, the splat and the add should use the same mode. */
2323 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2324 && (splat_val >= 0 || (step == 1 && copies == 1)))
2330 /* Check if VAL is present in every STEP-th element, and the
2331 other elements are filled with its most significant bit. */
2332 for (i = 0; i < nunits - 1; ++i)
2334 HOST_WIDE_INT desired_val;
2335 if (((i + 1) & (step - 1)) == 0)
2338 desired_val = msb_val;
2340 if (desired_val != const_vector_elt_as_int (op, i))
2348 /* Return true if OP is of the given MODE and can be synthesized
2349 with a vspltisb, vspltish or vspltisw. */
2352 easy_altivec_constant (rtx op, enum machine_mode mode)
2354 unsigned step, copies;
2356 if (mode == VOIDmode)
2357 mode = GET_MODE (op);
2358 else if (mode != GET_MODE (op))
2361 /* Start with a vspltisw. */
2362 step = GET_MODE_NUNITS (mode) / 4;
2365 if (vspltis_constant (op, step, copies))
2368 /* Then try with a vspltish. */
2374 if (vspltis_constant (op, step, copies))
2377 /* And finally a vspltisb. */
2383 if (vspltis_constant (op, step, copies))
2389 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2390 result is OP. Abort if it is not possible. */
2393 gen_easy_altivec_constant (rtx op)
2395 enum machine_mode mode = GET_MODE (op);
2396 int nunits = GET_MODE_NUNITS (mode);
2397 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2398 unsigned step = nunits / 4;
2399 unsigned copies = 1;
2401 /* Start with a vspltisw. */
2402 if (vspltis_constant (op, step, copies))
2403 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2405 /* Then try with a vspltish. */
2411 if (vspltis_constant (op, step, copies))
2412 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2414 /* And finally a vspltisb. */
2420 if (vspltis_constant (op, step, copies))
2421 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2427 output_vec_const_move (rtx *operands)
2430 enum machine_mode mode;
2435 mode = GET_MODE (dest);
2440 if (zero_constant (vec, mode))
2441 return "vxor %0,%0,%0";
2443 splat_vec = gen_easy_altivec_constant (vec);
2444 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2445 operands[1] = XEXP (splat_vec, 0);
2446 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2449 switch (GET_MODE (splat_vec))
2452 return "vspltisw %0,%1";
2455 return "vspltish %0,%1";
2458 return "vspltisb %0,%1";
2465 gcc_assert (TARGET_SPE);
2467 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2468 pattern of V1DI, V4HI, and V2SF.
2470 FIXME: We should probably return # and add post reload
2471 splitters for these, but this way is so easy ;-). */
2472 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2473 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2474 operands[1] = CONST_VECTOR_ELT (vec, 0);
2475 operands[2] = CONST_VECTOR_ELT (vec, 1);
2477 return "li %0,%1\n\tevmergelo %0,%0,%0";
2479 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2482 /* Initialize vector TARGET to VALS. */
2485 rs6000_expand_vector_init (rtx target, rtx vals)
2487 enum machine_mode mode = GET_MODE (target);
2488 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2489 int n_elts = GET_MODE_NUNITS (mode);
2490 int n_var = 0, one_var = -1;
2491 bool all_same = true, all_const_zero = true;
2495 for (i = 0; i < n_elts; ++i)
2497 x = XVECEXP (vals, 0, i);
2498 if (!CONSTANT_P (x))
2499 ++n_var, one_var = i;
2500 else if (x != CONST0_RTX (inner_mode))
2501 all_const_zero = false;
2503 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2509 if (mode != V4SFmode && all_const_zero)
2511 /* Zero register. */
2512 emit_insn (gen_rtx_SET (VOIDmode, target,
2513 gen_rtx_XOR (mode, target, target)));
2516 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2518 /* Splat immediate. */
2519 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2523 ; /* Splat vector element. */
2526 /* Load from constant pool. */
2527 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2532 /* Store value to stack temp. Load vector element. Splat. */
2535 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2536 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2537 XVECEXP (vals, 0, 0));
2538 x = gen_rtx_UNSPEC (VOIDmode,
2539 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2540 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2542 gen_rtx_SET (VOIDmode,
2545 x = gen_rtx_VEC_SELECT (inner_mode, target,
2546 gen_rtx_PARALLEL (VOIDmode,
2547 gen_rtvec (1, const0_rtx)));
2548 emit_insn (gen_rtx_SET (VOIDmode, target,
2549 gen_rtx_VEC_DUPLICATE (mode, x)));
2553 /* One field is non-constant. Load constant then overwrite
2557 rtx copy = copy_rtx (vals);
2559 /* Load constant part of vector, substitute neighboring value for
2561 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2562 rs6000_expand_vector_init (target, copy);
2564 /* Insert variable. */
2565 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2569 /* Construct the vector in memory one field at a time
2570 and load the whole vector. */
2571 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2572 for (i = 0; i < n_elts; i++)
2573 emit_move_insn (adjust_address_nv (mem, inner_mode,
2574 i * GET_MODE_SIZE (inner_mode)),
2575 XVECEXP (vals, 0, i));
2576 emit_move_insn (target, mem);
2579 /* Set field ELT of TARGET to VAL. */
2582 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2584 enum machine_mode mode = GET_MODE (target);
2585 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2586 rtx reg = gen_reg_rtx (mode);
2588 int width = GET_MODE_SIZE (inner_mode);
2591 /* Load single variable value. */
2592 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2593 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2594 x = gen_rtx_UNSPEC (VOIDmode,
2595 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2596 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2598 gen_rtx_SET (VOIDmode,
2602 /* Linear sequence. */
2603 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2604 for (i = 0; i < 16; ++i)
2605 XVECEXP (mask, 0, i) = GEN_INT (i);
2607 /* Set permute mask to insert element into target. */
2608 for (i = 0; i < width; ++i)
2609 XVECEXP (mask, 0, elt*width + i)
2610 = GEN_INT (i + 0x10);
2611 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2612 x = gen_rtx_UNSPEC (mode,
2613 gen_rtvec (3, target, reg,
2614 force_reg (V16QImode, x)),
2616 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2619 /* Extract field ELT from VEC into TARGET. */
2622 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2624 enum machine_mode mode = GET_MODE (vec);
2625 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2628 /* Allocate mode-sized buffer. */
2629 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2631 /* Add offset to field within buffer matching vector element. */
2632 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2634 /* Store single field into mode-sized buffer. */
2635 x = gen_rtx_UNSPEC (VOIDmode,
2636 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2637 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2639 gen_rtx_SET (VOIDmode,
2642 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2645 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2646 implement ANDing by the mask IN. */
2648 build_mask64_2_operands (rtx in, rtx *out)
2650 #if HOST_BITS_PER_WIDE_INT >= 64
2651 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2654 gcc_assert (GET_CODE (in) == CONST_INT);
2659 /* Assume c initially something like 0x00fff000000fffff. The idea
2660 is to rotate the word so that the middle ^^^^^^ group of zeros
2661 is at the MS end and can be cleared with an rldicl mask. We then
2662 rotate back and clear off the MS ^^ group of zeros with a
2664 c = ~c; /* c == 0xff000ffffff00000 */
2665 lsb = c & -c; /* lsb == 0x0000000000100000 */
2666 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2667 c = ~c; /* c == 0x00fff000000fffff */
2668 c &= -lsb; /* c == 0x00fff00000000000 */
2669 lsb = c & -c; /* lsb == 0x0000100000000000 */
2670 c = ~c; /* c == 0xff000fffffffffff */
2671 c &= -lsb; /* c == 0xff00000000000000 */
2673 while ((lsb >>= 1) != 0)
2674 shift++; /* shift == 44 on exit from loop */
2675 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2676 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2677 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2681 /* Assume c initially something like 0xff000f0000000000. The idea
2682 is to rotate the word so that the ^^^ middle group of zeros
2683 is at the LS end and can be cleared with an rldicr mask. We then
2684 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2686 lsb = c & -c; /* lsb == 0x0000010000000000 */
2687 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2688 c = ~c; /* c == 0x00fff0ffffffffff */
2689 c &= -lsb; /* c == 0x00fff00000000000 */
2690 lsb = c & -c; /* lsb == 0x0000100000000000 */
2691 c = ~c; /* c == 0xff000fffffffffff */
2692 c &= -lsb; /* c == 0xff00000000000000 */
2694 while ((lsb >>= 1) != 0)
2695 shift++; /* shift == 44 on exit from loop */
2696 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2697 m1 >>= shift; /* m1 == 0x0000000000000fff */
2698 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2701 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2702 masks will be all 1's. We are guaranteed more than one transition. */
2703 out[0] = GEN_INT (64 - shift);
2704 out[1] = GEN_INT (m1);
2705 out[2] = GEN_INT (shift);
2706 out[3] = GEN_INT (m2);
2714 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2717 invalid_e500_subreg (rtx op, enum machine_mode mode)
2719 if (TARGET_E500_DOUBLE)
2721 /* Reject (subreg:SI (reg:DF)). */
2722 if (GET_CODE (op) == SUBREG
2724 && REG_P (SUBREG_REG (op))
2725 && GET_MODE (SUBREG_REG (op)) == DFmode)
2728 /* Reject (subreg:DF (reg:DI)). */
2729 if (GET_CODE (op) == SUBREG
2731 && REG_P (SUBREG_REG (op))
2732 && GET_MODE (SUBREG_REG (op)) == DImode)
2737 && GET_CODE (op) == SUBREG
2739 && REG_P (SUBREG_REG (op))
2740 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2746 /* AIX increases natural record alignment to doubleword if the first
2747 field is an FP double while the FP fields remain word aligned. */
2750 rs6000_special_round_type_align (tree type, unsigned int computed,
2751 unsigned int specified)
2753 unsigned int align = MAX (computed, specified);
2754 tree field = TYPE_FIELDS (type);
2756 /* Skip all non field decls */
2757 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2758 field = TREE_CHAIN (field);
2760 if (field != NULL && field != type)
2762 type = TREE_TYPE (field);
2763 while (TREE_CODE (type) == ARRAY_TYPE)
2764 type = TREE_TYPE (type);
2766 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2767 align = MAX (align, 64);
2773 /* Darwin increases record alignment to the natural alignment of
2777 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2778 unsigned int specified)
2780 unsigned int align = MAX (computed, specified);
2782 if (TYPE_PACKED (type))
2785 /* Find the first field, looking down into aggregates. */
2787 tree field = TYPE_FIELDS (type);
2788 /* Skip all non field decls */
2789 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2790 field = TREE_CHAIN (field);
2793 type = TREE_TYPE (field);
2794 while (TREE_CODE (type) == ARRAY_TYPE)
2795 type = TREE_TYPE (type);
2796 } while (AGGREGATE_TYPE_P (type));
2798 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2799 align = MAX (align, TYPE_ALIGN (type));
2804 /* Return 1 for an operand in small memory on V.4/eabi. */
2807 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2808 enum machine_mode mode ATTRIBUTE_UNUSED)
2813 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2816 if (DEFAULT_ABI != ABI_V4)
2819 if (GET_CODE (op) == SYMBOL_REF)
2822 else if (GET_CODE (op) != CONST
2823 || GET_CODE (XEXP (op, 0)) != PLUS
2824 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2825 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2830 rtx sum = XEXP (op, 0);
2831 HOST_WIDE_INT summand;
2833 /* We have to be careful here, because it is the referenced address
2834 that must be 32k from _SDA_BASE_, not just the symbol. */
2835 summand = INTVAL (XEXP (sum, 1));
2836 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2839 sym_ref = XEXP (sum, 0);
2842 return SYMBOL_REF_SMALL_P (sym_ref);
2848 /* Return true if either operand is a general purpose register. */
2851 gpr_or_gpr_p (rtx op0, rtx op1)
2853 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2854 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2858 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2861 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2863 switch (GET_CODE (op))
2866 if (RS6000_SYMBOL_REF_TLS_P (op))
2868 else if (CONSTANT_POOL_ADDRESS_P (op))
2870 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2878 else if (! strcmp (XSTR (op, 0), toc_label_name))
2887 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2888 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2890 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2899 constant_pool_expr_p (rtx op)
2903 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2907 toc_relative_expr_p (rtx op)
2911 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2915 legitimate_constant_pool_address_p (rtx x)
2918 && GET_CODE (x) == PLUS
2919 && GET_CODE (XEXP (x, 0)) == REG
2920 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2921 && constant_pool_expr_p (XEXP (x, 1)));
2925 legitimate_small_data_p (enum machine_mode mode, rtx x)
2927 return (DEFAULT_ABI == ABI_V4
2928 && !flag_pic && !TARGET_TOC
2929 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2930 && small_data_operand (x, mode));
2933 /* SPE offset addressing is limited to 5-bits worth of double words. */
2934 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2937 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2939 unsigned HOST_WIDE_INT offset, extra;
2941 if (GET_CODE (x) != PLUS)
2943 if (GET_CODE (XEXP (x, 0)) != REG)
2945 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2947 if (legitimate_constant_pool_address_p (x))
2949 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2952 offset = INTVAL (XEXP (x, 1));
2960 /* AltiVec vector modes. Only reg+reg addressing is valid and
2961 constant offset zero should not occur due to canonicalization.
2962 Allow any offset when not strict before reload. */
2969 /* SPE vector modes. */
2970 return SPE_CONST_OFFSET_OK (offset);
2973 if (TARGET_E500_DOUBLE)
2974 return SPE_CONST_OFFSET_OK (offset);
2977 /* On e500v2, we may have:
2979 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2981 Which gets addressed with evldd instructions. */
2982 if (TARGET_E500_DOUBLE)
2983 return SPE_CONST_OFFSET_OK (offset);
2985 if (mode == DFmode || !TARGET_POWERPC64)
2987 else if (offset & 3)
2993 if (mode == TFmode || !TARGET_POWERPC64)
2995 else if (offset & 3)
3006 return (offset < 0x10000) && (offset + extra < 0x10000);
3010 legitimate_indexed_address_p (rtx x, int strict)
3014 if (GET_CODE (x) != PLUS)
3020 /* Recognize the rtl generated by reload which we know will later be
3021 replaced with proper base and index regs. */
3023 && reload_in_progress
3024 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3028 return (REG_P (op0) && REG_P (op1)
3029 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3030 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3031 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3032 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3036 legitimate_indirect_address_p (rtx x, int strict)
3038 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3042 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3044 if (!TARGET_MACHO || !flag_pic
3045 || mode != SImode || GET_CODE (x) != MEM)
3049 if (GET_CODE (x) != LO_SUM)
3051 if (GET_CODE (XEXP (x, 0)) != REG)
3053 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3057 return CONSTANT_P (x);
3061 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3063 if (GET_CODE (x) != LO_SUM)
3065 if (GET_CODE (XEXP (x, 0)) != REG)
3067 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3069 /* Restrict addressing for DI because of our SUBREG hackery. */
3070 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3074 if (TARGET_ELF || TARGET_MACHO)
3076 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3080 if (GET_MODE_NUNITS (mode) != 1)
3082 if (GET_MODE_BITSIZE (mode) > 64
3083 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3084 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3087 return CONSTANT_P (x);
3094 /* Try machine-dependent ways of modifying an illegitimate address
3095 to be legitimate. If we find one, return the new, valid address.
3096 This is used from only one place: `memory_address' in explow.c.
3098 OLDX is the address as it was before break_out_memory_refs was
3099 called. In some cases it is useful to look at this to decide what
3102 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3104 It is always safe for this function to do nothing. It exists to
3105 recognize opportunities to optimize the output.
3107 On RS/6000, first check for the sum of a register with a constant
3108 integer that is out of range. If so, generate code to add the
3109 constant with the low-order 16 bits masked to the register and force
3110 this result into another register (this can be done with `cau').
3111 Then generate an address of REG+(CONST&0xffff), allowing for the
3112 possibility of bit 16 being a one.
3114 Then check for the sum of a register and something not constant, try to
3115 load the other things into a register and return the sum. */
3118 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3119 enum machine_mode mode)
3121 if (GET_CODE (x) == SYMBOL_REF)
3123 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3125 return rs6000_legitimize_tls_address (x, model);
3128 if (GET_CODE (x) == PLUS
3129 && GET_CODE (XEXP (x, 0)) == REG
3130 && GET_CODE (XEXP (x, 1)) == CONST_INT
3131 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3133 HOST_WIDE_INT high_int, low_int;
3135 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3136 high_int = INTVAL (XEXP (x, 1)) - low_int;
3137 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3138 GEN_INT (high_int)), 0);
3139 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3141 else if (GET_CODE (x) == PLUS
3142 && GET_CODE (XEXP (x, 0)) == REG
3143 && GET_CODE (XEXP (x, 1)) != CONST_INT
3144 && GET_MODE_NUNITS (mode) == 1
3145 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3147 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
3149 && (TARGET_POWERPC64 || mode != DImode)
3152 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3153 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3155 else if (ALTIVEC_VECTOR_MODE (mode))
3159 /* Make sure both operands are registers. */
3160 if (GET_CODE (x) == PLUS)
3161 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3162 force_reg (Pmode, XEXP (x, 1)));
3164 reg = force_reg (Pmode, x);
3167 else if (SPE_VECTOR_MODE (mode)
3168 || (TARGET_E500_DOUBLE && (mode == DFmode
3169 || mode == DImode)))
3173 /* We accept [reg + reg] and [reg + OFFSET]. */
3175 if (GET_CODE (x) == PLUS)
3177 rtx op1 = XEXP (x, 0);
3178 rtx op2 = XEXP (x, 1);
3180 op1 = force_reg (Pmode, op1);
3182 if (GET_CODE (op2) != REG
3183 && (GET_CODE (op2) != CONST_INT
3184 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3185 op2 = force_reg (Pmode, op2);
3187 return gen_rtx_PLUS (Pmode, op1, op2);
3190 return force_reg (Pmode, x);
3196 && GET_CODE (x) != CONST_INT
3197 && GET_CODE (x) != CONST_DOUBLE
3199 && GET_MODE_NUNITS (mode) == 1
3200 && (GET_MODE_BITSIZE (mode) <= 32
3201 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3203 rtx reg = gen_reg_rtx (Pmode);
3204 emit_insn (gen_elf_high (reg, x));
3205 return gen_rtx_LO_SUM (Pmode, reg, x);
3207 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3210 && ! MACHO_DYNAMIC_NO_PIC_P
3212 && GET_CODE (x) != CONST_INT
3213 && GET_CODE (x) != CONST_DOUBLE
3215 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3219 rtx reg = gen_reg_rtx (Pmode);
3220 emit_insn (gen_macho_high (reg, x));
3221 return gen_rtx_LO_SUM (Pmode, reg, x);
3224 && constant_pool_expr_p (x)
3225 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3227 return create_TOC_reference (x);
3233 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3234 We need to emit DTP-relative relocations. */
3237 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3242 fputs ("\t.long\t", file);
3245 fputs (DOUBLE_INT_ASM_OP, file);
3250 output_addr_const (file, x);
3251 fputs ("@dtprel+0x8000", file);
3254 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3256 static GTY(()) rtx rs6000_tls_symbol;
3258 rs6000_tls_get_addr (void)
3260 if (!rs6000_tls_symbol)
3261 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3263 return rs6000_tls_symbol;
3266 /* Construct the SYMBOL_REF for TLS GOT references. */
3268 static GTY(()) rtx rs6000_got_symbol;
3270 rs6000_got_sym (void)
3272 if (!rs6000_got_symbol)
3274 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3275 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3276 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3279 return rs6000_got_symbol;
3282 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3283 this (thread-local) address. */
3286 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3290 dest = gen_reg_rtx (Pmode);
3291 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3297 tlsreg = gen_rtx_REG (Pmode, 13);
3298 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3302 tlsreg = gen_rtx_REG (Pmode, 2);
3303 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3307 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3311 tmp = gen_reg_rtx (Pmode);
3314 tlsreg = gen_rtx_REG (Pmode, 13);
3315 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3319 tlsreg = gen_rtx_REG (Pmode, 2);
3320 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3324 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3326 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3331 rtx r3, got, tga, tmp1, tmp2, eqv;
3333 /* We currently use relocations like @got@tlsgd for tls, which
3334 means the linker will handle allocation of tls entries, placing
3335 them in the .got section. So use a pointer to the .got section,
3336 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3337 or to secondary GOT sections used by 32-bit -fPIC. */
3339 got = gen_rtx_REG (Pmode, 2);
3343 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3346 rtx gsym = rs6000_got_sym ();
3347 got = gen_reg_rtx (Pmode);
3349 rs6000_emit_move (got, gsym, Pmode);
3352 rtx tempLR, tmp3, mem;
3355 tempLR = gen_reg_rtx (Pmode);
3356 tmp1 = gen_reg_rtx (Pmode);
3357 tmp2 = gen_reg_rtx (Pmode);
3358 tmp3 = gen_reg_rtx (Pmode);
3359 mem = gen_const_mem (Pmode, tmp1);
3361 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3362 emit_move_insn (tmp1, tempLR);
3363 emit_move_insn (tmp2, mem);
3364 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3365 last = emit_move_insn (got, tmp3);
3366 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3368 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3370 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3376 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3378 r3 = gen_rtx_REG (Pmode, 3);
3380 insn = gen_tls_gd_64 (r3, got, addr);
3382 insn = gen_tls_gd_32 (r3, got, addr);
3385 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3386 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3387 insn = emit_call_insn (insn);
3388 CONST_OR_PURE_CALL_P (insn) = 1;
3389 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3390 insn = get_insns ();
3392 emit_libcall_block (insn, dest, r3, addr);
3394 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3396 r3 = gen_rtx_REG (Pmode, 3);
3398 insn = gen_tls_ld_64 (r3, got);
3400 insn = gen_tls_ld_32 (r3, got);
3403 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3404 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3405 insn = emit_call_insn (insn);
3406 CONST_OR_PURE_CALL_P (insn) = 1;
3407 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3408 insn = get_insns ();
3410 tmp1 = gen_reg_rtx (Pmode);
3411 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3413 emit_libcall_block (insn, tmp1, r3, eqv);
3414 if (rs6000_tls_size == 16)
3417 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3419 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3421 else if (rs6000_tls_size == 32)
3423 tmp2 = gen_reg_rtx (Pmode);
3425 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3427 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3430 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3432 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3436 tmp2 = gen_reg_rtx (Pmode);
3438 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3440 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3442 insn = gen_rtx_SET (Pmode, dest,
3443 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3449 /* IE, or 64 bit offset LE. */
3450 tmp2 = gen_reg_rtx (Pmode);
3452 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3454 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3457 insn = gen_tls_tls_64 (dest, tmp2, addr);
3459 insn = gen_tls_tls_32 (dest, tmp2, addr);
3467 /* Return 1 if X contains a thread-local symbol. */
3470 rs6000_tls_referenced_p (rtx x)
3472 if (! TARGET_HAVE_TLS)
3475 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3478 /* Return 1 if *X is a thread-local symbol. This is the same as
3479 rs6000_tls_symbol_ref except for the type of the unused argument. */
3482 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3484 return RS6000_SYMBOL_REF_TLS_P (*x);
3487 /* The convention appears to be to define this wherever it is used.
3488 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3489 is now used here. */
3490 #ifndef REG_MODE_OK_FOR_BASE_P
3491 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3494 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3495 replace the input X, or the original X if no replacement is called for.
3496 The output parameter *WIN is 1 if the calling macro should goto WIN,
3499 For RS/6000, we wish to handle large displacements off a base
3500 register by splitting the addend across an addiu/addis and the mem insn.
3501 This cuts number of extra insns needed from 3 to 1.
3503 On Darwin, we use this to generate code for floating point constants.
3504 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3505 The Darwin code is inside #if TARGET_MACHO because only then is
3506 machopic_function_base_name() defined. */
3508 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3509 int opnum, int type,
3510 int ind_levels ATTRIBUTE_UNUSED, int *win)
3512 /* We must recognize output that we have already generated ourselves. */
3513 if (GET_CODE (x) == PLUS
3514 && GET_CODE (XEXP (x, 0)) == PLUS
3515 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3516 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3517 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3519 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3520 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3521 opnum, (enum reload_type)type);
3527 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3528 && GET_CODE (x) == LO_SUM
3529 && GET_CODE (XEXP (x, 0)) == PLUS
3530 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3531 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3532 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3533 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3534 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3535 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3536 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3538 /* Result of previous invocation of this function on Darwin
3539 floating point constant. */
3540 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3541 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3542 opnum, (enum reload_type)type);
3548 /* Force ld/std non-word aligned offset into base register by wrapping
3550 if (GET_CODE (x) == PLUS
3551 && GET_CODE (XEXP (x, 0)) == REG
3552 && REGNO (XEXP (x, 0)) < 32
3553 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3554 && GET_CODE (XEXP (x, 1)) == CONST_INT
3555 && (INTVAL (XEXP (x, 1)) & 3) != 0
3556 && !ALTIVEC_VECTOR_MODE (mode)
3557 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3558 && TARGET_POWERPC64)
3560 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3561 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3562 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3563 opnum, (enum reload_type) type);
3568 if (GET_CODE (x) == PLUS
3569 && GET_CODE (XEXP (x, 0)) == REG
3570 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3571 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3572 && GET_CODE (XEXP (x, 1)) == CONST_INT
3573 && !SPE_VECTOR_MODE (mode)
3574 && !(TARGET_E500_DOUBLE && (mode == DFmode
3576 && !ALTIVEC_VECTOR_MODE (mode))
3578 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3579 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3581 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3583 /* Check for 32-bit overflow. */
3584 if (high + low != val)
3590 /* Reload the high part into a base reg; leave the low part
3591 in the mem directly. */
3593 x = gen_rtx_PLUS (GET_MODE (x),
3594 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3598 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3599 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3600 opnum, (enum reload_type)type);
3605 if (GET_CODE (x) == SYMBOL_REF
3606 && !ALTIVEC_VECTOR_MODE (mode)
3607 && !SPE_VECTOR_MODE (mode)
3609 && DEFAULT_ABI == ABI_DARWIN
3610 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3612 && DEFAULT_ABI == ABI_V4
3615 /* Don't do this for TFmode, since the result isn't offsettable.
3616 The same goes for DImode without 64-bit gprs and DFmode
3619 && (mode != DImode || TARGET_POWERPC64)
3620 && (mode != DFmode || TARGET_POWERPC64
3621 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3626 rtx offset = gen_rtx_CONST (Pmode,
3627 gen_rtx_MINUS (Pmode, x,
3628 machopic_function_base_sym ()));
3629 x = gen_rtx_LO_SUM (GET_MODE (x),
3630 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3631 gen_rtx_HIGH (Pmode, offset)), offset);
3635 x = gen_rtx_LO_SUM (GET_MODE (x),
3636 gen_rtx_HIGH (Pmode, x), x);
3638 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3639 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3640 opnum, (enum reload_type)type);
3645 /* Reload an offset address wrapped by an AND that represents the
3646 masking of the lower bits. Strip the outer AND and let reload
3647 convert the offset address into an indirect address. */
3649 && ALTIVEC_VECTOR_MODE (mode)
3650 && GET_CODE (x) == AND
3651 && GET_CODE (XEXP (x, 0)) == PLUS
3652 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3653 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3654 && GET_CODE (XEXP (x, 1)) == CONST_INT
3655 && INTVAL (XEXP (x, 1)) == -16)
3663 && constant_pool_expr_p (x)
3664 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3666 x = create_TOC_reference (x);
3674 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3675 that is a valid memory address for an instruction.
3676 The MODE argument is the machine mode for the MEM expression
3677 that wants to use this address.
3679 On the RS/6000, there are four valid address: a SYMBOL_REF that
3680 refers to a constant pool entry of an address (or the sum of it
3681 plus a constant), a short (16-bit signed) constant plus a register,
3682 the sum of two registers, or a register indirect, possibly with an
3683 auto-increment. For DFmode and DImode with a constant plus register,
3684 we must ensure that both words are addressable or PowerPC64 with offset
3687 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3688 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3689 adjacent memory cells are accessed by adding word-sized offsets
3690 during assembly output. */
3692 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3694 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3696 && ALTIVEC_VECTOR_MODE (mode)
3697 && GET_CODE (x) == AND
3698 && GET_CODE (XEXP (x, 1)) == CONST_INT
3699 && INTVAL (XEXP (x, 1)) == -16)
3702 if (RS6000_SYMBOL_REF_TLS_P (x))
3704 if (legitimate_indirect_address_p (x, reg_ok_strict))
3706 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3707 && !ALTIVEC_VECTOR_MODE (mode)
3708 && !SPE_VECTOR_MODE (mode)
3710 /* Restrict addressing for DI because of our SUBREG hackery. */
3711 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3713 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3715 if (legitimate_small_data_p (mode, x))
3717 if (legitimate_constant_pool_address_p (x))
3719 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3721 && GET_CODE (x) == PLUS
3722 && GET_CODE (XEXP (x, 0)) == REG
3723 && (XEXP (x, 0) == virtual_stack_vars_rtx
3724 || XEXP (x, 0) == arg_pointer_rtx)
3725 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3727 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3731 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3733 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3734 && (TARGET_POWERPC64 || mode != DImode)
3735 && legitimate_indexed_address_p (x, reg_ok_strict))
3737 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3742 /* Go to LABEL if ADDR (a legitimate address expression)
3743 has an effect that depends on the machine mode it is used for.
3745 On the RS/6000 this is true of all integral offsets (since AltiVec
3746 modes don't allow them) or is a pre-increment or decrement.
3748 ??? Except that due to conceptual problems in offsettable_address_p
3749 we can't really report the problems of integral offsets. So leave
3750 this assuming that the adjustable offset must be valid for the
3751 sub-words of a TFmode operand, which is what we had before. */
3754 rs6000_mode_dependent_address (rtx addr)
3756 switch (GET_CODE (addr))
3759 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3761 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3762 return val + 12 + 0x8000 >= 0x10000;
3771 return TARGET_UPDATE;
3780 /* More elaborate version of recog's offsettable_memref_p predicate
3781 that works around the ??? note of rs6000_mode_dependent_address.
3782 In particular it accepts
3784 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3786 in 32-bit mode, that the recog predicate rejects. */
3789 rs6000_offsettable_memref_p (rtx op)
3794 /* First mimic offsettable_memref_p. */
3795 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3798 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3799 the latter predicate knows nothing about the mode of the memory
3800 reference and, therefore, assumes that it is the largest supported
3801 mode (TFmode). As a consequence, legitimate offsettable memory
3802 references are rejected. rs6000_legitimate_offset_address_p contains
3803 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3804 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3807 /* Return number of consecutive hard regs needed starting at reg REGNO
3808 to hold something of mode MODE.
3809 This is ordinarily the length in words of a value of mode MODE
3810 but can be less for certain modes in special long registers.
3812 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3813 scalar instructions. The upper 32 bits are only available to the
3816 POWER and PowerPC GPRs hold 32 bits worth;
3817 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3820 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3822 if (FP_REGNO_P (regno))
3823 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3825 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3826 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3828 if (ALTIVEC_REGNO_P (regno))
3830 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3832 /* The value returned for SCmode in the E500 double case is 2 for
3833 ABI compatibility; storing an SCmode value in a single register
3834 would require function_arg and rs6000_spe_function_arg to handle
3835 SCmode so as to pass the value correctly in a pair of
3837 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3838 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3840 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3843 /* Change register usage conditional on target flags. */
3845 rs6000_conditional_register_usage (void)
3849 /* Set MQ register fixed (already call_used) if not POWER
3850 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3855 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3857 fixed_regs[13] = call_used_regs[13]
3858 = call_really_used_regs[13] = 1;
3860 /* Conditionally disable FPRs. */
3861 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3862 for (i = 32; i < 64; i++)
3863 fixed_regs[i] = call_used_regs[i]
3864 = call_really_used_regs[i] = 1;
3866 /* The TOC register is not killed across calls in a way that is
3867 visible to the compiler. */
3868 if (DEFAULT_ABI == ABI_AIX)
3869 call_really_used_regs[2] = 0;
3871 if (DEFAULT_ABI == ABI_V4
3872 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3874 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3876 if (DEFAULT_ABI == ABI_V4
3877 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3879 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3880 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3881 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3883 if (DEFAULT_ABI == ABI_DARWIN
3884 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3885 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3886 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3887 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3889 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3890 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3891 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3894 global_regs[VSCR_REGNO] = 1;
3898 global_regs[SPEFSCR_REGNO] = 1;
3899 fixed_regs[FIXED_SCRATCH]
3900 = call_used_regs[FIXED_SCRATCH]
3901 = call_really_used_regs[FIXED_SCRATCH] = 1;
3904 if (! TARGET_ALTIVEC)
3906 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3907 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3908 call_really_used_regs[VRSAVE_REGNO] = 1;
3911 if (TARGET_ALTIVEC_ABI)
3912 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3913 call_used_regs[i] = call_really_used_regs[i] = 1;
3916 /* Try to output insns to set TARGET equal to the constant C if it can
3917 be done in less than N insns. Do all computations in MODE.
3918 Returns the place where the output has been placed if it can be
3919 done and the insns have been emitted. If it would take more than N
3920 insns, zero is returned and no insns and emitted. */
3923 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3924 rtx source, int n ATTRIBUTE_UNUSED)
3926 rtx result, insn, set;
3927 HOST_WIDE_INT c0, c1;
3934 dest = gen_reg_rtx (mode);
3935 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3939 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3941 emit_insn (gen_rtx_SET (VOIDmode, result,
3942 GEN_INT (INTVAL (source)
3943 & (~ (HOST_WIDE_INT) 0xffff))));
3944 emit_insn (gen_rtx_SET (VOIDmode, dest,
3945 gen_rtx_IOR (SImode, result,
3946 GEN_INT (INTVAL (source) & 0xffff))));
3951 switch (GET_CODE (source))
3954 c0 = INTVAL (source);
3959 #if HOST_BITS_PER_WIDE_INT >= 64
3960 c0 = CONST_DOUBLE_LOW (source);
3963 c0 = CONST_DOUBLE_LOW (source);
3964 c1 = CONST_DOUBLE_HIGH (source);
3972 result = rs6000_emit_set_long_const (dest, c0, c1);
3979 insn = get_last_insn ();
3980 set = single_set (insn);
3981 if (! CONSTANT_P (SET_SRC (set)))
3982 set_unique_reg_note (insn, REG_EQUAL, source);
3987 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3988 fall back to a straight forward decomposition. We do this to avoid
3989 exponential run times encountered when looking for longer sequences
3990 with rs6000_emit_set_const. */
3992 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3994 if (!TARGET_POWERPC64)
3996 rtx operand1, operand2;
3998 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4000 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
4002 emit_move_insn (operand1, GEN_INT (c1));
4003 emit_move_insn (operand2, GEN_INT (c2));
4007 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4010 ud2 = (c1 & 0xffff0000) >> 16;
4011 #if HOST_BITS_PER_WIDE_INT >= 64
4015 ud4 = (c2 & 0xffff0000) >> 16;
4017 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4018 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4021 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4023 emit_move_insn (dest, GEN_INT (ud1));
4026 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4027 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4030 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4033 emit_move_insn (dest, GEN_INT (ud2 << 16));
4035 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4037 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4038 || (ud4 == 0 && ! (ud3 & 0x8000)))
4041 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4044 emit_move_insn (dest, GEN_INT (ud3 << 16));
4047 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
4048 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
4050 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4055 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4058 emit_move_insn (dest, GEN_INT (ud4 << 16));
4061 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
4063 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
4065 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
4066 GEN_INT (ud2 << 16)));
4068 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
4074 /* Helper for the following. Get rid of [r+r] memory refs
4075 in cases where it won't work (TImode, TFmode). */
4078 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4080 if (GET_CODE (operands[0]) == MEM
4081 && GET_CODE (XEXP (operands[0], 0)) != REG
4082 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4083 && ! reload_in_progress)
4085 = replace_equiv_address (operands[0],
4086 copy_addr_to_reg (XEXP (operands[0], 0)));
4088 if (GET_CODE (operands[1]) == MEM
4089 && GET_CODE (XEXP (operands[1], 0)) != REG
4090 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4091 && ! reload_in_progress)
4093 = replace_equiv_address (operands[1],
4094 copy_addr_to_reg (XEXP (operands[1], 0)));
4097 /* Emit a move from SOURCE to DEST in mode MODE. */
4099 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4103 operands[1] = source;
4105 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4106 if (GET_CODE (operands[1]) == CONST_DOUBLE
4107 && ! FLOAT_MODE_P (mode)
4108 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4110 /* FIXME. This should never happen. */
4111 /* Since it seems that it does, do the safe thing and convert
4113 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4115 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4116 || FLOAT_MODE_P (mode)
4117 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4118 || CONST_DOUBLE_LOW (operands[1]) < 0)
4119 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4120 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4122 /* Check if GCC is setting up a block move that will end up using FP
4123 registers as temporaries. We must make sure this is acceptable. */
4124 if (GET_CODE (operands[0]) == MEM
4125 && GET_CODE (operands[1]) == MEM
4127 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4128 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4129 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4130 ? 32 : MEM_ALIGN (operands[0])))
4131 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4133 : MEM_ALIGN (operands[1]))))
4134 && ! MEM_VOLATILE_P (operands [0])
4135 && ! MEM_VOLATILE_P (operands [1]))
4137 emit_move_insn (adjust_address (operands[0], SImode, 0),
4138 adjust_address (operands[1], SImode, 0));
4139 emit_move_insn (adjust_address (operands[0], SImode, 4),
4140 adjust_address (operands[1], SImode, 4));
4144 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
4145 && !gpc_reg_operand (operands[1], mode))
4146 operands[1] = force_reg (mode, operands[1]);
4148 if (mode == SFmode && ! TARGET_POWERPC
4149 && TARGET_HARD_FLOAT && TARGET_FPRS
4150 && GET_CODE (operands[0]) == MEM)
4154 if (reload_in_progress || reload_completed)
4155 regnum = true_regnum (operands[1]);
4156 else if (GET_CODE (operands[1]) == REG)
4157 regnum = REGNO (operands[1]);
4161 /* If operands[1] is a register, on POWER it may have
4162 double-precision data in it, so truncate it to single
4164 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4167 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
4168 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4169 operands[1] = newreg;
4173 /* Recognize the case where operand[1] is a reference to thread-local
4174 data and load its address to a register. */
4175 if (rs6000_tls_referenced_p (operands[1]))
4177 enum tls_model model;
4178 rtx tmp = operands[1];
4181 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4183 addend = XEXP (XEXP (tmp, 0), 1);
4184 tmp = XEXP (XEXP (tmp, 0), 0);
4187 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4188 model = SYMBOL_REF_TLS_MODEL (tmp);
4189 gcc_assert (model != 0);
4191 tmp = rs6000_legitimize_tls_address (tmp, model);
4194 tmp = gen_rtx_PLUS (mode, tmp, addend);
4195 tmp = force_operand (tmp, operands[0]);
4200 /* Handle the case where reload calls us with an invalid address. */
4201 if (reload_in_progress && mode == Pmode
4202 && (! general_operand (operands[1], mode)
4203 || ! nonimmediate_operand (operands[0], mode)))
4206 /* 128-bit constant floating-point values on Darwin should really be
4207 loaded as two parts. */
4208 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4209 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4211 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4212 know how to get a DFmode SUBREG of a TFmode. */
4213 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
4214 simplify_gen_subreg (DImode, operands[1], mode, 0),
4216 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
4217 GET_MODE_SIZE (DImode)),
4218 simplify_gen_subreg (DImode, operands[1], mode,
4219 GET_MODE_SIZE (DImode)),
4224 /* FIXME: In the long term, this switch statement should go away
4225 and be replaced by a sequence of tests based on things like
4231 if (CONSTANT_P (operands[1])
4232 && GET_CODE (operands[1]) != CONST_INT)
4233 operands[1] = force_const_mem (mode, operands[1]);
4237 rs6000_eliminate_indexed_memrefs (operands);
4242 if (CONSTANT_P (operands[1])
4243 && ! easy_fp_constant (operands[1], mode))
4244 operands[1] = force_const_mem (mode, operands[1]);
4255 if (CONSTANT_P (operands[1])
4256 && !easy_vector_constant (operands[1], mode))
4257 operands[1] = force_const_mem (mode, operands[1]);
4262 /* Use default pattern for address of ELF small data */
4265 && DEFAULT_ABI == ABI_V4
4266 && (GET_CODE (operands[1]) == SYMBOL_REF
4267 || GET_CODE (operands[1]) == CONST)
4268 && small_data_operand (operands[1], mode))
4270 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4274 if (DEFAULT_ABI == ABI_V4
4275 && mode == Pmode && mode == SImode
4276 && flag_pic == 1 && got_operand (operands[1], mode))
4278 emit_insn (gen_movsi_got (operands[0], operands[1]));
4282 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4286 && CONSTANT_P (operands[1])
4287 && GET_CODE (operands[1]) != HIGH
4288 && GET_CODE (operands[1]) != CONST_INT)
4290 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
4292 /* If this is a function address on -mcall-aixdesc,
4293 convert it to the address of the descriptor. */
4294 if (DEFAULT_ABI == ABI_AIX
4295 && GET_CODE (operands[1]) == SYMBOL_REF
4296 && XSTR (operands[1], 0)[0] == '.')
4298 const char *name = XSTR (operands[1], 0);
4300 while (*name == '.')
4302 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4303 CONSTANT_POOL_ADDRESS_P (new_ref)
4304 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4305 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4306 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4307 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4308 operands[1] = new_ref;
4311 if (DEFAULT_ABI == ABI_DARWIN)
4314 if (MACHO_DYNAMIC_NO_PIC_P)
4316 /* Take care of any required data indirection. */
4317 operands[1] = rs6000_machopic_legitimize_pic_address (
4318 operands[1], mode, operands[0]);
4319 if (operands[0] != operands[1])
4320 emit_insn (gen_rtx_SET (VOIDmode,
4321 operands[0], operands[1]));
4325 emit_insn (gen_macho_high (target, operands[1]));
4326 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4330 emit_insn (gen_elf_high (target, operands[1]));
4331 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4335 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4336 and we have put it in the TOC, we just need to make a TOC-relative
4339 && GET_CODE (operands[1]) == SYMBOL_REF
4340 && constant_pool_expr_p (operands[1])
4341 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4342 get_pool_mode (operands[1])))
4344 operands[1] = create_TOC_reference (operands[1]);
4346 else if (mode == Pmode
4347 && CONSTANT_P (operands[1])
4348 && ((GET_CODE (operands[1]) != CONST_INT
4349 && ! easy_fp_constant (operands[1], mode))
4350 || (GET_CODE (operands[1]) == CONST_INT
4351 && num_insns_constant (operands[1], mode) > 2)
4352 || (GET_CODE (operands[0]) == REG
4353 && FP_REGNO_P (REGNO (operands[0]))))
4354 && GET_CODE (operands[1]) != HIGH
4355 && ! legitimate_constant_pool_address_p (operands[1])
4356 && ! toc_relative_expr_p (operands[1]))
4358 /* Emit a USE operation so that the constant isn't deleted if
4359 expensive optimizations are turned on because nobody
4360 references it. This should only be done for operands that
4361 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4362 This should not be done for operands that contain LABEL_REFs.
4363 For now, we just handle the obvious case. */
4364 if (GET_CODE (operands[1]) != LABEL_REF)
4365 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4368 /* Darwin uses a special PIC legitimizer. */
4369 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4372 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4374 if (operands[0] != operands[1])
4375 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4380 /* If we are to limit the number of things we put in the TOC and
4381 this is a symbol plus a constant we can add in one insn,
4382 just put the symbol in the TOC and add the constant. Don't do
4383 this if reload is in progress. */
4384 if (GET_CODE (operands[1]) == CONST
4385 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4386 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4387 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4388 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4389 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4390 && ! side_effects_p (operands[0]))
4393 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4394 rtx other = XEXP (XEXP (operands[1], 0), 1);
4396 sym = force_reg (mode, sym);
4398 emit_insn (gen_addsi3 (operands[0], sym, other));
4400 emit_insn (gen_adddi3 (operands[0], sym, other));
4404 operands[1] = force_const_mem (mode, operands[1]);
4407 && constant_pool_expr_p (XEXP (operands[1], 0))
4408 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4409 get_pool_constant (XEXP (operands[1], 0)),
4410 get_pool_mode (XEXP (operands[1], 0))))
4413 = gen_const_mem (mode,
4414 create_TOC_reference (XEXP (operands[1], 0)));
4415 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4421 rs6000_eliminate_indexed_memrefs (operands);
4425 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4427 gen_rtx_SET (VOIDmode,
4428 operands[0], operands[1]),
4429 gen_rtx_CLOBBER (VOIDmode,
4430 gen_rtx_SCRATCH (SImode)))));
4439 /* Above, we may have called force_const_mem which may have returned
4440 an invalid address. If we can, fix this up; otherwise, reload will
4441 have to deal with it. */
4442 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4443 operands[1] = validize_mem (operands[1]);
4446 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4449 /* Nonzero if we can use a floating-point register to pass this arg. */
4450 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4451 (SCALAR_FLOAT_MODE_P (MODE) \
4452 && !DECIMAL_FLOAT_MODE_P (MODE) \
4453 && (CUM)->fregno <= FP_ARG_MAX_REG \
4454 && TARGET_HARD_FLOAT && TARGET_FPRS)
4456 /* Nonzero if we can use an AltiVec register to pass this arg. */
4457 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4458 (ALTIVEC_VECTOR_MODE (MODE) \
4459 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4460 && TARGET_ALTIVEC_ABI \
4463 /* Return a nonzero value to say to return the function value in
4464 memory, just as large structures are always returned. TYPE will be
4465 the data type of the value, and FNTYPE will be the type of the
4466 function doing the returning, or @code{NULL} for libcalls.
4468 The AIX ABI for the RS/6000 specifies that all structures are
4469 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4470 specifies that structures <= 8 bytes are returned in r3/r4, but a
4471 draft put them in memory, and GCC used to implement the draft
4472 instead of the final standard. Therefore, aix_struct_return
4473 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4474 compatibility can change DRAFT_V4_STRUCT_RET to override the
4475 default, and -m switches get the final word. See
4476 rs6000_override_options for more details.
4478 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4479 long double support is enabled. These values are returned in memory.
4481 int_size_in_bytes returns -1 for variable size objects, which go in
4482 memory always. The cast to unsigned makes -1 > 8. */
4485 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4487 /* In the darwin64 abi, try to use registers for larger structs
4489 if (rs6000_darwin64_abi
4490 && TREE_CODE (type) == RECORD_TYPE
4491 && int_size_in_bytes (type) > 0)
4493 CUMULATIVE_ARGS valcum;
4497 valcum.fregno = FP_ARG_MIN_REG;
4498 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4499 /* Do a trial code generation as if this were going to be passed
4500 as an argument; if any part goes in memory, we return NULL. */
4501 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4504 /* Otherwise fall through to more conventional ABI rules. */
4507 if (AGGREGATE_TYPE_P (type)
4508 && (aix_struct_return
4509 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4512 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4513 modes only exist for GCC vector types if -maltivec. */
4514 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4515 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4518 /* Return synthetic vectors in memory. */
4519 if (TREE_CODE (type) == VECTOR_TYPE
4520 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4522 static bool warned_for_return_big_vectors = false;
4523 if (!warned_for_return_big_vectors)
4525 warning (0, "GCC vector returned by reference: "
4526 "non-standard ABI extension with no compatibility guarantee");
4527 warned_for_return_big_vectors = true;
4532 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4538 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4539 for a call to a function whose data type is FNTYPE.
4540 For a library call, FNTYPE is 0.
4542 For incoming args we set the number of arguments in the prototype large
4543 so we never return a PARALLEL. */
4546 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4547 rtx libname ATTRIBUTE_UNUSED, int incoming,
4548 int libcall, int n_named_args)
4550 static CUMULATIVE_ARGS zero_cumulative;
4552 *cum = zero_cumulative;
4554 cum->fregno = FP_ARG_MIN_REG;
4555 cum->vregno = ALTIVEC_ARG_MIN_REG;
4556 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4557 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4558 ? CALL_LIBCALL : CALL_NORMAL);
4559 cum->sysv_gregno = GP_ARG_MIN_REG;
4560 cum->stdarg = fntype
4561 && (TYPE_ARG_TYPES (fntype) != 0
4562 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4563 != void_type_node));
4565 cum->nargs_prototype = 0;
4566 if (incoming || cum->prototype)
4567 cum->nargs_prototype = n_named_args;
4569 /* Check for a longcall attribute. */
4570 if ((!fntype && rs6000_default_long_calls)
4572 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4573 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4574 cum->call_cookie |= CALL_LONG;
4576 if (TARGET_DEBUG_ARG)
4578 fprintf (stderr, "\ninit_cumulative_args:");
4581 tree ret_type = TREE_TYPE (fntype);
4582 fprintf (stderr, " ret code = %s,",
4583 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4586 if (cum->call_cookie & CALL_LONG)
4587 fprintf (stderr, " longcall,");
4589 fprintf (stderr, " proto = %d, nargs = %d\n",
4590 cum->prototype, cum->nargs_prototype);
4595 && TARGET_ALTIVEC_ABI
4596 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4598 error ("cannot return value in vector register because"
4599 " altivec instructions are disabled, use -maltivec"
4604 /* Return true if TYPE must be passed on the stack and not in registers. */
4607 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4609 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4610 return must_pass_in_stack_var_size (mode, type);
4612 return must_pass_in_stack_var_size_or_pad (mode, type);
4615 /* If defined, a C expression which determines whether, and in which
4616 direction, to pad out an argument with extra space. The value
4617 should be of type `enum direction': either `upward' to pad above
4618 the argument, `downward' to pad below, or `none' to inhibit
4621 For the AIX ABI structs are always stored left shifted in their
4625 function_arg_padding (enum machine_mode mode, tree type)
4627 #ifndef AGGREGATE_PADDING_FIXED
4628 #define AGGREGATE_PADDING_FIXED 0
4630 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4631 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4634 if (!AGGREGATE_PADDING_FIXED)
4636 /* GCC used to pass structures of the same size as integer types as
4637 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4638 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4639 passed padded downward, except that -mstrict-align further
4640 muddied the water in that multi-component structures of 2 and 4
4641 bytes in size were passed padded upward.
4643 The following arranges for best compatibility with previous
4644 versions of gcc, but removes the -mstrict-align dependency. */
4645 if (BYTES_BIG_ENDIAN)
4647 HOST_WIDE_INT size = 0;
4649 if (mode == BLKmode)
4651 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4652 size = int_size_in_bytes (type);
4655 size = GET_MODE_SIZE (mode);
4657 if (size == 1 || size == 2 || size == 4)
4663 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4665 if (type != 0 && AGGREGATE_TYPE_P (type))
4669 /* Fall back to the default. */
4670 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4673 /* If defined, a C expression that gives the alignment boundary, in bits,
4674 of an argument with the specified mode and type. If it is not defined,
4675 PARM_BOUNDARY is used for all arguments.
4677 V.4 wants long longs and doubles to be double word aligned. Just
4678 testing the mode size is a boneheaded way to do this as it means
4679 that other types such as complex int are also double word aligned.
4680 However, we're stuck with this because changing the ABI might break
4681 existing library interfaces.
4683 Doubleword align SPE vectors.
4684 Quadword align Altivec vectors.
4685 Quadword align large synthetic vector types. */
4688 function_arg_boundary (enum machine_mode mode, tree type)
4690 if (DEFAULT_ABI == ABI_V4
4691 && (GET_MODE_SIZE (mode) == 8
4692 || (TARGET_HARD_FLOAT
4694 && mode == TFmode)))
4696 else if (SPE_VECTOR_MODE (mode)
4697 || (type && TREE_CODE (type) == VECTOR_TYPE
4698 && int_size_in_bytes (type) >= 8
4699 && int_size_in_bytes (type) < 16))
4701 else if (ALTIVEC_VECTOR_MODE (mode)
4702 || (type && TREE_CODE (type) == VECTOR_TYPE
4703 && int_size_in_bytes (type) >= 16))
4705 else if (rs6000_darwin64_abi && mode == BLKmode
4706 && type && TYPE_ALIGN (type) > 64)
4709 return PARM_BOUNDARY;
4712 /* For a function parm of MODE and TYPE, return the starting word in
4713 the parameter area. NWORDS of the parameter area are already used. */
4716 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4719 unsigned int parm_offset;
4721 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4722 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4723 return nwords + (-(parm_offset + nwords) & align);
4726 /* Compute the size (in words) of a function argument. */
4728 static unsigned long
4729 rs6000_arg_size (enum machine_mode mode, tree type)
4733 if (mode != BLKmode)
4734 size = GET_MODE_SIZE (mode);
4736 size = int_size_in_bytes (type);
4739 return (size + 3) >> 2;
4741 return (size + 7) >> 3;
4744 /* Use this to flush pending int fields. */
4747 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4748 HOST_WIDE_INT bitpos)
4750 unsigned int startbit, endbit;
4751 int intregs, intoffset;
4752 enum machine_mode mode;
4754 if (cum->intoffset == -1)
4757 intoffset = cum->intoffset;
4758 cum->intoffset = -1;
4760 if (intoffset % BITS_PER_WORD != 0)
4762 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4764 if (mode == BLKmode)
4766 /* We couldn't find an appropriate mode, which happens,
4767 e.g., in packed structs when there are 3 bytes to load.
4768 Back intoffset back to the beginning of the word in this
4770 intoffset = intoffset & -BITS_PER_WORD;
4774 startbit = intoffset & -BITS_PER_WORD;
4775 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4776 intregs = (endbit - startbit) / BITS_PER_WORD;
4777 cum->words += intregs;
4780 /* The darwin64 ABI calls for us to recurse down through structs,
4781 looking for elements passed in registers. Unfortunately, we have
4782 to track int register count here also because of misalignments
4783 in powerpc alignment mode. */
4786 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4788 HOST_WIDE_INT startbitpos)
4792 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4793 if (TREE_CODE (f) == FIELD_DECL)
4795 HOST_WIDE_INT bitpos = startbitpos;
4796 tree ftype = TREE_TYPE (f);
4797 enum machine_mode mode;
4798 if (ftype == error_mark_node)
4800 mode = TYPE_MODE (ftype);
4802 if (DECL_SIZE (f) != 0
4803 && host_integerp (bit_position (f), 1))
4804 bitpos += int_bit_position (f);
4806 /* ??? FIXME: else assume zero offset. */
4808 if (TREE_CODE (ftype) == RECORD_TYPE)
4809 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4810 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4812 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4813 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4814 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4816 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4818 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4822 else if (cum->intoffset == -1)
4823 cum->intoffset = bitpos;
4827 /* Update the data in CUM to advance over an argument
4828 of mode MODE and data type TYPE.
4829 (TYPE is null for libcalls where that information may not be available.)
4831 Note that for args passed by reference, function_arg will be called
4832 with MODE and TYPE set to that of the pointer to the arg, not the arg
4836 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4837 tree type, int named, int depth)
4841 /* Only tick off an argument if we're not recursing. */
4843 cum->nargs_prototype--;
4845 if (TARGET_ALTIVEC_ABI
4846 && (ALTIVEC_VECTOR_MODE (mode)
4847 || (type && TREE_CODE (type) == VECTOR_TYPE
4848 && int_size_in_bytes (type) == 16)))
4852 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4855 if (!TARGET_ALTIVEC)
4856 error ("cannot pass argument in vector register because"
4857 " altivec instructions are disabled, use -maltivec"
4860 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4861 even if it is going to be passed in a vector register.
4862 Darwin does the same for variable-argument functions. */
4863 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4864 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4874 /* Vector parameters must be 16-byte aligned. This places
4875 them at 2 mod 4 in terms of words in 32-bit mode, since
4876 the parameter save area starts at offset 24 from the
4877 stack. In 64-bit mode, they just have to start on an
4878 even word, since the parameter save area is 16-byte
4879 aligned. Space for GPRs is reserved even if the argument
4880 will be passed in memory. */
4882 align = (2 - cum->words) & 3;
4884 align = cum->words & 1;
4885 cum->words += align + rs6000_arg_size (mode, type);
4887 if (TARGET_DEBUG_ARG)
4889 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4891 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4892 cum->nargs_prototype, cum->prototype,
4893 GET_MODE_NAME (mode));
4897 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4899 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4902 else if (rs6000_darwin64_abi
4904 && TREE_CODE (type) == RECORD_TYPE
4905 && (size = int_size_in_bytes (type)) > 0)
4907 /* Variable sized types have size == -1 and are
4908 treated as if consisting entirely of ints.
4909 Pad to 16 byte boundary if needed. */
4910 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4911 && (cum->words % 2) != 0)
4913 /* For varargs, we can just go up by the size of the struct. */
4915 cum->words += (size + 7) / 8;
4918 /* It is tempting to say int register count just goes up by
4919 sizeof(type)/8, but this is wrong in a case such as
4920 { int; double; int; } [powerpc alignment]. We have to
4921 grovel through the fields for these too. */
4923 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4924 rs6000_darwin64_record_arg_advance_flush (cum,
4925 size * BITS_PER_UNIT);
4928 else if (DEFAULT_ABI == ABI_V4)
4930 if (TARGET_HARD_FLOAT && TARGET_FPRS
4931 && (mode == SFmode || mode == DFmode
4932 || (mode == TFmode && !TARGET_IEEEQUAD)))
4934 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
4935 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4938 cum->fregno = FP_ARG_V4_MAX_REG + 1;
4939 if (mode == DFmode || mode == TFmode)
4940 cum->words += cum->words & 1;
4941 cum->words += rs6000_arg_size (mode, type);
4946 int n_words = rs6000_arg_size (mode, type);
4947 int gregno = cum->sysv_gregno;
4949 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4950 (r7,r8) or (r9,r10). As does any other 2 word item such
4951 as complex int due to a historical mistake. */
4953 gregno += (1 - gregno) & 1;
4955 /* Multi-reg args are not split between registers and stack. */
4956 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4958 /* Long long and SPE vectors are aligned on the stack.
4959 So are other 2 word items such as complex int due to
4960 a historical mistake. */
4962 cum->words += cum->words & 1;
4963 cum->words += n_words;
4966 /* Note: continuing to accumulate gregno past when we've started
4967 spilling to the stack indicates the fact that we've started
4968 spilling to the stack to expand_builtin_saveregs. */
4969 cum->sysv_gregno = gregno + n_words;
4972 if (TARGET_DEBUG_ARG)
4974 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4975 cum->words, cum->fregno);
4976 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4977 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4978 fprintf (stderr, "mode = %4s, named = %d\n",
4979 GET_MODE_NAME (mode), named);
4984 int n_words = rs6000_arg_size (mode, type);
4985 int start_words = cum->words;
4986 int align_words = rs6000_parm_start (mode, type, start_words);
4988 cum->words = align_words + n_words;
4990 if (SCALAR_FLOAT_MODE_P (mode)
4991 && !DECIMAL_FLOAT_MODE_P (mode)
4992 && TARGET_HARD_FLOAT && TARGET_FPRS)
4993 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4995 if (TARGET_DEBUG_ARG)
4997 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4998 cum->words, cum->fregno);
4999 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5000 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5001 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5002 named, align_words - start_words, depth);
5008 spe_build_register_parallel (enum machine_mode mode, int gregno)
5015 r1 = gen_rtx_REG (DImode, gregno);
5016 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5017 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5020 r1 = gen_rtx_REG (DImode, gregno);
5021 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5022 r3 = gen_rtx_REG (DImode, gregno + 2);
5023 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5024 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5031 /* Determine where to put a SIMD argument on the SPE. */
5033 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5036 int gregno = cum->sysv_gregno;
5038 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5039 are passed and returned in a pair of GPRs for ABI compatibility. */
5040 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
5042 int n_words = rs6000_arg_size (mode, type);
5044 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5046 gregno += (1 - gregno) & 1;
5048 /* Multi-reg args are not split between registers and stack. */
5049 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5052 return spe_build_register_parallel (mode, gregno);
5056 int n_words = rs6000_arg_size (mode, type);
5058 /* SPE vectors are put in odd registers. */
5059 if (n_words == 2 && (gregno & 1) == 0)
5062 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5065 enum machine_mode m = SImode;
5067 r1 = gen_rtx_REG (m, gregno);
5068 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5069 r2 = gen_rtx_REG (m, gregno + 1);
5070 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5071 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5078 if (gregno <= GP_ARG_MAX_REG)
5079 return gen_rtx_REG (mode, gregno);
5085 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5086 structure between cum->intoffset and bitpos to integer registers. */
5089 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5090 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5092 enum machine_mode mode;
5094 unsigned int startbit, endbit;
5095 int this_regno, intregs, intoffset;
5098 if (cum->intoffset == -1)
5101 intoffset = cum->intoffset;
5102 cum->intoffset = -1;
5104 /* If this is the trailing part of a word, try to only load that
5105 much into the register. Otherwise load the whole register. Note
5106 that in the latter case we may pick up unwanted bits. It's not a
5107 problem at the moment but may wish to revisit. */
5109 if (intoffset % BITS_PER_WORD != 0)
5111 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5113 if (mode == BLKmode)
5115 /* We couldn't find an appropriate mode, which happens,
5116 e.g., in packed structs when there are 3 bytes to load.
5117 Back intoffset back to the beginning of the word in this
5119 intoffset = intoffset & -BITS_PER_WORD;
5126 startbit = intoffset & -BITS_PER_WORD;
5127 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5128 intregs = (endbit - startbit) / BITS_PER_WORD;
5129 this_regno = cum->words + intoffset / BITS_PER_WORD;
5131 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5134 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5138 intoffset /= BITS_PER_UNIT;
5141 regno = GP_ARG_MIN_REG + this_regno;
5142 reg = gen_rtx_REG (mode, regno);
5144 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5147 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5151 while (intregs > 0);
5154 /* Recursive workhorse for the following. */
5157 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5158 HOST_WIDE_INT startbitpos, rtx rvec[],
5163 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5164 if (TREE_CODE (f) == FIELD_DECL)
5166 HOST_WIDE_INT bitpos = startbitpos;
5167 tree ftype = TREE_TYPE (f);
5168 enum machine_mode mode;
5169 if (ftype == error_mark_node)
5171 mode = TYPE_MODE (ftype);
5173 if (DECL_SIZE (f) != 0
5174 && host_integerp (bit_position (f), 1))
5175 bitpos += int_bit_position (f);
5177 /* ??? FIXME: else assume zero offset. */
5179 if (TREE_CODE (ftype) == RECORD_TYPE)
5180 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5181 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5186 case SCmode: mode = SFmode; break;
5187 case DCmode: mode = DFmode; break;
5188 case TCmode: mode = TFmode; break;
5192 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5194 = gen_rtx_EXPR_LIST (VOIDmode,
5195 gen_rtx_REG (mode, cum->fregno++),
5196 GEN_INT (bitpos / BITS_PER_UNIT));
5200 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5202 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5204 = gen_rtx_EXPR_LIST (VOIDmode,
5205 gen_rtx_REG (mode, cum->vregno++),
5206 GEN_INT (bitpos / BITS_PER_UNIT));
5208 else if (cum->intoffset == -1)
5209 cum->intoffset = bitpos;
5213 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5214 the register(s) to be used for each field and subfield of a struct
5215 being passed by value, along with the offset of where the
5216 register's value may be found in the block. FP fields go in FP
5217 register, vector fields go in vector registers, and everything
5218 else goes in int registers, packed as in memory.
5220 This code is also used for function return values. RETVAL indicates
5221 whether this is the case.
5223 Much of this is taken from the SPARC V9 port, which has a similar
5224 calling convention. */
5227 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5228 int named, bool retval)
5230 rtx rvec[FIRST_PSEUDO_REGISTER];
5231 int k = 1, kbase = 1;
5232 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5233 /* This is a copy; modifications are not visible to our caller. */
5234 CUMULATIVE_ARGS copy_cum = *orig_cum;
5235 CUMULATIVE_ARGS *cum = ©_cum;
5237 /* Pad to 16 byte boundary if needed. */
5238 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5239 && (cum->words % 2) != 0)
5246 /* Put entries into rvec[] for individual FP and vector fields, and
5247 for the chunks of memory that go in int regs. Note we start at
5248 element 1; 0 is reserved for an indication of using memory, and
5249 may or may not be filled in below. */
5250 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5251 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5253 /* If any part of the struct went on the stack put all of it there.
5254 This hack is because the generic code for
5255 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5256 parts of the struct are not at the beginning. */
5260 return NULL_RTX; /* doesn't go in registers at all */
5262 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5264 if (k > 1 || cum->use_stack)
5265 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5270 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5273 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5277 rtx rvec[GP_ARG_NUM_REG + 1];
5279 if (align_words >= GP_ARG_NUM_REG)
5282 n_units = rs6000_arg_size (mode, type);
5284 /* Optimize the simple case where the arg fits in one gpr, except in
5285 the case of BLKmode due to assign_parms assuming that registers are
5286 BITS_PER_WORD wide. */
5288 || (n_units == 1 && mode != BLKmode))
5289 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5292 if (align_words + n_units > GP_ARG_NUM_REG)
5293 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5294 using a magic NULL_RTX component.
5295 This is not strictly correct. Only some of the arg belongs in
5296 memory, not all of it. However, the normal scheme using
5297 function_arg_partial_nregs can result in unusual subregs, eg.
5298 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5299 store the whole arg to memory is often more efficient than code
5300 to store pieces, and we know that space is available in the right
5301 place for the whole arg. */
5302 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5307 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5308 rtx off = GEN_INT (i++ * 4);
5309 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5311 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5313 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5316 /* Determine where to put an argument to a function.
5317 Value is zero to push the argument on the stack,
5318 or a hard register in which to store the argument.
5320 MODE is the argument's machine mode.
5321 TYPE is the data type of the argument (as a tree).
5322 This is null for libcalls where that information may
5324 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5325 the preceding args and about the function being called. It is
5326 not modified in this routine.
5327 NAMED is nonzero if this argument is a named parameter
5328 (otherwise it is an extra parameter matching an ellipsis).
5330 On RS/6000 the first eight words of non-FP are normally in registers
5331 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5332 Under V.4, the first 8 FP args are in registers.
5334 If this is floating-point and no prototype is specified, we use
5335 both an FP and integer register (or possibly FP reg and stack). Library
5336 functions (when CALL_LIBCALL is set) always have the proper types for args,
5337 so we can pass the FP value just in one register. emit_library_function
5338 doesn't support PARALLEL anyway.
5340 Note that for args passed by reference, function_arg will be called
5341 with MODE and TYPE set to that of the pointer to the arg, not the arg
5345 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5346 tree type, int named)
5348 enum rs6000_abi abi = DEFAULT_ABI;
5350 /* Return a marker to indicate whether CR1 needs to set or clear the
5351 bit that V.4 uses to say fp args were passed in registers.
5352 Assume that we don't need the marker for software floating point,
5353 or compiler generated library calls. */
5354 if (mode == VOIDmode)
5357 && (cum->call_cookie & CALL_LIBCALL) == 0
5359 || (cum->nargs_prototype < 0
5360 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5362 /* For the SPE, we need to crxor CR6 always. */
5364 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5365 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5366 return GEN_INT (cum->call_cookie
5367 | ((cum->fregno == FP_ARG_MIN_REG)
5368 ? CALL_V4_SET_FP_ARGS
5369 : CALL_V4_CLEAR_FP_ARGS));
5372 return GEN_INT (cum->call_cookie);
5375 if (rs6000_darwin64_abi && mode == BLKmode
5376 && TREE_CODE (type) == RECORD_TYPE)
5378 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5379 if (rslt != NULL_RTX)
5381 /* Else fall through to usual handling. */
5384 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5385 if (TARGET_64BIT && ! cum->prototype)
5387 /* Vector parameters get passed in vector register
5388 and also in GPRs or memory, in absence of prototype. */
5391 align_words = (cum->words + 1) & ~1;
5393 if (align_words >= GP_ARG_NUM_REG)
5399 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5401 return gen_rtx_PARALLEL (mode,
5403 gen_rtx_EXPR_LIST (VOIDmode,
5405 gen_rtx_EXPR_LIST (VOIDmode,
5406 gen_rtx_REG (mode, cum->vregno),
5410 return gen_rtx_REG (mode, cum->vregno);
5411 else if (TARGET_ALTIVEC_ABI
5412 && (ALTIVEC_VECTOR_MODE (mode)
5413 || (type && TREE_CODE (type) == VECTOR_TYPE
5414 && int_size_in_bytes (type) == 16)))
5416 if (named || abi == ABI_V4)
5420 /* Vector parameters to varargs functions under AIX or Darwin
5421 get passed in memory and possibly also in GPRs. */
5422 int align, align_words, n_words;
5423 enum machine_mode part_mode;
5425 /* Vector parameters must be 16-byte aligned. This places them at
5426 2 mod 4 in terms of words in 32-bit mode, since the parameter
5427 save area starts at offset 24 from the stack. In 64-bit mode,
5428 they just have to start on an even word, since the parameter
5429 save area is 16-byte aligned. */
5431 align = (2 - cum->words) & 3;
5433 align = cum->words & 1;
5434 align_words = cum->words + align;
5436 /* Out of registers? Memory, then. */
5437 if (align_words >= GP_ARG_NUM_REG)
5440 if (TARGET_32BIT && TARGET_POWERPC64)
5441 return rs6000_mixed_function_arg (mode, type, align_words);
5443 /* The vector value goes in GPRs. Only the part of the
5444 value in GPRs is reported here. */
5446 n_words = rs6000_arg_size (mode, type);
5447 if (align_words + n_words > GP_ARG_NUM_REG)
5448 /* Fortunately, there are only two possibilities, the value
5449 is either wholly in GPRs or half in GPRs and half not. */
5452 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5455 else if (TARGET_SPE_ABI && TARGET_SPE
5456 && (SPE_VECTOR_MODE (mode)
5457 || (TARGET_E500_DOUBLE && (mode == DFmode
5458 || mode == DCmode))))
5459 return rs6000_spe_function_arg (cum, mode, type);
5461 else if (abi == ABI_V4)
5463 if (TARGET_HARD_FLOAT && TARGET_FPRS
5464 && (mode == SFmode || mode == DFmode
5465 || (mode == TFmode && !TARGET_IEEEQUAD)))
5467 if (cum->fregno + (mode == TFmode ? 1 : 0) <= FP_ARG_V4_MAX_REG)
5468 return gen_rtx_REG (mode, cum->fregno);
5474 int n_words = rs6000_arg_size (mode, type);
5475 int gregno = cum->sysv_gregno;
5477 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5478 (r7,r8) or (r9,r10). As does any other 2 word item such
5479 as complex int due to a historical mistake. */
5481 gregno += (1 - gregno) & 1;
5483 /* Multi-reg args are not split between registers and stack. */
5484 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5487 if (TARGET_32BIT && TARGET_POWERPC64)
5488 return rs6000_mixed_function_arg (mode, type,
5489 gregno - GP_ARG_MIN_REG);
5490 return gen_rtx_REG (mode, gregno);
5495 int align_words = rs6000_parm_start (mode, type, cum->words);
5497 if (USE_FP_FOR_ARG_P (cum, mode, type))
5499 rtx rvec[GP_ARG_NUM_REG + 1];
5503 enum machine_mode fmode = mode;
5504 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5506 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5508 /* Currently, we only ever need one reg here because complex
5509 doubles are split. */
5510 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5512 /* Long double split over regs and memory. */
5516 /* Do we also need to pass this arg in the parameter save
5519 && (cum->nargs_prototype <= 0
5520 || (DEFAULT_ABI == ABI_AIX
5522 && align_words >= GP_ARG_NUM_REG)));
5524 if (!needs_psave && mode == fmode)
5525 return gen_rtx_REG (fmode, cum->fregno);
5530 /* Describe the part that goes in gprs or the stack.
5531 This piece must come first, before the fprs. */
5532 if (align_words < GP_ARG_NUM_REG)
5534 unsigned long n_words = rs6000_arg_size (mode, type);
5536 if (align_words + n_words > GP_ARG_NUM_REG
5537 || (TARGET_32BIT && TARGET_POWERPC64))
5539 /* If this is partially on the stack, then we only
5540 include the portion actually in registers here. */
5541 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5544 if (align_words + n_words > GP_ARG_NUM_REG)
5545 /* Not all of the arg fits in gprs. Say that it
5546 goes in memory too, using a magic NULL_RTX
5547 component. Also see comment in
5548 rs6000_mixed_function_arg for why the normal
5549 function_arg_partial_nregs scheme doesn't work
5551 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5555 r = gen_rtx_REG (rmode,
5556 GP_ARG_MIN_REG + align_words);
5557 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5558 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5560 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5564 /* The whole arg fits in gprs. */
5565 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5566 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5570 /* It's entirely in memory. */
5571 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5574 /* Describe where this piece goes in the fprs. */
5575 r = gen_rtx_REG (fmode, cum->fregno);
5576 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5578 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5580 else if (align_words < GP_ARG_NUM_REG)
5582 if (TARGET_32BIT && TARGET_POWERPC64)
5583 return rs6000_mixed_function_arg (mode, type, align_words);
5585 if (mode == BLKmode)
5588 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5595 /* For an arg passed partly in registers and partly in memory, this is
5596 the number of bytes passed in registers. For args passed entirely in
5597 registers or entirely in memory, zero. When an arg is described by a
5598 PARALLEL, perhaps using more than one register type, this function
5599 returns the number of bytes used by the first element of the PARALLEL. */
5602 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5603 tree type, bool named)
5608 if (DEFAULT_ABI == ABI_V4)
5611 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5612 && cum->nargs_prototype >= 0)
5615 /* In this complicated case we just disable the partial_nregs code. */
5616 if (rs6000_darwin64_abi && mode == BLKmode
5617 && TREE_CODE (type) == RECORD_TYPE
5618 && int_size_in_bytes (type) > 0)
5621 align_words = rs6000_parm_start (mode, type, cum->words);
5623 if (USE_FP_FOR_ARG_P (cum, mode, type))
5625 /* If we are passing this arg in the fixed parameter save area
5626 (gprs or memory) as well as fprs, then this function should
5627 return the number of partial bytes passed in the parameter
5628 save area rather than partial bytes passed in fprs. */
5630 && (cum->nargs_prototype <= 0
5631 || (DEFAULT_ABI == ABI_AIX
5633 && align_words >= GP_ARG_NUM_REG)))
5635 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5636 > FP_ARG_MAX_REG + 1)
5637 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5638 else if (cum->nargs_prototype >= 0)
5642 if (align_words < GP_ARG_NUM_REG
5643 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5644 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5646 if (ret != 0 && TARGET_DEBUG_ARG)
5647 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5652 /* A C expression that indicates when an argument must be passed by
5653 reference. If nonzero for an argument, a copy of that argument is
5654 made in memory and a pointer to the argument is passed instead of
5655 the argument itself. The pointer is passed in whatever way is
5656 appropriate for passing a pointer to that type.
5658 Under V.4, aggregates and long double are passed by reference.
5660 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5661 reference unless the AltiVec vector extension ABI is in force.
5663 As an extension to all ABIs, variable sized types are passed by
5667 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5668 enum machine_mode mode, tree type,
5669 bool named ATTRIBUTE_UNUSED)
5671 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5673 if (TARGET_DEBUG_ARG)
5674 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5681 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5683 if (TARGET_DEBUG_ARG)
5684 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5688 if (int_size_in_bytes (type) < 0)
5690 if (TARGET_DEBUG_ARG)
5691 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5695 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5696 modes only exist for GCC vector types if -maltivec. */
5697 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5699 if (TARGET_DEBUG_ARG)
5700 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5704 /* Pass synthetic vectors in memory. */
5705 if (TREE_CODE (type) == VECTOR_TYPE
5706 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5708 static bool warned_for_pass_big_vectors = false;
5709 if (TARGET_DEBUG_ARG)
5710 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5711 if (!warned_for_pass_big_vectors)
5713 warning (0, "GCC vector passed by reference: "
5714 "non-standard ABI extension with no compatibility guarantee");
5715 warned_for_pass_big_vectors = true;
5724 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5727 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5732 for (i = 0; i < nregs; i++)
5734 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5735 if (reload_completed)
5737 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5740 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5741 i * GET_MODE_SIZE (reg_mode));
5744 tem = replace_equiv_address (tem, XEXP (tem, 0));
5748 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5752 /* Perform any needed actions needed for a function that is receiving a
5753 variable number of arguments.
5757 MODE and TYPE are the mode and type of the current parameter.
5759 PRETEND_SIZE is a variable that should be set to the amount of stack
5760 that must be pushed by the prolog to pretend that our caller pushed
5763 Normally, this macro will push all remaining incoming registers on the
5764 stack and set PRETEND_SIZE to the length of the registers pushed. */
5767 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5768 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5771 CUMULATIVE_ARGS next_cum;
5772 int reg_size = TARGET_32BIT ? 4 : 8;
5773 rtx save_area = NULL_RTX, mem;
5774 int first_reg_offset, set;
5776 /* Skip the last named argument. */
5778 function_arg_advance (&next_cum, mode, type, 1, 0);
5780 if (DEFAULT_ABI == ABI_V4)
5782 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5786 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5787 HOST_WIDE_INT offset = 0;
5789 /* Try to optimize the size of the varargs save area.
5790 The ABI requires that ap.reg_save_area is doubleword
5791 aligned, but we don't need to allocate space for all
5792 the bytes, only those to which we actually will save
5794 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5795 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5796 if (TARGET_HARD_FLOAT && TARGET_FPRS
5797 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5798 && cfun->va_list_fpr_size)
5801 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5802 * UNITS_PER_FP_WORD;
5803 if (cfun->va_list_fpr_size
5804 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5805 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5807 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5808 * UNITS_PER_FP_WORD;
5812 offset = -((first_reg_offset * reg_size) & ~7);
5813 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5815 gpr_reg_num = cfun->va_list_gpr_size;
5816 if (reg_size == 4 && (first_reg_offset & 1))
5819 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5822 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5824 - (int) (GP_ARG_NUM_REG * reg_size);
5826 if (gpr_size + fpr_size)
5829 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5830 gcc_assert (GET_CODE (reg_save_area) == MEM);
5831 reg_save_area = XEXP (reg_save_area, 0);
5832 if (GET_CODE (reg_save_area) == PLUS)
5834 gcc_assert (XEXP (reg_save_area, 0)
5835 == virtual_stack_vars_rtx);
5836 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5837 offset += INTVAL (XEXP (reg_save_area, 1));
5840 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5843 cfun->machine->varargs_save_offset = offset;
5844 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5849 first_reg_offset = next_cum.words;
5850 save_area = virtual_incoming_args_rtx;
5852 if (targetm.calls.must_pass_in_stack (mode, type))
5853 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5856 set = get_varargs_alias_set ();
5857 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5858 && cfun->va_list_gpr_size)
5860 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5862 if (va_list_gpr_counter_field)
5864 /* V4 va_list_gpr_size counts number of registers needed. */
5865 if (nregs > cfun->va_list_gpr_size)
5866 nregs = cfun->va_list_gpr_size;
5870 /* char * va_list instead counts number of bytes needed. */
5871 if (nregs > cfun->va_list_gpr_size / reg_size)
5872 nregs = cfun->va_list_gpr_size / reg_size;
5875 mem = gen_rtx_MEM (BLKmode,
5876 plus_constant (save_area,
5877 first_reg_offset * reg_size));
5878 MEM_NOTRAP_P (mem) = 1;
5879 set_mem_alias_set (mem, set);
5880 set_mem_align (mem, BITS_PER_WORD);
5882 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5886 /* Save FP registers if needed. */
5887 if (DEFAULT_ABI == ABI_V4
5888 && TARGET_HARD_FLOAT && TARGET_FPRS
5890 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5891 && cfun->va_list_fpr_size)
5893 int fregno = next_cum.fregno, nregs;
5894 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5895 rtx lab = gen_label_rtx ();
5896 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5897 * UNITS_PER_FP_WORD);
5900 (gen_rtx_SET (VOIDmode,
5902 gen_rtx_IF_THEN_ELSE (VOIDmode,
5903 gen_rtx_NE (VOIDmode, cr1,
5905 gen_rtx_LABEL_REF (VOIDmode, lab),
5909 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5910 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5912 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5913 MEM_NOTRAP_P (mem) = 1;
5914 set_mem_alias_set (mem, set);
5915 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5916 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5923 /* Create the va_list data type. */
5926 rs6000_build_builtin_va_list (void)
5928 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5930 /* For AIX, prefer 'char *' because that's what the system
5931 header files like. */
5932 if (DEFAULT_ABI != ABI_V4)
5933 return build_pointer_type (char_type_node);
5935 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5936 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5938 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5939 unsigned_char_type_node);
5940 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5941 unsigned_char_type_node);
5942 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5944 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5945 short_unsigned_type_node);
5946 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5948 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5951 va_list_gpr_counter_field = f_gpr;
5952 va_list_fpr_counter_field = f_fpr;
5954 DECL_FIELD_CONTEXT (f_gpr) = record;
5955 DECL_FIELD_CONTEXT (f_fpr) = record;
5956 DECL_FIELD_CONTEXT (f_res) = record;
5957 DECL_FIELD_CONTEXT (f_ovf) = record;
5958 DECL_FIELD_CONTEXT (f_sav) = record;
5960 TREE_CHAIN (record) = type_decl;
5961 TYPE_NAME (record) = type_decl;
5962 TYPE_FIELDS (record) = f_gpr;
5963 TREE_CHAIN (f_gpr) = f_fpr;
5964 TREE_CHAIN (f_fpr) = f_res;
5965 TREE_CHAIN (f_res) = f_ovf;
5966 TREE_CHAIN (f_ovf) = f_sav;
5968 layout_type (record);
5970 /* The correct type is an array type of one element. */
5971 return build_array_type (record, build_index_type (size_zero_node));
5974 /* Implement va_start. */
5977 rs6000_va_start (tree valist, rtx nextarg)
5979 HOST_WIDE_INT words, n_gpr, n_fpr;
5980 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5981 tree gpr, fpr, ovf, sav, t;
5983 /* Only SVR4 needs something special. */
5984 if (DEFAULT_ABI != ABI_V4)
5986 std_expand_builtin_va_start (valist, nextarg);
5990 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5991 f_fpr = TREE_CHAIN (f_gpr);
5992 f_res = TREE_CHAIN (f_fpr);
5993 f_ovf = TREE_CHAIN (f_res);
5994 f_sav = TREE_CHAIN (f_ovf);
5996 valist = build_va_arg_indirect_ref (valist);
5997 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5998 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5999 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6000 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6002 /* Count number of gp and fp argument registers used. */
6003 words = current_function_args_info.words;
6004 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6006 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6009 if (TARGET_DEBUG_ARG)
6010 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6011 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6012 words, n_gpr, n_fpr);
6014 if (cfun->va_list_gpr_size)
6016 t = build2 (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
6017 build_int_cst (NULL_TREE, n_gpr));
6018 TREE_SIDE_EFFECTS (t) = 1;
6019 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6022 if (cfun->va_list_fpr_size)
6024 t = build2 (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
6025 build_int_cst (NULL_TREE, n_fpr));
6026 TREE_SIDE_EFFECTS (t) = 1;
6027 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6030 /* Find the overflow area. */
6031 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6033 t = build2 (PLUS_EXPR, TREE_TYPE (ovf), t,
6034 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
6035 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6036 TREE_SIDE_EFFECTS (t) = 1;
6037 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6039 /* If there were no va_arg invocations, don't set up the register
6041 if (!cfun->va_list_gpr_size
6042 && !cfun->va_list_fpr_size
6043 && n_gpr < GP_ARG_NUM_REG
6044 && n_fpr < FP_ARG_V4_MAX_REG)
6047 /* Find the register save area. */
6048 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6049 if (cfun->machine->varargs_save_offset)
6050 t = build2 (PLUS_EXPR, TREE_TYPE (sav), t,
6051 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
6052 t = build2 (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
6053 TREE_SIDE_EFFECTS (t) = 1;
6054 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6057 /* Implement va_arg. */
6060 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6062 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6063 tree gpr, fpr, ovf, sav, reg, t, u;
6064 int size, rsize, n_reg, sav_ofs, sav_scale;
6065 tree lab_false, lab_over, addr;
6067 tree ptrtype = build_pointer_type (type);
6069 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6071 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6072 return build_va_arg_indirect_ref (t);
6075 if (DEFAULT_ABI != ABI_V4)
6077 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6079 tree elem_type = TREE_TYPE (type);
6080 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6081 int elem_size = GET_MODE_SIZE (elem_mode);
6083 if (elem_size < UNITS_PER_WORD)
6085 tree real_part, imag_part;
6086 tree post = NULL_TREE;
6088 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6090 /* Copy the value into a temporary, lest the formal temporary
6091 be reused out from under us. */
6092 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6093 append_to_statement_list (post, pre_p);
6095 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6098 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6102 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6105 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6106 f_fpr = TREE_CHAIN (f_gpr);
6107 f_res = TREE_CHAIN (f_fpr);
6108 f_ovf = TREE_CHAIN (f_res);
6109 f_sav = TREE_CHAIN (f_ovf);
6111 valist = build_va_arg_indirect_ref (valist);
6112 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6113 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6114 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6115 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6117 size = int_size_in_bytes (type);
6118 rsize = (size + 3) / 4;
6121 if (TARGET_HARD_FLOAT && TARGET_FPRS
6122 && (TYPE_MODE (type) == SFmode
6123 || TYPE_MODE (type) == DFmode
6124 || TYPE_MODE (type) == TFmode))
6126 /* FP args go in FP registers, if present. */
6128 n_reg = (size + 7) / 8;
6131 if (TYPE_MODE (type) != SFmode)
6136 /* Otherwise into GP registers. */
6145 /* Pull the value out of the saved registers.... */
6148 addr = create_tmp_var (ptr_type_node, "addr");
6149 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6151 /* AltiVec vectors never go in registers when -mabi=altivec. */
6152 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6156 lab_false = create_artificial_label ();
6157 lab_over = create_artificial_label ();
6159 /* Long long and SPE vectors are aligned in the registers.
6160 As are any other 2 gpr item such as complex int due to a
6161 historical mistake. */
6163 if (n_reg == 2 && reg == gpr)
6165 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6166 size_int (n_reg - 1));
6167 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6170 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6171 t = build2 (GE_EXPR, boolean_type_node, u, t);
6172 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6173 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6174 gimplify_and_add (t, pre_p);
6178 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6180 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6181 u = build1 (CONVERT_EXPR, integer_type_node, u);
6182 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
6183 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
6185 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
6186 gimplify_and_add (t, pre_p);
6188 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6189 gimplify_and_add (t, pre_p);
6191 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6192 append_to_statement_list (t, pre_p);
6194 if ((n_reg == 2 && reg != gpr) || n_reg > 2)
6196 /* Ensure that we don't find any more args in regs.
6197 Alignment has taken care of the n_reg == 2 gpr case. */
6198 t = build2 (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
6199 gimplify_and_add (t, pre_p);
6203 /* ... otherwise out of the overflow area. */
6205 /* Care for on-stack alignment if needed. */
6209 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6210 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6211 build_int_cst (NULL_TREE, -align));
6213 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6215 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
6216 gimplify_and_add (u, pre_p);
6218 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6219 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
6220 gimplify_and_add (t, pre_p);
6224 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6225 append_to_statement_list (t, pre_p);
6228 if (STRICT_ALIGNMENT
6229 && (TYPE_ALIGN (type)
6230 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6232 /* The value (of type complex double, for example) may not be
6233 aligned in memory in the saved registers, so copy via a
6234 temporary. (This is the same code as used for SPARC.) */
6235 tree tmp = create_tmp_var (type, "va_arg_tmp");
6236 tree dest_addr = build_fold_addr_expr (tmp);
6238 tree copy = build_function_call_expr
6239 (implicit_built_in_decls[BUILT_IN_MEMCPY],
6240 tree_cons (NULL_TREE, dest_addr,
6241 tree_cons (NULL_TREE, addr,
6242 tree_cons (NULL_TREE, size_int (rsize * 4),
6245 gimplify_and_add (copy, pre_p);
6249 addr = fold_convert (ptrtype, addr);
6250 return build_va_arg_indirect_ref (addr);
6256 def_builtin (int mask, const char *name, tree type, int code)
6258 if (mask & target_flags)
6260 if (rs6000_builtin_decls[code])
6263 rs6000_builtin_decls[code] =
6264 add_builtin_function (name, type, code, BUILT_IN_MD,
6269 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6271 static const struct builtin_description bdesc_3arg[] =
6273 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6274 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6275 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6276 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6277 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6278 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6279 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6280 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6281 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6282 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6283 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6284 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6285 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6286 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6287 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6288 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6289 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6290 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6291 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6292 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6293 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6294 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6295 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6297 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6298 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6299 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6300 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6301 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6302 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6303 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6304 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6305 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6306 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6307 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6308 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6309 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6310 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6311 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6314 /* DST operations: void foo (void *, const int, const char). */
6316 static const struct builtin_description bdesc_dst[] =
6318 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6319 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6320 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6321 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6323 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6324 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6325 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6326 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6329 /* Simple binary operations: VECc = foo (VECa, VECb). */
6331 static struct builtin_description bdesc_2arg[] =
6333 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6334 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6335 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6336 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6337 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6338 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6339 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6340 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6341 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6342 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6343 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6344 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6345 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6346 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6347 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6348 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6349 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6350 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6351 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6352 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6353 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6354 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6355 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6356 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6357 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6358 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6359 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6360 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6361 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6362 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6363 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6364 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6365 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6366 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6367 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6368 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6369 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6370 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6371 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6372 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6373 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6374 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6375 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6376 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6377 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6378 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6379 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6380 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6381 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6382 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6383 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6384 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6385 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6386 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6387 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6388 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6389 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6390 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6391 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6392 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6393 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6394 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6395 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6396 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6397 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6398 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6399 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6400 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6401 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6402 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6403 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6404 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6405 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6406 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6407 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6408 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6409 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6410 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6411 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6412 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6413 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6414 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6415 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6416 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6417 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6418 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6419 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6420 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6421 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6422 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6423 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6424 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6425 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6426 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6427 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6428 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6429 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6430 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6431 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6432 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6433 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6434 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6435 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6436 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6437 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6438 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6439 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6440 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6441 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6442 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6443 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6445 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6446 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6447 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6448 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6449 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6450 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6451 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6452 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6453 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6454 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6455 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6456 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6457 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6458 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6459 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6460 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6461 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6462 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6463 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6464 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6465 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6466 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6467 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6468 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6469 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6470 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6471 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6472 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6473 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6474 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6475 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6476 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6477 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6478 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6479 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6480 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6481 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6482 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6483 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6484 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6485 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6486 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6487 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6488 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6489 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6490 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6491 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6492 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6493 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6494 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6495 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6496 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6497 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6498 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6499 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6500 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6501 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6502 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6503 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6504 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6505 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6506 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6507 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6508 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6509 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6510 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6511 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6512 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6513 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6514 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6515 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6516 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6517 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6518 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6519 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6520 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6521 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6522 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6523 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6524 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6525 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6526 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6527 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6528 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6529 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6530 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6531 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6536 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6537 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6538 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6539 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6540 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6541 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6542 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6543 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6544 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6545 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6546 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6547 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6548 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6549 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6550 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6551 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6552 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6553 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6554 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6555 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6556 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6557 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6558 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6559 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6560 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6561 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6562 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6563 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6564 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6565 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6566 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6567 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6568 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6569 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6570 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6571 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6573 /* Place holder, leave as first spe builtin. */
6574 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6575 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6576 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6577 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6578 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6579 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6580 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6581 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6582 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6583 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6584 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6585 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6586 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6587 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6588 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6589 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6590 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6591 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6592 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6593 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6594 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6595 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6596 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6597 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6598 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6599 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6600 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6601 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6602 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6603 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6604 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6605 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6606 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6607 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6608 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6609 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6610 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6611 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6612 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6613 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6614 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6615 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6616 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6617 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6618 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6619 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6620 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6621 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6622 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6623 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6624 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6625 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6626 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6627 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6628 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6629 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6630 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6631 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6632 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6633 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6634 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6635 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6636 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6637 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6638 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6639 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6640 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6641 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6642 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6643 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6644 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6645 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6646 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6647 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6648 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6649 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6650 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6651 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6652 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6653 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6654 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6655 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6656 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6657 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6658 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6659 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6660 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6661 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6662 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6663 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6664 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6665 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6666 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6667 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6668 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6669 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6670 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6671 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6672 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6673 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6674 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6675 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6676 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6677 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6678 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6679 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6680 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6681 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6682 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6684 /* SPE binary operations expecting a 5-bit unsigned literal. */
6685 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6687 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6688 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6689 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6690 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6691 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6692 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6693 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6694 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6695 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6696 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6697 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6698 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6699 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6700 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6701 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6702 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6703 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6704 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6705 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6706 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6707 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6708 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6709 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6710 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6711 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6712 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6714 /* Place-holder. Leave as last binary SPE builtin. */
6715 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6718 /* AltiVec predicates. */
6720 struct builtin_description_predicates
6722 const unsigned int mask;
6723 const enum insn_code icode;
6725 const char *const name;
6726 const enum rs6000_builtins code;
6729 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6731 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6732 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6733 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6734 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6735 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6736 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6737 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6738 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6739 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6740 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6745 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6746 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6747 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6750 /* SPE predicates. */
6751 static struct builtin_description bdesc_spe_predicates[] =
6753 /* Place-holder. Leave as first. */
6754 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6755 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6756 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6757 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6758 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6759 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6760 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6761 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6762 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6763 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6764 /* Place-holder. Leave as last. */
6765 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6768 /* SPE evsel predicates. */
6769 static struct builtin_description bdesc_spe_evsel[] =
6771 /* Place-holder. Leave as first. */
6772 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6773 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6774 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6775 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6776 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6777 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6778 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6779 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6780 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6781 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6782 /* Place-holder. Leave as last. */
6783 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6786 /* ABS* operations. */
6788 static const struct builtin_description bdesc_abs[] =
6790 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6791 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6792 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6793 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6794 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6795 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6796 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6799 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6802 static struct builtin_description bdesc_1arg[] =
6804 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6805 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6806 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6807 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6808 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6809 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6810 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6811 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6812 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6813 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6814 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6815 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6816 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6817 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6818 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6819 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6820 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6822 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6823 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6824 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6825 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6826 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6827 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6828 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6829 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6830 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6831 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6832 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6833 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6834 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6835 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6836 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6837 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6838 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6839 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6840 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6842 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6843 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6844 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6845 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6846 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6847 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6848 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6849 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6850 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6851 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6852 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6853 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6854 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6855 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6856 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6857 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6858 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6859 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6860 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6861 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6862 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6863 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6864 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6865 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6866 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6867 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6868 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6869 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6870 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6871 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6873 /* Place-holder. Leave as last unary SPE builtin. */
6874 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6878 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6881 tree arg0 = TREE_VALUE (arglist);
6882 rtx op0 = expand_normal (arg0);
6883 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6884 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6886 if (icode == CODE_FOR_nothing)
6887 /* Builtin not supported on this processor. */
6890 /* If we got invalid arguments bail out before generating bad rtl. */
6891 if (arg0 == error_mark_node)
6894 if (icode == CODE_FOR_altivec_vspltisb
6895 || icode == CODE_FOR_altivec_vspltish
6896 || icode == CODE_FOR_altivec_vspltisw
6897 || icode == CODE_FOR_spe_evsplatfi
6898 || icode == CODE_FOR_spe_evsplati)
6900 /* Only allow 5-bit *signed* literals. */
6901 if (GET_CODE (op0) != CONST_INT
6902 || INTVAL (op0) > 15
6903 || INTVAL (op0) < -16)
6905 error ("argument 1 must be a 5-bit signed literal");
6911 || GET_MODE (target) != tmode
6912 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6913 target = gen_reg_rtx (tmode);
6915 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6916 op0 = copy_to_mode_reg (mode0, op0);
6918 pat = GEN_FCN (icode) (target, op0);
6927 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6929 rtx pat, scratch1, scratch2;
6930 tree arg0 = TREE_VALUE (arglist);
6931 rtx op0 = expand_normal (arg0);
6932 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6933 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6935 /* If we have invalid arguments, bail out before generating bad rtl. */
6936 if (arg0 == error_mark_node)
6940 || GET_MODE (target) != tmode
6941 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6942 target = gen_reg_rtx (tmode);
6944 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6945 op0 = copy_to_mode_reg (mode0, op0);
6947 scratch1 = gen_reg_rtx (mode0);
6948 scratch2 = gen_reg_rtx (mode0);
6950 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6959 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6962 tree arg0 = TREE_VALUE (arglist);
6963 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6964 rtx op0 = expand_normal (arg0);
6965 rtx op1 = expand_normal (arg1);
6966 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6967 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6968 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6970 if (icode == CODE_FOR_nothing)
6971 /* Builtin not supported on this processor. */
6974 /* If we got invalid arguments bail out before generating bad rtl. */
6975 if (arg0 == error_mark_node || arg1 == error_mark_node)
6978 if (icode == CODE_FOR_altivec_vcfux
6979 || icode == CODE_FOR_altivec_vcfsx
6980 || icode == CODE_FOR_altivec_vctsxs
6981 || icode == CODE_FOR_altivec_vctuxs
6982 || icode == CODE_FOR_altivec_vspltb
6983 || icode == CODE_FOR_altivec_vsplth
6984 || icode == CODE_FOR_altivec_vspltw
6985 || icode == CODE_FOR_spe_evaddiw
6986 || icode == CODE_FOR_spe_evldd
6987 || icode == CODE_FOR_spe_evldh
6988 || icode == CODE_FOR_spe_evldw
6989 || icode == CODE_FOR_spe_evlhhesplat
6990 || icode == CODE_FOR_spe_evlhhossplat
6991 || icode == CODE_FOR_spe_evlhhousplat
6992 || icode == CODE_FOR_spe_evlwhe
6993 || icode == CODE_FOR_spe_evlwhos
6994 || icode == CODE_FOR_spe_evlwhou
6995 || icode == CODE_FOR_spe_evlwhsplat
6996 || icode == CODE_FOR_spe_evlwwsplat
6997 || icode == CODE_FOR_spe_evrlwi
6998 || icode == CODE_FOR_spe_evslwi
6999 || icode == CODE_FOR_spe_evsrwis
7000 || icode == CODE_FOR_spe_evsubifw
7001 || icode == CODE_FOR_spe_evsrwiu)
7003 /* Only allow 5-bit unsigned literals. */
7005 if (TREE_CODE (arg1) != INTEGER_CST
7006 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7008 error ("argument 2 must be a 5-bit unsigned literal");
7014 || GET_MODE (target) != tmode
7015 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7016 target = gen_reg_rtx (tmode);
7018 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7019 op0 = copy_to_mode_reg (mode0, op0);
7020 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7021 op1 = copy_to_mode_reg (mode1, op1);
7023 pat = GEN_FCN (icode) (target, op0, op1);
7032 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7033 tree arglist, rtx target)
7036 tree cr6_form = TREE_VALUE (arglist);
7037 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7038 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7039 rtx op0 = expand_normal (arg0);
7040 rtx op1 = expand_normal (arg1);
7041 enum machine_mode tmode = SImode;
7042 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7043 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7046 if (TREE_CODE (cr6_form) != INTEGER_CST)
7048 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7052 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7054 gcc_assert (mode0 == mode1);
7056 /* If we have invalid arguments, bail out before generating bad rtl. */
7057 if (arg0 == error_mark_node || arg1 == error_mark_node)
7061 || GET_MODE (target) != tmode
7062 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7063 target = gen_reg_rtx (tmode);
7065 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7066 op0 = copy_to_mode_reg (mode0, op0);
7067 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7068 op1 = copy_to_mode_reg (mode1, op1);
7070 scratch = gen_reg_rtx (mode0);
7072 pat = GEN_FCN (icode) (scratch, op0, op1,
7073 gen_rtx_SYMBOL_REF (Pmode, opcode));
7078 /* The vec_any* and vec_all* predicates use the same opcodes for two
7079 different operations, but the bits in CR6 will be different
7080 depending on what information we want. So we have to play tricks
7081 with CR6 to get the right bits out.
7083 If you think this is disgusting, look at the specs for the
7084 AltiVec predicates. */
7086 switch (cr6_form_int)
7089 emit_insn (gen_cr6_test_for_zero (target));
7092 emit_insn (gen_cr6_test_for_zero_reverse (target));
7095 emit_insn (gen_cr6_test_for_lt (target));
7098 emit_insn (gen_cr6_test_for_lt_reverse (target));
7101 error ("argument 1 of __builtin_altivec_predicate is out of range");
7109 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
7112 tree arg0 = TREE_VALUE (arglist);
7113 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7114 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7115 enum machine_mode mode0 = Pmode;
7116 enum machine_mode mode1 = Pmode;
7117 rtx op0 = expand_normal (arg0);
7118 rtx op1 = expand_normal (arg1);
7120 if (icode == CODE_FOR_nothing)
7121 /* Builtin not supported on this processor. */
7124 /* If we got invalid arguments bail out before generating bad rtl. */
7125 if (arg0 == error_mark_node || arg1 == error_mark_node)
7129 || GET_MODE (target) != tmode
7130 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7131 target = gen_reg_rtx (tmode);
7133 op1 = copy_to_mode_reg (mode1, op1);
7135 if (op0 == const0_rtx)
7137 addr = gen_rtx_MEM (tmode, op1);
7141 op0 = copy_to_mode_reg (mode0, op0);
7142 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7145 pat = GEN_FCN (icode) (target, addr);
7155 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
7157 tree arg0 = TREE_VALUE (arglist);
7158 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7159 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7160 rtx op0 = expand_normal (arg0);
7161 rtx op1 = expand_normal (arg1);
7162 rtx op2 = expand_normal (arg2);
7164 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7165 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7166 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7168 /* Invalid arguments. Bail before doing anything stoopid! */
7169 if (arg0 == error_mark_node
7170 || arg1 == error_mark_node
7171 || arg2 == error_mark_node)
7174 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7175 op0 = copy_to_mode_reg (mode2, op0);
7176 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7177 op1 = copy_to_mode_reg (mode0, op1);
7178 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7179 op2 = copy_to_mode_reg (mode1, op2);
7181 pat = GEN_FCN (icode) (op1, op2, op0);
7188 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
7190 tree arg0 = TREE_VALUE (arglist);
7191 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7192 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7193 rtx op0 = expand_normal (arg0);
7194 rtx op1 = expand_normal (arg1);
7195 rtx op2 = expand_normal (arg2);
7197 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7198 enum machine_mode mode1 = Pmode;
7199 enum machine_mode mode2 = Pmode;
7201 /* Invalid arguments. Bail before doing anything stoopid! */
7202 if (arg0 == error_mark_node
7203 || arg1 == error_mark_node
7204 || arg2 == error_mark_node)
7207 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7208 op0 = copy_to_mode_reg (tmode, op0);
7210 op2 = copy_to_mode_reg (mode2, op2);
7212 if (op1 == const0_rtx)
7214 addr = gen_rtx_MEM (tmode, op2);
7218 op1 = copy_to_mode_reg (mode1, op1);
7219 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7222 pat = GEN_FCN (icode) (addr, op0);
7229 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
7232 tree arg0 = TREE_VALUE (arglist);
7233 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7234 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7235 rtx op0 = expand_normal (arg0);
7236 rtx op1 = expand_normal (arg1);
7237 rtx op2 = expand_normal (arg2);
7238 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7239 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7240 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7241 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7243 if (icode == CODE_FOR_nothing)
7244 /* Builtin not supported on this processor. */
7247 /* If we got invalid arguments bail out before generating bad rtl. */
7248 if (arg0 == error_mark_node
7249 || arg1 == error_mark_node
7250 || arg2 == error_mark_node)
7253 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7254 || icode == CODE_FOR_altivec_vsldoi_v4si
7255 || icode == CODE_FOR_altivec_vsldoi_v8hi
7256 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7258 /* Only allow 4-bit unsigned literals. */
7260 if (TREE_CODE (arg2) != INTEGER_CST
7261 || TREE_INT_CST_LOW (arg2) & ~0xf)
7263 error ("argument 3 must be a 4-bit unsigned literal");
7269 || GET_MODE (target) != tmode
7270 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7271 target = gen_reg_rtx (tmode);
7273 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7274 op0 = copy_to_mode_reg (mode0, op0);
7275 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7276 op1 = copy_to_mode_reg (mode1, op1);
7277 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7278 op2 = copy_to_mode_reg (mode2, op2);
7280 pat = GEN_FCN (icode) (target, op0, op1, op2);
7288 /* Expand the lvx builtins. */
7290 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7292 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7293 tree arglist = TREE_OPERAND (exp, 1);
7294 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7296 enum machine_mode tmode, mode0;
7298 enum insn_code icode;
7302 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7303 icode = CODE_FOR_altivec_lvx_v16qi;
7305 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7306 icode = CODE_FOR_altivec_lvx_v8hi;
7308 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7309 icode = CODE_FOR_altivec_lvx_v4si;
7311 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7312 icode = CODE_FOR_altivec_lvx_v4sf;
7321 arg0 = TREE_VALUE (arglist);
7322 op0 = expand_normal (arg0);
7323 tmode = insn_data[icode].operand[0].mode;
7324 mode0 = insn_data[icode].operand[1].mode;
7327 || GET_MODE (target) != tmode
7328 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7329 target = gen_reg_rtx (tmode);
7331 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7332 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7334 pat = GEN_FCN (icode) (target, op0);
7341 /* Expand the stvx builtins. */
7343 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7346 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7347 tree arglist = TREE_OPERAND (exp, 1);
7348 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7350 enum machine_mode mode0, mode1;
7352 enum insn_code icode;
7356 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7357 icode = CODE_FOR_altivec_stvx_v16qi;
7359 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7360 icode = CODE_FOR_altivec_stvx_v8hi;
7362 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7363 icode = CODE_FOR_altivec_stvx_v4si;
7365 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7366 icode = CODE_FOR_altivec_stvx_v4sf;
7373 arg0 = TREE_VALUE (arglist);
7374 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7375 op0 = expand_normal (arg0);
7376 op1 = expand_normal (arg1);
7377 mode0 = insn_data[icode].operand[0].mode;
7378 mode1 = insn_data[icode].operand[1].mode;
7380 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7381 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7382 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7383 op1 = copy_to_mode_reg (mode1, op1);
7385 pat = GEN_FCN (icode) (op0, op1);
7393 /* Expand the dst builtins. */
7395 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7398 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7399 tree arglist = TREE_OPERAND (exp, 1);
7400 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7401 tree arg0, arg1, arg2;
7402 enum machine_mode mode0, mode1, mode2;
7403 rtx pat, op0, op1, op2;
7404 struct builtin_description *d;
7409 /* Handle DST variants. */
7410 d = (struct builtin_description *) bdesc_dst;
7411 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7412 if (d->code == fcode)
7414 arg0 = TREE_VALUE (arglist);
7415 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7416 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7417 op0 = expand_normal (arg0);
7418 op1 = expand_normal (arg1);
7419 op2 = expand_normal (arg2);
7420 mode0 = insn_data[d->icode].operand[0].mode;
7421 mode1 = insn_data[d->icode].operand[1].mode;
7422 mode2 = insn_data[d->icode].operand[2].mode;
7424 /* Invalid arguments, bail out before generating bad rtl. */
7425 if (arg0 == error_mark_node
7426 || arg1 == error_mark_node
7427 || arg2 == error_mark_node)
7432 if (TREE_CODE (arg2) != INTEGER_CST
7433 || TREE_INT_CST_LOW (arg2) & ~0x3)
7435 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7439 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7440 op0 = copy_to_mode_reg (Pmode, op0);
7441 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7442 op1 = copy_to_mode_reg (mode1, op1);
7444 pat = GEN_FCN (d->icode) (op0, op1, op2);
7454 /* Expand vec_init builtin. */
7456 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7458 enum machine_mode tmode = TYPE_MODE (type);
7459 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7460 int i, n_elt = GET_MODE_NUNITS (tmode);
7461 rtvec v = rtvec_alloc (n_elt);
7463 gcc_assert (VECTOR_MODE_P (tmode));
7465 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7467 rtx x = expand_normal (TREE_VALUE (arglist));
7468 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7471 gcc_assert (arglist == NULL);
7473 if (!target || !register_operand (target, tmode))
7474 target = gen_reg_rtx (tmode);
7476 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7480 /* Return the integer constant in ARG. Constrain it to be in the range
7481 of the subparts of VEC_TYPE; issue an error if not. */
7484 get_element_number (tree vec_type, tree arg)
7486 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7488 if (!host_integerp (arg, 1)
7489 || (elt = tree_low_cst (arg, 1), elt > max))
7491 error ("selector must be an integer constant in the range 0..%wi", max);
7498 /* Expand vec_set builtin. */
7500 altivec_expand_vec_set_builtin (tree arglist)
7502 enum machine_mode tmode, mode1;
7503 tree arg0, arg1, arg2;
7507 arg0 = TREE_VALUE (arglist);
7508 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7509 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7511 tmode = TYPE_MODE (TREE_TYPE (arg0));
7512 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7513 gcc_assert (VECTOR_MODE_P (tmode));
7515 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7516 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7517 elt = get_element_number (TREE_TYPE (arg0), arg2);
7519 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7520 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7522 op0 = force_reg (tmode, op0);
7523 op1 = force_reg (mode1, op1);
7525 rs6000_expand_vector_set (op0, op1, elt);
7530 /* Expand vec_ext builtin. */
7532 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7534 enum machine_mode tmode, mode0;
7539 arg0 = TREE_VALUE (arglist);
7540 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7542 op0 = expand_normal (arg0);
7543 elt = get_element_number (TREE_TYPE (arg0), arg1);
7545 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7546 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7547 gcc_assert (VECTOR_MODE_P (mode0));
7549 op0 = force_reg (mode0, op0);
7551 if (optimize || !target || !register_operand (target, tmode))
7552 target = gen_reg_rtx (tmode);
7554 rs6000_expand_vector_extract (target, op0, elt);
7559 /* Expand the builtin in EXP and store the result in TARGET. Store
7560 true in *EXPANDEDP if we found a builtin to expand. */
7562 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7564 struct builtin_description *d;
7565 struct builtin_description_predicates *dp;
7567 enum insn_code icode;
7568 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7569 tree arglist = TREE_OPERAND (exp, 1);
7572 enum machine_mode tmode, mode0;
7573 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7575 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7576 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7579 error ("unresolved overload for Altivec builtin %qF", fndecl);
7583 target = altivec_expand_ld_builtin (exp, target, expandedp);
7587 target = altivec_expand_st_builtin (exp, target, expandedp);
7591 target = altivec_expand_dst_builtin (exp, target, expandedp);
7599 case ALTIVEC_BUILTIN_STVX:
7600 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7601 case ALTIVEC_BUILTIN_STVEBX:
7602 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7603 case ALTIVEC_BUILTIN_STVEHX:
7604 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7605 case ALTIVEC_BUILTIN_STVEWX:
7606 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7607 case ALTIVEC_BUILTIN_STVXL:
7608 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7610 case ALTIVEC_BUILTIN_MFVSCR:
7611 icode = CODE_FOR_altivec_mfvscr;
7612 tmode = insn_data[icode].operand[0].mode;
7615 || GET_MODE (target) != tmode
7616 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7617 target = gen_reg_rtx (tmode);
7619 pat = GEN_FCN (icode) (target);
7625 case ALTIVEC_BUILTIN_MTVSCR:
7626 icode = CODE_FOR_altivec_mtvscr;
7627 arg0 = TREE_VALUE (arglist);
7628 op0 = expand_normal (arg0);
7629 mode0 = insn_data[icode].operand[0].mode;
7631 /* If we got invalid arguments bail out before generating bad rtl. */
7632 if (arg0 == error_mark_node)
7635 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7636 op0 = copy_to_mode_reg (mode0, op0);
7638 pat = GEN_FCN (icode) (op0);
7643 case ALTIVEC_BUILTIN_DSSALL:
7644 emit_insn (gen_altivec_dssall ());
7647 case ALTIVEC_BUILTIN_DSS:
7648 icode = CODE_FOR_altivec_dss;
7649 arg0 = TREE_VALUE (arglist);
7651 op0 = expand_normal (arg0);
7652 mode0 = insn_data[icode].operand[0].mode;
7654 /* If we got invalid arguments bail out before generating bad rtl. */
7655 if (arg0 == error_mark_node)
7658 if (TREE_CODE (arg0) != INTEGER_CST
7659 || TREE_INT_CST_LOW (arg0) & ~0x3)
7661 error ("argument to dss must be a 2-bit unsigned literal");
7665 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7666 op0 = copy_to_mode_reg (mode0, op0);
7668 emit_insn (gen_altivec_dss (op0));
7671 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7672 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7673 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7674 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7675 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7677 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7678 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7679 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7680 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7681 return altivec_expand_vec_set_builtin (arglist);
7683 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7684 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7685 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7686 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7687 return altivec_expand_vec_ext_builtin (arglist, target);
7694 /* Expand abs* operations. */
7695 d = (struct builtin_description *) bdesc_abs;
7696 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7697 if (d->code == fcode)
7698 return altivec_expand_abs_builtin (d->icode, arglist, target);
7700 /* Expand the AltiVec predicates. */
7701 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7702 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7703 if (dp->code == fcode)
7704 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7707 /* LV* are funky. We initialized them differently. */
7710 case ALTIVEC_BUILTIN_LVSL:
7711 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7713 case ALTIVEC_BUILTIN_LVSR:
7714 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7716 case ALTIVEC_BUILTIN_LVEBX:
7717 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7719 case ALTIVEC_BUILTIN_LVEHX:
7720 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7722 case ALTIVEC_BUILTIN_LVEWX:
7723 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7725 case ALTIVEC_BUILTIN_LVXL:
7726 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7728 case ALTIVEC_BUILTIN_LVX:
7729 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7740 /* Binops that need to be initialized manually, but can be expanded
7741 automagically by rs6000_expand_binop_builtin. */
7742 static struct builtin_description bdesc_2arg_spe[] =
7744 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7745 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7746 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7747 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7748 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7749 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7750 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7751 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7752 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7753 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7754 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7755 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7756 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7757 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7758 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7759 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7760 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7761 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7762 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7763 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7764 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7765 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7768 /* Expand the builtin in EXP and store the result in TARGET. Store
7769 true in *EXPANDEDP if we found a builtin to expand.
7771 This expands the SPE builtins that are not simple unary and binary
7774 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7776 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7777 tree arglist = TREE_OPERAND (exp, 1);
7779 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7780 enum insn_code icode;
7781 enum machine_mode tmode, mode0;
7783 struct builtin_description *d;
7788 /* Syntax check for a 5-bit unsigned immediate. */
7791 case SPE_BUILTIN_EVSTDD:
7792 case SPE_BUILTIN_EVSTDH:
7793 case SPE_BUILTIN_EVSTDW:
7794 case SPE_BUILTIN_EVSTWHE:
7795 case SPE_BUILTIN_EVSTWHO:
7796 case SPE_BUILTIN_EVSTWWE:
7797 case SPE_BUILTIN_EVSTWWO:
7798 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7799 if (TREE_CODE (arg1) != INTEGER_CST
7800 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7802 error ("argument 2 must be a 5-bit unsigned literal");
7810 /* The evsplat*i instructions are not quite generic. */
7813 case SPE_BUILTIN_EVSPLATFI:
7814 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7816 case SPE_BUILTIN_EVSPLATI:
7817 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7823 d = (struct builtin_description *) bdesc_2arg_spe;
7824 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7825 if (d->code == fcode)
7826 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7828 d = (struct builtin_description *) bdesc_spe_predicates;
7829 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7830 if (d->code == fcode)
7831 return spe_expand_predicate_builtin (d->icode, arglist, target);
7833 d = (struct builtin_description *) bdesc_spe_evsel;
7834 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7835 if (d->code == fcode)
7836 return spe_expand_evsel_builtin (d->icode, arglist, target);
7840 case SPE_BUILTIN_EVSTDDX:
7841 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7842 case SPE_BUILTIN_EVSTDHX:
7843 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7844 case SPE_BUILTIN_EVSTDWX:
7845 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7846 case SPE_BUILTIN_EVSTWHEX:
7847 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7848 case SPE_BUILTIN_EVSTWHOX:
7849 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7850 case SPE_BUILTIN_EVSTWWEX:
7851 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7852 case SPE_BUILTIN_EVSTWWOX:
7853 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7854 case SPE_BUILTIN_EVSTDD:
7855 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7856 case SPE_BUILTIN_EVSTDH:
7857 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7858 case SPE_BUILTIN_EVSTDW:
7859 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7860 case SPE_BUILTIN_EVSTWHE:
7861 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7862 case SPE_BUILTIN_EVSTWHO:
7863 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7864 case SPE_BUILTIN_EVSTWWE:
7865 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7866 case SPE_BUILTIN_EVSTWWO:
7867 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7868 case SPE_BUILTIN_MFSPEFSCR:
7869 icode = CODE_FOR_spe_mfspefscr;
7870 tmode = insn_data[icode].operand[0].mode;
7873 || GET_MODE (target) != tmode
7874 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7875 target = gen_reg_rtx (tmode);
7877 pat = GEN_FCN (icode) (target);
7882 case SPE_BUILTIN_MTSPEFSCR:
7883 icode = CODE_FOR_spe_mtspefscr;
7884 arg0 = TREE_VALUE (arglist);
7885 op0 = expand_normal (arg0);
7886 mode0 = insn_data[icode].operand[0].mode;
7888 if (arg0 == error_mark_node)
7891 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7892 op0 = copy_to_mode_reg (mode0, op0);
7894 pat = GEN_FCN (icode) (op0);
7907 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7909 rtx pat, scratch, tmp;
7910 tree form = TREE_VALUE (arglist);
7911 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7912 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7913 rtx op0 = expand_normal (arg0);
7914 rtx op1 = expand_normal (arg1);
7915 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7916 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7920 if (TREE_CODE (form) != INTEGER_CST)
7922 error ("argument 1 of __builtin_spe_predicate must be a constant");
7926 form_int = TREE_INT_CST_LOW (form);
7928 gcc_assert (mode0 == mode1);
7930 if (arg0 == error_mark_node || arg1 == error_mark_node)
7934 || GET_MODE (target) != SImode
7935 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7936 target = gen_reg_rtx (SImode);
7938 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7939 op0 = copy_to_mode_reg (mode0, op0);
7940 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7941 op1 = copy_to_mode_reg (mode1, op1);
7943 scratch = gen_reg_rtx (CCmode);
7945 pat = GEN_FCN (icode) (scratch, op0, op1);
7950 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7951 _lower_. We use one compare, but look in different bits of the
7952 CR for each variant.
7954 There are 2 elements in each SPE simd type (upper/lower). The CR
7955 bits are set as follows:
7957 BIT0 | BIT 1 | BIT 2 | BIT 3
7958 U | L | (U | L) | (U & L)
7960 So, for an "all" relationship, BIT 3 would be set.
7961 For an "any" relationship, BIT 2 would be set. Etc.
7963 Following traditional nomenclature, these bits map to:
7965 BIT0 | BIT 1 | BIT 2 | BIT 3
7968 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7973 /* All variant. OV bit. */
7975 /* We need to get to the OV bit, which is the ORDERED bit. We
7976 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7977 that's ugly and will make validate_condition_mode die.
7978 So let's just use another pattern. */
7979 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7981 /* Any variant. EQ bit. */
7985 /* Upper variant. LT bit. */
7989 /* Lower variant. GT bit. */
7994 error ("argument 1 of __builtin_spe_predicate is out of range");
7998 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7999 emit_move_insn (target, tmp);
8004 /* The evsel builtins look like this:
8006 e = __builtin_spe_evsel_OP (a, b, c, d);
8010 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8011 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8015 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
8018 tree arg0 = TREE_VALUE (arglist);
8019 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
8020 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
8021 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
8022 rtx op0 = expand_normal (arg0);
8023 rtx op1 = expand_normal (arg1);
8024 rtx op2 = expand_normal (arg2);
8025 rtx op3 = expand_normal (arg3);
8026 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8027 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8029 gcc_assert (mode0 == mode1);
8031 if (arg0 == error_mark_node || arg1 == error_mark_node
8032 || arg2 == error_mark_node || arg3 == error_mark_node)
8036 || GET_MODE (target) != mode0
8037 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8038 target = gen_reg_rtx (mode0);
8040 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8041 op0 = copy_to_mode_reg (mode0, op0);
8042 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8043 op1 = copy_to_mode_reg (mode0, op1);
8044 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8045 op2 = copy_to_mode_reg (mode0, op2);
8046 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8047 op3 = copy_to_mode_reg (mode0, op3);
8049 /* Generate the compare. */
8050 scratch = gen_reg_rtx (CCmode);
8051 pat = GEN_FCN (icode) (scratch, op0, op1);
8056 if (mode0 == V2SImode)
8057 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8059 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8064 /* Expand an expression EXP that calls a built-in function,
8065 with result going to TARGET if that's convenient
8066 (and in mode MODE if that's convenient).
8067 SUBTARGET may be used as the target for computing one of EXP's operands.
8068 IGNORE is nonzero if the value is to be ignored. */
8071 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8072 enum machine_mode mode ATTRIBUTE_UNUSED,
8073 int ignore ATTRIBUTE_UNUSED)
8075 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
8076 tree arglist = TREE_OPERAND (exp, 1);
8077 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8078 struct builtin_description *d;
8083 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8084 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8086 int icode = (int) CODE_FOR_altivec_lvsr;
8087 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8088 enum machine_mode mode = insn_data[icode].operand[1].mode;
8092 gcc_assert (TARGET_ALTIVEC);
8094 arg = TREE_VALUE (arglist);
8095 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8096 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8097 addr = memory_address (mode, op);
8098 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8102 /* For the load case need to negate the address. */
8103 op = gen_reg_rtx (GET_MODE (addr));
8104 emit_insn (gen_rtx_SET (VOIDmode, op,
8105 gen_rtx_NEG (GET_MODE (addr), addr)));
8107 op = gen_rtx_MEM (mode, op);
8110 || GET_MODE (target) != tmode
8111 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8112 target = gen_reg_rtx (tmode);
8114 /*pat = gen_altivec_lvsr (target, op);*/
8115 pat = GEN_FCN (icode) (target, op);
8125 ret = altivec_expand_builtin (exp, target, &success);
8132 ret = spe_expand_builtin (exp, target, &success);
8138 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8140 /* Handle simple unary operations. */
8141 d = (struct builtin_description *) bdesc_1arg;
8142 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8143 if (d->code == fcode)
8144 return rs6000_expand_unop_builtin (d->icode, arglist, target);
8146 /* Handle simple binary operations. */
8147 d = (struct builtin_description *) bdesc_2arg;
8148 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8149 if (d->code == fcode)
8150 return rs6000_expand_binop_builtin (d->icode, arglist, target);
8152 /* Handle simple ternary operations. */
8153 d = (struct builtin_description *) bdesc_3arg;
8154 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8155 if (d->code == fcode)
8156 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
8162 build_opaque_vector_type (tree node, int nunits)
8164 node = copy_node (node);
8165 TYPE_MAIN_VARIANT (node) = node;
8166 return build_vector_type (node, nunits);
8170 rs6000_init_builtins (void)
8172 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8173 V2SF_type_node = build_vector_type (float_type_node, 2);
8174 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8175 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8176 V4SF_type_node = build_vector_type (float_type_node, 4);
8177 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8178 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8180 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8181 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8182 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8184 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8185 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8186 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8187 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8189 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8190 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8191 'vector unsigned short'. */
8193 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8194 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8195 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8196 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8198 long_integer_type_internal_node = long_integer_type_node;
8199 long_unsigned_type_internal_node = long_unsigned_type_node;
8200 intQI_type_internal_node = intQI_type_node;
8201 uintQI_type_internal_node = unsigned_intQI_type_node;
8202 intHI_type_internal_node = intHI_type_node;
8203 uintHI_type_internal_node = unsigned_intHI_type_node;
8204 intSI_type_internal_node = intSI_type_node;
8205 uintSI_type_internal_node = unsigned_intSI_type_node;
8206 float_type_internal_node = float_type_node;
8207 void_type_internal_node = void_type_node;
8209 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8210 get_identifier ("__bool char"),
8211 bool_char_type_node));
8212 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8213 get_identifier ("__bool short"),
8214 bool_short_type_node));
8215 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8216 get_identifier ("__bool int"),
8217 bool_int_type_node));
8218 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8219 get_identifier ("__pixel"),
8222 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8223 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8224 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8225 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8227 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8228 get_identifier ("__vector unsigned char"),
8229 unsigned_V16QI_type_node));
8230 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8231 get_identifier ("__vector signed char"),
8233 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8234 get_identifier ("__vector __bool char"),
8235 bool_V16QI_type_node));
8237 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8238 get_identifier ("__vector unsigned short"),
8239 unsigned_V8HI_type_node));
8240 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8241 get_identifier ("__vector signed short"),
8243 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8244 get_identifier ("__vector __bool short"),
8245 bool_V8HI_type_node));
8247 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8248 get_identifier ("__vector unsigned int"),
8249 unsigned_V4SI_type_node));
8250 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8251 get_identifier ("__vector signed int"),
8253 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8254 get_identifier ("__vector __bool int"),
8255 bool_V4SI_type_node));
8257 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8258 get_identifier ("__vector float"),
8260 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8261 get_identifier ("__vector __pixel"),
8262 pixel_V8HI_type_node));
8265 spe_init_builtins ();
8267 altivec_init_builtins ();
8268 if (TARGET_ALTIVEC || TARGET_SPE)
8269 rs6000_common_init_builtins ();
8272 /* AIX libm provides clog as __clog. */
8273 if (built_in_decls [BUILT_IN_CLOG])
8274 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8278 /* Search through a set of builtins and enable the mask bits.
8279 DESC is an array of builtins.
8280 SIZE is the total number of builtins.
8281 START is the builtin enum at which to start.
8282 END is the builtin enum at which to end. */
8284 enable_mask_for_builtins (struct builtin_description *desc, int size,
8285 enum rs6000_builtins start,
8286 enum rs6000_builtins end)
8290 for (i = 0; i < size; ++i)
8291 if (desc[i].code == start)
8297 for (; i < size; ++i)
8299 /* Flip all the bits on. */
8300 desc[i].mask = target_flags;
8301 if (desc[i].code == end)
8307 spe_init_builtins (void)
8309 tree endlink = void_list_node;
8310 tree puint_type_node = build_pointer_type (unsigned_type_node);
8311 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8312 struct builtin_description *d;
8315 tree v2si_ftype_4_v2si
8316 = build_function_type
8317 (opaque_V2SI_type_node,
8318 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8319 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8320 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8321 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8324 tree v2sf_ftype_4_v2sf
8325 = build_function_type
8326 (opaque_V2SF_type_node,
8327 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8328 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8329 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8330 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8333 tree int_ftype_int_v2si_v2si
8334 = build_function_type
8336 tree_cons (NULL_TREE, integer_type_node,
8337 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8338 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8341 tree int_ftype_int_v2sf_v2sf
8342 = build_function_type
8344 tree_cons (NULL_TREE, integer_type_node,
8345 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8346 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8349 tree void_ftype_v2si_puint_int
8350 = build_function_type (void_type_node,
8351 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8352 tree_cons (NULL_TREE, puint_type_node,
8353 tree_cons (NULL_TREE,
8357 tree void_ftype_v2si_puint_char
8358 = build_function_type (void_type_node,
8359 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8360 tree_cons (NULL_TREE, puint_type_node,
8361 tree_cons (NULL_TREE,
8365 tree void_ftype_v2si_pv2si_int
8366 = build_function_type (void_type_node,
8367 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8368 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8369 tree_cons (NULL_TREE,
8373 tree void_ftype_v2si_pv2si_char
8374 = build_function_type (void_type_node,
8375 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8376 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8377 tree_cons (NULL_TREE,
8382 = build_function_type (void_type_node,
8383 tree_cons (NULL_TREE, integer_type_node, endlink));
8386 = build_function_type (integer_type_node, endlink);
8388 tree v2si_ftype_pv2si_int
8389 = build_function_type (opaque_V2SI_type_node,
8390 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8391 tree_cons (NULL_TREE, integer_type_node,
8394 tree v2si_ftype_puint_int
8395 = build_function_type (opaque_V2SI_type_node,
8396 tree_cons (NULL_TREE, puint_type_node,
8397 tree_cons (NULL_TREE, integer_type_node,
8400 tree v2si_ftype_pushort_int
8401 = build_function_type (opaque_V2SI_type_node,
8402 tree_cons (NULL_TREE, pushort_type_node,
8403 tree_cons (NULL_TREE, integer_type_node,
8406 tree v2si_ftype_signed_char
8407 = build_function_type (opaque_V2SI_type_node,
8408 tree_cons (NULL_TREE, signed_char_type_node,
8411 /* The initialization of the simple binary and unary builtins is
8412 done in rs6000_common_init_builtins, but we have to enable the
8413 mask bits here manually because we have run out of `target_flags'
8414 bits. We really need to redesign this mask business. */
8416 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8417 ARRAY_SIZE (bdesc_2arg),
8420 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8421 ARRAY_SIZE (bdesc_1arg),
8423 SPE_BUILTIN_EVSUBFUSIAAW);
8424 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8425 ARRAY_SIZE (bdesc_spe_predicates),
8426 SPE_BUILTIN_EVCMPEQ,
8427 SPE_BUILTIN_EVFSTSTLT);
8428 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8429 ARRAY_SIZE (bdesc_spe_evsel),
8430 SPE_BUILTIN_EVSEL_CMPGTS,
8431 SPE_BUILTIN_EVSEL_FSTSTEQ);
8433 (*lang_hooks.decls.pushdecl)
8434 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8435 opaque_V2SI_type_node));
8437 /* Initialize irregular SPE builtins. */
8439 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8440 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8441 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8442 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8443 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8444 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8445 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8446 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8447 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8448 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8449 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8450 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8451 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8452 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8453 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8454 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8455 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8456 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8459 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8460 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8461 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8462 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8463 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8464 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8465 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8466 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8467 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8468 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8469 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8470 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8471 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8472 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8473 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8474 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8475 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8476 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8477 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8478 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8479 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8480 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8483 d = (struct builtin_description *) bdesc_spe_predicates;
8484 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8488 switch (insn_data[d->icode].operand[1].mode)
8491 type = int_ftype_int_v2si_v2si;
8494 type = int_ftype_int_v2sf_v2sf;
8500 def_builtin (d->mask, d->name, type, d->code);
8503 /* Evsel predicates. */
8504 d = (struct builtin_description *) bdesc_spe_evsel;
8505 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8509 switch (insn_data[d->icode].operand[1].mode)
8512 type = v2si_ftype_4_v2si;
8515 type = v2sf_ftype_4_v2sf;
8521 def_builtin (d->mask, d->name, type, d->code);
8526 altivec_init_builtins (void)
8528 struct builtin_description *d;
8529 struct builtin_description_predicates *dp;
8533 tree pfloat_type_node = build_pointer_type (float_type_node);
8534 tree pint_type_node = build_pointer_type (integer_type_node);
8535 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8536 tree pchar_type_node = build_pointer_type (char_type_node);
8538 tree pvoid_type_node = build_pointer_type (void_type_node);
8540 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8541 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8542 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8543 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8545 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8547 tree int_ftype_opaque
8548 = build_function_type_list (integer_type_node,
8549 opaque_V4SI_type_node, NULL_TREE);
8551 tree opaque_ftype_opaque_int
8552 = build_function_type_list (opaque_V4SI_type_node,
8553 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8554 tree opaque_ftype_opaque_opaque_int
8555 = build_function_type_list (opaque_V4SI_type_node,
8556 opaque_V4SI_type_node, opaque_V4SI_type_node,
8557 integer_type_node, NULL_TREE);
8558 tree int_ftype_int_opaque_opaque
8559 = build_function_type_list (integer_type_node,
8560 integer_type_node, opaque_V4SI_type_node,
8561 opaque_V4SI_type_node, NULL_TREE);
8562 tree int_ftype_int_v4si_v4si
8563 = build_function_type_list (integer_type_node,
8564 integer_type_node, V4SI_type_node,
8565 V4SI_type_node, NULL_TREE);
8566 tree v4sf_ftype_pcfloat
8567 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8568 tree void_ftype_pfloat_v4sf
8569 = build_function_type_list (void_type_node,
8570 pfloat_type_node, V4SF_type_node, NULL_TREE);
8571 tree v4si_ftype_pcint
8572 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8573 tree void_ftype_pint_v4si
8574 = build_function_type_list (void_type_node,
8575 pint_type_node, V4SI_type_node, NULL_TREE);
8576 tree v8hi_ftype_pcshort
8577 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8578 tree void_ftype_pshort_v8hi
8579 = build_function_type_list (void_type_node,
8580 pshort_type_node, V8HI_type_node, NULL_TREE);
8581 tree v16qi_ftype_pcchar
8582 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8583 tree void_ftype_pchar_v16qi
8584 = build_function_type_list (void_type_node,
8585 pchar_type_node, V16QI_type_node, NULL_TREE);
8586 tree void_ftype_v4si
8587 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8588 tree v8hi_ftype_void
8589 = build_function_type (V8HI_type_node, void_list_node);
8590 tree void_ftype_void
8591 = build_function_type (void_type_node, void_list_node);
8593 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8595 tree opaque_ftype_long_pcvoid
8596 = build_function_type_list (opaque_V4SI_type_node,
8597 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8598 tree v16qi_ftype_long_pcvoid
8599 = build_function_type_list (V16QI_type_node,
8600 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8601 tree v8hi_ftype_long_pcvoid
8602 = build_function_type_list (V8HI_type_node,
8603 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8604 tree v4si_ftype_long_pcvoid
8605 = build_function_type_list (V4SI_type_node,
8606 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8608 tree void_ftype_opaque_long_pvoid
8609 = build_function_type_list (void_type_node,
8610 opaque_V4SI_type_node, long_integer_type_node,
8611 pvoid_type_node, NULL_TREE);
8612 tree void_ftype_v4si_long_pvoid
8613 = build_function_type_list (void_type_node,
8614 V4SI_type_node, long_integer_type_node,
8615 pvoid_type_node, NULL_TREE);
8616 tree void_ftype_v16qi_long_pvoid
8617 = build_function_type_list (void_type_node,
8618 V16QI_type_node, long_integer_type_node,
8619 pvoid_type_node, NULL_TREE);
8620 tree void_ftype_v8hi_long_pvoid
8621 = build_function_type_list (void_type_node,
8622 V8HI_type_node, long_integer_type_node,
8623 pvoid_type_node, NULL_TREE);
8624 tree int_ftype_int_v8hi_v8hi
8625 = build_function_type_list (integer_type_node,
8626 integer_type_node, V8HI_type_node,
8627 V8HI_type_node, NULL_TREE);
8628 tree int_ftype_int_v16qi_v16qi
8629 = build_function_type_list (integer_type_node,
8630 integer_type_node, V16QI_type_node,
8631 V16QI_type_node, NULL_TREE);
8632 tree int_ftype_int_v4sf_v4sf
8633 = build_function_type_list (integer_type_node,
8634 integer_type_node, V4SF_type_node,
8635 V4SF_type_node, NULL_TREE);
8636 tree v4si_ftype_v4si
8637 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8638 tree v8hi_ftype_v8hi
8639 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8640 tree v16qi_ftype_v16qi
8641 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8642 tree v4sf_ftype_v4sf
8643 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8644 tree void_ftype_pcvoid_int_int
8645 = build_function_type_list (void_type_node,
8646 pcvoid_type_node, integer_type_node,
8647 integer_type_node, NULL_TREE);
8649 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8650 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8651 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8652 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8653 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8654 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8655 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8656 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8657 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8658 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8659 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8660 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8661 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8662 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8663 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8664 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8665 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8666 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8667 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8668 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8669 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8670 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8671 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8672 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8673 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8674 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8675 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8676 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8677 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8678 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8679 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8680 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8681 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8682 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8683 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8684 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8685 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8686 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8687 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8688 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8689 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8690 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8691 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8692 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8693 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8694 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8696 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8698 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8699 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8700 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8701 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8702 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8703 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8704 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8705 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8706 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8707 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8709 /* Add the DST variants. */
8710 d = (struct builtin_description *) bdesc_dst;
8711 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8712 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8714 /* Initialize the predicates. */
8715 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8716 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8718 enum machine_mode mode1;
8720 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8721 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8726 mode1 = insn_data[dp->icode].operand[1].mode;
8731 type = int_ftype_int_opaque_opaque;
8734 type = int_ftype_int_v4si_v4si;
8737 type = int_ftype_int_v8hi_v8hi;
8740 type = int_ftype_int_v16qi_v16qi;
8743 type = int_ftype_int_v4sf_v4sf;
8749 def_builtin (dp->mask, dp->name, type, dp->code);
8752 /* Initialize the abs* operators. */
8753 d = (struct builtin_description *) bdesc_abs;
8754 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8756 enum machine_mode mode0;
8759 mode0 = insn_data[d->icode].operand[0].mode;
8764 type = v4si_ftype_v4si;
8767 type = v8hi_ftype_v8hi;
8770 type = v16qi_ftype_v16qi;
8773 type = v4sf_ftype_v4sf;
8779 def_builtin (d->mask, d->name, type, d->code);
8786 /* Initialize target builtin that implements
8787 targetm.vectorize.builtin_mask_for_load. */
8789 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
8790 v16qi_ftype_long_pcvoid,
8791 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8793 tree_cons (get_identifier ("const"),
8794 NULL_TREE, NULL_TREE));
8795 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8796 altivec_builtin_mask_for_load = decl;
8799 /* Access to the vec_init patterns. */
8800 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8801 integer_type_node, integer_type_node,
8802 integer_type_node, NULL_TREE);
8803 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8804 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8806 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8807 short_integer_type_node,
8808 short_integer_type_node,
8809 short_integer_type_node,
8810 short_integer_type_node,
8811 short_integer_type_node,
8812 short_integer_type_node,
8813 short_integer_type_node, NULL_TREE);
8814 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8815 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8817 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8818 char_type_node, char_type_node,
8819 char_type_node, char_type_node,
8820 char_type_node, char_type_node,
8821 char_type_node, char_type_node,
8822 char_type_node, char_type_node,
8823 char_type_node, char_type_node,
8824 char_type_node, char_type_node,
8825 char_type_node, NULL_TREE);
8826 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8827 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8829 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8830 float_type_node, float_type_node,
8831 float_type_node, NULL_TREE);
8832 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8833 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8835 /* Access to the vec_set patterns. */
8836 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8838 integer_type_node, NULL_TREE);
8839 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8840 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8842 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8844 integer_type_node, NULL_TREE);
8845 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8846 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8848 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8850 integer_type_node, NULL_TREE);
8851 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8852 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8854 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8856 integer_type_node, NULL_TREE);
8857 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8858 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8860 /* Access to the vec_extract patterns. */
8861 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8862 integer_type_node, NULL_TREE);
8863 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8864 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8866 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8867 integer_type_node, NULL_TREE);
8868 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8869 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8871 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8872 integer_type_node, NULL_TREE);
8873 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8874 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8876 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8877 integer_type_node, NULL_TREE);
8878 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8879 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8883 rs6000_common_init_builtins (void)
8885 struct builtin_description *d;
8888 tree v4sf_ftype_v4sf_v4sf_v16qi
8889 = build_function_type_list (V4SF_type_node,
8890 V4SF_type_node, V4SF_type_node,
8891 V16QI_type_node, NULL_TREE);
8892 tree v4si_ftype_v4si_v4si_v16qi
8893 = build_function_type_list (V4SI_type_node,
8894 V4SI_type_node, V4SI_type_node,
8895 V16QI_type_node, NULL_TREE);
8896 tree v8hi_ftype_v8hi_v8hi_v16qi
8897 = build_function_type_list (V8HI_type_node,
8898 V8HI_type_node, V8HI_type_node,
8899 V16QI_type_node, NULL_TREE);
8900 tree v16qi_ftype_v16qi_v16qi_v16qi
8901 = build_function_type_list (V16QI_type_node,
8902 V16QI_type_node, V16QI_type_node,
8903 V16QI_type_node, NULL_TREE);
8905 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8907 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8908 tree v16qi_ftype_int
8909 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8910 tree v8hi_ftype_v16qi
8911 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8912 tree v4sf_ftype_v4sf
8913 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8915 tree v2si_ftype_v2si_v2si
8916 = build_function_type_list (opaque_V2SI_type_node,
8917 opaque_V2SI_type_node,
8918 opaque_V2SI_type_node, NULL_TREE);
8920 tree v2sf_ftype_v2sf_v2sf
8921 = build_function_type_list (opaque_V2SF_type_node,
8922 opaque_V2SF_type_node,
8923 opaque_V2SF_type_node, NULL_TREE);
8925 tree v2si_ftype_int_int
8926 = build_function_type_list (opaque_V2SI_type_node,
8927 integer_type_node, integer_type_node,
8930 tree opaque_ftype_opaque
8931 = build_function_type_list (opaque_V4SI_type_node,
8932 opaque_V4SI_type_node, NULL_TREE);
8934 tree v2si_ftype_v2si
8935 = build_function_type_list (opaque_V2SI_type_node,
8936 opaque_V2SI_type_node, NULL_TREE);
8938 tree v2sf_ftype_v2sf
8939 = build_function_type_list (opaque_V2SF_type_node,
8940 opaque_V2SF_type_node, NULL_TREE);
8942 tree v2sf_ftype_v2si
8943 = build_function_type_list (opaque_V2SF_type_node,
8944 opaque_V2SI_type_node, NULL_TREE);
8946 tree v2si_ftype_v2sf
8947 = build_function_type_list (opaque_V2SI_type_node,
8948 opaque_V2SF_type_node, NULL_TREE);
8950 tree v2si_ftype_v2si_char
8951 = build_function_type_list (opaque_V2SI_type_node,
8952 opaque_V2SI_type_node,
8953 char_type_node, NULL_TREE);
8955 tree v2si_ftype_int_char
8956 = build_function_type_list (opaque_V2SI_type_node,
8957 integer_type_node, char_type_node, NULL_TREE);
8959 tree v2si_ftype_char
8960 = build_function_type_list (opaque_V2SI_type_node,
8961 char_type_node, NULL_TREE);
8963 tree int_ftype_int_int
8964 = build_function_type_list (integer_type_node,
8965 integer_type_node, integer_type_node,
8968 tree opaque_ftype_opaque_opaque
8969 = build_function_type_list (opaque_V4SI_type_node,
8970 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8971 tree v4si_ftype_v4si_v4si
8972 = build_function_type_list (V4SI_type_node,
8973 V4SI_type_node, V4SI_type_node, NULL_TREE);
8974 tree v4sf_ftype_v4si_int
8975 = build_function_type_list (V4SF_type_node,
8976 V4SI_type_node, integer_type_node, NULL_TREE);
8977 tree v4si_ftype_v4sf_int
8978 = build_function_type_list (V4SI_type_node,
8979 V4SF_type_node, integer_type_node, NULL_TREE);
8980 tree v4si_ftype_v4si_int
8981 = build_function_type_list (V4SI_type_node,
8982 V4SI_type_node, integer_type_node, NULL_TREE);
8983 tree v8hi_ftype_v8hi_int
8984 = build_function_type_list (V8HI_type_node,
8985 V8HI_type_node, integer_type_node, NULL_TREE);
8986 tree v16qi_ftype_v16qi_int
8987 = build_function_type_list (V16QI_type_node,
8988 V16QI_type_node, integer_type_node, NULL_TREE);
8989 tree v16qi_ftype_v16qi_v16qi_int
8990 = build_function_type_list (V16QI_type_node,
8991 V16QI_type_node, V16QI_type_node,
8992 integer_type_node, NULL_TREE);
8993 tree v8hi_ftype_v8hi_v8hi_int
8994 = build_function_type_list (V8HI_type_node,
8995 V8HI_type_node, V8HI_type_node,
8996 integer_type_node, NULL_TREE);
8997 tree v4si_ftype_v4si_v4si_int
8998 = build_function_type_list (V4SI_type_node,
8999 V4SI_type_node, V4SI_type_node,
9000 integer_type_node, NULL_TREE);
9001 tree v4sf_ftype_v4sf_v4sf_int
9002 = build_function_type_list (V4SF_type_node,
9003 V4SF_type_node, V4SF_type_node,
9004 integer_type_node, NULL_TREE);
9005 tree v4sf_ftype_v4sf_v4sf
9006 = build_function_type_list (V4SF_type_node,
9007 V4SF_type_node, V4SF_type_node, NULL_TREE);
9008 tree opaque_ftype_opaque_opaque_opaque
9009 = build_function_type_list (opaque_V4SI_type_node,
9010 opaque_V4SI_type_node, opaque_V4SI_type_node,
9011 opaque_V4SI_type_node, NULL_TREE);
9012 tree v4sf_ftype_v4sf_v4sf_v4si
9013 = build_function_type_list (V4SF_type_node,
9014 V4SF_type_node, V4SF_type_node,
9015 V4SI_type_node, NULL_TREE);
9016 tree v4sf_ftype_v4sf_v4sf_v4sf
9017 = build_function_type_list (V4SF_type_node,
9018 V4SF_type_node, V4SF_type_node,
9019 V4SF_type_node, NULL_TREE);
9020 tree v4si_ftype_v4si_v4si_v4si
9021 = build_function_type_list (V4SI_type_node,
9022 V4SI_type_node, V4SI_type_node,
9023 V4SI_type_node, NULL_TREE);
9024 tree v8hi_ftype_v8hi_v8hi
9025 = build_function_type_list (V8HI_type_node,
9026 V8HI_type_node, V8HI_type_node, NULL_TREE);
9027 tree v8hi_ftype_v8hi_v8hi_v8hi
9028 = build_function_type_list (V8HI_type_node,
9029 V8HI_type_node, V8HI_type_node,
9030 V8HI_type_node, NULL_TREE);
9031 tree v4si_ftype_v8hi_v8hi_v4si
9032 = build_function_type_list (V4SI_type_node,
9033 V8HI_type_node, V8HI_type_node,
9034 V4SI_type_node, NULL_TREE);
9035 tree v4si_ftype_v16qi_v16qi_v4si
9036 = build_function_type_list (V4SI_type_node,
9037 V16QI_type_node, V16QI_type_node,
9038 V4SI_type_node, NULL_TREE);
9039 tree v16qi_ftype_v16qi_v16qi
9040 = build_function_type_list (V16QI_type_node,
9041 V16QI_type_node, V16QI_type_node, NULL_TREE);
9042 tree v4si_ftype_v4sf_v4sf
9043 = build_function_type_list (V4SI_type_node,
9044 V4SF_type_node, V4SF_type_node, NULL_TREE);
9045 tree v8hi_ftype_v16qi_v16qi
9046 = build_function_type_list (V8HI_type_node,
9047 V16QI_type_node, V16QI_type_node, NULL_TREE);
9048 tree v4si_ftype_v8hi_v8hi
9049 = build_function_type_list (V4SI_type_node,
9050 V8HI_type_node, V8HI_type_node, NULL_TREE);
9051 tree v8hi_ftype_v4si_v4si
9052 = build_function_type_list (V8HI_type_node,
9053 V4SI_type_node, V4SI_type_node, NULL_TREE);
9054 tree v16qi_ftype_v8hi_v8hi
9055 = build_function_type_list (V16QI_type_node,
9056 V8HI_type_node, V8HI_type_node, NULL_TREE);
9057 tree v4si_ftype_v16qi_v4si
9058 = build_function_type_list (V4SI_type_node,
9059 V16QI_type_node, V4SI_type_node, NULL_TREE);
9060 tree v4si_ftype_v16qi_v16qi
9061 = build_function_type_list (V4SI_type_node,
9062 V16QI_type_node, V16QI_type_node, NULL_TREE);
9063 tree v4si_ftype_v8hi_v4si
9064 = build_function_type_list (V4SI_type_node,
9065 V8HI_type_node, V4SI_type_node, NULL_TREE);
9066 tree v4si_ftype_v8hi
9067 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9068 tree int_ftype_v4si_v4si
9069 = build_function_type_list (integer_type_node,
9070 V4SI_type_node, V4SI_type_node, NULL_TREE);
9071 tree int_ftype_v4sf_v4sf
9072 = build_function_type_list (integer_type_node,
9073 V4SF_type_node, V4SF_type_node, NULL_TREE);
9074 tree int_ftype_v16qi_v16qi
9075 = build_function_type_list (integer_type_node,
9076 V16QI_type_node, V16QI_type_node, NULL_TREE);
9077 tree int_ftype_v8hi_v8hi
9078 = build_function_type_list (integer_type_node,
9079 V8HI_type_node, V8HI_type_node, NULL_TREE);
9081 /* Add the simple ternary operators. */
9082 d = (struct builtin_description *) bdesc_3arg;
9083 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9085 enum machine_mode mode0, mode1, mode2, mode3;
9087 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9088 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9099 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9102 mode0 = insn_data[d->icode].operand[0].mode;
9103 mode1 = insn_data[d->icode].operand[1].mode;
9104 mode2 = insn_data[d->icode].operand[2].mode;
9105 mode3 = insn_data[d->icode].operand[3].mode;
9108 /* When all four are of the same mode. */
9109 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9114 type = opaque_ftype_opaque_opaque_opaque;
9117 type = v4si_ftype_v4si_v4si_v4si;
9120 type = v4sf_ftype_v4sf_v4sf_v4sf;
9123 type = v8hi_ftype_v8hi_v8hi_v8hi;
9126 type = v16qi_ftype_v16qi_v16qi_v16qi;
9132 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9137 type = v4si_ftype_v4si_v4si_v16qi;
9140 type = v4sf_ftype_v4sf_v4sf_v16qi;
9143 type = v8hi_ftype_v8hi_v8hi_v16qi;
9146 type = v16qi_ftype_v16qi_v16qi_v16qi;
9152 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9153 && mode3 == V4SImode)
9154 type = v4si_ftype_v16qi_v16qi_v4si;
9155 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9156 && mode3 == V4SImode)
9157 type = v4si_ftype_v8hi_v8hi_v4si;
9158 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9159 && mode3 == V4SImode)
9160 type = v4sf_ftype_v4sf_v4sf_v4si;
9162 /* vchar, vchar, vchar, 4 bit literal. */
9163 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9165 type = v16qi_ftype_v16qi_v16qi_int;
9167 /* vshort, vshort, vshort, 4 bit literal. */
9168 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9170 type = v8hi_ftype_v8hi_v8hi_int;
9172 /* vint, vint, vint, 4 bit literal. */
9173 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9175 type = v4si_ftype_v4si_v4si_int;
9177 /* vfloat, vfloat, vfloat, 4 bit literal. */
9178 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9180 type = v4sf_ftype_v4sf_v4sf_int;
9185 def_builtin (d->mask, d->name, type, d->code);
9188 /* Add the simple binary operators. */
9189 d = (struct builtin_description *) bdesc_2arg;
9190 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9192 enum machine_mode mode0, mode1, mode2;
9194 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9195 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9205 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9208 mode0 = insn_data[d->icode].operand[0].mode;
9209 mode1 = insn_data[d->icode].operand[1].mode;
9210 mode2 = insn_data[d->icode].operand[2].mode;
9213 /* When all three operands are of the same mode. */
9214 if (mode0 == mode1 && mode1 == mode2)
9219 type = opaque_ftype_opaque_opaque;
9222 type = v4sf_ftype_v4sf_v4sf;
9225 type = v4si_ftype_v4si_v4si;
9228 type = v16qi_ftype_v16qi_v16qi;
9231 type = v8hi_ftype_v8hi_v8hi;
9234 type = v2si_ftype_v2si_v2si;
9237 type = v2sf_ftype_v2sf_v2sf;
9240 type = int_ftype_int_int;
9247 /* A few other combos we really don't want to do manually. */
9249 /* vint, vfloat, vfloat. */
9250 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9251 type = v4si_ftype_v4sf_v4sf;
9253 /* vshort, vchar, vchar. */
9254 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9255 type = v8hi_ftype_v16qi_v16qi;
9257 /* vint, vshort, vshort. */
9258 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9259 type = v4si_ftype_v8hi_v8hi;
9261 /* vshort, vint, vint. */
9262 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9263 type = v8hi_ftype_v4si_v4si;
9265 /* vchar, vshort, vshort. */
9266 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9267 type = v16qi_ftype_v8hi_v8hi;
9269 /* vint, vchar, vint. */
9270 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9271 type = v4si_ftype_v16qi_v4si;
9273 /* vint, vchar, vchar. */
9274 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9275 type = v4si_ftype_v16qi_v16qi;
9277 /* vint, vshort, vint. */
9278 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9279 type = v4si_ftype_v8hi_v4si;
9281 /* vint, vint, 5 bit literal. */
9282 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9283 type = v4si_ftype_v4si_int;
9285 /* vshort, vshort, 5 bit literal. */
9286 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9287 type = v8hi_ftype_v8hi_int;
9289 /* vchar, vchar, 5 bit literal. */
9290 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9291 type = v16qi_ftype_v16qi_int;
9293 /* vfloat, vint, 5 bit literal. */
9294 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9295 type = v4sf_ftype_v4si_int;
9297 /* vint, vfloat, 5 bit literal. */
9298 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9299 type = v4si_ftype_v4sf_int;
9301 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9302 type = v2si_ftype_int_int;
9304 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9305 type = v2si_ftype_v2si_char;
9307 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9308 type = v2si_ftype_int_char;
9313 gcc_assert (mode0 == SImode);
9317 type = int_ftype_v4si_v4si;
9320 type = int_ftype_v4sf_v4sf;
9323 type = int_ftype_v16qi_v16qi;
9326 type = int_ftype_v8hi_v8hi;
9333 def_builtin (d->mask, d->name, type, d->code);
9336 /* Add the simple unary operators. */
9337 d = (struct builtin_description *) bdesc_1arg;
9338 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9340 enum machine_mode mode0, mode1;
9342 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9343 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9352 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9355 mode0 = insn_data[d->icode].operand[0].mode;
9356 mode1 = insn_data[d->icode].operand[1].mode;
9359 if (mode0 == V4SImode && mode1 == QImode)
9360 type = v4si_ftype_int;
9361 else if (mode0 == V8HImode && mode1 == QImode)
9362 type = v8hi_ftype_int;
9363 else if (mode0 == V16QImode && mode1 == QImode)
9364 type = v16qi_ftype_int;
9365 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9366 type = opaque_ftype_opaque;
9367 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9368 type = v4sf_ftype_v4sf;
9369 else if (mode0 == V8HImode && mode1 == V16QImode)
9370 type = v8hi_ftype_v16qi;
9371 else if (mode0 == V4SImode && mode1 == V8HImode)
9372 type = v4si_ftype_v8hi;
9373 else if (mode0 == V2SImode && mode1 == V2SImode)
9374 type = v2si_ftype_v2si;
9375 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9376 type = v2sf_ftype_v2sf;
9377 else if (mode0 == V2SFmode && mode1 == V2SImode)
9378 type = v2sf_ftype_v2si;
9379 else if (mode0 == V2SImode && mode1 == V2SFmode)
9380 type = v2si_ftype_v2sf;
9381 else if (mode0 == V2SImode && mode1 == QImode)
9382 type = v2si_ftype_char;
9386 def_builtin (d->mask, d->name, type, d->code);
9391 rs6000_init_libfuncs (void)
9393 if (!TARGET_HARD_FLOAT)
9396 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9397 && !TARGET_POWER2 && !TARGET_POWERPC)
9399 /* AIX library routines for float->int conversion. */
9400 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9401 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9402 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9403 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9406 if (!TARGET_IEEEQUAD)
9407 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9408 if (!TARGET_XL_COMPAT)
9410 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9411 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9412 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9413 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9417 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9418 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9419 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9420 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9424 /* 32-bit SVR4 quad floating point routines. */
9426 set_optab_libfunc (add_optab, TFmode, "_q_add");
9427 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9428 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9429 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9430 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9431 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9432 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9434 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9435 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9436 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9437 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9438 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9439 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9441 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9442 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9443 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9444 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9445 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9446 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9447 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9448 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9453 /* Expand a block clear operation, and return 1 if successful. Return 0
9454 if we should let the compiler generate normal code.
9456 operands[0] is the destination
9457 operands[1] is the length
9458 operands[3] is the alignment */
9461 expand_block_clear (rtx operands[])
9463 rtx orig_dest = operands[0];
9464 rtx bytes_rtx = operands[1];
9465 rtx align_rtx = operands[3];
9466 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9467 HOST_WIDE_INT align;
9468 HOST_WIDE_INT bytes;
9473 /* If this is not a fixed size move, just call memcpy */
9477 /* This must be a fixed size alignment */
9478 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9479 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9481 /* Anything to clear? */
9482 bytes = INTVAL (bytes_rtx);
9486 /* Use the builtin memset after a point, to avoid huge code bloat.
9487 When optimize_size, avoid any significant code bloat; calling
9488 memset is about 4 instructions, so allow for one instruction to
9489 load zero and three to do clearing. */
9490 if (TARGET_ALTIVEC && align >= 128)
9492 else if (TARGET_POWERPC64 && align >= 32)
9497 if (optimize_size && bytes > 3 * clear_step)
9499 if (! optimize_size && bytes > 8 * clear_step)
9502 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9504 enum machine_mode mode = BLKmode;
9507 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9512 else if (bytes >= 8 && TARGET_POWERPC64
9513 /* 64-bit loads and stores require word-aligned
9515 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9520 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9521 { /* move 4 bytes */
9525 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9526 { /* move 2 bytes */
9530 else /* move 1 byte at a time */
9536 dest = adjust_address (orig_dest, mode, offset);
9538 emit_move_insn (dest, CONST0_RTX (mode));
9545 /* Expand a block move operation, and return 1 if successful. Return 0
9546 if we should let the compiler generate normal code.
9548 operands[0] is the destination
9549 operands[1] is the source
9550 operands[2] is the length
9551 operands[3] is the alignment */
9553 #define MAX_MOVE_REG 4
9556 expand_block_move (rtx operands[])
9558 rtx orig_dest = operands[0];
9559 rtx orig_src = operands[1];
9560 rtx bytes_rtx = operands[2];
9561 rtx align_rtx = operands[3];
9562 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9567 rtx stores[MAX_MOVE_REG];
9570 /* If this is not a fixed size move, just call memcpy */
9574 /* This must be a fixed size alignment */
9575 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9576 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9578 /* Anything to move? */
9579 bytes = INTVAL (bytes_rtx);
9583 /* store_one_arg depends on expand_block_move to handle at least the size of
9584 reg_parm_stack_space. */
9585 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9588 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9591 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9592 rtx (*mov) (rtx, rtx);
9594 enum machine_mode mode = BLKmode;
9597 /* Altivec first, since it will be faster than a string move
9598 when it applies, and usually not significantly larger. */
9599 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9603 gen_func.mov = gen_movv4si;
9605 else if (TARGET_STRING
9606 && bytes > 24 /* move up to 32 bytes at a time */
9614 && ! fixed_regs[12])
9616 move_bytes = (bytes > 32) ? 32 : bytes;
9617 gen_func.movmemsi = gen_movmemsi_8reg;
9619 else if (TARGET_STRING
9620 && bytes > 16 /* move up to 24 bytes at a time */
9626 && ! fixed_regs[10])
9628 move_bytes = (bytes > 24) ? 24 : bytes;
9629 gen_func.movmemsi = gen_movmemsi_6reg;
9631 else if (TARGET_STRING
9632 && bytes > 8 /* move up to 16 bytes at a time */
9638 move_bytes = (bytes > 16) ? 16 : bytes;
9639 gen_func.movmemsi = gen_movmemsi_4reg;
9641 else if (bytes >= 8 && TARGET_POWERPC64
9642 /* 64-bit loads and stores require word-aligned
9644 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9648 gen_func.mov = gen_movdi;
9650 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9651 { /* move up to 8 bytes at a time */
9652 move_bytes = (bytes > 8) ? 8 : bytes;
9653 gen_func.movmemsi = gen_movmemsi_2reg;
9655 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9656 { /* move 4 bytes */
9659 gen_func.mov = gen_movsi;
9661 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9662 { /* move 2 bytes */
9665 gen_func.mov = gen_movhi;
9667 else if (TARGET_STRING && bytes > 1)
9668 { /* move up to 4 bytes at a time */
9669 move_bytes = (bytes > 4) ? 4 : bytes;
9670 gen_func.movmemsi = gen_movmemsi_1reg;
9672 else /* move 1 byte at a time */
9676 gen_func.mov = gen_movqi;
9679 src = adjust_address (orig_src, mode, offset);
9680 dest = adjust_address (orig_dest, mode, offset);
9682 if (mode != BLKmode)
9684 rtx tmp_reg = gen_reg_rtx (mode);
9686 emit_insn ((*gen_func.mov) (tmp_reg, src));
9687 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9690 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9693 for (i = 0; i < num_reg; i++)
9694 emit_insn (stores[i]);
9698 if (mode == BLKmode)
9700 /* Move the address into scratch registers. The movmemsi
9701 patterns require zero offset. */
9702 if (!REG_P (XEXP (src, 0)))
9704 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9705 src = replace_equiv_address (src, src_reg);
9707 set_mem_size (src, GEN_INT (move_bytes));
9709 if (!REG_P (XEXP (dest, 0)))
9711 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9712 dest = replace_equiv_address (dest, dest_reg);
9714 set_mem_size (dest, GEN_INT (move_bytes));
9716 emit_insn ((*gen_func.movmemsi) (dest, src,
9717 GEN_INT (move_bytes & 31),
9726 /* Return a string to perform a load_multiple operation.
9727 operands[0] is the vector.
9728 operands[1] is the source address.
9729 operands[2] is the first destination register. */
9732 rs6000_output_load_multiple (rtx operands[3])
9734 /* We have to handle the case where the pseudo used to contain the address
9735 is assigned to one of the output registers. */
9737 int words = XVECLEN (operands[0], 0);
9740 if (XVECLEN (operands[0], 0) == 1)
9741 return "{l|lwz} %2,0(%1)";
9743 for (i = 0; i < words; i++)
9744 if (refers_to_regno_p (REGNO (operands[2]) + i,
9745 REGNO (operands[2]) + i + 1, operands[1], 0))
9749 xop[0] = GEN_INT (4 * (words-1));
9750 xop[1] = operands[1];
9751 xop[2] = operands[2];
9752 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9757 xop[0] = GEN_INT (4 * (words-1));
9758 xop[1] = operands[1];
9759 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9760 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9765 for (j = 0; j < words; j++)
9768 xop[0] = GEN_INT (j * 4);
9769 xop[1] = operands[1];
9770 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9771 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9773 xop[0] = GEN_INT (i * 4);
9774 xop[1] = operands[1];
9775 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9780 return "{lsi|lswi} %2,%1,%N0";
9784 /* A validation routine: say whether CODE, a condition code, and MODE
9785 match. The other alternatives either don't make sense or should
9786 never be generated. */
9789 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9791 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9792 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9793 && GET_MODE_CLASS (mode) == MODE_CC);
9795 /* These don't make sense. */
9796 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9797 || mode != CCUNSmode);
9799 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9800 || mode == CCUNSmode);
9802 gcc_assert (mode == CCFPmode
9803 || (code != ORDERED && code != UNORDERED
9804 && code != UNEQ && code != LTGT
9805 && code != UNGT && code != UNLT
9806 && code != UNGE && code != UNLE));
9808 /* These should never be generated except for
9809 flag_finite_math_only. */
9810 gcc_assert (mode != CCFPmode
9811 || flag_finite_math_only
9812 || (code != LE && code != GE
9813 && code != UNEQ && code != LTGT
9814 && code != UNGT && code != UNLT));
9816 /* These are invalid; the information is not there. */
9817 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9821 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9822 mask required to convert the result of a rotate insn into a shift
9823 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9826 includes_lshift_p (rtx shiftop, rtx andop)
9828 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9830 shift_mask <<= INTVAL (shiftop);
9832 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9835 /* Similar, but for right shift. */
9838 includes_rshift_p (rtx shiftop, rtx andop)
9840 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9842 shift_mask >>= INTVAL (shiftop);
9844 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9847 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9848 to perform a left shift. It must have exactly SHIFTOP least
9849 significant 0's, then one or more 1's, then zero or more 0's. */
9852 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9854 if (GET_CODE (andop) == CONST_INT)
9856 HOST_WIDE_INT c, lsb, shift_mask;
9859 if (c == 0 || c == ~0)
9863 shift_mask <<= INTVAL (shiftop);
9865 /* Find the least significant one bit. */
9868 /* It must coincide with the LSB of the shift mask. */
9869 if (-lsb != shift_mask)
9872 /* Invert to look for the next transition (if any). */
9875 /* Remove the low group of ones (originally low group of zeros). */
9878 /* Again find the lsb, and check we have all 1's above. */
9882 else if (GET_CODE (andop) == CONST_DOUBLE
9883 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9885 HOST_WIDE_INT low, high, lsb;
9886 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9888 low = CONST_DOUBLE_LOW (andop);
9889 if (HOST_BITS_PER_WIDE_INT < 64)
9890 high = CONST_DOUBLE_HIGH (andop);
9892 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9893 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9896 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9898 shift_mask_high = ~0;
9899 if (INTVAL (shiftop) > 32)
9900 shift_mask_high <<= INTVAL (shiftop) - 32;
9904 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9911 return high == -lsb;
9914 shift_mask_low = ~0;
9915 shift_mask_low <<= INTVAL (shiftop);
9919 if (-lsb != shift_mask_low)
9922 if (HOST_BITS_PER_WIDE_INT < 64)
9927 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9930 return high == -lsb;
9934 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9940 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9941 to perform a left shift. It must have SHIFTOP or more least
9942 significant 0's, with the remainder of the word 1's. */
9945 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9947 if (GET_CODE (andop) == CONST_INT)
9949 HOST_WIDE_INT c, lsb, shift_mask;
9952 shift_mask <<= INTVAL (shiftop);
9955 /* Find the least significant one bit. */
9958 /* It must be covered by the shift mask.
9959 This test also rejects c == 0. */
9960 if ((lsb & shift_mask) == 0)
9963 /* Check we have all 1's above the transition, and reject all 1's. */
9964 return c == -lsb && lsb != 1;
9966 else if (GET_CODE (andop) == CONST_DOUBLE
9967 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9969 HOST_WIDE_INT low, lsb, shift_mask_low;
9971 low = CONST_DOUBLE_LOW (andop);
9973 if (HOST_BITS_PER_WIDE_INT < 64)
9975 HOST_WIDE_INT high, shift_mask_high;
9977 high = CONST_DOUBLE_HIGH (andop);
9981 shift_mask_high = ~0;
9982 if (INTVAL (shiftop) > 32)
9983 shift_mask_high <<= INTVAL (shiftop) - 32;
9987 if ((lsb & shift_mask_high) == 0)
9990 return high == -lsb;
9996 shift_mask_low = ~0;
9997 shift_mask_low <<= INTVAL (shiftop);
10001 if ((lsb & shift_mask_low) == 0)
10004 return low == -lsb && lsb != 1;
10010 /* Return 1 if operands will generate a valid arguments to rlwimi
10011 instruction for insert with right shift in 64-bit mode. The mask may
10012 not start on the first bit or stop on the last bit because wrap-around
10013 effects of instruction do not correspond to semantics of RTL insn. */
10016 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10018 if (INTVAL (startop) > 32
10019 && INTVAL (startop) < 64
10020 && INTVAL (sizeop) > 1
10021 && INTVAL (sizeop) + INTVAL (startop) < 64
10022 && INTVAL (shiftop) > 0
10023 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10024 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10030 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10031 for lfq and stfq insns iff the registers are hard registers. */
10034 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10036 /* We might have been passed a SUBREG. */
10037 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10040 /* We might have been passed non floating point registers. */
10041 if (!FP_REGNO_P (REGNO (reg1))
10042 || !FP_REGNO_P (REGNO (reg2)))
10045 return (REGNO (reg1) == REGNO (reg2) - 1);
10048 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10049 addr1 and addr2 must be in consecutive memory locations
10050 (addr2 == addr1 + 8). */
10053 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10056 unsigned int reg1, reg2;
10057 int offset1, offset2;
10059 /* The mems cannot be volatile. */
10060 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10063 addr1 = XEXP (mem1, 0);
10064 addr2 = XEXP (mem2, 0);
10066 /* Extract an offset (if used) from the first addr. */
10067 if (GET_CODE (addr1) == PLUS)
10069 /* If not a REG, return zero. */
10070 if (GET_CODE (XEXP (addr1, 0)) != REG)
10074 reg1 = REGNO (XEXP (addr1, 0));
10075 /* The offset must be constant! */
10076 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10078 offset1 = INTVAL (XEXP (addr1, 1));
10081 else if (GET_CODE (addr1) != REG)
10085 reg1 = REGNO (addr1);
10086 /* This was a simple (mem (reg)) expression. Offset is 0. */
10090 /* And now for the second addr. */
10091 if (GET_CODE (addr2) == PLUS)
10093 /* If not a REG, return zero. */
10094 if (GET_CODE (XEXP (addr2, 0)) != REG)
10098 reg2 = REGNO (XEXP (addr2, 0));
10099 /* The offset must be constant. */
10100 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10102 offset2 = INTVAL (XEXP (addr2, 1));
10105 else if (GET_CODE (addr2) != REG)
10109 reg2 = REGNO (addr2);
10110 /* This was a simple (mem (reg)) expression. Offset is 0. */
10114 /* Both of these must have the same base register. */
10118 /* The offset for the second addr must be 8 more than the first addr. */
10119 if (offset2 != offset1 + 8)
10122 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10127 /* Return the register class of a scratch register needed to copy IN into
10128 or out of a register in CLASS in MODE. If it can be done directly,
10129 NO_REGS is returned. */
10132 rs6000_secondary_reload_class (enum reg_class class,
10133 enum machine_mode mode ATTRIBUTE_UNUSED,
10138 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10140 && MACHOPIC_INDIRECT
10144 /* We cannot copy a symbolic operand directly into anything
10145 other than BASE_REGS for TARGET_ELF. So indicate that a
10146 register from BASE_REGS is needed as an intermediate
10149 On Darwin, pic addresses require a load from memory, which
10150 needs a base register. */
10151 if (class != BASE_REGS
10152 && (GET_CODE (in) == SYMBOL_REF
10153 || GET_CODE (in) == HIGH
10154 || GET_CODE (in) == LABEL_REF
10155 || GET_CODE (in) == CONST))
10159 if (GET_CODE (in) == REG)
10161 regno = REGNO (in);
10162 if (regno >= FIRST_PSEUDO_REGISTER)
10164 regno = true_regnum (in);
10165 if (regno >= FIRST_PSEUDO_REGISTER)
10169 else if (GET_CODE (in) == SUBREG)
10171 regno = true_regnum (in);
10172 if (regno >= FIRST_PSEUDO_REGISTER)
10178 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10180 if (class == GENERAL_REGS || class == BASE_REGS
10181 || (regno >= 0 && INT_REGNO_P (regno)))
10184 /* Constants, memory, and FP registers can go into FP registers. */
10185 if ((regno == -1 || FP_REGNO_P (regno))
10186 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10189 /* Memory, and AltiVec registers can go into AltiVec registers. */
10190 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10191 && class == ALTIVEC_REGS)
10194 /* We can copy among the CR registers. */
10195 if ((class == CR_REGS || class == CR0_REGS)
10196 && regno >= 0 && CR_REGNO_P (regno))
10199 /* Otherwise, we need GENERAL_REGS. */
10200 return GENERAL_REGS;
10203 /* Given a comparison operation, return the bit number in CCR to test. We
10204 know this is a valid comparison.
10206 SCC_P is 1 if this is for an scc. That means that %D will have been
10207 used instead of %C, so the bits will be in different places.
10209 Return -1 if OP isn't a valid comparison for some reason. */
10212 ccr_bit (rtx op, int scc_p)
10214 enum rtx_code code = GET_CODE (op);
10215 enum machine_mode cc_mode;
10220 if (!COMPARISON_P (op))
10223 reg = XEXP (op, 0);
10225 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10227 cc_mode = GET_MODE (reg);
10228 cc_regnum = REGNO (reg);
10229 base_bit = 4 * (cc_regnum - CR0_REGNO);
10231 validate_condition_mode (code, cc_mode);
10233 /* When generating a sCOND operation, only positive conditions are
10236 || code == EQ || code == GT || code == LT || code == UNORDERED
10237 || code == GTU || code == LTU);
10242 return scc_p ? base_bit + 3 : base_bit + 2;
10244 return base_bit + 2;
10245 case GT: case GTU: case UNLE:
10246 return base_bit + 1;
10247 case LT: case LTU: case UNGE:
10249 case ORDERED: case UNORDERED:
10250 return base_bit + 3;
10253 /* If scc, we will have done a cror to put the bit in the
10254 unordered position. So test that bit. For integer, this is ! LT
10255 unless this is an scc insn. */
10256 return scc_p ? base_bit + 3 : base_bit;
10259 return scc_p ? base_bit + 3 : base_bit + 1;
10262 gcc_unreachable ();
10266 /* Return the GOT register. */
10269 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10271 /* The second flow pass currently (June 1999) can't update
10272 regs_ever_live without disturbing other parts of the compiler, so
10273 update it here to make the prolog/epilogue code happy. */
10274 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
10275 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
10277 current_function_uses_pic_offset_table = 1;
10279 return pic_offset_table_rtx;
10282 /* Function to init struct machine_function.
10283 This will be called, via a pointer variable,
10284 from push_function_context. */
10286 static struct machine_function *
10287 rs6000_init_machine_status (void)
10289 return ggc_alloc_cleared (sizeof (machine_function));
10292 /* These macros test for integers and extract the low-order bits. */
10294 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10295 && GET_MODE (X) == VOIDmode)
10297 #define INT_LOWPART(X) \
10298 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10301 extract_MB (rtx op)
10304 unsigned long val = INT_LOWPART (op);
10306 /* If the high bit is zero, the value is the first 1 bit we find
10308 if ((val & 0x80000000) == 0)
10310 gcc_assert (val & 0xffffffff);
10313 while (((val <<= 1) & 0x80000000) == 0)
10318 /* If the high bit is set and the low bit is not, or the mask is all
10319 1's, the value is zero. */
10320 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10323 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10326 while (((val >>= 1) & 1) != 0)
10333 extract_ME (rtx op)
10336 unsigned long val = INT_LOWPART (op);
10338 /* If the low bit is zero, the value is the first 1 bit we find from
10340 if ((val & 1) == 0)
10342 gcc_assert (val & 0xffffffff);
10345 while (((val >>= 1) & 1) == 0)
10351 /* If the low bit is set and the high bit is not, or the mask is all
10352 1's, the value is 31. */
10353 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10356 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10359 while (((val <<= 1) & 0x80000000) != 0)
10365 /* Locate some local-dynamic symbol still in use by this function
10366 so that we can print its name in some tls_ld pattern. */
10368 static const char *
10369 rs6000_get_some_local_dynamic_name (void)
10373 if (cfun->machine->some_ld_name)
10374 return cfun->machine->some_ld_name;
10376 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10378 && for_each_rtx (&PATTERN (insn),
10379 rs6000_get_some_local_dynamic_name_1, 0))
10380 return cfun->machine->some_ld_name;
10382 gcc_unreachable ();
10385 /* Helper function for rs6000_get_some_local_dynamic_name. */
10388 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10392 if (GET_CODE (x) == SYMBOL_REF)
10394 const char *str = XSTR (x, 0);
10395 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10397 cfun->machine->some_ld_name = str;
10405 /* Write out a function code label. */
10408 rs6000_output_function_entry (FILE *file, const char *fname)
10410 if (fname[0] != '.')
10412 switch (DEFAULT_ABI)
10415 gcc_unreachable ();
10421 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10430 RS6000_OUTPUT_BASENAME (file, fname);
10432 assemble_name (file, fname);
10435 /* Print an operand. Recognize special options, documented below. */
10438 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10439 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10441 #define SMALL_DATA_RELOC "sda21"
10442 #define SMALL_DATA_REG 0
10446 print_operand (FILE *file, rtx x, int code)
10450 unsigned HOST_WIDE_INT uval;
10455 /* Write out an instruction after the call which may be replaced
10456 with glue code by the loader. This depends on the AIX version. */
10457 asm_fprintf (file, RS6000_CALL_GLUE);
10460 /* %a is output_address. */
10463 /* If X is a constant integer whose low-order 5 bits are zero,
10464 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10465 in the AIX assembler where "sri" with a zero shift count
10466 writes a trash instruction. */
10467 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10474 /* If constant, low-order 16 bits of constant, unsigned.
10475 Otherwise, write normally. */
10477 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10479 print_operand (file, x, 0);
10483 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10484 for 64-bit mask direction. */
10485 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10488 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10492 /* X is a CR register. Print the number of the GT bit of the CR. */
10493 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10494 output_operand_lossage ("invalid %%E value");
10496 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10500 /* Like 'J' but get to the GT bit only. */
10501 gcc_assert (GET_CODE (x) == REG);
10503 /* Bit 1 is GT bit. */
10504 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10506 /* Add one for shift count in rlinm for scc. */
10507 fprintf (file, "%d", i + 1);
10511 /* X is a CR register. Print the number of the EQ bit of the CR */
10512 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10513 output_operand_lossage ("invalid %%E value");
10515 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10519 /* X is a CR register. Print the shift count needed to move it
10520 to the high-order four bits. */
10521 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10522 output_operand_lossage ("invalid %%f value");
10524 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10528 /* Similar, but print the count for the rotate in the opposite
10530 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10531 output_operand_lossage ("invalid %%F value");
10533 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10537 /* X is a constant integer. If it is negative, print "m",
10538 otherwise print "z". This is to make an aze or ame insn. */
10539 if (GET_CODE (x) != CONST_INT)
10540 output_operand_lossage ("invalid %%G value");
10541 else if (INTVAL (x) >= 0)
10548 /* If constant, output low-order five bits. Otherwise, write
10551 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10553 print_operand (file, x, 0);
10557 /* If constant, output low-order six bits. Otherwise, write
10560 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10562 print_operand (file, x, 0);
10566 /* Print `i' if this is a constant, else nothing. */
10572 /* Write the bit number in CCR for jump. */
10573 i = ccr_bit (x, 0);
10575 output_operand_lossage ("invalid %%j code");
10577 fprintf (file, "%d", i);
10581 /* Similar, but add one for shift count in rlinm for scc and pass
10582 scc flag to `ccr_bit'. */
10583 i = ccr_bit (x, 1);
10585 output_operand_lossage ("invalid %%J code");
10587 /* If we want bit 31, write a shift count of zero, not 32. */
10588 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10592 /* X must be a constant. Write the 1's complement of the
10595 output_operand_lossage ("invalid %%k value");
10597 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10601 /* X must be a symbolic constant on ELF. Write an
10602 expression suitable for an 'addi' that adds in the low 16
10603 bits of the MEM. */
10604 if (GET_CODE (x) != CONST)
10606 print_operand_address (file, x);
10607 fputs ("@l", file);
10611 if (GET_CODE (XEXP (x, 0)) != PLUS
10612 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10613 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10614 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10615 output_operand_lossage ("invalid %%K value");
10616 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10617 fputs ("@l", file);
10618 /* For GNU as, there must be a non-alphanumeric character
10619 between 'l' and the number. The '-' is added by
10620 print_operand() already. */
10621 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10623 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10627 /* %l is output_asm_label. */
10630 /* Write second word of DImode or DFmode reference. Works on register
10631 or non-indexed memory only. */
10632 if (GET_CODE (x) == REG)
10633 fputs (reg_names[REGNO (x) + 1], file);
10634 else if (GET_CODE (x) == MEM)
10636 /* Handle possible auto-increment. Since it is pre-increment and
10637 we have already done it, we can just use an offset of word. */
10638 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10639 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10640 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10643 output_address (XEXP (adjust_address_nv (x, SImode,
10647 if (small_data_operand (x, GET_MODE (x)))
10648 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10649 reg_names[SMALL_DATA_REG]);
10654 /* MB value for a mask operand. */
10655 if (! mask_operand (x, SImode))
10656 output_operand_lossage ("invalid %%m value");
10658 fprintf (file, "%d", extract_MB (x));
10662 /* ME value for a mask operand. */
10663 if (! mask_operand (x, SImode))
10664 output_operand_lossage ("invalid %%M value");
10666 fprintf (file, "%d", extract_ME (x));
10669 /* %n outputs the negative of its operand. */
10672 /* Write the number of elements in the vector times 4. */
10673 if (GET_CODE (x) != PARALLEL)
10674 output_operand_lossage ("invalid %%N value");
10676 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10680 /* Similar, but subtract 1 first. */
10681 if (GET_CODE (x) != PARALLEL)
10682 output_operand_lossage ("invalid %%O value");
10684 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10688 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10690 || INT_LOWPART (x) < 0
10691 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10692 output_operand_lossage ("invalid %%p value");
10694 fprintf (file, "%d", i);
10698 /* The operand must be an indirect memory reference. The result
10699 is the register name. */
10700 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10701 || REGNO (XEXP (x, 0)) >= 32)
10702 output_operand_lossage ("invalid %%P value");
10704 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10708 /* This outputs the logical code corresponding to a boolean
10709 expression. The expression may have one or both operands
10710 negated (if one, only the first one). For condition register
10711 logical operations, it will also treat the negated
10712 CR codes as NOTs, but not handle NOTs of them. */
10714 const char *const *t = 0;
10716 enum rtx_code code = GET_CODE (x);
10717 static const char * const tbl[3][3] = {
10718 { "and", "andc", "nor" },
10719 { "or", "orc", "nand" },
10720 { "xor", "eqv", "xor" } };
10724 else if (code == IOR)
10726 else if (code == XOR)
10729 output_operand_lossage ("invalid %%q value");
10731 if (GET_CODE (XEXP (x, 0)) != NOT)
10735 if (GET_CODE (XEXP (x, 1)) == NOT)
10753 /* X is a CR register. Print the mask for `mtcrf'. */
10754 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10755 output_operand_lossage ("invalid %%R value");
10757 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10761 /* Low 5 bits of 32 - value */
10763 output_operand_lossage ("invalid %%s value");
10765 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10769 /* PowerPC64 mask position. All 0's is excluded.
10770 CONST_INT 32-bit mask is considered sign-extended so any
10771 transition must occur within the CONST_INT, not on the boundary. */
10772 if (! mask64_operand (x, DImode))
10773 output_operand_lossage ("invalid %%S value");
10775 uval = INT_LOWPART (x);
10777 if (uval & 1) /* Clear Left */
10779 #if HOST_BITS_PER_WIDE_INT > 64
10780 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10784 else /* Clear Right */
10787 #if HOST_BITS_PER_WIDE_INT > 64
10788 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10794 gcc_assert (i >= 0);
10795 fprintf (file, "%d", i);
10799 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10800 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10802 /* Bit 3 is OV bit. */
10803 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10805 /* If we want bit 31, write a shift count of zero, not 32. */
10806 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10810 /* Print the symbolic name of a branch target register. */
10811 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10812 && REGNO (x) != COUNT_REGISTER_REGNUM))
10813 output_operand_lossage ("invalid %%T value");
10814 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10815 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10817 fputs ("ctr", file);
10821 /* High-order 16 bits of constant for use in unsigned operand. */
10823 output_operand_lossage ("invalid %%u value");
10825 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10826 (INT_LOWPART (x) >> 16) & 0xffff);
10830 /* High-order 16 bits of constant for use in signed operand. */
10832 output_operand_lossage ("invalid %%v value");
10834 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10835 (INT_LOWPART (x) >> 16) & 0xffff);
10839 /* Print `u' if this has an auto-increment or auto-decrement. */
10840 if (GET_CODE (x) == MEM
10841 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10842 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10847 /* Print the trap code for this operand. */
10848 switch (GET_CODE (x))
10851 fputs ("eq", file); /* 4 */
10854 fputs ("ne", file); /* 24 */
10857 fputs ("lt", file); /* 16 */
10860 fputs ("le", file); /* 20 */
10863 fputs ("gt", file); /* 8 */
10866 fputs ("ge", file); /* 12 */
10869 fputs ("llt", file); /* 2 */
10872 fputs ("lle", file); /* 6 */
10875 fputs ("lgt", file); /* 1 */
10878 fputs ("lge", file); /* 5 */
10881 gcc_unreachable ();
10886 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10889 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10890 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10892 print_operand (file, x, 0);
10896 /* MB value for a PowerPC64 rldic operand. */
10897 val = (GET_CODE (x) == CONST_INT
10898 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10903 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10904 if ((val <<= 1) < 0)
10907 #if HOST_BITS_PER_WIDE_INT == 32
10908 if (GET_CODE (x) == CONST_INT && i >= 0)
10909 i += 32; /* zero-extend high-part was all 0's */
10910 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10912 val = CONST_DOUBLE_LOW (x);
10918 for ( ; i < 64; i++)
10919 if ((val <<= 1) < 0)
10924 fprintf (file, "%d", i + 1);
10928 if (GET_CODE (x) == MEM
10929 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10934 /* Like 'L', for third word of TImode */
10935 if (GET_CODE (x) == REG)
10936 fputs (reg_names[REGNO (x) + 2], file);
10937 else if (GET_CODE (x) == MEM)
10939 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10940 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10941 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10943 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10944 if (small_data_operand (x, GET_MODE (x)))
10945 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10946 reg_names[SMALL_DATA_REG]);
10951 /* X is a SYMBOL_REF. Write out the name preceded by a
10952 period and without any trailing data in brackets. Used for function
10953 names. If we are configured for System V (or the embedded ABI) on
10954 the PowerPC, do not emit the period, since those systems do not use
10955 TOCs and the like. */
10956 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10958 /* Mark the decl as referenced so that cgraph will output the
10960 if (SYMBOL_REF_DECL (x))
10961 mark_decl_referenced (SYMBOL_REF_DECL (x));
10963 /* For macho, check to see if we need a stub. */
10966 const char *name = XSTR (x, 0);
10968 if (MACHOPIC_INDIRECT
10969 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10970 name = machopic_indirection_name (x, /*stub_p=*/true);
10972 assemble_name (file, name);
10974 else if (!DOT_SYMBOLS)
10975 assemble_name (file, XSTR (x, 0));
10977 rs6000_output_function_entry (file, XSTR (x, 0));
10981 /* Like 'L', for last word of TImode. */
10982 if (GET_CODE (x) == REG)
10983 fputs (reg_names[REGNO (x) + 3], file);
10984 else if (GET_CODE (x) == MEM)
10986 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10987 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10988 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10990 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10991 if (small_data_operand (x, GET_MODE (x)))
10992 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10993 reg_names[SMALL_DATA_REG]);
10997 /* Print AltiVec or SPE memory operand. */
11002 gcc_assert (GET_CODE (x) == MEM);
11006 /* Ugly hack because %y is overloaded. */
11007 if (TARGET_E500 && GET_MODE_SIZE (GET_MODE (x)) == 8)
11009 /* Handle [reg]. */
11010 if (GET_CODE (tmp) == REG)
11012 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11015 /* Handle [reg+UIMM]. */
11016 else if (GET_CODE (tmp) == PLUS &&
11017 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11021 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11023 x = INTVAL (XEXP (tmp, 1));
11024 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11028 /* Fall through. Must be [reg+reg]. */
11031 && GET_CODE (tmp) == AND
11032 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11033 && INTVAL (XEXP (tmp, 1)) == -16)
11034 tmp = XEXP (tmp, 0);
11035 if (GET_CODE (tmp) == REG)
11036 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11039 gcc_assert (GET_CODE (tmp) == PLUS
11040 && REG_P (XEXP (tmp, 0))
11041 && REG_P (XEXP (tmp, 1)));
11043 if (REGNO (XEXP (tmp, 0)) == 0)
11044 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11045 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11047 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11048 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11054 if (GET_CODE (x) == REG)
11055 fprintf (file, "%s", reg_names[REGNO (x)]);
11056 else if (GET_CODE (x) == MEM)
11058 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11059 know the width from the mode. */
11060 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11061 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11062 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11063 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11064 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11065 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11067 output_address (XEXP (x, 0));
11070 output_addr_const (file, x);
11074 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11078 output_operand_lossage ("invalid %%xn code");
11082 /* Print the address of an operand. */
11085 print_operand_address (FILE *file, rtx x)
11087 if (GET_CODE (x) == REG)
11088 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11089 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11090 || GET_CODE (x) == LABEL_REF)
11092 output_addr_const (file, x);
11093 if (small_data_operand (x, GET_MODE (x)))
11094 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11095 reg_names[SMALL_DATA_REG]);
11097 gcc_assert (!TARGET_TOC);
11099 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11101 gcc_assert (REG_P (XEXP (x, 0)));
11102 if (REGNO (XEXP (x, 0)) == 0)
11103 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11104 reg_names[ REGNO (XEXP (x, 0)) ]);
11106 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11107 reg_names[ REGNO (XEXP (x, 1)) ]);
11109 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11110 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11111 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11113 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11114 && CONSTANT_P (XEXP (x, 1)))
11116 output_addr_const (file, XEXP (x, 1));
11117 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11121 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11122 && CONSTANT_P (XEXP (x, 1)))
11124 fprintf (file, "lo16(");
11125 output_addr_const (file, XEXP (x, 1));
11126 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11129 else if (legitimate_constant_pool_address_p (x))
11131 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11133 rtx contains_minus = XEXP (x, 1);
11137 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11138 turn it into (sym) for output_addr_const. */
11139 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11140 contains_minus = XEXP (contains_minus, 0);
11142 minus = XEXP (contains_minus, 0);
11143 symref = XEXP (minus, 0);
11144 XEXP (contains_minus, 0) = symref;
11149 name = XSTR (symref, 0);
11150 newname = alloca (strlen (name) + sizeof ("@toc"));
11151 strcpy (newname, name);
11152 strcat (newname, "@toc");
11153 XSTR (symref, 0) = newname;
11155 output_addr_const (file, XEXP (x, 1));
11157 XSTR (symref, 0) = name;
11158 XEXP (contains_minus, 0) = minus;
11161 output_addr_const (file, XEXP (x, 1));
11163 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11166 gcc_unreachable ();
11169 /* Target hook for assembling integer objects. The PowerPC version has
11170 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11171 is defined. It also needs to handle DI-mode objects on 64-bit
11175 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11177 #ifdef RELOCATABLE_NEEDS_FIXUP
11178 /* Special handling for SI values. */
11179 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11181 static int recurse = 0;
11183 /* For -mrelocatable, we mark all addresses that need to be fixed up
11184 in the .fixup section. */
11185 if (TARGET_RELOCATABLE
11186 && in_section != toc_section
11187 && in_section != text_section
11188 && !unlikely_text_section_p (in_section)
11190 && GET_CODE (x) != CONST_INT
11191 && GET_CODE (x) != CONST_DOUBLE
11197 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11199 ASM_OUTPUT_LABEL (asm_out_file, buf);
11200 fprintf (asm_out_file, "\t.long\t(");
11201 output_addr_const (asm_out_file, x);
11202 fprintf (asm_out_file, ")@fixup\n");
11203 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11204 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11205 fprintf (asm_out_file, "\t.long\t");
11206 assemble_name (asm_out_file, buf);
11207 fprintf (asm_out_file, "\n\t.previous\n");
11211 /* Remove initial .'s to turn a -mcall-aixdesc function
11212 address into the address of the descriptor, not the function
11214 else if (GET_CODE (x) == SYMBOL_REF
11215 && XSTR (x, 0)[0] == '.'
11216 && DEFAULT_ABI == ABI_AIX)
11218 const char *name = XSTR (x, 0);
11219 while (*name == '.')
11222 fprintf (asm_out_file, "\t.long\t%s\n", name);
11226 #endif /* RELOCATABLE_NEEDS_FIXUP */
11227 return default_assemble_integer (x, size, aligned_p);
11230 #ifdef HAVE_GAS_HIDDEN
11231 /* Emit an assembler directive to set symbol visibility for DECL to
11232 VISIBILITY_TYPE. */
11235 rs6000_assemble_visibility (tree decl, int vis)
11237 /* Functions need to have their entry point symbol visibility set as
11238 well as their descriptor symbol visibility. */
11239 if (DEFAULT_ABI == ABI_AIX
11241 && TREE_CODE (decl) == FUNCTION_DECL)
11243 static const char * const visibility_types[] = {
11244 NULL, "internal", "hidden", "protected"
11247 const char *name, *type;
11249 name = ((* targetm.strip_name_encoding)
11250 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11251 type = visibility_types[vis];
11253 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11254 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11257 default_assemble_visibility (decl, vis);
11262 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11264 /* Reversal of FP compares takes care -- an ordered compare
11265 becomes an unordered compare and vice versa. */
11266 if (mode == CCFPmode
11267 && (!flag_finite_math_only
11268 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11269 || code == UNEQ || code == LTGT))
11270 return reverse_condition_maybe_unordered (code);
11272 return reverse_condition (code);
11275 /* Generate a compare for CODE. Return a brand-new rtx that
11276 represents the result of the compare. */
11279 rs6000_generate_compare (enum rtx_code code)
11281 enum machine_mode comp_mode;
11282 rtx compare_result;
11284 if (rs6000_compare_fp_p)
11285 comp_mode = CCFPmode;
11286 else if (code == GTU || code == LTU
11287 || code == GEU || code == LEU)
11288 comp_mode = CCUNSmode;
11289 else if ((code == EQ || code == NE)
11290 && GET_CODE (rs6000_compare_op0) == SUBREG
11291 && GET_CODE (rs6000_compare_op1) == SUBREG
11292 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11293 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11294 /* These are unsigned values, perhaps there will be a later
11295 ordering compare that can be shared with this one.
11296 Unfortunately we cannot detect the signedness of the operands
11297 for non-subregs. */
11298 comp_mode = CCUNSmode;
11300 comp_mode = CCmode;
11302 /* First, the compare. */
11303 compare_result = gen_reg_rtx (comp_mode);
11305 /* E500 FP compare instructions on the GPRs. Yuck! */
11306 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11307 && rs6000_compare_fp_p)
11309 rtx cmp, or_result, compare_result2;
11310 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11312 if (op_mode == VOIDmode)
11313 op_mode = GET_MODE (rs6000_compare_op1);
11315 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11316 This explains the following mess. */
11320 case EQ: case UNEQ: case NE: case LTGT:
11324 cmp = flag_unsafe_math_optimizations
11325 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11326 rs6000_compare_op1)
11327 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11328 rs6000_compare_op1);
11332 cmp = flag_unsafe_math_optimizations
11333 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11334 rs6000_compare_op1)
11335 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11336 rs6000_compare_op1);
11340 gcc_unreachable ();
11344 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11348 cmp = flag_unsafe_math_optimizations
11349 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11350 rs6000_compare_op1)
11351 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11352 rs6000_compare_op1);
11356 cmp = flag_unsafe_math_optimizations
11357 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11358 rs6000_compare_op1)
11359 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11360 rs6000_compare_op1);
11364 gcc_unreachable ();
11368 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11372 cmp = flag_unsafe_math_optimizations
11373 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11374 rs6000_compare_op1)
11375 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11376 rs6000_compare_op1);
11380 cmp = flag_unsafe_math_optimizations
11381 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11382 rs6000_compare_op1)
11383 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11384 rs6000_compare_op1);
11388 gcc_unreachable ();
11392 gcc_unreachable ();
11395 /* Synthesize LE and GE from LT/GT || EQ. */
11396 if (code == LE || code == GE || code == LEU || code == GEU)
11402 case LE: code = LT; break;
11403 case GE: code = GT; break;
11404 case LEU: code = LT; break;
11405 case GEU: code = GT; break;
11406 default: gcc_unreachable ();
11409 compare_result2 = gen_reg_rtx (CCFPmode);
11415 cmp = flag_unsafe_math_optimizations
11416 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11417 rs6000_compare_op1)
11418 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11419 rs6000_compare_op1);
11423 cmp = flag_unsafe_math_optimizations
11424 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11425 rs6000_compare_op1)
11426 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11427 rs6000_compare_op1);
11431 gcc_unreachable ();
11435 /* OR them together. */
11436 or_result = gen_reg_rtx (CCFPmode);
11437 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11439 compare_result = or_result;
11444 if (code == NE || code == LTGT)
11454 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11455 CLOBBERs to match cmptf_internal2 pattern. */
11456 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11457 && GET_MODE (rs6000_compare_op0) == TFmode
11458 && !TARGET_IEEEQUAD
11459 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11460 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11462 gen_rtx_SET (VOIDmode,
11464 gen_rtx_COMPARE (comp_mode,
11465 rs6000_compare_op0,
11466 rs6000_compare_op1)),
11467 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11468 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11469 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11470 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11471 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11472 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11473 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11474 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11475 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11476 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11478 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11479 comp_mode = CCEQmode;
11480 compare_result = gen_reg_rtx (CCEQmode);
11482 emit_insn (gen_stack_protect_testdi (compare_result,
11483 rs6000_compare_op0, op1));
11485 emit_insn (gen_stack_protect_testsi (compare_result,
11486 rs6000_compare_op0, op1));
11489 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11490 gen_rtx_COMPARE (comp_mode,
11491 rs6000_compare_op0,
11492 rs6000_compare_op1)));
11495 /* Some kinds of FP comparisons need an OR operation;
11496 under flag_finite_math_only we don't bother. */
11497 if (rs6000_compare_fp_p
11498 && !flag_finite_math_only
11499 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11500 && (code == LE || code == GE
11501 || code == UNEQ || code == LTGT
11502 || code == UNGT || code == UNLT))
11504 enum rtx_code or1, or2;
11505 rtx or1_rtx, or2_rtx, compare2_rtx;
11506 rtx or_result = gen_reg_rtx (CCEQmode);
11510 case LE: or1 = LT; or2 = EQ; break;
11511 case GE: or1 = GT; or2 = EQ; break;
11512 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11513 case LTGT: or1 = LT; or2 = GT; break;
11514 case UNGT: or1 = UNORDERED; or2 = GT; break;
11515 case UNLT: or1 = UNORDERED; or2 = LT; break;
11516 default: gcc_unreachable ();
11518 validate_condition_mode (or1, comp_mode);
11519 validate_condition_mode (or2, comp_mode);
11520 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11521 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11522 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11523 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11525 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11527 compare_result = or_result;
11531 validate_condition_mode (code, GET_MODE (compare_result));
11533 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11537 /* Emit the RTL for an sCOND pattern. */
11540 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11543 enum machine_mode op_mode;
11544 enum rtx_code cond_code;
11546 condition_rtx = rs6000_generate_compare (code);
11547 cond_code = GET_CODE (condition_rtx);
11549 if (TARGET_E500 && rs6000_compare_fp_p
11550 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11554 PUT_MODE (condition_rtx, SImode);
11555 t = XEXP (condition_rtx, 0);
11557 gcc_assert (cond_code == NE || cond_code == EQ);
11559 if (cond_code == NE)
11560 emit_insn (gen_e500_flip_gt_bit (t, t));
11562 emit_insn (gen_move_from_CR_gt_bit (result, t));
11566 if (cond_code == NE
11567 || cond_code == GE || cond_code == LE
11568 || cond_code == GEU || cond_code == LEU
11569 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11571 rtx not_result = gen_reg_rtx (CCEQmode);
11572 rtx not_op, rev_cond_rtx;
11573 enum machine_mode cc_mode;
11575 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11577 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11578 SImode, XEXP (condition_rtx, 0), const0_rtx);
11579 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11580 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11581 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11584 op_mode = GET_MODE (rs6000_compare_op0);
11585 if (op_mode == VOIDmode)
11586 op_mode = GET_MODE (rs6000_compare_op1);
11588 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11590 PUT_MODE (condition_rtx, DImode);
11591 convert_move (result, condition_rtx, 0);
11595 PUT_MODE (condition_rtx, SImode);
11596 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11600 /* Emit a branch of kind CODE to location LOC. */
11603 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11605 rtx condition_rtx, loc_ref;
11607 condition_rtx = rs6000_generate_compare (code);
11608 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11609 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11610 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11611 loc_ref, pc_rtx)));
11614 /* Return the string to output a conditional branch to LABEL, which is
11615 the operand number of the label, or -1 if the branch is really a
11616 conditional return.
11618 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11619 condition code register and its mode specifies what kind of
11620 comparison we made.
11622 REVERSED is nonzero if we should reverse the sense of the comparison.
11624 INSN is the insn. */
11627 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11629 static char string[64];
11630 enum rtx_code code = GET_CODE (op);
11631 rtx cc_reg = XEXP (op, 0);
11632 enum machine_mode mode = GET_MODE (cc_reg);
11633 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11634 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11635 int really_reversed = reversed ^ need_longbranch;
11641 validate_condition_mode (code, mode);
11643 /* Work out which way this really branches. We could use
11644 reverse_condition_maybe_unordered here always but this
11645 makes the resulting assembler clearer. */
11646 if (really_reversed)
11648 /* Reversal of FP compares takes care -- an ordered compare
11649 becomes an unordered compare and vice versa. */
11650 if (mode == CCFPmode)
11651 code = reverse_condition_maybe_unordered (code);
11653 code = reverse_condition (code);
11656 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11658 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11663 /* Opposite of GT. */
11672 gcc_unreachable ();
11678 /* Not all of these are actually distinct opcodes, but
11679 we distinguish them for clarity of the resulting assembler. */
11680 case NE: case LTGT:
11681 ccode = "ne"; break;
11682 case EQ: case UNEQ:
11683 ccode = "eq"; break;
11685 ccode = "ge"; break;
11686 case GT: case GTU: case UNGT:
11687 ccode = "gt"; break;
11689 ccode = "le"; break;
11690 case LT: case LTU: case UNLT:
11691 ccode = "lt"; break;
11692 case UNORDERED: ccode = "un"; break;
11693 case ORDERED: ccode = "nu"; break;
11694 case UNGE: ccode = "nl"; break;
11695 case UNLE: ccode = "ng"; break;
11697 gcc_unreachable ();
11700 /* Maybe we have a guess as to how likely the branch is.
11701 The old mnemonics don't have a way to specify this information. */
11703 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11704 if (note != NULL_RTX)
11706 /* PROB is the difference from 50%. */
11707 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11709 /* Only hint for highly probable/improbable branches on newer
11710 cpus as static prediction overrides processor dynamic
11711 prediction. For older cpus we may as well always hint, but
11712 assume not taken for branches that are very close to 50% as a
11713 mispredicted taken branch is more expensive than a
11714 mispredicted not-taken branch. */
11715 if (rs6000_always_hint
11716 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
11717 && br_prob_note_reliable_p (note)))
11719 if (abs (prob) > REG_BR_PROB_BASE / 20
11720 && ((prob > 0) ^ need_longbranch))
11728 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11730 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11732 /* We need to escape any '%' characters in the reg_names string.
11733 Assume they'd only be the first character.... */
11734 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11736 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11740 /* If the branch distance was too far, we may have to use an
11741 unconditional branch to go the distance. */
11742 if (need_longbranch)
11743 s += sprintf (s, ",$+8\n\tb %s", label);
11745 s += sprintf (s, ",%s", label);
11751 /* Return the string to flip the GT bit on a CR. */
11753 output_e500_flip_gt_bit (rtx dst, rtx src)
11755 static char string[64];
11758 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11759 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11762 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11763 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11765 sprintf (string, "crnot %d,%d", a, b);
11769 /* Return insn index for the vector compare instruction for given CODE,
11770 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11774 get_vec_cmp_insn (enum rtx_code code,
11775 enum machine_mode dest_mode,
11776 enum machine_mode op_mode)
11778 if (!TARGET_ALTIVEC)
11779 return INSN_NOT_AVAILABLE;
11784 if (dest_mode == V16QImode && op_mode == V16QImode)
11785 return UNSPEC_VCMPEQUB;
11786 if (dest_mode == V8HImode && op_mode == V8HImode)
11787 return UNSPEC_VCMPEQUH;
11788 if (dest_mode == V4SImode && op_mode == V4SImode)
11789 return UNSPEC_VCMPEQUW;
11790 if (dest_mode == V4SImode && op_mode == V4SFmode)
11791 return UNSPEC_VCMPEQFP;
11794 if (dest_mode == V4SImode && op_mode == V4SFmode)
11795 return UNSPEC_VCMPGEFP;
11797 if (dest_mode == V16QImode && op_mode == V16QImode)
11798 return UNSPEC_VCMPGTSB;
11799 if (dest_mode == V8HImode && op_mode == V8HImode)
11800 return UNSPEC_VCMPGTSH;
11801 if (dest_mode == V4SImode && op_mode == V4SImode)
11802 return UNSPEC_VCMPGTSW;
11803 if (dest_mode == V4SImode && op_mode == V4SFmode)
11804 return UNSPEC_VCMPGTFP;
11807 if (dest_mode == V16QImode && op_mode == V16QImode)
11808 return UNSPEC_VCMPGTUB;
11809 if (dest_mode == V8HImode && op_mode == V8HImode)
11810 return UNSPEC_VCMPGTUH;
11811 if (dest_mode == V4SImode && op_mode == V4SImode)
11812 return UNSPEC_VCMPGTUW;
11817 return INSN_NOT_AVAILABLE;
11820 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11821 DMODE is expected destination mode. This is a recursive function. */
11824 rs6000_emit_vector_compare (enum rtx_code rcode,
11826 enum machine_mode dmode)
11830 enum machine_mode dest_mode;
11831 enum machine_mode op_mode = GET_MODE (op1);
11833 gcc_assert (TARGET_ALTIVEC);
11834 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11836 /* Floating point vector compare instructions uses destination V4SImode.
11837 Move destination to appropriate mode later. */
11838 if (dmode == V4SFmode)
11839 dest_mode = V4SImode;
11843 mask = gen_reg_rtx (dest_mode);
11844 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11846 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11848 bool swap_operands = false;
11849 bool try_again = false;
11854 swap_operands = true;
11859 swap_operands = true;
11863 /* Treat A != B as ~(A==B). */
11865 enum insn_code nor_code;
11866 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11869 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11870 gcc_assert (nor_code != CODE_FOR_nothing);
11871 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11873 if (dmode != dest_mode)
11875 rtx temp = gen_reg_rtx (dest_mode);
11876 convert_move (temp, mask, 0);
11886 /* Try GT/GTU/LT/LTU OR EQ */
11889 enum insn_code ior_code;
11890 enum rtx_code new_code;
11911 gcc_unreachable ();
11914 c_rtx = rs6000_emit_vector_compare (new_code,
11915 op0, op1, dest_mode);
11916 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11919 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11920 gcc_assert (ior_code != CODE_FOR_nothing);
11921 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11922 if (dmode != dest_mode)
11924 rtx temp = gen_reg_rtx (dest_mode);
11925 convert_move (temp, mask, 0);
11932 gcc_unreachable ();
11937 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11938 /* You only get two chances. */
11939 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11951 emit_insn (gen_rtx_SET (VOIDmode, mask,
11952 gen_rtx_UNSPEC (dest_mode,
11953 gen_rtvec (2, op0, op1),
11955 if (dmode != dest_mode)
11957 rtx temp = gen_reg_rtx (dest_mode);
11958 convert_move (temp, mask, 0);
11964 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11965 valid insn doesn exist for given mode. */
11968 get_vsel_insn (enum machine_mode mode)
11973 return UNSPEC_VSEL4SI;
11976 return UNSPEC_VSEL4SF;
11979 return UNSPEC_VSEL8HI;
11982 return UNSPEC_VSEL16QI;
11985 return INSN_NOT_AVAILABLE;
11988 return INSN_NOT_AVAILABLE;
11991 /* Emit vector select insn where DEST is destination using
11992 operands OP1, OP2 and MASK. */
11995 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11998 enum machine_mode dest_mode = GET_MODE (dest);
11999 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12001 temp = gen_reg_rtx (dest_mode);
12003 /* For each vector element, select op1 when mask is 1 otherwise
12005 t = gen_rtx_SET (VOIDmode, temp,
12006 gen_rtx_UNSPEC (dest_mode,
12007 gen_rtvec (3, op2, op1, mask),
12010 emit_move_insn (dest, temp);
12014 /* Emit vector conditional expression.
12015 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12016 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12019 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12020 rtx cond, rtx cc_op0, rtx cc_op1)
12022 enum machine_mode dest_mode = GET_MODE (dest);
12023 enum rtx_code rcode = GET_CODE (cond);
12026 if (!TARGET_ALTIVEC)
12029 /* Get the vector mask for the given relational operations. */
12030 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12032 rs6000_emit_vector_select (dest, op1, op2, mask);
12037 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12038 operands of the last comparison is nonzero/true, FALSE_COND if it
12039 is zero/false. Return 0 if the hardware has no such operation. */
12042 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12044 enum rtx_code code = GET_CODE (op);
12045 rtx op0 = rs6000_compare_op0;
12046 rtx op1 = rs6000_compare_op1;
12047 REAL_VALUE_TYPE c1;
12048 enum machine_mode compare_mode = GET_MODE (op0);
12049 enum machine_mode result_mode = GET_MODE (dest);
12051 bool is_against_zero;
12053 /* These modes should always match. */
12054 if (GET_MODE (op1) != compare_mode
12055 /* In the isel case however, we can use a compare immediate, so
12056 op1 may be a small constant. */
12057 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12059 if (GET_MODE (true_cond) != result_mode)
12061 if (GET_MODE (false_cond) != result_mode)
12064 /* First, work out if the hardware can do this at all, or
12065 if it's too slow.... */
12066 if (! rs6000_compare_fp_p)
12069 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12072 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
12073 && SCALAR_FLOAT_MODE_P (compare_mode))
12076 is_against_zero = op1 == CONST0_RTX (compare_mode);
12078 /* A floating-point subtract might overflow, underflow, or produce
12079 an inexact result, thus changing the floating-point flags, so it
12080 can't be generated if we care about that. It's safe if one side
12081 of the construct is zero, since then no subtract will be
12083 if (SCALAR_FLOAT_MODE_P (compare_mode)
12084 && flag_trapping_math && ! is_against_zero)
12087 /* Eliminate half of the comparisons by switching operands, this
12088 makes the remaining code simpler. */
12089 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12090 || code == LTGT || code == LT || code == UNLE)
12092 code = reverse_condition_maybe_unordered (code);
12094 true_cond = false_cond;
12098 /* UNEQ and LTGT take four instructions for a comparison with zero,
12099 it'll probably be faster to use a branch here too. */
12100 if (code == UNEQ && HONOR_NANS (compare_mode))
12103 if (GET_CODE (op1) == CONST_DOUBLE)
12104 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12106 /* We're going to try to implement comparisons by performing
12107 a subtract, then comparing against zero. Unfortunately,
12108 Inf - Inf is NaN which is not zero, and so if we don't
12109 know that the operand is finite and the comparison
12110 would treat EQ different to UNORDERED, we can't do it. */
12111 if (HONOR_INFINITIES (compare_mode)
12112 && code != GT && code != UNGE
12113 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12114 /* Constructs of the form (a OP b ? a : b) are safe. */
12115 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12116 || (! rtx_equal_p (op0, true_cond)
12117 && ! rtx_equal_p (op1, true_cond))))
12120 /* At this point we know we can use fsel. */
12122 /* Reduce the comparison to a comparison against zero. */
12123 if (! is_against_zero)
12125 temp = gen_reg_rtx (compare_mode);
12126 emit_insn (gen_rtx_SET (VOIDmode, temp,
12127 gen_rtx_MINUS (compare_mode, op0, op1)));
12129 op1 = CONST0_RTX (compare_mode);
12132 /* If we don't care about NaNs we can reduce some of the comparisons
12133 down to faster ones. */
12134 if (! HONOR_NANS (compare_mode))
12140 true_cond = false_cond;
12153 /* Now, reduce everything down to a GE. */
12160 temp = gen_reg_rtx (compare_mode);
12161 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12166 temp = gen_reg_rtx (compare_mode);
12167 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12172 temp = gen_reg_rtx (compare_mode);
12173 emit_insn (gen_rtx_SET (VOIDmode, temp,
12174 gen_rtx_NEG (compare_mode,
12175 gen_rtx_ABS (compare_mode, op0))));
12180 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12181 temp = gen_reg_rtx (result_mode);
12182 emit_insn (gen_rtx_SET (VOIDmode, temp,
12183 gen_rtx_IF_THEN_ELSE (result_mode,
12184 gen_rtx_GE (VOIDmode,
12186 true_cond, false_cond)));
12187 false_cond = true_cond;
12190 temp = gen_reg_rtx (compare_mode);
12191 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12196 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12197 temp = gen_reg_rtx (result_mode);
12198 emit_insn (gen_rtx_SET (VOIDmode, temp,
12199 gen_rtx_IF_THEN_ELSE (result_mode,
12200 gen_rtx_GE (VOIDmode,
12202 true_cond, false_cond)));
12203 true_cond = false_cond;
12206 temp = gen_reg_rtx (compare_mode);
12207 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12212 gcc_unreachable ();
12215 emit_insn (gen_rtx_SET (VOIDmode, dest,
12216 gen_rtx_IF_THEN_ELSE (result_mode,
12217 gen_rtx_GE (VOIDmode,
12219 true_cond, false_cond)));
12223 /* Same as above, but for ints (isel). */
12226 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12228 rtx condition_rtx, cr;
12230 /* All isel implementations thus far are 32-bits. */
12231 if (GET_MODE (rs6000_compare_op0) != SImode)
12234 /* We still have to do the compare, because isel doesn't do a
12235 compare, it just looks at the CRx bits set by a previous compare
12237 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12238 cr = XEXP (condition_rtx, 0);
12240 if (GET_MODE (cr) == CCmode)
12241 emit_insn (gen_isel_signed (dest, condition_rtx,
12242 true_cond, false_cond, cr));
12244 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12245 true_cond, false_cond, cr));
12251 output_isel (rtx *operands)
12253 enum rtx_code code;
12255 code = GET_CODE (operands[1]);
12256 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12258 PUT_CODE (operands[1], reverse_condition (code));
12259 return "isel %0,%3,%2,%j1";
12262 return "isel %0,%2,%3,%j1";
12266 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12268 enum machine_mode mode = GET_MODE (op0);
12272 if (code == SMAX || code == SMIN)
12277 if (code == SMAX || code == UMAX)
12278 target = emit_conditional_move (dest, c, op0, op1, mode,
12279 op0, op1, mode, 0);
12281 target = emit_conditional_move (dest, c, op0, op1, mode,
12282 op1, op0, mode, 0);
12283 gcc_assert (target);
12284 if (target != dest)
12285 emit_move_insn (dest, target);
12288 /* Emit instructions to perform a load-reserved/store-conditional operation.
12289 The operation performed is an atomic
12290 (set M (CODE:MODE M OP))
12291 If not NULL, BEFORE is atomically set to M before the operation, and
12292 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12293 If SYNC_P then a memory barrier is emitted before the operation.
12294 Either OP or M may be wrapped in a NOT operation. */
12297 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12298 rtx m, rtx op, rtx before_param, rtx after_param,
12301 enum machine_mode used_mode;
12302 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12305 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12306 rtx shift = NULL_RTX;
12309 emit_insn (gen_memory_barrier ());
12311 if (GET_CODE (m) == NOT)
12312 used_m = XEXP (m, 0);
12316 /* If this is smaller than SImode, we'll have to use SImode with
12318 if (mode == QImode || mode == HImode)
12322 if (MEM_ALIGN (used_m) >= 32)
12325 if (BYTES_BIG_ENDIAN)
12326 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12328 shift = GEN_INT (ishift);
12332 rtx addrSI, aligned_addr;
12333 int shift_mask = mode == QImode ? 0x18 : 0x10;
12335 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12336 XEXP (used_m, 0)));
12337 shift = gen_reg_rtx (SImode);
12339 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12340 GEN_INT (shift_mask)));
12341 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12343 aligned_addr = expand_binop (Pmode, and_optab,
12345 GEN_INT (-4), NULL_RTX,
12346 1, OPTAB_LIB_WIDEN);
12347 used_m = change_address (used_m, SImode, aligned_addr);
12348 set_mem_align (used_m, 32);
12349 /* It's safe to keep the old alias set of USED_M, because
12350 the operation is atomic and only affects the original
12352 if (GET_CODE (m) == NOT)
12353 m = gen_rtx_NOT (SImode, used_m);
12358 if (GET_CODE (op) == NOT)
12360 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12361 oldop = gen_rtx_NOT (SImode, oldop);
12364 oldop = lowpart_subreg (SImode, op, mode);
12370 newop = expand_binop (SImode, and_optab,
12371 oldop, GEN_INT (imask), NULL_RTX,
12372 1, OPTAB_LIB_WIDEN);
12373 emit_insn (gen_ashlsi3 (newop, newop, shift));
12377 newop = expand_binop (SImode, ior_optab,
12378 oldop, GEN_INT (~imask), NULL_RTX,
12379 1, OPTAB_LIB_WIDEN);
12380 emit_insn (gen_rotlsi3 (newop, newop, shift));
12388 newop = expand_binop (SImode, and_optab,
12389 oldop, GEN_INT (imask), NULL_RTX,
12390 1, OPTAB_LIB_WIDEN);
12391 emit_insn (gen_ashlsi3 (newop, newop, shift));
12393 mask = gen_reg_rtx (SImode);
12394 emit_move_insn (mask, GEN_INT (imask));
12395 emit_insn (gen_ashlsi3 (mask, mask, shift));
12398 newop = gen_rtx_PLUS (SImode, m, newop);
12400 newop = gen_rtx_MINUS (SImode, m, newop);
12401 newop = gen_rtx_AND (SImode, newop, mask);
12402 newop = gen_rtx_IOR (SImode, newop,
12403 gen_rtx_AND (SImode,
12404 gen_rtx_NOT (SImode, mask),
12410 gcc_unreachable ();
12413 if (GET_CODE (m) == NOT)
12417 mask = gen_reg_rtx (SImode);
12418 emit_move_insn (mask, GEN_INT (imask));
12419 emit_insn (gen_ashlsi3 (mask, mask, shift));
12421 xorm = gen_rtx_XOR (SImode, used_m, mask);
12422 /* Depending on the value of 'op', the XOR or the operation might
12423 be able to be simplified away. */
12424 newop = simplify_gen_binary (code, SImode, xorm, newop);
12427 used_mode = SImode;
12428 before = gen_reg_rtx (used_mode);
12429 after = gen_reg_rtx (used_mode);
12434 before = before_param;
12435 after = after_param;
12437 if (before == NULL_RTX)
12438 before = gen_reg_rtx (used_mode);
12439 if (after == NULL_RTX)
12440 after = gen_reg_rtx (used_mode);
12443 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12444 && used_mode != mode)
12445 the_op = op; /* Computed above. */
12446 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12447 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12449 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12451 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12452 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12453 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12454 gen_rtx_UNSPEC (used_mode,
12455 gen_rtvec (1, the_op),
12457 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12459 if ((code == PLUS || code == MINUS) && used_mode != mode)
12460 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12461 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12463 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12464 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12466 /* Shift and mask the return values properly. */
12467 if (used_mode != mode && before_param)
12469 emit_insn (gen_lshrsi3 (before, before, shift));
12470 convert_move (before_param, before, 1);
12473 if (used_mode != mode && after_param)
12475 emit_insn (gen_lshrsi3 (after, after, shift));
12476 convert_move (after_param, after, 1);
12479 /* The previous sequence will end with a branch that's dependent on
12480 the conditional store, so placing an isync will ensure that no
12481 other instructions (especially, no load or store instructions)
12482 can start before the atomic operation completes. */
12484 emit_insn (gen_isync ());
12487 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12488 COND is true. Mark the jump as unlikely to be taken. */
12491 emit_unlikely_jump (rtx cond, rtx label)
12493 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12496 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12497 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12498 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12501 /* A subroutine of the atomic operation splitters. Emit a load-locked
12502 instruction in MODE. */
12505 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12507 rtx (*fn) (rtx, rtx) = NULL;
12508 if (mode == SImode)
12509 fn = gen_load_locked_si;
12510 else if (mode == DImode)
12511 fn = gen_load_locked_di;
12512 emit_insn (fn (reg, mem));
12515 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12516 instruction in MODE. */
12519 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12521 rtx (*fn) (rtx, rtx, rtx) = NULL;
12522 if (mode == SImode)
12523 fn = gen_store_conditional_si;
12524 else if (mode == DImode)
12525 fn = gen_store_conditional_di;
12527 /* Emit sync before stwcx. to address PPC405 Erratum. */
12528 if (PPC405_ERRATUM77)
12529 emit_insn (gen_memory_barrier ());
12531 emit_insn (fn (res, mem, val));
12534 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12535 to perform. MEM is the memory on which to operate. VAL is the second
12536 operand of the binary operator. BEFORE and AFTER are optional locations to
12537 return the value of MEM either before of after the operation. SCRATCH is
12538 a scratch register. */
12541 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12542 rtx before, rtx after, rtx scratch)
12544 enum machine_mode mode = GET_MODE (mem);
12545 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12547 emit_insn (gen_memory_barrier ());
12549 label = gen_label_rtx ();
12550 emit_label (label);
12551 label = gen_rtx_LABEL_REF (VOIDmode, label);
12553 if (before == NULL_RTX)
12555 emit_load_locked (mode, before, mem);
12558 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12559 else if (code == AND)
12560 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12562 x = gen_rtx_fmt_ee (code, mode, before, val);
12564 if (after != NULL_RTX)
12565 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12566 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12568 emit_store_conditional (mode, cond, mem, scratch);
12570 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12571 emit_unlikely_jump (x, label);
12573 emit_insn (gen_isync ());
12576 /* Expand an atomic compare and swap operation. MEM is the memory on which
12577 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12578 value to be stored. SCRATCH is a scratch GPR. */
12581 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12584 enum machine_mode mode = GET_MODE (mem);
12585 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12587 emit_insn (gen_memory_barrier ());
12589 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12590 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12591 emit_label (XEXP (label1, 0));
12593 emit_load_locked (mode, retval, mem);
12595 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12596 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12598 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12599 emit_unlikely_jump (x, label2);
12601 emit_move_insn (scratch, newval);
12602 emit_store_conditional (mode, cond, mem, scratch);
12604 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12605 emit_unlikely_jump (x, label1);
12607 emit_insn (gen_isync ());
12608 emit_label (XEXP (label2, 0));
12611 /* Expand an atomic test and set operation. MEM is the memory on which
12612 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12615 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12617 enum machine_mode mode = GET_MODE (mem);
12618 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12620 emit_insn (gen_memory_barrier ());
12622 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12623 emit_label (XEXP (label, 0));
12625 emit_load_locked (mode, retval, mem);
12626 emit_move_insn (scratch, val);
12627 emit_store_conditional (mode, cond, mem, scratch);
12629 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12630 emit_unlikely_jump (x, label);
12632 emit_insn (gen_isync ());
12636 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12638 enum machine_mode mode = GET_MODE (mem);
12639 rtx addrSI, align, wdst, shift, mask;
12640 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12641 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12643 /* Shift amount for subword relative to aligned word. */
12644 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12645 shift = gen_reg_rtx (SImode);
12646 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12647 GEN_INT (shift_mask)));
12648 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12650 /* Shift and mask old value into position within word. */
12651 oldval = convert_modes (SImode, mode, oldval, 1);
12652 oldval = expand_binop (SImode, and_optab,
12653 oldval, GEN_INT (imask), NULL_RTX,
12654 1, OPTAB_LIB_WIDEN);
12655 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12657 /* Shift and mask new value into position within word. */
12658 newval = convert_modes (SImode, mode, newval, 1);
12659 newval = expand_binop (SImode, and_optab,
12660 newval, GEN_INT (imask), NULL_RTX,
12661 1, OPTAB_LIB_WIDEN);
12662 emit_insn (gen_ashlsi3 (newval, newval, shift));
12664 /* Mask for insertion. */
12665 mask = gen_reg_rtx (SImode);
12666 emit_move_insn (mask, GEN_INT (imask));
12667 emit_insn (gen_ashlsi3 (mask, mask, shift));
12669 /* Address of aligned word containing subword. */
12670 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12671 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12672 mem = change_address (mem, SImode, align);
12673 set_mem_align (mem, 32);
12674 MEM_VOLATILE_P (mem) = 1;
12676 wdst = gen_reg_rtx (SImode);
12677 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12678 oldval, newval, mem));
12680 emit_move_insn (dst, gen_lowpart (mode, wdst));
12684 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12685 rtx oldval, rtx newval, rtx mem,
12688 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12690 emit_insn (gen_memory_barrier ());
12691 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12692 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12693 emit_label (XEXP (label1, 0));
12695 emit_load_locked (SImode, scratch, mem);
12697 /* Mask subword within loaded value for comparison with oldval.
12698 Use UNSPEC_AND to avoid clobber.*/
12699 emit_insn (gen_rtx_SET (SImode, dest,
12700 gen_rtx_UNSPEC (SImode,
12701 gen_rtvec (2, scratch, mask),
12704 x = gen_rtx_COMPARE (CCmode, dest, oldval);
12705 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12707 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12708 emit_unlikely_jump (x, label2);
12710 /* Clear subword within loaded value for insertion of new value. */
12711 emit_insn (gen_rtx_SET (SImode, scratch,
12712 gen_rtx_AND (SImode,
12713 gen_rtx_NOT (SImode, mask), scratch)));
12714 emit_insn (gen_iorsi3 (scratch, scratch, newval));
12715 emit_store_conditional (SImode, cond, mem, scratch);
12717 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12718 emit_unlikely_jump (x, label1);
12720 emit_insn (gen_isync ());
12721 emit_label (XEXP (label2, 0));
12725 /* Emit instructions to move SRC to DST. Called by splitters for
12726 multi-register moves. It will emit at most one instruction for
12727 each register that is accessed; that is, it won't emit li/lis pairs
12728 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12732 rs6000_split_multireg_move (rtx dst, rtx src)
12734 /* The register number of the first register being moved. */
12736 /* The mode that is to be moved. */
12737 enum machine_mode mode;
12738 /* The mode that the move is being done in, and its size. */
12739 enum machine_mode reg_mode;
12741 /* The number of registers that will be moved. */
12744 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12745 mode = GET_MODE (dst);
12746 nregs = hard_regno_nregs[reg][mode];
12747 if (FP_REGNO_P (reg))
12749 else if (ALTIVEC_REGNO_P (reg))
12750 reg_mode = V16QImode;
12751 else if (TARGET_E500_DOUBLE && mode == TFmode)
12754 reg_mode = word_mode;
12755 reg_mode_size = GET_MODE_SIZE (reg_mode);
12757 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12759 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12761 /* Move register range backwards, if we might have destructive
12764 for (i = nregs - 1; i >= 0; i--)
12765 emit_insn (gen_rtx_SET (VOIDmode,
12766 simplify_gen_subreg (reg_mode, dst, mode,
12767 i * reg_mode_size),
12768 simplify_gen_subreg (reg_mode, src, mode,
12769 i * reg_mode_size)));
12775 bool used_update = false;
12777 if (MEM_P (src) && INT_REGNO_P (reg))
12781 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12782 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12785 breg = XEXP (XEXP (src, 0), 0);
12786 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12787 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12788 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12789 emit_insn (TARGET_32BIT
12790 ? gen_addsi3 (breg, breg, delta_rtx)
12791 : gen_adddi3 (breg, breg, delta_rtx));
12792 src = replace_equiv_address (src, breg);
12794 else if (! rs6000_offsettable_memref_p (src))
12797 basereg = gen_rtx_REG (Pmode, reg);
12798 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12799 src = replace_equiv_address (src, basereg);
12802 breg = XEXP (src, 0);
12803 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12804 breg = XEXP (breg, 0);
12806 /* If the base register we are using to address memory is
12807 also a destination reg, then change that register last. */
12809 && REGNO (breg) >= REGNO (dst)
12810 && REGNO (breg) < REGNO (dst) + nregs)
12811 j = REGNO (breg) - REGNO (dst);
12814 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12818 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12819 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12822 breg = XEXP (XEXP (dst, 0), 0);
12823 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12824 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12825 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12827 /* We have to update the breg before doing the store.
12828 Use store with update, if available. */
12832 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12833 emit_insn (TARGET_32BIT
12834 ? (TARGET_POWERPC64
12835 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12836 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12837 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12838 used_update = true;
12841 emit_insn (TARGET_32BIT
12842 ? gen_addsi3 (breg, breg, delta_rtx)
12843 : gen_adddi3 (breg, breg, delta_rtx));
12844 dst = replace_equiv_address (dst, breg);
12847 gcc_assert (rs6000_offsettable_memref_p (dst));
12850 for (i = 0; i < nregs; i++)
12852 /* Calculate index to next subword. */
12857 /* If compiler already emitted move of first word by
12858 store with update, no need to do anything. */
12859 if (j == 0 && used_update)
12862 emit_insn (gen_rtx_SET (VOIDmode,
12863 simplify_gen_subreg (reg_mode, dst, mode,
12864 j * reg_mode_size),
12865 simplify_gen_subreg (reg_mode, src, mode,
12866 j * reg_mode_size)));
12872 /* This page contains routines that are used to determine what the
12873 function prologue and epilogue code will do and write them out. */
12875 /* Return the first fixed-point register that is required to be
12876 saved. 32 if none. */
12879 first_reg_to_save (void)
12883 /* Find lowest numbered live register. */
12884 for (first_reg = 13; first_reg <= 31; first_reg++)
12885 if (regs_ever_live[first_reg]
12886 && (! call_used_regs[first_reg]
12887 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12888 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12889 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12890 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12895 && current_function_uses_pic_offset_table
12896 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12897 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12903 /* Similar, for FP regs. */
12906 first_fp_reg_to_save (void)
12910 /* Find lowest numbered live register. */
12911 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12912 if (regs_ever_live[first_reg])
12918 /* Similar, for AltiVec regs. */
12921 first_altivec_reg_to_save (void)
12925 /* Stack frame remains as is unless we are in AltiVec ABI. */
12926 if (! TARGET_ALTIVEC_ABI)
12927 return LAST_ALTIVEC_REGNO + 1;
12929 /* Find lowest numbered live register. */
12930 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12931 if (regs_ever_live[i])
12937 /* Return a 32-bit mask of the AltiVec registers we need to set in
12938 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12939 the 32-bit word is 0. */
12941 static unsigned int
12942 compute_vrsave_mask (void)
12944 unsigned int i, mask = 0;
12946 /* First, find out if we use _any_ altivec registers. */
12947 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12948 if (regs_ever_live[i])
12949 mask |= ALTIVEC_REG_BIT (i);
12954 /* Next, remove the argument registers from the set. These must
12955 be in the VRSAVE mask set by the caller, so we don't need to add
12956 them in again. More importantly, the mask we compute here is
12957 used to generate CLOBBERs in the set_vrsave insn, and we do not
12958 wish the argument registers to die. */
12959 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12960 mask &= ~ALTIVEC_REG_BIT (i);
12962 /* Similarly, remove the return value from the set. */
12965 diddle_return_value (is_altivec_return_reg, &yes);
12967 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12973 /* For a very restricted set of circumstances, we can cut down the
12974 size of prologues/epilogues by calling our own save/restore-the-world
12978 compute_save_world_info (rs6000_stack_t *info_ptr)
12980 info_ptr->world_save_p = 1;
12981 info_ptr->world_save_p
12982 = (WORLD_SAVE_P (info_ptr)
12983 && DEFAULT_ABI == ABI_DARWIN
12984 && ! (current_function_calls_setjmp && flag_exceptions)
12985 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12986 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12987 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12988 && info_ptr->cr_save_p);
12990 /* This will not work in conjunction with sibcalls. Make sure there
12991 are none. (This check is expensive, but seldom executed.) */
12992 if (WORLD_SAVE_P (info_ptr))
12995 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12996 if ( GET_CODE (insn) == CALL_INSN
12997 && SIBLING_CALL_P (insn))
12999 info_ptr->world_save_p = 0;
13004 if (WORLD_SAVE_P (info_ptr))
13006 /* Even if we're not touching VRsave, make sure there's room on the
13007 stack for it, if it looks like we're calling SAVE_WORLD, which
13008 will attempt to save it. */
13009 info_ptr->vrsave_size = 4;
13011 /* "Save" the VRsave register too if we're saving the world. */
13012 if (info_ptr->vrsave_mask == 0)
13013 info_ptr->vrsave_mask = compute_vrsave_mask ();
13015 /* Because the Darwin register save/restore routines only handle
13016 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13018 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13019 && (info_ptr->first_altivec_reg_save
13020 >= FIRST_SAVED_ALTIVEC_REGNO));
13027 is_altivec_return_reg (rtx reg, void *xyes)
13029 bool *yes = (bool *) xyes;
13030 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13035 /* Calculate the stack information for the current function. This is
13036 complicated by having two separate calling sequences, the AIX calling
13037 sequence and the V.4 calling sequence.
13039 AIX (and Darwin/Mac OS X) stack frames look like:
13041 SP----> +---------------------------------------+
13042 | back chain to caller | 0 0
13043 +---------------------------------------+
13044 | saved CR | 4 8 (8-11)
13045 +---------------------------------------+
13047 +---------------------------------------+
13048 | reserved for compilers | 12 24
13049 +---------------------------------------+
13050 | reserved for binders | 16 32
13051 +---------------------------------------+
13052 | saved TOC pointer | 20 40
13053 +---------------------------------------+
13054 | Parameter save area (P) | 24 48
13055 +---------------------------------------+
13056 | Alloca space (A) | 24+P etc.
13057 +---------------------------------------+
13058 | Local variable space (L) | 24+P+A
13059 +---------------------------------------+
13060 | Float/int conversion temporary (X) | 24+P+A+L
13061 +---------------------------------------+
13062 | Save area for AltiVec registers (W) | 24+P+A+L+X
13063 +---------------------------------------+
13064 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13065 +---------------------------------------+
13066 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13067 +---------------------------------------+
13068 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13069 +---------------------------------------+
13070 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13071 +---------------------------------------+
13072 old SP->| back chain to caller's caller |
13073 +---------------------------------------+
13075 The required alignment for AIX configurations is two words (i.e., 8
13079 V.4 stack frames look like:
13081 SP----> +---------------------------------------+
13082 | back chain to caller | 0
13083 +---------------------------------------+
13084 | caller's saved LR | 4
13085 +---------------------------------------+
13086 | Parameter save area (P) | 8
13087 +---------------------------------------+
13088 | Alloca space (A) | 8+P
13089 +---------------------------------------+
13090 | Varargs save area (V) | 8+P+A
13091 +---------------------------------------+
13092 | Local variable space (L) | 8+P+A+V
13093 +---------------------------------------+
13094 | Float/int conversion temporary (X) | 8+P+A+V+L
13095 +---------------------------------------+
13096 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13097 +---------------------------------------+
13098 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13099 +---------------------------------------+
13100 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13101 +---------------------------------------+
13102 | SPE: area for 64-bit GP registers |
13103 +---------------------------------------+
13104 | SPE alignment padding |
13105 +---------------------------------------+
13106 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13107 +---------------------------------------+
13108 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13109 +---------------------------------------+
13110 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13111 +---------------------------------------+
13112 old SP->| back chain to caller's caller |
13113 +---------------------------------------+
13115 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13116 given. (But note below and in sysv4.h that we require only 8 and
13117 may round up the size of our stack frame anyways. The historical
13118 reason is early versions of powerpc-linux which didn't properly
13119 align the stack at program startup. A happy side-effect is that
13120 -mno-eabi libraries can be used with -meabi programs.)
13122 The EABI configuration defaults to the V.4 layout. However,
13123 the stack alignment requirements may differ. If -mno-eabi is not
13124 given, the required stack alignment is 8 bytes; if -mno-eabi is
13125 given, the required alignment is 16 bytes. (But see V.4 comment
13128 #ifndef ABI_STACK_BOUNDARY
13129 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13132 static rs6000_stack_t *
13133 rs6000_stack_info (void)
13135 static rs6000_stack_t info;
13136 rs6000_stack_t *info_ptr = &info;
13137 int reg_size = TARGET_32BIT ? 4 : 8;
13140 HOST_WIDE_INT non_fixed_size;
13142 memset (&info, 0, sizeof (info));
13146 /* Cache value so we don't rescan instruction chain over and over. */
13147 if (cfun->machine->insn_chain_scanned_p == 0)
13148 cfun->machine->insn_chain_scanned_p
13149 = spe_func_has_64bit_regs_p () + 1;
13150 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13153 /* Select which calling sequence. */
13154 info_ptr->abi = DEFAULT_ABI;
13156 /* Calculate which registers need to be saved & save area size. */
13157 info_ptr->first_gp_reg_save = first_reg_to_save ();
13158 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13159 even if it currently looks like we won't. */
13160 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13161 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13162 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13163 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13164 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13166 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13168 /* For the SPE, we have an additional upper 32-bits on each GPR.
13169 Ideally we should save the entire 64-bits only when the upper
13170 half is used in SIMD instructions. Since we only record
13171 registers live (not the size they are used in), this proves
13172 difficult because we'd have to traverse the instruction chain at
13173 the right time, taking reload into account. This is a real pain,
13174 so we opt to save the GPRs in 64-bits always if but one register
13175 gets used in 64-bits. Otherwise, all the registers in the frame
13176 get saved in 32-bits.
13178 So... since when we save all GPRs (except the SP) in 64-bits, the
13179 traditional GP save area will be empty. */
13180 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13181 info_ptr->gp_size = 0;
13183 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13184 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13186 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13187 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13188 - info_ptr->first_altivec_reg_save);
13190 /* Does this function call anything? */
13191 info_ptr->calls_p = (! current_function_is_leaf
13192 || cfun->machine->ra_needs_full_frame);
13194 /* Determine if we need to save the link register. */
13195 if ((DEFAULT_ABI == ABI_AIX
13196 && current_function_profile
13197 && !TARGET_PROFILE_KERNEL)
13198 #ifdef TARGET_RELOCATABLE
13199 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13201 || (info_ptr->first_fp_reg_save != 64
13202 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13203 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13204 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13205 || info_ptr->calls_p
13206 || rs6000_ra_ever_killed ())
13208 info_ptr->lr_save_p = 1;
13209 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
13212 /* Determine if we need to save the condition code registers. */
13213 if (regs_ever_live[CR2_REGNO]
13214 || regs_ever_live[CR3_REGNO]
13215 || regs_ever_live[CR4_REGNO])
13217 info_ptr->cr_save_p = 1;
13218 if (DEFAULT_ABI == ABI_V4)
13219 info_ptr->cr_size = reg_size;
13222 /* If the current function calls __builtin_eh_return, then we need
13223 to allocate stack space for registers that will hold data for
13224 the exception handler. */
13225 if (current_function_calls_eh_return)
13228 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13231 /* SPE saves EH registers in 64-bits. */
13232 ehrd_size = i * (TARGET_SPE_ABI
13233 && info_ptr->spe_64bit_regs_used != 0
13234 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13239 /* Determine various sizes. */
13240 info_ptr->reg_size = reg_size;
13241 info_ptr->fixed_size = RS6000_SAVE_AREA;
13242 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13243 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13244 TARGET_ALTIVEC ? 16 : 8);
13245 if (FRAME_GROWS_DOWNWARD)
13246 info_ptr->vars_size
13247 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13248 + info_ptr->parm_size,
13249 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13250 - (info_ptr->fixed_size + info_ptr->vars_size
13251 + info_ptr->parm_size);
13253 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13254 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13256 info_ptr->spe_gp_size = 0;
13258 if (TARGET_ALTIVEC_ABI)
13259 info_ptr->vrsave_mask = compute_vrsave_mask ();
13261 info_ptr->vrsave_mask = 0;
13263 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13264 info_ptr->vrsave_size = 4;
13266 info_ptr->vrsave_size = 0;
13268 compute_save_world_info (info_ptr);
13270 /* Calculate the offsets. */
13271 switch (DEFAULT_ABI)
13275 gcc_unreachable ();
13279 info_ptr->fp_save_offset = - info_ptr->fp_size;
13280 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13282 if (TARGET_ALTIVEC_ABI)
13284 info_ptr->vrsave_save_offset
13285 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13287 /* Align stack so vector save area is on a quadword boundary. */
13288 if (info_ptr->altivec_size != 0)
13289 info_ptr->altivec_padding_size
13290 = 16 - (-info_ptr->vrsave_save_offset % 16);
13292 info_ptr->altivec_padding_size = 0;
13294 info_ptr->altivec_save_offset
13295 = info_ptr->vrsave_save_offset
13296 - info_ptr->altivec_padding_size
13297 - info_ptr->altivec_size;
13299 /* Adjust for AltiVec case. */
13300 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13303 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13304 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13305 info_ptr->lr_save_offset = 2*reg_size;
13309 info_ptr->fp_save_offset = - info_ptr->fp_size;
13310 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13311 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13313 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13315 /* Align stack so SPE GPR save area is aligned on a
13316 double-word boundary. */
13317 if (info_ptr->spe_gp_size != 0)
13318 info_ptr->spe_padding_size
13319 = 8 - (-info_ptr->cr_save_offset % 8);
13321 info_ptr->spe_padding_size = 0;
13323 info_ptr->spe_gp_save_offset
13324 = info_ptr->cr_save_offset
13325 - info_ptr->spe_padding_size
13326 - info_ptr->spe_gp_size;
13328 /* Adjust for SPE case. */
13329 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13331 else if (TARGET_ALTIVEC_ABI)
13333 info_ptr->vrsave_save_offset
13334 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13336 /* Align stack so vector save area is on a quadword boundary. */
13337 if (info_ptr->altivec_size != 0)
13338 info_ptr->altivec_padding_size
13339 = 16 - (-info_ptr->vrsave_save_offset % 16);
13341 info_ptr->altivec_padding_size = 0;
13343 info_ptr->altivec_save_offset
13344 = info_ptr->vrsave_save_offset
13345 - info_ptr->altivec_padding_size
13346 - info_ptr->altivec_size;
13348 /* Adjust for AltiVec case. */
13349 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13352 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13353 info_ptr->ehrd_offset -= ehrd_size;
13354 info_ptr->lr_save_offset = reg_size;
13358 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13359 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13360 + info_ptr->gp_size
13361 + info_ptr->altivec_size
13362 + info_ptr->altivec_padding_size
13363 + info_ptr->spe_gp_size
13364 + info_ptr->spe_padding_size
13366 + info_ptr->cr_size
13367 + info_ptr->vrsave_size,
13370 non_fixed_size = (info_ptr->vars_size
13371 + info_ptr->parm_size
13372 + info_ptr->save_size);
13374 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13375 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13377 /* Determine if we need to allocate any stack frame:
13379 For AIX we need to push the stack if a frame pointer is needed
13380 (because the stack might be dynamically adjusted), if we are
13381 debugging, if we make calls, or if the sum of fp_save, gp_save,
13382 and local variables are more than the space needed to save all
13383 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13384 + 18*8 = 288 (GPR13 reserved).
13386 For V.4 we don't have the stack cushion that AIX uses, but assume
13387 that the debugger can handle stackless frames. */
13389 if (info_ptr->calls_p)
13390 info_ptr->push_p = 1;
13392 else if (DEFAULT_ABI == ABI_V4)
13393 info_ptr->push_p = non_fixed_size != 0;
13395 else if (frame_pointer_needed)
13396 info_ptr->push_p = 1;
13398 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13399 info_ptr->push_p = 1;
13402 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13404 /* Zero offsets if we're not saving those registers. */
13405 if (info_ptr->fp_size == 0)
13406 info_ptr->fp_save_offset = 0;
13408 if (info_ptr->gp_size == 0)
13409 info_ptr->gp_save_offset = 0;
13411 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13412 info_ptr->altivec_save_offset = 0;
13414 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13415 info_ptr->vrsave_save_offset = 0;
13417 if (! TARGET_SPE_ABI
13418 || info_ptr->spe_64bit_regs_used == 0
13419 || info_ptr->spe_gp_size == 0)
13420 info_ptr->spe_gp_save_offset = 0;
13422 if (! info_ptr->lr_save_p)
13423 info_ptr->lr_save_offset = 0;
13425 if (! info_ptr->cr_save_p)
13426 info_ptr->cr_save_offset = 0;
13431 /* Return true if the current function uses any GPRs in 64-bit SIMD
13435 spe_func_has_64bit_regs_p (void)
13439 /* Functions that save and restore all the call-saved registers will
13440 need to save/restore the registers in 64-bits. */
13441 if (current_function_calls_eh_return
13442 || current_function_calls_setjmp
13443 || current_function_has_nonlocal_goto)
13446 insns = get_insns ();
13448 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13454 /* FIXME: This should be implemented with attributes...
13456 (set_attr "spe64" "true")....then,
13457 if (get_spe64(insn)) return true;
13459 It's the only reliable way to do the stuff below. */
13461 i = PATTERN (insn);
13462 if (GET_CODE (i) == SET)
13464 enum machine_mode mode = GET_MODE (SET_SRC (i));
13466 if (SPE_VECTOR_MODE (mode))
13468 if (TARGET_E500_DOUBLE && mode == DFmode)
13478 debug_stack_info (rs6000_stack_t *info)
13480 const char *abi_string;
13483 info = rs6000_stack_info ();
13485 fprintf (stderr, "\nStack information for function %s:\n",
13486 ((current_function_decl && DECL_NAME (current_function_decl))
13487 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13492 default: abi_string = "Unknown"; break;
13493 case ABI_NONE: abi_string = "NONE"; break;
13494 case ABI_AIX: abi_string = "AIX"; break;
13495 case ABI_DARWIN: abi_string = "Darwin"; break;
13496 case ABI_V4: abi_string = "V.4"; break;
13499 fprintf (stderr, "\tABI = %5s\n", abi_string);
13501 if (TARGET_ALTIVEC_ABI)
13502 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13504 if (TARGET_SPE_ABI)
13505 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13507 if (info->first_gp_reg_save != 32)
13508 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13510 if (info->first_fp_reg_save != 64)
13511 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13513 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13514 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13515 info->first_altivec_reg_save);
13517 if (info->lr_save_p)
13518 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13520 if (info->cr_save_p)
13521 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13523 if (info->vrsave_mask)
13524 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13527 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13530 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13532 if (info->gp_save_offset)
13533 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13535 if (info->fp_save_offset)
13536 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13538 if (info->altivec_save_offset)
13539 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13540 info->altivec_save_offset);
13542 if (info->spe_gp_save_offset)
13543 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13544 info->spe_gp_save_offset);
13546 if (info->vrsave_save_offset)
13547 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13548 info->vrsave_save_offset);
13550 if (info->lr_save_offset)
13551 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13553 if (info->cr_save_offset)
13554 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13556 if (info->varargs_save_offset)
13557 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13559 if (info->total_size)
13560 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13563 if (info->vars_size)
13564 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13567 if (info->parm_size)
13568 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13570 if (info->fixed_size)
13571 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13574 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13576 if (info->spe_gp_size)
13577 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13580 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13582 if (info->altivec_size)
13583 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13585 if (info->vrsave_size)
13586 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13588 if (info->altivec_padding_size)
13589 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13590 info->altivec_padding_size);
13592 if (info->spe_padding_size)
13593 fprintf (stderr, "\tspe_padding_size = %5d\n",
13594 info->spe_padding_size);
13597 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13599 if (info->save_size)
13600 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13602 if (info->reg_size != 4)
13603 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13605 fprintf (stderr, "\n");
13609 rs6000_return_addr (int count, rtx frame)
13611 /* Currently we don't optimize very well between prolog and body
13612 code and for PIC code the code can be actually quite bad, so
13613 don't try to be too clever here. */
13614 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13616 cfun->machine->ra_needs_full_frame = 1;
13623 plus_constant (copy_to_reg
13624 (gen_rtx_MEM (Pmode,
13625 memory_address (Pmode, frame))),
13626 RETURN_ADDRESS_OFFSET)));
13629 cfun->machine->ra_need_lr = 1;
13630 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13633 /* Say whether a function is a candidate for sibcall handling or not.
13634 We do not allow indirect calls to be optimized into sibling calls.
13635 Also, we can't do it if there are any vector parameters; there's
13636 nowhere to put the VRsave code so it works; note that functions with
13637 vector parameters are required to have a prototype, so the argument
13638 type info must be available here. (The tail recursion case can work
13639 with vector parameters, but there's no way to distinguish here.) */
13641 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13646 if (TARGET_ALTIVEC_VRSAVE)
13648 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13649 type; type = TREE_CHAIN (type))
13651 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13655 if (DEFAULT_ABI == ABI_DARWIN
13656 || (*targetm.binds_local_p) (decl))
13658 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13660 if (!lookup_attribute ("longcall", attr_list)
13661 || lookup_attribute ("shortcall", attr_list))
13668 /* NULL if INSN insn is valid within a low-overhead loop.
13669 Otherwise return why doloop cannot be applied.
13670 PowerPC uses the COUNT register for branch on table instructions. */
13672 static const char *
13673 rs6000_invalid_within_doloop (rtx insn)
13676 return "Function call in the loop.";
13679 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13680 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13681 return "Computed branch in the loop.";
13687 rs6000_ra_ever_killed (void)
13693 if (current_function_is_thunk)
13696 /* regs_ever_live has LR marked as used if any sibcalls are present,
13697 but this should not force saving and restoring in the
13698 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13699 clobbers LR, so that is inappropriate. */
13701 /* Also, the prologue can generate a store into LR that
13702 doesn't really count, like this:
13705 bcl to set PIC register
13709 When we're called from the epilogue, we need to avoid counting
13710 this as a store. */
13712 push_topmost_sequence ();
13713 top = get_insns ();
13714 pop_topmost_sequence ();
13715 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13717 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13723 if (!SIBLING_CALL_P (insn))
13726 else if (find_regno_note (insn, REG_INC, LINK_REGISTER_REGNUM))
13728 else if (set_of (reg, insn) != NULL_RTX
13729 && !prologue_epilogue_contains (insn))
13736 /* Add a REG_MAYBE_DEAD note to the insn. */
13738 rs6000_maybe_dead (rtx insn)
13740 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13745 /* Emit instructions needed to load the TOC register.
13746 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13747 a constant pool; or for SVR4 -fpic. */
13750 rs6000_emit_load_toc_table (int fromprolog)
13753 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13755 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13758 rtx lab, tmp1, tmp2, got, tempLR;
13760 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13761 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13763 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13765 got = rs6000_got_sym ();
13766 tmp1 = tmp2 = dest;
13769 tmp1 = gen_reg_rtx (Pmode);
13770 tmp2 = gen_reg_rtx (Pmode);
13772 tempLR = (fromprolog
13773 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13774 : gen_reg_rtx (Pmode));
13775 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13777 rs6000_maybe_dead (insn);
13778 insn = emit_move_insn (tmp1, tempLR);
13780 rs6000_maybe_dead (insn);
13781 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13783 rs6000_maybe_dead (insn);
13784 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13786 rs6000_maybe_dead (insn);
13788 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13790 rtx tempLR = (fromprolog
13791 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13792 : gen_reg_rtx (Pmode));
13794 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13796 rs6000_maybe_dead (insn);
13797 insn = emit_move_insn (dest, tempLR);
13799 rs6000_maybe_dead (insn);
13801 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13804 rtx tempLR = (fromprolog
13805 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13806 : gen_reg_rtx (Pmode));
13807 rtx temp0 = (fromprolog
13808 ? gen_rtx_REG (Pmode, 0)
13809 : gen_reg_rtx (Pmode));
13815 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13816 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13818 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13819 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13821 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13823 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13824 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13832 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13833 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13834 emit_move_insn (dest, tempLR);
13835 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13837 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13839 rs6000_maybe_dead (insn);
13841 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13843 /* This is for AIX code running in non-PIC ELF32. */
13846 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13847 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13849 insn = emit_insn (gen_elf_high (dest, realsym));
13851 rs6000_maybe_dead (insn);
13852 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13854 rs6000_maybe_dead (insn);
13858 gcc_assert (DEFAULT_ABI == ABI_AIX);
13861 insn = emit_insn (gen_load_toc_aix_si (dest));
13863 insn = emit_insn (gen_load_toc_aix_di (dest));
13865 rs6000_maybe_dead (insn);
13869 /* Emit instructions to restore the link register after determining where
13870 its value has been stored. */
13873 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13875 rs6000_stack_t *info = rs6000_stack_info ();
13878 operands[0] = source;
13879 operands[1] = scratch;
13881 if (info->lr_save_p)
13883 rtx frame_rtx = stack_pointer_rtx;
13884 HOST_WIDE_INT sp_offset = 0;
13887 if (frame_pointer_needed
13888 || current_function_calls_alloca
13889 || info->total_size > 32767)
13891 tmp = gen_frame_mem (Pmode, frame_rtx);
13892 emit_move_insn (operands[1], tmp);
13893 frame_rtx = operands[1];
13895 else if (info->push_p)
13896 sp_offset = info->total_size;
13898 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13899 tmp = gen_frame_mem (Pmode, tmp);
13900 emit_move_insn (tmp, operands[0]);
13903 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13906 static GTY(()) int set = -1;
13909 get_TOC_alias_set (void)
13912 set = new_alias_set ();
13916 /* This returns nonzero if the current function uses the TOC. This is
13917 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13918 is generated by the ABI_V4 load_toc_* patterns. */
13925 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13928 rtx pat = PATTERN (insn);
13931 if (GET_CODE (pat) == PARALLEL)
13932 for (i = 0; i < XVECLEN (pat, 0); i++)
13934 rtx sub = XVECEXP (pat, 0, i);
13935 if (GET_CODE (sub) == USE)
13937 sub = XEXP (sub, 0);
13938 if (GET_CODE (sub) == UNSPEC
13939 && XINT (sub, 1) == UNSPEC_TOC)
13949 create_TOC_reference (rtx symbol)
13951 if (no_new_pseudos)
13952 regs_ever_live[TOC_REGISTER] = 1;
13953 return gen_rtx_PLUS (Pmode,
13954 gen_rtx_REG (Pmode, TOC_REGISTER),
13955 gen_rtx_CONST (Pmode,
13956 gen_rtx_MINUS (Pmode, symbol,
13957 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13960 /* If _Unwind_* has been called from within the same module,
13961 toc register is not guaranteed to be saved to 40(1) on function
13962 entry. Save it there in that case. */
13965 rs6000_aix_emit_builtin_unwind_init (void)
13968 rtx stack_top = gen_reg_rtx (Pmode);
13969 rtx opcode_addr = gen_reg_rtx (Pmode);
13970 rtx opcode = gen_reg_rtx (SImode);
13971 rtx tocompare = gen_reg_rtx (SImode);
13972 rtx no_toc_save_needed = gen_label_rtx ();
13974 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
13975 emit_move_insn (stack_top, mem);
13977 mem = gen_frame_mem (Pmode,
13978 gen_rtx_PLUS (Pmode, stack_top,
13979 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13980 emit_move_insn (opcode_addr, mem);
13981 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13982 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13983 : 0xE8410028, SImode));
13985 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13986 SImode, NULL_RTX, NULL_RTX,
13987 no_toc_save_needed);
13989 mem = gen_frame_mem (Pmode,
13990 gen_rtx_PLUS (Pmode, stack_top,
13991 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13992 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13993 emit_label (no_toc_save_needed);
13996 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
13997 and the change to the stack pointer. */
14000 rs6000_emit_stack_tie (void)
14002 rtx mem = gen_frame_mem (BLKmode,
14003 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14005 emit_insn (gen_stack_tie (mem));
14008 /* Emit the correct code for allocating stack space, as insns.
14009 If COPY_R12, make sure a copy of the old frame is left in r12.
14010 The generated code may use hard register 0 as a temporary. */
14013 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14016 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14017 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14018 rtx todec = gen_int_mode (-size, Pmode);
14020 if (INTVAL (todec) != -size)
14022 warning (0, "stack frame too large");
14023 emit_insn (gen_trap ());
14027 if (current_function_limit_stack)
14029 if (REG_P (stack_limit_rtx)
14030 && REGNO (stack_limit_rtx) > 1
14031 && REGNO (stack_limit_rtx) <= 31)
14033 emit_insn (TARGET_32BIT
14034 ? gen_addsi3 (tmp_reg,
14037 : gen_adddi3 (tmp_reg,
14041 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14044 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14046 && DEFAULT_ABI == ABI_V4)
14048 rtx toload = gen_rtx_CONST (VOIDmode,
14049 gen_rtx_PLUS (Pmode,
14053 emit_insn (gen_elf_high (tmp_reg, toload));
14054 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14055 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14059 warning (0, "stack limit expression is not supported");
14062 if (copy_r12 || ! TARGET_UPDATE)
14063 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14069 /* Need a note here so that try_split doesn't get confused. */
14070 if (get_last_insn () == NULL_RTX)
14071 emit_note (NOTE_INSN_DELETED);
14072 insn = emit_move_insn (tmp_reg, todec);
14073 try_split (PATTERN (insn), insn, 0);
14077 insn = emit_insn (TARGET_32BIT
14078 ? gen_movsi_update (stack_reg, stack_reg,
14080 : gen_movdi_di_update (stack_reg, stack_reg,
14081 todec, stack_reg));
14085 insn = emit_insn (TARGET_32BIT
14086 ? gen_addsi3 (stack_reg, stack_reg, todec)
14087 : gen_adddi3 (stack_reg, stack_reg, todec));
14088 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14089 gen_rtx_REG (Pmode, 12));
14092 RTX_FRAME_RELATED_P (insn) = 1;
14094 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14095 gen_rtx_SET (VOIDmode, stack_reg,
14096 gen_rtx_PLUS (Pmode, stack_reg,
14101 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14102 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14103 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14104 deduce these equivalences by itself so it wasn't necessary to hold
14105 its hand so much. */
14108 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14109 rtx reg2, rtx rreg)
14113 /* copy_rtx will not make unique copies of registers, so we need to
14114 ensure we don't have unwanted sharing here. */
14116 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14119 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14121 real = copy_rtx (PATTERN (insn));
14123 if (reg2 != NULL_RTX)
14124 real = replace_rtx (real, reg2, rreg);
14126 real = replace_rtx (real, reg,
14127 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14128 STACK_POINTER_REGNUM),
14131 /* We expect that 'real' is either a SET or a PARALLEL containing
14132 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14133 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14135 if (GET_CODE (real) == SET)
14139 temp = simplify_rtx (SET_SRC (set));
14141 SET_SRC (set) = temp;
14142 temp = simplify_rtx (SET_DEST (set));
14144 SET_DEST (set) = temp;
14145 if (GET_CODE (SET_DEST (set)) == MEM)
14147 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14149 XEXP (SET_DEST (set), 0) = temp;
14156 gcc_assert (GET_CODE (real) == PARALLEL);
14157 for (i = 0; i < XVECLEN (real, 0); i++)
14158 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14160 rtx set = XVECEXP (real, 0, i);
14162 temp = simplify_rtx (SET_SRC (set));
14164 SET_SRC (set) = temp;
14165 temp = simplify_rtx (SET_DEST (set));
14167 SET_DEST (set) = temp;
14168 if (GET_CODE (SET_DEST (set)) == MEM)
14170 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14172 XEXP (SET_DEST (set), 0) = temp;
14174 RTX_FRAME_RELATED_P (set) = 1;
14179 real = spe_synthesize_frame_save (real);
14181 RTX_FRAME_RELATED_P (insn) = 1;
14182 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14187 /* Given an SPE frame note, return a PARALLEL of SETs with the
14188 original note, plus a synthetic register save. */
14191 spe_synthesize_frame_save (rtx real)
14193 rtx synth, offset, reg, real2;
14195 if (GET_CODE (real) != SET
14196 || GET_MODE (SET_SRC (real)) != V2SImode)
14199 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14200 frame related note. The parallel contains a set of the register
14201 being saved, and another set to a synthetic register (n+1200).
14202 This is so we can differentiate between 64-bit and 32-bit saves.
14203 Words cannot describe this nastiness. */
14205 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14206 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14207 && GET_CODE (SET_SRC (real)) == REG);
14210 (set (mem (plus (reg x) (const y)))
14213 (set (mem (plus (reg x) (const y+4)))
14217 real2 = copy_rtx (real);
14218 PUT_MODE (SET_DEST (real2), SImode);
14219 reg = SET_SRC (real2);
14220 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14221 synth = copy_rtx (real2);
14223 if (BYTES_BIG_ENDIAN)
14225 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14226 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14229 reg = SET_SRC (synth);
14231 synth = replace_rtx (synth, reg,
14232 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14234 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14235 synth = replace_rtx (synth, offset,
14236 GEN_INT (INTVAL (offset)
14237 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14239 RTX_FRAME_RELATED_P (synth) = 1;
14240 RTX_FRAME_RELATED_P (real2) = 1;
14241 if (BYTES_BIG_ENDIAN)
14242 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14244 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14249 /* Returns an insn that has a vrsave set operation with the
14250 appropriate CLOBBERs. */
14253 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14256 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14257 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14260 = gen_rtx_SET (VOIDmode,
14262 gen_rtx_UNSPEC_VOLATILE (SImode,
14263 gen_rtvec (2, reg, vrsave),
14264 UNSPECV_SET_VRSAVE));
14268 /* We need to clobber the registers in the mask so the scheduler
14269 does not move sets to VRSAVE before sets of AltiVec registers.
14271 However, if the function receives nonlocal gotos, reload will set
14272 all call saved registers live. We will end up with:
14274 (set (reg 999) (mem))
14275 (parallel [ (set (reg vrsave) (unspec blah))
14276 (clobber (reg 999))])
14278 The clobber will cause the store into reg 999 to be dead, and
14279 flow will attempt to delete an epilogue insn. In this case, we
14280 need an unspec use/set of the register. */
14282 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14283 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14285 if (!epiloguep || call_used_regs [i])
14286 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14287 gen_rtx_REG (V4SImode, i));
14290 rtx reg = gen_rtx_REG (V4SImode, i);
14293 = gen_rtx_SET (VOIDmode,
14295 gen_rtx_UNSPEC (V4SImode,
14296 gen_rtvec (1, reg), 27));
14300 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14302 for (i = 0; i < nclobs; ++i)
14303 XVECEXP (insn, 0, i) = clobs[i];
14308 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14309 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14312 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14313 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14315 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14316 rtx replacea, replaceb;
14318 int_rtx = GEN_INT (offset);
14320 /* Some cases that need register indexed addressing. */
14321 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14322 || (TARGET_E500_DOUBLE && mode == DFmode)
14324 && SPE_VECTOR_MODE (mode)
14325 && !SPE_CONST_OFFSET_OK (offset)))
14327 /* Whomever calls us must make sure r11 is available in the
14328 flow path of instructions in the prologue. */
14329 offset_rtx = gen_rtx_REG (Pmode, 11);
14330 emit_move_insn (offset_rtx, int_rtx);
14332 replacea = offset_rtx;
14333 replaceb = int_rtx;
14337 offset_rtx = int_rtx;
14338 replacea = NULL_RTX;
14339 replaceb = NULL_RTX;
14342 reg = gen_rtx_REG (mode, regno);
14343 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14344 mem = gen_frame_mem (mode, addr);
14346 insn = emit_move_insn (mem, reg);
14348 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14351 /* Emit an offset memory reference suitable for a frame store, while
14352 converting to a valid addressing mode. */
14355 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14357 rtx int_rtx, offset_rtx;
14359 int_rtx = GEN_INT (offset);
14361 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14362 || (TARGET_E500_DOUBLE && mode == DFmode))
14364 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14365 emit_move_insn (offset_rtx, int_rtx);
14368 offset_rtx = int_rtx;
14370 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14373 /* Look for user-defined global regs. We should not save and restore these,
14374 and cannot use stmw/lmw if there are any in its range. */
14377 no_global_regs_above (int first_greg)
14380 for (i = 0; i < 32 - first_greg; i++)
14381 if (global_regs[first_greg + i])
14386 #ifndef TARGET_FIX_AND_CONTINUE
14387 #define TARGET_FIX_AND_CONTINUE 0
14390 /* Emit function prologue as insns. */
14393 rs6000_emit_prologue (void)
14395 rs6000_stack_t *info = rs6000_stack_info ();
14396 enum machine_mode reg_mode = Pmode;
14397 int reg_size = TARGET_32BIT ? 4 : 8;
14398 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14399 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14400 rtx frame_reg_rtx = sp_reg_rtx;
14401 rtx cr_save_rtx = NULL_RTX;
14403 int saving_FPRs_inline;
14404 int using_store_multiple;
14405 HOST_WIDE_INT sp_offset = 0;
14407 if (TARGET_FIX_AND_CONTINUE)
14409 /* gdb on darwin arranges to forward a function from the old
14410 address by modifying the first 5 instructions of the function
14411 to branch to the overriding function. This is necessary to
14412 permit function pointers that point to the old function to
14413 actually forward to the new function. */
14414 emit_insn (gen_nop ());
14415 emit_insn (gen_nop ());
14416 emit_insn (gen_nop ());
14417 emit_insn (gen_nop ());
14418 emit_insn (gen_nop ());
14421 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14423 reg_mode = V2SImode;
14427 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14428 && (!TARGET_SPE_ABI
14429 || info->spe_64bit_regs_used == 0)
14430 && info->first_gp_reg_save < 31
14431 && no_global_regs_above (info->first_gp_reg_save));
14432 saving_FPRs_inline = (info->first_fp_reg_save == 64
14433 || FP_SAVE_INLINE (info->first_fp_reg_save)
14434 || current_function_calls_eh_return
14435 || cfun->machine->ra_need_lr);
14437 /* For V.4, update stack before we do any saving and set back pointer. */
14439 && (DEFAULT_ABI == ABI_V4
14440 || current_function_calls_eh_return))
14442 if (info->total_size < 32767)
14443 sp_offset = info->total_size;
14445 frame_reg_rtx = frame_ptr_rtx;
14446 rs6000_emit_allocate_stack (info->total_size,
14447 (frame_reg_rtx != sp_reg_rtx
14448 && (info->cr_save_p
14450 || info->first_fp_reg_save < 64
14451 || info->first_gp_reg_save < 32
14453 if (frame_reg_rtx != sp_reg_rtx)
14454 rs6000_emit_stack_tie ();
14457 /* Handle world saves specially here. */
14458 if (WORLD_SAVE_P (info))
14464 /* save_world expects lr in r0. */
14465 if (info->lr_save_p)
14467 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14468 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14469 RTX_FRAME_RELATED_P (insn) = 1;
14472 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14473 assumptions about the offsets of various bits of the stack
14475 gcc_assert (info->gp_save_offset == -220
14476 && info->fp_save_offset == -144
14477 && info->lr_save_offset == 8
14478 && info->cr_save_offset == 4
14481 && (!current_function_calls_eh_return
14482 || info->ehrd_offset == -432)
14483 && info->vrsave_save_offset == -224
14484 && info->altivec_save_offset == (-224 -16 -192));
14486 treg = gen_rtx_REG (SImode, 11);
14487 emit_move_insn (treg, GEN_INT (-info->total_size));
14489 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14490 in R11. It also clobbers R12, so beware! */
14492 /* Preserve CR2 for save_world prologues */
14494 sz += 32 - info->first_gp_reg_save;
14495 sz += 64 - info->first_fp_reg_save;
14496 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14497 p = rtvec_alloc (sz);
14499 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14500 gen_rtx_REG (Pmode,
14501 LINK_REGISTER_REGNUM));
14502 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14503 gen_rtx_SYMBOL_REF (Pmode,
14505 /* We do floats first so that the instruction pattern matches
14507 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14509 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14510 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14511 GEN_INT (info->fp_save_offset
14512 + sp_offset + 8 * i));
14513 rtx mem = gen_frame_mem (DFmode, addr);
14515 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14517 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14519 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14520 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14521 GEN_INT (info->altivec_save_offset
14522 + sp_offset + 16 * i));
14523 rtx mem = gen_frame_mem (V4SImode, addr);
14525 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14527 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14529 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14530 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14531 GEN_INT (info->gp_save_offset
14532 + sp_offset + reg_size * i));
14533 rtx mem = gen_frame_mem (reg_mode, addr);
14535 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14539 /* CR register traditionally saved as CR2. */
14540 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14541 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14542 GEN_INT (info->cr_save_offset
14544 rtx mem = gen_frame_mem (reg_mode, addr);
14546 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14548 /* Prevent any attempt to delete the setting of r0 and treg! */
14549 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14550 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14551 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14553 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14554 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14555 NULL_RTX, NULL_RTX);
14557 if (current_function_calls_eh_return)
14562 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14563 if (regno == INVALID_REGNUM)
14565 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14566 info->ehrd_offset + sp_offset
14567 + reg_size * (int) i,
14573 /* Save AltiVec registers if needed. */
14574 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14578 /* There should be a non inline version of this, for when we
14579 are saving lots of vector registers. */
14580 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14581 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14583 rtx areg, savereg, mem;
14586 offset = info->altivec_save_offset + sp_offset
14587 + 16 * (i - info->first_altivec_reg_save);
14589 savereg = gen_rtx_REG (V4SImode, i);
14591 areg = gen_rtx_REG (Pmode, 0);
14592 emit_move_insn (areg, GEN_INT (offset));
14594 /* AltiVec addressing mode is [reg+reg]. */
14595 mem = gen_frame_mem (V4SImode,
14596 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14598 insn = emit_move_insn (mem, savereg);
14600 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14601 areg, GEN_INT (offset));
14605 /* VRSAVE is a bit vector representing which AltiVec registers
14606 are used. The OS uses this to determine which vector
14607 registers to save on a context switch. We need to save
14608 VRSAVE on the stack frame, add whatever AltiVec registers we
14609 used in this function, and do the corresponding magic in the
14612 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14613 && info->vrsave_mask != 0)
14615 rtx reg, mem, vrsave;
14618 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14619 as frame_reg_rtx and r11 as the static chain pointer for
14620 nested functions. */
14621 reg = gen_rtx_REG (SImode, 0);
14622 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14624 emit_insn (gen_get_vrsave_internal (reg));
14626 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14628 if (!WORLD_SAVE_P (info))
14631 offset = info->vrsave_save_offset + sp_offset;
14632 mem = gen_frame_mem (SImode,
14633 gen_rtx_PLUS (Pmode, frame_reg_rtx,
14634 GEN_INT (offset)));
14635 insn = emit_move_insn (mem, reg);
14638 /* Include the registers in the mask. */
14639 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14641 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14644 /* If we use the link register, get it into r0. */
14645 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14647 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14648 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14649 RTX_FRAME_RELATED_P (insn) = 1;
14652 /* If we need to save CR, put it into r12. */
14653 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14657 cr_save_rtx = gen_rtx_REG (SImode, 12);
14658 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14659 RTX_FRAME_RELATED_P (insn) = 1;
14660 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14661 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14662 But that's OK. All we have to do is specify that _one_ condition
14663 code register is saved in this stack slot. The thrower's epilogue
14664 will then restore all the call-saved registers.
14665 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14666 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14667 gen_rtx_REG (SImode, CR2_REGNO));
14668 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14673 /* Do any required saving of fpr's. If only one or two to save, do
14674 it ourselves. Otherwise, call function. */
14675 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14678 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14679 if ((regs_ever_live[info->first_fp_reg_save+i]
14680 && ! call_used_regs[info->first_fp_reg_save+i]))
14681 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14682 info->first_fp_reg_save + i,
14683 info->fp_save_offset + sp_offset + 8 * i,
14686 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14690 const char *alloc_rname;
14692 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14694 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14695 gen_rtx_REG (Pmode,
14696 LINK_REGISTER_REGNUM));
14697 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14698 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14699 alloc_rname = ggc_strdup (rname);
14700 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14701 gen_rtx_SYMBOL_REF (Pmode,
14703 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14705 rtx addr, reg, mem;
14706 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14707 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14708 GEN_INT (info->fp_save_offset
14709 + sp_offset + 8*i));
14710 mem = gen_frame_mem (DFmode, addr);
14712 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14714 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14715 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14716 NULL_RTX, NULL_RTX);
14719 /* Save GPRs. This is done as a PARALLEL if we are using
14720 the store-multiple instructions. */
14721 if (!WORLD_SAVE_P (info) && using_store_multiple)
14725 p = rtvec_alloc (32 - info->first_gp_reg_save);
14726 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14728 rtx addr, reg, mem;
14729 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14730 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14731 GEN_INT (info->gp_save_offset
14734 mem = gen_frame_mem (reg_mode, addr);
14736 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14738 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14739 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14740 NULL_RTX, NULL_RTX);
14742 else if (!WORLD_SAVE_P (info))
14745 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14746 if ((regs_ever_live[info->first_gp_reg_save + i]
14747 && (!call_used_regs[info->first_gp_reg_save + i]
14748 || (i + info->first_gp_reg_save
14749 == RS6000_PIC_OFFSET_TABLE_REGNUM
14750 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14751 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14752 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14753 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14755 rtx addr, reg, mem;
14756 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14758 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14760 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14763 if (!SPE_CONST_OFFSET_OK (offset))
14765 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14766 emit_move_insn (b, GEN_INT (offset));
14769 b = GEN_INT (offset);
14771 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14772 mem = gen_frame_mem (V2SImode, addr);
14773 insn = emit_move_insn (mem, reg);
14775 if (GET_CODE (b) == CONST_INT)
14776 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14777 NULL_RTX, NULL_RTX);
14779 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14780 b, GEN_INT (offset));
14784 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14785 GEN_INT (info->gp_save_offset
14788 mem = gen_frame_mem (reg_mode, addr);
14790 insn = emit_move_insn (mem, reg);
14791 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14792 NULL_RTX, NULL_RTX);
14797 /* ??? There's no need to emit actual instructions here, but it's the
14798 easiest way to get the frame unwind information emitted. */
14799 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14801 unsigned int i, regno;
14803 /* In AIX ABI we need to pretend we save r2 here. */
14806 rtx addr, reg, mem;
14808 reg = gen_rtx_REG (reg_mode, 2);
14809 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14810 GEN_INT (sp_offset + 5 * reg_size));
14811 mem = gen_frame_mem (reg_mode, addr);
14813 insn = emit_move_insn (mem, reg);
14814 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14815 NULL_RTX, NULL_RTX);
14816 PATTERN (insn) = gen_blockage ();
14821 regno = EH_RETURN_DATA_REGNO (i);
14822 if (regno == INVALID_REGNUM)
14825 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14826 info->ehrd_offset + sp_offset
14827 + reg_size * (int) i,
14832 /* Save lr if we used it. */
14833 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14835 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14836 GEN_INT (info->lr_save_offset + sp_offset));
14837 rtx reg = gen_rtx_REG (Pmode, 0);
14838 rtx mem = gen_rtx_MEM (Pmode, addr);
14839 /* This should not be of frame_alias_set, because of
14840 __builtin_return_address. */
14842 insn = emit_move_insn (mem, reg);
14843 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14844 NULL_RTX, NULL_RTX);
14847 /* Save CR if we use any that must be preserved. */
14848 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14850 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14851 GEN_INT (info->cr_save_offset + sp_offset));
14852 rtx mem = gen_frame_mem (SImode, addr);
14853 /* See the large comment above about why CR2_REGNO is used. */
14854 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14856 /* If r12 was used to hold the original sp, copy cr into r0 now
14858 if (REGNO (frame_reg_rtx) == 12)
14862 cr_save_rtx = gen_rtx_REG (SImode, 0);
14863 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14864 RTX_FRAME_RELATED_P (insn) = 1;
14865 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14866 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14871 insn = emit_move_insn (mem, cr_save_rtx);
14873 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14874 NULL_RTX, NULL_RTX);
14877 /* Update stack and set back pointer unless this is V.4,
14878 for which it was done previously. */
14879 if (!WORLD_SAVE_P (info) && info->push_p
14880 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14881 rs6000_emit_allocate_stack (info->total_size, FALSE);
14883 /* Set frame pointer, if needed. */
14884 if (frame_pointer_needed)
14886 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14888 RTX_FRAME_RELATED_P (insn) = 1;
14891 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14892 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14893 || (DEFAULT_ABI == ABI_V4
14894 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14895 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14897 /* If emit_load_toc_table will use the link register, we need to save
14898 it. We use R12 for this purpose because emit_load_toc_table
14899 can use register 0. This allows us to use a plain 'blr' to return
14900 from the procedure more often. */
14901 int save_LR_around_toc_setup = (TARGET_ELF
14902 && DEFAULT_ABI != ABI_AIX
14904 && ! info->lr_save_p
14905 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14906 if (save_LR_around_toc_setup)
14908 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14910 insn = emit_move_insn (frame_ptr_rtx, lr);
14911 rs6000_maybe_dead (insn);
14912 RTX_FRAME_RELATED_P (insn) = 1;
14914 rs6000_emit_load_toc_table (TRUE);
14916 insn = emit_move_insn (lr, frame_ptr_rtx);
14917 rs6000_maybe_dead (insn);
14918 RTX_FRAME_RELATED_P (insn) = 1;
14921 rs6000_emit_load_toc_table (TRUE);
14925 if (DEFAULT_ABI == ABI_DARWIN
14926 && flag_pic && current_function_uses_pic_offset_table)
14928 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14929 rtx src = machopic_function_base_sym ();
14931 /* Save and restore LR locally around this call (in R0). */
14932 if (!info->lr_save_p)
14933 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14935 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14937 insn = emit_move_insn (gen_rtx_REG (Pmode,
14938 RS6000_PIC_OFFSET_TABLE_REGNUM),
14940 rs6000_maybe_dead (insn);
14942 if (!info->lr_save_p)
14943 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14948 /* Write function prologue. */
14951 rs6000_output_function_prologue (FILE *file,
14952 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14954 rs6000_stack_t *info = rs6000_stack_info ();
14956 if (TARGET_DEBUG_STACK)
14957 debug_stack_info (info);
14959 /* Write .extern for any function we will call to save and restore
14961 if (info->first_fp_reg_save < 64
14962 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14963 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14964 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14965 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14966 RESTORE_FP_SUFFIX);
14968 /* Write .extern for AIX common mode routines, if needed. */
14969 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14971 fputs ("\t.extern __mulh\n", file);
14972 fputs ("\t.extern __mull\n", file);
14973 fputs ("\t.extern __divss\n", file);
14974 fputs ("\t.extern __divus\n", file);
14975 fputs ("\t.extern __quoss\n", file);
14976 fputs ("\t.extern __quous\n", file);
14977 common_mode_defined = 1;
14980 if (! HAVE_prologue)
14984 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14985 the "toplevel" insn chain. */
14986 emit_note (NOTE_INSN_DELETED);
14987 rs6000_emit_prologue ();
14988 emit_note (NOTE_INSN_DELETED);
14990 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14994 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14996 INSN_ADDRESSES_NEW (insn, addr);
15001 if (TARGET_DEBUG_STACK)
15002 debug_rtx_list (get_insns (), 100);
15003 final (get_insns (), file, FALSE);
15007 rs6000_pic_labelno++;
15010 /* Emit function epilogue as insns.
15012 At present, dwarf2out_frame_debug_expr doesn't understand
15013 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15014 anywhere in the epilogue. Most of the insns below would in any case
15015 need special notes to explain where r11 is in relation to the stack. */
15018 rs6000_emit_epilogue (int sibcall)
15020 rs6000_stack_t *info;
15021 int restoring_FPRs_inline;
15022 int using_load_multiple;
15023 int using_mtcr_multiple;
15024 int use_backchain_to_restore_sp;
15026 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15027 rtx frame_reg_rtx = sp_reg_rtx;
15028 enum machine_mode reg_mode = Pmode;
15029 int reg_size = TARGET_32BIT ? 4 : 8;
15032 info = rs6000_stack_info ();
15034 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15036 reg_mode = V2SImode;
15040 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15041 && (!TARGET_SPE_ABI
15042 || info->spe_64bit_regs_used == 0)
15043 && info->first_gp_reg_save < 31
15044 && no_global_regs_above (info->first_gp_reg_save));
15045 restoring_FPRs_inline = (sibcall
15046 || current_function_calls_eh_return
15047 || info->first_fp_reg_save == 64
15048 || FP_SAVE_INLINE (info->first_fp_reg_save));
15049 use_backchain_to_restore_sp = (frame_pointer_needed
15050 || current_function_calls_alloca
15051 || info->total_size > 32767);
15052 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15053 || rs6000_cpu == PROCESSOR_PPC603
15054 || rs6000_cpu == PROCESSOR_PPC750
15057 if (WORLD_SAVE_P (info))
15061 const char *alloc_rname;
15064 /* eh_rest_world_r10 will return to the location saved in the LR
15065 stack slot (which is not likely to be our caller.)
15066 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15067 rest_world is similar, except any R10 parameter is ignored.
15068 The exception-handling stuff that was here in 2.95 is no
15069 longer necessary. */
15073 + 32 - info->first_gp_reg_save
15074 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15075 + 63 + 1 - info->first_fp_reg_save);
15077 strcpy (rname, ((current_function_calls_eh_return) ?
15078 "*eh_rest_world_r10" : "*rest_world"));
15079 alloc_rname = ggc_strdup (rname);
15082 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15083 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15084 gen_rtx_REG (Pmode,
15085 LINK_REGISTER_REGNUM));
15087 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15088 /* The instruction pattern requires a clobber here;
15089 it is shared with the restVEC helper. */
15091 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15094 /* CR register traditionally saved as CR2. */
15095 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15096 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15097 GEN_INT (info->cr_save_offset));
15098 rtx mem = gen_frame_mem (reg_mode, addr);
15100 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15103 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15105 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15106 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15107 GEN_INT (info->gp_save_offset
15109 rtx mem = gen_frame_mem (reg_mode, addr);
15111 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15113 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15115 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15116 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15117 GEN_INT (info->altivec_save_offset
15119 rtx mem = gen_frame_mem (V4SImode, addr);
15121 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15123 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15125 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15126 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15127 GEN_INT (info->fp_save_offset
15129 rtx mem = gen_frame_mem (DFmode, addr);
15131 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15134 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15136 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15138 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15140 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15142 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15143 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15148 /* If we have a frame pointer, a call to alloca, or a large stack
15149 frame, restore the old stack pointer using the backchain. Otherwise,
15150 we know what size to update it with. */
15151 if (use_backchain_to_restore_sp)
15153 /* Under V.4, don't reset the stack pointer until after we're done
15154 loading the saved registers. */
15155 if (DEFAULT_ABI == ABI_V4)
15156 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15158 emit_move_insn (frame_reg_rtx,
15159 gen_rtx_MEM (Pmode, sp_reg_rtx));
15161 else if (info->push_p)
15163 if (DEFAULT_ABI == ABI_V4
15164 || current_function_calls_eh_return)
15165 sp_offset = info->total_size;
15168 emit_insn (TARGET_32BIT
15169 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15170 GEN_INT (info->total_size))
15171 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15172 GEN_INT (info->total_size)));
15176 /* Restore AltiVec registers if needed. */
15177 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15181 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15182 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15184 rtx addr, areg, mem;
15186 areg = gen_rtx_REG (Pmode, 0);
15188 (areg, GEN_INT (info->altivec_save_offset
15190 + 16 * (i - info->first_altivec_reg_save)));
15192 /* AltiVec addressing mode is [reg+reg]. */
15193 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15194 mem = gen_frame_mem (V4SImode, addr);
15196 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15200 /* Restore VRSAVE if needed. */
15201 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15202 && info->vrsave_mask != 0)
15204 rtx addr, mem, reg;
15206 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15207 GEN_INT (info->vrsave_save_offset + sp_offset));
15208 mem = gen_frame_mem (SImode, addr);
15209 reg = gen_rtx_REG (SImode, 12);
15210 emit_move_insn (reg, mem);
15212 emit_insn (generate_set_vrsave (reg, info, 1));
15215 /* Get the old lr if we saved it. */
15216 if (info->lr_save_p)
15218 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15219 info->lr_save_offset + sp_offset);
15221 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15224 /* Get the old cr if we saved it. */
15225 if (info->cr_save_p)
15227 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15228 GEN_INT (info->cr_save_offset + sp_offset));
15229 rtx mem = gen_frame_mem (SImode, addr);
15231 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15234 /* Set LR here to try to overlap restores below. */
15235 if (info->lr_save_p)
15236 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
15237 gen_rtx_REG (Pmode, 0));
15239 /* Load exception handler data registers, if needed. */
15240 if (current_function_calls_eh_return)
15242 unsigned int i, regno;
15246 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15247 GEN_INT (sp_offset + 5 * reg_size));
15248 rtx mem = gen_frame_mem (reg_mode, addr);
15250 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15257 regno = EH_RETURN_DATA_REGNO (i);
15258 if (regno == INVALID_REGNUM)
15261 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15262 info->ehrd_offset + sp_offset
15263 + reg_size * (int) i);
15265 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15269 /* Restore GPRs. This is done as a PARALLEL if we are using
15270 the load-multiple instructions. */
15271 if (using_load_multiple)
15274 p = rtvec_alloc (32 - info->first_gp_reg_save);
15275 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15277 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15278 GEN_INT (info->gp_save_offset
15281 rtx mem = gen_frame_mem (reg_mode, addr);
15284 gen_rtx_SET (VOIDmode,
15285 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15288 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15291 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15292 if ((regs_ever_live[info->first_gp_reg_save + i]
15293 && (!call_used_regs[info->first_gp_reg_save + i]
15294 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15295 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15296 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
15297 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15298 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
15300 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15301 GEN_INT (info->gp_save_offset
15304 rtx mem = gen_frame_mem (reg_mode, addr);
15306 /* Restore 64-bit quantities for SPE. */
15307 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15309 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
15312 if (!SPE_CONST_OFFSET_OK (offset))
15314 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15315 emit_move_insn (b, GEN_INT (offset));
15318 b = GEN_INT (offset);
15320 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
15321 mem = gen_frame_mem (V2SImode, addr);
15324 emit_move_insn (gen_rtx_REG (reg_mode,
15325 info->first_gp_reg_save + i), mem);
15328 /* Restore fpr's if we need to do it without calling a function. */
15329 if (restoring_FPRs_inline)
15330 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15331 if ((regs_ever_live[info->first_fp_reg_save+i]
15332 && ! call_used_regs[info->first_fp_reg_save+i]))
15335 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15336 GEN_INT (info->fp_save_offset
15339 mem = gen_frame_mem (DFmode, addr);
15341 emit_move_insn (gen_rtx_REG (DFmode,
15342 info->first_fp_reg_save + i),
15346 /* If we saved cr, restore it here. Just those that were used. */
15347 if (info->cr_save_p)
15349 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15352 if (using_mtcr_multiple)
15354 for (i = 0; i < 8; i++)
15355 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15357 gcc_assert (count);
15360 if (using_mtcr_multiple && count > 1)
15365 p = rtvec_alloc (count);
15368 for (i = 0; i < 8; i++)
15369 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15371 rtvec r = rtvec_alloc (2);
15372 RTVEC_ELT (r, 0) = r12_rtx;
15373 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15374 RTVEC_ELT (p, ndx) =
15375 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15376 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15379 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15380 gcc_assert (ndx == count);
15383 for (i = 0; i < 8; i++)
15384 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
15386 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15392 /* If this is V.4, unwind the stack pointer after all of the loads
15394 if (frame_reg_rtx != sp_reg_rtx)
15396 /* This blockage is needed so that sched doesn't decide to move
15397 the sp change before the register restores. */
15398 rs6000_emit_stack_tie ();
15399 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15401 else if (sp_offset != 0)
15402 emit_insn (TARGET_32BIT
15403 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15404 GEN_INT (sp_offset))
15405 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15406 GEN_INT (sp_offset)));
15408 if (current_function_calls_eh_return)
15410 rtx sa = EH_RETURN_STACKADJ_RTX;
15411 emit_insn (TARGET_32BIT
15412 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15413 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15419 if (! restoring_FPRs_inline)
15420 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15422 p = rtvec_alloc (2);
15424 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15425 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15426 gen_rtx_REG (Pmode,
15427 LINK_REGISTER_REGNUM));
15429 /* If we have to restore more than two FP registers, branch to the
15430 restore function. It will return to our caller. */
15431 if (! restoring_FPRs_inline)
15435 const char *alloc_rname;
15437 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15438 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15439 alloc_rname = ggc_strdup (rname);
15440 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15441 gen_rtx_SYMBOL_REF (Pmode,
15444 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15447 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15448 GEN_INT (info->fp_save_offset + 8*i));
15449 mem = gen_frame_mem (DFmode, addr);
15451 RTVEC_ELT (p, i+3) =
15452 gen_rtx_SET (VOIDmode,
15453 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15458 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15462 /* Write function epilogue. */
15465 rs6000_output_function_epilogue (FILE *file,
15466 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15468 if (! HAVE_epilogue)
15470 rtx insn = get_last_insn ();
15471 /* If the last insn was a BARRIER, we don't have to write anything except
15472 the trace table. */
15473 if (GET_CODE (insn) == NOTE)
15474 insn = prev_nonnote_insn (insn);
15475 if (insn == 0 || GET_CODE (insn) != BARRIER)
15477 /* This is slightly ugly, but at least we don't have two
15478 copies of the epilogue-emitting code. */
15481 /* A NOTE_INSN_DELETED is supposed to be at the start
15482 and end of the "toplevel" insn chain. */
15483 emit_note (NOTE_INSN_DELETED);
15484 rs6000_emit_epilogue (FALSE);
15485 emit_note (NOTE_INSN_DELETED);
15487 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15491 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15493 INSN_ADDRESSES_NEW (insn, addr);
15498 if (TARGET_DEBUG_STACK)
15499 debug_rtx_list (get_insns (), 100);
15500 final (get_insns (), file, FALSE);
15506 macho_branch_islands ();
15507 /* Mach-O doesn't support labels at the end of objects, so if
15508 it looks like we might want one, insert a NOP. */
15510 rtx insn = get_last_insn ();
15513 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15514 insn = PREV_INSN (insn);
15518 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15519 fputs ("\tnop\n", file);
15523 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15526 We don't output a traceback table if -finhibit-size-directive was
15527 used. The documentation for -finhibit-size-directive reads
15528 ``don't output a @code{.size} assembler directive, or anything
15529 else that would cause trouble if the function is split in the
15530 middle, and the two halves are placed at locations far apart in
15531 memory.'' The traceback table has this property, since it
15532 includes the offset from the start of the function to the
15533 traceback table itself.
15535 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15536 different traceback table. */
15537 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15538 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15540 const char *fname = NULL;
15541 const char *language_string = lang_hooks.name;
15542 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15544 int optional_tbtab;
15545 rs6000_stack_t *info = rs6000_stack_info ();
15547 if (rs6000_traceback == traceback_full)
15548 optional_tbtab = 1;
15549 else if (rs6000_traceback == traceback_part)
15550 optional_tbtab = 0;
15552 optional_tbtab = !optimize_size && !TARGET_ELF;
15554 if (optional_tbtab)
15556 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15557 while (*fname == '.') /* V.4 encodes . in the name */
15560 /* Need label immediately before tbtab, so we can compute
15561 its offset from the function start. */
15562 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15563 ASM_OUTPUT_LABEL (file, fname);
15566 /* The .tbtab pseudo-op can only be used for the first eight
15567 expressions, since it can't handle the possibly variable
15568 length fields that follow. However, if you omit the optional
15569 fields, the assembler outputs zeros for all optional fields
15570 anyways, giving each variable length field is minimum length
15571 (as defined in sys/debug.h). Thus we can not use the .tbtab
15572 pseudo-op at all. */
15574 /* An all-zero word flags the start of the tbtab, for debuggers
15575 that have to find it by searching forward from the entry
15576 point or from the current pc. */
15577 fputs ("\t.long 0\n", file);
15579 /* Tbtab format type. Use format type 0. */
15580 fputs ("\t.byte 0,", file);
15582 /* Language type. Unfortunately, there does not seem to be any
15583 official way to discover the language being compiled, so we
15584 use language_string.
15585 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15586 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15587 a number, so for now use 9. */
15588 if (! strcmp (language_string, "GNU C"))
15590 else if (! strcmp (language_string, "GNU F77")
15591 || ! strcmp (language_string, "GNU F95"))
15593 else if (! strcmp (language_string, "GNU Pascal"))
15595 else if (! strcmp (language_string, "GNU Ada"))
15597 else if (! strcmp (language_string, "GNU C++")
15598 || ! strcmp (language_string, "GNU Objective-C++"))
15600 else if (! strcmp (language_string, "GNU Java"))
15602 else if (! strcmp (language_string, "GNU Objective-C"))
15605 gcc_unreachable ();
15606 fprintf (file, "%d,", i);
15608 /* 8 single bit fields: global linkage (not set for C extern linkage,
15609 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15610 from start of procedure stored in tbtab, internal function, function
15611 has controlled storage, function has no toc, function uses fp,
15612 function logs/aborts fp operations. */
15613 /* Assume that fp operations are used if any fp reg must be saved. */
15614 fprintf (file, "%d,",
15615 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15617 /* 6 bitfields: function is interrupt handler, name present in
15618 proc table, function calls alloca, on condition directives
15619 (controls stack walks, 3 bits), saves condition reg, saves
15621 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15622 set up as a frame pointer, even when there is no alloca call. */
15623 fprintf (file, "%d,",
15624 ((optional_tbtab << 6)
15625 | ((optional_tbtab & frame_pointer_needed) << 5)
15626 | (info->cr_save_p << 1)
15627 | (info->lr_save_p)));
15629 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15631 fprintf (file, "%d,",
15632 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15634 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15635 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15637 if (optional_tbtab)
15639 /* Compute the parameter info from the function decl argument
15642 int next_parm_info_bit = 31;
15644 for (decl = DECL_ARGUMENTS (current_function_decl);
15645 decl; decl = TREE_CHAIN (decl))
15647 rtx parameter = DECL_INCOMING_RTL (decl);
15648 enum machine_mode mode = GET_MODE (parameter);
15650 if (GET_CODE (parameter) == REG)
15652 if (SCALAR_FLOAT_MODE_P (mode))
15670 gcc_unreachable ();
15673 /* If only one bit will fit, don't or in this entry. */
15674 if (next_parm_info_bit > 0)
15675 parm_info |= (bits << (next_parm_info_bit - 1));
15676 next_parm_info_bit -= 2;
15680 fixed_parms += ((GET_MODE_SIZE (mode)
15681 + (UNITS_PER_WORD - 1))
15683 next_parm_info_bit -= 1;
15689 /* Number of fixed point parameters. */
15690 /* This is actually the number of words of fixed point parameters; thus
15691 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15692 fprintf (file, "%d,", fixed_parms);
15694 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15696 /* This is actually the number of fp registers that hold parameters;
15697 and thus the maximum value is 13. */
15698 /* Set parameters on stack bit if parameters are not in their original
15699 registers, regardless of whether they are on the stack? Xlc
15700 seems to set the bit when not optimizing. */
15701 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15703 if (! optional_tbtab)
15706 /* Optional fields follow. Some are variable length. */
15708 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15709 11 double float. */
15710 /* There is an entry for each parameter in a register, in the order that
15711 they occur in the parameter list. Any intervening arguments on the
15712 stack are ignored. If the list overflows a long (max possible length
15713 34 bits) then completely leave off all elements that don't fit. */
15714 /* Only emit this long if there was at least one parameter. */
15715 if (fixed_parms || float_parms)
15716 fprintf (file, "\t.long %d\n", parm_info);
15718 /* Offset from start of code to tb table. */
15719 fputs ("\t.long ", file);
15720 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15722 RS6000_OUTPUT_BASENAME (file, fname);
15724 assemble_name (file, fname);
15726 rs6000_output_function_entry (file, fname);
15729 /* Interrupt handler mask. */
15730 /* Omit this long, since we never set the interrupt handler bit
15733 /* Number of CTL (controlled storage) anchors. */
15734 /* Omit this long, since the has_ctl bit is never set above. */
15736 /* Displacement into stack of each CTL anchor. */
15737 /* Omit this list of longs, because there are no CTL anchors. */
15739 /* Length of function name. */
15742 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15744 /* Function name. */
15745 assemble_string (fname, strlen (fname));
15747 /* Register for alloca automatic storage; this is always reg 31.
15748 Only emit this if the alloca bit was set above. */
15749 if (frame_pointer_needed)
15750 fputs ("\t.byte 31\n", file);
15752 fputs ("\t.align 2\n", file);
15756 /* A C compound statement that outputs the assembler code for a thunk
15757 function, used to implement C++ virtual function calls with
15758 multiple inheritance. The thunk acts as a wrapper around a virtual
15759 function, adjusting the implicit object parameter before handing
15760 control off to the real function.
15762 First, emit code to add the integer DELTA to the location that
15763 contains the incoming first argument. Assume that this argument
15764 contains a pointer, and is the one used to pass the `this' pointer
15765 in C++. This is the incoming argument *before* the function
15766 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15767 values of all other incoming arguments.
15769 After the addition, emit code to jump to FUNCTION, which is a
15770 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15771 not touch the return address. Hence returning from FUNCTION will
15772 return to whoever called the current `thunk'.
15774 The effect must be as if FUNCTION had been called directly with the
15775 adjusted first argument. This macro is responsible for emitting
15776 all of the code for a thunk function; output_function_prologue()
15777 and output_function_epilogue() are not invoked.
15779 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15780 been extracted from it.) It might possibly be useful on some
15781 targets, but probably not.
15783 If you do not define this macro, the target-independent code in the
15784 C++ frontend will generate a less efficient heavyweight thunk that
15785 calls FUNCTION instead of jumping to it. The generic approach does
15786 not support varargs. */
15789 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15790 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15793 rtx this, insn, funexp;
15795 reload_completed = 1;
15796 epilogue_completed = 1;
15797 no_new_pseudos = 1;
15798 reset_block_changes ();
15800 /* Mark the end of the (empty) prologue. */
15801 emit_note (NOTE_INSN_PROLOGUE_END);
15803 /* Find the "this" pointer. If the function returns a structure,
15804 the structure return pointer is in r3. */
15805 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15806 this = gen_rtx_REG (Pmode, 4);
15808 this = gen_rtx_REG (Pmode, 3);
15810 /* Apply the constant offset, if required. */
15813 rtx delta_rtx = GEN_INT (delta);
15814 emit_insn (TARGET_32BIT
15815 ? gen_addsi3 (this, this, delta_rtx)
15816 : gen_adddi3 (this, this, delta_rtx));
15819 /* Apply the offset from the vtable, if required. */
15822 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15823 rtx tmp = gen_rtx_REG (Pmode, 12);
15825 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15826 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15828 emit_insn (TARGET_32BIT
15829 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15830 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15831 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15835 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15837 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15839 emit_insn (TARGET_32BIT
15840 ? gen_addsi3 (this, this, tmp)
15841 : gen_adddi3 (this, this, tmp));
15844 /* Generate a tail call to the target function. */
15845 if (!TREE_USED (function))
15847 assemble_external (function);
15848 TREE_USED (function) = 1;
15850 funexp = XEXP (DECL_RTL (function), 0);
15851 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15854 if (MACHOPIC_INDIRECT)
15855 funexp = machopic_indirect_call_target (funexp);
15858 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15859 generate sibcall RTL explicitly. */
15860 insn = emit_call_insn (
15861 gen_rtx_PARALLEL (VOIDmode,
15863 gen_rtx_CALL (VOIDmode,
15864 funexp, const0_rtx),
15865 gen_rtx_USE (VOIDmode, const0_rtx),
15866 gen_rtx_USE (VOIDmode,
15867 gen_rtx_REG (SImode,
15868 LINK_REGISTER_REGNUM)),
15869 gen_rtx_RETURN (VOIDmode))));
15870 SIBLING_CALL_P (insn) = 1;
15873 /* Run just enough of rest_of_compilation to get the insns emitted.
15874 There's not really enough bulk here to make other passes such as
15875 instruction scheduling worth while. Note that use_thunk calls
15876 assemble_start_function and assemble_end_function. */
15877 insn = get_insns ();
15878 insn_locators_initialize ();
15879 shorten_branches (insn);
15880 final_start_function (insn, file, 1);
15881 final (insn, file, 1);
15882 final_end_function ();
15884 reload_completed = 0;
15885 epilogue_completed = 0;
15886 no_new_pseudos = 0;
15889 /* A quick summary of the various types of 'constant-pool tables'
15892 Target Flags Name One table per
15893 AIX (none) AIX TOC object file
15894 AIX -mfull-toc AIX TOC object file
15895 AIX -mminimal-toc AIX minimal TOC translation unit
15896 SVR4/EABI (none) SVR4 SDATA object file
15897 SVR4/EABI -fpic SVR4 pic object file
15898 SVR4/EABI -fPIC SVR4 PIC translation unit
15899 SVR4/EABI -mrelocatable EABI TOC function
15900 SVR4/EABI -maix AIX TOC object file
15901 SVR4/EABI -maix -mminimal-toc
15902 AIX minimal TOC translation unit
15904 Name Reg. Set by entries contains:
15905 made by addrs? fp? sum?
15907 AIX TOC 2 crt0 as Y option option
15908 AIX minimal TOC 30 prolog gcc Y Y option
15909 SVR4 SDATA 13 crt0 gcc N Y N
15910 SVR4 pic 30 prolog ld Y not yet N
15911 SVR4 PIC 30 prolog gcc Y option option
15912 EABI TOC 30 prolog gcc Y option option
15916 /* Hash functions for the hash table. */
15919 rs6000_hash_constant (rtx k)
15921 enum rtx_code code = GET_CODE (k);
15922 enum machine_mode mode = GET_MODE (k);
15923 unsigned result = (code << 3) ^ mode;
15924 const char *format;
15927 format = GET_RTX_FORMAT (code);
15928 flen = strlen (format);
15934 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15937 if (mode != VOIDmode)
15938 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15950 for (; fidx < flen; fidx++)
15951 switch (format[fidx])
15956 const char *str = XSTR (k, fidx);
15957 len = strlen (str);
15958 result = result * 613 + len;
15959 for (i = 0; i < len; i++)
15960 result = result * 613 + (unsigned) str[i];
15965 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15969 result = result * 613 + (unsigned) XINT (k, fidx);
15972 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15973 result = result * 613 + (unsigned) XWINT (k, fidx);
15977 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15978 result = result * 613 + (unsigned) (XWINT (k, fidx)
15985 gcc_unreachable ();
15992 toc_hash_function (const void *hash_entry)
15994 const struct toc_hash_struct *thc =
15995 (const struct toc_hash_struct *) hash_entry;
15996 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15999 /* Compare H1 and H2 for equivalence. */
16002 toc_hash_eq (const void *h1, const void *h2)
16004 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16005 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16007 if (((const struct toc_hash_struct *) h1)->key_mode
16008 != ((const struct toc_hash_struct *) h2)->key_mode)
16011 return rtx_equal_p (r1, r2);
16014 /* These are the names given by the C++ front-end to vtables, and
16015 vtable-like objects. Ideally, this logic should not be here;
16016 instead, there should be some programmatic way of inquiring as
16017 to whether or not an object is a vtable. */
16019 #define VTABLE_NAME_P(NAME) \
16020 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16021 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16022 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16023 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16024 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16027 rs6000_output_symbol_ref (FILE *file, rtx x)
16029 /* Currently C++ toc references to vtables can be emitted before it
16030 is decided whether the vtable is public or private. If this is
16031 the case, then the linker will eventually complain that there is
16032 a reference to an unknown section. Thus, for vtables only,
16033 we emit the TOC reference to reference the symbol and not the
16035 const char *name = XSTR (x, 0);
16037 if (VTABLE_NAME_P (name))
16039 RS6000_OUTPUT_BASENAME (file, name);
16042 assemble_name (file, name);
16045 /* Output a TOC entry. We derive the entry name from what is being
16049 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16052 const char *name = buf;
16053 const char *real_name;
16055 HOST_WIDE_INT offset = 0;
16057 gcc_assert (!TARGET_NO_TOC);
16059 /* When the linker won't eliminate them, don't output duplicate
16060 TOC entries (this happens on AIX if there is any kind of TOC,
16061 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16063 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16065 struct toc_hash_struct *h;
16068 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16069 time because GGC is not initialized at that point. */
16070 if (toc_hash_table == NULL)
16071 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16072 toc_hash_eq, NULL);
16074 h = ggc_alloc (sizeof (*h));
16076 h->key_mode = mode;
16077 h->labelno = labelno;
16079 found = htab_find_slot (toc_hash_table, h, 1);
16080 if (*found == NULL)
16082 else /* This is indeed a duplicate.
16083 Set this label equal to that label. */
16085 fputs ("\t.set ", file);
16086 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16087 fprintf (file, "%d,", labelno);
16088 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16089 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16095 /* If we're going to put a double constant in the TOC, make sure it's
16096 aligned properly when strict alignment is on. */
16097 if (GET_CODE (x) == CONST_DOUBLE
16098 && STRICT_ALIGNMENT
16099 && GET_MODE_BITSIZE (mode) >= 64
16100 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16101 ASM_OUTPUT_ALIGN (file, 3);
16104 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16106 /* Handle FP constants specially. Note that if we have a minimal
16107 TOC, things we put here aren't actually in the TOC, so we can allow
16109 if (GET_CODE (x) == CONST_DOUBLE &&
16110 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16112 REAL_VALUE_TYPE rv;
16115 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16116 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16117 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16119 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16123 if (TARGET_MINIMAL_TOC)
16124 fputs (DOUBLE_INT_ASM_OP, file);
16126 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16127 k[0] & 0xffffffff, k[1] & 0xffffffff,
16128 k[2] & 0xffffffff, k[3] & 0xffffffff);
16129 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16130 k[0] & 0xffffffff, k[1] & 0xffffffff,
16131 k[2] & 0xffffffff, k[3] & 0xffffffff);
16136 if (TARGET_MINIMAL_TOC)
16137 fputs ("\t.long ", file);
16139 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16140 k[0] & 0xffffffff, k[1] & 0xffffffff,
16141 k[2] & 0xffffffff, k[3] & 0xffffffff);
16142 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16143 k[0] & 0xffffffff, k[1] & 0xffffffff,
16144 k[2] & 0xffffffff, k[3] & 0xffffffff);
16148 else if (GET_CODE (x) == CONST_DOUBLE &&
16149 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16151 REAL_VALUE_TYPE rv;
16154 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16156 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16157 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16159 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16163 if (TARGET_MINIMAL_TOC)
16164 fputs (DOUBLE_INT_ASM_OP, file);
16166 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16167 k[0] & 0xffffffff, k[1] & 0xffffffff);
16168 fprintf (file, "0x%lx%08lx\n",
16169 k[0] & 0xffffffff, k[1] & 0xffffffff);
16174 if (TARGET_MINIMAL_TOC)
16175 fputs ("\t.long ", file);
16177 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16178 k[0] & 0xffffffff, k[1] & 0xffffffff);
16179 fprintf (file, "0x%lx,0x%lx\n",
16180 k[0] & 0xffffffff, k[1] & 0xffffffff);
16184 else if (GET_CODE (x) == CONST_DOUBLE &&
16185 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16187 REAL_VALUE_TYPE rv;
16190 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16191 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16192 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16194 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16198 if (TARGET_MINIMAL_TOC)
16199 fputs (DOUBLE_INT_ASM_OP, file);
16201 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16202 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16207 if (TARGET_MINIMAL_TOC)
16208 fputs ("\t.long ", file);
16210 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16211 fprintf (file, "0x%lx\n", l & 0xffffffff);
16215 else if (GET_MODE (x) == VOIDmode
16216 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16218 unsigned HOST_WIDE_INT low;
16219 HOST_WIDE_INT high;
16221 if (GET_CODE (x) == CONST_DOUBLE)
16223 low = CONST_DOUBLE_LOW (x);
16224 high = CONST_DOUBLE_HIGH (x);
16227 #if HOST_BITS_PER_WIDE_INT == 32
16230 high = (low & 0x80000000) ? ~0 : 0;
16234 low = INTVAL (x) & 0xffffffff;
16235 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16239 /* TOC entries are always Pmode-sized, but since this
16240 is a bigendian machine then if we're putting smaller
16241 integer constants in the TOC we have to pad them.
16242 (This is still a win over putting the constants in
16243 a separate constant pool, because then we'd have
16244 to have both a TOC entry _and_ the actual constant.)
16246 For a 32-bit target, CONST_INT values are loaded and shifted
16247 entirely within `low' and can be stored in one TOC entry. */
16249 /* It would be easy to make this work, but it doesn't now. */
16250 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16252 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16254 #if HOST_BITS_PER_WIDE_INT == 32
16255 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16256 POINTER_SIZE, &low, &high, 0);
16259 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16260 high = (HOST_WIDE_INT) low >> 32;
16267 if (TARGET_MINIMAL_TOC)
16268 fputs (DOUBLE_INT_ASM_OP, file);
16270 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16271 (long) high & 0xffffffff, (long) low & 0xffffffff);
16272 fprintf (file, "0x%lx%08lx\n",
16273 (long) high & 0xffffffff, (long) low & 0xffffffff);
16278 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16280 if (TARGET_MINIMAL_TOC)
16281 fputs ("\t.long ", file);
16283 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16284 (long) high & 0xffffffff, (long) low & 0xffffffff);
16285 fprintf (file, "0x%lx,0x%lx\n",
16286 (long) high & 0xffffffff, (long) low & 0xffffffff);
16290 if (TARGET_MINIMAL_TOC)
16291 fputs ("\t.long ", file);
16293 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16294 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16300 if (GET_CODE (x) == CONST)
16302 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16304 base = XEXP (XEXP (x, 0), 0);
16305 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16308 switch (GET_CODE (base))
16311 name = XSTR (base, 0);
16315 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16316 CODE_LABEL_NUMBER (XEXP (base, 0)));
16320 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16324 gcc_unreachable ();
16327 real_name = (*targetm.strip_name_encoding) (name);
16328 if (TARGET_MINIMAL_TOC)
16329 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16332 fprintf (file, "\t.tc %s", real_name);
16335 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16337 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16339 fputs ("[TC],", file);
16342 /* Currently C++ toc references to vtables can be emitted before it
16343 is decided whether the vtable is public or private. If this is
16344 the case, then the linker will eventually complain that there is
16345 a TOC reference to an unknown section. Thus, for vtables only,
16346 we emit the TOC reference to reference the symbol and not the
16348 if (VTABLE_NAME_P (name))
16350 RS6000_OUTPUT_BASENAME (file, name);
16352 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16353 else if (offset > 0)
16354 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16357 output_addr_const (file, x);
16361 /* Output an assembler pseudo-op to write an ASCII string of N characters
16362 starting at P to FILE.
16364 On the RS/6000, we have to do this using the .byte operation and
16365 write out special characters outside the quoted string.
16366 Also, the assembler is broken; very long strings are truncated,
16367 so we must artificially break them up early. */
16370 output_ascii (FILE *file, const char *p, int n)
16373 int i, count_string;
16374 const char *for_string = "\t.byte \"";
16375 const char *for_decimal = "\t.byte ";
16376 const char *to_close = NULL;
16379 for (i = 0; i < n; i++)
16382 if (c >= ' ' && c < 0177)
16385 fputs (for_string, file);
16388 /* Write two quotes to get one. */
16396 for_decimal = "\"\n\t.byte ";
16400 if (count_string >= 512)
16402 fputs (to_close, file);
16404 for_string = "\t.byte \"";
16405 for_decimal = "\t.byte ";
16413 fputs (for_decimal, file);
16414 fprintf (file, "%d", c);
16416 for_string = "\n\t.byte \"";
16417 for_decimal = ", ";
16423 /* Now close the string if we have written one. Then end the line. */
16425 fputs (to_close, file);
16428 /* Generate a unique section name for FILENAME for a section type
16429 represented by SECTION_DESC. Output goes into BUF.
16431 SECTION_DESC can be any string, as long as it is different for each
16432 possible section type.
16434 We name the section in the same manner as xlc. The name begins with an
16435 underscore followed by the filename (after stripping any leading directory
16436 names) with the last period replaced by the string SECTION_DESC. If
16437 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16441 rs6000_gen_section_name (char **buf, const char *filename,
16442 const char *section_desc)
16444 const char *q, *after_last_slash, *last_period = 0;
16448 after_last_slash = filename;
16449 for (q = filename; *q; q++)
16452 after_last_slash = q + 1;
16453 else if (*q == '.')
16457 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16458 *buf = (char *) xmalloc (len);
16463 for (q = after_last_slash; *q; q++)
16465 if (q == last_period)
16467 strcpy (p, section_desc);
16468 p += strlen (section_desc);
16472 else if (ISALNUM (*q))
16476 if (last_period == 0)
16477 strcpy (p, section_desc);
16482 /* Emit profile function. */
16485 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16487 /* Non-standard profiling for kernels, which just saves LR then calls
16488 _mcount without worrying about arg saves. The idea is to change
16489 the function prologue as little as possible as it isn't easy to
16490 account for arg save/restore code added just for _mcount. */
16491 if (TARGET_PROFILE_KERNEL)
16494 if (DEFAULT_ABI == ABI_AIX)
16496 #ifndef NO_PROFILE_COUNTERS
16497 # define NO_PROFILE_COUNTERS 0
16499 if (NO_PROFILE_COUNTERS)
16500 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16504 const char *label_name;
16507 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16508 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16509 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16511 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16515 else if (DEFAULT_ABI == ABI_DARWIN)
16517 const char *mcount_name = RS6000_MCOUNT;
16518 int caller_addr_regno = LINK_REGISTER_REGNUM;
16520 /* Be conservative and always set this, at least for now. */
16521 current_function_uses_pic_offset_table = 1;
16524 /* For PIC code, set up a stub and collect the caller's address
16525 from r0, which is where the prologue puts it. */
16526 if (MACHOPIC_INDIRECT
16527 && current_function_uses_pic_offset_table)
16528 caller_addr_regno = 0;
16530 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16532 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16536 /* Write function profiler code. */
16539 output_function_profiler (FILE *file, int labelno)
16543 switch (DEFAULT_ABI)
16546 gcc_unreachable ();
16551 warning (0, "no profiling of 64-bit code for this ABI");
16554 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16555 fprintf (file, "\tmflr %s\n", reg_names[0]);
16556 if (NO_PROFILE_COUNTERS)
16558 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16559 reg_names[0], reg_names[1]);
16561 else if (TARGET_SECURE_PLT && flag_pic)
16563 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16564 reg_names[0], reg_names[1]);
16565 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16566 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16567 reg_names[12], reg_names[12]);
16568 assemble_name (file, buf);
16569 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16570 assemble_name (file, buf);
16571 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16573 else if (flag_pic == 1)
16575 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16576 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16577 reg_names[0], reg_names[1]);
16578 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16579 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16580 assemble_name (file, buf);
16581 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16583 else if (flag_pic > 1)
16585 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16586 reg_names[0], reg_names[1]);
16587 /* Now, we need to get the address of the label. */
16588 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16589 assemble_name (file, buf);
16590 fputs ("-.\n1:", file);
16591 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16592 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16593 reg_names[0], reg_names[11]);
16594 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16595 reg_names[0], reg_names[0], reg_names[11]);
16599 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16600 assemble_name (file, buf);
16601 fputs ("@ha\n", file);
16602 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16603 reg_names[0], reg_names[1]);
16604 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16605 assemble_name (file, buf);
16606 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16609 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16610 fprintf (file, "\tbl %s%s\n",
16611 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16616 if (!TARGET_PROFILE_KERNEL)
16618 /* Don't do anything, done in output_profile_hook (). */
16622 gcc_assert (!TARGET_32BIT);
16624 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16625 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16627 if (cfun->static_chain_decl != NULL)
16629 asm_fprintf (file, "\tstd %s,24(%s)\n",
16630 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16631 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16632 asm_fprintf (file, "\tld %s,24(%s)\n",
16633 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16636 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16644 /* The following variable value is the last issued insn. */
16646 static rtx last_scheduled_insn;
16648 /* The following variable helps to balance issuing of load and
16649 store instructions */
16651 static int load_store_pendulum;
16653 /* Power4 load update and store update instructions are cracked into a
16654 load or store and an integer insn which are executed in the same cycle.
16655 Branches have their own dispatch slot which does not count against the
16656 GCC issue rate, but it changes the program flow so there are no other
16657 instructions to issue in this cycle. */
16660 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16661 int verbose ATTRIBUTE_UNUSED,
16662 rtx insn, int more)
16664 last_scheduled_insn = insn;
16665 if (GET_CODE (PATTERN (insn)) == USE
16666 || GET_CODE (PATTERN (insn)) == CLOBBER)
16668 cached_can_issue_more = more;
16669 return cached_can_issue_more;
16672 if (insn_terminates_group_p (insn, current_group))
16674 cached_can_issue_more = 0;
16675 return cached_can_issue_more;
16678 /* If no reservation, but reach here */
16679 if (recog_memoized (insn) < 0)
16682 if (rs6000_sched_groups)
16684 if (is_microcoded_insn (insn))
16685 cached_can_issue_more = 0;
16686 else if (is_cracked_insn (insn))
16687 cached_can_issue_more = more > 2 ? more - 2 : 0;
16689 cached_can_issue_more = more - 1;
16691 return cached_can_issue_more;
16694 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
16697 cached_can_issue_more = more - 1;
16698 return cached_can_issue_more;
16701 /* Adjust the cost of a scheduling dependency. Return the new cost of
16702 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16705 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16707 enum attr_type attr_type;
16709 if (! recog_memoized (insn))
16712 switch (REG_NOTE_KIND (link))
16716 /* Data dependency; DEP_INSN writes a register that INSN reads
16717 some cycles later. */
16719 /* Separate a load from a narrower, dependent store. */
16720 if (rs6000_sched_groups
16721 && GET_CODE (PATTERN (insn)) == SET
16722 && GET_CODE (PATTERN (dep_insn)) == SET
16723 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16724 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16725 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16726 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16729 attr_type = get_attr_type (insn);
16734 /* Tell the first scheduling pass about the latency between
16735 a mtctr and bctr (and mtlr and br/blr). The first
16736 scheduling pass will not know about this latency since
16737 the mtctr instruction, which has the latency associated
16738 to it, will be generated by reload. */
16739 return TARGET_POWER ? 5 : 4;
16741 /* Leave some extra cycles between a compare and its
16742 dependent branch, to inhibit expensive mispredicts. */
16743 if ((rs6000_cpu_attr == CPU_PPC603
16744 || rs6000_cpu_attr == CPU_PPC604
16745 || rs6000_cpu_attr == CPU_PPC604E
16746 || rs6000_cpu_attr == CPU_PPC620
16747 || rs6000_cpu_attr == CPU_PPC630
16748 || rs6000_cpu_attr == CPU_PPC750
16749 || rs6000_cpu_attr == CPU_PPC7400
16750 || rs6000_cpu_attr == CPU_PPC7450
16751 || rs6000_cpu_attr == CPU_POWER4
16752 || rs6000_cpu_attr == CPU_POWER5
16753 || rs6000_cpu_attr == CPU_CELL)
16754 && recog_memoized (dep_insn)
16755 && (INSN_CODE (dep_insn) >= 0))
16757 switch (get_attr_type (dep_insn))
16761 case TYPE_DELAYED_COMPARE:
16762 case TYPE_IMUL_COMPARE:
16763 case TYPE_LMUL_COMPARE:
16764 case TYPE_FPCOMPARE:
16765 case TYPE_CR_LOGICAL:
16766 case TYPE_DELAYED_CR:
16775 case TYPE_STORE_UX:
16777 case TYPE_FPSTORE_U:
16778 case TYPE_FPSTORE_UX:
16779 if ((rs6000_cpu == PROCESSOR_POWER6)
16780 && recog_memoized (dep_insn)
16781 && (INSN_CODE (dep_insn) >= 0))
16784 if (GET_CODE (PATTERN (insn)) != SET)
16785 /* If this happens, we have to extend this to schedule
16786 optimally. Return default for now. */
16789 /* Adjust the cost for the case where the value written
16790 by a fixed point operation is used as the address
16791 gen value on a store. */
16792 switch (get_attr_type (dep_insn))
16799 if (! store_data_bypass_p (dep_insn, insn))
16803 case TYPE_LOAD_EXT:
16804 case TYPE_LOAD_EXT_U:
16805 case TYPE_LOAD_EXT_UX:
16806 case TYPE_VAR_SHIFT_ROTATE:
16807 case TYPE_VAR_DELAYED_COMPARE:
16809 if (! store_data_bypass_p (dep_insn, insn))
16815 case TYPE_FAST_COMPARE:
16818 case TYPE_INSERT_WORD:
16819 case TYPE_INSERT_DWORD:
16820 case TYPE_FPLOAD_U:
16821 case TYPE_FPLOAD_UX:
16823 case TYPE_STORE_UX:
16824 case TYPE_FPSTORE_U:
16825 case TYPE_FPSTORE_UX:
16827 if (! store_data_bypass_p (dep_insn, insn))
16835 case TYPE_IMUL_COMPARE:
16836 case TYPE_LMUL_COMPARE:
16838 if (! store_data_bypass_p (dep_insn, insn))
16844 if (! store_data_bypass_p (dep_insn, insn))
16850 if (! store_data_bypass_p (dep_insn, insn))
16863 case TYPE_LOAD_EXT:
16864 case TYPE_LOAD_EXT_U:
16865 case TYPE_LOAD_EXT_UX:
16866 if ((rs6000_cpu == PROCESSOR_POWER6)
16867 && recog_memoized (dep_insn)
16868 && (INSN_CODE (dep_insn) >= 0))
16871 /* Adjust the cost for the case where the value written
16872 by a fixed point instruction is used within the address
16873 gen portion of a subsequent load(u)(x) */
16874 switch (get_attr_type (dep_insn))
16881 if (set_to_load_agen (dep_insn, insn))
16885 case TYPE_LOAD_EXT:
16886 case TYPE_LOAD_EXT_U:
16887 case TYPE_LOAD_EXT_UX:
16888 case TYPE_VAR_SHIFT_ROTATE:
16889 case TYPE_VAR_DELAYED_COMPARE:
16891 if (set_to_load_agen (dep_insn, insn))
16897 case TYPE_FAST_COMPARE:
16900 case TYPE_INSERT_WORD:
16901 case TYPE_INSERT_DWORD:
16902 case TYPE_FPLOAD_U:
16903 case TYPE_FPLOAD_UX:
16905 case TYPE_STORE_UX:
16906 case TYPE_FPSTORE_U:
16907 case TYPE_FPSTORE_UX:
16909 if (set_to_load_agen (dep_insn, insn))
16917 case TYPE_IMUL_COMPARE:
16918 case TYPE_LMUL_COMPARE:
16920 if (set_to_load_agen (dep_insn, insn))
16926 if (set_to_load_agen (dep_insn, insn))
16932 if (set_to_load_agen (dep_insn, insn))
16943 if ((rs6000_cpu == PROCESSOR_POWER6)
16944 && recog_memoized (dep_insn)
16945 && (INSN_CODE (dep_insn) >= 0)
16946 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
16953 /* Fall out to return default cost. */
16957 case REG_DEP_OUTPUT:
16958 /* Output dependency; DEP_INSN writes a register that INSN writes some
16960 if ((rs6000_cpu == PROCESSOR_POWER6)
16961 && recog_memoized (dep_insn)
16962 && (INSN_CODE (dep_insn) >= 0))
16964 attr_type = get_attr_type (insn);
16969 if (get_attr_type (dep_insn) == TYPE_FP)
16973 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
16981 /* Anti dependency; DEP_INSN reads a register that INSN writes some
16986 gcc_unreachable ();
16992 /* The function returns a true if INSN is microcoded.
16993 Return false otherwise. */
16996 is_microcoded_insn (rtx insn)
16998 if (!insn || !INSN_P (insn)
16999 || GET_CODE (PATTERN (insn)) == USE
17000 || GET_CODE (PATTERN (insn)) == CLOBBER)
17003 if (rs6000_cpu_attr == CPU_CELL)
17004 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17006 if (rs6000_sched_groups)
17008 enum attr_type type = get_attr_type (insn);
17009 if (type == TYPE_LOAD_EXT_U
17010 || type == TYPE_LOAD_EXT_UX
17011 || type == TYPE_LOAD_UX
17012 || type == TYPE_STORE_UX
17013 || type == TYPE_MFCR)
17020 /* The function returns true if INSN is cracked into 2 instructions
17021 by the processor (and therefore occupies 2 issue slots). */
17024 is_cracked_insn (rtx insn)
17026 if (!insn || !INSN_P (insn)
17027 || GET_CODE (PATTERN (insn)) == USE
17028 || GET_CODE (PATTERN (insn)) == CLOBBER)
17031 if (rs6000_sched_groups)
17033 enum attr_type type = get_attr_type (insn);
17034 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17035 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17036 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17037 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17038 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17039 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17040 || type == TYPE_IDIV || type == TYPE_LDIV
17041 || type == TYPE_INSERT_WORD)
17048 /* The function returns true if INSN can be issued only from
17049 the branch slot. */
17052 is_branch_slot_insn (rtx insn)
17054 if (!insn || !INSN_P (insn)
17055 || GET_CODE (PATTERN (insn)) == USE
17056 || GET_CODE (PATTERN (insn)) == CLOBBER)
17059 if (rs6000_sched_groups)
17061 enum attr_type type = get_attr_type (insn);
17062 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17070 /* The function returns true if out_inst sets a value that is
17071 used in the address generation computation of in_insn */
17073 set_to_load_agen (rtx out_insn, rtx in_insn)
17075 rtx out_set, in_set;
17077 /* For performance reasons, only handle the simple case where
17078 both loads are a single_set. */
17079 out_set = single_set (out_insn);
17082 in_set = single_set (in_insn);
17084 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17090 /* The function returns true if the target storage location of
17091 out_insn is adjacent to the target storage location of in_insn */
17092 /* Return 1 if memory locations are adjacent. */
17095 adjacent_mem_locations (rtx insn1, rtx insn2)
17098 rtx a = get_store_dest (PATTERN (insn1));
17099 rtx b = get_store_dest (PATTERN (insn2));
17101 if ((GET_CODE (XEXP (a, 0)) == REG
17102 || (GET_CODE (XEXP (a, 0)) == PLUS
17103 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17104 && (GET_CODE (XEXP (b, 0)) == REG
17105 || (GET_CODE (XEXP (b, 0)) == PLUS
17106 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17108 HOST_WIDE_INT val0 = 0, val1 = 0;
17112 if (GET_CODE (XEXP (a, 0)) == PLUS)
17114 reg0 = XEXP (XEXP (a, 0), 0);
17115 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17118 reg0 = XEXP (a, 0);
17120 if (GET_CODE (XEXP (b, 0)) == PLUS)
17122 reg1 = XEXP (XEXP (b, 0), 0);
17123 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17126 reg1 = XEXP (b, 0);
17128 val_diff = val1 - val0;
17130 return ((REGNO (reg0) == REGNO (reg1))
17131 && (val_diff == INTVAL (MEM_SIZE (a))
17132 || val_diff == -INTVAL (MEM_SIZE (b))));
17138 /* A C statement (sans semicolon) to update the integer scheduling
17139 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17140 INSN earlier, reduce the priority to execute INSN later. Do not
17141 define this macro if you do not need to adjust the scheduling
17142 priorities of insns. */
17145 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17147 /* On machines (like the 750) which have asymmetric integer units,
17148 where one integer unit can do multiply and divides and the other
17149 can't, reduce the priority of multiply/divide so it is scheduled
17150 before other integer operations. */
17153 if (! INSN_P (insn))
17156 if (GET_CODE (PATTERN (insn)) == USE)
17159 switch (rs6000_cpu_attr) {
17161 switch (get_attr_type (insn))
17168 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17169 priority, priority);
17170 if (priority >= 0 && priority < 0x01000000)
17177 if (insn_must_be_first_in_group (insn)
17178 && reload_completed
17179 && current_sched_info->sched_max_insns_priority
17180 && rs6000_sched_restricted_insns_priority)
17183 /* Prioritize insns that can be dispatched only in the first
17185 if (rs6000_sched_restricted_insns_priority == 1)
17186 /* Attach highest priority to insn. This means that in
17187 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17188 precede 'priority' (critical path) considerations. */
17189 return current_sched_info->sched_max_insns_priority;
17190 else if (rs6000_sched_restricted_insns_priority == 2)
17191 /* Increase priority of insn by a minimal amount. This means that in
17192 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17193 considerations precede dispatch-slot restriction considerations. */
17194 return (priority + 1);
17197 if (rs6000_cpu == PROCESSOR_POWER6
17198 && ((load_store_pendulum == -2 && is_load_insn (insn))
17199 || (load_store_pendulum == 2 && is_store_insn (insn))))
17200 /* Attach highest priority to insn if the scheduler has just issued two
17201 stores and this instruction is a load, or two loads and this instruction
17202 is a store. Power6 wants loads and stores scheduled alternately
17204 return current_sched_info->sched_max_insns_priority;
17209 /* Return true if the instruction is nonpipelined on the Cell. */
17211 is_nonpipeline_insn (rtx insn)
17213 enum attr_type type;
17214 if (!insn || !INSN_P (insn)
17215 || GET_CODE (PATTERN (insn)) == USE
17216 || GET_CODE (PATTERN (insn)) == CLOBBER)
17219 type = get_attr_type (insn);
17220 if (type == TYPE_IMUL
17221 || type == TYPE_IMUL2
17222 || type == TYPE_IMUL3
17223 || type == TYPE_LMUL
17224 || type == TYPE_IDIV
17225 || type == TYPE_LDIV
17226 || type == TYPE_SDIV
17227 || type == TYPE_DDIV
17228 || type == TYPE_SSQRT
17229 || type == TYPE_DSQRT
17230 || type == TYPE_MFCR
17231 || type == TYPE_MFCRF
17232 || type == TYPE_MFJMPR)
17240 /* Return how many instructions the machine can issue per cycle. */
17243 rs6000_issue_rate (void)
17245 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17246 if (!reload_completed)
17249 switch (rs6000_cpu_attr) {
17250 case CPU_RIOS1: /* ? */
17252 case CPU_PPC601: /* ? */
17277 /* Return how many instructions to look ahead for better insn
17281 rs6000_use_sched_lookahead (void)
17283 if (rs6000_cpu_attr == CPU_PPC8540)
17285 if (rs6000_cpu_attr == CPU_CELL)
17286 return (reload_completed ? 8 : 0);
17290 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17292 rs6000_use_sched_lookahead_guard (rtx insn)
17294 if (rs6000_cpu_attr != CPU_CELL)
17297 if (insn == NULL_RTX || !INSN_P (insn))
17300 if (!reload_completed
17301 || is_nonpipeline_insn (insn)
17302 || is_microcoded_insn (insn))
17308 /* Determine is PAT refers to memory. */
17311 is_mem_ref (rtx pat)
17317 if (GET_CODE (pat) == MEM)
17320 /* Recursively process the pattern. */
17321 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17323 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17326 ret |= is_mem_ref (XEXP (pat, i));
17327 else if (fmt[i] == 'E')
17328 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17329 ret |= is_mem_ref (XVECEXP (pat, i, j));
17335 /* Determine if PAT is a PATTERN of a load insn. */
17338 is_load_insn1 (rtx pat)
17340 if (!pat || pat == NULL_RTX)
17343 if (GET_CODE (pat) == SET)
17344 return is_mem_ref (SET_SRC (pat));
17346 if (GET_CODE (pat) == PARALLEL)
17350 for (i = 0; i < XVECLEN (pat, 0); i++)
17351 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17358 /* Determine if INSN loads from memory. */
17361 is_load_insn (rtx insn)
17363 if (!insn || !INSN_P (insn))
17366 if (GET_CODE (insn) == CALL_INSN)
17369 return is_load_insn1 (PATTERN (insn));
17372 /* Determine if PAT is a PATTERN of a store insn. */
17375 is_store_insn1 (rtx pat)
17377 if (!pat || pat == NULL_RTX)
17380 if (GET_CODE (pat) == SET)
17381 return is_mem_ref (SET_DEST (pat));
17383 if (GET_CODE (pat) == PARALLEL)
17387 for (i = 0; i < XVECLEN (pat, 0); i++)
17388 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17395 /* Determine if INSN stores to memory. */
17398 is_store_insn (rtx insn)
17400 if (!insn || !INSN_P (insn))
17403 return is_store_insn1 (PATTERN (insn));
17406 /* Return the dest of a store insn. */
17409 get_store_dest (rtx pat)
17411 gcc_assert (is_store_insn1 (pat));
17413 if (GET_CODE (pat) == SET)
17414 return SET_DEST (pat);
17415 else if (GET_CODE (pat) == PARALLEL)
17419 for (i = 0; i < XVECLEN (pat, 0); i++)
17421 rtx inner_pat = XVECEXP (pat, 0, i);
17422 if (GET_CODE (inner_pat) == SET
17423 && is_mem_ref (SET_DEST (inner_pat)))
17427 /* We shouldn't get here, because we should have either a simple
17428 store insn or a store with update which are covered above. */
17432 /* Returns whether the dependence between INSN and NEXT is considered
17433 costly by the given target. */
17436 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
17439 /* If the flag is not enabled - no dependence is considered costly;
17440 allow all dependent insns in the same group.
17441 This is the most aggressive option. */
17442 if (rs6000_sched_costly_dep == no_dep_costly)
17445 /* If the flag is set to 1 - a dependence is always considered costly;
17446 do not allow dependent instructions in the same group.
17447 This is the most conservative option. */
17448 if (rs6000_sched_costly_dep == all_deps_costly)
17451 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17452 && is_load_insn (next)
17453 && is_store_insn (insn))
17454 /* Prevent load after store in the same group. */
17457 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17458 && is_load_insn (next)
17459 && is_store_insn (insn)
17460 && (!link || (int) REG_NOTE_KIND (link) == 0))
17461 /* Prevent load after store in the same group if it is a true
17465 /* The flag is set to X; dependences with latency >= X are considered costly,
17466 and will not be scheduled in the same group. */
17467 if (rs6000_sched_costly_dep <= max_dep_latency
17468 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17474 /* Return the next insn after INSN that is found before TAIL is reached,
17475 skipping any "non-active" insns - insns that will not actually occupy
17476 an issue slot. Return NULL_RTX if such an insn is not found. */
17479 get_next_active_insn (rtx insn, rtx tail)
17481 if (insn == NULL_RTX || insn == tail)
17486 insn = NEXT_INSN (insn);
17487 if (insn == NULL_RTX || insn == tail)
17492 || (NONJUMP_INSN_P (insn)
17493 && GET_CODE (PATTERN (insn)) != USE
17494 && GET_CODE (PATTERN (insn)) != CLOBBER
17495 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17501 /* We are about to begin issuing insns for this clock cycle. */
17504 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17505 rtx *ready ATTRIBUTE_UNUSED,
17506 int *pn_ready ATTRIBUTE_UNUSED,
17507 int clock_var ATTRIBUTE_UNUSED)
17509 int n_ready = *pn_ready;
17512 fprintf (dump, "// rs6000_sched_reorder :\n");
17514 /* Reorder the ready list, if the second to last ready insn
17515 is a nonepipeline insn. */
17516 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17518 if (is_nonpipeline_insn (ready[n_ready - 1])
17519 && (recog_memoized (ready[n_ready - 2]) > 0))
17520 /* Simply swap first two insns. */
17522 rtx tmp = ready[n_ready - 1];
17523 ready[n_ready - 1] = ready[n_ready - 2];
17524 ready[n_ready - 2] = tmp;
17528 if (rs6000_cpu == PROCESSOR_POWER6)
17529 load_store_pendulum = 0;
17531 return rs6000_issue_rate ();
17534 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17537 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17538 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17541 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17543 /* For Power6, we need to handle some special cases to try and keep the
17544 store queue from overflowing and triggering expensive flushes.
17546 This code monitors how load and store instructions are being issued
17547 and skews the ready list one way or the other to increase the likelihood
17548 that a desired instruction is issued at the proper time.
17550 A couple of things are done. First, we maintain a "load_store_pendulum"
17551 to track the current state of load/store issue.
17553 - If the pendulum is at zero, then no loads or stores have been
17554 issued in the current cycle so we do nothing.
17556 - If the pendulum is 1, then a single load has been issued in this
17557 cycle and we attempt to locate another load in the ready list to
17560 - If the pendulum is -2, then two stores have already been
17561 issued in this cycle, so we increase the priority of the first load
17562 in the ready list to increase it's likelihood of being chosen first
17565 - If the pendulum is -1, then a single store has been issued in this
17566 cycle and we attempt to locate another store in the ready list to
17567 issue with it, preferring a store to an adjacent memory location to
17568 facilitate store pairing in the store queue.
17570 - If the pendulum is 2, then two loads have already been
17571 issued in this cycle, so we increase the priority of the first store
17572 in the ready list to increase it's likelihood of being chosen first
17575 - If the pendulum < -2 or > 2, then do nothing.
17577 Note: This code covers the most common scenarios. There exist non
17578 load/store instructions which make use of the LSU and which
17579 would need to be accounted for to strictly model the behavior
17580 of the machine. Those instructions are currently unaccounted
17581 for to help minimize compile time overhead of this code.
17583 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17589 if (is_store_insn (last_scheduled_insn))
17590 /* Issuing a store, swing the load_store_pendulum to the left */
17591 load_store_pendulum--;
17592 else if (is_load_insn (last_scheduled_insn))
17593 /* Issuing a load, swing the load_store_pendulum to the right */
17594 load_store_pendulum++;
17596 return cached_can_issue_more;
17598 /* If the pendulum is balanced, or there is only one instruction on
17599 the ready list, then all is well, so return. */
17600 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17601 return cached_can_issue_more;
17603 if (load_store_pendulum == 1)
17605 /* A load has been issued in this cycle. Scan the ready list
17606 for another load to issue with it */
17611 if (is_load_insn (ready[pos]))
17613 /* Found a load. Move it to the head of the ready list,
17614 and adjust it's priority so that it is more likely to
17617 for (i=pos; i<*pn_ready-1; i++)
17618 ready[i] = ready[i + 1];
17619 ready[*pn_ready-1] = tmp;
17620 if INSN_PRIORITY_KNOWN (tmp)
17621 INSN_PRIORITY (tmp)++;
17627 else if (load_store_pendulum == -2)
17629 /* Two stores have been issued in this cycle. Increase the
17630 priority of the first load in the ready list to favor it for
17631 issuing in the next cycle. */
17636 if (is_load_insn (ready[pos])
17637 && INSN_PRIORITY_KNOWN (ready[pos]))
17639 INSN_PRIORITY (ready[pos])++;
17641 /* Adjust the pendulum to account for the fact that a load
17642 was found and increased in priority. This is to prevent
17643 increasing the priority of multiple loads */
17644 load_store_pendulum--;
17651 else if (load_store_pendulum == -1)
17653 /* A store has been issued in this cycle. Scan the ready list for
17654 another store to issue with it, preferring a store to an adjacent
17656 int first_store_pos = -1;
17662 if (is_store_insn (ready[pos]))
17664 /* Maintain the index of the first store found on the
17666 if (first_store_pos == -1)
17667 first_store_pos = pos;
17669 if (is_store_insn (last_scheduled_insn)
17670 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
17672 /* Found an adjacent store. Move it to the head of the
17673 ready list, and adjust it's priority so that it is
17674 more likely to stay there */
17676 for (i=pos; i<*pn_ready-1; i++)
17677 ready[i] = ready[i + 1];
17678 ready[*pn_ready-1] = tmp;
17679 if INSN_PRIORITY_KNOWN (tmp)
17680 INSN_PRIORITY (tmp)++;
17681 first_store_pos = -1;
17689 if (first_store_pos >= 0)
17691 /* An adjacent store wasn't found, but a non-adjacent store was,
17692 so move the non-adjacent store to the front of the ready
17693 list, and adjust its priority so that it is more likely to
17695 tmp = ready[first_store_pos];
17696 for (i=first_store_pos; i<*pn_ready-1; i++)
17697 ready[i] = ready[i + 1];
17698 ready[*pn_ready-1] = tmp;
17699 if INSN_PRIORITY_KNOWN (tmp)
17700 INSN_PRIORITY (tmp)++;
17703 else if (load_store_pendulum == 2)
17705 /* Two loads have been issued in this cycle. Increase the priority
17706 of the first store in the ready list to favor it for issuing in
17712 if (is_store_insn (ready[pos])
17713 && INSN_PRIORITY_KNOWN (ready[pos]))
17715 INSN_PRIORITY (ready[pos])++;
17717 /* Adjust the pendulum to account for the fact that a store
17718 was found and increased in priority. This is to prevent
17719 increasing the priority of multiple stores */
17720 load_store_pendulum++;
17729 return cached_can_issue_more;
17732 /* Return whether the presence of INSN causes a dispatch group termination
17733 of group WHICH_GROUP.
17735 If WHICH_GROUP == current_group, this function will return true if INSN
17736 causes the termination of the current group (i.e, the dispatch group to
17737 which INSN belongs). This means that INSN will be the last insn in the
17738 group it belongs to.
17740 If WHICH_GROUP == previous_group, this function will return true if INSN
17741 causes the termination of the previous group (i.e, the dispatch group that
17742 precedes the group to which INSN belongs). This means that INSN will be
17743 the first insn in the group it belongs to). */
17746 insn_terminates_group_p (rtx insn, enum group_termination which_group)
17753 first = insn_must_be_first_in_group (insn);
17754 last = insn_must_be_last_in_group (insn);
17759 if (which_group == current_group)
17761 else if (which_group == previous_group)
17769 insn_must_be_first_in_group (rtx insn)
17771 enum attr_type type;
17774 || insn == NULL_RTX
17775 || GET_CODE (insn) == NOTE
17776 || GET_CODE (PATTERN (insn)) == USE
17777 || GET_CODE (PATTERN (insn)) == CLOBBER)
17780 switch (rs6000_cpu)
17782 case PROCESSOR_POWER5:
17783 if (is_cracked_insn (insn))
17785 case PROCESSOR_POWER4:
17786 if (is_microcoded_insn (insn))
17789 if (!rs6000_sched_groups)
17792 type = get_attr_type (insn);
17799 case TYPE_DELAYED_CR:
17800 case TYPE_CR_LOGICAL:
17814 case PROCESSOR_POWER6:
17815 type = get_attr_type (insn);
17819 case TYPE_INSERT_DWORD:
17823 case TYPE_VAR_SHIFT_ROTATE:
17830 case TYPE_INSERT_WORD:
17831 case TYPE_DELAYED_COMPARE:
17832 case TYPE_IMUL_COMPARE:
17833 case TYPE_LMUL_COMPARE:
17834 case TYPE_FPCOMPARE:
17845 case TYPE_LOAD_EXT_UX:
17847 case TYPE_STORE_UX:
17848 case TYPE_FPLOAD_U:
17849 case TYPE_FPLOAD_UX:
17850 case TYPE_FPSTORE_U:
17851 case TYPE_FPSTORE_UX:
17865 insn_must_be_last_in_group (rtx insn)
17867 enum attr_type type;
17870 || insn == NULL_RTX
17871 || GET_CODE (insn) == NOTE
17872 || GET_CODE (PATTERN (insn)) == USE
17873 || GET_CODE (PATTERN (insn)) == CLOBBER)
17876 switch (rs6000_cpu) {
17877 case PROCESSOR_POWER4:
17878 case PROCESSOR_POWER5:
17879 if (is_microcoded_insn (insn))
17882 if (is_branch_slot_insn (insn))
17886 case PROCESSOR_POWER6:
17887 type = get_attr_type (insn);
17894 case TYPE_VAR_SHIFT_ROTATE:
17901 case TYPE_DELAYED_COMPARE:
17902 case TYPE_IMUL_COMPARE:
17903 case TYPE_LMUL_COMPARE:
17904 case TYPE_FPCOMPARE:
17925 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
17926 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
17929 is_costly_group (rtx *group_insns, rtx next_insn)
17934 int issue_rate = rs6000_issue_rate ();
17936 for (i = 0; i < issue_rate; i++)
17938 rtx insn = group_insns[i];
17941 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
17943 rtx next = XEXP (link, 0);
17944 if (next == next_insn)
17946 cost = insn_cost (insn, link, next_insn);
17947 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
17956 /* Utility of the function redefine_groups.
17957 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
17958 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
17959 to keep it "far" (in a separate group) from GROUP_INSNS, following
17960 one of the following schemes, depending on the value of the flag
17961 -minsert_sched_nops = X:
17962 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
17963 in order to force NEXT_INSN into a separate group.
17964 (2) X < sched_finish_regroup_exact: insert exactly X nops.
17965 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
17966 insertion (has a group just ended, how many vacant issue slots remain in the
17967 last group, and how many dispatch groups were encountered so far). */
17970 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
17971 rtx next_insn, bool *group_end, int can_issue_more,
17976 int issue_rate = rs6000_issue_rate ();
17977 bool end = *group_end;
17980 if (next_insn == NULL_RTX)
17981 return can_issue_more;
17983 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
17984 return can_issue_more;
17986 force = is_costly_group (group_insns, next_insn);
17988 return can_issue_more;
17990 if (sched_verbose > 6)
17991 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
17992 *group_count ,can_issue_more);
17994 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
17997 can_issue_more = 0;
17999 /* Since only a branch can be issued in the last issue_slot, it is
18000 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18001 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18002 in this case the last nop will start a new group and the branch
18003 will be forced to the new group. */
18004 if (can_issue_more && !is_branch_slot_insn (next_insn))
18007 while (can_issue_more > 0)
18010 emit_insn_before (nop, next_insn);
18018 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18020 int n_nops = rs6000_sched_insert_nops;
18022 /* Nops can't be issued from the branch slot, so the effective
18023 issue_rate for nops is 'issue_rate - 1'. */
18024 if (can_issue_more == 0)
18025 can_issue_more = issue_rate;
18027 if (can_issue_more == 0)
18029 can_issue_more = issue_rate - 1;
18032 for (i = 0; i < issue_rate; i++)
18034 group_insns[i] = 0;
18041 emit_insn_before (nop, next_insn);
18042 if (can_issue_more == issue_rate - 1) /* new group begins */
18045 if (can_issue_more == 0)
18047 can_issue_more = issue_rate - 1;
18050 for (i = 0; i < issue_rate; i++)
18052 group_insns[i] = 0;
18058 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18061 /* Is next_insn going to start a new group? */
18064 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18065 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18066 || (can_issue_more < issue_rate &&
18067 insn_terminates_group_p (next_insn, previous_group)));
18068 if (*group_end && end)
18071 if (sched_verbose > 6)
18072 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18073 *group_count, can_issue_more);
18074 return can_issue_more;
18077 return can_issue_more;
18080 /* This function tries to synch the dispatch groups that the compiler "sees"
18081 with the dispatch groups that the processor dispatcher is expected to
18082 form in practice. It tries to achieve this synchronization by forcing the
18083 estimated processor grouping on the compiler (as opposed to the function
18084 'pad_goups' which tries to force the scheduler's grouping on the processor).
18086 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18087 examines the (estimated) dispatch groups that will be formed by the processor
18088 dispatcher. It marks these group boundaries to reflect the estimated
18089 processor grouping, overriding the grouping that the scheduler had marked.
18090 Depending on the value of the flag '-minsert-sched-nops' this function can
18091 force certain insns into separate groups or force a certain distance between
18092 them by inserting nops, for example, if there exists a "costly dependence"
18095 The function estimates the group boundaries that the processor will form as
18096 follows: It keeps track of how many vacant issue slots are available after
18097 each insn. A subsequent insn will start a new group if one of the following
18099 - no more vacant issue slots remain in the current dispatch group.
18100 - only the last issue slot, which is the branch slot, is vacant, but the next
18101 insn is not a branch.
18102 - only the last 2 or less issue slots, including the branch slot, are vacant,
18103 which means that a cracked insn (which occupies two issue slots) can't be
18104 issued in this group.
18105 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18106 start a new group. */
18109 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18111 rtx insn, next_insn;
18113 int can_issue_more;
18116 int group_count = 0;
18120 issue_rate = rs6000_issue_rate ();
18121 group_insns = alloca (issue_rate * sizeof (rtx));
18122 for (i = 0; i < issue_rate; i++)
18124 group_insns[i] = 0;
18126 can_issue_more = issue_rate;
18128 insn = get_next_active_insn (prev_head_insn, tail);
18131 while (insn != NULL_RTX)
18133 slot = (issue_rate - can_issue_more);
18134 group_insns[slot] = insn;
18136 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18137 if (insn_terminates_group_p (insn, current_group))
18138 can_issue_more = 0;
18140 next_insn = get_next_active_insn (insn, tail);
18141 if (next_insn == NULL_RTX)
18142 return group_count + 1;
18144 /* Is next_insn going to start a new group? */
18146 = (can_issue_more == 0
18147 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18148 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18149 || (can_issue_more < issue_rate &&
18150 insn_terminates_group_p (next_insn, previous_group)));
18152 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18153 next_insn, &group_end, can_issue_more,
18159 can_issue_more = 0;
18160 for (i = 0; i < issue_rate; i++)
18162 group_insns[i] = 0;
18166 if (GET_MODE (next_insn) == TImode && can_issue_more)
18167 PUT_MODE (next_insn, VOIDmode);
18168 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18169 PUT_MODE (next_insn, TImode);
18172 if (can_issue_more == 0)
18173 can_issue_more = issue_rate;
18176 return group_count;
18179 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18180 dispatch group boundaries that the scheduler had marked. Pad with nops
18181 any dispatch groups which have vacant issue slots, in order to force the
18182 scheduler's grouping on the processor dispatcher. The function
18183 returns the number of dispatch groups found. */
18186 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18188 rtx insn, next_insn;
18191 int can_issue_more;
18193 int group_count = 0;
18195 /* Initialize issue_rate. */
18196 issue_rate = rs6000_issue_rate ();
18197 can_issue_more = issue_rate;
18199 insn = get_next_active_insn (prev_head_insn, tail);
18200 next_insn = get_next_active_insn (insn, tail);
18202 while (insn != NULL_RTX)
18205 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18207 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18209 if (next_insn == NULL_RTX)
18214 /* If the scheduler had marked group termination at this location
18215 (between insn and next_indn), and neither insn nor next_insn will
18216 force group termination, pad the group with nops to force group
18219 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18220 && !insn_terminates_group_p (insn, current_group)
18221 && !insn_terminates_group_p (next_insn, previous_group))
18223 if (!is_branch_slot_insn (next_insn))
18226 while (can_issue_more)
18229 emit_insn_before (nop, next_insn);
18234 can_issue_more = issue_rate;
18239 next_insn = get_next_active_insn (insn, tail);
18242 return group_count;
18245 /* We're beginning a new block. Initialize data structures as necessary. */
18248 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18249 int sched_verbose ATTRIBUTE_UNUSED,
18250 int max_ready ATTRIBUTE_UNUSED)
18252 last_scheduled_insn = NULL_RTX;
18253 load_store_pendulum = 0;
18256 /* The following function is called at the end of scheduling BB.
18257 After reload, it inserts nops at insn group bundling. */
18260 rs6000_sched_finish (FILE *dump, int sched_verbose)
18265 fprintf (dump, "=== Finishing schedule.\n");
18267 if (reload_completed && rs6000_sched_groups)
18269 if (rs6000_sched_insert_nops == sched_finish_none)
18272 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18273 n_groups = pad_groups (dump, sched_verbose,
18274 current_sched_info->prev_head,
18275 current_sched_info->next_tail);
18277 n_groups = redefine_groups (dump, sched_verbose,
18278 current_sched_info->prev_head,
18279 current_sched_info->next_tail);
18281 if (sched_verbose >= 6)
18283 fprintf (dump, "ngroups = %d\n", n_groups);
18284 print_rtl (dump, current_sched_info->prev_head);
18285 fprintf (dump, "Done finish_sched\n");
18290 /* Length in units of the trampoline for entering a nested function. */
18293 rs6000_trampoline_size (void)
18297 switch (DEFAULT_ABI)
18300 gcc_unreachable ();
18303 ret = (TARGET_32BIT) ? 12 : 24;
18308 ret = (TARGET_32BIT) ? 40 : 48;
18315 /* Emit RTL insns to initialize the variable parts of a trampoline.
18316 FNADDR is an RTX for the address of the function's pure code.
18317 CXT is an RTX for the static chain value for the function. */
18320 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18322 int regsize = (TARGET_32BIT) ? 4 : 8;
18323 rtx ctx_reg = force_reg (Pmode, cxt);
18325 switch (DEFAULT_ABI)
18328 gcc_unreachable ();
18330 /* Macros to shorten the code expansions below. */
18331 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18332 #define MEM_PLUS(addr,offset) \
18333 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18335 /* Under AIX, just build the 3 word function descriptor */
18338 rtx fn_reg = gen_reg_rtx (Pmode);
18339 rtx toc_reg = gen_reg_rtx (Pmode);
18340 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18341 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18342 emit_move_insn (MEM_DEREF (addr), fn_reg);
18343 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18344 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18348 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18351 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18352 FALSE, VOIDmode, 4,
18354 GEN_INT (rs6000_trampoline_size ()), SImode,
18364 /* Table of valid machine attributes. */
18366 const struct attribute_spec rs6000_attribute_table[] =
18368 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18369 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18370 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18371 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18372 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18373 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18374 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18375 SUBTARGET_ATTRIBUTE_TABLE,
18377 { NULL, 0, 0, false, false, false, NULL }
18380 /* Handle the "altivec" attribute. The attribute may have
18381 arguments as follows:
18383 __attribute__((altivec(vector__)))
18384 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18385 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18387 and may appear more than once (e.g., 'vector bool char') in a
18388 given declaration. */
18391 rs6000_handle_altivec_attribute (tree *node,
18392 tree name ATTRIBUTE_UNUSED,
18394 int flags ATTRIBUTE_UNUSED,
18395 bool *no_add_attrs)
18397 tree type = *node, result = NULL_TREE;
18398 enum machine_mode mode;
18401 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18402 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18403 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18406 while (POINTER_TYPE_P (type)
18407 || TREE_CODE (type) == FUNCTION_TYPE
18408 || TREE_CODE (type) == METHOD_TYPE
18409 || TREE_CODE (type) == ARRAY_TYPE)
18410 type = TREE_TYPE (type);
18412 mode = TYPE_MODE (type);
18414 /* Check for invalid AltiVec type qualifiers. */
18415 if (type == long_unsigned_type_node || type == long_integer_type_node)
18418 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18419 else if (rs6000_warn_altivec_long)
18420 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18422 else if (type == long_long_unsigned_type_node
18423 || type == long_long_integer_type_node)
18424 error ("use of %<long long%> in AltiVec types is invalid");
18425 else if (type == double_type_node)
18426 error ("use of %<double%> in AltiVec types is invalid");
18427 else if (type == long_double_type_node)
18428 error ("use of %<long double%> in AltiVec types is invalid");
18429 else if (type == boolean_type_node)
18430 error ("use of boolean types in AltiVec types is invalid");
18431 else if (TREE_CODE (type) == COMPLEX_TYPE)
18432 error ("use of %<complex%> in AltiVec types is invalid");
18433 else if (DECIMAL_FLOAT_MODE_P (mode))
18434 error ("use of decimal floating point types in AltiVec types is invalid");
18436 switch (altivec_type)
18439 unsigned_p = TYPE_UNSIGNED (type);
18443 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18446 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18449 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18451 case SFmode: result = V4SF_type_node; break;
18452 /* If the user says 'vector int bool', we may be handed the 'bool'
18453 attribute _before_ the 'vector' attribute, and so select the
18454 proper type in the 'b' case below. */
18455 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18463 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18464 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18465 case QImode: case V16QImode: result = bool_V16QI_type_node;
18472 case V8HImode: result = pixel_V8HI_type_node;
18478 if (result && result != type && TYPE_READONLY (type))
18479 result = build_qualified_type (result, TYPE_QUAL_CONST);
18481 *no_add_attrs = true; /* No need to hang on to the attribute. */
18484 *node = reconstruct_complex_type (*node, result);
18489 /* AltiVec defines four built-in scalar types that serve as vector
18490 elements; we must teach the compiler how to mangle them. */
18492 static const char *
18493 rs6000_mangle_fundamental_type (tree type)
18495 if (type == bool_char_type_node) return "U6__boolc";
18496 if (type == bool_short_type_node) return "U6__bools";
18497 if (type == pixel_type_node) return "u7__pixel";
18498 if (type == bool_int_type_node) return "U6__booli";
18500 /* Mangle IBM extended float long double as `g' (__float128) on
18501 powerpc*-linux where long-double-64 previously was the default. */
18502 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18504 && TARGET_LONG_DOUBLE_128
18505 && !TARGET_IEEEQUAD)
18508 /* For all other types, use normal C++ mangling. */
18512 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18513 struct attribute_spec.handler. */
18516 rs6000_handle_longcall_attribute (tree *node, tree name,
18517 tree args ATTRIBUTE_UNUSED,
18518 int flags ATTRIBUTE_UNUSED,
18519 bool *no_add_attrs)
18521 if (TREE_CODE (*node) != FUNCTION_TYPE
18522 && TREE_CODE (*node) != FIELD_DECL
18523 && TREE_CODE (*node) != TYPE_DECL)
18525 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18526 IDENTIFIER_POINTER (name));
18527 *no_add_attrs = true;
18533 /* Set longcall attributes on all functions declared when
18534 rs6000_default_long_calls is true. */
18536 rs6000_set_default_type_attributes (tree type)
18538 if (rs6000_default_long_calls
18539 && (TREE_CODE (type) == FUNCTION_TYPE
18540 || TREE_CODE (type) == METHOD_TYPE))
18541 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18543 TYPE_ATTRIBUTES (type));
18546 darwin_set_default_type_attributes (type);
18550 /* Return a reference suitable for calling a function with the
18551 longcall attribute. */
18554 rs6000_longcall_ref (rtx call_ref)
18556 const char *call_name;
18559 if (GET_CODE (call_ref) != SYMBOL_REF)
18562 /* System V adds '.' to the internal name, so skip them. */
18563 call_name = XSTR (call_ref, 0);
18564 if (*call_name == '.')
18566 while (*call_name == '.')
18569 node = get_identifier (call_name);
18570 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18573 return force_reg (Pmode, call_ref);
18576 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18577 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18580 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18581 struct attribute_spec.handler. */
18583 rs6000_handle_struct_attribute (tree *node, tree name,
18584 tree args ATTRIBUTE_UNUSED,
18585 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18588 if (DECL_P (*node))
18590 if (TREE_CODE (*node) == TYPE_DECL)
18591 type = &TREE_TYPE (*node);
18596 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18597 || TREE_CODE (*type) == UNION_TYPE)))
18599 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18600 *no_add_attrs = true;
18603 else if ((is_attribute_p ("ms_struct", name)
18604 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18605 || ((is_attribute_p ("gcc_struct", name)
18606 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
18608 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
18609 IDENTIFIER_POINTER (name));
18610 *no_add_attrs = true;
18617 rs6000_ms_bitfield_layout_p (tree record_type)
18619 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
18620 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
18621 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
18624 #ifdef USING_ELFOS_H
18626 /* A get_unnamed_section callback, used for switching to toc_section. */
18629 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
18631 if (DEFAULT_ABI == ABI_AIX
18632 && TARGET_MINIMAL_TOC
18633 && !TARGET_RELOCATABLE)
18635 if (!toc_initialized)
18637 toc_initialized = 1;
18638 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18639 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
18640 fprintf (asm_out_file, "\t.tc ");
18641 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
18642 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18643 fprintf (asm_out_file, "\n");
18645 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18646 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18647 fprintf (asm_out_file, " = .+32768\n");
18650 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18652 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
18653 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
18656 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18657 if (!toc_initialized)
18659 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
18660 fprintf (asm_out_file, " = .+32768\n");
18661 toc_initialized = 1;
18666 /* Implement TARGET_ASM_INIT_SECTIONS. */
18669 rs6000_elf_asm_init_sections (void)
18672 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
18675 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
18676 SDATA2_SECTION_ASM_OP);
18679 /* Implement TARGET_SELECT_RTX_SECTION. */
18682 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
18683 unsigned HOST_WIDE_INT align)
18685 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18686 return toc_section;
18688 return default_elf_select_rtx_section (mode, x, align);
18691 /* Implement TARGET_ASM_SELECT_SECTION for ELF targets. */
18694 rs6000_elf_select_section (tree decl, int reloc,
18695 unsigned HOST_WIDE_INT align)
18697 /* Pretend that we're always building for a shared library when
18698 ABI_AIX, because otherwise we end up with dynamic relocations
18699 in read-only sections. This happens for function pointers,
18700 references to vtables in typeinfo, and probably other cases. */
18701 return default_elf_select_section_1 (decl, reloc, align,
18702 flag_pic || DEFAULT_ABI == ABI_AIX);
18705 /* A C statement to build up a unique section name, expressed as a
18706 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
18707 RELOC indicates whether the initial value of EXP requires
18708 link-time relocations. If you do not define this macro, GCC will use
18709 the symbol name prefixed by `.' as the section name. Note - this
18710 macro can now be called for uninitialized data items as well as
18711 initialized data and functions. */
18714 rs6000_elf_unique_section (tree decl, int reloc)
18716 /* As above, pretend that we're always building for a shared library
18717 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
18718 default_unique_section_1 (decl, reloc,
18719 flag_pic || DEFAULT_ABI == ABI_AIX);
18722 /* For a SYMBOL_REF, set generic flags and then perform some
18723 target-specific processing.
18725 When the AIX ABI is requested on a non-AIX system, replace the
18726 function name with the real name (with a leading .) rather than the
18727 function descriptor name. This saves a lot of overriding code to
18728 read the prefixes. */
18731 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
18733 default_encode_section_info (decl, rtl, first);
18736 && TREE_CODE (decl) == FUNCTION_DECL
18738 && DEFAULT_ABI == ABI_AIX)
18740 rtx sym_ref = XEXP (rtl, 0);
18741 size_t len = strlen (XSTR (sym_ref, 0));
18742 char *str = alloca (len + 2);
18744 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
18745 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
18750 rs6000_elf_in_small_data_p (tree decl)
18752 if (rs6000_sdata == SDATA_NONE)
18755 /* We want to merge strings, so we never consider them small data. */
18756 if (TREE_CODE (decl) == STRING_CST)
18759 /* Functions are never in the small data area. */
18760 if (TREE_CODE (decl) == FUNCTION_DECL)
18763 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
18765 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
18766 if (strcmp (section, ".sdata") == 0
18767 || strcmp (section, ".sdata2") == 0
18768 || strcmp (section, ".sbss") == 0
18769 || strcmp (section, ".sbss2") == 0
18770 || strcmp (section, ".PPC.EMB.sdata0") == 0
18771 || strcmp (section, ".PPC.EMB.sbss0") == 0)
18776 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
18779 && (unsigned HOST_WIDE_INT) size <= g_switch_value
18780 /* If it's not public, and we're not going to reference it there,
18781 there's no need to put it in the small data section. */
18782 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
18789 #endif /* USING_ELFOS_H */
18791 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
18794 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
18796 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
18799 /* Return a REG that occurs in ADDR with coefficient 1.
18800 ADDR can be effectively incremented by incrementing REG.
18802 r0 is special and we must not select it as an address
18803 register by this routine since our caller will try to
18804 increment the returned register via an "la" instruction. */
18807 find_addr_reg (rtx addr)
18809 while (GET_CODE (addr) == PLUS)
18811 if (GET_CODE (XEXP (addr, 0)) == REG
18812 && REGNO (XEXP (addr, 0)) != 0)
18813 addr = XEXP (addr, 0);
18814 else if (GET_CODE (XEXP (addr, 1)) == REG
18815 && REGNO (XEXP (addr, 1)) != 0)
18816 addr = XEXP (addr, 1);
18817 else if (CONSTANT_P (XEXP (addr, 0)))
18818 addr = XEXP (addr, 1);
18819 else if (CONSTANT_P (XEXP (addr, 1)))
18820 addr = XEXP (addr, 0);
18822 gcc_unreachable ();
18824 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
18829 rs6000_fatal_bad_address (rtx op)
18831 fatal_insn ("bad address", op);
18836 static tree branch_island_list = 0;
18838 /* Remember to generate a branch island for far calls to the given
18842 add_compiler_branch_island (tree label_name, tree function_name,
18845 tree branch_island = build_tree_list (function_name, label_name);
18846 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
18847 TREE_CHAIN (branch_island) = branch_island_list;
18848 branch_island_list = branch_island;
18851 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
18852 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
18853 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
18854 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
18856 /* Generate far-jump branch islands for everything on the
18857 branch_island_list. Invoked immediately after the last instruction
18858 of the epilogue has been emitted; the branch-islands must be
18859 appended to, and contiguous with, the function body. Mach-O stubs
18860 are generated in machopic_output_stub(). */
18863 macho_branch_islands (void)
18866 tree branch_island;
18868 for (branch_island = branch_island_list;
18870 branch_island = TREE_CHAIN (branch_island))
18872 const char *label =
18873 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
18875 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
18876 char name_buf[512];
18877 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
18878 if (name[0] == '*' || name[0] == '&')
18879 strcpy (name_buf, name+1);
18883 strcpy (name_buf+1, name);
18885 strcpy (tmp_buf, "\n");
18886 strcat (tmp_buf, label);
18887 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
18888 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
18889 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
18890 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
18893 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
18894 strcat (tmp_buf, label);
18895 strcat (tmp_buf, "_pic\n");
18896 strcat (tmp_buf, label);
18897 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
18899 strcat (tmp_buf, "\taddis r11,r11,ha16(");
18900 strcat (tmp_buf, name_buf);
18901 strcat (tmp_buf, " - ");
18902 strcat (tmp_buf, label);
18903 strcat (tmp_buf, "_pic)\n");
18905 strcat (tmp_buf, "\tmtlr r0\n");
18907 strcat (tmp_buf, "\taddi r12,r11,lo16(");
18908 strcat (tmp_buf, name_buf);
18909 strcat (tmp_buf, " - ");
18910 strcat (tmp_buf, label);
18911 strcat (tmp_buf, "_pic)\n");
18913 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
18917 strcat (tmp_buf, ":\nlis r12,hi16(");
18918 strcat (tmp_buf, name_buf);
18919 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
18920 strcat (tmp_buf, name_buf);
18921 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
18923 output_asm_insn (tmp_buf, 0);
18924 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
18925 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
18926 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
18927 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
18930 branch_island_list = 0;
18933 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
18934 already there or not. */
18937 no_previous_def (tree function_name)
18939 tree branch_island;
18940 for (branch_island = branch_island_list;
18942 branch_island = TREE_CHAIN (branch_island))
18943 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
18948 /* GET_PREV_LABEL gets the label name from the previous definition of
18952 get_prev_label (tree function_name)
18954 tree branch_island;
18955 for (branch_island = branch_island_list;
18957 branch_island = TREE_CHAIN (branch_island))
18958 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
18959 return BRANCH_ISLAND_LABEL_NAME (branch_island);
18963 /* INSN is either a function call or a millicode call. It may have an
18964 unconditional jump in its delay slot.
18966 CALL_DEST is the routine we are calling. */
18969 output_call (rtx insn, rtx *operands, int dest_operand_number,
18970 int cookie_operand_number)
18972 static char buf[256];
18973 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
18974 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
18977 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
18979 if (no_previous_def (funname))
18981 int line_number = 0;
18982 rtx label_rtx = gen_label_rtx ();
18983 char *label_buf, temp_buf[256];
18984 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
18985 CODE_LABEL_NUMBER (label_rtx));
18986 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
18987 labelname = get_identifier (label_buf);
18988 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
18990 line_number = NOTE_LINE_NUMBER (insn);
18991 add_compiler_branch_island (labelname, funname, line_number);
18994 labelname = get_prev_label (funname);
18996 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
18997 instruction will reach 'foo', otherwise link as 'bl L42'".
18998 "L42" should be a 'branch island', that will do a far jump to
18999 'foo'. Branch islands are generated in
19000 macho_branch_islands(). */
19001 sprintf (buf, "jbsr %%z%d,%.246s",
19002 dest_operand_number, IDENTIFIER_POINTER (labelname));
19005 sprintf (buf, "bl %%z%d", dest_operand_number);
19009 /* Generate PIC and indirect symbol stubs. */
19012 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19014 unsigned int length;
19015 char *symbol_name, *lazy_ptr_name;
19016 char *local_label_0;
19017 static int label = 0;
19019 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19020 symb = (*targetm.strip_name_encoding) (symb);
19023 length = strlen (symb);
19024 symbol_name = alloca (length + 32);
19025 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19027 lazy_ptr_name = alloca (length + 32);
19028 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19031 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19033 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19037 fprintf (file, "\t.align 5\n");
19039 fprintf (file, "%s:\n", stub);
19040 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19043 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19044 sprintf (local_label_0, "\"L%011d$spb\"", label);
19046 fprintf (file, "\tmflr r0\n");
19047 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19048 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19049 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19050 lazy_ptr_name, local_label_0);
19051 fprintf (file, "\tmtlr r0\n");
19052 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19053 (TARGET_64BIT ? "ldu" : "lwzu"),
19054 lazy_ptr_name, local_label_0);
19055 fprintf (file, "\tmtctr r12\n");
19056 fprintf (file, "\tbctr\n");
19060 fprintf (file, "\t.align 4\n");
19062 fprintf (file, "%s:\n", stub);
19063 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19065 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19066 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19067 (TARGET_64BIT ? "ldu" : "lwzu"),
19069 fprintf (file, "\tmtctr r12\n");
19070 fprintf (file, "\tbctr\n");
19073 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19074 fprintf (file, "%s:\n", lazy_ptr_name);
19075 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19076 fprintf (file, "%sdyld_stub_binding_helper\n",
19077 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19080 /* Legitimize PIC addresses. If the address is already
19081 position-independent, we return ORIG. Newly generated
19082 position-independent addresses go into a reg. This is REG if non
19083 zero, otherwise we allocate register(s) as necessary. */
19085 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19088 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19093 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19094 reg = gen_reg_rtx (Pmode);
19096 if (GET_CODE (orig) == CONST)
19100 if (GET_CODE (XEXP (orig, 0)) == PLUS
19101 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19104 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19106 /* Use a different reg for the intermediate value, as
19107 it will be marked UNCHANGING. */
19108 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
19109 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19112 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19115 if (GET_CODE (offset) == CONST_INT)
19117 if (SMALL_INT (offset))
19118 return plus_constant (base, INTVAL (offset));
19119 else if (! reload_in_progress && ! reload_completed)
19120 offset = force_reg (Pmode, offset);
19123 rtx mem = force_const_mem (Pmode, orig);
19124 return machopic_legitimize_pic_address (mem, Pmode, reg);
19127 return gen_rtx_PLUS (Pmode, base, offset);
19130 /* Fall back on generic machopic code. */
19131 return machopic_legitimize_pic_address (orig, mode, reg);
19134 /* Output a .machine directive for the Darwin assembler, and call
19135 the generic start_file routine. */
19138 rs6000_darwin_file_start (void)
19140 static const struct
19146 { "ppc64", "ppc64", MASK_64BIT },
19147 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19148 { "power4", "ppc970", 0 },
19149 { "G5", "ppc970", 0 },
19150 { "7450", "ppc7450", 0 },
19151 { "7400", "ppc7400", MASK_ALTIVEC },
19152 { "G4", "ppc7400", 0 },
19153 { "750", "ppc750", 0 },
19154 { "740", "ppc750", 0 },
19155 { "G3", "ppc750", 0 },
19156 { "604e", "ppc604e", 0 },
19157 { "604", "ppc604", 0 },
19158 { "603e", "ppc603", 0 },
19159 { "603", "ppc603", 0 },
19160 { "601", "ppc601", 0 },
19161 { NULL, "ppc", 0 } };
19162 const char *cpu_id = "";
19165 rs6000_file_start ();
19166 darwin_file_start ();
19168 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19169 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19170 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19171 && rs6000_select[i].string[0] != '\0')
19172 cpu_id = rs6000_select[i].string;
19174 /* Look through the mapping array. Pick the first name that either
19175 matches the argument, has a bit set in IF_SET that is also set
19176 in the target flags, or has a NULL name. */
19179 while (mapping[i].arg != NULL
19180 && strcmp (mapping[i].arg, cpu_id) != 0
19181 && (mapping[i].if_set & target_flags) == 0)
19184 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19187 #endif /* TARGET_MACHO */
19190 static unsigned int
19191 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
19193 return default_section_type_flags_1 (decl, name, reloc,
19194 flag_pic || DEFAULT_ABI == ABI_AIX);
19197 /* Record an element in the table of global constructors. SYMBOL is
19198 a SYMBOL_REF of the function to be called; PRIORITY is a number
19199 between 0 and MAX_INIT_PRIORITY.
19201 This differs from default_named_section_asm_out_constructor in
19202 that we have special handling for -mrelocatable. */
19205 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19207 const char *section = ".ctors";
19210 if (priority != DEFAULT_INIT_PRIORITY)
19212 sprintf (buf, ".ctors.%.5u",
19213 /* Invert the numbering so the linker puts us in the proper
19214 order; constructors are run from right to left, and the
19215 linker sorts in increasing order. */
19216 MAX_INIT_PRIORITY - priority);
19220 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19221 assemble_align (POINTER_SIZE);
19223 if (TARGET_RELOCATABLE)
19225 fputs ("\t.long (", asm_out_file);
19226 output_addr_const (asm_out_file, symbol);
19227 fputs (")@fixup\n", asm_out_file);
19230 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19234 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19236 const char *section = ".dtors";
19239 if (priority != DEFAULT_INIT_PRIORITY)
19241 sprintf (buf, ".dtors.%.5u",
19242 /* Invert the numbering so the linker puts us in the proper
19243 order; constructors are run from right to left, and the
19244 linker sorts in increasing order. */
19245 MAX_INIT_PRIORITY - priority);
19249 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19250 assemble_align (POINTER_SIZE);
19252 if (TARGET_RELOCATABLE)
19254 fputs ("\t.long (", asm_out_file);
19255 output_addr_const (asm_out_file, symbol);
19256 fputs (")@fixup\n", asm_out_file);
19259 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19263 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19267 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19268 ASM_OUTPUT_LABEL (file, name);
19269 fputs (DOUBLE_INT_ASM_OP, file);
19270 rs6000_output_function_entry (file, name);
19271 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19274 fputs ("\t.size\t", file);
19275 assemble_name (file, name);
19276 fputs (",24\n\t.type\t.", file);
19277 assemble_name (file, name);
19278 fputs (",@function\n", file);
19279 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19281 fputs ("\t.globl\t.", file);
19282 assemble_name (file, name);
19287 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19288 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19289 rs6000_output_function_entry (file, name);
19290 fputs (":\n", file);
19294 if (TARGET_RELOCATABLE
19295 && !TARGET_SECURE_PLT
19296 && (get_pool_size () != 0 || current_function_profile)
19301 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19303 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19304 fprintf (file, "\t.long ");
19305 assemble_name (file, buf);
19307 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19308 assemble_name (file, buf);
19312 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19313 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19315 if (DEFAULT_ABI == ABI_AIX)
19317 const char *desc_name, *orig_name;
19319 orig_name = (*targetm.strip_name_encoding) (name);
19320 desc_name = orig_name;
19321 while (*desc_name == '.')
19324 if (TREE_PUBLIC (decl))
19325 fprintf (file, "\t.globl %s\n", desc_name);
19327 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19328 fprintf (file, "%s:\n", desc_name);
19329 fprintf (file, "\t.long %s\n", orig_name);
19330 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19331 if (DEFAULT_ABI == ABI_AIX)
19332 fputs ("\t.long 0\n", file);
19333 fprintf (file, "\t.previous\n");
19335 ASM_OUTPUT_LABEL (file, name);
19339 rs6000_elf_end_indicate_exec_stack (void)
19342 file_end_indicate_exec_stack ();
19348 rs6000_xcoff_asm_output_anchor (rtx symbol)
19352 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19353 SYMBOL_REF_BLOCK_OFFSET (symbol));
19354 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19358 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19360 fputs (GLOBAL_ASM_OP, stream);
19361 RS6000_OUTPUT_BASENAME (stream, name);
19362 putc ('\n', stream);
19365 /* A get_unnamed_decl callback, used for read-only sections. PTR
19366 points to the section string variable. */
19369 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19371 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19372 *(const char *const *) directive);
19375 /* Likewise for read-write sections. */
19378 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19380 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19381 *(const char *const *) directive);
19384 /* A get_unnamed_section callback, used for switching to toc_section. */
19387 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19389 if (TARGET_MINIMAL_TOC)
19391 /* toc_section is always selected at least once from
19392 rs6000_xcoff_file_start, so this is guaranteed to
19393 always be defined once and only once in each file. */
19394 if (!toc_initialized)
19396 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19397 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19398 toc_initialized = 1;
19400 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19401 (TARGET_32BIT ? "" : ",3"));
19404 fputs ("\t.toc\n", asm_out_file);
19407 /* Implement TARGET_ASM_INIT_SECTIONS. */
19410 rs6000_xcoff_asm_init_sections (void)
19412 read_only_data_section
19413 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19414 &xcoff_read_only_section_name);
19416 private_data_section
19417 = get_unnamed_section (SECTION_WRITE,
19418 rs6000_xcoff_output_readwrite_section_asm_op,
19419 &xcoff_private_data_section_name);
19421 read_only_private_data_section
19422 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19423 &xcoff_private_data_section_name);
19426 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19428 readonly_data_section = read_only_data_section;
19429 exception_section = data_section;
19433 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19434 tree decl ATTRIBUTE_UNUSED)
19437 static const char * const suffix[3] = { "PR", "RO", "RW" };
19439 if (flags & SECTION_CODE)
19441 else if (flags & SECTION_WRITE)
19446 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19447 (flags & SECTION_CODE) ? "." : "",
19448 name, suffix[smclass], flags & SECTION_ENTSIZE);
19452 rs6000_xcoff_select_section (tree decl, int reloc,
19453 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19455 if (decl_readonly_section_1 (decl, reloc, 1))
19457 if (TREE_PUBLIC (decl))
19458 return read_only_data_section;
19460 return read_only_private_data_section;
19464 if (TREE_PUBLIC (decl))
19465 return data_section;
19467 return private_data_section;
19472 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19476 /* Use select_section for private and uninitialized data. */
19477 if (!TREE_PUBLIC (decl)
19478 || DECL_COMMON (decl)
19479 || DECL_INITIAL (decl) == NULL_TREE
19480 || DECL_INITIAL (decl) == error_mark_node
19481 || (flag_zero_initialized_in_bss
19482 && initializer_zerop (DECL_INITIAL (decl))))
19485 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19486 name = (*targetm.strip_name_encoding) (name);
19487 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19490 /* Select section for constant in constant pool.
19492 On RS/6000, all constants are in the private read-only data area.
19493 However, if this is being placed in the TOC it must be output as a
19497 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19498 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19500 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19501 return toc_section;
19503 return read_only_private_data_section;
19506 /* Remove any trailing [DS] or the like from the symbol name. */
19508 static const char *
19509 rs6000_xcoff_strip_name_encoding (const char *name)
19514 len = strlen (name);
19515 if (name[len - 1] == ']')
19516 return ggc_alloc_string (name, len - 4);
19521 /* Section attributes. AIX is always PIC. */
19523 static unsigned int
19524 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19526 unsigned int align;
19527 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
19529 /* Align to at least UNIT size. */
19530 if (flags & SECTION_CODE)
19531 align = MIN_UNITS_PER_WORD;
19533 /* Increase alignment of large objects if not already stricter. */
19534 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19535 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19536 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19538 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19541 /* Output at beginning of assembler file.
19543 Initialize the section names for the RS/6000 at this point.
19545 Specify filename, including full path, to assembler.
19547 We want to go into the TOC section so at least one .toc will be emitted.
19548 Also, in order to output proper .bs/.es pairs, we need at least one static
19549 [RW] section emitted.
19551 Finally, declare mcount when profiling to make the assembler happy. */
19554 rs6000_xcoff_file_start (void)
19556 rs6000_gen_section_name (&xcoff_bss_section_name,
19557 main_input_filename, ".bss_");
19558 rs6000_gen_section_name (&xcoff_private_data_section_name,
19559 main_input_filename, ".rw_");
19560 rs6000_gen_section_name (&xcoff_read_only_section_name,
19561 main_input_filename, ".ro_");
19563 fputs ("\t.file\t", asm_out_file);
19564 output_quoted_string (asm_out_file, main_input_filename);
19565 fputc ('\n', asm_out_file);
19566 if (write_symbols != NO_DEBUG)
19567 switch_to_section (private_data_section);
19568 switch_to_section (text_section);
19570 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19571 rs6000_file_start ();
19574 /* Output at end of assembler file.
19575 On the RS/6000, referencing data should automatically pull in text. */
19578 rs6000_xcoff_file_end (void)
19580 switch_to_section (text_section);
19581 fputs ("_section_.text:\n", asm_out_file);
19582 switch_to_section (data_section);
19583 fputs (TARGET_32BIT
19584 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19587 #endif /* TARGET_XCOFF */
19589 /* Compute a (partial) cost for rtx X. Return true if the complete
19590 cost has been computed, and false if subexpressions should be
19591 scanned. In either case, *TOTAL contains the cost result. */
19594 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19596 enum machine_mode mode = GET_MODE (x);
19600 /* On the RS/6000, if it is valid in the insn, it is free. */
19602 if (((outer_code == SET
19603 || outer_code == PLUS
19604 || outer_code == MINUS)
19605 && (satisfies_constraint_I (x)
19606 || satisfies_constraint_L (x)))
19607 || (outer_code == AND
19608 && (satisfies_constraint_K (x)
19610 ? satisfies_constraint_L (x)
19611 : satisfies_constraint_J (x))
19612 || mask_operand (x, mode)
19614 && mask64_operand (x, DImode))))
19615 || ((outer_code == IOR || outer_code == XOR)
19616 && (satisfies_constraint_K (x)
19618 ? satisfies_constraint_L (x)
19619 : satisfies_constraint_J (x))))
19620 || outer_code == ASHIFT
19621 || outer_code == ASHIFTRT
19622 || outer_code == LSHIFTRT
19623 || outer_code == ROTATE
19624 || outer_code == ROTATERT
19625 || outer_code == ZERO_EXTRACT
19626 || (outer_code == MULT
19627 && satisfies_constraint_I (x))
19628 || ((outer_code == DIV || outer_code == UDIV
19629 || outer_code == MOD || outer_code == UMOD)
19630 && exact_log2 (INTVAL (x)) >= 0)
19631 || (outer_code == COMPARE
19632 && (satisfies_constraint_I (x)
19633 || satisfies_constraint_K (x)))
19634 || (outer_code == EQ
19635 && (satisfies_constraint_I (x)
19636 || satisfies_constraint_K (x)
19638 ? satisfies_constraint_L (x)
19639 : satisfies_constraint_J (x))))
19640 || (outer_code == GTU
19641 && satisfies_constraint_I (x))
19642 || (outer_code == LTU
19643 && satisfies_constraint_P (x)))
19648 else if ((outer_code == PLUS
19649 && reg_or_add_cint_operand (x, VOIDmode))
19650 || (outer_code == MINUS
19651 && reg_or_sub_cint_operand (x, VOIDmode))
19652 || ((outer_code == SET
19653 || outer_code == IOR
19654 || outer_code == XOR)
19656 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
19658 *total = COSTS_N_INSNS (1);
19664 if (mode == DImode && code == CONST_DOUBLE)
19666 if ((outer_code == IOR || outer_code == XOR)
19667 && CONST_DOUBLE_HIGH (x) == 0
19668 && (CONST_DOUBLE_LOW (x)
19669 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
19674 else if ((outer_code == AND && and64_2_operand (x, DImode))
19675 || ((outer_code == SET
19676 || outer_code == IOR
19677 || outer_code == XOR)
19678 && CONST_DOUBLE_HIGH (x) == 0))
19680 *total = COSTS_N_INSNS (1);
19690 /* When optimizing for size, MEM should be slightly more expensive
19691 than generating address, e.g., (plus (reg) (const)).
19692 L1 cache latency is about two instructions. */
19693 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
19701 if (mode == DFmode)
19703 if (GET_CODE (XEXP (x, 0)) == MULT)
19705 /* FNMA accounted in outer NEG. */
19706 if (outer_code == NEG)
19707 *total = rs6000_cost->dmul - rs6000_cost->fp;
19709 *total = rs6000_cost->dmul;
19712 *total = rs6000_cost->fp;
19714 else if (mode == SFmode)
19716 /* FNMA accounted in outer NEG. */
19717 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19720 *total = rs6000_cost->fp;
19723 *total = COSTS_N_INSNS (1);
19727 if (mode == DFmode)
19729 if (GET_CODE (XEXP (x, 0)) == MULT)
19731 /* FNMA accounted in outer NEG. */
19732 if (outer_code == NEG)
19735 *total = rs6000_cost->dmul;
19738 *total = rs6000_cost->fp;
19740 else if (mode == SFmode)
19742 /* FNMA accounted in outer NEG. */
19743 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
19746 *total = rs6000_cost->fp;
19749 *total = COSTS_N_INSNS (1);
19753 if (GET_CODE (XEXP (x, 1)) == CONST_INT
19754 && satisfies_constraint_I (XEXP (x, 1)))
19756 if (INTVAL (XEXP (x, 1)) >= -256
19757 && INTVAL (XEXP (x, 1)) <= 255)
19758 *total = rs6000_cost->mulsi_const9;
19760 *total = rs6000_cost->mulsi_const;
19762 /* FMA accounted in outer PLUS/MINUS. */
19763 else if ((mode == DFmode || mode == SFmode)
19764 && (outer_code == PLUS || outer_code == MINUS))
19766 else if (mode == DFmode)
19767 *total = rs6000_cost->dmul;
19768 else if (mode == SFmode)
19769 *total = rs6000_cost->fp;
19770 else if (mode == DImode)
19771 *total = rs6000_cost->muldi;
19773 *total = rs6000_cost->mulsi;
19778 if (FLOAT_MODE_P (mode))
19780 *total = mode == DFmode ? rs6000_cost->ddiv
19781 : rs6000_cost->sdiv;
19788 if (GET_CODE (XEXP (x, 1)) == CONST_INT
19789 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
19791 if (code == DIV || code == MOD)
19793 *total = COSTS_N_INSNS (2);
19796 *total = COSTS_N_INSNS (1);
19800 if (GET_MODE (XEXP (x, 1)) == DImode)
19801 *total = rs6000_cost->divdi;
19803 *total = rs6000_cost->divsi;
19805 /* Add in shift and subtract for MOD. */
19806 if (code == MOD || code == UMOD)
19807 *total += COSTS_N_INSNS (2);
19811 *total = COSTS_N_INSNS (4);
19815 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
19826 *total = COSTS_N_INSNS (1);
19834 /* Handle mul_highpart. */
19835 if (outer_code == TRUNCATE
19836 && GET_CODE (XEXP (x, 0)) == MULT)
19838 if (mode == DImode)
19839 *total = rs6000_cost->muldi;
19841 *total = rs6000_cost->mulsi;
19844 else if (outer_code == AND)
19847 *total = COSTS_N_INSNS (1);
19852 if (GET_CODE (XEXP (x, 0)) == MEM)
19855 *total = COSTS_N_INSNS (1);
19861 if (!FLOAT_MODE_P (mode))
19863 *total = COSTS_N_INSNS (1);
19869 case UNSIGNED_FLOAT:
19872 case FLOAT_TRUNCATE:
19873 *total = rs6000_cost->fp;
19877 if (mode == DFmode)
19880 *total = rs6000_cost->fp;
19884 switch (XINT (x, 1))
19887 *total = rs6000_cost->fp;
19899 *total = COSTS_N_INSNS (1);
19902 else if (FLOAT_MODE_P (mode)
19903 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
19905 *total = rs6000_cost->fp;
19913 /* Carry bit requires mode == Pmode.
19914 NEG or PLUS already counted so only add one. */
19916 && (outer_code == NEG || outer_code == PLUS))
19918 *total = COSTS_N_INSNS (1);
19921 if (outer_code == SET)
19923 if (XEXP (x, 1) == const0_rtx)
19925 *total = COSTS_N_INSNS (2);
19928 else if (mode == Pmode)
19930 *total = COSTS_N_INSNS (3);
19939 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
19941 *total = COSTS_N_INSNS (2);
19945 if (outer_code == COMPARE)
19959 /* A C expression returning the cost of moving data from a register of class
19960 CLASS1 to one of CLASS2. */
19963 rs6000_register_move_cost (enum machine_mode mode,
19964 enum reg_class from, enum reg_class to)
19966 /* Moves from/to GENERAL_REGS. */
19967 if (reg_classes_intersect_p (to, GENERAL_REGS)
19968 || reg_classes_intersect_p (from, GENERAL_REGS))
19970 if (! reg_classes_intersect_p (to, GENERAL_REGS))
19973 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
19974 return (rs6000_memory_move_cost (mode, from, 0)
19975 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
19977 /* It's more expensive to move CR_REGS than CR0_REGS because of the
19979 else if (from == CR_REGS)
19983 /* A move will cost one instruction per GPR moved. */
19984 return 2 * hard_regno_nregs[0][mode];
19987 /* Moving between two similar registers is just one instruction. */
19988 else if (reg_classes_intersect_p (to, from))
19989 return mode == TFmode ? 4 : 2;
19991 /* Everything else has to go through GENERAL_REGS. */
19993 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
19994 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
19997 /* A C expressions returning the cost of moving data of MODE from a register to
20001 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20002 int in ATTRIBUTE_UNUSED)
20004 if (reg_classes_intersect_p (class, GENERAL_REGS))
20005 return 4 * hard_regno_nregs[0][mode];
20006 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20007 return 4 * hard_regno_nregs[32][mode];
20008 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20009 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20011 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20014 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20015 Assumes no trapping math and finite arguments. */
20018 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20020 rtx x0, e0, e1, y1, u0, v0, one;
20022 x0 = gen_reg_rtx (SFmode);
20023 e0 = gen_reg_rtx (SFmode);
20024 e1 = gen_reg_rtx (SFmode);
20025 y1 = gen_reg_rtx (SFmode);
20026 u0 = gen_reg_rtx (SFmode);
20027 v0 = gen_reg_rtx (SFmode);
20028 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20030 /* x0 = 1./d estimate */
20031 emit_insn (gen_rtx_SET (VOIDmode, x0,
20032 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20034 /* e0 = 1. - d * x0 */
20035 emit_insn (gen_rtx_SET (VOIDmode, e0,
20036 gen_rtx_MINUS (SFmode, one,
20037 gen_rtx_MULT (SFmode, d, x0))));
20038 /* e1 = e0 + e0 * e0 */
20039 emit_insn (gen_rtx_SET (VOIDmode, e1,
20040 gen_rtx_PLUS (SFmode,
20041 gen_rtx_MULT (SFmode, e0, e0), e0)));
20042 /* y1 = x0 + e1 * x0 */
20043 emit_insn (gen_rtx_SET (VOIDmode, y1,
20044 gen_rtx_PLUS (SFmode,
20045 gen_rtx_MULT (SFmode, e1, x0), x0)));
20047 emit_insn (gen_rtx_SET (VOIDmode, u0,
20048 gen_rtx_MULT (SFmode, n, y1)));
20049 /* v0 = n - d * u0 */
20050 emit_insn (gen_rtx_SET (VOIDmode, v0,
20051 gen_rtx_MINUS (SFmode, n,
20052 gen_rtx_MULT (SFmode, d, u0))));
20053 /* res = u0 + v0 * y1 */
20054 emit_insn (gen_rtx_SET (VOIDmode, res,
20055 gen_rtx_PLUS (SFmode,
20056 gen_rtx_MULT (SFmode, v0, y1), u0)));
20059 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20060 Assumes no trapping math and finite arguments. */
20063 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20065 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20067 x0 = gen_reg_rtx (DFmode);
20068 e0 = gen_reg_rtx (DFmode);
20069 e1 = gen_reg_rtx (DFmode);
20070 e2 = gen_reg_rtx (DFmode);
20071 y1 = gen_reg_rtx (DFmode);
20072 y2 = gen_reg_rtx (DFmode);
20073 y3 = gen_reg_rtx (DFmode);
20074 u0 = gen_reg_rtx (DFmode);
20075 v0 = gen_reg_rtx (DFmode);
20076 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20078 /* x0 = 1./d estimate */
20079 emit_insn (gen_rtx_SET (VOIDmode, x0,
20080 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20082 /* e0 = 1. - d * x0 */
20083 emit_insn (gen_rtx_SET (VOIDmode, e0,
20084 gen_rtx_MINUS (DFmode, one,
20085 gen_rtx_MULT (SFmode, d, x0))));
20086 /* y1 = x0 + e0 * x0 */
20087 emit_insn (gen_rtx_SET (VOIDmode, y1,
20088 gen_rtx_PLUS (DFmode,
20089 gen_rtx_MULT (DFmode, e0, x0), x0)));
20091 emit_insn (gen_rtx_SET (VOIDmode, e1,
20092 gen_rtx_MULT (DFmode, e0, e0)));
20093 /* y2 = y1 + e1 * y1 */
20094 emit_insn (gen_rtx_SET (VOIDmode, y2,
20095 gen_rtx_PLUS (DFmode,
20096 gen_rtx_MULT (DFmode, e1, y1), y1)));
20098 emit_insn (gen_rtx_SET (VOIDmode, e2,
20099 gen_rtx_MULT (DFmode, e1, e1)));
20100 /* y3 = y2 + e2 * y2 */
20101 emit_insn (gen_rtx_SET (VOIDmode, y3,
20102 gen_rtx_PLUS (DFmode,
20103 gen_rtx_MULT (DFmode, e2, y2), y2)));
20105 emit_insn (gen_rtx_SET (VOIDmode, u0,
20106 gen_rtx_MULT (DFmode, n, y3)));
20107 /* v0 = n - d * u0 */
20108 emit_insn (gen_rtx_SET (VOIDmode, v0,
20109 gen_rtx_MINUS (DFmode, n,
20110 gen_rtx_MULT (DFmode, d, u0))));
20111 /* res = u0 + v0 * y3 */
20112 emit_insn (gen_rtx_SET (VOIDmode, res,
20113 gen_rtx_PLUS (DFmode,
20114 gen_rtx_MULT (DFmode, v0, y3), u0)));
20117 /* Return an RTX representing where to find the function value of a
20118 function returning MODE. */
20120 rs6000_complex_function_value (enum machine_mode mode)
20122 unsigned int regno;
20124 enum machine_mode inner = GET_MODE_INNER (mode);
20125 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20127 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20128 regno = FP_ARG_RETURN;
20131 regno = GP_ARG_RETURN;
20133 /* 32-bit is OK since it'll go in r3/r4. */
20134 if (TARGET_32BIT && inner_bytes >= 4)
20135 return gen_rtx_REG (mode, regno);
20138 if (inner_bytes >= 8)
20139 return gen_rtx_REG (mode, regno);
20141 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20143 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20144 GEN_INT (inner_bytes));
20145 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20148 /* Define how to find the value returned by a function.
20149 VALTYPE is the data type of the value (as a tree).
20150 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20151 otherwise, FUNC is 0.
20153 On the SPE, both FPs and vectors are returned in r3.
20155 On RS/6000 an integer value is in r3 and a floating-point value is in
20156 fp1, unless -msoft-float. */
20159 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20161 enum machine_mode mode;
20162 unsigned int regno;
20164 /* Special handling for structs in darwin64. */
20165 if (rs6000_darwin64_abi
20166 && TYPE_MODE (valtype) == BLKmode
20167 && TREE_CODE (valtype) == RECORD_TYPE
20168 && int_size_in_bytes (valtype) > 0)
20170 CUMULATIVE_ARGS valcum;
20174 valcum.fregno = FP_ARG_MIN_REG;
20175 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20176 /* Do a trial code generation as if this were going to be passed as
20177 an argument; if any part goes in memory, we return NULL. */
20178 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20181 /* Otherwise fall through to standard ABI rules. */
20184 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20186 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20187 return gen_rtx_PARALLEL (DImode,
20189 gen_rtx_EXPR_LIST (VOIDmode,
20190 gen_rtx_REG (SImode, GP_ARG_RETURN),
20192 gen_rtx_EXPR_LIST (VOIDmode,
20193 gen_rtx_REG (SImode,
20194 GP_ARG_RETURN + 1),
20197 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20199 return gen_rtx_PARALLEL (DCmode,
20201 gen_rtx_EXPR_LIST (VOIDmode,
20202 gen_rtx_REG (SImode, GP_ARG_RETURN),
20204 gen_rtx_EXPR_LIST (VOIDmode,
20205 gen_rtx_REG (SImode,
20206 GP_ARG_RETURN + 1),
20208 gen_rtx_EXPR_LIST (VOIDmode,
20209 gen_rtx_REG (SImode,
20210 GP_ARG_RETURN + 2),
20212 gen_rtx_EXPR_LIST (VOIDmode,
20213 gen_rtx_REG (SImode,
20214 GP_ARG_RETURN + 3),
20218 if ((INTEGRAL_TYPE_P (valtype)
20219 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
20220 || POINTER_TYPE_P (valtype))
20221 mode = TARGET_32BIT ? SImode : DImode;
20223 mode = TYPE_MODE (valtype);
20225 if (DECIMAL_FLOAT_MODE_P (mode))
20226 regno = GP_ARG_RETURN;
20227 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20228 regno = FP_ARG_RETURN;
20229 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20230 && targetm.calls.split_complex_arg)
20231 return rs6000_complex_function_value (mode);
20232 else if (TREE_CODE (valtype) == VECTOR_TYPE
20233 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20234 && ALTIVEC_VECTOR_MODE (mode))
20235 regno = ALTIVEC_ARG_RETURN;
20236 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20237 && (mode == DFmode || mode == DCmode))
20238 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20240 regno = GP_ARG_RETURN;
20242 return gen_rtx_REG (mode, regno);
20245 /* Define how to find the value returned by a library function
20246 assuming the value has mode MODE. */
20248 rs6000_libcall_value (enum machine_mode mode)
20250 unsigned int regno;
20252 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20254 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20255 return gen_rtx_PARALLEL (DImode,
20257 gen_rtx_EXPR_LIST (VOIDmode,
20258 gen_rtx_REG (SImode, GP_ARG_RETURN),
20260 gen_rtx_EXPR_LIST (VOIDmode,
20261 gen_rtx_REG (SImode,
20262 GP_ARG_RETURN + 1),
20266 if (DECIMAL_FLOAT_MODE_P (mode))
20267 regno = GP_ARG_RETURN;
20268 else if (SCALAR_FLOAT_MODE_P (mode)
20269 && TARGET_HARD_FLOAT && TARGET_FPRS)
20270 regno = FP_ARG_RETURN;
20271 else if (ALTIVEC_VECTOR_MODE (mode)
20272 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20273 regno = ALTIVEC_ARG_RETURN;
20274 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20275 return rs6000_complex_function_value (mode);
20276 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20277 && (mode == DFmode || mode == DCmode))
20278 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20280 regno = GP_ARG_RETURN;
20282 return gen_rtx_REG (mode, regno);
20285 /* Define the offset between two registers, FROM to be eliminated and its
20286 replacement TO, at the start of a routine. */
20288 rs6000_initial_elimination_offset (int from, int to)
20290 rs6000_stack_t *info = rs6000_stack_info ();
20291 HOST_WIDE_INT offset;
20293 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20294 offset = info->push_p ? 0 : -info->total_size;
20295 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20297 offset = info->push_p ? 0 : -info->total_size;
20298 if (FRAME_GROWS_DOWNWARD)
20299 offset += info->fixed_size + info->vars_size + info->parm_size;
20301 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20302 offset = FRAME_GROWS_DOWNWARD
20303 ? info->fixed_size + info->vars_size + info->parm_size
20305 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20306 offset = info->total_size;
20307 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20308 offset = info->push_p ? info->total_size : 0;
20309 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20312 gcc_unreachable ();
20317 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20320 rs6000_is_opaque_type (tree type)
20322 return (type == opaque_V2SI_type_node
20323 || type == opaque_V2SF_type_node
20324 || type == opaque_p_V2SI_type_node
20325 || type == opaque_V4SI_type_node);
20329 rs6000_dwarf_register_span (rtx reg)
20334 && (SPE_VECTOR_MODE (GET_MODE (reg))
20335 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20340 regno = REGNO (reg);
20342 /* The duality of the SPE register size wreaks all kinds of havoc.
20343 This is a way of distinguishing r0 in 32-bits from r0 in
20346 gen_rtx_PARALLEL (VOIDmode,
20349 gen_rtx_REG (SImode, regno + 1200),
20350 gen_rtx_REG (SImode, regno))
20352 gen_rtx_REG (SImode, regno),
20353 gen_rtx_REG (SImode, regno + 1200)));
20356 /* Map internal gcc register numbers to DWARF2 register numbers. */
20359 rs6000_dbx_register_number (unsigned int regno)
20361 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20363 if (regno == MQ_REGNO)
20365 if (regno == LINK_REGISTER_REGNUM)
20367 if (regno == COUNT_REGISTER_REGNUM)
20369 if (CR_REGNO_P (regno))
20370 return regno - CR0_REGNO + 86;
20371 if (regno == XER_REGNO)
20373 if (ALTIVEC_REGNO_P (regno))
20374 return regno - FIRST_ALTIVEC_REGNO + 1124;
20375 if (regno == VRSAVE_REGNO)
20377 if (regno == VSCR_REGNO)
20379 if (regno == SPE_ACC_REGNO)
20381 if (regno == SPEFSCR_REGNO)
20383 /* SPE high reg number. We get these values of regno from
20384 rs6000_dwarf_register_span. */
20385 gcc_assert (regno >= 1200 && regno < 1232);
20389 /* target hook eh_return_filter_mode */
20390 static enum machine_mode
20391 rs6000_eh_return_filter_mode (void)
20393 return TARGET_32BIT ? SImode : word_mode;
20396 /* Target hook for scalar_mode_supported_p. */
20398 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20400 if (DECIMAL_FLOAT_MODE_P (mode))
20403 return default_scalar_mode_supported_p (mode);
20406 /* Target hook for vector_mode_supported_p. */
20408 rs6000_vector_mode_supported_p (enum machine_mode mode)
20411 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20414 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20421 /* Target hook for invalid_arg_for_unprototyped_fn. */
20422 static const char *
20423 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20425 return (!rs6000_darwin64_abi
20427 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20428 && (funcdecl == NULL_TREE
20429 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20430 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20431 ? N_("AltiVec argument passed to unprototyped function")
20435 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20436 setup by using __stack_chk_fail_local hidden function instead of
20437 calling __stack_chk_fail directly. Otherwise it is better to call
20438 __stack_chk_fail directly. */
20441 rs6000_stack_protect_fail (void)
20443 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20444 ? default_hidden_stack_protect_fail ()
20445 : default_external_stack_protect_fail ();
20448 #include "gt-rs6000.h"