1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 2, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the
21 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
22 MA 02110-1301, USA. */
26 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "basic-block.h"
45 #include "integrate.h"
51 #include "target-def.h"
52 #include "langhooks.h"
54 #include "cfglayout.h"
55 #include "sched-int.h"
56 #include "tree-gimple.h"
59 #include "tm-constrs.h"
61 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
64 #include "gstab.h" /* for N_SLINE */
67 #ifndef TARGET_NO_PROTOTYPE
68 #define TARGET_NO_PROTOTYPE 0
71 #define min(A,B) ((A) < (B) ? (A) : (B))
72 #define max(A,B) ((A) > (B) ? (A) : (B))
74 /* Structure used to define the rs6000 stack */
75 typedef struct rs6000_stack {
76 int first_gp_reg_save; /* first callee saved GP register used */
77 int first_fp_reg_save; /* first callee saved FP register used */
78 int first_altivec_reg_save; /* first callee saved AltiVec register used */
79 int lr_save_p; /* true if the link reg needs to be saved */
80 int cr_save_p; /* true if the CR reg needs to be saved */
81 unsigned int vrsave_mask; /* mask of vec registers to save */
82 int push_p; /* true if we need to allocate stack space */
83 int calls_p; /* true if the function makes any calls */
84 int world_save_p; /* true if we're saving *everything*:
85 r13-r31, cr, f14-f31, vrsave, v20-v31 */
86 enum rs6000_abi abi; /* which ABI to use */
87 int gp_save_offset; /* offset to save GP regs from initial SP */
88 int fp_save_offset; /* offset to save FP regs from initial SP */
89 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
90 int lr_save_offset; /* offset to save LR from initial SP */
91 int cr_save_offset; /* offset to save CR from initial SP */
92 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
93 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
94 int varargs_save_offset; /* offset to save the varargs registers */
95 int ehrd_offset; /* offset to EH return data */
96 int reg_size; /* register size (4 or 8) */
97 HOST_WIDE_INT vars_size; /* variable save area size */
98 int parm_size; /* outgoing parameter size */
99 int save_size; /* save area size */
100 int fixed_size; /* fixed size of stack frame */
101 int gp_size; /* size of saved GP registers */
102 int fp_size; /* size of saved FP registers */
103 int altivec_size; /* size of saved AltiVec registers */
104 int cr_size; /* size to hold CR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
111 int spe_64bit_regs_used;
114 /* A C structure for machine-specific, per-function data.
115 This is added to the cfun structure. */
116 typedef struct machine_function GTY(())
118 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
119 int ra_needs_full_frame;
120 /* Some local-dynamic symbol. */
121 const char *some_ld_name;
122 /* Whether the instruction chain has been scanned already. */
123 int insn_chain_scanned_p;
124 /* Flags if __builtin_return_address (0) was used. */
126 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
127 varargs save area. */
128 HOST_WIDE_INT varargs_save_offset;
131 /* Target cpu type */
133 enum processor_type rs6000_cpu;
134 struct rs6000_cpu_select rs6000_select[3] =
136 /* switch name, tune arch */
137 { (const char *)0, "--with-cpu=", 1, 1 },
138 { (const char *)0, "-mcpu=", 1, 1 },
139 { (const char *)0, "-mtune=", 1, 0 },
142 static GTY(()) bool rs6000_cell_dont_microcode;
144 /* Always emit branch hint bits. */
145 static GTY(()) bool rs6000_always_hint;
147 /* Schedule instructions for group formation. */
148 static GTY(()) bool rs6000_sched_groups;
150 /* Align branch targets. */
151 static GTY(()) bool rs6000_align_branch_targets;
153 /* Support for -msched-costly-dep option. */
154 const char *rs6000_sched_costly_dep_str;
155 enum rs6000_dependence_cost rs6000_sched_costly_dep;
157 /* Support for -minsert-sched-nops option. */
158 const char *rs6000_sched_insert_nops_str;
159 enum rs6000_nop_insertion rs6000_sched_insert_nops;
161 /* Support targetm.vectorize.builtin_mask_for_load. */
162 static GTY(()) tree altivec_builtin_mask_for_load;
164 /* Size of long double. */
165 int rs6000_long_double_type_size;
167 /* IEEE quad extended precision long double. */
170 /* Whether -mabi=altivec has appeared. */
171 int rs6000_altivec_abi;
173 /* Nonzero if we want SPE ABI extensions. */
176 /* Nonzero if floating point operations are done in the GPRs. */
177 int rs6000_float_gprs = 0;
179 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
180 int rs6000_darwin64_abi;
182 /* Set to nonzero once AIX common-mode calls have been defined. */
183 static GTY(()) int common_mode_defined;
185 /* Save information from a "cmpxx" operation until the branch or scc is
187 rtx rs6000_compare_op0, rs6000_compare_op1;
188 int rs6000_compare_fp_p;
190 /* Label number of label created for -mrelocatable, to call to so we can
191 get the address of the GOT section */
192 int rs6000_pic_labelno;
195 /* Which abi to adhere to */
196 const char *rs6000_abi_name;
198 /* Semantics of the small data area */
199 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
201 /* Which small data model to use */
202 const char *rs6000_sdata_name = (char *)0;
204 /* Counter for labels which are to be placed in .fixup. */
205 int fixuplabelno = 0;
208 /* Bit size of immediate TLS offsets and string from which it is decoded. */
209 int rs6000_tls_size = 32;
210 const char *rs6000_tls_size_string;
212 /* ABI enumeration available for subtarget to use. */
213 enum rs6000_abi rs6000_current_abi;
215 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
219 const char *rs6000_debug_name;
220 int rs6000_debug_stack; /* debug stack applications */
221 int rs6000_debug_arg; /* debug argument handling */
223 /* Value is TRUE if register/mode pair is acceptable. */
224 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
226 /* Built in types. */
228 tree rs6000_builtin_types[RS6000_BTI_MAX];
229 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
231 const char *rs6000_traceback_name;
233 traceback_default = 0,
239 /* Flag to say the TOC is initialized */
241 char toc_label_name[10];
243 /* Cached value of rs6000_variable_issue. This is cached in
244 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
245 static short cached_can_issue_more;
247 static GTY(()) section *read_only_data_section;
248 static GTY(()) section *private_data_section;
249 static GTY(()) section *read_only_private_data_section;
250 static GTY(()) section *sdata2_section;
251 static GTY(()) section *toc_section;
253 /* Control alignment for fields within structures. */
254 /* String from -malign-XXXXX. */
255 int rs6000_alignment_flags;
257 /* True for any options that were explicitly set. */
259 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
260 bool alignment; /* True if -malign- was used. */
261 bool abi; /* True if -mabi=spe/nospe was used. */
262 bool spe; /* True if -mspe= was used. */
263 bool float_gprs; /* True if -mfloat-gprs= was used. */
264 bool isel; /* True if -misel was used. */
265 bool long_double; /* True if -mlong-double- was used. */
266 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
267 } rs6000_explicit_options;
269 struct builtin_description
271 /* mask is not const because we're going to alter it below. This
272 nonsense will go away when we rewrite the -march infrastructure
273 to give us more target flag bits. */
275 const enum insn_code icode;
276 const char *const name;
277 const enum rs6000_builtins code;
280 /* Target cpu costs. */
282 struct processor_costs {
283 const int mulsi; /* cost of SImode multiplication. */
284 const int mulsi_const; /* cost of SImode multiplication by constant. */
285 const int mulsi_const9; /* cost of SImode mult by short constant. */
286 const int muldi; /* cost of DImode multiplication. */
287 const int divsi; /* cost of SImode division. */
288 const int divdi; /* cost of DImode division. */
289 const int fp; /* cost of simple SFmode and DFmode insns. */
290 const int dmul; /* cost of DFmode multiplication (and fmadd). */
291 const int sdiv; /* cost of SFmode division (fdivs). */
292 const int ddiv; /* cost of DFmode division (fdiv). */
295 const struct processor_costs *rs6000_cost;
297 /* Processor costs (relative to an add) */
299 /* Instruction size costs on 32bit processors. */
301 struct processor_costs size32_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction size costs on 64bit processors. */
316 struct processor_costs size64_cost = {
317 COSTS_N_INSNS (1), /* mulsi */
318 COSTS_N_INSNS (1), /* mulsi_const */
319 COSTS_N_INSNS (1), /* mulsi_const9 */
320 COSTS_N_INSNS (1), /* muldi */
321 COSTS_N_INSNS (1), /* divsi */
322 COSTS_N_INSNS (1), /* divdi */
323 COSTS_N_INSNS (1), /* fp */
324 COSTS_N_INSNS (1), /* dmul */
325 COSTS_N_INSNS (1), /* sdiv */
326 COSTS_N_INSNS (1), /* ddiv */
329 /* Instruction costs on RIOS1 processors. */
331 struct processor_costs rios1_cost = {
332 COSTS_N_INSNS (5), /* mulsi */
333 COSTS_N_INSNS (4), /* mulsi_const */
334 COSTS_N_INSNS (3), /* mulsi_const9 */
335 COSTS_N_INSNS (5), /* muldi */
336 COSTS_N_INSNS (19), /* divsi */
337 COSTS_N_INSNS (19), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (19), /* sdiv */
341 COSTS_N_INSNS (19), /* ddiv */
344 /* Instruction costs on RIOS2 processors. */
346 struct processor_costs rios2_cost = {
347 COSTS_N_INSNS (2), /* mulsi */
348 COSTS_N_INSNS (2), /* mulsi_const */
349 COSTS_N_INSNS (2), /* mulsi_const9 */
350 COSTS_N_INSNS (2), /* muldi */
351 COSTS_N_INSNS (13), /* divsi */
352 COSTS_N_INSNS (13), /* divdi */
353 COSTS_N_INSNS (2), /* fp */
354 COSTS_N_INSNS (2), /* dmul */
355 COSTS_N_INSNS (17), /* sdiv */
356 COSTS_N_INSNS (17), /* ddiv */
359 /* Instruction costs on RS64A processors. */
361 struct processor_costs rs64a_cost = {
362 COSTS_N_INSNS (20), /* mulsi */
363 COSTS_N_INSNS (12), /* mulsi_const */
364 COSTS_N_INSNS (8), /* mulsi_const9 */
365 COSTS_N_INSNS (34), /* muldi */
366 COSTS_N_INSNS (65), /* divsi */
367 COSTS_N_INSNS (67), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (4), /* dmul */
370 COSTS_N_INSNS (31), /* sdiv */
371 COSTS_N_INSNS (31), /* ddiv */
374 /* Instruction costs on MPCCORE processors. */
376 struct processor_costs mpccore_cost = {
377 COSTS_N_INSNS (2), /* mulsi */
378 COSTS_N_INSNS (2), /* mulsi_const */
379 COSTS_N_INSNS (2), /* mulsi_const9 */
380 COSTS_N_INSNS (2), /* muldi */
381 COSTS_N_INSNS (6), /* divsi */
382 COSTS_N_INSNS (6), /* divdi */
383 COSTS_N_INSNS (4), /* fp */
384 COSTS_N_INSNS (5), /* dmul */
385 COSTS_N_INSNS (10), /* sdiv */
386 COSTS_N_INSNS (17), /* ddiv */
389 /* Instruction costs on PPC403 processors. */
391 struct processor_costs ppc403_cost = {
392 COSTS_N_INSNS (4), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (4), /* mulsi_const9 */
395 COSTS_N_INSNS (4), /* muldi */
396 COSTS_N_INSNS (33), /* divsi */
397 COSTS_N_INSNS (33), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC405 processors. */
406 struct processor_costs ppc405_cost = {
407 COSTS_N_INSNS (5), /* mulsi */
408 COSTS_N_INSNS (4), /* mulsi_const */
409 COSTS_N_INSNS (3), /* mulsi_const9 */
410 COSTS_N_INSNS (5), /* muldi */
411 COSTS_N_INSNS (35), /* divsi */
412 COSTS_N_INSNS (35), /* divdi */
413 COSTS_N_INSNS (11), /* fp */
414 COSTS_N_INSNS (11), /* dmul */
415 COSTS_N_INSNS (11), /* sdiv */
416 COSTS_N_INSNS (11), /* ddiv */
419 /* Instruction costs on PPC440 processors. */
421 struct processor_costs ppc440_cost = {
422 COSTS_N_INSNS (3), /* mulsi */
423 COSTS_N_INSNS (2), /* mulsi_const */
424 COSTS_N_INSNS (2), /* mulsi_const9 */
425 COSTS_N_INSNS (3), /* muldi */
426 COSTS_N_INSNS (34), /* divsi */
427 COSTS_N_INSNS (34), /* divdi */
428 COSTS_N_INSNS (5), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (19), /* sdiv */
431 COSTS_N_INSNS (33), /* ddiv */
434 /* Instruction costs on PPC601 processors. */
436 struct processor_costs ppc601_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (5), /* mulsi_const */
439 COSTS_N_INSNS (5), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (36), /* divsi */
442 COSTS_N_INSNS (36), /* divdi */
443 COSTS_N_INSNS (4), /* fp */
444 COSTS_N_INSNS (5), /* dmul */
445 COSTS_N_INSNS (17), /* sdiv */
446 COSTS_N_INSNS (31), /* ddiv */
449 /* Instruction costs on PPC603 processors. */
451 struct processor_costs ppc603_cost = {
452 COSTS_N_INSNS (5), /* mulsi */
453 COSTS_N_INSNS (3), /* mulsi_const */
454 COSTS_N_INSNS (2), /* mulsi_const9 */
455 COSTS_N_INSNS (5), /* muldi */
456 COSTS_N_INSNS (37), /* divsi */
457 COSTS_N_INSNS (37), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (4), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (33), /* ddiv */
464 /* Instruction costs on PPC604 processors. */
466 struct processor_costs ppc604_cost = {
467 COSTS_N_INSNS (4), /* mulsi */
468 COSTS_N_INSNS (4), /* mulsi_const */
469 COSTS_N_INSNS (4), /* mulsi_const9 */
470 COSTS_N_INSNS (4), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC604e processors. */
481 struct processor_costs ppc604e_cost = {
482 COSTS_N_INSNS (2), /* mulsi */
483 COSTS_N_INSNS (2), /* mulsi_const */
484 COSTS_N_INSNS (2), /* mulsi_const9 */
485 COSTS_N_INSNS (2), /* muldi */
486 COSTS_N_INSNS (20), /* divsi */
487 COSTS_N_INSNS (20), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC620 processors. */
496 struct processor_costs ppc620_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (18), /* sdiv */
506 COSTS_N_INSNS (32), /* ddiv */
509 /* Instruction costs on PPC630 processors. */
511 struct processor_costs ppc630_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (4), /* mulsi_const */
514 COSTS_N_INSNS (3), /* mulsi_const9 */
515 COSTS_N_INSNS (7), /* muldi */
516 COSTS_N_INSNS (21), /* divsi */
517 COSTS_N_INSNS (37), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (21), /* ddiv */
524 /* Instruction costs on Cell processor. */
525 /* COSTS_N_INSNS (1) ~ one add. */
527 struct processor_costs ppccell_cost = {
528 COSTS_N_INSNS (9/2)+2, /* mulsi */
529 COSTS_N_INSNS (6/2), /* mulsi_const */
530 COSTS_N_INSNS (6/2), /* mulsi_const9 */
531 COSTS_N_INSNS (15/2)+2, /* muldi */
532 COSTS_N_INSNS (38/2), /* divsi */
533 COSTS_N_INSNS (70/2), /* divdi */
534 COSTS_N_INSNS (10/2), /* fp */
535 COSTS_N_INSNS (10/2), /* dmul */
536 COSTS_N_INSNS (74/2), /* sdiv */
537 COSTS_N_INSNS (74/2), /* ddiv */
540 /* Instruction costs on PPC750 and PPC7400 processors. */
542 struct processor_costs ppc750_cost = {
543 COSTS_N_INSNS (5), /* mulsi */
544 COSTS_N_INSNS (3), /* mulsi_const */
545 COSTS_N_INSNS (2), /* mulsi_const9 */
546 COSTS_N_INSNS (5), /* muldi */
547 COSTS_N_INSNS (17), /* divsi */
548 COSTS_N_INSNS (17), /* divdi */
549 COSTS_N_INSNS (3), /* fp */
550 COSTS_N_INSNS (3), /* dmul */
551 COSTS_N_INSNS (17), /* sdiv */
552 COSTS_N_INSNS (31), /* ddiv */
555 /* Instruction costs on PPC7450 processors. */
557 struct processor_costs ppc7450_cost = {
558 COSTS_N_INSNS (4), /* mulsi */
559 COSTS_N_INSNS (3), /* mulsi_const */
560 COSTS_N_INSNS (3), /* mulsi_const9 */
561 COSTS_N_INSNS (4), /* muldi */
562 COSTS_N_INSNS (23), /* divsi */
563 COSTS_N_INSNS (23), /* divdi */
564 COSTS_N_INSNS (5), /* fp */
565 COSTS_N_INSNS (5), /* dmul */
566 COSTS_N_INSNS (21), /* sdiv */
567 COSTS_N_INSNS (35), /* ddiv */
570 /* Instruction costs on PPC8540 processors. */
572 struct processor_costs ppc8540_cost = {
573 COSTS_N_INSNS (4), /* mulsi */
574 COSTS_N_INSNS (4), /* mulsi_const */
575 COSTS_N_INSNS (4), /* mulsi_const9 */
576 COSTS_N_INSNS (4), /* muldi */
577 COSTS_N_INSNS (19), /* divsi */
578 COSTS_N_INSNS (19), /* divdi */
579 COSTS_N_INSNS (4), /* fp */
580 COSTS_N_INSNS (4), /* dmul */
581 COSTS_N_INSNS (29), /* sdiv */
582 COSTS_N_INSNS (29), /* ddiv */
585 /* Instruction costs on POWER4 and POWER5 processors. */
587 struct processor_costs power4_cost = {
588 COSTS_N_INSNS (3), /* mulsi */
589 COSTS_N_INSNS (2), /* mulsi_const */
590 COSTS_N_INSNS (2), /* mulsi_const9 */
591 COSTS_N_INSNS (4), /* muldi */
592 COSTS_N_INSNS (18), /* divsi */
593 COSTS_N_INSNS (34), /* divdi */
594 COSTS_N_INSNS (3), /* fp */
595 COSTS_N_INSNS (3), /* dmul */
596 COSTS_N_INSNS (17), /* sdiv */
597 COSTS_N_INSNS (17), /* ddiv */
600 /* Instruction costs on POWER6 processors. */
602 struct processor_costs power6_cost = {
603 COSTS_N_INSNS (8), /* mulsi */
604 COSTS_N_INSNS (8), /* mulsi_const */
605 COSTS_N_INSNS (8), /* mulsi_const9 */
606 COSTS_N_INSNS (8), /* muldi */
607 COSTS_N_INSNS (22), /* divsi */
608 COSTS_N_INSNS (28), /* divdi */
609 COSTS_N_INSNS (3), /* fp */
610 COSTS_N_INSNS (3), /* dmul */
611 COSTS_N_INSNS (13), /* sdiv */
612 COSTS_N_INSNS (16), /* ddiv */
616 static bool rs6000_function_ok_for_sibcall (tree, tree);
617 static const char *rs6000_invalid_within_doloop (rtx);
618 static rtx rs6000_generate_compare (enum rtx_code);
619 static void rs6000_emit_stack_tie (void);
620 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
621 static rtx spe_synthesize_frame_save (rtx);
622 static bool spe_func_has_64bit_regs_p (void);
623 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
625 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
626 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
627 static unsigned rs6000_hash_constant (rtx);
628 static unsigned toc_hash_function (const void *);
629 static int toc_hash_eq (const void *, const void *);
630 static int constant_pool_expr_1 (rtx, int *, int *);
631 static bool constant_pool_expr_p (rtx);
632 static bool legitimate_small_data_p (enum machine_mode, rtx);
633 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
634 static struct machine_function * rs6000_init_machine_status (void);
635 static bool rs6000_assemble_integer (rtx, unsigned int, int);
636 static bool no_global_regs_above (int);
637 #ifdef HAVE_GAS_HIDDEN
638 static void rs6000_assemble_visibility (tree, int);
640 static int rs6000_ra_ever_killed (void);
641 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
642 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
643 static bool rs6000_ms_bitfield_layout_p (tree);
644 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
645 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
646 static const char *rs6000_mangle_fundamental_type (tree);
647 extern const struct attribute_spec rs6000_attribute_table[];
648 static void rs6000_set_default_type_attributes (tree);
649 static bool rs6000_reg_live_or_pic_offset_p (int);
650 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
651 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
652 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
654 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
655 static bool rs6000_return_in_memory (tree, tree);
656 static void rs6000_file_start (void);
658 static int rs6000_elf_reloc_rw_mask (void);
659 static void rs6000_elf_asm_out_constructor (rtx, int);
660 static void rs6000_elf_asm_out_destructor (rtx, int);
661 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
662 static void rs6000_elf_asm_init_sections (void);
663 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
664 unsigned HOST_WIDE_INT);
665 static void rs6000_elf_encode_section_info (tree, rtx, int)
668 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, rtx);
670 static void rs6000_xcoff_asm_output_anchor (rtx);
671 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
672 static void rs6000_xcoff_asm_init_sections (void);
673 static int rs6000_xcoff_reloc_rw_mask (void);
674 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
675 static section *rs6000_xcoff_select_section (tree, int,
676 unsigned HOST_WIDE_INT);
677 static void rs6000_xcoff_unique_section (tree, int);
678 static section *rs6000_xcoff_select_rtx_section
679 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
680 static const char * rs6000_xcoff_strip_name_encoding (const char *);
681 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
682 static void rs6000_xcoff_file_start (void);
683 static void rs6000_xcoff_file_end (void);
685 static int rs6000_variable_issue (FILE *, int, rtx, int);
686 static bool rs6000_rtx_costs (rtx, int, int, int *);
687 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
688 static void rs6000_sched_init (FILE *, int, int);
689 static bool is_microcoded_insn (rtx);
690 static bool is_nonpipeline_insn (rtx);
691 static bool is_cracked_insn (rtx);
692 static bool is_branch_slot_insn (rtx);
693 static bool is_load_insn (rtx);
694 static rtx get_store_dest (rtx pat);
695 static bool is_store_insn (rtx);
696 static bool set_to_load_agen (rtx,rtx);
697 static bool adjacent_mem_locations (rtx,rtx);
698 static int rs6000_adjust_priority (rtx, int);
699 static int rs6000_issue_rate (void);
700 static bool rs6000_is_costly_dependence (dep_t, int, int);
701 static rtx get_next_active_insn (rtx, rtx);
702 static bool insn_terminates_group_p (rtx , enum group_termination);
703 static bool insn_must_be_first_in_group (rtx);
704 static bool insn_must_be_last_in_group (rtx);
705 static bool is_costly_group (rtx *, rtx);
706 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
707 static int redefine_groups (FILE *, int, rtx, rtx);
708 static int pad_groups (FILE *, int, rtx, rtx);
709 static void rs6000_sched_finish (FILE *, int);
710 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
711 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
712 static int rs6000_use_sched_lookahead (void);
713 static int rs6000_use_sched_lookahead_guard (rtx);
714 static tree rs6000_builtin_mask_for_load (void);
715 static tree rs6000_builtin_mul_widen_even (tree);
716 static tree rs6000_builtin_mul_widen_odd (tree);
717 static tree rs6000_builtin_conversion (enum tree_code, tree);
719 static void def_builtin (int, const char *, tree, int);
720 static bool rs6000_vector_alignment_reachable (tree, bool);
721 static void rs6000_init_builtins (void);
722 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
723 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
724 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
725 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
726 static void altivec_init_builtins (void);
727 static void rs6000_common_init_builtins (void);
728 static void rs6000_init_libfuncs (void);
730 static void enable_mask_for_builtins (struct builtin_description *, int,
731 enum rs6000_builtins,
732 enum rs6000_builtins);
733 static tree build_opaque_vector_type (tree, int);
734 static void spe_init_builtins (void);
735 static rtx spe_expand_builtin (tree, rtx, bool *);
736 static rtx spe_expand_stv_builtin (enum insn_code, tree);
737 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
738 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
739 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
740 static rs6000_stack_t *rs6000_stack_info (void);
741 static void debug_stack_info (rs6000_stack_t *);
743 static rtx altivec_expand_builtin (tree, rtx, bool *);
744 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
745 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
746 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
747 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
748 static rtx altivec_expand_predicate_builtin (enum insn_code,
749 const char *, tree, rtx);
750 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
751 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
752 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
753 static rtx altivec_expand_vec_set_builtin (tree);
754 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
755 static int get_element_number (tree, tree);
756 static bool rs6000_handle_option (size_t, const char *, int);
757 static void rs6000_parse_tls_size_option (void);
758 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
759 static int first_altivec_reg_to_save (void);
760 static unsigned int compute_vrsave_mask (void);
761 static void compute_save_world_info (rs6000_stack_t *info_ptr);
762 static void is_altivec_return_reg (rtx, void *);
763 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
764 int easy_vector_constant (rtx, enum machine_mode);
765 static bool rs6000_is_opaque_type (tree);
766 static rtx rs6000_dwarf_register_span (rtx);
767 static void rs6000_init_dwarf_reg_sizes_extra (tree);
768 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
769 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
770 static rtx rs6000_tls_get_addr (void);
771 static rtx rs6000_got_sym (void);
772 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
773 static const char *rs6000_get_some_local_dynamic_name (void);
774 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
775 static rtx rs6000_complex_function_value (enum machine_mode);
776 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
777 enum machine_mode, tree);
778 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
780 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
781 tree, HOST_WIDE_INT);
782 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
785 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
788 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
789 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
790 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
791 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
792 enum machine_mode, tree,
794 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
796 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
798 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
800 static void macho_branch_islands (void);
801 static int no_previous_def (tree function_name);
802 static tree get_prev_label (tree function_name);
803 static void rs6000_darwin_file_start (void);
806 static tree rs6000_build_builtin_va_list (void);
807 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
808 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
809 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
810 static bool rs6000_vector_mode_supported_p (enum machine_mode);
811 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
813 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
815 static int get_vsel_insn (enum machine_mode);
816 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
817 static tree rs6000_stack_protect_fail (void);
819 const int INSN_NOT_AVAILABLE = -1;
820 static enum machine_mode rs6000_eh_return_filter_mode (void);
822 /* Hash table stuff for keeping track of TOC entries. */
824 struct toc_hash_struct GTY(())
826 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
827 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
829 enum machine_mode key_mode;
833 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
835 /* Default register names. */
836 char rs6000_reg_names[][8] =
838 "0", "1", "2", "3", "4", "5", "6", "7",
839 "8", "9", "10", "11", "12", "13", "14", "15",
840 "16", "17", "18", "19", "20", "21", "22", "23",
841 "24", "25", "26", "27", "28", "29", "30", "31",
842 "0", "1", "2", "3", "4", "5", "6", "7",
843 "8", "9", "10", "11", "12", "13", "14", "15",
844 "16", "17", "18", "19", "20", "21", "22", "23",
845 "24", "25", "26", "27", "28", "29", "30", "31",
846 "mq", "lr", "ctr","ap",
847 "0", "1", "2", "3", "4", "5", "6", "7",
849 /* AltiVec registers. */
850 "0", "1", "2", "3", "4", "5", "6", "7",
851 "8", "9", "10", "11", "12", "13", "14", "15",
852 "16", "17", "18", "19", "20", "21", "22", "23",
853 "24", "25", "26", "27", "28", "29", "30", "31",
856 "spe_acc", "spefscr",
857 /* Soft frame pointer. */
861 #ifdef TARGET_REGNAMES
862 static const char alt_reg_names[][8] =
864 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
865 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
866 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
867 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
868 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
869 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
870 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
871 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
872 "mq", "lr", "ctr", "ap",
873 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
875 /* AltiVec registers. */
876 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
877 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
878 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
879 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
882 "spe_acc", "spefscr",
883 /* Soft frame pointer. */
888 #ifndef MASK_STRICT_ALIGN
889 #define MASK_STRICT_ALIGN 0
891 #ifndef TARGET_PROFILE_KERNEL
892 #define TARGET_PROFILE_KERNEL 0
895 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
896 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
898 /* Initialize the GCC target structure. */
899 #undef TARGET_ATTRIBUTE_TABLE
900 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
901 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
902 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
904 #undef TARGET_ASM_ALIGNED_DI_OP
905 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
907 /* Default unaligned ops are only provided for ELF. Find the ops needed
908 for non-ELF systems. */
909 #ifndef OBJECT_FORMAT_ELF
911 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
913 #undef TARGET_ASM_UNALIGNED_HI_OP
914 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
915 #undef TARGET_ASM_UNALIGNED_SI_OP
916 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
917 #undef TARGET_ASM_UNALIGNED_DI_OP
918 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
921 #undef TARGET_ASM_UNALIGNED_HI_OP
922 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
923 #undef TARGET_ASM_UNALIGNED_SI_OP
924 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
925 #undef TARGET_ASM_UNALIGNED_DI_OP
926 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
927 #undef TARGET_ASM_ALIGNED_DI_OP
928 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
932 /* This hook deals with fixups for relocatable code and DI-mode objects
934 #undef TARGET_ASM_INTEGER
935 #define TARGET_ASM_INTEGER rs6000_assemble_integer
937 #ifdef HAVE_GAS_HIDDEN
938 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
939 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
942 #undef TARGET_HAVE_TLS
943 #define TARGET_HAVE_TLS HAVE_AS_TLS
945 #undef TARGET_CANNOT_FORCE_CONST_MEM
946 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
948 #undef TARGET_ASM_FUNCTION_PROLOGUE
949 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
950 #undef TARGET_ASM_FUNCTION_EPILOGUE
951 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
953 #undef TARGET_SCHED_VARIABLE_ISSUE
954 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
956 #undef TARGET_SCHED_ISSUE_RATE
957 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
958 #undef TARGET_SCHED_ADJUST_COST
959 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
960 #undef TARGET_SCHED_ADJUST_PRIORITY
961 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
962 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
963 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
964 #undef TARGET_SCHED_INIT
965 #define TARGET_SCHED_INIT rs6000_sched_init
966 #undef TARGET_SCHED_FINISH
967 #define TARGET_SCHED_FINISH rs6000_sched_finish
968 #undef TARGET_SCHED_REORDER
969 #define TARGET_SCHED_REORDER rs6000_sched_reorder
970 #undef TARGET_SCHED_REORDER2
971 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
973 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
974 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
976 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
977 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
979 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
980 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
981 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
982 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
983 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
984 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
985 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
986 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
988 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
989 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
991 #undef TARGET_INIT_BUILTINS
992 #define TARGET_INIT_BUILTINS rs6000_init_builtins
994 #undef TARGET_EXPAND_BUILTIN
995 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
997 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
998 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
1000 #undef TARGET_INIT_LIBFUNCS
1001 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1004 #undef TARGET_BINDS_LOCAL_P
1005 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1008 #undef TARGET_MS_BITFIELD_LAYOUT_P
1009 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1011 #undef TARGET_ASM_OUTPUT_MI_THUNK
1012 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1014 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1015 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
1017 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1018 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1020 #undef TARGET_INVALID_WITHIN_DOLOOP
1021 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1023 #undef TARGET_RTX_COSTS
1024 #define TARGET_RTX_COSTS rs6000_rtx_costs
1025 #undef TARGET_ADDRESS_COST
1026 #define TARGET_ADDRESS_COST hook_int_rtx_0
1028 #undef TARGET_VECTOR_OPAQUE_P
1029 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1031 #undef TARGET_DWARF_REGISTER_SPAN
1032 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1034 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1035 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1037 /* On rs6000, function arguments are promoted, as are function return
1039 #undef TARGET_PROMOTE_FUNCTION_ARGS
1040 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
1041 #undef TARGET_PROMOTE_FUNCTION_RETURN
1042 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
1044 #undef TARGET_RETURN_IN_MEMORY
1045 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1047 #undef TARGET_SETUP_INCOMING_VARARGS
1048 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1050 /* Always strict argument naming on rs6000. */
1051 #undef TARGET_STRICT_ARGUMENT_NAMING
1052 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1053 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1054 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1055 #undef TARGET_SPLIT_COMPLEX_ARG
1056 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
1057 #undef TARGET_MUST_PASS_IN_STACK
1058 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1059 #undef TARGET_PASS_BY_REFERENCE
1060 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1061 #undef TARGET_ARG_PARTIAL_BYTES
1062 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1064 #undef TARGET_BUILD_BUILTIN_VA_LIST
1065 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1067 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1068 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1070 #undef TARGET_EH_RETURN_FILTER_MODE
1071 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1073 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1074 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1076 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1077 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1079 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1080 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1082 #undef TARGET_HANDLE_OPTION
1083 #define TARGET_HANDLE_OPTION rs6000_handle_option
1085 #undef TARGET_DEFAULT_TARGET_FLAGS
1086 #define TARGET_DEFAULT_TARGET_FLAGS \
1089 #undef TARGET_STACK_PROTECT_FAIL
1090 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1092 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1093 The PowerPC architecture requires only weak consistency among
1094 processors--that is, memory accesses between processors need not be
1095 sequentially consistent and memory accesses among processors can occur
1096 in any order. The ability to order memory accesses weakly provides
1097 opportunities for more efficient use of the system bus. Unless a
1098 dependency exists, the 604e allows read operations to precede store
1100 #undef TARGET_RELAXED_ORDERING
1101 #define TARGET_RELAXED_ORDERING true
1104 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1105 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1108 /* Use a 32-bit anchor range. This leads to sequences like:
1110 addis tmp,anchor,high
1113 where tmp itself acts as an anchor, and can be shared between
1114 accesses to the same 64k page. */
1115 #undef TARGET_MIN_ANCHOR_OFFSET
1116 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1117 #undef TARGET_MAX_ANCHOR_OFFSET
1118 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1119 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1120 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1122 struct gcc_target targetm = TARGET_INITIALIZER;
1125 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1128 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1130 /* The GPRs can hold any mode, but values bigger than one register
1131 cannot go past R31. */
1132 if (INT_REGNO_P (regno))
1133 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1135 /* The float registers can only hold floating modes and DImode.
1136 This excludes the 32-bit decimal float mode for now. */
1137 if (FP_REGNO_P (regno))
1139 (SCALAR_FLOAT_MODE_P (mode)
1140 && (mode != TDmode || (regno % 2) == 0)
1142 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1143 || (GET_MODE_CLASS (mode) == MODE_INT
1144 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1146 /* The CR register can only hold CC modes. */
1147 if (CR_REGNO_P (regno))
1148 return GET_MODE_CLASS (mode) == MODE_CC;
1150 if (XER_REGNO_P (regno))
1151 return mode == PSImode;
1153 /* AltiVec only in AldyVec registers. */
1154 if (ALTIVEC_REGNO_P (regno))
1155 return ALTIVEC_VECTOR_MODE (mode);
1157 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1158 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1161 /* We cannot put TImode anywhere except general register and it must be
1162 able to fit within the register set. */
1164 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1167 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1169 rs6000_init_hard_regno_mode_ok (void)
1173 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1174 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1175 if (rs6000_hard_regno_mode_ok (r, m))
1176 rs6000_hard_regno_mode_ok_p[m][r] = true;
1180 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1183 darwin_rs6000_override_options (void)
1185 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1187 rs6000_altivec_abi = 1;
1188 TARGET_ALTIVEC_VRSAVE = 1;
1189 if (DEFAULT_ABI == ABI_DARWIN)
1191 if (MACHO_DYNAMIC_NO_PIC_P)
1194 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1197 else if (flag_pic == 1)
1202 if (TARGET_64BIT && ! TARGET_POWERPC64)
1204 target_flags |= MASK_POWERPC64;
1205 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1209 rs6000_default_long_calls = 1;
1210 target_flags |= MASK_SOFT_FLOAT;
1213 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1215 if (!flag_mkernel && !flag_apple_kext
1217 && ! (target_flags_explicit & MASK_ALTIVEC))
1218 target_flags |= MASK_ALTIVEC;
1220 /* Unless the user (not the configurer) has explicitly overridden
1221 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1222 G4 unless targetting the kernel. */
1225 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1226 && ! (target_flags_explicit & MASK_ALTIVEC)
1227 && ! rs6000_select[1].string)
1229 target_flags |= MASK_ALTIVEC;
1234 /* If not otherwise specified by a target, make 'long double' equivalent to
1237 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1238 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1241 /* Override command line options. Mostly we process the processor
1242 type and sometimes adjust other TARGET_ options. */
1245 rs6000_override_options (const char *default_cpu)
1248 struct rs6000_cpu_select *ptr;
1251 /* Simplifications for entries below. */
1254 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1255 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1258 /* This table occasionally claims that a processor does not support
1259 a particular feature even though it does, but the feature is slower
1260 than the alternative. Thus, it shouldn't be relied on as a
1261 complete description of the processor's support.
1263 Please keep this list in order, and don't forget to update the
1264 documentation in invoke.texi when adding a new processor or
1268 const char *const name; /* Canonical processor name. */
1269 const enum processor_type processor; /* Processor type enum value. */
1270 const int target_enable; /* Target flags to enable. */
1271 } const processor_target_table[]
1272 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1273 {"403", PROCESSOR_PPC403,
1274 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1275 {"405", PROCESSOR_PPC405,
1276 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1277 {"405fp", PROCESSOR_PPC405,
1278 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1279 {"440", PROCESSOR_PPC440,
1280 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1281 {"440fp", PROCESSOR_PPC440,
1282 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1283 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1284 {"601", PROCESSOR_PPC601,
1285 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1286 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1287 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1288 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1289 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1290 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1291 {"620", PROCESSOR_PPC620,
1292 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1293 {"630", PROCESSOR_PPC630,
1294 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1295 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1296 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1297 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1298 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1299 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1300 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1301 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1302 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1303 /* 8548 has a dummy entry for now. */
1304 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1305 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1306 {"970", PROCESSOR_POWER4,
1307 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1308 {"cell", PROCESSOR_CELL,
1309 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1310 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1311 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1312 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1313 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1314 {"G5", PROCESSOR_POWER4,
1315 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1316 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1317 {"power2", PROCESSOR_POWER,
1318 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1319 {"power3", PROCESSOR_PPC630,
1320 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1321 {"power4", PROCESSOR_POWER4,
1322 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1323 {"power5", PROCESSOR_POWER5,
1324 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1325 | MASK_MFCRF | MASK_POPCNTB},
1326 {"power5+", PROCESSOR_POWER5,
1327 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1328 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1329 {"power6", PROCESSOR_POWER6,
1330 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1331 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1332 {"power6x", PROCESSOR_POWER6,
1333 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1334 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1335 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1336 {"powerpc64", PROCESSOR_POWERPC64,
1337 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1338 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1339 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1340 {"rios2", PROCESSOR_RIOS2,
1341 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1342 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1343 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1344 {"rs64", PROCESSOR_RS64A,
1345 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1348 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1350 /* Some OSs don't support saving the high part of 64-bit registers on
1351 context switch. Other OSs don't support saving Altivec registers.
1352 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1353 settings; if the user wants either, the user must explicitly specify
1354 them and we won't interfere with the user's specification. */
1357 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1358 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1359 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1360 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1361 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1364 rs6000_init_hard_regno_mode_ok ();
1366 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1367 #ifdef OS_MISSING_POWERPC64
1368 if (OS_MISSING_POWERPC64)
1369 set_masks &= ~MASK_POWERPC64;
1371 #ifdef OS_MISSING_ALTIVEC
1372 if (OS_MISSING_ALTIVEC)
1373 set_masks &= ~MASK_ALTIVEC;
1376 /* Don't override by the processor default if given explicitly. */
1377 set_masks &= ~target_flags_explicit;
1379 /* Identify the processor type. */
1380 rs6000_select[0].string = default_cpu;
1381 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1383 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1385 ptr = &rs6000_select[i];
1386 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1388 for (j = 0; j < ptt_size; j++)
1389 if (! strcmp (ptr->string, processor_target_table[j].name))
1391 if (ptr->set_tune_p)
1392 rs6000_cpu = processor_target_table[j].processor;
1394 if (ptr->set_arch_p)
1396 target_flags &= ~set_masks;
1397 target_flags |= (processor_target_table[j].target_enable
1404 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1411 /* If we are optimizing big endian systems for space, use the load/store
1412 multiple and string instructions. */
1413 if (BYTES_BIG_ENDIAN && optimize_size)
1414 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1416 /* Don't allow -mmultiple or -mstring on little endian systems
1417 unless the cpu is a 750, because the hardware doesn't support the
1418 instructions used in little endian mode, and causes an alignment
1419 trap. The 750 does not cause an alignment trap (except when the
1420 target is unaligned). */
1422 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1424 if (TARGET_MULTIPLE)
1426 target_flags &= ~MASK_MULTIPLE;
1427 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1428 warning (0, "-mmultiple is not supported on little endian systems");
1433 target_flags &= ~MASK_STRING;
1434 if ((target_flags_explicit & MASK_STRING) != 0)
1435 warning (0, "-mstring is not supported on little endian systems");
1439 /* Set debug flags */
1440 if (rs6000_debug_name)
1442 if (! strcmp (rs6000_debug_name, "all"))
1443 rs6000_debug_stack = rs6000_debug_arg = 1;
1444 else if (! strcmp (rs6000_debug_name, "stack"))
1445 rs6000_debug_stack = 1;
1446 else if (! strcmp (rs6000_debug_name, "arg"))
1447 rs6000_debug_arg = 1;
1449 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1452 if (rs6000_traceback_name)
1454 if (! strncmp (rs6000_traceback_name, "full", 4))
1455 rs6000_traceback = traceback_full;
1456 else if (! strncmp (rs6000_traceback_name, "part", 4))
1457 rs6000_traceback = traceback_part;
1458 else if (! strncmp (rs6000_traceback_name, "no", 2))
1459 rs6000_traceback = traceback_none;
1461 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1462 rs6000_traceback_name);
1465 if (!rs6000_explicit_options.long_double)
1466 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1468 #ifndef POWERPC_LINUX
1469 if (!rs6000_explicit_options.ieee)
1470 rs6000_ieeequad = 1;
1473 /* Set Altivec ABI as default for powerpc64 linux. */
1474 if (TARGET_ELF && TARGET_64BIT)
1476 rs6000_altivec_abi = 1;
1477 TARGET_ALTIVEC_VRSAVE = 1;
1480 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1481 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1483 rs6000_darwin64_abi = 1;
1485 darwin_one_byte_bool = 1;
1487 /* Default to natural alignment, for better performance. */
1488 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1491 /* Place FP constants in the constant pool instead of TOC
1492 if section anchors enabled. */
1493 if (flag_section_anchors)
1494 TARGET_NO_FP_IN_TOC = 1;
1496 /* Handle -mtls-size option. */
1497 rs6000_parse_tls_size_option ();
1499 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1500 SUBTARGET_OVERRIDE_OPTIONS;
1502 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1503 SUBSUBTARGET_OVERRIDE_OPTIONS;
1505 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1506 SUB3TARGET_OVERRIDE_OPTIONS;
1511 /* The e500 does not have string instructions, and we set
1512 MASK_STRING above when optimizing for size. */
1513 if ((target_flags & MASK_STRING) != 0)
1514 target_flags = target_flags & ~MASK_STRING;
1516 else if (rs6000_select[1].string != NULL)
1518 /* For the powerpc-eabispe configuration, we set all these by
1519 default, so let's unset them if we manually set another
1520 CPU that is not the E500. */
1521 if (!rs6000_explicit_options.abi)
1523 if (!rs6000_explicit_options.spe)
1525 if (!rs6000_explicit_options.float_gprs)
1526 rs6000_float_gprs = 0;
1527 if (!rs6000_explicit_options.isel)
1531 /* Detect invalid option combinations with E500. */
1534 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1535 && rs6000_cpu != PROCESSOR_POWER5
1536 && rs6000_cpu != PROCESSOR_POWER6
1537 && rs6000_cpu != PROCESSOR_CELL);
1538 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1539 || rs6000_cpu == PROCESSOR_POWER5);
1540 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1541 || rs6000_cpu == PROCESSOR_POWER5
1542 || rs6000_cpu == PROCESSOR_POWER6);
1544 rs6000_sched_restricted_insns_priority
1545 = (rs6000_sched_groups ? 1 : 0);
1547 /* Handle -msched-costly-dep option. */
1548 rs6000_sched_costly_dep
1549 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1551 if (rs6000_sched_costly_dep_str)
1553 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1554 rs6000_sched_costly_dep = no_dep_costly;
1555 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1556 rs6000_sched_costly_dep = all_deps_costly;
1557 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1558 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1559 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1560 rs6000_sched_costly_dep = store_to_load_dep_costly;
1562 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1565 /* Handle -minsert-sched-nops option. */
1566 rs6000_sched_insert_nops
1567 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1569 if (rs6000_sched_insert_nops_str)
1571 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1572 rs6000_sched_insert_nops = sched_finish_none;
1573 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1574 rs6000_sched_insert_nops = sched_finish_pad_groups;
1575 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1576 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1578 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1581 #ifdef TARGET_REGNAMES
1582 /* If the user desires alternate register names, copy in the
1583 alternate names now. */
1584 if (TARGET_REGNAMES)
1585 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1588 /* Set aix_struct_return last, after the ABI is determined.
1589 If -maix-struct-return or -msvr4-struct-return was explicitly
1590 used, don't override with the ABI default. */
1591 if (!rs6000_explicit_options.aix_struct_ret)
1592 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1594 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1595 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1598 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1600 /* We can only guarantee the availability of DI pseudo-ops when
1601 assembling for 64-bit targets. */
1604 targetm.asm_out.aligned_op.di = NULL;
1605 targetm.asm_out.unaligned_op.di = NULL;
1608 /* Set branch target alignment, if not optimizing for size. */
1611 /* Cell wants to be aligned 8byte for dual issue. */
1612 if (rs6000_cpu == PROCESSOR_CELL)
1614 if (align_functions <= 0)
1615 align_functions = 8;
1616 if (align_jumps <= 0)
1618 if (align_loops <= 0)
1621 if (rs6000_align_branch_targets)
1623 if (align_functions <= 0)
1624 align_functions = 16;
1625 if (align_jumps <= 0)
1627 if (align_loops <= 0)
1630 if (align_jumps_max_skip <= 0)
1631 align_jumps_max_skip = 15;
1632 if (align_loops_max_skip <= 0)
1633 align_loops_max_skip = 15;
1636 /* Arrange to save and restore machine status around nested functions. */
1637 init_machine_status = rs6000_init_machine_status;
1639 /* We should always be splitting complex arguments, but we can't break
1640 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1641 if (DEFAULT_ABI != ABI_AIX)
1642 targetm.calls.split_complex_arg = NULL;
1644 /* Initialize rs6000_cost with the appropriate target costs. */
1646 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1650 case PROCESSOR_RIOS1:
1651 rs6000_cost = &rios1_cost;
1654 case PROCESSOR_RIOS2:
1655 rs6000_cost = &rios2_cost;
1658 case PROCESSOR_RS64A:
1659 rs6000_cost = &rs64a_cost;
1662 case PROCESSOR_MPCCORE:
1663 rs6000_cost = &mpccore_cost;
1666 case PROCESSOR_PPC403:
1667 rs6000_cost = &ppc403_cost;
1670 case PROCESSOR_PPC405:
1671 rs6000_cost = &ppc405_cost;
1674 case PROCESSOR_PPC440:
1675 rs6000_cost = &ppc440_cost;
1678 case PROCESSOR_PPC601:
1679 rs6000_cost = &ppc601_cost;
1682 case PROCESSOR_PPC603:
1683 rs6000_cost = &ppc603_cost;
1686 case PROCESSOR_PPC604:
1687 rs6000_cost = &ppc604_cost;
1690 case PROCESSOR_PPC604e:
1691 rs6000_cost = &ppc604e_cost;
1694 case PROCESSOR_PPC620:
1695 rs6000_cost = &ppc620_cost;
1698 case PROCESSOR_PPC630:
1699 rs6000_cost = &ppc630_cost;
1702 case PROCESSOR_CELL:
1703 rs6000_cost = &ppccell_cost;
1706 case PROCESSOR_PPC750:
1707 case PROCESSOR_PPC7400:
1708 rs6000_cost = &ppc750_cost;
1711 case PROCESSOR_PPC7450:
1712 rs6000_cost = &ppc7450_cost;
1715 case PROCESSOR_PPC8540:
1716 rs6000_cost = &ppc8540_cost;
1719 case PROCESSOR_POWER4:
1720 case PROCESSOR_POWER5:
1721 rs6000_cost = &power4_cost;
1724 case PROCESSOR_POWER6:
1725 rs6000_cost = &power6_cost;
1733 /* Implement targetm.vectorize.builtin_mask_for_load. */
1735 rs6000_builtin_mask_for_load (void)
1738 return altivec_builtin_mask_for_load;
1743 /* Implement targetm.vectorize.builtin_conversion. */
1745 rs6000_builtin_conversion (enum tree_code code, tree type)
1747 if (!TARGET_ALTIVEC)
1753 switch (TYPE_MODE (type))
1756 return TYPE_UNSIGNED (type) ?
1757 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1758 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1767 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1769 rs6000_builtin_mul_widen_even (tree type)
1771 if (!TARGET_ALTIVEC)
1774 switch (TYPE_MODE (type))
1777 return TYPE_UNSIGNED (type) ?
1778 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1779 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1782 return TYPE_UNSIGNED (type) ?
1783 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1784 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1790 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1792 rs6000_builtin_mul_widen_odd (tree type)
1794 if (!TARGET_ALTIVEC)
1797 switch (TYPE_MODE (type))
1800 return TYPE_UNSIGNED (type) ?
1801 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1802 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1805 return TYPE_UNSIGNED (type) ?
1806 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1807 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1814 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1815 after applying N number of iterations. This routine does not determine
1816 how may iterations are required to reach desired alignment. */
1819 rs6000_vector_alignment_reachable (tree type ATTRIBUTE_UNUSED, bool is_packed)
1826 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1829 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1839 /* Assuming that all other types are naturally aligned. CHECKME! */
1844 /* Handle generic options of the form -mfoo=yes/no.
1845 NAME is the option name.
1846 VALUE is the option value.
1847 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1848 whether the option value is 'yes' or 'no' respectively. */
1850 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1854 else if (!strcmp (value, "yes"))
1856 else if (!strcmp (value, "no"))
1859 error ("unknown -m%s= option specified: '%s'", name, value);
1862 /* Validate and record the size specified with the -mtls-size option. */
1865 rs6000_parse_tls_size_option (void)
1867 if (rs6000_tls_size_string == 0)
1869 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1870 rs6000_tls_size = 16;
1871 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1872 rs6000_tls_size = 32;
1873 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1874 rs6000_tls_size = 64;
1876 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1880 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1882 if (DEFAULT_ABI == ABI_DARWIN)
1883 /* The Darwin libraries never set errno, so we might as well
1884 avoid calling them when that's the only reason we would. */
1885 flag_errno_math = 0;
1887 /* Double growth factor to counter reduced min jump length. */
1888 set_param_value ("max-grow-copy-bb-insns", 16);
1890 /* Enable section anchors by default.
1891 Skip section anchors for Objective C and Objective C++
1892 until front-ends fixed. */
1893 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
1894 flag_section_anchors = 1;
1897 /* Implement TARGET_HANDLE_OPTION. */
1900 rs6000_handle_option (size_t code, const char *arg, int value)
1905 target_flags &= ~(MASK_POWER | MASK_POWER2
1906 | MASK_MULTIPLE | MASK_STRING);
1907 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1908 | MASK_MULTIPLE | MASK_STRING);
1910 case OPT_mno_powerpc:
1911 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1912 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1913 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1914 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1917 target_flags &= ~MASK_MINIMAL_TOC;
1918 TARGET_NO_FP_IN_TOC = 0;
1919 TARGET_NO_SUM_IN_TOC = 0;
1920 target_flags_explicit |= MASK_MINIMAL_TOC;
1921 #ifdef TARGET_USES_SYSV4_OPT
1922 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1923 just the same as -mminimal-toc. */
1924 target_flags |= MASK_MINIMAL_TOC;
1925 target_flags_explicit |= MASK_MINIMAL_TOC;
1929 #ifdef TARGET_USES_SYSV4_OPT
1931 /* Make -mtoc behave like -mminimal-toc. */
1932 target_flags |= MASK_MINIMAL_TOC;
1933 target_flags_explicit |= MASK_MINIMAL_TOC;
1937 #ifdef TARGET_USES_AIX64_OPT
1942 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
1943 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
1944 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
1947 #ifdef TARGET_USES_AIX64_OPT
1952 target_flags &= ~MASK_POWERPC64;
1953 target_flags_explicit |= MASK_POWERPC64;
1956 case OPT_minsert_sched_nops_:
1957 rs6000_sched_insert_nops_str = arg;
1960 case OPT_mminimal_toc:
1963 TARGET_NO_FP_IN_TOC = 0;
1964 TARGET_NO_SUM_IN_TOC = 0;
1971 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1972 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1979 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1980 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1984 case OPT_mpowerpc_gpopt:
1985 case OPT_mpowerpc_gfxopt:
1988 target_flags |= MASK_POWERPC;
1989 target_flags_explicit |= MASK_POWERPC;
1993 case OPT_maix_struct_return:
1994 case OPT_msvr4_struct_return:
1995 rs6000_explicit_options.aix_struct_ret = true;
1999 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2003 rs6000_explicit_options.isel = true;
2004 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2008 rs6000_explicit_options.spe = true;
2009 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2013 rs6000_debug_name = arg;
2016 #ifdef TARGET_USES_SYSV4_OPT
2018 rs6000_abi_name = arg;
2022 rs6000_sdata_name = arg;
2025 case OPT_mtls_size_:
2026 rs6000_tls_size_string = arg;
2029 case OPT_mrelocatable:
2032 target_flags |= MASK_MINIMAL_TOC;
2033 target_flags_explicit |= MASK_MINIMAL_TOC;
2034 TARGET_NO_FP_IN_TOC = 1;
2038 case OPT_mrelocatable_lib:
2041 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2042 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2043 TARGET_NO_FP_IN_TOC = 1;
2047 target_flags &= ~MASK_RELOCATABLE;
2048 target_flags_explicit |= MASK_RELOCATABLE;
2054 if (!strcmp (arg, "altivec"))
2056 rs6000_explicit_options.abi = true;
2057 rs6000_altivec_abi = 1;
2060 else if (! strcmp (arg, "no-altivec"))
2062 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2063 the default for rs6000_spe_abi to be chosen later. */
2064 rs6000_altivec_abi = 0;
2066 else if (! strcmp (arg, "spe"))
2068 rs6000_explicit_options.abi = true;
2070 rs6000_altivec_abi = 0;
2071 if (!TARGET_SPE_ABI)
2072 error ("not configured for ABI: '%s'", arg);
2074 else if (! strcmp (arg, "no-spe"))
2076 rs6000_explicit_options.abi = true;
2080 /* These are here for testing during development only, do not
2081 document in the manual please. */
2082 else if (! strcmp (arg, "d64"))
2084 rs6000_darwin64_abi = 1;
2085 warning (0, "Using darwin64 ABI");
2087 else if (! strcmp (arg, "d32"))
2089 rs6000_darwin64_abi = 0;
2090 warning (0, "Using old darwin ABI");
2093 else if (! strcmp (arg, "ibmlongdouble"))
2095 rs6000_explicit_options.ieee = true;
2096 rs6000_ieeequad = 0;
2097 warning (0, "Using IBM extended precision long double");
2099 else if (! strcmp (arg, "ieeelongdouble"))
2101 rs6000_explicit_options.ieee = true;
2102 rs6000_ieeequad = 1;
2103 warning (0, "Using IEEE extended precision long double");
2108 error ("unknown ABI specified: '%s'", arg);
2114 rs6000_select[1].string = arg;
2118 rs6000_select[2].string = arg;
2121 case OPT_mtraceback_:
2122 rs6000_traceback_name = arg;
2125 case OPT_mfloat_gprs_:
2126 rs6000_explicit_options.float_gprs = true;
2127 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2128 rs6000_float_gprs = 1;
2129 else if (! strcmp (arg, "double"))
2130 rs6000_float_gprs = 2;
2131 else if (! strcmp (arg, "no"))
2132 rs6000_float_gprs = 0;
2135 error ("invalid option for -mfloat-gprs: '%s'", arg);
2140 case OPT_mlong_double_:
2141 rs6000_explicit_options.long_double = true;
2142 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2143 if (value != 64 && value != 128)
2145 error ("Unknown switch -mlong-double-%s", arg);
2146 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2150 rs6000_long_double_type_size = value;
2153 case OPT_msched_costly_dep_:
2154 rs6000_sched_costly_dep_str = arg;
2158 rs6000_explicit_options.alignment = true;
2159 if (! strcmp (arg, "power"))
2161 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2162 some C library functions, so warn about it. The flag may be
2163 useful for performance studies from time to time though, so
2164 don't disable it entirely. */
2165 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2166 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2167 " it is incompatible with the installed C and C++ libraries");
2168 rs6000_alignment_flags = MASK_ALIGN_POWER;
2170 else if (! strcmp (arg, "natural"))
2171 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2174 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2182 /* Do anything needed at the start of the asm file. */
2185 rs6000_file_start (void)
2189 const char *start = buffer;
2190 struct rs6000_cpu_select *ptr;
2191 const char *default_cpu = TARGET_CPU_DEFAULT;
2192 FILE *file = asm_out_file;
2194 default_file_start ();
2196 #ifdef TARGET_BI_ARCH
2197 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2201 if (flag_verbose_asm)
2203 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2204 rs6000_select[0].string = default_cpu;
2206 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2208 ptr = &rs6000_select[i];
2209 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2211 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2216 if (PPC405_ERRATUM77)
2218 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2222 #ifdef USING_ELFOS_H
2223 switch (rs6000_sdata)
2225 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2226 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2227 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2228 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2231 if (rs6000_sdata && g_switch_value)
2233 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2243 #ifdef HAVE_AS_GNU_ATTRIBUTE
2244 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2245 fprintf (file, "\t.gnu_attribute 4, %d\n",
2246 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2249 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2251 switch_to_section (toc_section);
2252 switch_to_section (text_section);
2257 /* Return nonzero if this function is known to have a null epilogue. */
2260 direct_return (void)
2262 if (reload_completed)
2264 rs6000_stack_t *info = rs6000_stack_info ();
2266 if (info->first_gp_reg_save == 32
2267 && info->first_fp_reg_save == 64
2268 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2269 && ! info->lr_save_p
2270 && ! info->cr_save_p
2271 && info->vrsave_mask == 0
2279 /* Return the number of instructions it takes to form a constant in an
2280 integer register. */
2283 num_insns_constant_wide (HOST_WIDE_INT value)
2285 /* signed constant loadable with {cal|addi} */
2286 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2289 /* constant loadable with {cau|addis} */
2290 else if ((value & 0xffff) == 0
2291 && (value >> 31 == -1 || value >> 31 == 0))
2294 #if HOST_BITS_PER_WIDE_INT == 64
2295 else if (TARGET_POWERPC64)
2297 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2298 HOST_WIDE_INT high = value >> 31;
2300 if (high == 0 || high == -1)
2306 return num_insns_constant_wide (high) + 1;
2308 return (num_insns_constant_wide (high)
2309 + num_insns_constant_wide (low) + 1);
2318 num_insns_constant (rtx op, enum machine_mode mode)
2320 HOST_WIDE_INT low, high;
2322 switch (GET_CODE (op))
2325 #if HOST_BITS_PER_WIDE_INT == 64
2326 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2327 && mask64_operand (op, mode))
2331 return num_insns_constant_wide (INTVAL (op));
2339 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2340 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2341 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2344 if (mode == VOIDmode || mode == DImode)
2346 high = CONST_DOUBLE_HIGH (op);
2347 low = CONST_DOUBLE_LOW (op);
2354 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2355 if (DECIMAL_FLOAT_MODE_P (mode))
2356 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2358 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2359 high = l[WORDS_BIG_ENDIAN == 0];
2360 low = l[WORDS_BIG_ENDIAN != 0];
2364 return (num_insns_constant_wide (low)
2365 + num_insns_constant_wide (high));
2368 if ((high == 0 && low >= 0)
2369 || (high == -1 && low < 0))
2370 return num_insns_constant_wide (low);
2372 else if (mask64_operand (op, mode))
2376 return num_insns_constant_wide (high) + 1;
2379 return (num_insns_constant_wide (high)
2380 + num_insns_constant_wide (low) + 1);
2388 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2389 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2390 corresponding element of the vector, but for V4SFmode and V2SFmode,
2391 the corresponding "float" is interpreted as an SImode integer. */
2393 static HOST_WIDE_INT
2394 const_vector_elt_as_int (rtx op, unsigned int elt)
2396 rtx tmp = CONST_VECTOR_ELT (op, elt);
2397 if (GET_MODE (op) == V4SFmode
2398 || GET_MODE (op) == V2SFmode)
2399 tmp = gen_lowpart (SImode, tmp);
2400 return INTVAL (tmp);
2403 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2404 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2405 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2406 all items are set to the same value and contain COPIES replicas of the
2407 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2408 operand and the others are set to the value of the operand's msb. */
2411 vspltis_constant (rtx op, unsigned step, unsigned copies)
2413 enum machine_mode mode = GET_MODE (op);
2414 enum machine_mode inner = GET_MODE_INNER (mode);
2417 unsigned nunits = GET_MODE_NUNITS (mode);
2418 unsigned bitsize = GET_MODE_BITSIZE (inner);
2419 unsigned mask = GET_MODE_MASK (inner);
2421 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2422 HOST_WIDE_INT splat_val = val;
2423 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2425 /* Construct the value to be splatted, if possible. If not, return 0. */
2426 for (i = 2; i <= copies; i *= 2)
2428 HOST_WIDE_INT small_val;
2430 small_val = splat_val >> bitsize;
2432 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2434 splat_val = small_val;
2437 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2438 if (EASY_VECTOR_15 (splat_val))
2441 /* Also check if we can splat, and then add the result to itself. Do so if
2442 the value is positive, of if the splat instruction is using OP's mode;
2443 for splat_val < 0, the splat and the add should use the same mode. */
2444 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2445 && (splat_val >= 0 || (step == 1 && copies == 1)))
2451 /* Check if VAL is present in every STEP-th element, and the
2452 other elements are filled with its most significant bit. */
2453 for (i = 0; i < nunits - 1; ++i)
2455 HOST_WIDE_INT desired_val;
2456 if (((i + 1) & (step - 1)) == 0)
2459 desired_val = msb_val;
2461 if (desired_val != const_vector_elt_as_int (op, i))
2469 /* Return true if OP is of the given MODE and can be synthesized
2470 with a vspltisb, vspltish or vspltisw. */
2473 easy_altivec_constant (rtx op, enum machine_mode mode)
2475 unsigned step, copies;
2477 if (mode == VOIDmode)
2478 mode = GET_MODE (op);
2479 else if (mode != GET_MODE (op))
2482 /* Start with a vspltisw. */
2483 step = GET_MODE_NUNITS (mode) / 4;
2486 if (vspltis_constant (op, step, copies))
2489 /* Then try with a vspltish. */
2495 if (vspltis_constant (op, step, copies))
2498 /* And finally a vspltisb. */
2504 if (vspltis_constant (op, step, copies))
2510 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2511 result is OP. Abort if it is not possible. */
2514 gen_easy_altivec_constant (rtx op)
2516 enum machine_mode mode = GET_MODE (op);
2517 int nunits = GET_MODE_NUNITS (mode);
2518 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2519 unsigned step = nunits / 4;
2520 unsigned copies = 1;
2522 /* Start with a vspltisw. */
2523 if (vspltis_constant (op, step, copies))
2524 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2526 /* Then try with a vspltish. */
2532 if (vspltis_constant (op, step, copies))
2533 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2535 /* And finally a vspltisb. */
2541 if (vspltis_constant (op, step, copies))
2542 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2548 output_vec_const_move (rtx *operands)
2551 enum machine_mode mode;
2556 mode = GET_MODE (dest);
2561 if (zero_constant (vec, mode))
2562 return "vxor %0,%0,%0";
2564 splat_vec = gen_easy_altivec_constant (vec);
2565 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2566 operands[1] = XEXP (splat_vec, 0);
2567 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2570 switch (GET_MODE (splat_vec))
2573 return "vspltisw %0,%1";
2576 return "vspltish %0,%1";
2579 return "vspltisb %0,%1";
2586 gcc_assert (TARGET_SPE);
2588 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2589 pattern of V1DI, V4HI, and V2SF.
2591 FIXME: We should probably return # and add post reload
2592 splitters for these, but this way is so easy ;-). */
2593 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2594 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2595 operands[1] = CONST_VECTOR_ELT (vec, 0);
2596 operands[2] = CONST_VECTOR_ELT (vec, 1);
2598 return "li %0,%1\n\tevmergelo %0,%0,%0";
2600 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2603 /* Initialize vector TARGET to VALS. */
2606 rs6000_expand_vector_init (rtx target, rtx vals)
2608 enum machine_mode mode = GET_MODE (target);
2609 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2610 int n_elts = GET_MODE_NUNITS (mode);
2611 int n_var = 0, one_var = -1;
2612 bool all_same = true, all_const_zero = true;
2616 for (i = 0; i < n_elts; ++i)
2618 x = XVECEXP (vals, 0, i);
2619 if (!CONSTANT_P (x))
2620 ++n_var, one_var = i;
2621 else if (x != CONST0_RTX (inner_mode))
2622 all_const_zero = false;
2624 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2630 if (mode != V4SFmode && all_const_zero)
2632 /* Zero register. */
2633 emit_insn (gen_rtx_SET (VOIDmode, target,
2634 gen_rtx_XOR (mode, target, target)));
2637 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2639 /* Splat immediate. */
2640 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2644 ; /* Splat vector element. */
2647 /* Load from constant pool. */
2648 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2653 /* Store value to stack temp. Load vector element. Splat. */
2656 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2657 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2658 XVECEXP (vals, 0, 0));
2659 x = gen_rtx_UNSPEC (VOIDmode,
2660 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2661 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2663 gen_rtx_SET (VOIDmode,
2666 x = gen_rtx_VEC_SELECT (inner_mode, target,
2667 gen_rtx_PARALLEL (VOIDmode,
2668 gen_rtvec (1, const0_rtx)));
2669 emit_insn (gen_rtx_SET (VOIDmode, target,
2670 gen_rtx_VEC_DUPLICATE (mode, x)));
2674 /* One field is non-constant. Load constant then overwrite
2678 rtx copy = copy_rtx (vals);
2680 /* Load constant part of vector, substitute neighboring value for
2682 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2683 rs6000_expand_vector_init (target, copy);
2685 /* Insert variable. */
2686 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2690 /* Construct the vector in memory one field at a time
2691 and load the whole vector. */
2692 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2693 for (i = 0; i < n_elts; i++)
2694 emit_move_insn (adjust_address_nv (mem, inner_mode,
2695 i * GET_MODE_SIZE (inner_mode)),
2696 XVECEXP (vals, 0, i));
2697 emit_move_insn (target, mem);
2700 /* Set field ELT of TARGET to VAL. */
2703 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2705 enum machine_mode mode = GET_MODE (target);
2706 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2707 rtx reg = gen_reg_rtx (mode);
2709 int width = GET_MODE_SIZE (inner_mode);
2712 /* Load single variable value. */
2713 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2714 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2715 x = gen_rtx_UNSPEC (VOIDmode,
2716 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2717 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2719 gen_rtx_SET (VOIDmode,
2723 /* Linear sequence. */
2724 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2725 for (i = 0; i < 16; ++i)
2726 XVECEXP (mask, 0, i) = GEN_INT (i);
2728 /* Set permute mask to insert element into target. */
2729 for (i = 0; i < width; ++i)
2730 XVECEXP (mask, 0, elt*width + i)
2731 = GEN_INT (i + 0x10);
2732 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2733 x = gen_rtx_UNSPEC (mode,
2734 gen_rtvec (3, target, reg,
2735 force_reg (V16QImode, x)),
2737 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2740 /* Extract field ELT from VEC into TARGET. */
2743 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2745 enum machine_mode mode = GET_MODE (vec);
2746 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2749 /* Allocate mode-sized buffer. */
2750 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2752 /* Add offset to field within buffer matching vector element. */
2753 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2755 /* Store single field into mode-sized buffer. */
2756 x = gen_rtx_UNSPEC (VOIDmode,
2757 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2758 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2760 gen_rtx_SET (VOIDmode,
2763 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2766 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2767 implement ANDing by the mask IN. */
2769 build_mask64_2_operands (rtx in, rtx *out)
2771 #if HOST_BITS_PER_WIDE_INT >= 64
2772 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2775 gcc_assert (GET_CODE (in) == CONST_INT);
2780 /* Assume c initially something like 0x00fff000000fffff. The idea
2781 is to rotate the word so that the middle ^^^^^^ group of zeros
2782 is at the MS end and can be cleared with an rldicl mask. We then
2783 rotate back and clear off the MS ^^ group of zeros with a
2785 c = ~c; /* c == 0xff000ffffff00000 */
2786 lsb = c & -c; /* lsb == 0x0000000000100000 */
2787 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2788 c = ~c; /* c == 0x00fff000000fffff */
2789 c &= -lsb; /* c == 0x00fff00000000000 */
2790 lsb = c & -c; /* lsb == 0x0000100000000000 */
2791 c = ~c; /* c == 0xff000fffffffffff */
2792 c &= -lsb; /* c == 0xff00000000000000 */
2794 while ((lsb >>= 1) != 0)
2795 shift++; /* shift == 44 on exit from loop */
2796 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2797 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2798 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2802 /* Assume c initially something like 0xff000f0000000000. The idea
2803 is to rotate the word so that the ^^^ middle group of zeros
2804 is at the LS end and can be cleared with an rldicr mask. We then
2805 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2807 lsb = c & -c; /* lsb == 0x0000010000000000 */
2808 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2809 c = ~c; /* c == 0x00fff0ffffffffff */
2810 c &= -lsb; /* c == 0x00fff00000000000 */
2811 lsb = c & -c; /* lsb == 0x0000100000000000 */
2812 c = ~c; /* c == 0xff000fffffffffff */
2813 c &= -lsb; /* c == 0xff00000000000000 */
2815 while ((lsb >>= 1) != 0)
2816 shift++; /* shift == 44 on exit from loop */
2817 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2818 m1 >>= shift; /* m1 == 0x0000000000000fff */
2819 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2822 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2823 masks will be all 1's. We are guaranteed more than one transition. */
2824 out[0] = GEN_INT (64 - shift);
2825 out[1] = GEN_INT (m1);
2826 out[2] = GEN_INT (shift);
2827 out[3] = GEN_INT (m2);
2835 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2838 invalid_e500_subreg (rtx op, enum machine_mode mode)
2840 if (TARGET_E500_DOUBLE)
2842 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
2843 subreg:TI and reg:TF. */
2844 if (GET_CODE (op) == SUBREG
2845 && (mode == SImode || mode == DImode || mode == TImode)
2846 && REG_P (SUBREG_REG (op))
2847 && (GET_MODE (SUBREG_REG (op)) == DFmode
2848 || GET_MODE (SUBREG_REG (op)) == TFmode))
2851 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
2853 if (GET_CODE (op) == SUBREG
2854 && (mode == DFmode || mode == TFmode)
2855 && REG_P (SUBREG_REG (op))
2856 && (GET_MODE (SUBREG_REG (op)) == DImode
2857 || GET_MODE (SUBREG_REG (op)) == TImode))
2862 && GET_CODE (op) == SUBREG
2864 && REG_P (SUBREG_REG (op))
2865 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
2871 /* AIX increases natural record alignment to doubleword if the first
2872 field is an FP double while the FP fields remain word aligned. */
2875 rs6000_special_round_type_align (tree type, unsigned int computed,
2876 unsigned int specified)
2878 unsigned int align = MAX (computed, specified);
2879 tree field = TYPE_FIELDS (type);
2881 /* Skip all non field decls */
2882 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2883 field = TREE_CHAIN (field);
2885 if (field != NULL && field != type)
2887 type = TREE_TYPE (field);
2888 while (TREE_CODE (type) == ARRAY_TYPE)
2889 type = TREE_TYPE (type);
2891 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
2892 align = MAX (align, 64);
2898 /* Darwin increases record alignment to the natural alignment of
2902 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
2903 unsigned int specified)
2905 unsigned int align = MAX (computed, specified);
2907 if (TYPE_PACKED (type))
2910 /* Find the first field, looking down into aggregates. */
2912 tree field = TYPE_FIELDS (type);
2913 /* Skip all non field decls */
2914 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2915 field = TREE_CHAIN (field);
2918 type = TREE_TYPE (field);
2919 while (TREE_CODE (type) == ARRAY_TYPE)
2920 type = TREE_TYPE (type);
2921 } while (AGGREGATE_TYPE_P (type));
2923 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
2924 align = MAX (align, TYPE_ALIGN (type));
2929 /* Return 1 for an operand in small memory on V.4/eabi. */
2932 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2933 enum machine_mode mode ATTRIBUTE_UNUSED)
2938 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2941 if (DEFAULT_ABI != ABI_V4)
2944 if (GET_CODE (op) == SYMBOL_REF)
2947 else if (GET_CODE (op) != CONST
2948 || GET_CODE (XEXP (op, 0)) != PLUS
2949 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2950 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2955 rtx sum = XEXP (op, 0);
2956 HOST_WIDE_INT summand;
2958 /* We have to be careful here, because it is the referenced address
2959 that must be 32k from _SDA_BASE_, not just the symbol. */
2960 summand = INTVAL (XEXP (sum, 1));
2961 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2964 sym_ref = XEXP (sum, 0);
2967 return SYMBOL_REF_SMALL_P (sym_ref);
2973 /* Return true if either operand is a general purpose register. */
2976 gpr_or_gpr_p (rtx op0, rtx op1)
2978 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2979 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2983 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2986 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2988 switch (GET_CODE (op))
2991 if (RS6000_SYMBOL_REF_TLS_P (op))
2993 else if (CONSTANT_POOL_ADDRESS_P (op))
2995 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3003 else if (! strcmp (XSTR (op, 0), toc_label_name))
3012 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3013 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3015 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3024 constant_pool_expr_p (rtx op)
3028 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3032 toc_relative_expr_p (rtx op)
3036 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3040 legitimate_constant_pool_address_p (rtx x)
3043 && GET_CODE (x) == PLUS
3044 && GET_CODE (XEXP (x, 0)) == REG
3045 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3046 && constant_pool_expr_p (XEXP (x, 1)));
3050 legitimate_small_data_p (enum machine_mode mode, rtx x)
3052 return (DEFAULT_ABI == ABI_V4
3053 && !flag_pic && !TARGET_TOC
3054 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3055 && small_data_operand (x, mode));
3058 /* SPE offset addressing is limited to 5-bits worth of double words. */
3059 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3062 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3064 unsigned HOST_WIDE_INT offset, extra;
3066 if (GET_CODE (x) != PLUS)
3068 if (GET_CODE (XEXP (x, 0)) != REG)
3070 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3072 if (legitimate_constant_pool_address_p (x))
3074 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3077 offset = INTVAL (XEXP (x, 1));
3085 /* AltiVec vector modes. Only reg+reg addressing is valid and
3086 constant offset zero should not occur due to canonicalization.
3087 Allow any offset when not strict before reload. */
3094 /* SPE vector modes. */
3095 return SPE_CONST_OFFSET_OK (offset);
3099 if (TARGET_E500_DOUBLE)
3100 return SPE_CONST_OFFSET_OK (offset);
3103 /* On e500v2, we may have:
3105 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3107 Which gets addressed with evldd instructions. */
3108 if (TARGET_E500_DOUBLE)
3109 return SPE_CONST_OFFSET_OK (offset);
3111 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3113 else if (offset & 3)
3118 if (TARGET_E500_DOUBLE)
3119 return (SPE_CONST_OFFSET_OK (offset)
3120 && SPE_CONST_OFFSET_OK (offset + 8));
3124 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3126 else if (offset & 3)
3137 return (offset < 0x10000) && (offset + extra < 0x10000);
3141 legitimate_indexed_address_p (rtx x, int strict)
3145 if (GET_CODE (x) != PLUS)
3151 /* Recognize the rtl generated by reload which we know will later be
3152 replaced with proper base and index regs. */
3154 && reload_in_progress
3155 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3159 return (REG_P (op0) && REG_P (op1)
3160 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3161 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3162 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3163 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3167 legitimate_indirect_address_p (rtx x, int strict)
3169 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3173 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3175 if (!TARGET_MACHO || !flag_pic
3176 || mode != SImode || GET_CODE (x) != MEM)
3180 if (GET_CODE (x) != LO_SUM)
3182 if (GET_CODE (XEXP (x, 0)) != REG)
3184 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3188 return CONSTANT_P (x);
3192 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3194 if (GET_CODE (x) != LO_SUM)
3196 if (GET_CODE (XEXP (x, 0)) != REG)
3198 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3200 /* Restrict addressing for DI because of our SUBREG hackery. */
3201 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3206 if (TARGET_ELF || TARGET_MACHO)
3208 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3212 if (GET_MODE_NUNITS (mode) != 1)
3214 if (GET_MODE_BITSIZE (mode) > 64
3215 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3216 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3219 return CONSTANT_P (x);
3226 /* Try machine-dependent ways of modifying an illegitimate address
3227 to be legitimate. If we find one, return the new, valid address.
3228 This is used from only one place: `memory_address' in explow.c.
3230 OLDX is the address as it was before break_out_memory_refs was
3231 called. In some cases it is useful to look at this to decide what
3234 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3236 It is always safe for this function to do nothing. It exists to
3237 recognize opportunities to optimize the output.
3239 On RS/6000, first check for the sum of a register with a constant
3240 integer that is out of range. If so, generate code to add the
3241 constant with the low-order 16 bits masked to the register and force
3242 this result into another register (this can be done with `cau').
3243 Then generate an address of REG+(CONST&0xffff), allowing for the
3244 possibility of bit 16 being a one.
3246 Then check for the sum of a register and something not constant, try to
3247 load the other things into a register and return the sum. */
3250 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3251 enum machine_mode mode)
3253 if (GET_CODE (x) == SYMBOL_REF)
3255 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3257 return rs6000_legitimize_tls_address (x, model);
3260 if (GET_CODE (x) == PLUS
3261 && GET_CODE (XEXP (x, 0)) == REG
3262 && GET_CODE (XEXP (x, 1)) == CONST_INT
3263 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
3265 HOST_WIDE_INT high_int, low_int;
3267 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3268 high_int = INTVAL (XEXP (x, 1)) - low_int;
3269 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3270 GEN_INT (high_int)), 0);
3271 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3273 else if (GET_CODE (x) == PLUS
3274 && GET_CODE (XEXP (x, 0)) == REG
3275 && GET_CODE (XEXP (x, 1)) != CONST_INT
3276 && GET_MODE_NUNITS (mode) == 1
3277 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3279 || (((mode != DImode && mode != DFmode && mode != DDmode)
3280 || TARGET_E500_DOUBLE)
3281 && mode != TFmode && mode != TDmode))
3282 && (TARGET_POWERPC64 || mode != DImode)
3285 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3286 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3288 else if (ALTIVEC_VECTOR_MODE (mode))
3292 /* Make sure both operands are registers. */
3293 if (GET_CODE (x) == PLUS)
3294 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3295 force_reg (Pmode, XEXP (x, 1)));
3297 reg = force_reg (Pmode, x);
3300 else if (SPE_VECTOR_MODE (mode)
3301 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3302 || mode == DDmode || mode == TDmode
3303 || mode == DImode)))
3307 /* We accept [reg + reg] and [reg + OFFSET]. */
3309 if (GET_CODE (x) == PLUS)
3311 rtx op1 = XEXP (x, 0);
3312 rtx op2 = XEXP (x, 1);
3314 op1 = force_reg (Pmode, op1);
3316 if (GET_CODE (op2) != REG
3317 && (GET_CODE (op2) != CONST_INT
3318 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3319 op2 = force_reg (Pmode, op2);
3321 return gen_rtx_PLUS (Pmode, op1, op2);
3324 return force_reg (Pmode, x);
3330 && GET_CODE (x) != CONST_INT
3331 && GET_CODE (x) != CONST_DOUBLE
3333 && GET_MODE_NUNITS (mode) == 1
3334 && (GET_MODE_BITSIZE (mode) <= 32
3335 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3337 rtx reg = gen_reg_rtx (Pmode);
3338 emit_insn (gen_elf_high (reg, x));
3339 return gen_rtx_LO_SUM (Pmode, reg, x);
3341 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3344 && ! MACHO_DYNAMIC_NO_PIC_P
3346 && GET_CODE (x) != CONST_INT
3347 && GET_CODE (x) != CONST_DOUBLE
3349 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3353 rtx reg = gen_reg_rtx (Pmode);
3354 emit_insn (gen_macho_high (reg, x));
3355 return gen_rtx_LO_SUM (Pmode, reg, x);
3358 && constant_pool_expr_p (x)
3359 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3361 return create_TOC_reference (x);
3367 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3368 We need to emit DTP-relative relocations. */
3371 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3376 fputs ("\t.long\t", file);
3379 fputs (DOUBLE_INT_ASM_OP, file);
3384 output_addr_const (file, x);
3385 fputs ("@dtprel+0x8000", file);
3388 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3390 static GTY(()) rtx rs6000_tls_symbol;
3392 rs6000_tls_get_addr (void)
3394 if (!rs6000_tls_symbol)
3395 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3397 return rs6000_tls_symbol;
3400 /* Construct the SYMBOL_REF for TLS GOT references. */
3402 static GTY(()) rtx rs6000_got_symbol;
3404 rs6000_got_sym (void)
3406 if (!rs6000_got_symbol)
3408 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3409 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3410 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3413 return rs6000_got_symbol;
3416 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3417 this (thread-local) address. */
3420 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3424 dest = gen_reg_rtx (Pmode);
3425 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3431 tlsreg = gen_rtx_REG (Pmode, 13);
3432 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3436 tlsreg = gen_rtx_REG (Pmode, 2);
3437 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3441 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3445 tmp = gen_reg_rtx (Pmode);
3448 tlsreg = gen_rtx_REG (Pmode, 13);
3449 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3453 tlsreg = gen_rtx_REG (Pmode, 2);
3454 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3458 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3460 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3465 rtx r3, got, tga, tmp1, tmp2, eqv;
3467 /* We currently use relocations like @got@tlsgd for tls, which
3468 means the linker will handle allocation of tls entries, placing
3469 them in the .got section. So use a pointer to the .got section,
3470 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3471 or to secondary GOT sections used by 32-bit -fPIC. */
3473 got = gen_rtx_REG (Pmode, 2);
3477 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3480 rtx gsym = rs6000_got_sym ();
3481 got = gen_reg_rtx (Pmode);
3483 rs6000_emit_move (got, gsym, Pmode);
3489 tmp1 = gen_reg_rtx (Pmode);
3490 tmp2 = gen_reg_rtx (Pmode);
3491 tmp3 = gen_reg_rtx (Pmode);
3492 mem = gen_const_mem (Pmode, tmp1);
3494 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3495 emit_move_insn (tmp1,
3496 gen_rtx_REG (Pmode, LR_REGNO));
3497 emit_move_insn (tmp2, mem);
3498 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3499 last = emit_move_insn (got, tmp3);
3500 set_unique_reg_note (last, REG_EQUAL, gsym);
3501 maybe_encapsulate_block (first, last, gsym);
3506 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3508 r3 = gen_rtx_REG (Pmode, 3);
3510 insn = gen_tls_gd_64 (r3, got, addr);
3512 insn = gen_tls_gd_32 (r3, got, addr);
3515 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3516 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3517 insn = emit_call_insn (insn);
3518 CONST_OR_PURE_CALL_P (insn) = 1;
3519 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3520 insn = get_insns ();
3522 emit_libcall_block (insn, dest, r3, addr);
3524 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3526 r3 = gen_rtx_REG (Pmode, 3);
3528 insn = gen_tls_ld_64 (r3, got);
3530 insn = gen_tls_ld_32 (r3, got);
3533 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3534 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3535 insn = emit_call_insn (insn);
3536 CONST_OR_PURE_CALL_P (insn) = 1;
3537 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3538 insn = get_insns ();
3540 tmp1 = gen_reg_rtx (Pmode);
3541 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3543 emit_libcall_block (insn, tmp1, r3, eqv);
3544 if (rs6000_tls_size == 16)
3547 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3549 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3551 else if (rs6000_tls_size == 32)
3553 tmp2 = gen_reg_rtx (Pmode);
3555 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3557 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3560 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3562 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3566 tmp2 = gen_reg_rtx (Pmode);
3568 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3570 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3572 insn = gen_rtx_SET (Pmode, dest,
3573 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3579 /* IE, or 64-bit offset LE. */
3580 tmp2 = gen_reg_rtx (Pmode);
3582 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3584 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3587 insn = gen_tls_tls_64 (dest, tmp2, addr);
3589 insn = gen_tls_tls_32 (dest, tmp2, addr);
3597 /* Return 1 if X contains a thread-local symbol. */
3600 rs6000_tls_referenced_p (rtx x)
3602 if (! TARGET_HAVE_TLS)
3605 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3608 /* Return 1 if *X is a thread-local symbol. This is the same as
3609 rs6000_tls_symbol_ref except for the type of the unused argument. */
3612 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3614 return RS6000_SYMBOL_REF_TLS_P (*x);
3617 /* The convention appears to be to define this wherever it is used.
3618 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3619 is now used here. */
3620 #ifndef REG_MODE_OK_FOR_BASE_P
3621 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3624 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3625 replace the input X, or the original X if no replacement is called for.
3626 The output parameter *WIN is 1 if the calling macro should goto WIN,
3629 For RS/6000, we wish to handle large displacements off a base
3630 register by splitting the addend across an addiu/addis and the mem insn.
3631 This cuts number of extra insns needed from 3 to 1.
3633 On Darwin, we use this to generate code for floating point constants.
3634 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3635 The Darwin code is inside #if TARGET_MACHO because only then is
3636 machopic_function_base_name() defined. */
3638 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3639 int opnum, int type,
3640 int ind_levels ATTRIBUTE_UNUSED, int *win)
3642 /* We must recognize output that we have already generated ourselves. */
3643 if (GET_CODE (x) == PLUS
3644 && GET_CODE (XEXP (x, 0)) == PLUS
3645 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3646 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3647 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3649 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3650 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3651 opnum, (enum reload_type)type);
3657 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3658 && GET_CODE (x) == LO_SUM
3659 && GET_CODE (XEXP (x, 0)) == PLUS
3660 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3661 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3662 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3663 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3664 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3665 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3666 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3668 /* Result of previous invocation of this function on Darwin
3669 floating point constant. */
3670 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3671 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3672 opnum, (enum reload_type)type);
3678 /* Force ld/std non-word aligned offset into base register by wrapping
3680 if (GET_CODE (x) == PLUS
3681 && GET_CODE (XEXP (x, 0)) == REG
3682 && REGNO (XEXP (x, 0)) < 32
3683 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3684 && GET_CODE (XEXP (x, 1)) == CONST_INT
3685 && (INTVAL (XEXP (x, 1)) & 3) != 0
3686 && !ALTIVEC_VECTOR_MODE (mode)
3687 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3688 && TARGET_POWERPC64)
3690 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3691 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3692 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3693 opnum, (enum reload_type) type);
3698 if (GET_CODE (x) == PLUS
3699 && GET_CODE (XEXP (x, 0)) == REG
3700 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3701 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3702 && GET_CODE (XEXP (x, 1)) == CONST_INT
3703 && !SPE_VECTOR_MODE (mode)
3704 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3706 && !ALTIVEC_VECTOR_MODE (mode))
3708 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3709 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3711 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3713 /* Check for 32-bit overflow. */
3714 if (high + low != val)
3720 /* Reload the high part into a base reg; leave the low part
3721 in the mem directly. */
3723 x = gen_rtx_PLUS (GET_MODE (x),
3724 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3728 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3729 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3730 opnum, (enum reload_type)type);
3735 if (GET_CODE (x) == SYMBOL_REF
3736 && !ALTIVEC_VECTOR_MODE (mode)
3737 && !SPE_VECTOR_MODE (mode)
3739 && DEFAULT_ABI == ABI_DARWIN
3740 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3742 && DEFAULT_ABI == ABI_V4
3745 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3746 The same goes for DImode without 64-bit gprs and DFmode
3750 && (mode != DImode || TARGET_POWERPC64)
3751 && (mode != DFmode || TARGET_POWERPC64
3752 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3757 rtx offset = gen_rtx_CONST (Pmode,
3758 gen_rtx_MINUS (Pmode, x,
3759 machopic_function_base_sym ()));
3760 x = gen_rtx_LO_SUM (GET_MODE (x),
3761 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3762 gen_rtx_HIGH (Pmode, offset)), offset);
3766 x = gen_rtx_LO_SUM (GET_MODE (x),
3767 gen_rtx_HIGH (Pmode, x), x);
3769 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3770 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3771 opnum, (enum reload_type)type);
3776 /* Reload an offset address wrapped by an AND that represents the
3777 masking of the lower bits. Strip the outer AND and let reload
3778 convert the offset address into an indirect address. */
3780 && ALTIVEC_VECTOR_MODE (mode)
3781 && GET_CODE (x) == AND
3782 && GET_CODE (XEXP (x, 0)) == PLUS
3783 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3784 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3785 && GET_CODE (XEXP (x, 1)) == CONST_INT
3786 && INTVAL (XEXP (x, 1)) == -16)
3794 && constant_pool_expr_p (x)
3795 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3797 x = create_TOC_reference (x);
3805 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3806 that is a valid memory address for an instruction.
3807 The MODE argument is the machine mode for the MEM expression
3808 that wants to use this address.
3810 On the RS/6000, there are four valid address: a SYMBOL_REF that
3811 refers to a constant pool entry of an address (or the sum of it
3812 plus a constant), a short (16-bit signed) constant plus a register,
3813 the sum of two registers, or a register indirect, possibly with an
3814 auto-increment. For DFmode and DImode with a constant plus register,
3815 we must ensure that both words are addressable or PowerPC64 with offset
3818 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3819 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3820 because adjacent memory cells are accessed by adding word-sized offsets
3821 during assembly output. */
3823 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3825 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3827 && ALTIVEC_VECTOR_MODE (mode)
3828 && GET_CODE (x) == AND
3829 && GET_CODE (XEXP (x, 1)) == CONST_INT
3830 && INTVAL (XEXP (x, 1)) == -16)
3833 if (RS6000_SYMBOL_REF_TLS_P (x))
3835 if (legitimate_indirect_address_p (x, reg_ok_strict))
3837 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3838 && !ALTIVEC_VECTOR_MODE (mode)
3839 && !SPE_VECTOR_MODE (mode)
3842 /* Restrict addressing for DI because of our SUBREG hackery. */
3843 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3846 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3848 if (legitimate_small_data_p (mode, x))
3850 if (legitimate_constant_pool_address_p (x))
3852 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3854 && GET_CODE (x) == PLUS
3855 && GET_CODE (XEXP (x, 0)) == REG
3856 && (XEXP (x, 0) == virtual_stack_vars_rtx
3857 || XEXP (x, 0) == arg_pointer_rtx)
3858 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3860 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3865 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3867 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3868 && (TARGET_POWERPC64 || mode != DImode)
3869 && legitimate_indexed_address_p (x, reg_ok_strict))
3871 if (GET_CODE (x) == PRE_MODIFY
3875 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3877 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3878 && (TARGET_POWERPC64 || mode != DImode)
3879 && !ALTIVEC_VECTOR_MODE (mode)
3880 && !SPE_VECTOR_MODE (mode)
3881 /* Restrict addressing for DI because of our SUBREG hackery. */
3882 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3884 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
3885 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
3886 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
3887 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
3889 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3894 /* Go to LABEL if ADDR (a legitimate address expression)
3895 has an effect that depends on the machine mode it is used for.
3897 On the RS/6000 this is true of all integral offsets (since AltiVec
3898 modes don't allow them) or is a pre-increment or decrement.
3900 ??? Except that due to conceptual problems in offsettable_address_p
3901 we can't really report the problems of integral offsets. So leave
3902 this assuming that the adjustable offset must be valid for the
3903 sub-words of a TFmode operand, which is what we had before. */
3906 rs6000_mode_dependent_address (rtx addr)
3908 switch (GET_CODE (addr))
3911 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3913 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3914 return val + 12 + 0x8000 >= 0x10000;
3924 return TARGET_UPDATE;
3933 /* More elaborate version of recog's offsettable_memref_p predicate
3934 that works around the ??? note of rs6000_mode_dependent_address.
3935 In particular it accepts
3937 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
3939 in 32-bit mode, that the recog predicate rejects. */
3942 rs6000_offsettable_memref_p (rtx op)
3947 /* First mimic offsettable_memref_p. */
3948 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
3951 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
3952 the latter predicate knows nothing about the mode of the memory
3953 reference and, therefore, assumes that it is the largest supported
3954 mode (TFmode). As a consequence, legitimate offsettable memory
3955 references are rejected. rs6000_legitimate_offset_address_p contains
3956 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
3957 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
3960 /* Return number of consecutive hard regs needed starting at reg REGNO
3961 to hold something of mode MODE.
3962 This is ordinarily the length in words of a value of mode MODE
3963 but can be less for certain modes in special long registers.
3965 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3966 scalar instructions. The upper 32 bits are only available to the
3969 POWER and PowerPC GPRs hold 32 bits worth;
3970 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3973 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3975 if (FP_REGNO_P (regno))
3976 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3978 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3979 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3981 if (ALTIVEC_REGNO_P (regno))
3983 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3985 /* The value returned for SCmode in the E500 double case is 2 for
3986 ABI compatibility; storing an SCmode value in a single register
3987 would require function_arg and rs6000_spe_function_arg to handle
3988 SCmode so as to pass the value correctly in a pair of
3990 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
3991 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3993 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3996 /* Change register usage conditional on target flags. */
3998 rs6000_conditional_register_usage (void)
4002 /* Set MQ register fixed (already call_used) if not POWER
4003 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4008 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4010 fixed_regs[13] = call_used_regs[13]
4011 = call_really_used_regs[13] = 1;
4013 /* Conditionally disable FPRs. */
4014 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4015 for (i = 32; i < 64; i++)
4016 fixed_regs[i] = call_used_regs[i]
4017 = call_really_used_regs[i] = 1;
4019 /* The TOC register is not killed across calls in a way that is
4020 visible to the compiler. */
4021 if (DEFAULT_ABI == ABI_AIX)
4022 call_really_used_regs[2] = 0;
4024 if (DEFAULT_ABI == ABI_V4
4025 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4027 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4029 if (DEFAULT_ABI == ABI_V4
4030 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4032 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4033 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4034 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4036 if (DEFAULT_ABI == ABI_DARWIN
4037 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4038 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4039 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4040 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4042 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4043 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4044 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4047 global_regs[VSCR_REGNO] = 1;
4051 global_regs[SPEFSCR_REGNO] = 1;
4052 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4053 registers in prologues and epilogues. We no longer use r14
4054 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4055 pool for link-compatibility with older versions of GCC. Once
4056 "old" code has died out, we can return r14 to the allocation
4059 = call_used_regs[14]
4060 = call_really_used_regs[14] = 1;
4063 if (! TARGET_ALTIVEC)
4065 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4066 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4067 call_really_used_regs[VRSAVE_REGNO] = 1;
4070 if (TARGET_ALTIVEC_ABI)
4071 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4072 call_used_regs[i] = call_really_used_regs[i] = 1;
4075 /* Try to output insns to set TARGET equal to the constant C if it can
4076 be done in less than N insns. Do all computations in MODE.
4077 Returns the place where the output has been placed if it can be
4078 done and the insns have been emitted. If it would take more than N
4079 insns, zero is returned and no insns and emitted. */
4082 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4083 rtx source, int n ATTRIBUTE_UNUSED)
4085 rtx result, insn, set;
4086 HOST_WIDE_INT c0, c1;
4093 dest = gen_reg_rtx (mode);
4094 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4098 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4100 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4101 GEN_INT (INTVAL (source)
4102 & (~ (HOST_WIDE_INT) 0xffff))));
4103 emit_insn (gen_rtx_SET (VOIDmode, dest,
4104 gen_rtx_IOR (SImode, copy_rtx (result),
4105 GEN_INT (INTVAL (source) & 0xffff))));
4110 switch (GET_CODE (source))
4113 c0 = INTVAL (source);
4118 #if HOST_BITS_PER_WIDE_INT >= 64
4119 c0 = CONST_DOUBLE_LOW (source);
4122 c0 = CONST_DOUBLE_LOW (source);
4123 c1 = CONST_DOUBLE_HIGH (source);
4131 result = rs6000_emit_set_long_const (dest, c0, c1);
4138 insn = get_last_insn ();
4139 set = single_set (insn);
4140 if (! CONSTANT_P (SET_SRC (set)))
4141 set_unique_reg_note (insn, REG_EQUAL, source);
4146 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4147 fall back to a straight forward decomposition. We do this to avoid
4148 exponential run times encountered when looking for longer sequences
4149 with rs6000_emit_set_const. */
4151 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4153 if (!TARGET_POWERPC64)
4155 rtx operand1, operand2;
4157 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4159 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4161 emit_move_insn (operand1, GEN_INT (c1));
4162 emit_move_insn (operand2, GEN_INT (c2));
4166 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4169 ud2 = (c1 & 0xffff0000) >> 16;
4170 #if HOST_BITS_PER_WIDE_INT >= 64
4174 ud4 = (c2 & 0xffff0000) >> 16;
4176 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4177 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4180 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4182 emit_move_insn (dest, GEN_INT (ud1));
4185 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4186 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4189 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4192 emit_move_insn (dest, GEN_INT (ud2 << 16));
4194 emit_move_insn (copy_rtx (dest),
4195 gen_rtx_IOR (DImode, copy_rtx (dest),
4198 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4199 || (ud4 == 0 && ! (ud3 & 0x8000)))
4202 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4205 emit_move_insn (dest, GEN_INT (ud3 << 16));
4208 emit_move_insn (copy_rtx (dest),
4209 gen_rtx_IOR (DImode, copy_rtx (dest),
4211 emit_move_insn (copy_rtx (dest),
4212 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4215 emit_move_insn (copy_rtx (dest),
4216 gen_rtx_IOR (DImode, copy_rtx (dest),
4222 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4225 emit_move_insn (dest, GEN_INT (ud4 << 16));
4228 emit_move_insn (copy_rtx (dest),
4229 gen_rtx_IOR (DImode, copy_rtx (dest),
4232 emit_move_insn (copy_rtx (dest),
4233 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4236 emit_move_insn (copy_rtx (dest),
4237 gen_rtx_IOR (DImode, copy_rtx (dest),
4238 GEN_INT (ud2 << 16)));
4240 emit_move_insn (copy_rtx (dest),
4241 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4247 /* Helper for the following. Get rid of [r+r] memory refs
4248 in cases where it won't work (TImode, TFmode, TDmode). */
4251 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4253 if (GET_CODE (operands[0]) == MEM
4254 && GET_CODE (XEXP (operands[0], 0)) != REG
4255 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4256 && ! reload_in_progress)
4258 = replace_equiv_address (operands[0],
4259 copy_addr_to_reg (XEXP (operands[0], 0)));
4261 if (GET_CODE (operands[1]) == MEM
4262 && GET_CODE (XEXP (operands[1], 0)) != REG
4263 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4264 && ! reload_in_progress)
4266 = replace_equiv_address (operands[1],
4267 copy_addr_to_reg (XEXP (operands[1], 0)));
4270 /* Emit a move from SOURCE to DEST in mode MODE. */
4272 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4276 operands[1] = source;
4278 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4279 if (GET_CODE (operands[1]) == CONST_DOUBLE
4280 && ! FLOAT_MODE_P (mode)
4281 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4283 /* FIXME. This should never happen. */
4284 /* Since it seems that it does, do the safe thing and convert
4286 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4288 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4289 || FLOAT_MODE_P (mode)
4290 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4291 || CONST_DOUBLE_LOW (operands[1]) < 0)
4292 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4293 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4295 /* Check if GCC is setting up a block move that will end up using FP
4296 registers as temporaries. We must make sure this is acceptable. */
4297 if (GET_CODE (operands[0]) == MEM
4298 && GET_CODE (operands[1]) == MEM
4300 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4301 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4302 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4303 ? 32 : MEM_ALIGN (operands[0])))
4304 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4306 : MEM_ALIGN (operands[1]))))
4307 && ! MEM_VOLATILE_P (operands [0])
4308 && ! MEM_VOLATILE_P (operands [1]))
4310 emit_move_insn (adjust_address (operands[0], SImode, 0),
4311 adjust_address (operands[1], SImode, 0));
4312 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4313 adjust_address (copy_rtx (operands[1]), SImode, 4));
4317 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4318 && !gpc_reg_operand (operands[1], mode))
4319 operands[1] = force_reg (mode, operands[1]);
4321 if (mode == SFmode && ! TARGET_POWERPC
4322 && TARGET_HARD_FLOAT && TARGET_FPRS
4323 && GET_CODE (operands[0]) == MEM)
4327 if (reload_in_progress || reload_completed)
4328 regnum = true_regnum (operands[1]);
4329 else if (GET_CODE (operands[1]) == REG)
4330 regnum = REGNO (operands[1]);
4334 /* If operands[1] is a register, on POWER it may have
4335 double-precision data in it, so truncate it to single
4337 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4340 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4341 : gen_reg_rtx (mode));
4342 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4343 operands[1] = newreg;
4347 /* Recognize the case where operand[1] is a reference to thread-local
4348 data and load its address to a register. */
4349 if (rs6000_tls_referenced_p (operands[1]))
4351 enum tls_model model;
4352 rtx tmp = operands[1];
4355 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4357 addend = XEXP (XEXP (tmp, 0), 1);
4358 tmp = XEXP (XEXP (tmp, 0), 0);
4361 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4362 model = SYMBOL_REF_TLS_MODEL (tmp);
4363 gcc_assert (model != 0);
4365 tmp = rs6000_legitimize_tls_address (tmp, model);
4368 tmp = gen_rtx_PLUS (mode, tmp, addend);
4369 tmp = force_operand (tmp, operands[0]);
4374 /* Handle the case where reload calls us with an invalid address. */
4375 if (reload_in_progress && mode == Pmode
4376 && (! general_operand (operands[1], mode)
4377 || ! nonimmediate_operand (operands[0], mode)))
4380 /* 128-bit constant floating-point values on Darwin should really be
4381 loaded as two parts. */
4382 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4383 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4385 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4386 know how to get a DFmode SUBREG of a TFmode. */
4387 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4388 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4389 simplify_gen_subreg (imode, operands[1], mode, 0),
4391 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4392 GET_MODE_SIZE (imode)),
4393 simplify_gen_subreg (imode, operands[1], mode,
4394 GET_MODE_SIZE (imode)),
4399 /* FIXME: In the long term, this switch statement should go away
4400 and be replaced by a sequence of tests based on things like
4406 if (CONSTANT_P (operands[1])
4407 && GET_CODE (operands[1]) != CONST_INT)
4408 operands[1] = force_const_mem (mode, operands[1]);
4413 rs6000_eliminate_indexed_memrefs (operands);
4419 if (CONSTANT_P (operands[1])
4420 && ! easy_fp_constant (operands[1], mode))
4421 operands[1] = force_const_mem (mode, operands[1]);
4432 if (CONSTANT_P (operands[1])
4433 && !easy_vector_constant (operands[1], mode))
4434 operands[1] = force_const_mem (mode, operands[1]);
4439 /* Use default pattern for address of ELF small data */
4442 && DEFAULT_ABI == ABI_V4
4443 && (GET_CODE (operands[1]) == SYMBOL_REF
4444 || GET_CODE (operands[1]) == CONST)
4445 && small_data_operand (operands[1], mode))
4447 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4451 if (DEFAULT_ABI == ABI_V4
4452 && mode == Pmode && mode == SImode
4453 && flag_pic == 1 && got_operand (operands[1], mode))
4455 emit_insn (gen_movsi_got (operands[0], operands[1]));
4459 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4463 && CONSTANT_P (operands[1])
4464 && GET_CODE (operands[1]) != HIGH
4465 && GET_CODE (operands[1]) != CONST_INT)
4467 rtx target = (!can_create_pseudo_p ()
4469 : gen_reg_rtx (mode));
4471 /* If this is a function address on -mcall-aixdesc,
4472 convert it to the address of the descriptor. */
4473 if (DEFAULT_ABI == ABI_AIX
4474 && GET_CODE (operands[1]) == SYMBOL_REF
4475 && XSTR (operands[1], 0)[0] == '.')
4477 const char *name = XSTR (operands[1], 0);
4479 while (*name == '.')
4481 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4482 CONSTANT_POOL_ADDRESS_P (new_ref)
4483 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4484 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4485 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4486 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4487 operands[1] = new_ref;
4490 if (DEFAULT_ABI == ABI_DARWIN)
4493 if (MACHO_DYNAMIC_NO_PIC_P)
4495 /* Take care of any required data indirection. */
4496 operands[1] = rs6000_machopic_legitimize_pic_address (
4497 operands[1], mode, operands[0]);
4498 if (operands[0] != operands[1])
4499 emit_insn (gen_rtx_SET (VOIDmode,
4500 operands[0], operands[1]));
4504 emit_insn (gen_macho_high (target, operands[1]));
4505 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4509 emit_insn (gen_elf_high (target, operands[1]));
4510 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4514 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4515 and we have put it in the TOC, we just need to make a TOC-relative
4518 && GET_CODE (operands[1]) == SYMBOL_REF
4519 && constant_pool_expr_p (operands[1])
4520 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4521 get_pool_mode (operands[1])))
4523 operands[1] = create_TOC_reference (operands[1]);
4525 else if (mode == Pmode
4526 && CONSTANT_P (operands[1])
4527 && ((GET_CODE (operands[1]) != CONST_INT
4528 && ! easy_fp_constant (operands[1], mode))
4529 || (GET_CODE (operands[1]) == CONST_INT
4530 && num_insns_constant (operands[1], mode) > 2)
4531 || (GET_CODE (operands[0]) == REG
4532 && FP_REGNO_P (REGNO (operands[0]))))
4533 && GET_CODE (operands[1]) != HIGH
4534 && ! legitimate_constant_pool_address_p (operands[1])
4535 && ! toc_relative_expr_p (operands[1]))
4537 /* Emit a USE operation so that the constant isn't deleted if
4538 expensive optimizations are turned on because nobody
4539 references it. This should only be done for operands that
4540 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4541 This should not be done for operands that contain LABEL_REFs.
4542 For now, we just handle the obvious case. */
4543 if (GET_CODE (operands[1]) != LABEL_REF)
4544 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4547 /* Darwin uses a special PIC legitimizer. */
4548 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4551 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4553 if (operands[0] != operands[1])
4554 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4559 /* If we are to limit the number of things we put in the TOC and
4560 this is a symbol plus a constant we can add in one insn,
4561 just put the symbol in the TOC and add the constant. Don't do
4562 this if reload is in progress. */
4563 if (GET_CODE (operands[1]) == CONST
4564 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4565 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4566 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4567 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4568 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4569 && ! side_effects_p (operands[0]))
4572 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4573 rtx other = XEXP (XEXP (operands[1], 0), 1);
4575 sym = force_reg (mode, sym);
4577 emit_insn (gen_addsi3 (operands[0], sym, other));
4579 emit_insn (gen_adddi3 (operands[0], sym, other));
4583 operands[1] = force_const_mem (mode, operands[1]);
4586 && constant_pool_expr_p (XEXP (operands[1], 0))
4587 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4588 get_pool_constant (XEXP (operands[1], 0)),
4589 get_pool_mode (XEXP (operands[1], 0))))
4592 = gen_const_mem (mode,
4593 create_TOC_reference (XEXP (operands[1], 0)));
4594 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4600 rs6000_eliminate_indexed_memrefs (operands);
4604 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4606 gen_rtx_SET (VOIDmode,
4607 operands[0], operands[1]),
4608 gen_rtx_CLOBBER (VOIDmode,
4609 gen_rtx_SCRATCH (SImode)))));
4618 /* Above, we may have called force_const_mem which may have returned
4619 an invalid address. If we can, fix this up; otherwise, reload will
4620 have to deal with it. */
4621 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4622 operands[1] = validize_mem (operands[1]);
4625 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4628 /* Nonzero if we can use a floating-point register to pass this arg. */
4629 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4630 (SCALAR_FLOAT_MODE_P (MODE) \
4631 && (MODE) != SDmode \
4632 && (CUM)->fregno <= FP_ARG_MAX_REG \
4633 && TARGET_HARD_FLOAT && TARGET_FPRS)
4635 /* Nonzero if we can use an AltiVec register to pass this arg. */
4636 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4637 (ALTIVEC_VECTOR_MODE (MODE) \
4638 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4639 && TARGET_ALTIVEC_ABI \
4642 /* Return a nonzero value to say to return the function value in
4643 memory, just as large structures are always returned. TYPE will be
4644 the data type of the value, and FNTYPE will be the type of the
4645 function doing the returning, or @code{NULL} for libcalls.
4647 The AIX ABI for the RS/6000 specifies that all structures are
4648 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4649 specifies that structures <= 8 bytes are returned in r3/r4, but a
4650 draft put them in memory, and GCC used to implement the draft
4651 instead of the final standard. Therefore, aix_struct_return
4652 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4653 compatibility can change DRAFT_V4_STRUCT_RET to override the
4654 default, and -m switches get the final word. See
4655 rs6000_override_options for more details.
4657 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4658 long double support is enabled. These values are returned in memory.
4660 int_size_in_bytes returns -1 for variable size objects, which go in
4661 memory always. The cast to unsigned makes -1 > 8. */
4664 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4666 /* In the darwin64 abi, try to use registers for larger structs
4668 if (rs6000_darwin64_abi
4669 && TREE_CODE (type) == RECORD_TYPE
4670 && int_size_in_bytes (type) > 0)
4672 CUMULATIVE_ARGS valcum;
4676 valcum.fregno = FP_ARG_MIN_REG;
4677 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4678 /* Do a trial code generation as if this were going to be passed
4679 as an argument; if any part goes in memory, we return NULL. */
4680 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4683 /* Otherwise fall through to more conventional ABI rules. */
4686 if (AGGREGATE_TYPE_P (type)
4687 && (aix_struct_return
4688 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4691 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4692 modes only exist for GCC vector types if -maltivec. */
4693 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4694 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4697 /* Return synthetic vectors in memory. */
4698 if (TREE_CODE (type) == VECTOR_TYPE
4699 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4701 static bool warned_for_return_big_vectors = false;
4702 if (!warned_for_return_big_vectors)
4704 warning (0, "GCC vector returned by reference: "
4705 "non-standard ABI extension with no compatibility guarantee");
4706 warned_for_return_big_vectors = true;
4711 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4717 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4718 for a call to a function whose data type is FNTYPE.
4719 For a library call, FNTYPE is 0.
4721 For incoming args we set the number of arguments in the prototype large
4722 so we never return a PARALLEL. */
4725 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4726 rtx libname ATTRIBUTE_UNUSED, int incoming,
4727 int libcall, int n_named_args)
4729 static CUMULATIVE_ARGS zero_cumulative;
4731 *cum = zero_cumulative;
4733 cum->fregno = FP_ARG_MIN_REG;
4734 cum->vregno = ALTIVEC_ARG_MIN_REG;
4735 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4736 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4737 ? CALL_LIBCALL : CALL_NORMAL);
4738 cum->sysv_gregno = GP_ARG_MIN_REG;
4739 cum->stdarg = fntype
4740 && (TYPE_ARG_TYPES (fntype) != 0
4741 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4742 != void_type_node));
4744 cum->nargs_prototype = 0;
4745 if (incoming || cum->prototype)
4746 cum->nargs_prototype = n_named_args;
4748 /* Check for a longcall attribute. */
4749 if ((!fntype && rs6000_default_long_calls)
4751 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4752 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4753 cum->call_cookie |= CALL_LONG;
4755 if (TARGET_DEBUG_ARG)
4757 fprintf (stderr, "\ninit_cumulative_args:");
4760 tree ret_type = TREE_TYPE (fntype);
4761 fprintf (stderr, " ret code = %s,",
4762 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4765 if (cum->call_cookie & CALL_LONG)
4766 fprintf (stderr, " longcall,");
4768 fprintf (stderr, " proto = %d, nargs = %d\n",
4769 cum->prototype, cum->nargs_prototype);
4774 && TARGET_ALTIVEC_ABI
4775 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4777 error ("cannot return value in vector register because"
4778 " altivec instructions are disabled, use -maltivec"
4783 /* Return true if TYPE must be passed on the stack and not in registers. */
4786 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4788 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4789 return must_pass_in_stack_var_size (mode, type);
4791 return must_pass_in_stack_var_size_or_pad (mode, type);
4794 /* If defined, a C expression which determines whether, and in which
4795 direction, to pad out an argument with extra space. The value
4796 should be of type `enum direction': either `upward' to pad above
4797 the argument, `downward' to pad below, or `none' to inhibit
4800 For the AIX ABI structs are always stored left shifted in their
4804 function_arg_padding (enum machine_mode mode, tree type)
4806 #ifndef AGGREGATE_PADDING_FIXED
4807 #define AGGREGATE_PADDING_FIXED 0
4809 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4810 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4813 if (!AGGREGATE_PADDING_FIXED)
4815 /* GCC used to pass structures of the same size as integer types as
4816 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4817 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4818 passed padded downward, except that -mstrict-align further
4819 muddied the water in that multi-component structures of 2 and 4
4820 bytes in size were passed padded upward.
4822 The following arranges for best compatibility with previous
4823 versions of gcc, but removes the -mstrict-align dependency. */
4824 if (BYTES_BIG_ENDIAN)
4826 HOST_WIDE_INT size = 0;
4828 if (mode == BLKmode)
4830 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4831 size = int_size_in_bytes (type);
4834 size = GET_MODE_SIZE (mode);
4836 if (size == 1 || size == 2 || size == 4)
4842 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4844 if (type != 0 && AGGREGATE_TYPE_P (type))
4848 /* Fall back to the default. */
4849 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4852 /* If defined, a C expression that gives the alignment boundary, in bits,
4853 of an argument with the specified mode and type. If it is not defined,
4854 PARM_BOUNDARY is used for all arguments.
4856 V.4 wants long longs and doubles to be double word aligned. Just
4857 testing the mode size is a boneheaded way to do this as it means
4858 that other types such as complex int are also double word aligned.
4859 However, we're stuck with this because changing the ABI might break
4860 existing library interfaces.
4862 Doubleword align SPE vectors.
4863 Quadword align Altivec vectors.
4864 Quadword align large synthetic vector types. */
4867 function_arg_boundary (enum machine_mode mode, tree type)
4869 if (DEFAULT_ABI == ABI_V4
4870 && (GET_MODE_SIZE (mode) == 8
4871 || (TARGET_HARD_FLOAT
4873 && (mode == TFmode || mode == TDmode))))
4875 else if (SPE_VECTOR_MODE (mode)
4876 || (type && TREE_CODE (type) == VECTOR_TYPE
4877 && int_size_in_bytes (type) >= 8
4878 && int_size_in_bytes (type) < 16))
4880 else if (ALTIVEC_VECTOR_MODE (mode)
4881 || (type && TREE_CODE (type) == VECTOR_TYPE
4882 && int_size_in_bytes (type) >= 16))
4884 else if (rs6000_darwin64_abi && mode == BLKmode
4885 && type && TYPE_ALIGN (type) > 64)
4888 return PARM_BOUNDARY;
4891 /* For a function parm of MODE and TYPE, return the starting word in
4892 the parameter area. NWORDS of the parameter area are already used. */
4895 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4898 unsigned int parm_offset;
4900 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4901 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4902 return nwords + (-(parm_offset + nwords) & align);
4905 /* Compute the size (in words) of a function argument. */
4907 static unsigned long
4908 rs6000_arg_size (enum machine_mode mode, tree type)
4912 if (mode != BLKmode)
4913 size = GET_MODE_SIZE (mode);
4915 size = int_size_in_bytes (type);
4918 return (size + 3) >> 2;
4920 return (size + 7) >> 3;
4923 /* Use this to flush pending int fields. */
4926 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4927 HOST_WIDE_INT bitpos)
4929 unsigned int startbit, endbit;
4930 int intregs, intoffset;
4931 enum machine_mode mode;
4933 if (cum->intoffset == -1)
4936 intoffset = cum->intoffset;
4937 cum->intoffset = -1;
4939 if (intoffset % BITS_PER_WORD != 0)
4941 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4943 if (mode == BLKmode)
4945 /* We couldn't find an appropriate mode, which happens,
4946 e.g., in packed structs when there are 3 bytes to load.
4947 Back intoffset back to the beginning of the word in this
4949 intoffset = intoffset & -BITS_PER_WORD;
4953 startbit = intoffset & -BITS_PER_WORD;
4954 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4955 intregs = (endbit - startbit) / BITS_PER_WORD;
4956 cum->words += intregs;
4959 /* The darwin64 ABI calls for us to recurse down through structs,
4960 looking for elements passed in registers. Unfortunately, we have
4961 to track int register count here also because of misalignments
4962 in powerpc alignment mode. */
4965 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4967 HOST_WIDE_INT startbitpos)
4971 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4972 if (TREE_CODE (f) == FIELD_DECL)
4974 HOST_WIDE_INT bitpos = startbitpos;
4975 tree ftype = TREE_TYPE (f);
4976 enum machine_mode mode;
4977 if (ftype == error_mark_node)
4979 mode = TYPE_MODE (ftype);
4981 if (DECL_SIZE (f) != 0
4982 && host_integerp (bit_position (f), 1))
4983 bitpos += int_bit_position (f);
4985 /* ??? FIXME: else assume zero offset. */
4987 if (TREE_CODE (ftype) == RECORD_TYPE)
4988 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4989 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4991 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4992 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4993 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4995 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4997 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5001 else if (cum->intoffset == -1)
5002 cum->intoffset = bitpos;
5006 /* Update the data in CUM to advance over an argument
5007 of mode MODE and data type TYPE.
5008 (TYPE is null for libcalls where that information may not be available.)
5010 Note that for args passed by reference, function_arg will be called
5011 with MODE and TYPE set to that of the pointer to the arg, not the arg
5015 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5016 tree type, int named, int depth)
5020 /* Only tick off an argument if we're not recursing. */
5022 cum->nargs_prototype--;
5024 if (TARGET_ALTIVEC_ABI
5025 && (ALTIVEC_VECTOR_MODE (mode)
5026 || (type && TREE_CODE (type) == VECTOR_TYPE
5027 && int_size_in_bytes (type) == 16)))
5031 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5034 if (!TARGET_ALTIVEC)
5035 error ("cannot pass argument in vector register because"
5036 " altivec instructions are disabled, use -maltivec"
5039 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5040 even if it is going to be passed in a vector register.
5041 Darwin does the same for variable-argument functions. */
5042 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5043 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5053 /* Vector parameters must be 16-byte aligned. This places
5054 them at 2 mod 4 in terms of words in 32-bit mode, since
5055 the parameter save area starts at offset 24 from the
5056 stack. In 64-bit mode, they just have to start on an
5057 even word, since the parameter save area is 16-byte
5058 aligned. Space for GPRs is reserved even if the argument
5059 will be passed in memory. */
5061 align = (2 - cum->words) & 3;
5063 align = cum->words & 1;
5064 cum->words += align + rs6000_arg_size (mode, type);
5066 if (TARGET_DEBUG_ARG)
5068 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5070 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5071 cum->nargs_prototype, cum->prototype,
5072 GET_MODE_NAME (mode));
5076 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5078 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5081 else if (rs6000_darwin64_abi
5083 && TREE_CODE (type) == RECORD_TYPE
5084 && (size = int_size_in_bytes (type)) > 0)
5086 /* Variable sized types have size == -1 and are
5087 treated as if consisting entirely of ints.
5088 Pad to 16 byte boundary if needed. */
5089 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5090 && (cum->words % 2) != 0)
5092 /* For varargs, we can just go up by the size of the struct. */
5094 cum->words += (size + 7) / 8;
5097 /* It is tempting to say int register count just goes up by
5098 sizeof(type)/8, but this is wrong in a case such as
5099 { int; double; int; } [powerpc alignment]. We have to
5100 grovel through the fields for these too. */
5102 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5103 rs6000_darwin64_record_arg_advance_flush (cum,
5104 size * BITS_PER_UNIT);
5107 else if (DEFAULT_ABI == ABI_V4)
5109 if (TARGET_HARD_FLOAT && TARGET_FPRS
5110 && (mode == SFmode || mode == DFmode
5111 || mode == DDmode || mode == TDmode
5112 || (mode == TFmode && !TARGET_IEEEQUAD)))
5114 /* _Decimal128 must use an even/odd register pair. This assumes
5115 that the register number is odd when fregno is odd. */
5116 if (mode == TDmode && (cum->fregno % 2) == 1)
5119 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5120 <= FP_ARG_V4_MAX_REG)
5121 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5124 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5125 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5126 cum->words += cum->words & 1;
5127 cum->words += rs6000_arg_size (mode, type);
5132 int n_words = rs6000_arg_size (mode, type);
5133 int gregno = cum->sysv_gregno;
5135 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5136 (r7,r8) or (r9,r10). As does any other 2 word item such
5137 as complex int due to a historical mistake. */
5139 gregno += (1 - gregno) & 1;
5141 /* Multi-reg args are not split between registers and stack. */
5142 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5144 /* Long long and SPE vectors are aligned on the stack.
5145 So are other 2 word items such as complex int due to
5146 a historical mistake. */
5148 cum->words += cum->words & 1;
5149 cum->words += n_words;
5152 /* Note: continuing to accumulate gregno past when we've started
5153 spilling to the stack indicates the fact that we've started
5154 spilling to the stack to expand_builtin_saveregs. */
5155 cum->sysv_gregno = gregno + n_words;
5158 if (TARGET_DEBUG_ARG)
5160 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5161 cum->words, cum->fregno);
5162 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5163 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5164 fprintf (stderr, "mode = %4s, named = %d\n",
5165 GET_MODE_NAME (mode), named);
5170 int n_words = rs6000_arg_size (mode, type);
5171 int start_words = cum->words;
5172 int align_words = rs6000_parm_start (mode, type, start_words);
5174 cum->words = align_words + n_words;
5176 if (SCALAR_FLOAT_MODE_P (mode)
5178 && TARGET_HARD_FLOAT && TARGET_FPRS)
5180 /* _Decimal128 must be passed in an even/odd float register pair.
5181 This assumes that the register number is odd when fregno is
5183 if (mode == TDmode && (cum->fregno % 2) == 1)
5185 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5188 if (TARGET_DEBUG_ARG)
5190 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5191 cum->words, cum->fregno);
5192 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5193 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5194 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5195 named, align_words - start_words, depth);
5201 spe_build_register_parallel (enum machine_mode mode, int gregno)
5208 r1 = gen_rtx_REG (DImode, gregno);
5209 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5210 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5214 r1 = gen_rtx_REG (DImode, gregno);
5215 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5216 r3 = gen_rtx_REG (DImode, gregno + 2);
5217 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5218 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5221 r1 = gen_rtx_REG (DImode, gregno);
5222 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5223 r3 = gen_rtx_REG (DImode, gregno + 2);
5224 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5225 r5 = gen_rtx_REG (DImode, gregno + 4);
5226 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5227 r7 = gen_rtx_REG (DImode, gregno + 6);
5228 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5229 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5236 /* Determine where to put a SIMD argument on the SPE. */
5238 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5241 int gregno = cum->sysv_gregno;
5243 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5244 are passed and returned in a pair of GPRs for ABI compatibility. */
5245 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5246 || mode == TFmode || mode == TCmode))
5248 int n_words = rs6000_arg_size (mode, type);
5250 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5252 gregno += (1 - gregno) & 1;
5254 /* Multi-reg args are not split between registers and stack. */
5255 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5258 return spe_build_register_parallel (mode, gregno);
5262 int n_words = rs6000_arg_size (mode, type);
5264 /* SPE vectors are put in odd registers. */
5265 if (n_words == 2 && (gregno & 1) == 0)
5268 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5271 enum machine_mode m = SImode;
5273 r1 = gen_rtx_REG (m, gregno);
5274 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5275 r2 = gen_rtx_REG (m, gregno + 1);
5276 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5277 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5284 if (gregno <= GP_ARG_MAX_REG)
5285 return gen_rtx_REG (mode, gregno);
5291 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5292 structure between cum->intoffset and bitpos to integer registers. */
5295 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5296 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5298 enum machine_mode mode;
5300 unsigned int startbit, endbit;
5301 int this_regno, intregs, intoffset;
5304 if (cum->intoffset == -1)
5307 intoffset = cum->intoffset;
5308 cum->intoffset = -1;
5310 /* If this is the trailing part of a word, try to only load that
5311 much into the register. Otherwise load the whole register. Note
5312 that in the latter case we may pick up unwanted bits. It's not a
5313 problem at the moment but may wish to revisit. */
5315 if (intoffset % BITS_PER_WORD != 0)
5317 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5319 if (mode == BLKmode)
5321 /* We couldn't find an appropriate mode, which happens,
5322 e.g., in packed structs when there are 3 bytes to load.
5323 Back intoffset back to the beginning of the word in this
5325 intoffset = intoffset & -BITS_PER_WORD;
5332 startbit = intoffset & -BITS_PER_WORD;
5333 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5334 intregs = (endbit - startbit) / BITS_PER_WORD;
5335 this_regno = cum->words + intoffset / BITS_PER_WORD;
5337 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5340 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5344 intoffset /= BITS_PER_UNIT;
5347 regno = GP_ARG_MIN_REG + this_regno;
5348 reg = gen_rtx_REG (mode, regno);
5350 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5353 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5357 while (intregs > 0);
5360 /* Recursive workhorse for the following. */
5363 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
5364 HOST_WIDE_INT startbitpos, rtx rvec[],
5369 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5370 if (TREE_CODE (f) == FIELD_DECL)
5372 HOST_WIDE_INT bitpos = startbitpos;
5373 tree ftype = TREE_TYPE (f);
5374 enum machine_mode mode;
5375 if (ftype == error_mark_node)
5377 mode = TYPE_MODE (ftype);
5379 if (DECL_SIZE (f) != 0
5380 && host_integerp (bit_position (f), 1))
5381 bitpos += int_bit_position (f);
5383 /* ??? FIXME: else assume zero offset. */
5385 if (TREE_CODE (ftype) == RECORD_TYPE)
5386 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5387 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5392 case SCmode: mode = SFmode; break;
5393 case DCmode: mode = DFmode; break;
5394 case TCmode: mode = TFmode; break;
5398 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5400 = gen_rtx_EXPR_LIST (VOIDmode,
5401 gen_rtx_REG (mode, cum->fregno++),
5402 GEN_INT (bitpos / BITS_PER_UNIT));
5403 if (mode == TFmode || mode == TDmode)
5406 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5408 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5410 = gen_rtx_EXPR_LIST (VOIDmode,
5411 gen_rtx_REG (mode, cum->vregno++),
5412 GEN_INT (bitpos / BITS_PER_UNIT));
5414 else if (cum->intoffset == -1)
5415 cum->intoffset = bitpos;
5419 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5420 the register(s) to be used for each field and subfield of a struct
5421 being passed by value, along with the offset of where the
5422 register's value may be found in the block. FP fields go in FP
5423 register, vector fields go in vector registers, and everything
5424 else goes in int registers, packed as in memory.
5426 This code is also used for function return values. RETVAL indicates
5427 whether this is the case.
5429 Much of this is taken from the SPARC V9 port, which has a similar
5430 calling convention. */
5433 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
5434 int named, bool retval)
5436 rtx rvec[FIRST_PSEUDO_REGISTER];
5437 int k = 1, kbase = 1;
5438 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5439 /* This is a copy; modifications are not visible to our caller. */
5440 CUMULATIVE_ARGS copy_cum = *orig_cum;
5441 CUMULATIVE_ARGS *cum = ©_cum;
5443 /* Pad to 16 byte boundary if needed. */
5444 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5445 && (cum->words % 2) != 0)
5452 /* Put entries into rvec[] for individual FP and vector fields, and
5453 for the chunks of memory that go in int regs. Note we start at
5454 element 1; 0 is reserved for an indication of using memory, and
5455 may or may not be filled in below. */
5456 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5457 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5459 /* If any part of the struct went on the stack put all of it there.
5460 This hack is because the generic code for
5461 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5462 parts of the struct are not at the beginning. */
5466 return NULL_RTX; /* doesn't go in registers at all */
5468 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5470 if (k > 1 || cum->use_stack)
5471 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5476 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5479 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5483 rtx rvec[GP_ARG_NUM_REG + 1];
5485 if (align_words >= GP_ARG_NUM_REG)
5488 n_units = rs6000_arg_size (mode, type);
5490 /* Optimize the simple case where the arg fits in one gpr, except in
5491 the case of BLKmode due to assign_parms assuming that registers are
5492 BITS_PER_WORD wide. */
5494 || (n_units == 1 && mode != BLKmode))
5495 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5498 if (align_words + n_units > GP_ARG_NUM_REG)
5499 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5500 using a magic NULL_RTX component.
5501 This is not strictly correct. Only some of the arg belongs in
5502 memory, not all of it. However, the normal scheme using
5503 function_arg_partial_nregs can result in unusual subregs, eg.
5504 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5505 store the whole arg to memory is often more efficient than code
5506 to store pieces, and we know that space is available in the right
5507 place for the whole arg. */
5508 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5513 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5514 rtx off = GEN_INT (i++ * 4);
5515 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5517 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5519 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5522 /* Determine where to put an argument to a function.
5523 Value is zero to push the argument on the stack,
5524 or a hard register in which to store the argument.
5526 MODE is the argument's machine mode.
5527 TYPE is the data type of the argument (as a tree).
5528 This is null for libcalls where that information may
5530 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5531 the preceding args and about the function being called. It is
5532 not modified in this routine.
5533 NAMED is nonzero if this argument is a named parameter
5534 (otherwise it is an extra parameter matching an ellipsis).
5536 On RS/6000 the first eight words of non-FP are normally in registers
5537 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5538 Under V.4, the first 8 FP args are in registers.
5540 If this is floating-point and no prototype is specified, we use
5541 both an FP and integer register (or possibly FP reg and stack). Library
5542 functions (when CALL_LIBCALL is set) always have the proper types for args,
5543 so we can pass the FP value just in one register. emit_library_function
5544 doesn't support PARALLEL anyway.
5546 Note that for args passed by reference, function_arg will be called
5547 with MODE and TYPE set to that of the pointer to the arg, not the arg
5551 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5552 tree type, int named)
5554 enum rs6000_abi abi = DEFAULT_ABI;
5556 /* Return a marker to indicate whether CR1 needs to set or clear the
5557 bit that V.4 uses to say fp args were passed in registers.
5558 Assume that we don't need the marker for software floating point,
5559 or compiler generated library calls. */
5560 if (mode == VOIDmode)
5563 && (cum->call_cookie & CALL_LIBCALL) == 0
5565 || (cum->nargs_prototype < 0
5566 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5568 /* For the SPE, we need to crxor CR6 always. */
5570 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5571 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5572 return GEN_INT (cum->call_cookie
5573 | ((cum->fregno == FP_ARG_MIN_REG)
5574 ? CALL_V4_SET_FP_ARGS
5575 : CALL_V4_CLEAR_FP_ARGS));
5578 return GEN_INT (cum->call_cookie);
5581 if (rs6000_darwin64_abi && mode == BLKmode
5582 && TREE_CODE (type) == RECORD_TYPE)
5584 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5585 if (rslt != NULL_RTX)
5587 /* Else fall through to usual handling. */
5590 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5591 if (TARGET_64BIT && ! cum->prototype)
5593 /* Vector parameters get passed in vector register
5594 and also in GPRs or memory, in absence of prototype. */
5597 align_words = (cum->words + 1) & ~1;
5599 if (align_words >= GP_ARG_NUM_REG)
5605 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5607 return gen_rtx_PARALLEL (mode,
5609 gen_rtx_EXPR_LIST (VOIDmode,
5611 gen_rtx_EXPR_LIST (VOIDmode,
5612 gen_rtx_REG (mode, cum->vregno),
5616 return gen_rtx_REG (mode, cum->vregno);
5617 else if (TARGET_ALTIVEC_ABI
5618 && (ALTIVEC_VECTOR_MODE (mode)
5619 || (type && TREE_CODE (type) == VECTOR_TYPE
5620 && int_size_in_bytes (type) == 16)))
5622 if (named || abi == ABI_V4)
5626 /* Vector parameters to varargs functions under AIX or Darwin
5627 get passed in memory and possibly also in GPRs. */
5628 int align, align_words, n_words;
5629 enum machine_mode part_mode;
5631 /* Vector parameters must be 16-byte aligned. This places them at
5632 2 mod 4 in terms of words in 32-bit mode, since the parameter
5633 save area starts at offset 24 from the stack. In 64-bit mode,
5634 they just have to start on an even word, since the parameter
5635 save area is 16-byte aligned. */
5637 align = (2 - cum->words) & 3;
5639 align = cum->words & 1;
5640 align_words = cum->words + align;
5642 /* Out of registers? Memory, then. */
5643 if (align_words >= GP_ARG_NUM_REG)
5646 if (TARGET_32BIT && TARGET_POWERPC64)
5647 return rs6000_mixed_function_arg (mode, type, align_words);
5649 /* The vector value goes in GPRs. Only the part of the
5650 value in GPRs is reported here. */
5652 n_words = rs6000_arg_size (mode, type);
5653 if (align_words + n_words > GP_ARG_NUM_REG)
5654 /* Fortunately, there are only two possibilities, the value
5655 is either wholly in GPRs or half in GPRs and half not. */
5658 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5661 else if (TARGET_SPE_ABI && TARGET_SPE
5662 && (SPE_VECTOR_MODE (mode)
5663 || (TARGET_E500_DOUBLE && (mode == DFmode
5668 || mode == TCmode))))
5669 return rs6000_spe_function_arg (cum, mode, type);
5671 else if (abi == ABI_V4)
5673 if (TARGET_HARD_FLOAT && TARGET_FPRS
5674 && (mode == SFmode || mode == DFmode
5675 || (mode == TFmode && !TARGET_IEEEQUAD)
5676 || mode == DDmode || mode == TDmode))
5678 /* _Decimal128 must use an even/odd register pair. This assumes
5679 that the register number is odd when fregno is odd. */
5680 if (mode == TDmode && (cum->fregno % 2) == 1)
5683 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5684 <= FP_ARG_V4_MAX_REG)
5685 return gen_rtx_REG (mode, cum->fregno);
5691 int n_words = rs6000_arg_size (mode, type);
5692 int gregno = cum->sysv_gregno;
5694 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5695 (r7,r8) or (r9,r10). As does any other 2 word item such
5696 as complex int due to a historical mistake. */
5698 gregno += (1 - gregno) & 1;
5700 /* Multi-reg args are not split between registers and stack. */
5701 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5704 if (TARGET_32BIT && TARGET_POWERPC64)
5705 return rs6000_mixed_function_arg (mode, type,
5706 gregno - GP_ARG_MIN_REG);
5707 return gen_rtx_REG (mode, gregno);
5712 int align_words = rs6000_parm_start (mode, type, cum->words);
5714 /* _Decimal128 must be passed in an even/odd float register pair.
5715 This assumes that the register number is odd when fregno is odd. */
5716 if (mode == TDmode && (cum->fregno % 2) == 1)
5719 if (USE_FP_FOR_ARG_P (cum, mode, type))
5721 rtx rvec[GP_ARG_NUM_REG + 1];
5725 enum machine_mode fmode = mode;
5726 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5728 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5730 /* Currently, we only ever need one reg here because complex
5731 doubles are split. */
5732 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5733 && (fmode == TFmode || fmode == TDmode));
5735 /* Long double or _Decimal128 split over regs and memory. */
5736 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5739 /* Do we also need to pass this arg in the parameter save
5742 && (cum->nargs_prototype <= 0
5743 || (DEFAULT_ABI == ABI_AIX
5745 && align_words >= GP_ARG_NUM_REG)));
5747 if (!needs_psave && mode == fmode)
5748 return gen_rtx_REG (fmode, cum->fregno);
5753 /* Describe the part that goes in gprs or the stack.
5754 This piece must come first, before the fprs. */
5755 if (align_words < GP_ARG_NUM_REG)
5757 unsigned long n_words = rs6000_arg_size (mode, type);
5759 if (align_words + n_words > GP_ARG_NUM_REG
5760 || (TARGET_32BIT && TARGET_POWERPC64))
5762 /* If this is partially on the stack, then we only
5763 include the portion actually in registers here. */
5764 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5767 if (align_words + n_words > GP_ARG_NUM_REG)
5768 /* Not all of the arg fits in gprs. Say that it
5769 goes in memory too, using a magic NULL_RTX
5770 component. Also see comment in
5771 rs6000_mixed_function_arg for why the normal
5772 function_arg_partial_nregs scheme doesn't work
5774 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5778 r = gen_rtx_REG (rmode,
5779 GP_ARG_MIN_REG + align_words);
5780 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5781 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5783 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5787 /* The whole arg fits in gprs. */
5788 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5789 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5793 /* It's entirely in memory. */
5794 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5797 /* Describe where this piece goes in the fprs. */
5798 r = gen_rtx_REG (fmode, cum->fregno);
5799 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5801 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5803 else if (align_words < GP_ARG_NUM_REG)
5805 if (TARGET_32BIT && TARGET_POWERPC64)
5806 return rs6000_mixed_function_arg (mode, type, align_words);
5808 if (mode == BLKmode)
5811 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5818 /* For an arg passed partly in registers and partly in memory, this is
5819 the number of bytes passed in registers. For args passed entirely in
5820 registers or entirely in memory, zero. When an arg is described by a
5821 PARALLEL, perhaps using more than one register type, this function
5822 returns the number of bytes used by the first element of the PARALLEL. */
5825 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5826 tree type, bool named)
5831 if (DEFAULT_ABI == ABI_V4)
5834 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5835 && cum->nargs_prototype >= 0)
5838 /* In this complicated case we just disable the partial_nregs code. */
5839 if (rs6000_darwin64_abi && mode == BLKmode
5840 && TREE_CODE (type) == RECORD_TYPE
5841 && int_size_in_bytes (type) > 0)
5844 align_words = rs6000_parm_start (mode, type, cum->words);
5846 if (USE_FP_FOR_ARG_P (cum, mode, type))
5848 /* If we are passing this arg in the fixed parameter save area
5849 (gprs or memory) as well as fprs, then this function should
5850 return the number of partial bytes passed in the parameter
5851 save area rather than partial bytes passed in fprs. */
5853 && (cum->nargs_prototype <= 0
5854 || (DEFAULT_ABI == ABI_AIX
5856 && align_words >= GP_ARG_NUM_REG)))
5858 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
5859 > FP_ARG_MAX_REG + 1)
5860 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5861 else if (cum->nargs_prototype >= 0)
5865 if (align_words < GP_ARG_NUM_REG
5866 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5867 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5869 if (ret != 0 && TARGET_DEBUG_ARG)
5870 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5875 /* A C expression that indicates when an argument must be passed by
5876 reference. If nonzero for an argument, a copy of that argument is
5877 made in memory and a pointer to the argument is passed instead of
5878 the argument itself. The pointer is passed in whatever way is
5879 appropriate for passing a pointer to that type.
5881 Under V.4, aggregates and long double are passed by reference.
5883 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5884 reference unless the AltiVec vector extension ABI is in force.
5886 As an extension to all ABIs, variable sized types are passed by
5890 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5891 enum machine_mode mode, tree type,
5892 bool named ATTRIBUTE_UNUSED)
5894 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
5896 if (TARGET_DEBUG_ARG)
5897 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5904 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5906 if (TARGET_DEBUG_ARG)
5907 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5911 if (int_size_in_bytes (type) < 0)
5913 if (TARGET_DEBUG_ARG)
5914 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5918 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5919 modes only exist for GCC vector types if -maltivec. */
5920 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5922 if (TARGET_DEBUG_ARG)
5923 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5927 /* Pass synthetic vectors in memory. */
5928 if (TREE_CODE (type) == VECTOR_TYPE
5929 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5931 static bool warned_for_pass_big_vectors = false;
5932 if (TARGET_DEBUG_ARG)
5933 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5934 if (!warned_for_pass_big_vectors)
5936 warning (0, "GCC vector passed by reference: "
5937 "non-standard ABI extension with no compatibility guarantee");
5938 warned_for_pass_big_vectors = true;
5947 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5950 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5955 for (i = 0; i < nregs; i++)
5957 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5958 if (reload_completed)
5960 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5963 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5964 i * GET_MODE_SIZE (reg_mode));
5967 tem = replace_equiv_address (tem, XEXP (tem, 0));
5971 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5975 /* Perform any needed actions needed for a function that is receiving a
5976 variable number of arguments.
5980 MODE and TYPE are the mode and type of the current parameter.
5982 PRETEND_SIZE is a variable that should be set to the amount of stack
5983 that must be pushed by the prolog to pretend that our caller pushed
5986 Normally, this macro will push all remaining incoming registers on the
5987 stack and set PRETEND_SIZE to the length of the registers pushed. */
5990 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5991 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5994 CUMULATIVE_ARGS next_cum;
5995 int reg_size = TARGET_32BIT ? 4 : 8;
5996 rtx save_area = NULL_RTX, mem;
5997 int first_reg_offset, set;
5999 /* Skip the last named argument. */
6001 function_arg_advance (&next_cum, mode, type, 1, 0);
6003 if (DEFAULT_ABI == ABI_V4)
6005 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6009 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6010 HOST_WIDE_INT offset = 0;
6012 /* Try to optimize the size of the varargs save area.
6013 The ABI requires that ap.reg_save_area is doubleword
6014 aligned, but we don't need to allocate space for all
6015 the bytes, only those to which we actually will save
6017 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6018 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6019 if (TARGET_HARD_FLOAT && TARGET_FPRS
6020 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6021 && cfun->va_list_fpr_size)
6024 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6025 * UNITS_PER_FP_WORD;
6026 if (cfun->va_list_fpr_size
6027 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6028 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6030 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6031 * UNITS_PER_FP_WORD;
6035 offset = -((first_reg_offset * reg_size) & ~7);
6036 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6038 gpr_reg_num = cfun->va_list_gpr_size;
6039 if (reg_size == 4 && (first_reg_offset & 1))
6042 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6045 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6047 - (int) (GP_ARG_NUM_REG * reg_size);
6049 if (gpr_size + fpr_size)
6052 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6053 gcc_assert (GET_CODE (reg_save_area) == MEM);
6054 reg_save_area = XEXP (reg_save_area, 0);
6055 if (GET_CODE (reg_save_area) == PLUS)
6057 gcc_assert (XEXP (reg_save_area, 0)
6058 == virtual_stack_vars_rtx);
6059 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6060 offset += INTVAL (XEXP (reg_save_area, 1));
6063 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6066 cfun->machine->varargs_save_offset = offset;
6067 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6072 first_reg_offset = next_cum.words;
6073 save_area = virtual_incoming_args_rtx;
6075 if (targetm.calls.must_pass_in_stack (mode, type))
6076 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6079 set = get_varargs_alias_set ();
6080 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6081 && cfun->va_list_gpr_size)
6083 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6085 if (va_list_gpr_counter_field)
6087 /* V4 va_list_gpr_size counts number of registers needed. */
6088 if (nregs > cfun->va_list_gpr_size)
6089 nregs = cfun->va_list_gpr_size;
6093 /* char * va_list instead counts number of bytes needed. */
6094 if (nregs > cfun->va_list_gpr_size / reg_size)
6095 nregs = cfun->va_list_gpr_size / reg_size;
6098 mem = gen_rtx_MEM (BLKmode,
6099 plus_constant (save_area,
6100 first_reg_offset * reg_size));
6101 MEM_NOTRAP_P (mem) = 1;
6102 set_mem_alias_set (mem, set);
6103 set_mem_align (mem, BITS_PER_WORD);
6105 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6109 /* Save FP registers if needed. */
6110 if (DEFAULT_ABI == ABI_V4
6111 && TARGET_HARD_FLOAT && TARGET_FPRS
6113 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6114 && cfun->va_list_fpr_size)
6116 int fregno = next_cum.fregno, nregs;
6117 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6118 rtx lab = gen_label_rtx ();
6119 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6120 * UNITS_PER_FP_WORD);
6123 (gen_rtx_SET (VOIDmode,
6125 gen_rtx_IF_THEN_ELSE (VOIDmode,
6126 gen_rtx_NE (VOIDmode, cr1,
6128 gen_rtx_LABEL_REF (VOIDmode, lab),
6132 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6133 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6135 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6136 MEM_NOTRAP_P (mem) = 1;
6137 set_mem_alias_set (mem, set);
6138 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6139 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6146 /* Create the va_list data type. */
6149 rs6000_build_builtin_va_list (void)
6151 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6153 /* For AIX, prefer 'char *' because that's what the system
6154 header files like. */
6155 if (DEFAULT_ABI != ABI_V4)
6156 return build_pointer_type (char_type_node);
6158 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6159 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6161 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6162 unsigned_char_type_node);
6163 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6164 unsigned_char_type_node);
6165 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6167 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6168 short_unsigned_type_node);
6169 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6171 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6174 va_list_gpr_counter_field = f_gpr;
6175 va_list_fpr_counter_field = f_fpr;
6177 DECL_FIELD_CONTEXT (f_gpr) = record;
6178 DECL_FIELD_CONTEXT (f_fpr) = record;
6179 DECL_FIELD_CONTEXT (f_res) = record;
6180 DECL_FIELD_CONTEXT (f_ovf) = record;
6181 DECL_FIELD_CONTEXT (f_sav) = record;
6183 TREE_CHAIN (record) = type_decl;
6184 TYPE_NAME (record) = type_decl;
6185 TYPE_FIELDS (record) = f_gpr;
6186 TREE_CHAIN (f_gpr) = f_fpr;
6187 TREE_CHAIN (f_fpr) = f_res;
6188 TREE_CHAIN (f_res) = f_ovf;
6189 TREE_CHAIN (f_ovf) = f_sav;
6191 layout_type (record);
6193 /* The correct type is an array type of one element. */
6194 return build_array_type (record, build_index_type (size_zero_node));
6197 /* Implement va_start. */
6200 rs6000_va_start (tree valist, rtx nextarg)
6202 HOST_WIDE_INT words, n_gpr, n_fpr;
6203 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6204 tree gpr, fpr, ovf, sav, t;
6206 /* Only SVR4 needs something special. */
6207 if (DEFAULT_ABI != ABI_V4)
6209 std_expand_builtin_va_start (valist, nextarg);
6213 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6214 f_fpr = TREE_CHAIN (f_gpr);
6215 f_res = TREE_CHAIN (f_fpr);
6216 f_ovf = TREE_CHAIN (f_res);
6217 f_sav = TREE_CHAIN (f_ovf);
6219 valist = build_va_arg_indirect_ref (valist);
6220 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6221 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6222 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6223 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6225 /* Count number of gp and fp argument registers used. */
6226 words = current_function_args_info.words;
6227 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6229 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6232 if (TARGET_DEBUG_ARG)
6233 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6234 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6235 words, n_gpr, n_fpr);
6237 if (cfun->va_list_gpr_size)
6239 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6240 build_int_cst (NULL_TREE, n_gpr));
6241 TREE_SIDE_EFFECTS (t) = 1;
6242 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6245 if (cfun->va_list_fpr_size)
6247 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6248 build_int_cst (NULL_TREE, n_fpr));
6249 TREE_SIDE_EFFECTS (t) = 1;
6250 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6253 /* Find the overflow area. */
6254 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6256 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6257 size_int (words * UNITS_PER_WORD));
6258 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6259 TREE_SIDE_EFFECTS (t) = 1;
6260 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6262 /* If there were no va_arg invocations, don't set up the register
6264 if (!cfun->va_list_gpr_size
6265 && !cfun->va_list_fpr_size
6266 && n_gpr < GP_ARG_NUM_REG
6267 && n_fpr < FP_ARG_V4_MAX_REG)
6270 /* Find the register save area. */
6271 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6272 if (cfun->machine->varargs_save_offset)
6273 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6274 size_int (cfun->machine->varargs_save_offset));
6275 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6276 TREE_SIDE_EFFECTS (t) = 1;
6277 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6280 /* Implement va_arg. */
6283 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6285 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6286 tree gpr, fpr, ovf, sav, reg, t, u;
6287 int size, rsize, n_reg, sav_ofs, sav_scale;
6288 tree lab_false, lab_over, addr;
6290 tree ptrtype = build_pointer_type (type);
6293 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6295 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6296 return build_va_arg_indirect_ref (t);
6299 if (DEFAULT_ABI != ABI_V4)
6301 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6303 tree elem_type = TREE_TYPE (type);
6304 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6305 int elem_size = GET_MODE_SIZE (elem_mode);
6307 if (elem_size < UNITS_PER_WORD)
6309 tree real_part, imag_part;
6310 tree post = NULL_TREE;
6312 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6314 /* Copy the value into a temporary, lest the formal temporary
6315 be reused out from under us. */
6316 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6317 append_to_statement_list (post, pre_p);
6319 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6322 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6326 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6329 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6330 f_fpr = TREE_CHAIN (f_gpr);
6331 f_res = TREE_CHAIN (f_fpr);
6332 f_ovf = TREE_CHAIN (f_res);
6333 f_sav = TREE_CHAIN (f_ovf);
6335 valist = build_va_arg_indirect_ref (valist);
6336 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6337 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6338 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6339 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6341 size = int_size_in_bytes (type);
6342 rsize = (size + 3) / 4;
6345 if (TARGET_HARD_FLOAT && TARGET_FPRS
6346 && (TYPE_MODE (type) == SFmode
6347 || TYPE_MODE (type) == DFmode
6348 || TYPE_MODE (type) == TFmode
6349 || TYPE_MODE (type) == DDmode
6350 || TYPE_MODE (type) == TDmode))
6352 /* FP args go in FP registers, if present. */
6354 n_reg = (size + 7) / 8;
6357 if (TYPE_MODE (type) != SFmode)
6362 /* Otherwise into GP registers. */
6371 /* Pull the value out of the saved registers.... */
6374 addr = create_tmp_var (ptr_type_node, "addr");
6375 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6377 /* AltiVec vectors never go in registers when -mabi=altivec. */
6378 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6382 lab_false = create_artificial_label ();
6383 lab_over = create_artificial_label ();
6385 /* Long long and SPE vectors are aligned in the registers.
6386 As are any other 2 gpr item such as complex int due to a
6387 historical mistake. */
6389 if (n_reg == 2 && reg == gpr)
6392 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6393 size_int (n_reg - 1));
6394 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6396 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6397 reg number is 0 for f1, so we want to make it odd. */
6398 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6401 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6402 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6405 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6406 t = build2 (GE_EXPR, boolean_type_node, u, t);
6407 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6408 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6409 gimplify_and_add (t, pre_p);
6413 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6415 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
6416 u = fold_convert (sizetype, u);
6417 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6418 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6420 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6421 gimplify_and_add (t, pre_p);
6423 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6424 gimplify_and_add (t, pre_p);
6426 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6427 append_to_statement_list (t, pre_p);
6429 if ((n_reg == 2 && !regalign) || n_reg > 2)
6431 /* Ensure that we don't find any more args in regs.
6432 Alignment has taken care of for special cases. */
6433 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6434 gimplify_and_add (t, pre_p);
6438 /* ... otherwise out of the overflow area. */
6440 /* Care for on-stack alignment if needed. */
6444 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6445 t = fold_convert (sizetype, t);
6446 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6448 t = fold_convert (TREE_TYPE (ovf), t);
6450 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6452 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6453 gimplify_and_add (u, pre_p);
6455 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6456 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6457 gimplify_and_add (t, pre_p);
6461 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6462 append_to_statement_list (t, pre_p);
6465 if (STRICT_ALIGNMENT
6466 && (TYPE_ALIGN (type)
6467 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6469 /* The value (of type complex double, for example) may not be
6470 aligned in memory in the saved registers, so copy via a
6471 temporary. (This is the same code as used for SPARC.) */
6472 tree tmp = create_tmp_var (type, "va_arg_tmp");
6473 tree dest_addr = build_fold_addr_expr (tmp);
6475 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6476 3, dest_addr, addr, size_int (rsize * 4));
6478 gimplify_and_add (copy, pre_p);
6482 addr = fold_convert (ptrtype, addr);
6483 return build_va_arg_indirect_ref (addr);
6489 def_builtin (int mask, const char *name, tree type, int code)
6491 if (mask & target_flags)
6493 if (rs6000_builtin_decls[code])
6496 rs6000_builtin_decls[code] =
6497 add_builtin_function (name, type, code, BUILT_IN_MD,
6502 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6504 static const struct builtin_description bdesc_3arg[] =
6506 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6507 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6508 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6509 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6510 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6511 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6512 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6513 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6514 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6515 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6516 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6517 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6518 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6519 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6520 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6521 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6522 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6523 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6524 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6525 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6526 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6527 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6528 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6530 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6531 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6532 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6533 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6534 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6535 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6536 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6537 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6538 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6539 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6540 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6541 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6542 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6543 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6544 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6547 /* DST operations: void foo (void *, const int, const char). */
6549 static const struct builtin_description bdesc_dst[] =
6551 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6552 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6553 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6554 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6556 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6557 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6558 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6559 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6562 /* Simple binary operations: VECc = foo (VECa, VECb). */
6564 static struct builtin_description bdesc_2arg[] =
6566 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6567 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6568 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6569 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6570 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6571 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6572 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6573 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6574 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6575 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6576 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6577 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6578 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6579 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6580 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6581 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6582 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6583 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6584 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6585 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6586 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6587 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6588 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6589 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6590 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6591 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6592 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6593 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6594 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6595 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6596 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6597 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6598 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6599 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6600 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6601 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6602 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6603 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6604 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6605 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6606 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6607 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6608 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6609 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6610 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6611 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6612 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6613 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6614 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6615 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6616 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6617 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6618 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6619 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6620 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6621 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6622 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6623 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6624 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6625 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6626 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6627 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6628 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6629 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6630 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6631 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6632 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6633 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6634 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6635 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6636 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6637 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6638 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6639 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6640 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6641 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6642 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6643 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6644 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6645 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6646 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6647 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6648 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6649 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6650 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6651 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6652 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6653 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6654 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6655 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6656 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6657 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6658 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6659 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6660 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6661 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6662 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6663 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6664 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6665 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6666 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6667 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6668 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6669 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6670 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6671 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6672 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6673 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6674 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6675 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6676 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6678 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6679 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6680 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6681 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6682 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6683 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6684 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6685 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6686 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6687 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6688 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6689 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6690 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6691 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6692 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6693 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6694 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6695 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6696 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6697 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6698 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6699 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6700 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6701 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6702 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6703 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6704 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6705 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6706 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6707 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6708 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6724 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6725 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6726 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6727 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6728 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6729 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6730 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6731 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6732 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6733 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6734 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6735 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6736 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6737 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6738 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6739 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6740 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6741 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6742 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6743 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6744 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6745 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6746 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6747 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6748 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6749 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6750 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6751 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6752 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6753 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6754 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6755 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6756 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6757 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6758 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6759 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6760 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6761 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6762 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6763 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6764 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6765 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6766 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6767 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6768 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6769 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6770 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6771 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6772 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6773 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6774 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6775 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6776 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6777 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6778 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6779 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6780 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6781 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6782 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6783 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6784 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6785 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6786 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6787 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6788 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6789 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6790 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6791 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6792 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6793 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6794 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6795 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6796 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6797 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6798 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6799 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6800 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6801 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6802 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6803 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6804 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6806 /* Place holder, leave as first spe builtin. */
6807 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6808 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6809 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6810 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6811 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6812 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6813 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6814 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6815 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6816 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6817 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6818 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6819 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6820 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6821 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6822 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6823 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6824 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6825 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6826 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6827 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6828 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6829 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6830 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6831 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6832 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6833 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6834 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6835 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6836 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6837 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6838 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6839 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6840 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6841 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6842 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6843 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6844 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6845 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6846 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6847 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6848 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6849 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6850 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6851 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6852 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6853 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6854 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6855 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6856 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6857 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6858 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6859 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6860 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6861 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6862 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6863 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6864 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6865 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6866 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6867 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6868 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6869 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6870 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6871 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6872 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6873 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6874 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6875 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6876 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6877 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6878 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6879 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6880 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6881 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6882 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6883 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6884 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6885 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6886 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6887 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6888 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6889 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6890 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6891 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6892 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6893 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6894 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6895 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6896 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6897 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6898 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6899 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6900 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6901 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6902 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6903 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6904 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6905 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6906 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6907 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6908 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6909 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6910 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6911 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6912 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6913 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6914 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6915 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6917 /* SPE binary operations expecting a 5-bit unsigned literal. */
6918 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6920 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6921 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6922 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6923 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6924 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6925 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6926 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6927 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6928 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6929 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6930 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6931 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6932 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6933 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6934 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6935 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6936 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6937 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6938 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6939 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6940 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6941 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6942 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6943 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6944 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6945 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6947 /* Place-holder. Leave as last binary SPE builtin. */
6948 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6951 /* AltiVec predicates. */
6953 struct builtin_description_predicates
6955 const unsigned int mask;
6956 const enum insn_code icode;
6958 const char *const name;
6959 const enum rs6000_builtins code;
6962 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6964 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6965 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6966 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6967 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6968 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6969 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6970 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6971 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6972 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6973 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6974 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6975 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6976 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6978 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6979 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6980 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6983 /* SPE predicates. */
6984 static struct builtin_description bdesc_spe_predicates[] =
6986 /* Place-holder. Leave as first. */
6987 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6988 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6989 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6990 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6991 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6992 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6993 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6994 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6995 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6996 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6997 /* Place-holder. Leave as last. */
6998 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7001 /* SPE evsel predicates. */
7002 static struct builtin_description bdesc_spe_evsel[] =
7004 /* Place-holder. Leave as first. */
7005 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7006 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7007 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7008 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7009 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7010 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7011 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7012 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7013 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7014 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7015 /* Place-holder. Leave as last. */
7016 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7019 /* ABS* operations. */
7021 static const struct builtin_description bdesc_abs[] =
7023 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7024 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7025 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7026 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7027 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7028 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7029 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7032 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7035 static struct builtin_description bdesc_1arg[] =
7037 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7038 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7039 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7040 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7041 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7042 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7043 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7044 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7045 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7046 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7047 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7048 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7049 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7050 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7051 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7052 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7053 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7055 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7056 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7057 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7058 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7059 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7060 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7061 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7062 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7063 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7064 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7065 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7066 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7067 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7068 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7069 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7070 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7073 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7075 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7076 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7077 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7078 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7079 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7080 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7081 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7082 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7083 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7084 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7085 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7086 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7087 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7088 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7089 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7090 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7091 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7092 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7093 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7094 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7095 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7096 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7097 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7098 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7099 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7100 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7101 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7102 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7103 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7104 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7106 /* Place-holder. Leave as last unary SPE builtin. */
7107 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
7111 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7114 tree arg0 = CALL_EXPR_ARG (exp, 0);
7115 rtx op0 = expand_normal (arg0);
7116 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7117 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7119 if (icode == CODE_FOR_nothing)
7120 /* Builtin not supported on this processor. */
7123 /* If we got invalid arguments bail out before generating bad rtl. */
7124 if (arg0 == error_mark_node)
7127 if (icode == CODE_FOR_altivec_vspltisb
7128 || icode == CODE_FOR_altivec_vspltish
7129 || icode == CODE_FOR_altivec_vspltisw
7130 || icode == CODE_FOR_spe_evsplatfi
7131 || icode == CODE_FOR_spe_evsplati)
7133 /* Only allow 5-bit *signed* literals. */
7134 if (GET_CODE (op0) != CONST_INT
7135 || INTVAL (op0) > 15
7136 || INTVAL (op0) < -16)
7138 error ("argument 1 must be a 5-bit signed literal");
7144 || GET_MODE (target) != tmode
7145 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7146 target = gen_reg_rtx (tmode);
7148 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7149 op0 = copy_to_mode_reg (mode0, op0);
7151 pat = GEN_FCN (icode) (target, op0);
7160 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7162 rtx pat, scratch1, scratch2;
7163 tree arg0 = CALL_EXPR_ARG (exp, 0);
7164 rtx op0 = expand_normal (arg0);
7165 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7166 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7168 /* If we have invalid arguments, bail out before generating bad rtl. */
7169 if (arg0 == error_mark_node)
7173 || GET_MODE (target) != tmode
7174 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7175 target = gen_reg_rtx (tmode);
7177 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7178 op0 = copy_to_mode_reg (mode0, op0);
7180 scratch1 = gen_reg_rtx (mode0);
7181 scratch2 = gen_reg_rtx (mode0);
7183 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7192 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7195 tree arg0 = CALL_EXPR_ARG (exp, 0);
7196 tree arg1 = CALL_EXPR_ARG (exp, 1);
7197 rtx op0 = expand_normal (arg0);
7198 rtx op1 = expand_normal (arg1);
7199 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7200 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7201 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7203 if (icode == CODE_FOR_nothing)
7204 /* Builtin not supported on this processor. */
7207 /* If we got invalid arguments bail out before generating bad rtl. */
7208 if (arg0 == error_mark_node || arg1 == error_mark_node)
7211 if (icode == CODE_FOR_altivec_vcfux
7212 || icode == CODE_FOR_altivec_vcfsx
7213 || icode == CODE_FOR_altivec_vctsxs
7214 || icode == CODE_FOR_altivec_vctuxs
7215 || icode == CODE_FOR_altivec_vspltb
7216 || icode == CODE_FOR_altivec_vsplth
7217 || icode == CODE_FOR_altivec_vspltw
7218 || icode == CODE_FOR_spe_evaddiw
7219 || icode == CODE_FOR_spe_evldd
7220 || icode == CODE_FOR_spe_evldh
7221 || icode == CODE_FOR_spe_evldw
7222 || icode == CODE_FOR_spe_evlhhesplat
7223 || icode == CODE_FOR_spe_evlhhossplat
7224 || icode == CODE_FOR_spe_evlhhousplat
7225 || icode == CODE_FOR_spe_evlwhe
7226 || icode == CODE_FOR_spe_evlwhos
7227 || icode == CODE_FOR_spe_evlwhou
7228 || icode == CODE_FOR_spe_evlwhsplat
7229 || icode == CODE_FOR_spe_evlwwsplat
7230 || icode == CODE_FOR_spe_evrlwi
7231 || icode == CODE_FOR_spe_evslwi
7232 || icode == CODE_FOR_spe_evsrwis
7233 || icode == CODE_FOR_spe_evsubifw
7234 || icode == CODE_FOR_spe_evsrwiu)
7236 /* Only allow 5-bit unsigned literals. */
7238 if (TREE_CODE (arg1) != INTEGER_CST
7239 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7241 error ("argument 2 must be a 5-bit unsigned literal");
7247 || GET_MODE (target) != tmode
7248 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7249 target = gen_reg_rtx (tmode);
7251 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7252 op0 = copy_to_mode_reg (mode0, op0);
7253 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7254 op1 = copy_to_mode_reg (mode1, op1);
7256 pat = GEN_FCN (icode) (target, op0, op1);
7265 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7266 tree exp, rtx target)
7269 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7270 tree arg0 = CALL_EXPR_ARG (exp, 1);
7271 tree arg1 = CALL_EXPR_ARG (exp, 2);
7272 rtx op0 = expand_normal (arg0);
7273 rtx op1 = expand_normal (arg1);
7274 enum machine_mode tmode = SImode;
7275 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7276 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7279 if (TREE_CODE (cr6_form) != INTEGER_CST)
7281 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7285 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7287 gcc_assert (mode0 == mode1);
7289 /* If we have invalid arguments, bail out before generating bad rtl. */
7290 if (arg0 == error_mark_node || arg1 == error_mark_node)
7294 || GET_MODE (target) != tmode
7295 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7296 target = gen_reg_rtx (tmode);
7298 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7299 op0 = copy_to_mode_reg (mode0, op0);
7300 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7301 op1 = copy_to_mode_reg (mode1, op1);
7303 scratch = gen_reg_rtx (mode0);
7305 pat = GEN_FCN (icode) (scratch, op0, op1,
7306 gen_rtx_SYMBOL_REF (Pmode, opcode));
7311 /* The vec_any* and vec_all* predicates use the same opcodes for two
7312 different operations, but the bits in CR6 will be different
7313 depending on what information we want. So we have to play tricks
7314 with CR6 to get the right bits out.
7316 If you think this is disgusting, look at the specs for the
7317 AltiVec predicates. */
7319 switch (cr6_form_int)
7322 emit_insn (gen_cr6_test_for_zero (target));
7325 emit_insn (gen_cr6_test_for_zero_reverse (target));
7328 emit_insn (gen_cr6_test_for_lt (target));
7331 emit_insn (gen_cr6_test_for_lt_reverse (target));
7334 error ("argument 1 of __builtin_altivec_predicate is out of range");
7342 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7345 tree arg0 = CALL_EXPR_ARG (exp, 0);
7346 tree arg1 = CALL_EXPR_ARG (exp, 1);
7347 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7348 enum machine_mode mode0 = Pmode;
7349 enum machine_mode mode1 = Pmode;
7350 rtx op0 = expand_normal (arg0);
7351 rtx op1 = expand_normal (arg1);
7353 if (icode == CODE_FOR_nothing)
7354 /* Builtin not supported on this processor. */
7357 /* If we got invalid arguments bail out before generating bad rtl. */
7358 if (arg0 == error_mark_node || arg1 == error_mark_node)
7362 || GET_MODE (target) != tmode
7363 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7364 target = gen_reg_rtx (tmode);
7366 op1 = copy_to_mode_reg (mode1, op1);
7368 if (op0 == const0_rtx)
7370 addr = gen_rtx_MEM (tmode, op1);
7374 op0 = copy_to_mode_reg (mode0, op0);
7375 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7378 pat = GEN_FCN (icode) (target, addr);
7388 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7390 tree arg0 = CALL_EXPR_ARG (exp, 0);
7391 tree arg1 = CALL_EXPR_ARG (exp, 1);
7392 tree arg2 = CALL_EXPR_ARG (exp, 2);
7393 rtx op0 = expand_normal (arg0);
7394 rtx op1 = expand_normal (arg1);
7395 rtx op2 = expand_normal (arg2);
7397 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7398 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7399 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7401 /* Invalid arguments. Bail before doing anything stoopid! */
7402 if (arg0 == error_mark_node
7403 || arg1 == error_mark_node
7404 || arg2 == error_mark_node)
7407 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7408 op0 = copy_to_mode_reg (mode2, op0);
7409 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7410 op1 = copy_to_mode_reg (mode0, op1);
7411 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7412 op2 = copy_to_mode_reg (mode1, op2);
7414 pat = GEN_FCN (icode) (op1, op2, op0);
7421 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7423 tree arg0 = CALL_EXPR_ARG (exp, 0);
7424 tree arg1 = CALL_EXPR_ARG (exp, 1);
7425 tree arg2 = CALL_EXPR_ARG (exp, 2);
7426 rtx op0 = expand_normal (arg0);
7427 rtx op1 = expand_normal (arg1);
7428 rtx op2 = expand_normal (arg2);
7430 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7431 enum machine_mode mode1 = Pmode;
7432 enum machine_mode mode2 = Pmode;
7434 /* Invalid arguments. Bail before doing anything stoopid! */
7435 if (arg0 == error_mark_node
7436 || arg1 == error_mark_node
7437 || arg2 == error_mark_node)
7440 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7441 op0 = copy_to_mode_reg (tmode, op0);
7443 op2 = copy_to_mode_reg (mode2, op2);
7445 if (op1 == const0_rtx)
7447 addr = gen_rtx_MEM (tmode, op2);
7451 op1 = copy_to_mode_reg (mode1, op1);
7452 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7455 pat = GEN_FCN (icode) (addr, op0);
7462 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7465 tree arg0 = CALL_EXPR_ARG (exp, 0);
7466 tree arg1 = CALL_EXPR_ARG (exp, 1);
7467 tree arg2 = CALL_EXPR_ARG (exp, 2);
7468 rtx op0 = expand_normal (arg0);
7469 rtx op1 = expand_normal (arg1);
7470 rtx op2 = expand_normal (arg2);
7471 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7472 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7473 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7474 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7476 if (icode == CODE_FOR_nothing)
7477 /* Builtin not supported on this processor. */
7480 /* If we got invalid arguments bail out before generating bad rtl. */
7481 if (arg0 == error_mark_node
7482 || arg1 == error_mark_node
7483 || arg2 == error_mark_node)
7486 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7487 || icode == CODE_FOR_altivec_vsldoi_v4si
7488 || icode == CODE_FOR_altivec_vsldoi_v8hi
7489 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7491 /* Only allow 4-bit unsigned literals. */
7493 if (TREE_CODE (arg2) != INTEGER_CST
7494 || TREE_INT_CST_LOW (arg2) & ~0xf)
7496 error ("argument 3 must be a 4-bit unsigned literal");
7502 || GET_MODE (target) != tmode
7503 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7504 target = gen_reg_rtx (tmode);
7506 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7507 op0 = copy_to_mode_reg (mode0, op0);
7508 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7509 op1 = copy_to_mode_reg (mode1, op1);
7510 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7511 op2 = copy_to_mode_reg (mode2, op2);
7513 pat = GEN_FCN (icode) (target, op0, op1, op2);
7521 /* Expand the lvx builtins. */
7523 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7525 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7526 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7528 enum machine_mode tmode, mode0;
7530 enum insn_code icode;
7534 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7535 icode = CODE_FOR_altivec_lvx_v16qi;
7537 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7538 icode = CODE_FOR_altivec_lvx_v8hi;
7540 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7541 icode = CODE_FOR_altivec_lvx_v4si;
7543 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7544 icode = CODE_FOR_altivec_lvx_v4sf;
7553 arg0 = CALL_EXPR_ARG (exp, 0);
7554 op0 = expand_normal (arg0);
7555 tmode = insn_data[icode].operand[0].mode;
7556 mode0 = insn_data[icode].operand[1].mode;
7559 || GET_MODE (target) != tmode
7560 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7561 target = gen_reg_rtx (tmode);
7563 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7564 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7566 pat = GEN_FCN (icode) (target, op0);
7573 /* Expand the stvx builtins. */
7575 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7578 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7579 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7581 enum machine_mode mode0, mode1;
7583 enum insn_code icode;
7587 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7588 icode = CODE_FOR_altivec_stvx_v16qi;
7590 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7591 icode = CODE_FOR_altivec_stvx_v8hi;
7593 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7594 icode = CODE_FOR_altivec_stvx_v4si;
7596 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7597 icode = CODE_FOR_altivec_stvx_v4sf;
7604 arg0 = CALL_EXPR_ARG (exp, 0);
7605 arg1 = CALL_EXPR_ARG (exp, 1);
7606 op0 = expand_normal (arg0);
7607 op1 = expand_normal (arg1);
7608 mode0 = insn_data[icode].operand[0].mode;
7609 mode1 = insn_data[icode].operand[1].mode;
7611 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7612 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7613 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7614 op1 = copy_to_mode_reg (mode1, op1);
7616 pat = GEN_FCN (icode) (op0, op1);
7624 /* Expand the dst builtins. */
7626 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7629 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7630 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7631 tree arg0, arg1, arg2;
7632 enum machine_mode mode0, mode1, mode2;
7633 rtx pat, op0, op1, op2;
7634 struct builtin_description *d;
7639 /* Handle DST variants. */
7640 d = (struct builtin_description *) bdesc_dst;
7641 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7642 if (d->code == fcode)
7644 arg0 = CALL_EXPR_ARG (exp, 0);
7645 arg1 = CALL_EXPR_ARG (exp, 1);
7646 arg2 = CALL_EXPR_ARG (exp, 2);
7647 op0 = expand_normal (arg0);
7648 op1 = expand_normal (arg1);
7649 op2 = expand_normal (arg2);
7650 mode0 = insn_data[d->icode].operand[0].mode;
7651 mode1 = insn_data[d->icode].operand[1].mode;
7652 mode2 = insn_data[d->icode].operand[2].mode;
7654 /* Invalid arguments, bail out before generating bad rtl. */
7655 if (arg0 == error_mark_node
7656 || arg1 == error_mark_node
7657 || arg2 == error_mark_node)
7662 if (TREE_CODE (arg2) != INTEGER_CST
7663 || TREE_INT_CST_LOW (arg2) & ~0x3)
7665 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7669 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7670 op0 = copy_to_mode_reg (Pmode, op0);
7671 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7672 op1 = copy_to_mode_reg (mode1, op1);
7674 pat = GEN_FCN (d->icode) (op0, op1, op2);
7684 /* Expand vec_init builtin. */
7686 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7688 enum machine_mode tmode = TYPE_MODE (type);
7689 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7690 int i, n_elt = GET_MODE_NUNITS (tmode);
7691 rtvec v = rtvec_alloc (n_elt);
7693 gcc_assert (VECTOR_MODE_P (tmode));
7694 gcc_assert (n_elt == call_expr_nargs (exp));
7696 for (i = 0; i < n_elt; ++i)
7698 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
7699 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7702 if (!target || !register_operand (target, tmode))
7703 target = gen_reg_rtx (tmode);
7705 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7709 /* Return the integer constant in ARG. Constrain it to be in the range
7710 of the subparts of VEC_TYPE; issue an error if not. */
7713 get_element_number (tree vec_type, tree arg)
7715 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7717 if (!host_integerp (arg, 1)
7718 || (elt = tree_low_cst (arg, 1), elt > max))
7720 error ("selector must be an integer constant in the range 0..%wi", max);
7727 /* Expand vec_set builtin. */
7729 altivec_expand_vec_set_builtin (tree exp)
7731 enum machine_mode tmode, mode1;
7732 tree arg0, arg1, arg2;
7736 arg0 = CALL_EXPR_ARG (exp, 0);
7737 arg1 = CALL_EXPR_ARG (exp, 1);
7738 arg2 = CALL_EXPR_ARG (exp, 2);
7740 tmode = TYPE_MODE (TREE_TYPE (arg0));
7741 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7742 gcc_assert (VECTOR_MODE_P (tmode));
7744 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7745 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7746 elt = get_element_number (TREE_TYPE (arg0), arg2);
7748 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7749 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7751 op0 = force_reg (tmode, op0);
7752 op1 = force_reg (mode1, op1);
7754 rs6000_expand_vector_set (op0, op1, elt);
7759 /* Expand vec_ext builtin. */
7761 altivec_expand_vec_ext_builtin (tree exp, rtx target)
7763 enum machine_mode tmode, mode0;
7768 arg0 = CALL_EXPR_ARG (exp, 0);
7769 arg1 = CALL_EXPR_ARG (exp, 1);
7771 op0 = expand_normal (arg0);
7772 elt = get_element_number (TREE_TYPE (arg0), arg1);
7774 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7775 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7776 gcc_assert (VECTOR_MODE_P (mode0));
7778 op0 = force_reg (mode0, op0);
7780 if (optimize || !target || !register_operand (target, tmode))
7781 target = gen_reg_rtx (tmode);
7783 rs6000_expand_vector_extract (target, op0, elt);
7788 /* Expand the builtin in EXP and store the result in TARGET. Store
7789 true in *EXPANDEDP if we found a builtin to expand. */
7791 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7793 struct builtin_description *d;
7794 struct builtin_description_predicates *dp;
7796 enum insn_code icode;
7797 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7800 enum machine_mode tmode, mode0;
7801 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7803 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7804 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7807 error ("unresolved overload for Altivec builtin %qF", fndecl);
7811 target = altivec_expand_ld_builtin (exp, target, expandedp);
7815 target = altivec_expand_st_builtin (exp, target, expandedp);
7819 target = altivec_expand_dst_builtin (exp, target, expandedp);
7827 case ALTIVEC_BUILTIN_STVX:
7828 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
7829 case ALTIVEC_BUILTIN_STVEBX:
7830 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
7831 case ALTIVEC_BUILTIN_STVEHX:
7832 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
7833 case ALTIVEC_BUILTIN_STVEWX:
7834 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
7835 case ALTIVEC_BUILTIN_STVXL:
7836 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
7838 case ALTIVEC_BUILTIN_MFVSCR:
7839 icode = CODE_FOR_altivec_mfvscr;
7840 tmode = insn_data[icode].operand[0].mode;
7843 || GET_MODE (target) != tmode
7844 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7845 target = gen_reg_rtx (tmode);
7847 pat = GEN_FCN (icode) (target);
7853 case ALTIVEC_BUILTIN_MTVSCR:
7854 icode = CODE_FOR_altivec_mtvscr;
7855 arg0 = CALL_EXPR_ARG (exp, 0);
7856 op0 = expand_normal (arg0);
7857 mode0 = insn_data[icode].operand[0].mode;
7859 /* If we got invalid arguments bail out before generating bad rtl. */
7860 if (arg0 == error_mark_node)
7863 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7864 op0 = copy_to_mode_reg (mode0, op0);
7866 pat = GEN_FCN (icode) (op0);
7871 case ALTIVEC_BUILTIN_DSSALL:
7872 emit_insn (gen_altivec_dssall ());
7875 case ALTIVEC_BUILTIN_DSS:
7876 icode = CODE_FOR_altivec_dss;
7877 arg0 = CALL_EXPR_ARG (exp, 0);
7879 op0 = expand_normal (arg0);
7880 mode0 = insn_data[icode].operand[0].mode;
7882 /* If we got invalid arguments bail out before generating bad rtl. */
7883 if (arg0 == error_mark_node)
7886 if (TREE_CODE (arg0) != INTEGER_CST
7887 || TREE_INT_CST_LOW (arg0) & ~0x3)
7889 error ("argument to dss must be a 2-bit unsigned literal");
7893 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7894 op0 = copy_to_mode_reg (mode0, op0);
7896 emit_insn (gen_altivec_dss (op0));
7899 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7900 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7901 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7902 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7903 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
7905 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7906 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7907 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7908 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7909 return altivec_expand_vec_set_builtin (exp);
7911 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7912 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7913 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7914 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7915 return altivec_expand_vec_ext_builtin (exp, target);
7922 /* Expand abs* operations. */
7923 d = (struct builtin_description *) bdesc_abs;
7924 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7925 if (d->code == fcode)
7926 return altivec_expand_abs_builtin (d->icode, exp, target);
7928 /* Expand the AltiVec predicates. */
7929 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7930 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7931 if (dp->code == fcode)
7932 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7935 /* LV* are funky. We initialized them differently. */
7938 case ALTIVEC_BUILTIN_LVSL:
7939 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7941 case ALTIVEC_BUILTIN_LVSR:
7942 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7944 case ALTIVEC_BUILTIN_LVEBX:
7945 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7947 case ALTIVEC_BUILTIN_LVEHX:
7948 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7950 case ALTIVEC_BUILTIN_LVEWX:
7951 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7953 case ALTIVEC_BUILTIN_LVXL:
7954 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7956 case ALTIVEC_BUILTIN_LVX:
7957 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7968 /* Binops that need to be initialized manually, but can be expanded
7969 automagically by rs6000_expand_binop_builtin. */
7970 static struct builtin_description bdesc_2arg_spe[] =
7972 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7973 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7974 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7975 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7976 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7977 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7978 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7979 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7980 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7981 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7982 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7983 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7984 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7985 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7986 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7987 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7988 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7989 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7990 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7991 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7992 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7993 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7996 /* Expand the builtin in EXP and store the result in TARGET. Store
7997 true in *EXPANDEDP if we found a builtin to expand.
7999 This expands the SPE builtins that are not simple unary and binary
8002 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8004 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8006 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8007 enum insn_code icode;
8008 enum machine_mode tmode, mode0;
8010 struct builtin_description *d;
8015 /* Syntax check for a 5-bit unsigned immediate. */
8018 case SPE_BUILTIN_EVSTDD:
8019 case SPE_BUILTIN_EVSTDH:
8020 case SPE_BUILTIN_EVSTDW:
8021 case SPE_BUILTIN_EVSTWHE:
8022 case SPE_BUILTIN_EVSTWHO:
8023 case SPE_BUILTIN_EVSTWWE:
8024 case SPE_BUILTIN_EVSTWWO:
8025 arg1 = CALL_EXPR_ARG (exp, 2);
8026 if (TREE_CODE (arg1) != INTEGER_CST
8027 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8029 error ("argument 2 must be a 5-bit unsigned literal");
8037 /* The evsplat*i instructions are not quite generic. */
8040 case SPE_BUILTIN_EVSPLATFI:
8041 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8043 case SPE_BUILTIN_EVSPLATI:
8044 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8050 d = (struct builtin_description *) bdesc_2arg_spe;
8051 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8052 if (d->code == fcode)
8053 return rs6000_expand_binop_builtin (d->icode, exp, target);
8055 d = (struct builtin_description *) bdesc_spe_predicates;
8056 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8057 if (d->code == fcode)
8058 return spe_expand_predicate_builtin (d->icode, exp, target);
8060 d = (struct builtin_description *) bdesc_spe_evsel;
8061 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8062 if (d->code == fcode)
8063 return spe_expand_evsel_builtin (d->icode, exp, target);
8067 case SPE_BUILTIN_EVSTDDX:
8068 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8069 case SPE_BUILTIN_EVSTDHX:
8070 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8071 case SPE_BUILTIN_EVSTDWX:
8072 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8073 case SPE_BUILTIN_EVSTWHEX:
8074 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8075 case SPE_BUILTIN_EVSTWHOX:
8076 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8077 case SPE_BUILTIN_EVSTWWEX:
8078 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8079 case SPE_BUILTIN_EVSTWWOX:
8080 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8081 case SPE_BUILTIN_EVSTDD:
8082 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8083 case SPE_BUILTIN_EVSTDH:
8084 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8085 case SPE_BUILTIN_EVSTDW:
8086 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8087 case SPE_BUILTIN_EVSTWHE:
8088 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8089 case SPE_BUILTIN_EVSTWHO:
8090 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8091 case SPE_BUILTIN_EVSTWWE:
8092 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8093 case SPE_BUILTIN_EVSTWWO:
8094 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8095 case SPE_BUILTIN_MFSPEFSCR:
8096 icode = CODE_FOR_spe_mfspefscr;
8097 tmode = insn_data[icode].operand[0].mode;
8100 || GET_MODE (target) != tmode
8101 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8102 target = gen_reg_rtx (tmode);
8104 pat = GEN_FCN (icode) (target);
8109 case SPE_BUILTIN_MTSPEFSCR:
8110 icode = CODE_FOR_spe_mtspefscr;
8111 arg0 = CALL_EXPR_ARG (exp, 0);
8112 op0 = expand_normal (arg0);
8113 mode0 = insn_data[icode].operand[0].mode;
8115 if (arg0 == error_mark_node)
8118 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8119 op0 = copy_to_mode_reg (mode0, op0);
8121 pat = GEN_FCN (icode) (op0);
8134 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8136 rtx pat, scratch, tmp;
8137 tree form = CALL_EXPR_ARG (exp, 0);
8138 tree arg0 = CALL_EXPR_ARG (exp, 1);
8139 tree arg1 = CALL_EXPR_ARG (exp, 2);
8140 rtx op0 = expand_normal (arg0);
8141 rtx op1 = expand_normal (arg1);
8142 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8143 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8147 if (TREE_CODE (form) != INTEGER_CST)
8149 error ("argument 1 of __builtin_spe_predicate must be a constant");
8153 form_int = TREE_INT_CST_LOW (form);
8155 gcc_assert (mode0 == mode1);
8157 if (arg0 == error_mark_node || arg1 == error_mark_node)
8161 || GET_MODE (target) != SImode
8162 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8163 target = gen_reg_rtx (SImode);
8165 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8166 op0 = copy_to_mode_reg (mode0, op0);
8167 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8168 op1 = copy_to_mode_reg (mode1, op1);
8170 scratch = gen_reg_rtx (CCmode);
8172 pat = GEN_FCN (icode) (scratch, op0, op1);
8177 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8178 _lower_. We use one compare, but look in different bits of the
8179 CR for each variant.
8181 There are 2 elements in each SPE simd type (upper/lower). The CR
8182 bits are set as follows:
8184 BIT0 | BIT 1 | BIT 2 | BIT 3
8185 U | L | (U | L) | (U & L)
8187 So, for an "all" relationship, BIT 3 would be set.
8188 For an "any" relationship, BIT 2 would be set. Etc.
8190 Following traditional nomenclature, these bits map to:
8192 BIT0 | BIT 1 | BIT 2 | BIT 3
8195 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8200 /* All variant. OV bit. */
8202 /* We need to get to the OV bit, which is the ORDERED bit. We
8203 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8204 that's ugly and will make validate_condition_mode die.
8205 So let's just use another pattern. */
8206 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8208 /* Any variant. EQ bit. */
8212 /* Upper variant. LT bit. */
8216 /* Lower variant. GT bit. */
8221 error ("argument 1 of __builtin_spe_predicate is out of range");
8225 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8226 emit_move_insn (target, tmp);
8231 /* The evsel builtins look like this:
8233 e = __builtin_spe_evsel_OP (a, b, c, d);
8237 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8238 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8242 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8245 tree arg0 = CALL_EXPR_ARG (exp, 0);
8246 tree arg1 = CALL_EXPR_ARG (exp, 1);
8247 tree arg2 = CALL_EXPR_ARG (exp, 2);
8248 tree arg3 = CALL_EXPR_ARG (exp, 3);
8249 rtx op0 = expand_normal (arg0);
8250 rtx op1 = expand_normal (arg1);
8251 rtx op2 = expand_normal (arg2);
8252 rtx op3 = expand_normal (arg3);
8253 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8254 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8256 gcc_assert (mode0 == mode1);
8258 if (arg0 == error_mark_node || arg1 == error_mark_node
8259 || arg2 == error_mark_node || arg3 == error_mark_node)
8263 || GET_MODE (target) != mode0
8264 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8265 target = gen_reg_rtx (mode0);
8267 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8268 op0 = copy_to_mode_reg (mode0, op0);
8269 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8270 op1 = copy_to_mode_reg (mode0, op1);
8271 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8272 op2 = copy_to_mode_reg (mode0, op2);
8273 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8274 op3 = copy_to_mode_reg (mode0, op3);
8276 /* Generate the compare. */
8277 scratch = gen_reg_rtx (CCmode);
8278 pat = GEN_FCN (icode) (scratch, op0, op1);
8283 if (mode0 == V2SImode)
8284 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8286 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8291 /* Expand an expression EXP that calls a built-in function,
8292 with result going to TARGET if that's convenient
8293 (and in mode MODE if that's convenient).
8294 SUBTARGET may be used as the target for computing one of EXP's operands.
8295 IGNORE is nonzero if the value is to be ignored. */
8298 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8299 enum machine_mode mode ATTRIBUTE_UNUSED,
8300 int ignore ATTRIBUTE_UNUSED)
8302 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8303 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8304 struct builtin_description *d;
8309 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8310 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8312 int icode = (int) CODE_FOR_altivec_lvsr;
8313 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8314 enum machine_mode mode = insn_data[icode].operand[1].mode;
8318 gcc_assert (TARGET_ALTIVEC);
8320 arg = CALL_EXPR_ARG (exp, 0);
8321 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8322 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8323 addr = memory_address (mode, op);
8324 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8328 /* For the load case need to negate the address. */
8329 op = gen_reg_rtx (GET_MODE (addr));
8330 emit_insn (gen_rtx_SET (VOIDmode, op,
8331 gen_rtx_NEG (GET_MODE (addr), addr)));
8333 op = gen_rtx_MEM (mode, op);
8336 || GET_MODE (target) != tmode
8337 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8338 target = gen_reg_rtx (tmode);
8340 /*pat = gen_altivec_lvsr (target, op);*/
8341 pat = GEN_FCN (icode) (target, op);
8349 /* FIXME: There's got to be a nicer way to handle this case than
8350 constructing a new CALL_EXPR. */
8351 if (fcode == ALTIVEC_BUILTIN_VCFUX
8352 || fcode == ALTIVEC_BUILTIN_VCFSX)
8354 if (call_expr_nargs (exp) == 1)
8355 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8356 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8361 ret = altivec_expand_builtin (exp, target, &success);
8368 ret = spe_expand_builtin (exp, target, &success);
8374 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
8376 /* Handle simple unary operations. */
8377 d = (struct builtin_description *) bdesc_1arg;
8378 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8379 if (d->code == fcode)
8380 return rs6000_expand_unop_builtin (d->icode, exp, target);
8382 /* Handle simple binary operations. */
8383 d = (struct builtin_description *) bdesc_2arg;
8384 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8385 if (d->code == fcode)
8386 return rs6000_expand_binop_builtin (d->icode, exp, target);
8388 /* Handle simple ternary operations. */
8389 d = (struct builtin_description *) bdesc_3arg;
8390 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8391 if (d->code == fcode)
8392 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8398 build_opaque_vector_type (tree node, int nunits)
8400 node = copy_node (node);
8401 TYPE_MAIN_VARIANT (node) = node;
8402 return build_vector_type (node, nunits);
8406 rs6000_init_builtins (void)
8408 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8409 V2SF_type_node = build_vector_type (float_type_node, 2);
8410 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8411 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8412 V4SF_type_node = build_vector_type (float_type_node, 4);
8413 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8414 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8416 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8417 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8418 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8420 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8421 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8422 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8423 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8425 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8426 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8427 'vector unsigned short'. */
8429 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8430 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8431 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8432 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8434 long_integer_type_internal_node = long_integer_type_node;
8435 long_unsigned_type_internal_node = long_unsigned_type_node;
8436 intQI_type_internal_node = intQI_type_node;
8437 uintQI_type_internal_node = unsigned_intQI_type_node;
8438 intHI_type_internal_node = intHI_type_node;
8439 uintHI_type_internal_node = unsigned_intHI_type_node;
8440 intSI_type_internal_node = intSI_type_node;
8441 uintSI_type_internal_node = unsigned_intSI_type_node;
8442 float_type_internal_node = float_type_node;
8443 void_type_internal_node = void_type_node;
8445 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8446 get_identifier ("__bool char"),
8447 bool_char_type_node));
8448 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8449 get_identifier ("__bool short"),
8450 bool_short_type_node));
8451 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8452 get_identifier ("__bool int"),
8453 bool_int_type_node));
8454 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8455 get_identifier ("__pixel"),
8458 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8459 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8460 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8461 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8463 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8464 get_identifier ("__vector unsigned char"),
8465 unsigned_V16QI_type_node));
8466 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8467 get_identifier ("__vector signed char"),
8469 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8470 get_identifier ("__vector __bool char"),
8471 bool_V16QI_type_node));
8473 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8474 get_identifier ("__vector unsigned short"),
8475 unsigned_V8HI_type_node));
8476 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8477 get_identifier ("__vector signed short"),
8479 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8480 get_identifier ("__vector __bool short"),
8481 bool_V8HI_type_node));
8483 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8484 get_identifier ("__vector unsigned int"),
8485 unsigned_V4SI_type_node));
8486 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8487 get_identifier ("__vector signed int"),
8489 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8490 get_identifier ("__vector __bool int"),
8491 bool_V4SI_type_node));
8493 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8494 get_identifier ("__vector float"),
8496 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8497 get_identifier ("__vector __pixel"),
8498 pixel_V8HI_type_node));
8501 spe_init_builtins ();
8503 altivec_init_builtins ();
8504 if (TARGET_ALTIVEC || TARGET_SPE)
8505 rs6000_common_init_builtins ();
8508 /* AIX libm provides clog as __clog. */
8509 if (built_in_decls [BUILT_IN_CLOG])
8510 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8514 /* Search through a set of builtins and enable the mask bits.
8515 DESC is an array of builtins.
8516 SIZE is the total number of builtins.
8517 START is the builtin enum at which to start.
8518 END is the builtin enum at which to end. */
8520 enable_mask_for_builtins (struct builtin_description *desc, int size,
8521 enum rs6000_builtins start,
8522 enum rs6000_builtins end)
8526 for (i = 0; i < size; ++i)
8527 if (desc[i].code == start)
8533 for (; i < size; ++i)
8535 /* Flip all the bits on. */
8536 desc[i].mask = target_flags;
8537 if (desc[i].code == end)
8543 spe_init_builtins (void)
8545 tree endlink = void_list_node;
8546 tree puint_type_node = build_pointer_type (unsigned_type_node);
8547 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
8548 struct builtin_description *d;
8551 tree v2si_ftype_4_v2si
8552 = build_function_type
8553 (opaque_V2SI_type_node,
8554 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8555 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8556 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8557 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8560 tree v2sf_ftype_4_v2sf
8561 = build_function_type
8562 (opaque_V2SF_type_node,
8563 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8564 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8565 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8566 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8569 tree int_ftype_int_v2si_v2si
8570 = build_function_type
8572 tree_cons (NULL_TREE, integer_type_node,
8573 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8574 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8577 tree int_ftype_int_v2sf_v2sf
8578 = build_function_type
8580 tree_cons (NULL_TREE, integer_type_node,
8581 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8582 tree_cons (NULL_TREE, opaque_V2SF_type_node,
8585 tree void_ftype_v2si_puint_int
8586 = build_function_type (void_type_node,
8587 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8588 tree_cons (NULL_TREE, puint_type_node,
8589 tree_cons (NULL_TREE,
8593 tree void_ftype_v2si_puint_char
8594 = build_function_type (void_type_node,
8595 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8596 tree_cons (NULL_TREE, puint_type_node,
8597 tree_cons (NULL_TREE,
8601 tree void_ftype_v2si_pv2si_int
8602 = build_function_type (void_type_node,
8603 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8604 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8605 tree_cons (NULL_TREE,
8609 tree void_ftype_v2si_pv2si_char
8610 = build_function_type (void_type_node,
8611 tree_cons (NULL_TREE, opaque_V2SI_type_node,
8612 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8613 tree_cons (NULL_TREE,
8618 = build_function_type (void_type_node,
8619 tree_cons (NULL_TREE, integer_type_node, endlink));
8622 = build_function_type (integer_type_node, endlink);
8624 tree v2si_ftype_pv2si_int
8625 = build_function_type (opaque_V2SI_type_node,
8626 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8627 tree_cons (NULL_TREE, integer_type_node,
8630 tree v2si_ftype_puint_int
8631 = build_function_type (opaque_V2SI_type_node,
8632 tree_cons (NULL_TREE, puint_type_node,
8633 tree_cons (NULL_TREE, integer_type_node,
8636 tree v2si_ftype_pushort_int
8637 = build_function_type (opaque_V2SI_type_node,
8638 tree_cons (NULL_TREE, pushort_type_node,
8639 tree_cons (NULL_TREE, integer_type_node,
8642 tree v2si_ftype_signed_char
8643 = build_function_type (opaque_V2SI_type_node,
8644 tree_cons (NULL_TREE, signed_char_type_node,
8647 /* The initialization of the simple binary and unary builtins is
8648 done in rs6000_common_init_builtins, but we have to enable the
8649 mask bits here manually because we have run out of `target_flags'
8650 bits. We really need to redesign this mask business. */
8652 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8653 ARRAY_SIZE (bdesc_2arg),
8656 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8657 ARRAY_SIZE (bdesc_1arg),
8659 SPE_BUILTIN_EVSUBFUSIAAW);
8660 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8661 ARRAY_SIZE (bdesc_spe_predicates),
8662 SPE_BUILTIN_EVCMPEQ,
8663 SPE_BUILTIN_EVFSTSTLT);
8664 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8665 ARRAY_SIZE (bdesc_spe_evsel),
8666 SPE_BUILTIN_EVSEL_CMPGTS,
8667 SPE_BUILTIN_EVSEL_FSTSTEQ);
8669 (*lang_hooks.decls.pushdecl)
8670 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8671 opaque_V2SI_type_node));
8673 /* Initialize irregular SPE builtins. */
8675 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8676 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8677 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8678 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8679 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8680 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8681 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8682 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8683 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8684 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8685 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8686 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8687 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8688 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8689 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8690 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8691 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8692 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8695 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8696 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8697 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8698 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8699 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8700 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8701 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8702 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8703 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8704 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8705 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8706 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8707 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8708 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8709 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8710 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8711 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8712 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8713 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8714 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8715 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8716 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8719 d = (struct builtin_description *) bdesc_spe_predicates;
8720 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8724 switch (insn_data[d->icode].operand[1].mode)
8727 type = int_ftype_int_v2si_v2si;
8730 type = int_ftype_int_v2sf_v2sf;
8736 def_builtin (d->mask, d->name, type, d->code);
8739 /* Evsel predicates. */
8740 d = (struct builtin_description *) bdesc_spe_evsel;
8741 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8745 switch (insn_data[d->icode].operand[1].mode)
8748 type = v2si_ftype_4_v2si;
8751 type = v2sf_ftype_4_v2sf;
8757 def_builtin (d->mask, d->name, type, d->code);
8762 altivec_init_builtins (void)
8764 struct builtin_description *d;
8765 struct builtin_description_predicates *dp;
8769 tree pfloat_type_node = build_pointer_type (float_type_node);
8770 tree pint_type_node = build_pointer_type (integer_type_node);
8771 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8772 tree pchar_type_node = build_pointer_type (char_type_node);
8774 tree pvoid_type_node = build_pointer_type (void_type_node);
8776 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8777 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8778 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8779 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8781 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8783 tree int_ftype_opaque
8784 = build_function_type_list (integer_type_node,
8785 opaque_V4SI_type_node, NULL_TREE);
8787 tree opaque_ftype_opaque_int
8788 = build_function_type_list (opaque_V4SI_type_node,
8789 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8790 tree opaque_ftype_opaque_opaque_int
8791 = build_function_type_list (opaque_V4SI_type_node,
8792 opaque_V4SI_type_node, opaque_V4SI_type_node,
8793 integer_type_node, NULL_TREE);
8794 tree int_ftype_int_opaque_opaque
8795 = build_function_type_list (integer_type_node,
8796 integer_type_node, opaque_V4SI_type_node,
8797 opaque_V4SI_type_node, NULL_TREE);
8798 tree int_ftype_int_v4si_v4si
8799 = build_function_type_list (integer_type_node,
8800 integer_type_node, V4SI_type_node,
8801 V4SI_type_node, NULL_TREE);
8802 tree v4sf_ftype_pcfloat
8803 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8804 tree void_ftype_pfloat_v4sf
8805 = build_function_type_list (void_type_node,
8806 pfloat_type_node, V4SF_type_node, NULL_TREE);
8807 tree v4si_ftype_pcint
8808 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8809 tree void_ftype_pint_v4si
8810 = build_function_type_list (void_type_node,
8811 pint_type_node, V4SI_type_node, NULL_TREE);
8812 tree v8hi_ftype_pcshort
8813 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8814 tree void_ftype_pshort_v8hi
8815 = build_function_type_list (void_type_node,
8816 pshort_type_node, V8HI_type_node, NULL_TREE);
8817 tree v16qi_ftype_pcchar
8818 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8819 tree void_ftype_pchar_v16qi
8820 = build_function_type_list (void_type_node,
8821 pchar_type_node, V16QI_type_node, NULL_TREE);
8822 tree void_ftype_v4si
8823 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8824 tree v8hi_ftype_void
8825 = build_function_type (V8HI_type_node, void_list_node);
8826 tree void_ftype_void
8827 = build_function_type (void_type_node, void_list_node);
8829 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8831 tree opaque_ftype_long_pcvoid
8832 = build_function_type_list (opaque_V4SI_type_node,
8833 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8834 tree v16qi_ftype_long_pcvoid
8835 = build_function_type_list (V16QI_type_node,
8836 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8837 tree v8hi_ftype_long_pcvoid
8838 = build_function_type_list (V8HI_type_node,
8839 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8840 tree v4si_ftype_long_pcvoid
8841 = build_function_type_list (V4SI_type_node,
8842 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8844 tree void_ftype_opaque_long_pvoid
8845 = build_function_type_list (void_type_node,
8846 opaque_V4SI_type_node, long_integer_type_node,
8847 pvoid_type_node, NULL_TREE);
8848 tree void_ftype_v4si_long_pvoid
8849 = build_function_type_list (void_type_node,
8850 V4SI_type_node, long_integer_type_node,
8851 pvoid_type_node, NULL_TREE);
8852 tree void_ftype_v16qi_long_pvoid
8853 = build_function_type_list (void_type_node,
8854 V16QI_type_node, long_integer_type_node,
8855 pvoid_type_node, NULL_TREE);
8856 tree void_ftype_v8hi_long_pvoid
8857 = build_function_type_list (void_type_node,
8858 V8HI_type_node, long_integer_type_node,
8859 pvoid_type_node, NULL_TREE);
8860 tree int_ftype_int_v8hi_v8hi
8861 = build_function_type_list (integer_type_node,
8862 integer_type_node, V8HI_type_node,
8863 V8HI_type_node, NULL_TREE);
8864 tree int_ftype_int_v16qi_v16qi
8865 = build_function_type_list (integer_type_node,
8866 integer_type_node, V16QI_type_node,
8867 V16QI_type_node, NULL_TREE);
8868 tree int_ftype_int_v4sf_v4sf
8869 = build_function_type_list (integer_type_node,
8870 integer_type_node, V4SF_type_node,
8871 V4SF_type_node, NULL_TREE);
8872 tree v4si_ftype_v4si
8873 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8874 tree v8hi_ftype_v8hi
8875 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8876 tree v16qi_ftype_v16qi
8877 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8878 tree v4sf_ftype_v4sf
8879 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8880 tree void_ftype_pcvoid_int_int
8881 = build_function_type_list (void_type_node,
8882 pcvoid_type_node, integer_type_node,
8883 integer_type_node, NULL_TREE);
8885 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8886 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8887 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8888 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8889 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8890 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8891 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8892 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8893 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8894 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8895 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8896 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8897 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8898 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8899 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8900 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8901 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8902 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8903 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8904 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8905 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8906 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8907 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8908 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8909 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8910 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8911 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8912 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8913 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8914 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8915 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8916 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8917 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8918 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8919 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8920 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8921 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8922 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8923 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8924 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8925 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8926 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8927 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8928 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8929 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8930 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8932 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8934 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8935 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8936 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8937 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8938 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8939 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8940 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8941 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8942 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8943 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8945 /* Add the DST variants. */
8946 d = (struct builtin_description *) bdesc_dst;
8947 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8948 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8950 /* Initialize the predicates. */
8951 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8952 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8954 enum machine_mode mode1;
8956 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8957 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8962 mode1 = insn_data[dp->icode].operand[1].mode;
8967 type = int_ftype_int_opaque_opaque;
8970 type = int_ftype_int_v4si_v4si;
8973 type = int_ftype_int_v8hi_v8hi;
8976 type = int_ftype_int_v16qi_v16qi;
8979 type = int_ftype_int_v4sf_v4sf;
8985 def_builtin (dp->mask, dp->name, type, dp->code);
8988 /* Initialize the abs* operators. */
8989 d = (struct builtin_description *) bdesc_abs;
8990 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8992 enum machine_mode mode0;
8995 mode0 = insn_data[d->icode].operand[0].mode;
9000 type = v4si_ftype_v4si;
9003 type = v8hi_ftype_v8hi;
9006 type = v16qi_ftype_v16qi;
9009 type = v4sf_ftype_v4sf;
9015 def_builtin (d->mask, d->name, type, d->code);
9022 /* Initialize target builtin that implements
9023 targetm.vectorize.builtin_mask_for_load. */
9025 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9026 v16qi_ftype_long_pcvoid,
9027 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9028 BUILT_IN_MD, NULL, NULL_TREE);
9029 TREE_READONLY (decl) = 1;
9030 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9031 altivec_builtin_mask_for_load = decl;
9034 /* Access to the vec_init patterns. */
9035 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9036 integer_type_node, integer_type_node,
9037 integer_type_node, NULL_TREE);
9038 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9039 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9041 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9042 short_integer_type_node,
9043 short_integer_type_node,
9044 short_integer_type_node,
9045 short_integer_type_node,
9046 short_integer_type_node,
9047 short_integer_type_node,
9048 short_integer_type_node, NULL_TREE);
9049 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9050 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9052 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9053 char_type_node, char_type_node,
9054 char_type_node, char_type_node,
9055 char_type_node, char_type_node,
9056 char_type_node, char_type_node,
9057 char_type_node, char_type_node,
9058 char_type_node, char_type_node,
9059 char_type_node, char_type_node,
9060 char_type_node, NULL_TREE);
9061 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9062 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9064 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9065 float_type_node, float_type_node,
9066 float_type_node, NULL_TREE);
9067 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9068 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9070 /* Access to the vec_set patterns. */
9071 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9073 integer_type_node, NULL_TREE);
9074 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9075 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9077 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9079 integer_type_node, NULL_TREE);
9080 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9081 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9083 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9085 integer_type_node, NULL_TREE);
9086 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9087 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9089 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9091 integer_type_node, NULL_TREE);
9092 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9093 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9095 /* Access to the vec_extract patterns. */
9096 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9097 integer_type_node, NULL_TREE);
9098 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9099 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9101 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9102 integer_type_node, NULL_TREE);
9103 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9104 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9106 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9107 integer_type_node, NULL_TREE);
9108 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9109 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9111 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9112 integer_type_node, NULL_TREE);
9113 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9114 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9118 rs6000_common_init_builtins (void)
9120 struct builtin_description *d;
9123 tree v4sf_ftype_v4sf_v4sf_v16qi
9124 = build_function_type_list (V4SF_type_node,
9125 V4SF_type_node, V4SF_type_node,
9126 V16QI_type_node, NULL_TREE);
9127 tree v4si_ftype_v4si_v4si_v16qi
9128 = build_function_type_list (V4SI_type_node,
9129 V4SI_type_node, V4SI_type_node,
9130 V16QI_type_node, NULL_TREE);
9131 tree v8hi_ftype_v8hi_v8hi_v16qi
9132 = build_function_type_list (V8HI_type_node,
9133 V8HI_type_node, V8HI_type_node,
9134 V16QI_type_node, NULL_TREE);
9135 tree v16qi_ftype_v16qi_v16qi_v16qi
9136 = build_function_type_list (V16QI_type_node,
9137 V16QI_type_node, V16QI_type_node,
9138 V16QI_type_node, NULL_TREE);
9140 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9142 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9143 tree v16qi_ftype_int
9144 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9145 tree v8hi_ftype_v16qi
9146 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9147 tree v4sf_ftype_v4sf
9148 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9150 tree v2si_ftype_v2si_v2si
9151 = build_function_type_list (opaque_V2SI_type_node,
9152 opaque_V2SI_type_node,
9153 opaque_V2SI_type_node, NULL_TREE);
9155 tree v2sf_ftype_v2sf_v2sf
9156 = build_function_type_list (opaque_V2SF_type_node,
9157 opaque_V2SF_type_node,
9158 opaque_V2SF_type_node, NULL_TREE);
9160 tree v2si_ftype_int_int
9161 = build_function_type_list (opaque_V2SI_type_node,
9162 integer_type_node, integer_type_node,
9165 tree opaque_ftype_opaque
9166 = build_function_type_list (opaque_V4SI_type_node,
9167 opaque_V4SI_type_node, NULL_TREE);
9169 tree v2si_ftype_v2si
9170 = build_function_type_list (opaque_V2SI_type_node,
9171 opaque_V2SI_type_node, NULL_TREE);
9173 tree v2sf_ftype_v2sf
9174 = build_function_type_list (opaque_V2SF_type_node,
9175 opaque_V2SF_type_node, NULL_TREE);
9177 tree v2sf_ftype_v2si
9178 = build_function_type_list (opaque_V2SF_type_node,
9179 opaque_V2SI_type_node, NULL_TREE);
9181 tree v2si_ftype_v2sf
9182 = build_function_type_list (opaque_V2SI_type_node,
9183 opaque_V2SF_type_node, NULL_TREE);
9185 tree v2si_ftype_v2si_char
9186 = build_function_type_list (opaque_V2SI_type_node,
9187 opaque_V2SI_type_node,
9188 char_type_node, NULL_TREE);
9190 tree v2si_ftype_int_char
9191 = build_function_type_list (opaque_V2SI_type_node,
9192 integer_type_node, char_type_node, NULL_TREE);
9194 tree v2si_ftype_char
9195 = build_function_type_list (opaque_V2SI_type_node,
9196 char_type_node, NULL_TREE);
9198 tree int_ftype_int_int
9199 = build_function_type_list (integer_type_node,
9200 integer_type_node, integer_type_node,
9203 tree opaque_ftype_opaque_opaque
9204 = build_function_type_list (opaque_V4SI_type_node,
9205 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9206 tree v4si_ftype_v4si_v4si
9207 = build_function_type_list (V4SI_type_node,
9208 V4SI_type_node, V4SI_type_node, NULL_TREE);
9209 tree v4sf_ftype_v4si_int
9210 = build_function_type_list (V4SF_type_node,
9211 V4SI_type_node, integer_type_node, NULL_TREE);
9212 tree v4si_ftype_v4sf_int
9213 = build_function_type_list (V4SI_type_node,
9214 V4SF_type_node, integer_type_node, NULL_TREE);
9215 tree v4si_ftype_v4si_int
9216 = build_function_type_list (V4SI_type_node,
9217 V4SI_type_node, integer_type_node, NULL_TREE);
9218 tree v8hi_ftype_v8hi_int
9219 = build_function_type_list (V8HI_type_node,
9220 V8HI_type_node, integer_type_node, NULL_TREE);
9221 tree v16qi_ftype_v16qi_int
9222 = build_function_type_list (V16QI_type_node,
9223 V16QI_type_node, integer_type_node, NULL_TREE);
9224 tree v16qi_ftype_v16qi_v16qi_int
9225 = build_function_type_list (V16QI_type_node,
9226 V16QI_type_node, V16QI_type_node,
9227 integer_type_node, NULL_TREE);
9228 tree v8hi_ftype_v8hi_v8hi_int
9229 = build_function_type_list (V8HI_type_node,
9230 V8HI_type_node, V8HI_type_node,
9231 integer_type_node, NULL_TREE);
9232 tree v4si_ftype_v4si_v4si_int
9233 = build_function_type_list (V4SI_type_node,
9234 V4SI_type_node, V4SI_type_node,
9235 integer_type_node, NULL_TREE);
9236 tree v4sf_ftype_v4sf_v4sf_int
9237 = build_function_type_list (V4SF_type_node,
9238 V4SF_type_node, V4SF_type_node,
9239 integer_type_node, NULL_TREE);
9240 tree v4sf_ftype_v4sf_v4sf
9241 = build_function_type_list (V4SF_type_node,
9242 V4SF_type_node, V4SF_type_node, NULL_TREE);
9243 tree opaque_ftype_opaque_opaque_opaque
9244 = build_function_type_list (opaque_V4SI_type_node,
9245 opaque_V4SI_type_node, opaque_V4SI_type_node,
9246 opaque_V4SI_type_node, NULL_TREE);
9247 tree v4sf_ftype_v4sf_v4sf_v4si
9248 = build_function_type_list (V4SF_type_node,
9249 V4SF_type_node, V4SF_type_node,
9250 V4SI_type_node, NULL_TREE);
9251 tree v4sf_ftype_v4sf_v4sf_v4sf
9252 = build_function_type_list (V4SF_type_node,
9253 V4SF_type_node, V4SF_type_node,
9254 V4SF_type_node, NULL_TREE);
9255 tree v4si_ftype_v4si_v4si_v4si
9256 = build_function_type_list (V4SI_type_node,
9257 V4SI_type_node, V4SI_type_node,
9258 V4SI_type_node, NULL_TREE);
9259 tree v8hi_ftype_v8hi_v8hi
9260 = build_function_type_list (V8HI_type_node,
9261 V8HI_type_node, V8HI_type_node, NULL_TREE);
9262 tree v8hi_ftype_v8hi_v8hi_v8hi
9263 = build_function_type_list (V8HI_type_node,
9264 V8HI_type_node, V8HI_type_node,
9265 V8HI_type_node, NULL_TREE);
9266 tree v4si_ftype_v8hi_v8hi_v4si
9267 = build_function_type_list (V4SI_type_node,
9268 V8HI_type_node, V8HI_type_node,
9269 V4SI_type_node, NULL_TREE);
9270 tree v4si_ftype_v16qi_v16qi_v4si
9271 = build_function_type_list (V4SI_type_node,
9272 V16QI_type_node, V16QI_type_node,
9273 V4SI_type_node, NULL_TREE);
9274 tree v16qi_ftype_v16qi_v16qi
9275 = build_function_type_list (V16QI_type_node,
9276 V16QI_type_node, V16QI_type_node, NULL_TREE);
9277 tree v4si_ftype_v4sf_v4sf
9278 = build_function_type_list (V4SI_type_node,
9279 V4SF_type_node, V4SF_type_node, NULL_TREE);
9280 tree v8hi_ftype_v16qi_v16qi
9281 = build_function_type_list (V8HI_type_node,
9282 V16QI_type_node, V16QI_type_node, NULL_TREE);
9283 tree v4si_ftype_v8hi_v8hi
9284 = build_function_type_list (V4SI_type_node,
9285 V8HI_type_node, V8HI_type_node, NULL_TREE);
9286 tree v8hi_ftype_v4si_v4si
9287 = build_function_type_list (V8HI_type_node,
9288 V4SI_type_node, V4SI_type_node, NULL_TREE);
9289 tree v16qi_ftype_v8hi_v8hi
9290 = build_function_type_list (V16QI_type_node,
9291 V8HI_type_node, V8HI_type_node, NULL_TREE);
9292 tree v4si_ftype_v16qi_v4si
9293 = build_function_type_list (V4SI_type_node,
9294 V16QI_type_node, V4SI_type_node, NULL_TREE);
9295 tree v4si_ftype_v16qi_v16qi
9296 = build_function_type_list (V4SI_type_node,
9297 V16QI_type_node, V16QI_type_node, NULL_TREE);
9298 tree v4si_ftype_v8hi_v4si
9299 = build_function_type_list (V4SI_type_node,
9300 V8HI_type_node, V4SI_type_node, NULL_TREE);
9301 tree v4si_ftype_v8hi
9302 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9303 tree int_ftype_v4si_v4si
9304 = build_function_type_list (integer_type_node,
9305 V4SI_type_node, V4SI_type_node, NULL_TREE);
9306 tree int_ftype_v4sf_v4sf
9307 = build_function_type_list (integer_type_node,
9308 V4SF_type_node, V4SF_type_node, NULL_TREE);
9309 tree int_ftype_v16qi_v16qi
9310 = build_function_type_list (integer_type_node,
9311 V16QI_type_node, V16QI_type_node, NULL_TREE);
9312 tree int_ftype_v8hi_v8hi
9313 = build_function_type_list (integer_type_node,
9314 V8HI_type_node, V8HI_type_node, NULL_TREE);
9316 /* Add the simple ternary operators. */
9317 d = (struct builtin_description *) bdesc_3arg;
9318 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9320 enum machine_mode mode0, mode1, mode2, mode3;
9322 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9323 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9334 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9337 mode0 = insn_data[d->icode].operand[0].mode;
9338 mode1 = insn_data[d->icode].operand[1].mode;
9339 mode2 = insn_data[d->icode].operand[2].mode;
9340 mode3 = insn_data[d->icode].operand[3].mode;
9343 /* When all four are of the same mode. */
9344 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9349 type = opaque_ftype_opaque_opaque_opaque;
9352 type = v4si_ftype_v4si_v4si_v4si;
9355 type = v4sf_ftype_v4sf_v4sf_v4sf;
9358 type = v8hi_ftype_v8hi_v8hi_v8hi;
9361 type = v16qi_ftype_v16qi_v16qi_v16qi;
9367 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9372 type = v4si_ftype_v4si_v4si_v16qi;
9375 type = v4sf_ftype_v4sf_v4sf_v16qi;
9378 type = v8hi_ftype_v8hi_v8hi_v16qi;
9381 type = v16qi_ftype_v16qi_v16qi_v16qi;
9387 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9388 && mode3 == V4SImode)
9389 type = v4si_ftype_v16qi_v16qi_v4si;
9390 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9391 && mode3 == V4SImode)
9392 type = v4si_ftype_v8hi_v8hi_v4si;
9393 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9394 && mode3 == V4SImode)
9395 type = v4sf_ftype_v4sf_v4sf_v4si;
9397 /* vchar, vchar, vchar, 4-bit literal. */
9398 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9400 type = v16qi_ftype_v16qi_v16qi_int;
9402 /* vshort, vshort, vshort, 4-bit literal. */
9403 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9405 type = v8hi_ftype_v8hi_v8hi_int;
9407 /* vint, vint, vint, 4-bit literal. */
9408 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9410 type = v4si_ftype_v4si_v4si_int;
9412 /* vfloat, vfloat, vfloat, 4-bit literal. */
9413 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9415 type = v4sf_ftype_v4sf_v4sf_int;
9420 def_builtin (d->mask, d->name, type, d->code);
9423 /* Add the simple binary operators. */
9424 d = (struct builtin_description *) bdesc_2arg;
9425 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9427 enum machine_mode mode0, mode1, mode2;
9429 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9430 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9440 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9443 mode0 = insn_data[d->icode].operand[0].mode;
9444 mode1 = insn_data[d->icode].operand[1].mode;
9445 mode2 = insn_data[d->icode].operand[2].mode;
9448 /* When all three operands are of the same mode. */
9449 if (mode0 == mode1 && mode1 == mode2)
9454 type = opaque_ftype_opaque_opaque;
9457 type = v4sf_ftype_v4sf_v4sf;
9460 type = v4si_ftype_v4si_v4si;
9463 type = v16qi_ftype_v16qi_v16qi;
9466 type = v8hi_ftype_v8hi_v8hi;
9469 type = v2si_ftype_v2si_v2si;
9472 type = v2sf_ftype_v2sf_v2sf;
9475 type = int_ftype_int_int;
9482 /* A few other combos we really don't want to do manually. */
9484 /* vint, vfloat, vfloat. */
9485 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
9486 type = v4si_ftype_v4sf_v4sf;
9488 /* vshort, vchar, vchar. */
9489 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
9490 type = v8hi_ftype_v16qi_v16qi;
9492 /* vint, vshort, vshort. */
9493 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
9494 type = v4si_ftype_v8hi_v8hi;
9496 /* vshort, vint, vint. */
9497 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
9498 type = v8hi_ftype_v4si_v4si;
9500 /* vchar, vshort, vshort. */
9501 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
9502 type = v16qi_ftype_v8hi_v8hi;
9504 /* vint, vchar, vint. */
9505 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
9506 type = v4si_ftype_v16qi_v4si;
9508 /* vint, vchar, vchar. */
9509 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
9510 type = v4si_ftype_v16qi_v16qi;
9512 /* vint, vshort, vint. */
9513 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
9514 type = v4si_ftype_v8hi_v4si;
9516 /* vint, vint, 5-bit literal. */
9517 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
9518 type = v4si_ftype_v4si_int;
9520 /* vshort, vshort, 5-bit literal. */
9521 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
9522 type = v8hi_ftype_v8hi_int;
9524 /* vchar, vchar, 5-bit literal. */
9525 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
9526 type = v16qi_ftype_v16qi_int;
9528 /* vfloat, vint, 5-bit literal. */
9529 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
9530 type = v4sf_ftype_v4si_int;
9532 /* vint, vfloat, 5-bit literal. */
9533 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
9534 type = v4si_ftype_v4sf_int;
9536 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
9537 type = v2si_ftype_int_int;
9539 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
9540 type = v2si_ftype_v2si_char;
9542 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
9543 type = v2si_ftype_int_char;
9548 gcc_assert (mode0 == SImode);
9552 type = int_ftype_v4si_v4si;
9555 type = int_ftype_v4sf_v4sf;
9558 type = int_ftype_v16qi_v16qi;
9561 type = int_ftype_v8hi_v8hi;
9568 def_builtin (d->mask, d->name, type, d->code);
9571 /* Add the simple unary operators. */
9572 d = (struct builtin_description *) bdesc_1arg;
9573 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
9575 enum machine_mode mode0, mode1;
9577 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9578 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9587 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9590 mode0 = insn_data[d->icode].operand[0].mode;
9591 mode1 = insn_data[d->icode].operand[1].mode;
9594 if (mode0 == V4SImode && mode1 == QImode)
9595 type = v4si_ftype_int;
9596 else if (mode0 == V8HImode && mode1 == QImode)
9597 type = v8hi_ftype_int;
9598 else if (mode0 == V16QImode && mode1 == QImode)
9599 type = v16qi_ftype_int;
9600 else if (mode0 == VOIDmode && mode1 == VOIDmode)
9601 type = opaque_ftype_opaque;
9602 else if (mode0 == V4SFmode && mode1 == V4SFmode)
9603 type = v4sf_ftype_v4sf;
9604 else if (mode0 == V8HImode && mode1 == V16QImode)
9605 type = v8hi_ftype_v16qi;
9606 else if (mode0 == V4SImode && mode1 == V8HImode)
9607 type = v4si_ftype_v8hi;
9608 else if (mode0 == V2SImode && mode1 == V2SImode)
9609 type = v2si_ftype_v2si;
9610 else if (mode0 == V2SFmode && mode1 == V2SFmode)
9611 type = v2sf_ftype_v2sf;
9612 else if (mode0 == V2SFmode && mode1 == V2SImode)
9613 type = v2sf_ftype_v2si;
9614 else if (mode0 == V2SImode && mode1 == V2SFmode)
9615 type = v2si_ftype_v2sf;
9616 else if (mode0 == V2SImode && mode1 == QImode)
9617 type = v2si_ftype_char;
9621 def_builtin (d->mask, d->name, type, d->code);
9626 rs6000_init_libfuncs (void)
9628 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
9629 && !TARGET_POWER2 && !TARGET_POWERPC)
9631 /* AIX library routines for float->int conversion. */
9632 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9633 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9634 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9635 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9638 if (!TARGET_IEEEQUAD)
9639 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9640 if (!TARGET_XL_COMPAT)
9642 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9643 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9644 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9645 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9647 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
9649 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
9650 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
9651 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
9652 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
9653 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
9654 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
9655 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
9657 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
9658 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
9659 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
9660 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
9661 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
9662 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
9663 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
9664 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
9667 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
9668 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
9672 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9673 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9674 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9675 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9679 /* 32-bit SVR4 quad floating point routines. */
9681 set_optab_libfunc (add_optab, TFmode, "_q_add");
9682 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9683 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9684 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9685 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9686 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9687 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9689 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9690 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9691 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9692 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9693 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9694 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9696 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9697 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9698 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9699 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9700 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9701 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9702 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9703 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
9708 /* Expand a block clear operation, and return 1 if successful. Return 0
9709 if we should let the compiler generate normal code.
9711 operands[0] is the destination
9712 operands[1] is the length
9713 operands[3] is the alignment */
9716 expand_block_clear (rtx operands[])
9718 rtx orig_dest = operands[0];
9719 rtx bytes_rtx = operands[1];
9720 rtx align_rtx = operands[3];
9721 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9722 HOST_WIDE_INT align;
9723 HOST_WIDE_INT bytes;
9728 /* If this is not a fixed size move, just call memcpy */
9732 /* This must be a fixed size alignment */
9733 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9734 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9736 /* Anything to clear? */
9737 bytes = INTVAL (bytes_rtx);
9741 /* Use the builtin memset after a point, to avoid huge code bloat.
9742 When optimize_size, avoid any significant code bloat; calling
9743 memset is about 4 instructions, so allow for one instruction to
9744 load zero and three to do clearing. */
9745 if (TARGET_ALTIVEC && align >= 128)
9747 else if (TARGET_POWERPC64 && align >= 32)
9752 if (optimize_size && bytes > 3 * clear_step)
9754 if (! optimize_size && bytes > 8 * clear_step)
9757 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9759 enum machine_mode mode = BLKmode;
9762 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9767 else if (bytes >= 8 && TARGET_POWERPC64
9768 /* 64-bit loads and stores require word-aligned
9770 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9775 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9776 { /* move 4 bytes */
9780 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9781 { /* move 2 bytes */
9785 else /* move 1 byte at a time */
9791 dest = adjust_address (orig_dest, mode, offset);
9793 emit_move_insn (dest, CONST0_RTX (mode));
9800 /* Expand a block move operation, and return 1 if successful. Return 0
9801 if we should let the compiler generate normal code.
9803 operands[0] is the destination
9804 operands[1] is the source
9805 operands[2] is the length
9806 operands[3] is the alignment */
9808 #define MAX_MOVE_REG 4
9811 expand_block_move (rtx operands[])
9813 rtx orig_dest = operands[0];
9814 rtx orig_src = operands[1];
9815 rtx bytes_rtx = operands[2];
9816 rtx align_rtx = operands[3];
9817 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9822 rtx stores[MAX_MOVE_REG];
9825 /* If this is not a fixed size move, just call memcpy */
9829 /* This must be a fixed size alignment */
9830 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9831 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9833 /* Anything to move? */
9834 bytes = INTVAL (bytes_rtx);
9838 /* store_one_arg depends on expand_block_move to handle at least the size of
9839 reg_parm_stack_space. */
9840 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9843 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9846 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9847 rtx (*mov) (rtx, rtx);
9849 enum machine_mode mode = BLKmode;
9852 /* Altivec first, since it will be faster than a string move
9853 when it applies, and usually not significantly larger. */
9854 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9858 gen_func.mov = gen_movv4si;
9860 else if (TARGET_STRING
9861 && bytes > 24 /* move up to 32 bytes at a time */
9869 && ! fixed_regs[12])
9871 move_bytes = (bytes > 32) ? 32 : bytes;
9872 gen_func.movmemsi = gen_movmemsi_8reg;
9874 else if (TARGET_STRING
9875 && bytes > 16 /* move up to 24 bytes at a time */
9881 && ! fixed_regs[10])
9883 move_bytes = (bytes > 24) ? 24 : bytes;
9884 gen_func.movmemsi = gen_movmemsi_6reg;
9886 else if (TARGET_STRING
9887 && bytes > 8 /* move up to 16 bytes at a time */
9893 move_bytes = (bytes > 16) ? 16 : bytes;
9894 gen_func.movmemsi = gen_movmemsi_4reg;
9896 else if (bytes >= 8 && TARGET_POWERPC64
9897 /* 64-bit loads and stores require word-aligned
9899 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9903 gen_func.mov = gen_movdi;
9905 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9906 { /* move up to 8 bytes at a time */
9907 move_bytes = (bytes > 8) ? 8 : bytes;
9908 gen_func.movmemsi = gen_movmemsi_2reg;
9910 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9911 { /* move 4 bytes */
9914 gen_func.mov = gen_movsi;
9916 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
9917 { /* move 2 bytes */
9920 gen_func.mov = gen_movhi;
9922 else if (TARGET_STRING && bytes > 1)
9923 { /* move up to 4 bytes at a time */
9924 move_bytes = (bytes > 4) ? 4 : bytes;
9925 gen_func.movmemsi = gen_movmemsi_1reg;
9927 else /* move 1 byte at a time */
9931 gen_func.mov = gen_movqi;
9934 src = adjust_address (orig_src, mode, offset);
9935 dest = adjust_address (orig_dest, mode, offset);
9937 if (mode != BLKmode)
9939 rtx tmp_reg = gen_reg_rtx (mode);
9941 emit_insn ((*gen_func.mov) (tmp_reg, src));
9942 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9945 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9948 for (i = 0; i < num_reg; i++)
9949 emit_insn (stores[i]);
9953 if (mode == BLKmode)
9955 /* Move the address into scratch registers. The movmemsi
9956 patterns require zero offset. */
9957 if (!REG_P (XEXP (src, 0)))
9959 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9960 src = replace_equiv_address (src, src_reg);
9962 set_mem_size (src, GEN_INT (move_bytes));
9964 if (!REG_P (XEXP (dest, 0)))
9966 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9967 dest = replace_equiv_address (dest, dest_reg);
9969 set_mem_size (dest, GEN_INT (move_bytes));
9971 emit_insn ((*gen_func.movmemsi) (dest, src,
9972 GEN_INT (move_bytes & 31),
9981 /* Return a string to perform a load_multiple operation.
9982 operands[0] is the vector.
9983 operands[1] is the source address.
9984 operands[2] is the first destination register. */
9987 rs6000_output_load_multiple (rtx operands[3])
9989 /* We have to handle the case where the pseudo used to contain the address
9990 is assigned to one of the output registers. */
9992 int words = XVECLEN (operands[0], 0);
9995 if (XVECLEN (operands[0], 0) == 1)
9996 return "{l|lwz} %2,0(%1)";
9998 for (i = 0; i < words; i++)
9999 if (refers_to_regno_p (REGNO (operands[2]) + i,
10000 REGNO (operands[2]) + i + 1, operands[1], 0))
10004 xop[0] = GEN_INT (4 * (words-1));
10005 xop[1] = operands[1];
10006 xop[2] = operands[2];
10007 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10012 xop[0] = GEN_INT (4 * (words-1));
10013 xop[1] = operands[1];
10014 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10015 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10020 for (j = 0; j < words; j++)
10023 xop[0] = GEN_INT (j * 4);
10024 xop[1] = operands[1];
10025 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10026 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10028 xop[0] = GEN_INT (i * 4);
10029 xop[1] = operands[1];
10030 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10035 return "{lsi|lswi} %2,%1,%N0";
10039 /* A validation routine: say whether CODE, a condition code, and MODE
10040 match. The other alternatives either don't make sense or should
10041 never be generated. */
10044 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10046 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10047 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10048 && GET_MODE_CLASS (mode) == MODE_CC);
10050 /* These don't make sense. */
10051 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10052 || mode != CCUNSmode);
10054 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10055 || mode == CCUNSmode);
10057 gcc_assert (mode == CCFPmode
10058 || (code != ORDERED && code != UNORDERED
10059 && code != UNEQ && code != LTGT
10060 && code != UNGT && code != UNLT
10061 && code != UNGE && code != UNLE));
10063 /* These should never be generated except for
10064 flag_finite_math_only. */
10065 gcc_assert (mode != CCFPmode
10066 || flag_finite_math_only
10067 || (code != LE && code != GE
10068 && code != UNEQ && code != LTGT
10069 && code != UNGT && code != UNLT));
10071 /* These are invalid; the information is not there. */
10072 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10076 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10077 mask required to convert the result of a rotate insn into a shift
10078 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10081 includes_lshift_p (rtx shiftop, rtx andop)
10083 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10085 shift_mask <<= INTVAL (shiftop);
10087 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10090 /* Similar, but for right shift. */
10093 includes_rshift_p (rtx shiftop, rtx andop)
10095 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10097 shift_mask >>= INTVAL (shiftop);
10099 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10102 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10103 to perform a left shift. It must have exactly SHIFTOP least
10104 significant 0's, then one or more 1's, then zero or more 0's. */
10107 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10109 if (GET_CODE (andop) == CONST_INT)
10111 HOST_WIDE_INT c, lsb, shift_mask;
10113 c = INTVAL (andop);
10114 if (c == 0 || c == ~0)
10118 shift_mask <<= INTVAL (shiftop);
10120 /* Find the least significant one bit. */
10123 /* It must coincide with the LSB of the shift mask. */
10124 if (-lsb != shift_mask)
10127 /* Invert to look for the next transition (if any). */
10130 /* Remove the low group of ones (originally low group of zeros). */
10133 /* Again find the lsb, and check we have all 1's above. */
10137 else if (GET_CODE (andop) == CONST_DOUBLE
10138 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10140 HOST_WIDE_INT low, high, lsb;
10141 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10143 low = CONST_DOUBLE_LOW (andop);
10144 if (HOST_BITS_PER_WIDE_INT < 64)
10145 high = CONST_DOUBLE_HIGH (andop);
10147 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10148 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10151 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10153 shift_mask_high = ~0;
10154 if (INTVAL (shiftop) > 32)
10155 shift_mask_high <<= INTVAL (shiftop) - 32;
10157 lsb = high & -high;
10159 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10165 lsb = high & -high;
10166 return high == -lsb;
10169 shift_mask_low = ~0;
10170 shift_mask_low <<= INTVAL (shiftop);
10174 if (-lsb != shift_mask_low)
10177 if (HOST_BITS_PER_WIDE_INT < 64)
10182 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10184 lsb = high & -high;
10185 return high == -lsb;
10189 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10195 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10196 to perform a left shift. It must have SHIFTOP or more least
10197 significant 0's, with the remainder of the word 1's. */
10200 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10202 if (GET_CODE (andop) == CONST_INT)
10204 HOST_WIDE_INT c, lsb, shift_mask;
10207 shift_mask <<= INTVAL (shiftop);
10208 c = INTVAL (andop);
10210 /* Find the least significant one bit. */
10213 /* It must be covered by the shift mask.
10214 This test also rejects c == 0. */
10215 if ((lsb & shift_mask) == 0)
10218 /* Check we have all 1's above the transition, and reject all 1's. */
10219 return c == -lsb && lsb != 1;
10221 else if (GET_CODE (andop) == CONST_DOUBLE
10222 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10224 HOST_WIDE_INT low, lsb, shift_mask_low;
10226 low = CONST_DOUBLE_LOW (andop);
10228 if (HOST_BITS_PER_WIDE_INT < 64)
10230 HOST_WIDE_INT high, shift_mask_high;
10232 high = CONST_DOUBLE_HIGH (andop);
10236 shift_mask_high = ~0;
10237 if (INTVAL (shiftop) > 32)
10238 shift_mask_high <<= INTVAL (shiftop) - 32;
10240 lsb = high & -high;
10242 if ((lsb & shift_mask_high) == 0)
10245 return high == -lsb;
10251 shift_mask_low = ~0;
10252 shift_mask_low <<= INTVAL (shiftop);
10256 if ((lsb & shift_mask_low) == 0)
10259 return low == -lsb && lsb != 1;
10265 /* Return 1 if operands will generate a valid arguments to rlwimi
10266 instruction for insert with right shift in 64-bit mode. The mask may
10267 not start on the first bit or stop on the last bit because wrap-around
10268 effects of instruction do not correspond to semantics of RTL insn. */
10271 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10273 if (INTVAL (startop) > 32
10274 && INTVAL (startop) < 64
10275 && INTVAL (sizeop) > 1
10276 && INTVAL (sizeop) + INTVAL (startop) < 64
10277 && INTVAL (shiftop) > 0
10278 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10279 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10285 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10286 for lfq and stfq insns iff the registers are hard registers. */
10289 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10291 /* We might have been passed a SUBREG. */
10292 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10295 /* We might have been passed non floating point registers. */
10296 if (!FP_REGNO_P (REGNO (reg1))
10297 || !FP_REGNO_P (REGNO (reg2)))
10300 return (REGNO (reg1) == REGNO (reg2) - 1);
10303 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10304 addr1 and addr2 must be in consecutive memory locations
10305 (addr2 == addr1 + 8). */
10308 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10311 unsigned int reg1, reg2;
10312 int offset1, offset2;
10314 /* The mems cannot be volatile. */
10315 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10318 addr1 = XEXP (mem1, 0);
10319 addr2 = XEXP (mem2, 0);
10321 /* Extract an offset (if used) from the first addr. */
10322 if (GET_CODE (addr1) == PLUS)
10324 /* If not a REG, return zero. */
10325 if (GET_CODE (XEXP (addr1, 0)) != REG)
10329 reg1 = REGNO (XEXP (addr1, 0));
10330 /* The offset must be constant! */
10331 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10333 offset1 = INTVAL (XEXP (addr1, 1));
10336 else if (GET_CODE (addr1) != REG)
10340 reg1 = REGNO (addr1);
10341 /* This was a simple (mem (reg)) expression. Offset is 0. */
10345 /* And now for the second addr. */
10346 if (GET_CODE (addr2) == PLUS)
10348 /* If not a REG, return zero. */
10349 if (GET_CODE (XEXP (addr2, 0)) != REG)
10353 reg2 = REGNO (XEXP (addr2, 0));
10354 /* The offset must be constant. */
10355 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10357 offset2 = INTVAL (XEXP (addr2, 1));
10360 else if (GET_CODE (addr2) != REG)
10364 reg2 = REGNO (addr2);
10365 /* This was a simple (mem (reg)) expression. Offset is 0. */
10369 /* Both of these must have the same base register. */
10373 /* The offset for the second addr must be 8 more than the first addr. */
10374 if (offset2 != offset1 + 8)
10377 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10382 /* Return the register class of a scratch register needed to copy IN into
10383 or out of a register in CLASS in MODE. If it can be done directly,
10384 NO_REGS is returned. */
10387 rs6000_secondary_reload_class (enum reg_class class,
10388 enum machine_mode mode ATTRIBUTE_UNUSED,
10393 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10395 && MACHOPIC_INDIRECT
10399 /* We cannot copy a symbolic operand directly into anything
10400 other than BASE_REGS for TARGET_ELF. So indicate that a
10401 register from BASE_REGS is needed as an intermediate
10404 On Darwin, pic addresses require a load from memory, which
10405 needs a base register. */
10406 if (class != BASE_REGS
10407 && (GET_CODE (in) == SYMBOL_REF
10408 || GET_CODE (in) == HIGH
10409 || GET_CODE (in) == LABEL_REF
10410 || GET_CODE (in) == CONST))
10414 if (GET_CODE (in) == REG)
10416 regno = REGNO (in);
10417 if (regno >= FIRST_PSEUDO_REGISTER)
10419 regno = true_regnum (in);
10420 if (regno >= FIRST_PSEUDO_REGISTER)
10424 else if (GET_CODE (in) == SUBREG)
10426 regno = true_regnum (in);
10427 if (regno >= FIRST_PSEUDO_REGISTER)
10433 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10435 if (class == GENERAL_REGS || class == BASE_REGS
10436 || (regno >= 0 && INT_REGNO_P (regno)))
10439 /* Constants, memory, and FP registers can go into FP registers. */
10440 if ((regno == -1 || FP_REGNO_P (regno))
10441 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10444 /* Memory, and AltiVec registers can go into AltiVec registers. */
10445 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10446 && class == ALTIVEC_REGS)
10449 /* We can copy among the CR registers. */
10450 if ((class == CR_REGS || class == CR0_REGS)
10451 && regno >= 0 && CR_REGNO_P (regno))
10454 /* Otherwise, we need GENERAL_REGS. */
10455 return GENERAL_REGS;
10458 /* Given a comparison operation, return the bit number in CCR to test. We
10459 know this is a valid comparison.
10461 SCC_P is 1 if this is for an scc. That means that %D will have been
10462 used instead of %C, so the bits will be in different places.
10464 Return -1 if OP isn't a valid comparison for some reason. */
10467 ccr_bit (rtx op, int scc_p)
10469 enum rtx_code code = GET_CODE (op);
10470 enum machine_mode cc_mode;
10475 if (!COMPARISON_P (op))
10478 reg = XEXP (op, 0);
10480 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
10482 cc_mode = GET_MODE (reg);
10483 cc_regnum = REGNO (reg);
10484 base_bit = 4 * (cc_regnum - CR0_REGNO);
10486 validate_condition_mode (code, cc_mode);
10488 /* When generating a sCOND operation, only positive conditions are
10491 || code == EQ || code == GT || code == LT || code == UNORDERED
10492 || code == GTU || code == LTU);
10497 return scc_p ? base_bit + 3 : base_bit + 2;
10499 return base_bit + 2;
10500 case GT: case GTU: case UNLE:
10501 return base_bit + 1;
10502 case LT: case LTU: case UNGE:
10504 case ORDERED: case UNORDERED:
10505 return base_bit + 3;
10508 /* If scc, we will have done a cror to put the bit in the
10509 unordered position. So test that bit. For integer, this is ! LT
10510 unless this is an scc insn. */
10511 return scc_p ? base_bit + 3 : base_bit;
10514 return scc_p ? base_bit + 3 : base_bit + 1;
10517 gcc_unreachable ();
10521 /* Return the GOT register. */
10524 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
10526 /* The second flow pass currently (June 1999) can't update
10527 regs_ever_live without disturbing other parts of the compiler, so
10528 update it here to make the prolog/epilogue code happy. */
10529 if (!can_create_pseudo_p ()
10530 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
10531 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
10533 current_function_uses_pic_offset_table = 1;
10535 return pic_offset_table_rtx;
10538 /* Function to init struct machine_function.
10539 This will be called, via a pointer variable,
10540 from push_function_context. */
10542 static struct machine_function *
10543 rs6000_init_machine_status (void)
10545 return ggc_alloc_cleared (sizeof (machine_function));
10548 /* These macros test for integers and extract the low-order bits. */
10550 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
10551 && GET_MODE (X) == VOIDmode)
10553 #define INT_LOWPART(X) \
10554 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
10557 extract_MB (rtx op)
10560 unsigned long val = INT_LOWPART (op);
10562 /* If the high bit is zero, the value is the first 1 bit we find
10564 if ((val & 0x80000000) == 0)
10566 gcc_assert (val & 0xffffffff);
10569 while (((val <<= 1) & 0x80000000) == 0)
10574 /* If the high bit is set and the low bit is not, or the mask is all
10575 1's, the value is zero. */
10576 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
10579 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10582 while (((val >>= 1) & 1) != 0)
10589 extract_ME (rtx op)
10592 unsigned long val = INT_LOWPART (op);
10594 /* If the low bit is zero, the value is the first 1 bit we find from
10596 if ((val & 1) == 0)
10598 gcc_assert (val & 0xffffffff);
10601 while (((val >>= 1) & 1) == 0)
10607 /* If the low bit is set and the high bit is not, or the mask is all
10608 1's, the value is 31. */
10609 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
10612 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
10615 while (((val <<= 1) & 0x80000000) != 0)
10621 /* Locate some local-dynamic symbol still in use by this function
10622 so that we can print its name in some tls_ld pattern. */
10624 static const char *
10625 rs6000_get_some_local_dynamic_name (void)
10629 if (cfun->machine->some_ld_name)
10630 return cfun->machine->some_ld_name;
10632 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
10634 && for_each_rtx (&PATTERN (insn),
10635 rs6000_get_some_local_dynamic_name_1, 0))
10636 return cfun->machine->some_ld_name;
10638 gcc_unreachable ();
10641 /* Helper function for rs6000_get_some_local_dynamic_name. */
10644 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10648 if (GET_CODE (x) == SYMBOL_REF)
10650 const char *str = XSTR (x, 0);
10651 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10653 cfun->machine->some_ld_name = str;
10661 /* Write out a function code label. */
10664 rs6000_output_function_entry (FILE *file, const char *fname)
10666 if (fname[0] != '.')
10668 switch (DEFAULT_ABI)
10671 gcc_unreachable ();
10677 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10686 RS6000_OUTPUT_BASENAME (file, fname);
10688 assemble_name (file, fname);
10691 /* Print an operand. Recognize special options, documented below. */
10694 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10695 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10697 #define SMALL_DATA_RELOC "sda21"
10698 #define SMALL_DATA_REG 0
10702 print_operand (FILE *file, rtx x, int code)
10706 unsigned HOST_WIDE_INT uval;
10711 /* Write out an instruction after the call which may be replaced
10712 with glue code by the loader. This depends on the AIX version. */
10713 asm_fprintf (file, RS6000_CALL_GLUE);
10716 /* %a is output_address. */
10719 /* If X is a constant integer whose low-order 5 bits are zero,
10720 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10721 in the AIX assembler where "sri" with a zero shift count
10722 writes a trash instruction. */
10723 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10730 /* If constant, low-order 16 bits of constant, unsigned.
10731 Otherwise, write normally. */
10733 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10735 print_operand (file, x, 0);
10739 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10740 for 64-bit mask direction. */
10741 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10744 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10748 /* X is a CR register. Print the number of the GT bit of the CR. */
10749 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10750 output_operand_lossage ("invalid %%E value");
10752 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10756 /* Like 'J' but get to the GT bit only. */
10757 gcc_assert (GET_CODE (x) == REG);
10759 /* Bit 1 is GT bit. */
10760 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
10762 /* Add one for shift count in rlinm for scc. */
10763 fprintf (file, "%d", i + 1);
10767 /* X is a CR register. Print the number of the EQ bit of the CR */
10768 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10769 output_operand_lossage ("invalid %%E value");
10771 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10775 /* X is a CR register. Print the shift count needed to move it
10776 to the high-order four bits. */
10777 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10778 output_operand_lossage ("invalid %%f value");
10780 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10784 /* Similar, but print the count for the rotate in the opposite
10786 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10787 output_operand_lossage ("invalid %%F value");
10789 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10793 /* X is a constant integer. If it is negative, print "m",
10794 otherwise print "z". This is to make an aze or ame insn. */
10795 if (GET_CODE (x) != CONST_INT)
10796 output_operand_lossage ("invalid %%G value");
10797 else if (INTVAL (x) >= 0)
10804 /* If constant, output low-order five bits. Otherwise, write
10807 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10809 print_operand (file, x, 0);
10813 /* If constant, output low-order six bits. Otherwise, write
10816 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10818 print_operand (file, x, 0);
10822 /* Print `i' if this is a constant, else nothing. */
10828 /* Write the bit number in CCR for jump. */
10829 i = ccr_bit (x, 0);
10831 output_operand_lossage ("invalid %%j code");
10833 fprintf (file, "%d", i);
10837 /* Similar, but add one for shift count in rlinm for scc and pass
10838 scc flag to `ccr_bit'. */
10839 i = ccr_bit (x, 1);
10841 output_operand_lossage ("invalid %%J code");
10843 /* If we want bit 31, write a shift count of zero, not 32. */
10844 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10848 /* X must be a constant. Write the 1's complement of the
10851 output_operand_lossage ("invalid %%k value");
10853 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10857 /* X must be a symbolic constant on ELF. Write an
10858 expression suitable for an 'addi' that adds in the low 16
10859 bits of the MEM. */
10860 if (GET_CODE (x) != CONST)
10862 print_operand_address (file, x);
10863 fputs ("@l", file);
10867 if (GET_CODE (XEXP (x, 0)) != PLUS
10868 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10869 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10870 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10871 output_operand_lossage ("invalid %%K value");
10872 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10873 fputs ("@l", file);
10874 /* For GNU as, there must be a non-alphanumeric character
10875 between 'l' and the number. The '-' is added by
10876 print_operand() already. */
10877 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10879 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10883 /* %l is output_asm_label. */
10886 /* Write second word of DImode or DFmode reference. Works on register
10887 or non-indexed memory only. */
10888 if (GET_CODE (x) == REG)
10889 fputs (reg_names[REGNO (x) + 1], file);
10890 else if (GET_CODE (x) == MEM)
10892 /* Handle possible auto-increment. Since it is pre-increment and
10893 we have already done it, we can just use an offset of word. */
10894 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10895 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10896 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10898 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
10899 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10902 output_address (XEXP (adjust_address_nv (x, SImode,
10906 if (small_data_operand (x, GET_MODE (x)))
10907 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10908 reg_names[SMALL_DATA_REG]);
10913 /* MB value for a mask operand. */
10914 if (! mask_operand (x, SImode))
10915 output_operand_lossage ("invalid %%m value");
10917 fprintf (file, "%d", extract_MB (x));
10921 /* ME value for a mask operand. */
10922 if (! mask_operand (x, SImode))
10923 output_operand_lossage ("invalid %%M value");
10925 fprintf (file, "%d", extract_ME (x));
10928 /* %n outputs the negative of its operand. */
10931 /* Write the number of elements in the vector times 4. */
10932 if (GET_CODE (x) != PARALLEL)
10933 output_operand_lossage ("invalid %%N value");
10935 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10939 /* Similar, but subtract 1 first. */
10940 if (GET_CODE (x) != PARALLEL)
10941 output_operand_lossage ("invalid %%O value");
10943 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10947 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10949 || INT_LOWPART (x) < 0
10950 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10951 output_operand_lossage ("invalid %%p value");
10953 fprintf (file, "%d", i);
10957 /* The operand must be an indirect memory reference. The result
10958 is the register name. */
10959 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10960 || REGNO (XEXP (x, 0)) >= 32)
10961 output_operand_lossage ("invalid %%P value");
10963 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10967 /* This outputs the logical code corresponding to a boolean
10968 expression. The expression may have one or both operands
10969 negated (if one, only the first one). For condition register
10970 logical operations, it will also treat the negated
10971 CR codes as NOTs, but not handle NOTs of them. */
10973 const char *const *t = 0;
10975 enum rtx_code code = GET_CODE (x);
10976 static const char * const tbl[3][3] = {
10977 { "and", "andc", "nor" },
10978 { "or", "orc", "nand" },
10979 { "xor", "eqv", "xor" } };
10983 else if (code == IOR)
10985 else if (code == XOR)
10988 output_operand_lossage ("invalid %%q value");
10990 if (GET_CODE (XEXP (x, 0)) != NOT)
10994 if (GET_CODE (XEXP (x, 1)) == NOT)
11012 /* X is a CR register. Print the mask for `mtcrf'. */
11013 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11014 output_operand_lossage ("invalid %%R value");
11016 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11020 /* Low 5 bits of 32 - value */
11022 output_operand_lossage ("invalid %%s value");
11024 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11028 /* PowerPC64 mask position. All 0's is excluded.
11029 CONST_INT 32-bit mask is considered sign-extended so any
11030 transition must occur within the CONST_INT, not on the boundary. */
11031 if (! mask64_operand (x, DImode))
11032 output_operand_lossage ("invalid %%S value");
11034 uval = INT_LOWPART (x);
11036 if (uval & 1) /* Clear Left */
11038 #if HOST_BITS_PER_WIDE_INT > 64
11039 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11043 else /* Clear Right */
11046 #if HOST_BITS_PER_WIDE_INT > 64
11047 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11053 gcc_assert (i >= 0);
11054 fprintf (file, "%d", i);
11058 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11059 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11061 /* Bit 3 is OV bit. */
11062 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11064 /* If we want bit 31, write a shift count of zero, not 32. */
11065 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11069 /* Print the symbolic name of a branch target register. */
11070 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11071 && REGNO (x) != CTR_REGNO))
11072 output_operand_lossage ("invalid %%T value");
11073 else if (REGNO (x) == LR_REGNO)
11074 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11076 fputs ("ctr", file);
11080 /* High-order 16 bits of constant for use in unsigned operand. */
11082 output_operand_lossage ("invalid %%u value");
11084 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11085 (INT_LOWPART (x) >> 16) & 0xffff);
11089 /* High-order 16 bits of constant for use in signed operand. */
11091 output_operand_lossage ("invalid %%v value");
11093 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11094 (INT_LOWPART (x) >> 16) & 0xffff);
11098 /* Print `u' if this has an auto-increment or auto-decrement. */
11099 if (GET_CODE (x) == MEM
11100 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11101 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11102 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11107 /* Print the trap code for this operand. */
11108 switch (GET_CODE (x))
11111 fputs ("eq", file); /* 4 */
11114 fputs ("ne", file); /* 24 */
11117 fputs ("lt", file); /* 16 */
11120 fputs ("le", file); /* 20 */
11123 fputs ("gt", file); /* 8 */
11126 fputs ("ge", file); /* 12 */
11129 fputs ("llt", file); /* 2 */
11132 fputs ("lle", file); /* 6 */
11135 fputs ("lgt", file); /* 1 */
11138 fputs ("lge", file); /* 5 */
11141 gcc_unreachable ();
11146 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11149 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11150 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11152 print_operand (file, x, 0);
11156 /* MB value for a PowerPC64 rldic operand. */
11157 val = (GET_CODE (x) == CONST_INT
11158 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11163 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11164 if ((val <<= 1) < 0)
11167 #if HOST_BITS_PER_WIDE_INT == 32
11168 if (GET_CODE (x) == CONST_INT && i >= 0)
11169 i += 32; /* zero-extend high-part was all 0's */
11170 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11172 val = CONST_DOUBLE_LOW (x);
11178 for ( ; i < 64; i++)
11179 if ((val <<= 1) < 0)
11184 fprintf (file, "%d", i + 1);
11188 if (GET_CODE (x) == MEM
11189 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11190 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11191 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11196 /* Like 'L', for third word of TImode */
11197 if (GET_CODE (x) == REG)
11198 fputs (reg_names[REGNO (x) + 2], file);
11199 else if (GET_CODE (x) == MEM)
11201 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11202 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11203 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11204 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11205 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11207 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11208 if (small_data_operand (x, GET_MODE (x)))
11209 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11210 reg_names[SMALL_DATA_REG]);
11215 /* X is a SYMBOL_REF. Write out the name preceded by a
11216 period and without any trailing data in brackets. Used for function
11217 names. If we are configured for System V (or the embedded ABI) on
11218 the PowerPC, do not emit the period, since those systems do not use
11219 TOCs and the like. */
11220 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11222 /* Mark the decl as referenced so that cgraph will output the
11224 if (SYMBOL_REF_DECL (x))
11225 mark_decl_referenced (SYMBOL_REF_DECL (x));
11227 /* For macho, check to see if we need a stub. */
11230 const char *name = XSTR (x, 0);
11232 if (MACHOPIC_INDIRECT
11233 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11234 name = machopic_indirection_name (x, /*stub_p=*/true);
11236 assemble_name (file, name);
11238 else if (!DOT_SYMBOLS)
11239 assemble_name (file, XSTR (x, 0));
11241 rs6000_output_function_entry (file, XSTR (x, 0));
11245 /* Like 'L', for last word of TImode. */
11246 if (GET_CODE (x) == REG)
11247 fputs (reg_names[REGNO (x) + 3], file);
11248 else if (GET_CODE (x) == MEM)
11250 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11251 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11252 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11253 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11254 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11256 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11257 if (small_data_operand (x, GET_MODE (x)))
11258 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11259 reg_names[SMALL_DATA_REG]);
11263 /* Print AltiVec or SPE memory operand. */
11268 gcc_assert (GET_CODE (x) == MEM);
11272 /* Ugly hack because %y is overloaded. */
11273 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11274 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11275 || GET_MODE (x) == TFmode
11276 || GET_MODE (x) == TImode))
11278 /* Handle [reg]. */
11279 if (GET_CODE (tmp) == REG)
11281 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11284 /* Handle [reg+UIMM]. */
11285 else if (GET_CODE (tmp) == PLUS &&
11286 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11290 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11292 x = INTVAL (XEXP (tmp, 1));
11293 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11297 /* Fall through. Must be [reg+reg]. */
11300 && GET_CODE (tmp) == AND
11301 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11302 && INTVAL (XEXP (tmp, 1)) == -16)
11303 tmp = XEXP (tmp, 0);
11304 if (GET_CODE (tmp) == REG)
11305 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11308 gcc_assert (GET_CODE (tmp) == PLUS
11309 && REG_P (XEXP (tmp, 0))
11310 && REG_P (XEXP (tmp, 1)));
11312 if (REGNO (XEXP (tmp, 0)) == 0)
11313 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11314 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11316 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11317 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11323 if (GET_CODE (x) == REG)
11324 fprintf (file, "%s", reg_names[REGNO (x)]);
11325 else if (GET_CODE (x) == MEM)
11327 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11328 know the width from the mode. */
11329 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11330 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11331 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11332 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11333 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11334 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11335 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11336 output_address (XEXP (XEXP (x, 0), 1));
11338 output_address (XEXP (x, 0));
11341 output_addr_const (file, x);
11345 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11349 output_operand_lossage ("invalid %%xn code");
11353 /* Print the address of an operand. */
11356 print_operand_address (FILE *file, rtx x)
11358 if (GET_CODE (x) == REG)
11359 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11360 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11361 || GET_CODE (x) == LABEL_REF)
11363 output_addr_const (file, x);
11364 if (small_data_operand (x, GET_MODE (x)))
11365 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11366 reg_names[SMALL_DATA_REG]);
11368 gcc_assert (!TARGET_TOC);
11370 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11372 gcc_assert (REG_P (XEXP (x, 0)));
11373 if (REGNO (XEXP (x, 0)) == 0)
11374 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11375 reg_names[ REGNO (XEXP (x, 0)) ]);
11377 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11378 reg_names[ REGNO (XEXP (x, 1)) ]);
11380 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11381 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11382 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11384 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11385 && CONSTANT_P (XEXP (x, 1)))
11387 output_addr_const (file, XEXP (x, 1));
11388 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11392 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11393 && CONSTANT_P (XEXP (x, 1)))
11395 fprintf (file, "lo16(");
11396 output_addr_const (file, XEXP (x, 1));
11397 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11400 else if (legitimate_constant_pool_address_p (x))
11402 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11404 rtx contains_minus = XEXP (x, 1);
11408 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11409 turn it into (sym) for output_addr_const. */
11410 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11411 contains_minus = XEXP (contains_minus, 0);
11413 minus = XEXP (contains_minus, 0);
11414 symref = XEXP (minus, 0);
11415 XEXP (contains_minus, 0) = symref;
11420 name = XSTR (symref, 0);
11421 newname = alloca (strlen (name) + sizeof ("@toc"));
11422 strcpy (newname, name);
11423 strcat (newname, "@toc");
11424 XSTR (symref, 0) = newname;
11426 output_addr_const (file, XEXP (x, 1));
11428 XSTR (symref, 0) = name;
11429 XEXP (contains_minus, 0) = minus;
11432 output_addr_const (file, XEXP (x, 1));
11434 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11437 gcc_unreachable ();
11440 /* Target hook for assembling integer objects. The PowerPC version has
11441 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11442 is defined. It also needs to handle DI-mode objects on 64-bit
11446 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11448 #ifdef RELOCATABLE_NEEDS_FIXUP
11449 /* Special handling for SI values. */
11450 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
11452 static int recurse = 0;
11454 /* For -mrelocatable, we mark all addresses that need to be fixed up
11455 in the .fixup section. */
11456 if (TARGET_RELOCATABLE
11457 && in_section != toc_section
11458 && in_section != text_section
11459 && !unlikely_text_section_p (in_section)
11461 && GET_CODE (x) != CONST_INT
11462 && GET_CODE (x) != CONST_DOUBLE
11468 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
11470 ASM_OUTPUT_LABEL (asm_out_file, buf);
11471 fprintf (asm_out_file, "\t.long\t(");
11472 output_addr_const (asm_out_file, x);
11473 fprintf (asm_out_file, ")@fixup\n");
11474 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
11475 ASM_OUTPUT_ALIGN (asm_out_file, 2);
11476 fprintf (asm_out_file, "\t.long\t");
11477 assemble_name (asm_out_file, buf);
11478 fprintf (asm_out_file, "\n\t.previous\n");
11482 /* Remove initial .'s to turn a -mcall-aixdesc function
11483 address into the address of the descriptor, not the function
11485 else if (GET_CODE (x) == SYMBOL_REF
11486 && XSTR (x, 0)[0] == '.'
11487 && DEFAULT_ABI == ABI_AIX)
11489 const char *name = XSTR (x, 0);
11490 while (*name == '.')
11493 fprintf (asm_out_file, "\t.long\t%s\n", name);
11497 #endif /* RELOCATABLE_NEEDS_FIXUP */
11498 return default_assemble_integer (x, size, aligned_p);
11501 #ifdef HAVE_GAS_HIDDEN
11502 /* Emit an assembler directive to set symbol visibility for DECL to
11503 VISIBILITY_TYPE. */
11506 rs6000_assemble_visibility (tree decl, int vis)
11508 /* Functions need to have their entry point symbol visibility set as
11509 well as their descriptor symbol visibility. */
11510 if (DEFAULT_ABI == ABI_AIX
11512 && TREE_CODE (decl) == FUNCTION_DECL)
11514 static const char * const visibility_types[] = {
11515 NULL, "internal", "hidden", "protected"
11518 const char *name, *type;
11520 name = ((* targetm.strip_name_encoding)
11521 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
11522 type = visibility_types[vis];
11524 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
11525 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
11528 default_assemble_visibility (decl, vis);
11533 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
11535 /* Reversal of FP compares takes care -- an ordered compare
11536 becomes an unordered compare and vice versa. */
11537 if (mode == CCFPmode
11538 && (!flag_finite_math_only
11539 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
11540 || code == UNEQ || code == LTGT))
11541 return reverse_condition_maybe_unordered (code);
11543 return reverse_condition (code);
11546 /* Generate a compare for CODE. Return a brand-new rtx that
11547 represents the result of the compare. */
11550 rs6000_generate_compare (enum rtx_code code)
11552 enum machine_mode comp_mode;
11553 rtx compare_result;
11555 if (rs6000_compare_fp_p)
11556 comp_mode = CCFPmode;
11557 else if (code == GTU || code == LTU
11558 || code == GEU || code == LEU)
11559 comp_mode = CCUNSmode;
11560 else if ((code == EQ || code == NE)
11561 && GET_CODE (rs6000_compare_op0) == SUBREG
11562 && GET_CODE (rs6000_compare_op1) == SUBREG
11563 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
11564 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
11565 /* These are unsigned values, perhaps there will be a later
11566 ordering compare that can be shared with this one.
11567 Unfortunately we cannot detect the signedness of the operands
11568 for non-subregs. */
11569 comp_mode = CCUNSmode;
11571 comp_mode = CCmode;
11573 /* First, the compare. */
11574 compare_result = gen_reg_rtx (comp_mode);
11576 /* E500 FP compare instructions on the GPRs. Yuck! */
11577 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
11578 && rs6000_compare_fp_p)
11580 rtx cmp, or_result, compare_result2;
11581 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
11583 if (op_mode == VOIDmode)
11584 op_mode = GET_MODE (rs6000_compare_op1);
11586 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
11587 This explains the following mess. */
11591 case EQ: case UNEQ: case NE: case LTGT:
11595 cmp = flag_unsafe_math_optimizations
11596 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
11597 rs6000_compare_op1)
11598 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
11599 rs6000_compare_op1);
11603 cmp = flag_unsafe_math_optimizations
11604 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
11605 rs6000_compare_op1)
11606 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
11607 rs6000_compare_op1);
11611 cmp = flag_unsafe_math_optimizations
11612 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
11613 rs6000_compare_op1)
11614 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
11615 rs6000_compare_op1);
11619 gcc_unreachable ();
11623 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
11627 cmp = flag_unsafe_math_optimizations
11628 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
11629 rs6000_compare_op1)
11630 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
11631 rs6000_compare_op1);
11635 cmp = flag_unsafe_math_optimizations
11636 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
11637 rs6000_compare_op1)
11638 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
11639 rs6000_compare_op1);
11643 cmp = flag_unsafe_math_optimizations
11644 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
11645 rs6000_compare_op1)
11646 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
11647 rs6000_compare_op1);
11651 gcc_unreachable ();
11655 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
11659 cmp = flag_unsafe_math_optimizations
11660 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
11661 rs6000_compare_op1)
11662 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
11663 rs6000_compare_op1);
11667 cmp = flag_unsafe_math_optimizations
11668 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
11669 rs6000_compare_op1)
11670 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
11671 rs6000_compare_op1);
11675 cmp = flag_unsafe_math_optimizations
11676 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
11677 rs6000_compare_op1)
11678 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
11679 rs6000_compare_op1);
11683 gcc_unreachable ();
11687 gcc_unreachable ();
11690 /* Synthesize LE and GE from LT/GT || EQ. */
11691 if (code == LE || code == GE || code == LEU || code == GEU)
11697 case LE: code = LT; break;
11698 case GE: code = GT; break;
11699 case LEU: code = LT; break;
11700 case GEU: code = GT; break;
11701 default: gcc_unreachable ();
11704 compare_result2 = gen_reg_rtx (CCFPmode);
11710 cmp = flag_unsafe_math_optimizations
11711 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11712 rs6000_compare_op1)
11713 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11714 rs6000_compare_op1);
11718 cmp = flag_unsafe_math_optimizations
11719 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11720 rs6000_compare_op1)
11721 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11722 rs6000_compare_op1);
11726 cmp = flag_unsafe_math_optimizations
11727 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
11728 rs6000_compare_op1)
11729 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
11730 rs6000_compare_op1);
11734 gcc_unreachable ();
11738 /* OR them together. */
11739 or_result = gen_reg_rtx (CCFPmode);
11740 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11742 compare_result = or_result;
11747 if (code == NE || code == LTGT)
11757 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11758 CLOBBERs to match cmptf_internal2 pattern. */
11759 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11760 && GET_MODE (rs6000_compare_op0) == TFmode
11761 && !TARGET_IEEEQUAD
11762 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11763 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11765 gen_rtx_SET (VOIDmode,
11767 gen_rtx_COMPARE (comp_mode,
11768 rs6000_compare_op0,
11769 rs6000_compare_op1)),
11770 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11771 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11772 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11773 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11774 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11775 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11776 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11777 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11778 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11779 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11781 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11782 comp_mode = CCEQmode;
11783 compare_result = gen_reg_rtx (CCEQmode);
11785 emit_insn (gen_stack_protect_testdi (compare_result,
11786 rs6000_compare_op0, op1));
11788 emit_insn (gen_stack_protect_testsi (compare_result,
11789 rs6000_compare_op0, op1));
11792 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11793 gen_rtx_COMPARE (comp_mode,
11794 rs6000_compare_op0,
11795 rs6000_compare_op1)));
11798 /* Some kinds of FP comparisons need an OR operation;
11799 under flag_finite_math_only we don't bother. */
11800 if (rs6000_compare_fp_p
11801 && !flag_finite_math_only
11802 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
11803 && (code == LE || code == GE
11804 || code == UNEQ || code == LTGT
11805 || code == UNGT || code == UNLT))
11807 enum rtx_code or1, or2;
11808 rtx or1_rtx, or2_rtx, compare2_rtx;
11809 rtx or_result = gen_reg_rtx (CCEQmode);
11813 case LE: or1 = LT; or2 = EQ; break;
11814 case GE: or1 = GT; or2 = EQ; break;
11815 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11816 case LTGT: or1 = LT; or2 = GT; break;
11817 case UNGT: or1 = UNORDERED; or2 = GT; break;
11818 case UNLT: or1 = UNORDERED; or2 = LT; break;
11819 default: gcc_unreachable ();
11821 validate_condition_mode (or1, comp_mode);
11822 validate_condition_mode (or2, comp_mode);
11823 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11824 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11825 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11826 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11828 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11830 compare_result = or_result;
11834 validate_condition_mode (code, GET_MODE (compare_result));
11836 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11840 /* Emit the RTL for an sCOND pattern. */
11843 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11846 enum machine_mode op_mode;
11847 enum rtx_code cond_code;
11849 condition_rtx = rs6000_generate_compare (code);
11850 cond_code = GET_CODE (condition_rtx);
11852 if (rs6000_compare_fp_p
11853 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11857 PUT_MODE (condition_rtx, SImode);
11858 t = XEXP (condition_rtx, 0);
11860 gcc_assert (cond_code == NE || cond_code == EQ);
11862 if (cond_code == NE)
11863 emit_insn (gen_e500_flip_gt_bit (t, t));
11865 emit_insn (gen_move_from_CR_gt_bit (result, t));
11869 if (cond_code == NE
11870 || cond_code == GE || cond_code == LE
11871 || cond_code == GEU || cond_code == LEU
11872 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11874 rtx not_result = gen_reg_rtx (CCEQmode);
11875 rtx not_op, rev_cond_rtx;
11876 enum machine_mode cc_mode;
11878 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11880 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11881 SImode, XEXP (condition_rtx, 0), const0_rtx);
11882 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11883 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11884 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11887 op_mode = GET_MODE (rs6000_compare_op0);
11888 if (op_mode == VOIDmode)
11889 op_mode = GET_MODE (rs6000_compare_op1);
11891 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11893 PUT_MODE (condition_rtx, DImode);
11894 convert_move (result, condition_rtx, 0);
11898 PUT_MODE (condition_rtx, SImode);
11899 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11903 /* Emit a branch of kind CODE to location LOC. */
11906 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11908 rtx condition_rtx, loc_ref;
11910 condition_rtx = rs6000_generate_compare (code);
11911 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11912 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11913 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11914 loc_ref, pc_rtx)));
11917 /* Return the string to output a conditional branch to LABEL, which is
11918 the operand number of the label, or -1 if the branch is really a
11919 conditional return.
11921 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11922 condition code register and its mode specifies what kind of
11923 comparison we made.
11925 REVERSED is nonzero if we should reverse the sense of the comparison.
11927 INSN is the insn. */
11930 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11932 static char string[64];
11933 enum rtx_code code = GET_CODE (op);
11934 rtx cc_reg = XEXP (op, 0);
11935 enum machine_mode mode = GET_MODE (cc_reg);
11936 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11937 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11938 int really_reversed = reversed ^ need_longbranch;
11944 validate_condition_mode (code, mode);
11946 /* Work out which way this really branches. We could use
11947 reverse_condition_maybe_unordered here always but this
11948 makes the resulting assembler clearer. */
11949 if (really_reversed)
11951 /* Reversal of FP compares takes care -- an ordered compare
11952 becomes an unordered compare and vice versa. */
11953 if (mode == CCFPmode)
11954 code = reverse_condition_maybe_unordered (code);
11956 code = reverse_condition (code);
11959 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11961 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11966 /* Opposite of GT. */
11975 gcc_unreachable ();
11981 /* Not all of these are actually distinct opcodes, but
11982 we distinguish them for clarity of the resulting assembler. */
11983 case NE: case LTGT:
11984 ccode = "ne"; break;
11985 case EQ: case UNEQ:
11986 ccode = "eq"; break;
11988 ccode = "ge"; break;
11989 case GT: case GTU: case UNGT:
11990 ccode = "gt"; break;
11992 ccode = "le"; break;
11993 case LT: case LTU: case UNLT:
11994 ccode = "lt"; break;
11995 case UNORDERED: ccode = "un"; break;
11996 case ORDERED: ccode = "nu"; break;
11997 case UNGE: ccode = "nl"; break;
11998 case UNLE: ccode = "ng"; break;
12000 gcc_unreachable ();
12003 /* Maybe we have a guess as to how likely the branch is.
12004 The old mnemonics don't have a way to specify this information. */
12006 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12007 if (note != NULL_RTX)
12009 /* PROB is the difference from 50%. */
12010 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12012 /* Only hint for highly probable/improbable branches on newer
12013 cpus as static prediction overrides processor dynamic
12014 prediction. For older cpus we may as well always hint, but
12015 assume not taken for branches that are very close to 50% as a
12016 mispredicted taken branch is more expensive than a
12017 mispredicted not-taken branch. */
12018 if (rs6000_always_hint
12019 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12020 && br_prob_note_reliable_p (note)))
12022 if (abs (prob) > REG_BR_PROB_BASE / 20
12023 && ((prob > 0) ^ need_longbranch))
12031 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12033 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12035 /* We need to escape any '%' characters in the reg_names string.
12036 Assume they'd only be the first character.... */
12037 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12039 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12043 /* If the branch distance was too far, we may have to use an
12044 unconditional branch to go the distance. */
12045 if (need_longbranch)
12046 s += sprintf (s, ",$+8\n\tb %s", label);
12048 s += sprintf (s, ",%s", label);
12054 /* Return the string to flip the GT bit on a CR. */
12056 output_e500_flip_gt_bit (rtx dst, rtx src)
12058 static char string[64];
12061 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12062 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12065 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12066 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12068 sprintf (string, "crnot %d,%d", a, b);
12072 /* Return insn index for the vector compare instruction for given CODE,
12073 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12077 get_vec_cmp_insn (enum rtx_code code,
12078 enum machine_mode dest_mode,
12079 enum machine_mode op_mode)
12081 if (!TARGET_ALTIVEC)
12082 return INSN_NOT_AVAILABLE;
12087 if (dest_mode == V16QImode && op_mode == V16QImode)
12088 return UNSPEC_VCMPEQUB;
12089 if (dest_mode == V8HImode && op_mode == V8HImode)
12090 return UNSPEC_VCMPEQUH;
12091 if (dest_mode == V4SImode && op_mode == V4SImode)
12092 return UNSPEC_VCMPEQUW;
12093 if (dest_mode == V4SImode && op_mode == V4SFmode)
12094 return UNSPEC_VCMPEQFP;
12097 if (dest_mode == V4SImode && op_mode == V4SFmode)
12098 return UNSPEC_VCMPGEFP;
12100 if (dest_mode == V16QImode && op_mode == V16QImode)
12101 return UNSPEC_VCMPGTSB;
12102 if (dest_mode == V8HImode && op_mode == V8HImode)
12103 return UNSPEC_VCMPGTSH;
12104 if (dest_mode == V4SImode && op_mode == V4SImode)
12105 return UNSPEC_VCMPGTSW;
12106 if (dest_mode == V4SImode && op_mode == V4SFmode)
12107 return UNSPEC_VCMPGTFP;
12110 if (dest_mode == V16QImode && op_mode == V16QImode)
12111 return UNSPEC_VCMPGTUB;
12112 if (dest_mode == V8HImode && op_mode == V8HImode)
12113 return UNSPEC_VCMPGTUH;
12114 if (dest_mode == V4SImode && op_mode == V4SImode)
12115 return UNSPEC_VCMPGTUW;
12120 return INSN_NOT_AVAILABLE;
12123 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12124 DMODE is expected destination mode. This is a recursive function. */
12127 rs6000_emit_vector_compare (enum rtx_code rcode,
12129 enum machine_mode dmode)
12133 enum machine_mode dest_mode;
12134 enum machine_mode op_mode = GET_MODE (op1);
12136 gcc_assert (TARGET_ALTIVEC);
12137 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12139 /* Floating point vector compare instructions uses destination V4SImode.
12140 Move destination to appropriate mode later. */
12141 if (dmode == V4SFmode)
12142 dest_mode = V4SImode;
12146 mask = gen_reg_rtx (dest_mode);
12147 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12149 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12151 bool swap_operands = false;
12152 bool try_again = false;
12157 swap_operands = true;
12162 swap_operands = true;
12170 /* Invert condition and try again.
12171 e.g., A != B becomes ~(A==B). */
12173 enum rtx_code rev_code;
12174 enum insn_code nor_code;
12177 rev_code = reverse_condition_maybe_unordered (rcode);
12178 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12181 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
12182 gcc_assert (nor_code != CODE_FOR_nothing);
12183 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12185 if (dmode != dest_mode)
12187 rtx temp = gen_reg_rtx (dest_mode);
12188 convert_move (temp, mask, 0);
12198 /* Try GT/GTU/LT/LTU OR EQ */
12201 enum insn_code ior_code;
12202 enum rtx_code new_code;
12223 gcc_unreachable ();
12226 c_rtx = rs6000_emit_vector_compare (new_code,
12227 op0, op1, dest_mode);
12228 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12231 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
12232 gcc_assert (ior_code != CODE_FOR_nothing);
12233 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12234 if (dmode != dest_mode)
12236 rtx temp = gen_reg_rtx (dest_mode);
12237 convert_move (temp, mask, 0);
12244 gcc_unreachable ();
12249 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12250 /* You only get two chances. */
12251 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12263 emit_insn (gen_rtx_SET (VOIDmode, mask,
12264 gen_rtx_UNSPEC (dest_mode,
12265 gen_rtvec (2, op0, op1),
12267 if (dmode != dest_mode)
12269 rtx temp = gen_reg_rtx (dest_mode);
12270 convert_move (temp, mask, 0);
12276 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12277 valid insn doesn exist for given mode. */
12280 get_vsel_insn (enum machine_mode mode)
12285 return UNSPEC_VSEL4SI;
12288 return UNSPEC_VSEL4SF;
12291 return UNSPEC_VSEL8HI;
12294 return UNSPEC_VSEL16QI;
12297 return INSN_NOT_AVAILABLE;
12300 return INSN_NOT_AVAILABLE;
12303 /* Emit vector select insn where DEST is destination using
12304 operands OP1, OP2 and MASK. */
12307 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12310 enum machine_mode dest_mode = GET_MODE (dest);
12311 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12313 temp = gen_reg_rtx (dest_mode);
12315 /* For each vector element, select op1 when mask is 1 otherwise
12317 t = gen_rtx_SET (VOIDmode, temp,
12318 gen_rtx_UNSPEC (dest_mode,
12319 gen_rtvec (3, op2, op1, mask),
12322 emit_move_insn (dest, temp);
12326 /* Emit vector conditional expression.
12327 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12328 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12331 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12332 rtx cond, rtx cc_op0, rtx cc_op1)
12334 enum machine_mode dest_mode = GET_MODE (dest);
12335 enum rtx_code rcode = GET_CODE (cond);
12338 if (!TARGET_ALTIVEC)
12341 /* Get the vector mask for the given relational operations. */
12342 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12344 rs6000_emit_vector_select (dest, op1, op2, mask);
12349 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12350 operands of the last comparison is nonzero/true, FALSE_COND if it
12351 is zero/false. Return 0 if the hardware has no such operation. */
12354 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12356 enum rtx_code code = GET_CODE (op);
12357 rtx op0 = rs6000_compare_op0;
12358 rtx op1 = rs6000_compare_op1;
12359 REAL_VALUE_TYPE c1;
12360 enum machine_mode compare_mode = GET_MODE (op0);
12361 enum machine_mode result_mode = GET_MODE (dest);
12363 bool is_against_zero;
12365 /* These modes should always match. */
12366 if (GET_MODE (op1) != compare_mode
12367 /* In the isel case however, we can use a compare immediate, so
12368 op1 may be a small constant. */
12369 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12371 if (GET_MODE (true_cond) != result_mode)
12373 if (GET_MODE (false_cond) != result_mode)
12376 /* First, work out if the hardware can do this at all, or
12377 if it's too slow.... */
12378 if (! rs6000_compare_fp_p)
12381 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12384 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12385 && SCALAR_FLOAT_MODE_P (compare_mode))
12388 is_against_zero = op1 == CONST0_RTX (compare_mode);
12390 /* A floating-point subtract might overflow, underflow, or produce
12391 an inexact result, thus changing the floating-point flags, so it
12392 can't be generated if we care about that. It's safe if one side
12393 of the construct is zero, since then no subtract will be
12395 if (SCALAR_FLOAT_MODE_P (compare_mode)
12396 && flag_trapping_math && ! is_against_zero)
12399 /* Eliminate half of the comparisons by switching operands, this
12400 makes the remaining code simpler. */
12401 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12402 || code == LTGT || code == LT || code == UNLE)
12404 code = reverse_condition_maybe_unordered (code);
12406 true_cond = false_cond;
12410 /* UNEQ and LTGT take four instructions for a comparison with zero,
12411 it'll probably be faster to use a branch here too. */
12412 if (code == UNEQ && HONOR_NANS (compare_mode))
12415 if (GET_CODE (op1) == CONST_DOUBLE)
12416 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12418 /* We're going to try to implement comparisons by performing
12419 a subtract, then comparing against zero. Unfortunately,
12420 Inf - Inf is NaN which is not zero, and so if we don't
12421 know that the operand is finite and the comparison
12422 would treat EQ different to UNORDERED, we can't do it. */
12423 if (HONOR_INFINITIES (compare_mode)
12424 && code != GT && code != UNGE
12425 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12426 /* Constructs of the form (a OP b ? a : b) are safe. */
12427 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12428 || (! rtx_equal_p (op0, true_cond)
12429 && ! rtx_equal_p (op1, true_cond))))
12432 /* At this point we know we can use fsel. */
12434 /* Reduce the comparison to a comparison against zero. */
12435 if (! is_against_zero)
12437 temp = gen_reg_rtx (compare_mode);
12438 emit_insn (gen_rtx_SET (VOIDmode, temp,
12439 gen_rtx_MINUS (compare_mode, op0, op1)));
12441 op1 = CONST0_RTX (compare_mode);
12444 /* If we don't care about NaNs we can reduce some of the comparisons
12445 down to faster ones. */
12446 if (! HONOR_NANS (compare_mode))
12452 true_cond = false_cond;
12465 /* Now, reduce everything down to a GE. */
12472 temp = gen_reg_rtx (compare_mode);
12473 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12478 temp = gen_reg_rtx (compare_mode);
12479 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
12484 temp = gen_reg_rtx (compare_mode);
12485 emit_insn (gen_rtx_SET (VOIDmode, temp,
12486 gen_rtx_NEG (compare_mode,
12487 gen_rtx_ABS (compare_mode, op0))));
12492 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
12493 temp = gen_reg_rtx (result_mode);
12494 emit_insn (gen_rtx_SET (VOIDmode, temp,
12495 gen_rtx_IF_THEN_ELSE (result_mode,
12496 gen_rtx_GE (VOIDmode,
12498 true_cond, false_cond)));
12499 false_cond = true_cond;
12502 temp = gen_reg_rtx (compare_mode);
12503 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12508 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
12509 temp = gen_reg_rtx (result_mode);
12510 emit_insn (gen_rtx_SET (VOIDmode, temp,
12511 gen_rtx_IF_THEN_ELSE (result_mode,
12512 gen_rtx_GE (VOIDmode,
12514 true_cond, false_cond)));
12515 true_cond = false_cond;
12518 temp = gen_reg_rtx (compare_mode);
12519 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
12524 gcc_unreachable ();
12527 emit_insn (gen_rtx_SET (VOIDmode, dest,
12528 gen_rtx_IF_THEN_ELSE (result_mode,
12529 gen_rtx_GE (VOIDmode,
12531 true_cond, false_cond)));
12535 /* Same as above, but for ints (isel). */
12538 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12540 rtx condition_rtx, cr;
12542 /* All isel implementations thus far are 32-bits. */
12543 if (GET_MODE (rs6000_compare_op0) != SImode)
12546 /* We still have to do the compare, because isel doesn't do a
12547 compare, it just looks at the CRx bits set by a previous compare
12549 condition_rtx = rs6000_generate_compare (GET_CODE (op));
12550 cr = XEXP (condition_rtx, 0);
12552 if (GET_MODE (cr) == CCmode)
12553 emit_insn (gen_isel_signed (dest, condition_rtx,
12554 true_cond, false_cond, cr));
12556 emit_insn (gen_isel_unsigned (dest, condition_rtx,
12557 true_cond, false_cond, cr));
12563 output_isel (rtx *operands)
12565 enum rtx_code code;
12567 code = GET_CODE (operands[1]);
12568 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
12570 PUT_CODE (operands[1], reverse_condition (code));
12571 return "isel %0,%3,%2,%j1";
12574 return "isel %0,%2,%3,%j1";
12578 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
12580 enum machine_mode mode = GET_MODE (op0);
12584 if (code == SMAX || code == SMIN)
12589 if (code == SMAX || code == UMAX)
12590 target = emit_conditional_move (dest, c, op0, op1, mode,
12591 op0, op1, mode, 0);
12593 target = emit_conditional_move (dest, c, op0, op1, mode,
12594 op1, op0, mode, 0);
12595 gcc_assert (target);
12596 if (target != dest)
12597 emit_move_insn (dest, target);
12600 /* Emit instructions to perform a load-reserved/store-conditional operation.
12601 The operation performed is an atomic
12602 (set M (CODE:MODE M OP))
12603 If not NULL, BEFORE is atomically set to M before the operation, and
12604 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
12605 If SYNC_P then a memory barrier is emitted before the operation.
12606 Either OP or M may be wrapped in a NOT operation. */
12609 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
12610 rtx m, rtx op, rtx before_param, rtx after_param,
12613 enum machine_mode used_mode;
12614 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
12617 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12618 rtx shift = NULL_RTX;
12621 emit_insn (gen_memory_barrier ());
12623 if (GET_CODE (m) == NOT)
12624 used_m = XEXP (m, 0);
12628 /* If this is smaller than SImode, we'll have to use SImode with
12630 if (mode == QImode || mode == HImode)
12634 if (MEM_ALIGN (used_m) >= 32)
12637 if (BYTES_BIG_ENDIAN)
12638 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
12640 shift = GEN_INT (ishift);
12644 rtx addrSI, aligned_addr;
12645 int shift_mask = mode == QImode ? 0x18 : 0x10;
12647 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
12648 XEXP (used_m, 0)));
12649 shift = gen_reg_rtx (SImode);
12651 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12652 GEN_INT (shift_mask)));
12653 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12655 aligned_addr = expand_binop (Pmode, and_optab,
12657 GEN_INT (-4), NULL_RTX,
12658 1, OPTAB_LIB_WIDEN);
12659 used_m = change_address (used_m, SImode, aligned_addr);
12660 set_mem_align (used_m, 32);
12661 /* It's safe to keep the old alias set of USED_M, because
12662 the operation is atomic and only affects the original
12664 if (GET_CODE (m) == NOT)
12665 m = gen_rtx_NOT (SImode, used_m);
12670 if (GET_CODE (op) == NOT)
12672 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
12673 oldop = gen_rtx_NOT (SImode, oldop);
12676 oldop = lowpart_subreg (SImode, op, mode);
12682 newop = expand_binop (SImode, and_optab,
12683 oldop, GEN_INT (imask), NULL_RTX,
12684 1, OPTAB_LIB_WIDEN);
12685 emit_insn (gen_ashlsi3 (newop, newop, shift));
12689 newop = expand_binop (SImode, ior_optab,
12690 oldop, GEN_INT (~imask), NULL_RTX,
12691 1, OPTAB_LIB_WIDEN);
12692 emit_insn (gen_rotlsi3 (newop, newop, shift));
12700 newop = expand_binop (SImode, and_optab,
12701 oldop, GEN_INT (imask), NULL_RTX,
12702 1, OPTAB_LIB_WIDEN);
12703 emit_insn (gen_ashlsi3 (newop, newop, shift));
12705 mask = gen_reg_rtx (SImode);
12706 emit_move_insn (mask, GEN_INT (imask));
12707 emit_insn (gen_ashlsi3 (mask, mask, shift));
12710 newop = gen_rtx_PLUS (SImode, m, newop);
12712 newop = gen_rtx_MINUS (SImode, m, newop);
12713 newop = gen_rtx_AND (SImode, newop, mask);
12714 newop = gen_rtx_IOR (SImode, newop,
12715 gen_rtx_AND (SImode,
12716 gen_rtx_NOT (SImode, mask),
12722 gcc_unreachable ();
12725 if (GET_CODE (m) == NOT)
12729 mask = gen_reg_rtx (SImode);
12730 emit_move_insn (mask, GEN_INT (imask));
12731 emit_insn (gen_ashlsi3 (mask, mask, shift));
12733 xorm = gen_rtx_XOR (SImode, used_m, mask);
12734 /* Depending on the value of 'op', the XOR or the operation might
12735 be able to be simplified away. */
12736 newop = simplify_gen_binary (code, SImode, xorm, newop);
12739 used_mode = SImode;
12740 before = gen_reg_rtx (used_mode);
12741 after = gen_reg_rtx (used_mode);
12746 before = before_param;
12747 after = after_param;
12749 if (before == NULL_RTX)
12750 before = gen_reg_rtx (used_mode);
12751 if (after == NULL_RTX)
12752 after = gen_reg_rtx (used_mode);
12755 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12756 && used_mode != mode)
12757 the_op = op; /* Computed above. */
12758 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12759 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12761 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12763 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12764 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12765 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12766 gen_rtx_UNSPEC (used_mode,
12767 gen_rtvec (1, the_op),
12769 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12771 if ((code == PLUS || code == MINUS) && used_mode != mode)
12772 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12773 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12775 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12776 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12778 /* Shift and mask the return values properly. */
12779 if (used_mode != mode && before_param)
12781 emit_insn (gen_lshrsi3 (before, before, shift));
12782 convert_move (before_param, before, 1);
12785 if (used_mode != mode && after_param)
12787 emit_insn (gen_lshrsi3 (after, after, shift));
12788 convert_move (after_param, after, 1);
12791 /* The previous sequence will end with a branch that's dependent on
12792 the conditional store, so placing an isync will ensure that no
12793 other instructions (especially, no load or store instructions)
12794 can start before the atomic operation completes. */
12796 emit_insn (gen_isync ());
12799 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12800 COND is true. Mark the jump as unlikely to be taken. */
12803 emit_unlikely_jump (rtx cond, rtx label)
12805 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12808 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12809 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12810 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12813 /* A subroutine of the atomic operation splitters. Emit a load-locked
12814 instruction in MODE. */
12817 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12819 rtx (*fn) (rtx, rtx) = NULL;
12820 if (mode == SImode)
12821 fn = gen_load_locked_si;
12822 else if (mode == DImode)
12823 fn = gen_load_locked_di;
12824 emit_insn (fn (reg, mem));
12827 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12828 instruction in MODE. */
12831 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12833 rtx (*fn) (rtx, rtx, rtx) = NULL;
12834 if (mode == SImode)
12835 fn = gen_store_conditional_si;
12836 else if (mode == DImode)
12837 fn = gen_store_conditional_di;
12839 /* Emit sync before stwcx. to address PPC405 Erratum. */
12840 if (PPC405_ERRATUM77)
12841 emit_insn (gen_memory_barrier ());
12843 emit_insn (fn (res, mem, val));
12846 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
12847 to perform. MEM is the memory on which to operate. VAL is the second
12848 operand of the binary operator. BEFORE and AFTER are optional locations to
12849 return the value of MEM either before of after the operation. SCRATCH is
12850 a scratch register. */
12853 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12854 rtx before, rtx after, rtx scratch)
12856 enum machine_mode mode = GET_MODE (mem);
12857 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12859 emit_insn (gen_memory_barrier ());
12861 label = gen_label_rtx ();
12862 emit_label (label);
12863 label = gen_rtx_LABEL_REF (VOIDmode, label);
12865 if (before == NULL_RTX)
12867 emit_load_locked (mode, before, mem);
12870 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12871 else if (code == AND)
12872 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12874 x = gen_rtx_fmt_ee (code, mode, before, val);
12876 if (after != NULL_RTX)
12877 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12878 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12880 emit_store_conditional (mode, cond, mem, scratch);
12882 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12883 emit_unlikely_jump (x, label);
12885 emit_insn (gen_isync ());
12888 /* Expand an atomic compare and swap operation. MEM is the memory on which
12889 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12890 value to be stored. SCRATCH is a scratch GPR. */
12893 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12896 enum machine_mode mode = GET_MODE (mem);
12897 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12899 emit_insn (gen_memory_barrier ());
12901 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12902 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12903 emit_label (XEXP (label1, 0));
12905 emit_load_locked (mode, retval, mem);
12907 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12908 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12910 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12911 emit_unlikely_jump (x, label2);
12913 emit_move_insn (scratch, newval);
12914 emit_store_conditional (mode, cond, mem, scratch);
12916 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12917 emit_unlikely_jump (x, label1);
12919 emit_insn (gen_isync ());
12920 emit_label (XEXP (label2, 0));
12923 /* Expand an atomic test and set operation. MEM is the memory on which
12924 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12927 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12929 enum machine_mode mode = GET_MODE (mem);
12930 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12932 emit_insn (gen_memory_barrier ());
12934 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12935 emit_label (XEXP (label, 0));
12937 emit_load_locked (mode, retval, mem);
12938 emit_move_insn (scratch, val);
12939 emit_store_conditional (mode, cond, mem, scratch);
12941 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12942 emit_unlikely_jump (x, label);
12944 emit_insn (gen_isync ());
12948 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
12950 enum machine_mode mode = GET_MODE (mem);
12951 rtx addrSI, align, wdst, shift, mask;
12952 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
12953 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
12955 /* Shift amount for subword relative to aligned word. */
12956 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
12957 shift = gen_reg_rtx (SImode);
12958 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
12959 GEN_INT (shift_mask)));
12960 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
12962 /* Shift and mask old value into position within word. */
12963 oldval = convert_modes (SImode, mode, oldval, 1);
12964 oldval = expand_binop (SImode, and_optab,
12965 oldval, GEN_INT (imask), NULL_RTX,
12966 1, OPTAB_LIB_WIDEN);
12967 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
12969 /* Shift and mask new value into position within word. */
12970 newval = convert_modes (SImode, mode, newval, 1);
12971 newval = expand_binop (SImode, and_optab,
12972 newval, GEN_INT (imask), NULL_RTX,
12973 1, OPTAB_LIB_WIDEN);
12974 emit_insn (gen_ashlsi3 (newval, newval, shift));
12976 /* Mask for insertion. */
12977 mask = gen_reg_rtx (SImode);
12978 emit_move_insn (mask, GEN_INT (imask));
12979 emit_insn (gen_ashlsi3 (mask, mask, shift));
12981 /* Address of aligned word containing subword. */
12982 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
12983 NULL_RTX, 1, OPTAB_LIB_WIDEN);
12984 mem = change_address (mem, SImode, align);
12985 set_mem_align (mem, 32);
12986 MEM_VOLATILE_P (mem) = 1;
12988 wdst = gen_reg_rtx (SImode);
12989 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
12990 oldval, newval, mem));
12992 emit_move_insn (dst, gen_lowpart (mode, wdst));
12996 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
12997 rtx oldval, rtx newval, rtx mem,
13000 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13002 emit_insn (gen_memory_barrier ());
13003 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13004 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13005 emit_label (XEXP (label1, 0));
13007 emit_load_locked (SImode, scratch, mem);
13009 /* Mask subword within loaded value for comparison with oldval.
13010 Use UNSPEC_AND to avoid clobber.*/
13011 emit_insn (gen_rtx_SET (SImode, dest,
13012 gen_rtx_UNSPEC (SImode,
13013 gen_rtvec (2, scratch, mask),
13016 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13017 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13019 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13020 emit_unlikely_jump (x, label2);
13022 /* Clear subword within loaded value for insertion of new value. */
13023 emit_insn (gen_rtx_SET (SImode, scratch,
13024 gen_rtx_AND (SImode,
13025 gen_rtx_NOT (SImode, mask), scratch)));
13026 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13027 emit_store_conditional (SImode, cond, mem, scratch);
13029 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13030 emit_unlikely_jump (x, label1);
13032 emit_insn (gen_isync ());
13033 emit_label (XEXP (label2, 0));
13037 /* Emit instructions to move SRC to DST. Called by splitters for
13038 multi-register moves. It will emit at most one instruction for
13039 each register that is accessed; that is, it won't emit li/lis pairs
13040 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13044 rs6000_split_multireg_move (rtx dst, rtx src)
13046 /* The register number of the first register being moved. */
13048 /* The mode that is to be moved. */
13049 enum machine_mode mode;
13050 /* The mode that the move is being done in, and its size. */
13051 enum machine_mode reg_mode;
13053 /* The number of registers that will be moved. */
13056 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13057 mode = GET_MODE (dst);
13058 nregs = hard_regno_nregs[reg][mode];
13059 if (FP_REGNO_P (reg))
13060 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13061 else if (ALTIVEC_REGNO_P (reg))
13062 reg_mode = V16QImode;
13063 else if (TARGET_E500_DOUBLE && mode == TFmode)
13066 reg_mode = word_mode;
13067 reg_mode_size = GET_MODE_SIZE (reg_mode);
13069 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13071 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13073 /* Move register range backwards, if we might have destructive
13076 for (i = nregs - 1; i >= 0; i--)
13077 emit_insn (gen_rtx_SET (VOIDmode,
13078 simplify_gen_subreg (reg_mode, dst, mode,
13079 i * reg_mode_size),
13080 simplify_gen_subreg (reg_mode, src, mode,
13081 i * reg_mode_size)));
13087 bool used_update = false;
13089 if (MEM_P (src) && INT_REGNO_P (reg))
13093 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13094 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13097 breg = XEXP (XEXP (src, 0), 0);
13098 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13099 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13100 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13101 emit_insn (TARGET_32BIT
13102 ? gen_addsi3 (breg, breg, delta_rtx)
13103 : gen_adddi3 (breg, breg, delta_rtx));
13104 src = replace_equiv_address (src, breg);
13106 else if (! rs6000_offsettable_memref_p (src))
13109 basereg = gen_rtx_REG (Pmode, reg);
13110 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13111 src = replace_equiv_address (src, basereg);
13114 breg = XEXP (src, 0);
13115 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13116 breg = XEXP (breg, 0);
13118 /* If the base register we are using to address memory is
13119 also a destination reg, then change that register last. */
13121 && REGNO (breg) >= REGNO (dst)
13122 && REGNO (breg) < REGNO (dst) + nregs)
13123 j = REGNO (breg) - REGNO (dst);
13126 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13130 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13131 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13134 breg = XEXP (XEXP (dst, 0), 0);
13135 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13136 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13137 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13139 /* We have to update the breg before doing the store.
13140 Use store with update, if available. */
13144 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13145 emit_insn (TARGET_32BIT
13146 ? (TARGET_POWERPC64
13147 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13148 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13149 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13150 used_update = true;
13153 emit_insn (TARGET_32BIT
13154 ? gen_addsi3 (breg, breg, delta_rtx)
13155 : gen_adddi3 (breg, breg, delta_rtx));
13156 dst = replace_equiv_address (dst, breg);
13159 gcc_assert (rs6000_offsettable_memref_p (dst));
13162 for (i = 0; i < nregs; i++)
13164 /* Calculate index to next subword. */
13169 /* If compiler already emitted move of first word by
13170 store with update, no need to do anything. */
13171 if (j == 0 && used_update)
13174 emit_insn (gen_rtx_SET (VOIDmode,
13175 simplify_gen_subreg (reg_mode, dst, mode,
13176 j * reg_mode_size),
13177 simplify_gen_subreg (reg_mode, src, mode,
13178 j * reg_mode_size)));
13184 /* This page contains routines that are used to determine what the
13185 function prologue and epilogue code will do and write them out. */
13187 /* Return the first fixed-point register that is required to be
13188 saved. 32 if none. */
13191 first_reg_to_save (void)
13195 /* Find lowest numbered live register. */
13196 for (first_reg = 13; first_reg <= 31; first_reg++)
13197 if (df_regs_ever_live_p (first_reg)
13198 && (! call_used_regs[first_reg]
13199 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13200 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13201 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13202 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13207 && current_function_uses_pic_offset_table
13208 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13209 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13215 /* Similar, for FP regs. */
13218 first_fp_reg_to_save (void)
13222 /* Find lowest numbered live register. */
13223 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13224 if (df_regs_ever_live_p (first_reg))
13230 /* Similar, for AltiVec regs. */
13233 first_altivec_reg_to_save (void)
13237 /* Stack frame remains as is unless we are in AltiVec ABI. */
13238 if (! TARGET_ALTIVEC_ABI)
13239 return LAST_ALTIVEC_REGNO + 1;
13241 /* On Darwin, the unwind routines are compiled without
13242 TARGET_ALTIVEC, and use save_world to save/restore the
13243 altivec registers when necessary. */
13244 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13245 && ! TARGET_ALTIVEC)
13246 return FIRST_ALTIVEC_REGNO + 20;
13248 /* Find lowest numbered live register. */
13249 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13250 if (df_regs_ever_live_p (i))
13256 /* Return a 32-bit mask of the AltiVec registers we need to set in
13257 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13258 the 32-bit word is 0. */
13260 static unsigned int
13261 compute_vrsave_mask (void)
13263 unsigned int i, mask = 0;
13265 /* On Darwin, the unwind routines are compiled without
13266 TARGET_ALTIVEC, and use save_world to save/restore the
13267 call-saved altivec registers when necessary. */
13268 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13269 && ! TARGET_ALTIVEC)
13272 /* First, find out if we use _any_ altivec registers. */
13273 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13274 if (df_regs_ever_live_p (i))
13275 mask |= ALTIVEC_REG_BIT (i);
13280 /* Next, remove the argument registers from the set. These must
13281 be in the VRSAVE mask set by the caller, so we don't need to add
13282 them in again. More importantly, the mask we compute here is
13283 used to generate CLOBBERs in the set_vrsave insn, and we do not
13284 wish the argument registers to die. */
13285 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13286 mask &= ~ALTIVEC_REG_BIT (i);
13288 /* Similarly, remove the return value from the set. */
13291 diddle_return_value (is_altivec_return_reg, &yes);
13293 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13299 /* For a very restricted set of circumstances, we can cut down the
13300 size of prologues/epilogues by calling our own save/restore-the-world
13304 compute_save_world_info (rs6000_stack_t *info_ptr)
13306 info_ptr->world_save_p = 1;
13307 info_ptr->world_save_p
13308 = (WORLD_SAVE_P (info_ptr)
13309 && DEFAULT_ABI == ABI_DARWIN
13310 && ! (current_function_calls_setjmp && flag_exceptions)
13311 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13312 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13313 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13314 && info_ptr->cr_save_p);
13316 /* This will not work in conjunction with sibcalls. Make sure there
13317 are none. (This check is expensive, but seldom executed.) */
13318 if (WORLD_SAVE_P (info_ptr))
13321 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13322 if ( GET_CODE (insn) == CALL_INSN
13323 && SIBLING_CALL_P (insn))
13325 info_ptr->world_save_p = 0;
13330 if (WORLD_SAVE_P (info_ptr))
13332 /* Even if we're not touching VRsave, make sure there's room on the
13333 stack for it, if it looks like we're calling SAVE_WORLD, which
13334 will attempt to save it. */
13335 info_ptr->vrsave_size = 4;
13337 /* "Save" the VRsave register too if we're saving the world. */
13338 if (info_ptr->vrsave_mask == 0)
13339 info_ptr->vrsave_mask = compute_vrsave_mask ();
13341 /* Because the Darwin register save/restore routines only handle
13342 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13344 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13345 && (info_ptr->first_altivec_reg_save
13346 >= FIRST_SAVED_ALTIVEC_REGNO));
13353 is_altivec_return_reg (rtx reg, void *xyes)
13355 bool *yes = (bool *) xyes;
13356 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13361 /* Calculate the stack information for the current function. This is
13362 complicated by having two separate calling sequences, the AIX calling
13363 sequence and the V.4 calling sequence.
13365 AIX (and Darwin/Mac OS X) stack frames look like:
13367 SP----> +---------------------------------------+
13368 | back chain to caller | 0 0
13369 +---------------------------------------+
13370 | saved CR | 4 8 (8-11)
13371 +---------------------------------------+
13373 +---------------------------------------+
13374 | reserved for compilers | 12 24
13375 +---------------------------------------+
13376 | reserved for binders | 16 32
13377 +---------------------------------------+
13378 | saved TOC pointer | 20 40
13379 +---------------------------------------+
13380 | Parameter save area (P) | 24 48
13381 +---------------------------------------+
13382 | Alloca space (A) | 24+P etc.
13383 +---------------------------------------+
13384 | Local variable space (L) | 24+P+A
13385 +---------------------------------------+
13386 | Float/int conversion temporary (X) | 24+P+A+L
13387 +---------------------------------------+
13388 | Save area for AltiVec registers (W) | 24+P+A+L+X
13389 +---------------------------------------+
13390 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13391 +---------------------------------------+
13392 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13393 +---------------------------------------+
13394 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13395 +---------------------------------------+
13396 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13397 +---------------------------------------+
13398 old SP->| back chain to caller's caller |
13399 +---------------------------------------+
13401 The required alignment for AIX configurations is two words (i.e., 8
13405 V.4 stack frames look like:
13407 SP----> +---------------------------------------+
13408 | back chain to caller | 0
13409 +---------------------------------------+
13410 | caller's saved LR | 4
13411 +---------------------------------------+
13412 | Parameter save area (P) | 8
13413 +---------------------------------------+
13414 | Alloca space (A) | 8+P
13415 +---------------------------------------+
13416 | Varargs save area (V) | 8+P+A
13417 +---------------------------------------+
13418 | Local variable space (L) | 8+P+A+V
13419 +---------------------------------------+
13420 | Float/int conversion temporary (X) | 8+P+A+V+L
13421 +---------------------------------------+
13422 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13423 +---------------------------------------+
13424 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13425 +---------------------------------------+
13426 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13427 +---------------------------------------+
13428 | SPE: area for 64-bit GP registers |
13429 +---------------------------------------+
13430 | SPE alignment padding |
13431 +---------------------------------------+
13432 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13433 +---------------------------------------+
13434 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13435 +---------------------------------------+
13436 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13437 +---------------------------------------+
13438 old SP->| back chain to caller's caller |
13439 +---------------------------------------+
13441 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13442 given. (But note below and in sysv4.h that we require only 8 and
13443 may round up the size of our stack frame anyways. The historical
13444 reason is early versions of powerpc-linux which didn't properly
13445 align the stack at program startup. A happy side-effect is that
13446 -mno-eabi libraries can be used with -meabi programs.)
13448 The EABI configuration defaults to the V.4 layout. However,
13449 the stack alignment requirements may differ. If -mno-eabi is not
13450 given, the required stack alignment is 8 bytes; if -mno-eabi is
13451 given, the required alignment is 16 bytes. (But see V.4 comment
13454 #ifndef ABI_STACK_BOUNDARY
13455 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
13458 static rs6000_stack_t *
13459 rs6000_stack_info (void)
13461 static rs6000_stack_t info;
13462 rs6000_stack_t *info_ptr = &info;
13463 int reg_size = TARGET_32BIT ? 4 : 8;
13466 HOST_WIDE_INT non_fixed_size;
13468 memset (&info, 0, sizeof (info));
13472 /* Cache value so we don't rescan instruction chain over and over. */
13473 if (cfun->machine->insn_chain_scanned_p == 0)
13474 cfun->machine->insn_chain_scanned_p
13475 = spe_func_has_64bit_regs_p () + 1;
13476 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
13479 /* Select which calling sequence. */
13480 info_ptr->abi = DEFAULT_ABI;
13482 /* Calculate which registers need to be saved & save area size. */
13483 info_ptr->first_gp_reg_save = first_reg_to_save ();
13484 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
13485 even if it currently looks like we won't. */
13486 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
13487 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
13488 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
13489 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
13490 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
13492 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
13494 /* For the SPE, we have an additional upper 32-bits on each GPR.
13495 Ideally we should save the entire 64-bits only when the upper
13496 half is used in SIMD instructions. Since we only record
13497 registers live (not the size they are used in), this proves
13498 difficult because we'd have to traverse the instruction chain at
13499 the right time, taking reload into account. This is a real pain,
13500 so we opt to save the GPRs in 64-bits always if but one register
13501 gets used in 64-bits. Otherwise, all the registers in the frame
13502 get saved in 32-bits.
13504 So... since when we save all GPRs (except the SP) in 64-bits, the
13505 traditional GP save area will be empty. */
13506 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13507 info_ptr->gp_size = 0;
13509 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
13510 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
13512 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
13513 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
13514 - info_ptr->first_altivec_reg_save);
13516 /* Does this function call anything? */
13517 info_ptr->calls_p = (! current_function_is_leaf
13518 || cfun->machine->ra_needs_full_frame);
13520 /* Determine if we need to save the link register. */
13521 if ((DEFAULT_ABI == ABI_AIX
13522 && current_function_profile
13523 && !TARGET_PROFILE_KERNEL)
13524 #ifdef TARGET_RELOCATABLE
13525 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
13527 || (info_ptr->first_fp_reg_save != 64
13528 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
13529 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
13530 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
13531 || info_ptr->calls_p
13532 || rs6000_ra_ever_killed ())
13534 info_ptr->lr_save_p = 1;
13535 df_set_regs_ever_live (LR_REGNO, true);
13538 /* Determine if we need to save the condition code registers. */
13539 if (df_regs_ever_live_p (CR2_REGNO)
13540 || df_regs_ever_live_p (CR3_REGNO)
13541 || df_regs_ever_live_p (CR4_REGNO))
13543 info_ptr->cr_save_p = 1;
13544 if (DEFAULT_ABI == ABI_V4)
13545 info_ptr->cr_size = reg_size;
13548 /* If the current function calls __builtin_eh_return, then we need
13549 to allocate stack space for registers that will hold data for
13550 the exception handler. */
13551 if (current_function_calls_eh_return)
13554 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
13557 /* SPE saves EH registers in 64-bits. */
13558 ehrd_size = i * (TARGET_SPE_ABI
13559 && info_ptr->spe_64bit_regs_used != 0
13560 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
13565 /* Determine various sizes. */
13566 info_ptr->reg_size = reg_size;
13567 info_ptr->fixed_size = RS6000_SAVE_AREA;
13568 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
13569 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
13570 TARGET_ALTIVEC ? 16 : 8);
13571 if (FRAME_GROWS_DOWNWARD)
13572 info_ptr->vars_size
13573 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
13574 + info_ptr->parm_size,
13575 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
13576 - (info_ptr->fixed_size + info_ptr->vars_size
13577 + info_ptr->parm_size);
13579 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13580 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
13582 info_ptr->spe_gp_size = 0;
13584 if (TARGET_ALTIVEC_ABI)
13585 info_ptr->vrsave_mask = compute_vrsave_mask ();
13587 info_ptr->vrsave_mask = 0;
13589 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
13590 info_ptr->vrsave_size = 4;
13592 info_ptr->vrsave_size = 0;
13594 compute_save_world_info (info_ptr);
13596 /* Calculate the offsets. */
13597 switch (DEFAULT_ABI)
13601 gcc_unreachable ();
13605 info_ptr->fp_save_offset = - info_ptr->fp_size;
13606 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13608 if (TARGET_ALTIVEC_ABI)
13610 info_ptr->vrsave_save_offset
13611 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
13613 /* Align stack so vector save area is on a quadword boundary.
13614 The padding goes above the vectors. */
13615 if (info_ptr->altivec_size != 0)
13616 info_ptr->altivec_padding_size
13617 = info_ptr->vrsave_save_offset & 0xF;
13619 info_ptr->altivec_padding_size = 0;
13621 info_ptr->altivec_save_offset
13622 = info_ptr->vrsave_save_offset
13623 - info_ptr->altivec_padding_size
13624 - info_ptr->altivec_size;
13625 gcc_assert (info_ptr->altivec_size == 0
13626 || info_ptr->altivec_save_offset % 16 == 0);
13628 /* Adjust for AltiVec case. */
13629 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
13632 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
13633 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
13634 info_ptr->lr_save_offset = 2*reg_size;
13638 info_ptr->fp_save_offset = - info_ptr->fp_size;
13639 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
13640 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
13642 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
13644 /* Align stack so SPE GPR save area is aligned on a
13645 double-word boundary. */
13646 if (info_ptr->spe_gp_size != 0)
13647 info_ptr->spe_padding_size
13648 = 8 - (-info_ptr->cr_save_offset % 8);
13650 info_ptr->spe_padding_size = 0;
13652 info_ptr->spe_gp_save_offset
13653 = info_ptr->cr_save_offset
13654 - info_ptr->spe_padding_size
13655 - info_ptr->spe_gp_size;
13657 /* Adjust for SPE case. */
13658 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
13660 else if (TARGET_ALTIVEC_ABI)
13662 info_ptr->vrsave_save_offset
13663 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
13665 /* Align stack so vector save area is on a quadword boundary. */
13666 if (info_ptr->altivec_size != 0)
13667 info_ptr->altivec_padding_size
13668 = 16 - (-info_ptr->vrsave_save_offset % 16);
13670 info_ptr->altivec_padding_size = 0;
13672 info_ptr->altivec_save_offset
13673 = info_ptr->vrsave_save_offset
13674 - info_ptr->altivec_padding_size
13675 - info_ptr->altivec_size;
13677 /* Adjust for AltiVec case. */
13678 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
13681 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
13682 info_ptr->ehrd_offset -= ehrd_size;
13683 info_ptr->lr_save_offset = reg_size;
13687 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
13688 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
13689 + info_ptr->gp_size
13690 + info_ptr->altivec_size
13691 + info_ptr->altivec_padding_size
13692 + info_ptr->spe_gp_size
13693 + info_ptr->spe_padding_size
13695 + info_ptr->cr_size
13696 + info_ptr->vrsave_size,
13699 non_fixed_size = (info_ptr->vars_size
13700 + info_ptr->parm_size
13701 + info_ptr->save_size);
13703 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
13704 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
13706 /* Determine if we need to allocate any stack frame:
13708 For AIX we need to push the stack if a frame pointer is needed
13709 (because the stack might be dynamically adjusted), if we are
13710 debugging, if we make calls, or if the sum of fp_save, gp_save,
13711 and local variables are more than the space needed to save all
13712 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
13713 + 18*8 = 288 (GPR13 reserved).
13715 For V.4 we don't have the stack cushion that AIX uses, but assume
13716 that the debugger can handle stackless frames. */
13718 if (info_ptr->calls_p)
13719 info_ptr->push_p = 1;
13721 else if (DEFAULT_ABI == ABI_V4)
13722 info_ptr->push_p = non_fixed_size != 0;
13724 else if (frame_pointer_needed)
13725 info_ptr->push_p = 1;
13727 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
13728 info_ptr->push_p = 1;
13731 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
13733 /* Zero offsets if we're not saving those registers. */
13734 if (info_ptr->fp_size == 0)
13735 info_ptr->fp_save_offset = 0;
13737 if (info_ptr->gp_size == 0)
13738 info_ptr->gp_save_offset = 0;
13740 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
13741 info_ptr->altivec_save_offset = 0;
13743 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
13744 info_ptr->vrsave_save_offset = 0;
13746 if (! TARGET_SPE_ABI
13747 || info_ptr->spe_64bit_regs_used == 0
13748 || info_ptr->spe_gp_size == 0)
13749 info_ptr->spe_gp_save_offset = 0;
13751 if (! info_ptr->lr_save_p)
13752 info_ptr->lr_save_offset = 0;
13754 if (! info_ptr->cr_save_p)
13755 info_ptr->cr_save_offset = 0;
13760 /* Return true if the current function uses any GPRs in 64-bit SIMD
13764 spe_func_has_64bit_regs_p (void)
13768 /* Functions that save and restore all the call-saved registers will
13769 need to save/restore the registers in 64-bits. */
13770 if (current_function_calls_eh_return
13771 || current_function_calls_setjmp
13772 || current_function_has_nonlocal_goto)
13775 insns = get_insns ();
13777 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
13783 /* FIXME: This should be implemented with attributes...
13785 (set_attr "spe64" "true")....then,
13786 if (get_spe64(insn)) return true;
13788 It's the only reliable way to do the stuff below. */
13790 i = PATTERN (insn);
13791 if (GET_CODE (i) == SET)
13793 enum machine_mode mode = GET_MODE (SET_SRC (i));
13795 if (SPE_VECTOR_MODE (mode))
13797 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
13807 debug_stack_info (rs6000_stack_t *info)
13809 const char *abi_string;
13812 info = rs6000_stack_info ();
13814 fprintf (stderr, "\nStack information for function %s:\n",
13815 ((current_function_decl && DECL_NAME (current_function_decl))
13816 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13821 default: abi_string = "Unknown"; break;
13822 case ABI_NONE: abi_string = "NONE"; break;
13823 case ABI_AIX: abi_string = "AIX"; break;
13824 case ABI_DARWIN: abi_string = "Darwin"; break;
13825 case ABI_V4: abi_string = "V.4"; break;
13828 fprintf (stderr, "\tABI = %5s\n", abi_string);
13830 if (TARGET_ALTIVEC_ABI)
13831 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13833 if (TARGET_SPE_ABI)
13834 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13836 if (info->first_gp_reg_save != 32)
13837 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13839 if (info->first_fp_reg_save != 64)
13840 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13842 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13843 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13844 info->first_altivec_reg_save);
13846 if (info->lr_save_p)
13847 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13849 if (info->cr_save_p)
13850 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13852 if (info->vrsave_mask)
13853 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13856 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13859 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13861 if (info->gp_save_offset)
13862 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13864 if (info->fp_save_offset)
13865 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13867 if (info->altivec_save_offset)
13868 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13869 info->altivec_save_offset);
13871 if (info->spe_gp_save_offset)
13872 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13873 info->spe_gp_save_offset);
13875 if (info->vrsave_save_offset)
13876 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13877 info->vrsave_save_offset);
13879 if (info->lr_save_offset)
13880 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13882 if (info->cr_save_offset)
13883 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13885 if (info->varargs_save_offset)
13886 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13888 if (info->total_size)
13889 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13892 if (info->vars_size)
13893 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13896 if (info->parm_size)
13897 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13899 if (info->fixed_size)
13900 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13903 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13905 if (info->spe_gp_size)
13906 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13909 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13911 if (info->altivec_size)
13912 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13914 if (info->vrsave_size)
13915 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13917 if (info->altivec_padding_size)
13918 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13919 info->altivec_padding_size);
13921 if (info->spe_padding_size)
13922 fprintf (stderr, "\tspe_padding_size = %5d\n",
13923 info->spe_padding_size);
13926 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13928 if (info->save_size)
13929 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13931 if (info->reg_size != 4)
13932 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13934 fprintf (stderr, "\n");
13938 rs6000_return_addr (int count, rtx frame)
13940 /* Currently we don't optimize very well between prolog and body
13941 code and for PIC code the code can be actually quite bad, so
13942 don't try to be too clever here. */
13943 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13945 cfun->machine->ra_needs_full_frame = 1;
13952 plus_constant (copy_to_reg
13953 (gen_rtx_MEM (Pmode,
13954 memory_address (Pmode, frame))),
13955 RETURN_ADDRESS_OFFSET)));
13958 cfun->machine->ra_need_lr = 1;
13959 return get_hard_reg_initial_val (Pmode, LR_REGNO);
13962 /* Say whether a function is a candidate for sibcall handling or not.
13963 We do not allow indirect calls to be optimized into sibling calls.
13964 Also, we can't do it if there are any vector parameters; there's
13965 nowhere to put the VRsave code so it works; note that functions with
13966 vector parameters are required to have a prototype, so the argument
13967 type info must be available here. (The tail recursion case can work
13968 with vector parameters, but there's no way to distinguish here.) */
13970 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13975 if (TARGET_ALTIVEC_VRSAVE)
13977 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13978 type; type = TREE_CHAIN (type))
13980 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13984 if (DEFAULT_ABI == ABI_DARWIN
13985 || ((*targetm.binds_local_p) (decl)
13986 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
13988 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13990 if (!lookup_attribute ("longcall", attr_list)
13991 || lookup_attribute ("shortcall", attr_list))
13998 /* NULL if INSN insn is valid within a low-overhead loop.
13999 Otherwise return why doloop cannot be applied.
14000 PowerPC uses the COUNT register for branch on table instructions. */
14002 static const char *
14003 rs6000_invalid_within_doloop (rtx insn)
14006 return "Function call in the loop.";
14009 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14010 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14011 return "Computed branch in the loop.";
14017 rs6000_ra_ever_killed (void)
14023 if (current_function_is_thunk)
14026 /* regs_ever_live has LR marked as used if any sibcalls are present,
14027 but this should not force saving and restoring in the
14028 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14029 clobbers LR, so that is inappropriate. */
14031 /* Also, the prologue can generate a store into LR that
14032 doesn't really count, like this:
14035 bcl to set PIC register
14039 When we're called from the epilogue, we need to avoid counting
14040 this as a store. */
14042 push_topmost_sequence ();
14043 top = get_insns ();
14044 pop_topmost_sequence ();
14045 reg = gen_rtx_REG (Pmode, LR_REGNO);
14047 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14053 if (!SIBLING_CALL_P (insn))
14056 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14058 else if (set_of (reg, insn) != NULL_RTX
14059 && !prologue_epilogue_contains (insn))
14066 /* Emit instructions needed to load the TOC register.
14067 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14068 a constant pool; or for SVR4 -fpic. */
14071 rs6000_emit_load_toc_table (int fromprolog)
14074 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14076 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14079 rtx lab, tmp1, tmp2, got;
14081 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14082 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14084 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14086 got = rs6000_got_sym ();
14087 tmp1 = tmp2 = dest;
14090 tmp1 = gen_reg_rtx (Pmode);
14091 tmp2 = gen_reg_rtx (Pmode);
14093 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14094 emit_move_insn (tmp1,
14095 gen_rtx_REG (Pmode, LR_REGNO));
14096 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14097 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14099 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14101 emit_insn (gen_load_toc_v4_pic_si ());
14102 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14104 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14107 rtx temp0 = (fromprolog
14108 ? gen_rtx_REG (Pmode, 0)
14109 : gen_reg_rtx (Pmode));
14115 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14116 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14118 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14119 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14121 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14122 emit_move_insn (dest,
14123 gen_rtx_REG (Pmode, LR_REGNO));
14124 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14130 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14131 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14132 emit_move_insn (dest,
14133 gen_rtx_REG (Pmode, LR_REGNO));
14134 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14136 emit_insn (gen_addsi3 (dest, temp0, dest));
14138 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14140 /* This is for AIX code running in non-PIC ELF32. */
14143 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14144 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14146 emit_insn (gen_elf_high (dest, realsym));
14147 emit_insn (gen_elf_low (dest, dest, realsym));
14151 gcc_assert (DEFAULT_ABI == ABI_AIX);
14154 emit_insn (gen_load_toc_aix_si (dest));
14156 emit_insn (gen_load_toc_aix_di (dest));
14160 /* Emit instructions to restore the link register after determining where
14161 its value has been stored. */
14164 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14166 rs6000_stack_t *info = rs6000_stack_info ();
14169 operands[0] = source;
14170 operands[1] = scratch;
14172 if (info->lr_save_p)
14174 rtx frame_rtx = stack_pointer_rtx;
14175 HOST_WIDE_INT sp_offset = 0;
14178 if (frame_pointer_needed
14179 || current_function_calls_alloca
14180 || info->total_size > 32767)
14182 tmp = gen_frame_mem (Pmode, frame_rtx);
14183 emit_move_insn (operands[1], tmp);
14184 frame_rtx = operands[1];
14186 else if (info->push_p)
14187 sp_offset = info->total_size;
14189 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14190 tmp = gen_frame_mem (Pmode, tmp);
14191 emit_move_insn (tmp, operands[0]);
14194 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14197 static GTY(()) int set = -1;
14200 get_TOC_alias_set (void)
14203 set = new_alias_set ();
14207 /* This returns nonzero if the current function uses the TOC. This is
14208 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14209 is generated by the ABI_V4 load_toc_* patterns. */
14216 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14219 rtx pat = PATTERN (insn);
14222 if (GET_CODE (pat) == PARALLEL)
14223 for (i = 0; i < XVECLEN (pat, 0); i++)
14225 rtx sub = XVECEXP (pat, 0, i);
14226 if (GET_CODE (sub) == USE)
14228 sub = XEXP (sub, 0);
14229 if (GET_CODE (sub) == UNSPEC
14230 && XINT (sub, 1) == UNSPEC_TOC)
14240 create_TOC_reference (rtx symbol)
14242 if (!can_create_pseudo_p ())
14243 df_set_regs_ever_live (TOC_REGISTER, true);
14244 return gen_rtx_PLUS (Pmode,
14245 gen_rtx_REG (Pmode, TOC_REGISTER),
14246 gen_rtx_CONST (Pmode,
14247 gen_rtx_MINUS (Pmode, symbol,
14248 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14251 /* If _Unwind_* has been called from within the same module,
14252 toc register is not guaranteed to be saved to 40(1) on function
14253 entry. Save it there in that case. */
14256 rs6000_aix_emit_builtin_unwind_init (void)
14259 rtx stack_top = gen_reg_rtx (Pmode);
14260 rtx opcode_addr = gen_reg_rtx (Pmode);
14261 rtx opcode = gen_reg_rtx (SImode);
14262 rtx tocompare = gen_reg_rtx (SImode);
14263 rtx no_toc_save_needed = gen_label_rtx ();
14265 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14266 emit_move_insn (stack_top, mem);
14268 mem = gen_frame_mem (Pmode,
14269 gen_rtx_PLUS (Pmode, stack_top,
14270 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14271 emit_move_insn (opcode_addr, mem);
14272 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14273 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14274 : 0xE8410028, SImode));
14276 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14277 SImode, NULL_RTX, NULL_RTX,
14278 no_toc_save_needed);
14280 mem = gen_frame_mem (Pmode,
14281 gen_rtx_PLUS (Pmode, stack_top,
14282 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14283 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14284 emit_label (no_toc_save_needed);
14287 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14288 and the change to the stack pointer. */
14291 rs6000_emit_stack_tie (void)
14293 rtx mem = gen_frame_mem (BLKmode,
14294 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14296 emit_insn (gen_stack_tie (mem));
14299 /* Emit the correct code for allocating stack space, as insns.
14300 If COPY_R12, make sure a copy of the old frame is left in r12.
14301 The generated code may use hard register 0 as a temporary. */
14304 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14307 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14308 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14309 rtx todec = gen_int_mode (-size, Pmode);
14311 if (INTVAL (todec) != -size)
14313 warning (0, "stack frame too large");
14314 emit_insn (gen_trap ());
14318 if (current_function_limit_stack)
14320 if (REG_P (stack_limit_rtx)
14321 && REGNO (stack_limit_rtx) > 1
14322 && REGNO (stack_limit_rtx) <= 31)
14324 emit_insn (TARGET_32BIT
14325 ? gen_addsi3 (tmp_reg,
14328 : gen_adddi3 (tmp_reg,
14332 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14335 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14337 && DEFAULT_ABI == ABI_V4)
14339 rtx toload = gen_rtx_CONST (VOIDmode,
14340 gen_rtx_PLUS (Pmode,
14344 emit_insn (gen_elf_high (tmp_reg, toload));
14345 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14346 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14350 warning (0, "stack limit expression is not supported");
14353 if (copy_r12 || ! TARGET_UPDATE)
14354 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14360 /* Need a note here so that try_split doesn't get confused. */
14361 if (get_last_insn () == NULL_RTX)
14362 emit_note (NOTE_INSN_DELETED);
14363 insn = emit_move_insn (tmp_reg, todec);
14364 try_split (PATTERN (insn), insn, 0);
14368 insn = emit_insn (TARGET_32BIT
14369 ? gen_movsi_update (stack_reg, stack_reg,
14371 : gen_movdi_di_update (stack_reg, stack_reg,
14372 todec, stack_reg));
14376 insn = emit_insn (TARGET_32BIT
14377 ? gen_addsi3 (stack_reg, stack_reg, todec)
14378 : gen_adddi3 (stack_reg, stack_reg, todec));
14379 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14380 gen_rtx_REG (Pmode, 12));
14383 RTX_FRAME_RELATED_P (insn) = 1;
14385 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14386 gen_rtx_SET (VOIDmode, stack_reg,
14387 gen_rtx_PLUS (Pmode, stack_reg,
14392 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14393 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14394 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14395 deduce these equivalences by itself so it wasn't necessary to hold
14396 its hand so much. */
14399 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14400 rtx reg2, rtx rreg)
14404 /* copy_rtx will not make unique copies of registers, so we need to
14405 ensure we don't have unwanted sharing here. */
14407 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14410 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14412 real = copy_rtx (PATTERN (insn));
14414 if (reg2 != NULL_RTX)
14415 real = replace_rtx (real, reg2, rreg);
14417 real = replace_rtx (real, reg,
14418 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14419 STACK_POINTER_REGNUM),
14422 /* We expect that 'real' is either a SET or a PARALLEL containing
14423 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14424 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14426 if (GET_CODE (real) == SET)
14430 temp = simplify_rtx (SET_SRC (set));
14432 SET_SRC (set) = temp;
14433 temp = simplify_rtx (SET_DEST (set));
14435 SET_DEST (set) = temp;
14436 if (GET_CODE (SET_DEST (set)) == MEM)
14438 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14440 XEXP (SET_DEST (set), 0) = temp;
14447 gcc_assert (GET_CODE (real) == PARALLEL);
14448 for (i = 0; i < XVECLEN (real, 0); i++)
14449 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
14451 rtx set = XVECEXP (real, 0, i);
14453 temp = simplify_rtx (SET_SRC (set));
14455 SET_SRC (set) = temp;
14456 temp = simplify_rtx (SET_DEST (set));
14458 SET_DEST (set) = temp;
14459 if (GET_CODE (SET_DEST (set)) == MEM)
14461 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14463 XEXP (SET_DEST (set), 0) = temp;
14465 RTX_FRAME_RELATED_P (set) = 1;
14470 real = spe_synthesize_frame_save (real);
14472 RTX_FRAME_RELATED_P (insn) = 1;
14473 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14478 /* Given an SPE frame note, return a PARALLEL of SETs with the
14479 original note, plus a synthetic register save. */
14482 spe_synthesize_frame_save (rtx real)
14484 rtx synth, offset, reg, real2;
14486 if (GET_CODE (real) != SET
14487 || GET_MODE (SET_SRC (real)) != V2SImode)
14490 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
14491 frame related note. The parallel contains a set of the register
14492 being saved, and another set to a synthetic register (n+1200).
14493 This is so we can differentiate between 64-bit and 32-bit saves.
14494 Words cannot describe this nastiness. */
14496 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
14497 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
14498 && GET_CODE (SET_SRC (real)) == REG);
14501 (set (mem (plus (reg x) (const y)))
14504 (set (mem (plus (reg x) (const y+4)))
14508 real2 = copy_rtx (real);
14509 PUT_MODE (SET_DEST (real2), SImode);
14510 reg = SET_SRC (real2);
14511 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
14512 synth = copy_rtx (real2);
14514 if (BYTES_BIG_ENDIAN)
14516 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
14517 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
14520 reg = SET_SRC (synth);
14522 synth = replace_rtx (synth, reg,
14523 gen_rtx_REG (SImode, REGNO (reg) + 1200));
14525 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
14526 synth = replace_rtx (synth, offset,
14527 GEN_INT (INTVAL (offset)
14528 + (BYTES_BIG_ENDIAN ? 0 : 4)));
14530 RTX_FRAME_RELATED_P (synth) = 1;
14531 RTX_FRAME_RELATED_P (real2) = 1;
14532 if (BYTES_BIG_ENDIAN)
14533 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
14535 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
14540 /* Returns an insn that has a vrsave set operation with the
14541 appropriate CLOBBERs. */
14544 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
14547 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
14548 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14551 = gen_rtx_SET (VOIDmode,
14553 gen_rtx_UNSPEC_VOLATILE (SImode,
14554 gen_rtvec (2, reg, vrsave),
14555 UNSPECV_SET_VRSAVE));
14559 /* We need to clobber the registers in the mask so the scheduler
14560 does not move sets to VRSAVE before sets of AltiVec registers.
14562 However, if the function receives nonlocal gotos, reload will set
14563 all call saved registers live. We will end up with:
14565 (set (reg 999) (mem))
14566 (parallel [ (set (reg vrsave) (unspec blah))
14567 (clobber (reg 999))])
14569 The clobber will cause the store into reg 999 to be dead, and
14570 flow will attempt to delete an epilogue insn. In this case, we
14571 need an unspec use/set of the register. */
14573 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
14574 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14576 if (!epiloguep || call_used_regs [i])
14577 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
14578 gen_rtx_REG (V4SImode, i));
14581 rtx reg = gen_rtx_REG (V4SImode, i);
14584 = gen_rtx_SET (VOIDmode,
14586 gen_rtx_UNSPEC (V4SImode,
14587 gen_rtvec (1, reg), 27));
14591 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
14593 for (i = 0; i < nclobs; ++i)
14594 XVECEXP (insn, 0, i) = clobs[i];
14599 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
14600 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
14603 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
14604 unsigned int regno, int offset, HOST_WIDE_INT total_size)
14606 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
14607 rtx replacea, replaceb;
14609 int_rtx = GEN_INT (offset);
14611 /* Some cases that need register indexed addressing. */
14612 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
14613 || (TARGET_E500_DOUBLE && mode == DFmode)
14615 && SPE_VECTOR_MODE (mode)
14616 && !SPE_CONST_OFFSET_OK (offset)))
14618 /* Whomever calls us must make sure r11 is available in the
14619 flow path of instructions in the prologue. */
14620 offset_rtx = gen_rtx_REG (Pmode, 11);
14621 emit_move_insn (offset_rtx, int_rtx);
14623 replacea = offset_rtx;
14624 replaceb = int_rtx;
14628 offset_rtx = int_rtx;
14629 replacea = NULL_RTX;
14630 replaceb = NULL_RTX;
14633 reg = gen_rtx_REG (mode, regno);
14634 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
14635 mem = gen_frame_mem (mode, addr);
14637 insn = emit_move_insn (mem, reg);
14639 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
14642 /* Emit an offset memory reference suitable for a frame store, while
14643 converting to a valid addressing mode. */
14646 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
14648 rtx int_rtx, offset_rtx;
14650 int_rtx = GEN_INT (offset);
14652 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
14653 || (TARGET_E500_DOUBLE && mode == DFmode))
14655 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14656 emit_move_insn (offset_rtx, int_rtx);
14659 offset_rtx = int_rtx;
14661 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
14664 /* Look for user-defined global regs. We should not save and restore these,
14665 and cannot use stmw/lmw if there are any in its range. */
14668 no_global_regs_above (int first_greg)
14671 for (i = 0; i < 32 - first_greg; i++)
14672 if (global_regs[first_greg + i])
14677 #ifndef TARGET_FIX_AND_CONTINUE
14678 #define TARGET_FIX_AND_CONTINUE 0
14681 /* Determine whether the gp REG is really used. */
14684 rs6000_reg_live_or_pic_offset_p (int reg)
14686 return ((df_regs_ever_live_p (reg)
14687 && (!call_used_regs[reg]
14688 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14689 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14690 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
14691 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14692 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
14695 /* Emit function prologue as insns. */
14698 rs6000_emit_prologue (void)
14700 rs6000_stack_t *info = rs6000_stack_info ();
14701 enum machine_mode reg_mode = Pmode;
14702 int reg_size = TARGET_32BIT ? 4 : 8;
14703 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14704 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
14705 rtx frame_reg_rtx = sp_reg_rtx;
14706 rtx cr_save_rtx = NULL_RTX;
14708 int saving_FPRs_inline;
14709 int using_store_multiple;
14710 HOST_WIDE_INT sp_offset = 0;
14712 if (TARGET_FIX_AND_CONTINUE)
14714 /* gdb on darwin arranges to forward a function from the old
14715 address by modifying the first 5 instructions of the function
14716 to branch to the overriding function. This is necessary to
14717 permit function pointers that point to the old function to
14718 actually forward to the new function. */
14719 emit_insn (gen_nop ());
14720 emit_insn (gen_nop ());
14721 emit_insn (gen_nop ());
14722 emit_insn (gen_nop ());
14723 emit_insn (gen_nop ());
14726 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14728 reg_mode = V2SImode;
14732 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14733 && (!TARGET_SPE_ABI
14734 || info->spe_64bit_regs_used == 0)
14735 && info->first_gp_reg_save < 31
14736 && no_global_regs_above (info->first_gp_reg_save));
14737 saving_FPRs_inline = (info->first_fp_reg_save == 64
14738 || FP_SAVE_INLINE (info->first_fp_reg_save)
14739 || current_function_calls_eh_return
14740 || cfun->machine->ra_need_lr);
14742 /* For V.4, update stack before we do any saving and set back pointer. */
14743 if (! WORLD_SAVE_P (info)
14745 && (DEFAULT_ABI == ABI_V4
14746 || current_function_calls_eh_return))
14748 if (info->total_size < 32767)
14749 sp_offset = info->total_size;
14751 frame_reg_rtx = frame_ptr_rtx;
14752 rs6000_emit_allocate_stack (info->total_size,
14753 (frame_reg_rtx != sp_reg_rtx
14754 && (info->cr_save_p
14756 || info->first_fp_reg_save < 64
14757 || info->first_gp_reg_save < 32
14759 if (frame_reg_rtx != sp_reg_rtx)
14760 rs6000_emit_stack_tie ();
14763 /* Handle world saves specially here. */
14764 if (WORLD_SAVE_P (info))
14771 /* save_world expects lr in r0. */
14772 reg0 = gen_rtx_REG (Pmode, 0);
14773 if (info->lr_save_p)
14775 insn = emit_move_insn (reg0,
14776 gen_rtx_REG (Pmode, LR_REGNO));
14777 RTX_FRAME_RELATED_P (insn) = 1;
14780 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14781 assumptions about the offsets of various bits of the stack
14783 gcc_assert (info->gp_save_offset == -220
14784 && info->fp_save_offset == -144
14785 && info->lr_save_offset == 8
14786 && info->cr_save_offset == 4
14789 && (!current_function_calls_eh_return
14790 || info->ehrd_offset == -432)
14791 && info->vrsave_save_offset == -224
14792 && info->altivec_save_offset == -416);
14794 treg = gen_rtx_REG (SImode, 11);
14795 emit_move_insn (treg, GEN_INT (-info->total_size));
14797 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14798 in R11. It also clobbers R12, so beware! */
14800 /* Preserve CR2 for save_world prologues */
14802 sz += 32 - info->first_gp_reg_save;
14803 sz += 64 - info->first_fp_reg_save;
14804 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14805 p = rtvec_alloc (sz);
14807 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14808 gen_rtx_REG (SImode,
14810 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14811 gen_rtx_SYMBOL_REF (Pmode,
14813 /* We do floats first so that the instruction pattern matches
14815 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14817 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14818 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14819 GEN_INT (info->fp_save_offset
14820 + sp_offset + 8 * i));
14821 rtx mem = gen_frame_mem (DFmode, addr);
14823 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14825 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14827 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14828 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14829 GEN_INT (info->altivec_save_offset
14830 + sp_offset + 16 * i));
14831 rtx mem = gen_frame_mem (V4SImode, addr);
14833 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14835 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14837 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14838 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14839 GEN_INT (info->gp_save_offset
14840 + sp_offset + reg_size * i));
14841 rtx mem = gen_frame_mem (reg_mode, addr);
14843 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14847 /* CR register traditionally saved as CR2. */
14848 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14849 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14850 GEN_INT (info->cr_save_offset
14852 rtx mem = gen_frame_mem (reg_mode, addr);
14854 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14856 /* Explain about use of R0. */
14857 if (info->lr_save_p)
14859 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14860 GEN_INT (info->lr_save_offset
14862 rtx mem = gen_frame_mem (reg_mode, addr);
14864 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
14866 /* Explain what happens to the stack pointer. */
14868 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
14869 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
14872 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14873 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14874 treg, GEN_INT (-info->total_size));
14875 sp_offset = info->total_size;
14878 /* If we use the link register, get it into r0. */
14879 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14881 rtx addr, reg, mem;
14883 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14884 gen_rtx_REG (Pmode, LR_REGNO));
14885 RTX_FRAME_RELATED_P (insn) = 1;
14887 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14888 GEN_INT (info->lr_save_offset + sp_offset));
14889 reg = gen_rtx_REG (Pmode, 0);
14890 mem = gen_rtx_MEM (Pmode, addr);
14891 /* This should not be of rs6000_sr_alias_set, because of
14892 __builtin_return_address. */
14894 insn = emit_move_insn (mem, reg);
14895 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14896 NULL_RTX, NULL_RTX);
14899 /* If we need to save CR, put it into r12. */
14900 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14904 cr_save_rtx = gen_rtx_REG (SImode, 12);
14905 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14906 RTX_FRAME_RELATED_P (insn) = 1;
14907 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14908 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14909 But that's OK. All we have to do is specify that _one_ condition
14910 code register is saved in this stack slot. The thrower's epilogue
14911 will then restore all the call-saved registers.
14912 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14913 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14914 gen_rtx_REG (SImode, CR2_REGNO));
14915 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14920 /* Do any required saving of fpr's. If only one or two to save, do
14921 it ourselves. Otherwise, call function. */
14922 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14925 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14926 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
14927 && ! call_used_regs[info->first_fp_reg_save+i]))
14928 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14929 info->first_fp_reg_save + i,
14930 info->fp_save_offset + sp_offset + 8 * i,
14933 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14937 const char *alloc_rname;
14939 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14941 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14942 gen_rtx_REG (Pmode,
14944 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14945 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14946 alloc_rname = ggc_strdup (rname);
14947 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14948 gen_rtx_SYMBOL_REF (Pmode,
14950 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14952 rtx addr, reg, mem;
14953 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14954 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14955 GEN_INT (info->fp_save_offset
14956 + sp_offset + 8*i));
14957 mem = gen_frame_mem (DFmode, addr);
14959 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14961 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14962 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14963 NULL_RTX, NULL_RTX);
14966 /* Save GPRs. This is done as a PARALLEL if we are using
14967 the store-multiple instructions. */
14968 if (!WORLD_SAVE_P (info) && using_store_multiple)
14972 p = rtvec_alloc (32 - info->first_gp_reg_save);
14973 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14975 rtx addr, reg, mem;
14976 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14977 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14978 GEN_INT (info->gp_save_offset
14981 mem = gen_frame_mem (reg_mode, addr);
14983 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14985 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14986 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14987 NULL_RTX, NULL_RTX);
14989 else if (!WORLD_SAVE_P (info)
14991 && info->spe_64bit_regs_used != 0
14992 && info->first_gp_reg_save != 32)
14995 rtx spe_save_area_ptr;
14996 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
14997 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
14998 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15000 /* Determine whether we can address all of the registers that need
15001 to be saved with an offset from the stack pointer that fits in
15002 the small const field for SPE memory instructions. */
15003 int spe_regs_addressable_via_sp
15004 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15005 + (32 - info->first_gp_reg_save - 1) * reg_size);
15008 if (spe_regs_addressable_via_sp)
15010 spe_save_area_ptr = sp_reg_rtx;
15011 spe_offset = info->spe_gp_save_offset + sp_offset;
15015 /* Make r11 point to the start of the SPE save area. We need
15016 to be careful here if r11 is holding the static chain. If
15017 it is, then temporarily save it in r0. We would use r0 as
15018 our base register here, but using r0 as a base register in
15019 loads and stores means something different from what we
15021 if (using_static_chain_p)
15023 rtx r0 = gen_rtx_REG (Pmode, 0);
15025 gcc_assert (info->first_gp_reg_save > 11);
15027 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15030 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15031 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15032 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15037 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15038 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15040 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15041 rtx offset, addr, mem;
15043 /* We're doing all this to ensure that the offset fits into
15044 the immediate offset of 'evstdd'. */
15045 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15047 offset = GEN_INT (reg_size * i + spe_offset);
15048 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15049 mem = gen_rtx_MEM (V2SImode, addr);
15051 insn = emit_move_insn (mem, reg);
15053 rs6000_frame_related (insn, spe_save_area_ptr,
15054 info->spe_gp_save_offset
15055 + sp_offset + reg_size * i,
15056 offset, const0_rtx);
15059 /* Move the static chain pointer back. */
15060 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15061 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15063 else if (!WORLD_SAVE_P (info))
15066 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15067 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15069 rtx addr, reg, mem;
15070 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15072 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15073 GEN_INT (info->gp_save_offset
15076 mem = gen_frame_mem (reg_mode, addr);
15078 insn = emit_move_insn (mem, reg);
15079 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15080 NULL_RTX, NULL_RTX);
15084 /* ??? There's no need to emit actual instructions here, but it's the
15085 easiest way to get the frame unwind information emitted. */
15086 if (current_function_calls_eh_return)
15088 unsigned int i, regno;
15090 /* In AIX ABI we need to pretend we save r2 here. */
15093 rtx addr, reg, mem;
15095 reg = gen_rtx_REG (reg_mode, 2);
15096 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15097 GEN_INT (sp_offset + 5 * reg_size));
15098 mem = gen_frame_mem (reg_mode, addr);
15100 insn = emit_move_insn (mem, reg);
15101 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15102 NULL_RTX, NULL_RTX);
15103 PATTERN (insn) = gen_blockage ();
15108 regno = EH_RETURN_DATA_REGNO (i);
15109 if (regno == INVALID_REGNUM)
15112 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15113 info->ehrd_offset + sp_offset
15114 + reg_size * (int) i,
15119 /* Save CR if we use any that must be preserved. */
15120 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15122 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15123 GEN_INT (info->cr_save_offset + sp_offset));
15124 rtx mem = gen_frame_mem (SImode, addr);
15125 /* See the large comment above about why CR2_REGNO is used. */
15126 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15128 /* If r12 was used to hold the original sp, copy cr into r0 now
15130 if (REGNO (frame_reg_rtx) == 12)
15134 cr_save_rtx = gen_rtx_REG (SImode, 0);
15135 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15136 RTX_FRAME_RELATED_P (insn) = 1;
15137 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15138 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15143 insn = emit_move_insn (mem, cr_save_rtx);
15145 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15146 NULL_RTX, NULL_RTX);
15149 /* Update stack and set back pointer unless this is V.4,
15150 for which it was done previously. */
15151 if (!WORLD_SAVE_P (info) && info->push_p
15152 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15154 if (info->total_size < 32767)
15155 sp_offset = info->total_size;
15157 frame_reg_rtx = frame_ptr_rtx;
15158 rs6000_emit_allocate_stack (info->total_size,
15159 (frame_reg_rtx != sp_reg_rtx
15160 && ((info->altivec_size != 0)
15161 || (info->vrsave_mask != 0)
15163 if (frame_reg_rtx != sp_reg_rtx)
15164 rs6000_emit_stack_tie ();
15167 /* Set frame pointer, if needed. */
15168 if (frame_pointer_needed)
15170 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15172 RTX_FRAME_RELATED_P (insn) = 1;
15175 /* Save AltiVec registers if needed. Save here because the red zone does
15176 not include AltiVec registers. */
15177 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15181 /* There should be a non inline version of this, for when we
15182 are saving lots of vector registers. */
15183 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15184 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15186 rtx areg, savereg, mem;
15189 offset = info->altivec_save_offset + sp_offset
15190 + 16 * (i - info->first_altivec_reg_save);
15192 savereg = gen_rtx_REG (V4SImode, i);
15194 areg = gen_rtx_REG (Pmode, 0);
15195 emit_move_insn (areg, GEN_INT (offset));
15197 /* AltiVec addressing mode is [reg+reg]. */
15198 mem = gen_frame_mem (V4SImode,
15199 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15201 insn = emit_move_insn (mem, savereg);
15203 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15204 areg, GEN_INT (offset));
15208 /* VRSAVE is a bit vector representing which AltiVec registers
15209 are used. The OS uses this to determine which vector
15210 registers to save on a context switch. We need to save
15211 VRSAVE on the stack frame, add whatever AltiVec registers we
15212 used in this function, and do the corresponding magic in the
15215 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15216 && info->vrsave_mask != 0)
15218 rtx reg, mem, vrsave;
15221 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15222 as frame_reg_rtx and r11 as the static chain pointer for
15223 nested functions. */
15224 reg = gen_rtx_REG (SImode, 0);
15225 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15227 emit_insn (gen_get_vrsave_internal (reg));
15229 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15231 if (!WORLD_SAVE_P (info))
15234 offset = info->vrsave_save_offset + sp_offset;
15235 mem = gen_frame_mem (SImode,
15236 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15237 GEN_INT (offset)));
15238 insn = emit_move_insn (mem, reg);
15241 /* Include the registers in the mask. */
15242 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15244 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15247 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15248 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15249 || (DEFAULT_ABI == ABI_V4
15250 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15251 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15253 /* If emit_load_toc_table will use the link register, we need to save
15254 it. We use R12 for this purpose because emit_load_toc_table
15255 can use register 0. This allows us to use a plain 'blr' to return
15256 from the procedure more often. */
15257 int save_LR_around_toc_setup = (TARGET_ELF
15258 && DEFAULT_ABI != ABI_AIX
15260 && ! info->lr_save_p
15261 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15262 if (save_LR_around_toc_setup)
15264 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15266 insn = emit_move_insn (frame_ptr_rtx, lr);
15267 RTX_FRAME_RELATED_P (insn) = 1;
15269 rs6000_emit_load_toc_table (TRUE);
15271 insn = emit_move_insn (lr, frame_ptr_rtx);
15272 RTX_FRAME_RELATED_P (insn) = 1;
15275 rs6000_emit_load_toc_table (TRUE);
15279 if (DEFAULT_ABI == ABI_DARWIN
15280 && flag_pic && current_function_uses_pic_offset_table)
15282 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15283 rtx src = machopic_function_base_sym ();
15285 /* Save and restore LR locally around this call (in R0). */
15286 if (!info->lr_save_p)
15287 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15289 emit_insn (gen_load_macho_picbase (src));
15291 emit_move_insn (gen_rtx_REG (Pmode,
15292 RS6000_PIC_OFFSET_TABLE_REGNUM),
15295 if (!info->lr_save_p)
15296 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15301 /* Write function prologue. */
15304 rs6000_output_function_prologue (FILE *file,
15305 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15307 rs6000_stack_t *info = rs6000_stack_info ();
15309 if (TARGET_DEBUG_STACK)
15310 debug_stack_info (info);
15312 /* Write .extern for any function we will call to save and restore
15314 if (info->first_fp_reg_save < 64
15315 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15316 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15317 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15318 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15319 RESTORE_FP_SUFFIX);
15321 /* Write .extern for AIX common mode routines, if needed. */
15322 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15324 fputs ("\t.extern __mulh\n", file);
15325 fputs ("\t.extern __mull\n", file);
15326 fputs ("\t.extern __divss\n", file);
15327 fputs ("\t.extern __divus\n", file);
15328 fputs ("\t.extern __quoss\n", file);
15329 fputs ("\t.extern __quous\n", file);
15330 common_mode_defined = 1;
15333 if (! HAVE_prologue)
15337 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15338 the "toplevel" insn chain. */
15339 emit_note (NOTE_INSN_DELETED);
15340 rs6000_emit_prologue ();
15341 emit_note (NOTE_INSN_DELETED);
15343 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15347 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15349 INSN_ADDRESSES_NEW (insn, addr);
15354 if (TARGET_DEBUG_STACK)
15355 debug_rtx_list (get_insns (), 100);
15356 final (get_insns (), file, FALSE);
15360 rs6000_pic_labelno++;
15363 /* Emit function epilogue as insns.
15365 At present, dwarf2out_frame_debug_expr doesn't understand
15366 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15367 anywhere in the epilogue. Most of the insns below would in any case
15368 need special notes to explain where r11 is in relation to the stack. */
15371 rs6000_emit_epilogue (int sibcall)
15373 rs6000_stack_t *info;
15374 int restoring_FPRs_inline;
15375 int using_load_multiple;
15376 int using_mtcr_multiple;
15377 int use_backchain_to_restore_sp;
15379 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15380 rtx frame_reg_rtx = sp_reg_rtx;
15381 enum machine_mode reg_mode = Pmode;
15382 int reg_size = TARGET_32BIT ? 4 : 8;
15385 info = rs6000_stack_info ();
15387 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15389 reg_mode = V2SImode;
15393 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15394 && (!TARGET_SPE_ABI
15395 || info->spe_64bit_regs_used == 0)
15396 && info->first_gp_reg_save < 31
15397 && no_global_regs_above (info->first_gp_reg_save));
15398 restoring_FPRs_inline = (sibcall
15399 || current_function_calls_eh_return
15400 || info->first_fp_reg_save == 64
15401 || FP_SAVE_INLINE (info->first_fp_reg_save));
15402 use_backchain_to_restore_sp = (frame_pointer_needed
15403 || current_function_calls_alloca
15404 || info->total_size > 32767);
15405 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15406 || rs6000_cpu == PROCESSOR_PPC603
15407 || rs6000_cpu == PROCESSOR_PPC750
15410 if (WORLD_SAVE_P (info))
15414 const char *alloc_rname;
15417 /* eh_rest_world_r10 will return to the location saved in the LR
15418 stack slot (which is not likely to be our caller.)
15419 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15420 rest_world is similar, except any R10 parameter is ignored.
15421 The exception-handling stuff that was here in 2.95 is no
15422 longer necessary. */
15426 + 32 - info->first_gp_reg_save
15427 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15428 + 63 + 1 - info->first_fp_reg_save);
15430 strcpy (rname, ((current_function_calls_eh_return) ?
15431 "*eh_rest_world_r10" : "*rest_world"));
15432 alloc_rname = ggc_strdup (rname);
15435 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15436 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15437 gen_rtx_REG (Pmode,
15440 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15441 /* The instruction pattern requires a clobber here;
15442 it is shared with the restVEC helper. */
15444 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
15447 /* CR register traditionally saved as CR2. */
15448 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15449 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15450 GEN_INT (info->cr_save_offset));
15451 rtx mem = gen_frame_mem (reg_mode, addr);
15453 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15456 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15458 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15459 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15460 GEN_INT (info->gp_save_offset
15462 rtx mem = gen_frame_mem (reg_mode, addr);
15464 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15466 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15468 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15469 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15470 GEN_INT (info->altivec_save_offset
15472 rtx mem = gen_frame_mem (V4SImode, addr);
15474 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15476 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
15478 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15479 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15480 GEN_INT (info->fp_save_offset
15482 rtx mem = gen_frame_mem (DFmode, addr);
15484 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
15487 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
15489 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
15491 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
15493 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
15495 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
15496 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15501 /* Set sp_offset based on the stack push from the prologue. */
15502 if (info->total_size < 32767)
15503 sp_offset = info->total_size;
15505 /* Restore AltiVec registers if needed. */
15506 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15510 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15511 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15513 rtx addr, areg, mem;
15515 areg = gen_rtx_REG (Pmode, 0);
15517 (areg, GEN_INT (info->altivec_save_offset
15519 + 16 * (i - info->first_altivec_reg_save)));
15521 /* AltiVec addressing mode is [reg+reg]. */
15522 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
15523 mem = gen_frame_mem (V4SImode, addr);
15525 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
15529 /* Restore VRSAVE if needed. */
15530 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15531 && info->vrsave_mask != 0)
15533 rtx addr, mem, reg;
15535 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15536 GEN_INT (info->vrsave_save_offset + sp_offset));
15537 mem = gen_frame_mem (SImode, addr);
15538 reg = gen_rtx_REG (SImode, 12);
15539 emit_move_insn (reg, mem);
15541 emit_insn (generate_set_vrsave (reg, info, 1));
15546 /* If we have a frame pointer, a call to alloca, or a large stack
15547 frame, restore the old stack pointer using the backchain. Otherwise,
15548 we know what size to update it with. */
15549 if (use_backchain_to_restore_sp)
15551 /* Under V.4, don't reset the stack pointer until after we're done
15552 loading the saved registers. */
15553 if (DEFAULT_ABI == ABI_V4)
15554 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
15556 emit_move_insn (frame_reg_rtx,
15557 gen_rtx_MEM (Pmode, sp_reg_rtx));
15559 else if (info->push_p)
15561 if (DEFAULT_ABI == ABI_V4
15562 || current_function_calls_eh_return)
15563 sp_offset = info->total_size;
15566 emit_insn (TARGET_32BIT
15567 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15568 GEN_INT (info->total_size))
15569 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15570 GEN_INT (info->total_size)));
15574 /* Get the old lr if we saved it. */
15575 if (info->lr_save_p)
15577 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
15578 info->lr_save_offset + sp_offset);
15580 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
15583 /* Get the old cr if we saved it. */
15584 if (info->cr_save_p)
15586 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15587 GEN_INT (info->cr_save_offset + sp_offset));
15588 rtx mem = gen_frame_mem (SImode, addr);
15590 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
15593 /* Set LR here to try to overlap restores below. */
15594 if (info->lr_save_p)
15595 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
15596 gen_rtx_REG (Pmode, 0));
15598 /* Load exception handler data registers, if needed. */
15599 if (current_function_calls_eh_return)
15601 unsigned int i, regno;
15605 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15606 GEN_INT (sp_offset + 5 * reg_size));
15607 rtx mem = gen_frame_mem (reg_mode, addr);
15609 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
15616 regno = EH_RETURN_DATA_REGNO (i);
15617 if (regno == INVALID_REGNUM)
15620 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
15621 info->ehrd_offset + sp_offset
15622 + reg_size * (int) i);
15624 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
15628 /* Restore GPRs. This is done as a PARALLEL if we are using
15629 the load-multiple instructions. */
15630 if (using_load_multiple)
15633 p = rtvec_alloc (32 - info->first_gp_reg_save);
15634 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15636 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15637 GEN_INT (info->gp_save_offset
15640 rtx mem = gen_frame_mem (reg_mode, addr);
15643 gen_rtx_SET (VOIDmode,
15644 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15647 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15649 else if (TARGET_SPE_ABI
15650 && info->spe_64bit_regs_used != 0
15651 && info->first_gp_reg_save != 32)
15653 rtx spe_save_area_ptr;
15654 /* Determine whether we can address all of the registers that need
15655 to be saved with an offset from the stack pointer that fits in
15656 the small const field for SPE memory instructions. */
15657 int spe_regs_addressable_via_sp
15658 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15659 + (32 - info->first_gp_reg_save - 1) * reg_size);
15662 if (spe_regs_addressable_via_sp)
15664 spe_save_area_ptr = frame_reg_rtx;
15665 spe_offset = info->spe_gp_save_offset + sp_offset;
15669 /* Make r11 point to the start of the SPE save area. We worried about
15670 not clobbering it when we were saving registers in the prologue.
15671 There's no need to worry here because the static chain is passed
15672 anew to every function. */
15673 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15675 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
15676 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15681 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15682 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15684 rtx offset, addr, mem;
15686 /* We're doing all this to ensure that the immediate offset
15687 fits into the immediate field of 'evldd'. */
15688 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
15690 offset = GEN_INT (spe_offset + reg_size * i);
15691 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15692 mem = gen_rtx_MEM (V2SImode, addr);
15694 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
15699 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15700 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15702 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15703 GEN_INT (info->gp_save_offset
15706 rtx mem = gen_frame_mem (reg_mode, addr);
15708 emit_move_insn (gen_rtx_REG (reg_mode,
15709 info->first_gp_reg_save + i), mem);
15712 /* Restore fpr's if we need to do it without calling a function. */
15713 if (restoring_FPRs_inline)
15714 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15715 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15716 && ! call_used_regs[info->first_fp_reg_save+i]))
15719 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15720 GEN_INT (info->fp_save_offset
15723 mem = gen_frame_mem (DFmode, addr);
15725 emit_move_insn (gen_rtx_REG (DFmode,
15726 info->first_fp_reg_save + i),
15730 /* If we saved cr, restore it here. Just those that were used. */
15731 if (info->cr_save_p)
15733 rtx r12_rtx = gen_rtx_REG (SImode, 12);
15736 if (using_mtcr_multiple)
15738 for (i = 0; i < 8; i++)
15739 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15741 gcc_assert (count);
15744 if (using_mtcr_multiple && count > 1)
15749 p = rtvec_alloc (count);
15752 for (i = 0; i < 8; i++)
15753 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15755 rtvec r = rtvec_alloc (2);
15756 RTVEC_ELT (r, 0) = r12_rtx;
15757 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
15758 RTVEC_ELT (p, ndx) =
15759 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
15760 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
15763 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15764 gcc_assert (ndx == count);
15767 for (i = 0; i < 8; i++)
15768 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
15770 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
15776 /* If this is V.4, unwind the stack pointer after all of the loads
15778 if (frame_reg_rtx != sp_reg_rtx)
15780 /* This blockage is needed so that sched doesn't decide to move
15781 the sp change before the register restores. */
15782 rs6000_emit_stack_tie ();
15784 && info->spe_64bit_regs_used != 0
15785 && info->first_gp_reg_save != 32)
15786 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
15787 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
15789 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
15791 else if (sp_offset != 0)
15792 emit_insn (TARGET_32BIT
15793 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
15794 GEN_INT (sp_offset))
15795 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
15796 GEN_INT (sp_offset)));
15798 if (current_function_calls_eh_return)
15800 rtx sa = EH_RETURN_STACKADJ_RTX;
15801 emit_insn (TARGET_32BIT
15802 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
15803 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
15809 if (! restoring_FPRs_inline)
15810 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
15812 p = rtvec_alloc (2);
15814 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15815 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15816 gen_rtx_REG (Pmode,
15819 /* If we have to restore more than two FP registers, branch to the
15820 restore function. It will return to our caller. */
15821 if (! restoring_FPRs_inline)
15825 const char *alloc_rname;
15827 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15828 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15829 alloc_rname = ggc_strdup (rname);
15830 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15831 gen_rtx_SYMBOL_REF (Pmode,
15834 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15837 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15838 GEN_INT (info->fp_save_offset + 8*i));
15839 mem = gen_frame_mem (DFmode, addr);
15841 RTVEC_ELT (p, i+3) =
15842 gen_rtx_SET (VOIDmode,
15843 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15848 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15852 /* Write function epilogue. */
15855 rs6000_output_function_epilogue (FILE *file,
15856 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15858 if (! HAVE_epilogue)
15860 rtx insn = get_last_insn ();
15861 /* If the last insn was a BARRIER, we don't have to write anything except
15862 the trace table. */
15863 if (GET_CODE (insn) == NOTE)
15864 insn = prev_nonnote_insn (insn);
15865 if (insn == 0 || GET_CODE (insn) != BARRIER)
15867 /* This is slightly ugly, but at least we don't have two
15868 copies of the epilogue-emitting code. */
15871 /* A NOTE_INSN_DELETED is supposed to be at the start
15872 and end of the "toplevel" insn chain. */
15873 emit_note (NOTE_INSN_DELETED);
15874 rs6000_emit_epilogue (FALSE);
15875 emit_note (NOTE_INSN_DELETED);
15877 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15881 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15883 INSN_ADDRESSES_NEW (insn, addr);
15888 if (TARGET_DEBUG_STACK)
15889 debug_rtx_list (get_insns (), 100);
15890 final (get_insns (), file, FALSE);
15896 macho_branch_islands ();
15897 /* Mach-O doesn't support labels at the end of objects, so if
15898 it looks like we might want one, insert a NOP. */
15900 rtx insn = get_last_insn ();
15903 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
15904 insn = PREV_INSN (insn);
15908 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
15909 fputs ("\tnop\n", file);
15913 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15916 We don't output a traceback table if -finhibit-size-directive was
15917 used. The documentation for -finhibit-size-directive reads
15918 ``don't output a @code{.size} assembler directive, or anything
15919 else that would cause trouble if the function is split in the
15920 middle, and the two halves are placed at locations far apart in
15921 memory.'' The traceback table has this property, since it
15922 includes the offset from the start of the function to the
15923 traceback table itself.
15925 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15926 different traceback table. */
15927 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15928 && rs6000_traceback != traceback_none && !current_function_is_thunk)
15930 const char *fname = NULL;
15931 const char *language_string = lang_hooks.name;
15932 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15934 int optional_tbtab;
15935 rs6000_stack_t *info = rs6000_stack_info ();
15937 if (rs6000_traceback == traceback_full)
15938 optional_tbtab = 1;
15939 else if (rs6000_traceback == traceback_part)
15940 optional_tbtab = 0;
15942 optional_tbtab = !optimize_size && !TARGET_ELF;
15944 if (optional_tbtab)
15946 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15947 while (*fname == '.') /* V.4 encodes . in the name */
15950 /* Need label immediately before tbtab, so we can compute
15951 its offset from the function start. */
15952 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15953 ASM_OUTPUT_LABEL (file, fname);
15956 /* The .tbtab pseudo-op can only be used for the first eight
15957 expressions, since it can't handle the possibly variable
15958 length fields that follow. However, if you omit the optional
15959 fields, the assembler outputs zeros for all optional fields
15960 anyways, giving each variable length field is minimum length
15961 (as defined in sys/debug.h). Thus we can not use the .tbtab
15962 pseudo-op at all. */
15964 /* An all-zero word flags the start of the tbtab, for debuggers
15965 that have to find it by searching forward from the entry
15966 point or from the current pc. */
15967 fputs ("\t.long 0\n", file);
15969 /* Tbtab format type. Use format type 0. */
15970 fputs ("\t.byte 0,", file);
15972 /* Language type. Unfortunately, there does not seem to be any
15973 official way to discover the language being compiled, so we
15974 use language_string.
15975 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15976 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
15977 a number, so for now use 9. */
15978 if (! strcmp (language_string, "GNU C"))
15980 else if (! strcmp (language_string, "GNU F77")
15981 || ! strcmp (language_string, "GNU F95"))
15983 else if (! strcmp (language_string, "GNU Pascal"))
15985 else if (! strcmp (language_string, "GNU Ada"))
15987 else if (! strcmp (language_string, "GNU C++")
15988 || ! strcmp (language_string, "GNU Objective-C++"))
15990 else if (! strcmp (language_string, "GNU Java"))
15992 else if (! strcmp (language_string, "GNU Objective-C"))
15995 gcc_unreachable ();
15996 fprintf (file, "%d,", i);
15998 /* 8 single bit fields: global linkage (not set for C extern linkage,
15999 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16000 from start of procedure stored in tbtab, internal function, function
16001 has controlled storage, function has no toc, function uses fp,
16002 function logs/aborts fp operations. */
16003 /* Assume that fp operations are used if any fp reg must be saved. */
16004 fprintf (file, "%d,",
16005 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16007 /* 6 bitfields: function is interrupt handler, name present in
16008 proc table, function calls alloca, on condition directives
16009 (controls stack walks, 3 bits), saves condition reg, saves
16011 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16012 set up as a frame pointer, even when there is no alloca call. */
16013 fprintf (file, "%d,",
16014 ((optional_tbtab << 6)
16015 | ((optional_tbtab & frame_pointer_needed) << 5)
16016 | (info->cr_save_p << 1)
16017 | (info->lr_save_p)));
16019 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16021 fprintf (file, "%d,",
16022 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16024 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16025 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16027 if (optional_tbtab)
16029 /* Compute the parameter info from the function decl argument
16032 int next_parm_info_bit = 31;
16034 for (decl = DECL_ARGUMENTS (current_function_decl);
16035 decl; decl = TREE_CHAIN (decl))
16037 rtx parameter = DECL_INCOMING_RTL (decl);
16038 enum machine_mode mode = GET_MODE (parameter);
16040 if (GET_CODE (parameter) == REG)
16042 if (SCALAR_FLOAT_MODE_P (mode))
16062 gcc_unreachable ();
16065 /* If only one bit will fit, don't or in this entry. */
16066 if (next_parm_info_bit > 0)
16067 parm_info |= (bits << (next_parm_info_bit - 1));
16068 next_parm_info_bit -= 2;
16072 fixed_parms += ((GET_MODE_SIZE (mode)
16073 + (UNITS_PER_WORD - 1))
16075 next_parm_info_bit -= 1;
16081 /* Number of fixed point parameters. */
16082 /* This is actually the number of words of fixed point parameters; thus
16083 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16084 fprintf (file, "%d,", fixed_parms);
16086 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16088 /* This is actually the number of fp registers that hold parameters;
16089 and thus the maximum value is 13. */
16090 /* Set parameters on stack bit if parameters are not in their original
16091 registers, regardless of whether they are on the stack? Xlc
16092 seems to set the bit when not optimizing. */
16093 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16095 if (! optional_tbtab)
16098 /* Optional fields follow. Some are variable length. */
16100 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16101 11 double float. */
16102 /* There is an entry for each parameter in a register, in the order that
16103 they occur in the parameter list. Any intervening arguments on the
16104 stack are ignored. If the list overflows a long (max possible length
16105 34 bits) then completely leave off all elements that don't fit. */
16106 /* Only emit this long if there was at least one parameter. */
16107 if (fixed_parms || float_parms)
16108 fprintf (file, "\t.long %d\n", parm_info);
16110 /* Offset from start of code to tb table. */
16111 fputs ("\t.long ", file);
16112 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16114 RS6000_OUTPUT_BASENAME (file, fname);
16116 assemble_name (file, fname);
16118 rs6000_output_function_entry (file, fname);
16121 /* Interrupt handler mask. */
16122 /* Omit this long, since we never set the interrupt handler bit
16125 /* Number of CTL (controlled storage) anchors. */
16126 /* Omit this long, since the has_ctl bit is never set above. */
16128 /* Displacement into stack of each CTL anchor. */
16129 /* Omit this list of longs, because there are no CTL anchors. */
16131 /* Length of function name. */
16134 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16136 /* Function name. */
16137 assemble_string (fname, strlen (fname));
16139 /* Register for alloca automatic storage; this is always reg 31.
16140 Only emit this if the alloca bit was set above. */
16141 if (frame_pointer_needed)
16142 fputs ("\t.byte 31\n", file);
16144 fputs ("\t.align 2\n", file);
16148 /* A C compound statement that outputs the assembler code for a thunk
16149 function, used to implement C++ virtual function calls with
16150 multiple inheritance. The thunk acts as a wrapper around a virtual
16151 function, adjusting the implicit object parameter before handing
16152 control off to the real function.
16154 First, emit code to add the integer DELTA to the location that
16155 contains the incoming first argument. Assume that this argument
16156 contains a pointer, and is the one used to pass the `this' pointer
16157 in C++. This is the incoming argument *before* the function
16158 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16159 values of all other incoming arguments.
16161 After the addition, emit code to jump to FUNCTION, which is a
16162 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16163 not touch the return address. Hence returning from FUNCTION will
16164 return to whoever called the current `thunk'.
16166 The effect must be as if FUNCTION had been called directly with the
16167 adjusted first argument. This macro is responsible for emitting
16168 all of the code for a thunk function; output_function_prologue()
16169 and output_function_epilogue() are not invoked.
16171 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16172 been extracted from it.) It might possibly be useful on some
16173 targets, but probably not.
16175 If you do not define this macro, the target-independent code in the
16176 C++ frontend will generate a less efficient heavyweight thunk that
16177 calls FUNCTION instead of jumping to it. The generic approach does
16178 not support varargs. */
16181 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16182 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16185 rtx this, insn, funexp;
16187 reload_completed = 1;
16188 epilogue_completed = 1;
16190 /* Mark the end of the (empty) prologue. */
16191 emit_note (NOTE_INSN_PROLOGUE_END);
16193 /* Find the "this" pointer. If the function returns a structure,
16194 the structure return pointer is in r3. */
16195 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16196 this = gen_rtx_REG (Pmode, 4);
16198 this = gen_rtx_REG (Pmode, 3);
16200 /* Apply the constant offset, if required. */
16203 rtx delta_rtx = GEN_INT (delta);
16204 emit_insn (TARGET_32BIT
16205 ? gen_addsi3 (this, this, delta_rtx)
16206 : gen_adddi3 (this, this, delta_rtx));
16209 /* Apply the offset from the vtable, if required. */
16212 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16213 rtx tmp = gen_rtx_REG (Pmode, 12);
16215 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16216 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16218 emit_insn (TARGET_32BIT
16219 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16220 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16221 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16225 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16227 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16229 emit_insn (TARGET_32BIT
16230 ? gen_addsi3 (this, this, tmp)
16231 : gen_adddi3 (this, this, tmp));
16234 /* Generate a tail call to the target function. */
16235 if (!TREE_USED (function))
16237 assemble_external (function);
16238 TREE_USED (function) = 1;
16240 funexp = XEXP (DECL_RTL (function), 0);
16241 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16244 if (MACHOPIC_INDIRECT)
16245 funexp = machopic_indirect_call_target (funexp);
16248 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16249 generate sibcall RTL explicitly. */
16250 insn = emit_call_insn (
16251 gen_rtx_PARALLEL (VOIDmode,
16253 gen_rtx_CALL (VOIDmode,
16254 funexp, const0_rtx),
16255 gen_rtx_USE (VOIDmode, const0_rtx),
16256 gen_rtx_USE (VOIDmode,
16257 gen_rtx_REG (SImode,
16259 gen_rtx_RETURN (VOIDmode))));
16260 SIBLING_CALL_P (insn) = 1;
16263 /* Run just enough of rest_of_compilation to get the insns emitted.
16264 There's not really enough bulk here to make other passes such as
16265 instruction scheduling worth while. Note that use_thunk calls
16266 assemble_start_function and assemble_end_function. */
16267 insn = get_insns ();
16268 insn_locators_alloc ();
16269 shorten_branches (insn);
16270 final_start_function (insn, file, 1);
16271 final (insn, file, 1);
16272 final_end_function ();
16274 reload_completed = 0;
16275 epilogue_completed = 0;
16278 /* A quick summary of the various types of 'constant-pool tables'
16281 Target Flags Name One table per
16282 AIX (none) AIX TOC object file
16283 AIX -mfull-toc AIX TOC object file
16284 AIX -mminimal-toc AIX minimal TOC translation unit
16285 SVR4/EABI (none) SVR4 SDATA object file
16286 SVR4/EABI -fpic SVR4 pic object file
16287 SVR4/EABI -fPIC SVR4 PIC translation unit
16288 SVR4/EABI -mrelocatable EABI TOC function
16289 SVR4/EABI -maix AIX TOC object file
16290 SVR4/EABI -maix -mminimal-toc
16291 AIX minimal TOC translation unit
16293 Name Reg. Set by entries contains:
16294 made by addrs? fp? sum?
16296 AIX TOC 2 crt0 as Y option option
16297 AIX minimal TOC 30 prolog gcc Y Y option
16298 SVR4 SDATA 13 crt0 gcc N Y N
16299 SVR4 pic 30 prolog ld Y not yet N
16300 SVR4 PIC 30 prolog gcc Y option option
16301 EABI TOC 30 prolog gcc Y option option
16305 /* Hash functions for the hash table. */
16308 rs6000_hash_constant (rtx k)
16310 enum rtx_code code = GET_CODE (k);
16311 enum machine_mode mode = GET_MODE (k);
16312 unsigned result = (code << 3) ^ mode;
16313 const char *format;
16316 format = GET_RTX_FORMAT (code);
16317 flen = strlen (format);
16323 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16326 if (mode != VOIDmode)
16327 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16339 for (; fidx < flen; fidx++)
16340 switch (format[fidx])
16345 const char *str = XSTR (k, fidx);
16346 len = strlen (str);
16347 result = result * 613 + len;
16348 for (i = 0; i < len; i++)
16349 result = result * 613 + (unsigned) str[i];
16354 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16358 result = result * 613 + (unsigned) XINT (k, fidx);
16361 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16362 result = result * 613 + (unsigned) XWINT (k, fidx);
16366 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16367 result = result * 613 + (unsigned) (XWINT (k, fidx)
16374 gcc_unreachable ();
16381 toc_hash_function (const void *hash_entry)
16383 const struct toc_hash_struct *thc =
16384 (const struct toc_hash_struct *) hash_entry;
16385 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16388 /* Compare H1 and H2 for equivalence. */
16391 toc_hash_eq (const void *h1, const void *h2)
16393 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16394 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16396 if (((const struct toc_hash_struct *) h1)->key_mode
16397 != ((const struct toc_hash_struct *) h2)->key_mode)
16400 return rtx_equal_p (r1, r2);
16403 /* These are the names given by the C++ front-end to vtables, and
16404 vtable-like objects. Ideally, this logic should not be here;
16405 instead, there should be some programmatic way of inquiring as
16406 to whether or not an object is a vtable. */
16408 #define VTABLE_NAME_P(NAME) \
16409 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16410 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16411 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16412 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16413 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16416 rs6000_output_symbol_ref (FILE *file, rtx x)
16418 /* Currently C++ toc references to vtables can be emitted before it
16419 is decided whether the vtable is public or private. If this is
16420 the case, then the linker will eventually complain that there is
16421 a reference to an unknown section. Thus, for vtables only,
16422 we emit the TOC reference to reference the symbol and not the
16424 const char *name = XSTR (x, 0);
16426 if (VTABLE_NAME_P (name))
16428 RS6000_OUTPUT_BASENAME (file, name);
16431 assemble_name (file, name);
16434 /* Output a TOC entry. We derive the entry name from what is being
16438 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16441 const char *name = buf;
16442 const char *real_name;
16444 HOST_WIDE_INT offset = 0;
16446 gcc_assert (!TARGET_NO_TOC);
16448 /* When the linker won't eliminate them, don't output duplicate
16449 TOC entries (this happens on AIX if there is any kind of TOC,
16450 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
16452 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
16454 struct toc_hash_struct *h;
16457 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
16458 time because GGC is not initialized at that point. */
16459 if (toc_hash_table == NULL)
16460 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
16461 toc_hash_eq, NULL);
16463 h = ggc_alloc (sizeof (*h));
16465 h->key_mode = mode;
16466 h->labelno = labelno;
16468 found = htab_find_slot (toc_hash_table, h, 1);
16469 if (*found == NULL)
16471 else /* This is indeed a duplicate.
16472 Set this label equal to that label. */
16474 fputs ("\t.set ", file);
16475 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16476 fprintf (file, "%d,", labelno);
16477 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
16478 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
16484 /* If we're going to put a double constant in the TOC, make sure it's
16485 aligned properly when strict alignment is on. */
16486 if (GET_CODE (x) == CONST_DOUBLE
16487 && STRICT_ALIGNMENT
16488 && GET_MODE_BITSIZE (mode) >= 64
16489 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
16490 ASM_OUTPUT_ALIGN (file, 3);
16493 (*targetm.asm_out.internal_label) (file, "LC", labelno);
16495 /* Handle FP constants specially. Note that if we have a minimal
16496 TOC, things we put here aren't actually in the TOC, so we can allow
16498 if (GET_CODE (x) == CONST_DOUBLE &&
16499 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
16501 REAL_VALUE_TYPE rv;
16504 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16505 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16506 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
16508 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
16512 if (TARGET_MINIMAL_TOC)
16513 fputs (DOUBLE_INT_ASM_OP, file);
16515 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16516 k[0] & 0xffffffff, k[1] & 0xffffffff,
16517 k[2] & 0xffffffff, k[3] & 0xffffffff);
16518 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
16519 k[0] & 0xffffffff, k[1] & 0xffffffff,
16520 k[2] & 0xffffffff, k[3] & 0xffffffff);
16525 if (TARGET_MINIMAL_TOC)
16526 fputs ("\t.long ", file);
16528 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
16529 k[0] & 0xffffffff, k[1] & 0xffffffff,
16530 k[2] & 0xffffffff, k[3] & 0xffffffff);
16531 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
16532 k[0] & 0xffffffff, k[1] & 0xffffffff,
16533 k[2] & 0xffffffff, k[3] & 0xffffffff);
16537 else if (GET_CODE (x) == CONST_DOUBLE &&
16538 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
16540 REAL_VALUE_TYPE rv;
16543 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16545 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16546 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
16548 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
16552 if (TARGET_MINIMAL_TOC)
16553 fputs (DOUBLE_INT_ASM_OP, file);
16555 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16556 k[0] & 0xffffffff, k[1] & 0xffffffff);
16557 fprintf (file, "0x%lx%08lx\n",
16558 k[0] & 0xffffffff, k[1] & 0xffffffff);
16563 if (TARGET_MINIMAL_TOC)
16564 fputs ("\t.long ", file);
16566 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
16567 k[0] & 0xffffffff, k[1] & 0xffffffff);
16568 fprintf (file, "0x%lx,0x%lx\n",
16569 k[0] & 0xffffffff, k[1] & 0xffffffff);
16573 else if (GET_CODE (x) == CONST_DOUBLE &&
16574 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
16576 REAL_VALUE_TYPE rv;
16579 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
16580 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
16581 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
16583 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
16587 if (TARGET_MINIMAL_TOC)
16588 fputs (DOUBLE_INT_ASM_OP, file);
16590 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16591 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
16596 if (TARGET_MINIMAL_TOC)
16597 fputs ("\t.long ", file);
16599 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
16600 fprintf (file, "0x%lx\n", l & 0xffffffff);
16604 else if (GET_MODE (x) == VOIDmode
16605 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
16607 unsigned HOST_WIDE_INT low;
16608 HOST_WIDE_INT high;
16610 if (GET_CODE (x) == CONST_DOUBLE)
16612 low = CONST_DOUBLE_LOW (x);
16613 high = CONST_DOUBLE_HIGH (x);
16616 #if HOST_BITS_PER_WIDE_INT == 32
16619 high = (low & 0x80000000) ? ~0 : 0;
16623 low = INTVAL (x) & 0xffffffff;
16624 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
16628 /* TOC entries are always Pmode-sized, but since this
16629 is a bigendian machine then if we're putting smaller
16630 integer constants in the TOC we have to pad them.
16631 (This is still a win over putting the constants in
16632 a separate constant pool, because then we'd have
16633 to have both a TOC entry _and_ the actual constant.)
16635 For a 32-bit target, CONST_INT values are loaded and shifted
16636 entirely within `low' and can be stored in one TOC entry. */
16638 /* It would be easy to make this work, but it doesn't now. */
16639 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
16641 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
16643 #if HOST_BITS_PER_WIDE_INT == 32
16644 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
16645 POINTER_SIZE, &low, &high, 0);
16648 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
16649 high = (HOST_WIDE_INT) low >> 32;
16656 if (TARGET_MINIMAL_TOC)
16657 fputs (DOUBLE_INT_ASM_OP, file);
16659 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16660 (long) high & 0xffffffff, (long) low & 0xffffffff);
16661 fprintf (file, "0x%lx%08lx\n",
16662 (long) high & 0xffffffff, (long) low & 0xffffffff);
16667 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
16669 if (TARGET_MINIMAL_TOC)
16670 fputs ("\t.long ", file);
16672 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
16673 (long) high & 0xffffffff, (long) low & 0xffffffff);
16674 fprintf (file, "0x%lx,0x%lx\n",
16675 (long) high & 0xffffffff, (long) low & 0xffffffff);
16679 if (TARGET_MINIMAL_TOC)
16680 fputs ("\t.long ", file);
16682 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
16683 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
16689 if (GET_CODE (x) == CONST)
16691 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
16693 base = XEXP (XEXP (x, 0), 0);
16694 offset = INTVAL (XEXP (XEXP (x, 0), 1));
16697 switch (GET_CODE (base))
16700 name = XSTR (base, 0);
16704 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
16705 CODE_LABEL_NUMBER (XEXP (base, 0)));
16709 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
16713 gcc_unreachable ();
16716 real_name = (*targetm.strip_name_encoding) (name);
16717 if (TARGET_MINIMAL_TOC)
16718 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
16721 fprintf (file, "\t.tc %s", real_name);
16724 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
16726 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
16728 fputs ("[TC],", file);
16731 /* Currently C++ toc references to vtables can be emitted before it
16732 is decided whether the vtable is public or private. If this is
16733 the case, then the linker will eventually complain that there is
16734 a TOC reference to an unknown section. Thus, for vtables only,
16735 we emit the TOC reference to reference the symbol and not the
16737 if (VTABLE_NAME_P (name))
16739 RS6000_OUTPUT_BASENAME (file, name);
16741 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
16742 else if (offset > 0)
16743 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
16746 output_addr_const (file, x);
16750 /* Output an assembler pseudo-op to write an ASCII string of N characters
16751 starting at P to FILE.
16753 On the RS/6000, we have to do this using the .byte operation and
16754 write out special characters outside the quoted string.
16755 Also, the assembler is broken; very long strings are truncated,
16756 so we must artificially break them up early. */
16759 output_ascii (FILE *file, const char *p, int n)
16762 int i, count_string;
16763 const char *for_string = "\t.byte \"";
16764 const char *for_decimal = "\t.byte ";
16765 const char *to_close = NULL;
16768 for (i = 0; i < n; i++)
16771 if (c >= ' ' && c < 0177)
16774 fputs (for_string, file);
16777 /* Write two quotes to get one. */
16785 for_decimal = "\"\n\t.byte ";
16789 if (count_string >= 512)
16791 fputs (to_close, file);
16793 for_string = "\t.byte \"";
16794 for_decimal = "\t.byte ";
16802 fputs (for_decimal, file);
16803 fprintf (file, "%d", c);
16805 for_string = "\n\t.byte \"";
16806 for_decimal = ", ";
16812 /* Now close the string if we have written one. Then end the line. */
16814 fputs (to_close, file);
16817 /* Generate a unique section name for FILENAME for a section type
16818 represented by SECTION_DESC. Output goes into BUF.
16820 SECTION_DESC can be any string, as long as it is different for each
16821 possible section type.
16823 We name the section in the same manner as xlc. The name begins with an
16824 underscore followed by the filename (after stripping any leading directory
16825 names) with the last period replaced by the string SECTION_DESC. If
16826 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16830 rs6000_gen_section_name (char **buf, const char *filename,
16831 const char *section_desc)
16833 const char *q, *after_last_slash, *last_period = 0;
16837 after_last_slash = filename;
16838 for (q = filename; *q; q++)
16841 after_last_slash = q + 1;
16842 else if (*q == '.')
16846 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16847 *buf = (char *) xmalloc (len);
16852 for (q = after_last_slash; *q; q++)
16854 if (q == last_period)
16856 strcpy (p, section_desc);
16857 p += strlen (section_desc);
16861 else if (ISALNUM (*q))
16865 if (last_period == 0)
16866 strcpy (p, section_desc);
16871 /* Emit profile function. */
16874 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16876 /* Non-standard profiling for kernels, which just saves LR then calls
16877 _mcount without worrying about arg saves. The idea is to change
16878 the function prologue as little as possible as it isn't easy to
16879 account for arg save/restore code added just for _mcount. */
16880 if (TARGET_PROFILE_KERNEL)
16883 if (DEFAULT_ABI == ABI_AIX)
16885 #ifndef NO_PROFILE_COUNTERS
16886 # define NO_PROFILE_COUNTERS 0
16888 if (NO_PROFILE_COUNTERS)
16889 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16893 const char *label_name;
16896 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16897 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16898 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16900 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16904 else if (DEFAULT_ABI == ABI_DARWIN)
16906 const char *mcount_name = RS6000_MCOUNT;
16907 int caller_addr_regno = LR_REGNO;
16909 /* Be conservative and always set this, at least for now. */
16910 current_function_uses_pic_offset_table = 1;
16913 /* For PIC code, set up a stub and collect the caller's address
16914 from r0, which is where the prologue puts it. */
16915 if (MACHOPIC_INDIRECT
16916 && current_function_uses_pic_offset_table)
16917 caller_addr_regno = 0;
16919 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16921 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16925 /* Write function profiler code. */
16928 output_function_profiler (FILE *file, int labelno)
16932 switch (DEFAULT_ABI)
16935 gcc_unreachable ();
16940 warning (0, "no profiling of 64-bit code for this ABI");
16943 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16944 fprintf (file, "\tmflr %s\n", reg_names[0]);
16945 if (NO_PROFILE_COUNTERS)
16947 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16948 reg_names[0], reg_names[1]);
16950 else if (TARGET_SECURE_PLT && flag_pic)
16952 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16953 reg_names[0], reg_names[1]);
16954 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16955 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16956 reg_names[12], reg_names[12]);
16957 assemble_name (file, buf);
16958 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16959 assemble_name (file, buf);
16960 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16962 else if (flag_pic == 1)
16964 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16965 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16966 reg_names[0], reg_names[1]);
16967 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16968 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16969 assemble_name (file, buf);
16970 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16972 else if (flag_pic > 1)
16974 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16975 reg_names[0], reg_names[1]);
16976 /* Now, we need to get the address of the label. */
16977 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16978 assemble_name (file, buf);
16979 fputs ("-.\n1:", file);
16980 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16981 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16982 reg_names[0], reg_names[11]);
16983 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16984 reg_names[0], reg_names[0], reg_names[11]);
16988 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16989 assemble_name (file, buf);
16990 fputs ("@ha\n", file);
16991 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16992 reg_names[0], reg_names[1]);
16993 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16994 assemble_name (file, buf);
16995 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16998 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16999 fprintf (file, "\tbl %s%s\n",
17000 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17005 if (!TARGET_PROFILE_KERNEL)
17007 /* Don't do anything, done in output_profile_hook (). */
17011 gcc_assert (!TARGET_32BIT);
17013 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17014 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17016 if (cfun->static_chain_decl != NULL)
17018 asm_fprintf (file, "\tstd %s,24(%s)\n",
17019 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17020 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17021 asm_fprintf (file, "\tld %s,24(%s)\n",
17022 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17025 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17033 /* The following variable value is the last issued insn. */
17035 static rtx last_scheduled_insn;
17037 /* The following variable helps to balance issuing of load and
17038 store instructions */
17040 static int load_store_pendulum;
17042 /* Power4 load update and store update instructions are cracked into a
17043 load or store and an integer insn which are executed in the same cycle.
17044 Branches have their own dispatch slot which does not count against the
17045 GCC issue rate, but it changes the program flow so there are no other
17046 instructions to issue in this cycle. */
17049 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17050 int verbose ATTRIBUTE_UNUSED,
17051 rtx insn, int more)
17053 last_scheduled_insn = insn;
17054 if (GET_CODE (PATTERN (insn)) == USE
17055 || GET_CODE (PATTERN (insn)) == CLOBBER)
17057 cached_can_issue_more = more;
17058 return cached_can_issue_more;
17061 if (insn_terminates_group_p (insn, current_group))
17063 cached_can_issue_more = 0;
17064 return cached_can_issue_more;
17067 /* If no reservation, but reach here */
17068 if (recog_memoized (insn) < 0)
17071 if (rs6000_sched_groups)
17073 if (is_microcoded_insn (insn))
17074 cached_can_issue_more = 0;
17075 else if (is_cracked_insn (insn))
17076 cached_can_issue_more = more > 2 ? more - 2 : 0;
17078 cached_can_issue_more = more - 1;
17080 return cached_can_issue_more;
17083 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17086 cached_can_issue_more = more - 1;
17087 return cached_can_issue_more;
17090 /* Adjust the cost of a scheduling dependency. Return the new cost of
17091 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17094 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17096 enum attr_type attr_type;
17098 if (! recog_memoized (insn))
17101 switch (REG_NOTE_KIND (link))
17105 /* Data dependency; DEP_INSN writes a register that INSN reads
17106 some cycles later. */
17108 /* Separate a load from a narrower, dependent store. */
17109 if (rs6000_sched_groups
17110 && GET_CODE (PATTERN (insn)) == SET
17111 && GET_CODE (PATTERN (dep_insn)) == SET
17112 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17113 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17114 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17115 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17118 attr_type = get_attr_type (insn);
17123 /* Tell the first scheduling pass about the latency between
17124 a mtctr and bctr (and mtlr and br/blr). The first
17125 scheduling pass will not know about this latency since
17126 the mtctr instruction, which has the latency associated
17127 to it, will be generated by reload. */
17128 return TARGET_POWER ? 5 : 4;
17130 /* Leave some extra cycles between a compare and its
17131 dependent branch, to inhibit expensive mispredicts. */
17132 if ((rs6000_cpu_attr == CPU_PPC603
17133 || rs6000_cpu_attr == CPU_PPC604
17134 || rs6000_cpu_attr == CPU_PPC604E
17135 || rs6000_cpu_attr == CPU_PPC620
17136 || rs6000_cpu_attr == CPU_PPC630
17137 || rs6000_cpu_attr == CPU_PPC750
17138 || rs6000_cpu_attr == CPU_PPC7400
17139 || rs6000_cpu_attr == CPU_PPC7450
17140 || rs6000_cpu_attr == CPU_POWER4
17141 || rs6000_cpu_attr == CPU_POWER5
17142 || rs6000_cpu_attr == CPU_CELL)
17143 && recog_memoized (dep_insn)
17144 && (INSN_CODE (dep_insn) >= 0))
17146 switch (get_attr_type (dep_insn))
17150 case TYPE_DELAYED_COMPARE:
17151 case TYPE_IMUL_COMPARE:
17152 case TYPE_LMUL_COMPARE:
17153 case TYPE_FPCOMPARE:
17154 case TYPE_CR_LOGICAL:
17155 case TYPE_DELAYED_CR:
17164 case TYPE_STORE_UX:
17166 case TYPE_FPSTORE_U:
17167 case TYPE_FPSTORE_UX:
17168 if ((rs6000_cpu == PROCESSOR_POWER6)
17169 && recog_memoized (dep_insn)
17170 && (INSN_CODE (dep_insn) >= 0))
17173 if (GET_CODE (PATTERN (insn)) != SET)
17174 /* If this happens, we have to extend this to schedule
17175 optimally. Return default for now. */
17178 /* Adjust the cost for the case where the value written
17179 by a fixed point operation is used as the address
17180 gen value on a store. */
17181 switch (get_attr_type (dep_insn))
17188 if (! store_data_bypass_p (dep_insn, insn))
17192 case TYPE_LOAD_EXT:
17193 case TYPE_LOAD_EXT_U:
17194 case TYPE_LOAD_EXT_UX:
17195 case TYPE_VAR_SHIFT_ROTATE:
17196 case TYPE_VAR_DELAYED_COMPARE:
17198 if (! store_data_bypass_p (dep_insn, insn))
17204 case TYPE_FAST_COMPARE:
17207 case TYPE_INSERT_WORD:
17208 case TYPE_INSERT_DWORD:
17209 case TYPE_FPLOAD_U:
17210 case TYPE_FPLOAD_UX:
17212 case TYPE_STORE_UX:
17213 case TYPE_FPSTORE_U:
17214 case TYPE_FPSTORE_UX:
17216 if (! store_data_bypass_p (dep_insn, insn))
17224 case TYPE_IMUL_COMPARE:
17225 case TYPE_LMUL_COMPARE:
17227 if (! store_data_bypass_p (dep_insn, insn))
17233 if (! store_data_bypass_p (dep_insn, insn))
17239 if (! store_data_bypass_p (dep_insn, insn))
17252 case TYPE_LOAD_EXT:
17253 case TYPE_LOAD_EXT_U:
17254 case TYPE_LOAD_EXT_UX:
17255 if ((rs6000_cpu == PROCESSOR_POWER6)
17256 && recog_memoized (dep_insn)
17257 && (INSN_CODE (dep_insn) >= 0))
17260 /* Adjust the cost for the case where the value written
17261 by a fixed point instruction is used within the address
17262 gen portion of a subsequent load(u)(x) */
17263 switch (get_attr_type (dep_insn))
17270 if (set_to_load_agen (dep_insn, insn))
17274 case TYPE_LOAD_EXT:
17275 case TYPE_LOAD_EXT_U:
17276 case TYPE_LOAD_EXT_UX:
17277 case TYPE_VAR_SHIFT_ROTATE:
17278 case TYPE_VAR_DELAYED_COMPARE:
17280 if (set_to_load_agen (dep_insn, insn))
17286 case TYPE_FAST_COMPARE:
17289 case TYPE_INSERT_WORD:
17290 case TYPE_INSERT_DWORD:
17291 case TYPE_FPLOAD_U:
17292 case TYPE_FPLOAD_UX:
17294 case TYPE_STORE_UX:
17295 case TYPE_FPSTORE_U:
17296 case TYPE_FPSTORE_UX:
17298 if (set_to_load_agen (dep_insn, insn))
17306 case TYPE_IMUL_COMPARE:
17307 case TYPE_LMUL_COMPARE:
17309 if (set_to_load_agen (dep_insn, insn))
17315 if (set_to_load_agen (dep_insn, insn))
17321 if (set_to_load_agen (dep_insn, insn))
17332 if ((rs6000_cpu == PROCESSOR_POWER6)
17333 && recog_memoized (dep_insn)
17334 && (INSN_CODE (dep_insn) >= 0)
17335 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17342 /* Fall out to return default cost. */
17346 case REG_DEP_OUTPUT:
17347 /* Output dependency; DEP_INSN writes a register that INSN writes some
17349 if ((rs6000_cpu == PROCESSOR_POWER6)
17350 && recog_memoized (dep_insn)
17351 && (INSN_CODE (dep_insn) >= 0))
17353 attr_type = get_attr_type (insn);
17358 if (get_attr_type (dep_insn) == TYPE_FP)
17362 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17370 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17375 gcc_unreachable ();
17381 /* The function returns a true if INSN is microcoded.
17382 Return false otherwise. */
17385 is_microcoded_insn (rtx insn)
17387 if (!insn || !INSN_P (insn)
17388 || GET_CODE (PATTERN (insn)) == USE
17389 || GET_CODE (PATTERN (insn)) == CLOBBER)
17392 if (rs6000_cpu_attr == CPU_CELL)
17393 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17395 if (rs6000_sched_groups)
17397 enum attr_type type = get_attr_type (insn);
17398 if (type == TYPE_LOAD_EXT_U
17399 || type == TYPE_LOAD_EXT_UX
17400 || type == TYPE_LOAD_UX
17401 || type == TYPE_STORE_UX
17402 || type == TYPE_MFCR)
17409 /* The function returns true if INSN is cracked into 2 instructions
17410 by the processor (and therefore occupies 2 issue slots). */
17413 is_cracked_insn (rtx insn)
17415 if (!insn || !INSN_P (insn)
17416 || GET_CODE (PATTERN (insn)) == USE
17417 || GET_CODE (PATTERN (insn)) == CLOBBER)
17420 if (rs6000_sched_groups)
17422 enum attr_type type = get_attr_type (insn);
17423 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17424 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17425 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17426 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17427 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17428 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17429 || type == TYPE_IDIV || type == TYPE_LDIV
17430 || type == TYPE_INSERT_WORD)
17437 /* The function returns true if INSN can be issued only from
17438 the branch slot. */
17441 is_branch_slot_insn (rtx insn)
17443 if (!insn || !INSN_P (insn)
17444 || GET_CODE (PATTERN (insn)) == USE
17445 || GET_CODE (PATTERN (insn)) == CLOBBER)
17448 if (rs6000_sched_groups)
17450 enum attr_type type = get_attr_type (insn);
17451 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
17459 /* The function returns true if out_inst sets a value that is
17460 used in the address generation computation of in_insn */
17462 set_to_load_agen (rtx out_insn, rtx in_insn)
17464 rtx out_set, in_set;
17466 /* For performance reasons, only handle the simple case where
17467 both loads are a single_set. */
17468 out_set = single_set (out_insn);
17471 in_set = single_set (in_insn);
17473 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
17479 /* The function returns true if the target storage location of
17480 out_insn is adjacent to the target storage location of in_insn */
17481 /* Return 1 if memory locations are adjacent. */
17484 adjacent_mem_locations (rtx insn1, rtx insn2)
17487 rtx a = get_store_dest (PATTERN (insn1));
17488 rtx b = get_store_dest (PATTERN (insn2));
17490 if ((GET_CODE (XEXP (a, 0)) == REG
17491 || (GET_CODE (XEXP (a, 0)) == PLUS
17492 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
17493 && (GET_CODE (XEXP (b, 0)) == REG
17494 || (GET_CODE (XEXP (b, 0)) == PLUS
17495 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
17497 HOST_WIDE_INT val0 = 0, val1 = 0;
17501 if (GET_CODE (XEXP (a, 0)) == PLUS)
17503 reg0 = XEXP (XEXP (a, 0), 0);
17504 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
17507 reg0 = XEXP (a, 0);
17509 if (GET_CODE (XEXP (b, 0)) == PLUS)
17511 reg1 = XEXP (XEXP (b, 0), 0);
17512 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
17515 reg1 = XEXP (b, 0);
17517 val_diff = val1 - val0;
17519 return ((REGNO (reg0) == REGNO (reg1))
17520 && (val_diff == INTVAL (MEM_SIZE (a))
17521 || val_diff == -INTVAL (MEM_SIZE (b))));
17527 /* A C statement (sans semicolon) to update the integer scheduling
17528 priority INSN_PRIORITY (INSN). Increase the priority to execute the
17529 INSN earlier, reduce the priority to execute INSN later. Do not
17530 define this macro if you do not need to adjust the scheduling
17531 priorities of insns. */
17534 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
17536 /* On machines (like the 750) which have asymmetric integer units,
17537 where one integer unit can do multiply and divides and the other
17538 can't, reduce the priority of multiply/divide so it is scheduled
17539 before other integer operations. */
17542 if (! INSN_P (insn))
17545 if (GET_CODE (PATTERN (insn)) == USE)
17548 switch (rs6000_cpu_attr) {
17550 switch (get_attr_type (insn))
17557 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
17558 priority, priority);
17559 if (priority >= 0 && priority < 0x01000000)
17566 if (insn_must_be_first_in_group (insn)
17567 && reload_completed
17568 && current_sched_info->sched_max_insns_priority
17569 && rs6000_sched_restricted_insns_priority)
17572 /* Prioritize insns that can be dispatched only in the first
17574 if (rs6000_sched_restricted_insns_priority == 1)
17575 /* Attach highest priority to insn. This means that in
17576 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
17577 precede 'priority' (critical path) considerations. */
17578 return current_sched_info->sched_max_insns_priority;
17579 else if (rs6000_sched_restricted_insns_priority == 2)
17580 /* Increase priority of insn by a minimal amount. This means that in
17581 haifa-sched.c:ready_sort(), only 'priority' (critical path)
17582 considerations precede dispatch-slot restriction considerations. */
17583 return (priority + 1);
17586 if (rs6000_cpu == PROCESSOR_POWER6
17587 && ((load_store_pendulum == -2 && is_load_insn (insn))
17588 || (load_store_pendulum == 2 && is_store_insn (insn))))
17589 /* Attach highest priority to insn if the scheduler has just issued two
17590 stores and this instruction is a load, or two loads and this instruction
17591 is a store. Power6 wants loads and stores scheduled alternately
17593 return current_sched_info->sched_max_insns_priority;
17598 /* Return true if the instruction is nonpipelined on the Cell. */
17600 is_nonpipeline_insn (rtx insn)
17602 enum attr_type type;
17603 if (!insn || !INSN_P (insn)
17604 || GET_CODE (PATTERN (insn)) == USE
17605 || GET_CODE (PATTERN (insn)) == CLOBBER)
17608 type = get_attr_type (insn);
17609 if (type == TYPE_IMUL
17610 || type == TYPE_IMUL2
17611 || type == TYPE_IMUL3
17612 || type == TYPE_LMUL
17613 || type == TYPE_IDIV
17614 || type == TYPE_LDIV
17615 || type == TYPE_SDIV
17616 || type == TYPE_DDIV
17617 || type == TYPE_SSQRT
17618 || type == TYPE_DSQRT
17619 || type == TYPE_MFCR
17620 || type == TYPE_MFCRF
17621 || type == TYPE_MFJMPR)
17629 /* Return how many instructions the machine can issue per cycle. */
17632 rs6000_issue_rate (void)
17634 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
17635 if (!reload_completed)
17638 switch (rs6000_cpu_attr) {
17639 case CPU_RIOS1: /* ? */
17641 case CPU_PPC601: /* ? */
17666 /* Return how many instructions to look ahead for better insn
17670 rs6000_use_sched_lookahead (void)
17672 if (rs6000_cpu_attr == CPU_PPC8540)
17674 if (rs6000_cpu_attr == CPU_CELL)
17675 return (reload_completed ? 8 : 0);
17679 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
17681 rs6000_use_sched_lookahead_guard (rtx insn)
17683 if (rs6000_cpu_attr != CPU_CELL)
17686 if (insn == NULL_RTX || !INSN_P (insn))
17689 if (!reload_completed
17690 || is_nonpipeline_insn (insn)
17691 || is_microcoded_insn (insn))
17697 /* Determine is PAT refers to memory. */
17700 is_mem_ref (rtx pat)
17706 if (GET_CODE (pat) == MEM)
17709 /* Recursively process the pattern. */
17710 fmt = GET_RTX_FORMAT (GET_CODE (pat));
17712 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
17715 ret |= is_mem_ref (XEXP (pat, i));
17716 else if (fmt[i] == 'E')
17717 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
17718 ret |= is_mem_ref (XVECEXP (pat, i, j));
17724 /* Determine if PAT is a PATTERN of a load insn. */
17727 is_load_insn1 (rtx pat)
17729 if (!pat || pat == NULL_RTX)
17732 if (GET_CODE (pat) == SET)
17733 return is_mem_ref (SET_SRC (pat));
17735 if (GET_CODE (pat) == PARALLEL)
17739 for (i = 0; i < XVECLEN (pat, 0); i++)
17740 if (is_load_insn1 (XVECEXP (pat, 0, i)))
17747 /* Determine if INSN loads from memory. */
17750 is_load_insn (rtx insn)
17752 if (!insn || !INSN_P (insn))
17755 if (GET_CODE (insn) == CALL_INSN)
17758 return is_load_insn1 (PATTERN (insn));
17761 /* Determine if PAT is a PATTERN of a store insn. */
17764 is_store_insn1 (rtx pat)
17766 if (!pat || pat == NULL_RTX)
17769 if (GET_CODE (pat) == SET)
17770 return is_mem_ref (SET_DEST (pat));
17772 if (GET_CODE (pat) == PARALLEL)
17776 for (i = 0; i < XVECLEN (pat, 0); i++)
17777 if (is_store_insn1 (XVECEXP (pat, 0, i)))
17784 /* Determine if INSN stores to memory. */
17787 is_store_insn (rtx insn)
17789 if (!insn || !INSN_P (insn))
17792 return is_store_insn1 (PATTERN (insn));
17795 /* Return the dest of a store insn. */
17798 get_store_dest (rtx pat)
17800 gcc_assert (is_store_insn1 (pat));
17802 if (GET_CODE (pat) == SET)
17803 return SET_DEST (pat);
17804 else if (GET_CODE (pat) == PARALLEL)
17808 for (i = 0; i < XVECLEN (pat, 0); i++)
17810 rtx inner_pat = XVECEXP (pat, 0, i);
17811 if (GET_CODE (inner_pat) == SET
17812 && is_mem_ref (SET_DEST (inner_pat)))
17816 /* We shouldn't get here, because we should have either a simple
17817 store insn or a store with update which are covered above. */
17821 /* Returns whether the dependence between INSN and NEXT is considered
17822 costly by the given target. */
17825 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
17830 /* If the flag is not enabled - no dependence is considered costly;
17831 allow all dependent insns in the same group.
17832 This is the most aggressive option. */
17833 if (rs6000_sched_costly_dep == no_dep_costly)
17836 /* If the flag is set to 1 - a dependence is always considered costly;
17837 do not allow dependent instructions in the same group.
17838 This is the most conservative option. */
17839 if (rs6000_sched_costly_dep == all_deps_costly)
17842 insn = DEP_PRO (dep);
17843 next = DEP_CON (dep);
17845 if (rs6000_sched_costly_dep == store_to_load_dep_costly
17846 && is_load_insn (next)
17847 && is_store_insn (insn))
17848 /* Prevent load after store in the same group. */
17851 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
17852 && is_load_insn (next)
17853 && is_store_insn (insn)
17854 && DEP_KIND (dep) == REG_DEP_TRUE)
17855 /* Prevent load after store in the same group if it is a true
17859 /* The flag is set to X; dependences with latency >= X are considered costly,
17860 and will not be scheduled in the same group. */
17861 if (rs6000_sched_costly_dep <= max_dep_latency
17862 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
17868 /* Return the next insn after INSN that is found before TAIL is reached,
17869 skipping any "non-active" insns - insns that will not actually occupy
17870 an issue slot. Return NULL_RTX if such an insn is not found. */
17873 get_next_active_insn (rtx insn, rtx tail)
17875 if (insn == NULL_RTX || insn == tail)
17880 insn = NEXT_INSN (insn);
17881 if (insn == NULL_RTX || insn == tail)
17886 || (NONJUMP_INSN_P (insn)
17887 && GET_CODE (PATTERN (insn)) != USE
17888 && GET_CODE (PATTERN (insn)) != CLOBBER
17889 && INSN_CODE (insn) != CODE_FOR_stack_tie))
17895 /* We are about to begin issuing insns for this clock cycle. */
17898 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
17899 rtx *ready ATTRIBUTE_UNUSED,
17900 int *pn_ready ATTRIBUTE_UNUSED,
17901 int clock_var ATTRIBUTE_UNUSED)
17903 int n_ready = *pn_ready;
17906 fprintf (dump, "// rs6000_sched_reorder :\n");
17908 /* Reorder the ready list, if the second to last ready insn
17909 is a nonepipeline insn. */
17910 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
17912 if (is_nonpipeline_insn (ready[n_ready - 1])
17913 && (recog_memoized (ready[n_ready - 2]) > 0))
17914 /* Simply swap first two insns. */
17916 rtx tmp = ready[n_ready - 1];
17917 ready[n_ready - 1] = ready[n_ready - 2];
17918 ready[n_ready - 2] = tmp;
17922 if (rs6000_cpu == PROCESSOR_POWER6)
17923 load_store_pendulum = 0;
17925 return rs6000_issue_rate ();
17928 /* Like rs6000_sched_reorder, but called after issuing each insn. */
17931 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
17932 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
17935 fprintf (dump, "// rs6000_sched_reorder2 :\n");
17937 /* For Power6, we need to handle some special cases to try and keep the
17938 store queue from overflowing and triggering expensive flushes.
17940 This code monitors how load and store instructions are being issued
17941 and skews the ready list one way or the other to increase the likelihood
17942 that a desired instruction is issued at the proper time.
17944 A couple of things are done. First, we maintain a "load_store_pendulum"
17945 to track the current state of load/store issue.
17947 - If the pendulum is at zero, then no loads or stores have been
17948 issued in the current cycle so we do nothing.
17950 - If the pendulum is 1, then a single load has been issued in this
17951 cycle and we attempt to locate another load in the ready list to
17954 - If the pendulum is -2, then two stores have already been
17955 issued in this cycle, so we increase the priority of the first load
17956 in the ready list to increase it's likelihood of being chosen first
17959 - If the pendulum is -1, then a single store has been issued in this
17960 cycle and we attempt to locate another store in the ready list to
17961 issue with it, preferring a store to an adjacent memory location to
17962 facilitate store pairing in the store queue.
17964 - If the pendulum is 2, then two loads have already been
17965 issued in this cycle, so we increase the priority of the first store
17966 in the ready list to increase it's likelihood of being chosen first
17969 - If the pendulum < -2 or > 2, then do nothing.
17971 Note: This code covers the most common scenarios. There exist non
17972 load/store instructions which make use of the LSU and which
17973 would need to be accounted for to strictly model the behavior
17974 of the machine. Those instructions are currently unaccounted
17975 for to help minimize compile time overhead of this code.
17977 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
17983 if (is_store_insn (last_scheduled_insn))
17984 /* Issuing a store, swing the load_store_pendulum to the left */
17985 load_store_pendulum--;
17986 else if (is_load_insn (last_scheduled_insn))
17987 /* Issuing a load, swing the load_store_pendulum to the right */
17988 load_store_pendulum++;
17990 return cached_can_issue_more;
17992 /* If the pendulum is balanced, or there is only one instruction on
17993 the ready list, then all is well, so return. */
17994 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
17995 return cached_can_issue_more;
17997 if (load_store_pendulum == 1)
17999 /* A load has been issued in this cycle. Scan the ready list
18000 for another load to issue with it */
18005 if (is_load_insn (ready[pos]))
18007 /* Found a load. Move it to the head of the ready list,
18008 and adjust it's priority so that it is more likely to
18011 for (i=pos; i<*pn_ready-1; i++)
18012 ready[i] = ready[i + 1];
18013 ready[*pn_ready-1] = tmp;
18014 if INSN_PRIORITY_KNOWN (tmp)
18015 INSN_PRIORITY (tmp)++;
18021 else if (load_store_pendulum == -2)
18023 /* Two stores have been issued in this cycle. Increase the
18024 priority of the first load in the ready list to favor it for
18025 issuing in the next cycle. */
18030 if (is_load_insn (ready[pos])
18031 && INSN_PRIORITY_KNOWN (ready[pos]))
18033 INSN_PRIORITY (ready[pos])++;
18035 /* Adjust the pendulum to account for the fact that a load
18036 was found and increased in priority. This is to prevent
18037 increasing the priority of multiple loads */
18038 load_store_pendulum--;
18045 else if (load_store_pendulum == -1)
18047 /* A store has been issued in this cycle. Scan the ready list for
18048 another store to issue with it, preferring a store to an adjacent
18050 int first_store_pos = -1;
18056 if (is_store_insn (ready[pos]))
18058 /* Maintain the index of the first store found on the
18060 if (first_store_pos == -1)
18061 first_store_pos = pos;
18063 if (is_store_insn (last_scheduled_insn)
18064 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18066 /* Found an adjacent store. Move it to the head of the
18067 ready list, and adjust it's priority so that it is
18068 more likely to stay there */
18070 for (i=pos; i<*pn_ready-1; i++)
18071 ready[i] = ready[i + 1];
18072 ready[*pn_ready-1] = tmp;
18073 if INSN_PRIORITY_KNOWN (tmp)
18074 INSN_PRIORITY (tmp)++;
18075 first_store_pos = -1;
18083 if (first_store_pos >= 0)
18085 /* An adjacent store wasn't found, but a non-adjacent store was,
18086 so move the non-adjacent store to the front of the ready
18087 list, and adjust its priority so that it is more likely to
18089 tmp = ready[first_store_pos];
18090 for (i=first_store_pos; i<*pn_ready-1; i++)
18091 ready[i] = ready[i + 1];
18092 ready[*pn_ready-1] = tmp;
18093 if INSN_PRIORITY_KNOWN (tmp)
18094 INSN_PRIORITY (tmp)++;
18097 else if (load_store_pendulum == 2)
18099 /* Two loads have been issued in this cycle. Increase the priority
18100 of the first store in the ready list to favor it for issuing in
18106 if (is_store_insn (ready[pos])
18107 && INSN_PRIORITY_KNOWN (ready[pos]))
18109 INSN_PRIORITY (ready[pos])++;
18111 /* Adjust the pendulum to account for the fact that a store
18112 was found and increased in priority. This is to prevent
18113 increasing the priority of multiple stores */
18114 load_store_pendulum++;
18123 return cached_can_issue_more;
18126 /* Return whether the presence of INSN causes a dispatch group termination
18127 of group WHICH_GROUP.
18129 If WHICH_GROUP == current_group, this function will return true if INSN
18130 causes the termination of the current group (i.e, the dispatch group to
18131 which INSN belongs). This means that INSN will be the last insn in the
18132 group it belongs to.
18134 If WHICH_GROUP == previous_group, this function will return true if INSN
18135 causes the termination of the previous group (i.e, the dispatch group that
18136 precedes the group to which INSN belongs). This means that INSN will be
18137 the first insn in the group it belongs to). */
18140 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18147 first = insn_must_be_first_in_group (insn);
18148 last = insn_must_be_last_in_group (insn);
18153 if (which_group == current_group)
18155 else if (which_group == previous_group)
18163 insn_must_be_first_in_group (rtx insn)
18165 enum attr_type type;
18168 || insn == NULL_RTX
18169 || GET_CODE (insn) == NOTE
18170 || GET_CODE (PATTERN (insn)) == USE
18171 || GET_CODE (PATTERN (insn)) == CLOBBER)
18174 switch (rs6000_cpu)
18176 case PROCESSOR_POWER5:
18177 if (is_cracked_insn (insn))
18179 case PROCESSOR_POWER4:
18180 if (is_microcoded_insn (insn))
18183 if (!rs6000_sched_groups)
18186 type = get_attr_type (insn);
18193 case TYPE_DELAYED_CR:
18194 case TYPE_CR_LOGICAL:
18208 case PROCESSOR_POWER6:
18209 type = get_attr_type (insn);
18213 case TYPE_INSERT_DWORD:
18217 case TYPE_VAR_SHIFT_ROTATE:
18224 case TYPE_INSERT_WORD:
18225 case TYPE_DELAYED_COMPARE:
18226 case TYPE_IMUL_COMPARE:
18227 case TYPE_LMUL_COMPARE:
18228 case TYPE_FPCOMPARE:
18239 case TYPE_LOAD_EXT_UX:
18241 case TYPE_STORE_UX:
18242 case TYPE_FPLOAD_U:
18243 case TYPE_FPLOAD_UX:
18244 case TYPE_FPSTORE_U:
18245 case TYPE_FPSTORE_UX:
18259 insn_must_be_last_in_group (rtx insn)
18261 enum attr_type type;
18264 || insn == NULL_RTX
18265 || GET_CODE (insn) == NOTE
18266 || GET_CODE (PATTERN (insn)) == USE
18267 || GET_CODE (PATTERN (insn)) == CLOBBER)
18270 switch (rs6000_cpu) {
18271 case PROCESSOR_POWER4:
18272 case PROCESSOR_POWER5:
18273 if (is_microcoded_insn (insn))
18276 if (is_branch_slot_insn (insn))
18280 case PROCESSOR_POWER6:
18281 type = get_attr_type (insn);
18288 case TYPE_VAR_SHIFT_ROTATE:
18295 case TYPE_DELAYED_COMPARE:
18296 case TYPE_IMUL_COMPARE:
18297 case TYPE_LMUL_COMPARE:
18298 case TYPE_FPCOMPARE:
18319 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18320 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18323 is_costly_group (rtx *group_insns, rtx next_insn)
18326 int issue_rate = rs6000_issue_rate ();
18328 for (i = 0; i < issue_rate; i++)
18331 rtx insn = group_insns[i];
18336 FOR_EACH_DEP_LINK (link, INSN_FORW_DEPS (insn))
18338 dep_t dep = DEP_LINK_DEP (link);
18339 rtx next = DEP_CON (dep);
18341 if (next == next_insn
18342 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18350 /* Utility of the function redefine_groups.
18351 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18352 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18353 to keep it "far" (in a separate group) from GROUP_INSNS, following
18354 one of the following schemes, depending on the value of the flag
18355 -minsert_sched_nops = X:
18356 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18357 in order to force NEXT_INSN into a separate group.
18358 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18359 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18360 insertion (has a group just ended, how many vacant issue slots remain in the
18361 last group, and how many dispatch groups were encountered so far). */
18364 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18365 rtx next_insn, bool *group_end, int can_issue_more,
18370 int issue_rate = rs6000_issue_rate ();
18371 bool end = *group_end;
18374 if (next_insn == NULL_RTX)
18375 return can_issue_more;
18377 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18378 return can_issue_more;
18380 force = is_costly_group (group_insns, next_insn);
18382 return can_issue_more;
18384 if (sched_verbose > 6)
18385 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18386 *group_count ,can_issue_more);
18388 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18391 can_issue_more = 0;
18393 /* Since only a branch can be issued in the last issue_slot, it is
18394 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18395 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18396 in this case the last nop will start a new group and the branch
18397 will be forced to the new group. */
18398 if (can_issue_more && !is_branch_slot_insn (next_insn))
18401 while (can_issue_more > 0)
18404 emit_insn_before (nop, next_insn);
18412 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18414 int n_nops = rs6000_sched_insert_nops;
18416 /* Nops can't be issued from the branch slot, so the effective
18417 issue_rate for nops is 'issue_rate - 1'. */
18418 if (can_issue_more == 0)
18419 can_issue_more = issue_rate;
18421 if (can_issue_more == 0)
18423 can_issue_more = issue_rate - 1;
18426 for (i = 0; i < issue_rate; i++)
18428 group_insns[i] = 0;
18435 emit_insn_before (nop, next_insn);
18436 if (can_issue_more == issue_rate - 1) /* new group begins */
18439 if (can_issue_more == 0)
18441 can_issue_more = issue_rate - 1;
18444 for (i = 0; i < issue_rate; i++)
18446 group_insns[i] = 0;
18452 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
18455 /* Is next_insn going to start a new group? */
18458 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18459 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18460 || (can_issue_more < issue_rate &&
18461 insn_terminates_group_p (next_insn, previous_group)));
18462 if (*group_end && end)
18465 if (sched_verbose > 6)
18466 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
18467 *group_count, can_issue_more);
18468 return can_issue_more;
18471 return can_issue_more;
18474 /* This function tries to synch the dispatch groups that the compiler "sees"
18475 with the dispatch groups that the processor dispatcher is expected to
18476 form in practice. It tries to achieve this synchronization by forcing the
18477 estimated processor grouping on the compiler (as opposed to the function
18478 'pad_goups' which tries to force the scheduler's grouping on the processor).
18480 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
18481 examines the (estimated) dispatch groups that will be formed by the processor
18482 dispatcher. It marks these group boundaries to reflect the estimated
18483 processor grouping, overriding the grouping that the scheduler had marked.
18484 Depending on the value of the flag '-minsert-sched-nops' this function can
18485 force certain insns into separate groups or force a certain distance between
18486 them by inserting nops, for example, if there exists a "costly dependence"
18489 The function estimates the group boundaries that the processor will form as
18490 follows: It keeps track of how many vacant issue slots are available after
18491 each insn. A subsequent insn will start a new group if one of the following
18493 - no more vacant issue slots remain in the current dispatch group.
18494 - only the last issue slot, which is the branch slot, is vacant, but the next
18495 insn is not a branch.
18496 - only the last 2 or less issue slots, including the branch slot, are vacant,
18497 which means that a cracked insn (which occupies two issue slots) can't be
18498 issued in this group.
18499 - less than 'issue_rate' slots are vacant, and the next insn always needs to
18500 start a new group. */
18503 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18505 rtx insn, next_insn;
18507 int can_issue_more;
18510 int group_count = 0;
18514 issue_rate = rs6000_issue_rate ();
18515 group_insns = alloca (issue_rate * sizeof (rtx));
18516 for (i = 0; i < issue_rate; i++)
18518 group_insns[i] = 0;
18520 can_issue_more = issue_rate;
18522 insn = get_next_active_insn (prev_head_insn, tail);
18525 while (insn != NULL_RTX)
18527 slot = (issue_rate - can_issue_more);
18528 group_insns[slot] = insn;
18530 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18531 if (insn_terminates_group_p (insn, current_group))
18532 can_issue_more = 0;
18534 next_insn = get_next_active_insn (insn, tail);
18535 if (next_insn == NULL_RTX)
18536 return group_count + 1;
18538 /* Is next_insn going to start a new group? */
18540 = (can_issue_more == 0
18541 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
18542 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
18543 || (can_issue_more < issue_rate &&
18544 insn_terminates_group_p (next_insn, previous_group)));
18546 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
18547 next_insn, &group_end, can_issue_more,
18553 can_issue_more = 0;
18554 for (i = 0; i < issue_rate; i++)
18556 group_insns[i] = 0;
18560 if (GET_MODE (next_insn) == TImode && can_issue_more)
18561 PUT_MODE (next_insn, VOIDmode);
18562 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
18563 PUT_MODE (next_insn, TImode);
18566 if (can_issue_more == 0)
18567 can_issue_more = issue_rate;
18570 return group_count;
18573 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
18574 dispatch group boundaries that the scheduler had marked. Pad with nops
18575 any dispatch groups which have vacant issue slots, in order to force the
18576 scheduler's grouping on the processor dispatcher. The function
18577 returns the number of dispatch groups found. */
18580 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
18582 rtx insn, next_insn;
18585 int can_issue_more;
18587 int group_count = 0;
18589 /* Initialize issue_rate. */
18590 issue_rate = rs6000_issue_rate ();
18591 can_issue_more = issue_rate;
18593 insn = get_next_active_insn (prev_head_insn, tail);
18594 next_insn = get_next_active_insn (insn, tail);
18596 while (insn != NULL_RTX)
18599 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
18601 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
18603 if (next_insn == NULL_RTX)
18608 /* If the scheduler had marked group termination at this location
18609 (between insn and next_indn), and neither insn nor next_insn will
18610 force group termination, pad the group with nops to force group
18613 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
18614 && !insn_terminates_group_p (insn, current_group)
18615 && !insn_terminates_group_p (next_insn, previous_group))
18617 if (!is_branch_slot_insn (next_insn))
18620 while (can_issue_more)
18623 emit_insn_before (nop, next_insn);
18628 can_issue_more = issue_rate;
18633 next_insn = get_next_active_insn (insn, tail);
18636 return group_count;
18639 /* We're beginning a new block. Initialize data structures as necessary. */
18642 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
18643 int sched_verbose ATTRIBUTE_UNUSED,
18644 int max_ready ATTRIBUTE_UNUSED)
18646 last_scheduled_insn = NULL_RTX;
18647 load_store_pendulum = 0;
18650 /* The following function is called at the end of scheduling BB.
18651 After reload, it inserts nops at insn group bundling. */
18654 rs6000_sched_finish (FILE *dump, int sched_verbose)
18659 fprintf (dump, "=== Finishing schedule.\n");
18661 if (reload_completed && rs6000_sched_groups)
18663 if (rs6000_sched_insert_nops == sched_finish_none)
18666 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
18667 n_groups = pad_groups (dump, sched_verbose,
18668 current_sched_info->prev_head,
18669 current_sched_info->next_tail);
18671 n_groups = redefine_groups (dump, sched_verbose,
18672 current_sched_info->prev_head,
18673 current_sched_info->next_tail);
18675 if (sched_verbose >= 6)
18677 fprintf (dump, "ngroups = %d\n", n_groups);
18678 print_rtl (dump, current_sched_info->prev_head);
18679 fprintf (dump, "Done finish_sched\n");
18684 /* Length in units of the trampoline for entering a nested function. */
18687 rs6000_trampoline_size (void)
18691 switch (DEFAULT_ABI)
18694 gcc_unreachable ();
18697 ret = (TARGET_32BIT) ? 12 : 24;
18702 ret = (TARGET_32BIT) ? 40 : 48;
18709 /* Emit RTL insns to initialize the variable parts of a trampoline.
18710 FNADDR is an RTX for the address of the function's pure code.
18711 CXT is an RTX for the static chain value for the function. */
18714 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
18716 int regsize = (TARGET_32BIT) ? 4 : 8;
18717 rtx ctx_reg = force_reg (Pmode, cxt);
18719 switch (DEFAULT_ABI)
18722 gcc_unreachable ();
18724 /* Macros to shorten the code expansions below. */
18725 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
18726 #define MEM_PLUS(addr,offset) \
18727 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
18729 /* Under AIX, just build the 3 word function descriptor */
18732 rtx fn_reg = gen_reg_rtx (Pmode);
18733 rtx toc_reg = gen_reg_rtx (Pmode);
18734 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
18735 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
18736 emit_move_insn (MEM_DEREF (addr), fn_reg);
18737 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
18738 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
18742 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
18745 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
18746 FALSE, VOIDmode, 4,
18748 GEN_INT (rs6000_trampoline_size ()), SImode,
18758 /* Table of valid machine attributes. */
18760 const struct attribute_spec rs6000_attribute_table[] =
18762 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
18763 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
18764 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18765 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
18766 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18767 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
18768 #ifdef SUBTARGET_ATTRIBUTE_TABLE
18769 SUBTARGET_ATTRIBUTE_TABLE,
18771 { NULL, 0, 0, false, false, false, NULL }
18774 /* Handle the "altivec" attribute. The attribute may have
18775 arguments as follows:
18777 __attribute__((altivec(vector__)))
18778 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
18779 __attribute__((altivec(bool__))) (always followed by 'unsigned')
18781 and may appear more than once (e.g., 'vector bool char') in a
18782 given declaration. */
18785 rs6000_handle_altivec_attribute (tree *node,
18786 tree name ATTRIBUTE_UNUSED,
18788 int flags ATTRIBUTE_UNUSED,
18789 bool *no_add_attrs)
18791 tree type = *node, result = NULL_TREE;
18792 enum machine_mode mode;
18795 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
18796 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
18797 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
18800 while (POINTER_TYPE_P (type)
18801 || TREE_CODE (type) == FUNCTION_TYPE
18802 || TREE_CODE (type) == METHOD_TYPE
18803 || TREE_CODE (type) == ARRAY_TYPE)
18804 type = TREE_TYPE (type);
18806 mode = TYPE_MODE (type);
18808 /* Check for invalid AltiVec type qualifiers. */
18809 if (type == long_unsigned_type_node || type == long_integer_type_node)
18812 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
18813 else if (rs6000_warn_altivec_long)
18814 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
18816 else if (type == long_long_unsigned_type_node
18817 || type == long_long_integer_type_node)
18818 error ("use of %<long long%> in AltiVec types is invalid");
18819 else if (type == double_type_node)
18820 error ("use of %<double%> in AltiVec types is invalid");
18821 else if (type == long_double_type_node)
18822 error ("use of %<long double%> in AltiVec types is invalid");
18823 else if (type == boolean_type_node)
18824 error ("use of boolean types in AltiVec types is invalid");
18825 else if (TREE_CODE (type) == COMPLEX_TYPE)
18826 error ("use of %<complex%> in AltiVec types is invalid");
18827 else if (DECIMAL_FLOAT_MODE_P (mode))
18828 error ("use of decimal floating point types in AltiVec types is invalid");
18830 switch (altivec_type)
18833 unsigned_p = TYPE_UNSIGNED (type);
18837 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
18840 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
18843 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
18845 case SFmode: result = V4SF_type_node; break;
18846 /* If the user says 'vector int bool', we may be handed the 'bool'
18847 attribute _before_ the 'vector' attribute, and so select the
18848 proper type in the 'b' case below. */
18849 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
18857 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
18858 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
18859 case QImode: case V16QImode: result = bool_V16QI_type_node;
18866 case V8HImode: result = pixel_V8HI_type_node;
18872 if (result && result != type && TYPE_READONLY (type))
18873 result = build_qualified_type (result, TYPE_QUAL_CONST);
18875 *no_add_attrs = true; /* No need to hang on to the attribute. */
18878 *node = reconstruct_complex_type (*node, result);
18883 /* AltiVec defines four built-in scalar types that serve as vector
18884 elements; we must teach the compiler how to mangle them. */
18886 static const char *
18887 rs6000_mangle_fundamental_type (tree type)
18889 if (type == bool_char_type_node) return "U6__boolc";
18890 if (type == bool_short_type_node) return "U6__bools";
18891 if (type == pixel_type_node) return "u7__pixel";
18892 if (type == bool_int_type_node) return "U6__booli";
18894 /* Mangle IBM extended float long double as `g' (__float128) on
18895 powerpc*-linux where long-double-64 previously was the default. */
18896 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
18898 && TARGET_LONG_DOUBLE_128
18899 && !TARGET_IEEEQUAD)
18902 /* For all other types, use normal C++ mangling. */
18906 /* Handle a "longcall" or "shortcall" attribute; arguments as in
18907 struct attribute_spec.handler. */
18910 rs6000_handle_longcall_attribute (tree *node, tree name,
18911 tree args ATTRIBUTE_UNUSED,
18912 int flags ATTRIBUTE_UNUSED,
18913 bool *no_add_attrs)
18915 if (TREE_CODE (*node) != FUNCTION_TYPE
18916 && TREE_CODE (*node) != FIELD_DECL
18917 && TREE_CODE (*node) != TYPE_DECL)
18919 warning (OPT_Wattributes, "%qs attribute only applies to functions",
18920 IDENTIFIER_POINTER (name));
18921 *no_add_attrs = true;
18927 /* Set longcall attributes on all functions declared when
18928 rs6000_default_long_calls is true. */
18930 rs6000_set_default_type_attributes (tree type)
18932 if (rs6000_default_long_calls
18933 && (TREE_CODE (type) == FUNCTION_TYPE
18934 || TREE_CODE (type) == METHOD_TYPE))
18935 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
18937 TYPE_ATTRIBUTES (type));
18940 darwin_set_default_type_attributes (type);
18944 /* Return a reference suitable for calling a function with the
18945 longcall attribute. */
18948 rs6000_longcall_ref (rtx call_ref)
18950 const char *call_name;
18953 if (GET_CODE (call_ref) != SYMBOL_REF)
18956 /* System V adds '.' to the internal name, so skip them. */
18957 call_name = XSTR (call_ref, 0);
18958 if (*call_name == '.')
18960 while (*call_name == '.')
18963 node = get_identifier (call_name);
18964 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
18967 return force_reg (Pmode, call_ref);
18970 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
18971 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
18974 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
18975 struct attribute_spec.handler. */
18977 rs6000_handle_struct_attribute (tree *node, tree name,
18978 tree args ATTRIBUTE_UNUSED,
18979 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
18982 if (DECL_P (*node))
18984 if (TREE_CODE (*node) == TYPE_DECL)
18985 type = &TREE_TYPE (*node);
18990 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
18991 || TREE_CODE (*type) == UNION_TYPE)))
18993 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
18994 *no_add_attrs = true;
18997 else if ((is_attribute_p ("ms_struct", name)
18998 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
18999 || ((is_attribute_p ("gcc_struct", name)
19000 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19002 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19003 IDENTIFIER_POINTER (name));
19004 *no_add_attrs = true;
19011 rs6000_ms_bitfield_layout_p (tree record_type)
19013 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19014 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19015 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19018 #ifdef USING_ELFOS_H
19020 /* A get_unnamed_section callback, used for switching to toc_section. */
19023 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19025 if (DEFAULT_ABI == ABI_AIX
19026 && TARGET_MINIMAL_TOC
19027 && !TARGET_RELOCATABLE)
19029 if (!toc_initialized)
19031 toc_initialized = 1;
19032 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19033 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19034 fprintf (asm_out_file, "\t.tc ");
19035 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19036 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19037 fprintf (asm_out_file, "\n");
19039 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19040 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19041 fprintf (asm_out_file, " = .+32768\n");
19044 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19046 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19047 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19050 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19051 if (!toc_initialized)
19053 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19054 fprintf (asm_out_file, " = .+32768\n");
19055 toc_initialized = 1;
19060 /* Implement TARGET_ASM_INIT_SECTIONS. */
19063 rs6000_elf_asm_init_sections (void)
19066 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19069 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19070 SDATA2_SECTION_ASM_OP);
19073 /* Implement TARGET_SELECT_RTX_SECTION. */
19076 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19077 unsigned HOST_WIDE_INT align)
19079 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19080 return toc_section;
19082 return default_elf_select_rtx_section (mode, x, align);
19085 /* For a SYMBOL_REF, set generic flags and then perform some
19086 target-specific processing.
19088 When the AIX ABI is requested on a non-AIX system, replace the
19089 function name with the real name (with a leading .) rather than the
19090 function descriptor name. This saves a lot of overriding code to
19091 read the prefixes. */
19094 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19096 default_encode_section_info (decl, rtl, first);
19099 && TREE_CODE (decl) == FUNCTION_DECL
19101 && DEFAULT_ABI == ABI_AIX)
19103 rtx sym_ref = XEXP (rtl, 0);
19104 size_t len = strlen (XSTR (sym_ref, 0));
19105 char *str = alloca (len + 2);
19107 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19108 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19113 rs6000_elf_in_small_data_p (tree decl)
19115 if (rs6000_sdata == SDATA_NONE)
19118 /* We want to merge strings, so we never consider them small data. */
19119 if (TREE_CODE (decl) == STRING_CST)
19122 /* Functions are never in the small data area. */
19123 if (TREE_CODE (decl) == FUNCTION_DECL)
19126 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19128 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19129 if (strcmp (section, ".sdata") == 0
19130 || strcmp (section, ".sdata2") == 0
19131 || strcmp (section, ".sbss") == 0
19132 || strcmp (section, ".sbss2") == 0
19133 || strcmp (section, ".PPC.EMB.sdata0") == 0
19134 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19139 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19142 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19143 /* If it's not public, and we're not going to reference it there,
19144 there's no need to put it in the small data section. */
19145 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19152 #endif /* USING_ELFOS_H */
19154 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19157 rs6000_use_blocks_for_constant_p (enum machine_mode mode, rtx x)
19159 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19162 /* Return a REG that occurs in ADDR with coefficient 1.
19163 ADDR can be effectively incremented by incrementing REG.
19165 r0 is special and we must not select it as an address
19166 register by this routine since our caller will try to
19167 increment the returned register via an "la" instruction. */
19170 find_addr_reg (rtx addr)
19172 while (GET_CODE (addr) == PLUS)
19174 if (GET_CODE (XEXP (addr, 0)) == REG
19175 && REGNO (XEXP (addr, 0)) != 0)
19176 addr = XEXP (addr, 0);
19177 else if (GET_CODE (XEXP (addr, 1)) == REG
19178 && REGNO (XEXP (addr, 1)) != 0)
19179 addr = XEXP (addr, 1);
19180 else if (CONSTANT_P (XEXP (addr, 0)))
19181 addr = XEXP (addr, 1);
19182 else if (CONSTANT_P (XEXP (addr, 1)))
19183 addr = XEXP (addr, 0);
19185 gcc_unreachable ();
19187 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19192 rs6000_fatal_bad_address (rtx op)
19194 fatal_insn ("bad address", op);
19199 static tree branch_island_list = 0;
19201 /* Remember to generate a branch island for far calls to the given
19205 add_compiler_branch_island (tree label_name, tree function_name,
19208 tree branch_island = build_tree_list (function_name, label_name);
19209 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19210 TREE_CHAIN (branch_island) = branch_island_list;
19211 branch_island_list = branch_island;
19214 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19215 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19216 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19217 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19219 /* Generate far-jump branch islands for everything on the
19220 branch_island_list. Invoked immediately after the last instruction
19221 of the epilogue has been emitted; the branch-islands must be
19222 appended to, and contiguous with, the function body. Mach-O stubs
19223 are generated in machopic_output_stub(). */
19226 macho_branch_islands (void)
19229 tree branch_island;
19231 for (branch_island = branch_island_list;
19233 branch_island = TREE_CHAIN (branch_island))
19235 const char *label =
19236 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19238 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19239 char name_buf[512];
19240 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19241 if (name[0] == '*' || name[0] == '&')
19242 strcpy (name_buf, name+1);
19246 strcpy (name_buf+1, name);
19248 strcpy (tmp_buf, "\n");
19249 strcat (tmp_buf, label);
19250 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19251 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19252 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19253 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19256 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19257 strcat (tmp_buf, label);
19258 strcat (tmp_buf, "_pic\n");
19259 strcat (tmp_buf, label);
19260 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19262 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19263 strcat (tmp_buf, name_buf);
19264 strcat (tmp_buf, " - ");
19265 strcat (tmp_buf, label);
19266 strcat (tmp_buf, "_pic)\n");
19268 strcat (tmp_buf, "\tmtlr r0\n");
19270 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19271 strcat (tmp_buf, name_buf);
19272 strcat (tmp_buf, " - ");
19273 strcat (tmp_buf, label);
19274 strcat (tmp_buf, "_pic)\n");
19276 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19280 strcat (tmp_buf, ":\nlis r12,hi16(");
19281 strcat (tmp_buf, name_buf);
19282 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19283 strcat (tmp_buf, name_buf);
19284 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19286 output_asm_insn (tmp_buf, 0);
19287 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19288 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19289 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19290 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19293 branch_island_list = 0;
19296 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19297 already there or not. */
19300 no_previous_def (tree function_name)
19302 tree branch_island;
19303 for (branch_island = branch_island_list;
19305 branch_island = TREE_CHAIN (branch_island))
19306 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19311 /* GET_PREV_LABEL gets the label name from the previous definition of
19315 get_prev_label (tree function_name)
19317 tree branch_island;
19318 for (branch_island = branch_island_list;
19320 branch_island = TREE_CHAIN (branch_island))
19321 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19322 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19326 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19327 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19330 /* KEXTs still need branch islands. */
19331 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19332 || flag_mkernel || flag_apple_kext)
19334 /* INSN is either a function call or a millicode call. It may have an
19335 unconditional jump in its delay slot.
19337 CALL_DEST is the routine we are calling. */
19340 output_call (rtx insn, rtx *operands, int dest_operand_number,
19341 int cookie_operand_number)
19343 static char buf[256];
19344 if (DARWIN_GENERATE_ISLANDS
19345 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19346 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19349 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19351 if (no_previous_def (funname))
19353 rtx label_rtx = gen_label_rtx ();
19354 char *label_buf, temp_buf[256];
19355 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19356 CODE_LABEL_NUMBER (label_rtx));
19357 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19358 labelname = get_identifier (label_buf);
19359 add_compiler_branch_island (labelname, funname, insn_line (insn));
19362 labelname = get_prev_label (funname);
19364 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19365 instruction will reach 'foo', otherwise link as 'bl L42'".
19366 "L42" should be a 'branch island', that will do a far jump to
19367 'foo'. Branch islands are generated in
19368 macho_branch_islands(). */
19369 sprintf (buf, "jbsr %%z%d,%.246s",
19370 dest_operand_number, IDENTIFIER_POINTER (labelname));
19373 sprintf (buf, "bl %%z%d", dest_operand_number);
19377 /* Generate PIC and indirect symbol stubs. */
19380 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19382 unsigned int length;
19383 char *symbol_name, *lazy_ptr_name;
19384 char *local_label_0;
19385 static int label = 0;
19387 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19388 symb = (*targetm.strip_name_encoding) (symb);
19391 length = strlen (symb);
19392 symbol_name = alloca (length + 32);
19393 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19395 lazy_ptr_name = alloca (length + 32);
19396 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19399 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19401 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19405 fprintf (file, "\t.align 5\n");
19407 fprintf (file, "%s:\n", stub);
19408 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19411 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19412 sprintf (local_label_0, "\"L%011d$spb\"", label);
19414 fprintf (file, "\tmflr r0\n");
19415 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19416 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19417 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19418 lazy_ptr_name, local_label_0);
19419 fprintf (file, "\tmtlr r0\n");
19420 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19421 (TARGET_64BIT ? "ldu" : "lwzu"),
19422 lazy_ptr_name, local_label_0);
19423 fprintf (file, "\tmtctr r12\n");
19424 fprintf (file, "\tbctr\n");
19428 fprintf (file, "\t.align 4\n");
19430 fprintf (file, "%s:\n", stub);
19431 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19433 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
19434 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
19435 (TARGET_64BIT ? "ldu" : "lwzu"),
19437 fprintf (file, "\tmtctr r12\n");
19438 fprintf (file, "\tbctr\n");
19441 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
19442 fprintf (file, "%s:\n", lazy_ptr_name);
19443 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19444 fprintf (file, "%sdyld_stub_binding_helper\n",
19445 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
19448 /* Legitimize PIC addresses. If the address is already
19449 position-independent, we return ORIG. Newly generated
19450 position-independent addresses go into a reg. This is REG if non
19451 zero, otherwise we allocate register(s) as necessary. */
19453 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
19456 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
19461 if (reg == NULL && ! reload_in_progress && ! reload_completed)
19462 reg = gen_reg_rtx (Pmode);
19464 if (GET_CODE (orig) == CONST)
19468 if (GET_CODE (XEXP (orig, 0)) == PLUS
19469 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
19472 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
19474 /* Use a different reg for the intermediate value, as
19475 it will be marked UNCHANGING. */
19476 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
19477 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
19480 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
19483 if (GET_CODE (offset) == CONST_INT)
19485 if (SMALL_INT (offset))
19486 return plus_constant (base, INTVAL (offset));
19487 else if (! reload_in_progress && ! reload_completed)
19488 offset = force_reg (Pmode, offset);
19491 rtx mem = force_const_mem (Pmode, orig);
19492 return machopic_legitimize_pic_address (mem, Pmode, reg);
19495 return gen_rtx_PLUS (Pmode, base, offset);
19498 /* Fall back on generic machopic code. */
19499 return machopic_legitimize_pic_address (orig, mode, reg);
19502 /* Output a .machine directive for the Darwin assembler, and call
19503 the generic start_file routine. */
19506 rs6000_darwin_file_start (void)
19508 static const struct
19514 { "ppc64", "ppc64", MASK_64BIT },
19515 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
19516 { "power4", "ppc970", 0 },
19517 { "G5", "ppc970", 0 },
19518 { "7450", "ppc7450", 0 },
19519 { "7400", "ppc7400", MASK_ALTIVEC },
19520 { "G4", "ppc7400", 0 },
19521 { "750", "ppc750", 0 },
19522 { "740", "ppc750", 0 },
19523 { "G3", "ppc750", 0 },
19524 { "604e", "ppc604e", 0 },
19525 { "604", "ppc604", 0 },
19526 { "603e", "ppc603", 0 },
19527 { "603", "ppc603", 0 },
19528 { "601", "ppc601", 0 },
19529 { NULL, "ppc", 0 } };
19530 const char *cpu_id = "";
19533 rs6000_file_start ();
19534 darwin_file_start ();
19536 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
19537 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
19538 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
19539 && rs6000_select[i].string[0] != '\0')
19540 cpu_id = rs6000_select[i].string;
19542 /* Look through the mapping array. Pick the first name that either
19543 matches the argument, has a bit set in IF_SET that is also set
19544 in the target flags, or has a NULL name. */
19547 while (mapping[i].arg != NULL
19548 && strcmp (mapping[i].arg, cpu_id) != 0
19549 && (mapping[i].if_set & target_flags) == 0)
19552 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
19555 #endif /* TARGET_MACHO */
19559 rs6000_elf_reloc_rw_mask (void)
19563 else if (DEFAULT_ABI == ABI_AIX)
19569 /* Record an element in the table of global constructors. SYMBOL is
19570 a SYMBOL_REF of the function to be called; PRIORITY is a number
19571 between 0 and MAX_INIT_PRIORITY.
19573 This differs from default_named_section_asm_out_constructor in
19574 that we have special handling for -mrelocatable. */
19577 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
19579 const char *section = ".ctors";
19582 if (priority != DEFAULT_INIT_PRIORITY)
19584 sprintf (buf, ".ctors.%.5u",
19585 /* Invert the numbering so the linker puts us in the proper
19586 order; constructors are run from right to left, and the
19587 linker sorts in increasing order. */
19588 MAX_INIT_PRIORITY - priority);
19592 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19593 assemble_align (POINTER_SIZE);
19595 if (TARGET_RELOCATABLE)
19597 fputs ("\t.long (", asm_out_file);
19598 output_addr_const (asm_out_file, symbol);
19599 fputs (")@fixup\n", asm_out_file);
19602 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19606 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
19608 const char *section = ".dtors";
19611 if (priority != DEFAULT_INIT_PRIORITY)
19613 sprintf (buf, ".dtors.%.5u",
19614 /* Invert the numbering so the linker puts us in the proper
19615 order; constructors are run from right to left, and the
19616 linker sorts in increasing order. */
19617 MAX_INIT_PRIORITY - priority);
19621 switch_to_section (get_section (section, SECTION_WRITE, NULL));
19622 assemble_align (POINTER_SIZE);
19624 if (TARGET_RELOCATABLE)
19626 fputs ("\t.long (", asm_out_file);
19627 output_addr_const (asm_out_file, symbol);
19628 fputs (")@fixup\n", asm_out_file);
19631 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
19635 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
19639 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
19640 ASM_OUTPUT_LABEL (file, name);
19641 fputs (DOUBLE_INT_ASM_OP, file);
19642 rs6000_output_function_entry (file, name);
19643 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
19646 fputs ("\t.size\t", file);
19647 assemble_name (file, name);
19648 fputs (",24\n\t.type\t.", file);
19649 assemble_name (file, name);
19650 fputs (",@function\n", file);
19651 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
19653 fputs ("\t.globl\t.", file);
19654 assemble_name (file, name);
19659 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19660 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19661 rs6000_output_function_entry (file, name);
19662 fputs (":\n", file);
19666 if (TARGET_RELOCATABLE
19667 && !TARGET_SECURE_PLT
19668 && (get_pool_size () != 0 || current_function_profile)
19673 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
19675 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
19676 fprintf (file, "\t.long ");
19677 assemble_name (file, buf);
19679 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
19680 assemble_name (file, buf);
19684 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
19685 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
19687 if (DEFAULT_ABI == ABI_AIX)
19689 const char *desc_name, *orig_name;
19691 orig_name = (*targetm.strip_name_encoding) (name);
19692 desc_name = orig_name;
19693 while (*desc_name == '.')
19696 if (TREE_PUBLIC (decl))
19697 fprintf (file, "\t.globl %s\n", desc_name);
19699 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19700 fprintf (file, "%s:\n", desc_name);
19701 fprintf (file, "\t.long %s\n", orig_name);
19702 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
19703 if (DEFAULT_ABI == ABI_AIX)
19704 fputs ("\t.long 0\n", file);
19705 fprintf (file, "\t.previous\n");
19707 ASM_OUTPUT_LABEL (file, name);
19711 rs6000_elf_end_indicate_exec_stack (void)
19714 file_end_indicate_exec_stack ();
19720 rs6000_xcoff_asm_output_anchor (rtx symbol)
19724 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
19725 SYMBOL_REF_BLOCK_OFFSET (symbol));
19726 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
19730 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
19732 fputs (GLOBAL_ASM_OP, stream);
19733 RS6000_OUTPUT_BASENAME (stream, name);
19734 putc ('\n', stream);
19737 /* A get_unnamed_decl callback, used for read-only sections. PTR
19738 points to the section string variable. */
19741 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
19743 fprintf (asm_out_file, "\t.csect %s[RO],3\n",
19744 *(const char *const *) directive);
19747 /* Likewise for read-write sections. */
19750 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
19752 fprintf (asm_out_file, "\t.csect %s[RW],3\n",
19753 *(const char *const *) directive);
19756 /* A get_unnamed_section callback, used for switching to toc_section. */
19759 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19761 if (TARGET_MINIMAL_TOC)
19763 /* toc_section is always selected at least once from
19764 rs6000_xcoff_file_start, so this is guaranteed to
19765 always be defined once and only once in each file. */
19766 if (!toc_initialized)
19768 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
19769 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
19770 toc_initialized = 1;
19772 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
19773 (TARGET_32BIT ? "" : ",3"));
19776 fputs ("\t.toc\n", asm_out_file);
19779 /* Implement TARGET_ASM_INIT_SECTIONS. */
19782 rs6000_xcoff_asm_init_sections (void)
19784 read_only_data_section
19785 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19786 &xcoff_read_only_section_name);
19788 private_data_section
19789 = get_unnamed_section (SECTION_WRITE,
19790 rs6000_xcoff_output_readwrite_section_asm_op,
19791 &xcoff_private_data_section_name);
19793 read_only_private_data_section
19794 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
19795 &xcoff_private_data_section_name);
19798 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
19800 readonly_data_section = read_only_data_section;
19801 exception_section = data_section;
19805 rs6000_xcoff_reloc_rw_mask (void)
19811 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
19812 tree decl ATTRIBUTE_UNUSED)
19815 static const char * const suffix[3] = { "PR", "RO", "RW" };
19817 if (flags & SECTION_CODE)
19819 else if (flags & SECTION_WRITE)
19824 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
19825 (flags & SECTION_CODE) ? "." : "",
19826 name, suffix[smclass], flags & SECTION_ENTSIZE);
19830 rs6000_xcoff_select_section (tree decl, int reloc,
19831 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19833 if (decl_readonly_section (decl, reloc))
19835 if (TREE_PUBLIC (decl))
19836 return read_only_data_section;
19838 return read_only_private_data_section;
19842 if (TREE_PUBLIC (decl))
19843 return data_section;
19845 return private_data_section;
19850 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
19854 /* Use select_section for private and uninitialized data. */
19855 if (!TREE_PUBLIC (decl)
19856 || DECL_COMMON (decl)
19857 || DECL_INITIAL (decl) == NULL_TREE
19858 || DECL_INITIAL (decl) == error_mark_node
19859 || (flag_zero_initialized_in_bss
19860 && initializer_zerop (DECL_INITIAL (decl))))
19863 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
19864 name = (*targetm.strip_name_encoding) (name);
19865 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
19868 /* Select section for constant in constant pool.
19870 On RS/6000, all constants are in the private read-only data area.
19871 However, if this is being placed in the TOC it must be output as a
19875 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
19876 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
19878 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19879 return toc_section;
19881 return read_only_private_data_section;
19884 /* Remove any trailing [DS] or the like from the symbol name. */
19886 static const char *
19887 rs6000_xcoff_strip_name_encoding (const char *name)
19892 len = strlen (name);
19893 if (name[len - 1] == ']')
19894 return ggc_alloc_string (name, len - 4);
19899 /* Section attributes. AIX is always PIC. */
19901 static unsigned int
19902 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
19904 unsigned int align;
19905 unsigned int flags = default_section_type_flags (decl, name, reloc);
19907 /* Align to at least UNIT size. */
19908 if (flags & SECTION_CODE)
19909 align = MIN_UNITS_PER_WORD;
19911 /* Increase alignment of large objects if not already stricter. */
19912 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
19913 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
19914 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
19916 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
19919 /* Output at beginning of assembler file.
19921 Initialize the section names for the RS/6000 at this point.
19923 Specify filename, including full path, to assembler.
19925 We want to go into the TOC section so at least one .toc will be emitted.
19926 Also, in order to output proper .bs/.es pairs, we need at least one static
19927 [RW] section emitted.
19929 Finally, declare mcount when profiling to make the assembler happy. */
19932 rs6000_xcoff_file_start (void)
19934 rs6000_gen_section_name (&xcoff_bss_section_name,
19935 main_input_filename, ".bss_");
19936 rs6000_gen_section_name (&xcoff_private_data_section_name,
19937 main_input_filename, ".rw_");
19938 rs6000_gen_section_name (&xcoff_read_only_section_name,
19939 main_input_filename, ".ro_");
19941 fputs ("\t.file\t", asm_out_file);
19942 output_quoted_string (asm_out_file, main_input_filename);
19943 fputc ('\n', asm_out_file);
19944 if (write_symbols != NO_DEBUG)
19945 switch_to_section (private_data_section);
19946 switch_to_section (text_section);
19948 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
19949 rs6000_file_start ();
19952 /* Output at end of assembler file.
19953 On the RS/6000, referencing data should automatically pull in text. */
19956 rs6000_xcoff_file_end (void)
19958 switch_to_section (text_section);
19959 fputs ("_section_.text:\n", asm_out_file);
19960 switch_to_section (data_section);
19961 fputs (TARGET_32BIT
19962 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
19965 #endif /* TARGET_XCOFF */
19967 /* Compute a (partial) cost for rtx X. Return true if the complete
19968 cost has been computed, and false if subexpressions should be
19969 scanned. In either case, *TOTAL contains the cost result. */
19972 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
19974 enum machine_mode mode = GET_MODE (x);
19978 /* On the RS/6000, if it is valid in the insn, it is free. */
19980 if (((outer_code == SET
19981 || outer_code == PLUS
19982 || outer_code == MINUS)
19983 && (satisfies_constraint_I (x)
19984 || satisfies_constraint_L (x)))
19985 || (outer_code == AND
19986 && (satisfies_constraint_K (x)
19988 ? satisfies_constraint_L (x)
19989 : satisfies_constraint_J (x))
19990 || mask_operand (x, mode)
19992 && mask64_operand (x, DImode))))
19993 || ((outer_code == IOR || outer_code == XOR)
19994 && (satisfies_constraint_K (x)
19996 ? satisfies_constraint_L (x)
19997 : satisfies_constraint_J (x))))
19998 || outer_code == ASHIFT
19999 || outer_code == ASHIFTRT
20000 || outer_code == LSHIFTRT
20001 || outer_code == ROTATE
20002 || outer_code == ROTATERT
20003 || outer_code == ZERO_EXTRACT
20004 || (outer_code == MULT
20005 && satisfies_constraint_I (x))
20006 || ((outer_code == DIV || outer_code == UDIV
20007 || outer_code == MOD || outer_code == UMOD)
20008 && exact_log2 (INTVAL (x)) >= 0)
20009 || (outer_code == COMPARE
20010 && (satisfies_constraint_I (x)
20011 || satisfies_constraint_K (x)))
20012 || (outer_code == EQ
20013 && (satisfies_constraint_I (x)
20014 || satisfies_constraint_K (x)
20016 ? satisfies_constraint_L (x)
20017 : satisfies_constraint_J (x))))
20018 || (outer_code == GTU
20019 && satisfies_constraint_I (x))
20020 || (outer_code == LTU
20021 && satisfies_constraint_P (x)))
20026 else if ((outer_code == PLUS
20027 && reg_or_add_cint_operand (x, VOIDmode))
20028 || (outer_code == MINUS
20029 && reg_or_sub_cint_operand (x, VOIDmode))
20030 || ((outer_code == SET
20031 || outer_code == IOR
20032 || outer_code == XOR)
20034 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20036 *total = COSTS_N_INSNS (1);
20042 if (mode == DImode && code == CONST_DOUBLE)
20044 if ((outer_code == IOR || outer_code == XOR)
20045 && CONST_DOUBLE_HIGH (x) == 0
20046 && (CONST_DOUBLE_LOW (x)
20047 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20052 else if ((outer_code == AND && and64_2_operand (x, DImode))
20053 || ((outer_code == SET
20054 || outer_code == IOR
20055 || outer_code == XOR)
20056 && CONST_DOUBLE_HIGH (x) == 0))
20058 *total = COSTS_N_INSNS (1);
20068 /* When optimizing for size, MEM should be slightly more expensive
20069 than generating address, e.g., (plus (reg) (const)).
20070 L1 cache latency is about two instructions. */
20071 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20079 if (mode == DFmode)
20081 if (GET_CODE (XEXP (x, 0)) == MULT)
20083 /* FNMA accounted in outer NEG. */
20084 if (outer_code == NEG)
20085 *total = rs6000_cost->dmul - rs6000_cost->fp;
20087 *total = rs6000_cost->dmul;
20090 *total = rs6000_cost->fp;
20092 else if (mode == SFmode)
20094 /* FNMA accounted in outer NEG. */
20095 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20098 *total = rs6000_cost->fp;
20101 *total = COSTS_N_INSNS (1);
20105 if (mode == DFmode)
20107 if (GET_CODE (XEXP (x, 0)) == MULT
20108 || GET_CODE (XEXP (x, 1)) == MULT)
20110 /* FNMA accounted in outer NEG. */
20111 if (outer_code == NEG)
20112 *total = rs6000_cost->dmul - rs6000_cost->fp;
20114 *total = rs6000_cost->dmul;
20117 *total = rs6000_cost->fp;
20119 else if (mode == SFmode)
20121 /* FNMA accounted in outer NEG. */
20122 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20125 *total = rs6000_cost->fp;
20128 *total = COSTS_N_INSNS (1);
20132 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20133 && satisfies_constraint_I (XEXP (x, 1)))
20135 if (INTVAL (XEXP (x, 1)) >= -256
20136 && INTVAL (XEXP (x, 1)) <= 255)
20137 *total = rs6000_cost->mulsi_const9;
20139 *total = rs6000_cost->mulsi_const;
20141 /* FMA accounted in outer PLUS/MINUS. */
20142 else if ((mode == DFmode || mode == SFmode)
20143 && (outer_code == PLUS || outer_code == MINUS))
20145 else if (mode == DFmode)
20146 *total = rs6000_cost->dmul;
20147 else if (mode == SFmode)
20148 *total = rs6000_cost->fp;
20149 else if (mode == DImode)
20150 *total = rs6000_cost->muldi;
20152 *total = rs6000_cost->mulsi;
20157 if (FLOAT_MODE_P (mode))
20159 *total = mode == DFmode ? rs6000_cost->ddiv
20160 : rs6000_cost->sdiv;
20167 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20168 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20170 if (code == DIV || code == MOD)
20172 *total = COSTS_N_INSNS (2);
20175 *total = COSTS_N_INSNS (1);
20179 if (GET_MODE (XEXP (x, 1)) == DImode)
20180 *total = rs6000_cost->divdi;
20182 *total = rs6000_cost->divsi;
20184 /* Add in shift and subtract for MOD. */
20185 if (code == MOD || code == UMOD)
20186 *total += COSTS_N_INSNS (2);
20190 *total = COSTS_N_INSNS (4);
20194 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20205 *total = COSTS_N_INSNS (1);
20213 /* Handle mul_highpart. */
20214 if (outer_code == TRUNCATE
20215 && GET_CODE (XEXP (x, 0)) == MULT)
20217 if (mode == DImode)
20218 *total = rs6000_cost->muldi;
20220 *total = rs6000_cost->mulsi;
20223 else if (outer_code == AND)
20226 *total = COSTS_N_INSNS (1);
20231 if (GET_CODE (XEXP (x, 0)) == MEM)
20234 *total = COSTS_N_INSNS (1);
20240 if (!FLOAT_MODE_P (mode))
20242 *total = COSTS_N_INSNS (1);
20248 case UNSIGNED_FLOAT:
20251 case FLOAT_TRUNCATE:
20252 *total = rs6000_cost->fp;
20256 if (mode == DFmode)
20259 *total = rs6000_cost->fp;
20263 switch (XINT (x, 1))
20266 *total = rs6000_cost->fp;
20278 *total = COSTS_N_INSNS (1);
20281 else if (FLOAT_MODE_P (mode)
20282 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20284 *total = rs6000_cost->fp;
20292 /* Carry bit requires mode == Pmode.
20293 NEG or PLUS already counted so only add one. */
20295 && (outer_code == NEG || outer_code == PLUS))
20297 *total = COSTS_N_INSNS (1);
20300 if (outer_code == SET)
20302 if (XEXP (x, 1) == const0_rtx)
20304 *total = COSTS_N_INSNS (2);
20307 else if (mode == Pmode)
20309 *total = COSTS_N_INSNS (3);
20318 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20320 *total = COSTS_N_INSNS (2);
20324 if (outer_code == COMPARE)
20338 /* A C expression returning the cost of moving data from a register of class
20339 CLASS1 to one of CLASS2. */
20342 rs6000_register_move_cost (enum machine_mode mode,
20343 enum reg_class from, enum reg_class to)
20345 /* Moves from/to GENERAL_REGS. */
20346 if (reg_classes_intersect_p (to, GENERAL_REGS)
20347 || reg_classes_intersect_p (from, GENERAL_REGS))
20349 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20352 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20353 return (rs6000_memory_move_cost (mode, from, 0)
20354 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20356 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20358 else if (from == CR_REGS)
20362 /* A move will cost one instruction per GPR moved. */
20363 return 2 * hard_regno_nregs[0][mode];
20366 /* Moving between two similar registers is just one instruction. */
20367 else if (reg_classes_intersect_p (to, from))
20368 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20370 /* Everything else has to go through GENERAL_REGS. */
20372 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20373 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20376 /* A C expressions returning the cost of moving data of MODE from a register to
20380 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20381 int in ATTRIBUTE_UNUSED)
20383 if (reg_classes_intersect_p (class, GENERAL_REGS))
20384 return 4 * hard_regno_nregs[0][mode];
20385 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20386 return 4 * hard_regno_nregs[32][mode];
20387 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20388 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20390 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20393 /* Newton-Raphson approximation of single-precision floating point divide n/d.
20394 Assumes no trapping math and finite arguments. */
20397 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
20399 rtx x0, e0, e1, y1, u0, v0, one;
20401 x0 = gen_reg_rtx (SFmode);
20402 e0 = gen_reg_rtx (SFmode);
20403 e1 = gen_reg_rtx (SFmode);
20404 y1 = gen_reg_rtx (SFmode);
20405 u0 = gen_reg_rtx (SFmode);
20406 v0 = gen_reg_rtx (SFmode);
20407 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
20409 /* x0 = 1./d estimate */
20410 emit_insn (gen_rtx_SET (VOIDmode, x0,
20411 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
20413 /* e0 = 1. - d * x0 */
20414 emit_insn (gen_rtx_SET (VOIDmode, e0,
20415 gen_rtx_MINUS (SFmode, one,
20416 gen_rtx_MULT (SFmode, d, x0))));
20417 /* e1 = e0 + e0 * e0 */
20418 emit_insn (gen_rtx_SET (VOIDmode, e1,
20419 gen_rtx_PLUS (SFmode,
20420 gen_rtx_MULT (SFmode, e0, e0), e0)));
20421 /* y1 = x0 + e1 * x0 */
20422 emit_insn (gen_rtx_SET (VOIDmode, y1,
20423 gen_rtx_PLUS (SFmode,
20424 gen_rtx_MULT (SFmode, e1, x0), x0)));
20426 emit_insn (gen_rtx_SET (VOIDmode, u0,
20427 gen_rtx_MULT (SFmode, n, y1)));
20428 /* v0 = n - d * u0 */
20429 emit_insn (gen_rtx_SET (VOIDmode, v0,
20430 gen_rtx_MINUS (SFmode, n,
20431 gen_rtx_MULT (SFmode, d, u0))));
20432 /* res = u0 + v0 * y1 */
20433 emit_insn (gen_rtx_SET (VOIDmode, res,
20434 gen_rtx_PLUS (SFmode,
20435 gen_rtx_MULT (SFmode, v0, y1), u0)));
20438 /* Newton-Raphson approximation of double-precision floating point divide n/d.
20439 Assumes no trapping math and finite arguments. */
20442 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
20444 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
20446 x0 = gen_reg_rtx (DFmode);
20447 e0 = gen_reg_rtx (DFmode);
20448 e1 = gen_reg_rtx (DFmode);
20449 e2 = gen_reg_rtx (DFmode);
20450 y1 = gen_reg_rtx (DFmode);
20451 y2 = gen_reg_rtx (DFmode);
20452 y3 = gen_reg_rtx (DFmode);
20453 u0 = gen_reg_rtx (DFmode);
20454 v0 = gen_reg_rtx (DFmode);
20455 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
20457 /* x0 = 1./d estimate */
20458 emit_insn (gen_rtx_SET (VOIDmode, x0,
20459 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
20461 /* e0 = 1. - d * x0 */
20462 emit_insn (gen_rtx_SET (VOIDmode, e0,
20463 gen_rtx_MINUS (DFmode, one,
20464 gen_rtx_MULT (SFmode, d, x0))));
20465 /* y1 = x0 + e0 * x0 */
20466 emit_insn (gen_rtx_SET (VOIDmode, y1,
20467 gen_rtx_PLUS (DFmode,
20468 gen_rtx_MULT (DFmode, e0, x0), x0)));
20470 emit_insn (gen_rtx_SET (VOIDmode, e1,
20471 gen_rtx_MULT (DFmode, e0, e0)));
20472 /* y2 = y1 + e1 * y1 */
20473 emit_insn (gen_rtx_SET (VOIDmode, y2,
20474 gen_rtx_PLUS (DFmode,
20475 gen_rtx_MULT (DFmode, e1, y1), y1)));
20477 emit_insn (gen_rtx_SET (VOIDmode, e2,
20478 gen_rtx_MULT (DFmode, e1, e1)));
20479 /* y3 = y2 + e2 * y2 */
20480 emit_insn (gen_rtx_SET (VOIDmode, y3,
20481 gen_rtx_PLUS (DFmode,
20482 gen_rtx_MULT (DFmode, e2, y2), y2)));
20484 emit_insn (gen_rtx_SET (VOIDmode, u0,
20485 gen_rtx_MULT (DFmode, n, y3)));
20486 /* v0 = n - d * u0 */
20487 emit_insn (gen_rtx_SET (VOIDmode, v0,
20488 gen_rtx_MINUS (DFmode, n,
20489 gen_rtx_MULT (DFmode, d, u0))));
20490 /* res = u0 + v0 * y3 */
20491 emit_insn (gen_rtx_SET (VOIDmode, res,
20492 gen_rtx_PLUS (DFmode,
20493 gen_rtx_MULT (DFmode, v0, y3), u0)));
20497 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
20498 target, and SRC is the argument operand. */
20501 rs6000_emit_popcount (rtx dst, rtx src)
20503 enum machine_mode mode = GET_MODE (dst);
20506 tmp1 = gen_reg_rtx (mode);
20508 if (mode == SImode)
20510 emit_insn (gen_popcntbsi2 (tmp1, src));
20511 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
20513 tmp2 = force_reg (SImode, tmp2);
20514 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
20518 emit_insn (gen_popcntbdi2 (tmp1, src));
20519 tmp2 = expand_mult (DImode, tmp1,
20520 GEN_INT ((HOST_WIDE_INT)
20521 0x01010101 << 32 | 0x01010101),
20523 tmp2 = force_reg (DImode, tmp2);
20524 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
20529 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
20530 target, and SRC is the argument operand. */
20533 rs6000_emit_parity (rtx dst, rtx src)
20535 enum machine_mode mode = GET_MODE (dst);
20538 tmp = gen_reg_rtx (mode);
20539 if (mode == SImode)
20541 /* Is mult+shift >= shift+xor+shift+xor? */
20542 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
20544 rtx tmp1, tmp2, tmp3, tmp4;
20546 tmp1 = gen_reg_rtx (SImode);
20547 emit_insn (gen_popcntbsi2 (tmp1, src));
20549 tmp2 = gen_reg_rtx (SImode);
20550 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
20551 tmp3 = gen_reg_rtx (SImode);
20552 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
20554 tmp4 = gen_reg_rtx (SImode);
20555 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
20556 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
20559 rs6000_emit_popcount (tmp, src);
20560 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
20564 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
20565 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
20567 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
20569 tmp1 = gen_reg_rtx (DImode);
20570 emit_insn (gen_popcntbdi2 (tmp1, src));
20572 tmp2 = gen_reg_rtx (DImode);
20573 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
20574 tmp3 = gen_reg_rtx (DImode);
20575 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
20577 tmp4 = gen_reg_rtx (DImode);
20578 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
20579 tmp5 = gen_reg_rtx (DImode);
20580 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
20582 tmp6 = gen_reg_rtx (DImode);
20583 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
20584 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
20587 rs6000_emit_popcount (tmp, src);
20588 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
20592 /* Return an RTX representing where to find the function value of a
20593 function returning MODE. */
20595 rs6000_complex_function_value (enum machine_mode mode)
20597 unsigned int regno;
20599 enum machine_mode inner = GET_MODE_INNER (mode);
20600 unsigned int inner_bytes = GET_MODE_SIZE (inner);
20602 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
20603 regno = FP_ARG_RETURN;
20606 regno = GP_ARG_RETURN;
20608 /* 32-bit is OK since it'll go in r3/r4. */
20609 if (TARGET_32BIT && inner_bytes >= 4)
20610 return gen_rtx_REG (mode, regno);
20613 if (inner_bytes >= 8)
20614 return gen_rtx_REG (mode, regno);
20616 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
20618 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
20619 GEN_INT (inner_bytes));
20620 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
20623 /* Define how to find the value returned by a function.
20624 VALTYPE is the data type of the value (as a tree).
20625 If the precise function being called is known, FUNC is its FUNCTION_DECL;
20626 otherwise, FUNC is 0.
20628 On the SPE, both FPs and vectors are returned in r3.
20630 On RS/6000 an integer value is in r3 and a floating-point value is in
20631 fp1, unless -msoft-float. */
20634 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
20636 enum machine_mode mode;
20637 unsigned int regno;
20639 /* Special handling for structs in darwin64. */
20640 if (rs6000_darwin64_abi
20641 && TYPE_MODE (valtype) == BLKmode
20642 && TREE_CODE (valtype) == RECORD_TYPE
20643 && int_size_in_bytes (valtype) > 0)
20645 CUMULATIVE_ARGS valcum;
20649 valcum.fregno = FP_ARG_MIN_REG;
20650 valcum.vregno = ALTIVEC_ARG_MIN_REG;
20651 /* Do a trial code generation as if this were going to be passed as
20652 an argument; if any part goes in memory, we return NULL. */
20653 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
20656 /* Otherwise fall through to standard ABI rules. */
20659 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
20661 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20662 return gen_rtx_PARALLEL (DImode,
20664 gen_rtx_EXPR_LIST (VOIDmode,
20665 gen_rtx_REG (SImode, GP_ARG_RETURN),
20667 gen_rtx_EXPR_LIST (VOIDmode,
20668 gen_rtx_REG (SImode,
20669 GP_ARG_RETURN + 1),
20672 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
20674 return gen_rtx_PARALLEL (DCmode,
20676 gen_rtx_EXPR_LIST (VOIDmode,
20677 gen_rtx_REG (SImode, GP_ARG_RETURN),
20679 gen_rtx_EXPR_LIST (VOIDmode,
20680 gen_rtx_REG (SImode,
20681 GP_ARG_RETURN + 1),
20683 gen_rtx_EXPR_LIST (VOIDmode,
20684 gen_rtx_REG (SImode,
20685 GP_ARG_RETURN + 2),
20687 gen_rtx_EXPR_LIST (VOIDmode,
20688 gen_rtx_REG (SImode,
20689 GP_ARG_RETURN + 3),
20693 mode = TYPE_MODE (valtype);
20694 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
20695 || POINTER_TYPE_P (valtype))
20696 mode = TARGET_32BIT ? SImode : DImode;
20698 if (DECIMAL_FLOAT_MODE_P (mode))
20700 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20705 gcc_unreachable ();
20707 regno = GP_ARG_RETURN;
20710 regno = FP_ARG_RETURN;
20713 /* Use f2:f3 specified by the ABI. */
20714 regno = FP_ARG_RETURN + 1;
20719 regno = GP_ARG_RETURN;
20721 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
20722 regno = FP_ARG_RETURN;
20723 else if (TREE_CODE (valtype) == COMPLEX_TYPE
20724 && targetm.calls.split_complex_arg)
20725 return rs6000_complex_function_value (mode);
20726 else if (TREE_CODE (valtype) == VECTOR_TYPE
20727 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
20728 && ALTIVEC_VECTOR_MODE (mode))
20729 regno = ALTIVEC_ARG_RETURN;
20730 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20731 && (mode == DFmode || mode == DCmode
20732 || mode == TFmode || mode == TCmode))
20733 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20735 regno = GP_ARG_RETURN;
20737 return gen_rtx_REG (mode, regno);
20740 /* Define how to find the value returned by a library function
20741 assuming the value has mode MODE. */
20743 rs6000_libcall_value (enum machine_mode mode)
20745 unsigned int regno;
20747 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
20749 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
20750 return gen_rtx_PARALLEL (DImode,
20752 gen_rtx_EXPR_LIST (VOIDmode,
20753 gen_rtx_REG (SImode, GP_ARG_RETURN),
20755 gen_rtx_EXPR_LIST (VOIDmode,
20756 gen_rtx_REG (SImode,
20757 GP_ARG_RETURN + 1),
20761 if (DECIMAL_FLOAT_MODE_P (mode))
20763 if (TARGET_HARD_FLOAT && TARGET_FPRS)
20768 gcc_unreachable ();
20770 regno = GP_ARG_RETURN;
20773 regno = FP_ARG_RETURN;
20776 /* Use f2:f3 specified by the ABI. */
20777 regno = FP_ARG_RETURN + 1;
20782 regno = GP_ARG_RETURN;
20784 else if (SCALAR_FLOAT_MODE_P (mode)
20785 && TARGET_HARD_FLOAT && TARGET_FPRS)
20786 regno = FP_ARG_RETURN;
20787 else if (ALTIVEC_VECTOR_MODE (mode)
20788 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
20789 regno = ALTIVEC_ARG_RETURN;
20790 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
20791 return rs6000_complex_function_value (mode);
20792 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
20793 && (mode == DFmode || mode == DCmode
20794 || mode == TFmode || mode == TCmode))
20795 return spe_build_register_parallel (mode, GP_ARG_RETURN);
20797 regno = GP_ARG_RETURN;
20799 return gen_rtx_REG (mode, regno);
20802 /* Define the offset between two registers, FROM to be eliminated and its
20803 replacement TO, at the start of a routine. */
20805 rs6000_initial_elimination_offset (int from, int to)
20807 rs6000_stack_t *info = rs6000_stack_info ();
20808 HOST_WIDE_INT offset;
20810 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20811 offset = info->push_p ? 0 : -info->total_size;
20812 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20814 offset = info->push_p ? 0 : -info->total_size;
20815 if (FRAME_GROWS_DOWNWARD)
20816 offset += info->fixed_size + info->vars_size + info->parm_size;
20818 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20819 offset = FRAME_GROWS_DOWNWARD
20820 ? info->fixed_size + info->vars_size + info->parm_size
20822 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
20823 offset = info->total_size;
20824 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
20825 offset = info->push_p ? info->total_size : 0;
20826 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
20829 gcc_unreachable ();
20834 /* Return true if TYPE is a SPE or AltiVec opaque type. */
20837 rs6000_is_opaque_type (tree type)
20839 return (type == opaque_V2SI_type_node
20840 || type == opaque_V2SF_type_node
20841 || type == opaque_p_V2SI_type_node
20842 || type == opaque_V4SI_type_node);
20846 rs6000_dwarf_register_span (rtx reg)
20851 && (SPE_VECTOR_MODE (GET_MODE (reg))
20852 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
20857 regno = REGNO (reg);
20859 /* The duality of the SPE register size wreaks all kinds of havoc.
20860 This is a way of distinguishing r0 in 32-bits from r0 in
20863 gen_rtx_PARALLEL (VOIDmode,
20866 gen_rtx_REG (SImode, regno + 1200),
20867 gen_rtx_REG (SImode, regno))
20869 gen_rtx_REG (SImode, regno),
20870 gen_rtx_REG (SImode, regno + 1200)));
20873 /* Fill in sizes for SPE register high parts in table used by unwinder. */
20876 rs6000_init_dwarf_reg_sizes_extra (tree address)
20881 enum machine_mode mode = TYPE_MODE (char_type_node);
20882 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
20883 rtx mem = gen_rtx_MEM (BLKmode, addr);
20884 rtx value = gen_int_mode (4, mode);
20886 for (i = 1201; i < 1232; i++)
20888 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
20889 HOST_WIDE_INT offset
20890 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
20892 emit_move_insn (adjust_address (mem, mode, offset), value);
20897 /* Map internal gcc register numbers to DWARF2 register numbers. */
20900 rs6000_dbx_register_number (unsigned int regno)
20902 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
20904 if (regno == MQ_REGNO)
20906 if (regno == LR_REGNO)
20908 if (regno == CTR_REGNO)
20910 if (CR_REGNO_P (regno))
20911 return regno - CR0_REGNO + 86;
20912 if (regno == XER_REGNO)
20914 if (ALTIVEC_REGNO_P (regno))
20915 return regno - FIRST_ALTIVEC_REGNO + 1124;
20916 if (regno == VRSAVE_REGNO)
20918 if (regno == VSCR_REGNO)
20920 if (regno == SPE_ACC_REGNO)
20922 if (regno == SPEFSCR_REGNO)
20924 /* SPE high reg number. We get these values of regno from
20925 rs6000_dwarf_register_span. */
20926 gcc_assert (regno >= 1200 && regno < 1232);
20930 /* target hook eh_return_filter_mode */
20931 static enum machine_mode
20932 rs6000_eh_return_filter_mode (void)
20934 return TARGET_32BIT ? SImode : word_mode;
20937 /* Target hook for scalar_mode_supported_p. */
20939 rs6000_scalar_mode_supported_p (enum machine_mode mode)
20941 if (DECIMAL_FLOAT_MODE_P (mode))
20944 return default_scalar_mode_supported_p (mode);
20947 /* Target hook for vector_mode_supported_p. */
20949 rs6000_vector_mode_supported_p (enum machine_mode mode)
20952 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
20955 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
20962 /* Target hook for invalid_arg_for_unprototyped_fn. */
20963 static const char *
20964 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
20966 return (!rs6000_darwin64_abi
20968 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
20969 && (funcdecl == NULL_TREE
20970 || (TREE_CODE (funcdecl) == FUNCTION_DECL
20971 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
20972 ? N_("AltiVec argument passed to unprototyped function")
20976 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
20977 setup by using __stack_chk_fail_local hidden function instead of
20978 calling __stack_chk_fail directly. Otherwise it is better to call
20979 __stack_chk_fail directly. */
20982 rs6000_stack_protect_fail (void)
20984 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
20985 ? default_hidden_stack_protect_fail ()
20986 : default_external_stack_protect_fail ();
20989 #include "gt-rs6000.h"