1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
5 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it
10 under the terms of the GNU General Public License as published
11 by the Free Software Foundation; either version 3, or (at your
12 option) any later version.
14 GCC is distributed in the hope that it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
17 License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "tm-constrs.h"
60 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
63 #include "gstab.h" /* for N_SLINE */
66 #ifndef TARGET_NO_PROTOTYPE
67 #define TARGET_NO_PROTOTYPE 0
70 #define min(A,B) ((A) < (B) ? (A) : (B))
71 #define max(A,B) ((A) > (B) ? (A) : (B))
73 /* Structure used to define the rs6000 stack */
74 typedef struct rs6000_stack {
75 int first_gp_reg_save; /* first callee saved GP register used */
76 int first_fp_reg_save; /* first callee saved FP register used */
77 int first_altivec_reg_save; /* first callee saved AltiVec register used */
78 int lr_save_p; /* true if the link reg needs to be saved */
79 int cr_save_p; /* true if the CR reg needs to be saved */
80 unsigned int vrsave_mask; /* mask of vec registers to save */
81 int push_p; /* true if we need to allocate stack space */
82 int calls_p; /* true if the function makes any calls */
83 int world_save_p; /* true if we're saving *everything*:
84 r13-r31, cr, f14-f31, vrsave, v20-v31 */
85 enum rs6000_abi abi; /* which ABI to use */
86 int gp_save_offset; /* offset to save GP regs from initial SP */
87 int fp_save_offset; /* offset to save FP regs from initial SP */
88 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
89 int lr_save_offset; /* offset to save LR from initial SP */
90 int cr_save_offset; /* offset to save CR from initial SP */
91 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
92 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int vrsave_size; /* size to hold VRSAVE if not in save_size */
105 int altivec_padding_size; /* size of altivec alignment padding if
107 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
108 int spe_padding_size;
109 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
110 int spe_64bit_regs_used;
113 /* A C structure for machine-specific, per-function data.
114 This is added to the cfun structure. */
115 typedef struct machine_function GTY(())
117 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
118 int ra_needs_full_frame;
119 /* Some local-dynamic symbol. */
120 const char *some_ld_name;
121 /* Whether the instruction chain has been scanned already. */
122 int insn_chain_scanned_p;
123 /* Flags if __builtin_return_address (0) was used. */
125 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
126 varargs save area. */
127 HOST_WIDE_INT varargs_save_offset;
130 /* Target cpu type */
132 enum processor_type rs6000_cpu;
133 struct rs6000_cpu_select rs6000_select[3] =
135 /* switch name, tune arch */
136 { (const char *)0, "--with-cpu=", 1, 1 },
137 { (const char *)0, "-mcpu=", 1, 1 },
138 { (const char *)0, "-mtune=", 1, 0 },
141 static GTY(()) bool rs6000_cell_dont_microcode;
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Align branch targets. */
150 static GTY(()) bool rs6000_align_branch_targets;
152 /* Support for -msched-costly-dep option. */
153 const char *rs6000_sched_costly_dep_str;
154 enum rs6000_dependence_cost rs6000_sched_costly_dep;
156 /* Support for -minsert-sched-nops option. */
157 const char *rs6000_sched_insert_nops_str;
158 enum rs6000_nop_insertion rs6000_sched_insert_nops;
160 /* Support targetm.vectorize.builtin_mask_for_load. */
161 static GTY(()) tree altivec_builtin_mask_for_load;
163 /* Size of long double. */
164 int rs6000_long_double_type_size;
166 /* IEEE quad extended precision long double. */
169 /* Whether -mabi=altivec has appeared. */
170 int rs6000_altivec_abi;
172 /* Nonzero if we want SPE ABI extensions. */
175 /* Nonzero if floating point operations are done in the GPRs. */
176 int rs6000_float_gprs = 0;
178 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
179 int rs6000_darwin64_abi;
181 /* Set to nonzero once AIX common-mode calls have been defined. */
182 static GTY(()) int common_mode_defined;
184 /* Save information from a "cmpxx" operation until the branch or scc is
186 rtx rs6000_compare_op0, rs6000_compare_op1;
187 int rs6000_compare_fp_p;
189 /* Label number of label created for -mrelocatable, to call to so we can
190 get the address of the GOT section */
191 int rs6000_pic_labelno;
194 /* Which abi to adhere to */
195 const char *rs6000_abi_name;
197 /* Semantics of the small data area */
198 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
200 /* Which small data model to use */
201 const char *rs6000_sdata_name = (char *)0;
203 /* Counter for labels which are to be placed in .fixup. */
204 int fixuplabelno = 0;
207 /* Bit size of immediate TLS offsets and string from which it is decoded. */
208 int rs6000_tls_size = 32;
209 const char *rs6000_tls_size_string;
211 /* ABI enumeration available for subtarget to use. */
212 enum rs6000_abi rs6000_current_abi;
214 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
218 const char *rs6000_debug_name;
219 int rs6000_debug_stack; /* debug stack applications */
220 int rs6000_debug_arg; /* debug argument handling */
222 /* Value is TRUE if register/mode pair is acceptable. */
223 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
225 /* Built in types. */
227 tree rs6000_builtin_types[RS6000_BTI_MAX];
228 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
230 const char *rs6000_traceback_name;
232 traceback_default = 0,
238 /* Flag to say the TOC is initialized */
240 char toc_label_name[10];
242 /* Cached value of rs6000_variable_issue. This is cached in
243 rs6000_variable_issue hook and returned from rs6000_sched_reorder2. */
244 static short cached_can_issue_more;
246 static GTY(()) section *read_only_data_section;
247 static GTY(()) section *private_data_section;
248 static GTY(()) section *read_only_private_data_section;
249 static GTY(()) section *sdata2_section;
250 static GTY(()) section *toc_section;
252 /* Control alignment for fields within structures. */
253 /* String from -malign-XXXXX. */
254 int rs6000_alignment_flags;
256 /* True for any options that were explicitly set. */
258 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
259 bool alignment; /* True if -malign- was used. */
260 bool abi; /* True if -mabi=spe/nospe was used. */
261 bool spe; /* True if -mspe= was used. */
262 bool float_gprs; /* True if -mfloat-gprs= was used. */
263 bool isel; /* True if -misel was used. */
264 bool long_double; /* True if -mlong-double- was used. */
265 bool ieee; /* True if -mabi=ieee/ibmlongdouble used. */
266 } rs6000_explicit_options;
268 struct builtin_description
270 /* mask is not const because we're going to alter it below. This
271 nonsense will go away when we rewrite the -march infrastructure
272 to give us more target flag bits. */
274 const enum insn_code icode;
275 const char *const name;
276 const enum rs6000_builtins code;
279 /* Target cpu costs. */
281 struct processor_costs {
282 const int mulsi; /* cost of SImode multiplication. */
283 const int mulsi_const; /* cost of SImode multiplication by constant. */
284 const int mulsi_const9; /* cost of SImode mult by short constant. */
285 const int muldi; /* cost of DImode multiplication. */
286 const int divsi; /* cost of SImode division. */
287 const int divdi; /* cost of DImode division. */
288 const int fp; /* cost of simple SFmode and DFmode insns. */
289 const int dmul; /* cost of DFmode multiplication (and fmadd). */
290 const int sdiv; /* cost of SFmode division (fdivs). */
291 const int ddiv; /* cost of DFmode division (fdiv). */
292 const int cache_line_size; /* cache line size in bytes. */
293 const int l1_cache_size; /* size of l1 cache, in kilobytes. */
294 const int l2_cache_size; /* size of l2 cache, in kilobytes. */
295 const int simultaneous_prefetches; /* number of parallel prefetch
299 const struct processor_costs *rs6000_cost;
301 /* Processor costs (relative to an add) */
303 /* Instruction size costs on 32bit processors. */
305 struct processor_costs size32_cost = {
306 COSTS_N_INSNS (1), /* mulsi */
307 COSTS_N_INSNS (1), /* mulsi_const */
308 COSTS_N_INSNS (1), /* mulsi_const9 */
309 COSTS_N_INSNS (1), /* muldi */
310 COSTS_N_INSNS (1), /* divsi */
311 COSTS_N_INSNS (1), /* divdi */
312 COSTS_N_INSNS (1), /* fp */
313 COSTS_N_INSNS (1), /* dmul */
314 COSTS_N_INSNS (1), /* sdiv */
315 COSTS_N_INSNS (1), /* ddiv */
322 /* Instruction size costs on 64bit processors. */
324 struct processor_costs size64_cost = {
325 COSTS_N_INSNS (1), /* mulsi */
326 COSTS_N_INSNS (1), /* mulsi_const */
327 COSTS_N_INSNS (1), /* mulsi_const9 */
328 COSTS_N_INSNS (1), /* muldi */
329 COSTS_N_INSNS (1), /* divsi */
330 COSTS_N_INSNS (1), /* divdi */
331 COSTS_N_INSNS (1), /* fp */
332 COSTS_N_INSNS (1), /* dmul */
333 COSTS_N_INSNS (1), /* sdiv */
334 COSTS_N_INSNS (1), /* ddiv */
341 /* Instruction costs on RIOS1 processors. */
343 struct processor_costs rios1_cost = {
344 COSTS_N_INSNS (5), /* mulsi */
345 COSTS_N_INSNS (4), /* mulsi_const */
346 COSTS_N_INSNS (3), /* mulsi_const9 */
347 COSTS_N_INSNS (5), /* muldi */
348 COSTS_N_INSNS (19), /* divsi */
349 COSTS_N_INSNS (19), /* divdi */
350 COSTS_N_INSNS (2), /* fp */
351 COSTS_N_INSNS (2), /* dmul */
352 COSTS_N_INSNS (19), /* sdiv */
353 COSTS_N_INSNS (19), /* ddiv */
360 /* Instruction costs on RIOS2 processors. */
362 struct processor_costs rios2_cost = {
363 COSTS_N_INSNS (2), /* mulsi */
364 COSTS_N_INSNS (2), /* mulsi_const */
365 COSTS_N_INSNS (2), /* mulsi_const9 */
366 COSTS_N_INSNS (2), /* muldi */
367 COSTS_N_INSNS (13), /* divsi */
368 COSTS_N_INSNS (13), /* divdi */
369 COSTS_N_INSNS (2), /* fp */
370 COSTS_N_INSNS (2), /* dmul */
371 COSTS_N_INSNS (17), /* sdiv */
372 COSTS_N_INSNS (17), /* ddiv */
379 /* Instruction costs on RS64A processors. */
381 struct processor_costs rs64a_cost = {
382 COSTS_N_INSNS (20), /* mulsi */
383 COSTS_N_INSNS (12), /* mulsi_const */
384 COSTS_N_INSNS (8), /* mulsi_const9 */
385 COSTS_N_INSNS (34), /* muldi */
386 COSTS_N_INSNS (65), /* divsi */
387 COSTS_N_INSNS (67), /* divdi */
388 COSTS_N_INSNS (4), /* fp */
389 COSTS_N_INSNS (4), /* dmul */
390 COSTS_N_INSNS (31), /* sdiv */
391 COSTS_N_INSNS (31), /* ddiv */
398 /* Instruction costs on MPCCORE processors. */
400 struct processor_costs mpccore_cost = {
401 COSTS_N_INSNS (2), /* mulsi */
402 COSTS_N_INSNS (2), /* mulsi_const */
403 COSTS_N_INSNS (2), /* mulsi_const9 */
404 COSTS_N_INSNS (2), /* muldi */
405 COSTS_N_INSNS (6), /* divsi */
406 COSTS_N_INSNS (6), /* divdi */
407 COSTS_N_INSNS (4), /* fp */
408 COSTS_N_INSNS (5), /* dmul */
409 COSTS_N_INSNS (10), /* sdiv */
410 COSTS_N_INSNS (17), /* ddiv */
417 /* Instruction costs on PPC403 processors. */
419 struct processor_costs ppc403_cost = {
420 COSTS_N_INSNS (4), /* mulsi */
421 COSTS_N_INSNS (4), /* mulsi_const */
422 COSTS_N_INSNS (4), /* mulsi_const9 */
423 COSTS_N_INSNS (4), /* muldi */
424 COSTS_N_INSNS (33), /* divsi */
425 COSTS_N_INSNS (33), /* divdi */
426 COSTS_N_INSNS (11), /* fp */
427 COSTS_N_INSNS (11), /* dmul */
428 COSTS_N_INSNS (11), /* sdiv */
429 COSTS_N_INSNS (11), /* ddiv */
436 /* Instruction costs on PPC405 processors. */
438 struct processor_costs ppc405_cost = {
439 COSTS_N_INSNS (5), /* mulsi */
440 COSTS_N_INSNS (4), /* mulsi_const */
441 COSTS_N_INSNS (3), /* mulsi_const9 */
442 COSTS_N_INSNS (5), /* muldi */
443 COSTS_N_INSNS (35), /* divsi */
444 COSTS_N_INSNS (35), /* divdi */
445 COSTS_N_INSNS (11), /* fp */
446 COSTS_N_INSNS (11), /* dmul */
447 COSTS_N_INSNS (11), /* sdiv */
448 COSTS_N_INSNS (11), /* ddiv */
455 /* Instruction costs on PPC440 processors. */
457 struct processor_costs ppc440_cost = {
458 COSTS_N_INSNS (3), /* mulsi */
459 COSTS_N_INSNS (2), /* mulsi_const */
460 COSTS_N_INSNS (2), /* mulsi_const9 */
461 COSTS_N_INSNS (3), /* muldi */
462 COSTS_N_INSNS (34), /* divsi */
463 COSTS_N_INSNS (34), /* divdi */
464 COSTS_N_INSNS (5), /* fp */
465 COSTS_N_INSNS (5), /* dmul */
466 COSTS_N_INSNS (19), /* sdiv */
467 COSTS_N_INSNS (33), /* ddiv */
474 /* Instruction costs on PPC601 processors. */
476 struct processor_costs ppc601_cost = {
477 COSTS_N_INSNS (5), /* mulsi */
478 COSTS_N_INSNS (5), /* mulsi_const */
479 COSTS_N_INSNS (5), /* mulsi_const9 */
480 COSTS_N_INSNS (5), /* muldi */
481 COSTS_N_INSNS (36), /* divsi */
482 COSTS_N_INSNS (36), /* divdi */
483 COSTS_N_INSNS (4), /* fp */
484 COSTS_N_INSNS (5), /* dmul */
485 COSTS_N_INSNS (17), /* sdiv */
486 COSTS_N_INSNS (31), /* ddiv */
493 /* Instruction costs on PPC603 processors. */
495 struct processor_costs ppc603_cost = {
496 COSTS_N_INSNS (5), /* mulsi */
497 COSTS_N_INSNS (3), /* mulsi_const */
498 COSTS_N_INSNS (2), /* mulsi_const9 */
499 COSTS_N_INSNS (5), /* muldi */
500 COSTS_N_INSNS (37), /* divsi */
501 COSTS_N_INSNS (37), /* divdi */
502 COSTS_N_INSNS (3), /* fp */
503 COSTS_N_INSNS (4), /* dmul */
504 COSTS_N_INSNS (18), /* sdiv */
505 COSTS_N_INSNS (33), /* ddiv */
512 /* Instruction costs on PPC604 processors. */
514 struct processor_costs ppc604_cost = {
515 COSTS_N_INSNS (4), /* mulsi */
516 COSTS_N_INSNS (4), /* mulsi_const */
517 COSTS_N_INSNS (4), /* mulsi_const9 */
518 COSTS_N_INSNS (4), /* muldi */
519 COSTS_N_INSNS (20), /* divsi */
520 COSTS_N_INSNS (20), /* divdi */
521 COSTS_N_INSNS (3), /* fp */
522 COSTS_N_INSNS (3), /* dmul */
523 COSTS_N_INSNS (18), /* sdiv */
524 COSTS_N_INSNS (32), /* ddiv */
531 /* Instruction costs on PPC604e processors. */
533 struct processor_costs ppc604e_cost = {
534 COSTS_N_INSNS (2), /* mulsi */
535 COSTS_N_INSNS (2), /* mulsi_const */
536 COSTS_N_INSNS (2), /* mulsi_const9 */
537 COSTS_N_INSNS (2), /* muldi */
538 COSTS_N_INSNS (20), /* divsi */
539 COSTS_N_INSNS (20), /* divdi */
540 COSTS_N_INSNS (3), /* fp */
541 COSTS_N_INSNS (3), /* dmul */
542 COSTS_N_INSNS (18), /* sdiv */
543 COSTS_N_INSNS (32), /* ddiv */
550 /* Instruction costs on PPC620 processors. */
552 struct processor_costs ppc620_cost = {
553 COSTS_N_INSNS (5), /* mulsi */
554 COSTS_N_INSNS (4), /* mulsi_const */
555 COSTS_N_INSNS (3), /* mulsi_const9 */
556 COSTS_N_INSNS (7), /* muldi */
557 COSTS_N_INSNS (21), /* divsi */
558 COSTS_N_INSNS (37), /* divdi */
559 COSTS_N_INSNS (3), /* fp */
560 COSTS_N_INSNS (3), /* dmul */
561 COSTS_N_INSNS (18), /* sdiv */
562 COSTS_N_INSNS (32), /* ddiv */
569 /* Instruction costs on PPC630 processors. */
571 struct processor_costs ppc630_cost = {
572 COSTS_N_INSNS (5), /* mulsi */
573 COSTS_N_INSNS (4), /* mulsi_const */
574 COSTS_N_INSNS (3), /* mulsi_const9 */
575 COSTS_N_INSNS (7), /* muldi */
576 COSTS_N_INSNS (21), /* divsi */
577 COSTS_N_INSNS (37), /* divdi */
578 COSTS_N_INSNS (3), /* fp */
579 COSTS_N_INSNS (3), /* dmul */
580 COSTS_N_INSNS (17), /* sdiv */
581 COSTS_N_INSNS (21), /* ddiv */
588 /* Instruction costs on Cell processor. */
589 /* COSTS_N_INSNS (1) ~ one add. */
591 struct processor_costs ppccell_cost = {
592 COSTS_N_INSNS (9/2)+2, /* mulsi */
593 COSTS_N_INSNS (6/2), /* mulsi_const */
594 COSTS_N_INSNS (6/2), /* mulsi_const9 */
595 COSTS_N_INSNS (15/2)+2, /* muldi */
596 COSTS_N_INSNS (38/2), /* divsi */
597 COSTS_N_INSNS (70/2), /* divdi */
598 COSTS_N_INSNS (10/2), /* fp */
599 COSTS_N_INSNS (10/2), /* dmul */
600 COSTS_N_INSNS (74/2), /* sdiv */
601 COSTS_N_INSNS (74/2), /* ddiv */
608 /* Instruction costs on PPC750 and PPC7400 processors. */
610 struct processor_costs ppc750_cost = {
611 COSTS_N_INSNS (5), /* mulsi */
612 COSTS_N_INSNS (3), /* mulsi_const */
613 COSTS_N_INSNS (2), /* mulsi_const9 */
614 COSTS_N_INSNS (5), /* muldi */
615 COSTS_N_INSNS (17), /* divsi */
616 COSTS_N_INSNS (17), /* divdi */
617 COSTS_N_INSNS (3), /* fp */
618 COSTS_N_INSNS (3), /* dmul */
619 COSTS_N_INSNS (17), /* sdiv */
620 COSTS_N_INSNS (31), /* ddiv */
627 /* Instruction costs on PPC7450 processors. */
629 struct processor_costs ppc7450_cost = {
630 COSTS_N_INSNS (4), /* mulsi */
631 COSTS_N_INSNS (3), /* mulsi_const */
632 COSTS_N_INSNS (3), /* mulsi_const9 */
633 COSTS_N_INSNS (4), /* muldi */
634 COSTS_N_INSNS (23), /* divsi */
635 COSTS_N_INSNS (23), /* divdi */
636 COSTS_N_INSNS (5), /* fp */
637 COSTS_N_INSNS (5), /* dmul */
638 COSTS_N_INSNS (21), /* sdiv */
639 COSTS_N_INSNS (35), /* ddiv */
646 /* Instruction costs on PPC8540 processors. */
648 struct processor_costs ppc8540_cost = {
649 COSTS_N_INSNS (4), /* mulsi */
650 COSTS_N_INSNS (4), /* mulsi_const */
651 COSTS_N_INSNS (4), /* mulsi_const9 */
652 COSTS_N_INSNS (4), /* muldi */
653 COSTS_N_INSNS (19), /* divsi */
654 COSTS_N_INSNS (19), /* divdi */
655 COSTS_N_INSNS (4), /* fp */
656 COSTS_N_INSNS (4), /* dmul */
657 COSTS_N_INSNS (29), /* sdiv */
658 COSTS_N_INSNS (29), /* ddiv */
662 1, /* prefetch streams /*/
665 /* Instruction costs on POWER4 and POWER5 processors. */
667 struct processor_costs power4_cost = {
668 COSTS_N_INSNS (3), /* mulsi */
669 COSTS_N_INSNS (2), /* mulsi_const */
670 COSTS_N_INSNS (2), /* mulsi_const9 */
671 COSTS_N_INSNS (4), /* muldi */
672 COSTS_N_INSNS (18), /* divsi */
673 COSTS_N_INSNS (34), /* divdi */
674 COSTS_N_INSNS (3), /* fp */
675 COSTS_N_INSNS (3), /* dmul */
676 COSTS_N_INSNS (17), /* sdiv */
677 COSTS_N_INSNS (17), /* ddiv */
681 8, /* prefetch streams /*/
684 /* Instruction costs on POWER6 processors. */
686 struct processor_costs power6_cost = {
687 COSTS_N_INSNS (8), /* mulsi */
688 COSTS_N_INSNS (8), /* mulsi_const */
689 COSTS_N_INSNS (8), /* mulsi_const9 */
690 COSTS_N_INSNS (8), /* muldi */
691 COSTS_N_INSNS (22), /* divsi */
692 COSTS_N_INSNS (28), /* divdi */
693 COSTS_N_INSNS (3), /* fp */
694 COSTS_N_INSNS (3), /* dmul */
695 COSTS_N_INSNS (13), /* sdiv */
696 COSTS_N_INSNS (16), /* ddiv */
700 16, /* prefetch streams */
704 static bool rs6000_function_ok_for_sibcall (tree, tree);
705 static const char *rs6000_invalid_within_doloop (const_rtx);
706 static rtx rs6000_generate_compare (enum rtx_code);
707 static void rs6000_emit_stack_tie (void);
708 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
709 static rtx spe_synthesize_frame_save (rtx);
710 static bool spe_func_has_64bit_regs_p (void);
711 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
713 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
714 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
715 static unsigned rs6000_hash_constant (rtx);
716 static unsigned toc_hash_function (const void *);
717 static int toc_hash_eq (const void *, const void *);
718 static int constant_pool_expr_1 (rtx, int *, int *);
719 static bool constant_pool_expr_p (rtx);
720 static bool legitimate_small_data_p (enum machine_mode, rtx);
721 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
722 static struct machine_function * rs6000_init_machine_status (void);
723 static bool rs6000_assemble_integer (rtx, unsigned int, int);
724 static bool no_global_regs_above (int);
725 #ifdef HAVE_GAS_HIDDEN
726 static void rs6000_assemble_visibility (tree, int);
728 static int rs6000_ra_ever_killed (void);
729 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
730 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
731 static bool rs6000_ms_bitfield_layout_p (const_tree);
732 static tree rs6000_handle_struct_attribute (tree *, tree, tree, int, bool *);
733 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
734 static const char *rs6000_mangle_type (const_tree);
735 extern const struct attribute_spec rs6000_attribute_table[];
736 static void rs6000_set_default_type_attributes (tree);
737 static bool rs6000_reg_live_or_pic_offset_p (int);
738 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
739 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
740 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
742 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
743 static bool rs6000_return_in_memory (const_tree, const_tree);
744 static void rs6000_file_start (void);
746 static int rs6000_elf_reloc_rw_mask (void);
747 static void rs6000_elf_asm_out_constructor (rtx, int);
748 static void rs6000_elf_asm_out_destructor (rtx, int);
749 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
750 static void rs6000_elf_asm_init_sections (void);
751 static section *rs6000_elf_select_rtx_section (enum machine_mode, rtx,
752 unsigned HOST_WIDE_INT);
753 static void rs6000_elf_encode_section_info (tree, rtx, int)
756 static bool rs6000_use_blocks_for_constant_p (enum machine_mode, const_rtx);
758 static void rs6000_xcoff_asm_output_anchor (rtx);
759 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
760 static void rs6000_xcoff_asm_init_sections (void);
761 static int rs6000_xcoff_reloc_rw_mask (void);
762 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
763 static section *rs6000_xcoff_select_section (tree, int,
764 unsigned HOST_WIDE_INT);
765 static void rs6000_xcoff_unique_section (tree, int);
766 static section *rs6000_xcoff_select_rtx_section
767 (enum machine_mode, rtx, unsigned HOST_WIDE_INT);
768 static const char * rs6000_xcoff_strip_name_encoding (const char *);
769 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
770 static void rs6000_xcoff_file_start (void);
771 static void rs6000_xcoff_file_end (void);
773 static int rs6000_variable_issue (FILE *, int, rtx, int);
774 static bool rs6000_rtx_costs (rtx, int, int, int *);
775 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
776 static void rs6000_sched_init (FILE *, int, int);
777 static bool is_microcoded_insn (rtx);
778 static bool is_nonpipeline_insn (rtx);
779 static bool is_cracked_insn (rtx);
780 static bool is_branch_slot_insn (rtx);
781 static bool is_load_insn (rtx);
782 static rtx get_store_dest (rtx pat);
783 static bool is_store_insn (rtx);
784 static bool set_to_load_agen (rtx,rtx);
785 static bool adjacent_mem_locations (rtx,rtx);
786 static int rs6000_adjust_priority (rtx, int);
787 static int rs6000_issue_rate (void);
788 static bool rs6000_is_costly_dependence (dep_t, int, int);
789 static rtx get_next_active_insn (rtx, rtx);
790 static bool insn_terminates_group_p (rtx , enum group_termination);
791 static bool insn_must_be_first_in_group (rtx);
792 static bool insn_must_be_last_in_group (rtx);
793 static bool is_costly_group (rtx *, rtx);
794 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
795 static int redefine_groups (FILE *, int, rtx, rtx);
796 static int pad_groups (FILE *, int, rtx, rtx);
797 static void rs6000_sched_finish (FILE *, int);
798 static int rs6000_sched_reorder (FILE *, int, rtx *, int *, int);
799 static int rs6000_sched_reorder2 (FILE *, int, rtx *, int *, int);
800 static int rs6000_use_sched_lookahead (void);
801 static int rs6000_use_sched_lookahead_guard (rtx);
802 static tree rs6000_builtin_reciprocal (unsigned int, bool, bool);
803 static tree rs6000_builtin_mask_for_load (void);
804 static tree rs6000_builtin_mul_widen_even (tree);
805 static tree rs6000_builtin_mul_widen_odd (tree);
806 static tree rs6000_builtin_conversion (enum tree_code, tree);
808 static void def_builtin (int, const char *, tree, int);
809 static bool rs6000_vector_alignment_reachable (const_tree, bool);
810 static void rs6000_init_builtins (void);
811 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
812 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
813 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
814 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
815 static void altivec_init_builtins (void);
816 static void rs6000_common_init_builtins (void);
817 static void rs6000_init_libfuncs (void);
819 static void paired_init_builtins (void);
820 static rtx paired_expand_builtin (tree, rtx, bool *);
821 static rtx paired_expand_lv_builtin (enum insn_code, tree, rtx);
822 static rtx paired_expand_stv_builtin (enum insn_code, tree);
823 static rtx paired_expand_predicate_builtin (enum insn_code, tree, rtx);
825 static void enable_mask_for_builtins (struct builtin_description *, int,
826 enum rs6000_builtins,
827 enum rs6000_builtins);
828 static tree build_opaque_vector_type (tree, int);
829 static void spe_init_builtins (void);
830 static rtx spe_expand_builtin (tree, rtx, bool *);
831 static rtx spe_expand_stv_builtin (enum insn_code, tree);
832 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
833 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
834 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
835 static rs6000_stack_t *rs6000_stack_info (void);
836 static void debug_stack_info (rs6000_stack_t *);
838 static rtx altivec_expand_builtin (tree, rtx, bool *);
839 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
840 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
841 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
842 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
843 static rtx altivec_expand_predicate_builtin (enum insn_code,
844 const char *, tree, rtx);
845 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
846 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
847 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
848 static rtx altivec_expand_vec_set_builtin (tree);
849 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
850 static int get_element_number (tree, tree);
851 static bool rs6000_handle_option (size_t, const char *, int);
852 static void rs6000_parse_tls_size_option (void);
853 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
854 static int first_altivec_reg_to_save (void);
855 static unsigned int compute_vrsave_mask (void);
856 static void compute_save_world_info (rs6000_stack_t *info_ptr);
857 static void is_altivec_return_reg (rtx, void *);
858 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
859 int easy_vector_constant (rtx, enum machine_mode);
860 static bool rs6000_is_opaque_type (const_tree);
861 static rtx rs6000_dwarf_register_span (rtx);
862 static void rs6000_init_dwarf_reg_sizes_extra (tree);
863 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
864 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
865 static rtx rs6000_tls_get_addr (void);
866 static rtx rs6000_got_sym (void);
867 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
868 static const char *rs6000_get_some_local_dynamic_name (void);
869 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
870 static rtx rs6000_complex_function_value (enum machine_mode);
871 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
872 enum machine_mode, tree);
873 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
875 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
876 tree, HOST_WIDE_INT);
877 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
880 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
881 const_tree, HOST_WIDE_INT,
883 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, const_tree, int, bool);
884 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
885 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
886 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
887 enum machine_mode, tree,
889 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
891 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
893 static const char *invalid_arg_for_unprototyped_fn (const_tree, const_tree, const_tree);
895 static void macho_branch_islands (void);
896 static int no_previous_def (tree function_name);
897 static tree get_prev_label (tree function_name);
898 static void rs6000_darwin_file_start (void);
901 static tree rs6000_build_builtin_va_list (void);
902 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
903 static bool rs6000_must_pass_in_stack (enum machine_mode, const_tree);
904 static bool rs6000_scalar_mode_supported_p (enum machine_mode);
905 static bool rs6000_vector_mode_supported_p (enum machine_mode);
906 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
908 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
910 static int get_vsel_insn (enum machine_mode);
911 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
912 static tree rs6000_stack_protect_fail (void);
914 const int INSN_NOT_AVAILABLE = -1;
915 static enum machine_mode rs6000_eh_return_filter_mode (void);
917 /* Hash table stuff for keeping track of TOC entries. */
919 struct toc_hash_struct GTY(())
921 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
922 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
924 enum machine_mode key_mode;
928 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
930 /* Default register names. */
931 char rs6000_reg_names[][8] =
933 "0", "1", "2", "3", "4", "5", "6", "7",
934 "8", "9", "10", "11", "12", "13", "14", "15",
935 "16", "17", "18", "19", "20", "21", "22", "23",
936 "24", "25", "26", "27", "28", "29", "30", "31",
937 "0", "1", "2", "3", "4", "5", "6", "7",
938 "8", "9", "10", "11", "12", "13", "14", "15",
939 "16", "17", "18", "19", "20", "21", "22", "23",
940 "24", "25", "26", "27", "28", "29", "30", "31",
941 "mq", "lr", "ctr","ap",
942 "0", "1", "2", "3", "4", "5", "6", "7",
944 /* AltiVec registers. */
945 "0", "1", "2", "3", "4", "5", "6", "7",
946 "8", "9", "10", "11", "12", "13", "14", "15",
947 "16", "17", "18", "19", "20", "21", "22", "23",
948 "24", "25", "26", "27", "28", "29", "30", "31",
951 "spe_acc", "spefscr",
952 /* Soft frame pointer. */
956 #ifdef TARGET_REGNAMES
957 static const char alt_reg_names[][8] =
959 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
960 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
961 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
962 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
963 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
964 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
965 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
966 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
967 "mq", "lr", "ctr", "ap",
968 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
970 /* AltiVec registers. */
971 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
972 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
973 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
974 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
977 "spe_acc", "spefscr",
978 /* Soft frame pointer. */
983 #ifndef MASK_STRICT_ALIGN
984 #define MASK_STRICT_ALIGN 0
986 #ifndef TARGET_PROFILE_KERNEL
987 #define TARGET_PROFILE_KERNEL 0
990 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
991 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
993 /* Initialize the GCC target structure. */
994 #undef TARGET_ATTRIBUTE_TABLE
995 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
996 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
997 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
999 #undef TARGET_ASM_ALIGNED_DI_OP
1000 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
1002 /* Default unaligned ops are only provided for ELF. Find the ops needed
1003 for non-ELF systems. */
1004 #ifndef OBJECT_FORMAT_ELF
1006 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
1008 #undef TARGET_ASM_UNALIGNED_HI_OP
1009 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
1010 #undef TARGET_ASM_UNALIGNED_SI_OP
1011 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
1012 #undef TARGET_ASM_UNALIGNED_DI_OP
1013 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
1016 #undef TARGET_ASM_UNALIGNED_HI_OP
1017 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
1018 #undef TARGET_ASM_UNALIGNED_SI_OP
1019 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
1020 #undef TARGET_ASM_UNALIGNED_DI_OP
1021 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
1022 #undef TARGET_ASM_ALIGNED_DI_OP
1023 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
1027 /* This hook deals with fixups for relocatable code and DI-mode objects
1029 #undef TARGET_ASM_INTEGER
1030 #define TARGET_ASM_INTEGER rs6000_assemble_integer
1032 #ifdef HAVE_GAS_HIDDEN
1033 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
1034 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
1037 #undef TARGET_HAVE_TLS
1038 #define TARGET_HAVE_TLS HAVE_AS_TLS
1040 #undef TARGET_CANNOT_FORCE_CONST_MEM
1041 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
1043 #undef TARGET_ASM_FUNCTION_PROLOGUE
1044 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
1045 #undef TARGET_ASM_FUNCTION_EPILOGUE
1046 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
1048 #undef TARGET_SCHED_VARIABLE_ISSUE
1049 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
1051 #undef TARGET_SCHED_ISSUE_RATE
1052 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
1053 #undef TARGET_SCHED_ADJUST_COST
1054 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
1055 #undef TARGET_SCHED_ADJUST_PRIORITY
1056 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
1057 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
1058 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
1059 #undef TARGET_SCHED_INIT
1060 #define TARGET_SCHED_INIT rs6000_sched_init
1061 #undef TARGET_SCHED_FINISH
1062 #define TARGET_SCHED_FINISH rs6000_sched_finish
1063 #undef TARGET_SCHED_REORDER
1064 #define TARGET_SCHED_REORDER rs6000_sched_reorder
1065 #undef TARGET_SCHED_REORDER2
1066 #define TARGET_SCHED_REORDER2 rs6000_sched_reorder2
1068 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
1069 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
1071 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD
1072 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD_GUARD rs6000_use_sched_lookahead_guard
1074 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
1075 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
1076 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN
1077 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_EVEN rs6000_builtin_mul_widen_even
1078 #undef TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD
1079 #define TARGET_VECTORIZE_BUILTIN_MUL_WIDEN_ODD rs6000_builtin_mul_widen_odd
1080 #undef TARGET_VECTORIZE_BUILTIN_CONVERSION
1081 #define TARGET_VECTORIZE_BUILTIN_CONVERSION rs6000_builtin_conversion
1083 #undef TARGET_VECTOR_ALIGNMENT_REACHABLE
1084 #define TARGET_VECTOR_ALIGNMENT_REACHABLE rs6000_vector_alignment_reachable
1086 #undef TARGET_INIT_BUILTINS
1087 #define TARGET_INIT_BUILTINS rs6000_init_builtins
1089 #undef TARGET_EXPAND_BUILTIN
1090 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
1092 #undef TARGET_MANGLE_TYPE
1093 #define TARGET_MANGLE_TYPE rs6000_mangle_type
1095 #undef TARGET_INIT_LIBFUNCS
1096 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
1099 #undef TARGET_BINDS_LOCAL_P
1100 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
1103 #undef TARGET_MS_BITFIELD_LAYOUT_P
1104 #define TARGET_MS_BITFIELD_LAYOUT_P rs6000_ms_bitfield_layout_p
1106 #undef TARGET_ASM_OUTPUT_MI_THUNK
1107 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
1109 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
1110 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true
1112 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
1113 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
1115 #undef TARGET_INVALID_WITHIN_DOLOOP
1116 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
1118 #undef TARGET_RTX_COSTS
1119 #define TARGET_RTX_COSTS rs6000_rtx_costs
1120 #undef TARGET_ADDRESS_COST
1121 #define TARGET_ADDRESS_COST hook_int_rtx_0
1123 #undef TARGET_VECTOR_OPAQUE_P
1124 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
1126 #undef TARGET_DWARF_REGISTER_SPAN
1127 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
1129 #undef TARGET_INIT_DWARF_REG_SIZES_EXTRA
1130 #define TARGET_INIT_DWARF_REG_SIZES_EXTRA rs6000_init_dwarf_reg_sizes_extra
1132 /* On rs6000, function arguments are promoted, as are function return
1134 #undef TARGET_PROMOTE_FUNCTION_ARGS
1135 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
1136 #undef TARGET_PROMOTE_FUNCTION_RETURN
1137 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
1139 #undef TARGET_RETURN_IN_MEMORY
1140 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
1142 #undef TARGET_SETUP_INCOMING_VARARGS
1143 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
1145 /* Always strict argument naming on rs6000. */
1146 #undef TARGET_STRICT_ARGUMENT_NAMING
1147 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
1148 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
1149 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
1150 #undef TARGET_SPLIT_COMPLEX_ARG
1151 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true
1152 #undef TARGET_MUST_PASS_IN_STACK
1153 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
1154 #undef TARGET_PASS_BY_REFERENCE
1155 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
1156 #undef TARGET_ARG_PARTIAL_BYTES
1157 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
1159 #undef TARGET_BUILD_BUILTIN_VA_LIST
1160 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
1162 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
1163 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
1165 #undef TARGET_EH_RETURN_FILTER_MODE
1166 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
1168 #undef TARGET_SCALAR_MODE_SUPPORTED_P
1169 #define TARGET_SCALAR_MODE_SUPPORTED_P rs6000_scalar_mode_supported_p
1171 #undef TARGET_VECTOR_MODE_SUPPORTED_P
1172 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
1174 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
1175 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
1177 #undef TARGET_HANDLE_OPTION
1178 #define TARGET_HANDLE_OPTION rs6000_handle_option
1180 #undef TARGET_DEFAULT_TARGET_FLAGS
1181 #define TARGET_DEFAULT_TARGET_FLAGS \
1184 #undef TARGET_STACK_PROTECT_FAIL
1185 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
1187 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1188 The PowerPC architecture requires only weak consistency among
1189 processors--that is, memory accesses between processors need not be
1190 sequentially consistent and memory accesses among processors can occur
1191 in any order. The ability to order memory accesses weakly provides
1192 opportunities for more efficient use of the system bus. Unless a
1193 dependency exists, the 604e allows read operations to precede store
1195 #undef TARGET_RELAXED_ORDERING
1196 #define TARGET_RELAXED_ORDERING true
1199 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1200 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1203 /* Use a 32-bit anchor range. This leads to sequences like:
1205 addis tmp,anchor,high
1208 where tmp itself acts as an anchor, and can be shared between
1209 accesses to the same 64k page. */
1210 #undef TARGET_MIN_ANCHOR_OFFSET
1211 #define TARGET_MIN_ANCHOR_OFFSET -0x7fffffff - 1
1212 #undef TARGET_MAX_ANCHOR_OFFSET
1213 #define TARGET_MAX_ANCHOR_OFFSET 0x7fffffff
1214 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P
1215 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P rs6000_use_blocks_for_constant_p
1217 #undef TARGET_BUILTIN_RECIPROCAL
1218 #define TARGET_BUILTIN_RECIPROCAL rs6000_builtin_reciprocal
1220 struct gcc_target targetm = TARGET_INITIALIZER;
1223 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1226 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1228 /* The GPRs can hold any mode, but values bigger than one register
1229 cannot go past R31. */
1230 if (INT_REGNO_P (regno))
1231 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1233 /* The float registers can only hold floating modes and DImode.
1234 This excludes the 32-bit decimal float mode for now. */
1235 if (FP_REGNO_P (regno))
1237 ((SCALAR_FLOAT_MODE_P (mode)
1238 && (mode != TDmode || (regno % 2) == 0)
1240 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1241 || (GET_MODE_CLASS (mode) == MODE_INT
1242 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD)
1243 || (PAIRED_SIMD_REGNO_P (regno) && TARGET_PAIRED_FLOAT
1244 && PAIRED_VECTOR_MODE (mode)));
1246 /* The CR register can only hold CC modes. */
1247 if (CR_REGNO_P (regno))
1248 return GET_MODE_CLASS (mode) == MODE_CC;
1250 if (XER_REGNO_P (regno))
1251 return mode == PSImode;
1253 /* AltiVec only in AldyVec registers. */
1254 if (ALTIVEC_REGNO_P (regno))
1255 return ALTIVEC_VECTOR_MODE (mode);
1257 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1258 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1261 /* We cannot put TImode anywhere except general register and it must be
1262 able to fit within the register set. */
1264 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1267 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1269 rs6000_init_hard_regno_mode_ok (void)
1273 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1274 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1275 if (rs6000_hard_regno_mode_ok (r, m))
1276 rs6000_hard_regno_mode_ok_p[m][r] = true;
1280 /* The Darwin version of SUBTARGET_OVERRIDE_OPTIONS. */
1283 darwin_rs6000_override_options (void)
1285 /* The Darwin ABI always includes AltiVec, can't be (validly) turned
1287 rs6000_altivec_abi = 1;
1288 TARGET_ALTIVEC_VRSAVE = 1;
1289 if (DEFAULT_ABI == ABI_DARWIN)
1291 if (MACHO_DYNAMIC_NO_PIC_P)
1294 warning (0, "-mdynamic-no-pic overrides -fpic or -fPIC");
1297 else if (flag_pic == 1)
1302 if (TARGET_64BIT && ! TARGET_POWERPC64)
1304 target_flags |= MASK_POWERPC64;
1305 warning (0, "-m64 requires PowerPC64 architecture, enabling");
1309 rs6000_default_long_calls = 1;
1310 target_flags |= MASK_SOFT_FLOAT;
1313 /* Make -m64 imply -maltivec. Darwin's 64-bit ABI includes
1315 if (!flag_mkernel && !flag_apple_kext
1317 && ! (target_flags_explicit & MASK_ALTIVEC))
1318 target_flags |= MASK_ALTIVEC;
1320 /* Unless the user (not the configurer) has explicitly overridden
1321 it with -mcpu=G3 or -mno-altivec, then 10.5+ targets default to
1322 G4 unless targetting the kernel. */
1325 && strverscmp (darwin_macosx_version_min, "10.5") >= 0
1326 && ! (target_flags_explicit & MASK_ALTIVEC)
1327 && ! rs6000_select[1].string)
1329 target_flags |= MASK_ALTIVEC;
1334 /* If not otherwise specified by a target, make 'long double' equivalent to
1337 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1338 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1341 /* Override command line options. Mostly we process the processor
1342 type and sometimes adjust other TARGET_ options. */
1345 rs6000_override_options (const char *default_cpu)
1348 struct rs6000_cpu_select *ptr;
1351 /* Simplifications for entries below. */
1354 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1355 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1358 /* This table occasionally claims that a processor does not support
1359 a particular feature even though it does, but the feature is slower
1360 than the alternative. Thus, it shouldn't be relied on as a
1361 complete description of the processor's support.
1363 Please keep this list in order, and don't forget to update the
1364 documentation in invoke.texi when adding a new processor or
1368 const char *const name; /* Canonical processor name. */
1369 const enum processor_type processor; /* Processor type enum value. */
1370 const int target_enable; /* Target flags to enable. */
1371 } const processor_target_table[]
1372 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1373 {"403", PROCESSOR_PPC403,
1374 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1375 {"405", PROCESSOR_PPC405,
1376 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1377 {"405fp", PROCESSOR_PPC405,
1378 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1379 {"440", PROCESSOR_PPC440,
1380 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_MULHW | MASK_DLMZB},
1381 {"440fp", PROCESSOR_PPC440,
1382 POWERPC_BASE_MASK | MASK_MULHW | MASK_DLMZB},
1383 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1384 {"601", PROCESSOR_PPC601,
1385 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1386 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1387 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1388 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1389 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1390 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1391 {"620", PROCESSOR_PPC620,
1392 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1393 {"630", PROCESSOR_PPC630,
1394 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1395 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1396 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1397 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1398 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1399 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1400 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1401 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1402 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1403 /* 8548 has a dummy entry for now. */
1404 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN},
1405 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1406 {"970", PROCESSOR_POWER4,
1407 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1408 {"cell", PROCESSOR_CELL,
1409 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1410 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1411 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1412 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1413 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1414 {"G5", PROCESSOR_POWER4,
1415 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1416 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1417 {"power2", PROCESSOR_POWER,
1418 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1419 {"power3", PROCESSOR_PPC630,
1420 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1421 {"power4", PROCESSOR_POWER4,
1422 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1423 {"power5", PROCESSOR_POWER5,
1424 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1425 | MASK_MFCRF | MASK_POPCNTB},
1426 {"power5+", PROCESSOR_POWER5,
1427 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1428 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND},
1429 {"power6", PROCESSOR_POWER6,
1430 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1431 | MASK_FPRND | MASK_CMPB | MASK_DFP },
1432 {"power6x", PROCESSOR_POWER6,
1433 POWERPC_7400_MASK | MASK_POWERPC64 | MASK_MFCRF | MASK_POPCNTB
1434 | MASK_FPRND | MASK_CMPB | MASK_MFPGPR | MASK_DFP },
1435 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1436 {"powerpc64", PROCESSOR_POWERPC64,
1437 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1438 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1439 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1440 {"rios2", PROCESSOR_RIOS2,
1441 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1442 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1443 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1444 {"rs64", PROCESSOR_RS64A,
1445 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1448 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1450 /* Some OSs don't support saving the high part of 64-bit registers on
1451 context switch. Other OSs don't support saving Altivec registers.
1452 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1453 settings; if the user wants either, the user must explicitly specify
1454 them and we won't interfere with the user's specification. */
1457 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1458 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT | MASK_STRICT_ALIGN
1459 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1460 | MASK_MFCRF | MASK_POPCNTB | MASK_FPRND | MASK_MULHW
1461 | MASK_DLMZB | MASK_CMPB | MASK_MFPGPR | MASK_DFP)
1464 rs6000_init_hard_regno_mode_ok ();
1466 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1467 #ifdef OS_MISSING_POWERPC64
1468 if (OS_MISSING_POWERPC64)
1469 set_masks &= ~MASK_POWERPC64;
1471 #ifdef OS_MISSING_ALTIVEC
1472 if (OS_MISSING_ALTIVEC)
1473 set_masks &= ~MASK_ALTIVEC;
1476 /* Don't override by the processor default if given explicitly. */
1477 set_masks &= ~target_flags_explicit;
1479 /* Identify the processor type. */
1480 rs6000_select[0].string = default_cpu;
1481 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1483 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1485 ptr = &rs6000_select[i];
1486 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1488 for (j = 0; j < ptt_size; j++)
1489 if (! strcmp (ptr->string, processor_target_table[j].name))
1491 if (ptr->set_tune_p)
1492 rs6000_cpu = processor_target_table[j].processor;
1494 if (ptr->set_arch_p)
1496 target_flags &= ~set_masks;
1497 target_flags |= (processor_target_table[j].target_enable
1504 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1511 /* If we are optimizing big endian systems for space, use the load/store
1512 multiple and string instructions. */
1513 if (BYTES_BIG_ENDIAN && optimize_size)
1514 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1516 /* Don't allow -mmultiple or -mstring on little endian systems
1517 unless the cpu is a 750, because the hardware doesn't support the
1518 instructions used in little endian mode, and causes an alignment
1519 trap. The 750 does not cause an alignment trap (except when the
1520 target is unaligned). */
1522 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1524 if (TARGET_MULTIPLE)
1526 target_flags &= ~MASK_MULTIPLE;
1527 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1528 warning (0, "-mmultiple is not supported on little endian systems");
1533 target_flags &= ~MASK_STRING;
1534 if ((target_flags_explicit & MASK_STRING) != 0)
1535 warning (0, "-mstring is not supported on little endian systems");
1539 /* Set debug flags */
1540 if (rs6000_debug_name)
1542 if (! strcmp (rs6000_debug_name, "all"))
1543 rs6000_debug_stack = rs6000_debug_arg = 1;
1544 else if (! strcmp (rs6000_debug_name, "stack"))
1545 rs6000_debug_stack = 1;
1546 else if (! strcmp (rs6000_debug_name, "arg"))
1547 rs6000_debug_arg = 1;
1549 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1552 if (rs6000_traceback_name)
1554 if (! strncmp (rs6000_traceback_name, "full", 4))
1555 rs6000_traceback = traceback_full;
1556 else if (! strncmp (rs6000_traceback_name, "part", 4))
1557 rs6000_traceback = traceback_part;
1558 else if (! strncmp (rs6000_traceback_name, "no", 2))
1559 rs6000_traceback = traceback_none;
1561 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1562 rs6000_traceback_name);
1565 if (!rs6000_explicit_options.long_double)
1566 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1568 #ifndef POWERPC_LINUX
1569 if (!rs6000_explicit_options.ieee)
1570 rs6000_ieeequad = 1;
1573 /* Set Altivec ABI as default for powerpc64 linux. */
1574 if (TARGET_ELF && TARGET_64BIT)
1576 rs6000_altivec_abi = 1;
1577 TARGET_ALTIVEC_VRSAVE = 1;
1580 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1581 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1583 rs6000_darwin64_abi = 1;
1585 darwin_one_byte_bool = 1;
1587 /* Default to natural alignment, for better performance. */
1588 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1591 /* Place FP constants in the constant pool instead of TOC
1592 if section anchors enabled. */
1593 if (flag_section_anchors)
1594 TARGET_NO_FP_IN_TOC = 1;
1596 /* Handle -mtls-size option. */
1597 rs6000_parse_tls_size_option ();
1599 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1600 SUBTARGET_OVERRIDE_OPTIONS;
1602 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1603 SUBSUBTARGET_OVERRIDE_OPTIONS;
1605 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1606 SUB3TARGET_OVERRIDE_OPTIONS;
1611 /* The e500 does not have string instructions, and we set
1612 MASK_STRING above when optimizing for size. */
1613 if ((target_flags & MASK_STRING) != 0)
1614 target_flags = target_flags & ~MASK_STRING;
1616 else if (rs6000_select[1].string != NULL)
1618 /* For the powerpc-eabispe configuration, we set all these by
1619 default, so let's unset them if we manually set another
1620 CPU that is not the E500. */
1621 if (!rs6000_explicit_options.abi)
1623 if (!rs6000_explicit_options.spe)
1625 if (!rs6000_explicit_options.float_gprs)
1626 rs6000_float_gprs = 0;
1627 if (!rs6000_explicit_options.isel)
1631 /* Detect invalid option combinations with E500. */
1634 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1635 && rs6000_cpu != PROCESSOR_POWER5
1636 && rs6000_cpu != PROCESSOR_POWER6
1637 && rs6000_cpu != PROCESSOR_CELL);
1638 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1639 || rs6000_cpu == PROCESSOR_POWER5);
1640 rs6000_align_branch_targets = (rs6000_cpu == PROCESSOR_POWER4
1641 || rs6000_cpu == PROCESSOR_POWER5
1642 || rs6000_cpu == PROCESSOR_POWER6);
1644 rs6000_sched_restricted_insns_priority
1645 = (rs6000_sched_groups ? 1 : 0);
1647 /* Handle -msched-costly-dep option. */
1648 rs6000_sched_costly_dep
1649 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1651 if (rs6000_sched_costly_dep_str)
1653 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1654 rs6000_sched_costly_dep = no_dep_costly;
1655 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1656 rs6000_sched_costly_dep = all_deps_costly;
1657 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1658 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1659 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1660 rs6000_sched_costly_dep = store_to_load_dep_costly;
1662 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1665 /* Handle -minsert-sched-nops option. */
1666 rs6000_sched_insert_nops
1667 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1669 if (rs6000_sched_insert_nops_str)
1671 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1672 rs6000_sched_insert_nops = sched_finish_none;
1673 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1674 rs6000_sched_insert_nops = sched_finish_pad_groups;
1675 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1676 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1678 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1681 #ifdef TARGET_REGNAMES
1682 /* If the user desires alternate register names, copy in the
1683 alternate names now. */
1684 if (TARGET_REGNAMES)
1685 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1688 /* Set aix_struct_return last, after the ABI is determined.
1689 If -maix-struct-return or -msvr4-struct-return was explicitly
1690 used, don't override with the ABI default. */
1691 if (!rs6000_explicit_options.aix_struct_ret)
1692 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1694 if (TARGET_LONG_DOUBLE_128 && !TARGET_IEEEQUAD)
1695 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1698 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1700 /* We can only guarantee the availability of DI pseudo-ops when
1701 assembling for 64-bit targets. */
1704 targetm.asm_out.aligned_op.di = NULL;
1705 targetm.asm_out.unaligned_op.di = NULL;
1708 /* Set branch target alignment, if not optimizing for size. */
1711 /* Cell wants to be aligned 8byte for dual issue. */
1712 if (rs6000_cpu == PROCESSOR_CELL)
1714 if (align_functions <= 0)
1715 align_functions = 8;
1716 if (align_jumps <= 0)
1718 if (align_loops <= 0)
1721 if (rs6000_align_branch_targets)
1723 if (align_functions <= 0)
1724 align_functions = 16;
1725 if (align_jumps <= 0)
1727 if (align_loops <= 0)
1730 if (align_jumps_max_skip <= 0)
1731 align_jumps_max_skip = 15;
1732 if (align_loops_max_skip <= 0)
1733 align_loops_max_skip = 15;
1736 /* Arrange to save and restore machine status around nested functions. */
1737 init_machine_status = rs6000_init_machine_status;
1739 /* We should always be splitting complex arguments, but we can't break
1740 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1741 if (DEFAULT_ABI != ABI_AIX)
1742 targetm.calls.split_complex_arg = NULL;
1744 /* Initialize rs6000_cost with the appropriate target costs. */
1746 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1750 case PROCESSOR_RIOS1:
1751 rs6000_cost = &rios1_cost;
1754 case PROCESSOR_RIOS2:
1755 rs6000_cost = &rios2_cost;
1758 case PROCESSOR_RS64A:
1759 rs6000_cost = &rs64a_cost;
1762 case PROCESSOR_MPCCORE:
1763 rs6000_cost = &mpccore_cost;
1766 case PROCESSOR_PPC403:
1767 rs6000_cost = &ppc403_cost;
1770 case PROCESSOR_PPC405:
1771 rs6000_cost = &ppc405_cost;
1774 case PROCESSOR_PPC440:
1775 rs6000_cost = &ppc440_cost;
1778 case PROCESSOR_PPC601:
1779 rs6000_cost = &ppc601_cost;
1782 case PROCESSOR_PPC603:
1783 rs6000_cost = &ppc603_cost;
1786 case PROCESSOR_PPC604:
1787 rs6000_cost = &ppc604_cost;
1790 case PROCESSOR_PPC604e:
1791 rs6000_cost = &ppc604e_cost;
1794 case PROCESSOR_PPC620:
1795 rs6000_cost = &ppc620_cost;
1798 case PROCESSOR_PPC630:
1799 rs6000_cost = &ppc630_cost;
1802 case PROCESSOR_CELL:
1803 rs6000_cost = &ppccell_cost;
1806 case PROCESSOR_PPC750:
1807 case PROCESSOR_PPC7400:
1808 rs6000_cost = &ppc750_cost;
1811 case PROCESSOR_PPC7450:
1812 rs6000_cost = &ppc7450_cost;
1815 case PROCESSOR_PPC8540:
1816 rs6000_cost = &ppc8540_cost;
1819 case PROCESSOR_POWER4:
1820 case PROCESSOR_POWER5:
1821 rs6000_cost = &power4_cost;
1824 case PROCESSOR_POWER6:
1825 rs6000_cost = &power6_cost;
1832 if (!PARAM_SET_P (PARAM_SIMULTANEOUS_PREFETCHES))
1833 set_param_value ("simultaneous-prefetches",
1834 rs6000_cost->simultaneous_prefetches);
1835 if (!PARAM_SET_P (PARAM_L1_CACHE_SIZE))
1836 set_param_value ("l1-cache-size", rs6000_cost->l1_cache_size);
1837 if (!PARAM_SET_P (PARAM_L1_CACHE_LINE_SIZE))
1838 set_param_value ("l1-cache-line-size", rs6000_cost->cache_line_size);
1839 if (!PARAM_SET_P (PARAM_L2_CACHE_SIZE))
1840 set_param_value ("l2-cache-size", rs6000_cost->l2_cache_size);
1843 /* Implement targetm.vectorize.builtin_mask_for_load. */
1845 rs6000_builtin_mask_for_load (void)
1848 return altivec_builtin_mask_for_load;
1853 /* Implement targetm.vectorize.builtin_conversion. */
1855 rs6000_builtin_conversion (enum tree_code code, tree type)
1857 if (!TARGET_ALTIVEC)
1863 switch (TYPE_MODE (type))
1866 return TYPE_UNSIGNED (type) ?
1867 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFUX] :
1868 rs6000_builtin_decls[ALTIVEC_BUILTIN_VCFSX];
1877 /* Implement targetm.vectorize.builtin_mul_widen_even. */
1879 rs6000_builtin_mul_widen_even (tree type)
1881 if (!TARGET_ALTIVEC)
1884 switch (TYPE_MODE (type))
1887 return TYPE_UNSIGNED (type) ?
1888 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUH] :
1889 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESH];
1892 return TYPE_UNSIGNED (type) ?
1893 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULEUB] :
1894 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULESB];
1900 /* Implement targetm.vectorize.builtin_mul_widen_odd. */
1902 rs6000_builtin_mul_widen_odd (tree type)
1904 if (!TARGET_ALTIVEC)
1907 switch (TYPE_MODE (type))
1910 return TYPE_UNSIGNED (type) ?
1911 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUH] :
1912 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSH];
1915 return TYPE_UNSIGNED (type) ?
1916 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOUB] :
1917 rs6000_builtin_decls[ALTIVEC_BUILTIN_VMULOSB];
1924 /* Return true iff, data reference of TYPE can reach vector alignment (16)
1925 after applying N number of iterations. This routine does not determine
1926 how may iterations are required to reach desired alignment. */
1929 rs6000_vector_alignment_reachable (const_tree type ATTRIBUTE_UNUSED, bool is_packed)
1936 if (rs6000_alignment_flags == MASK_ALIGN_NATURAL)
1939 if (rs6000_alignment_flags == MASK_ALIGN_POWER)
1949 /* Assuming that all other types are naturally aligned. CHECKME! */
1954 /* Handle generic options of the form -mfoo=yes/no.
1955 NAME is the option name.
1956 VALUE is the option value.
1957 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1958 whether the option value is 'yes' or 'no' respectively. */
1960 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1964 else if (!strcmp (value, "yes"))
1966 else if (!strcmp (value, "no"))
1969 error ("unknown -m%s= option specified: '%s'", name, value);
1972 /* Validate and record the size specified with the -mtls-size option. */
1975 rs6000_parse_tls_size_option (void)
1977 if (rs6000_tls_size_string == 0)
1979 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1980 rs6000_tls_size = 16;
1981 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1982 rs6000_tls_size = 32;
1983 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1984 rs6000_tls_size = 64;
1986 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1990 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1992 if (DEFAULT_ABI == ABI_DARWIN)
1993 /* The Darwin libraries never set errno, so we might as well
1994 avoid calling them when that's the only reason we would. */
1995 flag_errno_math = 0;
1997 /* Double growth factor to counter reduced min jump length. */
1998 set_param_value ("max-grow-copy-bb-insns", 16);
2000 /* Enable section anchors by default.
2001 Skip section anchors for Objective C and Objective C++
2002 until front-ends fixed. */
2003 if (!TARGET_MACHO && lang_hooks.name[4] != 'O')
2004 flag_section_anchors = 1;
2007 /* Implement TARGET_HANDLE_OPTION. */
2010 rs6000_handle_option (size_t code, const char *arg, int value)
2015 target_flags &= ~(MASK_POWER | MASK_POWER2
2016 | MASK_MULTIPLE | MASK_STRING);
2017 target_flags_explicit |= (MASK_POWER | MASK_POWER2
2018 | MASK_MULTIPLE | MASK_STRING);
2020 case OPT_mno_powerpc:
2021 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
2022 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2023 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
2024 | MASK_PPC_GFXOPT | MASK_POWERPC64);
2027 target_flags &= ~MASK_MINIMAL_TOC;
2028 TARGET_NO_FP_IN_TOC = 0;
2029 TARGET_NO_SUM_IN_TOC = 0;
2030 target_flags_explicit |= MASK_MINIMAL_TOC;
2031 #ifdef TARGET_USES_SYSV4_OPT
2032 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
2033 just the same as -mminimal-toc. */
2034 target_flags |= MASK_MINIMAL_TOC;
2035 target_flags_explicit |= MASK_MINIMAL_TOC;
2039 #ifdef TARGET_USES_SYSV4_OPT
2041 /* Make -mtoc behave like -mminimal-toc. */
2042 target_flags |= MASK_MINIMAL_TOC;
2043 target_flags_explicit |= MASK_MINIMAL_TOC;
2047 #ifdef TARGET_USES_AIX64_OPT
2052 target_flags |= MASK_POWERPC64 | MASK_POWERPC;
2053 target_flags |= ~target_flags_explicit & MASK_PPC_GFXOPT;
2054 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC;
2057 #ifdef TARGET_USES_AIX64_OPT
2062 target_flags &= ~MASK_POWERPC64;
2063 target_flags_explicit |= MASK_POWERPC64;
2066 case OPT_minsert_sched_nops_:
2067 rs6000_sched_insert_nops_str = arg;
2070 case OPT_mminimal_toc:
2073 TARGET_NO_FP_IN_TOC = 0;
2074 TARGET_NO_SUM_IN_TOC = 0;
2081 target_flags |= (MASK_MULTIPLE | MASK_STRING);
2082 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
2089 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2090 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
2094 case OPT_mpowerpc_gpopt:
2095 case OPT_mpowerpc_gfxopt:
2098 target_flags |= MASK_POWERPC;
2099 target_flags_explicit |= MASK_POWERPC;
2103 case OPT_maix_struct_return:
2104 case OPT_msvr4_struct_return:
2105 rs6000_explicit_options.aix_struct_ret = true;
2109 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
2113 rs6000_explicit_options.isel = true;
2114 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
2118 rs6000_explicit_options.spe = true;
2119 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
2123 rs6000_debug_name = arg;
2126 #ifdef TARGET_USES_SYSV4_OPT
2128 rs6000_abi_name = arg;
2132 rs6000_sdata_name = arg;
2135 case OPT_mtls_size_:
2136 rs6000_tls_size_string = arg;
2139 case OPT_mrelocatable:
2142 target_flags |= MASK_MINIMAL_TOC;
2143 target_flags_explicit |= MASK_MINIMAL_TOC;
2144 TARGET_NO_FP_IN_TOC = 1;
2148 case OPT_mrelocatable_lib:
2151 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2152 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC;
2153 TARGET_NO_FP_IN_TOC = 1;
2157 target_flags &= ~MASK_RELOCATABLE;
2158 target_flags_explicit |= MASK_RELOCATABLE;
2164 if (!strcmp (arg, "altivec"))
2166 rs6000_explicit_options.abi = true;
2167 rs6000_altivec_abi = 1;
2170 else if (! strcmp (arg, "no-altivec"))
2172 /* ??? Don't set rs6000_explicit_options.abi here, to allow
2173 the default for rs6000_spe_abi to be chosen later. */
2174 rs6000_altivec_abi = 0;
2176 else if (! strcmp (arg, "spe"))
2178 rs6000_explicit_options.abi = true;
2180 rs6000_altivec_abi = 0;
2181 if (!TARGET_SPE_ABI)
2182 error ("not configured for ABI: '%s'", arg);
2184 else if (! strcmp (arg, "no-spe"))
2186 rs6000_explicit_options.abi = true;
2190 /* These are here for testing during development only, do not
2191 document in the manual please. */
2192 else if (! strcmp (arg, "d64"))
2194 rs6000_darwin64_abi = 1;
2195 warning (0, "Using darwin64 ABI");
2197 else if (! strcmp (arg, "d32"))
2199 rs6000_darwin64_abi = 0;
2200 warning (0, "Using old darwin ABI");
2203 else if (! strcmp (arg, "ibmlongdouble"))
2205 rs6000_explicit_options.ieee = true;
2206 rs6000_ieeequad = 0;
2207 warning (0, "Using IBM extended precision long double");
2209 else if (! strcmp (arg, "ieeelongdouble"))
2211 rs6000_explicit_options.ieee = true;
2212 rs6000_ieeequad = 1;
2213 warning (0, "Using IEEE extended precision long double");
2218 error ("unknown ABI specified: '%s'", arg);
2224 rs6000_select[1].string = arg;
2228 rs6000_select[2].string = arg;
2231 case OPT_mtraceback_:
2232 rs6000_traceback_name = arg;
2235 case OPT_mfloat_gprs_:
2236 rs6000_explicit_options.float_gprs = true;
2237 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
2238 rs6000_float_gprs = 1;
2239 else if (! strcmp (arg, "double"))
2240 rs6000_float_gprs = 2;
2241 else if (! strcmp (arg, "no"))
2242 rs6000_float_gprs = 0;
2245 error ("invalid option for -mfloat-gprs: '%s'", arg);
2250 case OPT_mlong_double_:
2251 rs6000_explicit_options.long_double = true;
2252 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2253 if (value != 64 && value != 128)
2255 error ("Unknown switch -mlong-double-%s", arg);
2256 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
2260 rs6000_long_double_type_size = value;
2263 case OPT_msched_costly_dep_:
2264 rs6000_sched_costly_dep_str = arg;
2268 rs6000_explicit_options.alignment = true;
2269 if (! strcmp (arg, "power"))
2271 /* On 64-bit Darwin, power alignment is ABI-incompatible with
2272 some C library functions, so warn about it. The flag may be
2273 useful for performance studies from time to time though, so
2274 don't disable it entirely. */
2275 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
2276 warning (0, "-malign-power is not supported for 64-bit Darwin;"
2277 " it is incompatible with the installed C and C++ libraries");
2278 rs6000_alignment_flags = MASK_ALIGN_POWER;
2280 else if (! strcmp (arg, "natural"))
2281 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
2284 error ("unknown -malign-XXXXX option specified: '%s'", arg);
2292 /* Do anything needed at the start of the asm file. */
2295 rs6000_file_start (void)
2299 const char *start = buffer;
2300 struct rs6000_cpu_select *ptr;
2301 const char *default_cpu = TARGET_CPU_DEFAULT;
2302 FILE *file = asm_out_file;
2304 default_file_start ();
2306 #ifdef TARGET_BI_ARCH
2307 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
2311 if (flag_verbose_asm)
2313 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
2314 rs6000_select[0].string = default_cpu;
2316 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
2318 ptr = &rs6000_select[i];
2319 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
2321 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
2326 if (PPC405_ERRATUM77)
2328 fprintf (file, "%s PPC405CR_ERRATUM77", start);
2332 #ifdef USING_ELFOS_H
2333 switch (rs6000_sdata)
2335 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
2336 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
2337 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
2338 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
2341 if (rs6000_sdata && g_switch_value)
2343 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
2353 #ifdef HAVE_AS_GNU_ATTRIBUTE
2354 if (TARGET_32BIT && DEFAULT_ABI == ABI_V4)
2356 fprintf (file, "\t.gnu_attribute 4, %d\n",
2357 (TARGET_HARD_FLOAT && TARGET_FPRS) ? 1 : 2);
2358 fprintf (file, "\t.gnu_attribute 8, %d\n",
2359 (TARGET_ALTIVEC_ABI ? 2
2360 : TARGET_SPE_ABI ? 3
2365 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
2367 switch_to_section (toc_section);
2368 switch_to_section (text_section);
2373 /* Return nonzero if this function is known to have a null epilogue. */
2376 direct_return (void)
2378 if (reload_completed)
2380 rs6000_stack_t *info = rs6000_stack_info ();
2382 if (info->first_gp_reg_save == 32
2383 && info->first_fp_reg_save == 64
2384 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
2385 && ! info->lr_save_p
2386 && ! info->cr_save_p
2387 && info->vrsave_mask == 0
2395 /* Return the number of instructions it takes to form a constant in an
2396 integer register. */
2399 num_insns_constant_wide (HOST_WIDE_INT value)
2401 /* signed constant loadable with {cal|addi} */
2402 if ((unsigned HOST_WIDE_INT) (value + 0x8000) < 0x10000)
2405 /* constant loadable with {cau|addis} */
2406 else if ((value & 0xffff) == 0
2407 && (value >> 31 == -1 || value >> 31 == 0))
2410 #if HOST_BITS_PER_WIDE_INT == 64
2411 else if (TARGET_POWERPC64)
2413 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
2414 HOST_WIDE_INT high = value >> 31;
2416 if (high == 0 || high == -1)
2422 return num_insns_constant_wide (high) + 1;
2424 return (num_insns_constant_wide (high)
2425 + num_insns_constant_wide (low) + 1);
2434 num_insns_constant (rtx op, enum machine_mode mode)
2436 HOST_WIDE_INT low, high;
2438 switch (GET_CODE (op))
2441 #if HOST_BITS_PER_WIDE_INT == 64
2442 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
2443 && mask64_operand (op, mode))
2447 return num_insns_constant_wide (INTVAL (op));
2455 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2456 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
2457 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2460 if (mode == VOIDmode || mode == DImode)
2462 high = CONST_DOUBLE_HIGH (op);
2463 low = CONST_DOUBLE_LOW (op);
2470 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2471 if (DECIMAL_FLOAT_MODE_P (mode))
2472 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, l);
2474 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2475 high = l[WORDS_BIG_ENDIAN == 0];
2476 low = l[WORDS_BIG_ENDIAN != 0];
2480 return (num_insns_constant_wide (low)
2481 + num_insns_constant_wide (high));
2484 if ((high == 0 && low >= 0)
2485 || (high == -1 && low < 0))
2486 return num_insns_constant_wide (low);
2488 else if (mask64_operand (op, mode))
2492 return num_insns_constant_wide (high) + 1;
2495 return (num_insns_constant_wide (high)
2496 + num_insns_constant_wide (low) + 1);
2504 /* Interpret element ELT of the CONST_VECTOR OP as an integer value.
2505 If the mode of OP is MODE_VECTOR_INT, this simply returns the
2506 corresponding element of the vector, but for V4SFmode and V2SFmode,
2507 the corresponding "float" is interpreted as an SImode integer. */
2509 static HOST_WIDE_INT
2510 const_vector_elt_as_int (rtx op, unsigned int elt)
2512 rtx tmp = CONST_VECTOR_ELT (op, elt);
2513 if (GET_MODE (op) == V4SFmode
2514 || GET_MODE (op) == V2SFmode)
2515 tmp = gen_lowpart (SImode, tmp);
2516 return INTVAL (tmp);
2519 /* Return true if OP can be synthesized with a particular vspltisb, vspltish
2520 or vspltisw instruction. OP is a CONST_VECTOR. Which instruction is used
2521 depends on STEP and COPIES, one of which will be 1. If COPIES > 1,
2522 all items are set to the same value and contain COPIES replicas of the
2523 vsplt's operand; if STEP > 1, one in STEP elements is set to the vsplt's
2524 operand and the others are set to the value of the operand's msb. */
2527 vspltis_constant (rtx op, unsigned step, unsigned copies)
2529 enum machine_mode mode = GET_MODE (op);
2530 enum machine_mode inner = GET_MODE_INNER (mode);
2533 unsigned nunits = GET_MODE_NUNITS (mode);
2534 unsigned bitsize = GET_MODE_BITSIZE (inner);
2535 unsigned mask = GET_MODE_MASK (inner);
2537 HOST_WIDE_INT val = const_vector_elt_as_int (op, nunits - 1);
2538 HOST_WIDE_INT splat_val = val;
2539 HOST_WIDE_INT msb_val = val > 0 ? 0 : -1;
2541 /* Construct the value to be splatted, if possible. If not, return 0. */
2542 for (i = 2; i <= copies; i *= 2)
2544 HOST_WIDE_INT small_val;
2546 small_val = splat_val >> bitsize;
2548 if (splat_val != ((small_val << bitsize) | (small_val & mask)))
2550 splat_val = small_val;
2553 /* Check if SPLAT_VAL can really be the operand of a vspltis[bhw]. */
2554 if (EASY_VECTOR_15 (splat_val))
2557 /* Also check if we can splat, and then add the result to itself. Do so if
2558 the value is positive, of if the splat instruction is using OP's mode;
2559 for splat_val < 0, the splat and the add should use the same mode. */
2560 else if (EASY_VECTOR_15_ADD_SELF (splat_val)
2561 && (splat_val >= 0 || (step == 1 && copies == 1)))
2567 /* Check if VAL is present in every STEP-th element, and the
2568 other elements are filled with its most significant bit. */
2569 for (i = 0; i < nunits - 1; ++i)
2571 HOST_WIDE_INT desired_val;
2572 if (((i + 1) & (step - 1)) == 0)
2575 desired_val = msb_val;
2577 if (desired_val != const_vector_elt_as_int (op, i))
2585 /* Return true if OP is of the given MODE and can be synthesized
2586 with a vspltisb, vspltish or vspltisw. */
2589 easy_altivec_constant (rtx op, enum machine_mode mode)
2591 unsigned step, copies;
2593 if (mode == VOIDmode)
2594 mode = GET_MODE (op);
2595 else if (mode != GET_MODE (op))
2598 /* Start with a vspltisw. */
2599 step = GET_MODE_NUNITS (mode) / 4;
2602 if (vspltis_constant (op, step, copies))
2605 /* Then try with a vspltish. */
2611 if (vspltis_constant (op, step, copies))
2614 /* And finally a vspltisb. */
2620 if (vspltis_constant (op, step, copies))
2626 /* Generate a VEC_DUPLICATE representing a vspltis[bhw] instruction whose
2627 result is OP. Abort if it is not possible. */
2630 gen_easy_altivec_constant (rtx op)
2632 enum machine_mode mode = GET_MODE (op);
2633 int nunits = GET_MODE_NUNITS (mode);
2634 rtx last = CONST_VECTOR_ELT (op, nunits - 1);
2635 unsigned step = nunits / 4;
2636 unsigned copies = 1;
2638 /* Start with a vspltisw. */
2639 if (vspltis_constant (op, step, copies))
2640 return gen_rtx_VEC_DUPLICATE (V4SImode, gen_lowpart (SImode, last));
2642 /* Then try with a vspltish. */
2648 if (vspltis_constant (op, step, copies))
2649 return gen_rtx_VEC_DUPLICATE (V8HImode, gen_lowpart (HImode, last));
2651 /* And finally a vspltisb. */
2657 if (vspltis_constant (op, step, copies))
2658 return gen_rtx_VEC_DUPLICATE (V16QImode, gen_lowpart (QImode, last));
2664 output_vec_const_move (rtx *operands)
2667 enum machine_mode mode;
2672 mode = GET_MODE (dest);
2677 if (zero_constant (vec, mode))
2678 return "vxor %0,%0,%0";
2680 splat_vec = gen_easy_altivec_constant (vec);
2681 gcc_assert (GET_CODE (splat_vec) == VEC_DUPLICATE);
2682 operands[1] = XEXP (splat_vec, 0);
2683 if (!EASY_VECTOR_15 (INTVAL (operands[1])))
2686 switch (GET_MODE (splat_vec))
2689 return "vspltisw %0,%1";
2692 return "vspltish %0,%1";
2695 return "vspltisb %0,%1";
2702 gcc_assert (TARGET_SPE);
2704 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2705 pattern of V1DI, V4HI, and V2SF.
2707 FIXME: We should probably return # and add post reload
2708 splitters for these, but this way is so easy ;-). */
2709 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2710 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2711 operands[1] = CONST_VECTOR_ELT (vec, 0);
2712 operands[2] = CONST_VECTOR_ELT (vec, 1);
2714 return "li %0,%1\n\tevmergelo %0,%0,%0";
2716 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2719 /* Initialize TARGET of vector PAIRED to VALS. */
2722 paired_expand_vector_init (rtx target, rtx vals)
2724 enum machine_mode mode = GET_MODE (target);
2725 int n_elts = GET_MODE_NUNITS (mode);
2727 rtx x, new, tmp, constant_op, op1, op2;
2730 for (i = 0; i < n_elts; ++i)
2732 x = XVECEXP (vals, 0, i);
2733 if (!CONSTANT_P (x))
2738 /* Load from constant pool. */
2739 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2745 /* The vector is initialized only with non-constants. */
2746 new = gen_rtx_VEC_CONCAT (V2SFmode, XVECEXP (vals, 0, 0),
2747 XVECEXP (vals, 0, 1));
2749 emit_move_insn (target, new);
2753 /* One field is non-constant and the other one is a constant. Load the
2754 constant from the constant pool and use ps_merge instruction to
2755 construct the whole vector. */
2756 op1 = XVECEXP (vals, 0, 0);
2757 op2 = XVECEXP (vals, 0, 1);
2759 constant_op = (CONSTANT_P (op1)) ? op1 : op2;
2761 tmp = gen_reg_rtx (GET_MODE (constant_op));
2762 emit_move_insn (tmp, constant_op);
2764 if (CONSTANT_P (op1))
2765 new = gen_rtx_VEC_CONCAT (V2SFmode, tmp, op2);
2767 new = gen_rtx_VEC_CONCAT (V2SFmode, op1, tmp);
2769 emit_move_insn (target, new);
2772 /* Initialize vector TARGET to VALS. */
2775 rs6000_expand_vector_init (rtx target, rtx vals)
2777 enum machine_mode mode = GET_MODE (target);
2778 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2779 int n_elts = GET_MODE_NUNITS (mode);
2780 int n_var = 0, one_var = -1;
2781 bool all_same = true, all_const_zero = true;
2785 for (i = 0; i < n_elts; ++i)
2787 x = XVECEXP (vals, 0, i);
2788 if (!CONSTANT_P (x))
2789 ++n_var, one_var = i;
2790 else if (x != CONST0_RTX (inner_mode))
2791 all_const_zero = false;
2793 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2799 if (mode != V4SFmode && all_const_zero)
2801 /* Zero register. */
2802 emit_insn (gen_rtx_SET (VOIDmode, target,
2803 gen_rtx_XOR (mode, target, target)));
2806 else if (mode != V4SFmode && easy_vector_constant (vals, mode))
2808 /* Splat immediate. */
2809 emit_insn (gen_rtx_SET (VOIDmode, target, vals));
2813 ; /* Splat vector element. */
2816 /* Load from constant pool. */
2817 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2822 /* Store value to stack temp. Load vector element. Splat. */
2825 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2826 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2827 XVECEXP (vals, 0, 0));
2828 x = gen_rtx_UNSPEC (VOIDmode,
2829 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2830 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2832 gen_rtx_SET (VOIDmode,
2835 x = gen_rtx_VEC_SELECT (inner_mode, target,
2836 gen_rtx_PARALLEL (VOIDmode,
2837 gen_rtvec (1, const0_rtx)));
2838 emit_insn (gen_rtx_SET (VOIDmode, target,
2839 gen_rtx_VEC_DUPLICATE (mode, x)));
2843 /* One field is non-constant. Load constant then overwrite
2847 rtx copy = copy_rtx (vals);
2849 /* Load constant part of vector, substitute neighboring value for
2851 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2852 rs6000_expand_vector_init (target, copy);
2854 /* Insert variable. */
2855 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2859 /* Construct the vector in memory one field at a time
2860 and load the whole vector. */
2861 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2862 for (i = 0; i < n_elts; i++)
2863 emit_move_insn (adjust_address_nv (mem, inner_mode,
2864 i * GET_MODE_SIZE (inner_mode)),
2865 XVECEXP (vals, 0, i));
2866 emit_move_insn (target, mem);
2869 /* Set field ELT of TARGET to VAL. */
2872 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2874 enum machine_mode mode = GET_MODE (target);
2875 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2876 rtx reg = gen_reg_rtx (mode);
2878 int width = GET_MODE_SIZE (inner_mode);
2881 /* Load single variable value. */
2882 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2883 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2884 x = gen_rtx_UNSPEC (VOIDmode,
2885 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2886 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2888 gen_rtx_SET (VOIDmode,
2892 /* Linear sequence. */
2893 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2894 for (i = 0; i < 16; ++i)
2895 XVECEXP (mask, 0, i) = GEN_INT (i);
2897 /* Set permute mask to insert element into target. */
2898 for (i = 0; i < width; ++i)
2899 XVECEXP (mask, 0, elt*width + i)
2900 = GEN_INT (i + 0x10);
2901 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2902 x = gen_rtx_UNSPEC (mode,
2903 gen_rtvec (3, target, reg,
2904 force_reg (V16QImode, x)),
2906 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2909 /* Extract field ELT from VEC into TARGET. */
2912 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2914 enum machine_mode mode = GET_MODE (vec);
2915 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2918 /* Allocate mode-sized buffer. */
2919 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2921 /* Add offset to field within buffer matching vector element. */
2922 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2924 /* Store single field into mode-sized buffer. */
2925 x = gen_rtx_UNSPEC (VOIDmode,
2926 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2927 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2929 gen_rtx_SET (VOIDmode,
2932 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2935 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2936 implement ANDing by the mask IN. */
2938 build_mask64_2_operands (rtx in, rtx *out)
2940 #if HOST_BITS_PER_WIDE_INT >= 64
2941 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2944 gcc_assert (GET_CODE (in) == CONST_INT);
2949 /* Assume c initially something like 0x00fff000000fffff. The idea
2950 is to rotate the word so that the middle ^^^^^^ group of zeros
2951 is at the MS end and can be cleared with an rldicl mask. We then
2952 rotate back and clear off the MS ^^ group of zeros with a
2954 c = ~c; /* c == 0xff000ffffff00000 */
2955 lsb = c & -c; /* lsb == 0x0000000000100000 */
2956 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2957 c = ~c; /* c == 0x00fff000000fffff */
2958 c &= -lsb; /* c == 0x00fff00000000000 */
2959 lsb = c & -c; /* lsb == 0x0000100000000000 */
2960 c = ~c; /* c == 0xff000fffffffffff */
2961 c &= -lsb; /* c == 0xff00000000000000 */
2963 while ((lsb >>= 1) != 0)
2964 shift++; /* shift == 44 on exit from loop */
2965 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2966 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2967 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2971 /* Assume c initially something like 0xff000f0000000000. The idea
2972 is to rotate the word so that the ^^^ middle group of zeros
2973 is at the LS end and can be cleared with an rldicr mask. We then
2974 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2976 lsb = c & -c; /* lsb == 0x0000010000000000 */
2977 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2978 c = ~c; /* c == 0x00fff0ffffffffff */
2979 c &= -lsb; /* c == 0x00fff00000000000 */
2980 lsb = c & -c; /* lsb == 0x0000100000000000 */
2981 c = ~c; /* c == 0xff000fffffffffff */
2982 c &= -lsb; /* c == 0xff00000000000000 */
2984 while ((lsb >>= 1) != 0)
2985 shift++; /* shift == 44 on exit from loop */
2986 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2987 m1 >>= shift; /* m1 == 0x0000000000000fff */
2988 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2991 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2992 masks will be all 1's. We are guaranteed more than one transition. */
2993 out[0] = GEN_INT (64 - shift);
2994 out[1] = GEN_INT (m1);
2995 out[2] = GEN_INT (shift);
2996 out[3] = GEN_INT (m2);
3004 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
3007 invalid_e500_subreg (rtx op, enum machine_mode mode)
3009 if (TARGET_E500_DOUBLE)
3011 /* Reject (subreg:SI (reg:DF)); likewise with subreg:DI or
3012 subreg:TI and reg:TF. */
3013 if (GET_CODE (op) == SUBREG
3014 && (mode == SImode || mode == DImode || mode == TImode)
3015 && REG_P (SUBREG_REG (op))
3016 && (GET_MODE (SUBREG_REG (op)) == DFmode
3017 || GET_MODE (SUBREG_REG (op)) == TFmode))
3020 /* Reject (subreg:DF (reg:DI)); likewise with subreg:TF and
3022 if (GET_CODE (op) == SUBREG
3023 && (mode == DFmode || mode == TFmode)
3024 && REG_P (SUBREG_REG (op))
3025 && (GET_MODE (SUBREG_REG (op)) == DImode
3026 || GET_MODE (SUBREG_REG (op)) == TImode))
3031 && GET_CODE (op) == SUBREG
3033 && REG_P (SUBREG_REG (op))
3034 && SPE_VECTOR_MODE (GET_MODE (SUBREG_REG (op))))
3040 /* AIX increases natural record alignment to doubleword if the first
3041 field is an FP double while the FP fields remain word aligned. */
3044 rs6000_special_round_type_align (tree type, unsigned int computed,
3045 unsigned int specified)
3047 unsigned int align = MAX (computed, specified);
3048 tree field = TYPE_FIELDS (type);
3050 /* Skip all non field decls */
3051 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3052 field = TREE_CHAIN (field);
3054 if (field != NULL && field != type)
3056 type = TREE_TYPE (field);
3057 while (TREE_CODE (type) == ARRAY_TYPE)
3058 type = TREE_TYPE (type);
3060 if (type != error_mark_node && TYPE_MODE (type) == DFmode)
3061 align = MAX (align, 64);
3067 /* Darwin increases record alignment to the natural alignment of
3071 darwin_rs6000_special_round_type_align (tree type, unsigned int computed,
3072 unsigned int specified)
3074 unsigned int align = MAX (computed, specified);
3076 if (TYPE_PACKED (type))
3079 /* Find the first field, looking down into aggregates. */
3081 tree field = TYPE_FIELDS (type);
3082 /* Skip all non field decls */
3083 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
3084 field = TREE_CHAIN (field);
3087 type = TREE_TYPE (field);
3088 while (TREE_CODE (type) == ARRAY_TYPE)
3089 type = TREE_TYPE (type);
3090 } while (AGGREGATE_TYPE_P (type));
3092 if (! AGGREGATE_TYPE_P (type) && type != error_mark_node)
3093 align = MAX (align, TYPE_ALIGN (type));
3098 /* Return 1 for an operand in small memory on V.4/eabi. */
3101 small_data_operand (rtx op ATTRIBUTE_UNUSED,
3102 enum machine_mode mode ATTRIBUTE_UNUSED)
3107 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
3110 if (DEFAULT_ABI != ABI_V4)
3113 if (GET_CODE (op) == SYMBOL_REF)
3116 else if (GET_CODE (op) != CONST
3117 || GET_CODE (XEXP (op, 0)) != PLUS
3118 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
3119 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
3124 rtx sum = XEXP (op, 0);
3125 HOST_WIDE_INT summand;
3127 /* We have to be careful here, because it is the referenced address
3128 that must be 32k from _SDA_BASE_, not just the symbol. */
3129 summand = INTVAL (XEXP (sum, 1));
3130 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
3133 sym_ref = XEXP (sum, 0);
3136 return SYMBOL_REF_SMALL_P (sym_ref);
3142 /* Return true if either operand is a general purpose register. */
3145 gpr_or_gpr_p (rtx op0, rtx op1)
3147 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
3148 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
3152 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
3155 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
3157 switch (GET_CODE (op))
3160 if (RS6000_SYMBOL_REF_TLS_P (op))
3162 else if (CONSTANT_POOL_ADDRESS_P (op))
3164 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
3172 else if (! strcmp (XSTR (op, 0), toc_label_name))
3181 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
3182 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
3184 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
3193 constant_pool_expr_p (rtx op)
3197 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
3201 toc_relative_expr_p (rtx op)
3205 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
3209 legitimate_constant_pool_address_p (rtx x)
3212 && GET_CODE (x) == PLUS
3213 && GET_CODE (XEXP (x, 0)) == REG
3214 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
3215 && constant_pool_expr_p (XEXP (x, 1)));
3219 legitimate_small_data_p (enum machine_mode mode, rtx x)
3221 return (DEFAULT_ABI == ABI_V4
3222 && !flag_pic && !TARGET_TOC
3223 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
3224 && small_data_operand (x, mode));
3227 /* SPE offset addressing is limited to 5-bits worth of double words. */
3228 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
3231 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
3233 unsigned HOST_WIDE_INT offset, extra;
3235 if (GET_CODE (x) != PLUS)
3237 if (GET_CODE (XEXP (x, 0)) != REG)
3239 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3241 if (legitimate_constant_pool_address_p (x))
3243 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
3246 offset = INTVAL (XEXP (x, 1));
3254 /* AltiVec vector modes. Only reg+reg addressing is valid and
3255 constant offset zero should not occur due to canonicalization.
3256 Allow any offset when not strict before reload. */
3263 /* Paired vector modes. Only reg+reg addressing is valid and
3264 constant offset zero should not occur due to canonicalization.
3265 Allow any offset when not strict before reload. */
3266 if (TARGET_PAIRED_FLOAT)
3268 /* SPE vector modes. */
3269 return SPE_CONST_OFFSET_OK (offset);
3273 if (TARGET_E500_DOUBLE)
3274 return SPE_CONST_OFFSET_OK (offset);
3277 /* On e500v2, we may have:
3279 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
3281 Which gets addressed with evldd instructions. */
3282 if (TARGET_E500_DOUBLE)
3283 return SPE_CONST_OFFSET_OK (offset);
3285 if (mode == DFmode || mode == DDmode || !TARGET_POWERPC64)
3287 else if (offset & 3)
3292 if (TARGET_E500_DOUBLE)
3293 return (SPE_CONST_OFFSET_OK (offset)
3294 && SPE_CONST_OFFSET_OK (offset + 8));
3298 if (mode == TFmode || mode == TDmode || !TARGET_POWERPC64)
3300 else if (offset & 3)
3311 return (offset < 0x10000) && (offset + extra < 0x10000);
3315 legitimate_indexed_address_p (rtx x, int strict)
3319 if (GET_CODE (x) != PLUS)
3325 /* Recognize the rtl generated by reload which we know will later be
3326 replaced with proper base and index regs. */
3328 && reload_in_progress
3329 && (REG_P (op0) || GET_CODE (op0) == PLUS)
3333 return (REG_P (op0) && REG_P (op1)
3334 && ((INT_REG_OK_FOR_BASE_P (op0, strict)
3335 && INT_REG_OK_FOR_INDEX_P (op1, strict))
3336 || (INT_REG_OK_FOR_BASE_P (op1, strict)
3337 && INT_REG_OK_FOR_INDEX_P (op0, strict))));
3341 legitimate_indirect_address_p (rtx x, int strict)
3343 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
3347 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
3349 if (!TARGET_MACHO || !flag_pic
3350 || mode != SImode || GET_CODE (x) != MEM)
3354 if (GET_CODE (x) != LO_SUM)
3356 if (GET_CODE (XEXP (x, 0)) != REG)
3358 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
3362 return CONSTANT_P (x);
3366 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
3368 if (GET_CODE (x) != LO_SUM)
3370 if (GET_CODE (XEXP (x, 0)) != REG)
3372 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
3374 /* Restrict addressing for DI because of our SUBREG hackery. */
3375 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3380 if (TARGET_ELF || TARGET_MACHO)
3382 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
3386 if (GET_MODE_NUNITS (mode) != 1)
3388 if (GET_MODE_BITSIZE (mode) > 64
3389 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
3390 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
3393 return CONSTANT_P (x);
3400 /* Try machine-dependent ways of modifying an illegitimate address
3401 to be legitimate. If we find one, return the new, valid address.
3402 This is used from only one place: `memory_address' in explow.c.
3404 OLDX is the address as it was before break_out_memory_refs was
3405 called. In some cases it is useful to look at this to decide what
3408 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
3410 It is always safe for this function to do nothing. It exists to
3411 recognize opportunities to optimize the output.
3413 On RS/6000, first check for the sum of a register with a constant
3414 integer that is out of range. If so, generate code to add the
3415 constant with the low-order 16 bits masked to the register and force
3416 this result into another register (this can be done with `cau').
3417 Then generate an address of REG+(CONST&0xffff), allowing for the
3418 possibility of bit 16 being a one.
3420 Then check for the sum of a register and something not constant, try to
3421 load the other things into a register and return the sum. */
3424 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
3425 enum machine_mode mode)
3427 if (GET_CODE (x) == SYMBOL_REF)
3429 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
3431 return rs6000_legitimize_tls_address (x, model);
3434 if (GET_CODE (x) == PLUS
3435 && GET_CODE (XEXP (x, 0)) == REG
3436 && GET_CODE (XEXP (x, 1)) == CONST_INT
3437 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000
3438 && !(SPE_VECTOR_MODE (mode)
3439 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3440 || mode == DImode))))
3442 HOST_WIDE_INT high_int, low_int;
3444 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
3445 high_int = INTVAL (XEXP (x, 1)) - low_int;
3446 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
3447 GEN_INT (high_int)), 0);
3448 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
3450 else if (GET_CODE (x) == PLUS
3451 && GET_CODE (XEXP (x, 0)) == REG
3452 && GET_CODE (XEXP (x, 1)) != CONST_INT
3453 && GET_MODE_NUNITS (mode) == 1
3454 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3456 || (((mode != DImode && mode != DFmode && mode != DDmode)
3457 || TARGET_E500_DOUBLE)
3458 && mode != TFmode && mode != TDmode))
3459 && (TARGET_POWERPC64 || mode != DImode)
3462 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
3463 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
3465 else if (ALTIVEC_VECTOR_MODE (mode))
3469 /* Make sure both operands are registers. */
3470 if (GET_CODE (x) == PLUS)
3471 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
3472 force_reg (Pmode, XEXP (x, 1)));
3474 reg = force_reg (Pmode, x);
3477 else if (SPE_VECTOR_MODE (mode)
3478 || (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3479 || mode == DDmode || mode == TDmode
3480 || mode == DImode)))
3484 /* We accept [reg + reg] and [reg + OFFSET]. */
3486 if (GET_CODE (x) == PLUS)
3488 rtx op1 = XEXP (x, 0);
3489 rtx op2 = XEXP (x, 1);
3491 op1 = force_reg (Pmode, op1);
3493 if (GET_CODE (op2) != REG
3494 && (GET_CODE (op2) != CONST_INT
3495 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
3496 op2 = force_reg (Pmode, op2);
3498 return gen_rtx_PLUS (Pmode, op1, op2);
3501 return force_reg (Pmode, x);
3507 && GET_CODE (x) != CONST_INT
3508 && GET_CODE (x) != CONST_DOUBLE
3510 && GET_MODE_NUNITS (mode) == 1
3511 && (GET_MODE_BITSIZE (mode) <= 32
3512 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
3514 rtx reg = gen_reg_rtx (Pmode);
3515 emit_insn (gen_elf_high (reg, x));
3516 return gen_rtx_LO_SUM (Pmode, reg, x);
3518 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
3521 && ! MACHO_DYNAMIC_NO_PIC_P
3523 && GET_CODE (x) != CONST_INT
3524 && GET_CODE (x) != CONST_DOUBLE
3526 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
3530 rtx reg = gen_reg_rtx (Pmode);
3531 emit_insn (gen_macho_high (reg, x));
3532 return gen_rtx_LO_SUM (Pmode, reg, x);
3535 && constant_pool_expr_p (x)
3536 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
3538 return create_TOC_reference (x);
3544 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
3545 We need to emit DTP-relative relocations. */
3548 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
3553 fputs ("\t.long\t", file);
3556 fputs (DOUBLE_INT_ASM_OP, file);
3561 output_addr_const (file, x);
3562 fputs ("@dtprel+0x8000", file);
3565 /* Construct the SYMBOL_REF for the tls_get_addr function. */
3567 static GTY(()) rtx rs6000_tls_symbol;
3569 rs6000_tls_get_addr (void)
3571 if (!rs6000_tls_symbol)
3572 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
3574 return rs6000_tls_symbol;
3577 /* Construct the SYMBOL_REF for TLS GOT references. */
3579 static GTY(()) rtx rs6000_got_symbol;
3581 rs6000_got_sym (void)
3583 if (!rs6000_got_symbol)
3585 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
3586 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
3587 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
3590 return rs6000_got_symbol;
3593 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
3594 this (thread-local) address. */
3597 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
3601 dest = gen_reg_rtx (Pmode);
3602 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3608 tlsreg = gen_rtx_REG (Pmode, 13);
3609 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3613 tlsreg = gen_rtx_REG (Pmode, 2);
3614 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3618 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3622 tmp = gen_reg_rtx (Pmode);
3625 tlsreg = gen_rtx_REG (Pmode, 13);
3626 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3630 tlsreg = gen_rtx_REG (Pmode, 2);
3631 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3635 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3637 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3642 rtx r3, got, tga, tmp1, tmp2, eqv;
3644 /* We currently use relocations like @got@tlsgd for tls, which
3645 means the linker will handle allocation of tls entries, placing
3646 them in the .got section. So use a pointer to the .got section,
3647 not one to secondary TOC sections used by 64-bit -mminimal-toc,
3648 or to secondary GOT sections used by 32-bit -fPIC. */
3650 got = gen_rtx_REG (Pmode, 2);
3654 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3657 rtx gsym = rs6000_got_sym ();
3658 got = gen_reg_rtx (Pmode);
3660 rs6000_emit_move (got, gsym, Pmode);
3666 tmp1 = gen_reg_rtx (Pmode);
3667 tmp2 = gen_reg_rtx (Pmode);
3668 tmp3 = gen_reg_rtx (Pmode);
3669 mem = gen_const_mem (Pmode, tmp1);
3671 first = emit_insn (gen_load_toc_v4_PIC_1b (gsym));
3672 emit_move_insn (tmp1,
3673 gen_rtx_REG (Pmode, LR_REGNO));
3674 emit_move_insn (tmp2, mem);
3675 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3676 last = emit_move_insn (got, tmp3);
3677 set_unique_reg_note (last, REG_EQUAL, gsym);
3678 maybe_encapsulate_block (first, last, gsym);
3683 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3685 r3 = gen_rtx_REG (Pmode, 3);
3687 insn = gen_tls_gd_64 (r3, got, addr);
3689 insn = gen_tls_gd_32 (r3, got, addr);
3692 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3693 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3694 insn = emit_call_insn (insn);
3695 CONST_OR_PURE_CALL_P (insn) = 1;
3696 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3697 insn = get_insns ();
3699 emit_libcall_block (insn, dest, r3, addr);
3701 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3703 r3 = gen_rtx_REG (Pmode, 3);
3705 insn = gen_tls_ld_64 (r3, got);
3707 insn = gen_tls_ld_32 (r3, got);
3710 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3711 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3712 insn = emit_call_insn (insn);
3713 CONST_OR_PURE_CALL_P (insn) = 1;
3714 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3715 insn = get_insns ();
3717 tmp1 = gen_reg_rtx (Pmode);
3718 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3720 emit_libcall_block (insn, tmp1, r3, eqv);
3721 if (rs6000_tls_size == 16)
3724 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3726 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3728 else if (rs6000_tls_size == 32)
3730 tmp2 = gen_reg_rtx (Pmode);
3732 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3734 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3737 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3739 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3743 tmp2 = gen_reg_rtx (Pmode);
3745 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3747 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3749 insn = gen_rtx_SET (Pmode, dest,
3750 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3756 /* IE, or 64-bit offset LE. */
3757 tmp2 = gen_reg_rtx (Pmode);
3759 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3761 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3764 insn = gen_tls_tls_64 (dest, tmp2, addr);
3766 insn = gen_tls_tls_32 (dest, tmp2, addr);
3774 /* Return 1 if X contains a thread-local symbol. */
3777 rs6000_tls_referenced_p (rtx x)
3779 if (! TARGET_HAVE_TLS)
3782 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3785 /* Return 1 if *X is a thread-local symbol. This is the same as
3786 rs6000_tls_symbol_ref except for the type of the unused argument. */
3789 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3791 return RS6000_SYMBOL_REF_TLS_P (*x);
3794 /* The convention appears to be to define this wherever it is used.
3795 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3796 is now used here. */
3797 #ifndef REG_MODE_OK_FOR_BASE_P
3798 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3801 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3802 replace the input X, or the original X if no replacement is called for.
3803 The output parameter *WIN is 1 if the calling macro should goto WIN,
3806 For RS/6000, we wish to handle large displacements off a base
3807 register by splitting the addend across an addiu/addis and the mem insn.
3808 This cuts number of extra insns needed from 3 to 1.
3810 On Darwin, we use this to generate code for floating point constants.
3811 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3812 The Darwin code is inside #if TARGET_MACHO because only then is
3813 machopic_function_base_name() defined. */
3815 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3816 int opnum, int type,
3817 int ind_levels ATTRIBUTE_UNUSED, int *win)
3819 /* We must recognize output that we have already generated ourselves. */
3820 if (GET_CODE (x) == PLUS
3821 && GET_CODE (XEXP (x, 0)) == PLUS
3822 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3823 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3824 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3826 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3827 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3828 opnum, (enum reload_type)type);
3834 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3835 && GET_CODE (x) == LO_SUM
3836 && GET_CODE (XEXP (x, 0)) == PLUS
3837 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3838 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3839 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3840 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3841 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3842 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3843 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3845 /* Result of previous invocation of this function on Darwin
3846 floating point constant. */
3847 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3848 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3849 opnum, (enum reload_type)type);
3855 /* Force ld/std non-word aligned offset into base register by wrapping
3857 if (GET_CODE (x) == PLUS
3858 && GET_CODE (XEXP (x, 0)) == REG
3859 && REGNO (XEXP (x, 0)) < 32
3860 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3861 && GET_CODE (XEXP (x, 1)) == CONST_INT
3862 && (INTVAL (XEXP (x, 1)) & 3) != 0
3863 && !ALTIVEC_VECTOR_MODE (mode)
3864 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3865 && TARGET_POWERPC64)
3867 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3868 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3869 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3870 opnum, (enum reload_type) type);
3875 if (GET_CODE (x) == PLUS
3876 && GET_CODE (XEXP (x, 0)) == REG
3877 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3878 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3879 && GET_CODE (XEXP (x, 1)) == CONST_INT
3880 && !SPE_VECTOR_MODE (mode)
3881 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
3883 && !ALTIVEC_VECTOR_MODE (mode))
3885 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3886 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3888 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3890 /* Check for 32-bit overflow. */
3891 if (high + low != val)
3897 /* Reload the high part into a base reg; leave the low part
3898 in the mem directly. */
3900 x = gen_rtx_PLUS (GET_MODE (x),
3901 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3905 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3906 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3907 opnum, (enum reload_type)type);
3912 if (GET_CODE (x) == SYMBOL_REF
3913 && !ALTIVEC_VECTOR_MODE (mode)
3914 && !SPE_VECTOR_MODE (mode)
3916 && DEFAULT_ABI == ABI_DARWIN
3917 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3919 && DEFAULT_ABI == ABI_V4
3922 /* Don't do this for TFmode or TDmode, since the result isn't offsettable.
3923 The same goes for DImode without 64-bit gprs and DFmode
3927 && (mode != DImode || TARGET_POWERPC64)
3928 && (mode != DFmode || TARGET_POWERPC64
3929 || (TARGET_FPRS && TARGET_HARD_FLOAT)))
3934 rtx offset = gen_rtx_CONST (Pmode,
3935 gen_rtx_MINUS (Pmode, x,
3936 machopic_function_base_sym ()));
3937 x = gen_rtx_LO_SUM (GET_MODE (x),
3938 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3939 gen_rtx_HIGH (Pmode, offset)), offset);
3943 x = gen_rtx_LO_SUM (GET_MODE (x),
3944 gen_rtx_HIGH (Pmode, x), x);
3946 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3947 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3948 opnum, (enum reload_type)type);
3953 /* Reload an offset address wrapped by an AND that represents the
3954 masking of the lower bits. Strip the outer AND and let reload
3955 convert the offset address into an indirect address. */
3957 && ALTIVEC_VECTOR_MODE (mode)
3958 && GET_CODE (x) == AND
3959 && GET_CODE (XEXP (x, 0)) == PLUS
3960 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3961 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3962 && GET_CODE (XEXP (x, 1)) == CONST_INT
3963 && INTVAL (XEXP (x, 1)) == -16)
3971 && constant_pool_expr_p (x)
3972 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3974 x = create_TOC_reference (x);
3982 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3983 that is a valid memory address for an instruction.
3984 The MODE argument is the machine mode for the MEM expression
3985 that wants to use this address.
3987 On the RS/6000, there are four valid address: a SYMBOL_REF that
3988 refers to a constant pool entry of an address (or the sum of it
3989 plus a constant), a short (16-bit signed) constant plus a register,
3990 the sum of two registers, or a register indirect, possibly with an
3991 auto-increment. For DFmode and DImode with a constant plus register,
3992 we must ensure that both words are addressable or PowerPC64 with offset
3995 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3996 32-bit DImode, TImode, TFmode, TDmode), indexed addressing cannot be used
3997 because adjacent memory cells are accessed by adding word-sized offsets
3998 during assembly output. */
4000 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
4002 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
4004 && ALTIVEC_VECTOR_MODE (mode)
4005 && GET_CODE (x) == AND
4006 && GET_CODE (XEXP (x, 1)) == CONST_INT
4007 && INTVAL (XEXP (x, 1)) == -16)
4010 if (RS6000_SYMBOL_REF_TLS_P (x))
4012 if (legitimate_indirect_address_p (x, reg_ok_strict))
4014 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
4015 && !ALTIVEC_VECTOR_MODE (mode)
4016 && !SPE_VECTOR_MODE (mode)
4019 /* Restrict addressing for DI because of our SUBREG hackery. */
4020 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode
4023 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
4025 if (legitimate_small_data_p (mode, x))
4027 if (legitimate_constant_pool_address_p (x))
4029 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
4031 && GET_CODE (x) == PLUS
4032 && GET_CODE (XEXP (x, 0)) == REG
4033 && (XEXP (x, 0) == virtual_stack_vars_rtx
4034 || XEXP (x, 0) == arg_pointer_rtx)
4035 && GET_CODE (XEXP (x, 1)) == CONST_INT)
4037 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
4042 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4044 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
4045 && (TARGET_POWERPC64 || mode != DImode)
4046 && legitimate_indexed_address_p (x, reg_ok_strict))
4048 if (GET_CODE (x) == PRE_MODIFY
4052 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
4054 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
4055 && (TARGET_POWERPC64 || mode != DImode)
4056 && !ALTIVEC_VECTOR_MODE (mode)
4057 && !SPE_VECTOR_MODE (mode)
4058 /* Restrict addressing for DI because of our SUBREG hackery. */
4059 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
4061 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict)
4062 && (rs6000_legitimate_offset_address_p (mode, XEXP (x, 1), reg_ok_strict)
4063 || legitimate_indexed_address_p (XEXP (x, 1), reg_ok_strict))
4064 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4066 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
4071 /* Go to LABEL if ADDR (a legitimate address expression)
4072 has an effect that depends on the machine mode it is used for.
4074 On the RS/6000 this is true of all integral offsets (since AltiVec
4075 modes don't allow them) or is a pre-increment or decrement.
4077 ??? Except that due to conceptual problems in offsettable_address_p
4078 we can't really report the problems of integral offsets. So leave
4079 this assuming that the adjustable offset must be valid for the
4080 sub-words of a TFmode operand, which is what we had before. */
4083 rs6000_mode_dependent_address (rtx addr)
4085 switch (GET_CODE (addr))
4088 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
4090 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
4091 return val + 12 + 0x8000 >= 0x10000;
4101 return TARGET_UPDATE;
4110 /* More elaborate version of recog's offsettable_memref_p predicate
4111 that works around the ??? note of rs6000_mode_dependent_address.
4112 In particular it accepts
4114 (mem:DI (plus:SI (reg/f:SI 31 31) (const_int 32760 [0x7ff8])))
4116 in 32-bit mode, that the recog predicate rejects. */
4119 rs6000_offsettable_memref_p (rtx op)
4124 /* First mimic offsettable_memref_p. */
4125 if (offsettable_address_p (1, GET_MODE (op), XEXP (op, 0)))
4128 /* offsettable_address_p invokes rs6000_mode_dependent_address, but
4129 the latter predicate knows nothing about the mode of the memory
4130 reference and, therefore, assumes that it is the largest supported
4131 mode (TFmode). As a consequence, legitimate offsettable memory
4132 references are rejected. rs6000_legitimate_offset_address_p contains
4133 the correct logic for the PLUS case of rs6000_mode_dependent_address. */
4134 return rs6000_legitimate_offset_address_p (GET_MODE (op), XEXP (op, 0), 1);
4137 /* Return number of consecutive hard regs needed starting at reg REGNO
4138 to hold something of mode MODE.
4139 This is ordinarily the length in words of a value of mode MODE
4140 but can be less for certain modes in special long registers.
4142 For the SPE, GPRs are 64 bits but only 32 bits are visible in
4143 scalar instructions. The upper 32 bits are only available to the
4146 POWER and PowerPC GPRs hold 32 bits worth;
4147 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
4150 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
4152 if (FP_REGNO_P (regno))
4153 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4155 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
4156 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
4158 if (ALTIVEC_REGNO_P (regno))
4160 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
4162 /* The value returned for SCmode in the E500 double case is 2 for
4163 ABI compatibility; storing an SCmode value in a single register
4164 would require function_arg and rs6000_spe_function_arg to handle
4165 SCmode so as to pass the value correctly in a pair of
4167 if (TARGET_E500_DOUBLE && FLOAT_MODE_P (mode) && mode != SCmode)
4168 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
4170 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
4173 /* Change register usage conditional on target flags. */
4175 rs6000_conditional_register_usage (void)
4179 /* Set MQ register fixed (already call_used) if not POWER
4180 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
4185 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
4187 fixed_regs[13] = call_used_regs[13]
4188 = call_really_used_regs[13] = 1;
4190 /* Conditionally disable FPRs. */
4191 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
4192 for (i = 32; i < 64; i++)
4193 fixed_regs[i] = call_used_regs[i]
4194 = call_really_used_regs[i] = 1;
4196 /* The TOC register is not killed across calls in a way that is
4197 visible to the compiler. */
4198 if (DEFAULT_ABI == ABI_AIX)
4199 call_really_used_regs[2] = 0;
4201 if (DEFAULT_ABI == ABI_V4
4202 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4204 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4206 if (DEFAULT_ABI == ABI_V4
4207 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
4209 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4210 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4211 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4213 if (DEFAULT_ABI == ABI_DARWIN
4214 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
4215 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4216 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4217 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4219 if (TARGET_TOC && TARGET_MINIMAL_TOC)
4220 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
4221 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
4224 global_regs[VSCR_REGNO] = 1;
4228 global_regs[SPEFSCR_REGNO] = 1;
4229 /* We used to use r14 as FIXED_SCRATCH to address SPE 64-bit
4230 registers in prologues and epilogues. We no longer use r14
4231 for FIXED_SCRATCH, but we're keeping r14 out of the allocation
4232 pool for link-compatibility with older versions of GCC. Once
4233 "old" code has died out, we can return r14 to the allocation
4236 = call_used_regs[14]
4237 = call_really_used_regs[14] = 1;
4240 if (! TARGET_ALTIVEC)
4242 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
4243 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
4244 call_really_used_regs[VRSAVE_REGNO] = 1;
4247 if (TARGET_ALTIVEC_ABI)
4248 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
4249 call_used_regs[i] = call_really_used_regs[i] = 1;
4252 /* Try to output insns to set TARGET equal to the constant C if it can
4253 be done in less than N insns. Do all computations in MODE.
4254 Returns the place where the output has been placed if it can be
4255 done and the insns have been emitted. If it would take more than N
4256 insns, zero is returned and no insns and emitted. */
4259 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
4260 rtx source, int n ATTRIBUTE_UNUSED)
4262 rtx result, insn, set;
4263 HOST_WIDE_INT c0, c1;
4270 dest = gen_reg_rtx (mode);
4271 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
4275 result = !can_create_pseudo_p () ? dest : gen_reg_rtx (SImode);
4277 emit_insn (gen_rtx_SET (VOIDmode, copy_rtx (result),
4278 GEN_INT (INTVAL (source)
4279 & (~ (HOST_WIDE_INT) 0xffff))));
4280 emit_insn (gen_rtx_SET (VOIDmode, dest,
4281 gen_rtx_IOR (SImode, copy_rtx (result),
4282 GEN_INT (INTVAL (source) & 0xffff))));
4287 switch (GET_CODE (source))
4290 c0 = INTVAL (source);
4295 #if HOST_BITS_PER_WIDE_INT >= 64
4296 c0 = CONST_DOUBLE_LOW (source);
4299 c0 = CONST_DOUBLE_LOW (source);
4300 c1 = CONST_DOUBLE_HIGH (source);
4308 result = rs6000_emit_set_long_const (dest, c0, c1);
4315 insn = get_last_insn ();
4316 set = single_set (insn);
4317 if (! CONSTANT_P (SET_SRC (set)))
4318 set_unique_reg_note (insn, REG_EQUAL, source);
4323 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
4324 fall back to a straight forward decomposition. We do this to avoid
4325 exponential run times encountered when looking for longer sequences
4326 with rs6000_emit_set_const. */
4328 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
4330 if (!TARGET_POWERPC64)
4332 rtx operand1, operand2;
4334 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
4336 operand2 = operand_subword_force (copy_rtx (dest), WORDS_BIG_ENDIAN != 0,
4338 emit_move_insn (operand1, GEN_INT (c1));
4339 emit_move_insn (operand2, GEN_INT (c2));
4343 HOST_WIDE_INT ud1, ud2, ud3, ud4;
4346 ud2 = (c1 & 0xffff0000) >> 16;
4347 #if HOST_BITS_PER_WIDE_INT >= 64
4351 ud4 = (c2 & 0xffff0000) >> 16;
4353 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
4354 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
4357 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
4359 emit_move_insn (dest, GEN_INT (ud1));
4362 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
4363 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
4366 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
4369 emit_move_insn (dest, GEN_INT (ud2 << 16));
4371 emit_move_insn (copy_rtx (dest),
4372 gen_rtx_IOR (DImode, copy_rtx (dest),
4375 else if ((ud4 == 0xffff && (ud3 & 0x8000))
4376 || (ud4 == 0 && ! (ud3 & 0x8000)))
4379 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
4382 emit_move_insn (dest, GEN_INT (ud3 << 16));
4385 emit_move_insn (copy_rtx (dest),
4386 gen_rtx_IOR (DImode, copy_rtx (dest),
4388 emit_move_insn (copy_rtx (dest),
4389 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4392 emit_move_insn (copy_rtx (dest),
4393 gen_rtx_IOR (DImode, copy_rtx (dest),
4399 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
4402 emit_move_insn (dest, GEN_INT (ud4 << 16));
4405 emit_move_insn (copy_rtx (dest),
4406 gen_rtx_IOR (DImode, copy_rtx (dest),
4409 emit_move_insn (copy_rtx (dest),
4410 gen_rtx_ASHIFT (DImode, copy_rtx (dest),
4413 emit_move_insn (copy_rtx (dest),
4414 gen_rtx_IOR (DImode, copy_rtx (dest),
4415 GEN_INT (ud2 << 16)));
4417 emit_move_insn (copy_rtx (dest),
4418 gen_rtx_IOR (DImode, copy_rtx (dest), GEN_INT (ud1)));
4424 /* Helper for the following. Get rid of [r+r] memory refs
4425 in cases where it won't work (TImode, TFmode, TDmode). */
4428 rs6000_eliminate_indexed_memrefs (rtx operands[2])
4430 if (GET_CODE (operands[0]) == MEM
4431 && GET_CODE (XEXP (operands[0], 0)) != REG
4432 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
4433 && ! reload_in_progress)
4435 = replace_equiv_address (operands[0],
4436 copy_addr_to_reg (XEXP (operands[0], 0)));
4438 if (GET_CODE (operands[1]) == MEM
4439 && GET_CODE (XEXP (operands[1], 0)) != REG
4440 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
4441 && ! reload_in_progress)
4443 = replace_equiv_address (operands[1],
4444 copy_addr_to_reg (XEXP (operands[1], 0)));
4447 /* Emit a move from SOURCE to DEST in mode MODE. */
4449 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
4453 operands[1] = source;
4455 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
4456 if (GET_CODE (operands[1]) == CONST_DOUBLE
4457 && ! FLOAT_MODE_P (mode)
4458 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4460 /* FIXME. This should never happen. */
4461 /* Since it seems that it does, do the safe thing and convert
4463 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
4465 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
4466 || FLOAT_MODE_P (mode)
4467 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
4468 || CONST_DOUBLE_LOW (operands[1]) < 0)
4469 && (CONST_DOUBLE_HIGH (operands[1]) != -1
4470 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
4472 /* Check if GCC is setting up a block move that will end up using FP
4473 registers as temporaries. We must make sure this is acceptable. */
4474 if (GET_CODE (operands[0]) == MEM
4475 && GET_CODE (operands[1]) == MEM
4477 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
4478 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
4479 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
4480 ? 32 : MEM_ALIGN (operands[0])))
4481 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
4483 : MEM_ALIGN (operands[1]))))
4484 && ! MEM_VOLATILE_P (operands [0])
4485 && ! MEM_VOLATILE_P (operands [1]))
4487 emit_move_insn (adjust_address (operands[0], SImode, 0),
4488 adjust_address (operands[1], SImode, 0));
4489 emit_move_insn (adjust_address (copy_rtx (operands[0]), SImode, 4),
4490 adjust_address (copy_rtx (operands[1]), SImode, 4));
4494 if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM
4495 && !gpc_reg_operand (operands[1], mode))
4496 operands[1] = force_reg (mode, operands[1]);
4498 if (mode == SFmode && ! TARGET_POWERPC
4499 && TARGET_HARD_FLOAT && TARGET_FPRS
4500 && GET_CODE (operands[0]) == MEM)
4504 if (reload_in_progress || reload_completed)
4505 regnum = true_regnum (operands[1]);
4506 else if (GET_CODE (operands[1]) == REG)
4507 regnum = REGNO (operands[1]);
4511 /* If operands[1] is a register, on POWER it may have
4512 double-precision data in it, so truncate it to single
4514 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
4517 newreg = (!can_create_pseudo_p () ? copy_rtx (operands[1])
4518 : gen_reg_rtx (mode));
4519 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
4520 operands[1] = newreg;
4524 /* Recognize the case where operand[1] is a reference to thread-local
4525 data and load its address to a register. */
4526 if (rs6000_tls_referenced_p (operands[1]))
4528 enum tls_model model;
4529 rtx tmp = operands[1];
4532 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
4534 addend = XEXP (XEXP (tmp, 0), 1);
4535 tmp = XEXP (XEXP (tmp, 0), 0);
4538 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
4539 model = SYMBOL_REF_TLS_MODEL (tmp);
4540 gcc_assert (model != 0);
4542 tmp = rs6000_legitimize_tls_address (tmp, model);
4545 tmp = gen_rtx_PLUS (mode, tmp, addend);
4546 tmp = force_operand (tmp, operands[0]);
4551 /* Handle the case where reload calls us with an invalid address. */
4552 if (reload_in_progress && mode == Pmode
4553 && (! general_operand (operands[1], mode)
4554 || ! nonimmediate_operand (operands[0], mode)))
4557 /* 128-bit constant floating-point values on Darwin should really be
4558 loaded as two parts. */
4559 if (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128
4560 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
4562 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
4563 know how to get a DFmode SUBREG of a TFmode. */
4564 enum machine_mode imode = (TARGET_E500_DOUBLE ? DFmode : DImode);
4565 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode, 0),
4566 simplify_gen_subreg (imode, operands[1], mode, 0),
4568 rs6000_emit_move (simplify_gen_subreg (imode, operands[0], mode,
4569 GET_MODE_SIZE (imode)),
4570 simplify_gen_subreg (imode, operands[1], mode,
4571 GET_MODE_SIZE (imode)),
4576 /* FIXME: In the long term, this switch statement should go away
4577 and be replaced by a sequence of tests based on things like
4583 if (CONSTANT_P (operands[1])
4584 && GET_CODE (operands[1]) != CONST_INT)
4585 operands[1] = force_const_mem (mode, operands[1]);
4590 rs6000_eliminate_indexed_memrefs (operands);
4596 if (CONSTANT_P (operands[1])
4597 && ! easy_fp_constant (operands[1], mode))
4598 operands[1] = force_const_mem (mode, operands[1]);
4609 if (CONSTANT_P (operands[1])
4610 && !easy_vector_constant (operands[1], mode))
4611 operands[1] = force_const_mem (mode, operands[1]);
4616 /* Use default pattern for address of ELF small data */
4619 && DEFAULT_ABI == ABI_V4
4620 && (GET_CODE (operands[1]) == SYMBOL_REF
4621 || GET_CODE (operands[1]) == CONST)
4622 && small_data_operand (operands[1], mode))
4624 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4628 if (DEFAULT_ABI == ABI_V4
4629 && mode == Pmode && mode == SImode
4630 && flag_pic == 1 && got_operand (operands[1], mode))
4632 emit_insn (gen_movsi_got (operands[0], operands[1]));
4636 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
4640 && CONSTANT_P (operands[1])
4641 && GET_CODE (operands[1]) != HIGH
4642 && GET_CODE (operands[1]) != CONST_INT)
4644 rtx target = (!can_create_pseudo_p ()
4646 : gen_reg_rtx (mode));
4648 /* If this is a function address on -mcall-aixdesc,
4649 convert it to the address of the descriptor. */
4650 if (DEFAULT_ABI == ABI_AIX
4651 && GET_CODE (operands[1]) == SYMBOL_REF
4652 && XSTR (operands[1], 0)[0] == '.')
4654 const char *name = XSTR (operands[1], 0);
4656 while (*name == '.')
4658 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
4659 CONSTANT_POOL_ADDRESS_P (new_ref)
4660 = CONSTANT_POOL_ADDRESS_P (operands[1]);
4661 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
4662 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
4663 SYMBOL_REF_DATA (new_ref) = SYMBOL_REF_DATA (operands[1]);
4664 operands[1] = new_ref;
4667 if (DEFAULT_ABI == ABI_DARWIN)
4670 if (MACHO_DYNAMIC_NO_PIC_P)
4672 /* Take care of any required data indirection. */
4673 operands[1] = rs6000_machopic_legitimize_pic_address (
4674 operands[1], mode, operands[0]);
4675 if (operands[0] != operands[1])
4676 emit_insn (gen_rtx_SET (VOIDmode,
4677 operands[0], operands[1]));
4681 emit_insn (gen_macho_high (target, operands[1]));
4682 emit_insn (gen_macho_low (operands[0], target, operands[1]));
4686 emit_insn (gen_elf_high (target, operands[1]));
4687 emit_insn (gen_elf_low (operands[0], target, operands[1]));
4691 /* If this is a SYMBOL_REF that refers to a constant pool entry,
4692 and we have put it in the TOC, we just need to make a TOC-relative
4695 && GET_CODE (operands[1]) == SYMBOL_REF
4696 && constant_pool_expr_p (operands[1])
4697 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4698 get_pool_mode (operands[1])))
4700 operands[1] = create_TOC_reference (operands[1]);
4702 else if (mode == Pmode
4703 && CONSTANT_P (operands[1])
4704 && ((GET_CODE (operands[1]) != CONST_INT
4705 && ! easy_fp_constant (operands[1], mode))
4706 || (GET_CODE (operands[1]) == CONST_INT
4707 && num_insns_constant (operands[1], mode) > 2)
4708 || (GET_CODE (operands[0]) == REG
4709 && FP_REGNO_P (REGNO (operands[0]))))
4710 && GET_CODE (operands[1]) != HIGH
4711 && ! legitimate_constant_pool_address_p (operands[1])
4712 && ! toc_relative_expr_p (operands[1]))
4714 /* Emit a USE operation so that the constant isn't deleted if
4715 expensive optimizations are turned on because nobody
4716 references it. This should only be done for operands that
4717 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4718 This should not be done for operands that contain LABEL_REFs.
4719 For now, we just handle the obvious case. */
4720 if (GET_CODE (operands[1]) != LABEL_REF)
4721 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4724 /* Darwin uses a special PIC legitimizer. */
4725 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4728 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4730 if (operands[0] != operands[1])
4731 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4736 /* If we are to limit the number of things we put in the TOC and
4737 this is a symbol plus a constant we can add in one insn,
4738 just put the symbol in the TOC and add the constant. Don't do
4739 this if reload is in progress. */
4740 if (GET_CODE (operands[1]) == CONST
4741 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4742 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4743 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4744 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4745 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4746 && ! side_effects_p (operands[0]))
4749 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4750 rtx other = XEXP (XEXP (operands[1], 0), 1);
4752 sym = force_reg (mode, sym);
4754 emit_insn (gen_addsi3 (operands[0], sym, other));
4756 emit_insn (gen_adddi3 (operands[0], sym, other));
4760 operands[1] = force_const_mem (mode, operands[1]);
4763 && constant_pool_expr_p (XEXP (operands[1], 0))
4764 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4765 get_pool_constant (XEXP (operands[1], 0)),
4766 get_pool_mode (XEXP (operands[1], 0))))
4769 = gen_const_mem (mode,
4770 create_TOC_reference (XEXP (operands[1], 0)));
4771 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4777 rs6000_eliminate_indexed_memrefs (operands);
4781 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4783 gen_rtx_SET (VOIDmode,
4784 operands[0], operands[1]),
4785 gen_rtx_CLOBBER (VOIDmode,
4786 gen_rtx_SCRATCH (SImode)))));
4795 /* Above, we may have called force_const_mem which may have returned
4796 an invalid address. If we can, fix this up; otherwise, reload will
4797 have to deal with it. */
4798 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4799 operands[1] = validize_mem (operands[1]);
4802 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4805 /* Nonzero if we can use a floating-point register to pass this arg. */
4806 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4807 (SCALAR_FLOAT_MODE_P (MODE) \
4808 && (MODE) != SDmode \
4809 && (CUM)->fregno <= FP_ARG_MAX_REG \
4810 && TARGET_HARD_FLOAT && TARGET_FPRS)
4812 /* Nonzero if we can use an AltiVec register to pass this arg. */
4813 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4814 (ALTIVEC_VECTOR_MODE (MODE) \
4815 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4816 && TARGET_ALTIVEC_ABI \
4819 /* Return a nonzero value to say to return the function value in
4820 memory, just as large structures are always returned. TYPE will be
4821 the data type of the value, and FNTYPE will be the type of the
4822 function doing the returning, or @code{NULL} for libcalls.
4824 The AIX ABI for the RS/6000 specifies that all structures are
4825 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4826 specifies that structures <= 8 bytes are returned in r3/r4, but a
4827 draft put them in memory, and GCC used to implement the draft
4828 instead of the final standard. Therefore, aix_struct_return
4829 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4830 compatibility can change DRAFT_V4_STRUCT_RET to override the
4831 default, and -m switches get the final word. See
4832 rs6000_override_options for more details.
4834 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4835 long double support is enabled. These values are returned in memory.
4837 int_size_in_bytes returns -1 for variable size objects, which go in
4838 memory always. The cast to unsigned makes -1 > 8. */
4841 rs6000_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
4843 /* In the darwin64 abi, try to use registers for larger structs
4845 if (rs6000_darwin64_abi
4846 && TREE_CODE (type) == RECORD_TYPE
4847 && int_size_in_bytes (type) > 0)
4849 CUMULATIVE_ARGS valcum;
4853 valcum.fregno = FP_ARG_MIN_REG;
4854 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4855 /* Do a trial code generation as if this were going to be passed
4856 as an argument; if any part goes in memory, we return NULL. */
4857 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4860 /* Otherwise fall through to more conventional ABI rules. */
4863 if (AGGREGATE_TYPE_P (type)
4864 && (aix_struct_return
4865 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4868 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4869 modes only exist for GCC vector types if -maltivec. */
4870 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4871 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4874 /* Return synthetic vectors in memory. */
4875 if (TREE_CODE (type) == VECTOR_TYPE
4876 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4878 static bool warned_for_return_big_vectors = false;
4879 if (!warned_for_return_big_vectors)
4881 warning (0, "GCC vector returned by reference: "
4882 "non-standard ABI extension with no compatibility guarantee");
4883 warned_for_return_big_vectors = true;
4888 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && TYPE_MODE (type) == TFmode)
4894 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4895 for a call to a function whose data type is FNTYPE.
4896 For a library call, FNTYPE is 0.
4898 For incoming args we set the number of arguments in the prototype large
4899 so we never return a PARALLEL. */
4902 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4903 rtx libname ATTRIBUTE_UNUSED, int incoming,
4904 int libcall, int n_named_args)
4906 static CUMULATIVE_ARGS zero_cumulative;
4908 *cum = zero_cumulative;
4910 cum->fregno = FP_ARG_MIN_REG;
4911 cum->vregno = ALTIVEC_ARG_MIN_REG;
4912 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4913 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4914 ? CALL_LIBCALL : CALL_NORMAL);
4915 cum->sysv_gregno = GP_ARG_MIN_REG;
4916 cum->stdarg = fntype
4917 && (TYPE_ARG_TYPES (fntype) != 0
4918 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4919 != void_type_node));
4921 cum->nargs_prototype = 0;
4922 if (incoming || cum->prototype)
4923 cum->nargs_prototype = n_named_args;
4925 /* Check for a longcall attribute. */
4926 if ((!fntype && rs6000_default_long_calls)
4928 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4929 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4930 cum->call_cookie |= CALL_LONG;
4932 if (TARGET_DEBUG_ARG)
4934 fprintf (stderr, "\ninit_cumulative_args:");
4937 tree ret_type = TREE_TYPE (fntype);
4938 fprintf (stderr, " ret code = %s,",
4939 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4942 if (cum->call_cookie & CALL_LONG)
4943 fprintf (stderr, " longcall,");
4945 fprintf (stderr, " proto = %d, nargs = %d\n",
4946 cum->prototype, cum->nargs_prototype);
4951 && TARGET_ALTIVEC_ABI
4952 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4954 error ("cannot return value in vector register because"
4955 " altivec instructions are disabled, use -maltivec"
4960 /* Return true if TYPE must be passed on the stack and not in registers. */
4963 rs6000_must_pass_in_stack (enum machine_mode mode, const_tree type)
4965 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4966 return must_pass_in_stack_var_size (mode, type);
4968 return must_pass_in_stack_var_size_or_pad (mode, type);
4971 /* If defined, a C expression which determines whether, and in which
4972 direction, to pad out an argument with extra space. The value
4973 should be of type `enum direction': either `upward' to pad above
4974 the argument, `downward' to pad below, or `none' to inhibit
4977 For the AIX ABI structs are always stored left shifted in their
4981 function_arg_padding (enum machine_mode mode, const_tree type)
4983 #ifndef AGGREGATE_PADDING_FIXED
4984 #define AGGREGATE_PADDING_FIXED 0
4986 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4987 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4990 if (!AGGREGATE_PADDING_FIXED)
4992 /* GCC used to pass structures of the same size as integer types as
4993 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4994 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4995 passed padded downward, except that -mstrict-align further
4996 muddied the water in that multi-component structures of 2 and 4
4997 bytes in size were passed padded upward.
4999 The following arranges for best compatibility with previous
5000 versions of gcc, but removes the -mstrict-align dependency. */
5001 if (BYTES_BIG_ENDIAN)
5003 HOST_WIDE_INT size = 0;
5005 if (mode == BLKmode)
5007 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5008 size = int_size_in_bytes (type);
5011 size = GET_MODE_SIZE (mode);
5013 if (size == 1 || size == 2 || size == 4)
5019 if (AGGREGATES_PAD_UPWARD_ALWAYS)
5021 if (type != 0 && AGGREGATE_TYPE_P (type))
5025 /* Fall back to the default. */
5026 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
5029 /* If defined, a C expression that gives the alignment boundary, in bits,
5030 of an argument with the specified mode and type. If it is not defined,
5031 PARM_BOUNDARY is used for all arguments.
5033 V.4 wants long longs and doubles to be double word aligned. Just
5034 testing the mode size is a boneheaded way to do this as it means
5035 that other types such as complex int are also double word aligned.
5036 However, we're stuck with this because changing the ABI might break
5037 existing library interfaces.
5039 Doubleword align SPE vectors.
5040 Quadword align Altivec vectors.
5041 Quadword align large synthetic vector types. */
5044 function_arg_boundary (enum machine_mode mode, tree type)
5046 if (DEFAULT_ABI == ABI_V4
5047 && (GET_MODE_SIZE (mode) == 8
5048 || (TARGET_HARD_FLOAT
5050 && (mode == TFmode || mode == TDmode))))
5052 else if (SPE_VECTOR_MODE (mode)
5053 || (type && TREE_CODE (type) == VECTOR_TYPE
5054 && int_size_in_bytes (type) >= 8
5055 && int_size_in_bytes (type) < 16))
5057 else if (ALTIVEC_VECTOR_MODE (mode)
5058 || (type && TREE_CODE (type) == VECTOR_TYPE
5059 && int_size_in_bytes (type) >= 16))
5061 else if (rs6000_darwin64_abi && mode == BLKmode
5062 && type && TYPE_ALIGN (type) > 64)
5065 return PARM_BOUNDARY;
5068 /* For a function parm of MODE and TYPE, return the starting word in
5069 the parameter area. NWORDS of the parameter area are already used. */
5072 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
5075 unsigned int parm_offset;
5077 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
5078 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
5079 return nwords + (-(parm_offset + nwords) & align);
5082 /* Compute the size (in words) of a function argument. */
5084 static unsigned long
5085 rs6000_arg_size (enum machine_mode mode, tree type)
5089 if (mode != BLKmode)
5090 size = GET_MODE_SIZE (mode);
5092 size = int_size_in_bytes (type);
5095 return (size + 3) >> 2;
5097 return (size + 7) >> 3;
5100 /* Use this to flush pending int fields. */
5103 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
5104 HOST_WIDE_INT bitpos)
5106 unsigned int startbit, endbit;
5107 int intregs, intoffset;
5108 enum machine_mode mode;
5110 if (cum->intoffset == -1)
5113 intoffset = cum->intoffset;
5114 cum->intoffset = -1;
5116 if (intoffset % BITS_PER_WORD != 0)
5118 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5120 if (mode == BLKmode)
5122 /* We couldn't find an appropriate mode, which happens,
5123 e.g., in packed structs when there are 3 bytes to load.
5124 Back intoffset back to the beginning of the word in this
5126 intoffset = intoffset & -BITS_PER_WORD;
5130 startbit = intoffset & -BITS_PER_WORD;
5131 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5132 intregs = (endbit - startbit) / BITS_PER_WORD;
5133 cum->words += intregs;
5136 /* The darwin64 ABI calls for us to recurse down through structs,
5137 looking for elements passed in registers. Unfortunately, we have
5138 to track int register count here also because of misalignments
5139 in powerpc alignment mode. */
5142 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
5144 HOST_WIDE_INT startbitpos)
5148 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5149 if (TREE_CODE (f) == FIELD_DECL)
5151 HOST_WIDE_INT bitpos = startbitpos;
5152 tree ftype = TREE_TYPE (f);
5153 enum machine_mode mode;
5154 if (ftype == error_mark_node)
5156 mode = TYPE_MODE (ftype);
5158 if (DECL_SIZE (f) != 0
5159 && host_integerp (bit_position (f), 1))
5160 bitpos += int_bit_position (f);
5162 /* ??? FIXME: else assume zero offset. */
5164 if (TREE_CODE (ftype) == RECORD_TYPE)
5165 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
5166 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
5168 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5169 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5170 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
5172 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
5174 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
5178 else if (cum->intoffset == -1)
5179 cum->intoffset = bitpos;
5183 /* Update the data in CUM to advance over an argument
5184 of mode MODE and data type TYPE.
5185 (TYPE is null for libcalls where that information may not be available.)
5187 Note that for args passed by reference, function_arg will be called
5188 with MODE and TYPE set to that of the pointer to the arg, not the arg
5192 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5193 tree type, int named, int depth)
5197 /* Only tick off an argument if we're not recursing. */
5199 cum->nargs_prototype--;
5201 if (TARGET_ALTIVEC_ABI
5202 && (ALTIVEC_VECTOR_MODE (mode)
5203 || (type && TREE_CODE (type) == VECTOR_TYPE
5204 && int_size_in_bytes (type) == 16)))
5208 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5211 if (!TARGET_ALTIVEC)
5212 error ("cannot pass argument in vector register because"
5213 " altivec instructions are disabled, use -maltivec"
5216 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
5217 even if it is going to be passed in a vector register.
5218 Darwin does the same for variable-argument functions. */
5219 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
5220 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
5230 /* Vector parameters must be 16-byte aligned. This places
5231 them at 2 mod 4 in terms of words in 32-bit mode, since
5232 the parameter save area starts at offset 24 from the
5233 stack. In 64-bit mode, they just have to start on an
5234 even word, since the parameter save area is 16-byte
5235 aligned. Space for GPRs is reserved even if the argument
5236 will be passed in memory. */
5238 align = (2 - cum->words) & 3;
5240 align = cum->words & 1;
5241 cum->words += align + rs6000_arg_size (mode, type);
5243 if (TARGET_DEBUG_ARG)
5245 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
5247 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
5248 cum->nargs_prototype, cum->prototype,
5249 GET_MODE_NAME (mode));
5253 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
5255 && cum->sysv_gregno <= GP_ARG_MAX_REG)
5258 else if (rs6000_darwin64_abi
5260 && TREE_CODE (type) == RECORD_TYPE
5261 && (size = int_size_in_bytes (type)) > 0)
5263 /* Variable sized types have size == -1 and are
5264 treated as if consisting entirely of ints.
5265 Pad to 16 byte boundary if needed. */
5266 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5267 && (cum->words % 2) != 0)
5269 /* For varargs, we can just go up by the size of the struct. */
5271 cum->words += (size + 7) / 8;
5274 /* It is tempting to say int register count just goes up by
5275 sizeof(type)/8, but this is wrong in a case such as
5276 { int; double; int; } [powerpc alignment]. We have to
5277 grovel through the fields for these too. */
5279 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
5280 rs6000_darwin64_record_arg_advance_flush (cum,
5281 size * BITS_PER_UNIT);
5284 else if (DEFAULT_ABI == ABI_V4)
5286 if (TARGET_HARD_FLOAT && TARGET_FPRS
5287 && (mode == SFmode || mode == DFmode
5288 || mode == DDmode || mode == TDmode
5289 || (mode == TFmode && !TARGET_IEEEQUAD)))
5291 /* _Decimal128 must use an even/odd register pair. This assumes
5292 that the register number is odd when fregno is odd. */
5293 if (mode == TDmode && (cum->fregno % 2) == 1)
5296 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5297 <= FP_ARG_V4_MAX_REG)
5298 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5301 cum->fregno = FP_ARG_V4_MAX_REG + 1;
5302 if (mode == DFmode || mode == TFmode || mode == DDmode || mode == TDmode)
5303 cum->words += cum->words & 1;
5304 cum->words += rs6000_arg_size (mode, type);
5309 int n_words = rs6000_arg_size (mode, type);
5310 int gregno = cum->sysv_gregno;
5312 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5313 (r7,r8) or (r9,r10). As does any other 2 word item such
5314 as complex int due to a historical mistake. */
5316 gregno += (1 - gregno) & 1;
5318 /* Multi-reg args are not split between registers and stack. */
5319 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5321 /* Long long and SPE vectors are aligned on the stack.
5322 So are other 2 word items such as complex int due to
5323 a historical mistake. */
5325 cum->words += cum->words & 1;
5326 cum->words += n_words;
5329 /* Note: continuing to accumulate gregno past when we've started
5330 spilling to the stack indicates the fact that we've started
5331 spilling to the stack to expand_builtin_saveregs. */
5332 cum->sysv_gregno = gregno + n_words;
5335 if (TARGET_DEBUG_ARG)
5337 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5338 cum->words, cum->fregno);
5339 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
5340 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
5341 fprintf (stderr, "mode = %4s, named = %d\n",
5342 GET_MODE_NAME (mode), named);
5347 int n_words = rs6000_arg_size (mode, type);
5348 int start_words = cum->words;
5349 int align_words = rs6000_parm_start (mode, type, start_words);
5351 cum->words = align_words + n_words;
5353 if (SCALAR_FLOAT_MODE_P (mode)
5355 && TARGET_HARD_FLOAT && TARGET_FPRS)
5357 /* _Decimal128 must be passed in an even/odd float register pair.
5358 This assumes that the register number is odd when fregno is
5360 if (mode == TDmode && (cum->fregno % 2) == 1)
5362 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
5365 if (TARGET_DEBUG_ARG)
5367 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
5368 cum->words, cum->fregno);
5369 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
5370 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
5371 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
5372 named, align_words - start_words, depth);
5378 spe_build_register_parallel (enum machine_mode mode, int gregno)
5385 r1 = gen_rtx_REG (DImode, gregno);
5386 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5387 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
5391 r1 = gen_rtx_REG (DImode, gregno);
5392 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5393 r3 = gen_rtx_REG (DImode, gregno + 2);
5394 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5395 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
5398 r1 = gen_rtx_REG (DImode, gregno);
5399 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
5400 r3 = gen_rtx_REG (DImode, gregno + 2);
5401 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
5402 r5 = gen_rtx_REG (DImode, gregno + 4);
5403 r5 = gen_rtx_EXPR_LIST (VOIDmode, r5, GEN_INT (16));
5404 r7 = gen_rtx_REG (DImode, gregno + 6);
5405 r7 = gen_rtx_EXPR_LIST (VOIDmode, r7, GEN_INT (24));
5406 return gen_rtx_PARALLEL (mode, gen_rtvec (4, r1, r3, r5, r7));
5413 /* Determine where to put a SIMD argument on the SPE. */
5415 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5418 int gregno = cum->sysv_gregno;
5420 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
5421 are passed and returned in a pair of GPRs for ABI compatibility. */
5422 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode
5423 || mode == TFmode || mode == TCmode))
5425 int n_words = rs6000_arg_size (mode, type);
5427 /* Doubles go in an odd/even register pair (r5/r6, etc). */
5429 gregno += (1 - gregno) & 1;
5431 /* Multi-reg args are not split between registers and stack. */
5432 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5435 return spe_build_register_parallel (mode, gregno);
5439 int n_words = rs6000_arg_size (mode, type);
5441 /* SPE vectors are put in odd registers. */
5442 if (n_words == 2 && (gregno & 1) == 0)
5445 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
5448 enum machine_mode m = SImode;
5450 r1 = gen_rtx_REG (m, gregno);
5451 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
5452 r2 = gen_rtx_REG (m, gregno + 1);
5453 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
5454 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
5461 if (gregno <= GP_ARG_MAX_REG)
5462 return gen_rtx_REG (mode, gregno);
5468 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
5469 structure between cum->intoffset and bitpos to integer registers. */
5472 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
5473 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
5475 enum machine_mode mode;
5477 unsigned int startbit, endbit;
5478 int this_regno, intregs, intoffset;
5481 if (cum->intoffset == -1)
5484 intoffset = cum->intoffset;
5485 cum->intoffset = -1;
5487 /* If this is the trailing part of a word, try to only load that
5488 much into the register. Otherwise load the whole register. Note
5489 that in the latter case we may pick up unwanted bits. It's not a
5490 problem at the moment but may wish to revisit. */
5492 if (intoffset % BITS_PER_WORD != 0)
5494 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
5496 if (mode == BLKmode)
5498 /* We couldn't find an appropriate mode, which happens,
5499 e.g., in packed structs when there are 3 bytes to load.
5500 Back intoffset back to the beginning of the word in this
5502 intoffset = intoffset & -BITS_PER_WORD;
5509 startbit = intoffset & -BITS_PER_WORD;
5510 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
5511 intregs = (endbit - startbit) / BITS_PER_WORD;
5512 this_regno = cum->words + intoffset / BITS_PER_WORD;
5514 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
5517 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
5521 intoffset /= BITS_PER_UNIT;
5524 regno = GP_ARG_MIN_REG + this_regno;
5525 reg = gen_rtx_REG (mode, regno);
5527 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
5530 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
5534 while (intregs > 0);
5537 /* Recursive workhorse for the following. */
5540 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, const_tree type,
5541 HOST_WIDE_INT startbitpos, rtx rvec[],
5546 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
5547 if (TREE_CODE (f) == FIELD_DECL)
5549 HOST_WIDE_INT bitpos = startbitpos;
5550 tree ftype = TREE_TYPE (f);
5551 enum machine_mode mode;
5552 if (ftype == error_mark_node)
5554 mode = TYPE_MODE (ftype);
5556 if (DECL_SIZE (f) != 0
5557 && host_integerp (bit_position (f), 1))
5558 bitpos += int_bit_position (f);
5560 /* ??? FIXME: else assume zero offset. */
5562 if (TREE_CODE (ftype) == RECORD_TYPE)
5563 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
5564 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
5569 case SCmode: mode = SFmode; break;
5570 case DCmode: mode = DFmode; break;
5571 case TCmode: mode = TFmode; break;
5575 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5577 = gen_rtx_EXPR_LIST (VOIDmode,
5578 gen_rtx_REG (mode, cum->fregno++),
5579 GEN_INT (bitpos / BITS_PER_UNIT));
5580 if (mode == TFmode || mode == TDmode)
5583 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
5585 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
5587 = gen_rtx_EXPR_LIST (VOIDmode,
5588 gen_rtx_REG (mode, cum->vregno++),
5589 GEN_INT (bitpos / BITS_PER_UNIT));
5591 else if (cum->intoffset == -1)
5592 cum->intoffset = bitpos;
5596 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
5597 the register(s) to be used for each field and subfield of a struct
5598 being passed by value, along with the offset of where the
5599 register's value may be found in the block. FP fields go in FP
5600 register, vector fields go in vector registers, and everything
5601 else goes in int registers, packed as in memory.
5603 This code is also used for function return values. RETVAL indicates
5604 whether this is the case.
5606 Much of this is taken from the SPARC V9 port, which has a similar
5607 calling convention. */
5610 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, const_tree type,
5611 int named, bool retval)
5613 rtx rvec[FIRST_PSEUDO_REGISTER];
5614 int k = 1, kbase = 1;
5615 HOST_WIDE_INT typesize = int_size_in_bytes (type);
5616 /* This is a copy; modifications are not visible to our caller. */
5617 CUMULATIVE_ARGS copy_cum = *orig_cum;
5618 CUMULATIVE_ARGS *cum = ©_cum;
5620 /* Pad to 16 byte boundary if needed. */
5621 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
5622 && (cum->words % 2) != 0)
5629 /* Put entries into rvec[] for individual FP and vector fields, and
5630 for the chunks of memory that go in int regs. Note we start at
5631 element 1; 0 is reserved for an indication of using memory, and
5632 may or may not be filled in below. */
5633 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
5634 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
5636 /* If any part of the struct went on the stack put all of it there.
5637 This hack is because the generic code for
5638 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
5639 parts of the struct are not at the beginning. */
5643 return NULL_RTX; /* doesn't go in registers at all */
5645 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5647 if (k > 1 || cum->use_stack)
5648 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
5653 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
5656 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
5660 rtx rvec[GP_ARG_NUM_REG + 1];
5662 if (align_words >= GP_ARG_NUM_REG)
5665 n_units = rs6000_arg_size (mode, type);
5667 /* Optimize the simple case where the arg fits in one gpr, except in
5668 the case of BLKmode due to assign_parms assuming that registers are
5669 BITS_PER_WORD wide. */
5671 || (n_units == 1 && mode != BLKmode))
5672 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5675 if (align_words + n_units > GP_ARG_NUM_REG)
5676 /* Not all of the arg fits in gprs. Say that it goes in memory too,
5677 using a magic NULL_RTX component.
5678 This is not strictly correct. Only some of the arg belongs in
5679 memory, not all of it. However, the normal scheme using
5680 function_arg_partial_nregs can result in unusual subregs, eg.
5681 (subreg:SI (reg:DF) 4), which are not handled well. The code to
5682 store the whole arg to memory is often more efficient than code
5683 to store pieces, and we know that space is available in the right
5684 place for the whole arg. */
5685 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5690 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
5691 rtx off = GEN_INT (i++ * 4);
5692 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5694 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
5696 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5699 /* Determine where to put an argument to a function.
5700 Value is zero to push the argument on the stack,
5701 or a hard register in which to store the argument.
5703 MODE is the argument's machine mode.
5704 TYPE is the data type of the argument (as a tree).
5705 This is null for libcalls where that information may
5707 CUM is a variable of type CUMULATIVE_ARGS which gives info about
5708 the preceding args and about the function being called. It is
5709 not modified in this routine.
5710 NAMED is nonzero if this argument is a named parameter
5711 (otherwise it is an extra parameter matching an ellipsis).
5713 On RS/6000 the first eight words of non-FP are normally in registers
5714 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
5715 Under V.4, the first 8 FP args are in registers.
5717 If this is floating-point and no prototype is specified, we use
5718 both an FP and integer register (or possibly FP reg and stack). Library
5719 functions (when CALL_LIBCALL is set) always have the proper types for args,
5720 so we can pass the FP value just in one register. emit_library_function
5721 doesn't support PARALLEL anyway.
5723 Note that for args passed by reference, function_arg will be called
5724 with MODE and TYPE set to that of the pointer to the arg, not the arg
5728 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5729 tree type, int named)
5731 enum rs6000_abi abi = DEFAULT_ABI;
5733 /* Return a marker to indicate whether CR1 needs to set or clear the
5734 bit that V.4 uses to say fp args were passed in registers.
5735 Assume that we don't need the marker for software floating point,
5736 or compiler generated library calls. */
5737 if (mode == VOIDmode)
5740 && (cum->call_cookie & CALL_LIBCALL) == 0
5742 || (cum->nargs_prototype < 0
5743 && (cum->prototype || TARGET_NO_PROTOTYPE))))
5745 /* For the SPE, we need to crxor CR6 always. */
5747 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5748 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5749 return GEN_INT (cum->call_cookie
5750 | ((cum->fregno == FP_ARG_MIN_REG)
5751 ? CALL_V4_SET_FP_ARGS
5752 : CALL_V4_CLEAR_FP_ARGS));
5755 return GEN_INT (cum->call_cookie);
5758 if (rs6000_darwin64_abi && mode == BLKmode
5759 && TREE_CODE (type) == RECORD_TYPE)
5761 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5762 if (rslt != NULL_RTX)
5764 /* Else fall through to usual handling. */
5767 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5768 if (TARGET_64BIT && ! cum->prototype)
5770 /* Vector parameters get passed in vector register
5771 and also in GPRs or memory, in absence of prototype. */
5774 align_words = (cum->words + 1) & ~1;
5776 if (align_words >= GP_ARG_NUM_REG)
5782 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5784 return gen_rtx_PARALLEL (mode,
5786 gen_rtx_EXPR_LIST (VOIDmode,
5788 gen_rtx_EXPR_LIST (VOIDmode,
5789 gen_rtx_REG (mode, cum->vregno),
5793 return gen_rtx_REG (mode, cum->vregno);
5794 else if (TARGET_ALTIVEC_ABI
5795 && (ALTIVEC_VECTOR_MODE (mode)
5796 || (type && TREE_CODE (type) == VECTOR_TYPE
5797 && int_size_in_bytes (type) == 16)))
5799 if (named || abi == ABI_V4)
5803 /* Vector parameters to varargs functions under AIX or Darwin
5804 get passed in memory and possibly also in GPRs. */
5805 int align, align_words, n_words;
5806 enum machine_mode part_mode;
5808 /* Vector parameters must be 16-byte aligned. This places them at
5809 2 mod 4 in terms of words in 32-bit mode, since the parameter
5810 save area starts at offset 24 from the stack. In 64-bit mode,
5811 they just have to start on an even word, since the parameter
5812 save area is 16-byte aligned. */
5814 align = (2 - cum->words) & 3;
5816 align = cum->words & 1;
5817 align_words = cum->words + align;
5819 /* Out of registers? Memory, then. */
5820 if (align_words >= GP_ARG_NUM_REG)
5823 if (TARGET_32BIT && TARGET_POWERPC64)
5824 return rs6000_mixed_function_arg (mode, type, align_words);
5826 /* The vector value goes in GPRs. Only the part of the
5827 value in GPRs is reported here. */
5829 n_words = rs6000_arg_size (mode, type);
5830 if (align_words + n_words > GP_ARG_NUM_REG)
5831 /* Fortunately, there are only two possibilities, the value
5832 is either wholly in GPRs or half in GPRs and half not. */
5835 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5838 else if (TARGET_SPE_ABI && TARGET_SPE
5839 && (SPE_VECTOR_MODE (mode)
5840 || (TARGET_E500_DOUBLE && (mode == DFmode
5845 || mode == TCmode))))
5846 return rs6000_spe_function_arg (cum, mode, type);
5848 else if (abi == ABI_V4)
5850 if (TARGET_HARD_FLOAT && TARGET_FPRS
5851 && (mode == SFmode || mode == DFmode
5852 || (mode == TFmode && !TARGET_IEEEQUAD)
5853 || mode == DDmode || mode == TDmode))
5855 /* _Decimal128 must use an even/odd register pair. This assumes
5856 that the register number is odd when fregno is odd. */
5857 if (mode == TDmode && (cum->fregno % 2) == 1)
5860 if (cum->fregno + (mode == TFmode || mode == TDmode ? 1 : 0)
5861 <= FP_ARG_V4_MAX_REG)
5862 return gen_rtx_REG (mode, cum->fregno);
5868 int n_words = rs6000_arg_size (mode, type);
5869 int gregno = cum->sysv_gregno;
5871 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5872 (r7,r8) or (r9,r10). As does any other 2 word item such
5873 as complex int due to a historical mistake. */
5875 gregno += (1 - gregno) & 1;
5877 /* Multi-reg args are not split between registers and stack. */
5878 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5881 if (TARGET_32BIT && TARGET_POWERPC64)
5882 return rs6000_mixed_function_arg (mode, type,
5883 gregno - GP_ARG_MIN_REG);
5884 return gen_rtx_REG (mode, gregno);
5889 int align_words = rs6000_parm_start (mode, type, cum->words);
5891 /* _Decimal128 must be passed in an even/odd float register pair.
5892 This assumes that the register number is odd when fregno is odd. */
5893 if (mode == TDmode && (cum->fregno % 2) == 1)
5896 if (USE_FP_FOR_ARG_P (cum, mode, type))
5898 rtx rvec[GP_ARG_NUM_REG + 1];
5902 enum machine_mode fmode = mode;
5903 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5905 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5907 /* Currently, we only ever need one reg here because complex
5908 doubles are split. */
5909 gcc_assert (cum->fregno == FP_ARG_MAX_REG
5910 && (fmode == TFmode || fmode == TDmode));
5912 /* Long double or _Decimal128 split over regs and memory. */
5913 fmode = DECIMAL_FLOAT_MODE_P (fmode) ? DDmode : DFmode;
5916 /* Do we also need to pass this arg in the parameter save
5919 && (cum->nargs_prototype <= 0
5920 || (DEFAULT_ABI == ABI_AIX
5922 && align_words >= GP_ARG_NUM_REG)));
5924 if (!needs_psave && mode == fmode)
5925 return gen_rtx_REG (fmode, cum->fregno);
5930 /* Describe the part that goes in gprs or the stack.
5931 This piece must come first, before the fprs. */
5932 if (align_words < GP_ARG_NUM_REG)
5934 unsigned long n_words = rs6000_arg_size (mode, type);
5936 if (align_words + n_words > GP_ARG_NUM_REG
5937 || (TARGET_32BIT && TARGET_POWERPC64))
5939 /* If this is partially on the stack, then we only
5940 include the portion actually in registers here. */
5941 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5944 if (align_words + n_words > GP_ARG_NUM_REG)
5945 /* Not all of the arg fits in gprs. Say that it
5946 goes in memory too, using a magic NULL_RTX
5947 component. Also see comment in
5948 rs6000_mixed_function_arg for why the normal
5949 function_arg_partial_nregs scheme doesn't work
5951 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5955 r = gen_rtx_REG (rmode,
5956 GP_ARG_MIN_REG + align_words);
5957 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5958 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5960 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5964 /* The whole arg fits in gprs. */
5965 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5966 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5970 /* It's entirely in memory. */
5971 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5974 /* Describe where this piece goes in the fprs. */
5975 r = gen_rtx_REG (fmode, cum->fregno);
5976 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5978 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5980 else if (align_words < GP_ARG_NUM_REG)
5982 if (TARGET_32BIT && TARGET_POWERPC64)
5983 return rs6000_mixed_function_arg (mode, type, align_words);
5985 if (mode == BLKmode)
5988 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5995 /* For an arg passed partly in registers and partly in memory, this is
5996 the number of bytes passed in registers. For args passed entirely in
5997 registers or entirely in memory, zero. When an arg is described by a
5998 PARALLEL, perhaps using more than one register type, this function
5999 returns the number of bytes used by the first element of the PARALLEL. */
6002 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6003 tree type, bool named)
6008 if (DEFAULT_ABI == ABI_V4)
6011 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
6012 && cum->nargs_prototype >= 0)
6015 /* In this complicated case we just disable the partial_nregs code. */
6016 if (rs6000_darwin64_abi && mode == BLKmode
6017 && TREE_CODE (type) == RECORD_TYPE
6018 && int_size_in_bytes (type) > 0)
6021 align_words = rs6000_parm_start (mode, type, cum->words);
6023 if (USE_FP_FOR_ARG_P (cum, mode, type))
6025 /* If we are passing this arg in the fixed parameter save area
6026 (gprs or memory) as well as fprs, then this function should
6027 return the number of partial bytes passed in the parameter
6028 save area rather than partial bytes passed in fprs. */
6030 && (cum->nargs_prototype <= 0
6031 || (DEFAULT_ABI == ABI_AIX
6033 && align_words >= GP_ARG_NUM_REG)))
6035 else if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3)
6036 > FP_ARG_MAX_REG + 1)
6037 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
6038 else if (cum->nargs_prototype >= 0)
6042 if (align_words < GP_ARG_NUM_REG
6043 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
6044 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
6046 if (ret != 0 && TARGET_DEBUG_ARG)
6047 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
6052 /* A C expression that indicates when an argument must be passed by
6053 reference. If nonzero for an argument, a copy of that argument is
6054 made in memory and a pointer to the argument is passed instead of
6055 the argument itself. The pointer is passed in whatever way is
6056 appropriate for passing a pointer to that type.
6058 Under V.4, aggregates and long double are passed by reference.
6060 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
6061 reference unless the AltiVec vector extension ABI is in force.
6063 As an extension to all ABIs, variable sized types are passed by
6067 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
6068 enum machine_mode mode, const_tree type,
6069 bool named ATTRIBUTE_UNUSED)
6071 if (DEFAULT_ABI == ABI_V4 && TARGET_IEEEQUAD && mode == TFmode)
6073 if (TARGET_DEBUG_ARG)
6074 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
6081 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
6083 if (TARGET_DEBUG_ARG)
6084 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
6088 if (int_size_in_bytes (type) < 0)
6090 if (TARGET_DEBUG_ARG)
6091 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
6095 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
6096 modes only exist for GCC vector types if -maltivec. */
6097 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
6099 if (TARGET_DEBUG_ARG)
6100 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
6104 /* Pass synthetic vectors in memory. */
6105 if (TREE_CODE (type) == VECTOR_TYPE
6106 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
6108 static bool warned_for_pass_big_vectors = false;
6109 if (TARGET_DEBUG_ARG)
6110 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
6111 if (!warned_for_pass_big_vectors)
6113 warning (0, "GCC vector passed by reference: "
6114 "non-standard ABI extension with no compatibility guarantee");
6115 warned_for_pass_big_vectors = true;
6124 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
6127 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
6132 for (i = 0; i < nregs; i++)
6134 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
6135 if (reload_completed)
6137 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
6140 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
6141 i * GET_MODE_SIZE (reg_mode));
6144 tem = replace_equiv_address (tem, XEXP (tem, 0));
6148 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
6152 /* Perform any needed actions needed for a function that is receiving a
6153 variable number of arguments.
6157 MODE and TYPE are the mode and type of the current parameter.
6159 PRETEND_SIZE is a variable that should be set to the amount of stack
6160 that must be pushed by the prolog to pretend that our caller pushed
6163 Normally, this macro will push all remaining incoming registers on the
6164 stack and set PRETEND_SIZE to the length of the registers pushed. */
6167 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
6168 tree type, int *pretend_size ATTRIBUTE_UNUSED,
6171 CUMULATIVE_ARGS next_cum;
6172 int reg_size = TARGET_32BIT ? 4 : 8;
6173 rtx save_area = NULL_RTX, mem;
6174 int first_reg_offset;
6177 /* Skip the last named argument. */
6179 function_arg_advance (&next_cum, mode, type, 1, 0);
6181 if (DEFAULT_ABI == ABI_V4)
6183 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
6187 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
6188 HOST_WIDE_INT offset = 0;
6190 /* Try to optimize the size of the varargs save area.
6191 The ABI requires that ap.reg_save_area is doubleword
6192 aligned, but we don't need to allocate space for all
6193 the bytes, only those to which we actually will save
6195 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
6196 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
6197 if (TARGET_HARD_FLOAT && TARGET_FPRS
6198 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6199 && cfun->va_list_fpr_size)
6202 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
6203 * UNITS_PER_FP_WORD;
6204 if (cfun->va_list_fpr_size
6205 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6206 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
6208 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
6209 * UNITS_PER_FP_WORD;
6213 offset = -((first_reg_offset * reg_size) & ~7);
6214 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
6216 gpr_reg_num = cfun->va_list_gpr_size;
6217 if (reg_size == 4 && (first_reg_offset & 1))
6220 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
6223 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
6225 - (int) (GP_ARG_NUM_REG * reg_size);
6227 if (gpr_size + fpr_size)
6230 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
6231 gcc_assert (GET_CODE (reg_save_area) == MEM);
6232 reg_save_area = XEXP (reg_save_area, 0);
6233 if (GET_CODE (reg_save_area) == PLUS)
6235 gcc_assert (XEXP (reg_save_area, 0)
6236 == virtual_stack_vars_rtx);
6237 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
6238 offset += INTVAL (XEXP (reg_save_area, 1));
6241 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
6244 cfun->machine->varargs_save_offset = offset;
6245 save_area = plus_constant (virtual_stack_vars_rtx, offset);
6250 first_reg_offset = next_cum.words;
6251 save_area = virtual_incoming_args_rtx;
6253 if (targetm.calls.must_pass_in_stack (mode, type))
6254 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
6257 set = get_varargs_alias_set ();
6258 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
6259 && cfun->va_list_gpr_size)
6261 int nregs = GP_ARG_NUM_REG - first_reg_offset;
6263 if (va_list_gpr_counter_field)
6265 /* V4 va_list_gpr_size counts number of registers needed. */
6266 if (nregs > cfun->va_list_gpr_size)
6267 nregs = cfun->va_list_gpr_size;
6271 /* char * va_list instead counts number of bytes needed. */
6272 if (nregs > cfun->va_list_gpr_size / reg_size)
6273 nregs = cfun->va_list_gpr_size / reg_size;
6276 mem = gen_rtx_MEM (BLKmode,
6277 plus_constant (save_area,
6278 first_reg_offset * reg_size));
6279 MEM_NOTRAP_P (mem) = 1;
6280 set_mem_alias_set (mem, set);
6281 set_mem_align (mem, BITS_PER_WORD);
6283 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
6287 /* Save FP registers if needed. */
6288 if (DEFAULT_ABI == ABI_V4
6289 && TARGET_HARD_FLOAT && TARGET_FPRS
6291 && next_cum.fregno <= FP_ARG_V4_MAX_REG
6292 && cfun->va_list_fpr_size)
6294 int fregno = next_cum.fregno, nregs;
6295 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
6296 rtx lab = gen_label_rtx ();
6297 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
6298 * UNITS_PER_FP_WORD);
6301 (gen_rtx_SET (VOIDmode,
6303 gen_rtx_IF_THEN_ELSE (VOIDmode,
6304 gen_rtx_NE (VOIDmode, cr1,
6306 gen_rtx_LABEL_REF (VOIDmode, lab),
6310 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
6311 fregno++, off += UNITS_PER_FP_WORD, nregs++)
6313 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
6314 MEM_NOTRAP_P (mem) = 1;
6315 set_mem_alias_set (mem, set);
6316 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
6317 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
6324 /* Create the va_list data type. */
6327 rs6000_build_builtin_va_list (void)
6329 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
6331 /* For AIX, prefer 'char *' because that's what the system
6332 header files like. */
6333 if (DEFAULT_ABI != ABI_V4)
6334 return build_pointer_type (char_type_node);
6336 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
6337 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
6339 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
6340 unsigned_char_type_node);
6341 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
6342 unsigned_char_type_node);
6343 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
6345 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
6346 short_unsigned_type_node);
6347 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
6349 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
6352 va_list_gpr_counter_field = f_gpr;
6353 va_list_fpr_counter_field = f_fpr;
6355 DECL_FIELD_CONTEXT (f_gpr) = record;
6356 DECL_FIELD_CONTEXT (f_fpr) = record;
6357 DECL_FIELD_CONTEXT (f_res) = record;
6358 DECL_FIELD_CONTEXT (f_ovf) = record;
6359 DECL_FIELD_CONTEXT (f_sav) = record;
6361 TREE_CHAIN (record) = type_decl;
6362 TYPE_NAME (record) = type_decl;
6363 TYPE_FIELDS (record) = f_gpr;
6364 TREE_CHAIN (f_gpr) = f_fpr;
6365 TREE_CHAIN (f_fpr) = f_res;
6366 TREE_CHAIN (f_res) = f_ovf;
6367 TREE_CHAIN (f_ovf) = f_sav;
6369 layout_type (record);
6371 /* The correct type is an array type of one element. */
6372 return build_array_type (record, build_index_type (size_zero_node));
6375 /* Implement va_start. */
6378 rs6000_va_start (tree valist, rtx nextarg)
6380 HOST_WIDE_INT words, n_gpr, n_fpr;
6381 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6382 tree gpr, fpr, ovf, sav, t;
6384 /* Only SVR4 needs something special. */
6385 if (DEFAULT_ABI != ABI_V4)
6387 std_expand_builtin_va_start (valist, nextarg);
6391 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6392 f_fpr = TREE_CHAIN (f_gpr);
6393 f_res = TREE_CHAIN (f_fpr);
6394 f_ovf = TREE_CHAIN (f_res);
6395 f_sav = TREE_CHAIN (f_ovf);
6397 valist = build_va_arg_indirect_ref (valist);
6398 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6399 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6400 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6401 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6403 /* Count number of gp and fp argument registers used. */
6404 words = current_function_args_info.words;
6405 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
6407 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
6410 if (TARGET_DEBUG_ARG)
6411 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
6412 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
6413 words, n_gpr, n_fpr);
6415 if (cfun->va_list_gpr_size)
6417 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (gpr), gpr,
6418 build_int_cst (NULL_TREE, n_gpr));
6419 TREE_SIDE_EFFECTS (t) = 1;
6420 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6423 if (cfun->va_list_fpr_size)
6425 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (fpr), fpr,
6426 build_int_cst (NULL_TREE, n_fpr));
6427 TREE_SIDE_EFFECTS (t) = 1;
6428 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6431 /* Find the overflow area. */
6432 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
6434 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (ovf), t,
6435 size_int (words * UNITS_PER_WORD));
6436 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6437 TREE_SIDE_EFFECTS (t) = 1;
6438 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6440 /* If there were no va_arg invocations, don't set up the register
6442 if (!cfun->va_list_gpr_size
6443 && !cfun->va_list_fpr_size
6444 && n_gpr < GP_ARG_NUM_REG
6445 && n_fpr < FP_ARG_V4_MAX_REG)
6448 /* Find the register save area. */
6449 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
6450 if (cfun->machine->varargs_save_offset)
6451 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (sav), t,
6452 size_int (cfun->machine->varargs_save_offset));
6453 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (sav), sav, t);
6454 TREE_SIDE_EFFECTS (t) = 1;
6455 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
6458 /* Implement va_arg. */
6461 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
6463 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
6464 tree gpr, fpr, ovf, sav, reg, t, u;
6465 int size, rsize, n_reg, sav_ofs, sav_scale;
6466 tree lab_false, lab_over, addr;
6468 tree ptrtype = build_pointer_type (type);
6471 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
6473 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
6474 return build_va_arg_indirect_ref (t);
6477 if (DEFAULT_ABI != ABI_V4)
6479 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
6481 tree elem_type = TREE_TYPE (type);
6482 enum machine_mode elem_mode = TYPE_MODE (elem_type);
6483 int elem_size = GET_MODE_SIZE (elem_mode);
6485 if (elem_size < UNITS_PER_WORD)
6487 tree real_part, imag_part;
6488 tree post = NULL_TREE;
6490 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6492 /* Copy the value into a temporary, lest the formal temporary
6493 be reused out from under us. */
6494 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
6495 append_to_statement_list (post, pre_p);
6497 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
6500 return build2 (COMPLEX_EXPR, type, real_part, imag_part);
6504 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6507 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
6508 f_fpr = TREE_CHAIN (f_gpr);
6509 f_res = TREE_CHAIN (f_fpr);
6510 f_ovf = TREE_CHAIN (f_res);
6511 f_sav = TREE_CHAIN (f_ovf);
6513 valist = build_va_arg_indirect_ref (valist);
6514 gpr = build3 (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
6515 fpr = build3 (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
6516 ovf = build3 (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
6517 sav = build3 (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
6519 size = int_size_in_bytes (type);
6520 rsize = (size + 3) / 4;
6523 if (TARGET_HARD_FLOAT && TARGET_FPRS
6524 && (TYPE_MODE (type) == SFmode
6525 || TYPE_MODE (type) == DFmode
6526 || TYPE_MODE (type) == TFmode
6527 || TYPE_MODE (type) == DDmode
6528 || TYPE_MODE (type) == TDmode))
6530 /* FP args go in FP registers, if present. */
6532 n_reg = (size + 7) / 8;
6535 if (TYPE_MODE (type) != SFmode)
6540 /* Otherwise into GP registers. */
6549 /* Pull the value out of the saved registers.... */
6552 addr = create_tmp_var (ptr_type_node, "addr");
6553 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
6555 /* AltiVec vectors never go in registers when -mabi=altivec. */
6556 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
6560 lab_false = create_artificial_label ();
6561 lab_over = create_artificial_label ();
6563 /* Long long and SPE vectors are aligned in the registers.
6564 As are any other 2 gpr item such as complex int due to a
6565 historical mistake. */
6567 if (n_reg == 2 && reg == gpr)
6570 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
6571 build_int_cst (TREE_TYPE (reg), n_reg - 1));
6572 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
6574 /* _Decimal128 is passed in even/odd fpr pairs; the stored
6575 reg number is 0 for f1, so we want to make it odd. */
6576 else if (reg == fpr && TYPE_MODE (type) == TDmode)
6579 t = build2 (BIT_IOR_EXPR, TREE_TYPE (reg), reg, size_int (1));
6580 u = build2 (MODIFY_EXPR, void_type_node, reg, t);
6583 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
6584 t = build2 (GE_EXPR, boolean_type_node, u, t);
6585 u = build1 (GOTO_EXPR, void_type_node, lab_false);
6586 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
6587 gimplify_and_add (t, pre_p);
6591 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
6593 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg,
6594 build_int_cst (TREE_TYPE (reg), n_reg));
6595 u = fold_convert (sizetype, u);
6596 u = build2 (MULT_EXPR, sizetype, u, size_int (sav_scale));
6597 t = build2 (POINTER_PLUS_EXPR, ptr_type_node, t, u);
6599 t = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6600 gimplify_and_add (t, pre_p);
6602 t = build1 (GOTO_EXPR, void_type_node, lab_over);
6603 gimplify_and_add (t, pre_p);
6605 t = build1 (LABEL_EXPR, void_type_node, lab_false);
6606 append_to_statement_list (t, pre_p);
6608 if ((n_reg == 2 && !regalign) || n_reg > 2)
6610 /* Ensure that we don't find any more args in regs.
6611 Alignment has taken care of for special cases. */
6612 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (reg), reg, size_int (8));
6613 gimplify_and_add (t, pre_p);
6617 /* ... otherwise out of the overflow area. */
6619 /* Care for on-stack alignment if needed. */
6623 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
6624 t = fold_convert (sizetype, t);
6625 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
6627 t = fold_convert (TREE_TYPE (ovf), t);
6629 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
6631 u = build2 (GIMPLE_MODIFY_STMT, void_type_node, addr, t);
6632 gimplify_and_add (u, pre_p);
6634 t = build2 (POINTER_PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
6635 t = build2 (GIMPLE_MODIFY_STMT, TREE_TYPE (ovf), ovf, t);
6636 gimplify_and_add (t, pre_p);
6640 t = build1 (LABEL_EXPR, void_type_node, lab_over);
6641 append_to_statement_list (t, pre_p);
6644 if (STRICT_ALIGNMENT
6645 && (TYPE_ALIGN (type)
6646 > (unsigned) BITS_PER_UNIT * (align < 4 ? 4 : align)))
6648 /* The value (of type complex double, for example) may not be
6649 aligned in memory in the saved registers, so copy via a
6650 temporary. (This is the same code as used for SPARC.) */
6651 tree tmp = create_tmp_var (type, "va_arg_tmp");
6652 tree dest_addr = build_fold_addr_expr (tmp);
6654 tree copy = build_call_expr (implicit_built_in_decls[BUILT_IN_MEMCPY],
6655 3, dest_addr, addr, size_int (rsize * 4));
6657 gimplify_and_add (copy, pre_p);
6661 addr = fold_convert (ptrtype, addr);
6662 return build_va_arg_indirect_ref (addr);
6668 def_builtin (int mask, const char *name, tree type, int code)
6670 if ((mask & target_flags) || TARGET_PAIRED_FLOAT)
6672 if (rs6000_builtin_decls[code])
6675 rs6000_builtin_decls[code] =
6676 add_builtin_function (name, type, code, BUILT_IN_MD,
6681 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
6683 static const struct builtin_description bdesc_3arg[] =
6685 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
6686 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
6687 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
6688 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
6689 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
6690 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
6691 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
6692 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
6693 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
6694 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
6695 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
6696 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
6697 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
6698 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
6699 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
6700 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
6701 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
6702 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
6703 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
6704 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
6705 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
6706 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
6707 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
6709 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
6710 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
6711 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
6712 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
6713 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
6714 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
6715 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
6716 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
6717 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
6718 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
6719 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
6720 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
6721 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
6722 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
6723 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
6725 { 0, CODE_FOR_paired_msub, "__builtin_paired_msub", PAIRED_BUILTIN_MSUB },
6726 { 0, CODE_FOR_paired_madd, "__builtin_paired_madd", PAIRED_BUILTIN_MADD },
6727 { 0, CODE_FOR_paired_madds0, "__builtin_paired_madds0", PAIRED_BUILTIN_MADDS0 },
6728 { 0, CODE_FOR_paired_madds1, "__builtin_paired_madds1", PAIRED_BUILTIN_MADDS1 },
6729 { 0, CODE_FOR_paired_nmsub, "__builtin_paired_nmsub", PAIRED_BUILTIN_NMSUB },
6730 { 0, CODE_FOR_paired_nmadd, "__builtin_paired_nmadd", PAIRED_BUILTIN_NMADD },
6731 { 0, CODE_FOR_paired_sum0, "__builtin_paired_sum0", PAIRED_BUILTIN_SUM0 },
6732 { 0, CODE_FOR_paired_sum1, "__builtin_paired_sum1", PAIRED_BUILTIN_SUM1 },
6733 { 0, CODE_FOR_selv2sf4, "__builtin_paired_selv2sf4", PAIRED_BUILTIN_SELV2SF4 },
6736 /* DST operations: void foo (void *, const int, const char). */
6738 static const struct builtin_description bdesc_dst[] =
6740 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
6741 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
6742 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
6743 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
6745 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
6746 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
6747 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
6748 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
6751 /* Simple binary operations: VECc = foo (VECa, VECb). */
6753 static struct builtin_description bdesc_2arg[] =
6755 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
6756 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
6757 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
6758 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
6759 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
6760 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
6761 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
6762 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
6763 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
6764 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
6765 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
6766 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
6767 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
6768 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
6769 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
6770 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
6771 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
6772 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
6773 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
6774 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
6775 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
6776 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
6777 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
6778 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
6779 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
6780 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
6781 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
6782 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
6783 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
6784 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
6785 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
6786 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
6787 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
6788 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
6789 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
6790 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
6791 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
6792 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
6793 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
6794 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
6795 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
6796 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
6797 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
6798 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
6799 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
6800 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
6801 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
6802 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
6803 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
6804 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
6805 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
6806 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6807 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6808 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6809 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6810 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6811 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6812 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6813 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6814 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6815 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6816 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6817 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6818 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6819 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6820 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6821 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6822 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6823 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6824 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6825 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6826 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6827 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6828 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6829 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6830 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6831 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6832 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6833 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6834 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6835 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6836 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6837 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6838 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6839 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6840 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6841 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6842 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6843 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6844 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6845 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6846 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6847 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6848 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6849 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6850 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6851 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6852 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6853 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6854 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6855 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6856 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6857 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6858 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6859 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6860 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6861 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6862 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6863 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6864 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6865 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6867 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6868 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6869 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6870 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6871 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6872 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6873 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6874 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6875 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6876 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6877 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6878 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6879 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6880 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6881 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6882 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6883 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6884 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6885 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6886 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6887 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6888 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6889 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6890 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6891 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6892 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6893 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6894 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6895 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6896 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6897 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6898 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6899 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6900 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6901 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6902 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6903 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6904 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6905 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6906 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6907 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6908 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6909 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6910 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6911 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6912 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6913 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6914 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6915 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6916 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6917 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6918 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6919 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6920 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6921 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6922 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6923 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6924 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6925 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6926 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6927 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6928 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6929 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6930 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6931 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6932 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6933 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6934 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6935 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6936 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6937 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6938 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6939 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6940 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6941 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6942 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6943 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6944 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6945 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6946 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6947 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6948 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6949 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6950 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6951 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6952 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6953 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6954 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6955 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6956 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6957 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6958 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6959 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6960 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6961 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6962 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6963 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6964 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6965 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6966 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6967 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6968 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6969 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6970 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6971 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6972 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6973 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6974 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6975 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6976 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6977 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6978 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6979 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6980 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6981 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6982 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6983 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6984 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6985 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6986 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6987 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6988 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6989 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6990 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6991 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6992 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6993 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6995 { 0, CODE_FOR_divv2sf3, "__builtin_paired_divv2sf3", PAIRED_BUILTIN_DIVV2SF3 },
6996 { 0, CODE_FOR_addv2sf3, "__builtin_paired_addv2sf3", PAIRED_BUILTIN_ADDV2SF3 },
6997 { 0, CODE_FOR_subv2sf3, "__builtin_paired_subv2sf3", PAIRED_BUILTIN_SUBV2SF3 },
6998 { 0, CODE_FOR_mulv2sf3, "__builtin_paired_mulv2sf3", PAIRED_BUILTIN_MULV2SF3 },
6999 { 0, CODE_FOR_paired_muls0, "__builtin_paired_muls0", PAIRED_BUILTIN_MULS0 },
7000 { 0, CODE_FOR_paired_muls1, "__builtin_paired_muls1", PAIRED_BUILTIN_MULS1 },
7001 { 0, CODE_FOR_paired_merge00, "__builtin_paired_merge00", PAIRED_BUILTIN_MERGE00 },
7002 { 0, CODE_FOR_paired_merge01, "__builtin_paired_merge01", PAIRED_BUILTIN_MERGE01 },
7003 { 0, CODE_FOR_paired_merge10, "__builtin_paired_merge10", PAIRED_BUILTIN_MERGE10 },
7004 { 0, CODE_FOR_paired_merge11, "__builtin_paired_merge11", PAIRED_BUILTIN_MERGE11 },
7006 /* Place holder, leave as first spe builtin. */
7007 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
7008 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
7009 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
7010 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
7011 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
7012 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
7013 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
7014 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
7015 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
7016 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
7017 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
7018 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
7019 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
7020 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
7021 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
7022 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
7023 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
7024 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
7025 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
7026 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
7027 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
7028 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
7029 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
7030 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
7031 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
7032 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
7033 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
7034 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
7035 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
7036 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
7037 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
7038 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
7039 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
7040 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
7041 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
7042 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
7043 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
7044 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
7045 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
7046 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
7047 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
7048 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
7049 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
7050 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
7051 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
7052 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
7053 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
7054 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
7055 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
7056 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
7057 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
7058 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
7059 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
7060 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
7061 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
7062 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
7063 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
7064 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
7065 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
7066 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
7067 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
7068 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
7069 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
7070 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
7071 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
7072 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
7073 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
7074 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
7075 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
7076 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
7077 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
7078 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
7079 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
7080 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
7081 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
7082 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
7083 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
7084 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
7085 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
7086 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
7087 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
7088 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
7089 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
7090 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
7091 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
7092 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
7093 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
7094 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
7095 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
7096 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
7097 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
7098 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
7099 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
7100 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
7101 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
7102 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
7103 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
7104 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
7105 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
7106 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
7107 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
7108 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
7109 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
7110 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
7111 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
7112 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
7113 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
7114 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
7115 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
7117 /* SPE binary operations expecting a 5-bit unsigned literal. */
7118 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
7120 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
7121 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
7122 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
7123 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
7124 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
7125 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
7126 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
7127 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
7128 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
7129 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
7130 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
7131 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
7132 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
7133 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
7134 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
7135 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
7136 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
7137 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
7138 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
7139 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
7140 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
7141 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
7142 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
7143 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
7144 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
7145 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
7147 /* Place-holder. Leave as last binary SPE builtin. */
7148 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
7151 /* AltiVec predicates. */
7153 struct builtin_description_predicates
7155 const unsigned int mask;
7156 const enum insn_code icode;
7158 const char *const name;
7159 const enum rs6000_builtins code;
7162 static const struct builtin_description_predicates bdesc_altivec_preds[] =
7164 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
7165 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
7166 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
7167 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
7168 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
7169 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
7170 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
7171 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
7172 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
7173 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
7174 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
7175 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
7176 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
7178 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
7179 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
7180 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
7183 /* SPE predicates. */
7184 static struct builtin_description bdesc_spe_predicates[] =
7186 /* Place-holder. Leave as first. */
7187 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
7188 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
7189 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
7190 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
7191 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
7192 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
7193 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
7194 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
7195 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
7196 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
7197 /* Place-holder. Leave as last. */
7198 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
7201 /* SPE evsel predicates. */
7202 static struct builtin_description bdesc_spe_evsel[] =
7204 /* Place-holder. Leave as first. */
7205 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
7206 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
7207 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
7208 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
7209 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
7210 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
7211 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
7212 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
7213 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
7214 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
7215 /* Place-holder. Leave as last. */
7216 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
7219 /* PAIRED predicates. */
7220 static const struct builtin_description bdesc_paired_preds[] =
7222 /* Place-holder. Leave as first. */
7223 { 0, CODE_FOR_paired_cmpu0, "__builtin_paired_cmpu0", PAIRED_BUILTIN_CMPU0 },
7224 /* Place-holder. Leave as last. */
7225 { 0, CODE_FOR_paired_cmpu1, "__builtin_paired_cmpu1", PAIRED_BUILTIN_CMPU1 },
7228 /* ABS* operations. */
7230 static const struct builtin_description bdesc_abs[] =
7232 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
7233 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
7234 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
7235 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
7236 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
7237 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
7238 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
7241 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
7244 static struct builtin_description bdesc_1arg[] =
7246 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
7247 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
7248 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
7249 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
7250 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
7251 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
7252 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
7253 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
7254 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
7255 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
7256 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
7257 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
7258 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
7259 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
7260 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
7261 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
7262 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
7264 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
7265 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
7266 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
7267 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
7268 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
7269 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
7270 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
7271 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
7272 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
7273 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
7274 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
7275 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
7276 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
7277 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
7278 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
7279 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
7280 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
7281 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
7282 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
7284 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
7285 end with SPE_BUILTIN_EVSUBFUSIAAW. */
7286 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
7287 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
7288 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
7289 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
7290 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
7291 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
7292 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
7293 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
7294 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
7295 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
7296 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
7297 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
7298 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
7299 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
7300 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
7301 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
7302 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
7303 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
7304 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
7305 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
7306 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
7307 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
7308 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
7309 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
7310 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
7311 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
7312 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
7313 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
7315 /* Place-holder. Leave as last unary SPE builtin. */
7316 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW },
7318 { 0, CODE_FOR_absv2sf2, "__builtin_paired_absv2sf2", PAIRED_BUILTIN_ABSV2SF2 },
7319 { 0, CODE_FOR_nabsv2sf2, "__builtin_paired_nabsv2sf2", PAIRED_BUILTIN_NABSV2SF2 },
7320 { 0, CODE_FOR_negv2sf2, "__builtin_paired_negv2sf2", PAIRED_BUILTIN_NEGV2SF2 },
7321 { 0, CODE_FOR_sqrtv2sf2, "__builtin_paired_sqrtv2sf2", PAIRED_BUILTIN_SQRTV2SF2 },
7322 { 0, CODE_FOR_resv2sf2, "__builtin_paired_resv2sf2", PAIRED_BUILTIN_RESV2SF2 }
7326 rs6000_expand_unop_builtin (enum insn_code icode, tree exp, rtx target)
7329 tree arg0 = CALL_EXPR_ARG (exp, 0);
7330 rtx op0 = expand_normal (arg0);
7331 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7332 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7334 if (icode == CODE_FOR_nothing)
7335 /* Builtin not supported on this processor. */
7338 /* If we got invalid arguments bail out before generating bad rtl. */
7339 if (arg0 == error_mark_node)
7342 if (icode == CODE_FOR_altivec_vspltisb
7343 || icode == CODE_FOR_altivec_vspltish
7344 || icode == CODE_FOR_altivec_vspltisw
7345 || icode == CODE_FOR_spe_evsplatfi
7346 || icode == CODE_FOR_spe_evsplati)
7348 /* Only allow 5-bit *signed* literals. */
7349 if (GET_CODE (op0) != CONST_INT
7350 || INTVAL (op0) > 15
7351 || INTVAL (op0) < -16)
7353 error ("argument 1 must be a 5-bit signed literal");
7359 || GET_MODE (target) != tmode
7360 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7361 target = gen_reg_rtx (tmode);
7363 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7364 op0 = copy_to_mode_reg (mode0, op0);
7366 pat = GEN_FCN (icode) (target, op0);
7375 altivec_expand_abs_builtin (enum insn_code icode, tree exp, rtx target)
7377 rtx pat, scratch1, scratch2;
7378 tree arg0 = CALL_EXPR_ARG (exp, 0);
7379 rtx op0 = expand_normal (arg0);
7380 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7381 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7383 /* If we have invalid arguments, bail out before generating bad rtl. */
7384 if (arg0 == error_mark_node)
7388 || GET_MODE (target) != tmode
7389 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7390 target = gen_reg_rtx (tmode);
7392 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7393 op0 = copy_to_mode_reg (mode0, op0);
7395 scratch1 = gen_reg_rtx (mode0);
7396 scratch2 = gen_reg_rtx (mode0);
7398 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
7407 rs6000_expand_binop_builtin (enum insn_code icode, tree exp, rtx target)
7410 tree arg0 = CALL_EXPR_ARG (exp, 0);
7411 tree arg1 = CALL_EXPR_ARG (exp, 1);
7412 rtx op0 = expand_normal (arg0);
7413 rtx op1 = expand_normal (arg1);
7414 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7415 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7416 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7418 if (icode == CODE_FOR_nothing)
7419 /* Builtin not supported on this processor. */
7422 /* If we got invalid arguments bail out before generating bad rtl. */
7423 if (arg0 == error_mark_node || arg1 == error_mark_node)
7426 if (icode == CODE_FOR_altivec_vcfux
7427 || icode == CODE_FOR_altivec_vcfsx
7428 || icode == CODE_FOR_altivec_vctsxs
7429 || icode == CODE_FOR_altivec_vctuxs
7430 || icode == CODE_FOR_altivec_vspltb
7431 || icode == CODE_FOR_altivec_vsplth
7432 || icode == CODE_FOR_altivec_vspltw
7433 || icode == CODE_FOR_spe_evaddiw
7434 || icode == CODE_FOR_spe_evldd
7435 || icode == CODE_FOR_spe_evldh
7436 || icode == CODE_FOR_spe_evldw
7437 || icode == CODE_FOR_spe_evlhhesplat
7438 || icode == CODE_FOR_spe_evlhhossplat
7439 || icode == CODE_FOR_spe_evlhhousplat
7440 || icode == CODE_FOR_spe_evlwhe
7441 || icode == CODE_FOR_spe_evlwhos
7442 || icode == CODE_FOR_spe_evlwhou
7443 || icode == CODE_FOR_spe_evlwhsplat
7444 || icode == CODE_FOR_spe_evlwwsplat
7445 || icode == CODE_FOR_spe_evrlwi
7446 || icode == CODE_FOR_spe_evslwi
7447 || icode == CODE_FOR_spe_evsrwis
7448 || icode == CODE_FOR_spe_evsubifw
7449 || icode == CODE_FOR_spe_evsrwiu)
7451 /* Only allow 5-bit unsigned literals. */
7453 if (TREE_CODE (arg1) != INTEGER_CST
7454 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7456 error ("argument 2 must be a 5-bit unsigned literal");
7462 || GET_MODE (target) != tmode
7463 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7464 target = gen_reg_rtx (tmode);
7466 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7467 op0 = copy_to_mode_reg (mode0, op0);
7468 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7469 op1 = copy_to_mode_reg (mode1, op1);
7471 pat = GEN_FCN (icode) (target, op0, op1);
7480 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
7481 tree exp, rtx target)
7484 tree cr6_form = CALL_EXPR_ARG (exp, 0);
7485 tree arg0 = CALL_EXPR_ARG (exp, 1);
7486 tree arg1 = CALL_EXPR_ARG (exp, 2);
7487 rtx op0 = expand_normal (arg0);
7488 rtx op1 = expand_normal (arg1);
7489 enum machine_mode tmode = SImode;
7490 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7491 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7494 if (TREE_CODE (cr6_form) != INTEGER_CST)
7496 error ("argument 1 of __builtin_altivec_predicate must be a constant");
7500 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
7502 gcc_assert (mode0 == mode1);
7504 /* If we have invalid arguments, bail out before generating bad rtl. */
7505 if (arg0 == error_mark_node || arg1 == error_mark_node)
7509 || GET_MODE (target) != tmode
7510 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7511 target = gen_reg_rtx (tmode);
7513 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7514 op0 = copy_to_mode_reg (mode0, op0);
7515 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7516 op1 = copy_to_mode_reg (mode1, op1);
7518 scratch = gen_reg_rtx (mode0);
7520 pat = GEN_FCN (icode) (scratch, op0, op1,
7521 gen_rtx_SYMBOL_REF (Pmode, opcode));
7526 /* The vec_any* and vec_all* predicates use the same opcodes for two
7527 different operations, but the bits in CR6 will be different
7528 depending on what information we want. So we have to play tricks
7529 with CR6 to get the right bits out.
7531 If you think this is disgusting, look at the specs for the
7532 AltiVec predicates. */
7534 switch (cr6_form_int)
7537 emit_insn (gen_cr6_test_for_zero (target));
7540 emit_insn (gen_cr6_test_for_zero_reverse (target));
7543 emit_insn (gen_cr6_test_for_lt (target));
7546 emit_insn (gen_cr6_test_for_lt_reverse (target));
7549 error ("argument 1 of __builtin_altivec_predicate is out of range");
7557 paired_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7560 tree arg0 = CALL_EXPR_ARG (exp, 0);
7561 tree arg1 = CALL_EXPR_ARG (exp, 1);
7562 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7563 enum machine_mode mode0 = Pmode;
7564 enum machine_mode mode1 = Pmode;
7565 rtx op0 = expand_normal (arg0);
7566 rtx op1 = expand_normal (arg1);
7568 if (icode == CODE_FOR_nothing)
7569 /* Builtin not supported on this processor. */
7572 /* If we got invalid arguments bail out before generating bad rtl. */
7573 if (arg0 == error_mark_node || arg1 == error_mark_node)
7577 || GET_MODE (target) != tmode
7578 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7579 target = gen_reg_rtx (tmode);
7581 op1 = copy_to_mode_reg (mode1, op1);
7583 if (op0 == const0_rtx)
7585 addr = gen_rtx_MEM (tmode, op1);
7589 op0 = copy_to_mode_reg (mode0, op0);
7590 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7593 pat = GEN_FCN (icode) (target, addr);
7603 altivec_expand_lv_builtin (enum insn_code icode, tree exp, rtx target)
7606 tree arg0 = CALL_EXPR_ARG (exp, 0);
7607 tree arg1 = CALL_EXPR_ARG (exp, 1);
7608 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7609 enum machine_mode mode0 = Pmode;
7610 enum machine_mode mode1 = Pmode;
7611 rtx op0 = expand_normal (arg0);
7612 rtx op1 = expand_normal (arg1);
7614 if (icode == CODE_FOR_nothing)
7615 /* Builtin not supported on this processor. */
7618 /* If we got invalid arguments bail out before generating bad rtl. */
7619 if (arg0 == error_mark_node || arg1 == error_mark_node)
7623 || GET_MODE (target) != tmode
7624 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7625 target = gen_reg_rtx (tmode);
7627 op1 = copy_to_mode_reg (mode1, op1);
7629 if (op0 == const0_rtx)
7631 addr = gen_rtx_MEM (tmode, op1);
7635 op0 = copy_to_mode_reg (mode0, op0);
7636 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
7639 pat = GEN_FCN (icode) (target, addr);
7649 spe_expand_stv_builtin (enum insn_code icode, tree exp)
7651 tree arg0 = CALL_EXPR_ARG (exp, 0);
7652 tree arg1 = CALL_EXPR_ARG (exp, 1);
7653 tree arg2 = CALL_EXPR_ARG (exp, 2);
7654 rtx op0 = expand_normal (arg0);
7655 rtx op1 = expand_normal (arg1);
7656 rtx op2 = expand_normal (arg2);
7658 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
7659 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
7660 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
7662 /* Invalid arguments. Bail before doing anything stoopid! */
7663 if (arg0 == error_mark_node
7664 || arg1 == error_mark_node
7665 || arg2 == error_mark_node)
7668 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
7669 op0 = copy_to_mode_reg (mode2, op0);
7670 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
7671 op1 = copy_to_mode_reg (mode0, op1);
7672 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7673 op2 = copy_to_mode_reg (mode1, op2);
7675 pat = GEN_FCN (icode) (op1, op2, op0);
7682 paired_expand_stv_builtin (enum insn_code icode, tree exp)
7684 tree arg0 = CALL_EXPR_ARG (exp, 0);
7685 tree arg1 = CALL_EXPR_ARG (exp, 1);
7686 tree arg2 = CALL_EXPR_ARG (exp, 2);
7687 rtx op0 = expand_normal (arg0);
7688 rtx op1 = expand_normal (arg1);
7689 rtx op2 = expand_normal (arg2);
7691 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7692 enum machine_mode mode1 = Pmode;
7693 enum machine_mode mode2 = Pmode;
7695 /* Invalid arguments. Bail before doing anything stoopid! */
7696 if (arg0 == error_mark_node
7697 || arg1 == error_mark_node
7698 || arg2 == error_mark_node)
7701 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7702 op0 = copy_to_mode_reg (tmode, op0);
7704 op2 = copy_to_mode_reg (mode2, op2);
7706 if (op1 == const0_rtx)
7708 addr = gen_rtx_MEM (tmode, op2);
7712 op1 = copy_to_mode_reg (mode1, op1);
7713 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7716 pat = GEN_FCN (icode) (addr, op0);
7723 altivec_expand_stv_builtin (enum insn_code icode, tree exp)
7725 tree arg0 = CALL_EXPR_ARG (exp, 0);
7726 tree arg1 = CALL_EXPR_ARG (exp, 1);
7727 tree arg2 = CALL_EXPR_ARG (exp, 2);
7728 rtx op0 = expand_normal (arg0);
7729 rtx op1 = expand_normal (arg1);
7730 rtx op2 = expand_normal (arg2);
7732 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7733 enum machine_mode mode1 = Pmode;
7734 enum machine_mode mode2 = Pmode;
7736 /* Invalid arguments. Bail before doing anything stoopid! */
7737 if (arg0 == error_mark_node
7738 || arg1 == error_mark_node
7739 || arg2 == error_mark_node)
7742 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
7743 op0 = copy_to_mode_reg (tmode, op0);
7745 op2 = copy_to_mode_reg (mode2, op2);
7747 if (op1 == const0_rtx)
7749 addr = gen_rtx_MEM (tmode, op2);
7753 op1 = copy_to_mode_reg (mode1, op1);
7754 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
7757 pat = GEN_FCN (icode) (addr, op0);
7764 rs6000_expand_ternop_builtin (enum insn_code icode, tree exp, rtx target)
7767 tree arg0 = CALL_EXPR_ARG (exp, 0);
7768 tree arg1 = CALL_EXPR_ARG (exp, 1);
7769 tree arg2 = CALL_EXPR_ARG (exp, 2);
7770 rtx op0 = expand_normal (arg0);
7771 rtx op1 = expand_normal (arg1);
7772 rtx op2 = expand_normal (arg2);
7773 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7774 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7775 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7776 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
7778 if (icode == CODE_FOR_nothing)
7779 /* Builtin not supported on this processor. */
7782 /* If we got invalid arguments bail out before generating bad rtl. */
7783 if (arg0 == error_mark_node
7784 || arg1 == error_mark_node
7785 || arg2 == error_mark_node)
7788 if (icode == CODE_FOR_altivec_vsldoi_v4sf
7789 || icode == CODE_FOR_altivec_vsldoi_v4si
7790 || icode == CODE_FOR_altivec_vsldoi_v8hi
7791 || icode == CODE_FOR_altivec_vsldoi_v16qi)
7793 /* Only allow 4-bit unsigned literals. */
7795 if (TREE_CODE (arg2) != INTEGER_CST
7796 || TREE_INT_CST_LOW (arg2) & ~0xf)
7798 error ("argument 3 must be a 4-bit unsigned literal");
7804 || GET_MODE (target) != tmode
7805 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7806 target = gen_reg_rtx (tmode);
7808 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7809 op0 = copy_to_mode_reg (mode0, op0);
7810 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7811 op1 = copy_to_mode_reg (mode1, op1);
7812 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
7813 op2 = copy_to_mode_reg (mode2, op2);
7815 if (TARGET_PAIRED_FLOAT && icode == CODE_FOR_selv2sf4)
7816 pat = GEN_FCN (icode) (target, op0, op1, op2, CONST0_RTX (SFmode));
7818 pat = GEN_FCN (icode) (target, op0, op1, op2);
7826 /* Expand the lvx builtins. */
7828 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
7830 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7831 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7833 enum machine_mode tmode, mode0;
7835 enum insn_code icode;
7839 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
7840 icode = CODE_FOR_altivec_lvx_v16qi;
7842 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
7843 icode = CODE_FOR_altivec_lvx_v8hi;
7845 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
7846 icode = CODE_FOR_altivec_lvx_v4si;
7848 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
7849 icode = CODE_FOR_altivec_lvx_v4sf;
7858 arg0 = CALL_EXPR_ARG (exp, 0);
7859 op0 = expand_normal (arg0);
7860 tmode = insn_data[icode].operand[0].mode;
7861 mode0 = insn_data[icode].operand[1].mode;
7864 || GET_MODE (target) != tmode
7865 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7866 target = gen_reg_rtx (tmode);
7868 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7869 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7871 pat = GEN_FCN (icode) (target, op0);
7878 /* Expand the stvx builtins. */
7880 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7883 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7884 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7886 enum machine_mode mode0, mode1;
7888 enum insn_code icode;
7892 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
7893 icode = CODE_FOR_altivec_stvx_v16qi;
7895 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
7896 icode = CODE_FOR_altivec_stvx_v8hi;
7898 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
7899 icode = CODE_FOR_altivec_stvx_v4si;
7901 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
7902 icode = CODE_FOR_altivec_stvx_v4sf;
7909 arg0 = CALL_EXPR_ARG (exp, 0);
7910 arg1 = CALL_EXPR_ARG (exp, 1);
7911 op0 = expand_normal (arg0);
7912 op1 = expand_normal (arg1);
7913 mode0 = insn_data[icode].operand[0].mode;
7914 mode1 = insn_data[icode].operand[1].mode;
7916 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7917 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
7918 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7919 op1 = copy_to_mode_reg (mode1, op1);
7921 pat = GEN_FCN (icode) (op0, op1);
7929 /* Expand the dst builtins. */
7931 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7934 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
7935 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7936 tree arg0, arg1, arg2;
7937 enum machine_mode mode0, mode1, mode2;
7938 rtx pat, op0, op1, op2;
7939 const struct builtin_description *d;
7944 /* Handle DST variants. */
7946 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7947 if (d->code == fcode)
7949 arg0 = CALL_EXPR_ARG (exp, 0);
7950 arg1 = CALL_EXPR_ARG (exp, 1);
7951 arg2 = CALL_EXPR_ARG (exp, 2);
7952 op0 = expand_normal (arg0);
7953 op1 = expand_normal (arg1);
7954 op2 = expand_normal (arg2);
7955 mode0 = insn_data[d->icode].operand[0].mode;
7956 mode1 = insn_data[d->icode].operand[1].mode;
7957 mode2 = insn_data[d->icode].operand[2].mode;
7959 /* Invalid arguments, bail out before generating bad rtl. */
7960 if (arg0 == error_mark_node
7961 || arg1 == error_mark_node
7962 || arg2 == error_mark_node)
7967 if (TREE_CODE (arg2) != INTEGER_CST
7968 || TREE_INT_CST_LOW (arg2) & ~0x3)
7970 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7974 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7975 op0 = copy_to_mode_reg (Pmode, op0);
7976 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7977 op1 = copy_to_mode_reg (mode1, op1);
7979 pat = GEN_FCN (d->icode) (op0, op1, op2);
7989 /* Expand vec_init builtin. */
7991 altivec_expand_vec_init_builtin (tree type, tree exp, rtx target)
7993 enum machine_mode tmode = TYPE_MODE (type);
7994 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7995 int i, n_elt = GET_MODE_NUNITS (tmode);
7996 rtvec v = rtvec_alloc (n_elt);
7998 gcc_assert (VECTOR_MODE_P (tmode));
7999 gcc_assert (n_elt == call_expr_nargs (exp));
8001 for (i = 0; i < n_elt; ++i)
8003 rtx x = expand_normal (CALL_EXPR_ARG (exp, i));
8004 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
8007 if (!target || !register_operand (target, tmode))
8008 target = gen_reg_rtx (tmode);
8010 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
8014 /* Return the integer constant in ARG. Constrain it to be in the range
8015 of the subparts of VEC_TYPE; issue an error if not. */
8018 get_element_number (tree vec_type, tree arg)
8020 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
8022 if (!host_integerp (arg, 1)
8023 || (elt = tree_low_cst (arg, 1), elt > max))
8025 error ("selector must be an integer constant in the range 0..%wi", max);
8032 /* Expand vec_set builtin. */
8034 altivec_expand_vec_set_builtin (tree exp)
8036 enum machine_mode tmode, mode1;
8037 tree arg0, arg1, arg2;
8041 arg0 = CALL_EXPR_ARG (exp, 0);
8042 arg1 = CALL_EXPR_ARG (exp, 1);
8043 arg2 = CALL_EXPR_ARG (exp, 2);
8045 tmode = TYPE_MODE (TREE_TYPE (arg0));
8046 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8047 gcc_assert (VECTOR_MODE_P (tmode));
8049 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
8050 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
8051 elt = get_element_number (TREE_TYPE (arg0), arg2);
8053 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
8054 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
8056 op0 = force_reg (tmode, op0);
8057 op1 = force_reg (mode1, op1);
8059 rs6000_expand_vector_set (op0, op1, elt);
8064 /* Expand vec_ext builtin. */
8066 altivec_expand_vec_ext_builtin (tree exp, rtx target)
8068 enum machine_mode tmode, mode0;
8073 arg0 = CALL_EXPR_ARG (exp, 0);
8074 arg1 = CALL_EXPR_ARG (exp, 1);
8076 op0 = expand_normal (arg0);
8077 elt = get_element_number (TREE_TYPE (arg0), arg1);
8079 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
8080 mode0 = TYPE_MODE (TREE_TYPE (arg0));
8081 gcc_assert (VECTOR_MODE_P (mode0));
8083 op0 = force_reg (mode0, op0);
8085 if (optimize || !target || !register_operand (target, tmode))
8086 target = gen_reg_rtx (tmode);
8088 rs6000_expand_vector_extract (target, op0, elt);
8093 /* Expand the builtin in EXP and store the result in TARGET. Store
8094 true in *EXPANDEDP if we found a builtin to expand. */
8096 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
8098 const struct builtin_description *d;
8099 const struct builtin_description_predicates *dp;
8101 enum insn_code icode;
8102 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8105 enum machine_mode tmode, mode0;
8106 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8108 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8109 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
8112 error ("unresolved overload for Altivec builtin %qF", fndecl);
8116 target = altivec_expand_ld_builtin (exp, target, expandedp);
8120 target = altivec_expand_st_builtin (exp, target, expandedp);
8124 target = altivec_expand_dst_builtin (exp, target, expandedp);
8132 case ALTIVEC_BUILTIN_STVX:
8133 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, exp);
8134 case ALTIVEC_BUILTIN_STVEBX:
8135 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, exp);
8136 case ALTIVEC_BUILTIN_STVEHX:
8137 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, exp);
8138 case ALTIVEC_BUILTIN_STVEWX:
8139 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, exp);
8140 case ALTIVEC_BUILTIN_STVXL:
8141 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, exp);
8143 case ALTIVEC_BUILTIN_MFVSCR:
8144 icode = CODE_FOR_altivec_mfvscr;
8145 tmode = insn_data[icode].operand[0].mode;
8148 || GET_MODE (target) != tmode
8149 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8150 target = gen_reg_rtx (tmode);
8152 pat = GEN_FCN (icode) (target);
8158 case ALTIVEC_BUILTIN_MTVSCR:
8159 icode = CODE_FOR_altivec_mtvscr;
8160 arg0 = CALL_EXPR_ARG (exp, 0);
8161 op0 = expand_normal (arg0);
8162 mode0 = insn_data[icode].operand[0].mode;
8164 /* If we got invalid arguments bail out before generating bad rtl. */
8165 if (arg0 == error_mark_node)
8168 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8169 op0 = copy_to_mode_reg (mode0, op0);
8171 pat = GEN_FCN (icode) (op0);
8176 case ALTIVEC_BUILTIN_DSSALL:
8177 emit_insn (gen_altivec_dssall ());
8180 case ALTIVEC_BUILTIN_DSS:
8181 icode = CODE_FOR_altivec_dss;
8182 arg0 = CALL_EXPR_ARG (exp, 0);
8184 op0 = expand_normal (arg0);
8185 mode0 = insn_data[icode].operand[0].mode;
8187 /* If we got invalid arguments bail out before generating bad rtl. */
8188 if (arg0 == error_mark_node)
8191 if (TREE_CODE (arg0) != INTEGER_CST
8192 || TREE_INT_CST_LOW (arg0) & ~0x3)
8194 error ("argument to dss must be a 2-bit unsigned literal");
8198 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8199 op0 = copy_to_mode_reg (mode0, op0);
8201 emit_insn (gen_altivec_dss (op0));
8204 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
8205 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
8206 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
8207 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
8208 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), exp, target);
8210 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
8211 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
8212 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
8213 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
8214 return altivec_expand_vec_set_builtin (exp);
8216 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
8217 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
8218 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
8219 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
8220 return altivec_expand_vec_ext_builtin (exp, target);
8227 /* Expand abs* operations. */
8229 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8230 if (d->code == fcode)
8231 return altivec_expand_abs_builtin (d->icode, exp, target);
8233 /* Expand the AltiVec predicates. */
8234 dp = bdesc_altivec_preds;
8235 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8236 if (dp->code == fcode)
8237 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
8240 /* LV* are funky. We initialized them differently. */
8243 case ALTIVEC_BUILTIN_LVSL:
8244 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
8246 case ALTIVEC_BUILTIN_LVSR:
8247 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
8249 case ALTIVEC_BUILTIN_LVEBX:
8250 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
8252 case ALTIVEC_BUILTIN_LVEHX:
8253 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
8255 case ALTIVEC_BUILTIN_LVEWX:
8256 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
8258 case ALTIVEC_BUILTIN_LVXL:
8259 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
8261 case ALTIVEC_BUILTIN_LVX:
8262 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
8273 /* Expand the builtin in EXP and store the result in TARGET. Store
8274 true in *EXPANDEDP if we found a builtin to expand. */
8276 paired_expand_builtin (tree exp, rtx target, bool * expandedp)
8278 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8279 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8280 const struct builtin_description *d;
8287 case PAIRED_BUILTIN_STX:
8288 return paired_expand_stv_builtin (CODE_FOR_paired_stx, exp);
8289 case PAIRED_BUILTIN_LX:
8290 return paired_expand_lv_builtin (CODE_FOR_paired_lx, exp, target);
8296 /* Expand the paired predicates. */
8297 d = bdesc_paired_preds;
8298 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); i++, d++)
8299 if (d->code == fcode)
8300 return paired_expand_predicate_builtin (d->icode, exp, target);
8306 /* Binops that need to be initialized manually, but can be expanded
8307 automagically by rs6000_expand_binop_builtin. */
8308 static struct builtin_description bdesc_2arg_spe[] =
8310 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
8311 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
8312 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
8313 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
8314 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
8315 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
8316 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
8317 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
8318 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
8319 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
8320 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
8321 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
8322 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
8323 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
8324 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
8325 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
8326 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
8327 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
8328 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
8329 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
8330 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
8331 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
8334 /* Expand the builtin in EXP and store the result in TARGET. Store
8335 true in *EXPANDEDP if we found a builtin to expand.
8337 This expands the SPE builtins that are not simple unary and binary
8340 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
8342 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8344 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8345 enum insn_code icode;
8346 enum machine_mode tmode, mode0;
8348 struct builtin_description *d;
8353 /* Syntax check for a 5-bit unsigned immediate. */
8356 case SPE_BUILTIN_EVSTDD:
8357 case SPE_BUILTIN_EVSTDH:
8358 case SPE_BUILTIN_EVSTDW:
8359 case SPE_BUILTIN_EVSTWHE:
8360 case SPE_BUILTIN_EVSTWHO:
8361 case SPE_BUILTIN_EVSTWWE:
8362 case SPE_BUILTIN_EVSTWWO:
8363 arg1 = CALL_EXPR_ARG (exp, 2);
8364 if (TREE_CODE (arg1) != INTEGER_CST
8365 || TREE_INT_CST_LOW (arg1) & ~0x1f)
8367 error ("argument 2 must be a 5-bit unsigned literal");
8375 /* The evsplat*i instructions are not quite generic. */
8378 case SPE_BUILTIN_EVSPLATFI:
8379 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
8381 case SPE_BUILTIN_EVSPLATI:
8382 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
8388 d = (struct builtin_description *) bdesc_2arg_spe;
8389 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
8390 if (d->code == fcode)
8391 return rs6000_expand_binop_builtin (d->icode, exp, target);
8393 d = (struct builtin_description *) bdesc_spe_predicates;
8394 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
8395 if (d->code == fcode)
8396 return spe_expand_predicate_builtin (d->icode, exp, target);
8398 d = (struct builtin_description *) bdesc_spe_evsel;
8399 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
8400 if (d->code == fcode)
8401 return spe_expand_evsel_builtin (d->icode, exp, target);
8405 case SPE_BUILTIN_EVSTDDX:
8406 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, exp);
8407 case SPE_BUILTIN_EVSTDHX:
8408 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, exp);
8409 case SPE_BUILTIN_EVSTDWX:
8410 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, exp);
8411 case SPE_BUILTIN_EVSTWHEX:
8412 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, exp);
8413 case SPE_BUILTIN_EVSTWHOX:
8414 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, exp);
8415 case SPE_BUILTIN_EVSTWWEX:
8416 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, exp);
8417 case SPE_BUILTIN_EVSTWWOX:
8418 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, exp);
8419 case SPE_BUILTIN_EVSTDD:
8420 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, exp);
8421 case SPE_BUILTIN_EVSTDH:
8422 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, exp);
8423 case SPE_BUILTIN_EVSTDW:
8424 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, exp);
8425 case SPE_BUILTIN_EVSTWHE:
8426 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, exp);
8427 case SPE_BUILTIN_EVSTWHO:
8428 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, exp);
8429 case SPE_BUILTIN_EVSTWWE:
8430 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, exp);
8431 case SPE_BUILTIN_EVSTWWO:
8432 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, exp);
8433 case SPE_BUILTIN_MFSPEFSCR:
8434 icode = CODE_FOR_spe_mfspefscr;
8435 tmode = insn_data[icode].operand[0].mode;
8438 || GET_MODE (target) != tmode
8439 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8440 target = gen_reg_rtx (tmode);
8442 pat = GEN_FCN (icode) (target);
8447 case SPE_BUILTIN_MTSPEFSCR:
8448 icode = CODE_FOR_spe_mtspefscr;
8449 arg0 = CALL_EXPR_ARG (exp, 0);
8450 op0 = expand_normal (arg0);
8451 mode0 = insn_data[icode].operand[0].mode;
8453 if (arg0 == error_mark_node)
8456 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
8457 op0 = copy_to_mode_reg (mode0, op0);
8459 pat = GEN_FCN (icode) (op0);
8472 paired_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8474 rtx pat, scratch, tmp;
8475 tree form = CALL_EXPR_ARG (exp, 0);
8476 tree arg0 = CALL_EXPR_ARG (exp, 1);
8477 tree arg1 = CALL_EXPR_ARG (exp, 2);
8478 rtx op0 = expand_normal (arg0);
8479 rtx op1 = expand_normal (arg1);
8480 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8481 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8485 if (TREE_CODE (form) != INTEGER_CST)
8487 error ("argument 1 of __builtin_paired_predicate must be a constant");
8491 form_int = TREE_INT_CST_LOW (form);
8493 gcc_assert (mode0 == mode1);
8495 if (arg0 == error_mark_node || arg1 == error_mark_node)
8499 || GET_MODE (target) != SImode
8500 || !(*insn_data[icode].operand[0].predicate) (target, SImode))
8501 target = gen_reg_rtx (SImode);
8502 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
8503 op0 = copy_to_mode_reg (mode0, op0);
8504 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
8505 op1 = copy_to_mode_reg (mode1, op1);
8507 scratch = gen_reg_rtx (CCFPmode);
8509 pat = GEN_FCN (icode) (scratch, op0, op1);
8531 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8534 error ("argument 1 of __builtin_paired_predicate is out of range");
8538 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8539 emit_move_insn (target, tmp);
8544 spe_expand_predicate_builtin (enum insn_code icode, tree exp, rtx target)
8546 rtx pat, scratch, tmp;
8547 tree form = CALL_EXPR_ARG (exp, 0);
8548 tree arg0 = CALL_EXPR_ARG (exp, 1);
8549 tree arg1 = CALL_EXPR_ARG (exp, 2);
8550 rtx op0 = expand_normal (arg0);
8551 rtx op1 = expand_normal (arg1);
8552 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8553 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8557 if (TREE_CODE (form) != INTEGER_CST)
8559 error ("argument 1 of __builtin_spe_predicate must be a constant");
8563 form_int = TREE_INT_CST_LOW (form);
8565 gcc_assert (mode0 == mode1);
8567 if (arg0 == error_mark_node || arg1 == error_mark_node)
8571 || GET_MODE (target) != SImode
8572 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
8573 target = gen_reg_rtx (SImode);
8575 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8576 op0 = copy_to_mode_reg (mode0, op0);
8577 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
8578 op1 = copy_to_mode_reg (mode1, op1);
8580 scratch = gen_reg_rtx (CCmode);
8582 pat = GEN_FCN (icode) (scratch, op0, op1);
8587 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
8588 _lower_. We use one compare, but look in different bits of the
8589 CR for each variant.
8591 There are 2 elements in each SPE simd type (upper/lower). The CR
8592 bits are set as follows:
8594 BIT0 | BIT 1 | BIT 2 | BIT 3
8595 U | L | (U | L) | (U & L)
8597 So, for an "all" relationship, BIT 3 would be set.
8598 For an "any" relationship, BIT 2 would be set. Etc.
8600 Following traditional nomenclature, these bits map to:
8602 BIT0 | BIT 1 | BIT 2 | BIT 3
8605 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
8610 /* All variant. OV bit. */
8612 /* We need to get to the OV bit, which is the ORDERED bit. We
8613 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
8614 that's ugly and will make validate_condition_mode die.
8615 So let's just use another pattern. */
8616 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
8618 /* Any variant. EQ bit. */
8622 /* Upper variant. LT bit. */
8626 /* Lower variant. GT bit. */
8631 error ("argument 1 of __builtin_spe_predicate is out of range");
8635 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
8636 emit_move_insn (target, tmp);
8641 /* The evsel builtins look like this:
8643 e = __builtin_spe_evsel_OP (a, b, c, d);
8647 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
8648 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
8652 spe_expand_evsel_builtin (enum insn_code icode, tree exp, rtx target)
8655 tree arg0 = CALL_EXPR_ARG (exp, 0);
8656 tree arg1 = CALL_EXPR_ARG (exp, 1);
8657 tree arg2 = CALL_EXPR_ARG (exp, 2);
8658 tree arg3 = CALL_EXPR_ARG (exp, 3);
8659 rtx op0 = expand_normal (arg0);
8660 rtx op1 = expand_normal (arg1);
8661 rtx op2 = expand_normal (arg2);
8662 rtx op3 = expand_normal (arg3);
8663 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
8664 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
8666 gcc_assert (mode0 == mode1);
8668 if (arg0 == error_mark_node || arg1 == error_mark_node
8669 || arg2 == error_mark_node || arg3 == error_mark_node)
8673 || GET_MODE (target) != mode0
8674 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
8675 target = gen_reg_rtx (mode0);
8677 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
8678 op0 = copy_to_mode_reg (mode0, op0);
8679 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
8680 op1 = copy_to_mode_reg (mode0, op1);
8681 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
8682 op2 = copy_to_mode_reg (mode0, op2);
8683 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
8684 op3 = copy_to_mode_reg (mode0, op3);
8686 /* Generate the compare. */
8687 scratch = gen_reg_rtx (CCmode);
8688 pat = GEN_FCN (icode) (scratch, op0, op1);
8693 if (mode0 == V2SImode)
8694 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
8696 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
8701 /* Expand an expression EXP that calls a built-in function,
8702 with result going to TARGET if that's convenient
8703 (and in mode MODE if that's convenient).
8704 SUBTARGET may be used as the target for computing one of EXP's operands.
8705 IGNORE is nonzero if the value is to be ignored. */
8708 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
8709 enum machine_mode mode ATTRIBUTE_UNUSED,
8710 int ignore ATTRIBUTE_UNUSED)
8712 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
8713 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
8714 const struct builtin_description *d;
8719 if (fcode == RS6000_BUILTIN_RECIP)
8720 return rs6000_expand_binop_builtin (CODE_FOR_recipdf3, exp, target);
8722 if (fcode == RS6000_BUILTIN_RECIPF)
8723 return rs6000_expand_binop_builtin (CODE_FOR_recipsf3, exp, target);
8725 if (fcode == RS6000_BUILTIN_RSQRTF)
8726 return rs6000_expand_unop_builtin (CODE_FOR_rsqrtsf2, exp, target);
8728 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
8729 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8731 int icode = (int) CODE_FOR_altivec_lvsr;
8732 enum machine_mode tmode = insn_data[icode].operand[0].mode;
8733 enum machine_mode mode = insn_data[icode].operand[1].mode;
8737 gcc_assert (TARGET_ALTIVEC);
8739 arg = CALL_EXPR_ARG (exp, 0);
8740 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
8741 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
8742 addr = memory_address (mode, op);
8743 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
8747 /* For the load case need to negate the address. */
8748 op = gen_reg_rtx (GET_MODE (addr));
8749 emit_insn (gen_rtx_SET (VOIDmode, op,
8750 gen_rtx_NEG (GET_MODE (addr), addr)));
8752 op = gen_rtx_MEM (mode, op);
8755 || GET_MODE (target) != tmode
8756 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
8757 target = gen_reg_rtx (tmode);
8759 /*pat = gen_altivec_lvsr (target, op);*/
8760 pat = GEN_FCN (icode) (target, op);
8768 /* FIXME: There's got to be a nicer way to handle this case than
8769 constructing a new CALL_EXPR. */
8770 if (fcode == ALTIVEC_BUILTIN_VCFUX
8771 || fcode == ALTIVEC_BUILTIN_VCFSX)
8773 if (call_expr_nargs (exp) == 1)
8774 exp = build_call_nary (TREE_TYPE (exp), CALL_EXPR_FN (exp),
8775 2, CALL_EXPR_ARG (exp, 0), integer_zero_node);
8780 ret = altivec_expand_builtin (exp, target, &success);
8787 ret = spe_expand_builtin (exp, target, &success);
8792 if (TARGET_PAIRED_FLOAT)
8794 ret = paired_expand_builtin (exp, target, &success);
8800 gcc_assert (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT);
8802 /* Handle simple unary operations. */
8803 d = (struct builtin_description *) bdesc_1arg;
8804 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8805 if (d->code == fcode)
8806 return rs6000_expand_unop_builtin (d->icode, exp, target);
8808 /* Handle simple binary operations. */
8809 d = (struct builtin_description *) bdesc_2arg;
8810 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8811 if (d->code == fcode)
8812 return rs6000_expand_binop_builtin (d->icode, exp, target);
8814 /* Handle simple ternary operations. */
8816 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8817 if (d->code == fcode)
8818 return rs6000_expand_ternop_builtin (d->icode, exp, target);
8824 build_opaque_vector_type (tree node, int nunits)
8826 node = copy_node (node);
8827 TYPE_MAIN_VARIANT (node) = node;
8828 return build_vector_type (node, nunits);
8832 rs6000_init_builtins (void)
8834 V2SI_type_node = build_vector_type (intSI_type_node, 2);
8835 V2SF_type_node = build_vector_type (float_type_node, 2);
8836 V4HI_type_node = build_vector_type (intHI_type_node, 4);
8837 V4SI_type_node = build_vector_type (intSI_type_node, 4);
8838 V4SF_type_node = build_vector_type (float_type_node, 4);
8839 V8HI_type_node = build_vector_type (intHI_type_node, 8);
8840 V16QI_type_node = build_vector_type (intQI_type_node, 16);
8842 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
8843 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
8844 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
8846 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
8847 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
8848 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
8849 opaque_V4SI_type_node = copy_node (V4SI_type_node);
8851 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
8852 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
8853 'vector unsigned short'. */
8855 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
8856 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8857 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
8858 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
8860 long_integer_type_internal_node = long_integer_type_node;
8861 long_unsigned_type_internal_node = long_unsigned_type_node;
8862 intQI_type_internal_node = intQI_type_node;
8863 uintQI_type_internal_node = unsigned_intQI_type_node;
8864 intHI_type_internal_node = intHI_type_node;
8865 uintHI_type_internal_node = unsigned_intHI_type_node;
8866 intSI_type_internal_node = intSI_type_node;
8867 uintSI_type_internal_node = unsigned_intSI_type_node;
8868 float_type_internal_node = float_type_node;
8869 void_type_internal_node = void_type_node;
8871 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8872 get_identifier ("__bool char"),
8873 bool_char_type_node));
8874 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8875 get_identifier ("__bool short"),
8876 bool_short_type_node));
8877 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8878 get_identifier ("__bool int"),
8879 bool_int_type_node));
8880 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8881 get_identifier ("__pixel"),
8884 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
8885 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
8886 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
8887 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
8889 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8890 get_identifier ("__vector unsigned char"),
8891 unsigned_V16QI_type_node));
8892 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8893 get_identifier ("__vector signed char"),
8895 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8896 get_identifier ("__vector __bool char"),
8897 bool_V16QI_type_node));
8899 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8900 get_identifier ("__vector unsigned short"),
8901 unsigned_V8HI_type_node));
8902 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8903 get_identifier ("__vector signed short"),
8905 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8906 get_identifier ("__vector __bool short"),
8907 bool_V8HI_type_node));
8909 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8910 get_identifier ("__vector unsigned int"),
8911 unsigned_V4SI_type_node));
8912 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8913 get_identifier ("__vector signed int"),
8915 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8916 get_identifier ("__vector __bool int"),
8917 bool_V4SI_type_node));
8919 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8920 get_identifier ("__vector float"),
8922 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
8923 get_identifier ("__vector __pixel"),
8924 pixel_V8HI_type_node));
8926 if (TARGET_PAIRED_FLOAT)
8927 paired_init_builtins ();
8929 spe_init_builtins ();
8931 altivec_init_builtins ();
8932 if (TARGET_ALTIVEC || TARGET_SPE || TARGET_PAIRED_FLOAT)
8933 rs6000_common_init_builtins ();
8934 if (TARGET_PPC_GFXOPT)
8936 tree ftype = build_function_type_list (float_type_node,
8940 def_builtin (MASK_PPC_GFXOPT, "__builtin_recipdivf", ftype,
8941 RS6000_BUILTIN_RECIPF);
8943 ftype = build_function_type_list (float_type_node,
8946 def_builtin (MASK_PPC_GFXOPT, "__builtin_rsqrtf", ftype,
8947 RS6000_BUILTIN_RSQRTF);
8951 tree ftype = build_function_type_list (double_type_node,
8955 def_builtin (MASK_POPCNTB, "__builtin_recipdiv", ftype,
8956 RS6000_BUILTIN_RECIP);
8961 /* AIX libm provides clog as __clog. */
8962 if (built_in_decls [BUILT_IN_CLOG])
8963 set_user_assembler_name (built_in_decls [BUILT_IN_CLOG], "__clog");
8967 /* Search through a set of builtins and enable the mask bits.
8968 DESC is an array of builtins.
8969 SIZE is the total number of builtins.
8970 START is the builtin enum at which to start.
8971 END is the builtin enum at which to end. */
8973 enable_mask_for_builtins (struct builtin_description *desc, int size,
8974 enum rs6000_builtins start,
8975 enum rs6000_builtins end)
8979 for (i = 0; i < size; ++i)
8980 if (desc[i].code == start)
8986 for (; i < size; ++i)
8988 /* Flip all the bits on. */
8989 desc[i].mask = target_flags;
8990 if (desc[i].code == end)
8996 spe_init_builtins (void)
8998 tree endlink = void_list_node;
8999 tree puint_type_node = build_pointer_type (unsigned_type_node);
9000 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
9001 struct builtin_description *d;
9004 tree v2si_ftype_4_v2si
9005 = build_function_type
9006 (opaque_V2SI_type_node,
9007 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9008 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9009 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9010 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9013 tree v2sf_ftype_4_v2sf
9014 = build_function_type
9015 (opaque_V2SF_type_node,
9016 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9017 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9018 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9019 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9022 tree int_ftype_int_v2si_v2si
9023 = build_function_type
9025 tree_cons (NULL_TREE, integer_type_node,
9026 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9027 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9030 tree int_ftype_int_v2sf_v2sf
9031 = build_function_type
9033 tree_cons (NULL_TREE, integer_type_node,
9034 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9035 tree_cons (NULL_TREE, opaque_V2SF_type_node,
9038 tree void_ftype_v2si_puint_int
9039 = build_function_type (void_type_node,
9040 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9041 tree_cons (NULL_TREE, puint_type_node,
9042 tree_cons (NULL_TREE,
9046 tree void_ftype_v2si_puint_char
9047 = build_function_type (void_type_node,
9048 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9049 tree_cons (NULL_TREE, puint_type_node,
9050 tree_cons (NULL_TREE,
9054 tree void_ftype_v2si_pv2si_int
9055 = build_function_type (void_type_node,
9056 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9057 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9058 tree_cons (NULL_TREE,
9062 tree void_ftype_v2si_pv2si_char
9063 = build_function_type (void_type_node,
9064 tree_cons (NULL_TREE, opaque_V2SI_type_node,
9065 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9066 tree_cons (NULL_TREE,
9071 = build_function_type (void_type_node,
9072 tree_cons (NULL_TREE, integer_type_node, endlink));
9075 = build_function_type (integer_type_node, endlink);
9077 tree v2si_ftype_pv2si_int
9078 = build_function_type (opaque_V2SI_type_node,
9079 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
9080 tree_cons (NULL_TREE, integer_type_node,
9083 tree v2si_ftype_puint_int
9084 = build_function_type (opaque_V2SI_type_node,
9085 tree_cons (NULL_TREE, puint_type_node,
9086 tree_cons (NULL_TREE, integer_type_node,
9089 tree v2si_ftype_pushort_int
9090 = build_function_type (opaque_V2SI_type_node,
9091 tree_cons (NULL_TREE, pushort_type_node,
9092 tree_cons (NULL_TREE, integer_type_node,
9095 tree v2si_ftype_signed_char
9096 = build_function_type (opaque_V2SI_type_node,
9097 tree_cons (NULL_TREE, signed_char_type_node,
9100 /* The initialization of the simple binary and unary builtins is
9101 done in rs6000_common_init_builtins, but we have to enable the
9102 mask bits here manually because we have run out of `target_flags'
9103 bits. We really need to redesign this mask business. */
9105 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
9106 ARRAY_SIZE (bdesc_2arg),
9109 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
9110 ARRAY_SIZE (bdesc_1arg),
9112 SPE_BUILTIN_EVSUBFUSIAAW);
9113 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
9114 ARRAY_SIZE (bdesc_spe_predicates),
9115 SPE_BUILTIN_EVCMPEQ,
9116 SPE_BUILTIN_EVFSTSTLT);
9117 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
9118 ARRAY_SIZE (bdesc_spe_evsel),
9119 SPE_BUILTIN_EVSEL_CMPGTS,
9120 SPE_BUILTIN_EVSEL_FSTSTEQ);
9122 (*lang_hooks.decls.pushdecl)
9123 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
9124 opaque_V2SI_type_node));
9126 /* Initialize irregular SPE builtins. */
9128 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
9129 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
9130 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
9131 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
9132 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
9133 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
9134 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
9135 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
9136 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
9137 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
9138 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
9139 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
9140 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
9141 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
9142 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
9143 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
9144 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
9145 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
9148 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
9149 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
9150 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
9151 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
9152 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
9153 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
9154 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
9155 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
9156 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
9157 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
9158 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
9159 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
9160 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
9161 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
9162 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
9163 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
9164 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
9165 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
9166 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
9167 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
9168 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
9169 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
9172 d = (struct builtin_description *) bdesc_spe_predicates;
9173 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
9177 switch (insn_data[d->icode].operand[1].mode)
9180 type = int_ftype_int_v2si_v2si;
9183 type = int_ftype_int_v2sf_v2sf;
9189 def_builtin (d->mask, d->name, type, d->code);
9192 /* Evsel predicates. */
9193 d = (struct builtin_description *) bdesc_spe_evsel;
9194 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
9198 switch (insn_data[d->icode].operand[1].mode)
9201 type = v2si_ftype_4_v2si;
9204 type = v2sf_ftype_4_v2sf;
9210 def_builtin (d->mask, d->name, type, d->code);
9215 paired_init_builtins (void)
9217 const struct builtin_description *d;
9219 tree endlink = void_list_node;
9221 tree int_ftype_int_v2sf_v2sf
9222 = build_function_type
9224 tree_cons (NULL_TREE, integer_type_node,
9225 tree_cons (NULL_TREE, V2SF_type_node,
9226 tree_cons (NULL_TREE, V2SF_type_node,
9228 tree pcfloat_type_node =
9229 build_pointer_type (build_qualified_type
9230 (float_type_node, TYPE_QUAL_CONST));
9232 tree v2sf_ftype_long_pcfloat = build_function_type_list (V2SF_type_node,
9233 long_integer_type_node,
9236 tree void_ftype_v2sf_long_pcfloat =
9237 build_function_type_list (void_type_node,
9239 long_integer_type_node,
9244 def_builtin (0, "__builtin_paired_lx", v2sf_ftype_long_pcfloat,
9248 def_builtin (0, "__builtin_paired_stx", void_ftype_v2sf_long_pcfloat,
9249 PAIRED_BUILTIN_STX);
9252 d = bdesc_paired_preds;
9253 for (i = 0; i < ARRAY_SIZE (bdesc_paired_preds); ++i, d++)
9257 switch (insn_data[d->icode].operand[1].mode)
9260 type = int_ftype_int_v2sf_v2sf;
9266 def_builtin (d->mask, d->name, type, d->code);
9271 altivec_init_builtins (void)
9273 const struct builtin_description *d;
9274 const struct builtin_description_predicates *dp;
9278 tree pfloat_type_node = build_pointer_type (float_type_node);
9279 tree pint_type_node = build_pointer_type (integer_type_node);
9280 tree pshort_type_node = build_pointer_type (short_integer_type_node);
9281 tree pchar_type_node = build_pointer_type (char_type_node);
9283 tree pvoid_type_node = build_pointer_type (void_type_node);
9285 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
9286 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
9287 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
9288 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
9290 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
9292 tree int_ftype_opaque
9293 = build_function_type_list (integer_type_node,
9294 opaque_V4SI_type_node, NULL_TREE);
9296 tree opaque_ftype_opaque_int
9297 = build_function_type_list (opaque_V4SI_type_node,
9298 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
9299 tree opaque_ftype_opaque_opaque_int
9300 = build_function_type_list (opaque_V4SI_type_node,
9301 opaque_V4SI_type_node, opaque_V4SI_type_node,
9302 integer_type_node, NULL_TREE);
9303 tree int_ftype_int_opaque_opaque
9304 = build_function_type_list (integer_type_node,
9305 integer_type_node, opaque_V4SI_type_node,
9306 opaque_V4SI_type_node, NULL_TREE);
9307 tree int_ftype_int_v4si_v4si
9308 = build_function_type_list (integer_type_node,
9309 integer_type_node, V4SI_type_node,
9310 V4SI_type_node, NULL_TREE);
9311 tree v4sf_ftype_pcfloat
9312 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
9313 tree void_ftype_pfloat_v4sf
9314 = build_function_type_list (void_type_node,
9315 pfloat_type_node, V4SF_type_node, NULL_TREE);
9316 tree v4si_ftype_pcint
9317 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
9318 tree void_ftype_pint_v4si
9319 = build_function_type_list (void_type_node,
9320 pint_type_node, V4SI_type_node, NULL_TREE);
9321 tree v8hi_ftype_pcshort
9322 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
9323 tree void_ftype_pshort_v8hi
9324 = build_function_type_list (void_type_node,
9325 pshort_type_node, V8HI_type_node, NULL_TREE);
9326 tree v16qi_ftype_pcchar
9327 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
9328 tree void_ftype_pchar_v16qi
9329 = build_function_type_list (void_type_node,
9330 pchar_type_node, V16QI_type_node, NULL_TREE);
9331 tree void_ftype_v4si
9332 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
9333 tree v8hi_ftype_void
9334 = build_function_type (V8HI_type_node, void_list_node);
9335 tree void_ftype_void
9336 = build_function_type (void_type_node, void_list_node);
9338 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
9340 tree opaque_ftype_long_pcvoid
9341 = build_function_type_list (opaque_V4SI_type_node,
9342 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9343 tree v16qi_ftype_long_pcvoid
9344 = build_function_type_list (V16QI_type_node,
9345 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9346 tree v8hi_ftype_long_pcvoid
9347 = build_function_type_list (V8HI_type_node,
9348 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9349 tree v4si_ftype_long_pcvoid
9350 = build_function_type_list (V4SI_type_node,
9351 long_integer_type_node, pcvoid_type_node, NULL_TREE);
9353 tree void_ftype_opaque_long_pvoid
9354 = build_function_type_list (void_type_node,
9355 opaque_V4SI_type_node, long_integer_type_node,
9356 pvoid_type_node, NULL_TREE);
9357 tree void_ftype_v4si_long_pvoid
9358 = build_function_type_list (void_type_node,
9359 V4SI_type_node, long_integer_type_node,
9360 pvoid_type_node, NULL_TREE);
9361 tree void_ftype_v16qi_long_pvoid
9362 = build_function_type_list (void_type_node,
9363 V16QI_type_node, long_integer_type_node,
9364 pvoid_type_node, NULL_TREE);
9365 tree void_ftype_v8hi_long_pvoid
9366 = build_function_type_list (void_type_node,
9367 V8HI_type_node, long_integer_type_node,
9368 pvoid_type_node, NULL_TREE);
9369 tree int_ftype_int_v8hi_v8hi
9370 = build_function_type_list (integer_type_node,
9371 integer_type_node, V8HI_type_node,
9372 V8HI_type_node, NULL_TREE);
9373 tree int_ftype_int_v16qi_v16qi
9374 = build_function_type_list (integer_type_node,
9375 integer_type_node, V16QI_type_node,
9376 V16QI_type_node, NULL_TREE);
9377 tree int_ftype_int_v4sf_v4sf
9378 = build_function_type_list (integer_type_node,
9379 integer_type_node, V4SF_type_node,
9380 V4SF_type_node, NULL_TREE);
9381 tree v4si_ftype_v4si
9382 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
9383 tree v8hi_ftype_v8hi
9384 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
9385 tree v16qi_ftype_v16qi
9386 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
9387 tree v4sf_ftype_v4sf
9388 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9389 tree void_ftype_pcvoid_int_int
9390 = build_function_type_list (void_type_node,
9391 pcvoid_type_node, integer_type_node,
9392 integer_type_node, NULL_TREE);
9394 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
9395 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
9396 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
9397 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
9398 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
9399 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
9400 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
9401 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
9402 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
9403 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
9404 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
9405 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
9406 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
9407 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
9408 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
9409 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
9410 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
9411 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
9412 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
9413 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
9414 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
9415 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
9416 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
9417 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
9418 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
9419 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
9420 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
9421 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
9422 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
9423 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
9424 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
9425 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
9426 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
9427 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
9428 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
9429 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
9430 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
9431 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
9432 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
9433 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
9434 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
9435 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
9436 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
9437 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
9438 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
9439 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
9441 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
9443 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
9444 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
9445 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
9446 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
9447 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
9448 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
9449 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
9450 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
9451 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
9452 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
9454 /* Add the DST variants. */
9456 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
9457 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
9459 /* Initialize the predicates. */
9460 dp = bdesc_altivec_preds;
9461 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
9463 enum machine_mode mode1;
9465 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9466 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9471 mode1 = insn_data[dp->icode].operand[1].mode;
9476 type = int_ftype_int_opaque_opaque;
9479 type = int_ftype_int_v4si_v4si;
9482 type = int_ftype_int_v8hi_v8hi;
9485 type = int_ftype_int_v16qi_v16qi;
9488 type = int_ftype_int_v4sf_v4sf;
9494 def_builtin (dp->mask, dp->name, type, dp->code);
9497 /* Initialize the abs* operators. */
9499 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
9501 enum machine_mode mode0;
9504 mode0 = insn_data[d->icode].operand[0].mode;
9509 type = v4si_ftype_v4si;
9512 type = v8hi_ftype_v8hi;
9515 type = v16qi_ftype_v16qi;
9518 type = v4sf_ftype_v4sf;
9524 def_builtin (d->mask, d->name, type, d->code);
9531 /* Initialize target builtin that implements
9532 targetm.vectorize.builtin_mask_for_load. */
9534 decl = add_builtin_function ("__builtin_altivec_mask_for_load",
9535 v16qi_ftype_long_pcvoid,
9536 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
9537 BUILT_IN_MD, NULL, NULL_TREE);
9538 TREE_READONLY (decl) = 1;
9539 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
9540 altivec_builtin_mask_for_load = decl;
9543 /* Access to the vec_init patterns. */
9544 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
9545 integer_type_node, integer_type_node,
9546 integer_type_node, NULL_TREE);
9547 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
9548 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
9550 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
9551 short_integer_type_node,
9552 short_integer_type_node,
9553 short_integer_type_node,
9554 short_integer_type_node,
9555 short_integer_type_node,
9556 short_integer_type_node,
9557 short_integer_type_node, NULL_TREE);
9558 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
9559 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
9561 ftype = build_function_type_list (V16QI_type_node, char_type_node,
9562 char_type_node, char_type_node,
9563 char_type_node, char_type_node,
9564 char_type_node, char_type_node,
9565 char_type_node, char_type_node,
9566 char_type_node, char_type_node,
9567 char_type_node, char_type_node,
9568 char_type_node, char_type_node,
9569 char_type_node, NULL_TREE);
9570 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
9571 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
9573 ftype = build_function_type_list (V4SF_type_node, float_type_node,
9574 float_type_node, float_type_node,
9575 float_type_node, NULL_TREE);
9576 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
9577 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
9579 /* Access to the vec_set patterns. */
9580 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
9582 integer_type_node, NULL_TREE);
9583 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
9584 ALTIVEC_BUILTIN_VEC_SET_V4SI);
9586 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
9588 integer_type_node, NULL_TREE);
9589 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
9590 ALTIVEC_BUILTIN_VEC_SET_V8HI);
9592 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
9594 integer_type_node, NULL_TREE);
9595 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
9596 ALTIVEC_BUILTIN_VEC_SET_V16QI);
9598 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
9600 integer_type_node, NULL_TREE);
9601 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
9602 ALTIVEC_BUILTIN_VEC_SET_V4SF);
9604 /* Access to the vec_extract patterns. */
9605 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
9606 integer_type_node, NULL_TREE);
9607 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
9608 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
9610 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
9611 integer_type_node, NULL_TREE);
9612 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
9613 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
9615 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
9616 integer_type_node, NULL_TREE);
9617 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
9618 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
9620 ftype = build_function_type_list (float_type_node, V4SF_type_node,
9621 integer_type_node, NULL_TREE);
9622 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
9623 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
9627 rs6000_common_init_builtins (void)
9629 const struct builtin_description *d;
9632 tree v2sf_ftype_v2sf_v2sf_v2sf
9633 = build_function_type_list (V2SF_type_node,
9634 V2SF_type_node, V2SF_type_node,
9635 V2SF_type_node, NULL_TREE);
9637 tree v4sf_ftype_v4sf_v4sf_v16qi
9638 = build_function_type_list (V4SF_type_node,
9639 V4SF_type_node, V4SF_type_node,
9640 V16QI_type_node, NULL_TREE);
9641 tree v4si_ftype_v4si_v4si_v16qi
9642 = build_function_type_list (V4SI_type_node,
9643 V4SI_type_node, V4SI_type_node,
9644 V16QI_type_node, NULL_TREE);
9645 tree v8hi_ftype_v8hi_v8hi_v16qi
9646 = build_function_type_list (V8HI_type_node,
9647 V8HI_type_node, V8HI_type_node,
9648 V16QI_type_node, NULL_TREE);
9649 tree v16qi_ftype_v16qi_v16qi_v16qi
9650 = build_function_type_list (V16QI_type_node,
9651 V16QI_type_node, V16QI_type_node,
9652 V16QI_type_node, NULL_TREE);
9654 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
9656 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
9657 tree v16qi_ftype_int
9658 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
9659 tree v8hi_ftype_v16qi
9660 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
9661 tree v4sf_ftype_v4sf
9662 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
9664 tree v2si_ftype_v2si_v2si
9665 = build_function_type_list (opaque_V2SI_type_node,
9666 opaque_V2SI_type_node,
9667 opaque_V2SI_type_node, NULL_TREE);
9669 tree v2sf_ftype_v2sf_v2sf_spe
9670 = build_function_type_list (opaque_V2SF_type_node,
9671 opaque_V2SF_type_node,
9672 opaque_V2SF_type_node, NULL_TREE);
9674 tree v2sf_ftype_v2sf_v2sf
9675 = build_function_type_list (V2SF_type_node,
9677 V2SF_type_node, NULL_TREE);
9680 tree v2si_ftype_int_int
9681 = build_function_type_list (opaque_V2SI_type_node,
9682 integer_type_node, integer_type_node,
9685 tree opaque_ftype_opaque
9686 = build_function_type_list (opaque_V4SI_type_node,
9687 opaque_V4SI_type_node, NULL_TREE);
9689 tree v2si_ftype_v2si
9690 = build_function_type_list (opaque_V2SI_type_node,
9691 opaque_V2SI_type_node, NULL_TREE);
9693 tree v2sf_ftype_v2sf_spe
9694 = build_function_type_list (opaque_V2SF_type_node,
9695 opaque_V2SF_type_node, NULL_TREE);
9697 tree v2sf_ftype_v2sf
9698 = build_function_type_list (V2SF_type_node,
9699 V2SF_type_node, NULL_TREE);
9701 tree v2sf_ftype_v2si
9702 = build_function_type_list (opaque_V2SF_type_node,
9703 opaque_V2SI_type_node, NULL_TREE);
9705 tree v2si_ftype_v2sf
9706 = build_function_type_list (opaque_V2SI_type_node,
9707 opaque_V2SF_type_node, NULL_TREE);
9709 tree v2si_ftype_v2si_char
9710 = build_function_type_list (opaque_V2SI_type_node,
9711 opaque_V2SI_type_node,
9712 char_type_node, NULL_TREE);
9714 tree v2si_ftype_int_char
9715 = build_function_type_list (opaque_V2SI_type_node,
9716 integer_type_node, char_type_node, NULL_TREE);
9718 tree v2si_ftype_char
9719 = build_function_type_list (opaque_V2SI_type_node,
9720 char_type_node, NULL_TREE);
9722 tree int_ftype_int_int
9723 = build_function_type_list (integer_type_node,
9724 integer_type_node, integer_type_node,
9727 tree opaque_ftype_opaque_opaque
9728 = build_function_type_list (opaque_V4SI_type_node,
9729 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
9730 tree v4si_ftype_v4si_v4si
9731 = build_function_type_list (V4SI_type_node,
9732 V4SI_type_node, V4SI_type_node, NULL_TREE);
9733 tree v4sf_ftype_v4si_int
9734 = build_function_type_list (V4SF_type_node,
9735 V4SI_type_node, integer_type_node, NULL_TREE);
9736 tree v4si_ftype_v4sf_int
9737 = build_function_type_list (V4SI_type_node,
9738 V4SF_type_node, integer_type_node, NULL_TREE);
9739 tree v4si_ftype_v4si_int
9740 = build_function_type_list (V4SI_type_node,
9741 V4SI_type_node, integer_type_node, NULL_TREE);
9742 tree v8hi_ftype_v8hi_int
9743 = build_function_type_list (V8HI_type_node,
9744 V8HI_type_node, integer_type_node, NULL_TREE);
9745 tree v16qi_ftype_v16qi_int
9746 = build_function_type_list (V16QI_type_node,
9747 V16QI_type_node, integer_type_node, NULL_TREE);
9748 tree v16qi_ftype_v16qi_v16qi_int
9749 = build_function_type_list (V16QI_type_node,
9750 V16QI_type_node, V16QI_type_node,
9751 integer_type_node, NULL_TREE);
9752 tree v8hi_ftype_v8hi_v8hi_int
9753 = build_function_type_list (V8HI_type_node,
9754 V8HI_type_node, V8HI_type_node,
9755 integer_type_node, NULL_TREE);
9756 tree v4si_ftype_v4si_v4si_int
9757 = build_function_type_list (V4SI_type_node,
9758 V4SI_type_node, V4SI_type_node,
9759 integer_type_node, NULL_TREE);
9760 tree v4sf_ftype_v4sf_v4sf_int
9761 = build_function_type_list (V4SF_type_node,
9762 V4SF_type_node, V4SF_type_node,
9763 integer_type_node, NULL_TREE);
9764 tree v4sf_ftype_v4sf_v4sf
9765 = build_function_type_list (V4SF_type_node,
9766 V4SF_type_node, V4SF_type_node, NULL_TREE);
9767 tree opaque_ftype_opaque_opaque_opaque
9768 = build_function_type_list (opaque_V4SI_type_node,
9769 opaque_V4SI_type_node, opaque_V4SI_type_node,
9770 opaque_V4SI_type_node, NULL_TREE);
9771 tree v4sf_ftype_v4sf_v4sf_v4si
9772 = build_function_type_list (V4SF_type_node,
9773 V4SF_type_node, V4SF_type_node,
9774 V4SI_type_node, NULL_TREE);
9775 tree v4sf_ftype_v4sf_v4sf_v4sf
9776 = build_function_type_list (V4SF_type_node,
9777 V4SF_type_node, V4SF_type_node,
9778 V4SF_type_node, NULL_TREE);
9779 tree v4si_ftype_v4si_v4si_v4si
9780 = build_function_type_list (V4SI_type_node,
9781 V4SI_type_node, V4SI_type_node,
9782 V4SI_type_node, NULL_TREE);
9783 tree v8hi_ftype_v8hi_v8hi
9784 = build_function_type_list (V8HI_type_node,
9785 V8HI_type_node, V8HI_type_node, NULL_TREE);
9786 tree v8hi_ftype_v8hi_v8hi_v8hi
9787 = build_function_type_list (V8HI_type_node,
9788 V8HI_type_node, V8HI_type_node,
9789 V8HI_type_node, NULL_TREE);
9790 tree v4si_ftype_v8hi_v8hi_v4si
9791 = build_function_type_list (V4SI_type_node,
9792 V8HI_type_node, V8HI_type_node,
9793 V4SI_type_node, NULL_TREE);
9794 tree v4si_ftype_v16qi_v16qi_v4si
9795 = build_function_type_list (V4SI_type_node,
9796 V16QI_type_node, V16QI_type_node,
9797 V4SI_type_node, NULL_TREE);
9798 tree v16qi_ftype_v16qi_v16qi
9799 = build_function_type_list (V16QI_type_node,
9800 V16QI_type_node, V16QI_type_node, NULL_TREE);
9801 tree v4si_ftype_v4sf_v4sf
9802 = build_function_type_list (V4SI_type_node,
9803 V4SF_type_node, V4SF_type_node, NULL_TREE);
9804 tree v8hi_ftype_v16qi_v16qi
9805 = build_function_type_list (V8HI_type_node,
9806 V16QI_type_node, V16QI_type_node, NULL_TREE);
9807 tree v4si_ftype_v8hi_v8hi
9808 = build_function_type_list (V4SI_type_node,
9809 V8HI_type_node, V8HI_type_node, NULL_TREE);
9810 tree v8hi_ftype_v4si_v4si
9811 = build_function_type_list (V8HI_type_node,
9812 V4SI_type_node, V4SI_type_node, NULL_TREE);
9813 tree v16qi_ftype_v8hi_v8hi
9814 = build_function_type_list (V16QI_type_node,
9815 V8HI_type_node, V8HI_type_node, NULL_TREE);
9816 tree v4si_ftype_v16qi_v4si
9817 = build_function_type_list (V4SI_type_node,
9818 V16QI_type_node, V4SI_type_node, NULL_TREE);
9819 tree v4si_ftype_v16qi_v16qi
9820 = build_function_type_list (V4SI_type_node,
9821 V16QI_type_node, V16QI_type_node, NULL_TREE);
9822 tree v4si_ftype_v8hi_v4si
9823 = build_function_type_list (V4SI_type_node,
9824 V8HI_type_node, V4SI_type_node, NULL_TREE);
9825 tree v4si_ftype_v8hi
9826 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
9827 tree int_ftype_v4si_v4si
9828 = build_function_type_list (integer_type_node,
9829 V4SI_type_node, V4SI_type_node, NULL_TREE);
9830 tree int_ftype_v4sf_v4sf
9831 = build_function_type_list (integer_type_node,
9832 V4SF_type_node, V4SF_type_node, NULL_TREE);
9833 tree int_ftype_v16qi_v16qi
9834 = build_function_type_list (integer_type_node,
9835 V16QI_type_node, V16QI_type_node, NULL_TREE);
9836 tree int_ftype_v8hi_v8hi
9837 = build_function_type_list (integer_type_node,
9838 V8HI_type_node, V8HI_type_node, NULL_TREE);
9840 /* Add the simple ternary operators. */
9842 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
9844 enum machine_mode mode0, mode1, mode2, mode3;
9846 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9847 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9858 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9861 mode0 = insn_data[d->icode].operand[0].mode;
9862 mode1 = insn_data[d->icode].operand[1].mode;
9863 mode2 = insn_data[d->icode].operand[2].mode;
9864 mode3 = insn_data[d->icode].operand[3].mode;
9867 /* When all four are of the same mode. */
9868 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
9873 type = opaque_ftype_opaque_opaque_opaque;
9876 type = v4si_ftype_v4si_v4si_v4si;
9879 type = v4sf_ftype_v4sf_v4sf_v4sf;
9882 type = v8hi_ftype_v8hi_v8hi_v8hi;
9885 type = v16qi_ftype_v16qi_v16qi_v16qi;
9888 type = v2sf_ftype_v2sf_v2sf_v2sf;
9894 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
9899 type = v4si_ftype_v4si_v4si_v16qi;
9902 type = v4sf_ftype_v4sf_v4sf_v16qi;
9905 type = v8hi_ftype_v8hi_v8hi_v16qi;
9908 type = v16qi_ftype_v16qi_v16qi_v16qi;
9914 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
9915 && mode3 == V4SImode)
9916 type = v4si_ftype_v16qi_v16qi_v4si;
9917 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
9918 && mode3 == V4SImode)
9919 type = v4si_ftype_v8hi_v8hi_v4si;
9920 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
9921 && mode3 == V4SImode)
9922 type = v4sf_ftype_v4sf_v4sf_v4si;
9924 /* vchar, vchar, vchar, 4-bit literal. */
9925 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
9927 type = v16qi_ftype_v16qi_v16qi_int;
9929 /* vshort, vshort, vshort, 4-bit literal. */
9930 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
9932 type = v8hi_ftype_v8hi_v8hi_int;
9934 /* vint, vint, vint, 4-bit literal. */
9935 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
9937 type = v4si_ftype_v4si_v4si_int;
9939 /* vfloat, vfloat, vfloat, 4-bit literal. */
9940 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
9942 type = v4sf_ftype_v4sf_v4sf_int;
9947 def_builtin (d->mask, d->name, type, d->code);
9950 /* Add the simple binary operators. */
9951 d = (struct builtin_description *) bdesc_2arg;
9952 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
9954 enum machine_mode mode0, mode1, mode2;
9956 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
9957 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
9967 if (d->name == 0 || d->icode == CODE_FOR_nothing)
9970 mode0 = insn_data[d->icode].operand[0].mode;
9971 mode1 = insn_data[d->icode].operand[1].mode;
9972 mode2 = insn_data[d->icode].operand[2].mode;
9975 /* When all three operands are of the same mode. */
9976 if (mode0 == mode1 && mode1 == mode2)
9981 type = opaque_ftype_opaque_opaque;
9984 type = v4sf_ftype_v4sf_v4sf;
9987 type = v4si_ftype_v4si_v4si;
9990 type = v16qi_ftype_v16qi_v16qi;
9993 type = v8hi_ftype_v8hi_v8hi;
9996 type = v2si_ftype_v2si_v2si;
9999 if (TARGET_PAIRED_FLOAT)
10000 type = v2sf_ftype_v2sf_v2sf;
10002 type = v2sf_ftype_v2sf_v2sf_spe;
10005 type = int_ftype_int_int;
10008 gcc_unreachable ();
10012 /* A few other combos we really don't want to do manually. */
10014 /* vint, vfloat, vfloat. */
10015 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
10016 type = v4si_ftype_v4sf_v4sf;
10018 /* vshort, vchar, vchar. */
10019 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
10020 type = v8hi_ftype_v16qi_v16qi;
10022 /* vint, vshort, vshort. */
10023 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
10024 type = v4si_ftype_v8hi_v8hi;
10026 /* vshort, vint, vint. */
10027 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
10028 type = v8hi_ftype_v4si_v4si;
10030 /* vchar, vshort, vshort. */
10031 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
10032 type = v16qi_ftype_v8hi_v8hi;
10034 /* vint, vchar, vint. */
10035 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
10036 type = v4si_ftype_v16qi_v4si;
10038 /* vint, vchar, vchar. */
10039 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
10040 type = v4si_ftype_v16qi_v16qi;
10042 /* vint, vshort, vint. */
10043 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
10044 type = v4si_ftype_v8hi_v4si;
10046 /* vint, vint, 5-bit literal. */
10047 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
10048 type = v4si_ftype_v4si_int;
10050 /* vshort, vshort, 5-bit literal. */
10051 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
10052 type = v8hi_ftype_v8hi_int;
10054 /* vchar, vchar, 5-bit literal. */
10055 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
10056 type = v16qi_ftype_v16qi_int;
10058 /* vfloat, vint, 5-bit literal. */
10059 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
10060 type = v4sf_ftype_v4si_int;
10062 /* vint, vfloat, 5-bit literal. */
10063 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
10064 type = v4si_ftype_v4sf_int;
10066 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
10067 type = v2si_ftype_int_int;
10069 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
10070 type = v2si_ftype_v2si_char;
10072 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
10073 type = v2si_ftype_int_char;
10078 gcc_assert (mode0 == SImode);
10082 type = int_ftype_v4si_v4si;
10085 type = int_ftype_v4sf_v4sf;
10088 type = int_ftype_v16qi_v16qi;
10091 type = int_ftype_v8hi_v8hi;
10094 gcc_unreachable ();
10098 def_builtin (d->mask, d->name, type, d->code);
10101 /* Add the simple unary operators. */
10102 d = (struct builtin_description *) bdesc_1arg;
10103 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
10105 enum machine_mode mode0, mode1;
10107 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
10108 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
10117 if (d->name == 0 || d->icode == CODE_FOR_nothing)
10120 mode0 = insn_data[d->icode].operand[0].mode;
10121 mode1 = insn_data[d->icode].operand[1].mode;
10124 if (mode0 == V4SImode && mode1 == QImode)
10125 type = v4si_ftype_int;
10126 else if (mode0 == V8HImode && mode1 == QImode)
10127 type = v8hi_ftype_int;
10128 else if (mode0 == V16QImode && mode1 == QImode)
10129 type = v16qi_ftype_int;
10130 else if (mode0 == VOIDmode && mode1 == VOIDmode)
10131 type = opaque_ftype_opaque;
10132 else if (mode0 == V4SFmode && mode1 == V4SFmode)
10133 type = v4sf_ftype_v4sf;
10134 else if (mode0 == V8HImode && mode1 == V16QImode)
10135 type = v8hi_ftype_v16qi;
10136 else if (mode0 == V4SImode && mode1 == V8HImode)
10137 type = v4si_ftype_v8hi;
10138 else if (mode0 == V2SImode && mode1 == V2SImode)
10139 type = v2si_ftype_v2si;
10140 else if (mode0 == V2SFmode && mode1 == V2SFmode)
10142 if (TARGET_PAIRED_FLOAT)
10143 type = v2sf_ftype_v2sf;
10145 type = v2sf_ftype_v2sf_spe;
10147 else if (mode0 == V2SFmode && mode1 == V2SImode)
10148 type = v2sf_ftype_v2si;
10149 else if (mode0 == V2SImode && mode1 == V2SFmode)
10150 type = v2si_ftype_v2sf;
10151 else if (mode0 == V2SImode && mode1 == QImode)
10152 type = v2si_ftype_char;
10154 gcc_unreachable ();
10156 def_builtin (d->mask, d->name, type, d->code);
10161 rs6000_init_libfuncs (void)
10163 if (DEFAULT_ABI != ABI_V4 && TARGET_XCOFF
10164 && !TARGET_POWER2 && !TARGET_POWERPC)
10166 /* AIX library routines for float->int conversion. */
10167 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
10168 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
10169 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
10170 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
10173 if (!TARGET_IEEEQUAD)
10174 /* AIX/Darwin/64-bit Linux quad floating point routines. */
10175 if (!TARGET_XL_COMPAT)
10177 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
10178 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
10179 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
10180 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
10182 if (!(TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)))
10184 set_optab_libfunc (neg_optab, TFmode, "__gcc_qneg");
10185 set_optab_libfunc (eq_optab, TFmode, "__gcc_qeq");
10186 set_optab_libfunc (ne_optab, TFmode, "__gcc_qne");
10187 set_optab_libfunc (gt_optab, TFmode, "__gcc_qgt");
10188 set_optab_libfunc (ge_optab, TFmode, "__gcc_qge");
10189 set_optab_libfunc (lt_optab, TFmode, "__gcc_qlt");
10190 set_optab_libfunc (le_optab, TFmode, "__gcc_qle");
10192 set_conv_libfunc (sext_optab, TFmode, SFmode, "__gcc_stoq");
10193 set_conv_libfunc (sext_optab, TFmode, DFmode, "__gcc_dtoq");
10194 set_conv_libfunc (trunc_optab, SFmode, TFmode, "__gcc_qtos");
10195 set_conv_libfunc (trunc_optab, DFmode, TFmode, "__gcc_qtod");
10196 set_conv_libfunc (sfix_optab, SImode, TFmode, "__gcc_qtoi");
10197 set_conv_libfunc (ufix_optab, SImode, TFmode, "__gcc_qtou");
10198 set_conv_libfunc (sfloat_optab, TFmode, SImode, "__gcc_itoq");
10199 set_conv_libfunc (ufloat_optab, TFmode, SImode, "__gcc_utoq");
10202 if (!(TARGET_HARD_FLOAT && TARGET_FPRS))
10203 set_optab_libfunc (unord_optab, TFmode, "__gcc_qunord");
10207 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
10208 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
10209 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
10210 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
10214 /* 32-bit SVR4 quad floating point routines. */
10216 set_optab_libfunc (add_optab, TFmode, "_q_add");
10217 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
10218 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
10219 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
10220 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
10221 if (TARGET_PPC_GPOPT || TARGET_POWER2)
10222 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
10224 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
10225 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
10226 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
10227 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
10228 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
10229 set_optab_libfunc (le_optab, TFmode, "_q_fle");
10231 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
10232 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
10233 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
10234 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
10235 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
10236 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
10237 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
10238 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_q_utoq");
10243 /* Expand a block clear operation, and return 1 if successful. Return 0
10244 if we should let the compiler generate normal code.
10246 operands[0] is the destination
10247 operands[1] is the length
10248 operands[3] is the alignment */
10251 expand_block_clear (rtx operands[])
10253 rtx orig_dest = operands[0];
10254 rtx bytes_rtx = operands[1];
10255 rtx align_rtx = operands[3];
10256 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
10257 HOST_WIDE_INT align;
10258 HOST_WIDE_INT bytes;
10263 /* If this is not a fixed size move, just call memcpy */
10267 /* This must be a fixed size alignment */
10268 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10269 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10271 /* Anything to clear? */
10272 bytes = INTVAL (bytes_rtx);
10276 /* Use the builtin memset after a point, to avoid huge code bloat.
10277 When optimize_size, avoid any significant code bloat; calling
10278 memset is about 4 instructions, so allow for one instruction to
10279 load zero and three to do clearing. */
10280 if (TARGET_ALTIVEC && align >= 128)
10282 else if (TARGET_POWERPC64 && align >= 32)
10284 else if (TARGET_SPE && align >= 64)
10289 if (optimize_size && bytes > 3 * clear_step)
10291 if (! optimize_size && bytes > 8 * clear_step)
10294 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
10296 enum machine_mode mode = BLKmode;
10299 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
10304 else if (bytes >= 8 && TARGET_SPE && align >= 64)
10309 else if (bytes >= 8 && TARGET_POWERPC64
10310 /* 64-bit loads and stores require word-aligned
10312 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10317 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10318 { /* move 4 bytes */
10322 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10323 { /* move 2 bytes */
10327 else /* move 1 byte at a time */
10333 dest = adjust_address (orig_dest, mode, offset);
10335 emit_move_insn (dest, CONST0_RTX (mode));
10342 /* Expand a block move operation, and return 1 if successful. Return 0
10343 if we should let the compiler generate normal code.
10345 operands[0] is the destination
10346 operands[1] is the source
10347 operands[2] is the length
10348 operands[3] is the alignment */
10350 #define MAX_MOVE_REG 4
10353 expand_block_move (rtx operands[])
10355 rtx orig_dest = operands[0];
10356 rtx orig_src = operands[1];
10357 rtx bytes_rtx = operands[2];
10358 rtx align_rtx = operands[3];
10359 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
10364 rtx stores[MAX_MOVE_REG];
10367 /* If this is not a fixed size move, just call memcpy */
10371 /* This must be a fixed size alignment */
10372 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
10373 align = INTVAL (align_rtx) * BITS_PER_UNIT;
10375 /* Anything to move? */
10376 bytes = INTVAL (bytes_rtx);
10380 /* store_one_arg depends on expand_block_move to handle at least the size of
10381 reg_parm_stack_space. */
10382 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
10385 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
10388 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
10389 rtx (*mov) (rtx, rtx);
10391 enum machine_mode mode = BLKmode;
10394 /* Altivec first, since it will be faster than a string move
10395 when it applies, and usually not significantly larger. */
10396 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
10400 gen_func.mov = gen_movv4si;
10402 else if (TARGET_SPE && bytes >= 8 && align >= 64)
10406 gen_func.mov = gen_movv2si;
10408 else if (TARGET_STRING
10409 && bytes > 24 /* move up to 32 bytes at a time */
10415 && ! fixed_regs[10]
10416 && ! fixed_regs[11]
10417 && ! fixed_regs[12])
10419 move_bytes = (bytes > 32) ? 32 : bytes;
10420 gen_func.movmemsi = gen_movmemsi_8reg;
10422 else if (TARGET_STRING
10423 && bytes > 16 /* move up to 24 bytes at a time */
10429 && ! fixed_regs[10])
10431 move_bytes = (bytes > 24) ? 24 : bytes;
10432 gen_func.movmemsi = gen_movmemsi_6reg;
10434 else if (TARGET_STRING
10435 && bytes > 8 /* move up to 16 bytes at a time */
10439 && ! fixed_regs[8])
10441 move_bytes = (bytes > 16) ? 16 : bytes;
10442 gen_func.movmemsi = gen_movmemsi_4reg;
10444 else if (bytes >= 8 && TARGET_POWERPC64
10445 /* 64-bit loads and stores require word-aligned
10447 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
10451 gen_func.mov = gen_movdi;
10453 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
10454 { /* move up to 8 bytes at a time */
10455 move_bytes = (bytes > 8) ? 8 : bytes;
10456 gen_func.movmemsi = gen_movmemsi_2reg;
10458 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
10459 { /* move 4 bytes */
10462 gen_func.mov = gen_movsi;
10464 else if (bytes >= 2 && (align >= 16 || !STRICT_ALIGNMENT))
10465 { /* move 2 bytes */
10468 gen_func.mov = gen_movhi;
10470 else if (TARGET_STRING && bytes > 1)
10471 { /* move up to 4 bytes at a time */
10472 move_bytes = (bytes > 4) ? 4 : bytes;
10473 gen_func.movmemsi = gen_movmemsi_1reg;
10475 else /* move 1 byte at a time */
10479 gen_func.mov = gen_movqi;
10482 src = adjust_address (orig_src, mode, offset);
10483 dest = adjust_address (orig_dest, mode, offset);
10485 if (mode != BLKmode)
10487 rtx tmp_reg = gen_reg_rtx (mode);
10489 emit_insn ((*gen_func.mov) (tmp_reg, src));
10490 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
10493 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
10496 for (i = 0; i < num_reg; i++)
10497 emit_insn (stores[i]);
10501 if (mode == BLKmode)
10503 /* Move the address into scratch registers. The movmemsi
10504 patterns require zero offset. */
10505 if (!REG_P (XEXP (src, 0)))
10507 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
10508 src = replace_equiv_address (src, src_reg);
10510 set_mem_size (src, GEN_INT (move_bytes));
10512 if (!REG_P (XEXP (dest, 0)))
10514 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
10515 dest = replace_equiv_address (dest, dest_reg);
10517 set_mem_size (dest, GEN_INT (move_bytes));
10519 emit_insn ((*gen_func.movmemsi) (dest, src,
10520 GEN_INT (move_bytes & 31),
10529 /* Return a string to perform a load_multiple operation.
10530 operands[0] is the vector.
10531 operands[1] is the source address.
10532 operands[2] is the first destination register. */
10535 rs6000_output_load_multiple (rtx operands[3])
10537 /* We have to handle the case where the pseudo used to contain the address
10538 is assigned to one of the output registers. */
10540 int words = XVECLEN (operands[0], 0);
10543 if (XVECLEN (operands[0], 0) == 1)
10544 return "{l|lwz} %2,0(%1)";
10546 for (i = 0; i < words; i++)
10547 if (refers_to_regno_p (REGNO (operands[2]) + i,
10548 REGNO (operands[2]) + i + 1, operands[1], 0))
10552 xop[0] = GEN_INT (4 * (words-1));
10553 xop[1] = operands[1];
10554 xop[2] = operands[2];
10555 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
10560 xop[0] = GEN_INT (4 * (words-1));
10561 xop[1] = operands[1];
10562 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
10563 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
10568 for (j = 0; j < words; j++)
10571 xop[0] = GEN_INT (j * 4);
10572 xop[1] = operands[1];
10573 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
10574 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
10576 xop[0] = GEN_INT (i * 4);
10577 xop[1] = operands[1];
10578 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
10583 return "{lsi|lswi} %2,%1,%N0";
10587 /* A validation routine: say whether CODE, a condition code, and MODE
10588 match. The other alternatives either don't make sense or should
10589 never be generated. */
10592 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
10594 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
10595 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
10596 && GET_MODE_CLASS (mode) == MODE_CC);
10598 /* These don't make sense. */
10599 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
10600 || mode != CCUNSmode);
10602 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
10603 || mode == CCUNSmode);
10605 gcc_assert (mode == CCFPmode
10606 || (code != ORDERED && code != UNORDERED
10607 && code != UNEQ && code != LTGT
10608 && code != UNGT && code != UNLT
10609 && code != UNGE && code != UNLE));
10611 /* These should never be generated except for
10612 flag_finite_math_only. */
10613 gcc_assert (mode != CCFPmode
10614 || flag_finite_math_only
10615 || (code != LE && code != GE
10616 && code != UNEQ && code != LTGT
10617 && code != UNGT && code != UNLT));
10619 /* These are invalid; the information is not there. */
10620 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
10624 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
10625 mask required to convert the result of a rotate insn into a shift
10626 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
10629 includes_lshift_p (rtx shiftop, rtx andop)
10631 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10633 shift_mask <<= INTVAL (shiftop);
10635 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10638 /* Similar, but for right shift. */
10641 includes_rshift_p (rtx shiftop, rtx andop)
10643 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
10645 shift_mask >>= INTVAL (shiftop);
10647 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
10650 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
10651 to perform a left shift. It must have exactly SHIFTOP least
10652 significant 0's, then one or more 1's, then zero or more 0's. */
10655 includes_rldic_lshift_p (rtx shiftop, rtx andop)
10657 if (GET_CODE (andop) == CONST_INT)
10659 HOST_WIDE_INT c, lsb, shift_mask;
10661 c = INTVAL (andop);
10662 if (c == 0 || c == ~0)
10666 shift_mask <<= INTVAL (shiftop);
10668 /* Find the least significant one bit. */
10671 /* It must coincide with the LSB of the shift mask. */
10672 if (-lsb != shift_mask)
10675 /* Invert to look for the next transition (if any). */
10678 /* Remove the low group of ones (originally low group of zeros). */
10681 /* Again find the lsb, and check we have all 1's above. */
10685 else if (GET_CODE (andop) == CONST_DOUBLE
10686 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10688 HOST_WIDE_INT low, high, lsb;
10689 HOST_WIDE_INT shift_mask_low, shift_mask_high;
10691 low = CONST_DOUBLE_LOW (andop);
10692 if (HOST_BITS_PER_WIDE_INT < 64)
10693 high = CONST_DOUBLE_HIGH (andop);
10695 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
10696 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
10699 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10701 shift_mask_high = ~0;
10702 if (INTVAL (shiftop) > 32)
10703 shift_mask_high <<= INTVAL (shiftop) - 32;
10705 lsb = high & -high;
10707 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
10713 lsb = high & -high;
10714 return high == -lsb;
10717 shift_mask_low = ~0;
10718 shift_mask_low <<= INTVAL (shiftop);
10722 if (-lsb != shift_mask_low)
10725 if (HOST_BITS_PER_WIDE_INT < 64)
10730 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
10732 lsb = high & -high;
10733 return high == -lsb;
10737 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
10743 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
10744 to perform a left shift. It must have SHIFTOP or more least
10745 significant 0's, with the remainder of the word 1's. */
10748 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
10750 if (GET_CODE (andop) == CONST_INT)
10752 HOST_WIDE_INT c, lsb, shift_mask;
10755 shift_mask <<= INTVAL (shiftop);
10756 c = INTVAL (andop);
10758 /* Find the least significant one bit. */
10761 /* It must be covered by the shift mask.
10762 This test also rejects c == 0. */
10763 if ((lsb & shift_mask) == 0)
10766 /* Check we have all 1's above the transition, and reject all 1's. */
10767 return c == -lsb && lsb != 1;
10769 else if (GET_CODE (andop) == CONST_DOUBLE
10770 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
10772 HOST_WIDE_INT low, lsb, shift_mask_low;
10774 low = CONST_DOUBLE_LOW (andop);
10776 if (HOST_BITS_PER_WIDE_INT < 64)
10778 HOST_WIDE_INT high, shift_mask_high;
10780 high = CONST_DOUBLE_HIGH (andop);
10784 shift_mask_high = ~0;
10785 if (INTVAL (shiftop) > 32)
10786 shift_mask_high <<= INTVAL (shiftop) - 32;
10788 lsb = high & -high;
10790 if ((lsb & shift_mask_high) == 0)
10793 return high == -lsb;
10799 shift_mask_low = ~0;
10800 shift_mask_low <<= INTVAL (shiftop);
10804 if ((lsb & shift_mask_low) == 0)
10807 return low == -lsb && lsb != 1;
10813 /* Return 1 if operands will generate a valid arguments to rlwimi
10814 instruction for insert with right shift in 64-bit mode. The mask may
10815 not start on the first bit or stop on the last bit because wrap-around
10816 effects of instruction do not correspond to semantics of RTL insn. */
10819 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
10821 if (INTVAL (startop) > 32
10822 && INTVAL (startop) < 64
10823 && INTVAL (sizeop) > 1
10824 && INTVAL (sizeop) + INTVAL (startop) < 64
10825 && INTVAL (shiftop) > 0
10826 && INTVAL (sizeop) + INTVAL (shiftop) < 32
10827 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
10833 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
10834 for lfq and stfq insns iff the registers are hard registers. */
10837 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
10839 /* We might have been passed a SUBREG. */
10840 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
10843 /* We might have been passed non floating point registers. */
10844 if (!FP_REGNO_P (REGNO (reg1))
10845 || !FP_REGNO_P (REGNO (reg2)))
10848 return (REGNO (reg1) == REGNO (reg2) - 1);
10851 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
10852 addr1 and addr2 must be in consecutive memory locations
10853 (addr2 == addr1 + 8). */
10856 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
10859 unsigned int reg1, reg2;
10860 int offset1, offset2;
10862 /* The mems cannot be volatile. */
10863 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
10866 addr1 = XEXP (mem1, 0);
10867 addr2 = XEXP (mem2, 0);
10869 /* Extract an offset (if used) from the first addr. */
10870 if (GET_CODE (addr1) == PLUS)
10872 /* If not a REG, return zero. */
10873 if (GET_CODE (XEXP (addr1, 0)) != REG)
10877 reg1 = REGNO (XEXP (addr1, 0));
10878 /* The offset must be constant! */
10879 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
10881 offset1 = INTVAL (XEXP (addr1, 1));
10884 else if (GET_CODE (addr1) != REG)
10888 reg1 = REGNO (addr1);
10889 /* This was a simple (mem (reg)) expression. Offset is 0. */
10893 /* And now for the second addr. */
10894 if (GET_CODE (addr2) == PLUS)
10896 /* If not a REG, return zero. */
10897 if (GET_CODE (XEXP (addr2, 0)) != REG)
10901 reg2 = REGNO (XEXP (addr2, 0));
10902 /* The offset must be constant. */
10903 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
10905 offset2 = INTVAL (XEXP (addr2, 1));
10908 else if (GET_CODE (addr2) != REG)
10912 reg2 = REGNO (addr2);
10913 /* This was a simple (mem (reg)) expression. Offset is 0. */
10917 /* Both of these must have the same base register. */
10921 /* The offset for the second addr must be 8 more than the first addr. */
10922 if (offset2 != offset1 + 8)
10925 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
10930 /* Return the register class of a scratch register needed to copy IN into
10931 or out of a register in CLASS in MODE. If it can be done directly,
10932 NO_REGS is returned. */
10935 rs6000_secondary_reload_class (enum reg_class class,
10936 enum machine_mode mode ATTRIBUTE_UNUSED,
10941 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
10943 && MACHOPIC_INDIRECT
10947 /* We cannot copy a symbolic operand directly into anything
10948 other than BASE_REGS for TARGET_ELF. So indicate that a
10949 register from BASE_REGS is needed as an intermediate
10952 On Darwin, pic addresses require a load from memory, which
10953 needs a base register. */
10954 if (class != BASE_REGS
10955 && (GET_CODE (in) == SYMBOL_REF
10956 || GET_CODE (in) == HIGH
10957 || GET_CODE (in) == LABEL_REF
10958 || GET_CODE (in) == CONST))
10962 if (GET_CODE (in) == REG)
10964 regno = REGNO (in);
10965 if (regno >= FIRST_PSEUDO_REGISTER)
10967 regno = true_regnum (in);
10968 if (regno >= FIRST_PSEUDO_REGISTER)
10972 else if (GET_CODE (in) == SUBREG)
10974 regno = true_regnum (in);
10975 if (regno >= FIRST_PSEUDO_REGISTER)
10981 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
10983 if (class == GENERAL_REGS || class == BASE_REGS
10984 || (regno >= 0 && INT_REGNO_P (regno)))
10987 /* Constants, memory, and FP registers can go into FP registers. */
10988 if ((regno == -1 || FP_REGNO_P (regno))
10989 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
10992 /* Memory, and AltiVec registers can go into AltiVec registers. */
10993 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
10994 && class == ALTIVEC_REGS)
10997 /* We can copy among the CR registers. */
10998 if ((class == CR_REGS || class == CR0_REGS)
10999 && regno >= 0 && CR_REGNO_P (regno))
11002 /* Otherwise, we need GENERAL_REGS. */
11003 return GENERAL_REGS;
11006 /* Given a comparison operation, return the bit number in CCR to test. We
11007 know this is a valid comparison.
11009 SCC_P is 1 if this is for an scc. That means that %D will have been
11010 used instead of %C, so the bits will be in different places.
11012 Return -1 if OP isn't a valid comparison for some reason. */
11015 ccr_bit (rtx op, int scc_p)
11017 enum rtx_code code = GET_CODE (op);
11018 enum machine_mode cc_mode;
11023 if (!COMPARISON_P (op))
11026 reg = XEXP (op, 0);
11028 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
11030 cc_mode = GET_MODE (reg);
11031 cc_regnum = REGNO (reg);
11032 base_bit = 4 * (cc_regnum - CR0_REGNO);
11034 validate_condition_mode (code, cc_mode);
11036 /* When generating a sCOND operation, only positive conditions are
11039 || code == EQ || code == GT || code == LT || code == UNORDERED
11040 || code == GTU || code == LTU);
11045 return scc_p ? base_bit + 3 : base_bit + 2;
11047 return base_bit + 2;
11048 case GT: case GTU: case UNLE:
11049 return base_bit + 1;
11050 case LT: case LTU: case UNGE:
11052 case ORDERED: case UNORDERED:
11053 return base_bit + 3;
11056 /* If scc, we will have done a cror to put the bit in the
11057 unordered position. So test that bit. For integer, this is ! LT
11058 unless this is an scc insn. */
11059 return scc_p ? base_bit + 3 : base_bit;
11062 return scc_p ? base_bit + 3 : base_bit + 1;
11065 gcc_unreachable ();
11069 /* Return the GOT register. */
11072 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
11074 /* The second flow pass currently (June 1999) can't update
11075 regs_ever_live without disturbing other parts of the compiler, so
11076 update it here to make the prolog/epilogue code happy. */
11077 if (!can_create_pseudo_p ()
11078 && !df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM))
11079 df_set_regs_ever_live (RS6000_PIC_OFFSET_TABLE_REGNUM, true);
11081 current_function_uses_pic_offset_table = 1;
11083 return pic_offset_table_rtx;
11086 /* Function to init struct machine_function.
11087 This will be called, via a pointer variable,
11088 from push_function_context. */
11090 static struct machine_function *
11091 rs6000_init_machine_status (void)
11093 return ggc_alloc_cleared (sizeof (machine_function));
11096 /* These macros test for integers and extract the low-order bits. */
11098 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
11099 && GET_MODE (X) == VOIDmode)
11101 #define INT_LOWPART(X) \
11102 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
11105 extract_MB (rtx op)
11108 unsigned long val = INT_LOWPART (op);
11110 /* If the high bit is zero, the value is the first 1 bit we find
11112 if ((val & 0x80000000) == 0)
11114 gcc_assert (val & 0xffffffff);
11117 while (((val <<= 1) & 0x80000000) == 0)
11122 /* If the high bit is set and the low bit is not, or the mask is all
11123 1's, the value is zero. */
11124 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
11127 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11130 while (((val >>= 1) & 1) != 0)
11137 extract_ME (rtx op)
11140 unsigned long val = INT_LOWPART (op);
11142 /* If the low bit is zero, the value is the first 1 bit we find from
11144 if ((val & 1) == 0)
11146 gcc_assert (val & 0xffffffff);
11149 while (((val >>= 1) & 1) == 0)
11155 /* If the low bit is set and the high bit is not, or the mask is all
11156 1's, the value is 31. */
11157 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
11160 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
11163 while (((val <<= 1) & 0x80000000) != 0)
11169 /* Locate some local-dynamic symbol still in use by this function
11170 so that we can print its name in some tls_ld pattern. */
11172 static const char *
11173 rs6000_get_some_local_dynamic_name (void)
11177 if (cfun->machine->some_ld_name)
11178 return cfun->machine->some_ld_name;
11180 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
11182 && for_each_rtx (&PATTERN (insn),
11183 rs6000_get_some_local_dynamic_name_1, 0))
11184 return cfun->machine->some_ld_name;
11186 gcc_unreachable ();
11189 /* Helper function for rs6000_get_some_local_dynamic_name. */
11192 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
11196 if (GET_CODE (x) == SYMBOL_REF)
11198 const char *str = XSTR (x, 0);
11199 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
11201 cfun->machine->some_ld_name = str;
11209 /* Write out a function code label. */
11212 rs6000_output_function_entry (FILE *file, const char *fname)
11214 if (fname[0] != '.')
11216 switch (DEFAULT_ABI)
11219 gcc_unreachable ();
11225 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
11234 RS6000_OUTPUT_BASENAME (file, fname);
11236 assemble_name (file, fname);
11239 /* Print an operand. Recognize special options, documented below. */
11242 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
11243 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
11245 #define SMALL_DATA_RELOC "sda21"
11246 #define SMALL_DATA_REG 0
11250 print_operand (FILE *file, rtx x, int code)
11254 unsigned HOST_WIDE_INT uval;
11259 /* Write out an instruction after the call which may be replaced
11260 with glue code by the loader. This depends on the AIX version. */
11261 asm_fprintf (file, RS6000_CALL_GLUE);
11264 /* %a is output_address. */
11267 /* If X is a constant integer whose low-order 5 bits are zero,
11268 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
11269 in the AIX assembler where "sri" with a zero shift count
11270 writes a trash instruction. */
11271 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
11278 /* If constant, low-order 16 bits of constant, unsigned.
11279 Otherwise, write normally. */
11281 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
11283 print_operand (file, x, 0);
11287 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
11288 for 64-bit mask direction. */
11289 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
11292 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
11296 /* X is a CR register. Print the number of the GT bit of the CR. */
11297 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11298 output_operand_lossage ("invalid %%E value");
11300 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
11304 /* Like 'J' but get to the GT bit only. */
11305 gcc_assert (GET_CODE (x) == REG);
11307 /* Bit 1 is GT bit. */
11308 i = 4 * (REGNO (x) - CR0_REGNO) + 1;
11310 /* Add one for shift count in rlinm for scc. */
11311 fprintf (file, "%d", i + 1);
11315 /* X is a CR register. Print the number of the EQ bit of the CR */
11316 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11317 output_operand_lossage ("invalid %%E value");
11319 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
11323 /* X is a CR register. Print the shift count needed to move it
11324 to the high-order four bits. */
11325 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11326 output_operand_lossage ("invalid %%f value");
11328 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
11332 /* Similar, but print the count for the rotate in the opposite
11334 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11335 output_operand_lossage ("invalid %%F value");
11337 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
11341 /* X is a constant integer. If it is negative, print "m",
11342 otherwise print "z". This is to make an aze or ame insn. */
11343 if (GET_CODE (x) != CONST_INT)
11344 output_operand_lossage ("invalid %%G value");
11345 else if (INTVAL (x) >= 0)
11352 /* If constant, output low-order five bits. Otherwise, write
11355 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
11357 print_operand (file, x, 0);
11361 /* If constant, output low-order six bits. Otherwise, write
11364 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
11366 print_operand (file, x, 0);
11370 /* Print `i' if this is a constant, else nothing. */
11376 /* Write the bit number in CCR for jump. */
11377 i = ccr_bit (x, 0);
11379 output_operand_lossage ("invalid %%j code");
11381 fprintf (file, "%d", i);
11385 /* Similar, but add one for shift count in rlinm for scc and pass
11386 scc flag to `ccr_bit'. */
11387 i = ccr_bit (x, 1);
11389 output_operand_lossage ("invalid %%J code");
11391 /* If we want bit 31, write a shift count of zero, not 32. */
11392 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11396 /* X must be a constant. Write the 1's complement of the
11399 output_operand_lossage ("invalid %%k value");
11401 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
11405 /* X must be a symbolic constant on ELF. Write an
11406 expression suitable for an 'addi' that adds in the low 16
11407 bits of the MEM. */
11408 if (GET_CODE (x) != CONST)
11410 print_operand_address (file, x);
11411 fputs ("@l", file);
11415 if (GET_CODE (XEXP (x, 0)) != PLUS
11416 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
11417 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
11418 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
11419 output_operand_lossage ("invalid %%K value");
11420 print_operand_address (file, XEXP (XEXP (x, 0), 0));
11421 fputs ("@l", file);
11422 /* For GNU as, there must be a non-alphanumeric character
11423 between 'l' and the number. The '-' is added by
11424 print_operand() already. */
11425 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
11427 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
11431 /* %l is output_asm_label. */
11434 /* Write second word of DImode or DFmode reference. Works on register
11435 or non-indexed memory only. */
11436 if (GET_CODE (x) == REG)
11437 fputs (reg_names[REGNO (x) + 1], file);
11438 else if (GET_CODE (x) == MEM)
11440 /* Handle possible auto-increment. Since it is pre-increment and
11441 we have already done it, we can just use an offset of word. */
11442 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11443 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11444 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11446 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11447 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
11450 output_address (XEXP (adjust_address_nv (x, SImode,
11454 if (small_data_operand (x, GET_MODE (x)))
11455 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11456 reg_names[SMALL_DATA_REG]);
11461 /* MB value for a mask operand. */
11462 if (! mask_operand (x, SImode))
11463 output_operand_lossage ("invalid %%m value");
11465 fprintf (file, "%d", extract_MB (x));
11469 /* ME value for a mask operand. */
11470 if (! mask_operand (x, SImode))
11471 output_operand_lossage ("invalid %%M value");
11473 fprintf (file, "%d", extract_ME (x));
11476 /* %n outputs the negative of its operand. */
11479 /* Write the number of elements in the vector times 4. */
11480 if (GET_CODE (x) != PARALLEL)
11481 output_operand_lossage ("invalid %%N value");
11483 fprintf (file, "%d", XVECLEN (x, 0) * 4);
11487 /* Similar, but subtract 1 first. */
11488 if (GET_CODE (x) != PARALLEL)
11489 output_operand_lossage ("invalid %%O value");
11491 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
11495 /* X is a CONST_INT that is a power of two. Output the logarithm. */
11497 || INT_LOWPART (x) < 0
11498 || (i = exact_log2 (INT_LOWPART (x))) < 0)
11499 output_operand_lossage ("invalid %%p value");
11501 fprintf (file, "%d", i);
11505 /* The operand must be an indirect memory reference. The result
11506 is the register name. */
11507 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
11508 || REGNO (XEXP (x, 0)) >= 32)
11509 output_operand_lossage ("invalid %%P value");
11511 fputs (reg_names[REGNO (XEXP (x, 0))], file);
11515 /* This outputs the logical code corresponding to a boolean
11516 expression. The expression may have one or both operands
11517 negated (if one, only the first one). For condition register
11518 logical operations, it will also treat the negated
11519 CR codes as NOTs, but not handle NOTs of them. */
11521 const char *const *t = 0;
11523 enum rtx_code code = GET_CODE (x);
11524 static const char * const tbl[3][3] = {
11525 { "and", "andc", "nor" },
11526 { "or", "orc", "nand" },
11527 { "xor", "eqv", "xor" } };
11531 else if (code == IOR)
11533 else if (code == XOR)
11536 output_operand_lossage ("invalid %%q value");
11538 if (GET_CODE (XEXP (x, 0)) != NOT)
11542 if (GET_CODE (XEXP (x, 1)) == NOT)
11560 /* X is a CR register. Print the mask for `mtcrf'. */
11561 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
11562 output_operand_lossage ("invalid %%R value");
11564 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
11568 /* Low 5 bits of 32 - value */
11570 output_operand_lossage ("invalid %%s value");
11572 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
11576 /* PowerPC64 mask position. All 0's is excluded.
11577 CONST_INT 32-bit mask is considered sign-extended so any
11578 transition must occur within the CONST_INT, not on the boundary. */
11579 if (! mask64_operand (x, DImode))
11580 output_operand_lossage ("invalid %%S value");
11582 uval = INT_LOWPART (x);
11584 if (uval & 1) /* Clear Left */
11586 #if HOST_BITS_PER_WIDE_INT > 64
11587 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11591 else /* Clear Right */
11594 #if HOST_BITS_PER_WIDE_INT > 64
11595 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
11601 gcc_assert (i >= 0);
11602 fprintf (file, "%d", i);
11606 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
11607 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
11609 /* Bit 3 is OV bit. */
11610 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
11612 /* If we want bit 31, write a shift count of zero, not 32. */
11613 fprintf (file, "%d", i == 31 ? 0 : i + 1);
11617 /* Print the symbolic name of a branch target register. */
11618 if (GET_CODE (x) != REG || (REGNO (x) != LR_REGNO
11619 && REGNO (x) != CTR_REGNO))
11620 output_operand_lossage ("invalid %%T value");
11621 else if (REGNO (x) == LR_REGNO)
11622 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
11624 fputs ("ctr", file);
11628 /* High-order 16 bits of constant for use in unsigned operand. */
11630 output_operand_lossage ("invalid %%u value");
11632 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11633 (INT_LOWPART (x) >> 16) & 0xffff);
11637 /* High-order 16 bits of constant for use in signed operand. */
11639 output_operand_lossage ("invalid %%v value");
11641 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
11642 (INT_LOWPART (x) >> 16) & 0xffff);
11646 /* Print `u' if this has an auto-increment or auto-decrement. */
11647 if (GET_CODE (x) == MEM
11648 && (GET_CODE (XEXP (x, 0)) == PRE_INC
11649 || GET_CODE (XEXP (x, 0)) == PRE_DEC
11650 || GET_CODE (XEXP (x, 0)) == PRE_MODIFY))
11655 /* Print the trap code for this operand. */
11656 switch (GET_CODE (x))
11659 fputs ("eq", file); /* 4 */
11662 fputs ("ne", file); /* 24 */
11665 fputs ("lt", file); /* 16 */
11668 fputs ("le", file); /* 20 */
11671 fputs ("gt", file); /* 8 */
11674 fputs ("ge", file); /* 12 */
11677 fputs ("llt", file); /* 2 */
11680 fputs ("lle", file); /* 6 */
11683 fputs ("lgt", file); /* 1 */
11686 fputs ("lge", file); /* 5 */
11689 gcc_unreachable ();
11694 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
11697 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
11698 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
11700 print_operand (file, x, 0);
11704 /* MB value for a PowerPC64 rldic operand. */
11705 val = (GET_CODE (x) == CONST_INT
11706 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
11711 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
11712 if ((val <<= 1) < 0)
11715 #if HOST_BITS_PER_WIDE_INT == 32
11716 if (GET_CODE (x) == CONST_INT && i >= 0)
11717 i += 32; /* zero-extend high-part was all 0's */
11718 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
11720 val = CONST_DOUBLE_LOW (x);
11726 for ( ; i < 64; i++)
11727 if ((val <<= 1) < 0)
11732 fprintf (file, "%d", i + 1);
11736 if (GET_CODE (x) == MEM
11737 && (legitimate_indexed_address_p (XEXP (x, 0), 0)
11738 || (GET_CODE (XEXP (x, 0)) == PRE_MODIFY
11739 && legitimate_indexed_address_p (XEXP (XEXP (x, 0), 1), 0))))
11744 /* Like 'L', for third word of TImode */
11745 if (GET_CODE (x) == REG)
11746 fputs (reg_names[REGNO (x) + 2], file);
11747 else if (GET_CODE (x) == MEM)
11749 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11750 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11751 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11752 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11753 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
11755 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
11756 if (small_data_operand (x, GET_MODE (x)))
11757 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11758 reg_names[SMALL_DATA_REG]);
11763 /* X is a SYMBOL_REF. Write out the name preceded by a
11764 period and without any trailing data in brackets. Used for function
11765 names. If we are configured for System V (or the embedded ABI) on
11766 the PowerPC, do not emit the period, since those systems do not use
11767 TOCs and the like. */
11768 gcc_assert (GET_CODE (x) == SYMBOL_REF);
11770 /* Mark the decl as referenced so that cgraph will output the
11772 if (SYMBOL_REF_DECL (x))
11773 mark_decl_referenced (SYMBOL_REF_DECL (x));
11775 /* For macho, check to see if we need a stub. */
11778 const char *name = XSTR (x, 0);
11780 if (MACHOPIC_INDIRECT
11781 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
11782 name = machopic_indirection_name (x, /*stub_p=*/true);
11784 assemble_name (file, name);
11786 else if (!DOT_SYMBOLS)
11787 assemble_name (file, XSTR (x, 0));
11789 rs6000_output_function_entry (file, XSTR (x, 0));
11793 /* Like 'L', for last word of TImode. */
11794 if (GET_CODE (x) == REG)
11795 fputs (reg_names[REGNO (x) + 3], file);
11796 else if (GET_CODE (x) == MEM)
11798 if (GET_CODE (XEXP (x, 0)) == PRE_INC
11799 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
11800 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11801 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11802 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
11804 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
11805 if (small_data_operand (x, GET_MODE (x)))
11806 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11807 reg_names[SMALL_DATA_REG]);
11811 /* Print AltiVec or SPE memory operand. */
11816 gcc_assert (GET_CODE (x) == MEM);
11820 /* Ugly hack because %y is overloaded. */
11821 if ((TARGET_SPE || TARGET_E500_DOUBLE)
11822 && (GET_MODE_SIZE (GET_MODE (x)) == 8
11823 || GET_MODE (x) == TFmode
11824 || GET_MODE (x) == TImode))
11826 /* Handle [reg]. */
11827 if (GET_CODE (tmp) == REG)
11829 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
11832 /* Handle [reg+UIMM]. */
11833 else if (GET_CODE (tmp) == PLUS &&
11834 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
11838 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
11840 x = INTVAL (XEXP (tmp, 1));
11841 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
11845 /* Fall through. Must be [reg+reg]. */
11848 && GET_CODE (tmp) == AND
11849 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
11850 && INTVAL (XEXP (tmp, 1)) == -16)
11851 tmp = XEXP (tmp, 0);
11852 if (GET_CODE (tmp) == REG)
11853 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
11856 gcc_assert (GET_CODE (tmp) == PLUS
11857 && REG_P (XEXP (tmp, 0))
11858 && REG_P (XEXP (tmp, 1)));
11860 if (REGNO (XEXP (tmp, 0)) == 0)
11861 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
11862 reg_names[ REGNO (XEXP (tmp, 0)) ]);
11864 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
11865 reg_names[ REGNO (XEXP (tmp, 1)) ]);
11871 if (GET_CODE (x) == REG)
11872 fprintf (file, "%s", reg_names[REGNO (x)]);
11873 else if (GET_CODE (x) == MEM)
11875 /* We need to handle PRE_INC and PRE_DEC here, since we need to
11876 know the width from the mode. */
11877 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
11878 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
11879 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11880 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
11881 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
11882 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
11883 else if (GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
11884 output_address (XEXP (XEXP (x, 0), 1));
11886 output_address (XEXP (x, 0));
11889 output_addr_const (file, x);
11893 assemble_name (file, rs6000_get_some_local_dynamic_name ());
11897 output_operand_lossage ("invalid %%xn code");
11901 /* Print the address of an operand. */
11904 print_operand_address (FILE *file, rtx x)
11906 if (GET_CODE (x) == REG)
11907 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
11908 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
11909 || GET_CODE (x) == LABEL_REF)
11911 output_addr_const (file, x);
11912 if (small_data_operand (x, GET_MODE (x)))
11913 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
11914 reg_names[SMALL_DATA_REG]);
11916 gcc_assert (!TARGET_TOC);
11918 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
11920 gcc_assert (REG_P (XEXP (x, 0)));
11921 if (REGNO (XEXP (x, 0)) == 0)
11922 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
11923 reg_names[ REGNO (XEXP (x, 0)) ]);
11925 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
11926 reg_names[ REGNO (XEXP (x, 1)) ]);
11928 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
11929 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
11930 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
11932 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11933 && CONSTANT_P (XEXP (x, 1)))
11935 output_addr_const (file, XEXP (x, 1));
11936 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11940 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
11941 && CONSTANT_P (XEXP (x, 1)))
11943 fprintf (file, "lo16(");
11944 output_addr_const (file, XEXP (x, 1));
11945 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
11948 else if (legitimate_constant_pool_address_p (x))
11950 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
11952 rtx contains_minus = XEXP (x, 1);
11956 /* Find the (minus (sym) (toc)) buried in X, and temporarily
11957 turn it into (sym) for output_addr_const. */
11958 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
11959 contains_minus = XEXP (contains_minus, 0);
11961 minus = XEXP (contains_minus, 0);
11962 symref = XEXP (minus, 0);
11963 XEXP (contains_minus, 0) = symref;
11968 name = XSTR (symref, 0);
11969 newname = alloca (strlen (name) + sizeof ("@toc"));
11970 strcpy (newname, name);
11971 strcat (newname, "@toc");
11972 XSTR (symref, 0) = newname;
11974 output_addr_const (file, XEXP (x, 1));
11976 XSTR (symref, 0) = name;
11977 XEXP (contains_minus, 0) = minus;
11980 output_addr_const (file, XEXP (x, 1));
11982 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
11985 gcc_unreachable ();
11988 /* Target hook for assembling integer objects. The PowerPC version has
11989 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
11990 is defined. It also needs to handle DI-mode objects on 64-bit
11994 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
11996 #ifdef RELOCATABLE_NEEDS_FIXUP
11997 /* Special handling for SI values. */
11998 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
12000 static int recurse = 0;
12002 /* For -mrelocatable, we mark all addresses that need to be fixed up
12003 in the .fixup section. */
12004 if (TARGET_RELOCATABLE
12005 && in_section != toc_section
12006 && in_section != text_section
12007 && !unlikely_text_section_p (in_section)
12009 && GET_CODE (x) != CONST_INT
12010 && GET_CODE (x) != CONST_DOUBLE
12016 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
12018 ASM_OUTPUT_LABEL (asm_out_file, buf);
12019 fprintf (asm_out_file, "\t.long\t(");
12020 output_addr_const (asm_out_file, x);
12021 fprintf (asm_out_file, ")@fixup\n");
12022 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
12023 ASM_OUTPUT_ALIGN (asm_out_file, 2);
12024 fprintf (asm_out_file, "\t.long\t");
12025 assemble_name (asm_out_file, buf);
12026 fprintf (asm_out_file, "\n\t.previous\n");
12030 /* Remove initial .'s to turn a -mcall-aixdesc function
12031 address into the address of the descriptor, not the function
12033 else if (GET_CODE (x) == SYMBOL_REF
12034 && XSTR (x, 0)[0] == '.'
12035 && DEFAULT_ABI == ABI_AIX)
12037 const char *name = XSTR (x, 0);
12038 while (*name == '.')
12041 fprintf (asm_out_file, "\t.long\t%s\n", name);
12045 #endif /* RELOCATABLE_NEEDS_FIXUP */
12046 return default_assemble_integer (x, size, aligned_p);
12049 #ifdef HAVE_GAS_HIDDEN
12050 /* Emit an assembler directive to set symbol visibility for DECL to
12051 VISIBILITY_TYPE. */
12054 rs6000_assemble_visibility (tree decl, int vis)
12056 /* Functions need to have their entry point symbol visibility set as
12057 well as their descriptor symbol visibility. */
12058 if (DEFAULT_ABI == ABI_AIX
12060 && TREE_CODE (decl) == FUNCTION_DECL)
12062 static const char * const visibility_types[] = {
12063 NULL, "internal", "hidden", "protected"
12066 const char *name, *type;
12068 name = ((* targetm.strip_name_encoding)
12069 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
12070 type = visibility_types[vis];
12072 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
12073 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
12076 default_assemble_visibility (decl, vis);
12081 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
12083 /* Reversal of FP compares takes care -- an ordered compare
12084 becomes an unordered compare and vice versa. */
12085 if (mode == CCFPmode
12086 && (!flag_finite_math_only
12087 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
12088 || code == UNEQ || code == LTGT))
12089 return reverse_condition_maybe_unordered (code);
12091 return reverse_condition (code);
12094 /* Generate a compare for CODE. Return a brand-new rtx that
12095 represents the result of the compare. */
12098 rs6000_generate_compare (enum rtx_code code)
12100 enum machine_mode comp_mode;
12101 rtx compare_result;
12103 if (rs6000_compare_fp_p)
12104 comp_mode = CCFPmode;
12105 else if (code == GTU || code == LTU
12106 || code == GEU || code == LEU)
12107 comp_mode = CCUNSmode;
12108 else if ((code == EQ || code == NE)
12109 && GET_CODE (rs6000_compare_op0) == SUBREG
12110 && GET_CODE (rs6000_compare_op1) == SUBREG
12111 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
12112 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
12113 /* These are unsigned values, perhaps there will be a later
12114 ordering compare that can be shared with this one.
12115 Unfortunately we cannot detect the signedness of the operands
12116 for non-subregs. */
12117 comp_mode = CCUNSmode;
12119 comp_mode = CCmode;
12121 /* First, the compare. */
12122 compare_result = gen_reg_rtx (comp_mode);
12124 /* E500 FP compare instructions on the GPRs. Yuck! */
12125 if ((!TARGET_FPRS && TARGET_HARD_FLOAT)
12126 && rs6000_compare_fp_p)
12128 rtx cmp, or_result, compare_result2;
12129 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
12131 if (op_mode == VOIDmode)
12132 op_mode = GET_MODE (rs6000_compare_op1);
12134 /* The E500 FP compare instructions toggle the GT bit (CR bit 1) only.
12135 This explains the following mess. */
12139 case EQ: case UNEQ: case NE: case LTGT:
12143 cmp = flag_unsafe_math_optimizations
12144 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
12145 rs6000_compare_op1)
12146 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
12147 rs6000_compare_op1);
12151 cmp = flag_unsafe_math_optimizations
12152 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
12153 rs6000_compare_op1)
12154 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
12155 rs6000_compare_op1);
12159 cmp = flag_unsafe_math_optimizations
12160 ? gen_tsttfeq_gpr (compare_result, rs6000_compare_op0,
12161 rs6000_compare_op1)
12162 : gen_cmptfeq_gpr (compare_result, rs6000_compare_op0,
12163 rs6000_compare_op1);
12167 gcc_unreachable ();
12171 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
12175 cmp = flag_unsafe_math_optimizations
12176 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
12177 rs6000_compare_op1)
12178 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
12179 rs6000_compare_op1);
12183 cmp = flag_unsafe_math_optimizations
12184 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
12185 rs6000_compare_op1)
12186 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
12187 rs6000_compare_op1);
12191 cmp = flag_unsafe_math_optimizations
12192 ? gen_tsttfgt_gpr (compare_result, rs6000_compare_op0,
12193 rs6000_compare_op1)
12194 : gen_cmptfgt_gpr (compare_result, rs6000_compare_op0,
12195 rs6000_compare_op1);
12199 gcc_unreachable ();
12203 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
12207 cmp = flag_unsafe_math_optimizations
12208 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
12209 rs6000_compare_op1)
12210 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
12211 rs6000_compare_op1);
12215 cmp = flag_unsafe_math_optimizations
12216 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
12217 rs6000_compare_op1)
12218 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
12219 rs6000_compare_op1);
12223 cmp = flag_unsafe_math_optimizations
12224 ? gen_tsttflt_gpr (compare_result, rs6000_compare_op0,
12225 rs6000_compare_op1)
12226 : gen_cmptflt_gpr (compare_result, rs6000_compare_op0,
12227 rs6000_compare_op1);
12231 gcc_unreachable ();
12235 gcc_unreachable ();
12238 /* Synthesize LE and GE from LT/GT || EQ. */
12239 if (code == LE || code == GE || code == LEU || code == GEU)
12245 case LE: code = LT; break;
12246 case GE: code = GT; break;
12247 case LEU: code = LT; break;
12248 case GEU: code = GT; break;
12249 default: gcc_unreachable ();
12252 compare_result2 = gen_reg_rtx (CCFPmode);
12258 cmp = flag_unsafe_math_optimizations
12259 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
12260 rs6000_compare_op1)
12261 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
12262 rs6000_compare_op1);
12266 cmp = flag_unsafe_math_optimizations
12267 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
12268 rs6000_compare_op1)
12269 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
12270 rs6000_compare_op1);
12274 cmp = flag_unsafe_math_optimizations
12275 ? gen_tsttfeq_gpr (compare_result2, rs6000_compare_op0,
12276 rs6000_compare_op1)
12277 : gen_cmptfeq_gpr (compare_result2, rs6000_compare_op0,
12278 rs6000_compare_op1);
12282 gcc_unreachable ();
12286 /* OR them together. */
12287 or_result = gen_reg_rtx (CCFPmode);
12288 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
12290 compare_result = or_result;
12295 if (code == NE || code == LTGT)
12305 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
12306 CLOBBERs to match cmptf_internal2 pattern. */
12307 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
12308 && GET_MODE (rs6000_compare_op0) == TFmode
12309 && !TARGET_IEEEQUAD
12310 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
12311 emit_insn (gen_rtx_PARALLEL (VOIDmode,
12313 gen_rtx_SET (VOIDmode,
12315 gen_rtx_COMPARE (comp_mode,
12316 rs6000_compare_op0,
12317 rs6000_compare_op1)),
12318 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12319 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12320 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12321 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12322 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12323 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12324 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
12325 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
12326 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
12327 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
12329 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
12330 comp_mode = CCEQmode;
12331 compare_result = gen_reg_rtx (CCEQmode);
12333 emit_insn (gen_stack_protect_testdi (compare_result,
12334 rs6000_compare_op0, op1));
12336 emit_insn (gen_stack_protect_testsi (compare_result,
12337 rs6000_compare_op0, op1));
12340 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
12341 gen_rtx_COMPARE (comp_mode,
12342 rs6000_compare_op0,
12343 rs6000_compare_op1)));
12346 /* Some kinds of FP comparisons need an OR operation;
12347 under flag_finite_math_only we don't bother. */
12348 if (rs6000_compare_fp_p
12349 && !flag_finite_math_only
12350 && !(TARGET_HARD_FLOAT && !TARGET_FPRS)
12351 && (code == LE || code == GE
12352 || code == UNEQ || code == LTGT
12353 || code == UNGT || code == UNLT))
12355 enum rtx_code or1, or2;
12356 rtx or1_rtx, or2_rtx, compare2_rtx;
12357 rtx or_result = gen_reg_rtx (CCEQmode);
12361 case LE: or1 = LT; or2 = EQ; break;
12362 case GE: or1 = GT; or2 = EQ; break;
12363 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
12364 case LTGT: or1 = LT; or2 = GT; break;
12365 case UNGT: or1 = UNORDERED; or2 = GT; break;
12366 case UNLT: or1 = UNORDERED; or2 = LT; break;
12367 default: gcc_unreachable ();
12369 validate_condition_mode (or1, comp_mode);
12370 validate_condition_mode (or2, comp_mode);
12371 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
12372 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
12373 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
12374 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
12376 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
12378 compare_result = or_result;
12382 validate_condition_mode (code, GET_MODE (compare_result));
12384 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
12388 /* Emit the RTL for an sCOND pattern. */
12391 rs6000_emit_sCOND (enum rtx_code code, rtx result)
12394 enum machine_mode op_mode;
12395 enum rtx_code cond_code;
12397 condition_rtx = rs6000_generate_compare (code);
12398 cond_code = GET_CODE (condition_rtx);
12400 if (rs6000_compare_fp_p
12401 && !TARGET_FPRS && TARGET_HARD_FLOAT)
12405 PUT_MODE (condition_rtx, SImode);
12406 t = XEXP (condition_rtx, 0);
12408 gcc_assert (cond_code == NE || cond_code == EQ);
12410 if (cond_code == NE)
12411 emit_insn (gen_e500_flip_gt_bit (t, t));
12413 emit_insn (gen_move_from_CR_gt_bit (result, t));
12417 if (cond_code == NE
12418 || cond_code == GE || cond_code == LE
12419 || cond_code == GEU || cond_code == LEU
12420 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
12422 rtx not_result = gen_reg_rtx (CCEQmode);
12423 rtx not_op, rev_cond_rtx;
12424 enum machine_mode cc_mode;
12426 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
12428 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
12429 SImode, XEXP (condition_rtx, 0), const0_rtx);
12430 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
12431 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
12432 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
12435 op_mode = GET_MODE (rs6000_compare_op0);
12436 if (op_mode == VOIDmode)
12437 op_mode = GET_MODE (rs6000_compare_op1);
12439 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
12441 PUT_MODE (condition_rtx, DImode);
12442 convert_move (result, condition_rtx, 0);
12446 PUT_MODE (condition_rtx, SImode);
12447 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
12451 /* Emit a branch of kind CODE to location LOC. */
12454 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
12456 rtx condition_rtx, loc_ref;
12458 condition_rtx = rs6000_generate_compare (code);
12459 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
12460 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
12461 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
12462 loc_ref, pc_rtx)));
12465 /* Return the string to output a conditional branch to LABEL, which is
12466 the operand number of the label, or -1 if the branch is really a
12467 conditional return.
12469 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
12470 condition code register and its mode specifies what kind of
12471 comparison we made.
12473 REVERSED is nonzero if we should reverse the sense of the comparison.
12475 INSN is the insn. */
12478 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
12480 static char string[64];
12481 enum rtx_code code = GET_CODE (op);
12482 rtx cc_reg = XEXP (op, 0);
12483 enum machine_mode mode = GET_MODE (cc_reg);
12484 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
12485 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
12486 int really_reversed = reversed ^ need_longbranch;
12492 validate_condition_mode (code, mode);
12494 /* Work out which way this really branches. We could use
12495 reverse_condition_maybe_unordered here always but this
12496 makes the resulting assembler clearer. */
12497 if (really_reversed)
12499 /* Reversal of FP compares takes care -- an ordered compare
12500 becomes an unordered compare and vice versa. */
12501 if (mode == CCFPmode)
12502 code = reverse_condition_maybe_unordered (code);
12504 code = reverse_condition (code);
12507 if ((!TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
12509 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
12514 /* Opposite of GT. */
12523 gcc_unreachable ();
12529 /* Not all of these are actually distinct opcodes, but
12530 we distinguish them for clarity of the resulting assembler. */
12531 case NE: case LTGT:
12532 ccode = "ne"; break;
12533 case EQ: case UNEQ:
12534 ccode = "eq"; break;
12536 ccode = "ge"; break;
12537 case GT: case GTU: case UNGT:
12538 ccode = "gt"; break;
12540 ccode = "le"; break;
12541 case LT: case LTU: case UNLT:
12542 ccode = "lt"; break;
12543 case UNORDERED: ccode = "un"; break;
12544 case ORDERED: ccode = "nu"; break;
12545 case UNGE: ccode = "nl"; break;
12546 case UNLE: ccode = "ng"; break;
12548 gcc_unreachable ();
12551 /* Maybe we have a guess as to how likely the branch is.
12552 The old mnemonics don't have a way to specify this information. */
12554 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
12555 if (note != NULL_RTX)
12557 /* PROB is the difference from 50%. */
12558 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
12560 /* Only hint for highly probable/improbable branches on newer
12561 cpus as static prediction overrides processor dynamic
12562 prediction. For older cpus we may as well always hint, but
12563 assume not taken for branches that are very close to 50% as a
12564 mispredicted taken branch is more expensive than a
12565 mispredicted not-taken branch. */
12566 if (rs6000_always_hint
12567 || (abs (prob) > REG_BR_PROB_BASE / 100 * 48
12568 && br_prob_note_reliable_p (note)))
12570 if (abs (prob) > REG_BR_PROB_BASE / 20
12571 && ((prob > 0) ^ need_longbranch))
12579 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
12581 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
12583 /* We need to escape any '%' characters in the reg_names string.
12584 Assume they'd only be the first character.... */
12585 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
12587 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
12591 /* If the branch distance was too far, we may have to use an
12592 unconditional branch to go the distance. */
12593 if (need_longbranch)
12594 s += sprintf (s, ",$+8\n\tb %s", label);
12596 s += sprintf (s, ",%s", label);
12602 /* Return the string to flip the GT bit on a CR. */
12604 output_e500_flip_gt_bit (rtx dst, rtx src)
12606 static char string[64];
12609 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
12610 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
12613 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
12614 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
12616 sprintf (string, "crnot %d,%d", a, b);
12620 /* Return insn index for the vector compare instruction for given CODE,
12621 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
12625 get_vec_cmp_insn (enum rtx_code code,
12626 enum machine_mode dest_mode,
12627 enum machine_mode op_mode)
12629 if (!TARGET_ALTIVEC)
12630 return INSN_NOT_AVAILABLE;
12635 if (dest_mode == V16QImode && op_mode == V16QImode)
12636 return UNSPEC_VCMPEQUB;
12637 if (dest_mode == V8HImode && op_mode == V8HImode)
12638 return UNSPEC_VCMPEQUH;
12639 if (dest_mode == V4SImode && op_mode == V4SImode)
12640 return UNSPEC_VCMPEQUW;
12641 if (dest_mode == V4SImode && op_mode == V4SFmode)
12642 return UNSPEC_VCMPEQFP;
12645 if (dest_mode == V4SImode && op_mode == V4SFmode)
12646 return UNSPEC_VCMPGEFP;
12648 if (dest_mode == V16QImode && op_mode == V16QImode)
12649 return UNSPEC_VCMPGTSB;
12650 if (dest_mode == V8HImode && op_mode == V8HImode)
12651 return UNSPEC_VCMPGTSH;
12652 if (dest_mode == V4SImode && op_mode == V4SImode)
12653 return UNSPEC_VCMPGTSW;
12654 if (dest_mode == V4SImode && op_mode == V4SFmode)
12655 return UNSPEC_VCMPGTFP;
12658 if (dest_mode == V16QImode && op_mode == V16QImode)
12659 return UNSPEC_VCMPGTUB;
12660 if (dest_mode == V8HImode && op_mode == V8HImode)
12661 return UNSPEC_VCMPGTUH;
12662 if (dest_mode == V4SImode && op_mode == V4SImode)
12663 return UNSPEC_VCMPGTUW;
12668 return INSN_NOT_AVAILABLE;
12671 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
12672 DMODE is expected destination mode. This is a recursive function. */
12675 rs6000_emit_vector_compare (enum rtx_code rcode,
12677 enum machine_mode dmode)
12681 enum machine_mode dest_mode;
12682 enum machine_mode op_mode = GET_MODE (op1);
12684 gcc_assert (TARGET_ALTIVEC);
12685 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
12687 /* Floating point vector compare instructions uses destination V4SImode.
12688 Move destination to appropriate mode later. */
12689 if (dmode == V4SFmode)
12690 dest_mode = V4SImode;
12694 mask = gen_reg_rtx (dest_mode);
12695 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12697 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
12699 bool swap_operands = false;
12700 bool try_again = false;
12705 swap_operands = true;
12710 swap_operands = true;
12718 /* Invert condition and try again.
12719 e.g., A != B becomes ~(A==B). */
12721 enum rtx_code rev_code;
12722 enum insn_code nor_code;
12725 rev_code = reverse_condition_maybe_unordered (rcode);
12726 eq_rtx = rs6000_emit_vector_compare (rev_code, op0, op1,
12729 nor_code = optab_handler (one_cmpl_optab, (int)dest_mode)->insn_code;
12730 gcc_assert (nor_code != CODE_FOR_nothing);
12731 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
12733 if (dmode != dest_mode)
12735 rtx temp = gen_reg_rtx (dest_mode);
12736 convert_move (temp, mask, 0);
12746 /* Try GT/GTU/LT/LTU OR EQ */
12749 enum insn_code ior_code;
12750 enum rtx_code new_code;
12771 gcc_unreachable ();
12774 c_rtx = rs6000_emit_vector_compare (new_code,
12775 op0, op1, dest_mode);
12776 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
12779 ior_code = optab_handler (ior_optab, (int)dest_mode)->insn_code;
12780 gcc_assert (ior_code != CODE_FOR_nothing);
12781 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
12782 if (dmode != dest_mode)
12784 rtx temp = gen_reg_rtx (dest_mode);
12785 convert_move (temp, mask, 0);
12792 gcc_unreachable ();
12797 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
12798 /* You only get two chances. */
12799 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
12811 emit_insn (gen_rtx_SET (VOIDmode, mask,
12812 gen_rtx_UNSPEC (dest_mode,
12813 gen_rtvec (2, op0, op1),
12815 if (dmode != dest_mode)
12817 rtx temp = gen_reg_rtx (dest_mode);
12818 convert_move (temp, mask, 0);
12824 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
12825 valid insn doesn exist for given mode. */
12828 get_vsel_insn (enum machine_mode mode)
12833 return UNSPEC_VSEL4SI;
12836 return UNSPEC_VSEL4SF;
12839 return UNSPEC_VSEL8HI;
12842 return UNSPEC_VSEL16QI;
12845 return INSN_NOT_AVAILABLE;
12848 return INSN_NOT_AVAILABLE;
12851 /* Emit vector select insn where DEST is destination using
12852 operands OP1, OP2 and MASK. */
12855 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
12858 enum machine_mode dest_mode = GET_MODE (dest);
12859 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
12861 temp = gen_reg_rtx (dest_mode);
12863 /* For each vector element, select op1 when mask is 1 otherwise
12865 t = gen_rtx_SET (VOIDmode, temp,
12866 gen_rtx_UNSPEC (dest_mode,
12867 gen_rtvec (3, op2, op1, mask),
12870 emit_move_insn (dest, temp);
12874 /* Emit vector conditional expression.
12875 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
12876 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
12879 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
12880 rtx cond, rtx cc_op0, rtx cc_op1)
12882 enum machine_mode dest_mode = GET_MODE (dest);
12883 enum rtx_code rcode = GET_CODE (cond);
12886 if (!TARGET_ALTIVEC)
12889 /* Get the vector mask for the given relational operations. */
12890 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
12892 rs6000_emit_vector_select (dest, op1, op2, mask);
12897 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
12898 operands of the last comparison is nonzero/true, FALSE_COND if it
12899 is zero/false. Return 0 if the hardware has no such operation. */
12902 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
12904 enum rtx_code code = GET_CODE (op);
12905 rtx op0 = rs6000_compare_op0;
12906 rtx op1 = rs6000_compare_op1;
12907 REAL_VALUE_TYPE c1;
12908 enum machine_mode compare_mode = GET_MODE (op0);
12909 enum machine_mode result_mode = GET_MODE (dest);
12911 bool is_against_zero;
12913 /* These modes should always match. */
12914 if (GET_MODE (op1) != compare_mode
12915 /* In the isel case however, we can use a compare immediate, so
12916 op1 may be a small constant. */
12917 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
12919 if (GET_MODE (true_cond) != result_mode)
12921 if (GET_MODE (false_cond) != result_mode)
12924 /* First, work out if the hardware can do this at all, or
12925 if it's too slow.... */
12926 if (! rs6000_compare_fp_p)
12929 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
12932 else if (TARGET_HARD_FLOAT && !TARGET_FPRS
12933 && SCALAR_FLOAT_MODE_P (compare_mode))
12936 is_against_zero = op1 == CONST0_RTX (compare_mode);
12938 /* A floating-point subtract might overflow, underflow, or produce
12939 an inexact result, thus changing the floating-point flags, so it
12940 can't be generated if we care about that. It's safe if one side
12941 of the construct is zero, since then no subtract will be
12943 if (SCALAR_FLOAT_MODE_P (compare_mode)
12944 && flag_trapping_math && ! is_against_zero)
12947 /* Eliminate half of the comparisons by switching operands, this
12948 makes the remaining code simpler. */
12949 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
12950 || code == LTGT || code == LT || code == UNLE)
12952 code = reverse_condition_maybe_unordered (code);
12954 true_cond = false_cond;
12958 /* UNEQ and LTGT take four instructions for a comparison with zero,
12959 it'll probably be faster to use a branch here too. */
12960 if (code == UNEQ && HONOR_NANS (compare_mode))
12963 if (GET_CODE (op1) == CONST_DOUBLE)
12964 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
12966 /* We're going to try to implement comparisons by performing
12967 a subtract, then comparing against zero. Unfortunately,
12968 Inf - Inf is NaN which is not zero, and so if we don't
12969 know that the operand is finite and the comparison
12970 would treat EQ different to UNORDERED, we can't do it. */
12971 if (HONOR_INFINITIES (compare_mode)
12972 && code != GT && code != UNGE
12973 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
12974 /* Constructs of the form (a OP b ? a : b) are safe. */
12975 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
12976 || (! rtx_equal_p (op0, true_cond)
12977 && ! rtx_equal_p (op1, true_cond))))
12980 /* At this point we know we can use fsel. */
12982 /* Reduce the comparison to a comparison against zero. */
12983 if (! is_against_zero)
12985 temp = gen_reg_rtx (compare_mode);
12986 emit_insn (gen_rtx_SET (VOIDmode, temp,
12987 gen_rtx_MINUS (compare_mode, op0, op1)));
12989 op1 = CONST0_RTX (compare_mode);
12992 /* If we don't care about NaNs we can reduce some of the comparisons
12993 down to faster ones. */
12994 if (! HONOR_NANS (compare_mode))
13000 true_cond = false_cond;
13013 /* Now, reduce everything down to a GE. */
13020 temp = gen_reg_rtx (compare_mode);
13021 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13026 temp = gen_reg_rtx (compare_mode);
13027 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
13032 temp = gen_reg_rtx (compare_mode);
13033 emit_insn (gen_rtx_SET (VOIDmode, temp,
13034 gen_rtx_NEG (compare_mode,
13035 gen_rtx_ABS (compare_mode, op0))));
13040 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
13041 temp = gen_reg_rtx (result_mode);
13042 emit_insn (gen_rtx_SET (VOIDmode, temp,
13043 gen_rtx_IF_THEN_ELSE (result_mode,
13044 gen_rtx_GE (VOIDmode,
13046 true_cond, false_cond)));
13047 false_cond = true_cond;
13050 temp = gen_reg_rtx (compare_mode);
13051 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13056 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
13057 temp = gen_reg_rtx (result_mode);
13058 emit_insn (gen_rtx_SET (VOIDmode, temp,
13059 gen_rtx_IF_THEN_ELSE (result_mode,
13060 gen_rtx_GE (VOIDmode,
13062 true_cond, false_cond)));
13063 true_cond = false_cond;
13066 temp = gen_reg_rtx (compare_mode);
13067 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
13072 gcc_unreachable ();
13075 emit_insn (gen_rtx_SET (VOIDmode, dest,
13076 gen_rtx_IF_THEN_ELSE (result_mode,
13077 gen_rtx_GE (VOIDmode,
13079 true_cond, false_cond)));
13083 /* Same as above, but for ints (isel). */
13086 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
13088 rtx condition_rtx, cr;
13090 /* All isel implementations thus far are 32-bits. */
13091 if (GET_MODE (rs6000_compare_op0) != SImode)
13094 /* We still have to do the compare, because isel doesn't do a
13095 compare, it just looks at the CRx bits set by a previous compare
13097 condition_rtx = rs6000_generate_compare (GET_CODE (op));
13098 cr = XEXP (condition_rtx, 0);
13100 if (GET_MODE (cr) == CCmode)
13101 emit_insn (gen_isel_signed (dest, condition_rtx,
13102 true_cond, false_cond, cr));
13104 emit_insn (gen_isel_unsigned (dest, condition_rtx,
13105 true_cond, false_cond, cr));
13111 output_isel (rtx *operands)
13113 enum rtx_code code;
13115 code = GET_CODE (operands[1]);
13116 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
13118 PUT_CODE (operands[1], reverse_condition (code));
13119 return "isel %0,%3,%2,%j1";
13122 return "isel %0,%2,%3,%j1";
13126 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
13128 enum machine_mode mode = GET_MODE (op0);
13132 if (code == SMAX || code == SMIN)
13137 if (code == SMAX || code == UMAX)
13138 target = emit_conditional_move (dest, c, op0, op1, mode,
13139 op0, op1, mode, 0);
13141 target = emit_conditional_move (dest, c, op0, op1, mode,
13142 op1, op0, mode, 0);
13143 gcc_assert (target);
13144 if (target != dest)
13145 emit_move_insn (dest, target);
13148 /* Emit instructions to perform a load-reserved/store-conditional operation.
13149 The operation performed is an atomic
13150 (set M (CODE:MODE M OP))
13151 If not NULL, BEFORE is atomically set to M before the operation, and
13152 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
13153 If SYNC_P then a memory barrier is emitted before the operation.
13154 Either OP or M may be wrapped in a NOT operation. */
13157 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
13158 rtx m, rtx op, rtx before_param, rtx after_param,
13161 enum machine_mode used_mode;
13162 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
13165 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13166 rtx shift = NULL_RTX;
13169 emit_insn (gen_memory_barrier ());
13171 if (GET_CODE (m) == NOT)
13172 used_m = XEXP (m, 0);
13176 /* If this is smaller than SImode, we'll have to use SImode with
13178 if (mode == QImode || mode == HImode)
13182 if (MEM_ALIGN (used_m) >= 32)
13185 if (BYTES_BIG_ENDIAN)
13186 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
13188 shift = GEN_INT (ishift);
13189 used_m = change_address (used_m, SImode, 0);
13193 rtx addrSI, aligned_addr;
13194 int shift_mask = mode == QImode ? 0x18 : 0x10;
13196 addrSI = gen_lowpart_common (SImode,
13197 force_reg (Pmode, XEXP (used_m, 0)));
13198 addrSI = force_reg (SImode, addrSI);
13199 shift = gen_reg_rtx (SImode);
13201 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13202 GEN_INT (shift_mask)));
13203 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13205 aligned_addr = expand_binop (Pmode, and_optab,
13207 GEN_INT (-4), NULL_RTX,
13208 1, OPTAB_LIB_WIDEN);
13209 used_m = change_address (used_m, SImode, aligned_addr);
13210 set_mem_align (used_m, 32);
13212 /* It's safe to keep the old alias set of USED_M, because
13213 the operation is atomic and only affects the original
13215 if (GET_CODE (m) == NOT)
13216 m = gen_rtx_NOT (SImode, used_m);
13220 if (GET_CODE (op) == NOT)
13222 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
13223 oldop = gen_rtx_NOT (SImode, oldop);
13226 oldop = lowpart_subreg (SImode, op, mode);
13232 newop = expand_binop (SImode, and_optab,
13233 oldop, GEN_INT (imask), NULL_RTX,
13234 1, OPTAB_LIB_WIDEN);
13235 emit_insn (gen_ashlsi3 (newop, newop, shift));
13239 newop = expand_binop (SImode, ior_optab,
13240 oldop, GEN_INT (~imask), NULL_RTX,
13241 1, OPTAB_LIB_WIDEN);
13242 emit_insn (gen_rotlsi3 (newop, newop, shift));
13250 newop = expand_binop (SImode, and_optab,
13251 oldop, GEN_INT (imask), NULL_RTX,
13252 1, OPTAB_LIB_WIDEN);
13253 emit_insn (gen_ashlsi3 (newop, newop, shift));
13255 mask = gen_reg_rtx (SImode);
13256 emit_move_insn (mask, GEN_INT (imask));
13257 emit_insn (gen_ashlsi3 (mask, mask, shift));
13260 newop = gen_rtx_PLUS (SImode, m, newop);
13262 newop = gen_rtx_MINUS (SImode, m, newop);
13263 newop = gen_rtx_AND (SImode, newop, mask);
13264 newop = gen_rtx_IOR (SImode, newop,
13265 gen_rtx_AND (SImode,
13266 gen_rtx_NOT (SImode, mask),
13272 gcc_unreachable ();
13275 if (GET_CODE (m) == NOT)
13279 mask = gen_reg_rtx (SImode);
13280 emit_move_insn (mask, GEN_INT (imask));
13281 emit_insn (gen_ashlsi3 (mask, mask, shift));
13283 xorm = gen_rtx_XOR (SImode, used_m, mask);
13284 /* Depending on the value of 'op', the XOR or the operation might
13285 be able to be simplified away. */
13286 newop = simplify_gen_binary (code, SImode, xorm, newop);
13289 used_mode = SImode;
13290 before = gen_reg_rtx (used_mode);
13291 after = gen_reg_rtx (used_mode);
13296 before = before_param;
13297 after = after_param;
13299 if (before == NULL_RTX)
13300 before = gen_reg_rtx (used_mode);
13301 if (after == NULL_RTX)
13302 after = gen_reg_rtx (used_mode);
13305 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
13306 && used_mode != mode)
13307 the_op = op; /* Computed above. */
13308 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
13309 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
13311 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
13313 set_after = gen_rtx_SET (VOIDmode, after, the_op);
13314 set_before = gen_rtx_SET (VOIDmode, before, used_m);
13315 set_atomic = gen_rtx_SET (VOIDmode, used_m,
13316 gen_rtx_UNSPEC (used_mode,
13317 gen_rtvec (1, the_op),
13319 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
13321 if ((code == PLUS || code == MINUS) && used_mode != mode)
13322 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
13323 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
13325 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
13326 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
13328 /* Shift and mask the return values properly. */
13329 if (used_mode != mode && before_param)
13331 emit_insn (gen_lshrsi3 (before, before, shift));
13332 convert_move (before_param, before, 1);
13335 if (used_mode != mode && after_param)
13337 emit_insn (gen_lshrsi3 (after, after, shift));
13338 convert_move (after_param, after, 1);
13341 /* The previous sequence will end with a branch that's dependent on
13342 the conditional store, so placing an isync will ensure that no
13343 other instructions (especially, no load or store instructions)
13344 can start before the atomic operation completes. */
13346 emit_insn (gen_isync ());
13349 /* A subroutine of the atomic operation splitters. Jump to LABEL if
13350 COND is true. Mark the jump as unlikely to be taken. */
13353 emit_unlikely_jump (rtx cond, rtx label)
13355 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
13358 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
13359 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
13360 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
13363 /* A subroutine of the atomic operation splitters. Emit a load-locked
13364 instruction in MODE. */
13367 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
13369 rtx (*fn) (rtx, rtx) = NULL;
13370 if (mode == SImode)
13371 fn = gen_load_locked_si;
13372 else if (mode == DImode)
13373 fn = gen_load_locked_di;
13374 emit_insn (fn (reg, mem));
13377 /* A subroutine of the atomic operation splitters. Emit a store-conditional
13378 instruction in MODE. */
13381 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
13383 rtx (*fn) (rtx, rtx, rtx) = NULL;
13384 if (mode == SImode)
13385 fn = gen_store_conditional_si;
13386 else if (mode == DImode)
13387 fn = gen_store_conditional_di;
13389 /* Emit sync before stwcx. to address PPC405 Erratum. */
13390 if (PPC405_ERRATUM77)
13391 emit_insn (gen_memory_barrier ());
13393 emit_insn (fn (res, mem, val));
13396 /* Expand an atomic fetch-and-operate pattern. CODE is the binary operation
13397 to perform. MEM is the memory on which to operate. VAL is the second
13398 operand of the binary operator. BEFORE and AFTER are optional locations to
13399 return the value of MEM either before of after the operation. SCRATCH is
13400 a scratch register. */
13403 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
13404 rtx before, rtx after, rtx scratch)
13406 enum machine_mode mode = GET_MODE (mem);
13407 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13409 emit_insn (gen_memory_barrier ());
13411 label = gen_label_rtx ();
13412 emit_label (label);
13413 label = gen_rtx_LABEL_REF (VOIDmode, label);
13415 if (before == NULL_RTX)
13417 emit_load_locked (mode, before, mem);
13420 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
13421 else if (code == AND)
13422 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
13424 x = gen_rtx_fmt_ee (code, mode, before, val);
13426 if (after != NULL_RTX)
13427 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
13428 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
13430 emit_store_conditional (mode, cond, mem, scratch);
13432 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13433 emit_unlikely_jump (x, label);
13435 emit_insn (gen_isync ());
13438 /* Expand an atomic compare and swap operation. MEM is the memory on which
13439 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
13440 value to be stored. SCRATCH is a scratch GPR. */
13443 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
13446 enum machine_mode mode = GET_MODE (mem);
13447 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13449 emit_insn (gen_memory_barrier ());
13451 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13452 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13453 emit_label (XEXP (label1, 0));
13455 emit_load_locked (mode, retval, mem);
13457 x = gen_rtx_COMPARE (CCmode, retval, oldval);
13458 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13460 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13461 emit_unlikely_jump (x, label2);
13463 emit_move_insn (scratch, newval);
13464 emit_store_conditional (mode, cond, mem, scratch);
13466 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13467 emit_unlikely_jump (x, label1);
13469 emit_insn (gen_isync ());
13470 emit_label (XEXP (label2, 0));
13473 /* Expand an atomic test and set operation. MEM is the memory on which
13474 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
13477 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
13479 enum machine_mode mode = GET_MODE (mem);
13480 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13482 emit_insn (gen_memory_barrier ());
13484 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13485 emit_label (XEXP (label, 0));
13487 emit_load_locked (mode, retval, mem);
13488 emit_move_insn (scratch, val);
13489 emit_store_conditional (mode, cond, mem, scratch);
13491 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13492 emit_unlikely_jump (x, label);
13494 emit_insn (gen_isync ());
13498 rs6000_expand_compare_and_swapqhi (rtx dst, rtx mem, rtx oldval, rtx newval)
13500 enum machine_mode mode = GET_MODE (mem);
13501 rtx addrSI, align, wdst, shift, mask;
13502 HOST_WIDE_INT shift_mask = mode == QImode ? 0x18 : 0x10;
13503 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
13505 /* Shift amount for subword relative to aligned word. */
13506 addrSI = force_reg (SImode, gen_lowpart_common (SImode, XEXP (mem, 0)));
13507 shift = gen_reg_rtx (SImode);
13508 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
13509 GEN_INT (shift_mask)));
13510 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
13512 /* Shift and mask old value into position within word. */
13513 oldval = convert_modes (SImode, mode, oldval, 1);
13514 oldval = expand_binop (SImode, and_optab,
13515 oldval, GEN_INT (imask), NULL_RTX,
13516 1, OPTAB_LIB_WIDEN);
13517 emit_insn (gen_ashlsi3 (oldval, oldval, shift));
13519 /* Shift and mask new value into position within word. */
13520 newval = convert_modes (SImode, mode, newval, 1);
13521 newval = expand_binop (SImode, and_optab,
13522 newval, GEN_INT (imask), NULL_RTX,
13523 1, OPTAB_LIB_WIDEN);
13524 emit_insn (gen_ashlsi3 (newval, newval, shift));
13526 /* Mask for insertion. */
13527 mask = gen_reg_rtx (SImode);
13528 emit_move_insn (mask, GEN_INT (imask));
13529 emit_insn (gen_ashlsi3 (mask, mask, shift));
13531 /* Address of aligned word containing subword. */
13532 align = expand_binop (Pmode, and_optab, XEXP (mem, 0), GEN_INT (-4),
13533 NULL_RTX, 1, OPTAB_LIB_WIDEN);
13534 mem = change_address (mem, SImode, align);
13535 set_mem_align (mem, 32);
13536 MEM_VOLATILE_P (mem) = 1;
13538 wdst = gen_reg_rtx (SImode);
13539 emit_insn (gen_sync_compare_and_swapqhi_internal (wdst, mask,
13540 oldval, newval, mem));
13542 emit_move_insn (dst, gen_lowpart (mode, wdst));
13546 rs6000_split_compare_and_swapqhi (rtx dest, rtx mask,
13547 rtx oldval, rtx newval, rtx mem,
13550 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
13552 emit_insn (gen_memory_barrier ());
13553 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13554 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
13555 emit_label (XEXP (label1, 0));
13557 emit_load_locked (SImode, scratch, mem);
13559 /* Mask subword within loaded value for comparison with oldval.
13560 Use UNSPEC_AND to avoid clobber.*/
13561 emit_insn (gen_rtx_SET (SImode, dest,
13562 gen_rtx_UNSPEC (SImode,
13563 gen_rtvec (2, scratch, mask),
13566 x = gen_rtx_COMPARE (CCmode, dest, oldval);
13567 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
13569 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13570 emit_unlikely_jump (x, label2);
13572 /* Clear subword within loaded value for insertion of new value. */
13573 emit_insn (gen_rtx_SET (SImode, scratch,
13574 gen_rtx_AND (SImode,
13575 gen_rtx_NOT (SImode, mask), scratch)));
13576 emit_insn (gen_iorsi3 (scratch, scratch, newval));
13577 emit_store_conditional (SImode, cond, mem, scratch);
13579 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
13580 emit_unlikely_jump (x, label1);
13582 emit_insn (gen_isync ());
13583 emit_label (XEXP (label2, 0));
13587 /* Emit instructions to move SRC to DST. Called by splitters for
13588 multi-register moves. It will emit at most one instruction for
13589 each register that is accessed; that is, it won't emit li/lis pairs
13590 (or equivalent for 64-bit code). One of SRC or DST must be a hard
13594 rs6000_split_multireg_move (rtx dst, rtx src)
13596 /* The register number of the first register being moved. */
13598 /* The mode that is to be moved. */
13599 enum machine_mode mode;
13600 /* The mode that the move is being done in, and its size. */
13601 enum machine_mode reg_mode;
13603 /* The number of registers that will be moved. */
13606 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
13607 mode = GET_MODE (dst);
13608 nregs = hard_regno_nregs[reg][mode];
13609 if (FP_REGNO_P (reg))
13610 reg_mode = DECIMAL_FLOAT_MODE_P (mode) ? DDmode : DFmode;
13611 else if (ALTIVEC_REGNO_P (reg))
13612 reg_mode = V16QImode;
13613 else if (TARGET_E500_DOUBLE && mode == TFmode)
13616 reg_mode = word_mode;
13617 reg_mode_size = GET_MODE_SIZE (reg_mode);
13619 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
13621 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
13623 /* Move register range backwards, if we might have destructive
13626 for (i = nregs - 1; i >= 0; i--)
13627 emit_insn (gen_rtx_SET (VOIDmode,
13628 simplify_gen_subreg (reg_mode, dst, mode,
13629 i * reg_mode_size),
13630 simplify_gen_subreg (reg_mode, src, mode,
13631 i * reg_mode_size)));
13637 bool used_update = false;
13639 if (MEM_P (src) && INT_REGNO_P (reg))
13643 if (GET_CODE (XEXP (src, 0)) == PRE_INC
13644 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
13647 breg = XEXP (XEXP (src, 0), 0);
13648 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
13649 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
13650 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
13651 emit_insn (TARGET_32BIT
13652 ? gen_addsi3 (breg, breg, delta_rtx)
13653 : gen_adddi3 (breg, breg, delta_rtx));
13654 src = replace_equiv_address (src, breg);
13656 else if (! rs6000_offsettable_memref_p (src))
13659 basereg = gen_rtx_REG (Pmode, reg);
13660 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
13661 src = replace_equiv_address (src, basereg);
13664 breg = XEXP (src, 0);
13665 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
13666 breg = XEXP (breg, 0);
13668 /* If the base register we are using to address memory is
13669 also a destination reg, then change that register last. */
13671 && REGNO (breg) >= REGNO (dst)
13672 && REGNO (breg) < REGNO (dst) + nregs)
13673 j = REGNO (breg) - REGNO (dst);
13676 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
13680 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
13681 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
13684 breg = XEXP (XEXP (dst, 0), 0);
13685 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
13686 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
13687 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
13689 /* We have to update the breg before doing the store.
13690 Use store with update, if available. */
13694 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
13695 emit_insn (TARGET_32BIT
13696 ? (TARGET_POWERPC64
13697 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
13698 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
13699 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
13700 used_update = true;
13703 emit_insn (TARGET_32BIT
13704 ? gen_addsi3 (breg, breg, delta_rtx)
13705 : gen_adddi3 (breg, breg, delta_rtx));
13706 dst = replace_equiv_address (dst, breg);
13709 gcc_assert (rs6000_offsettable_memref_p (dst));
13712 for (i = 0; i < nregs; i++)
13714 /* Calculate index to next subword. */
13719 /* If compiler already emitted move of first word by
13720 store with update, no need to do anything. */
13721 if (j == 0 && used_update)
13724 emit_insn (gen_rtx_SET (VOIDmode,
13725 simplify_gen_subreg (reg_mode, dst, mode,
13726 j * reg_mode_size),
13727 simplify_gen_subreg (reg_mode, src, mode,
13728 j * reg_mode_size)));
13734 /* This page contains routines that are used to determine what the
13735 function prologue and epilogue code will do and write them out. */
13737 /* Return the first fixed-point register that is required to be
13738 saved. 32 if none. */
13741 first_reg_to_save (void)
13745 /* Find lowest numbered live register. */
13746 for (first_reg = 13; first_reg <= 31; first_reg++)
13747 if (df_regs_ever_live_p (first_reg)
13748 && (! call_used_regs[first_reg]
13749 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
13750 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
13751 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
13752 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
13757 && current_function_uses_pic_offset_table
13758 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
13759 return RS6000_PIC_OFFSET_TABLE_REGNUM;
13765 /* Similar, for FP regs. */
13768 first_fp_reg_to_save (void)
13772 /* Find lowest numbered live register. */
13773 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
13774 if (df_regs_ever_live_p (first_reg))
13780 /* Similar, for AltiVec regs. */
13783 first_altivec_reg_to_save (void)
13787 /* Stack frame remains as is unless we are in AltiVec ABI. */
13788 if (! TARGET_ALTIVEC_ABI)
13789 return LAST_ALTIVEC_REGNO + 1;
13791 /* On Darwin, the unwind routines are compiled without
13792 TARGET_ALTIVEC, and use save_world to save/restore the
13793 altivec registers when necessary. */
13794 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13795 && ! TARGET_ALTIVEC)
13796 return FIRST_ALTIVEC_REGNO + 20;
13798 /* Find lowest numbered live register. */
13799 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
13800 if (df_regs_ever_live_p (i))
13806 /* Return a 32-bit mask of the AltiVec registers we need to set in
13807 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
13808 the 32-bit word is 0. */
13810 static unsigned int
13811 compute_vrsave_mask (void)
13813 unsigned int i, mask = 0;
13815 /* On Darwin, the unwind routines are compiled without
13816 TARGET_ALTIVEC, and use save_world to save/restore the
13817 call-saved altivec registers when necessary. */
13818 if (DEFAULT_ABI == ABI_DARWIN && current_function_calls_eh_return
13819 && ! TARGET_ALTIVEC)
13822 /* First, find out if we use _any_ altivec registers. */
13823 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13824 if (df_regs_ever_live_p (i))
13825 mask |= ALTIVEC_REG_BIT (i);
13830 /* Next, remove the argument registers from the set. These must
13831 be in the VRSAVE mask set by the caller, so we don't need to add
13832 them in again. More importantly, the mask we compute here is
13833 used to generate CLOBBERs in the set_vrsave insn, and we do not
13834 wish the argument registers to die. */
13835 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
13836 mask &= ~ALTIVEC_REG_BIT (i);
13838 /* Similarly, remove the return value from the set. */
13841 diddle_return_value (is_altivec_return_reg, &yes);
13843 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
13849 /* For a very restricted set of circumstances, we can cut down the
13850 size of prologues/epilogues by calling our own save/restore-the-world
13854 compute_save_world_info (rs6000_stack_t *info_ptr)
13856 info_ptr->world_save_p = 1;
13857 info_ptr->world_save_p
13858 = (WORLD_SAVE_P (info_ptr)
13859 && DEFAULT_ABI == ABI_DARWIN
13860 && ! (current_function_calls_setjmp && flag_exceptions)
13861 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
13862 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
13863 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
13864 && info_ptr->cr_save_p);
13866 /* This will not work in conjunction with sibcalls. Make sure there
13867 are none. (This check is expensive, but seldom executed.) */
13868 if (WORLD_SAVE_P (info_ptr))
13871 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
13872 if ( GET_CODE (insn) == CALL_INSN
13873 && SIBLING_CALL_P (insn))
13875 info_ptr->world_save_p = 0;
13880 if (WORLD_SAVE_P (info_ptr))
13882 /* Even if we're not touching VRsave, make sure there's room on the
13883 stack for it, if it looks like we're calling SAVE_WORLD, which
13884 will attempt to save it. */
13885 info_ptr->vrsave_size = 4;
13887 /* "Save" the VRsave register too if we're saving the world. */
13888 if (info_ptr->vrsave_mask == 0)
13889 info_ptr->vrsave_mask = compute_vrsave_mask ();
13891 /* Because the Darwin register save/restore routines only handle
13892 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
13894 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
13895 && (info_ptr->first_altivec_reg_save
13896 >= FIRST_SAVED_ALTIVEC_REGNO));
13903 is_altivec_return_reg (rtx reg, void *xyes)
13905 bool *yes = (bool *) xyes;
13906 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
13911 /* Calculate the stack information for the current function. This is
13912 complicated by having two separate calling sequences, the AIX calling
13913 sequence and the V.4 calling sequence.
13915 AIX (and Darwin/Mac OS X) stack frames look like:
13917 SP----> +---------------------------------------+
13918 | back chain to caller | 0 0
13919 +---------------------------------------+
13920 | saved CR | 4 8 (8-11)
13921 +---------------------------------------+
13923 +---------------------------------------+
13924 | reserved for compilers | 12 24
13925 +---------------------------------------+
13926 | reserved for binders | 16 32
13927 +---------------------------------------+
13928 | saved TOC pointer | 20 40
13929 +---------------------------------------+
13930 | Parameter save area (P) | 24 48
13931 +---------------------------------------+
13932 | Alloca space (A) | 24+P etc.
13933 +---------------------------------------+
13934 | Local variable space (L) | 24+P+A
13935 +---------------------------------------+
13936 | Float/int conversion temporary (X) | 24+P+A+L
13937 +---------------------------------------+
13938 | Save area for AltiVec registers (W) | 24+P+A+L+X
13939 +---------------------------------------+
13940 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
13941 +---------------------------------------+
13942 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
13943 +---------------------------------------+
13944 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
13945 +---------------------------------------+
13946 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
13947 +---------------------------------------+
13948 old SP->| back chain to caller's caller |
13949 +---------------------------------------+
13951 The required alignment for AIX configurations is two words (i.e., 8
13955 V.4 stack frames look like:
13957 SP----> +---------------------------------------+
13958 | back chain to caller | 0
13959 +---------------------------------------+
13960 | caller's saved LR | 4
13961 +---------------------------------------+
13962 | Parameter save area (P) | 8
13963 +---------------------------------------+
13964 | Alloca space (A) | 8+P
13965 +---------------------------------------+
13966 | Varargs save area (V) | 8+P+A
13967 +---------------------------------------+
13968 | Local variable space (L) | 8+P+A+V
13969 +---------------------------------------+
13970 | Float/int conversion temporary (X) | 8+P+A+V+L
13971 +---------------------------------------+
13972 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
13973 +---------------------------------------+
13974 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
13975 +---------------------------------------+
13976 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
13977 +---------------------------------------+
13978 | SPE: area for 64-bit GP registers |
13979 +---------------------------------------+
13980 | SPE alignment padding |
13981 +---------------------------------------+
13982 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
13983 +---------------------------------------+
13984 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
13985 +---------------------------------------+
13986 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
13987 +---------------------------------------+
13988 old SP->| back chain to caller's caller |
13989 +---------------------------------------+
13991 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
13992 given. (But note below and in sysv4.h that we require only 8 and
13993 may round up the size of our stack frame anyways. The historical
13994 reason is early versions of powerpc-linux which didn't properly
13995 align the stack at program startup. A happy side-effect is that
13996 -mno-eabi libraries can be used with -meabi programs.)
13998 The EABI configuration defaults to the V.4 layout. However,
13999 the stack alignment requirements may differ. If -mno-eabi is not
14000 given, the required stack alignment is 8 bytes; if -mno-eabi is
14001 given, the required alignment is 16 bytes. (But see V.4 comment
14004 #ifndef ABI_STACK_BOUNDARY
14005 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
14008 static rs6000_stack_t *
14009 rs6000_stack_info (void)
14011 static rs6000_stack_t info;
14012 rs6000_stack_t *info_ptr = &info;
14013 int reg_size = TARGET_32BIT ? 4 : 8;
14017 HOST_WIDE_INT non_fixed_size;
14019 memset (&info, 0, sizeof (info));
14023 /* Cache value so we don't rescan instruction chain over and over. */
14024 if (cfun->machine->insn_chain_scanned_p == 0)
14025 cfun->machine->insn_chain_scanned_p
14026 = spe_func_has_64bit_regs_p () + 1;
14027 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
14030 /* Select which calling sequence. */
14031 info_ptr->abi = DEFAULT_ABI;
14033 /* Calculate which registers need to be saved & save area size. */
14034 info_ptr->first_gp_reg_save = first_reg_to_save ();
14035 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
14036 even if it currently looks like we won't. Reload may need it to
14037 get at a constant; if so, it will have already created a constant
14038 pool entry for it. */
14039 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
14040 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
14041 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
14042 && current_function_uses_const_pool
14043 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
14044 first_gp = RS6000_PIC_OFFSET_TABLE_REGNUM;
14046 first_gp = info_ptr->first_gp_reg_save;
14048 info_ptr->gp_size = reg_size * (32 - first_gp);
14050 /* For the SPE, we have an additional upper 32-bits on each GPR.
14051 Ideally we should save the entire 64-bits only when the upper
14052 half is used in SIMD instructions. Since we only record
14053 registers live (not the size they are used in), this proves
14054 difficult because we'd have to traverse the instruction chain at
14055 the right time, taking reload into account. This is a real pain,
14056 so we opt to save the GPRs in 64-bits always if but one register
14057 gets used in 64-bits. Otherwise, all the registers in the frame
14058 get saved in 32-bits.
14060 So... since when we save all GPRs (except the SP) in 64-bits, the
14061 traditional GP save area will be empty. */
14062 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14063 info_ptr->gp_size = 0;
14065 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
14066 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
14068 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
14069 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
14070 - info_ptr->first_altivec_reg_save);
14072 /* Does this function call anything? */
14073 info_ptr->calls_p = (! current_function_is_leaf
14074 || cfun->machine->ra_needs_full_frame);
14076 /* Determine if we need to save the link register. */
14077 if ((DEFAULT_ABI == ABI_AIX
14078 && current_function_profile
14079 && !TARGET_PROFILE_KERNEL)
14080 #ifdef TARGET_RELOCATABLE
14081 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
14083 || (info_ptr->first_fp_reg_save != 64
14084 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
14085 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
14086 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
14087 || info_ptr->calls_p
14088 || rs6000_ra_ever_killed ())
14090 info_ptr->lr_save_p = 1;
14091 df_set_regs_ever_live (LR_REGNO, true);
14094 /* Determine if we need to save the condition code registers. */
14095 if (df_regs_ever_live_p (CR2_REGNO)
14096 || df_regs_ever_live_p (CR3_REGNO)
14097 || df_regs_ever_live_p (CR4_REGNO))
14099 info_ptr->cr_save_p = 1;
14100 if (DEFAULT_ABI == ABI_V4)
14101 info_ptr->cr_size = reg_size;
14104 /* If the current function calls __builtin_eh_return, then we need
14105 to allocate stack space for registers that will hold data for
14106 the exception handler. */
14107 if (current_function_calls_eh_return)
14110 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
14113 /* SPE saves EH registers in 64-bits. */
14114 ehrd_size = i * (TARGET_SPE_ABI
14115 && info_ptr->spe_64bit_regs_used != 0
14116 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
14121 /* Determine various sizes. */
14122 info_ptr->reg_size = reg_size;
14123 info_ptr->fixed_size = RS6000_SAVE_AREA;
14124 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
14125 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
14126 TARGET_ALTIVEC ? 16 : 8);
14127 if (FRAME_GROWS_DOWNWARD)
14128 info_ptr->vars_size
14129 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
14130 + info_ptr->parm_size,
14131 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
14132 - (info_ptr->fixed_size + info_ptr->vars_size
14133 + info_ptr->parm_size);
14135 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14136 info_ptr->spe_gp_size = 8 * (32 - first_gp);
14138 info_ptr->spe_gp_size = 0;
14140 if (TARGET_ALTIVEC_ABI)
14141 info_ptr->vrsave_mask = compute_vrsave_mask ();
14143 info_ptr->vrsave_mask = 0;
14145 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
14146 info_ptr->vrsave_size = 4;
14148 info_ptr->vrsave_size = 0;
14150 compute_save_world_info (info_ptr);
14152 /* Calculate the offsets. */
14153 switch (DEFAULT_ABI)
14157 gcc_unreachable ();
14161 info_ptr->fp_save_offset = - info_ptr->fp_size;
14162 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14164 if (TARGET_ALTIVEC_ABI)
14166 info_ptr->vrsave_save_offset
14167 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
14169 /* Align stack so vector save area is on a quadword boundary.
14170 The padding goes above the vectors. */
14171 if (info_ptr->altivec_size != 0)
14172 info_ptr->altivec_padding_size
14173 = info_ptr->vrsave_save_offset & 0xF;
14175 info_ptr->altivec_padding_size = 0;
14177 info_ptr->altivec_save_offset
14178 = info_ptr->vrsave_save_offset
14179 - info_ptr->altivec_padding_size
14180 - info_ptr->altivec_size;
14181 gcc_assert (info_ptr->altivec_size == 0
14182 || info_ptr->altivec_save_offset % 16 == 0);
14184 /* Adjust for AltiVec case. */
14185 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
14188 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
14189 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
14190 info_ptr->lr_save_offset = 2*reg_size;
14194 info_ptr->fp_save_offset = - info_ptr->fp_size;
14195 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
14196 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
14198 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
14200 /* Align stack so SPE GPR save area is aligned on a
14201 double-word boundary. */
14202 if (info_ptr->spe_gp_size != 0)
14203 info_ptr->spe_padding_size
14204 = 8 - (-info_ptr->cr_save_offset % 8);
14206 info_ptr->spe_padding_size = 0;
14208 info_ptr->spe_gp_save_offset
14209 = info_ptr->cr_save_offset
14210 - info_ptr->spe_padding_size
14211 - info_ptr->spe_gp_size;
14213 /* Adjust for SPE case. */
14214 info_ptr->ehrd_offset = info_ptr->spe_gp_save_offset;
14216 else if (TARGET_ALTIVEC_ABI)
14218 info_ptr->vrsave_save_offset
14219 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
14221 /* Align stack so vector save area is on a quadword boundary. */
14222 if (info_ptr->altivec_size != 0)
14223 info_ptr->altivec_padding_size
14224 = 16 - (-info_ptr->vrsave_save_offset % 16);
14226 info_ptr->altivec_padding_size = 0;
14228 info_ptr->altivec_save_offset
14229 = info_ptr->vrsave_save_offset
14230 - info_ptr->altivec_padding_size
14231 - info_ptr->altivec_size;
14233 /* Adjust for AltiVec case. */
14234 info_ptr->ehrd_offset = info_ptr->altivec_save_offset;
14237 info_ptr->ehrd_offset = info_ptr->cr_save_offset;
14238 info_ptr->ehrd_offset -= ehrd_size;
14239 info_ptr->lr_save_offset = reg_size;
14243 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
14244 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
14245 + info_ptr->gp_size
14246 + info_ptr->altivec_size
14247 + info_ptr->altivec_padding_size
14248 + info_ptr->spe_gp_size
14249 + info_ptr->spe_padding_size
14251 + info_ptr->cr_size
14252 + info_ptr->vrsave_size,
14255 non_fixed_size = (info_ptr->vars_size
14256 + info_ptr->parm_size
14257 + info_ptr->save_size);
14259 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
14260 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
14262 /* Determine if we need to allocate any stack frame:
14264 For AIX we need to push the stack if a frame pointer is needed
14265 (because the stack might be dynamically adjusted), if we are
14266 debugging, if we make calls, or if the sum of fp_save, gp_save,
14267 and local variables are more than the space needed to save all
14268 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
14269 + 18*8 = 288 (GPR13 reserved).
14271 For V.4 we don't have the stack cushion that AIX uses, but assume
14272 that the debugger can handle stackless frames. */
14274 if (info_ptr->calls_p)
14275 info_ptr->push_p = 1;
14277 else if (DEFAULT_ABI == ABI_V4)
14278 info_ptr->push_p = non_fixed_size != 0;
14280 else if (frame_pointer_needed)
14281 info_ptr->push_p = 1;
14283 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
14284 info_ptr->push_p = 1;
14287 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
14289 /* Zero offsets if we're not saving those registers. */
14290 if (info_ptr->fp_size == 0)
14291 info_ptr->fp_save_offset = 0;
14293 if (info_ptr->gp_size == 0)
14294 info_ptr->gp_save_offset = 0;
14296 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
14297 info_ptr->altivec_save_offset = 0;
14299 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
14300 info_ptr->vrsave_save_offset = 0;
14302 if (! TARGET_SPE_ABI
14303 || info_ptr->spe_64bit_regs_used == 0
14304 || info_ptr->spe_gp_size == 0)
14305 info_ptr->spe_gp_save_offset = 0;
14307 if (! info_ptr->lr_save_p)
14308 info_ptr->lr_save_offset = 0;
14310 if (! info_ptr->cr_save_p)
14311 info_ptr->cr_save_offset = 0;
14316 /* Return true if the current function uses any GPRs in 64-bit SIMD
14320 spe_func_has_64bit_regs_p (void)
14324 /* Functions that save and restore all the call-saved registers will
14325 need to save/restore the registers in 64-bits. */
14326 if (current_function_calls_eh_return
14327 || current_function_calls_setjmp
14328 || current_function_has_nonlocal_goto)
14331 insns = get_insns ();
14333 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
14339 /* FIXME: This should be implemented with attributes...
14341 (set_attr "spe64" "true")....then,
14342 if (get_spe64(insn)) return true;
14344 It's the only reliable way to do the stuff below. */
14346 i = PATTERN (insn);
14347 if (GET_CODE (i) == SET)
14349 enum machine_mode mode = GET_MODE (SET_SRC (i));
14351 if (SPE_VECTOR_MODE (mode))
14353 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == TFmode))
14363 debug_stack_info (rs6000_stack_t *info)
14365 const char *abi_string;
14368 info = rs6000_stack_info ();
14370 fprintf (stderr, "\nStack information for function %s:\n",
14371 ((current_function_decl && DECL_NAME (current_function_decl))
14372 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
14377 default: abi_string = "Unknown"; break;
14378 case ABI_NONE: abi_string = "NONE"; break;
14379 case ABI_AIX: abi_string = "AIX"; break;
14380 case ABI_DARWIN: abi_string = "Darwin"; break;
14381 case ABI_V4: abi_string = "V.4"; break;
14384 fprintf (stderr, "\tABI = %5s\n", abi_string);
14386 if (TARGET_ALTIVEC_ABI)
14387 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
14389 if (TARGET_SPE_ABI)
14390 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
14392 if (info->first_gp_reg_save != 32)
14393 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
14395 if (info->first_fp_reg_save != 64)
14396 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
14398 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
14399 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
14400 info->first_altivec_reg_save);
14402 if (info->lr_save_p)
14403 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
14405 if (info->cr_save_p)
14406 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
14408 if (info->vrsave_mask)
14409 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
14412 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
14415 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
14417 if (info->gp_save_offset)
14418 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
14420 if (info->fp_save_offset)
14421 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
14423 if (info->altivec_save_offset)
14424 fprintf (stderr, "\taltivec_save_offset = %5d\n",
14425 info->altivec_save_offset);
14427 if (info->spe_gp_save_offset)
14428 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
14429 info->spe_gp_save_offset);
14431 if (info->vrsave_save_offset)
14432 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
14433 info->vrsave_save_offset);
14435 if (info->lr_save_offset)
14436 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
14438 if (info->cr_save_offset)
14439 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
14441 if (info->varargs_save_offset)
14442 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
14444 if (info->total_size)
14445 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14448 if (info->vars_size)
14449 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
14452 if (info->parm_size)
14453 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
14455 if (info->fixed_size)
14456 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
14459 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
14461 if (info->spe_gp_size)
14462 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
14465 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
14467 if (info->altivec_size)
14468 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
14470 if (info->vrsave_size)
14471 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
14473 if (info->altivec_padding_size)
14474 fprintf (stderr, "\taltivec_padding_size= %5d\n",
14475 info->altivec_padding_size);
14477 if (info->spe_padding_size)
14478 fprintf (stderr, "\tspe_padding_size = %5d\n",
14479 info->spe_padding_size);
14482 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
14484 if (info->save_size)
14485 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
14487 if (info->reg_size != 4)
14488 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
14490 fprintf (stderr, "\n");
14494 rs6000_return_addr (int count, rtx frame)
14496 /* Currently we don't optimize very well between prolog and body
14497 code and for PIC code the code can be actually quite bad, so
14498 don't try to be too clever here. */
14499 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
14501 cfun->machine->ra_needs_full_frame = 1;
14508 plus_constant (copy_to_reg
14509 (gen_rtx_MEM (Pmode,
14510 memory_address (Pmode, frame))),
14511 RETURN_ADDRESS_OFFSET)));
14514 cfun->machine->ra_need_lr = 1;
14515 return get_hard_reg_initial_val (Pmode, LR_REGNO);
14518 /* Say whether a function is a candidate for sibcall handling or not.
14519 We do not allow indirect calls to be optimized into sibling calls.
14520 Also, we can't do it if there are any vector parameters; there's
14521 nowhere to put the VRsave code so it works; note that functions with
14522 vector parameters are required to have a prototype, so the argument
14523 type info must be available here. (The tail recursion case can work
14524 with vector parameters, but there's no way to distinguish here.) */
14526 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
14531 if (TARGET_ALTIVEC_VRSAVE)
14533 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
14534 type; type = TREE_CHAIN (type))
14536 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
14540 if (DEFAULT_ABI == ABI_DARWIN
14541 || ((*targetm.binds_local_p) (decl)
14542 && (DEFAULT_ABI != ABI_AIX || !DECL_EXTERNAL (decl))))
14544 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
14546 if (!lookup_attribute ("longcall", attr_list)
14547 || lookup_attribute ("shortcall", attr_list))
14554 /* NULL if INSN insn is valid within a low-overhead loop.
14555 Otherwise return why doloop cannot be applied.
14556 PowerPC uses the COUNT register for branch on table instructions. */
14558 static const char *
14559 rs6000_invalid_within_doloop (const_rtx insn)
14562 return "Function call in the loop.";
14565 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
14566 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
14567 return "Computed branch in the loop.";
14573 rs6000_ra_ever_killed (void)
14579 if (current_function_is_thunk)
14582 /* regs_ever_live has LR marked as used if any sibcalls are present,
14583 but this should not force saving and restoring in the
14584 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
14585 clobbers LR, so that is inappropriate. */
14587 /* Also, the prologue can generate a store into LR that
14588 doesn't really count, like this:
14591 bcl to set PIC register
14595 When we're called from the epilogue, we need to avoid counting
14596 this as a store. */
14598 push_topmost_sequence ();
14599 top = get_insns ();
14600 pop_topmost_sequence ();
14601 reg = gen_rtx_REG (Pmode, LR_REGNO);
14603 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
14609 if (!SIBLING_CALL_P (insn))
14612 else if (find_regno_note (insn, REG_INC, LR_REGNO))
14614 else if (set_of (reg, insn) != NULL_RTX
14615 && !prologue_epilogue_contains (insn))
14622 /* Emit instructions needed to load the TOC register.
14623 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
14624 a constant pool; or for SVR4 -fpic. */
14627 rs6000_emit_load_toc_table (int fromprolog)
14630 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
14632 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
14635 rtx lab, tmp1, tmp2, got;
14637 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14638 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14640 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14642 got = rs6000_got_sym ();
14643 tmp1 = tmp2 = dest;
14646 tmp1 = gen_reg_rtx (Pmode);
14647 tmp2 = gen_reg_rtx (Pmode);
14649 emit_insn (gen_load_toc_v4_PIC_1 (lab));
14650 emit_move_insn (tmp1,
14651 gen_rtx_REG (Pmode, LR_REGNO));
14652 emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
14653 emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
14655 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
14657 emit_insn (gen_load_toc_v4_pic_si ());
14658 emit_move_insn (dest, gen_rtx_REG (Pmode, LR_REGNO));
14660 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
14663 rtx temp0 = (fromprolog
14664 ? gen_rtx_REG (Pmode, 0)
14665 : gen_reg_rtx (Pmode));
14671 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
14672 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14674 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
14675 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14677 emit_insn (gen_load_toc_v4_PIC_1 (symF));
14678 emit_move_insn (dest,
14679 gen_rtx_REG (Pmode, LR_REGNO));
14680 emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest, symL, symF));
14686 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
14687 emit_insn (gen_load_toc_v4_PIC_1b (tocsym));
14688 emit_move_insn (dest,
14689 gen_rtx_REG (Pmode, LR_REGNO));
14690 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
14692 emit_insn (gen_addsi3 (dest, temp0, dest));
14694 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
14696 /* This is for AIX code running in non-PIC ELF32. */
14699 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
14700 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
14702 emit_insn (gen_elf_high (dest, realsym));
14703 emit_insn (gen_elf_low (dest, dest, realsym));
14707 gcc_assert (DEFAULT_ABI == ABI_AIX);
14710 emit_insn (gen_load_toc_aix_si (dest));
14712 emit_insn (gen_load_toc_aix_di (dest));
14716 /* Emit instructions to restore the link register after determining where
14717 its value has been stored. */
14720 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
14722 rs6000_stack_t *info = rs6000_stack_info ();
14725 operands[0] = source;
14726 operands[1] = scratch;
14728 if (info->lr_save_p)
14730 rtx frame_rtx = stack_pointer_rtx;
14731 HOST_WIDE_INT sp_offset = 0;
14734 if (frame_pointer_needed
14735 || current_function_calls_alloca
14736 || info->total_size > 32767)
14738 tmp = gen_frame_mem (Pmode, frame_rtx);
14739 emit_move_insn (operands[1], tmp);
14740 frame_rtx = operands[1];
14742 else if (info->push_p)
14743 sp_offset = info->total_size;
14745 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
14746 tmp = gen_frame_mem (Pmode, tmp);
14747 emit_move_insn (tmp, operands[0]);
14750 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO), operands[0]);
14753 static GTY(()) alias_set_type set = -1;
14756 get_TOC_alias_set (void)
14759 set = new_alias_set ();
14763 /* This returns nonzero if the current function uses the TOC. This is
14764 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
14765 is generated by the ABI_V4 load_toc_* patterns. */
14772 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
14775 rtx pat = PATTERN (insn);
14778 if (GET_CODE (pat) == PARALLEL)
14779 for (i = 0; i < XVECLEN (pat, 0); i++)
14781 rtx sub = XVECEXP (pat, 0, i);
14782 if (GET_CODE (sub) == USE)
14784 sub = XEXP (sub, 0);
14785 if (GET_CODE (sub) == UNSPEC
14786 && XINT (sub, 1) == UNSPEC_TOC)
14796 create_TOC_reference (rtx symbol)
14798 if (!can_create_pseudo_p ())
14799 df_set_regs_ever_live (TOC_REGISTER, true);
14800 return gen_rtx_PLUS (Pmode,
14801 gen_rtx_REG (Pmode, TOC_REGISTER),
14802 gen_rtx_CONST (Pmode,
14803 gen_rtx_MINUS (Pmode, symbol,
14804 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
14807 /* If _Unwind_* has been called from within the same module,
14808 toc register is not guaranteed to be saved to 40(1) on function
14809 entry. Save it there in that case. */
14812 rs6000_aix_emit_builtin_unwind_init (void)
14815 rtx stack_top = gen_reg_rtx (Pmode);
14816 rtx opcode_addr = gen_reg_rtx (Pmode);
14817 rtx opcode = gen_reg_rtx (SImode);
14818 rtx tocompare = gen_reg_rtx (SImode);
14819 rtx no_toc_save_needed = gen_label_rtx ();
14821 mem = gen_frame_mem (Pmode, hard_frame_pointer_rtx);
14822 emit_move_insn (stack_top, mem);
14824 mem = gen_frame_mem (Pmode,
14825 gen_rtx_PLUS (Pmode, stack_top,
14826 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
14827 emit_move_insn (opcode_addr, mem);
14828 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
14829 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
14830 : 0xE8410028, SImode));
14832 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
14833 SImode, NULL_RTX, NULL_RTX,
14834 no_toc_save_needed);
14836 mem = gen_frame_mem (Pmode,
14837 gen_rtx_PLUS (Pmode, stack_top,
14838 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
14839 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
14840 emit_label (no_toc_save_needed);
14843 /* This ties together stack memory (MEM with an alias set of frame_alias_set)
14844 and the change to the stack pointer. */
14847 rs6000_emit_stack_tie (void)
14849 rtx mem = gen_frame_mem (BLKmode,
14850 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
14852 emit_insn (gen_stack_tie (mem));
14855 /* Emit the correct code for allocating stack space, as insns.
14856 If COPY_R12, make sure a copy of the old frame is left in r12.
14857 The generated code may use hard register 0 as a temporary. */
14860 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
14863 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
14864 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
14865 rtx todec = gen_int_mode (-size, Pmode);
14867 if (INTVAL (todec) != -size)
14869 warning (0, "stack frame too large");
14870 emit_insn (gen_trap ());
14874 if (current_function_limit_stack)
14876 if (REG_P (stack_limit_rtx)
14877 && REGNO (stack_limit_rtx) > 1
14878 && REGNO (stack_limit_rtx) <= 31)
14880 emit_insn (TARGET_32BIT
14881 ? gen_addsi3 (tmp_reg,
14884 : gen_adddi3 (tmp_reg,
14888 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14891 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
14893 && DEFAULT_ABI == ABI_V4)
14895 rtx toload = gen_rtx_CONST (VOIDmode,
14896 gen_rtx_PLUS (Pmode,
14900 emit_insn (gen_elf_high (tmp_reg, toload));
14901 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
14902 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
14906 warning (0, "stack limit expression is not supported");
14909 if (copy_r12 || ! TARGET_UPDATE)
14910 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
14916 /* Need a note here so that try_split doesn't get confused. */
14917 if (get_last_insn () == NULL_RTX)
14918 emit_note (NOTE_INSN_DELETED);
14919 insn = emit_move_insn (tmp_reg, todec);
14920 try_split (PATTERN (insn), insn, 0);
14924 insn = emit_insn (TARGET_32BIT
14925 ? gen_movsi_update (stack_reg, stack_reg,
14927 : gen_movdi_di_update (stack_reg, stack_reg,
14928 todec, stack_reg));
14932 insn = emit_insn (TARGET_32BIT
14933 ? gen_addsi3 (stack_reg, stack_reg, todec)
14934 : gen_adddi3 (stack_reg, stack_reg, todec));
14935 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
14936 gen_rtx_REG (Pmode, 12));
14939 RTX_FRAME_RELATED_P (insn) = 1;
14941 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14942 gen_rtx_SET (VOIDmode, stack_reg,
14943 gen_rtx_PLUS (Pmode, stack_reg,
14948 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
14949 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
14950 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
14951 deduce these equivalences by itself so it wasn't necessary to hold
14952 its hand so much. */
14955 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
14956 rtx reg2, rtx rreg)
14960 /* copy_rtx will not make unique copies of registers, so we need to
14961 ensure we don't have unwanted sharing here. */
14963 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14966 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
14968 real = copy_rtx (PATTERN (insn));
14970 if (reg2 != NULL_RTX)
14971 real = replace_rtx (real, reg2, rreg);
14973 real = replace_rtx (real, reg,
14974 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
14975 STACK_POINTER_REGNUM),
14978 /* We expect that 'real' is either a SET or a PARALLEL containing
14979 SETs (and possibly other stuff). In a PARALLEL, all the SETs
14980 are important so they all have to be marked RTX_FRAME_RELATED_P. */
14982 if (GET_CODE (real) == SET)
14986 temp = simplify_rtx (SET_SRC (set));
14988 SET_SRC (set) = temp;
14989 temp = simplify_rtx (SET_DEST (set));
14991 SET_DEST (set) = temp;
14992 if (GET_CODE (SET_DEST (set)) == MEM)
14994 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
14996 XEXP (SET_DEST (set), 0) = temp;
15003 gcc_assert (GET_CODE (real) == PARALLEL);
15004 for (i = 0; i < XVECLEN (real, 0); i++)
15005 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
15007 rtx set = XVECEXP (real, 0, i);
15009 temp = simplify_rtx (SET_SRC (set));
15011 SET_SRC (set) = temp;
15012 temp = simplify_rtx (SET_DEST (set));
15014 SET_DEST (set) = temp;
15015 if (GET_CODE (SET_DEST (set)) == MEM)
15017 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
15019 XEXP (SET_DEST (set), 0) = temp;
15021 RTX_FRAME_RELATED_P (set) = 1;
15026 real = spe_synthesize_frame_save (real);
15028 RTX_FRAME_RELATED_P (insn) = 1;
15029 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15034 /* Given an SPE frame note, return a PARALLEL of SETs with the
15035 original note, plus a synthetic register save. */
15038 spe_synthesize_frame_save (rtx real)
15040 rtx synth, offset, reg, real2;
15042 if (GET_CODE (real) != SET
15043 || GET_MODE (SET_SRC (real)) != V2SImode)
15046 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
15047 frame related note. The parallel contains a set of the register
15048 being saved, and another set to a synthetic register (n+1200).
15049 This is so we can differentiate between 64-bit and 32-bit saves.
15050 Words cannot describe this nastiness. */
15052 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
15053 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
15054 && GET_CODE (SET_SRC (real)) == REG);
15057 (set (mem (plus (reg x) (const y)))
15060 (set (mem (plus (reg x) (const y+4)))
15064 real2 = copy_rtx (real);
15065 PUT_MODE (SET_DEST (real2), SImode);
15066 reg = SET_SRC (real2);
15067 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
15068 synth = copy_rtx (real2);
15070 if (BYTES_BIG_ENDIAN)
15072 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
15073 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
15076 reg = SET_SRC (synth);
15078 synth = replace_rtx (synth, reg,
15079 gen_rtx_REG (SImode, REGNO (reg) + 1200));
15081 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
15082 synth = replace_rtx (synth, offset,
15083 GEN_INT (INTVAL (offset)
15084 + (BYTES_BIG_ENDIAN ? 0 : 4)));
15086 RTX_FRAME_RELATED_P (synth) = 1;
15087 RTX_FRAME_RELATED_P (real2) = 1;
15088 if (BYTES_BIG_ENDIAN)
15089 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
15091 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
15096 /* Returns an insn that has a vrsave set operation with the
15097 appropriate CLOBBERs. */
15100 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
15103 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
15104 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15107 = gen_rtx_SET (VOIDmode,
15109 gen_rtx_UNSPEC_VOLATILE (SImode,
15110 gen_rtvec (2, reg, vrsave),
15111 UNSPECV_SET_VRSAVE));
15115 /* We need to clobber the registers in the mask so the scheduler
15116 does not move sets to VRSAVE before sets of AltiVec registers.
15118 However, if the function receives nonlocal gotos, reload will set
15119 all call saved registers live. We will end up with:
15121 (set (reg 999) (mem))
15122 (parallel [ (set (reg vrsave) (unspec blah))
15123 (clobber (reg 999))])
15125 The clobber will cause the store into reg 999 to be dead, and
15126 flow will attempt to delete an epilogue insn. In this case, we
15127 need an unspec use/set of the register. */
15129 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
15130 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15132 if (!epiloguep || call_used_regs [i])
15133 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
15134 gen_rtx_REG (V4SImode, i));
15137 rtx reg = gen_rtx_REG (V4SImode, i);
15140 = gen_rtx_SET (VOIDmode,
15142 gen_rtx_UNSPEC (V4SImode,
15143 gen_rtvec (1, reg), 27));
15147 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
15149 for (i = 0; i < nclobs; ++i)
15150 XVECEXP (insn, 0, i) = clobs[i];
15155 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
15156 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
15159 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
15160 unsigned int regno, int offset, HOST_WIDE_INT total_size)
15162 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
15163 rtx replacea, replaceb;
15165 int_rtx = GEN_INT (offset);
15167 /* Some cases that need register indexed addressing. */
15168 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
15169 || (TARGET_E500_DOUBLE && mode == DFmode)
15171 && SPE_VECTOR_MODE (mode)
15172 && !SPE_CONST_OFFSET_OK (offset)))
15174 /* Whomever calls us must make sure r11 is available in the
15175 flow path of instructions in the prologue. */
15176 offset_rtx = gen_rtx_REG (Pmode, 11);
15177 emit_move_insn (offset_rtx, int_rtx);
15179 replacea = offset_rtx;
15180 replaceb = int_rtx;
15184 offset_rtx = int_rtx;
15185 replacea = NULL_RTX;
15186 replaceb = NULL_RTX;
15189 reg = gen_rtx_REG (mode, regno);
15190 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
15191 mem = gen_frame_mem (mode, addr);
15193 insn = emit_move_insn (mem, reg);
15195 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
15198 /* Emit an offset memory reference suitable for a frame store, while
15199 converting to a valid addressing mode. */
15202 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
15204 rtx int_rtx, offset_rtx;
15206 int_rtx = GEN_INT (offset);
15208 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
15209 || (TARGET_E500_DOUBLE && mode == DFmode))
15211 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
15212 emit_move_insn (offset_rtx, int_rtx);
15215 offset_rtx = int_rtx;
15217 return gen_frame_mem (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
15220 /* Look for user-defined global regs. We should not save and restore these,
15221 and cannot use stmw/lmw if there are any in its range. */
15224 no_global_regs_above (int first_greg)
15227 for (i = 0; i < 32 - first_greg; i++)
15228 if (global_regs[first_greg + i])
15233 #ifndef TARGET_FIX_AND_CONTINUE
15234 #define TARGET_FIX_AND_CONTINUE 0
15237 /* Determine whether the gp REG is really used. */
15240 rs6000_reg_live_or_pic_offset_p (int reg)
15242 return ((df_regs_ever_live_p (reg)
15243 && (!call_used_regs[reg]
15244 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15245 && TARGET_TOC && TARGET_MINIMAL_TOC)))
15246 || (reg == RS6000_PIC_OFFSET_TABLE_REGNUM
15247 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
15248 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))));
15251 /* Emit function prologue as insns. */
15254 rs6000_emit_prologue (void)
15256 rs6000_stack_t *info = rs6000_stack_info ();
15257 enum machine_mode reg_mode = Pmode;
15258 int reg_size = TARGET_32BIT ? 4 : 8;
15259 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
15260 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
15261 rtx frame_reg_rtx = sp_reg_rtx;
15262 rtx cr_save_rtx = NULL_RTX;
15264 int saving_FPRs_inline;
15265 int using_store_multiple;
15266 HOST_WIDE_INT sp_offset = 0;
15268 if (TARGET_FIX_AND_CONTINUE)
15270 /* gdb on darwin arranges to forward a function from the old
15271 address by modifying the first 5 instructions of the function
15272 to branch to the overriding function. This is necessary to
15273 permit function pointers that point to the old function to
15274 actually forward to the new function. */
15275 emit_insn (gen_nop ());
15276 emit_insn (gen_nop ());
15277 emit_insn (gen_nop ());
15278 emit_insn (gen_nop ());
15279 emit_insn (gen_nop ());
15282 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15284 reg_mode = V2SImode;
15288 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15289 && (!TARGET_SPE_ABI
15290 || info->spe_64bit_regs_used == 0)
15291 && info->first_gp_reg_save < 31
15292 && no_global_regs_above (info->first_gp_reg_save));
15293 saving_FPRs_inline = (info->first_fp_reg_save == 64
15294 || FP_SAVE_INLINE (info->first_fp_reg_save)
15295 || current_function_calls_eh_return
15296 || cfun->machine->ra_need_lr);
15298 /* For V.4, update stack before we do any saving and set back pointer. */
15299 if (! WORLD_SAVE_P (info)
15301 && (DEFAULT_ABI == ABI_V4
15302 || current_function_calls_eh_return))
15304 if (info->total_size < 32767)
15305 sp_offset = info->total_size;
15307 frame_reg_rtx = frame_ptr_rtx;
15308 rs6000_emit_allocate_stack (info->total_size,
15309 (frame_reg_rtx != sp_reg_rtx
15310 && (info->cr_save_p
15312 || info->first_fp_reg_save < 64
15313 || info->first_gp_reg_save < 32
15315 if (frame_reg_rtx != sp_reg_rtx)
15316 rs6000_emit_stack_tie ();
15319 /* Handle world saves specially here. */
15320 if (WORLD_SAVE_P (info))
15327 /* save_world expects lr in r0. */
15328 reg0 = gen_rtx_REG (Pmode, 0);
15329 if (info->lr_save_p)
15331 insn = emit_move_insn (reg0,
15332 gen_rtx_REG (Pmode, LR_REGNO));
15333 RTX_FRAME_RELATED_P (insn) = 1;
15336 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
15337 assumptions about the offsets of various bits of the stack
15339 gcc_assert (info->gp_save_offset == -220
15340 && info->fp_save_offset == -144
15341 && info->lr_save_offset == 8
15342 && info->cr_save_offset == 4
15345 && (!current_function_calls_eh_return
15346 || info->ehrd_offset == -432)
15347 && info->vrsave_save_offset == -224
15348 && info->altivec_save_offset == -416);
15350 treg = gen_rtx_REG (SImode, 11);
15351 emit_move_insn (treg, GEN_INT (-info->total_size));
15353 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
15354 in R11. It also clobbers R12, so beware! */
15356 /* Preserve CR2 for save_world prologues */
15358 sz += 32 - info->first_gp_reg_save;
15359 sz += 64 - info->first_fp_reg_save;
15360 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
15361 p = rtvec_alloc (sz);
15363 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
15364 gen_rtx_REG (SImode,
15366 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15367 gen_rtx_SYMBOL_REF (Pmode,
15369 /* We do floats first so that the instruction pattern matches
15371 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15373 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15374 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15375 GEN_INT (info->fp_save_offset
15376 + sp_offset + 8 * i));
15377 rtx mem = gen_frame_mem (DFmode, addr);
15379 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15381 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
15383 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
15384 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15385 GEN_INT (info->altivec_save_offset
15386 + sp_offset + 16 * i));
15387 rtx mem = gen_frame_mem (V4SImode, addr);
15389 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15391 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15393 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15394 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15395 GEN_INT (info->gp_save_offset
15396 + sp_offset + reg_size * i));
15397 rtx mem = gen_frame_mem (reg_mode, addr);
15399 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15403 /* CR register traditionally saved as CR2. */
15404 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
15405 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15406 GEN_INT (info->cr_save_offset
15408 rtx mem = gen_frame_mem (reg_mode, addr);
15410 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
15412 /* Explain about use of R0. */
15413 if (info->lr_save_p)
15415 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15416 GEN_INT (info->lr_save_offset
15418 rtx mem = gen_frame_mem (reg_mode, addr);
15420 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg0);
15422 /* Explain what happens to the stack pointer. */
15424 rtx newval = gen_rtx_PLUS (Pmode, sp_reg_rtx, treg);
15425 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, sp_reg_rtx, newval);
15428 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15429 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15430 treg, GEN_INT (-info->total_size));
15431 sp_offset = info->total_size;
15434 /* If we use the link register, get it into r0. */
15435 if (!WORLD_SAVE_P (info) && info->lr_save_p)
15437 rtx addr, reg, mem;
15439 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
15440 gen_rtx_REG (Pmode, LR_REGNO));
15441 RTX_FRAME_RELATED_P (insn) = 1;
15443 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15444 GEN_INT (info->lr_save_offset + sp_offset));
15445 reg = gen_rtx_REG (Pmode, 0);
15446 mem = gen_rtx_MEM (Pmode, addr);
15447 /* This should not be of rs6000_sr_alias_set, because of
15448 __builtin_return_address. */
15450 insn = emit_move_insn (mem, reg);
15451 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15452 NULL_RTX, NULL_RTX);
15455 /* If we need to save CR, put it into r12. */
15456 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
15460 cr_save_rtx = gen_rtx_REG (SImode, 12);
15461 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15462 RTX_FRAME_RELATED_P (insn) = 1;
15463 /* Now, there's no way that dwarf2out_frame_debug_expr is going
15464 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
15465 But that's OK. All we have to do is specify that _one_ condition
15466 code register is saved in this stack slot. The thrower's epilogue
15467 will then restore all the call-saved registers.
15468 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
15469 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
15470 gen_rtx_REG (SImode, CR2_REGNO));
15471 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15476 /* Do any required saving of fpr's. If only one or two to save, do
15477 it ourselves. Otherwise, call function. */
15478 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
15481 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15482 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
15483 && ! call_used_regs[info->first_fp_reg_save+i]))
15484 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
15485 info->first_fp_reg_save + i,
15486 info->fp_save_offset + sp_offset + 8 * i,
15489 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
15493 const char *alloc_rname;
15495 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
15497 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
15498 gen_rtx_REG (Pmode,
15500 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
15501 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
15502 alloc_rname = ggc_strdup (rname);
15503 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15504 gen_rtx_SYMBOL_REF (Pmode,
15506 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15508 rtx addr, reg, mem;
15509 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
15510 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15511 GEN_INT (info->fp_save_offset
15512 + sp_offset + 8*i));
15513 mem = gen_frame_mem (DFmode, addr);
15515 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
15517 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15518 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15519 NULL_RTX, NULL_RTX);
15522 /* Save GPRs. This is done as a PARALLEL if we are using
15523 the store-multiple instructions. */
15524 if (!WORLD_SAVE_P (info) && using_store_multiple)
15528 p = rtvec_alloc (32 - info->first_gp_reg_save);
15529 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15531 rtx addr, reg, mem;
15532 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15533 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15534 GEN_INT (info->gp_save_offset
15537 mem = gen_frame_mem (reg_mode, addr);
15539 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
15541 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
15542 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15543 NULL_RTX, NULL_RTX);
15545 else if (!WORLD_SAVE_P (info)
15547 && info->spe_64bit_regs_used != 0
15548 && info->first_gp_reg_save != 32)
15551 rtx spe_save_area_ptr;
15552 int using_static_chain_p = (cfun->static_chain_decl != NULL_TREE
15553 && df_regs_ever_live_p (STATIC_CHAIN_REGNUM)
15554 && !call_used_regs[STATIC_CHAIN_REGNUM]);
15556 /* Determine whether we can address all of the registers that need
15557 to be saved with an offset from the stack pointer that fits in
15558 the small const field for SPE memory instructions. */
15559 int spe_regs_addressable_via_sp
15560 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
15561 + (32 - info->first_gp_reg_save - 1) * reg_size);
15564 if (spe_regs_addressable_via_sp)
15566 spe_save_area_ptr = sp_reg_rtx;
15567 spe_offset = info->spe_gp_save_offset + sp_offset;
15571 /* Make r11 point to the start of the SPE save area. We need
15572 to be careful here if r11 is holding the static chain. If
15573 it is, then temporarily save it in r0. We would use r0 as
15574 our base register here, but using r0 as a base register in
15575 loads and stores means something different from what we
15577 if (using_static_chain_p)
15579 rtx r0 = gen_rtx_REG (Pmode, 0);
15581 gcc_assert (info->first_gp_reg_save > 11);
15583 emit_move_insn (r0, gen_rtx_REG (Pmode, 11));
15586 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
15587 emit_insn (gen_addsi3 (spe_save_area_ptr, sp_reg_rtx,
15588 GEN_INT (info->spe_gp_save_offset + sp_offset)));
15593 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15594 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15596 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15597 rtx offset, addr, mem;
15599 /* We're doing all this to ensure that the offset fits into
15600 the immediate offset of 'evstdd'. */
15601 gcc_assert (SPE_CONST_OFFSET_OK (reg_size * i + spe_offset));
15603 offset = GEN_INT (reg_size * i + spe_offset);
15604 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
15605 mem = gen_rtx_MEM (V2SImode, addr);
15607 insn = emit_move_insn (mem, reg);
15609 rs6000_frame_related (insn, spe_save_area_ptr,
15610 info->spe_gp_save_offset
15611 + sp_offset + reg_size * i,
15612 offset, const0_rtx);
15615 /* Move the static chain pointer back. */
15616 if (using_static_chain_p && !spe_regs_addressable_via_sp)
15617 emit_move_insn (gen_rtx_REG (Pmode, 11), gen_rtx_REG (Pmode, 0));
15619 else if (!WORLD_SAVE_P (info))
15622 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
15623 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
15625 rtx addr, reg, mem;
15626 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
15628 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15629 GEN_INT (info->gp_save_offset
15632 mem = gen_frame_mem (reg_mode, addr);
15634 insn = emit_move_insn (mem, reg);
15635 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15636 NULL_RTX, NULL_RTX);
15640 /* ??? There's no need to emit actual instructions here, but it's the
15641 easiest way to get the frame unwind information emitted. */
15642 if (current_function_calls_eh_return)
15644 unsigned int i, regno;
15646 /* In AIX ABI we need to pretend we save r2 here. */
15649 rtx addr, reg, mem;
15651 reg = gen_rtx_REG (reg_mode, 2);
15652 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15653 GEN_INT (sp_offset + 5 * reg_size));
15654 mem = gen_frame_mem (reg_mode, addr);
15656 insn = emit_move_insn (mem, reg);
15657 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15658 NULL_RTX, NULL_RTX);
15659 PATTERN (insn) = gen_blockage ();
15664 regno = EH_RETURN_DATA_REGNO (i);
15665 if (regno == INVALID_REGNUM)
15668 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
15669 info->ehrd_offset + sp_offset
15670 + reg_size * (int) i,
15675 /* Save CR if we use any that must be preserved. */
15676 if (!WORLD_SAVE_P (info) && info->cr_save_p)
15678 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
15679 GEN_INT (info->cr_save_offset + sp_offset));
15680 rtx mem = gen_frame_mem (SImode, addr);
15681 /* See the large comment above about why CR2_REGNO is used. */
15682 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
15684 /* If r12 was used to hold the original sp, copy cr into r0 now
15686 if (REGNO (frame_reg_rtx) == 12)
15690 cr_save_rtx = gen_rtx_REG (SImode, 0);
15691 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
15692 RTX_FRAME_RELATED_P (insn) = 1;
15693 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
15694 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
15699 insn = emit_move_insn (mem, cr_save_rtx);
15701 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15702 NULL_RTX, NULL_RTX);
15705 /* Update stack and set back pointer unless this is V.4,
15706 for which it was done previously. */
15707 if (!WORLD_SAVE_P (info) && info->push_p
15708 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
15710 if (info->total_size < 32767)
15711 sp_offset = info->total_size;
15713 frame_reg_rtx = frame_ptr_rtx;
15714 rs6000_emit_allocate_stack (info->total_size,
15715 (frame_reg_rtx != sp_reg_rtx
15716 && ((info->altivec_size != 0)
15717 || (info->vrsave_mask != 0)
15719 if (frame_reg_rtx != sp_reg_rtx)
15720 rs6000_emit_stack_tie ();
15723 /* Set frame pointer, if needed. */
15724 if (frame_pointer_needed)
15726 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
15728 RTX_FRAME_RELATED_P (insn) = 1;
15731 /* Save AltiVec registers if needed. Save here because the red zone does
15732 not include AltiVec registers. */
15733 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
15737 /* There should be a non inline version of this, for when we
15738 are saving lots of vector registers. */
15739 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
15740 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
15742 rtx areg, savereg, mem;
15745 offset = info->altivec_save_offset + sp_offset
15746 + 16 * (i - info->first_altivec_reg_save);
15748 savereg = gen_rtx_REG (V4SImode, i);
15750 areg = gen_rtx_REG (Pmode, 0);
15751 emit_move_insn (areg, GEN_INT (offset));
15753 /* AltiVec addressing mode is [reg+reg]. */
15754 mem = gen_frame_mem (V4SImode,
15755 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
15757 insn = emit_move_insn (mem, savereg);
15759 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
15760 areg, GEN_INT (offset));
15764 /* VRSAVE is a bit vector representing which AltiVec registers
15765 are used. The OS uses this to determine which vector
15766 registers to save on a context switch. We need to save
15767 VRSAVE on the stack frame, add whatever AltiVec registers we
15768 used in this function, and do the corresponding magic in the
15771 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
15772 && info->vrsave_mask != 0)
15774 rtx reg, mem, vrsave;
15777 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
15778 as frame_reg_rtx and r11 as the static chain pointer for
15779 nested functions. */
15780 reg = gen_rtx_REG (SImode, 0);
15781 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
15783 emit_insn (gen_get_vrsave_internal (reg));
15785 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
15787 if (!WORLD_SAVE_P (info))
15790 offset = info->vrsave_save_offset + sp_offset;
15791 mem = gen_frame_mem (SImode,
15792 gen_rtx_PLUS (Pmode, frame_reg_rtx,
15793 GEN_INT (offset)));
15794 insn = emit_move_insn (mem, reg);
15797 /* Include the registers in the mask. */
15798 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
15800 insn = emit_insn (generate_set_vrsave (reg, info, 0));
15803 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
15804 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
15805 || (DEFAULT_ABI == ABI_V4
15806 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
15807 && df_regs_ever_live_p (RS6000_PIC_OFFSET_TABLE_REGNUM)))
15809 /* If emit_load_toc_table will use the link register, we need to save
15810 it. We use R12 for this purpose because emit_load_toc_table
15811 can use register 0. This allows us to use a plain 'blr' to return
15812 from the procedure more often. */
15813 int save_LR_around_toc_setup = (TARGET_ELF
15814 && DEFAULT_ABI != ABI_AIX
15816 && ! info->lr_save_p
15817 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
15818 if (save_LR_around_toc_setup)
15820 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15822 insn = emit_move_insn (frame_ptr_rtx, lr);
15823 RTX_FRAME_RELATED_P (insn) = 1;
15825 rs6000_emit_load_toc_table (TRUE);
15827 insn = emit_move_insn (lr, frame_ptr_rtx);
15828 RTX_FRAME_RELATED_P (insn) = 1;
15831 rs6000_emit_load_toc_table (TRUE);
15835 if (DEFAULT_ABI == ABI_DARWIN
15836 && flag_pic && current_function_uses_pic_offset_table)
15838 rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
15839 rtx src = machopic_function_base_sym ();
15841 /* Save and restore LR locally around this call (in R0). */
15842 if (!info->lr_save_p)
15843 emit_move_insn (gen_rtx_REG (Pmode, 0), lr);
15845 emit_insn (gen_load_macho_picbase (src));
15847 emit_move_insn (gen_rtx_REG (Pmode,
15848 RS6000_PIC_OFFSET_TABLE_REGNUM),
15851 if (!info->lr_save_p)
15852 emit_move_insn (lr, gen_rtx_REG (Pmode, 0));
15857 /* Write function prologue. */
15860 rs6000_output_function_prologue (FILE *file,
15861 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15863 rs6000_stack_t *info = rs6000_stack_info ();
15865 if (TARGET_DEBUG_STACK)
15866 debug_stack_info (info);
15868 /* Write .extern for any function we will call to save and restore
15870 if (info->first_fp_reg_save < 64
15871 && !FP_SAVE_INLINE (info->first_fp_reg_save))
15872 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
15873 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
15874 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
15875 RESTORE_FP_SUFFIX);
15877 /* Write .extern for AIX common mode routines, if needed. */
15878 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
15880 fputs ("\t.extern __mulh\n", file);
15881 fputs ("\t.extern __mull\n", file);
15882 fputs ("\t.extern __divss\n", file);
15883 fputs ("\t.extern __divus\n", file);
15884 fputs ("\t.extern __quoss\n", file);
15885 fputs ("\t.extern __quous\n", file);
15886 common_mode_defined = 1;
15889 if (! HAVE_prologue)
15893 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
15894 the "toplevel" insn chain. */
15895 emit_note (NOTE_INSN_DELETED);
15896 rs6000_emit_prologue ();
15897 emit_note (NOTE_INSN_DELETED);
15899 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15903 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15905 INSN_ADDRESSES_NEW (insn, addr);
15910 if (TARGET_DEBUG_STACK)
15911 debug_rtx_list (get_insns (), 100);
15912 final (get_insns (), file, FALSE);
15916 rs6000_pic_labelno++;
15919 /* Emit function epilogue as insns.
15921 At present, dwarf2out_frame_debug_expr doesn't understand
15922 register restores, so we don't bother setting RTX_FRAME_RELATED_P
15923 anywhere in the epilogue. Most of the insns below would in any case
15924 need special notes to explain where r11 is in relation to the stack. */
15927 rs6000_emit_epilogue (int sibcall)
15929 rs6000_stack_t *info;
15930 int restoring_FPRs_inline;
15931 int using_load_multiple;
15932 int using_mtcr_multiple;
15933 int use_backchain_to_restore_sp;
15935 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
15936 rtx frame_reg_rtx = sp_reg_rtx;
15937 enum machine_mode reg_mode = Pmode;
15938 int reg_size = TARGET_32BIT ? 4 : 8;
15941 info = rs6000_stack_info ();
15943 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
15945 reg_mode = V2SImode;
15949 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
15950 && (!TARGET_SPE_ABI
15951 || info->spe_64bit_regs_used == 0)
15952 && info->first_gp_reg_save < 31
15953 && no_global_regs_above (info->first_gp_reg_save));
15954 restoring_FPRs_inline = (sibcall
15955 || current_function_calls_eh_return
15956 || info->first_fp_reg_save == 64
15957 || FP_SAVE_INLINE (info->first_fp_reg_save));
15958 use_backchain_to_restore_sp = (frame_pointer_needed
15959 || current_function_calls_alloca
15960 || info->total_size > 32767);
15961 using_mtcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
15962 || rs6000_cpu == PROCESSOR_PPC603
15963 || rs6000_cpu == PROCESSOR_PPC750
15966 if (WORLD_SAVE_P (info))
15970 const char *alloc_rname;
15973 /* eh_rest_world_r10 will return to the location saved in the LR
15974 stack slot (which is not likely to be our caller.)
15975 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
15976 rest_world is similar, except any R10 parameter is ignored.
15977 The exception-handling stuff that was here in 2.95 is no
15978 longer necessary. */
15982 + 32 - info->first_gp_reg_save
15983 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
15984 + 63 + 1 - info->first_fp_reg_save);
15986 strcpy (rname, ((current_function_calls_eh_return) ?
15987 "*eh_rest_world_r10" : "*rest_world"));
15988 alloc_rname = ggc_strdup (rname);
15991 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
15992 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
15993 gen_rtx_REG (Pmode,
15996 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
15997 /* The instruction pattern requires a clobber here;
15998 it is shared with the restVEC helper. */
16000 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
16003 /* CR register traditionally saved as CR2. */
16004 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
16005 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16006 GEN_INT (info->cr_save_offset));
16007 rtx mem = gen_frame_mem (reg_mode, addr);
16009 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16012 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16014 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
16015 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16016 GEN_INT (info->gp_save_offset
16018 rtx mem = gen_frame_mem (reg_mode, addr);
16020 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16022 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
16024 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
16025 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16026 GEN_INT (info->altivec_save_offset
16028 rtx mem = gen_frame_mem (V4SImode, addr);
16030 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16032 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
16034 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
16035 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16036 GEN_INT (info->fp_save_offset
16038 rtx mem = gen_frame_mem (DFmode, addr);
16040 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
16043 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
16045 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
16047 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
16049 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
16051 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
16052 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16057 /* Set sp_offset based on the stack push from the prologue. */
16058 if (info->total_size < 32767)
16059 sp_offset = info->total_size;
16061 /* Restore AltiVec registers if needed. */
16062 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
16066 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
16067 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
16069 rtx addr, areg, mem;
16071 areg = gen_rtx_REG (Pmode, 0);
16073 (areg, GEN_INT (info->altivec_save_offset
16075 + 16 * (i - info->first_altivec_reg_save)));
16077 /* AltiVec addressing mode is [reg+reg]. */
16078 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
16079 mem = gen_frame_mem (V4SImode, addr);
16081 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
16085 /* Restore VRSAVE if needed. */
16086 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
16087 && info->vrsave_mask != 0)
16089 rtx addr, mem, reg;
16091 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16092 GEN_INT (info->vrsave_save_offset + sp_offset));
16093 mem = gen_frame_mem (SImode, addr);
16094 reg = gen_rtx_REG (SImode, 12);
16095 emit_move_insn (reg, mem);
16097 emit_insn (generate_set_vrsave (reg, info, 1));
16102 /* If we have a frame pointer, a call to alloca, or a large stack
16103 frame, restore the old stack pointer using the backchain. Otherwise,
16104 we know what size to update it with. */
16105 if (use_backchain_to_restore_sp)
16107 /* Under V.4, don't reset the stack pointer until after we're done
16108 loading the saved registers. */
16109 if (DEFAULT_ABI == ABI_V4)
16110 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
16112 emit_move_insn (frame_reg_rtx,
16113 gen_rtx_MEM (Pmode, sp_reg_rtx));
16115 else if (info->push_p)
16117 if (DEFAULT_ABI == ABI_V4
16118 || current_function_calls_eh_return)
16119 sp_offset = info->total_size;
16122 emit_insn (TARGET_32BIT
16123 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16124 GEN_INT (info->total_size))
16125 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16126 GEN_INT (info->total_size)));
16130 /* Get the old lr if we saved it. */
16131 if (info->lr_save_p)
16133 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
16134 info->lr_save_offset + sp_offset);
16136 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
16139 /* Get the old cr if we saved it. */
16140 if (info->cr_save_p)
16142 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16143 GEN_INT (info->cr_save_offset + sp_offset));
16144 rtx mem = gen_frame_mem (SImode, addr);
16146 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
16149 /* Set LR here to try to overlap restores below. */
16150 if (info->lr_save_p)
16151 emit_move_insn (gen_rtx_REG (Pmode, LR_REGNO),
16152 gen_rtx_REG (Pmode, 0));
16154 /* Load exception handler data registers, if needed. */
16155 if (current_function_calls_eh_return)
16157 unsigned int i, regno;
16161 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16162 GEN_INT (sp_offset + 5 * reg_size));
16163 rtx mem = gen_frame_mem (reg_mode, addr);
16165 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
16172 regno = EH_RETURN_DATA_REGNO (i);
16173 if (regno == INVALID_REGNUM)
16176 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
16177 info->ehrd_offset + sp_offset
16178 + reg_size * (int) i);
16180 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
16184 /* Restore GPRs. This is done as a PARALLEL if we are using
16185 the load-multiple instructions. */
16186 if (using_load_multiple)
16189 p = rtvec_alloc (32 - info->first_gp_reg_save);
16190 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16192 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16193 GEN_INT (info->gp_save_offset
16196 rtx mem = gen_frame_mem (reg_mode, addr);
16199 gen_rtx_SET (VOIDmode,
16200 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16203 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16205 else if (TARGET_SPE_ABI
16206 && info->spe_64bit_regs_used != 0
16207 && info->first_gp_reg_save != 32)
16209 rtx spe_save_area_ptr;
16210 /* Determine whether we can address all of the registers that need
16211 to be saved with an offset from the stack pointer that fits in
16212 the small const field for SPE memory instructions. */
16213 int spe_regs_addressable_via_sp
16214 = SPE_CONST_OFFSET_OK(info->spe_gp_save_offset + sp_offset
16215 + (32 - info->first_gp_reg_save - 1) * reg_size);
16218 if (spe_regs_addressable_via_sp)
16220 spe_save_area_ptr = frame_reg_rtx;
16221 spe_offset = info->spe_gp_save_offset + sp_offset;
16225 /* Make r11 point to the start of the SPE save area. We worried about
16226 not clobbering it when we were saving registers in the prologue.
16227 There's no need to worry here because the static chain is passed
16228 anew to every function. */
16229 spe_save_area_ptr = gen_rtx_REG (Pmode, 11);
16231 emit_insn (gen_addsi3 (spe_save_area_ptr, frame_reg_rtx,
16232 GEN_INT (info->spe_gp_save_offset + sp_offset)));
16237 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16238 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16240 rtx offset, addr, mem;
16242 /* We're doing all this to ensure that the immediate offset
16243 fits into the immediate field of 'evldd'. */
16244 gcc_assert (SPE_CONST_OFFSET_OK (spe_offset + reg_size * i));
16246 offset = GEN_INT (spe_offset + reg_size * i);
16247 addr = gen_rtx_PLUS (Pmode, spe_save_area_ptr, offset);
16248 mem = gen_rtx_MEM (V2SImode, addr);
16250 emit_move_insn (gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
16255 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
16256 if (rs6000_reg_live_or_pic_offset_p (info->first_gp_reg_save + i))
16258 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16259 GEN_INT (info->gp_save_offset
16262 rtx mem = gen_frame_mem (reg_mode, addr);
16264 emit_move_insn (gen_rtx_REG (reg_mode,
16265 info->first_gp_reg_save + i), mem);
16268 /* Restore fpr's if we need to do it without calling a function. */
16269 if (restoring_FPRs_inline)
16270 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16271 if ((df_regs_ever_live_p (info->first_fp_reg_save+i)
16272 && ! call_used_regs[info->first_fp_reg_save+i]))
16275 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
16276 GEN_INT (info->fp_save_offset
16279 mem = gen_frame_mem (DFmode, addr);
16281 emit_move_insn (gen_rtx_REG (DFmode,
16282 info->first_fp_reg_save + i),
16286 /* If we saved cr, restore it here. Just those that were used. */
16287 if (info->cr_save_p)
16289 rtx r12_rtx = gen_rtx_REG (SImode, 12);
16292 if (using_mtcr_multiple)
16294 for (i = 0; i < 8; i++)
16295 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16297 gcc_assert (count);
16300 if (using_mtcr_multiple && count > 1)
16305 p = rtvec_alloc (count);
16308 for (i = 0; i < 8; i++)
16309 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16311 rtvec r = rtvec_alloc (2);
16312 RTVEC_ELT (r, 0) = r12_rtx;
16313 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
16314 RTVEC_ELT (p, ndx) =
16315 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
16316 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
16319 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
16320 gcc_assert (ndx == count);
16323 for (i = 0; i < 8; i++)
16324 if (df_regs_ever_live_p (CR0_REGNO+i) && ! call_used_regs[CR0_REGNO+i])
16326 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
16332 /* If this is V.4, unwind the stack pointer after all of the loads
16334 if (frame_reg_rtx != sp_reg_rtx)
16336 /* This blockage is needed so that sched doesn't decide to move
16337 the sp change before the register restores. */
16338 rs6000_emit_stack_tie ();
16340 && info->spe_64bit_regs_used != 0
16341 && info->first_gp_reg_save != 32)
16342 emit_insn (gen_addsi3 (sp_reg_rtx, gen_rtx_REG (Pmode, 11),
16343 GEN_INT (-(info->spe_gp_save_offset + sp_offset))));
16345 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
16347 else if (sp_offset != 0)
16348 emit_insn (TARGET_32BIT
16349 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
16350 GEN_INT (sp_offset))
16351 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
16352 GEN_INT (sp_offset)));
16354 if (current_function_calls_eh_return)
16356 rtx sa = EH_RETURN_STACKADJ_RTX;
16357 emit_insn (TARGET_32BIT
16358 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
16359 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
16365 if (! restoring_FPRs_inline)
16366 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
16368 p = rtvec_alloc (2);
16370 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
16371 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
16372 gen_rtx_REG (Pmode,
16375 /* If we have to restore more than two FP registers, branch to the
16376 restore function. It will return to our caller. */
16377 if (! restoring_FPRs_inline)
16381 const char *alloc_rname;
16383 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
16384 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
16385 alloc_rname = ggc_strdup (rname);
16386 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
16387 gen_rtx_SYMBOL_REF (Pmode,
16390 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
16393 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
16394 GEN_INT (info->fp_save_offset + 8*i));
16395 mem = gen_frame_mem (DFmode, addr);
16397 RTVEC_ELT (p, i+3) =
16398 gen_rtx_SET (VOIDmode,
16399 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
16404 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
16408 /* Write function epilogue. */
16411 rs6000_output_function_epilogue (FILE *file,
16412 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
16414 if (! HAVE_epilogue)
16416 rtx insn = get_last_insn ();
16417 /* If the last insn was a BARRIER, we don't have to write anything except
16418 the trace table. */
16419 if (GET_CODE (insn) == NOTE)
16420 insn = prev_nonnote_insn (insn);
16421 if (insn == 0 || GET_CODE (insn) != BARRIER)
16423 /* This is slightly ugly, but at least we don't have two
16424 copies of the epilogue-emitting code. */
16427 /* A NOTE_INSN_DELETED is supposed to be at the start
16428 and end of the "toplevel" insn chain. */
16429 emit_note (NOTE_INSN_DELETED);
16430 rs6000_emit_epilogue (FALSE);
16431 emit_note (NOTE_INSN_DELETED);
16433 /* Expand INSN_ADDRESSES so final() doesn't crash. */
16437 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
16439 INSN_ADDRESSES_NEW (insn, addr);
16444 if (TARGET_DEBUG_STACK)
16445 debug_rtx_list (get_insns (), 100);
16446 final (get_insns (), file, FALSE);
16452 macho_branch_islands ();
16453 /* Mach-O doesn't support labels at the end of objects, so if
16454 it looks like we might want one, insert a NOP. */
16456 rtx insn = get_last_insn ();
16459 && NOTE_KIND (insn) != NOTE_INSN_DELETED_LABEL)
16460 insn = PREV_INSN (insn);
16464 && NOTE_KIND (insn) == NOTE_INSN_DELETED_LABEL)))
16465 fputs ("\tnop\n", file);
16469 /* Output a traceback table here. See /usr/include/sys/debug.h for info
16472 We don't output a traceback table if -finhibit-size-directive was
16473 used. The documentation for -finhibit-size-directive reads
16474 ``don't output a @code{.size} assembler directive, or anything
16475 else that would cause trouble if the function is split in the
16476 middle, and the two halves are placed at locations far apart in
16477 memory.'' The traceback table has this property, since it
16478 includes the offset from the start of the function to the
16479 traceback table itself.
16481 System V.4 Powerpc's (and the embedded ABI derived from it) use a
16482 different traceback table. */
16483 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
16484 && rs6000_traceback != traceback_none && !current_function_is_thunk)
16486 const char *fname = NULL;
16487 const char *language_string = lang_hooks.name;
16488 int fixed_parms = 0, float_parms = 0, parm_info = 0;
16490 int optional_tbtab;
16491 rs6000_stack_t *info = rs6000_stack_info ();
16493 if (rs6000_traceback == traceback_full)
16494 optional_tbtab = 1;
16495 else if (rs6000_traceback == traceback_part)
16496 optional_tbtab = 0;
16498 optional_tbtab = !optimize_size && !TARGET_ELF;
16500 if (optional_tbtab)
16502 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
16503 while (*fname == '.') /* V.4 encodes . in the name */
16506 /* Need label immediately before tbtab, so we can compute
16507 its offset from the function start. */
16508 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16509 ASM_OUTPUT_LABEL (file, fname);
16512 /* The .tbtab pseudo-op can only be used for the first eight
16513 expressions, since it can't handle the possibly variable
16514 length fields that follow. However, if you omit the optional
16515 fields, the assembler outputs zeros for all optional fields
16516 anyways, giving each variable length field is minimum length
16517 (as defined in sys/debug.h). Thus we can not use the .tbtab
16518 pseudo-op at all. */
16520 /* An all-zero word flags the start of the tbtab, for debuggers
16521 that have to find it by searching forward from the entry
16522 point or from the current pc. */
16523 fputs ("\t.long 0\n", file);
16525 /* Tbtab format type. Use format type 0. */
16526 fputs ("\t.byte 0,", file);
16528 /* Language type. Unfortunately, there does not seem to be any
16529 official way to discover the language being compiled, so we
16530 use language_string.
16531 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
16532 Java is 13. Objective-C is 14. Objective-C++ isn't assigned
16533 a number, so for now use 9. */
16534 if (! strcmp (language_string, "GNU C"))
16536 else if (! strcmp (language_string, "GNU F77")
16537 || ! strcmp (language_string, "GNU F95"))
16539 else if (! strcmp (language_string, "GNU Pascal"))
16541 else if (! strcmp (language_string, "GNU Ada"))
16543 else if (! strcmp (language_string, "GNU C++")
16544 || ! strcmp (language_string, "GNU Objective-C++"))
16546 else if (! strcmp (language_string, "GNU Java"))
16548 else if (! strcmp (language_string, "GNU Objective-C"))
16551 gcc_unreachable ();
16552 fprintf (file, "%d,", i);
16554 /* 8 single bit fields: global linkage (not set for C extern linkage,
16555 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
16556 from start of procedure stored in tbtab, internal function, function
16557 has controlled storage, function has no toc, function uses fp,
16558 function logs/aborts fp operations. */
16559 /* Assume that fp operations are used if any fp reg must be saved. */
16560 fprintf (file, "%d,",
16561 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
16563 /* 6 bitfields: function is interrupt handler, name present in
16564 proc table, function calls alloca, on condition directives
16565 (controls stack walks, 3 bits), saves condition reg, saves
16567 /* The `function calls alloca' bit seems to be set whenever reg 31 is
16568 set up as a frame pointer, even when there is no alloca call. */
16569 fprintf (file, "%d,",
16570 ((optional_tbtab << 6)
16571 | ((optional_tbtab & frame_pointer_needed) << 5)
16572 | (info->cr_save_p << 1)
16573 | (info->lr_save_p)));
16575 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
16577 fprintf (file, "%d,",
16578 (info->push_p << 7) | (64 - info->first_fp_reg_save));
16580 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
16581 fprintf (file, "%d,", (32 - first_reg_to_save ()));
16583 if (optional_tbtab)
16585 /* Compute the parameter info from the function decl argument
16588 int next_parm_info_bit = 31;
16590 for (decl = DECL_ARGUMENTS (current_function_decl);
16591 decl; decl = TREE_CHAIN (decl))
16593 rtx parameter = DECL_INCOMING_RTL (decl);
16594 enum machine_mode mode = GET_MODE (parameter);
16596 if (GET_CODE (parameter) == REG)
16598 if (SCALAR_FLOAT_MODE_P (mode))
16618 gcc_unreachable ();
16621 /* If only one bit will fit, don't or in this entry. */
16622 if (next_parm_info_bit > 0)
16623 parm_info |= (bits << (next_parm_info_bit - 1));
16624 next_parm_info_bit -= 2;
16628 fixed_parms += ((GET_MODE_SIZE (mode)
16629 + (UNITS_PER_WORD - 1))
16631 next_parm_info_bit -= 1;
16637 /* Number of fixed point parameters. */
16638 /* This is actually the number of words of fixed point parameters; thus
16639 an 8 byte struct counts as 2; and thus the maximum value is 8. */
16640 fprintf (file, "%d,", fixed_parms);
16642 /* 2 bitfields: number of floating point parameters (7 bits), parameters
16644 /* This is actually the number of fp registers that hold parameters;
16645 and thus the maximum value is 13. */
16646 /* Set parameters on stack bit if parameters are not in their original
16647 registers, regardless of whether they are on the stack? Xlc
16648 seems to set the bit when not optimizing. */
16649 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
16651 if (! optional_tbtab)
16654 /* Optional fields follow. Some are variable length. */
16656 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
16657 11 double float. */
16658 /* There is an entry for each parameter in a register, in the order that
16659 they occur in the parameter list. Any intervening arguments on the
16660 stack are ignored. If the list overflows a long (max possible length
16661 34 bits) then completely leave off all elements that don't fit. */
16662 /* Only emit this long if there was at least one parameter. */
16663 if (fixed_parms || float_parms)
16664 fprintf (file, "\t.long %d\n", parm_info);
16666 /* Offset from start of code to tb table. */
16667 fputs ("\t.long ", file);
16668 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
16670 RS6000_OUTPUT_BASENAME (file, fname);
16672 assemble_name (file, fname);
16674 rs6000_output_function_entry (file, fname);
16677 /* Interrupt handler mask. */
16678 /* Omit this long, since we never set the interrupt handler bit
16681 /* Number of CTL (controlled storage) anchors. */
16682 /* Omit this long, since the has_ctl bit is never set above. */
16684 /* Displacement into stack of each CTL anchor. */
16685 /* Omit this list of longs, because there are no CTL anchors. */
16687 /* Length of function name. */
16690 fprintf (file, "\t.short %d\n", (int) strlen (fname));
16692 /* Function name. */
16693 assemble_string (fname, strlen (fname));
16695 /* Register for alloca automatic storage; this is always reg 31.
16696 Only emit this if the alloca bit was set above. */
16697 if (frame_pointer_needed)
16698 fputs ("\t.byte 31\n", file);
16700 fputs ("\t.align 2\n", file);
16704 /* A C compound statement that outputs the assembler code for a thunk
16705 function, used to implement C++ virtual function calls with
16706 multiple inheritance. The thunk acts as a wrapper around a virtual
16707 function, adjusting the implicit object parameter before handing
16708 control off to the real function.
16710 First, emit code to add the integer DELTA to the location that
16711 contains the incoming first argument. Assume that this argument
16712 contains a pointer, and is the one used to pass the `this' pointer
16713 in C++. This is the incoming argument *before* the function
16714 prologue, e.g. `%o0' on a sparc. The addition must preserve the
16715 values of all other incoming arguments.
16717 After the addition, emit code to jump to FUNCTION, which is a
16718 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
16719 not touch the return address. Hence returning from FUNCTION will
16720 return to whoever called the current `thunk'.
16722 The effect must be as if FUNCTION had been called directly with the
16723 adjusted first argument. This macro is responsible for emitting
16724 all of the code for a thunk function; output_function_prologue()
16725 and output_function_epilogue() are not invoked.
16727 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
16728 been extracted from it.) It might possibly be useful on some
16729 targets, but probably not.
16731 If you do not define this macro, the target-independent code in the
16732 C++ frontend will generate a less efficient heavyweight thunk that
16733 calls FUNCTION instead of jumping to it. The generic approach does
16734 not support varargs. */
16737 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
16738 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
16741 rtx this, insn, funexp;
16743 reload_completed = 1;
16744 epilogue_completed = 1;
16746 /* Mark the end of the (empty) prologue. */
16747 emit_note (NOTE_INSN_PROLOGUE_END);
16749 /* Find the "this" pointer. If the function returns a structure,
16750 the structure return pointer is in r3. */
16751 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
16752 this = gen_rtx_REG (Pmode, 4);
16754 this = gen_rtx_REG (Pmode, 3);
16756 /* Apply the constant offset, if required. */
16759 rtx delta_rtx = GEN_INT (delta);
16760 emit_insn (TARGET_32BIT
16761 ? gen_addsi3 (this, this, delta_rtx)
16762 : gen_adddi3 (this, this, delta_rtx));
16765 /* Apply the offset from the vtable, if required. */
16768 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
16769 rtx tmp = gen_rtx_REG (Pmode, 12);
16771 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
16772 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
16774 emit_insn (TARGET_32BIT
16775 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
16776 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
16777 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
16781 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
16783 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
16785 emit_insn (TARGET_32BIT
16786 ? gen_addsi3 (this, this, tmp)
16787 : gen_adddi3 (this, this, tmp));
16790 /* Generate a tail call to the target function. */
16791 if (!TREE_USED (function))
16793 assemble_external (function);
16794 TREE_USED (function) = 1;
16796 funexp = XEXP (DECL_RTL (function), 0);
16797 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
16800 if (MACHOPIC_INDIRECT)
16801 funexp = machopic_indirect_call_target (funexp);
16804 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
16805 generate sibcall RTL explicitly. */
16806 insn = emit_call_insn (
16807 gen_rtx_PARALLEL (VOIDmode,
16809 gen_rtx_CALL (VOIDmode,
16810 funexp, const0_rtx),
16811 gen_rtx_USE (VOIDmode, const0_rtx),
16812 gen_rtx_USE (VOIDmode,
16813 gen_rtx_REG (SImode,
16815 gen_rtx_RETURN (VOIDmode))));
16816 SIBLING_CALL_P (insn) = 1;
16819 /* Run just enough of rest_of_compilation to get the insns emitted.
16820 There's not really enough bulk here to make other passes such as
16821 instruction scheduling worth while. Note that use_thunk calls
16822 assemble_start_function and assemble_end_function. */
16823 insn = get_insns ();
16824 insn_locators_alloc ();
16825 shorten_branches (insn);
16826 final_start_function (insn, file, 1);
16827 final (insn, file, 1);
16828 final_end_function ();
16830 reload_completed = 0;
16831 epilogue_completed = 0;
16834 /* A quick summary of the various types of 'constant-pool tables'
16837 Target Flags Name One table per
16838 AIX (none) AIX TOC object file
16839 AIX -mfull-toc AIX TOC object file
16840 AIX -mminimal-toc AIX minimal TOC translation unit
16841 SVR4/EABI (none) SVR4 SDATA object file
16842 SVR4/EABI -fpic SVR4 pic object file
16843 SVR4/EABI -fPIC SVR4 PIC translation unit
16844 SVR4/EABI -mrelocatable EABI TOC function
16845 SVR4/EABI -maix AIX TOC object file
16846 SVR4/EABI -maix -mminimal-toc
16847 AIX minimal TOC translation unit
16849 Name Reg. Set by entries contains:
16850 made by addrs? fp? sum?
16852 AIX TOC 2 crt0 as Y option option
16853 AIX minimal TOC 30 prolog gcc Y Y option
16854 SVR4 SDATA 13 crt0 gcc N Y N
16855 SVR4 pic 30 prolog ld Y not yet N
16856 SVR4 PIC 30 prolog gcc Y option option
16857 EABI TOC 30 prolog gcc Y option option
16861 /* Hash functions for the hash table. */
16864 rs6000_hash_constant (rtx k)
16866 enum rtx_code code = GET_CODE (k);
16867 enum machine_mode mode = GET_MODE (k);
16868 unsigned result = (code << 3) ^ mode;
16869 const char *format;
16872 format = GET_RTX_FORMAT (code);
16873 flen = strlen (format);
16879 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
16882 if (mode != VOIDmode)
16883 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
16895 for (; fidx < flen; fidx++)
16896 switch (format[fidx])
16901 const char *str = XSTR (k, fidx);
16902 len = strlen (str);
16903 result = result * 613 + len;
16904 for (i = 0; i < len; i++)
16905 result = result * 613 + (unsigned) str[i];
16910 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
16914 result = result * 613 + (unsigned) XINT (k, fidx);
16917 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
16918 result = result * 613 + (unsigned) XWINT (k, fidx);
16922 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
16923 result = result * 613 + (unsigned) (XWINT (k, fidx)
16930 gcc_unreachable ();
16937 toc_hash_function (const void *hash_entry)
16939 const struct toc_hash_struct *thc =
16940 (const struct toc_hash_struct *) hash_entry;
16941 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
16944 /* Compare H1 and H2 for equivalence. */
16947 toc_hash_eq (const void *h1, const void *h2)
16949 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
16950 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
16952 if (((const struct toc_hash_struct *) h1)->key_mode
16953 != ((const struct toc_hash_struct *) h2)->key_mode)
16956 return rtx_equal_p (r1, r2);
16959 /* These are the names given by the C++ front-end to vtables, and
16960 vtable-like objects. Ideally, this logic should not be here;
16961 instead, there should be some programmatic way of inquiring as
16962 to whether or not an object is a vtable. */
16964 #define VTABLE_NAME_P(NAME) \
16965 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
16966 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
16967 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
16968 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
16969 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
16972 rs6000_output_symbol_ref (FILE *file, rtx x)
16974 /* Currently C++ toc references to vtables can be emitted before it
16975 is decided whether the vtable is public or private. If this is
16976 the case, then the linker will eventually complain that there is
16977 a reference to an unknown section. Thus, for vtables only,
16978 we emit the TOC reference to reference the symbol and not the
16980 const char *name = XSTR (x, 0);
16982 if (VTABLE_NAME_P (name))
16984 RS6000_OUTPUT_BASENAME (file, name);
16987 assemble_name (file, name);
16990 /* Output a TOC entry. We derive the entry name from what is being
16994 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
16997 const char *name = buf;
16998 const char *real_name;
17000 HOST_WIDE_INT offset = 0;
17002 gcc_assert (!TARGET_NO_TOC);
17004 /* When the linker won't eliminate them, don't output duplicate
17005 TOC entries (this happens on AIX if there is any kind of TOC,
17006 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
17008 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
17010 struct toc_hash_struct *h;
17013 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
17014 time because GGC is not initialized at that point. */
17015 if (toc_hash_table == NULL)
17016 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
17017 toc_hash_eq, NULL);
17019 h = ggc_alloc (sizeof (*h));
17021 h->key_mode = mode;
17022 h->labelno = labelno;
17024 found = htab_find_slot (toc_hash_table, h, 1);
17025 if (*found == NULL)
17027 else /* This is indeed a duplicate.
17028 Set this label equal to that label. */
17030 fputs ("\t.set ", file);
17031 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17032 fprintf (file, "%d,", labelno);
17033 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
17034 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
17040 /* If we're going to put a double constant in the TOC, make sure it's
17041 aligned properly when strict alignment is on. */
17042 if (GET_CODE (x) == CONST_DOUBLE
17043 && STRICT_ALIGNMENT
17044 && GET_MODE_BITSIZE (mode) >= 64
17045 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
17046 ASM_OUTPUT_ALIGN (file, 3);
17049 (*targetm.asm_out.internal_label) (file, "LC", labelno);
17051 /* Handle FP constants specially. Note that if we have a minimal
17052 TOC, things we put here aren't actually in the TOC, so we can allow
17054 if (GET_CODE (x) == CONST_DOUBLE &&
17055 (GET_MODE (x) == TFmode || GET_MODE (x) == TDmode))
17057 REAL_VALUE_TYPE rv;
17060 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17061 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17062 REAL_VALUE_TO_TARGET_DECIMAL128 (rv, k);
17064 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
17068 if (TARGET_MINIMAL_TOC)
17069 fputs (DOUBLE_INT_ASM_OP, file);
17071 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17072 k[0] & 0xffffffff, k[1] & 0xffffffff,
17073 k[2] & 0xffffffff, k[3] & 0xffffffff);
17074 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
17075 k[0] & 0xffffffff, k[1] & 0xffffffff,
17076 k[2] & 0xffffffff, k[3] & 0xffffffff);
17081 if (TARGET_MINIMAL_TOC)
17082 fputs ("\t.long ", file);
17084 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
17085 k[0] & 0xffffffff, k[1] & 0xffffffff,
17086 k[2] & 0xffffffff, k[3] & 0xffffffff);
17087 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
17088 k[0] & 0xffffffff, k[1] & 0xffffffff,
17089 k[2] & 0xffffffff, k[3] & 0xffffffff);
17093 else if (GET_CODE (x) == CONST_DOUBLE &&
17094 (GET_MODE (x) == DFmode || GET_MODE (x) == DDmode))
17096 REAL_VALUE_TYPE rv;
17099 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17101 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17102 REAL_VALUE_TO_TARGET_DECIMAL64 (rv, k);
17104 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
17108 if (TARGET_MINIMAL_TOC)
17109 fputs (DOUBLE_INT_ASM_OP, file);
17111 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17112 k[0] & 0xffffffff, k[1] & 0xffffffff);
17113 fprintf (file, "0x%lx%08lx\n",
17114 k[0] & 0xffffffff, k[1] & 0xffffffff);
17119 if (TARGET_MINIMAL_TOC)
17120 fputs ("\t.long ", file);
17122 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
17123 k[0] & 0xffffffff, k[1] & 0xffffffff);
17124 fprintf (file, "0x%lx,0x%lx\n",
17125 k[0] & 0xffffffff, k[1] & 0xffffffff);
17129 else if (GET_CODE (x) == CONST_DOUBLE &&
17130 (GET_MODE (x) == SFmode || GET_MODE (x) == SDmode))
17132 REAL_VALUE_TYPE rv;
17135 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
17136 if (DECIMAL_FLOAT_MODE_P (GET_MODE (x)))
17137 REAL_VALUE_TO_TARGET_DECIMAL32 (rv, l);
17139 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
17143 if (TARGET_MINIMAL_TOC)
17144 fputs (DOUBLE_INT_ASM_OP, file);
17146 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17147 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
17152 if (TARGET_MINIMAL_TOC)
17153 fputs ("\t.long ", file);
17155 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
17156 fprintf (file, "0x%lx\n", l & 0xffffffff);
17160 else if (GET_MODE (x) == VOIDmode
17161 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
17163 unsigned HOST_WIDE_INT low;
17164 HOST_WIDE_INT high;
17166 if (GET_CODE (x) == CONST_DOUBLE)
17168 low = CONST_DOUBLE_LOW (x);
17169 high = CONST_DOUBLE_HIGH (x);
17172 #if HOST_BITS_PER_WIDE_INT == 32
17175 high = (low & 0x80000000) ? ~0 : 0;
17179 low = INTVAL (x) & 0xffffffff;
17180 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
17184 /* TOC entries are always Pmode-sized, but since this
17185 is a bigendian machine then if we're putting smaller
17186 integer constants in the TOC we have to pad them.
17187 (This is still a win over putting the constants in
17188 a separate constant pool, because then we'd have
17189 to have both a TOC entry _and_ the actual constant.)
17191 For a 32-bit target, CONST_INT values are loaded and shifted
17192 entirely within `low' and can be stored in one TOC entry. */
17194 /* It would be easy to make this work, but it doesn't now. */
17195 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
17197 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
17199 #if HOST_BITS_PER_WIDE_INT == 32
17200 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
17201 POINTER_SIZE, &low, &high, 0);
17204 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
17205 high = (HOST_WIDE_INT) low >> 32;
17212 if (TARGET_MINIMAL_TOC)
17213 fputs (DOUBLE_INT_ASM_OP, file);
17215 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17216 (long) high & 0xffffffff, (long) low & 0xffffffff);
17217 fprintf (file, "0x%lx%08lx\n",
17218 (long) high & 0xffffffff, (long) low & 0xffffffff);
17223 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
17225 if (TARGET_MINIMAL_TOC)
17226 fputs ("\t.long ", file);
17228 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
17229 (long) high & 0xffffffff, (long) low & 0xffffffff);
17230 fprintf (file, "0x%lx,0x%lx\n",
17231 (long) high & 0xffffffff, (long) low & 0xffffffff);
17235 if (TARGET_MINIMAL_TOC)
17236 fputs ("\t.long ", file);
17238 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
17239 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
17245 if (GET_CODE (x) == CONST)
17247 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
17249 base = XEXP (XEXP (x, 0), 0);
17250 offset = INTVAL (XEXP (XEXP (x, 0), 1));
17253 switch (GET_CODE (base))
17256 name = XSTR (base, 0);
17260 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
17261 CODE_LABEL_NUMBER (XEXP (base, 0)));
17265 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
17269 gcc_unreachable ();
17272 real_name = (*targetm.strip_name_encoding) (name);
17273 if (TARGET_MINIMAL_TOC)
17274 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
17277 fprintf (file, "\t.tc %s", real_name);
17280 fprintf (file, ".N" HOST_WIDE_INT_PRINT_UNSIGNED, - offset);
17282 fprintf (file, ".P" HOST_WIDE_INT_PRINT_UNSIGNED, offset);
17284 fputs ("[TC],", file);
17287 /* Currently C++ toc references to vtables can be emitted before it
17288 is decided whether the vtable is public or private. If this is
17289 the case, then the linker will eventually complain that there is
17290 a TOC reference to an unknown section. Thus, for vtables only,
17291 we emit the TOC reference to reference the symbol and not the
17293 if (VTABLE_NAME_P (name))
17295 RS6000_OUTPUT_BASENAME (file, name);
17297 fprintf (file, HOST_WIDE_INT_PRINT_DEC, offset);
17298 else if (offset > 0)
17299 fprintf (file, "+" HOST_WIDE_INT_PRINT_DEC, offset);
17302 output_addr_const (file, x);
17306 /* Output an assembler pseudo-op to write an ASCII string of N characters
17307 starting at P to FILE.
17309 On the RS/6000, we have to do this using the .byte operation and
17310 write out special characters outside the quoted string.
17311 Also, the assembler is broken; very long strings are truncated,
17312 so we must artificially break them up early. */
17315 output_ascii (FILE *file, const char *p, int n)
17318 int i, count_string;
17319 const char *for_string = "\t.byte \"";
17320 const char *for_decimal = "\t.byte ";
17321 const char *to_close = NULL;
17324 for (i = 0; i < n; i++)
17327 if (c >= ' ' && c < 0177)
17330 fputs (for_string, file);
17333 /* Write two quotes to get one. */
17341 for_decimal = "\"\n\t.byte ";
17345 if (count_string >= 512)
17347 fputs (to_close, file);
17349 for_string = "\t.byte \"";
17350 for_decimal = "\t.byte ";
17358 fputs (for_decimal, file);
17359 fprintf (file, "%d", c);
17361 for_string = "\n\t.byte \"";
17362 for_decimal = ", ";
17368 /* Now close the string if we have written one. Then end the line. */
17370 fputs (to_close, file);
17373 /* Generate a unique section name for FILENAME for a section type
17374 represented by SECTION_DESC. Output goes into BUF.
17376 SECTION_DESC can be any string, as long as it is different for each
17377 possible section type.
17379 We name the section in the same manner as xlc. The name begins with an
17380 underscore followed by the filename (after stripping any leading directory
17381 names) with the last period replaced by the string SECTION_DESC. If
17382 FILENAME does not contain a period, SECTION_DESC is appended to the end of
17386 rs6000_gen_section_name (char **buf, const char *filename,
17387 const char *section_desc)
17389 const char *q, *after_last_slash, *last_period = 0;
17393 after_last_slash = filename;
17394 for (q = filename; *q; q++)
17397 after_last_slash = q + 1;
17398 else if (*q == '.')
17402 len = strlen (after_last_slash) + strlen (section_desc) + 2;
17403 *buf = (char *) xmalloc (len);
17408 for (q = after_last_slash; *q; q++)
17410 if (q == last_period)
17412 strcpy (p, section_desc);
17413 p += strlen (section_desc);
17417 else if (ISALNUM (*q))
17421 if (last_period == 0)
17422 strcpy (p, section_desc);
17427 /* Emit profile function. */
17430 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
17432 /* Non-standard profiling for kernels, which just saves LR then calls
17433 _mcount without worrying about arg saves. The idea is to change
17434 the function prologue as little as possible as it isn't easy to
17435 account for arg save/restore code added just for _mcount. */
17436 if (TARGET_PROFILE_KERNEL)
17439 if (DEFAULT_ABI == ABI_AIX)
17441 #ifndef NO_PROFILE_COUNTERS
17442 # define NO_PROFILE_COUNTERS 0
17444 if (NO_PROFILE_COUNTERS)
17445 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
17449 const char *label_name;
17452 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17453 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
17454 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
17456 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
17460 else if (DEFAULT_ABI == ABI_DARWIN)
17462 const char *mcount_name = RS6000_MCOUNT;
17463 int caller_addr_regno = LR_REGNO;
17465 /* Be conservative and always set this, at least for now. */
17466 current_function_uses_pic_offset_table = 1;
17469 /* For PIC code, set up a stub and collect the caller's address
17470 from r0, which is where the prologue puts it. */
17471 if (MACHOPIC_INDIRECT
17472 && current_function_uses_pic_offset_table)
17473 caller_addr_regno = 0;
17475 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
17477 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
17481 /* Write function profiler code. */
17484 output_function_profiler (FILE *file, int labelno)
17488 switch (DEFAULT_ABI)
17491 gcc_unreachable ();
17496 warning (0, "no profiling of 64-bit code for this ABI");
17499 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
17500 fprintf (file, "\tmflr %s\n", reg_names[0]);
17501 if (NO_PROFILE_COUNTERS)
17503 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17504 reg_names[0], reg_names[1]);
17506 else if (TARGET_SECURE_PLT && flag_pic)
17508 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
17509 reg_names[0], reg_names[1]);
17510 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17511 asm_fprintf (file, "\t{cau|addis} %s,%s,",
17512 reg_names[12], reg_names[12]);
17513 assemble_name (file, buf);
17514 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
17515 assemble_name (file, buf);
17516 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
17518 else if (flag_pic == 1)
17520 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
17521 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17522 reg_names[0], reg_names[1]);
17523 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
17524 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
17525 assemble_name (file, buf);
17526 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
17528 else if (flag_pic > 1)
17530 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17531 reg_names[0], reg_names[1]);
17532 /* Now, we need to get the address of the label. */
17533 fputs ("\tbcl 20,31,1f\n\t.long ", file);
17534 assemble_name (file, buf);
17535 fputs ("-.\n1:", file);
17536 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
17537 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
17538 reg_names[0], reg_names[11]);
17539 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
17540 reg_names[0], reg_names[0], reg_names[11]);
17544 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
17545 assemble_name (file, buf);
17546 fputs ("@ha\n", file);
17547 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
17548 reg_names[0], reg_names[1]);
17549 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
17550 assemble_name (file, buf);
17551 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
17554 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
17555 fprintf (file, "\tbl %s%s\n",
17556 RS6000_MCOUNT, flag_pic ? "@plt" : "");
17561 if (!TARGET_PROFILE_KERNEL)
17563 /* Don't do anything, done in output_profile_hook (). */
17567 gcc_assert (!TARGET_32BIT);
17569 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
17570 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
17572 if (cfun->static_chain_decl != NULL)
17574 asm_fprintf (file, "\tstd %s,24(%s)\n",
17575 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17576 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17577 asm_fprintf (file, "\tld %s,24(%s)\n",
17578 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
17581 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
17589 /* The following variable value is the last issued insn. */
17591 static rtx last_scheduled_insn;
17593 /* The following variable helps to balance issuing of load and
17594 store instructions */
17596 static int load_store_pendulum;
17598 /* Power4 load update and store update instructions are cracked into a
17599 load or store and an integer insn which are executed in the same cycle.
17600 Branches have their own dispatch slot which does not count against the
17601 GCC issue rate, but it changes the program flow so there are no other
17602 instructions to issue in this cycle. */
17605 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
17606 int verbose ATTRIBUTE_UNUSED,
17607 rtx insn, int more)
17609 last_scheduled_insn = insn;
17610 if (GET_CODE (PATTERN (insn)) == USE
17611 || GET_CODE (PATTERN (insn)) == CLOBBER)
17613 cached_can_issue_more = more;
17614 return cached_can_issue_more;
17617 if (insn_terminates_group_p (insn, current_group))
17619 cached_can_issue_more = 0;
17620 return cached_can_issue_more;
17623 /* If no reservation, but reach here */
17624 if (recog_memoized (insn) < 0)
17627 if (rs6000_sched_groups)
17629 if (is_microcoded_insn (insn))
17630 cached_can_issue_more = 0;
17631 else if (is_cracked_insn (insn))
17632 cached_can_issue_more = more > 2 ? more - 2 : 0;
17634 cached_can_issue_more = more - 1;
17636 return cached_can_issue_more;
17639 if (rs6000_cpu_attr == CPU_CELL && is_nonpipeline_insn (insn))
17642 cached_can_issue_more = more - 1;
17643 return cached_can_issue_more;
17646 /* Adjust the cost of a scheduling dependency. Return the new cost of
17647 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
17650 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
17652 enum attr_type attr_type;
17654 if (! recog_memoized (insn))
17657 switch (REG_NOTE_KIND (link))
17661 /* Data dependency; DEP_INSN writes a register that INSN reads
17662 some cycles later. */
17664 /* Separate a load from a narrower, dependent store. */
17665 if (rs6000_sched_groups
17666 && GET_CODE (PATTERN (insn)) == SET
17667 && GET_CODE (PATTERN (dep_insn)) == SET
17668 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
17669 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
17670 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
17671 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
17674 attr_type = get_attr_type (insn);
17679 /* Tell the first scheduling pass about the latency between
17680 a mtctr and bctr (and mtlr and br/blr). The first
17681 scheduling pass will not know about this latency since
17682 the mtctr instruction, which has the latency associated
17683 to it, will be generated by reload. */
17684 return TARGET_POWER ? 5 : 4;
17686 /* Leave some extra cycles between a compare and its
17687 dependent branch, to inhibit expensive mispredicts. */
17688 if ((rs6000_cpu_attr == CPU_PPC603
17689 || rs6000_cpu_attr == CPU_PPC604
17690 || rs6000_cpu_attr == CPU_PPC604E
17691 || rs6000_cpu_attr == CPU_PPC620
17692 || rs6000_cpu_attr == CPU_PPC630
17693 || rs6000_cpu_attr == CPU_PPC750
17694 || rs6000_cpu_attr == CPU_PPC7400
17695 || rs6000_cpu_attr == CPU_PPC7450
17696 || rs6000_cpu_attr == CPU_POWER4
17697 || rs6000_cpu_attr == CPU_POWER5
17698 || rs6000_cpu_attr == CPU_CELL)
17699 && recog_memoized (dep_insn)
17700 && (INSN_CODE (dep_insn) >= 0))
17702 switch (get_attr_type (dep_insn))
17706 case TYPE_DELAYED_COMPARE:
17707 case TYPE_IMUL_COMPARE:
17708 case TYPE_LMUL_COMPARE:
17709 case TYPE_FPCOMPARE:
17710 case TYPE_CR_LOGICAL:
17711 case TYPE_DELAYED_CR:
17720 case TYPE_STORE_UX:
17722 case TYPE_FPSTORE_U:
17723 case TYPE_FPSTORE_UX:
17724 if ((rs6000_cpu == PROCESSOR_POWER6)
17725 && recog_memoized (dep_insn)
17726 && (INSN_CODE (dep_insn) >= 0))
17729 if (GET_CODE (PATTERN (insn)) != SET)
17730 /* If this happens, we have to extend this to schedule
17731 optimally. Return default for now. */
17734 /* Adjust the cost for the case where the value written
17735 by a fixed point operation is used as the address
17736 gen value on a store. */
17737 switch (get_attr_type (dep_insn))
17744 if (! store_data_bypass_p (dep_insn, insn))
17748 case TYPE_LOAD_EXT:
17749 case TYPE_LOAD_EXT_U:
17750 case TYPE_LOAD_EXT_UX:
17751 case TYPE_VAR_SHIFT_ROTATE:
17752 case TYPE_VAR_DELAYED_COMPARE:
17754 if (! store_data_bypass_p (dep_insn, insn))
17760 case TYPE_FAST_COMPARE:
17763 case TYPE_INSERT_WORD:
17764 case TYPE_INSERT_DWORD:
17765 case TYPE_FPLOAD_U:
17766 case TYPE_FPLOAD_UX:
17768 case TYPE_STORE_UX:
17769 case TYPE_FPSTORE_U:
17770 case TYPE_FPSTORE_UX:
17772 if (! store_data_bypass_p (dep_insn, insn))
17780 case TYPE_IMUL_COMPARE:
17781 case TYPE_LMUL_COMPARE:
17783 if (! store_data_bypass_p (dep_insn, insn))
17789 if (! store_data_bypass_p (dep_insn, insn))
17795 if (! store_data_bypass_p (dep_insn, insn))
17808 case TYPE_LOAD_EXT:
17809 case TYPE_LOAD_EXT_U:
17810 case TYPE_LOAD_EXT_UX:
17811 if ((rs6000_cpu == PROCESSOR_POWER6)
17812 && recog_memoized (dep_insn)
17813 && (INSN_CODE (dep_insn) >= 0))
17816 /* Adjust the cost for the case where the value written
17817 by a fixed point instruction is used within the address
17818 gen portion of a subsequent load(u)(x) */
17819 switch (get_attr_type (dep_insn))
17826 if (set_to_load_agen (dep_insn, insn))
17830 case TYPE_LOAD_EXT:
17831 case TYPE_LOAD_EXT_U:
17832 case TYPE_LOAD_EXT_UX:
17833 case TYPE_VAR_SHIFT_ROTATE:
17834 case TYPE_VAR_DELAYED_COMPARE:
17836 if (set_to_load_agen (dep_insn, insn))
17842 case TYPE_FAST_COMPARE:
17845 case TYPE_INSERT_WORD:
17846 case TYPE_INSERT_DWORD:
17847 case TYPE_FPLOAD_U:
17848 case TYPE_FPLOAD_UX:
17850 case TYPE_STORE_UX:
17851 case TYPE_FPSTORE_U:
17852 case TYPE_FPSTORE_UX:
17854 if (set_to_load_agen (dep_insn, insn))
17862 case TYPE_IMUL_COMPARE:
17863 case TYPE_LMUL_COMPARE:
17865 if (set_to_load_agen (dep_insn, insn))
17871 if (set_to_load_agen (dep_insn, insn))
17877 if (set_to_load_agen (dep_insn, insn))
17888 if ((rs6000_cpu == PROCESSOR_POWER6)
17889 && recog_memoized (dep_insn)
17890 && (INSN_CODE (dep_insn) >= 0)
17891 && (get_attr_type (dep_insn) == TYPE_MFFGPR))
17898 /* Fall out to return default cost. */
17902 case REG_DEP_OUTPUT:
17903 /* Output dependency; DEP_INSN writes a register that INSN writes some
17905 if ((rs6000_cpu == PROCESSOR_POWER6)
17906 && recog_memoized (dep_insn)
17907 && (INSN_CODE (dep_insn) >= 0))
17909 attr_type = get_attr_type (insn);
17914 if (get_attr_type (dep_insn) == TYPE_FP)
17918 if (get_attr_type (dep_insn) == TYPE_MFFGPR)
17926 /* Anti dependency; DEP_INSN reads a register that INSN writes some
17931 gcc_unreachable ();
17937 /* The function returns a true if INSN is microcoded.
17938 Return false otherwise. */
17941 is_microcoded_insn (rtx insn)
17943 if (!insn || !INSN_P (insn)
17944 || GET_CODE (PATTERN (insn)) == USE
17945 || GET_CODE (PATTERN (insn)) == CLOBBER)
17948 if (rs6000_cpu_attr == CPU_CELL)
17949 return get_attr_cell_micro (insn) == CELL_MICRO_ALWAYS;
17951 if (rs6000_sched_groups)
17953 enum attr_type type = get_attr_type (insn);
17954 if (type == TYPE_LOAD_EXT_U
17955 || type == TYPE_LOAD_EXT_UX
17956 || type == TYPE_LOAD_UX
17957 || type == TYPE_STORE_UX
17958 || type == TYPE_MFCR)
17965 /* The function returns true if INSN is cracked into 2 instructions
17966 by the processor (and therefore occupies 2 issue slots). */
17969 is_cracked_insn (rtx insn)
17971 if (!insn || !INSN_P (insn)
17972 || GET_CODE (PATTERN (insn)) == USE
17973 || GET_CODE (PATTERN (insn)) == CLOBBER)
17976 if (rs6000_sched_groups)
17978 enum attr_type type = get_attr_type (insn);
17979 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
17980 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
17981 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
17982 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
17983 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
17984 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
17985 || type == TYPE_IDIV || type == TYPE_LDIV
17986 || type == TYPE_INSERT_WORD)
17993 /* The function returns true if INSN can be issued only from
17994 the branch slot. */
17997 is_branch_slot_insn (rtx insn)
17999 if (!insn || !INSN_P (insn)
18000 || GET_CODE (PATTERN (insn)) == USE
18001 || GET_CODE (PATTERN (insn)) == CLOBBER)
18004 if (rs6000_sched_groups)
18006 enum attr_type type = get_attr_type (insn);
18007 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
18015 /* The function returns true if out_inst sets a value that is
18016 used in the address generation computation of in_insn */
18018 set_to_load_agen (rtx out_insn, rtx in_insn)
18020 rtx out_set, in_set;
18022 /* For performance reasons, only handle the simple case where
18023 both loads are a single_set. */
18024 out_set = single_set (out_insn);
18027 in_set = single_set (in_insn);
18029 return reg_mentioned_p (SET_DEST (out_set), SET_SRC (in_set));
18035 /* The function returns true if the target storage location of
18036 out_insn is adjacent to the target storage location of in_insn */
18037 /* Return 1 if memory locations are adjacent. */
18040 adjacent_mem_locations (rtx insn1, rtx insn2)
18043 rtx a = get_store_dest (PATTERN (insn1));
18044 rtx b = get_store_dest (PATTERN (insn2));
18046 if ((GET_CODE (XEXP (a, 0)) == REG
18047 || (GET_CODE (XEXP (a, 0)) == PLUS
18048 && GET_CODE (XEXP (XEXP (a, 0), 1)) == CONST_INT))
18049 && (GET_CODE (XEXP (b, 0)) == REG
18050 || (GET_CODE (XEXP (b, 0)) == PLUS
18051 && GET_CODE (XEXP (XEXP (b, 0), 1)) == CONST_INT)))
18053 HOST_WIDE_INT val0 = 0, val1 = 0;
18057 if (GET_CODE (XEXP (a, 0)) == PLUS)
18059 reg0 = XEXP (XEXP (a, 0), 0);
18060 val0 = INTVAL (XEXP (XEXP (a, 0), 1));
18063 reg0 = XEXP (a, 0);
18065 if (GET_CODE (XEXP (b, 0)) == PLUS)
18067 reg1 = XEXP (XEXP (b, 0), 0);
18068 val1 = INTVAL (XEXP (XEXP (b, 0), 1));
18071 reg1 = XEXP (b, 0);
18073 val_diff = val1 - val0;
18075 return ((REGNO (reg0) == REGNO (reg1))
18076 && (val_diff == INTVAL (MEM_SIZE (a))
18077 || val_diff == -INTVAL (MEM_SIZE (b))));
18083 /* A C statement (sans semicolon) to update the integer scheduling
18084 priority INSN_PRIORITY (INSN). Increase the priority to execute the
18085 INSN earlier, reduce the priority to execute INSN later. Do not
18086 define this macro if you do not need to adjust the scheduling
18087 priorities of insns. */
18090 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
18092 /* On machines (like the 750) which have asymmetric integer units,
18093 where one integer unit can do multiply and divides and the other
18094 can't, reduce the priority of multiply/divide so it is scheduled
18095 before other integer operations. */
18098 if (! INSN_P (insn))
18101 if (GET_CODE (PATTERN (insn)) == USE)
18104 switch (rs6000_cpu_attr) {
18106 switch (get_attr_type (insn))
18113 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
18114 priority, priority);
18115 if (priority >= 0 && priority < 0x01000000)
18122 if (insn_must_be_first_in_group (insn)
18123 && reload_completed
18124 && current_sched_info->sched_max_insns_priority
18125 && rs6000_sched_restricted_insns_priority)
18128 /* Prioritize insns that can be dispatched only in the first
18130 if (rs6000_sched_restricted_insns_priority == 1)
18131 /* Attach highest priority to insn. This means that in
18132 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
18133 precede 'priority' (critical path) considerations. */
18134 return current_sched_info->sched_max_insns_priority;
18135 else if (rs6000_sched_restricted_insns_priority == 2)
18136 /* Increase priority of insn by a minimal amount. This means that in
18137 haifa-sched.c:ready_sort(), only 'priority' (critical path)
18138 considerations precede dispatch-slot restriction considerations. */
18139 return (priority + 1);
18142 if (rs6000_cpu == PROCESSOR_POWER6
18143 && ((load_store_pendulum == -2 && is_load_insn (insn))
18144 || (load_store_pendulum == 2 && is_store_insn (insn))))
18145 /* Attach highest priority to insn if the scheduler has just issued two
18146 stores and this instruction is a load, or two loads and this instruction
18147 is a store. Power6 wants loads and stores scheduled alternately
18149 return current_sched_info->sched_max_insns_priority;
18154 /* Return true if the instruction is nonpipelined on the Cell. */
18156 is_nonpipeline_insn (rtx insn)
18158 enum attr_type type;
18159 if (!insn || !INSN_P (insn)
18160 || GET_CODE (PATTERN (insn)) == USE
18161 || GET_CODE (PATTERN (insn)) == CLOBBER)
18164 type = get_attr_type (insn);
18165 if (type == TYPE_IMUL
18166 || type == TYPE_IMUL2
18167 || type == TYPE_IMUL3
18168 || type == TYPE_LMUL
18169 || type == TYPE_IDIV
18170 || type == TYPE_LDIV
18171 || type == TYPE_SDIV
18172 || type == TYPE_DDIV
18173 || type == TYPE_SSQRT
18174 || type == TYPE_DSQRT
18175 || type == TYPE_MFCR
18176 || type == TYPE_MFCRF
18177 || type == TYPE_MFJMPR)
18185 /* Return how many instructions the machine can issue per cycle. */
18188 rs6000_issue_rate (void)
18190 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
18191 if (!reload_completed)
18194 switch (rs6000_cpu_attr) {
18195 case CPU_RIOS1: /* ? */
18197 case CPU_PPC601: /* ? */
18222 /* Return how many instructions to look ahead for better insn
18226 rs6000_use_sched_lookahead (void)
18228 if (rs6000_cpu_attr == CPU_PPC8540)
18230 if (rs6000_cpu_attr == CPU_CELL)
18231 return (reload_completed ? 8 : 0);
18235 /* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */
18237 rs6000_use_sched_lookahead_guard (rtx insn)
18239 if (rs6000_cpu_attr != CPU_CELL)
18242 if (insn == NULL_RTX || !INSN_P (insn))
18245 if (!reload_completed
18246 || is_nonpipeline_insn (insn)
18247 || is_microcoded_insn (insn))
18253 /* Determine is PAT refers to memory. */
18256 is_mem_ref (rtx pat)
18262 if (GET_CODE (pat) == MEM)
18265 /* Recursively process the pattern. */
18266 fmt = GET_RTX_FORMAT (GET_CODE (pat));
18268 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
18271 ret |= is_mem_ref (XEXP (pat, i));
18272 else if (fmt[i] == 'E')
18273 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
18274 ret |= is_mem_ref (XVECEXP (pat, i, j));
18280 /* Determine if PAT is a PATTERN of a load insn. */
18283 is_load_insn1 (rtx pat)
18285 if (!pat || pat == NULL_RTX)
18288 if (GET_CODE (pat) == SET)
18289 return is_mem_ref (SET_SRC (pat));
18291 if (GET_CODE (pat) == PARALLEL)
18295 for (i = 0; i < XVECLEN (pat, 0); i++)
18296 if (is_load_insn1 (XVECEXP (pat, 0, i)))
18303 /* Determine if INSN loads from memory. */
18306 is_load_insn (rtx insn)
18308 if (!insn || !INSN_P (insn))
18311 if (GET_CODE (insn) == CALL_INSN)
18314 return is_load_insn1 (PATTERN (insn));
18317 /* Determine if PAT is a PATTERN of a store insn. */
18320 is_store_insn1 (rtx pat)
18322 if (!pat || pat == NULL_RTX)
18325 if (GET_CODE (pat) == SET)
18326 return is_mem_ref (SET_DEST (pat));
18328 if (GET_CODE (pat) == PARALLEL)
18332 for (i = 0; i < XVECLEN (pat, 0); i++)
18333 if (is_store_insn1 (XVECEXP (pat, 0, i)))
18340 /* Determine if INSN stores to memory. */
18343 is_store_insn (rtx insn)
18345 if (!insn || !INSN_P (insn))
18348 return is_store_insn1 (PATTERN (insn));
18351 /* Return the dest of a store insn. */
18354 get_store_dest (rtx pat)
18356 gcc_assert (is_store_insn1 (pat));
18358 if (GET_CODE (pat) == SET)
18359 return SET_DEST (pat);
18360 else if (GET_CODE (pat) == PARALLEL)
18364 for (i = 0; i < XVECLEN (pat, 0); i++)
18366 rtx inner_pat = XVECEXP (pat, 0, i);
18367 if (GET_CODE (inner_pat) == SET
18368 && is_mem_ref (SET_DEST (inner_pat)))
18372 /* We shouldn't get here, because we should have either a simple
18373 store insn or a store with update which are covered above. */
18377 /* Returns whether the dependence between INSN and NEXT is considered
18378 costly by the given target. */
18381 rs6000_is_costly_dependence (dep_t dep, int cost, int distance)
18386 /* If the flag is not enabled - no dependence is considered costly;
18387 allow all dependent insns in the same group.
18388 This is the most aggressive option. */
18389 if (rs6000_sched_costly_dep == no_dep_costly)
18392 /* If the flag is set to 1 - a dependence is always considered costly;
18393 do not allow dependent instructions in the same group.
18394 This is the most conservative option. */
18395 if (rs6000_sched_costly_dep == all_deps_costly)
18398 insn = DEP_PRO (dep);
18399 next = DEP_CON (dep);
18401 if (rs6000_sched_costly_dep == store_to_load_dep_costly
18402 && is_load_insn (next)
18403 && is_store_insn (insn))
18404 /* Prevent load after store in the same group. */
18407 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
18408 && is_load_insn (next)
18409 && is_store_insn (insn)
18410 && DEP_TYPE (dep) == REG_DEP_TRUE)
18411 /* Prevent load after store in the same group if it is a true
18415 /* The flag is set to X; dependences with latency >= X are considered costly,
18416 and will not be scheduled in the same group. */
18417 if (rs6000_sched_costly_dep <= max_dep_latency
18418 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
18424 /* Return the next insn after INSN that is found before TAIL is reached,
18425 skipping any "non-active" insns - insns that will not actually occupy
18426 an issue slot. Return NULL_RTX if such an insn is not found. */
18429 get_next_active_insn (rtx insn, rtx tail)
18431 if (insn == NULL_RTX || insn == tail)
18436 insn = NEXT_INSN (insn);
18437 if (insn == NULL_RTX || insn == tail)
18442 || (NONJUMP_INSN_P (insn)
18443 && GET_CODE (PATTERN (insn)) != USE
18444 && GET_CODE (PATTERN (insn)) != CLOBBER
18445 && INSN_CODE (insn) != CODE_FOR_stack_tie))
18451 /* We are about to begin issuing insns for this clock cycle. */
18454 rs6000_sched_reorder (FILE *dump ATTRIBUTE_UNUSED, int sched_verbose,
18455 rtx *ready ATTRIBUTE_UNUSED,
18456 int *pn_ready ATTRIBUTE_UNUSED,
18457 int clock_var ATTRIBUTE_UNUSED)
18459 int n_ready = *pn_ready;
18462 fprintf (dump, "// rs6000_sched_reorder :\n");
18464 /* Reorder the ready list, if the second to last ready insn
18465 is a nonepipeline insn. */
18466 if (rs6000_cpu_attr == CPU_CELL && n_ready > 1)
18468 if (is_nonpipeline_insn (ready[n_ready - 1])
18469 && (recog_memoized (ready[n_ready - 2]) > 0))
18470 /* Simply swap first two insns. */
18472 rtx tmp = ready[n_ready - 1];
18473 ready[n_ready - 1] = ready[n_ready - 2];
18474 ready[n_ready - 2] = tmp;
18478 if (rs6000_cpu == PROCESSOR_POWER6)
18479 load_store_pendulum = 0;
18481 return rs6000_issue_rate ();
18484 /* Like rs6000_sched_reorder, but called after issuing each insn. */
18487 rs6000_sched_reorder2 (FILE *dump, int sched_verbose, rtx *ready,
18488 int *pn_ready, int clock_var ATTRIBUTE_UNUSED)
18491 fprintf (dump, "// rs6000_sched_reorder2 :\n");
18493 /* For Power6, we need to handle some special cases to try and keep the
18494 store queue from overflowing and triggering expensive flushes.
18496 This code monitors how load and store instructions are being issued
18497 and skews the ready list one way or the other to increase the likelihood
18498 that a desired instruction is issued at the proper time.
18500 A couple of things are done. First, we maintain a "load_store_pendulum"
18501 to track the current state of load/store issue.
18503 - If the pendulum is at zero, then no loads or stores have been
18504 issued in the current cycle so we do nothing.
18506 - If the pendulum is 1, then a single load has been issued in this
18507 cycle and we attempt to locate another load in the ready list to
18510 - If the pendulum is -2, then two stores have already been
18511 issued in this cycle, so we increase the priority of the first load
18512 in the ready list to increase it's likelihood of being chosen first
18515 - If the pendulum is -1, then a single store has been issued in this
18516 cycle and we attempt to locate another store in the ready list to
18517 issue with it, preferring a store to an adjacent memory location to
18518 facilitate store pairing in the store queue.
18520 - If the pendulum is 2, then two loads have already been
18521 issued in this cycle, so we increase the priority of the first store
18522 in the ready list to increase it's likelihood of being chosen first
18525 - If the pendulum < -2 or > 2, then do nothing.
18527 Note: This code covers the most common scenarios. There exist non
18528 load/store instructions which make use of the LSU and which
18529 would need to be accounted for to strictly model the behavior
18530 of the machine. Those instructions are currently unaccounted
18531 for to help minimize compile time overhead of this code.
18533 if (rs6000_cpu == PROCESSOR_POWER6 && last_scheduled_insn)
18539 if (is_store_insn (last_scheduled_insn))
18540 /* Issuing a store, swing the load_store_pendulum to the left */
18541 load_store_pendulum--;
18542 else if (is_load_insn (last_scheduled_insn))
18543 /* Issuing a load, swing the load_store_pendulum to the right */
18544 load_store_pendulum++;
18546 return cached_can_issue_more;
18548 /* If the pendulum is balanced, or there is only one instruction on
18549 the ready list, then all is well, so return. */
18550 if ((load_store_pendulum == 0) || (*pn_ready <= 1))
18551 return cached_can_issue_more;
18553 if (load_store_pendulum == 1)
18555 /* A load has been issued in this cycle. Scan the ready list
18556 for another load to issue with it */
18561 if (is_load_insn (ready[pos]))
18563 /* Found a load. Move it to the head of the ready list,
18564 and adjust it's priority so that it is more likely to
18567 for (i=pos; i<*pn_ready-1; i++)
18568 ready[i] = ready[i + 1];
18569 ready[*pn_ready-1] = tmp;
18570 if INSN_PRIORITY_KNOWN (tmp)
18571 INSN_PRIORITY (tmp)++;
18577 else if (load_store_pendulum == -2)
18579 /* Two stores have been issued in this cycle. Increase the
18580 priority of the first load in the ready list to favor it for
18581 issuing in the next cycle. */
18586 if (is_load_insn (ready[pos])
18587 && INSN_PRIORITY_KNOWN (ready[pos]))
18589 INSN_PRIORITY (ready[pos])++;
18591 /* Adjust the pendulum to account for the fact that a load
18592 was found and increased in priority. This is to prevent
18593 increasing the priority of multiple loads */
18594 load_store_pendulum--;
18601 else if (load_store_pendulum == -1)
18603 /* A store has been issued in this cycle. Scan the ready list for
18604 another store to issue with it, preferring a store to an adjacent
18606 int first_store_pos = -1;
18612 if (is_store_insn (ready[pos]))
18614 /* Maintain the index of the first store found on the
18616 if (first_store_pos == -1)
18617 first_store_pos = pos;
18619 if (is_store_insn (last_scheduled_insn)
18620 && adjacent_mem_locations (last_scheduled_insn,ready[pos]))
18622 /* Found an adjacent store. Move it to the head of the
18623 ready list, and adjust it's priority so that it is
18624 more likely to stay there */
18626 for (i=pos; i<*pn_ready-1; i++)
18627 ready[i] = ready[i + 1];
18628 ready[*pn_ready-1] = tmp;
18629 if INSN_PRIORITY_KNOWN (tmp)
18630 INSN_PRIORITY (tmp)++;
18631 first_store_pos = -1;
18639 if (first_store_pos >= 0)
18641 /* An adjacent store wasn't found, but a non-adjacent store was,
18642 so move the non-adjacent store to the front of the ready
18643 list, and adjust its priority so that it is more likely to
18645 tmp = ready[first_store_pos];
18646 for (i=first_store_pos; i<*pn_ready-1; i++)
18647 ready[i] = ready[i + 1];
18648 ready[*pn_ready-1] = tmp;
18649 if INSN_PRIORITY_KNOWN (tmp)
18650 INSN_PRIORITY (tmp)++;
18653 else if (load_store_pendulum == 2)
18655 /* Two loads have been issued in this cycle. Increase the priority
18656 of the first store in the ready list to favor it for issuing in
18662 if (is_store_insn (ready[pos])
18663 && INSN_PRIORITY_KNOWN (ready[pos]))
18665 INSN_PRIORITY (ready[pos])++;
18667 /* Adjust the pendulum to account for the fact that a store
18668 was found and increased in priority. This is to prevent
18669 increasing the priority of multiple stores */
18670 load_store_pendulum++;
18679 return cached_can_issue_more;
18682 /* Return whether the presence of INSN causes a dispatch group termination
18683 of group WHICH_GROUP.
18685 If WHICH_GROUP == current_group, this function will return true if INSN
18686 causes the termination of the current group (i.e, the dispatch group to
18687 which INSN belongs). This means that INSN will be the last insn in the
18688 group it belongs to.
18690 If WHICH_GROUP == previous_group, this function will return true if INSN
18691 causes the termination of the previous group (i.e, the dispatch group that
18692 precedes the group to which INSN belongs). This means that INSN will be
18693 the first insn in the group it belongs to). */
18696 insn_terminates_group_p (rtx insn, enum group_termination which_group)
18703 first = insn_must_be_first_in_group (insn);
18704 last = insn_must_be_last_in_group (insn);
18709 if (which_group == current_group)
18711 else if (which_group == previous_group)
18719 insn_must_be_first_in_group (rtx insn)
18721 enum attr_type type;
18724 || insn == NULL_RTX
18725 || GET_CODE (insn) == NOTE
18726 || GET_CODE (PATTERN (insn)) == USE
18727 || GET_CODE (PATTERN (insn)) == CLOBBER)
18730 switch (rs6000_cpu)
18732 case PROCESSOR_POWER5:
18733 if (is_cracked_insn (insn))
18735 case PROCESSOR_POWER4:
18736 if (is_microcoded_insn (insn))
18739 if (!rs6000_sched_groups)
18742 type = get_attr_type (insn);
18749 case TYPE_DELAYED_CR:
18750 case TYPE_CR_LOGICAL:
18764 case PROCESSOR_POWER6:
18765 type = get_attr_type (insn);
18769 case TYPE_INSERT_DWORD:
18773 case TYPE_VAR_SHIFT_ROTATE:
18780 case TYPE_INSERT_WORD:
18781 case TYPE_DELAYED_COMPARE:
18782 case TYPE_IMUL_COMPARE:
18783 case TYPE_LMUL_COMPARE:
18784 case TYPE_FPCOMPARE:
18795 case TYPE_LOAD_EXT_UX:
18797 case TYPE_STORE_UX:
18798 case TYPE_FPLOAD_U:
18799 case TYPE_FPLOAD_UX:
18800 case TYPE_FPSTORE_U:
18801 case TYPE_FPSTORE_UX:
18815 insn_must_be_last_in_group (rtx insn)
18817 enum attr_type type;
18820 || insn == NULL_RTX
18821 || GET_CODE (insn) == NOTE
18822 || GET_CODE (PATTERN (insn)) == USE
18823 || GET_CODE (PATTERN (insn)) == CLOBBER)
18826 switch (rs6000_cpu) {
18827 case PROCESSOR_POWER4:
18828 case PROCESSOR_POWER5:
18829 if (is_microcoded_insn (insn))
18832 if (is_branch_slot_insn (insn))
18836 case PROCESSOR_POWER6:
18837 type = get_attr_type (insn);
18844 case TYPE_VAR_SHIFT_ROTATE:
18851 case TYPE_DELAYED_COMPARE:
18852 case TYPE_IMUL_COMPARE:
18853 case TYPE_LMUL_COMPARE:
18854 case TYPE_FPCOMPARE:
18875 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
18876 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
18879 is_costly_group (rtx *group_insns, rtx next_insn)
18882 int issue_rate = rs6000_issue_rate ();
18884 for (i = 0; i < issue_rate; i++)
18886 sd_iterator_def sd_it;
18888 rtx insn = group_insns[i];
18893 FOR_EACH_DEP (insn, SD_LIST_FORW, sd_it, dep)
18895 rtx next = DEP_CON (dep);
18897 if (next == next_insn
18898 && rs6000_is_costly_dependence (dep, dep_cost (dep), 0))
18906 /* Utility of the function redefine_groups.
18907 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
18908 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
18909 to keep it "far" (in a separate group) from GROUP_INSNS, following
18910 one of the following schemes, depending on the value of the flag
18911 -minsert_sched_nops = X:
18912 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
18913 in order to force NEXT_INSN into a separate group.
18914 (2) X < sched_finish_regroup_exact: insert exactly X nops.
18915 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
18916 insertion (has a group just ended, how many vacant issue slots remain in the
18917 last group, and how many dispatch groups were encountered so far). */
18920 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
18921 rtx next_insn, bool *group_end, int can_issue_more,
18926 int issue_rate = rs6000_issue_rate ();
18927 bool end = *group_end;
18930 if (next_insn == NULL_RTX)
18931 return can_issue_more;
18933 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
18934 return can_issue_more;
18936 force = is_costly_group (group_insns, next_insn);
18938 return can_issue_more;
18940 if (sched_verbose > 6)
18941 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
18942 *group_count ,can_issue_more);
18944 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
18947 can_issue_more = 0;
18949 /* Since only a branch can be issued in the last issue_slot, it is
18950 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
18951 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
18952 in this case the last nop will start a new group and the branch
18953 will be forced to the new group. */
18954 if (can_issue_more && !is_branch_slot_insn (next_insn))
18957 while (can_issue_more > 0)
18960 emit_insn_before (nop, next_insn);
18968 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
18970 int n_nops = rs6000_sched_insert_nops;
18972 /* Nops can't be issued from the branch slot, so the effective
18973 issue_rate for nops is 'issue_rate - 1'. */
18974 if (can_issue_more == 0)
18975 can_issue_more = issue_rate;
18977 if (can_issue_more == 0)
18979 can_issue_more = issue_rate - 1;
18982 for (i = 0; i < issue_rate; i++)
18984 group_insns[i] = 0;
18991 emit_insn_before (nop, next_insn);
18992 if (can_issue_more == issue_rate - 1) /* new group begins */
18995 if (can_issue_more == 0)
18997 can_issue_more = issue_rate - 1;
19000 for (i = 0; i < issue_rate; i++)
19002 group_insns[i] = 0;
19008 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
19011 /* Is next_insn going to start a new group? */
19014 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19015 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19016 || (can_issue_more < issue_rate &&
19017 insn_terminates_group_p (next_insn, previous_group)));
19018 if (*group_end && end)
19021 if (sched_verbose > 6)
19022 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
19023 *group_count, can_issue_more);
19024 return can_issue_more;
19027 return can_issue_more;
19030 /* This function tries to synch the dispatch groups that the compiler "sees"
19031 with the dispatch groups that the processor dispatcher is expected to
19032 form in practice. It tries to achieve this synchronization by forcing the
19033 estimated processor grouping on the compiler (as opposed to the function
19034 'pad_goups' which tries to force the scheduler's grouping on the processor).
19036 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
19037 examines the (estimated) dispatch groups that will be formed by the processor
19038 dispatcher. It marks these group boundaries to reflect the estimated
19039 processor grouping, overriding the grouping that the scheduler had marked.
19040 Depending on the value of the flag '-minsert-sched-nops' this function can
19041 force certain insns into separate groups or force a certain distance between
19042 them by inserting nops, for example, if there exists a "costly dependence"
19045 The function estimates the group boundaries that the processor will form as
19046 follows: It keeps track of how many vacant issue slots are available after
19047 each insn. A subsequent insn will start a new group if one of the following
19049 - no more vacant issue slots remain in the current dispatch group.
19050 - only the last issue slot, which is the branch slot, is vacant, but the next
19051 insn is not a branch.
19052 - only the last 2 or less issue slots, including the branch slot, are vacant,
19053 which means that a cracked insn (which occupies two issue slots) can't be
19054 issued in this group.
19055 - less than 'issue_rate' slots are vacant, and the next insn always needs to
19056 start a new group. */
19059 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19061 rtx insn, next_insn;
19063 int can_issue_more;
19066 int group_count = 0;
19070 issue_rate = rs6000_issue_rate ();
19071 group_insns = alloca (issue_rate * sizeof (rtx));
19072 for (i = 0; i < issue_rate; i++)
19074 group_insns[i] = 0;
19076 can_issue_more = issue_rate;
19078 insn = get_next_active_insn (prev_head_insn, tail);
19081 while (insn != NULL_RTX)
19083 slot = (issue_rate - can_issue_more);
19084 group_insns[slot] = insn;
19086 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19087 if (insn_terminates_group_p (insn, current_group))
19088 can_issue_more = 0;
19090 next_insn = get_next_active_insn (insn, tail);
19091 if (next_insn == NULL_RTX)
19092 return group_count + 1;
19094 /* Is next_insn going to start a new group? */
19096 = (can_issue_more == 0
19097 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
19098 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
19099 || (can_issue_more < issue_rate &&
19100 insn_terminates_group_p (next_insn, previous_group)));
19102 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
19103 next_insn, &group_end, can_issue_more,
19109 can_issue_more = 0;
19110 for (i = 0; i < issue_rate; i++)
19112 group_insns[i] = 0;
19116 if (GET_MODE (next_insn) == TImode && can_issue_more)
19117 PUT_MODE (next_insn, VOIDmode);
19118 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
19119 PUT_MODE (next_insn, TImode);
19122 if (can_issue_more == 0)
19123 can_issue_more = issue_rate;
19126 return group_count;
19129 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
19130 dispatch group boundaries that the scheduler had marked. Pad with nops
19131 any dispatch groups which have vacant issue slots, in order to force the
19132 scheduler's grouping on the processor dispatcher. The function
19133 returns the number of dispatch groups found. */
19136 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
19138 rtx insn, next_insn;
19141 int can_issue_more;
19143 int group_count = 0;
19145 /* Initialize issue_rate. */
19146 issue_rate = rs6000_issue_rate ();
19147 can_issue_more = issue_rate;
19149 insn = get_next_active_insn (prev_head_insn, tail);
19150 next_insn = get_next_active_insn (insn, tail);
19152 while (insn != NULL_RTX)
19155 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
19157 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
19159 if (next_insn == NULL_RTX)
19164 /* If the scheduler had marked group termination at this location
19165 (between insn and next_indn), and neither insn nor next_insn will
19166 force group termination, pad the group with nops to force group
19169 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
19170 && !insn_terminates_group_p (insn, current_group)
19171 && !insn_terminates_group_p (next_insn, previous_group))
19173 if (!is_branch_slot_insn (next_insn))
19176 while (can_issue_more)
19179 emit_insn_before (nop, next_insn);
19184 can_issue_more = issue_rate;
19189 next_insn = get_next_active_insn (insn, tail);
19192 return group_count;
19195 /* We're beginning a new block. Initialize data structures as necessary. */
19198 rs6000_sched_init (FILE *dump ATTRIBUTE_UNUSED,
19199 int sched_verbose ATTRIBUTE_UNUSED,
19200 int max_ready ATTRIBUTE_UNUSED)
19202 last_scheduled_insn = NULL_RTX;
19203 load_store_pendulum = 0;
19206 /* The following function is called at the end of scheduling BB.
19207 After reload, it inserts nops at insn group bundling. */
19210 rs6000_sched_finish (FILE *dump, int sched_verbose)
19215 fprintf (dump, "=== Finishing schedule.\n");
19217 if (reload_completed && rs6000_sched_groups)
19219 if (rs6000_sched_insert_nops == sched_finish_none)
19222 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
19223 n_groups = pad_groups (dump, sched_verbose,
19224 current_sched_info->prev_head,
19225 current_sched_info->next_tail);
19227 n_groups = redefine_groups (dump, sched_verbose,
19228 current_sched_info->prev_head,
19229 current_sched_info->next_tail);
19231 if (sched_verbose >= 6)
19233 fprintf (dump, "ngroups = %d\n", n_groups);
19234 print_rtl (dump, current_sched_info->prev_head);
19235 fprintf (dump, "Done finish_sched\n");
19240 /* Length in units of the trampoline for entering a nested function. */
19243 rs6000_trampoline_size (void)
19247 switch (DEFAULT_ABI)
19250 gcc_unreachable ();
19253 ret = (TARGET_32BIT) ? 12 : 24;
19258 ret = (TARGET_32BIT) ? 40 : 48;
19265 /* Emit RTL insns to initialize the variable parts of a trampoline.
19266 FNADDR is an RTX for the address of the function's pure code.
19267 CXT is an RTX for the static chain value for the function. */
19270 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
19272 int regsize = (TARGET_32BIT) ? 4 : 8;
19273 rtx ctx_reg = force_reg (Pmode, cxt);
19275 switch (DEFAULT_ABI)
19278 gcc_unreachable ();
19280 /* Macros to shorten the code expansions below. */
19281 #define MEM_DEREF(addr) gen_rtx_MEM (Pmode, memory_address (Pmode, addr))
19282 #define MEM_PLUS(addr,offset) \
19283 gen_rtx_MEM (Pmode, memory_address (Pmode, plus_constant (addr, offset)))
19285 /* Under AIX, just build the 3 word function descriptor */
19288 rtx fn_reg = gen_reg_rtx (Pmode);
19289 rtx toc_reg = gen_reg_rtx (Pmode);
19290 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
19291 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
19292 emit_move_insn (MEM_DEREF (addr), fn_reg);
19293 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
19294 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
19298 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
19301 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__trampoline_setup"),
19302 FALSE, VOIDmode, 4,
19304 GEN_INT (rs6000_trampoline_size ()), SImode,
19314 /* Table of valid machine attributes. */
19316 const struct attribute_spec rs6000_attribute_table[] =
19318 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
19319 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
19320 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19321 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
19322 { "ms_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19323 { "gcc_struct", 0, 0, false, false, false, rs6000_handle_struct_attribute },
19324 #ifdef SUBTARGET_ATTRIBUTE_TABLE
19325 SUBTARGET_ATTRIBUTE_TABLE,
19327 { NULL, 0, 0, false, false, false, NULL }
19330 /* Handle the "altivec" attribute. The attribute may have
19331 arguments as follows:
19333 __attribute__((altivec(vector__)))
19334 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
19335 __attribute__((altivec(bool__))) (always followed by 'unsigned')
19337 and may appear more than once (e.g., 'vector bool char') in a
19338 given declaration. */
19341 rs6000_handle_altivec_attribute (tree *node,
19342 tree name ATTRIBUTE_UNUSED,
19344 int flags ATTRIBUTE_UNUSED,
19345 bool *no_add_attrs)
19347 tree type = *node, result = NULL_TREE;
19348 enum machine_mode mode;
19351 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
19352 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
19353 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
19356 while (POINTER_TYPE_P (type)
19357 || TREE_CODE (type) == FUNCTION_TYPE
19358 || TREE_CODE (type) == METHOD_TYPE
19359 || TREE_CODE (type) == ARRAY_TYPE)
19360 type = TREE_TYPE (type);
19362 mode = TYPE_MODE (type);
19364 /* Check for invalid AltiVec type qualifiers. */
19365 if (type == long_unsigned_type_node || type == long_integer_type_node)
19368 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
19369 else if (rs6000_warn_altivec_long)
19370 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
19372 else if (type == long_long_unsigned_type_node
19373 || type == long_long_integer_type_node)
19374 error ("use of %<long long%> in AltiVec types is invalid");
19375 else if (type == double_type_node)
19376 error ("use of %<double%> in AltiVec types is invalid");
19377 else if (type == long_double_type_node)
19378 error ("use of %<long double%> in AltiVec types is invalid");
19379 else if (type == boolean_type_node)
19380 error ("use of boolean types in AltiVec types is invalid");
19381 else if (TREE_CODE (type) == COMPLEX_TYPE)
19382 error ("use of %<complex%> in AltiVec types is invalid");
19383 else if (DECIMAL_FLOAT_MODE_P (mode))
19384 error ("use of decimal floating point types in AltiVec types is invalid");
19386 switch (altivec_type)
19389 unsigned_p = TYPE_UNSIGNED (type);
19393 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
19396 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
19399 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
19401 case SFmode: result = V4SF_type_node; break;
19402 /* If the user says 'vector int bool', we may be handed the 'bool'
19403 attribute _before_ the 'vector' attribute, and so select the
19404 proper type in the 'b' case below. */
19405 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
19413 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
19414 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
19415 case QImode: case V16QImode: result = bool_V16QI_type_node;
19422 case V8HImode: result = pixel_V8HI_type_node;
19428 if (result && result != type && TYPE_READONLY (type))
19429 result = build_qualified_type (result, TYPE_QUAL_CONST);
19431 *no_add_attrs = true; /* No need to hang on to the attribute. */
19434 *node = reconstruct_complex_type (*node, result);
19439 /* AltiVec defines four built-in scalar types that serve as vector
19440 elements; we must teach the compiler how to mangle them. */
19442 static const char *
19443 rs6000_mangle_type (const_tree type)
19445 type = TYPE_MAIN_VARIANT (type);
19447 if (TREE_CODE (type) != VOID_TYPE && TREE_CODE (type) != BOOLEAN_TYPE
19448 && TREE_CODE (type) != INTEGER_TYPE && TREE_CODE (type) != REAL_TYPE)
19451 if (type == bool_char_type_node) return "U6__boolc";
19452 if (type == bool_short_type_node) return "U6__bools";
19453 if (type == pixel_type_node) return "u7__pixel";
19454 if (type == bool_int_type_node) return "U6__booli";
19456 /* Mangle IBM extended float long double as `g' (__float128) on
19457 powerpc*-linux where long-double-64 previously was the default. */
19458 if (TYPE_MAIN_VARIANT (type) == long_double_type_node
19460 && TARGET_LONG_DOUBLE_128
19461 && !TARGET_IEEEQUAD)
19464 /* For all other types, use normal C++ mangling. */
19468 /* Handle a "longcall" or "shortcall" attribute; arguments as in
19469 struct attribute_spec.handler. */
19472 rs6000_handle_longcall_attribute (tree *node, tree name,
19473 tree args ATTRIBUTE_UNUSED,
19474 int flags ATTRIBUTE_UNUSED,
19475 bool *no_add_attrs)
19477 if (TREE_CODE (*node) != FUNCTION_TYPE
19478 && TREE_CODE (*node) != FIELD_DECL
19479 && TREE_CODE (*node) != TYPE_DECL)
19481 warning (OPT_Wattributes, "%qs attribute only applies to functions",
19482 IDENTIFIER_POINTER (name));
19483 *no_add_attrs = true;
19489 /* Set longcall attributes on all functions declared when
19490 rs6000_default_long_calls is true. */
19492 rs6000_set_default_type_attributes (tree type)
19494 if (rs6000_default_long_calls
19495 && (TREE_CODE (type) == FUNCTION_TYPE
19496 || TREE_CODE (type) == METHOD_TYPE))
19497 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
19499 TYPE_ATTRIBUTES (type));
19502 darwin_set_default_type_attributes (type);
19506 /* Return a reference suitable for calling a function with the
19507 longcall attribute. */
19510 rs6000_longcall_ref (rtx call_ref)
19512 const char *call_name;
19515 if (GET_CODE (call_ref) != SYMBOL_REF)
19518 /* System V adds '.' to the internal name, so skip them. */
19519 call_name = XSTR (call_ref, 0);
19520 if (*call_name == '.')
19522 while (*call_name == '.')
19525 node = get_identifier (call_name);
19526 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
19529 return force_reg (Pmode, call_ref);
19532 #ifndef TARGET_USE_MS_BITFIELD_LAYOUT
19533 #define TARGET_USE_MS_BITFIELD_LAYOUT 0
19536 /* Handle a "ms_struct" or "gcc_struct" attribute; arguments as in
19537 struct attribute_spec.handler. */
19539 rs6000_handle_struct_attribute (tree *node, tree name,
19540 tree args ATTRIBUTE_UNUSED,
19541 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs)
19544 if (DECL_P (*node))
19546 if (TREE_CODE (*node) == TYPE_DECL)
19547 type = &TREE_TYPE (*node);
19552 if (!(type && (TREE_CODE (*type) == RECORD_TYPE
19553 || TREE_CODE (*type) == UNION_TYPE)))
19555 warning (OPT_Wattributes, "%qs attribute ignored", IDENTIFIER_POINTER (name));
19556 *no_add_attrs = true;
19559 else if ((is_attribute_p ("ms_struct", name)
19560 && lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (*type)))
19561 || ((is_attribute_p ("gcc_struct", name)
19562 && lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (*type)))))
19564 warning (OPT_Wattributes, "%qs incompatible attribute ignored",
19565 IDENTIFIER_POINTER (name));
19566 *no_add_attrs = true;
19573 rs6000_ms_bitfield_layout_p (const_tree record_type)
19575 return (TARGET_USE_MS_BITFIELD_LAYOUT &&
19576 !lookup_attribute ("gcc_struct", TYPE_ATTRIBUTES (record_type)))
19577 || lookup_attribute ("ms_struct", TYPE_ATTRIBUTES (record_type));
19580 #ifdef USING_ELFOS_H
19582 /* A get_unnamed_section callback, used for switching to toc_section. */
19585 rs6000_elf_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
19587 if (DEFAULT_ABI == ABI_AIX
19588 && TARGET_MINIMAL_TOC
19589 && !TARGET_RELOCATABLE)
19591 if (!toc_initialized)
19593 toc_initialized = 1;
19594 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19595 (*targetm.asm_out.internal_label) (asm_out_file, "LCTOC", 0);
19596 fprintf (asm_out_file, "\t.tc ");
19597 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1[TC],");
19598 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19599 fprintf (asm_out_file, "\n");
19601 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19602 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19603 fprintf (asm_out_file, " = .+32768\n");
19606 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19608 else if (DEFAULT_ABI == ABI_AIX && !TARGET_RELOCATABLE)
19609 fprintf (asm_out_file, "%s\n", TOC_SECTION_ASM_OP);
19612 fprintf (asm_out_file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
19613 if (!toc_initialized)
19615 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (asm_out_file, "LCTOC1");
19616 fprintf (asm_out_file, " = .+32768\n");
19617 toc_initialized = 1;
19622 /* Implement TARGET_ASM_INIT_SECTIONS. */
19625 rs6000_elf_asm_init_sections (void)
19628 = get_unnamed_section (0, rs6000_elf_output_toc_section_asm_op, NULL);
19631 = get_unnamed_section (SECTION_WRITE, output_section_asm_op,
19632 SDATA2_SECTION_ASM_OP);
19635 /* Implement TARGET_SELECT_RTX_SECTION. */
19638 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
19639 unsigned HOST_WIDE_INT align)
19641 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
19642 return toc_section;
19644 return default_elf_select_rtx_section (mode, x, align);
19647 /* For a SYMBOL_REF, set generic flags and then perform some
19648 target-specific processing.
19650 When the AIX ABI is requested on a non-AIX system, replace the
19651 function name with the real name (with a leading .) rather than the
19652 function descriptor name. This saves a lot of overriding code to
19653 read the prefixes. */
19656 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
19658 default_encode_section_info (decl, rtl, first);
19661 && TREE_CODE (decl) == FUNCTION_DECL
19663 && DEFAULT_ABI == ABI_AIX)
19665 rtx sym_ref = XEXP (rtl, 0);
19666 size_t len = strlen (XSTR (sym_ref, 0));
19667 char *str = alloca (len + 2);
19669 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
19670 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
19675 compare_section_name (const char *section, const char *template)
19679 len = strlen (template);
19680 return (strncmp (section, template, len) == 0
19681 && (section[len] == 0 || section[len] == '.'));
19685 rs6000_elf_in_small_data_p (const_tree decl)
19687 if (rs6000_sdata == SDATA_NONE)
19690 /* We want to merge strings, so we never consider them small data. */
19691 if (TREE_CODE (decl) == STRING_CST)
19694 /* Functions are never in the small data area. */
19695 if (TREE_CODE (decl) == FUNCTION_DECL)
19698 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
19700 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
19701 if (compare_section_name (section, ".sdata")
19702 || compare_section_name (section, ".sdata2")
19703 || compare_section_name (section, ".gnu.linkonce.s")
19704 || compare_section_name (section, ".sbss")
19705 || compare_section_name (section, ".sbss2")
19706 || compare_section_name (section, ".gnu.linkonce.sb")
19707 || strcmp (section, ".PPC.EMB.sdata0") == 0
19708 || strcmp (section, ".PPC.EMB.sbss0") == 0)
19713 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
19716 && (unsigned HOST_WIDE_INT) size <= g_switch_value
19717 /* If it's not public, and we're not going to reference it there,
19718 there's no need to put it in the small data section. */
19719 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
19726 #endif /* USING_ELFOS_H */
19728 /* Implement TARGET_USE_BLOCKS_FOR_CONSTANT_P. */
19731 rs6000_use_blocks_for_constant_p (enum machine_mode mode, const_rtx x)
19733 return !ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode);
19736 /* Return a REG that occurs in ADDR with coefficient 1.
19737 ADDR can be effectively incremented by incrementing REG.
19739 r0 is special and we must not select it as an address
19740 register by this routine since our caller will try to
19741 increment the returned register via an "la" instruction. */
19744 find_addr_reg (rtx addr)
19746 while (GET_CODE (addr) == PLUS)
19748 if (GET_CODE (XEXP (addr, 0)) == REG
19749 && REGNO (XEXP (addr, 0)) != 0)
19750 addr = XEXP (addr, 0);
19751 else if (GET_CODE (XEXP (addr, 1)) == REG
19752 && REGNO (XEXP (addr, 1)) != 0)
19753 addr = XEXP (addr, 1);
19754 else if (CONSTANT_P (XEXP (addr, 0)))
19755 addr = XEXP (addr, 1);
19756 else if (CONSTANT_P (XEXP (addr, 1)))
19757 addr = XEXP (addr, 0);
19759 gcc_unreachable ();
19761 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
19766 rs6000_fatal_bad_address (rtx op)
19768 fatal_insn ("bad address", op);
19773 static tree branch_island_list = 0;
19775 /* Remember to generate a branch island for far calls to the given
19779 add_compiler_branch_island (tree label_name, tree function_name,
19782 tree branch_island = build_tree_list (function_name, label_name);
19783 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
19784 TREE_CHAIN (branch_island) = branch_island_list;
19785 branch_island_list = branch_island;
19788 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
19789 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
19790 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
19791 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
19793 /* Generate far-jump branch islands for everything on the
19794 branch_island_list. Invoked immediately after the last instruction
19795 of the epilogue has been emitted; the branch-islands must be
19796 appended to, and contiguous with, the function body. Mach-O stubs
19797 are generated in machopic_output_stub(). */
19800 macho_branch_islands (void)
19803 tree branch_island;
19805 for (branch_island = branch_island_list;
19807 branch_island = TREE_CHAIN (branch_island))
19809 const char *label =
19810 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
19812 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
19813 char name_buf[512];
19814 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
19815 if (name[0] == '*' || name[0] == '&')
19816 strcpy (name_buf, name+1);
19820 strcpy (name_buf+1, name);
19822 strcpy (tmp_buf, "\n");
19823 strcat (tmp_buf, label);
19824 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19825 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19826 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19827 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19830 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
19831 strcat (tmp_buf, label);
19832 strcat (tmp_buf, "_pic\n");
19833 strcat (tmp_buf, label);
19834 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
19836 strcat (tmp_buf, "\taddis r11,r11,ha16(");
19837 strcat (tmp_buf, name_buf);
19838 strcat (tmp_buf, " - ");
19839 strcat (tmp_buf, label);
19840 strcat (tmp_buf, "_pic)\n");
19842 strcat (tmp_buf, "\tmtlr r0\n");
19844 strcat (tmp_buf, "\taddi r12,r11,lo16(");
19845 strcat (tmp_buf, name_buf);
19846 strcat (tmp_buf, " - ");
19847 strcat (tmp_buf, label);
19848 strcat (tmp_buf, "_pic)\n");
19850 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
19854 strcat (tmp_buf, ":\nlis r12,hi16(");
19855 strcat (tmp_buf, name_buf);
19856 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
19857 strcat (tmp_buf, name_buf);
19858 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
19860 output_asm_insn (tmp_buf, 0);
19861 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
19862 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
19863 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
19864 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
19867 branch_island_list = 0;
19870 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
19871 already there or not. */
19874 no_previous_def (tree function_name)
19876 tree branch_island;
19877 for (branch_island = branch_island_list;
19879 branch_island = TREE_CHAIN (branch_island))
19880 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19885 /* GET_PREV_LABEL gets the label name from the previous definition of
19889 get_prev_label (tree function_name)
19891 tree branch_island;
19892 for (branch_island = branch_island_list;
19894 branch_island = TREE_CHAIN (branch_island))
19895 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
19896 return BRANCH_ISLAND_LABEL_NAME (branch_island);
19900 #ifndef DARWIN_LINKER_GENERATES_ISLANDS
19901 #define DARWIN_LINKER_GENERATES_ISLANDS 0
19904 /* KEXTs still need branch islands. */
19905 #define DARWIN_GENERATE_ISLANDS (!DARWIN_LINKER_GENERATES_ISLANDS \
19906 || flag_mkernel || flag_apple_kext)
19908 /* INSN is either a function call or a millicode call. It may have an
19909 unconditional jump in its delay slot.
19911 CALL_DEST is the routine we are calling. */
19914 output_call (rtx insn, rtx *operands, int dest_operand_number,
19915 int cookie_operand_number)
19917 static char buf[256];
19918 if (DARWIN_GENERATE_ISLANDS
19919 && GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
19920 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
19923 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
19925 if (no_previous_def (funname))
19927 rtx label_rtx = gen_label_rtx ();
19928 char *label_buf, temp_buf[256];
19929 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
19930 CODE_LABEL_NUMBER (label_rtx));
19931 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
19932 labelname = get_identifier (label_buf);
19933 add_compiler_branch_island (labelname, funname, insn_line (insn));
19936 labelname = get_prev_label (funname);
19938 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
19939 instruction will reach 'foo', otherwise link as 'bl L42'".
19940 "L42" should be a 'branch island', that will do a far jump to
19941 'foo'. Branch islands are generated in
19942 macho_branch_islands(). */
19943 sprintf (buf, "jbsr %%z%d,%.246s",
19944 dest_operand_number, IDENTIFIER_POINTER (labelname));
19947 sprintf (buf, "bl %%z%d", dest_operand_number);
19951 /* Generate PIC and indirect symbol stubs. */
19954 machopic_output_stub (FILE *file, const char *symb, const char *stub)
19956 unsigned int length;
19957 char *symbol_name, *lazy_ptr_name;
19958 char *local_label_0;
19959 static int label = 0;
19961 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
19962 symb = (*targetm.strip_name_encoding) (symb);
19965 length = strlen (symb);
19966 symbol_name = alloca (length + 32);
19967 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
19969 lazy_ptr_name = alloca (length + 32);
19970 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
19973 switch_to_section (darwin_sections[machopic_picsymbol_stub1_section]);
19975 switch_to_section (darwin_sections[machopic_symbol_stub1_section]);
19979 fprintf (file, "\t.align 5\n");
19981 fprintf (file, "%s:\n", stub);
19982 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
19985 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
19986 sprintf (local_label_0, "\"L%011d$spb\"", label);
19988 fprintf (file, "\tmflr r0\n");
19989 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
19990 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
19991 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
19992 lazy_ptr_name, local_label_0);
19993 fprintf (file, "\tmtlr r0\n");
19994 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
19995 (TARGET_64BIT ? "ldu" : "lwzu"),
19996 lazy_ptr_name, local_label_0);
19997 fprintf (file, "\tmtctr r12\n");
19998 fprintf (file, "\tbctr\n");
20002 fprintf (file, "\t.align 4\n");
20004 fprintf (file, "%s:\n", stub);
20005 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20007 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
20008 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
20009 (TARGET_64BIT ? "ldu" : "lwzu"),
20011 fprintf (file, "\tmtctr r12\n");
20012 fprintf (file, "\tbctr\n");
20015 switch_to_section (darwin_sections[machopic_lazy_symbol_ptr_section]);
20016 fprintf (file, "%s:\n", lazy_ptr_name);
20017 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
20018 fprintf (file, "%sdyld_stub_binding_helper\n",
20019 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
20022 /* Legitimize PIC addresses. If the address is already
20023 position-independent, we return ORIG. Newly generated
20024 position-independent addresses go into a reg. This is REG if non
20025 zero, otherwise we allocate register(s) as necessary. */
20027 #define SMALL_INT(X) ((UINTVAL (X) + 0x8000) < 0x10000)
20030 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
20035 if (reg == NULL && ! reload_in_progress && ! reload_completed)
20036 reg = gen_reg_rtx (Pmode);
20038 if (GET_CODE (orig) == CONST)
20042 if (GET_CODE (XEXP (orig, 0)) == PLUS
20043 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
20046 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
20048 /* Use a different reg for the intermediate value, as
20049 it will be marked UNCHANGING. */
20050 reg_temp = !can_create_pseudo_p () ? reg : gen_reg_rtx (Pmode);
20051 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
20054 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
20057 if (GET_CODE (offset) == CONST_INT)
20059 if (SMALL_INT (offset))
20060 return plus_constant (base, INTVAL (offset));
20061 else if (! reload_in_progress && ! reload_completed)
20062 offset = force_reg (Pmode, offset);
20065 rtx mem = force_const_mem (Pmode, orig);
20066 return machopic_legitimize_pic_address (mem, Pmode, reg);
20069 return gen_rtx_PLUS (Pmode, base, offset);
20072 /* Fall back on generic machopic code. */
20073 return machopic_legitimize_pic_address (orig, mode, reg);
20076 /* Output a .machine directive for the Darwin assembler, and call
20077 the generic start_file routine. */
20080 rs6000_darwin_file_start (void)
20082 static const struct
20088 { "ppc64", "ppc64", MASK_64BIT },
20089 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
20090 { "power4", "ppc970", 0 },
20091 { "G5", "ppc970", 0 },
20092 { "7450", "ppc7450", 0 },
20093 { "7400", "ppc7400", MASK_ALTIVEC },
20094 { "G4", "ppc7400", 0 },
20095 { "750", "ppc750", 0 },
20096 { "740", "ppc750", 0 },
20097 { "G3", "ppc750", 0 },
20098 { "604e", "ppc604e", 0 },
20099 { "604", "ppc604", 0 },
20100 { "603e", "ppc603", 0 },
20101 { "603", "ppc603", 0 },
20102 { "601", "ppc601", 0 },
20103 { NULL, "ppc", 0 } };
20104 const char *cpu_id = "";
20107 rs6000_file_start ();
20108 darwin_file_start ();
20110 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
20111 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
20112 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
20113 && rs6000_select[i].string[0] != '\0')
20114 cpu_id = rs6000_select[i].string;
20116 /* Look through the mapping array. Pick the first name that either
20117 matches the argument, has a bit set in IF_SET that is also set
20118 in the target flags, or has a NULL name. */
20121 while (mapping[i].arg != NULL
20122 && strcmp (mapping[i].arg, cpu_id) != 0
20123 && (mapping[i].if_set & target_flags) == 0)
20126 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
20129 #endif /* TARGET_MACHO */
20133 rs6000_elf_reloc_rw_mask (void)
20137 else if (DEFAULT_ABI == ABI_AIX)
20143 /* Record an element in the table of global constructors. SYMBOL is
20144 a SYMBOL_REF of the function to be called; PRIORITY is a number
20145 between 0 and MAX_INIT_PRIORITY.
20147 This differs from default_named_section_asm_out_constructor in
20148 that we have special handling for -mrelocatable. */
20151 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
20153 const char *section = ".ctors";
20156 if (priority != DEFAULT_INIT_PRIORITY)
20158 sprintf (buf, ".ctors.%.5u",
20159 /* Invert the numbering so the linker puts us in the proper
20160 order; constructors are run from right to left, and the
20161 linker sorts in increasing order. */
20162 MAX_INIT_PRIORITY - priority);
20166 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20167 assemble_align (POINTER_SIZE);
20169 if (TARGET_RELOCATABLE)
20171 fputs ("\t.long (", asm_out_file);
20172 output_addr_const (asm_out_file, symbol);
20173 fputs (")@fixup\n", asm_out_file);
20176 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20180 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
20182 const char *section = ".dtors";
20185 if (priority != DEFAULT_INIT_PRIORITY)
20187 sprintf (buf, ".dtors.%.5u",
20188 /* Invert the numbering so the linker puts us in the proper
20189 order; constructors are run from right to left, and the
20190 linker sorts in increasing order. */
20191 MAX_INIT_PRIORITY - priority);
20195 switch_to_section (get_section (section, SECTION_WRITE, NULL));
20196 assemble_align (POINTER_SIZE);
20198 if (TARGET_RELOCATABLE)
20200 fputs ("\t.long (", asm_out_file);
20201 output_addr_const (asm_out_file, symbol);
20202 fputs (")@fixup\n", asm_out_file);
20205 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
20209 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
20213 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
20214 ASM_OUTPUT_LABEL (file, name);
20215 fputs (DOUBLE_INT_ASM_OP, file);
20216 rs6000_output_function_entry (file, name);
20217 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
20220 fputs ("\t.size\t", file);
20221 assemble_name (file, name);
20222 fputs (",24\n\t.type\t.", file);
20223 assemble_name (file, name);
20224 fputs (",@function\n", file);
20225 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
20227 fputs ("\t.globl\t.", file);
20228 assemble_name (file, name);
20233 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20234 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20235 rs6000_output_function_entry (file, name);
20236 fputs (":\n", file);
20240 if (TARGET_RELOCATABLE
20241 && !TARGET_SECURE_PLT
20242 && (get_pool_size () != 0 || current_function_profile)
20247 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
20249 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
20250 fprintf (file, "\t.long ");
20251 assemble_name (file, buf);
20253 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
20254 assemble_name (file, buf);
20258 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
20259 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
20261 if (DEFAULT_ABI == ABI_AIX)
20263 const char *desc_name, *orig_name;
20265 orig_name = (*targetm.strip_name_encoding) (name);
20266 desc_name = orig_name;
20267 while (*desc_name == '.')
20270 if (TREE_PUBLIC (decl))
20271 fprintf (file, "\t.globl %s\n", desc_name);
20273 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
20274 fprintf (file, "%s:\n", desc_name);
20275 fprintf (file, "\t.long %s\n", orig_name);
20276 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
20277 if (DEFAULT_ABI == ABI_AIX)
20278 fputs ("\t.long 0\n", file);
20279 fprintf (file, "\t.previous\n");
20281 ASM_OUTPUT_LABEL (file, name);
20285 rs6000_elf_end_indicate_exec_stack (void)
20288 file_end_indicate_exec_stack ();
20294 rs6000_xcoff_asm_output_anchor (rtx symbol)
20298 sprintf (buffer, "$ + " HOST_WIDE_INT_PRINT_DEC,
20299 SYMBOL_REF_BLOCK_OFFSET (symbol));
20300 ASM_OUTPUT_DEF (asm_out_file, XSTR (symbol, 0), buffer);
20304 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
20306 fputs (GLOBAL_ASM_OP, stream);
20307 RS6000_OUTPUT_BASENAME (stream, name);
20308 putc ('\n', stream);
20311 /* A get_unnamed_decl callback, used for read-only sections. PTR
20312 points to the section string variable. */
20315 rs6000_xcoff_output_readonly_section_asm_op (const void *directive)
20317 fprintf (asm_out_file, "\t.csect %s[RO],%s\n",
20318 *(const char *const *) directive,
20319 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20322 /* Likewise for read-write sections. */
20325 rs6000_xcoff_output_readwrite_section_asm_op (const void *directive)
20327 fprintf (asm_out_file, "\t.csect %s[RW],%s\n",
20328 *(const char *const *) directive,
20329 XCOFF_CSECT_DEFAULT_ALIGNMENT_STR);
20332 /* A get_unnamed_section callback, used for switching to toc_section. */
20335 rs6000_xcoff_output_toc_section_asm_op (const void *data ATTRIBUTE_UNUSED)
20337 if (TARGET_MINIMAL_TOC)
20339 /* toc_section is always selected at least once from
20340 rs6000_xcoff_file_start, so this is guaranteed to
20341 always be defined once and only once in each file. */
20342 if (!toc_initialized)
20344 fputs ("\t.toc\nLCTOC..1:\n", asm_out_file);
20345 fputs ("\t.tc toc_table[TC],toc_table[RW]\n", asm_out_file);
20346 toc_initialized = 1;
20348 fprintf (asm_out_file, "\t.csect toc_table[RW]%s\n",
20349 (TARGET_32BIT ? "" : ",3"));
20352 fputs ("\t.toc\n", asm_out_file);
20355 /* Implement TARGET_ASM_INIT_SECTIONS. */
20358 rs6000_xcoff_asm_init_sections (void)
20360 read_only_data_section
20361 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20362 &xcoff_read_only_section_name);
20364 private_data_section
20365 = get_unnamed_section (SECTION_WRITE,
20366 rs6000_xcoff_output_readwrite_section_asm_op,
20367 &xcoff_private_data_section_name);
20369 read_only_private_data_section
20370 = get_unnamed_section (0, rs6000_xcoff_output_readonly_section_asm_op,
20371 &xcoff_private_data_section_name);
20374 = get_unnamed_section (0, rs6000_xcoff_output_toc_section_asm_op, NULL);
20376 readonly_data_section = read_only_data_section;
20377 exception_section = data_section;
20381 rs6000_xcoff_reloc_rw_mask (void)
20387 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
20388 tree decl ATTRIBUTE_UNUSED)
20391 static const char * const suffix[3] = { "PR", "RO", "RW" };
20393 if (flags & SECTION_CODE)
20395 else if (flags & SECTION_WRITE)
20400 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
20401 (flags & SECTION_CODE) ? "." : "",
20402 name, suffix[smclass], flags & SECTION_ENTSIZE);
20406 rs6000_xcoff_select_section (tree decl, int reloc,
20407 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20409 if (decl_readonly_section (decl, reloc))
20411 if (TREE_PUBLIC (decl))
20412 return read_only_data_section;
20414 return read_only_private_data_section;
20418 if (TREE_PUBLIC (decl))
20419 return data_section;
20421 return private_data_section;
20426 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
20430 /* Use select_section for private and uninitialized data. */
20431 if (!TREE_PUBLIC (decl)
20432 || DECL_COMMON (decl)
20433 || DECL_INITIAL (decl) == NULL_TREE
20434 || DECL_INITIAL (decl) == error_mark_node
20435 || (flag_zero_initialized_in_bss
20436 && initializer_zerop (DECL_INITIAL (decl))))
20439 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
20440 name = (*targetm.strip_name_encoding) (name);
20441 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
20444 /* Select section for constant in constant pool.
20446 On RS/6000, all constants are in the private read-only data area.
20447 However, if this is being placed in the TOC it must be output as a
20451 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
20452 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
20454 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
20455 return toc_section;
20457 return read_only_private_data_section;
20460 /* Remove any trailing [DS] or the like from the symbol name. */
20462 static const char *
20463 rs6000_xcoff_strip_name_encoding (const char *name)
20468 len = strlen (name);
20469 if (name[len - 1] == ']')
20470 return ggc_alloc_string (name, len - 4);
20475 /* Section attributes. AIX is always PIC. */
20477 static unsigned int
20478 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
20480 unsigned int align;
20481 unsigned int flags = default_section_type_flags (decl, name, reloc);
20483 /* Align to at least UNIT size. */
20484 if (flags & SECTION_CODE)
20485 align = MIN_UNITS_PER_WORD;
20487 /* Increase alignment of large objects if not already stricter. */
20488 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
20489 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
20490 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
20492 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
20495 /* Output at beginning of assembler file.
20497 Initialize the section names for the RS/6000 at this point.
20499 Specify filename, including full path, to assembler.
20501 We want to go into the TOC section so at least one .toc will be emitted.
20502 Also, in order to output proper .bs/.es pairs, we need at least one static
20503 [RW] section emitted.
20505 Finally, declare mcount when profiling to make the assembler happy. */
20508 rs6000_xcoff_file_start (void)
20510 rs6000_gen_section_name (&xcoff_bss_section_name,
20511 main_input_filename, ".bss_");
20512 rs6000_gen_section_name (&xcoff_private_data_section_name,
20513 main_input_filename, ".rw_");
20514 rs6000_gen_section_name (&xcoff_read_only_section_name,
20515 main_input_filename, ".ro_");
20517 fputs ("\t.file\t", asm_out_file);
20518 output_quoted_string (asm_out_file, main_input_filename);
20519 fputc ('\n', asm_out_file);
20520 if (write_symbols != NO_DEBUG)
20521 switch_to_section (private_data_section);
20522 switch_to_section (text_section);
20524 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
20525 rs6000_file_start ();
20528 /* Output at end of assembler file.
20529 On the RS/6000, referencing data should automatically pull in text. */
20532 rs6000_xcoff_file_end (void)
20534 switch_to_section (text_section);
20535 fputs ("_section_.text:\n", asm_out_file);
20536 switch_to_section (data_section);
20537 fputs (TARGET_32BIT
20538 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
20541 #endif /* TARGET_XCOFF */
20543 /* Compute a (partial) cost for rtx X. Return true if the complete
20544 cost has been computed, and false if subexpressions should be
20545 scanned. In either case, *TOTAL contains the cost result. */
20548 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
20550 enum machine_mode mode = GET_MODE (x);
20554 /* On the RS/6000, if it is valid in the insn, it is free. */
20556 if (((outer_code == SET
20557 || outer_code == PLUS
20558 || outer_code == MINUS)
20559 && (satisfies_constraint_I (x)
20560 || satisfies_constraint_L (x)))
20561 || (outer_code == AND
20562 && (satisfies_constraint_K (x)
20564 ? satisfies_constraint_L (x)
20565 : satisfies_constraint_J (x))
20566 || mask_operand (x, mode)
20568 && mask64_operand (x, DImode))))
20569 || ((outer_code == IOR || outer_code == XOR)
20570 && (satisfies_constraint_K (x)
20572 ? satisfies_constraint_L (x)
20573 : satisfies_constraint_J (x))))
20574 || outer_code == ASHIFT
20575 || outer_code == ASHIFTRT
20576 || outer_code == LSHIFTRT
20577 || outer_code == ROTATE
20578 || outer_code == ROTATERT
20579 || outer_code == ZERO_EXTRACT
20580 || (outer_code == MULT
20581 && satisfies_constraint_I (x))
20582 || ((outer_code == DIV || outer_code == UDIV
20583 || outer_code == MOD || outer_code == UMOD)
20584 && exact_log2 (INTVAL (x)) >= 0)
20585 || (outer_code == COMPARE
20586 && (satisfies_constraint_I (x)
20587 || satisfies_constraint_K (x)))
20588 || (outer_code == EQ
20589 && (satisfies_constraint_I (x)
20590 || satisfies_constraint_K (x)
20592 ? satisfies_constraint_L (x)
20593 : satisfies_constraint_J (x))))
20594 || (outer_code == GTU
20595 && satisfies_constraint_I (x))
20596 || (outer_code == LTU
20597 && satisfies_constraint_P (x)))
20602 else if ((outer_code == PLUS
20603 && reg_or_add_cint_operand (x, VOIDmode))
20604 || (outer_code == MINUS
20605 && reg_or_sub_cint_operand (x, VOIDmode))
20606 || ((outer_code == SET
20607 || outer_code == IOR
20608 || outer_code == XOR)
20610 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
20612 *total = COSTS_N_INSNS (1);
20618 if (mode == DImode && code == CONST_DOUBLE)
20620 if ((outer_code == IOR || outer_code == XOR)
20621 && CONST_DOUBLE_HIGH (x) == 0
20622 && (CONST_DOUBLE_LOW (x)
20623 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)
20628 else if ((outer_code == AND && and64_2_operand (x, DImode))
20629 || ((outer_code == SET
20630 || outer_code == IOR
20631 || outer_code == XOR)
20632 && CONST_DOUBLE_HIGH (x) == 0))
20634 *total = COSTS_N_INSNS (1);
20644 /* When optimizing for size, MEM should be slightly more expensive
20645 than generating address, e.g., (plus (reg) (const)).
20646 L1 cache latency is about two instructions. */
20647 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
20655 if (mode == DFmode)
20657 if (GET_CODE (XEXP (x, 0)) == MULT)
20659 /* FNMA accounted in outer NEG. */
20660 if (outer_code == NEG)
20661 *total = rs6000_cost->dmul - rs6000_cost->fp;
20663 *total = rs6000_cost->dmul;
20666 *total = rs6000_cost->fp;
20668 else if (mode == SFmode)
20670 /* FNMA accounted in outer NEG. */
20671 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20674 *total = rs6000_cost->fp;
20677 *total = COSTS_N_INSNS (1);
20681 if (mode == DFmode)
20683 if (GET_CODE (XEXP (x, 0)) == MULT
20684 || GET_CODE (XEXP (x, 1)) == MULT)
20686 /* FNMA accounted in outer NEG. */
20687 if (outer_code == NEG)
20688 *total = rs6000_cost->dmul - rs6000_cost->fp;
20690 *total = rs6000_cost->dmul;
20693 *total = rs6000_cost->fp;
20695 else if (mode == SFmode)
20697 /* FNMA accounted in outer NEG. */
20698 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
20701 *total = rs6000_cost->fp;
20704 *total = COSTS_N_INSNS (1);
20708 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20709 && satisfies_constraint_I (XEXP (x, 1)))
20711 if (INTVAL (XEXP (x, 1)) >= -256
20712 && INTVAL (XEXP (x, 1)) <= 255)
20713 *total = rs6000_cost->mulsi_const9;
20715 *total = rs6000_cost->mulsi_const;
20717 /* FMA accounted in outer PLUS/MINUS. */
20718 else if ((mode == DFmode || mode == SFmode)
20719 && (outer_code == PLUS || outer_code == MINUS))
20721 else if (mode == DFmode)
20722 *total = rs6000_cost->dmul;
20723 else if (mode == SFmode)
20724 *total = rs6000_cost->fp;
20725 else if (mode == DImode)
20726 *total = rs6000_cost->muldi;
20728 *total = rs6000_cost->mulsi;
20733 if (FLOAT_MODE_P (mode))
20735 *total = mode == DFmode ? rs6000_cost->ddiv
20736 : rs6000_cost->sdiv;
20743 if (GET_CODE (XEXP (x, 1)) == CONST_INT
20744 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
20746 if (code == DIV || code == MOD)
20748 *total = COSTS_N_INSNS (2);
20751 *total = COSTS_N_INSNS (1);
20755 if (GET_MODE (XEXP (x, 1)) == DImode)
20756 *total = rs6000_cost->divdi;
20758 *total = rs6000_cost->divsi;
20760 /* Add in shift and subtract for MOD. */
20761 if (code == MOD || code == UMOD)
20762 *total += COSTS_N_INSNS (2);
20767 *total = COSTS_N_INSNS (4);
20771 *total = COSTS_N_INSNS (6);
20775 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
20787 *total = COSTS_N_INSNS (1);
20795 /* Handle mul_highpart. */
20796 if (outer_code == TRUNCATE
20797 && GET_CODE (XEXP (x, 0)) == MULT)
20799 if (mode == DImode)
20800 *total = rs6000_cost->muldi;
20802 *total = rs6000_cost->mulsi;
20805 else if (outer_code == AND)
20808 *total = COSTS_N_INSNS (1);
20813 if (GET_CODE (XEXP (x, 0)) == MEM)
20816 *total = COSTS_N_INSNS (1);
20822 if (!FLOAT_MODE_P (mode))
20824 *total = COSTS_N_INSNS (1);
20830 case UNSIGNED_FLOAT:
20833 case FLOAT_TRUNCATE:
20834 *total = rs6000_cost->fp;
20838 if (mode == DFmode)
20841 *total = rs6000_cost->fp;
20845 switch (XINT (x, 1))
20848 *total = rs6000_cost->fp;
20860 *total = COSTS_N_INSNS (1);
20863 else if (FLOAT_MODE_P (mode)
20864 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
20866 *total = rs6000_cost->fp;
20874 /* Carry bit requires mode == Pmode.
20875 NEG or PLUS already counted so only add one. */
20877 && (outer_code == NEG || outer_code == PLUS))
20879 *total = COSTS_N_INSNS (1);
20882 if (outer_code == SET)
20884 if (XEXP (x, 1) == const0_rtx)
20886 *total = COSTS_N_INSNS (2);
20889 else if (mode == Pmode)
20891 *total = COSTS_N_INSNS (3);
20900 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
20902 *total = COSTS_N_INSNS (2);
20906 if (outer_code == COMPARE)
20920 /* A C expression returning the cost of moving data from a register of class
20921 CLASS1 to one of CLASS2. */
20924 rs6000_register_move_cost (enum machine_mode mode,
20925 enum reg_class from, enum reg_class to)
20927 /* Moves from/to GENERAL_REGS. */
20928 if (reg_classes_intersect_p (to, GENERAL_REGS)
20929 || reg_classes_intersect_p (from, GENERAL_REGS))
20931 if (! reg_classes_intersect_p (to, GENERAL_REGS))
20934 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
20935 return (rs6000_memory_move_cost (mode, from, 0)
20936 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
20938 /* It's more expensive to move CR_REGS than CR0_REGS because of the
20940 else if (from == CR_REGS)
20944 /* A move will cost one instruction per GPR moved. */
20945 return 2 * hard_regno_nregs[0][mode];
20948 /* Moving between two similar registers is just one instruction. */
20949 else if (reg_classes_intersect_p (to, from))
20950 return (mode == TFmode || mode == TDmode) ? 4 : 2;
20952 /* Everything else has to go through GENERAL_REGS. */
20954 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
20955 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
20958 /* A C expressions returning the cost of moving data of MODE from a register to
20962 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
20963 int in ATTRIBUTE_UNUSED)
20965 if (reg_classes_intersect_p (class, GENERAL_REGS))
20966 return 4 * hard_regno_nregs[0][mode];
20967 else if (reg_classes_intersect_p (class, FLOAT_REGS))
20968 return 4 * hard_regno_nregs[32][mode];
20969 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
20970 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
20972 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
20975 /* Returns a code for a target-specific builtin that implements
20976 reciprocal of the function, or NULL_TREE if not available. */
20979 rs6000_builtin_reciprocal (unsigned int fn, bool md_fn,
20980 bool sqrt ATTRIBUTE_UNUSED)
20982 if (! (TARGET_RECIP && TARGET_PPC_GFXOPT && !optimize_size
20983 && flag_finite_math_only && !flag_trapping_math
20984 && flag_unsafe_math_optimizations))
20992 case BUILT_IN_SQRTF:
20993 return rs6000_builtin_decls[RS6000_BUILTIN_RSQRTF];
21000 /* Newton-Raphson approximation of single-precision floating point divide n/d.
21001 Assumes no trapping math and finite arguments. */
21004 rs6000_emit_swdivsf (rtx dst, rtx n, rtx d)
21006 rtx x0, e0, e1, y1, u0, v0, one;
21008 x0 = gen_reg_rtx (SFmode);
21009 e0 = gen_reg_rtx (SFmode);
21010 e1 = gen_reg_rtx (SFmode);
21011 y1 = gen_reg_rtx (SFmode);
21012 u0 = gen_reg_rtx (SFmode);
21013 v0 = gen_reg_rtx (SFmode);
21014 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21016 /* x0 = 1./d estimate */
21017 emit_insn (gen_rtx_SET (VOIDmode, x0,
21018 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
21020 /* e0 = 1. - d * x0 */
21021 emit_insn (gen_rtx_SET (VOIDmode, e0,
21022 gen_rtx_MINUS (SFmode, one,
21023 gen_rtx_MULT (SFmode, d, x0))));
21024 /* e1 = e0 + e0 * e0 */
21025 emit_insn (gen_rtx_SET (VOIDmode, e1,
21026 gen_rtx_PLUS (SFmode,
21027 gen_rtx_MULT (SFmode, e0, e0), e0)));
21028 /* y1 = x0 + e1 * x0 */
21029 emit_insn (gen_rtx_SET (VOIDmode, y1,
21030 gen_rtx_PLUS (SFmode,
21031 gen_rtx_MULT (SFmode, e1, x0), x0)));
21033 emit_insn (gen_rtx_SET (VOIDmode, u0,
21034 gen_rtx_MULT (SFmode, n, y1)));
21035 /* v0 = n - d * u0 */
21036 emit_insn (gen_rtx_SET (VOIDmode, v0,
21037 gen_rtx_MINUS (SFmode, n,
21038 gen_rtx_MULT (SFmode, d, u0))));
21039 /* dst = u0 + v0 * y1 */
21040 emit_insn (gen_rtx_SET (VOIDmode, dst,
21041 gen_rtx_PLUS (SFmode,
21042 gen_rtx_MULT (SFmode, v0, y1), u0)));
21045 /* Newton-Raphson approximation of double-precision floating point divide n/d.
21046 Assumes no trapping math and finite arguments. */
21049 rs6000_emit_swdivdf (rtx dst, rtx n, rtx d)
21051 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
21053 x0 = gen_reg_rtx (DFmode);
21054 e0 = gen_reg_rtx (DFmode);
21055 e1 = gen_reg_rtx (DFmode);
21056 e2 = gen_reg_rtx (DFmode);
21057 y1 = gen_reg_rtx (DFmode);
21058 y2 = gen_reg_rtx (DFmode);
21059 y3 = gen_reg_rtx (DFmode);
21060 u0 = gen_reg_rtx (DFmode);
21061 v0 = gen_reg_rtx (DFmode);
21062 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
21064 /* x0 = 1./d estimate */
21065 emit_insn (gen_rtx_SET (VOIDmode, x0,
21066 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
21068 /* e0 = 1. - d * x0 */
21069 emit_insn (gen_rtx_SET (VOIDmode, e0,
21070 gen_rtx_MINUS (DFmode, one,
21071 gen_rtx_MULT (SFmode, d, x0))));
21072 /* y1 = x0 + e0 * x0 */
21073 emit_insn (gen_rtx_SET (VOIDmode, y1,
21074 gen_rtx_PLUS (DFmode,
21075 gen_rtx_MULT (DFmode, e0, x0), x0)));
21077 emit_insn (gen_rtx_SET (VOIDmode, e1,
21078 gen_rtx_MULT (DFmode, e0, e0)));
21079 /* y2 = y1 + e1 * y1 */
21080 emit_insn (gen_rtx_SET (VOIDmode, y2,
21081 gen_rtx_PLUS (DFmode,
21082 gen_rtx_MULT (DFmode, e1, y1), y1)));
21084 emit_insn (gen_rtx_SET (VOIDmode, e2,
21085 gen_rtx_MULT (DFmode, e1, e1)));
21086 /* y3 = y2 + e2 * y2 */
21087 emit_insn (gen_rtx_SET (VOIDmode, y3,
21088 gen_rtx_PLUS (DFmode,
21089 gen_rtx_MULT (DFmode, e2, y2), y2)));
21091 emit_insn (gen_rtx_SET (VOIDmode, u0,
21092 gen_rtx_MULT (DFmode, n, y3)));
21093 /* v0 = n - d * u0 */
21094 emit_insn (gen_rtx_SET (VOIDmode, v0,
21095 gen_rtx_MINUS (DFmode, n,
21096 gen_rtx_MULT (DFmode, d, u0))));
21097 /* dst = u0 + v0 * y3 */
21098 emit_insn (gen_rtx_SET (VOIDmode, dst,
21099 gen_rtx_PLUS (DFmode,
21100 gen_rtx_MULT (DFmode, v0, y3), u0)));
21104 /* Newton-Raphson approximation of single-precision floating point rsqrt.
21105 Assumes no trapping math and finite arguments. */
21108 rs6000_emit_swrsqrtsf (rtx dst, rtx src)
21110 rtx x0, x1, x2, y1, u0, u1, u2, v0, v1, v2, t0,
21111 half, one, halfthree, c1, cond, label;
21113 x0 = gen_reg_rtx (SFmode);
21114 x1 = gen_reg_rtx (SFmode);
21115 x2 = gen_reg_rtx (SFmode);
21116 y1 = gen_reg_rtx (SFmode);
21117 u0 = gen_reg_rtx (SFmode);
21118 u1 = gen_reg_rtx (SFmode);
21119 u2 = gen_reg_rtx (SFmode);
21120 v0 = gen_reg_rtx (SFmode);
21121 v1 = gen_reg_rtx (SFmode);
21122 v2 = gen_reg_rtx (SFmode);
21123 t0 = gen_reg_rtx (SFmode);
21124 halfthree = gen_reg_rtx (SFmode);
21125 cond = gen_rtx_REG (CCFPmode, CR1_REGNO);
21126 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
21128 /* check 0.0, 1.0, NaN, Inf by testing src * src = src */
21129 emit_insn (gen_rtx_SET (VOIDmode, t0,
21130 gen_rtx_MULT (SFmode, src, src)));
21132 emit_insn (gen_rtx_SET (VOIDmode, cond,
21133 gen_rtx_COMPARE (CCFPmode, t0, src)));
21134 c1 = gen_rtx_EQ (VOIDmode, cond, const0_rtx);
21135 emit_unlikely_jump (c1, label);
21137 half = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconsthalf, SFmode));
21138 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
21140 /* halfthree = 1.5 = 1.0 + 0.5 */
21141 emit_insn (gen_rtx_SET (VOIDmode, halfthree,
21142 gen_rtx_PLUS (SFmode, one, half)));
21144 /* x0 = rsqrt estimate */
21145 emit_insn (gen_rtx_SET (VOIDmode, x0,
21146 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, src),
21149 /* y1 = 0.5 * src = 1.5 * src - src -> fewer constants */
21150 emit_insn (gen_rtx_SET (VOIDmode, y1,
21151 gen_rtx_MINUS (SFmode,
21152 gen_rtx_MULT (SFmode, src, halfthree),
21155 /* x1 = x0 * (1.5 - y1 * (x0 * x0)) */
21156 emit_insn (gen_rtx_SET (VOIDmode, u0,
21157 gen_rtx_MULT (SFmode, x0, x0)));
21158 emit_insn (gen_rtx_SET (VOIDmode, v0,
21159 gen_rtx_MINUS (SFmode,
21161 gen_rtx_MULT (SFmode, y1, u0))));
21162 emit_insn (gen_rtx_SET (VOIDmode, x1,
21163 gen_rtx_MULT (SFmode, x0, v0)));
21165 /* x2 = x1 * (1.5 - y1 * (x1 * x1)) */
21166 emit_insn (gen_rtx_SET (VOIDmode, u1,
21167 gen_rtx_MULT (SFmode, x1, x1)));
21168 emit_insn (gen_rtx_SET (VOIDmode, v1,
21169 gen_rtx_MINUS (SFmode,
21171 gen_rtx_MULT (SFmode, y1, u1))));
21172 emit_insn (gen_rtx_SET (VOIDmode, x2,
21173 gen_rtx_MULT (SFmode, x1, v1)));
21175 /* dst = x2 * (1.5 - y1 * (x2 * x2)) */
21176 emit_insn (gen_rtx_SET (VOIDmode, u2,
21177 gen_rtx_MULT (SFmode, x2, x2)));
21178 emit_insn (gen_rtx_SET (VOIDmode, v2,
21179 gen_rtx_MINUS (SFmode,
21181 gen_rtx_MULT (SFmode, y1, u2))));
21182 emit_insn (gen_rtx_SET (VOIDmode, dst,
21183 gen_rtx_MULT (SFmode, x2, v2)));
21185 emit_label (XEXP (label, 0));
21188 /* Emit popcount intrinsic on TARGET_POPCNTB targets. DST is the
21189 target, and SRC is the argument operand. */
21192 rs6000_emit_popcount (rtx dst, rtx src)
21194 enum machine_mode mode = GET_MODE (dst);
21197 tmp1 = gen_reg_rtx (mode);
21199 if (mode == SImode)
21201 emit_insn (gen_popcntbsi2 (tmp1, src));
21202 tmp2 = expand_mult (SImode, tmp1, GEN_INT (0x01010101),
21204 tmp2 = force_reg (SImode, tmp2);
21205 emit_insn (gen_lshrsi3 (dst, tmp2, GEN_INT (24)));
21209 emit_insn (gen_popcntbdi2 (tmp1, src));
21210 tmp2 = expand_mult (DImode, tmp1,
21211 GEN_INT ((HOST_WIDE_INT)
21212 0x01010101 << 32 | 0x01010101),
21214 tmp2 = force_reg (DImode, tmp2);
21215 emit_insn (gen_lshrdi3 (dst, tmp2, GEN_INT (56)));
21220 /* Emit parity intrinsic on TARGET_POPCNTB targets. DST is the
21221 target, and SRC is the argument operand. */
21224 rs6000_emit_parity (rtx dst, rtx src)
21226 enum machine_mode mode = GET_MODE (dst);
21229 tmp = gen_reg_rtx (mode);
21230 if (mode == SImode)
21232 /* Is mult+shift >= shift+xor+shift+xor? */
21233 if (rs6000_cost->mulsi_const >= COSTS_N_INSNS (3))
21235 rtx tmp1, tmp2, tmp3, tmp4;
21237 tmp1 = gen_reg_rtx (SImode);
21238 emit_insn (gen_popcntbsi2 (tmp1, src));
21240 tmp2 = gen_reg_rtx (SImode);
21241 emit_insn (gen_lshrsi3 (tmp2, tmp1, GEN_INT (16)));
21242 tmp3 = gen_reg_rtx (SImode);
21243 emit_insn (gen_xorsi3 (tmp3, tmp1, tmp2));
21245 tmp4 = gen_reg_rtx (SImode);
21246 emit_insn (gen_lshrsi3 (tmp4, tmp3, GEN_INT (8)));
21247 emit_insn (gen_xorsi3 (tmp, tmp3, tmp4));
21250 rs6000_emit_popcount (tmp, src);
21251 emit_insn (gen_andsi3 (dst, tmp, const1_rtx));
21255 /* Is mult+shift >= shift+xor+shift+xor+shift+xor? */
21256 if (rs6000_cost->muldi >= COSTS_N_INSNS (5))
21258 rtx tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
21260 tmp1 = gen_reg_rtx (DImode);
21261 emit_insn (gen_popcntbdi2 (tmp1, src));
21263 tmp2 = gen_reg_rtx (DImode);
21264 emit_insn (gen_lshrdi3 (tmp2, tmp1, GEN_INT (32)));
21265 tmp3 = gen_reg_rtx (DImode);
21266 emit_insn (gen_xordi3 (tmp3, tmp1, tmp2));
21268 tmp4 = gen_reg_rtx (DImode);
21269 emit_insn (gen_lshrdi3 (tmp4, tmp3, GEN_INT (16)));
21270 tmp5 = gen_reg_rtx (DImode);
21271 emit_insn (gen_xordi3 (tmp5, tmp3, tmp4));
21273 tmp6 = gen_reg_rtx (DImode);
21274 emit_insn (gen_lshrdi3 (tmp6, tmp5, GEN_INT (8)));
21275 emit_insn (gen_xordi3 (tmp, tmp5, tmp6));
21278 rs6000_emit_popcount (tmp, src);
21279 emit_insn (gen_anddi3 (dst, tmp, const1_rtx));
21283 /* Return an RTX representing where to find the function value of a
21284 function returning MODE. */
21286 rs6000_complex_function_value (enum machine_mode mode)
21288 unsigned int regno;
21290 enum machine_mode inner = GET_MODE_INNER (mode);
21291 unsigned int inner_bytes = GET_MODE_SIZE (inner);
21293 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
21294 regno = FP_ARG_RETURN;
21297 regno = GP_ARG_RETURN;
21299 /* 32-bit is OK since it'll go in r3/r4. */
21300 if (TARGET_32BIT && inner_bytes >= 4)
21301 return gen_rtx_REG (mode, regno);
21304 if (inner_bytes >= 8)
21305 return gen_rtx_REG (mode, regno);
21307 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
21309 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
21310 GEN_INT (inner_bytes));
21311 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
21314 /* Define how to find the value returned by a function.
21315 VALTYPE is the data type of the value (as a tree).
21316 If the precise function being called is known, FUNC is its FUNCTION_DECL;
21317 otherwise, FUNC is 0.
21319 On the SPE, both FPs and vectors are returned in r3.
21321 On RS/6000 an integer value is in r3 and a floating-point value is in
21322 fp1, unless -msoft-float. */
21325 rs6000_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
21327 enum machine_mode mode;
21328 unsigned int regno;
21330 /* Special handling for structs in darwin64. */
21331 if (rs6000_darwin64_abi
21332 && TYPE_MODE (valtype) == BLKmode
21333 && TREE_CODE (valtype) == RECORD_TYPE
21334 && int_size_in_bytes (valtype) > 0)
21336 CUMULATIVE_ARGS valcum;
21340 valcum.fregno = FP_ARG_MIN_REG;
21341 valcum.vregno = ALTIVEC_ARG_MIN_REG;
21342 /* Do a trial code generation as if this were going to be passed as
21343 an argument; if any part goes in memory, we return NULL. */
21344 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
21347 /* Otherwise fall through to standard ABI rules. */
21350 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
21352 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21353 return gen_rtx_PARALLEL (DImode,
21355 gen_rtx_EXPR_LIST (VOIDmode,
21356 gen_rtx_REG (SImode, GP_ARG_RETURN),
21358 gen_rtx_EXPR_LIST (VOIDmode,
21359 gen_rtx_REG (SImode,
21360 GP_ARG_RETURN + 1),
21363 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DCmode)
21365 return gen_rtx_PARALLEL (DCmode,
21367 gen_rtx_EXPR_LIST (VOIDmode,
21368 gen_rtx_REG (SImode, GP_ARG_RETURN),
21370 gen_rtx_EXPR_LIST (VOIDmode,
21371 gen_rtx_REG (SImode,
21372 GP_ARG_RETURN + 1),
21374 gen_rtx_EXPR_LIST (VOIDmode,
21375 gen_rtx_REG (SImode,
21376 GP_ARG_RETURN + 2),
21378 gen_rtx_EXPR_LIST (VOIDmode,
21379 gen_rtx_REG (SImode,
21380 GP_ARG_RETURN + 3),
21384 mode = TYPE_MODE (valtype);
21385 if ((INTEGRAL_TYPE_P (valtype) && GET_MODE_BITSIZE (mode) < BITS_PER_WORD)
21386 || POINTER_TYPE_P (valtype))
21387 mode = TARGET_32BIT ? SImode : DImode;
21389 if (DECIMAL_FLOAT_MODE_P (mode))
21391 if (TARGET_HARD_FLOAT && TARGET_FPRS)
21396 gcc_unreachable ();
21398 regno = GP_ARG_RETURN;
21401 regno = FP_ARG_RETURN;
21404 /* Use f2:f3 specified by the ABI. */
21405 regno = FP_ARG_RETURN + 1;
21410 regno = GP_ARG_RETURN;
21412 else if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
21413 regno = FP_ARG_RETURN;
21414 else if (TREE_CODE (valtype) == COMPLEX_TYPE
21415 && targetm.calls.split_complex_arg)
21416 return rs6000_complex_function_value (mode);
21417 else if (TREE_CODE (valtype) == VECTOR_TYPE
21418 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
21419 && ALTIVEC_VECTOR_MODE (mode))
21420 regno = ALTIVEC_ARG_RETURN;
21421 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21422 && (mode == DFmode || mode == DCmode
21423 || mode == TFmode || mode == TCmode))
21424 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21426 regno = GP_ARG_RETURN;
21428 return gen_rtx_REG (mode, regno);
21431 /* Define how to find the value returned by a library function
21432 assuming the value has mode MODE. */
21434 rs6000_libcall_value (enum machine_mode mode)
21436 unsigned int regno;
21438 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
21440 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
21441 return gen_rtx_PARALLEL (DImode,
21443 gen_rtx_EXPR_LIST (VOIDmode,
21444 gen_rtx_REG (SImode, GP_ARG_RETURN),
21446 gen_rtx_EXPR_LIST (VOIDmode,
21447 gen_rtx_REG (SImode,
21448 GP_ARG_RETURN + 1),
21452 if (DECIMAL_FLOAT_MODE_P (mode))
21454 if (TARGET_HARD_FLOAT && TARGET_FPRS)
21459 gcc_unreachable ();
21461 regno = GP_ARG_RETURN;
21464 regno = FP_ARG_RETURN;
21467 /* Use f2:f3 specified by the ABI. */
21468 regno = FP_ARG_RETURN + 1;
21473 regno = GP_ARG_RETURN;
21475 else if (SCALAR_FLOAT_MODE_P (mode)
21476 && TARGET_HARD_FLOAT && TARGET_FPRS)
21477 regno = FP_ARG_RETURN;
21478 else if (ALTIVEC_VECTOR_MODE (mode)
21479 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
21480 regno = ALTIVEC_ARG_RETURN;
21481 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
21482 return rs6000_complex_function_value (mode);
21483 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
21484 && (mode == DFmode || mode == DCmode
21485 || mode == TFmode || mode == TCmode))
21486 return spe_build_register_parallel (mode, GP_ARG_RETURN);
21488 regno = GP_ARG_RETURN;
21490 return gen_rtx_REG (mode, regno);
21493 /* Define the offset between two registers, FROM to be eliminated and its
21494 replacement TO, at the start of a routine. */
21496 rs6000_initial_elimination_offset (int from, int to)
21498 rs6000_stack_t *info = rs6000_stack_info ();
21499 HOST_WIDE_INT offset;
21501 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21502 offset = info->push_p ? 0 : -info->total_size;
21503 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21505 offset = info->push_p ? 0 : -info->total_size;
21506 if (FRAME_GROWS_DOWNWARD)
21507 offset += info->fixed_size + info->vars_size + info->parm_size;
21509 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21510 offset = FRAME_GROWS_DOWNWARD
21511 ? info->fixed_size + info->vars_size + info->parm_size
21513 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
21514 offset = info->total_size;
21515 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
21516 offset = info->push_p ? info->total_size : 0;
21517 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
21520 gcc_unreachable ();
21525 /* Return true if TYPE is a SPE or AltiVec opaque type. */
21528 rs6000_is_opaque_type (const_tree type)
21530 return (type == opaque_V2SI_type_node
21531 || type == opaque_V2SF_type_node
21532 || type == opaque_p_V2SI_type_node
21533 || type == opaque_V4SI_type_node);
21537 rs6000_dwarf_register_span (rtx reg)
21542 && (SPE_VECTOR_MODE (GET_MODE (reg))
21543 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
21548 regno = REGNO (reg);
21550 /* The duality of the SPE register size wreaks all kinds of havoc.
21551 This is a way of distinguishing r0 in 32-bits from r0 in
21554 gen_rtx_PARALLEL (VOIDmode,
21557 gen_rtx_REG (SImode, regno + 1200),
21558 gen_rtx_REG (SImode, regno))
21560 gen_rtx_REG (SImode, regno),
21561 gen_rtx_REG (SImode, regno + 1200)));
21564 /* Fill in sizes for SPE register high parts in table used by unwinder. */
21567 rs6000_init_dwarf_reg_sizes_extra (tree address)
21572 enum machine_mode mode = TYPE_MODE (char_type_node);
21573 rtx addr = expand_expr (address, NULL_RTX, VOIDmode, 0);
21574 rtx mem = gen_rtx_MEM (BLKmode, addr);
21575 rtx value = gen_int_mode (4, mode);
21577 for (i = 1201; i < 1232; i++)
21579 int column = DWARF_REG_TO_UNWIND_COLUMN (i);
21580 HOST_WIDE_INT offset
21581 = DWARF_FRAME_REGNUM (column) * GET_MODE_SIZE (mode);
21583 emit_move_insn (adjust_address (mem, mode, offset), value);
21588 /* Map internal gcc register numbers to DWARF2 register numbers. */
21591 rs6000_dbx_register_number (unsigned int regno)
21593 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
21595 if (regno == MQ_REGNO)
21597 if (regno == LR_REGNO)
21599 if (regno == CTR_REGNO)
21601 if (CR_REGNO_P (regno))
21602 return regno - CR0_REGNO + 86;
21603 if (regno == XER_REGNO)
21605 if (ALTIVEC_REGNO_P (regno))
21606 return regno - FIRST_ALTIVEC_REGNO + 1124;
21607 if (regno == VRSAVE_REGNO)
21609 if (regno == VSCR_REGNO)
21611 if (regno == SPE_ACC_REGNO)
21613 if (regno == SPEFSCR_REGNO)
21615 /* SPE high reg number. We get these values of regno from
21616 rs6000_dwarf_register_span. */
21617 gcc_assert (regno >= 1200 && regno < 1232);
21621 /* target hook eh_return_filter_mode */
21622 static enum machine_mode
21623 rs6000_eh_return_filter_mode (void)
21625 return TARGET_32BIT ? SImode : word_mode;
21628 /* Target hook for scalar_mode_supported_p. */
21630 rs6000_scalar_mode_supported_p (enum machine_mode mode)
21632 if (DECIMAL_FLOAT_MODE_P (mode))
21635 return default_scalar_mode_supported_p (mode);
21638 /* Target hook for vector_mode_supported_p. */
21640 rs6000_vector_mode_supported_p (enum machine_mode mode)
21643 if (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (mode))
21646 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
21649 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
21656 /* Target hook for invalid_arg_for_unprototyped_fn. */
21657 static const char *
21658 invalid_arg_for_unprototyped_fn (const_tree typelist, const_tree funcdecl, const_tree val)
21660 return (!rs6000_darwin64_abi
21662 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
21663 && (funcdecl == NULL_TREE
21664 || (TREE_CODE (funcdecl) == FUNCTION_DECL
21665 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
21666 ? N_("AltiVec argument passed to unprototyped function")
21670 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
21671 setup by using __stack_chk_fail_local hidden function instead of
21672 calling __stack_chk_fail directly. Otherwise it is better to call
21673 __stack_chk_fail directly. */
21676 rs6000_stack_protect_fail (void)
21678 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
21679 ? default_hidden_stack_protect_fail ()
21680 : default_external_stack_protect_fail ();
21683 #include "gt-rs6000.h"