1 /* Subroutines used for code generation on IBM RS/6000.
2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu)
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published
10 by the Free Software Foundation; either version 2, or (at your
11 option) any later version.
13 GCC is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the
20 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
21 MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
53 #include "cfglayout.h"
54 #include "sched-int.h"
55 #include "tree-gimple.h"
58 #include "xcoffout.h" /* get declarations of xcoff_*_section_name */
61 #include "gstab.h" /* for N_SLINE */
64 #ifndef TARGET_NO_PROTOTYPE
65 #define TARGET_NO_PROTOTYPE 0
68 #define min(A,B) ((A) < (B) ? (A) : (B))
69 #define max(A,B) ((A) > (B) ? (A) : (B))
71 /* Structure used to define the rs6000 stack */
72 typedef struct rs6000_stack {
73 int first_gp_reg_save; /* first callee saved GP register used */
74 int first_fp_reg_save; /* first callee saved FP register used */
75 int first_altivec_reg_save; /* first callee saved AltiVec register used */
76 int lr_save_p; /* true if the link reg needs to be saved */
77 int cr_save_p; /* true if the CR reg needs to be saved */
78 unsigned int vrsave_mask; /* mask of vec registers to save */
79 int toc_save_p; /* true if the TOC needs to be saved */
80 int push_p; /* true if we need to allocate stack space */
81 int calls_p; /* true if the function makes any calls */
82 int world_save_p; /* true if we're saving *everything*:
83 r13-r31, cr, f14-f31, vrsave, v20-v31 */
84 enum rs6000_abi abi; /* which ABI to use */
85 int gp_save_offset; /* offset to save GP regs from initial SP */
86 int fp_save_offset; /* offset to save FP regs from initial SP */
87 int altivec_save_offset; /* offset to save AltiVec regs from initial SP */
88 int lr_save_offset; /* offset to save LR from initial SP */
89 int cr_save_offset; /* offset to save CR from initial SP */
90 int vrsave_save_offset; /* offset to save VRSAVE from initial SP */
91 int spe_gp_save_offset; /* offset to save spe 64-bit gprs */
92 int toc_save_offset; /* offset to save the TOC pointer */
93 int varargs_save_offset; /* offset to save the varargs registers */
94 int ehrd_offset; /* offset to EH return data */
95 int reg_size; /* register size (4 or 8) */
96 HOST_WIDE_INT vars_size; /* variable save area size */
97 int parm_size; /* outgoing parameter size */
98 int save_size; /* save area size */
99 int fixed_size; /* fixed size of stack frame */
100 int gp_size; /* size of saved GP registers */
101 int fp_size; /* size of saved FP registers */
102 int altivec_size; /* size of saved AltiVec registers */
103 int cr_size; /* size to hold CR if not in save_size */
104 int lr_size; /* size to hold LR if not in save_size */
105 int vrsave_size; /* size to hold VRSAVE if not in save_size */
106 int altivec_padding_size; /* size of altivec alignment padding if
108 int spe_gp_size; /* size of 64-bit GPR save size for SPE */
109 int spe_padding_size;
110 int toc_size; /* size to hold TOC if not in save_size */
111 HOST_WIDE_INT total_size; /* total bytes allocated for stack */
112 int spe_64bit_regs_used;
115 /* A C structure for machine-specific, per-function data.
116 This is added to the cfun structure. */
117 typedef struct machine_function GTY(())
119 /* Flags if __builtin_return_address (n) with n >= 1 was used. */
120 int ra_needs_full_frame;
121 /* Some local-dynamic symbol. */
122 const char *some_ld_name;
123 /* Whether the instruction chain has been scanned already. */
124 int insn_chain_scanned_p;
125 /* Flags if __builtin_return_address (0) was used. */
127 /* Offset from virtual_stack_vars_rtx to the start of the ABI_V4
128 varargs save area. */
129 HOST_WIDE_INT varargs_save_offset;
132 /* Target cpu type */
134 enum processor_type rs6000_cpu;
135 struct rs6000_cpu_select rs6000_select[3] =
137 /* switch name, tune arch */
138 { (const char *)0, "--with-cpu=", 1, 1 },
139 { (const char *)0, "-mcpu=", 1, 1 },
140 { (const char *)0, "-mtune=", 1, 0 },
143 /* Always emit branch hint bits. */
144 static GTY(()) bool rs6000_always_hint;
146 /* Schedule instructions for group formation. */
147 static GTY(()) bool rs6000_sched_groups;
149 /* Support for -msched-costly-dep option. */
150 const char *rs6000_sched_costly_dep_str;
151 enum rs6000_dependence_cost rs6000_sched_costly_dep;
153 /* Support for -minsert-sched-nops option. */
154 const char *rs6000_sched_insert_nops_str;
155 enum rs6000_nop_insertion rs6000_sched_insert_nops;
157 /* Support targetm.vectorize.builtin_mask_for_load. */
158 static GTY(()) tree altivec_builtin_mask_for_load;
160 /* Size of long double */
161 int rs6000_long_double_type_size;
163 /* Whether -mabi=altivec has appeared */
164 int rs6000_altivec_abi;
166 /* Nonzero if we want SPE ABI extensions. */
169 /* Nonzero if floating point operations are done in the GPRs. */
170 int rs6000_float_gprs = 0;
172 /* Nonzero if we want Darwin's struct-by-value-in-regs ABI. */
173 int rs6000_darwin64_abi;
175 /* Set to nonzero once AIX common-mode calls have been defined. */
176 static GTY(()) int common_mode_defined;
178 /* Save information from a "cmpxx" operation until the branch or scc is
180 rtx rs6000_compare_op0, rs6000_compare_op1;
181 int rs6000_compare_fp_p;
183 /* Label number of label created for -mrelocatable, to call to so we can
184 get the address of the GOT section */
185 int rs6000_pic_labelno;
188 /* Which abi to adhere to */
189 const char *rs6000_abi_name;
191 /* Semantics of the small data area */
192 enum rs6000_sdata_type rs6000_sdata = SDATA_DATA;
194 /* Which small data model to use */
195 const char *rs6000_sdata_name = (char *)0;
197 /* Counter for labels which are to be placed in .fixup. */
198 int fixuplabelno = 0;
201 /* Bit size of immediate TLS offsets and string from which it is decoded. */
202 int rs6000_tls_size = 32;
203 const char *rs6000_tls_size_string;
205 /* ABI enumeration available for subtarget to use. */
206 enum rs6000_abi rs6000_current_abi;
208 /* Whether to use variant of AIX ABI for PowerPC64 Linux. */
212 const char *rs6000_debug_name;
213 int rs6000_debug_stack; /* debug stack applications */
214 int rs6000_debug_arg; /* debug argument handling */
216 /* Value is TRUE if register/mode pair is acceptable. */
217 bool rs6000_hard_regno_mode_ok_p[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER];
219 /* Built in types. */
221 tree rs6000_builtin_types[RS6000_BTI_MAX];
222 tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT];
224 const char *rs6000_traceback_name;
226 traceback_default = 0,
232 /* Flag to say the TOC is initialized */
234 char toc_label_name[10];
236 /* Alias set for saves and restores from the rs6000 stack. */
237 static GTY(()) int rs6000_sr_alias_set;
239 /* Control alignment for fields within structures. */
240 /* String from -malign-XXXXX. */
241 int rs6000_alignment_flags;
243 /* True for any options that were explicitly set. */
245 bool aix_struct_ret; /* True if -maix-struct-ret was used. */
246 bool alignment; /* True if -malign- was used. */
247 bool abi; /* True if -mabi= was used. */
248 bool spe; /* True if -mspe= was used. */
249 bool float_gprs; /* True if -mfloat-gprs= was used. */
250 bool isel; /* True if -misel was used. */
251 bool long_double; /* True if -mlong-double- was used. */
252 } rs6000_explicit_options;
254 struct builtin_description
256 /* mask is not const because we're going to alter it below. This
257 nonsense will go away when we rewrite the -march infrastructure
258 to give us more target flag bits. */
260 const enum insn_code icode;
261 const char *const name;
262 const enum rs6000_builtins code;
265 /* Target cpu costs. */
267 struct processor_costs {
268 const int mulsi; /* cost of SImode multiplication. */
269 const int mulsi_const; /* cost of SImode multiplication by constant. */
270 const int mulsi_const9; /* cost of SImode mult by short constant. */
271 const int muldi; /* cost of DImode multiplication. */
272 const int divsi; /* cost of SImode division. */
273 const int divdi; /* cost of DImode division. */
274 const int fp; /* cost of simple SFmode and DFmode insns. */
275 const int dmul; /* cost of DFmode multiplication (and fmadd). */
276 const int sdiv; /* cost of SFmode division (fdivs). */
277 const int ddiv; /* cost of DFmode division (fdiv). */
280 const struct processor_costs *rs6000_cost;
282 /* Processor costs (relative to an add) */
284 /* Instruction size costs on 32bit processors. */
286 struct processor_costs size32_cost = {
287 COSTS_N_INSNS (1), /* mulsi */
288 COSTS_N_INSNS (1), /* mulsi_const */
289 COSTS_N_INSNS (1), /* mulsi_const9 */
290 COSTS_N_INSNS (1), /* muldi */
291 COSTS_N_INSNS (1), /* divsi */
292 COSTS_N_INSNS (1), /* divdi */
293 COSTS_N_INSNS (1), /* fp */
294 COSTS_N_INSNS (1), /* dmul */
295 COSTS_N_INSNS (1), /* sdiv */
296 COSTS_N_INSNS (1), /* ddiv */
299 /* Instruction size costs on 64bit processors. */
301 struct processor_costs size64_cost = {
302 COSTS_N_INSNS (1), /* mulsi */
303 COSTS_N_INSNS (1), /* mulsi_const */
304 COSTS_N_INSNS (1), /* mulsi_const9 */
305 COSTS_N_INSNS (1), /* muldi */
306 COSTS_N_INSNS (1), /* divsi */
307 COSTS_N_INSNS (1), /* divdi */
308 COSTS_N_INSNS (1), /* fp */
309 COSTS_N_INSNS (1), /* dmul */
310 COSTS_N_INSNS (1), /* sdiv */
311 COSTS_N_INSNS (1), /* ddiv */
314 /* Instruction costs on RIOS1 processors. */
316 struct processor_costs rios1_cost = {
317 COSTS_N_INSNS (5), /* mulsi */
318 COSTS_N_INSNS (4), /* mulsi_const */
319 COSTS_N_INSNS (3), /* mulsi_const9 */
320 COSTS_N_INSNS (5), /* muldi */
321 COSTS_N_INSNS (19), /* divsi */
322 COSTS_N_INSNS (19), /* divdi */
323 COSTS_N_INSNS (2), /* fp */
324 COSTS_N_INSNS (2), /* dmul */
325 COSTS_N_INSNS (19), /* sdiv */
326 COSTS_N_INSNS (19), /* ddiv */
329 /* Instruction costs on RIOS2 processors. */
331 struct processor_costs rios2_cost = {
332 COSTS_N_INSNS (2), /* mulsi */
333 COSTS_N_INSNS (2), /* mulsi_const */
334 COSTS_N_INSNS (2), /* mulsi_const9 */
335 COSTS_N_INSNS (2), /* muldi */
336 COSTS_N_INSNS (13), /* divsi */
337 COSTS_N_INSNS (13), /* divdi */
338 COSTS_N_INSNS (2), /* fp */
339 COSTS_N_INSNS (2), /* dmul */
340 COSTS_N_INSNS (17), /* sdiv */
341 COSTS_N_INSNS (17), /* ddiv */
344 /* Instruction costs on RS64A processors. */
346 struct processor_costs rs64a_cost = {
347 COSTS_N_INSNS (20), /* mulsi */
348 COSTS_N_INSNS (12), /* mulsi_const */
349 COSTS_N_INSNS (8), /* mulsi_const9 */
350 COSTS_N_INSNS (34), /* muldi */
351 COSTS_N_INSNS (65), /* divsi */
352 COSTS_N_INSNS (67), /* divdi */
353 COSTS_N_INSNS (4), /* fp */
354 COSTS_N_INSNS (4), /* dmul */
355 COSTS_N_INSNS (31), /* sdiv */
356 COSTS_N_INSNS (31), /* ddiv */
359 /* Instruction costs on MPCCORE processors. */
361 struct processor_costs mpccore_cost = {
362 COSTS_N_INSNS (2), /* mulsi */
363 COSTS_N_INSNS (2), /* mulsi_const */
364 COSTS_N_INSNS (2), /* mulsi_const9 */
365 COSTS_N_INSNS (2), /* muldi */
366 COSTS_N_INSNS (6), /* divsi */
367 COSTS_N_INSNS (6), /* divdi */
368 COSTS_N_INSNS (4), /* fp */
369 COSTS_N_INSNS (5), /* dmul */
370 COSTS_N_INSNS (10), /* sdiv */
371 COSTS_N_INSNS (17), /* ddiv */
374 /* Instruction costs on PPC403 processors. */
376 struct processor_costs ppc403_cost = {
377 COSTS_N_INSNS (4), /* mulsi */
378 COSTS_N_INSNS (4), /* mulsi_const */
379 COSTS_N_INSNS (4), /* mulsi_const9 */
380 COSTS_N_INSNS (4), /* muldi */
381 COSTS_N_INSNS (33), /* divsi */
382 COSTS_N_INSNS (33), /* divdi */
383 COSTS_N_INSNS (11), /* fp */
384 COSTS_N_INSNS (11), /* dmul */
385 COSTS_N_INSNS (11), /* sdiv */
386 COSTS_N_INSNS (11), /* ddiv */
389 /* Instruction costs on PPC405 processors. */
391 struct processor_costs ppc405_cost = {
392 COSTS_N_INSNS (5), /* mulsi */
393 COSTS_N_INSNS (4), /* mulsi_const */
394 COSTS_N_INSNS (3), /* mulsi_const9 */
395 COSTS_N_INSNS (5), /* muldi */
396 COSTS_N_INSNS (35), /* divsi */
397 COSTS_N_INSNS (35), /* divdi */
398 COSTS_N_INSNS (11), /* fp */
399 COSTS_N_INSNS (11), /* dmul */
400 COSTS_N_INSNS (11), /* sdiv */
401 COSTS_N_INSNS (11), /* ddiv */
404 /* Instruction costs on PPC440 processors. */
406 struct processor_costs ppc440_cost = {
407 COSTS_N_INSNS (3), /* mulsi */
408 COSTS_N_INSNS (2), /* mulsi_const */
409 COSTS_N_INSNS (2), /* mulsi_const9 */
410 COSTS_N_INSNS (3), /* muldi */
411 COSTS_N_INSNS (34), /* divsi */
412 COSTS_N_INSNS (34), /* divdi */
413 COSTS_N_INSNS (5), /* fp */
414 COSTS_N_INSNS (5), /* dmul */
415 COSTS_N_INSNS (19), /* sdiv */
416 COSTS_N_INSNS (33), /* ddiv */
419 /* Instruction costs on PPC601 processors. */
421 struct processor_costs ppc601_cost = {
422 COSTS_N_INSNS (5), /* mulsi */
423 COSTS_N_INSNS (5), /* mulsi_const */
424 COSTS_N_INSNS (5), /* mulsi_const9 */
425 COSTS_N_INSNS (5), /* muldi */
426 COSTS_N_INSNS (36), /* divsi */
427 COSTS_N_INSNS (36), /* divdi */
428 COSTS_N_INSNS (4), /* fp */
429 COSTS_N_INSNS (5), /* dmul */
430 COSTS_N_INSNS (17), /* sdiv */
431 COSTS_N_INSNS (31), /* ddiv */
434 /* Instruction costs on PPC603 processors. */
436 struct processor_costs ppc603_cost = {
437 COSTS_N_INSNS (5), /* mulsi */
438 COSTS_N_INSNS (3), /* mulsi_const */
439 COSTS_N_INSNS (2), /* mulsi_const9 */
440 COSTS_N_INSNS (5), /* muldi */
441 COSTS_N_INSNS (37), /* divsi */
442 COSTS_N_INSNS (37), /* divdi */
443 COSTS_N_INSNS (3), /* fp */
444 COSTS_N_INSNS (4), /* dmul */
445 COSTS_N_INSNS (18), /* sdiv */
446 COSTS_N_INSNS (33), /* ddiv */
449 /* Instruction costs on PPC604 processors. */
451 struct processor_costs ppc604_cost = {
452 COSTS_N_INSNS (4), /* mulsi */
453 COSTS_N_INSNS (4), /* mulsi_const */
454 COSTS_N_INSNS (4), /* mulsi_const9 */
455 COSTS_N_INSNS (4), /* muldi */
456 COSTS_N_INSNS (20), /* divsi */
457 COSTS_N_INSNS (20), /* divdi */
458 COSTS_N_INSNS (3), /* fp */
459 COSTS_N_INSNS (3), /* dmul */
460 COSTS_N_INSNS (18), /* sdiv */
461 COSTS_N_INSNS (32), /* ddiv */
464 /* Instruction costs on PPC604e processors. */
466 struct processor_costs ppc604e_cost = {
467 COSTS_N_INSNS (2), /* mulsi */
468 COSTS_N_INSNS (2), /* mulsi_const */
469 COSTS_N_INSNS (2), /* mulsi_const9 */
470 COSTS_N_INSNS (2), /* muldi */
471 COSTS_N_INSNS (20), /* divsi */
472 COSTS_N_INSNS (20), /* divdi */
473 COSTS_N_INSNS (3), /* fp */
474 COSTS_N_INSNS (3), /* dmul */
475 COSTS_N_INSNS (18), /* sdiv */
476 COSTS_N_INSNS (32), /* ddiv */
479 /* Instruction costs on PPC620 processors. */
481 struct processor_costs ppc620_cost = {
482 COSTS_N_INSNS (5), /* mulsi */
483 COSTS_N_INSNS (4), /* mulsi_const */
484 COSTS_N_INSNS (3), /* mulsi_const9 */
485 COSTS_N_INSNS (7), /* muldi */
486 COSTS_N_INSNS (21), /* divsi */
487 COSTS_N_INSNS (37), /* divdi */
488 COSTS_N_INSNS (3), /* fp */
489 COSTS_N_INSNS (3), /* dmul */
490 COSTS_N_INSNS (18), /* sdiv */
491 COSTS_N_INSNS (32), /* ddiv */
494 /* Instruction costs on PPC630 processors. */
496 struct processor_costs ppc630_cost = {
497 COSTS_N_INSNS (5), /* mulsi */
498 COSTS_N_INSNS (4), /* mulsi_const */
499 COSTS_N_INSNS (3), /* mulsi_const9 */
500 COSTS_N_INSNS (7), /* muldi */
501 COSTS_N_INSNS (21), /* divsi */
502 COSTS_N_INSNS (37), /* divdi */
503 COSTS_N_INSNS (3), /* fp */
504 COSTS_N_INSNS (3), /* dmul */
505 COSTS_N_INSNS (17), /* sdiv */
506 COSTS_N_INSNS (21), /* ddiv */
509 /* Instruction costs on PPC750 and PPC7400 processors. */
511 struct processor_costs ppc750_cost = {
512 COSTS_N_INSNS (5), /* mulsi */
513 COSTS_N_INSNS (3), /* mulsi_const */
514 COSTS_N_INSNS (2), /* mulsi_const9 */
515 COSTS_N_INSNS (5), /* muldi */
516 COSTS_N_INSNS (17), /* divsi */
517 COSTS_N_INSNS (17), /* divdi */
518 COSTS_N_INSNS (3), /* fp */
519 COSTS_N_INSNS (3), /* dmul */
520 COSTS_N_INSNS (17), /* sdiv */
521 COSTS_N_INSNS (31), /* ddiv */
524 /* Instruction costs on PPC7450 processors. */
526 struct processor_costs ppc7450_cost = {
527 COSTS_N_INSNS (4), /* mulsi */
528 COSTS_N_INSNS (3), /* mulsi_const */
529 COSTS_N_INSNS (3), /* mulsi_const9 */
530 COSTS_N_INSNS (4), /* muldi */
531 COSTS_N_INSNS (23), /* divsi */
532 COSTS_N_INSNS (23), /* divdi */
533 COSTS_N_INSNS (5), /* fp */
534 COSTS_N_INSNS (5), /* dmul */
535 COSTS_N_INSNS (21), /* sdiv */
536 COSTS_N_INSNS (35), /* ddiv */
539 /* Instruction costs on PPC8540 processors. */
541 struct processor_costs ppc8540_cost = {
542 COSTS_N_INSNS (4), /* mulsi */
543 COSTS_N_INSNS (4), /* mulsi_const */
544 COSTS_N_INSNS (4), /* mulsi_const9 */
545 COSTS_N_INSNS (4), /* muldi */
546 COSTS_N_INSNS (19), /* divsi */
547 COSTS_N_INSNS (19), /* divdi */
548 COSTS_N_INSNS (4), /* fp */
549 COSTS_N_INSNS (4), /* dmul */
550 COSTS_N_INSNS (29), /* sdiv */
551 COSTS_N_INSNS (29), /* ddiv */
554 /* Instruction costs on POWER4 and POWER5 processors. */
556 struct processor_costs power4_cost = {
557 COSTS_N_INSNS (3), /* mulsi */
558 COSTS_N_INSNS (2), /* mulsi_const */
559 COSTS_N_INSNS (2), /* mulsi_const9 */
560 COSTS_N_INSNS (4), /* muldi */
561 COSTS_N_INSNS (18), /* divsi */
562 COSTS_N_INSNS (34), /* divdi */
563 COSTS_N_INSNS (3), /* fp */
564 COSTS_N_INSNS (3), /* dmul */
565 COSTS_N_INSNS (17), /* sdiv */
566 COSTS_N_INSNS (17), /* ddiv */
570 static bool rs6000_function_ok_for_sibcall (tree, tree);
571 static const char *rs6000_invalid_within_doloop (rtx);
572 static rtx rs6000_generate_compare (enum rtx_code);
573 static void rs6000_maybe_dead (rtx);
574 static void rs6000_emit_stack_tie (void);
575 static void rs6000_frame_related (rtx, rtx, HOST_WIDE_INT, rtx, rtx);
576 static rtx spe_synthesize_frame_save (rtx);
577 static bool spe_func_has_64bit_regs_p (void);
578 static void emit_frame_save (rtx, rtx, enum machine_mode, unsigned int,
580 static rtx gen_frame_mem_offset (enum machine_mode, rtx, int);
581 static void rs6000_emit_allocate_stack (HOST_WIDE_INT, int);
582 static unsigned rs6000_hash_constant (rtx);
583 static unsigned toc_hash_function (const void *);
584 static int toc_hash_eq (const void *, const void *);
585 static int constant_pool_expr_1 (rtx, int *, int *);
586 static bool constant_pool_expr_p (rtx);
587 static bool legitimate_small_data_p (enum machine_mode, rtx);
588 static bool legitimate_indexed_address_p (rtx, int);
589 static bool legitimate_lo_sum_address_p (enum machine_mode, rtx, int);
590 static struct machine_function * rs6000_init_machine_status (void);
591 static bool rs6000_assemble_integer (rtx, unsigned int, int);
592 static bool no_global_regs_above (int);
593 #ifdef HAVE_GAS_HIDDEN
594 static void rs6000_assemble_visibility (tree, int);
596 static int rs6000_ra_ever_killed (void);
597 static tree rs6000_handle_longcall_attribute (tree *, tree, tree, int, bool *);
598 static tree rs6000_handle_altivec_attribute (tree *, tree, tree, int, bool *);
599 static void rs6000_eliminate_indexed_memrefs (rtx operands[2]);
600 static const char *rs6000_mangle_fundamental_type (tree);
601 extern const struct attribute_spec rs6000_attribute_table[];
602 static void rs6000_set_default_type_attributes (tree);
603 static void rs6000_output_function_prologue (FILE *, HOST_WIDE_INT);
604 static void rs6000_output_function_epilogue (FILE *, HOST_WIDE_INT);
605 static void rs6000_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT,
607 static rtx rs6000_emit_set_long_const (rtx, HOST_WIDE_INT, HOST_WIDE_INT);
608 static bool rs6000_return_in_memory (tree, tree);
609 static void rs6000_file_start (void);
611 static unsigned int rs6000_elf_section_type_flags (tree, const char *, int);
612 static void rs6000_elf_asm_out_constructor (rtx, int);
613 static void rs6000_elf_asm_out_destructor (rtx, int);
614 static void rs6000_elf_end_indicate_exec_stack (void) ATTRIBUTE_UNUSED;
615 static void rs6000_elf_select_section (tree, int, unsigned HOST_WIDE_INT);
616 static void rs6000_elf_unique_section (tree, int);
617 static void rs6000_elf_select_rtx_section (enum machine_mode, rtx,
618 unsigned HOST_WIDE_INT);
619 static void rs6000_elf_encode_section_info (tree, rtx, int)
621 static bool rs6000_elf_in_small_data_p (tree);
624 static void rs6000_xcoff_asm_globalize_label (FILE *, const char *);
625 static void rs6000_xcoff_asm_named_section (const char *, unsigned int, tree);
626 static void rs6000_xcoff_select_section (tree, int, unsigned HOST_WIDE_INT);
627 static void rs6000_xcoff_unique_section (tree, int);
628 static void rs6000_xcoff_select_rtx_section (enum machine_mode, rtx,
629 unsigned HOST_WIDE_INT);
630 static const char * rs6000_xcoff_strip_name_encoding (const char *);
631 static unsigned int rs6000_xcoff_section_type_flags (tree, const char *, int);
632 static void rs6000_xcoff_file_start (void);
633 static void rs6000_xcoff_file_end (void);
635 static int rs6000_variable_issue (FILE *, int, rtx, int);
636 static bool rs6000_rtx_costs (rtx, int, int, int *);
637 static int rs6000_adjust_cost (rtx, rtx, rtx, int);
638 static bool is_microcoded_insn (rtx);
639 static int is_dispatch_slot_restricted (rtx);
640 static bool is_cracked_insn (rtx);
641 static bool is_branch_slot_insn (rtx);
642 static int rs6000_adjust_priority (rtx, int);
643 static int rs6000_issue_rate (void);
644 static bool rs6000_is_costly_dependence (rtx, rtx, rtx, int, int);
645 static rtx get_next_active_insn (rtx, rtx);
646 static bool insn_terminates_group_p (rtx , enum group_termination);
647 static bool is_costly_group (rtx *, rtx);
648 static int force_new_group (int, FILE *, rtx *, rtx, bool *, int, int *);
649 static int redefine_groups (FILE *, int, rtx, rtx);
650 static int pad_groups (FILE *, int, rtx, rtx);
651 static void rs6000_sched_finish (FILE *, int);
652 static int rs6000_use_sched_lookahead (void);
653 static tree rs6000_builtin_mask_for_load (void);
655 static void def_builtin (int, const char *, tree, int);
656 static void rs6000_init_builtins (void);
657 static rtx rs6000_expand_unop_builtin (enum insn_code, tree, rtx);
658 static rtx rs6000_expand_binop_builtin (enum insn_code, tree, rtx);
659 static rtx rs6000_expand_ternop_builtin (enum insn_code, tree, rtx);
660 static rtx rs6000_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
661 static void altivec_init_builtins (void);
662 static void rs6000_common_init_builtins (void);
663 static void rs6000_init_libfuncs (void);
665 static void enable_mask_for_builtins (struct builtin_description *, int,
666 enum rs6000_builtins,
667 enum rs6000_builtins);
668 static tree build_opaque_vector_type (tree, int);
669 static void spe_init_builtins (void);
670 static rtx spe_expand_builtin (tree, rtx, bool *);
671 static rtx spe_expand_stv_builtin (enum insn_code, tree);
672 static rtx spe_expand_predicate_builtin (enum insn_code, tree, rtx);
673 static rtx spe_expand_evsel_builtin (enum insn_code, tree, rtx);
674 static int rs6000_emit_int_cmove (rtx, rtx, rtx, rtx);
675 static rs6000_stack_t *rs6000_stack_info (void);
676 static void debug_stack_info (rs6000_stack_t *);
678 static rtx altivec_expand_builtin (tree, rtx, bool *);
679 static rtx altivec_expand_ld_builtin (tree, rtx, bool *);
680 static rtx altivec_expand_st_builtin (tree, rtx, bool *);
681 static rtx altivec_expand_dst_builtin (tree, rtx, bool *);
682 static rtx altivec_expand_abs_builtin (enum insn_code, tree, rtx);
683 static rtx altivec_expand_predicate_builtin (enum insn_code,
684 const char *, tree, rtx);
685 static rtx altivec_expand_lv_builtin (enum insn_code, tree, rtx);
686 static rtx altivec_expand_stv_builtin (enum insn_code, tree);
687 static rtx altivec_expand_vec_init_builtin (tree, tree, rtx);
688 static rtx altivec_expand_vec_set_builtin (tree);
689 static rtx altivec_expand_vec_ext_builtin (tree, rtx);
690 static int get_element_number (tree, tree);
691 static bool rs6000_handle_option (size_t, const char *, int);
692 static void rs6000_parse_tls_size_option (void);
693 static void rs6000_parse_yes_no_option (const char *, const char *, int *);
694 static int first_altivec_reg_to_save (void);
695 static unsigned int compute_vrsave_mask (void);
696 static void compute_save_world_info (rs6000_stack_t *info_ptr);
697 static void is_altivec_return_reg (rtx, void *);
698 static rtx generate_set_vrsave (rtx, rs6000_stack_t *, int);
699 int easy_vector_constant (rtx, enum machine_mode);
700 static bool rs6000_is_opaque_type (tree);
701 static rtx rs6000_dwarf_register_span (rtx);
702 static rtx rs6000_legitimize_tls_address (rtx, enum tls_model);
703 static void rs6000_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED;
704 static rtx rs6000_tls_get_addr (void);
705 static rtx rs6000_got_sym (void);
706 static int rs6000_tls_symbol_ref_1 (rtx *, void *);
707 static const char *rs6000_get_some_local_dynamic_name (void);
708 static int rs6000_get_some_local_dynamic_name_1 (rtx *, void *);
709 static rtx rs6000_complex_function_value (enum machine_mode);
710 static rtx rs6000_spe_function_arg (CUMULATIVE_ARGS *,
711 enum machine_mode, tree);
712 static void rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *,
714 static void rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *,
715 tree, HOST_WIDE_INT);
716 static void rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *,
719 static void rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *,
722 static rtx rs6000_darwin64_record_arg (CUMULATIVE_ARGS *, tree, int, bool);
723 static rtx rs6000_mixed_function_arg (enum machine_mode, tree, int);
724 static void rs6000_move_block_from_reg (int regno, rtx x, int nregs);
725 static void setup_incoming_varargs (CUMULATIVE_ARGS *,
726 enum machine_mode, tree,
728 static bool rs6000_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
730 static int rs6000_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
732 static const char *invalid_arg_for_unprototyped_fn (tree, tree, tree);
734 static void macho_branch_islands (void);
735 static void add_compiler_branch_island (tree, tree, int);
736 static int no_previous_def (tree function_name);
737 static tree get_prev_label (tree function_name);
738 static void rs6000_darwin_file_start (void);
741 static tree rs6000_build_builtin_va_list (void);
742 static tree rs6000_gimplify_va_arg (tree, tree, tree *, tree *);
743 static bool rs6000_must_pass_in_stack (enum machine_mode, tree);
744 static bool rs6000_vector_mode_supported_p (enum machine_mode);
745 static int get_vec_cmp_insn (enum rtx_code, enum machine_mode,
747 static rtx rs6000_emit_vector_compare (enum rtx_code, rtx, rtx,
749 static int get_vsel_insn (enum machine_mode);
750 static void rs6000_emit_vector_select (rtx, rtx, rtx, rtx);
751 static tree rs6000_stack_protect_fail (void);
753 const int INSN_NOT_AVAILABLE = -1;
754 static enum machine_mode rs6000_eh_return_filter_mode (void);
756 /* Hash table stuff for keeping track of TOC entries. */
758 struct toc_hash_struct GTY(())
760 /* `key' will satisfy CONSTANT_P; in fact, it will satisfy
761 ASM_OUTPUT_SPECIAL_POOL_ENTRY_P. */
763 enum machine_mode key_mode;
767 static GTY ((param_is (struct toc_hash_struct))) htab_t toc_hash_table;
769 /* Default register names. */
770 char rs6000_reg_names[][8] =
772 "0", "1", "2", "3", "4", "5", "6", "7",
773 "8", "9", "10", "11", "12", "13", "14", "15",
774 "16", "17", "18", "19", "20", "21", "22", "23",
775 "24", "25", "26", "27", "28", "29", "30", "31",
776 "0", "1", "2", "3", "4", "5", "6", "7",
777 "8", "9", "10", "11", "12", "13", "14", "15",
778 "16", "17", "18", "19", "20", "21", "22", "23",
779 "24", "25", "26", "27", "28", "29", "30", "31",
780 "mq", "lr", "ctr","ap",
781 "0", "1", "2", "3", "4", "5", "6", "7",
783 /* AltiVec registers. */
784 "0", "1", "2", "3", "4", "5", "6", "7",
785 "8", "9", "10", "11", "12", "13", "14", "15",
786 "16", "17", "18", "19", "20", "21", "22", "23",
787 "24", "25", "26", "27", "28", "29", "30", "31",
790 "spe_acc", "spefscr",
791 /* Soft frame pointer. */
795 #ifdef TARGET_REGNAMES
796 static const char alt_reg_names[][8] =
798 "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7",
799 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
800 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
801 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
802 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7",
803 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15",
804 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23",
805 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31",
806 "mq", "lr", "ctr", "ap",
807 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
809 /* AltiVec registers. */
810 "%v0", "%v1", "%v2", "%v3", "%v4", "%v5", "%v6", "%v7",
811 "%v8", "%v9", "%v10", "%v11", "%v12", "%v13", "%v14", "%v15",
812 "%v16", "%v17", "%v18", "%v19", "%v20", "%v21", "%v22", "%v23",
813 "%v24", "%v25", "%v26", "%v27", "%v28", "%v29", "%v30", "%v31",
816 "spe_acc", "spefscr",
817 /* Soft frame pointer. */
822 #ifndef MASK_STRICT_ALIGN
823 #define MASK_STRICT_ALIGN 0
825 #ifndef TARGET_PROFILE_KERNEL
826 #define TARGET_PROFILE_KERNEL 0
829 /* The VRSAVE bitmask puts bit %v0 as the most significant bit. */
830 #define ALTIVEC_REG_BIT(REGNO) (0x80000000 >> ((REGNO) - FIRST_ALTIVEC_REGNO))
832 /* Initialize the GCC target structure. */
833 #undef TARGET_ATTRIBUTE_TABLE
834 #define TARGET_ATTRIBUTE_TABLE rs6000_attribute_table
835 #undef TARGET_SET_DEFAULT_TYPE_ATTRIBUTES
836 #define TARGET_SET_DEFAULT_TYPE_ATTRIBUTES rs6000_set_default_type_attributes
838 #undef TARGET_ASM_ALIGNED_DI_OP
839 #define TARGET_ASM_ALIGNED_DI_OP DOUBLE_INT_ASM_OP
841 /* Default unaligned ops are only provided for ELF. Find the ops needed
842 for non-ELF systems. */
843 #ifndef OBJECT_FORMAT_ELF
845 /* For XCOFF. rs6000_assemble_integer will handle unaligned DIs on
847 #undef TARGET_ASM_UNALIGNED_HI_OP
848 #define TARGET_ASM_UNALIGNED_HI_OP "\t.vbyte\t2,"
849 #undef TARGET_ASM_UNALIGNED_SI_OP
850 #define TARGET_ASM_UNALIGNED_SI_OP "\t.vbyte\t4,"
851 #undef TARGET_ASM_UNALIGNED_DI_OP
852 #define TARGET_ASM_UNALIGNED_DI_OP "\t.vbyte\t8,"
855 #undef TARGET_ASM_UNALIGNED_HI_OP
856 #define TARGET_ASM_UNALIGNED_HI_OP "\t.short\t"
857 #undef TARGET_ASM_UNALIGNED_SI_OP
858 #define TARGET_ASM_UNALIGNED_SI_OP "\t.long\t"
859 #undef TARGET_ASM_UNALIGNED_DI_OP
860 #define TARGET_ASM_UNALIGNED_DI_OP "\t.quad\t"
861 #undef TARGET_ASM_ALIGNED_DI_OP
862 #define TARGET_ASM_ALIGNED_DI_OP "\t.quad\t"
866 /* This hook deals with fixups for relocatable code and DI-mode objects
868 #undef TARGET_ASM_INTEGER
869 #define TARGET_ASM_INTEGER rs6000_assemble_integer
871 #ifdef HAVE_GAS_HIDDEN
872 #undef TARGET_ASM_ASSEMBLE_VISIBILITY
873 #define TARGET_ASM_ASSEMBLE_VISIBILITY rs6000_assemble_visibility
876 #undef TARGET_HAVE_TLS
877 #define TARGET_HAVE_TLS HAVE_AS_TLS
879 #undef TARGET_CANNOT_FORCE_CONST_MEM
880 #define TARGET_CANNOT_FORCE_CONST_MEM rs6000_tls_referenced_p
882 #undef TARGET_ASM_FUNCTION_PROLOGUE
883 #define TARGET_ASM_FUNCTION_PROLOGUE rs6000_output_function_prologue
884 #undef TARGET_ASM_FUNCTION_EPILOGUE
885 #define TARGET_ASM_FUNCTION_EPILOGUE rs6000_output_function_epilogue
887 #undef TARGET_SCHED_VARIABLE_ISSUE
888 #define TARGET_SCHED_VARIABLE_ISSUE rs6000_variable_issue
890 #undef TARGET_SCHED_ISSUE_RATE
891 #define TARGET_SCHED_ISSUE_RATE rs6000_issue_rate
892 #undef TARGET_SCHED_ADJUST_COST
893 #define TARGET_SCHED_ADJUST_COST rs6000_adjust_cost
894 #undef TARGET_SCHED_ADJUST_PRIORITY
895 #define TARGET_SCHED_ADJUST_PRIORITY rs6000_adjust_priority
896 #undef TARGET_SCHED_IS_COSTLY_DEPENDENCE
897 #define TARGET_SCHED_IS_COSTLY_DEPENDENCE rs6000_is_costly_dependence
898 #undef TARGET_SCHED_FINISH
899 #define TARGET_SCHED_FINISH rs6000_sched_finish
901 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
902 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD rs6000_use_sched_lookahead
904 #undef TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD
905 #define TARGET_VECTORIZE_BUILTIN_MASK_FOR_LOAD rs6000_builtin_mask_for_load
907 #undef TARGET_INIT_BUILTINS
908 #define TARGET_INIT_BUILTINS rs6000_init_builtins
910 #undef TARGET_EXPAND_BUILTIN
911 #define TARGET_EXPAND_BUILTIN rs6000_expand_builtin
913 #undef TARGET_MANGLE_FUNDAMENTAL_TYPE
914 #define TARGET_MANGLE_FUNDAMENTAL_TYPE rs6000_mangle_fundamental_type
916 #undef TARGET_INIT_LIBFUNCS
917 #define TARGET_INIT_LIBFUNCS rs6000_init_libfuncs
920 #undef TARGET_BINDS_LOCAL_P
921 #define TARGET_BINDS_LOCAL_P darwin_binds_local_p
924 #undef TARGET_ASM_OUTPUT_MI_THUNK
925 #define TARGET_ASM_OUTPUT_MI_THUNK rs6000_output_mi_thunk
927 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
928 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_tree_hwi_hwi_tree_true
930 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
931 #define TARGET_FUNCTION_OK_FOR_SIBCALL rs6000_function_ok_for_sibcall
933 #undef TARGET_INVALID_WITHIN_DOLOOP
934 #define TARGET_INVALID_WITHIN_DOLOOP rs6000_invalid_within_doloop
936 #undef TARGET_RTX_COSTS
937 #define TARGET_RTX_COSTS rs6000_rtx_costs
938 #undef TARGET_ADDRESS_COST
939 #define TARGET_ADDRESS_COST hook_int_rtx_0
941 #undef TARGET_VECTOR_OPAQUE_P
942 #define TARGET_VECTOR_OPAQUE_P rs6000_is_opaque_type
944 #undef TARGET_DWARF_REGISTER_SPAN
945 #define TARGET_DWARF_REGISTER_SPAN rs6000_dwarf_register_span
947 /* On rs6000, function arguments are promoted, as are function return
949 #undef TARGET_PROMOTE_FUNCTION_ARGS
950 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_tree_true
951 #undef TARGET_PROMOTE_FUNCTION_RETURN
952 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
954 #undef TARGET_RETURN_IN_MEMORY
955 #define TARGET_RETURN_IN_MEMORY rs6000_return_in_memory
957 #undef TARGET_SETUP_INCOMING_VARARGS
958 #define TARGET_SETUP_INCOMING_VARARGS setup_incoming_varargs
960 /* Always strict argument naming on rs6000. */
961 #undef TARGET_STRICT_ARGUMENT_NAMING
962 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true
963 #undef TARGET_PRETEND_OUTGOING_VARARGS_NAMED
964 #define TARGET_PRETEND_OUTGOING_VARARGS_NAMED hook_bool_CUMULATIVE_ARGS_true
965 #undef TARGET_SPLIT_COMPLEX_ARG
966 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_tree_true
967 #undef TARGET_MUST_PASS_IN_STACK
968 #define TARGET_MUST_PASS_IN_STACK rs6000_must_pass_in_stack
969 #undef TARGET_PASS_BY_REFERENCE
970 #define TARGET_PASS_BY_REFERENCE rs6000_pass_by_reference
971 #undef TARGET_ARG_PARTIAL_BYTES
972 #define TARGET_ARG_PARTIAL_BYTES rs6000_arg_partial_bytes
974 #undef TARGET_BUILD_BUILTIN_VA_LIST
975 #define TARGET_BUILD_BUILTIN_VA_LIST rs6000_build_builtin_va_list
977 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
978 #define TARGET_GIMPLIFY_VA_ARG_EXPR rs6000_gimplify_va_arg
980 #undef TARGET_EH_RETURN_FILTER_MODE
981 #define TARGET_EH_RETURN_FILTER_MODE rs6000_eh_return_filter_mode
983 #undef TARGET_VECTOR_MODE_SUPPORTED_P
984 #define TARGET_VECTOR_MODE_SUPPORTED_P rs6000_vector_mode_supported_p
986 #undef TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN
987 #define TARGET_INVALID_ARG_FOR_UNPROTOTYPED_FN invalid_arg_for_unprototyped_fn
989 #undef TARGET_HANDLE_OPTION
990 #define TARGET_HANDLE_OPTION rs6000_handle_option
992 #undef TARGET_DEFAULT_TARGET_FLAGS
993 #define TARGET_DEFAULT_TARGET_FLAGS \
994 (TARGET_DEFAULT | MASK_SCHED_PROLOG)
996 #undef TARGET_STACK_PROTECT_FAIL
997 #define TARGET_STACK_PROTECT_FAIL rs6000_stack_protect_fail
999 /* MPC604EUM 3.5.2 Weak Consistency between Multiple Processors
1000 The PowerPC architecture requires only weak consistency among
1001 processors--that is, memory accesses between processors need not be
1002 sequentially consistent and memory accesses among processors can occur
1003 in any order. The ability to order memory accesses weakly provides
1004 opportunities for more efficient use of the system bus. Unless a
1005 dependency exists, the 604e allows read operations to precede store
1007 #undef TARGET_RELAXED_ORDERING
1008 #define TARGET_RELAXED_ORDERING true
1011 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL
1012 #define TARGET_ASM_OUTPUT_DWARF_DTPREL rs6000_output_dwarf_dtprel
1015 struct gcc_target targetm = TARGET_INITIALIZER;
1018 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1021 rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
1023 /* The GPRs can hold any mode, but values bigger than one register
1024 cannot go past R31. */
1025 if (INT_REGNO_P (regno))
1026 return INT_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1);
1028 /* The float registers can only hold floating modes and DImode. */
1029 if (FP_REGNO_P (regno))
1031 (GET_MODE_CLASS (mode) == MODE_FLOAT
1032 && FP_REGNO_P (regno + HARD_REGNO_NREGS (regno, mode) - 1))
1033 || (GET_MODE_CLASS (mode) == MODE_INT
1034 && GET_MODE_SIZE (mode) == UNITS_PER_FP_WORD);
1036 /* The CR register can only hold CC modes. */
1037 if (CR_REGNO_P (regno))
1038 return GET_MODE_CLASS (mode) == MODE_CC;
1040 if (XER_REGNO_P (regno))
1041 return mode == PSImode;
1043 /* AltiVec only in AldyVec registers. */
1044 if (ALTIVEC_REGNO_P (regno))
1045 return ALTIVEC_VECTOR_MODE (mode);
1047 /* ...but GPRs can hold SIMD data on the SPE in one register. */
1048 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
1051 /* We cannot put TImode anywhere except general register and it must be
1052 able to fit within the register set. */
1054 return GET_MODE_SIZE (mode) <= UNITS_PER_WORD;
1057 /* Initialize rs6000_hard_regno_mode_ok_p table. */
1059 rs6000_init_hard_regno_mode_ok (void)
1063 for (r = 0; r < FIRST_PSEUDO_REGISTER; ++r)
1064 for (m = 0; m < NUM_MACHINE_MODES; ++m)
1065 if (rs6000_hard_regno_mode_ok (r, m))
1066 rs6000_hard_regno_mode_ok_p[m][r] = true;
1069 /* If not otherwise specified by a target, make 'long double' equivalent to
1072 #ifndef RS6000_DEFAULT_LONG_DOUBLE_SIZE
1073 #define RS6000_DEFAULT_LONG_DOUBLE_SIZE 64
1076 /* Override command line options. Mostly we process the processor
1077 type and sometimes adjust other TARGET_ options. */
1080 rs6000_override_options (const char *default_cpu)
1083 struct rs6000_cpu_select *ptr;
1086 /* Simplifications for entries below. */
1089 POWERPC_BASE_MASK = MASK_POWERPC | MASK_NEW_MNEMONICS,
1090 POWERPC_7400_MASK = POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_ALTIVEC
1093 /* This table occasionally claims that a processor does not support
1094 a particular feature even though it does, but the feature is slower
1095 than the alternative. Thus, it shouldn't be relied on as a
1096 complete description of the processor's support.
1098 Please keep this list in order, and don't forget to update the
1099 documentation in invoke.texi when adding a new processor or
1103 const char *const name; /* Canonical processor name. */
1104 const enum processor_type processor; /* Processor type enum value. */
1105 const int target_enable; /* Target flags to enable. */
1106 } const processor_target_table[]
1107 = {{"401", PROCESSOR_PPC403, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1108 {"403", PROCESSOR_PPC403,
1109 POWERPC_BASE_MASK | MASK_SOFT_FLOAT | MASK_STRICT_ALIGN},
1110 {"405", PROCESSOR_PPC405, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1111 {"405fp", PROCESSOR_PPC405, POWERPC_BASE_MASK},
1112 {"440", PROCESSOR_PPC440, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1113 {"440fp", PROCESSOR_PPC440, POWERPC_BASE_MASK},
1114 {"505", PROCESSOR_MPCCORE, POWERPC_BASE_MASK},
1115 {"601", PROCESSOR_PPC601,
1116 MASK_POWER | POWERPC_BASE_MASK | MASK_MULTIPLE | MASK_STRING},
1117 {"602", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1118 {"603", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1119 {"603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1120 {"604", PROCESSOR_PPC604, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1121 {"604e", PROCESSOR_PPC604e, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1122 {"620", PROCESSOR_PPC620,
1123 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1124 {"630", PROCESSOR_PPC630,
1125 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1126 {"740", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1127 {"7400", PROCESSOR_PPC7400, POWERPC_7400_MASK},
1128 {"7450", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1129 {"750", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1130 {"801", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1131 {"821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1132 {"823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1133 {"8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1134 /* 8548 has a dummy entry for now. */
1135 {"8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1136 {"860", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1137 {"970", PROCESSOR_POWER4,
1138 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1139 {"common", PROCESSOR_COMMON, MASK_NEW_MNEMONICS},
1140 {"ec603e", PROCESSOR_PPC603, POWERPC_BASE_MASK | MASK_SOFT_FLOAT},
1141 {"G3", PROCESSOR_PPC750, POWERPC_BASE_MASK | MASK_PPC_GFXOPT},
1142 {"G4", PROCESSOR_PPC7450, POWERPC_7400_MASK},
1143 {"G5", PROCESSOR_POWER4,
1144 POWERPC_7400_MASK | MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64},
1145 {"power", PROCESSOR_POWER, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1146 {"power2", PROCESSOR_POWER,
1147 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1148 {"power3", PROCESSOR_PPC630,
1149 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1150 {"power4", PROCESSOR_POWER4,
1151 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
1152 {"power5", PROCESSOR_POWER5,
1153 POWERPC_BASE_MASK | MASK_POWERPC64 | MASK_PPC_GFXOPT
1154 | MASK_MFCRF | MASK_POPCNTB},
1155 {"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
1156 {"powerpc64", PROCESSOR_POWERPC64,
1157 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
1158 {"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1159 {"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1160 {"rios2", PROCESSOR_RIOS2,
1161 MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
1162 {"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1163 {"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
1164 {"rs64", PROCESSOR_RS64A,
1165 POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
1168 const size_t ptt_size = ARRAY_SIZE (processor_target_table);
1170 /* Some OSs don't support saving the high part of 64-bit registers on
1171 context switch. Other OSs don't support saving Altivec registers.
1172 On those OSs, we don't touch the MASK_POWERPC64 or MASK_ALTIVEC
1173 settings; if the user wants either, the user must explicitly specify
1174 them and we won't interfere with the user's specification. */
1177 POWER_MASKS = MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING,
1178 POWERPC_MASKS = (POWERPC_BASE_MASK | MASK_PPC_GPOPT
1179 | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_ALTIVEC
1183 rs6000_init_hard_regno_mode_ok ();
1185 set_masks = POWER_MASKS | POWERPC_MASKS | MASK_SOFT_FLOAT;
1186 #ifdef OS_MISSING_POWERPC64
1187 if (OS_MISSING_POWERPC64)
1188 set_masks &= ~MASK_POWERPC64;
1190 #ifdef OS_MISSING_ALTIVEC
1191 if (OS_MISSING_ALTIVEC)
1192 set_masks &= ~MASK_ALTIVEC;
1195 /* Don't override by the processor default if given explicitly. */
1196 set_masks &= ~target_flags_explicit;
1198 /* Identify the processor type. */
1199 rs6000_select[0].string = default_cpu;
1200 rs6000_cpu = TARGET_POWERPC64 ? PROCESSOR_DEFAULT64 : PROCESSOR_DEFAULT;
1202 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1204 ptr = &rs6000_select[i];
1205 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1207 for (j = 0; j < ptt_size; j++)
1208 if (! strcmp (ptr->string, processor_target_table[j].name))
1210 if (ptr->set_tune_p)
1211 rs6000_cpu = processor_target_table[j].processor;
1213 if (ptr->set_arch_p)
1215 target_flags &= ~set_masks;
1216 target_flags |= (processor_target_table[j].target_enable
1223 error ("bad value (%s) for %s switch", ptr->string, ptr->name);
1230 /* If we are optimizing big endian systems for space, use the load/store
1231 multiple and string instructions. */
1232 if (BYTES_BIG_ENDIAN && optimize_size)
1233 target_flags |= ~target_flags_explicit & (MASK_MULTIPLE | MASK_STRING);
1235 /* Don't allow -mmultiple or -mstring on little endian systems
1236 unless the cpu is a 750, because the hardware doesn't support the
1237 instructions used in little endian mode, and causes an alignment
1238 trap. The 750 does not cause an alignment trap (except when the
1239 target is unaligned). */
1241 if (!BYTES_BIG_ENDIAN && rs6000_cpu != PROCESSOR_PPC750)
1243 if (TARGET_MULTIPLE)
1245 target_flags &= ~MASK_MULTIPLE;
1246 if ((target_flags_explicit & MASK_MULTIPLE) != 0)
1247 warning (0, "-mmultiple is not supported on little endian systems");
1252 target_flags &= ~MASK_STRING;
1253 if ((target_flags_explicit & MASK_STRING) != 0)
1254 warning (0, "-mstring is not supported on little endian systems");
1258 /* Set debug flags */
1259 if (rs6000_debug_name)
1261 if (! strcmp (rs6000_debug_name, "all"))
1262 rs6000_debug_stack = rs6000_debug_arg = 1;
1263 else if (! strcmp (rs6000_debug_name, "stack"))
1264 rs6000_debug_stack = 1;
1265 else if (! strcmp (rs6000_debug_name, "arg"))
1266 rs6000_debug_arg = 1;
1268 error ("unknown -mdebug-%s switch", rs6000_debug_name);
1271 if (rs6000_traceback_name)
1273 if (! strncmp (rs6000_traceback_name, "full", 4))
1274 rs6000_traceback = traceback_full;
1275 else if (! strncmp (rs6000_traceback_name, "part", 4))
1276 rs6000_traceback = traceback_part;
1277 else if (! strncmp (rs6000_traceback_name, "no", 2))
1278 rs6000_traceback = traceback_none;
1280 error ("unknown -mtraceback arg %qs; expecting %<full%>, %<partial%> or %<none%>",
1281 rs6000_traceback_name);
1284 if (!rs6000_explicit_options.long_double)
1285 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1287 /* Set Altivec ABI as default for powerpc64 linux. */
1288 if (TARGET_ELF && TARGET_64BIT)
1290 rs6000_altivec_abi = 1;
1291 TARGET_ALTIVEC_VRSAVE = 1;
1294 /* Set the Darwin64 ABI as default for 64-bit Darwin. */
1295 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1297 rs6000_darwin64_abi = 1;
1299 darwin_one_byte_bool = 1;
1301 /* Default to natural alignment, for better performance. */
1302 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1305 /* Handle -mtls-size option. */
1306 rs6000_parse_tls_size_option ();
1308 #ifdef SUBTARGET_OVERRIDE_OPTIONS
1309 SUBTARGET_OVERRIDE_OPTIONS;
1311 #ifdef SUBSUBTARGET_OVERRIDE_OPTIONS
1312 SUBSUBTARGET_OVERRIDE_OPTIONS;
1314 #ifdef SUB3TARGET_OVERRIDE_OPTIONS
1315 SUB3TARGET_OVERRIDE_OPTIONS;
1321 error ("AltiVec and E500 instructions cannot coexist");
1323 /* The e500 does not have string instructions, and we set
1324 MASK_STRING above when optimizing for size. */
1325 if ((target_flags & MASK_STRING) != 0)
1326 target_flags = target_flags & ~MASK_STRING;
1328 else if (rs6000_select[1].string != NULL)
1330 /* For the powerpc-eabispe configuration, we set all these by
1331 default, so let's unset them if we manually set another
1332 CPU that is not the E500. */
1333 if (!rs6000_explicit_options.abi)
1335 if (!rs6000_explicit_options.spe)
1337 if (!rs6000_explicit_options.float_gprs)
1338 rs6000_float_gprs = 0;
1339 if (!rs6000_explicit_options.isel)
1341 if (!rs6000_explicit_options.long_double)
1342 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1345 rs6000_always_hint = (rs6000_cpu != PROCESSOR_POWER4
1346 && rs6000_cpu != PROCESSOR_POWER5);
1347 rs6000_sched_groups = (rs6000_cpu == PROCESSOR_POWER4
1348 || rs6000_cpu == PROCESSOR_POWER5);
1350 rs6000_sched_restricted_insns_priority
1351 = (rs6000_sched_groups ? 1 : 0);
1353 /* Handle -msched-costly-dep option. */
1354 rs6000_sched_costly_dep
1355 = (rs6000_sched_groups ? store_to_load_dep_costly : no_dep_costly);
1357 if (rs6000_sched_costly_dep_str)
1359 if (! strcmp (rs6000_sched_costly_dep_str, "no"))
1360 rs6000_sched_costly_dep = no_dep_costly;
1361 else if (! strcmp (rs6000_sched_costly_dep_str, "all"))
1362 rs6000_sched_costly_dep = all_deps_costly;
1363 else if (! strcmp (rs6000_sched_costly_dep_str, "true_store_to_load"))
1364 rs6000_sched_costly_dep = true_store_to_load_dep_costly;
1365 else if (! strcmp (rs6000_sched_costly_dep_str, "store_to_load"))
1366 rs6000_sched_costly_dep = store_to_load_dep_costly;
1368 rs6000_sched_costly_dep = atoi (rs6000_sched_costly_dep_str);
1371 /* Handle -minsert-sched-nops option. */
1372 rs6000_sched_insert_nops
1373 = (rs6000_sched_groups ? sched_finish_regroup_exact : sched_finish_none);
1375 if (rs6000_sched_insert_nops_str)
1377 if (! strcmp (rs6000_sched_insert_nops_str, "no"))
1378 rs6000_sched_insert_nops = sched_finish_none;
1379 else if (! strcmp (rs6000_sched_insert_nops_str, "pad"))
1380 rs6000_sched_insert_nops = sched_finish_pad_groups;
1381 else if (! strcmp (rs6000_sched_insert_nops_str, "regroup_exact"))
1382 rs6000_sched_insert_nops = sched_finish_regroup_exact;
1384 rs6000_sched_insert_nops = atoi (rs6000_sched_insert_nops_str);
1387 #ifdef TARGET_REGNAMES
1388 /* If the user desires alternate register names, copy in the
1389 alternate names now. */
1390 if (TARGET_REGNAMES)
1391 memcpy (rs6000_reg_names, alt_reg_names, sizeof (rs6000_reg_names));
1394 /* Set aix_struct_return last, after the ABI is determined.
1395 If -maix-struct-return or -msvr4-struct-return was explicitly
1396 used, don't override with the ABI default. */
1397 if (!rs6000_explicit_options.aix_struct_ret)
1398 aix_struct_return = (DEFAULT_ABI != ABI_V4 || DRAFT_V4_STRUCT_RET);
1400 if (TARGET_LONG_DOUBLE_128
1401 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN))
1402 REAL_MODE_FORMAT (TFmode) = &ibm_extended_format;
1404 /* Allocate an alias set for register saves & restores from stack. */
1405 rs6000_sr_alias_set = new_alias_set ();
1408 ASM_GENERATE_INTERNAL_LABEL (toc_label_name, "LCTOC", 1);
1410 /* We can only guarantee the availability of DI pseudo-ops when
1411 assembling for 64-bit targets. */
1414 targetm.asm_out.aligned_op.di = NULL;
1415 targetm.asm_out.unaligned_op.di = NULL;
1418 /* Set branch target alignment, if not optimizing for size. */
1421 if (rs6000_sched_groups)
1423 if (align_functions <= 0)
1424 align_functions = 16;
1425 if (align_jumps <= 0)
1427 if (align_loops <= 0)
1430 if (align_jumps_max_skip <= 0)
1431 align_jumps_max_skip = 15;
1432 if (align_loops_max_skip <= 0)
1433 align_loops_max_skip = 15;
1436 /* Arrange to save and restore machine status around nested functions. */
1437 init_machine_status = rs6000_init_machine_status;
1439 /* We should always be splitting complex arguments, but we can't break
1440 Linux and Darwin ABIs at the moment. For now, only AIX is fixed. */
1441 if (DEFAULT_ABI != ABI_AIX)
1442 targetm.calls.split_complex_arg = NULL;
1444 /* Initialize rs6000_cost with the appropriate target costs. */
1446 rs6000_cost = TARGET_POWERPC64 ? &size64_cost : &size32_cost;
1450 case PROCESSOR_RIOS1:
1451 rs6000_cost = &rios1_cost;
1454 case PROCESSOR_RIOS2:
1455 rs6000_cost = &rios2_cost;
1458 case PROCESSOR_RS64A:
1459 rs6000_cost = &rs64a_cost;
1462 case PROCESSOR_MPCCORE:
1463 rs6000_cost = &mpccore_cost;
1466 case PROCESSOR_PPC403:
1467 rs6000_cost = &ppc403_cost;
1470 case PROCESSOR_PPC405:
1471 rs6000_cost = &ppc405_cost;
1474 case PROCESSOR_PPC440:
1475 rs6000_cost = &ppc440_cost;
1478 case PROCESSOR_PPC601:
1479 rs6000_cost = &ppc601_cost;
1482 case PROCESSOR_PPC603:
1483 rs6000_cost = &ppc603_cost;
1486 case PROCESSOR_PPC604:
1487 rs6000_cost = &ppc604_cost;
1490 case PROCESSOR_PPC604e:
1491 rs6000_cost = &ppc604e_cost;
1494 case PROCESSOR_PPC620:
1495 rs6000_cost = &ppc620_cost;
1498 case PROCESSOR_PPC630:
1499 rs6000_cost = &ppc630_cost;
1502 case PROCESSOR_PPC750:
1503 case PROCESSOR_PPC7400:
1504 rs6000_cost = &ppc750_cost;
1507 case PROCESSOR_PPC7450:
1508 rs6000_cost = &ppc7450_cost;
1511 case PROCESSOR_PPC8540:
1512 rs6000_cost = &ppc8540_cost;
1515 case PROCESSOR_POWER4:
1516 case PROCESSOR_POWER5:
1517 rs6000_cost = &power4_cost;
1525 /* Implement targetm.vectorize.builtin_mask_for_load. */
1527 rs6000_builtin_mask_for_load (void)
1530 return altivec_builtin_mask_for_load;
1535 /* Handle generic options of the form -mfoo=yes/no.
1536 NAME is the option name.
1537 VALUE is the option value.
1538 FLAG is the pointer to the flag where to store a 1 or 0, depending on
1539 whether the option value is 'yes' or 'no' respectively. */
1541 rs6000_parse_yes_no_option (const char *name, const char *value, int *flag)
1545 else if (!strcmp (value, "yes"))
1547 else if (!strcmp (value, "no"))
1550 error ("unknown -m%s= option specified: '%s'", name, value);
1553 /* Validate and record the size specified with the -mtls-size option. */
1556 rs6000_parse_tls_size_option (void)
1558 if (rs6000_tls_size_string == 0)
1560 else if (strcmp (rs6000_tls_size_string, "16") == 0)
1561 rs6000_tls_size = 16;
1562 else if (strcmp (rs6000_tls_size_string, "32") == 0)
1563 rs6000_tls_size = 32;
1564 else if (strcmp (rs6000_tls_size_string, "64") == 0)
1565 rs6000_tls_size = 64;
1567 error ("bad value %qs for -mtls-size switch", rs6000_tls_size_string);
1571 optimization_options (int level ATTRIBUTE_UNUSED, int size ATTRIBUTE_UNUSED)
1573 if (DEFAULT_ABI == ABI_DARWIN)
1574 /* The Darwin libraries never set errno, so we might as well
1575 avoid calling them when that's the only reason we would. */
1576 flag_errno_math = 0;
1579 /* Implement TARGET_HANDLE_OPTION. */
1582 rs6000_handle_option (size_t code, const char *arg, int value)
1587 target_flags &= ~(MASK_POWER | MASK_POWER2
1588 | MASK_MULTIPLE | MASK_STRING);
1589 target_flags_explicit |= (MASK_POWER | MASK_POWER2
1590 | MASK_MULTIPLE | MASK_STRING);
1592 case OPT_mno_powerpc:
1593 target_flags &= ~(MASK_POWERPC | MASK_PPC_GPOPT
1594 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1595 target_flags_explicit |= (MASK_POWERPC | MASK_PPC_GPOPT
1596 | MASK_PPC_GFXOPT | MASK_POWERPC64);
1599 target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1600 | MASK_NO_SUM_IN_TOC);
1601 target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
1602 | MASK_NO_SUM_IN_TOC);
1603 #ifdef TARGET_USES_SYSV4_OPT
1604 /* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
1605 just the same as -mminimal-toc. */
1606 target_flags |= MASK_MINIMAL_TOC;
1607 target_flags_explicit |= MASK_MINIMAL_TOC;
1611 #ifdef TARGET_USES_SYSV4_OPT
1613 /* Make -mtoc behave like -mminimal-toc. */
1614 target_flags |= MASK_MINIMAL_TOC;
1615 target_flags_explicit |= MASK_MINIMAL_TOC;
1619 #ifdef TARGET_USES_AIX64_OPT
1624 target_flags |= MASK_POWERPC64 | MASK_POWERPC | MASK_PPC_GFXOPT;
1625 target_flags_explicit |= MASK_POWERPC64 | MASK_POWERPC
1629 #ifdef TARGET_USES_AIX64_OPT
1634 target_flags &= ~MASK_POWERPC64;
1635 target_flags_explicit |= MASK_POWERPC64;
1638 case OPT_minsert_sched_nops_:
1639 rs6000_sched_insert_nops_str = arg;
1642 case OPT_mminimal_toc:
1645 target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1646 target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
1653 target_flags |= (MASK_MULTIPLE | MASK_STRING);
1654 target_flags_explicit |= (MASK_MULTIPLE | MASK_STRING);
1661 target_flags |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1662 target_flags_explicit |= (MASK_POWER | MASK_MULTIPLE | MASK_STRING);
1666 case OPT_mpowerpc_gpopt:
1667 case OPT_mpowerpc_gfxopt:
1670 target_flags |= MASK_POWERPC;
1671 target_flags_explicit |= MASK_POWERPC;
1675 case OPT_maix_struct_return:
1676 case OPT_msvr4_struct_return:
1677 rs6000_explicit_options.aix_struct_ret = true;
1681 rs6000_parse_yes_no_option ("vrsave", arg, &(TARGET_ALTIVEC_VRSAVE));
1685 rs6000_explicit_options.isel = true;
1686 rs6000_parse_yes_no_option ("isel", arg, &(rs6000_isel));
1690 rs6000_explicit_options.spe = true;
1691 rs6000_parse_yes_no_option ("spe", arg, &(rs6000_spe));
1692 /* No SPE means 64-bit long doubles, even if an E500. */
1694 rs6000_long_double_type_size = 64;
1698 rs6000_debug_name = arg;
1701 #ifdef TARGET_USES_SYSV4_OPT
1703 rs6000_abi_name = arg;
1707 rs6000_sdata_name = arg;
1710 case OPT_mtls_size_:
1711 rs6000_tls_size_string = arg;
1714 case OPT_mrelocatable:
1717 target_flags |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1718 target_flags_explicit |= MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC;
1722 case OPT_mrelocatable_lib:
1725 target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1726 | MASK_NO_FP_IN_TOC;
1727 target_flags_explicit |= MASK_RELOCATABLE | MASK_MINIMAL_TOC
1728 | MASK_NO_FP_IN_TOC;
1732 target_flags &= ~MASK_RELOCATABLE;
1733 target_flags_explicit |= MASK_RELOCATABLE;
1739 rs6000_explicit_options.abi = true;
1740 if (!strcmp (arg, "altivec"))
1742 rs6000_altivec_abi = 1;
1745 else if (! strcmp (arg, "no-altivec"))
1746 rs6000_altivec_abi = 0;
1747 else if (! strcmp (arg, "spe"))
1750 rs6000_altivec_abi = 0;
1751 if (!TARGET_SPE_ABI)
1752 error ("not configured for ABI: '%s'", arg);
1754 else if (! strcmp (arg, "no-spe"))
1757 /* These are here for testing during development only, do not
1758 document in the manual please. */
1759 else if (! strcmp (arg, "d64"))
1761 rs6000_darwin64_abi = 1;
1762 warning (0, "Using darwin64 ABI");
1764 else if (! strcmp (arg, "d32"))
1766 rs6000_darwin64_abi = 0;
1767 warning (0, "Using old darwin ABI");
1772 error ("unknown ABI specified: '%s'", arg);
1778 rs6000_select[1].string = arg;
1782 rs6000_select[2].string = arg;
1785 case OPT_mtraceback_:
1786 rs6000_traceback_name = arg;
1789 case OPT_mfloat_gprs_:
1790 rs6000_explicit_options.float_gprs = true;
1791 if (! strcmp (arg, "yes") || ! strcmp (arg, "single"))
1792 rs6000_float_gprs = 1;
1793 else if (! strcmp (arg, "double"))
1794 rs6000_float_gprs = 2;
1795 else if (! strcmp (arg, "no"))
1796 rs6000_float_gprs = 0;
1799 error ("invalid option for -mfloat-gprs: '%s'", arg);
1804 case OPT_mlong_double_:
1805 rs6000_explicit_options.long_double = true;
1806 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1807 if (value != 64 && value != 128)
1809 error ("Unknown switch -mlong-double-%s", arg);
1810 rs6000_long_double_type_size = RS6000_DEFAULT_LONG_DOUBLE_SIZE;
1814 rs6000_long_double_type_size = value;
1817 case OPT_msched_costly_dep_:
1818 rs6000_sched_costly_dep_str = arg;
1822 rs6000_explicit_options.alignment = true;
1823 if (! strcmp (arg, "power"))
1825 /* On 64-bit Darwin, power alignment is ABI-incompatible with
1826 some C library functions, so warn about it. The flag may be
1827 useful for performance studies from time to time though, so
1828 don't disable it entirely. */
1829 if (DEFAULT_ABI == ABI_DARWIN && TARGET_64BIT)
1830 warning (0, "-malign-power is not supported for 64-bit Darwin;"
1831 " it is incompatible with the installed C and C++ libraries");
1832 rs6000_alignment_flags = MASK_ALIGN_POWER;
1834 else if (! strcmp (arg, "natural"))
1835 rs6000_alignment_flags = MASK_ALIGN_NATURAL;
1838 error ("unknown -malign-XXXXX option specified: '%s'", arg);
1846 /* Do anything needed at the start of the asm file. */
1849 rs6000_file_start (void)
1853 const char *start = buffer;
1854 struct rs6000_cpu_select *ptr;
1855 const char *default_cpu = TARGET_CPU_DEFAULT;
1856 FILE *file = asm_out_file;
1858 default_file_start ();
1860 #ifdef TARGET_BI_ARCH
1861 if ((TARGET_DEFAULT ^ target_flags) & MASK_64BIT)
1865 if (flag_verbose_asm)
1867 sprintf (buffer, "\n%s rs6000/powerpc options:", ASM_COMMENT_START);
1868 rs6000_select[0].string = default_cpu;
1870 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
1872 ptr = &rs6000_select[i];
1873 if (ptr->string != (char *)0 && ptr->string[0] != '\0')
1875 fprintf (file, "%s %s%s", start, ptr->name, ptr->string);
1880 if (PPC405_ERRATUM77)
1882 fprintf (file, "%s PPC405CR_ERRATUM77", start);
1886 #ifdef USING_ELFOS_H
1887 switch (rs6000_sdata)
1889 case SDATA_NONE: fprintf (file, "%s -msdata=none", start); start = ""; break;
1890 case SDATA_DATA: fprintf (file, "%s -msdata=data", start); start = ""; break;
1891 case SDATA_SYSV: fprintf (file, "%s -msdata=sysv", start); start = ""; break;
1892 case SDATA_EABI: fprintf (file, "%s -msdata=eabi", start); start = ""; break;
1895 if (rs6000_sdata && g_switch_value)
1897 fprintf (file, "%s -G " HOST_WIDE_INT_PRINT_UNSIGNED, start,
1907 if (DEFAULT_ABI == ABI_AIX || (TARGET_ELF && flag_pic == 2))
1915 /* Return nonzero if this function is known to have a null epilogue. */
1918 direct_return (void)
1920 if (reload_completed)
1922 rs6000_stack_t *info = rs6000_stack_info ();
1924 if (info->first_gp_reg_save == 32
1925 && info->first_fp_reg_save == 64
1926 && info->first_altivec_reg_save == LAST_ALTIVEC_REGNO + 1
1927 && ! info->lr_save_p
1928 && ! info->cr_save_p
1929 && info->vrsave_mask == 0
1937 /* Return the number of instructions it takes to form a constant in an
1938 integer register. */
1941 num_insns_constant_wide (HOST_WIDE_INT value)
1943 /* signed constant loadable with {cal|addi} */
1944 if (CONST_OK_FOR_LETTER_P (value, 'I'))
1947 /* constant loadable with {cau|addis} */
1948 else if (CONST_OK_FOR_LETTER_P (value, 'L'))
1951 #if HOST_BITS_PER_WIDE_INT == 64
1952 else if (TARGET_POWERPC64)
1954 HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
1955 HOST_WIDE_INT high = value >> 31;
1957 if (high == 0 || high == -1)
1963 return num_insns_constant_wide (high) + 1;
1965 return (num_insns_constant_wide (high)
1966 + num_insns_constant_wide (low) + 1);
1975 num_insns_constant (rtx op, enum machine_mode mode)
1977 HOST_WIDE_INT low, high;
1979 switch (GET_CODE (op))
1982 #if HOST_BITS_PER_WIDE_INT == 64
1983 if ((INTVAL (op) >> 31) != 0 && (INTVAL (op) >> 31) != -1
1984 && mask_operand (op, mode))
1988 return num_insns_constant_wide (INTVAL (op));
1996 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
1997 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
1998 return num_insns_constant_wide ((HOST_WIDE_INT) l);
2001 if (mode == VOIDmode || mode == DImode)
2003 high = CONST_DOUBLE_HIGH (op);
2004 low = CONST_DOUBLE_LOW (op);
2011 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
2012 REAL_VALUE_TO_TARGET_DOUBLE (rv, l);
2013 high = l[WORDS_BIG_ENDIAN == 0];
2014 low = l[WORDS_BIG_ENDIAN != 0];
2018 return (num_insns_constant_wide (low)
2019 + num_insns_constant_wide (high));
2022 if ((high == 0 && low >= 0)
2023 || (high == -1 && low < 0))
2024 return num_insns_constant_wide (low);
2026 else if (mask_operand (op, mode))
2030 return num_insns_constant_wide (high) + 1;
2033 return (num_insns_constant_wide (high)
2034 + num_insns_constant_wide (low) + 1);
2042 /* Returns the constant for the splat instruction, if exists. */
2045 easy_vector_splat_const (int cst, enum machine_mode mode)
2050 if (EASY_VECTOR_15 (cst)
2051 || EASY_VECTOR_15_ADD_SELF (cst))
2053 if ((cst & 0xffff) != ((cst >> 16) & 0xffff))
2059 if (EASY_VECTOR_15 (cst)
2060 || EASY_VECTOR_15_ADD_SELF (cst))
2062 if ((cst & 0xff) != ((cst >> 8) & 0xff))
2068 if (EASY_VECTOR_15 (cst)
2069 || EASY_VECTOR_15_ADD_SELF (cst))
2077 /* Return nonzero if all elements of a vector have the same value. */
2080 easy_vector_same (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
2084 units = CONST_VECTOR_NUNITS (op);
2086 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
2087 for (i = 1; i < units; ++i)
2088 if (INTVAL (CONST_VECTOR_ELT (op, i)) != cst)
2090 if (i == units && easy_vector_splat_const (cst, mode))
2095 /* Generate easy_vector_constant out of a easy_vector_constant_add_self. */
2098 gen_easy_vector_constant_add_self (rtx op)
2102 units = GET_MODE_NUNITS (GET_MODE (op));
2103 v = rtvec_alloc (units);
2105 for (i = 0; i < units; i++)
2107 GEN_INT (INTVAL (CONST_VECTOR_ELT (op, i)) >> 1);
2108 return gen_rtx_raw_CONST_VECTOR (GET_MODE (op), v);
2112 output_vec_const_move (rtx *operands)
2115 enum machine_mode mode;
2121 cst = INTVAL (CONST_VECTOR_ELT (vec, 0));
2122 cst2 = INTVAL (CONST_VECTOR_ELT (vec, 1));
2123 mode = GET_MODE (dest);
2127 if (zero_constant (vec, mode))
2128 return "vxor %0,%0,%0";
2130 gcc_assert (easy_vector_constant (vec, mode));
2132 operands[1] = GEN_INT (cst);
2136 if (EASY_VECTOR_15 (cst))
2138 operands[1] = GEN_INT (cst);
2139 return "vspltisw %0,%1";
2141 else if (EASY_VECTOR_15_ADD_SELF (cst))
2147 if (EASY_VECTOR_15 (cst))
2149 operands[1] = GEN_INT (cst);
2150 return "vspltish %0,%1";
2152 else if (EASY_VECTOR_15_ADD_SELF (cst))
2158 if (EASY_VECTOR_15 (cst))
2160 operands[1] = GEN_INT (cst);
2161 return "vspltisb %0,%1";
2163 else if (EASY_VECTOR_15_ADD_SELF (cst))
2171 gcc_assert (TARGET_SPE);
2173 /* Vector constant 0 is handled as a splitter of V2SI, and in the
2174 pattern of V1DI, V4HI, and V2SF.
2176 FIXME: We should probably return # and add post reload
2177 splitters for these, but this way is so easy ;-). */
2178 operands[1] = GEN_INT (cst);
2179 operands[2] = GEN_INT (cst2);
2181 return "li %0,%1\n\tevmergelo %0,%0,%0";
2183 return "li %0,%1\n\tevmergelo %0,%0,%0\n\tli %0,%2";
2186 /* Initialize vector TARGET to VALS. */
2189 rs6000_expand_vector_init (rtx target, rtx vals)
2191 enum machine_mode mode = GET_MODE (target);
2192 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2193 int n_elts = GET_MODE_NUNITS (mode);
2194 int n_var = 0, one_var = -1;
2195 bool all_same = true, all_const_zero = true;
2199 for (i = 0; i < n_elts; ++i)
2201 x = XVECEXP (vals, 0, i);
2202 if (!CONSTANT_P (x))
2203 ++n_var, one_var = i;
2204 else if (x != CONST0_RTX (inner_mode))
2205 all_const_zero = false;
2207 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0)))
2213 if (mode != V4SFmode && all_const_zero)
2215 /* Zero register. */
2216 emit_insn (gen_rtx_SET (VOIDmode, target,
2217 gen_rtx_XOR (mode, target, target)));
2220 else if (mode != V4SFmode && easy_vector_same (vals, mode))
2222 /* Splat immediate. */
2223 x = gen_rtx_VEC_DUPLICATE (mode, CONST_VECTOR_ELT (vals, 0));
2224 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2228 ; /* Splat vector element. */
2231 /* Load from constant pool. */
2232 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0)));
2237 /* Store value to stack temp. Load vector element. Splat. */
2240 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2241 emit_move_insn (adjust_address_nv (mem, inner_mode, 0),
2242 XVECEXP (vals, 0, 0));
2243 x = gen_rtx_UNSPEC (VOIDmode,
2244 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2245 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2247 gen_rtx_SET (VOIDmode,
2250 x = gen_rtx_VEC_SELECT (inner_mode, target,
2251 gen_rtx_PARALLEL (VOIDmode,
2252 gen_rtvec (1, const0_rtx)));
2253 emit_insn (gen_rtx_SET (VOIDmode, target,
2254 gen_rtx_VEC_DUPLICATE (mode, x)));
2258 /* One field is non-constant. Load constant then overwrite
2262 rtx copy = copy_rtx (vals);
2264 /* Load constant part of vector, substititute neighboring value for
2266 XVECEXP (copy, 0, one_var) = XVECEXP (vals, 0, (one_var + 1) % n_elts);
2267 rs6000_expand_vector_init (target, copy);
2269 /* Insert variable. */
2270 rs6000_expand_vector_set (target, XVECEXP (vals, 0, one_var), one_var);
2274 /* Construct the vector in memory one field at a time
2275 and load the whole vector. */
2276 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2277 for (i = 0; i < n_elts; i++)
2278 emit_move_insn (adjust_address_nv (mem, inner_mode,
2279 i * GET_MODE_SIZE (inner_mode)),
2280 XVECEXP (vals, 0, i));
2281 emit_move_insn (target, mem);
2284 /* Set field ELT of TARGET to VAL. */
2287 rs6000_expand_vector_set (rtx target, rtx val, int elt)
2289 enum machine_mode mode = GET_MODE (target);
2290 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2291 rtx reg = gen_reg_rtx (mode);
2293 int width = GET_MODE_SIZE (inner_mode);
2296 /* Load single variable value. */
2297 mem = assign_stack_temp (mode, GET_MODE_SIZE (inner_mode), 0);
2298 emit_move_insn (adjust_address_nv (mem, inner_mode, 0), val);
2299 x = gen_rtx_UNSPEC (VOIDmode,
2300 gen_rtvec (1, const0_rtx), UNSPEC_LVE);
2301 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2303 gen_rtx_SET (VOIDmode,
2307 /* Linear sequence. */
2308 mask = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
2309 for (i = 0; i < 16; ++i)
2310 XVECEXP (mask, 0, i) = GEN_INT (i);
2312 /* Set permute mask to insert element into target. */
2313 for (i = 0; i < width; ++i)
2314 XVECEXP (mask, 0, elt*width + i)
2315 = GEN_INT (i + 0x10);
2316 x = gen_rtx_CONST_VECTOR (V16QImode, XVEC (mask, 0));
2317 x = gen_rtx_UNSPEC (mode,
2318 gen_rtvec (3, target, reg,
2319 force_reg (V16QImode, x)),
2321 emit_insn (gen_rtx_SET (VOIDmode, target, x));
2324 /* Extract field ELT from VEC into TARGET. */
2327 rs6000_expand_vector_extract (rtx target, rtx vec, int elt)
2329 enum machine_mode mode = GET_MODE (vec);
2330 enum machine_mode inner_mode = GET_MODE_INNER (mode);
2333 /* Allocate mode-sized buffer. */
2334 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode), 0);
2336 /* Add offset to field within buffer matching vector element. */
2337 mem = adjust_address_nv (mem, mode, elt * GET_MODE_SIZE (inner_mode));
2339 /* Store single field into mode-sized buffer. */
2340 x = gen_rtx_UNSPEC (VOIDmode,
2341 gen_rtvec (1, const0_rtx), UNSPEC_STVE);
2342 emit_insn (gen_rtx_PARALLEL (VOIDmode,
2344 gen_rtx_SET (VOIDmode,
2347 emit_move_insn (target, adjust_address_nv (mem, inner_mode, 0));
2351 mask64_1or2_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED,
2354 if (GET_CODE (op) == CONST_INT)
2356 HOST_WIDE_INT c, lsb;
2361 /* Disallow all zeros. */
2365 /* We can use a single rlwinm insn if no upper bits of C are set
2366 AND there are zero, one or two transitions in the _whole_ of
2368 one_ok = !(c & ~(HOST_WIDE_INT)0xffffffff);
2370 /* We don't change the number of transitions by inverting,
2371 so make sure we start with the LS bit zero. */
2375 /* Find the first transition. */
2378 /* Invert to look for a second transition. */
2381 /* Erase first transition. */
2384 /* Find the second transition. */
2387 /* Invert to look for a third transition. */
2390 /* Erase second transition. */
2393 if (one_ok && !(allow_one || c))
2396 /* Find the third transition (if any). */
2399 /* Match if all the bits above are 1's (or c is zero). */
2405 /* Generates shifts and masks for a pair of rldicl or rldicr insns to
2406 implement ANDing by the mask IN. */
2408 build_mask64_2_operands (rtx in, rtx *out)
2410 #if HOST_BITS_PER_WIDE_INT >= 64
2411 unsigned HOST_WIDE_INT c, lsb, m1, m2;
2414 gcc_assert (GET_CODE (in) == CONST_INT);
2419 /* Assume c initially something like 0x00fff000000fffff. The idea
2420 is to rotate the word so that the middle ^^^^^^ group of zeros
2421 is at the MS end and can be cleared with an rldicl mask. We then
2422 rotate back and clear off the MS ^^ group of zeros with a
2424 c = ~c; /* c == 0xff000ffffff00000 */
2425 lsb = c & -c; /* lsb == 0x0000000000100000 */
2426 m1 = -lsb; /* m1 == 0xfffffffffff00000 */
2427 c = ~c; /* c == 0x00fff000000fffff */
2428 c &= -lsb; /* c == 0x00fff00000000000 */
2429 lsb = c & -c; /* lsb == 0x0000100000000000 */
2430 c = ~c; /* c == 0xff000fffffffffff */
2431 c &= -lsb; /* c == 0xff00000000000000 */
2433 while ((lsb >>= 1) != 0)
2434 shift++; /* shift == 44 on exit from loop */
2435 m1 <<= 64 - shift; /* m1 == 0xffffff0000000000 */
2436 m1 = ~m1; /* m1 == 0x000000ffffffffff */
2437 m2 = ~c; /* m2 == 0x00ffffffffffffff */
2441 /* Assume c initially something like 0xff000f0000000000. The idea
2442 is to rotate the word so that the ^^^ middle group of zeros
2443 is at the LS end and can be cleared with an rldicr mask. We then
2444 rotate back and clear off the LS group of ^^^^^^^^^^ zeros with
2446 lsb = c & -c; /* lsb == 0x0000010000000000 */
2447 m2 = -lsb; /* m2 == 0xffffff0000000000 */
2448 c = ~c; /* c == 0x00fff0ffffffffff */
2449 c &= -lsb; /* c == 0x00fff00000000000 */
2450 lsb = c & -c; /* lsb == 0x0000100000000000 */
2451 c = ~c; /* c == 0xff000fffffffffff */
2452 c &= -lsb; /* c == 0xff00000000000000 */
2454 while ((lsb >>= 1) != 0)
2455 shift++; /* shift == 44 on exit from loop */
2456 m1 = ~c; /* m1 == 0x00ffffffffffffff */
2457 m1 >>= shift; /* m1 == 0x0000000000000fff */
2458 m1 = ~m1; /* m1 == 0xfffffffffffff000 */
2461 /* Note that when we only have two 0->1 and 1->0 transitions, one of the
2462 masks will be all 1's. We are guaranteed more than one transition. */
2463 out[0] = GEN_INT (64 - shift);
2464 out[1] = GEN_INT (m1);
2465 out[2] = GEN_INT (shift);
2466 out[3] = GEN_INT (m2);
2474 /* Return TRUE if OP is an invalid SUBREG operation on the e500. */
2477 invalid_e500_subreg (rtx op, enum machine_mode mode)
2479 /* Reject (subreg:SI (reg:DF)). */
2480 if (GET_CODE (op) == SUBREG
2482 && REG_P (SUBREG_REG (op))
2483 && GET_MODE (SUBREG_REG (op)) == DFmode)
2486 /* Reject (subreg:DF (reg:DI)). */
2487 if (GET_CODE (op) == SUBREG
2489 && REG_P (SUBREG_REG (op))
2490 && GET_MODE (SUBREG_REG (op)) == DImode)
2496 /* Darwin, AIX increases natural record alignment to doubleword if the first
2497 field is an FP double while the FP fields remain word aligned. */
2500 rs6000_special_round_type_align (tree type, int computed, int specified)
2502 tree field = TYPE_FIELDS (type);
2504 /* Skip all non field decls */
2505 while (field != NULL && TREE_CODE (field) != FIELD_DECL)
2506 field = TREE_CHAIN (field);
2508 if (field == NULL || field == type || DECL_MODE (field) != DFmode)
2509 return MAX (computed, specified);
2511 return MAX (MAX (computed, specified), 64);
2514 /* Return 1 for an operand in small memory on V.4/eabi. */
2517 small_data_operand (rtx op ATTRIBUTE_UNUSED,
2518 enum machine_mode mode ATTRIBUTE_UNUSED)
2523 if (rs6000_sdata == SDATA_NONE || rs6000_sdata == SDATA_DATA)
2526 if (DEFAULT_ABI != ABI_V4)
2529 if (GET_CODE (op) == SYMBOL_REF)
2532 else if (GET_CODE (op) != CONST
2533 || GET_CODE (XEXP (op, 0)) != PLUS
2534 || GET_CODE (XEXP (XEXP (op, 0), 0)) != SYMBOL_REF
2535 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT)
2540 rtx sum = XEXP (op, 0);
2541 HOST_WIDE_INT summand;
2543 /* We have to be careful here, because it is the referenced address
2544 that must be 32k from _SDA_BASE_, not just the symbol. */
2545 summand = INTVAL (XEXP (sum, 1));
2546 if (summand < 0 || (unsigned HOST_WIDE_INT) summand > g_switch_value)
2549 sym_ref = XEXP (sum, 0);
2552 return SYMBOL_REF_SMALL_P (sym_ref);
2558 /* Return true if either operand is a general purpose register. */
2561 gpr_or_gpr_p (rtx op0, rtx op1)
2563 return ((REG_P (op0) && INT_REGNO_P (REGNO (op0)))
2564 || (REG_P (op1) && INT_REGNO_P (REGNO (op1))));
2568 /* Subroutines of rs6000_legitimize_address and rs6000_legitimate_address. */
2571 constant_pool_expr_1 (rtx op, int *have_sym, int *have_toc)
2573 switch (GET_CODE (op))
2576 if (RS6000_SYMBOL_REF_TLS_P (op))
2578 else if (CONSTANT_POOL_ADDRESS_P (op))
2580 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (op), Pmode))
2588 else if (! strcmp (XSTR (op, 0), toc_label_name))
2597 return (constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc)
2598 && constant_pool_expr_1 (XEXP (op, 1), have_sym, have_toc));
2600 return constant_pool_expr_1 (XEXP (op, 0), have_sym, have_toc);
2609 constant_pool_expr_p (rtx op)
2613 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_sym;
2617 toc_relative_expr_p (rtx op)
2621 return constant_pool_expr_1 (op, &have_sym, &have_toc) && have_toc;
2625 legitimate_constant_pool_address_p (rtx x)
2628 && GET_CODE (x) == PLUS
2629 && GET_CODE (XEXP (x, 0)) == REG
2630 && (TARGET_MINIMAL_TOC || REGNO (XEXP (x, 0)) == TOC_REGISTER)
2631 && constant_pool_expr_p (XEXP (x, 1)));
2635 legitimate_small_data_p (enum machine_mode mode, rtx x)
2637 return (DEFAULT_ABI == ABI_V4
2638 && !flag_pic && !TARGET_TOC
2639 && (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST)
2640 && small_data_operand (x, mode));
2643 /* SPE offset addressing is limited to 5-bits worth of double words. */
2644 #define SPE_CONST_OFFSET_OK(x) (((x) & ~0xf8) == 0)
2647 rs6000_legitimate_offset_address_p (enum machine_mode mode, rtx x, int strict)
2649 unsigned HOST_WIDE_INT offset, extra;
2651 if (GET_CODE (x) != PLUS)
2653 if (GET_CODE (XEXP (x, 0)) != REG)
2655 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2657 if (legitimate_constant_pool_address_p (x))
2659 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
2662 offset = INTVAL (XEXP (x, 1));
2670 /* AltiVec vector modes. Only reg+reg addressing is valid and
2671 constant offset zero should not occur due to canonicalization.
2672 Allow any offset when not strict before reload. */
2679 /* SPE vector modes. */
2680 return SPE_CONST_OFFSET_OK (offset);
2683 if (TARGET_E500_DOUBLE)
2684 return SPE_CONST_OFFSET_OK (offset);
2687 /* On e500v2, we may have:
2689 (subreg:DF (mem:DI (plus (reg) (const_int))) 0).
2691 Which gets addressed with evldd instructions. */
2692 if (TARGET_E500_DOUBLE)
2693 return SPE_CONST_OFFSET_OK (offset);
2695 if (mode == DFmode || !TARGET_POWERPC64)
2697 else if (offset & 3)
2703 if (mode == TFmode || !TARGET_POWERPC64)
2705 else if (offset & 3)
2716 return (offset < 0x10000) && (offset + extra < 0x10000);
2720 legitimate_indexed_address_p (rtx x, int strict)
2724 if (GET_CODE (x) != PLUS)
2730 if (!REG_P (op0) || !REG_P (op1))
2733 return ((INT_REG_OK_FOR_BASE_P (op0, strict)
2734 && INT_REG_OK_FOR_INDEX_P (op1, strict))
2735 || (INT_REG_OK_FOR_BASE_P (op1, strict)
2736 && INT_REG_OK_FOR_INDEX_P (op0, strict)));
2740 legitimate_indirect_address_p (rtx x, int strict)
2742 return GET_CODE (x) == REG && INT_REG_OK_FOR_BASE_P (x, strict);
2746 macho_lo_sum_memory_operand (rtx x, enum machine_mode mode)
2748 if (!TARGET_MACHO || !flag_pic
2749 || mode != SImode || GET_CODE (x) != MEM)
2753 if (GET_CODE (x) != LO_SUM)
2755 if (GET_CODE (XEXP (x, 0)) != REG)
2757 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), 0))
2761 return CONSTANT_P (x);
2765 legitimate_lo_sum_address_p (enum machine_mode mode, rtx x, int strict)
2767 if (GET_CODE (x) != LO_SUM)
2769 if (GET_CODE (XEXP (x, 0)) != REG)
2771 if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
2773 /* Restrict addressing for DI because of our SUBREG hackery. */
2774 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
2778 if (TARGET_ELF || TARGET_MACHO)
2780 if (DEFAULT_ABI != ABI_AIX && DEFAULT_ABI != ABI_DARWIN && flag_pic)
2784 if (GET_MODE_NUNITS (mode) != 1)
2786 if (GET_MODE_BITSIZE (mode) > 64
2787 || (GET_MODE_BITSIZE (mode) > 32 && !TARGET_POWERPC64
2788 && !(TARGET_HARD_FLOAT && TARGET_FPRS && mode == DFmode)))
2791 return CONSTANT_P (x);
2798 /* Try machine-dependent ways of modifying an illegitimate address
2799 to be legitimate. If we find one, return the new, valid address.
2800 This is used from only one place: `memory_address' in explow.c.
2802 OLDX is the address as it was before break_out_memory_refs was
2803 called. In some cases it is useful to look at this to decide what
2806 MODE is passed so that this function can use GO_IF_LEGITIMATE_ADDRESS.
2808 It is always safe for this function to do nothing. It exists to
2809 recognize opportunities to optimize the output.
2811 On RS/6000, first check for the sum of a register with a constant
2812 integer that is out of range. If so, generate code to add the
2813 constant with the low-order 16 bits masked to the register and force
2814 this result into another register (this can be done with `cau').
2815 Then generate an address of REG+(CONST&0xffff), allowing for the
2816 possibility of bit 16 being a one.
2818 Then check for the sum of a register and something not constant, try to
2819 load the other things into a register and return the sum. */
2822 rs6000_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
2823 enum machine_mode mode)
2825 if (GET_CODE (x) == SYMBOL_REF)
2827 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
2829 return rs6000_legitimize_tls_address (x, model);
2832 if (GET_CODE (x) == PLUS
2833 && GET_CODE (XEXP (x, 0)) == REG
2834 && GET_CODE (XEXP (x, 1)) == CONST_INT
2835 && (unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 1)) + 0x8000) >= 0x10000)
2837 HOST_WIDE_INT high_int, low_int;
2839 low_int = ((INTVAL (XEXP (x, 1)) & 0xffff) ^ 0x8000) - 0x8000;
2840 high_int = INTVAL (XEXP (x, 1)) - low_int;
2841 sum = force_operand (gen_rtx_PLUS (Pmode, XEXP (x, 0),
2842 GEN_INT (high_int)), 0);
2843 return gen_rtx_PLUS (Pmode, sum, GEN_INT (low_int));
2845 else if (GET_CODE (x) == PLUS
2846 && GET_CODE (XEXP (x, 0)) == REG
2847 && GET_CODE (XEXP (x, 1)) != CONST_INT
2848 && GET_MODE_NUNITS (mode) == 1
2849 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
2851 || (((mode != DImode && mode != DFmode) || TARGET_E500_DOUBLE)
2853 && (TARGET_POWERPC64 || mode != DImode)
2856 return gen_rtx_PLUS (Pmode, XEXP (x, 0),
2857 force_reg (Pmode, force_operand (XEXP (x, 1), 0)));
2859 else if (ALTIVEC_VECTOR_MODE (mode))
2863 /* Make sure both operands are registers. */
2864 if (GET_CODE (x) == PLUS)
2865 return gen_rtx_PLUS (Pmode, force_reg (Pmode, XEXP (x, 0)),
2866 force_reg (Pmode, XEXP (x, 1)));
2868 reg = force_reg (Pmode, x);
2871 else if (SPE_VECTOR_MODE (mode)
2872 || (TARGET_E500_DOUBLE && (mode == DFmode
2873 || mode == DImode)))
2877 /* We accept [reg + reg] and [reg + OFFSET]. */
2879 if (GET_CODE (x) == PLUS)
2881 rtx op1 = XEXP (x, 0);
2882 rtx op2 = XEXP (x, 1);
2884 op1 = force_reg (Pmode, op1);
2886 if (GET_CODE (op2) != REG
2887 && (GET_CODE (op2) != CONST_INT
2888 || !SPE_CONST_OFFSET_OK (INTVAL (op2))))
2889 op2 = force_reg (Pmode, op2);
2891 return gen_rtx_PLUS (Pmode, op1, op2);
2894 return force_reg (Pmode, x);
2900 && GET_CODE (x) != CONST_INT
2901 && GET_CODE (x) != CONST_DOUBLE
2903 && GET_MODE_NUNITS (mode) == 1
2904 && (GET_MODE_BITSIZE (mode) <= 32
2905 || ((TARGET_HARD_FLOAT && TARGET_FPRS) && mode == DFmode)))
2907 rtx reg = gen_reg_rtx (Pmode);
2908 emit_insn (gen_elf_high (reg, x));
2909 return gen_rtx_LO_SUM (Pmode, reg, x);
2911 else if (TARGET_MACHO && TARGET_32BIT && TARGET_NO_TOC
2914 && ! MACHO_DYNAMIC_NO_PIC_P
2916 && GET_CODE (x) != CONST_INT
2917 && GET_CODE (x) != CONST_DOUBLE
2919 && ((TARGET_HARD_FLOAT && TARGET_FPRS) || mode != DFmode)
2923 rtx reg = gen_reg_rtx (Pmode);
2924 emit_insn (gen_macho_high (reg, x));
2925 return gen_rtx_LO_SUM (Pmode, reg, x);
2928 && constant_pool_expr_p (x)
2929 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), Pmode))
2931 return create_TOC_reference (x);
2937 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL.
2938 We need to emit DTP-relative relocations. */
2941 rs6000_output_dwarf_dtprel (FILE *file, int size, rtx x)
2946 fputs ("\t.long\t", file);
2949 fputs (DOUBLE_INT_ASM_OP, file);
2954 output_addr_const (file, x);
2955 fputs ("@dtprel+0x8000", file);
2958 /* Construct the SYMBOL_REF for the tls_get_addr function. */
2960 static GTY(()) rtx rs6000_tls_symbol;
2962 rs6000_tls_get_addr (void)
2964 if (!rs6000_tls_symbol)
2965 rs6000_tls_symbol = init_one_libfunc ("__tls_get_addr");
2967 return rs6000_tls_symbol;
2970 /* Construct the SYMBOL_REF for TLS GOT references. */
2972 static GTY(()) rtx rs6000_got_symbol;
2974 rs6000_got_sym (void)
2976 if (!rs6000_got_symbol)
2978 rs6000_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
2979 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_LOCAL;
2980 SYMBOL_REF_FLAGS (rs6000_got_symbol) |= SYMBOL_FLAG_EXTERNAL;
2983 return rs6000_got_symbol;
2986 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute
2987 this (thread-local) address. */
2990 rs6000_legitimize_tls_address (rtx addr, enum tls_model model)
2994 dest = gen_reg_rtx (Pmode);
2995 if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 16)
3001 tlsreg = gen_rtx_REG (Pmode, 13);
3002 insn = gen_tls_tprel_64 (dest, tlsreg, addr);
3006 tlsreg = gen_rtx_REG (Pmode, 2);
3007 insn = gen_tls_tprel_32 (dest, tlsreg, addr);
3011 else if (model == TLS_MODEL_LOCAL_EXEC && rs6000_tls_size == 32)
3015 tmp = gen_reg_rtx (Pmode);
3018 tlsreg = gen_rtx_REG (Pmode, 13);
3019 insn = gen_tls_tprel_ha_64 (tmp, tlsreg, addr);
3023 tlsreg = gen_rtx_REG (Pmode, 2);
3024 insn = gen_tls_tprel_ha_32 (tmp, tlsreg, addr);
3028 insn = gen_tls_tprel_lo_64 (dest, tmp, addr);
3030 insn = gen_tls_tprel_lo_32 (dest, tmp, addr);
3035 rtx r3, got, tga, tmp1, tmp2, eqv;
3038 got = gen_rtx_REG (Pmode, TOC_REGISTER);
3042 got = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
3045 rtx gsym = rs6000_got_sym ();
3046 got = gen_reg_rtx (Pmode);
3048 rs6000_emit_move (got, gsym, Pmode);
3051 rtx tempLR, tmp3, mem;
3054 tempLR = gen_reg_rtx (Pmode);
3055 tmp1 = gen_reg_rtx (Pmode);
3056 tmp2 = gen_reg_rtx (Pmode);
3057 tmp3 = gen_reg_rtx (Pmode);
3058 mem = gen_const_mem (Pmode, tmp1);
3060 first = emit_insn (gen_load_toc_v4_PIC_1b (tempLR, gsym));
3061 emit_move_insn (tmp1, tempLR);
3062 emit_move_insn (tmp2, mem);
3063 emit_insn (gen_addsi3 (tmp3, tmp1, tmp2));
3064 last = emit_move_insn (got, tmp3);
3065 REG_NOTES (last) = gen_rtx_EXPR_LIST (REG_EQUAL, gsym,
3067 REG_NOTES (first) = gen_rtx_INSN_LIST (REG_LIBCALL, last,
3069 REG_NOTES (last) = gen_rtx_INSN_LIST (REG_RETVAL, first,
3075 if (model == TLS_MODEL_GLOBAL_DYNAMIC)
3077 r3 = gen_rtx_REG (Pmode, 3);
3079 insn = gen_tls_gd_64 (r3, got, addr);
3081 insn = gen_tls_gd_32 (r3, got, addr);
3084 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3085 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3086 insn = emit_call_insn (insn);
3087 CONST_OR_PURE_CALL_P (insn) = 1;
3088 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3089 insn = get_insns ();
3091 emit_libcall_block (insn, dest, r3, addr);
3093 else if (model == TLS_MODEL_LOCAL_DYNAMIC)
3095 r3 = gen_rtx_REG (Pmode, 3);
3097 insn = gen_tls_ld_64 (r3, got);
3099 insn = gen_tls_ld_32 (r3, got);
3102 tga = gen_rtx_MEM (Pmode, rs6000_tls_get_addr ());
3103 insn = gen_call_value (r3, tga, const0_rtx, const0_rtx);
3104 insn = emit_call_insn (insn);
3105 CONST_OR_PURE_CALL_P (insn) = 1;
3106 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), r3);
3107 insn = get_insns ();
3109 tmp1 = gen_reg_rtx (Pmode);
3110 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
3112 emit_libcall_block (insn, tmp1, r3, eqv);
3113 if (rs6000_tls_size == 16)
3116 insn = gen_tls_dtprel_64 (dest, tmp1, addr);
3118 insn = gen_tls_dtprel_32 (dest, tmp1, addr);
3120 else if (rs6000_tls_size == 32)
3122 tmp2 = gen_reg_rtx (Pmode);
3124 insn = gen_tls_dtprel_ha_64 (tmp2, tmp1, addr);
3126 insn = gen_tls_dtprel_ha_32 (tmp2, tmp1, addr);
3129 insn = gen_tls_dtprel_lo_64 (dest, tmp2, addr);
3131 insn = gen_tls_dtprel_lo_32 (dest, tmp2, addr);
3135 tmp2 = gen_reg_rtx (Pmode);
3137 insn = gen_tls_got_dtprel_64 (tmp2, got, addr);
3139 insn = gen_tls_got_dtprel_32 (tmp2, got, addr);
3141 insn = gen_rtx_SET (Pmode, dest,
3142 gen_rtx_PLUS (Pmode, tmp2, tmp1));
3148 /* IE, or 64 bit offset LE. */
3149 tmp2 = gen_reg_rtx (Pmode);
3151 insn = gen_tls_got_tprel_64 (tmp2, got, addr);
3153 insn = gen_tls_got_tprel_32 (tmp2, got, addr);
3156 insn = gen_tls_tls_64 (dest, tmp2, addr);
3158 insn = gen_tls_tls_32 (dest, tmp2, addr);
3166 /* Return 1 if X contains a thread-local symbol. */
3169 rs6000_tls_referenced_p (rtx x)
3171 if (! TARGET_HAVE_TLS)
3174 return for_each_rtx (&x, &rs6000_tls_symbol_ref_1, 0);
3177 /* Return 1 if *X is a thread-local symbol. This is the same as
3178 rs6000_tls_symbol_ref except for the type of the unused argument. */
3181 rs6000_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
3183 return RS6000_SYMBOL_REF_TLS_P (*x);
3186 /* The convention appears to be to define this wherever it is used.
3187 With legitimize_reload_address now defined here, REG_MODE_OK_FOR_BASE_P
3188 is now used here. */
3189 #ifndef REG_MODE_OK_FOR_BASE_P
3190 #define REG_MODE_OK_FOR_BASE_P(REGNO, MODE) REG_OK_FOR_BASE_P (REGNO)
3193 /* Our implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to
3194 replace the input X, or the original X if no replacement is called for.
3195 The output parameter *WIN is 1 if the calling macro should goto WIN,
3198 For RS/6000, we wish to handle large displacements off a base
3199 register by splitting the addend across an addiu/addis and the mem insn.
3200 This cuts number of extra insns needed from 3 to 1.
3202 On Darwin, we use this to generate code for floating point constants.
3203 A movsf_low is generated so we wind up with 2 instructions rather than 3.
3204 The Darwin code is inside #if TARGET_MACHO because only then is
3205 machopic_function_base_name() defined. */
3207 rs6000_legitimize_reload_address (rtx x, enum machine_mode mode,
3208 int opnum, int type,
3209 int ind_levels ATTRIBUTE_UNUSED, int *win)
3211 /* We must recognize output that we have already generated ourselves. */
3212 if (GET_CODE (x) == PLUS
3213 && GET_CODE (XEXP (x, 0)) == PLUS
3214 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3215 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3216 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3218 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3219 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3220 opnum, (enum reload_type)type);
3226 if (DEFAULT_ABI == ABI_DARWIN && flag_pic
3227 && GET_CODE (x) == LO_SUM
3228 && GET_CODE (XEXP (x, 0)) == PLUS
3229 && XEXP (XEXP (x, 0), 0) == pic_offset_table_rtx
3230 && GET_CODE (XEXP (XEXP (x, 0), 1)) == HIGH
3231 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 1), 0)) == CONST
3232 && XEXP (XEXP (XEXP (x, 0), 1), 0) == XEXP (x, 1)
3233 && GET_CODE (XEXP (XEXP (x, 1), 0)) == MINUS
3234 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 0)) == SYMBOL_REF
3235 && GET_CODE (XEXP (XEXP (XEXP (x, 1), 0), 1)) == SYMBOL_REF)
3237 /* Result of previous invocation of this function on Darwin
3238 floating point constant. */
3239 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3240 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3241 opnum, (enum reload_type)type);
3247 /* Force ld/std non-word aligned offset into base register by wrapping
3249 if (GET_CODE (x) == PLUS
3250 && GET_CODE (XEXP (x, 0)) == REG
3251 && REGNO (XEXP (x, 0)) < 32
3252 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3253 && GET_CODE (XEXP (x, 1)) == CONST_INT
3254 && (INTVAL (XEXP (x, 1)) & 3) != 0
3255 && !ALTIVEC_VECTOR_MODE (mode)
3256 && GET_MODE_SIZE (mode) >= UNITS_PER_WORD
3257 && TARGET_POWERPC64)
3259 x = gen_rtx_PLUS (GET_MODE (x), x, GEN_INT (0));
3260 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3261 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3262 opnum, (enum reload_type) type);
3267 if (GET_CODE (x) == PLUS
3268 && GET_CODE (XEXP (x, 0)) == REG
3269 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
3270 && REG_MODE_OK_FOR_BASE_P (XEXP (x, 0), mode)
3271 && GET_CODE (XEXP (x, 1)) == CONST_INT
3272 && !SPE_VECTOR_MODE (mode)
3273 && !(TARGET_E500_DOUBLE && (mode == DFmode
3275 && !ALTIVEC_VECTOR_MODE (mode))
3277 HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
3278 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000;
3280 = (((val - low) & 0xffffffff) ^ 0x80000000) - 0x80000000;
3282 /* Check for 32-bit overflow. */
3283 if (high + low != val)
3289 /* Reload the high part into a base reg; leave the low part
3290 in the mem directly. */
3292 x = gen_rtx_PLUS (GET_MODE (x),
3293 gen_rtx_PLUS (GET_MODE (x), XEXP (x, 0),
3297 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3298 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0,
3299 opnum, (enum reload_type)type);
3305 if (GET_CODE (x) == SYMBOL_REF
3306 && DEFAULT_ABI == ABI_DARWIN
3307 && !ALTIVEC_VECTOR_MODE (mode)
3308 && (flag_pic || MACHO_DYNAMIC_NO_PIC_P)
3309 /* Don't do this for TFmode, since the result isn't offsettable.
3310 The same goes for DImode without 64-bit gprs. */
3312 && (mode != DImode || TARGET_POWERPC64))
3316 rtx offset = gen_rtx_CONST (Pmode,
3317 gen_rtx_MINUS (Pmode, x,
3318 machopic_function_base_sym ()));
3319 x = gen_rtx_LO_SUM (GET_MODE (x),
3320 gen_rtx_PLUS (Pmode, pic_offset_table_rtx,
3321 gen_rtx_HIGH (Pmode, offset)), offset);
3324 x = gen_rtx_LO_SUM (GET_MODE (x),
3325 gen_rtx_HIGH (Pmode, x), x);
3327 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL,
3328 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0,
3329 opnum, (enum reload_type)type);
3335 /* Reload an offset address wrapped by an AND that represents the
3336 masking of the lower bits. Strip the outer AND and let reload
3337 convert the offset address into an indirect address. */
3339 && ALTIVEC_VECTOR_MODE (mode)
3340 && GET_CODE (x) == AND
3341 && GET_CODE (XEXP (x, 0)) == PLUS
3342 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
3343 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3344 && GET_CODE (XEXP (x, 1)) == CONST_INT
3345 && INTVAL (XEXP (x, 1)) == -16)
3353 && constant_pool_expr_p (x)
3354 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (x), mode))
3356 (x) = create_TOC_reference (x);
3364 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
3365 that is a valid memory address for an instruction.
3366 The MODE argument is the machine mode for the MEM expression
3367 that wants to use this address.
3369 On the RS/6000, there are four valid address: a SYMBOL_REF that
3370 refers to a constant pool entry of an address (or the sum of it
3371 plus a constant), a short (16-bit signed) constant plus a register,
3372 the sum of two registers, or a register indirect, possibly with an
3373 auto-increment. For DFmode and DImode with a constant plus register,
3374 we must ensure that both words are addressable or PowerPC64 with offset
3377 For modes spanning multiple registers (DFmode in 32-bit GPRs,
3378 32-bit DImode, TImode, TFmode), indexed addressing cannot be used because
3379 adjacent memory cells are accessed by adding word-sized offsets
3380 during assembly output. */
3382 rs6000_legitimate_address (enum machine_mode mode, rtx x, int reg_ok_strict)
3384 /* If this is an unaligned stvx/ldvx type address, discard the outer AND. */
3386 && ALTIVEC_VECTOR_MODE (mode)
3387 && GET_CODE (x) == AND
3388 && GET_CODE (XEXP (x, 1)) == CONST_INT
3389 && INTVAL (XEXP (x, 1)) == -16)
3392 if (RS6000_SYMBOL_REF_TLS_P (x))
3394 if (legitimate_indirect_address_p (x, reg_ok_strict))
3396 if ((GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC)
3397 && !ALTIVEC_VECTOR_MODE (mode)
3398 && !SPE_VECTOR_MODE (mode)
3399 /* Restrict addressing for DI because of our SUBREG hackery. */
3400 && !(TARGET_E500_DOUBLE && (mode == DFmode || mode == DImode))
3402 && legitimate_indirect_address_p (XEXP (x, 0), reg_ok_strict))
3404 if (legitimate_small_data_p (mode, x))
3406 if (legitimate_constant_pool_address_p (x))
3408 /* If not REG_OK_STRICT (before reload) let pass any stack offset. */
3410 && GET_CODE (x) == PLUS
3411 && GET_CODE (XEXP (x, 0)) == REG
3412 && (XEXP (x, 0) == virtual_stack_vars_rtx
3413 || XEXP (x, 0) == arg_pointer_rtx)
3414 && GET_CODE (XEXP (x, 1)) == CONST_INT)
3416 if (rs6000_legitimate_offset_address_p (mode, x, reg_ok_strict))
3420 && ((TARGET_HARD_FLOAT && TARGET_FPRS)
3422 || ((mode != DFmode || TARGET_E500_DOUBLE) && mode != TFmode))
3423 && (TARGET_POWERPC64 || mode != DImode)
3424 && legitimate_indexed_address_p (x, reg_ok_strict))
3426 if (legitimate_lo_sum_address_p (mode, x, reg_ok_strict))
3431 /* Go to LABEL if ADDR (a legitimate address expression)
3432 has an effect that depends on the machine mode it is used for.
3434 On the RS/6000 this is true of all integral offsets (since AltiVec
3435 modes don't allow them) or is a pre-increment or decrement.
3437 ??? Except that due to conceptual problems in offsettable_address_p
3438 we can't really report the problems of integral offsets. So leave
3439 this assuming that the adjustable offset must be valid for the
3440 sub-words of a TFmode operand, which is what we had before. */
3443 rs6000_mode_dependent_address (rtx addr)
3445 switch (GET_CODE (addr))
3448 if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
3450 unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
3451 return val + 12 + 0x8000 >= 0x10000;
3460 return TARGET_UPDATE;
3469 /* Return number of consecutive hard regs needed starting at reg REGNO
3470 to hold something of mode MODE.
3471 This is ordinarily the length in words of a value of mode MODE
3472 but can be less for certain modes in special long registers.
3474 For the SPE, GPRs are 64 bits but only 32 bits are visible in
3475 scalar instructions. The upper 32 bits are only available to the
3478 POWER and PowerPC GPRs hold 32 bits worth;
3479 PowerPC64 GPRs and FPRs point register holds 64 bits worth. */
3482 rs6000_hard_regno_nregs (int regno, enum machine_mode mode)
3484 if (FP_REGNO_P (regno))
3485 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_WORD - 1) / UNITS_PER_FP_WORD;
3487 if (TARGET_E500_DOUBLE && mode == DFmode)
3490 if (SPE_SIMD_REGNO_P (regno) && TARGET_SPE && SPE_VECTOR_MODE (mode))
3491 return (GET_MODE_SIZE (mode) + UNITS_PER_SPE_WORD - 1) / UNITS_PER_SPE_WORD;
3493 if (ALTIVEC_REGNO_P (regno))
3495 (GET_MODE_SIZE (mode) + UNITS_PER_ALTIVEC_WORD - 1) / UNITS_PER_ALTIVEC_WORD;
3497 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3500 /* Change register usage conditional on target flags. */
3502 rs6000_conditional_register_usage (void)
3506 /* Set MQ register fixed (already call_used) if not POWER
3507 architecture (RIOS1, RIOS2, RSC, and PPC601) so that it will not
3512 /* 64-bit AIX and Linux reserve GPR13 for thread-private data. */
3514 fixed_regs[13] = call_used_regs[13]
3515 = call_really_used_regs[13] = 1;
3517 /* Conditionally disable FPRs. */
3518 if (TARGET_SOFT_FLOAT || !TARGET_FPRS)
3519 for (i = 32; i < 64; i++)
3520 fixed_regs[i] = call_used_regs[i]
3521 = call_really_used_regs[i] = 1;
3523 /* The TOC register is not killed across calls in a way that is
3524 visible to the compiler. */
3525 if (DEFAULT_ABI == ABI_AIX)
3526 call_really_used_regs[2] = 0;
3528 if (DEFAULT_ABI == ABI_V4
3529 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3531 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3533 if (DEFAULT_ABI == ABI_V4
3534 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM
3536 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3537 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3538 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3540 if (DEFAULT_ABI == ABI_DARWIN
3541 && PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM)
3542 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3543 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3544 = call_really_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3546 if (TARGET_TOC && TARGET_MINIMAL_TOC)
3547 fixed_regs[RS6000_PIC_OFFSET_TABLE_REGNUM]
3548 = call_used_regs[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
3551 global_regs[VSCR_REGNO] = 1;
3555 global_regs[SPEFSCR_REGNO] = 1;
3556 fixed_regs[FIXED_SCRATCH]
3557 = call_used_regs[FIXED_SCRATCH]
3558 = call_really_used_regs[FIXED_SCRATCH] = 1;
3561 if (! TARGET_ALTIVEC)
3563 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
3564 fixed_regs[i] = call_used_regs[i] = call_really_used_regs[i] = 1;
3565 call_really_used_regs[VRSAVE_REGNO] = 1;
3568 if (TARGET_ALTIVEC_ABI)
3569 for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
3570 call_used_regs[i] = call_really_used_regs[i] = 1;
3573 /* Try to output insns to set TARGET equal to the constant C if it can
3574 be done in less than N insns. Do all computations in MODE.
3575 Returns the place where the output has been placed if it can be
3576 done and the insns have been emitted. If it would take more than N
3577 insns, zero is returned and no insns and emitted. */
3580 rs6000_emit_set_const (rtx dest, enum machine_mode mode,
3581 rtx source, int n ATTRIBUTE_UNUSED)
3583 rtx result, insn, set;
3584 HOST_WIDE_INT c0, c1;
3591 dest = gen_reg_rtx (mode);
3592 emit_insn (gen_rtx_SET (VOIDmode, dest, source));
3596 result = no_new_pseudos ? dest : gen_reg_rtx (SImode);
3598 emit_insn (gen_rtx_SET (VOIDmode, result,
3599 GEN_INT (INTVAL (source)
3600 & (~ (HOST_WIDE_INT) 0xffff))));
3601 emit_insn (gen_rtx_SET (VOIDmode, dest,
3602 gen_rtx_IOR (SImode, result,
3603 GEN_INT (INTVAL (source) & 0xffff))));
3608 switch (GET_CODE (source))
3611 c0 = INTVAL (source);
3616 #if HOST_BITS_PER_WIDE_INT >= 64
3617 c0 = CONST_DOUBLE_LOW (source);
3620 c0 = CONST_DOUBLE_LOW (source);
3621 c1 = CONST_DOUBLE_HIGH (source);
3629 result = rs6000_emit_set_long_const (dest, c0, c1);
3636 insn = get_last_insn ();
3637 set = single_set (insn);
3638 if (! CONSTANT_P (SET_SRC (set)))
3639 set_unique_reg_note (insn, REG_EQUAL, source);
3644 /* Having failed to find a 3 insn sequence in rs6000_emit_set_const,
3645 fall back to a straight forward decomposition. We do this to avoid
3646 exponential run times encountered when looking for longer sequences
3647 with rs6000_emit_set_const. */
3649 rs6000_emit_set_long_const (rtx dest, HOST_WIDE_INT c1, HOST_WIDE_INT c2)
3651 if (!TARGET_POWERPC64)
3653 rtx operand1, operand2;
3655 operand1 = operand_subword_force (dest, WORDS_BIG_ENDIAN == 0,
3657 operand2 = operand_subword_force (dest, WORDS_BIG_ENDIAN != 0,
3659 emit_move_insn (operand1, GEN_INT (c1));
3660 emit_move_insn (operand2, GEN_INT (c2));
3664 HOST_WIDE_INT ud1, ud2, ud3, ud4;
3667 ud2 = (c1 & 0xffff0000) >> 16;
3668 #if HOST_BITS_PER_WIDE_INT >= 64
3672 ud4 = (c2 & 0xffff0000) >> 16;
3674 if ((ud4 == 0xffff && ud3 == 0xffff && ud2 == 0xffff && (ud1 & 0x8000))
3675 || (ud4 == 0 && ud3 == 0 && ud2 == 0 && ! (ud1 & 0x8000)))
3678 emit_move_insn (dest, GEN_INT (((ud1 ^ 0x8000) - 0x8000)));
3680 emit_move_insn (dest, GEN_INT (ud1));
3683 else if ((ud4 == 0xffff && ud3 == 0xffff && (ud2 & 0x8000))
3684 || (ud4 == 0 && ud3 == 0 && ! (ud2 & 0x8000)))
3687 emit_move_insn (dest, GEN_INT (((ud2 << 16) ^ 0x80000000)
3690 emit_move_insn (dest, GEN_INT (ud2 << 16));
3692 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3694 else if ((ud4 == 0xffff && (ud3 & 0x8000))
3695 || (ud4 == 0 && ! (ud3 & 0x8000)))
3698 emit_move_insn (dest, GEN_INT (((ud3 << 16) ^ 0x80000000)
3701 emit_move_insn (dest, GEN_INT (ud3 << 16));
3704 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud2)));
3705 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (16)));
3707 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3712 emit_move_insn (dest, GEN_INT (((ud4 << 16) ^ 0x80000000)
3715 emit_move_insn (dest, GEN_INT (ud4 << 16));
3718 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud3)));
3720 emit_move_insn (dest, gen_rtx_ASHIFT (DImode, dest, GEN_INT (32)));
3722 emit_move_insn (dest, gen_rtx_IOR (DImode, dest,
3723 GEN_INT (ud2 << 16)));
3725 emit_move_insn (dest, gen_rtx_IOR (DImode, dest, GEN_INT (ud1)));
3731 /* Helper for the following. Get rid of [r+r] memory refs
3732 in cases where it won't work (TImode, TFmode). */
3735 rs6000_eliminate_indexed_memrefs (rtx operands[2])
3737 if (GET_CODE (operands[0]) == MEM
3738 && GET_CODE (XEXP (operands[0], 0)) != REG
3739 && ! legitimate_constant_pool_address_p (XEXP (operands[0], 0))
3740 && ! reload_in_progress)
3742 = replace_equiv_address (operands[0],
3743 copy_addr_to_reg (XEXP (operands[0], 0)));
3745 if (GET_CODE (operands[1]) == MEM
3746 && GET_CODE (XEXP (operands[1], 0)) != REG
3747 && ! legitimate_constant_pool_address_p (XEXP (operands[1], 0))
3748 && ! reload_in_progress)
3750 = replace_equiv_address (operands[1],
3751 copy_addr_to_reg (XEXP (operands[1], 0)));
3754 /* Emit a move from SOURCE to DEST in mode MODE. */
3756 rs6000_emit_move (rtx dest, rtx source, enum machine_mode mode)
3760 operands[1] = source;
3762 /* Sanity checks. Check that we get CONST_DOUBLE only when we should. */
3763 if (GET_CODE (operands[1]) == CONST_DOUBLE
3764 && ! FLOAT_MODE_P (mode)
3765 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
3767 /* FIXME. This should never happen. */
3768 /* Since it seems that it does, do the safe thing and convert
3770 operands[1] = gen_int_mode (CONST_DOUBLE_LOW (operands[1]), mode);
3772 gcc_assert (GET_CODE (operands[1]) != CONST_DOUBLE
3773 || FLOAT_MODE_P (mode)
3774 || ((CONST_DOUBLE_HIGH (operands[1]) != 0
3775 || CONST_DOUBLE_LOW (operands[1]) < 0)
3776 && (CONST_DOUBLE_HIGH (operands[1]) != -1
3777 || CONST_DOUBLE_LOW (operands[1]) >= 0)));
3779 /* Check if GCC is setting up a block move that will end up using FP
3780 registers as temporaries. We must make sure this is acceptable. */
3781 if (GET_CODE (operands[0]) == MEM
3782 && GET_CODE (operands[1]) == MEM
3784 && (SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[0]))
3785 || SLOW_UNALIGNED_ACCESS (DImode, MEM_ALIGN (operands[1])))
3786 && ! (SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[0]) > 32
3787 ? 32 : MEM_ALIGN (operands[0])))
3788 || SLOW_UNALIGNED_ACCESS (SImode, (MEM_ALIGN (operands[1]) > 32
3790 : MEM_ALIGN (operands[1]))))
3791 && ! MEM_VOLATILE_P (operands [0])
3792 && ! MEM_VOLATILE_P (operands [1]))
3794 emit_move_insn (adjust_address (operands[0], SImode, 0),
3795 adjust_address (operands[1], SImode, 0));
3796 emit_move_insn (adjust_address (operands[0], SImode, 4),
3797 adjust_address (operands[1], SImode, 4));
3801 if (!no_new_pseudos && GET_CODE (operands[0]) == MEM
3802 && !gpc_reg_operand (operands[1], mode))
3803 operands[1] = force_reg (mode, operands[1]);
3805 if (mode == SFmode && ! TARGET_POWERPC
3806 && TARGET_HARD_FLOAT && TARGET_FPRS
3807 && GET_CODE (operands[0]) == MEM)
3811 if (reload_in_progress || reload_completed)
3812 regnum = true_regnum (operands[1]);
3813 else if (GET_CODE (operands[1]) == REG)
3814 regnum = REGNO (operands[1]);
3818 /* If operands[1] is a register, on POWER it may have
3819 double-precision data in it, so truncate it to single
3821 if (FP_REGNO_P (regnum) || regnum >= FIRST_PSEUDO_REGISTER)
3824 newreg = (no_new_pseudos ? operands[1] : gen_reg_rtx (mode));
3825 emit_insn (gen_aux_truncdfsf2 (newreg, operands[1]));
3826 operands[1] = newreg;
3830 /* Recognize the case where operand[1] is a reference to thread-local
3831 data and load its address to a register. */
3832 if (rs6000_tls_referenced_p (operands[1]))
3834 enum tls_model model;
3835 rtx tmp = operands[1];
3838 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
3840 addend = XEXP (XEXP (tmp, 0), 1);
3841 tmp = XEXP (XEXP (tmp, 0), 0);
3844 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
3845 model = SYMBOL_REF_TLS_MODEL (tmp);
3846 gcc_assert (model != 0);
3848 tmp = rs6000_legitimize_tls_address (tmp, model);
3851 tmp = gen_rtx_PLUS (mode, tmp, addend);
3852 tmp = force_operand (tmp, operands[0]);
3857 /* Handle the case where reload calls us with an invalid address. */
3858 if (reload_in_progress && mode == Pmode
3859 && (! general_operand (operands[1], mode)
3860 || ! nonimmediate_operand (operands[0], mode)))
3863 /* 128-bit constant floating-point values on Darwin should really be
3864 loaded as two parts. */
3865 if ((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
3866 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128
3867 && mode == TFmode && GET_CODE (operands[1]) == CONST_DOUBLE)
3869 /* DImode is used, not DFmode, because simplify_gen_subreg doesn't
3870 know how to get a DFmode SUBREG of a TFmode. */
3871 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode, 0),
3872 simplify_gen_subreg (DImode, operands[1], mode, 0),
3874 rs6000_emit_move (simplify_gen_subreg (DImode, operands[0], mode,
3875 GET_MODE_SIZE (DImode)),
3876 simplify_gen_subreg (DImode, operands[1], mode,
3877 GET_MODE_SIZE (DImode)),
3882 /* FIXME: In the long term, this switch statement should go away
3883 and be replaced by a sequence of tests based on things like
3889 if (CONSTANT_P (operands[1])
3890 && GET_CODE (operands[1]) != CONST_INT)
3891 operands[1] = force_const_mem (mode, operands[1]);
3895 rs6000_eliminate_indexed_memrefs (operands);
3900 if (CONSTANT_P (operands[1])
3901 && ! easy_fp_constant (operands[1], mode))
3902 operands[1] = force_const_mem (mode, operands[1]);
3913 if (CONSTANT_P (operands[1])
3914 && !easy_vector_constant (operands[1], mode))
3915 operands[1] = force_const_mem (mode, operands[1]);
3920 /* Use default pattern for address of ELF small data */
3923 && DEFAULT_ABI == ABI_V4
3924 && (GET_CODE (operands[1]) == SYMBOL_REF
3925 || GET_CODE (operands[1]) == CONST)
3926 && small_data_operand (operands[1], mode))
3928 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3932 if (DEFAULT_ABI == ABI_V4
3933 && mode == Pmode && mode == SImode
3934 && flag_pic == 1 && got_operand (operands[1], mode))
3936 emit_insn (gen_movsi_got (operands[0], operands[1]));
3940 if ((TARGET_ELF || DEFAULT_ABI == ABI_DARWIN)
3944 && CONSTANT_P (operands[1])
3945 && GET_CODE (operands[1]) != HIGH
3946 && GET_CODE (operands[1]) != CONST_INT)
3948 rtx target = (no_new_pseudos ? operands[0] : gen_reg_rtx (mode));
3950 /* If this is a function address on -mcall-aixdesc,
3951 convert it to the address of the descriptor. */
3952 if (DEFAULT_ABI == ABI_AIX
3953 && GET_CODE (operands[1]) == SYMBOL_REF
3954 && XSTR (operands[1], 0)[0] == '.')
3956 const char *name = XSTR (operands[1], 0);
3958 while (*name == '.')
3960 new_ref = gen_rtx_SYMBOL_REF (Pmode, name);
3961 CONSTANT_POOL_ADDRESS_P (new_ref)
3962 = CONSTANT_POOL_ADDRESS_P (operands[1]);
3963 SYMBOL_REF_FLAGS (new_ref) = SYMBOL_REF_FLAGS (operands[1]);
3964 SYMBOL_REF_USED (new_ref) = SYMBOL_REF_USED (operands[1]);
3965 SYMBOL_REF_DECL (new_ref) = SYMBOL_REF_DECL (operands[1]);
3966 operands[1] = new_ref;
3969 if (DEFAULT_ABI == ABI_DARWIN)
3972 if (MACHO_DYNAMIC_NO_PIC_P)
3974 /* Take care of any required data indirection. */
3975 operands[1] = rs6000_machopic_legitimize_pic_address (
3976 operands[1], mode, operands[0]);
3977 if (operands[0] != operands[1])
3978 emit_insn (gen_rtx_SET (VOIDmode,
3979 operands[0], operands[1]));
3983 emit_insn (gen_macho_high (target, operands[1]));
3984 emit_insn (gen_macho_low (operands[0], target, operands[1]));
3988 emit_insn (gen_elf_high (target, operands[1]));
3989 emit_insn (gen_elf_low (operands[0], target, operands[1]));
3993 /* If this is a SYMBOL_REF that refers to a constant pool entry,
3994 and we have put it in the TOC, we just need to make a TOC-relative
3997 && GET_CODE (operands[1]) == SYMBOL_REF
3998 && constant_pool_expr_p (operands[1])
3999 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (get_pool_constant (operands[1]),
4000 get_pool_mode (operands[1])))
4002 operands[1] = create_TOC_reference (operands[1]);
4004 else if (mode == Pmode
4005 && CONSTANT_P (operands[1])
4006 && ((GET_CODE (operands[1]) != CONST_INT
4007 && ! easy_fp_constant (operands[1], mode))
4008 || (GET_CODE (operands[1]) == CONST_INT
4009 && num_insns_constant (operands[1], mode) > 2)
4010 || (GET_CODE (operands[0]) == REG
4011 && FP_REGNO_P (REGNO (operands[0]))))
4012 && GET_CODE (operands[1]) != HIGH
4013 && ! legitimate_constant_pool_address_p (operands[1])
4014 && ! toc_relative_expr_p (operands[1]))
4016 /* Emit a USE operation so that the constant isn't deleted if
4017 expensive optimizations are turned on because nobody
4018 references it. This should only be done for operands that
4019 contain SYMBOL_REFs with CONSTANT_POOL_ADDRESS_P set.
4020 This should not be done for operands that contain LABEL_REFs.
4021 For now, we just handle the obvious case. */
4022 if (GET_CODE (operands[1]) != LABEL_REF)
4023 emit_insn (gen_rtx_USE (VOIDmode, operands[1]));
4026 /* Darwin uses a special PIC legitimizer. */
4027 if (DEFAULT_ABI == ABI_DARWIN && MACHOPIC_INDIRECT)
4030 rs6000_machopic_legitimize_pic_address (operands[1], mode,
4032 if (operands[0] != operands[1])
4033 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4038 /* If we are to limit the number of things we put in the TOC and
4039 this is a symbol plus a constant we can add in one insn,
4040 just put the symbol in the TOC and add the constant. Don't do
4041 this if reload is in progress. */
4042 if (GET_CODE (operands[1]) == CONST
4043 && TARGET_NO_SUM_IN_TOC && ! reload_in_progress
4044 && GET_CODE (XEXP (operands[1], 0)) == PLUS
4045 && add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
4046 && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
4047 || GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF)
4048 && ! side_effects_p (operands[0]))
4051 force_const_mem (mode, XEXP (XEXP (operands[1], 0), 0));
4052 rtx other = XEXP (XEXP (operands[1], 0), 1);
4054 sym = force_reg (mode, sym);
4056 emit_insn (gen_addsi3 (operands[0], sym, other));
4058 emit_insn (gen_adddi3 (operands[0], sym, other));
4062 operands[1] = force_const_mem (mode, operands[1]);
4065 && constant_pool_expr_p (XEXP (operands[1], 0))
4066 && ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (
4067 get_pool_constant (XEXP (operands[1], 0)),
4068 get_pool_mode (XEXP (operands[1], 0))))
4071 = gen_const_mem (mode,
4072 create_TOC_reference (XEXP (operands[1], 0)));
4073 set_mem_alias_set (operands[1], get_TOC_alias_set ());
4079 rs6000_eliminate_indexed_memrefs (operands);
4083 emit_insn (gen_rtx_PARALLEL (VOIDmode,
4085 gen_rtx_SET (VOIDmode,
4086 operands[0], operands[1]),
4087 gen_rtx_CLOBBER (VOIDmode,
4088 gen_rtx_SCRATCH (SImode)))));
4097 /* Above, we may have called force_const_mem which may have returned
4098 an invalid address. If we can, fix this up; otherwise, reload will
4099 have to deal with it. */
4100 if (GET_CODE (operands[1]) == MEM && ! reload_in_progress)
4101 operands[1] = validize_mem (operands[1]);
4104 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4107 /* Nonzero if we can use a floating-point register to pass this arg. */
4108 #define USE_FP_FOR_ARG_P(CUM,MODE,TYPE) \
4109 (GET_MODE_CLASS (MODE) == MODE_FLOAT \
4110 && (CUM)->fregno <= FP_ARG_MAX_REG \
4111 && TARGET_HARD_FLOAT && TARGET_FPRS)
4113 /* Nonzero if we can use an AltiVec register to pass this arg. */
4114 #define USE_ALTIVEC_FOR_ARG_P(CUM,MODE,TYPE,NAMED) \
4115 (ALTIVEC_VECTOR_MODE (MODE) \
4116 && (CUM)->vregno <= ALTIVEC_ARG_MAX_REG \
4117 && TARGET_ALTIVEC_ABI \
4120 /* Return a nonzero value to say to return the function value in
4121 memory, just as large structures are always returned. TYPE will be
4122 the data type of the value, and FNTYPE will be the type of the
4123 function doing the returning, or @code{NULL} for libcalls.
4125 The AIX ABI for the RS/6000 specifies that all structures are
4126 returned in memory. The Darwin ABI does the same. The SVR4 ABI
4127 specifies that structures <= 8 bytes are returned in r3/r4, but a
4128 draft put them in memory, and GCC used to implement the draft
4129 instead of the final standard. Therefore, aix_struct_return
4130 controls this instead of DEFAULT_ABI; V.4 targets needing backward
4131 compatibility can change DRAFT_V4_STRUCT_RET to override the
4132 default, and -m switches get the final word. See
4133 rs6000_override_options for more details.
4135 The PPC32 SVR4 ABI uses IEEE double extended for long double, if 128-bit
4136 long double support is enabled. These values are returned in memory.
4138 int_size_in_bytes returns -1 for variable size objects, which go in
4139 memory always. The cast to unsigned makes -1 > 8. */
4142 rs6000_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
4144 /* In the darwin64 abi, try to use registers for larger structs
4146 if (rs6000_darwin64_abi
4147 && TREE_CODE (type) == RECORD_TYPE
4148 && int_size_in_bytes (type) > 0)
4150 CUMULATIVE_ARGS valcum;
4154 valcum.fregno = FP_ARG_MIN_REG;
4155 valcum.vregno = ALTIVEC_ARG_MIN_REG;
4156 /* Do a trial code generation as if this were going to be passed
4157 as an argument; if any part goes in memory, we return NULL. */
4158 valret = rs6000_darwin64_record_arg (&valcum, type, 1, true);
4161 /* Otherwise fall through to more conventional ABI rules. */
4164 if (AGGREGATE_TYPE_P (type)
4165 && (aix_struct_return
4166 || (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8))
4169 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
4170 modes only exist for GCC vector types if -maltivec. */
4171 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI
4172 && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
4175 /* Return synthetic vectors in memory. */
4176 if (TREE_CODE (type) == VECTOR_TYPE
4177 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
4179 static bool warned_for_return_big_vectors = false;
4180 if (!warned_for_return_big_vectors)
4182 warning (0, "GCC vector returned by reference: "
4183 "non-standard ABI extension with no compatibility guarantee");
4184 warned_for_return_big_vectors = true;
4189 if (DEFAULT_ABI == ABI_V4 && TYPE_MODE (type) == TFmode)
4195 /* Initialize a variable CUM of type CUMULATIVE_ARGS
4196 for a call to a function whose data type is FNTYPE.
4197 For a library call, FNTYPE is 0.
4199 For incoming args we set the number of arguments in the prototype large
4200 so we never return a PARALLEL. */
4203 init_cumulative_args (CUMULATIVE_ARGS *cum, tree fntype,
4204 rtx libname ATTRIBUTE_UNUSED, int incoming,
4205 int libcall, int n_named_args)
4207 static CUMULATIVE_ARGS zero_cumulative;
4209 *cum = zero_cumulative;
4211 cum->fregno = FP_ARG_MIN_REG;
4212 cum->vregno = ALTIVEC_ARG_MIN_REG;
4213 cum->prototype = (fntype && TYPE_ARG_TYPES (fntype));
4214 cum->call_cookie = ((DEFAULT_ABI == ABI_V4 && libcall)
4215 ? CALL_LIBCALL : CALL_NORMAL);
4216 cum->sysv_gregno = GP_ARG_MIN_REG;
4217 cum->stdarg = fntype
4218 && (TYPE_ARG_TYPES (fntype) != 0
4219 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
4220 != void_type_node));
4222 cum->nargs_prototype = 0;
4223 if (incoming || cum->prototype)
4224 cum->nargs_prototype = n_named_args;
4226 /* Check for a longcall attribute. */
4227 if ((!fntype && rs6000_default_long_calls)
4229 && lookup_attribute ("longcall", TYPE_ATTRIBUTES (fntype))
4230 && !lookup_attribute ("shortcall", TYPE_ATTRIBUTES (fntype))))
4231 cum->call_cookie |= CALL_LONG;
4233 if (TARGET_DEBUG_ARG)
4235 fprintf (stderr, "\ninit_cumulative_args:");
4238 tree ret_type = TREE_TYPE (fntype);
4239 fprintf (stderr, " ret code = %s,",
4240 tree_code_name[ (int)TREE_CODE (ret_type) ]);
4243 if (cum->call_cookie & CALL_LONG)
4244 fprintf (stderr, " longcall,");
4246 fprintf (stderr, " proto = %d, nargs = %d\n",
4247 cum->prototype, cum->nargs_prototype);
4252 && TARGET_ALTIVEC_ABI
4253 && ALTIVEC_VECTOR_MODE (TYPE_MODE (TREE_TYPE (fntype))))
4255 error ("cannot return value in vector register because"
4256 " altivec instructions are disabled, use -maltivec"
4261 /* Return true if TYPE must be passed on the stack and not in registers. */
4264 rs6000_must_pass_in_stack (enum machine_mode mode, tree type)
4266 if (DEFAULT_ABI == ABI_AIX || TARGET_64BIT)
4267 return must_pass_in_stack_var_size (mode, type);
4269 return must_pass_in_stack_var_size_or_pad (mode, type);
4272 /* If defined, a C expression which determines whether, and in which
4273 direction, to pad out an argument with extra space. The value
4274 should be of type `enum direction': either `upward' to pad above
4275 the argument, `downward' to pad below, or `none' to inhibit
4278 For the AIX ABI structs are always stored left shifted in their
4282 function_arg_padding (enum machine_mode mode, tree type)
4284 #ifndef AGGREGATE_PADDING_FIXED
4285 #define AGGREGATE_PADDING_FIXED 0
4287 #ifndef AGGREGATES_PAD_UPWARD_ALWAYS
4288 #define AGGREGATES_PAD_UPWARD_ALWAYS 0
4291 if (!AGGREGATE_PADDING_FIXED)
4293 /* GCC used to pass structures of the same size as integer types as
4294 if they were in fact integers, ignoring FUNCTION_ARG_PADDING.
4295 i.e. Structures of size 1 or 2 (or 4 when TARGET_64BIT) were
4296 passed padded downward, except that -mstrict-align further
4297 muddied the water in that multi-component structures of 2 and 4
4298 bytes in size were passed padded upward.
4300 The following arranges for best compatibility with previous
4301 versions of gcc, but removes the -mstrict-align dependency. */
4302 if (BYTES_BIG_ENDIAN)
4304 HOST_WIDE_INT size = 0;
4306 if (mode == BLKmode)
4308 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
4309 size = int_size_in_bytes (type);
4312 size = GET_MODE_SIZE (mode);
4314 if (size == 1 || size == 2 || size == 4)
4320 if (AGGREGATES_PAD_UPWARD_ALWAYS)
4322 if (type != 0 && AGGREGATE_TYPE_P (type))
4326 /* Fall back to the default. */
4327 return DEFAULT_FUNCTION_ARG_PADDING (mode, type);
4330 /* If defined, a C expression that gives the alignment boundary, in bits,
4331 of an argument with the specified mode and type. If it is not defined,
4332 PARM_BOUNDARY is used for all arguments.
4334 V.4 wants long longs to be double word aligned.
4335 Doubleword align SPE vectors.
4336 Quadword align Altivec vectors.
4337 Quadword align large synthetic vector types. */
4340 function_arg_boundary (enum machine_mode mode, tree type)
4342 if (DEFAULT_ABI == ABI_V4 && GET_MODE_SIZE (mode) == 8)
4344 else if (SPE_VECTOR_MODE (mode)
4345 || (type && TREE_CODE (type) == VECTOR_TYPE
4346 && int_size_in_bytes (type) >= 8
4347 && int_size_in_bytes (type) < 16))
4349 else if (ALTIVEC_VECTOR_MODE (mode)
4350 || (type && TREE_CODE (type) == VECTOR_TYPE
4351 && int_size_in_bytes (type) >= 16))
4353 else if (rs6000_darwin64_abi && mode == BLKmode
4354 && type && TYPE_ALIGN (type) > 64)
4357 return PARM_BOUNDARY;
4360 /* For a function parm of MODE and TYPE, return the starting word in
4361 the parameter area. NWORDS of the parameter area are already used. */
4364 rs6000_parm_start (enum machine_mode mode, tree type, unsigned int nwords)
4367 unsigned int parm_offset;
4369 align = function_arg_boundary (mode, type) / PARM_BOUNDARY - 1;
4370 parm_offset = DEFAULT_ABI == ABI_V4 ? 2 : 6;
4371 return nwords + (-(parm_offset + nwords) & align);
4374 /* Compute the size (in words) of a function argument. */
4376 static unsigned long
4377 rs6000_arg_size (enum machine_mode mode, tree type)
4381 if (mode != BLKmode)
4382 size = GET_MODE_SIZE (mode);
4384 size = int_size_in_bytes (type);
4387 return (size + 3) >> 2;
4389 return (size + 7) >> 3;
4392 /* Use this to flush pending int fields. */
4395 rs6000_darwin64_record_arg_advance_flush (CUMULATIVE_ARGS *cum,
4396 HOST_WIDE_INT bitpos)
4398 unsigned int startbit, endbit;
4399 int intregs, intoffset;
4400 enum machine_mode mode;
4402 if (cum->intoffset == -1)
4405 intoffset = cum->intoffset;
4406 cum->intoffset = -1;
4408 if (intoffset % BITS_PER_WORD != 0)
4410 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4412 if (mode == BLKmode)
4414 /* We couldn't find an appropriate mode, which happens,
4415 e.g., in packed structs when there are 3 bytes to load.
4416 Back intoffset back to the beginning of the word in this
4418 intoffset = intoffset & -BITS_PER_WORD;
4422 startbit = intoffset & -BITS_PER_WORD;
4423 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4424 intregs = (endbit - startbit) / BITS_PER_WORD;
4425 cum->words += intregs;
4428 /* The darwin64 ABI calls for us to recurse down through structs,
4429 looking for elements passed in registers. Unfortunately, we have
4430 to track int register count here also because of misalignments
4431 in powerpc alignment mode. */
4434 rs6000_darwin64_record_arg_advance_recurse (CUMULATIVE_ARGS *cum,
4436 HOST_WIDE_INT startbitpos)
4440 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4441 if (TREE_CODE (f) == FIELD_DECL)
4443 HOST_WIDE_INT bitpos = startbitpos;
4444 tree ftype = TREE_TYPE (f);
4445 enum machine_mode mode = TYPE_MODE (ftype);
4447 if (DECL_SIZE (f) != 0
4448 && host_integerp (bit_position (f), 1))
4449 bitpos += int_bit_position (f);
4451 /* ??? FIXME: else assume zero offset. */
4453 if (TREE_CODE (ftype) == RECORD_TYPE)
4454 rs6000_darwin64_record_arg_advance_recurse (cum, ftype, bitpos);
4455 else if (USE_FP_FOR_ARG_P (cum, mode, ftype))
4457 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4458 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4459 cum->words += (GET_MODE_SIZE (mode) + 7) >> 3;
4461 else if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, 1))
4463 rs6000_darwin64_record_arg_advance_flush (cum, bitpos);
4467 else if (cum->intoffset == -1)
4468 cum->intoffset = bitpos;
4472 /* Update the data in CUM to advance over an argument
4473 of mode MODE and data type TYPE.
4474 (TYPE is null for libcalls where that information may not be available.)
4476 Note that for args passed by reference, function_arg will be called
4477 with MODE and TYPE set to that of the pointer to the arg, not the arg
4481 function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4482 tree type, int named, int depth)
4486 /* Only tick off an argument if we're not recursing. */
4488 cum->nargs_prototype--;
4490 if (TARGET_ALTIVEC_ABI
4491 && (ALTIVEC_VECTOR_MODE (mode)
4492 || (type && TREE_CODE (type) == VECTOR_TYPE
4493 && int_size_in_bytes (type) == 16)))
4497 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
4500 if (!TARGET_ALTIVEC)
4501 error ("cannot pass argument in vector register because"
4502 " altivec instructions are disabled, use -maltivec"
4505 /* PowerPC64 Linux and AIX allocate GPRs for a vector argument
4506 even if it is going to be passed in a vector register.
4507 Darwin does the same for variable-argument functions. */
4508 if ((DEFAULT_ABI == ABI_AIX && TARGET_64BIT)
4509 || (cum->stdarg && DEFAULT_ABI != ABI_V4))
4519 /* Vector parameters must be 16-byte aligned. This places
4520 them at 2 mod 4 in terms of words in 32-bit mode, since
4521 the parameter save area starts at offset 24 from the
4522 stack. In 64-bit mode, they just have to start on an
4523 even word, since the parameter save area is 16-byte
4524 aligned. Space for GPRs is reserved even if the argument
4525 will be passed in memory. */
4527 align = (2 - cum->words) & 3;
4529 align = cum->words & 1;
4530 cum->words += align + rs6000_arg_size (mode, type);
4532 if (TARGET_DEBUG_ARG)
4534 fprintf (stderr, "function_adv: words = %2d, align=%d, ",
4536 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s\n",
4537 cum->nargs_prototype, cum->prototype,
4538 GET_MODE_NAME (mode));
4542 else if (TARGET_SPE_ABI && TARGET_SPE && SPE_VECTOR_MODE (mode)
4544 && cum->sysv_gregno <= GP_ARG_MAX_REG)
4547 else if (rs6000_darwin64_abi
4549 && TREE_CODE (type) == RECORD_TYPE
4550 && (size = int_size_in_bytes (type)) > 0)
4552 /* Variable sized types have size == -1 and are
4553 treated as if consisting entirely of ints.
4554 Pad to 16 byte boundary if needed. */
4555 if (TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4556 && (cum->words % 2) != 0)
4558 /* For varargs, we can just go up by the size of the struct. */
4560 cum->words += (size + 7) / 8;
4563 /* It is tempting to say int register count just goes up by
4564 sizeof(type)/8, but this is wrong in a case such as
4565 { int; double; int; } [powerpc alignment]. We have to
4566 grovel through the fields for these too. */
4568 rs6000_darwin64_record_arg_advance_recurse (cum, type, 0);
4569 rs6000_darwin64_record_arg_advance_flush (cum,
4570 size * BITS_PER_UNIT);
4573 else if (DEFAULT_ABI == ABI_V4)
4575 if (TARGET_HARD_FLOAT && TARGET_FPRS
4576 && (mode == SFmode || mode == DFmode))
4578 if (cum->fregno <= FP_ARG_V4_MAX_REG)
4583 cum->words += cum->words & 1;
4584 cum->words += rs6000_arg_size (mode, type);
4589 int n_words = rs6000_arg_size (mode, type);
4590 int gregno = cum->sysv_gregno;
4592 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
4593 (r7,r8) or (r9,r10). As does any other 2 word item such
4594 as complex int due to a historical mistake. */
4596 gregno += (1 - gregno) & 1;
4598 /* Multi-reg args are not split between registers and stack. */
4599 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4601 /* Long long and SPE vectors are aligned on the stack.
4602 So are other 2 word items such as complex int due to
4603 a historical mistake. */
4605 cum->words += cum->words & 1;
4606 cum->words += n_words;
4609 /* Note: continuing to accumulate gregno past when we've started
4610 spilling to the stack indicates the fact that we've started
4611 spilling to the stack to expand_builtin_saveregs. */
4612 cum->sysv_gregno = gregno + n_words;
4615 if (TARGET_DEBUG_ARG)
4617 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4618 cum->words, cum->fregno);
4619 fprintf (stderr, "gregno = %2d, nargs = %4d, proto = %d, ",
4620 cum->sysv_gregno, cum->nargs_prototype, cum->prototype);
4621 fprintf (stderr, "mode = %4s, named = %d\n",
4622 GET_MODE_NAME (mode), named);
4627 int n_words = rs6000_arg_size (mode, type);
4628 int start_words = cum->words;
4629 int align_words = rs6000_parm_start (mode, type, start_words);
4631 cum->words = align_words + n_words;
4633 if (GET_MODE_CLASS (mode) == MODE_FLOAT
4634 && TARGET_HARD_FLOAT && TARGET_FPRS)
4635 cum->fregno += (GET_MODE_SIZE (mode) + 7) >> 3;
4637 if (TARGET_DEBUG_ARG)
4639 fprintf (stderr, "function_adv: words = %2d, fregno = %2d, ",
4640 cum->words, cum->fregno);
4641 fprintf (stderr, "nargs = %4d, proto = %d, mode = %4s, ",
4642 cum->nargs_prototype, cum->prototype, GET_MODE_NAME (mode));
4643 fprintf (stderr, "named = %d, align = %d, depth = %d\n",
4644 named, align_words - start_words, depth);
4650 spe_build_register_parallel (enum machine_mode mode, int gregno)
4657 r1 = gen_rtx_REG (DImode, gregno);
4658 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4659 return gen_rtx_PARALLEL (mode, gen_rtvec (1, r1));
4662 r1 = gen_rtx_REG (DImode, gregno);
4663 r1 = gen_rtx_EXPR_LIST (VOIDmode, r1, const0_rtx);
4664 r3 = gen_rtx_REG (DImode, gregno + 2);
4665 r3 = gen_rtx_EXPR_LIST (VOIDmode, r3, GEN_INT (8));
4666 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r3));
4673 /* Determine where to put a SIMD argument on the SPE. */
4675 rs6000_spe_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4678 int gregno = cum->sysv_gregno;
4680 /* On E500 v2, double arithmetic is done on the full 64-bit GPR, but
4681 are passed and returned in a pair of GPRs for ABI compatibility. */
4682 if (TARGET_E500_DOUBLE && (mode == DFmode || mode == DCmode))
4684 int n_words = rs6000_arg_size (mode, type);
4686 /* Doubles go in an odd/even register pair (r5/r6, etc). */
4688 gregno += (1 - gregno) & 1;
4690 /* Multi-reg args are not split between registers and stack. */
4691 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
4694 return spe_build_register_parallel (mode, gregno);
4698 int n_words = rs6000_arg_size (mode, type);
4700 /* SPE vectors are put in odd registers. */
4701 if (n_words == 2 && (gregno & 1) == 0)
4704 if (gregno + n_words - 1 <= GP_ARG_MAX_REG)
4707 enum machine_mode m = SImode;
4709 r1 = gen_rtx_REG (m, gregno);
4710 r1 = gen_rtx_EXPR_LIST (m, r1, const0_rtx);
4711 r2 = gen_rtx_REG (m, gregno + 1);
4712 r2 = gen_rtx_EXPR_LIST (m, r2, GEN_INT (4));
4713 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
4720 if (gregno <= GP_ARG_MAX_REG)
4721 return gen_rtx_REG (mode, gregno);
4727 /* A subroutine of rs6000_darwin64_record_arg. Assign the bits of the
4728 structure between cum->intoffset and bitpos to integer registers. */
4731 rs6000_darwin64_record_arg_flush (CUMULATIVE_ARGS *cum,
4732 HOST_WIDE_INT bitpos, rtx rvec[], int *k)
4734 enum machine_mode mode;
4736 unsigned int startbit, endbit;
4737 int this_regno, intregs, intoffset;
4740 if (cum->intoffset == -1)
4743 intoffset = cum->intoffset;
4744 cum->intoffset = -1;
4746 /* If this is the trailing part of a word, try to only load that
4747 much into the register. Otherwise load the whole register. Note
4748 that in the latter case we may pick up unwanted bits. It's not a
4749 problem at the moment but may wish to revisit. */
4751 if (intoffset % BITS_PER_WORD != 0)
4753 mode = mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD,
4755 if (mode == BLKmode)
4757 /* We couldn't find an appropriate mode, which happens,
4758 e.g., in packed structs when there are 3 bytes to load.
4759 Back intoffset back to the beginning of the word in this
4761 intoffset = intoffset & -BITS_PER_WORD;
4768 startbit = intoffset & -BITS_PER_WORD;
4769 endbit = (bitpos + BITS_PER_WORD - 1) & -BITS_PER_WORD;
4770 intregs = (endbit - startbit) / BITS_PER_WORD;
4771 this_regno = cum->words + intoffset / BITS_PER_WORD;
4773 if (intregs > 0 && intregs > GP_ARG_NUM_REG - this_regno)
4776 intregs = MIN (intregs, GP_ARG_NUM_REG - this_regno);
4780 intoffset /= BITS_PER_UNIT;
4783 regno = GP_ARG_MIN_REG + this_regno;
4784 reg = gen_rtx_REG (mode, regno);
4786 gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset));
4789 intoffset = (intoffset | (UNITS_PER_WORD-1)) + 1;
4793 while (intregs > 0);
4796 /* Recursive workhorse for the following. */
4799 rs6000_darwin64_record_arg_recurse (CUMULATIVE_ARGS *cum, tree type,
4800 HOST_WIDE_INT startbitpos, rtx rvec[],
4805 for (f = TYPE_FIELDS (type); f ; f = TREE_CHAIN (f))
4806 if (TREE_CODE (f) == FIELD_DECL)
4808 HOST_WIDE_INT bitpos = startbitpos;
4809 tree ftype = TREE_TYPE (f);
4810 enum machine_mode mode = TYPE_MODE (ftype);
4812 if (DECL_SIZE (f) != 0
4813 && host_integerp (bit_position (f), 1))
4814 bitpos += int_bit_position (f);
4816 /* ??? FIXME: else assume zero offset. */
4818 if (TREE_CODE (ftype) == RECORD_TYPE)
4819 rs6000_darwin64_record_arg_recurse (cum, ftype, bitpos, rvec, k);
4820 else if (cum->named && USE_FP_FOR_ARG_P (cum, mode, ftype))
4825 case SCmode: mode = SFmode; break;
4826 case DCmode: mode = DFmode; break;
4827 case TCmode: mode = TFmode; break;
4831 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4833 = gen_rtx_EXPR_LIST (VOIDmode,
4834 gen_rtx_REG (mode, cum->fregno++),
4835 GEN_INT (bitpos / BITS_PER_UNIT));
4839 else if (cum->named && USE_ALTIVEC_FOR_ARG_P (cum, mode, ftype, 1))
4841 rs6000_darwin64_record_arg_flush (cum, bitpos, rvec, k);
4843 = gen_rtx_EXPR_LIST (VOIDmode,
4844 gen_rtx_REG (mode, cum->vregno++),
4845 GEN_INT (bitpos / BITS_PER_UNIT));
4847 else if (cum->intoffset == -1)
4848 cum->intoffset = bitpos;
4852 /* For the darwin64 ABI, we want to construct a PARALLEL consisting of
4853 the register(s) to be used for each field and subfield of a struct
4854 being passed by value, along with the offset of where the
4855 register's value may be found in the block. FP fields go in FP
4856 register, vector fields go in vector registers, and everything
4857 else goes in int registers, packed as in memory.
4859 This code is also used for function return values. RETVAL indicates
4860 whether this is the case.
4862 Much of this is taken from the SPARC V9 port, which has a similar
4863 calling convention. */
4866 rs6000_darwin64_record_arg (CUMULATIVE_ARGS *orig_cum, tree type,
4867 int named, bool retval)
4869 rtx rvec[FIRST_PSEUDO_REGISTER];
4870 int k = 1, kbase = 1;
4871 HOST_WIDE_INT typesize = int_size_in_bytes (type);
4872 /* This is a copy; modifications are not visible to our caller. */
4873 CUMULATIVE_ARGS copy_cum = *orig_cum;
4874 CUMULATIVE_ARGS *cum = ©_cum;
4876 /* Pad to 16 byte boundary if needed. */
4877 if (!retval && TYPE_ALIGN (type) >= 2 * BITS_PER_WORD
4878 && (cum->words % 2) != 0)
4885 /* Put entries into rvec[] for individual FP and vector fields, and
4886 for the chunks of memory that go in int regs. Note we start at
4887 element 1; 0 is reserved for an indication of using memory, and
4888 may or may not be filled in below. */
4889 rs6000_darwin64_record_arg_recurse (cum, type, 0, rvec, &k);
4890 rs6000_darwin64_record_arg_flush (cum, typesize * BITS_PER_UNIT, rvec, &k);
4892 /* If any part of the struct went on the stack put all of it there.
4893 This hack is because the generic code for
4894 FUNCTION_ARG_PARTIAL_NREGS cannot handle cases where the register
4895 parts of the struct are not at the beginning. */
4899 return NULL_RTX; /* doesn't go in registers at all */
4901 rvec[0] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4903 if (k > 1 || cum->use_stack)
4904 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (k - kbase, &rvec[kbase]));
4909 /* Determine where to place an argument in 64-bit mode with 32-bit ABI. */
4912 rs6000_mixed_function_arg (enum machine_mode mode, tree type, int align_words)
4916 rtx rvec[GP_ARG_NUM_REG + 1];
4918 if (align_words >= GP_ARG_NUM_REG)
4921 n_units = rs6000_arg_size (mode, type);
4923 /* Optimize the simple case where the arg fits in one gpr, except in
4924 the case of BLKmode due to assign_parms assuming that registers are
4925 BITS_PER_WORD wide. */
4927 || (n_units == 1 && mode != BLKmode))
4928 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
4931 if (align_words + n_units > GP_ARG_NUM_REG)
4932 /* Not all of the arg fits in gprs. Say that it goes in memory too,
4933 using a magic NULL_RTX component.
4934 FIXME: This is not strictly correct. Only some of the arg
4935 belongs in memory, not all of it. However, there isn't any way
4936 to do this currently, apart from building rtx descriptions for
4937 the pieces of memory we want stored. Due to bugs in the generic
4938 code we can't use the normal function_arg_partial_nregs scheme
4939 with the PARALLEL arg description we emit here.
4940 In any case, the code to store the whole arg to memory is often
4941 more efficient than code to store pieces, and we know that space
4942 is available in the right place for the whole arg. */
4943 /* FIXME: This should be fixed since the conversion to
4944 TARGET_ARG_PARTIAL_BYTES. */
4945 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
4950 rtx r = gen_rtx_REG (SImode, GP_ARG_MIN_REG + align_words);
4951 rtx off = GEN_INT (i++ * 4);
4952 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
4954 while (++align_words < GP_ARG_NUM_REG && --n_units != 0);
4956 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
4959 /* Determine where to put an argument to a function.
4960 Value is zero to push the argument on the stack,
4961 or a hard register in which to store the argument.
4963 MODE is the argument's machine mode.
4964 TYPE is the data type of the argument (as a tree).
4965 This is null for libcalls where that information may
4967 CUM is a variable of type CUMULATIVE_ARGS which gives info about
4968 the preceding args and about the function being called. It is
4969 not modified in this routine.
4970 NAMED is nonzero if this argument is a named parameter
4971 (otherwise it is an extra parameter matching an ellipsis).
4973 On RS/6000 the first eight words of non-FP are normally in registers
4974 and the rest are pushed. Under AIX, the first 13 FP args are in registers.
4975 Under V.4, the first 8 FP args are in registers.
4977 If this is floating-point and no prototype is specified, we use
4978 both an FP and integer register (or possibly FP reg and stack). Library
4979 functions (when CALL_LIBCALL is set) always have the proper types for args,
4980 so we can pass the FP value just in one register. emit_library_function
4981 doesn't support PARALLEL anyway.
4983 Note that for args passed by reference, function_arg will be called
4984 with MODE and TYPE set to that of the pointer to the arg, not the arg
4988 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
4989 tree type, int named)
4991 enum rs6000_abi abi = DEFAULT_ABI;
4993 /* Return a marker to indicate whether CR1 needs to set or clear the
4994 bit that V.4 uses to say fp args were passed in registers.
4995 Assume that we don't need the marker for software floating point,
4996 or compiler generated library calls. */
4997 if (mode == VOIDmode)
5000 && cum->nargs_prototype < 0
5001 && (cum->call_cookie & CALL_LIBCALL) == 0
5002 && (cum->prototype || TARGET_NO_PROTOTYPE))
5004 /* For the SPE, we need to crxor CR6 always. */
5006 return GEN_INT (cum->call_cookie | CALL_V4_SET_FP_ARGS);
5007 else if (TARGET_HARD_FLOAT && TARGET_FPRS)
5008 return GEN_INT (cum->call_cookie
5009 | ((cum->fregno == FP_ARG_MIN_REG)
5010 ? CALL_V4_SET_FP_ARGS
5011 : CALL_V4_CLEAR_FP_ARGS));
5014 return GEN_INT (cum->call_cookie);
5017 if (rs6000_darwin64_abi && mode == BLKmode
5018 && TREE_CODE (type) == RECORD_TYPE)
5020 rtx rslt = rs6000_darwin64_record_arg (cum, type, named, false);
5021 if (rslt != NULL_RTX)
5023 /* Else fall through to usual handling. */
5026 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named))
5027 if (TARGET_64BIT && ! cum->prototype)
5029 /* Vector parameters get passed in vector register
5030 and also in GPRs or memory, in absence of prototype. */
5033 align_words = (cum->words + 1) & ~1;
5035 if (align_words >= GP_ARG_NUM_REG)
5041 slot = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5043 return gen_rtx_PARALLEL (mode,
5045 gen_rtx_EXPR_LIST (VOIDmode,
5047 gen_rtx_EXPR_LIST (VOIDmode,
5048 gen_rtx_REG (mode, cum->vregno),
5052 return gen_rtx_REG (mode, cum->vregno);
5053 else if (TARGET_ALTIVEC_ABI
5054 && (ALTIVEC_VECTOR_MODE (mode)
5055 || (type && TREE_CODE (type) == VECTOR_TYPE
5056 && int_size_in_bytes (type) == 16)))
5058 if (named || abi == ABI_V4)
5062 /* Vector parameters to varargs functions under AIX or Darwin
5063 get passed in memory and possibly also in GPRs. */
5064 int align, align_words, n_words;
5065 enum machine_mode part_mode;
5067 /* Vector parameters must be 16-byte aligned. This places them at
5068 2 mod 4 in terms of words in 32-bit mode, since the parameter
5069 save area starts at offset 24 from the stack. In 64-bit mode,
5070 they just have to start on an even word, since the parameter
5071 save area is 16-byte aligned. */
5073 align = (2 - cum->words) & 3;
5075 align = cum->words & 1;
5076 align_words = cum->words + align;
5078 /* Out of registers? Memory, then. */
5079 if (align_words >= GP_ARG_NUM_REG)
5082 if (TARGET_32BIT && TARGET_POWERPC64)
5083 return rs6000_mixed_function_arg (mode, type, align_words);
5085 /* The vector value goes in GPRs. Only the part of the
5086 value in GPRs is reported here. */
5088 n_words = rs6000_arg_size (mode, type);
5089 if (align_words + n_words > GP_ARG_NUM_REG)
5090 /* Fortunately, there are only two possibilities, the value
5091 is either wholly in GPRs or half in GPRs and half not. */
5094 return gen_rtx_REG (part_mode, GP_ARG_MIN_REG + align_words);
5097 else if (TARGET_SPE_ABI && TARGET_SPE
5098 && (SPE_VECTOR_MODE (mode)
5099 || (TARGET_E500_DOUBLE && (mode == DFmode
5100 || mode == DCmode))))
5101 return rs6000_spe_function_arg (cum, mode, type);
5103 else if (abi == ABI_V4)
5105 if (TARGET_HARD_FLOAT && TARGET_FPRS
5106 && (mode == SFmode || mode == DFmode))
5108 if (cum->fregno <= FP_ARG_V4_MAX_REG)
5109 return gen_rtx_REG (mode, cum->fregno);
5115 int n_words = rs6000_arg_size (mode, type);
5116 int gregno = cum->sysv_gregno;
5118 /* Long long and SPE vectors are put in (r3,r4), (r5,r6),
5119 (r7,r8) or (r9,r10). As does any other 2 word item such
5120 as complex int due to a historical mistake. */
5122 gregno += (1 - gregno) & 1;
5124 /* Multi-reg args are not split between registers and stack. */
5125 if (gregno + n_words - 1 > GP_ARG_MAX_REG)
5128 if (TARGET_32BIT && TARGET_POWERPC64)
5129 return rs6000_mixed_function_arg (mode, type,
5130 gregno - GP_ARG_MIN_REG);
5131 return gen_rtx_REG (mode, gregno);
5136 int align_words = rs6000_parm_start (mode, type, cum->words);
5138 if (USE_FP_FOR_ARG_P (cum, mode, type))
5140 rtx rvec[GP_ARG_NUM_REG + 1];
5144 enum machine_mode fmode = mode;
5145 unsigned long n_fpreg = (GET_MODE_SIZE (mode) + 7) >> 3;
5147 if (cum->fregno + n_fpreg > FP_ARG_MAX_REG + 1)
5149 /* Currently, we only ever need one reg here because complex
5150 doubles are split. */
5151 gcc_assert (cum->fregno == FP_ARG_MAX_REG && fmode == TFmode);
5153 /* Long double split over regs and memory. */
5157 /* Do we also need to pass this arg in the parameter save
5160 && (cum->nargs_prototype <= 0
5161 || (DEFAULT_ABI == ABI_AIX
5163 && align_words >= GP_ARG_NUM_REG)));
5165 if (!needs_psave && mode == fmode)
5166 return gen_rtx_REG (fmode, cum->fregno);
5171 /* Describe the part that goes in gprs or the stack.
5172 This piece must come first, before the fprs. */
5173 if (align_words < GP_ARG_NUM_REG)
5175 unsigned long n_words = rs6000_arg_size (mode, type);
5177 if (align_words + n_words > GP_ARG_NUM_REG
5178 || (TARGET_32BIT && TARGET_POWERPC64))
5180 /* If this is partially on the stack, then we only
5181 include the portion actually in registers here. */
5182 enum machine_mode rmode = TARGET_32BIT ? SImode : DImode;
5185 if (align_words + n_words > GP_ARG_NUM_REG
5186 && (TARGET_32BIT && TARGET_POWERPC64))
5187 /* Not all of the arg fits in gprs. Say that it
5188 goes in memory too, using a magic NULL_RTX
5189 component. Also see comment in
5190 rs6000_mixed_function_arg for why the normal
5191 function_arg_partial_nregs scheme doesn't work
5193 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX,
5197 r = gen_rtx_REG (rmode,
5198 GP_ARG_MIN_REG + align_words);
5199 off = GEN_INT (i++ * GET_MODE_SIZE (rmode));
5200 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, off);
5202 while (++align_words < GP_ARG_NUM_REG && --n_words != 0);
5206 /* The whole arg fits in gprs. */
5207 r = gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5208 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5212 /* It's entirely in memory. */
5213 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx);
5216 /* Describe where this piece goes in the fprs. */
5217 r = gen_rtx_REG (fmode, cum->fregno);
5218 rvec[k++] = gen_rtx_EXPR_LIST (VOIDmode, r, const0_rtx);
5220 return gen_rtx_PARALLEL (mode, gen_rtvec_v (k, rvec));
5222 else if (align_words < GP_ARG_NUM_REG)
5224 if (TARGET_32BIT && TARGET_POWERPC64)
5225 return rs6000_mixed_function_arg (mode, type, align_words);
5227 if (mode == BLKmode)
5230 return gen_rtx_REG (mode, GP_ARG_MIN_REG + align_words);
5237 /* For an arg passed partly in registers and partly in memory, this is
5238 the number of bytes passed in registers. For args passed entirely in
5239 registers or entirely in memory, zero. When an arg is described by a
5240 PARALLEL, perhaps using more than one register type, this function
5241 returns the number of bytes used by the first element of the PARALLEL. */
5244 rs6000_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5245 tree type, bool named)
5250 if (DEFAULT_ABI == ABI_V4)
5253 if (USE_ALTIVEC_FOR_ARG_P (cum, mode, type, named)
5254 && cum->nargs_prototype >= 0)
5257 /* In this complicated case we just disable the partial_nregs code. */
5258 if (rs6000_darwin64_abi && mode == BLKmode
5259 && TREE_CODE (type) == RECORD_TYPE
5260 && int_size_in_bytes (type) > 0)
5263 align_words = rs6000_parm_start (mode, type, cum->words);
5265 if (USE_FP_FOR_ARG_P (cum, mode, type)
5266 /* If we are passing this arg in the fixed parameter save area
5267 (gprs or memory) as well as fprs, then this function should
5268 return the number of bytes passed in the parameter save area
5269 rather than bytes passed in fprs. */
5271 && (cum->nargs_prototype <= 0
5272 || (DEFAULT_ABI == ABI_AIX
5274 && align_words >= GP_ARG_NUM_REG))))
5276 if (cum->fregno + ((GET_MODE_SIZE (mode) + 7) >> 3) > FP_ARG_MAX_REG + 1)
5277 ret = (FP_ARG_MAX_REG + 1 - cum->fregno) * 8;
5278 else if (cum->nargs_prototype >= 0)
5282 if (align_words < GP_ARG_NUM_REG
5283 && GP_ARG_NUM_REG < align_words + rs6000_arg_size (mode, type))
5284 ret = (GP_ARG_NUM_REG - align_words) * (TARGET_32BIT ? 4 : 8);
5286 if (ret != 0 && TARGET_DEBUG_ARG)
5287 fprintf (stderr, "rs6000_arg_partial_bytes: %d\n", ret);
5292 /* A C expression that indicates when an argument must be passed by
5293 reference. If nonzero for an argument, a copy of that argument is
5294 made in memory and a pointer to the argument is passed instead of
5295 the argument itself. The pointer is passed in whatever way is
5296 appropriate for passing a pointer to that type.
5298 Under V.4, aggregates and long double are passed by reference.
5300 As an extension to all 32-bit ABIs, AltiVec vectors are passed by
5301 reference unless the AltiVec vector extension ABI is in force.
5303 As an extension to all ABIs, variable sized types are passed by
5307 rs6000_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
5308 enum machine_mode mode, tree type,
5309 bool named ATTRIBUTE_UNUSED)
5311 if (DEFAULT_ABI == ABI_V4 && mode == TFmode)
5313 if (TARGET_DEBUG_ARG)
5314 fprintf (stderr, "function_arg_pass_by_reference: V4 long double\n");
5321 if (DEFAULT_ABI == ABI_V4 && AGGREGATE_TYPE_P (type))
5323 if (TARGET_DEBUG_ARG)
5324 fprintf (stderr, "function_arg_pass_by_reference: V4 aggregate\n");
5328 if (int_size_in_bytes (type) < 0)
5330 if (TARGET_DEBUG_ARG)
5331 fprintf (stderr, "function_arg_pass_by_reference: variable size\n");
5335 /* Allow -maltivec -mabi=no-altivec without warning. Altivec vector
5336 modes only exist for GCC vector types if -maltivec. */
5337 if (TARGET_32BIT && !TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
5339 if (TARGET_DEBUG_ARG)
5340 fprintf (stderr, "function_arg_pass_by_reference: AltiVec\n");
5344 /* Pass synthetic vectors in memory. */
5345 if (TREE_CODE (type) == VECTOR_TYPE
5346 && int_size_in_bytes (type) > (TARGET_ALTIVEC_ABI ? 16 : 8))
5348 static bool warned_for_pass_big_vectors = false;
5349 if (TARGET_DEBUG_ARG)
5350 fprintf (stderr, "function_arg_pass_by_reference: synthetic vector\n");
5351 if (!warned_for_pass_big_vectors)
5353 warning (0, "GCC vector passed by reference: "
5354 "non-standard ABI extension with no compatibility guarantee");
5355 warned_for_pass_big_vectors = true;
5364 rs6000_move_block_from_reg (int regno, rtx x, int nregs)
5367 enum machine_mode reg_mode = TARGET_32BIT ? SImode : DImode;
5372 for (i = 0; i < nregs; i++)
5374 rtx tem = adjust_address_nv (x, reg_mode, i * GET_MODE_SIZE (reg_mode));
5375 if (reload_completed)
5377 if (! strict_memory_address_p (reg_mode, XEXP (tem, 0)))
5380 tem = simplify_gen_subreg (reg_mode, x, BLKmode,
5381 i * GET_MODE_SIZE (reg_mode));
5384 tem = replace_equiv_address (tem, XEXP (tem, 0));
5388 emit_move_insn (tem, gen_rtx_REG (reg_mode, regno + i));
5392 /* Perform any needed actions needed for a function that is receiving a
5393 variable number of arguments.
5397 MODE and TYPE are the mode and type of the current parameter.
5399 PRETEND_SIZE is a variable that should be set to the amount of stack
5400 that must be pushed by the prolog to pretend that our caller pushed
5403 Normally, this macro will push all remaining incoming registers on the
5404 stack and set PRETEND_SIZE to the length of the registers pushed. */
5407 setup_incoming_varargs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
5408 tree type, int *pretend_size ATTRIBUTE_UNUSED,
5411 CUMULATIVE_ARGS next_cum;
5412 int reg_size = TARGET_32BIT ? 4 : 8;
5413 rtx save_area = NULL_RTX, mem;
5414 int first_reg_offset, set;
5416 /* Skip the last named argument. */
5418 function_arg_advance (&next_cum, mode, type, 1, 0);
5420 if (DEFAULT_ABI == ABI_V4)
5422 first_reg_offset = next_cum.sysv_gregno - GP_ARG_MIN_REG;
5426 int gpr_reg_num = 0, gpr_size = 0, fpr_size = 0;
5427 HOST_WIDE_INT offset = 0;
5429 /* Try to optimize the size of the varargs save area.
5430 The ABI requires that ap.reg_save_area is doubleword
5431 aligned, but we don't need to allocate space for all
5432 the bytes, only those to which we actually will save
5434 if (cfun->va_list_gpr_size && first_reg_offset < GP_ARG_NUM_REG)
5435 gpr_reg_num = GP_ARG_NUM_REG - first_reg_offset;
5436 if (TARGET_HARD_FLOAT && TARGET_FPRS
5437 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5438 && cfun->va_list_fpr_size)
5441 fpr_size = (next_cum.fregno - FP_ARG_MIN_REG)
5442 * UNITS_PER_FP_WORD;
5443 if (cfun->va_list_fpr_size
5444 < FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5445 fpr_size += cfun->va_list_fpr_size * UNITS_PER_FP_WORD;
5447 fpr_size += (FP_ARG_V4_MAX_REG + 1 - next_cum.fregno)
5448 * UNITS_PER_FP_WORD;
5452 offset = -((first_reg_offset * reg_size) & ~7);
5453 if (!fpr_size && gpr_reg_num > cfun->va_list_gpr_size)
5455 gpr_reg_num = cfun->va_list_gpr_size;
5456 if (reg_size == 4 && (first_reg_offset & 1))
5459 gpr_size = (gpr_reg_num * reg_size + 7) & ~7;
5462 offset = - (int) (next_cum.fregno - FP_ARG_MIN_REG)
5464 - (int) (GP_ARG_NUM_REG * reg_size);
5466 if (gpr_size + fpr_size)
5469 = assign_stack_local (BLKmode, gpr_size + fpr_size, 64);
5470 gcc_assert (GET_CODE (reg_save_area) == MEM);
5471 reg_save_area = XEXP (reg_save_area, 0);
5472 if (GET_CODE (reg_save_area) == PLUS)
5474 gcc_assert (XEXP (reg_save_area, 0)
5475 == virtual_stack_vars_rtx);
5476 gcc_assert (GET_CODE (XEXP (reg_save_area, 1)) == CONST_INT);
5477 offset += INTVAL (XEXP (reg_save_area, 1));
5480 gcc_assert (reg_save_area == virtual_stack_vars_rtx);
5483 cfun->machine->varargs_save_offset = offset;
5484 save_area = plus_constant (virtual_stack_vars_rtx, offset);
5489 first_reg_offset = next_cum.words;
5490 save_area = virtual_incoming_args_rtx;
5492 if (targetm.calls.must_pass_in_stack (mode, type))
5493 first_reg_offset += rs6000_arg_size (TYPE_MODE (type), type);
5496 set = get_varargs_alias_set ();
5497 if (! no_rtl && first_reg_offset < GP_ARG_NUM_REG
5498 && cfun->va_list_gpr_size)
5500 int nregs = GP_ARG_NUM_REG - first_reg_offset;
5502 if (va_list_gpr_counter_field)
5504 /* V4 va_list_gpr_size counts number of registers needed. */
5505 if (nregs > cfun->va_list_gpr_size)
5506 nregs = cfun->va_list_gpr_size;
5510 /* char * va_list instead counts number of bytes needed. */
5511 if (nregs > cfun->va_list_gpr_size / reg_size)
5512 nregs = cfun->va_list_gpr_size / reg_size;
5515 mem = gen_rtx_MEM (BLKmode,
5516 plus_constant (save_area,
5517 first_reg_offset * reg_size)),
5518 set_mem_alias_set (mem, set);
5519 set_mem_align (mem, BITS_PER_WORD);
5521 rs6000_move_block_from_reg (GP_ARG_MIN_REG + first_reg_offset, mem,
5525 /* Save FP registers if needed. */
5526 if (DEFAULT_ABI == ABI_V4
5527 && TARGET_HARD_FLOAT && TARGET_FPRS
5529 && next_cum.fregno <= FP_ARG_V4_MAX_REG
5530 && cfun->va_list_fpr_size)
5532 int fregno = next_cum.fregno, nregs;
5533 rtx cr1 = gen_rtx_REG (CCmode, CR1_REGNO);
5534 rtx lab = gen_label_rtx ();
5535 int off = (GP_ARG_NUM_REG * reg_size) + ((fregno - FP_ARG_MIN_REG)
5536 * UNITS_PER_FP_WORD);
5539 (gen_rtx_SET (VOIDmode,
5541 gen_rtx_IF_THEN_ELSE (VOIDmode,
5542 gen_rtx_NE (VOIDmode, cr1,
5544 gen_rtx_LABEL_REF (VOIDmode, lab),
5548 fregno <= FP_ARG_V4_MAX_REG && nregs < cfun->va_list_fpr_size;
5549 fregno++, off += UNITS_PER_FP_WORD, nregs++)
5551 mem = gen_rtx_MEM (DFmode, plus_constant (save_area, off));
5552 set_mem_alias_set (mem, set);
5553 set_mem_align (mem, GET_MODE_ALIGNMENT (DFmode));
5554 emit_move_insn (mem, gen_rtx_REG (DFmode, fregno));
5561 /* Create the va_list data type. */
5564 rs6000_build_builtin_va_list (void)
5566 tree f_gpr, f_fpr, f_res, f_ovf, f_sav, record, type_decl;
5568 /* For AIX, prefer 'char *' because that's what the system
5569 header files like. */
5570 if (DEFAULT_ABI != ABI_V4)
5571 return build_pointer_type (char_type_node);
5573 record = (*lang_hooks.types.make_type) (RECORD_TYPE);
5574 type_decl = build_decl (TYPE_DECL, get_identifier ("__va_list_tag"), record);
5576 f_gpr = build_decl (FIELD_DECL, get_identifier ("gpr"),
5577 unsigned_char_type_node);
5578 f_fpr = build_decl (FIELD_DECL, get_identifier ("fpr"),
5579 unsigned_char_type_node);
5580 /* Give the two bytes of padding a name, so that -Wpadded won't warn on
5582 f_res = build_decl (FIELD_DECL, get_identifier ("reserved"),
5583 short_unsigned_type_node);
5584 f_ovf = build_decl (FIELD_DECL, get_identifier ("overflow_arg_area"),
5586 f_sav = build_decl (FIELD_DECL, get_identifier ("reg_save_area"),
5589 va_list_gpr_counter_field = f_gpr;
5590 va_list_fpr_counter_field = f_fpr;
5592 DECL_FIELD_CONTEXT (f_gpr) = record;
5593 DECL_FIELD_CONTEXT (f_fpr) = record;
5594 DECL_FIELD_CONTEXT (f_res) = record;
5595 DECL_FIELD_CONTEXT (f_ovf) = record;
5596 DECL_FIELD_CONTEXT (f_sav) = record;
5598 TREE_CHAIN (record) = type_decl;
5599 TYPE_NAME (record) = type_decl;
5600 TYPE_FIELDS (record) = f_gpr;
5601 TREE_CHAIN (f_gpr) = f_fpr;
5602 TREE_CHAIN (f_fpr) = f_res;
5603 TREE_CHAIN (f_res) = f_ovf;
5604 TREE_CHAIN (f_ovf) = f_sav;
5606 layout_type (record);
5608 /* The correct type is an array type of one element. */
5609 return build_array_type (record, build_index_type (size_zero_node));
5612 /* Implement va_start. */
5615 rs6000_va_start (tree valist, rtx nextarg)
5617 HOST_WIDE_INT words, n_gpr, n_fpr;
5618 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5619 tree gpr, fpr, ovf, sav, t;
5621 /* Only SVR4 needs something special. */
5622 if (DEFAULT_ABI != ABI_V4)
5624 std_expand_builtin_va_start (valist, nextarg);
5628 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5629 f_fpr = TREE_CHAIN (f_gpr);
5630 f_res = TREE_CHAIN (f_fpr);
5631 f_ovf = TREE_CHAIN (f_res);
5632 f_sav = TREE_CHAIN (f_ovf);
5634 valist = build_va_arg_indirect_ref (valist);
5635 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5636 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5637 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5638 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5640 /* Count number of gp and fp argument registers used. */
5641 words = current_function_args_info.words;
5642 n_gpr = MIN (current_function_args_info.sysv_gregno - GP_ARG_MIN_REG,
5644 n_fpr = MIN (current_function_args_info.fregno - FP_ARG_MIN_REG,
5647 if (TARGET_DEBUG_ARG)
5648 fprintf (stderr, "va_start: words = "HOST_WIDE_INT_PRINT_DEC", n_gpr = "
5649 HOST_WIDE_INT_PRINT_DEC", n_fpr = "HOST_WIDE_INT_PRINT_DEC"\n",
5650 words, n_gpr, n_fpr);
5652 if (cfun->va_list_gpr_size)
5654 t = build (MODIFY_EXPR, TREE_TYPE (gpr), gpr,
5655 build_int_cst (NULL_TREE, n_gpr));
5656 TREE_SIDE_EFFECTS (t) = 1;
5657 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5660 if (cfun->va_list_fpr_size)
5662 t = build (MODIFY_EXPR, TREE_TYPE (fpr), fpr,
5663 build_int_cst (NULL_TREE, n_fpr));
5664 TREE_SIDE_EFFECTS (t) = 1;
5665 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5668 /* Find the overflow area. */
5669 t = make_tree (TREE_TYPE (ovf), virtual_incoming_args_rtx);
5671 t = build (PLUS_EXPR, TREE_TYPE (ovf), t,
5672 build_int_cst (NULL_TREE, words * UNITS_PER_WORD));
5673 t = build (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5674 TREE_SIDE_EFFECTS (t) = 1;
5675 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5677 /* If there were no va_arg invocations, don't set up the register
5679 if (!cfun->va_list_gpr_size
5680 && !cfun->va_list_fpr_size
5681 && n_gpr < GP_ARG_NUM_REG
5682 && n_fpr < FP_ARG_V4_MAX_REG)
5685 /* Find the register save area. */
5686 t = make_tree (TREE_TYPE (sav), virtual_stack_vars_rtx);
5687 if (cfun->machine->varargs_save_offset)
5688 t = build (PLUS_EXPR, TREE_TYPE (sav), t,
5689 build_int_cst (NULL_TREE, cfun->machine->varargs_save_offset));
5690 t = build (MODIFY_EXPR, TREE_TYPE (sav), sav, t);
5691 TREE_SIDE_EFFECTS (t) = 1;
5692 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5695 /* Implement va_arg. */
5698 rs6000_gimplify_va_arg (tree valist, tree type, tree *pre_p, tree *post_p)
5700 tree f_gpr, f_fpr, f_res, f_ovf, f_sav;
5701 tree gpr, fpr, ovf, sav, reg, t, u;
5702 int size, rsize, n_reg, sav_ofs, sav_scale;
5703 tree lab_false, lab_over, addr;
5705 tree ptrtype = build_pointer_type (type);
5707 if (pass_by_reference (NULL, TYPE_MODE (type), type, false))
5709 t = rs6000_gimplify_va_arg (valist, ptrtype, pre_p, post_p);
5710 return build_va_arg_indirect_ref (t);
5713 if (DEFAULT_ABI != ABI_V4)
5715 if (targetm.calls.split_complex_arg && TREE_CODE (type) == COMPLEX_TYPE)
5717 tree elem_type = TREE_TYPE (type);
5718 enum machine_mode elem_mode = TYPE_MODE (elem_type);
5719 int elem_size = GET_MODE_SIZE (elem_mode);
5721 if (elem_size < UNITS_PER_WORD)
5723 tree real_part, imag_part;
5724 tree post = NULL_TREE;
5726 real_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5728 /* Copy the value into a temporary, lest the formal temporary
5729 be reused out from under us. */
5730 real_part = get_initialized_tmp_var (real_part, pre_p, &post);
5731 append_to_statement_list (post, pre_p);
5733 imag_part = rs6000_gimplify_va_arg (valist, elem_type, pre_p,
5736 return build (COMPLEX_EXPR, type, real_part, imag_part);
5740 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5743 f_gpr = TYPE_FIELDS (TREE_TYPE (va_list_type_node));
5744 f_fpr = TREE_CHAIN (f_gpr);
5745 f_res = TREE_CHAIN (f_fpr);
5746 f_ovf = TREE_CHAIN (f_res);
5747 f_sav = TREE_CHAIN (f_ovf);
5749 valist = build_va_arg_indirect_ref (valist);
5750 gpr = build (COMPONENT_REF, TREE_TYPE (f_gpr), valist, f_gpr, NULL_TREE);
5751 fpr = build (COMPONENT_REF, TREE_TYPE (f_fpr), valist, f_fpr, NULL_TREE);
5752 ovf = build (COMPONENT_REF, TREE_TYPE (f_ovf), valist, f_ovf, NULL_TREE);
5753 sav = build (COMPONENT_REF, TREE_TYPE (f_sav), valist, f_sav, NULL_TREE);
5755 size = int_size_in_bytes (type);
5756 rsize = (size + 3) / 4;
5759 if (TARGET_HARD_FLOAT && TARGET_FPRS
5760 && (TYPE_MODE (type) == SFmode || TYPE_MODE (type) == DFmode))
5762 /* FP args go in FP registers, if present. */
5767 if (TYPE_MODE (type) == DFmode)
5772 /* Otherwise into GP registers. */
5781 /* Pull the value out of the saved registers.... */
5784 addr = create_tmp_var (ptr_type_node, "addr");
5785 DECL_POINTER_ALIAS_SET (addr) = get_varargs_alias_set ();
5787 /* AltiVec vectors never go in registers when -mabi=altivec. */
5788 if (TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (TYPE_MODE (type)))
5792 lab_false = create_artificial_label ();
5793 lab_over = create_artificial_label ();
5795 /* Long long and SPE vectors are aligned in the registers.
5796 As are any other 2 gpr item such as complex int due to a
5797 historical mistake. */
5801 u = build2 (BIT_AND_EXPR, TREE_TYPE (reg), reg,
5802 size_int (n_reg - 1));
5803 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, u);
5806 t = fold_convert (TREE_TYPE (reg), size_int (8 - n_reg + 1));
5807 t = build2 (GE_EXPR, boolean_type_node, u, t);
5808 u = build1 (GOTO_EXPR, void_type_node, lab_false);
5809 t = build3 (COND_EXPR, void_type_node, t, u, NULL_TREE);
5810 gimplify_and_add (t, pre_p);
5814 t = build2 (PLUS_EXPR, ptr_type_node, sav, size_int (sav_ofs));
5816 u = build2 (POSTINCREMENT_EXPR, TREE_TYPE (reg), reg, size_int (n_reg));
5817 u = build1 (CONVERT_EXPR, integer_type_node, u);
5818 u = build2 (MULT_EXPR, integer_type_node, u, size_int (sav_scale));
5819 t = build2 (PLUS_EXPR, ptr_type_node, t, u);
5821 t = build2 (MODIFY_EXPR, void_type_node, addr, t);
5822 gimplify_and_add (t, pre_p);
5824 t = build1 (GOTO_EXPR, void_type_node, lab_over);
5825 gimplify_and_add (t, pre_p);
5827 t = build1 (LABEL_EXPR, void_type_node, lab_false);
5828 append_to_statement_list (t, pre_p);
5832 /* Ensure that we don't find any more args in regs.
5833 Alignment has taken care of the n_reg == 2 case. */
5834 t = build (MODIFY_EXPR, TREE_TYPE (reg), reg, size_int (8));
5835 gimplify_and_add (t, pre_p);
5839 /* ... otherwise out of the overflow area. */
5841 /* Care for on-stack alignment if needed. */
5845 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (align - 1));
5846 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t,
5847 build_int_cst (NULL_TREE, -align));
5849 gimplify_expr (&t, pre_p, NULL, is_gimple_val, fb_rvalue);
5851 u = build2 (MODIFY_EXPR, void_type_node, addr, t);
5852 gimplify_and_add (u, pre_p);
5854 t = build2 (PLUS_EXPR, TREE_TYPE (t), t, size_int (size));
5855 t = build2 (MODIFY_EXPR, TREE_TYPE (ovf), ovf, t);
5856 gimplify_and_add (t, pre_p);
5860 t = build1 (LABEL_EXPR, void_type_node, lab_over);
5861 append_to_statement_list (t, pre_p);
5864 addr = fold_convert (ptrtype, addr);
5865 return build_va_arg_indirect_ref (addr);
5871 def_builtin (int mask, const char *name, tree type, int code)
5873 if (mask & target_flags)
5875 if (rs6000_builtin_decls[code])
5878 rs6000_builtin_decls[code] =
5879 lang_hooks.builtin_function (name, type, code, BUILT_IN_MD,
5884 /* Simple ternary operations: VECd = foo (VECa, VECb, VECc). */
5886 static const struct builtin_description bdesc_3arg[] =
5888 { MASK_ALTIVEC, CODE_FOR_altivec_vmaddfp, "__builtin_altivec_vmaddfp", ALTIVEC_BUILTIN_VMADDFP },
5889 { MASK_ALTIVEC, CODE_FOR_altivec_vmhaddshs, "__builtin_altivec_vmhaddshs", ALTIVEC_BUILTIN_VMHADDSHS },
5890 { MASK_ALTIVEC, CODE_FOR_altivec_vmhraddshs, "__builtin_altivec_vmhraddshs", ALTIVEC_BUILTIN_VMHRADDSHS },
5891 { MASK_ALTIVEC, CODE_FOR_altivec_vmladduhm, "__builtin_altivec_vmladduhm", ALTIVEC_BUILTIN_VMLADDUHM},
5892 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumubm, "__builtin_altivec_vmsumubm", ALTIVEC_BUILTIN_VMSUMUBM },
5893 { MASK_ALTIVEC, CODE_FOR_altivec_vmsummbm, "__builtin_altivec_vmsummbm", ALTIVEC_BUILTIN_VMSUMMBM },
5894 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhm, "__builtin_altivec_vmsumuhm", ALTIVEC_BUILTIN_VMSUMUHM },
5895 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshm, "__builtin_altivec_vmsumshm", ALTIVEC_BUILTIN_VMSUMSHM },
5896 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumuhs, "__builtin_altivec_vmsumuhs", ALTIVEC_BUILTIN_VMSUMUHS },
5897 { MASK_ALTIVEC, CODE_FOR_altivec_vmsumshs, "__builtin_altivec_vmsumshs", ALTIVEC_BUILTIN_VMSUMSHS },
5898 { MASK_ALTIVEC, CODE_FOR_altivec_vnmsubfp, "__builtin_altivec_vnmsubfp", ALTIVEC_BUILTIN_VNMSUBFP },
5899 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4sf, "__builtin_altivec_vperm_4sf", ALTIVEC_BUILTIN_VPERM_4SF },
5900 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v4si, "__builtin_altivec_vperm_4si", ALTIVEC_BUILTIN_VPERM_4SI },
5901 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v8hi, "__builtin_altivec_vperm_8hi", ALTIVEC_BUILTIN_VPERM_8HI },
5902 { MASK_ALTIVEC, CODE_FOR_altivec_vperm_v16qi, "__builtin_altivec_vperm_16qi", ALTIVEC_BUILTIN_VPERM_16QI },
5903 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4sf, "__builtin_altivec_vsel_4sf", ALTIVEC_BUILTIN_VSEL_4SF },
5904 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v4si, "__builtin_altivec_vsel_4si", ALTIVEC_BUILTIN_VSEL_4SI },
5905 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v8hi, "__builtin_altivec_vsel_8hi", ALTIVEC_BUILTIN_VSEL_8HI },
5906 { MASK_ALTIVEC, CODE_FOR_altivec_vsel_v16qi, "__builtin_altivec_vsel_16qi", ALTIVEC_BUILTIN_VSEL_16QI },
5907 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v16qi, "__builtin_altivec_vsldoi_16qi", ALTIVEC_BUILTIN_VSLDOI_16QI },
5908 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v8hi, "__builtin_altivec_vsldoi_8hi", ALTIVEC_BUILTIN_VSLDOI_8HI },
5909 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4si, "__builtin_altivec_vsldoi_4si", ALTIVEC_BUILTIN_VSLDOI_4SI },
5910 { MASK_ALTIVEC, CODE_FOR_altivec_vsldoi_v4sf, "__builtin_altivec_vsldoi_4sf", ALTIVEC_BUILTIN_VSLDOI_4SF },
5912 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madd", ALTIVEC_BUILTIN_VEC_MADD },
5913 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_madds", ALTIVEC_BUILTIN_VEC_MADDS },
5914 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mladd", ALTIVEC_BUILTIN_VEC_MLADD },
5915 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mradds", ALTIVEC_BUILTIN_VEC_MRADDS },
5916 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msum", ALTIVEC_BUILTIN_VEC_MSUM },
5917 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshm", ALTIVEC_BUILTIN_VEC_VMSUMSHM },
5918 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhm", ALTIVEC_BUILTIN_VEC_VMSUMUHM },
5919 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsummbm", ALTIVEC_BUILTIN_VEC_VMSUMMBM },
5920 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumubm", ALTIVEC_BUILTIN_VEC_VMSUMUBM },
5921 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_msums", ALTIVEC_BUILTIN_VEC_MSUMS },
5922 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumshs", ALTIVEC_BUILTIN_VEC_VMSUMSHS },
5923 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmsumuhs", ALTIVEC_BUILTIN_VEC_VMSUMUHS },
5924 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nmsub", ALTIVEC_BUILTIN_VEC_NMSUB },
5925 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_perm", ALTIVEC_BUILTIN_VEC_PERM },
5926 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sel", ALTIVEC_BUILTIN_VEC_SEL },
5929 /* DST operations: void foo (void *, const int, const char). */
5931 static const struct builtin_description bdesc_dst[] =
5933 { MASK_ALTIVEC, CODE_FOR_altivec_dst, "__builtin_altivec_dst", ALTIVEC_BUILTIN_DST },
5934 { MASK_ALTIVEC, CODE_FOR_altivec_dstt, "__builtin_altivec_dstt", ALTIVEC_BUILTIN_DSTT },
5935 { MASK_ALTIVEC, CODE_FOR_altivec_dstst, "__builtin_altivec_dstst", ALTIVEC_BUILTIN_DSTST },
5936 { MASK_ALTIVEC, CODE_FOR_altivec_dststt, "__builtin_altivec_dststt", ALTIVEC_BUILTIN_DSTSTT },
5938 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dst", ALTIVEC_BUILTIN_VEC_DST },
5939 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstt", ALTIVEC_BUILTIN_VEC_DSTT },
5940 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dstst", ALTIVEC_BUILTIN_VEC_DSTST },
5941 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_dststt", ALTIVEC_BUILTIN_VEC_DSTSTT }
5944 /* Simple binary operations: VECc = foo (VECa, VECb). */
5946 static struct builtin_description bdesc_2arg[] =
5948 { MASK_ALTIVEC, CODE_FOR_addv16qi3, "__builtin_altivec_vaddubm", ALTIVEC_BUILTIN_VADDUBM },
5949 { MASK_ALTIVEC, CODE_FOR_addv8hi3, "__builtin_altivec_vadduhm", ALTIVEC_BUILTIN_VADDUHM },
5950 { MASK_ALTIVEC, CODE_FOR_addv4si3, "__builtin_altivec_vadduwm", ALTIVEC_BUILTIN_VADDUWM },
5951 { MASK_ALTIVEC, CODE_FOR_addv4sf3, "__builtin_altivec_vaddfp", ALTIVEC_BUILTIN_VADDFP },
5952 { MASK_ALTIVEC, CODE_FOR_altivec_vaddcuw, "__builtin_altivec_vaddcuw", ALTIVEC_BUILTIN_VADDCUW },
5953 { MASK_ALTIVEC, CODE_FOR_altivec_vaddubs, "__builtin_altivec_vaddubs", ALTIVEC_BUILTIN_VADDUBS },
5954 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsbs, "__builtin_altivec_vaddsbs", ALTIVEC_BUILTIN_VADDSBS },
5955 { MASK_ALTIVEC, CODE_FOR_altivec_vadduhs, "__builtin_altivec_vadduhs", ALTIVEC_BUILTIN_VADDUHS },
5956 { MASK_ALTIVEC, CODE_FOR_altivec_vaddshs, "__builtin_altivec_vaddshs", ALTIVEC_BUILTIN_VADDSHS },
5957 { MASK_ALTIVEC, CODE_FOR_altivec_vadduws, "__builtin_altivec_vadduws", ALTIVEC_BUILTIN_VADDUWS },
5958 { MASK_ALTIVEC, CODE_FOR_altivec_vaddsws, "__builtin_altivec_vaddsws", ALTIVEC_BUILTIN_VADDSWS },
5959 { MASK_ALTIVEC, CODE_FOR_andv4si3, "__builtin_altivec_vand", ALTIVEC_BUILTIN_VAND },
5960 { MASK_ALTIVEC, CODE_FOR_andcv4si3, "__builtin_altivec_vandc", ALTIVEC_BUILTIN_VANDC },
5961 { MASK_ALTIVEC, CODE_FOR_altivec_vavgub, "__builtin_altivec_vavgub", ALTIVEC_BUILTIN_VAVGUB },
5962 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsb, "__builtin_altivec_vavgsb", ALTIVEC_BUILTIN_VAVGSB },
5963 { MASK_ALTIVEC, CODE_FOR_altivec_vavguh, "__builtin_altivec_vavguh", ALTIVEC_BUILTIN_VAVGUH },
5964 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsh, "__builtin_altivec_vavgsh", ALTIVEC_BUILTIN_VAVGSH },
5965 { MASK_ALTIVEC, CODE_FOR_altivec_vavguw, "__builtin_altivec_vavguw", ALTIVEC_BUILTIN_VAVGUW },
5966 { MASK_ALTIVEC, CODE_FOR_altivec_vavgsw, "__builtin_altivec_vavgsw", ALTIVEC_BUILTIN_VAVGSW },
5967 { MASK_ALTIVEC, CODE_FOR_altivec_vcfux, "__builtin_altivec_vcfux", ALTIVEC_BUILTIN_VCFUX },
5968 { MASK_ALTIVEC, CODE_FOR_altivec_vcfsx, "__builtin_altivec_vcfsx", ALTIVEC_BUILTIN_VCFSX },
5969 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpbfp, "__builtin_altivec_vcmpbfp", ALTIVEC_BUILTIN_VCMPBFP },
5970 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequb, "__builtin_altivec_vcmpequb", ALTIVEC_BUILTIN_VCMPEQUB },
5971 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequh, "__builtin_altivec_vcmpequh", ALTIVEC_BUILTIN_VCMPEQUH },
5972 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpequw, "__builtin_altivec_vcmpequw", ALTIVEC_BUILTIN_VCMPEQUW },
5973 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpeqfp, "__builtin_altivec_vcmpeqfp", ALTIVEC_BUILTIN_VCMPEQFP },
5974 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgefp, "__builtin_altivec_vcmpgefp", ALTIVEC_BUILTIN_VCMPGEFP },
5975 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtub, "__builtin_altivec_vcmpgtub", ALTIVEC_BUILTIN_VCMPGTUB },
5976 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsb, "__builtin_altivec_vcmpgtsb", ALTIVEC_BUILTIN_VCMPGTSB },
5977 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuh, "__builtin_altivec_vcmpgtuh", ALTIVEC_BUILTIN_VCMPGTUH },
5978 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsh, "__builtin_altivec_vcmpgtsh", ALTIVEC_BUILTIN_VCMPGTSH },
5979 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtuw, "__builtin_altivec_vcmpgtuw", ALTIVEC_BUILTIN_VCMPGTUW },
5980 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtsw, "__builtin_altivec_vcmpgtsw", ALTIVEC_BUILTIN_VCMPGTSW },
5981 { MASK_ALTIVEC, CODE_FOR_altivec_vcmpgtfp, "__builtin_altivec_vcmpgtfp", ALTIVEC_BUILTIN_VCMPGTFP },
5982 { MASK_ALTIVEC, CODE_FOR_altivec_vctsxs, "__builtin_altivec_vctsxs", ALTIVEC_BUILTIN_VCTSXS },
5983 { MASK_ALTIVEC, CODE_FOR_altivec_vctuxs, "__builtin_altivec_vctuxs", ALTIVEC_BUILTIN_VCTUXS },
5984 { MASK_ALTIVEC, CODE_FOR_umaxv16qi3, "__builtin_altivec_vmaxub", ALTIVEC_BUILTIN_VMAXUB },
5985 { MASK_ALTIVEC, CODE_FOR_smaxv16qi3, "__builtin_altivec_vmaxsb", ALTIVEC_BUILTIN_VMAXSB },
5986 { MASK_ALTIVEC, CODE_FOR_umaxv8hi3, "__builtin_altivec_vmaxuh", ALTIVEC_BUILTIN_VMAXUH },
5987 { MASK_ALTIVEC, CODE_FOR_smaxv8hi3, "__builtin_altivec_vmaxsh", ALTIVEC_BUILTIN_VMAXSH },
5988 { MASK_ALTIVEC, CODE_FOR_umaxv4si3, "__builtin_altivec_vmaxuw", ALTIVEC_BUILTIN_VMAXUW },
5989 { MASK_ALTIVEC, CODE_FOR_smaxv4si3, "__builtin_altivec_vmaxsw", ALTIVEC_BUILTIN_VMAXSW },
5990 { MASK_ALTIVEC, CODE_FOR_smaxv4sf3, "__builtin_altivec_vmaxfp", ALTIVEC_BUILTIN_VMAXFP },
5991 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghb, "__builtin_altivec_vmrghb", ALTIVEC_BUILTIN_VMRGHB },
5992 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghh, "__builtin_altivec_vmrghh", ALTIVEC_BUILTIN_VMRGHH },
5993 { MASK_ALTIVEC, CODE_FOR_altivec_vmrghw, "__builtin_altivec_vmrghw", ALTIVEC_BUILTIN_VMRGHW },
5994 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglb, "__builtin_altivec_vmrglb", ALTIVEC_BUILTIN_VMRGLB },
5995 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglh, "__builtin_altivec_vmrglh", ALTIVEC_BUILTIN_VMRGLH },
5996 { MASK_ALTIVEC, CODE_FOR_altivec_vmrglw, "__builtin_altivec_vmrglw", ALTIVEC_BUILTIN_VMRGLW },
5997 { MASK_ALTIVEC, CODE_FOR_uminv16qi3, "__builtin_altivec_vminub", ALTIVEC_BUILTIN_VMINUB },
5998 { MASK_ALTIVEC, CODE_FOR_sminv16qi3, "__builtin_altivec_vminsb", ALTIVEC_BUILTIN_VMINSB },
5999 { MASK_ALTIVEC, CODE_FOR_uminv8hi3, "__builtin_altivec_vminuh", ALTIVEC_BUILTIN_VMINUH },
6000 { MASK_ALTIVEC, CODE_FOR_sminv8hi3, "__builtin_altivec_vminsh", ALTIVEC_BUILTIN_VMINSH },
6001 { MASK_ALTIVEC, CODE_FOR_uminv4si3, "__builtin_altivec_vminuw", ALTIVEC_BUILTIN_VMINUW },
6002 { MASK_ALTIVEC, CODE_FOR_sminv4si3, "__builtin_altivec_vminsw", ALTIVEC_BUILTIN_VMINSW },
6003 { MASK_ALTIVEC, CODE_FOR_sminv4sf3, "__builtin_altivec_vminfp", ALTIVEC_BUILTIN_VMINFP },
6004 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleub, "__builtin_altivec_vmuleub", ALTIVEC_BUILTIN_VMULEUB },
6005 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesb, "__builtin_altivec_vmulesb", ALTIVEC_BUILTIN_VMULESB },
6006 { MASK_ALTIVEC, CODE_FOR_altivec_vmuleuh, "__builtin_altivec_vmuleuh", ALTIVEC_BUILTIN_VMULEUH },
6007 { MASK_ALTIVEC, CODE_FOR_altivec_vmulesh, "__builtin_altivec_vmulesh", ALTIVEC_BUILTIN_VMULESH },
6008 { MASK_ALTIVEC, CODE_FOR_altivec_vmuloub, "__builtin_altivec_vmuloub", ALTIVEC_BUILTIN_VMULOUB },
6009 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosb, "__builtin_altivec_vmulosb", ALTIVEC_BUILTIN_VMULOSB },
6010 { MASK_ALTIVEC, CODE_FOR_altivec_vmulouh, "__builtin_altivec_vmulouh", ALTIVEC_BUILTIN_VMULOUH },
6011 { MASK_ALTIVEC, CODE_FOR_altivec_vmulosh, "__builtin_altivec_vmulosh", ALTIVEC_BUILTIN_VMULOSH },
6012 { MASK_ALTIVEC, CODE_FOR_altivec_norv4si3, "__builtin_altivec_vnor", ALTIVEC_BUILTIN_VNOR },
6013 { MASK_ALTIVEC, CODE_FOR_iorv4si3, "__builtin_altivec_vor", ALTIVEC_BUILTIN_VOR },
6014 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhum, "__builtin_altivec_vpkuhum", ALTIVEC_BUILTIN_VPKUHUM },
6015 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwum, "__builtin_altivec_vpkuwum", ALTIVEC_BUILTIN_VPKUWUM },
6016 { MASK_ALTIVEC, CODE_FOR_altivec_vpkpx, "__builtin_altivec_vpkpx", ALTIVEC_BUILTIN_VPKPX },
6017 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhss, "__builtin_altivec_vpkuhss", ALTIVEC_BUILTIN_VPKUHSS },
6018 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshss, "__builtin_altivec_vpkshss", ALTIVEC_BUILTIN_VPKSHSS },
6019 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwss, "__builtin_altivec_vpkuwss", ALTIVEC_BUILTIN_VPKUWSS },
6020 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswss, "__builtin_altivec_vpkswss", ALTIVEC_BUILTIN_VPKSWSS },
6021 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuhus, "__builtin_altivec_vpkuhus", ALTIVEC_BUILTIN_VPKUHUS },
6022 { MASK_ALTIVEC, CODE_FOR_altivec_vpkshus, "__builtin_altivec_vpkshus", ALTIVEC_BUILTIN_VPKSHUS },
6023 { MASK_ALTIVEC, CODE_FOR_altivec_vpkuwus, "__builtin_altivec_vpkuwus", ALTIVEC_BUILTIN_VPKUWUS },
6024 { MASK_ALTIVEC, CODE_FOR_altivec_vpkswus, "__builtin_altivec_vpkswus", ALTIVEC_BUILTIN_VPKSWUS },
6025 { MASK_ALTIVEC, CODE_FOR_altivec_vrlb, "__builtin_altivec_vrlb", ALTIVEC_BUILTIN_VRLB },
6026 { MASK_ALTIVEC, CODE_FOR_altivec_vrlh, "__builtin_altivec_vrlh", ALTIVEC_BUILTIN_VRLH },
6027 { MASK_ALTIVEC, CODE_FOR_altivec_vrlw, "__builtin_altivec_vrlw", ALTIVEC_BUILTIN_VRLW },
6028 { MASK_ALTIVEC, CODE_FOR_altivec_vslb, "__builtin_altivec_vslb", ALTIVEC_BUILTIN_VSLB },
6029 { MASK_ALTIVEC, CODE_FOR_altivec_vslh, "__builtin_altivec_vslh", ALTIVEC_BUILTIN_VSLH },
6030 { MASK_ALTIVEC, CODE_FOR_altivec_vslw, "__builtin_altivec_vslw", ALTIVEC_BUILTIN_VSLW },
6031 { MASK_ALTIVEC, CODE_FOR_altivec_vsl, "__builtin_altivec_vsl", ALTIVEC_BUILTIN_VSL },
6032 { MASK_ALTIVEC, CODE_FOR_altivec_vslo, "__builtin_altivec_vslo", ALTIVEC_BUILTIN_VSLO },
6033 { MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
6034 { MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
6035 { MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
6036 { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
6037 { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
6038 { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
6039 { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
6040 { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
6041 { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
6042 { MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
6043 { MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
6044 { MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
6045 { MASK_ALTIVEC, CODE_FOR_subv8hi3, "__builtin_altivec_vsubuhm", ALTIVEC_BUILTIN_VSUBUHM },
6046 { MASK_ALTIVEC, CODE_FOR_subv4si3, "__builtin_altivec_vsubuwm", ALTIVEC_BUILTIN_VSUBUWM },
6047 { MASK_ALTIVEC, CODE_FOR_subv4sf3, "__builtin_altivec_vsubfp", ALTIVEC_BUILTIN_VSUBFP },
6048 { MASK_ALTIVEC, CODE_FOR_altivec_vsubcuw, "__builtin_altivec_vsubcuw", ALTIVEC_BUILTIN_VSUBCUW },
6049 { MASK_ALTIVEC, CODE_FOR_altivec_vsububs, "__builtin_altivec_vsububs", ALTIVEC_BUILTIN_VSUBUBS },
6050 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsbs, "__builtin_altivec_vsubsbs", ALTIVEC_BUILTIN_VSUBSBS },
6051 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuhs, "__builtin_altivec_vsubuhs", ALTIVEC_BUILTIN_VSUBUHS },
6052 { MASK_ALTIVEC, CODE_FOR_altivec_vsubshs, "__builtin_altivec_vsubshs", ALTIVEC_BUILTIN_VSUBSHS },
6053 { MASK_ALTIVEC, CODE_FOR_altivec_vsubuws, "__builtin_altivec_vsubuws", ALTIVEC_BUILTIN_VSUBUWS },
6054 { MASK_ALTIVEC, CODE_FOR_altivec_vsubsws, "__builtin_altivec_vsubsws", ALTIVEC_BUILTIN_VSUBSWS },
6055 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4ubs, "__builtin_altivec_vsum4ubs", ALTIVEC_BUILTIN_VSUM4UBS },
6056 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4sbs, "__builtin_altivec_vsum4sbs", ALTIVEC_BUILTIN_VSUM4SBS },
6057 { MASK_ALTIVEC, CODE_FOR_altivec_vsum4shs, "__builtin_altivec_vsum4shs", ALTIVEC_BUILTIN_VSUM4SHS },
6058 { MASK_ALTIVEC, CODE_FOR_altivec_vsum2sws, "__builtin_altivec_vsum2sws", ALTIVEC_BUILTIN_VSUM2SWS },
6059 { MASK_ALTIVEC, CODE_FOR_altivec_vsumsws, "__builtin_altivec_vsumsws", ALTIVEC_BUILTIN_VSUMSWS },
6060 { MASK_ALTIVEC, CODE_FOR_xorv4si3, "__builtin_altivec_vxor", ALTIVEC_BUILTIN_VXOR },
6062 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_add", ALTIVEC_BUILTIN_VEC_ADD },
6063 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddfp", ALTIVEC_BUILTIN_VEC_VADDFP },
6064 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduwm", ALTIVEC_BUILTIN_VEC_VADDUWM },
6065 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhm", ALTIVEC_BUILTIN_VEC_VADDUHM },
6066 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubm", ALTIVEC_BUILTIN_VEC_VADDUBM },
6067 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_addc", ALTIVEC_BUILTIN_VEC_ADDC },
6068 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_adds", ALTIVEC_BUILTIN_VEC_ADDS },
6069 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsws", ALTIVEC_BUILTIN_VEC_VADDSWS },
6070 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduws", ALTIVEC_BUILTIN_VEC_VADDUWS },
6071 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddshs", ALTIVEC_BUILTIN_VEC_VADDSHS },
6072 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vadduhs", ALTIVEC_BUILTIN_VEC_VADDUHS },
6073 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddsbs", ALTIVEC_BUILTIN_VEC_VADDSBS },
6074 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vaddubs", ALTIVEC_BUILTIN_VEC_VADDUBS },
6075 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_and", ALTIVEC_BUILTIN_VEC_AND },
6076 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_andc", ALTIVEC_BUILTIN_VEC_ANDC },
6077 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_avg", ALTIVEC_BUILTIN_VEC_AVG },
6078 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsw", ALTIVEC_BUILTIN_VEC_VAVGSW },
6079 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguw", ALTIVEC_BUILTIN_VEC_VAVGUW },
6080 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsh", ALTIVEC_BUILTIN_VEC_VAVGSH },
6081 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavguh", ALTIVEC_BUILTIN_VEC_VAVGUH },
6082 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgsb", ALTIVEC_BUILTIN_VEC_VAVGSB },
6083 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vavgub", ALTIVEC_BUILTIN_VEC_VAVGUB },
6084 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpb", ALTIVEC_BUILTIN_VEC_CMPB },
6085 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpeq", ALTIVEC_BUILTIN_VEC_CMPEQ },
6086 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpeqfp", ALTIVEC_BUILTIN_VEC_VCMPEQFP },
6087 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequw", ALTIVEC_BUILTIN_VEC_VCMPEQUW },
6088 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequh", ALTIVEC_BUILTIN_VEC_VCMPEQUH },
6089 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpequb", ALTIVEC_BUILTIN_VEC_VCMPEQUB },
6090 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpge", ALTIVEC_BUILTIN_VEC_CMPGE },
6091 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmpgt", ALTIVEC_BUILTIN_VEC_CMPGT },
6092 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtfp", ALTIVEC_BUILTIN_VEC_VCMPGTFP },
6093 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsw", ALTIVEC_BUILTIN_VEC_VCMPGTSW },
6094 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuw", ALTIVEC_BUILTIN_VEC_VCMPGTUW },
6095 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsh", ALTIVEC_BUILTIN_VEC_VCMPGTSH },
6096 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtuh", ALTIVEC_BUILTIN_VEC_VCMPGTUH },
6097 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtsb", ALTIVEC_BUILTIN_VEC_VCMPGTSB },
6098 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vcmpgtub", ALTIVEC_BUILTIN_VEC_VCMPGTUB },
6099 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmple", ALTIVEC_BUILTIN_VEC_CMPLE },
6100 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_cmplt", ALTIVEC_BUILTIN_VEC_CMPLT },
6101 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_max", ALTIVEC_BUILTIN_VEC_MAX },
6102 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxfp", ALTIVEC_BUILTIN_VEC_VMAXFP },
6103 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsw", ALTIVEC_BUILTIN_VEC_VMAXSW },
6104 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuw", ALTIVEC_BUILTIN_VEC_VMAXUW },
6105 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsh", ALTIVEC_BUILTIN_VEC_VMAXSH },
6106 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxuh", ALTIVEC_BUILTIN_VEC_VMAXUH },
6107 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxsb", ALTIVEC_BUILTIN_VEC_VMAXSB },
6108 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmaxub", ALTIVEC_BUILTIN_VEC_VMAXUB },
6109 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergeh", ALTIVEC_BUILTIN_VEC_MERGEH },
6110 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghw", ALTIVEC_BUILTIN_VEC_VMRGHW },
6111 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghh", ALTIVEC_BUILTIN_VEC_VMRGHH },
6112 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrghb", ALTIVEC_BUILTIN_VEC_VMRGHB },
6113 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mergel", ALTIVEC_BUILTIN_VEC_MERGEL },
6114 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglw", ALTIVEC_BUILTIN_VEC_VMRGLW },
6115 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglh", ALTIVEC_BUILTIN_VEC_VMRGLH },
6116 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmrglb", ALTIVEC_BUILTIN_VEC_VMRGLB },
6117 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_min", ALTIVEC_BUILTIN_VEC_MIN },
6118 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminfp", ALTIVEC_BUILTIN_VEC_VMINFP },
6119 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsw", ALTIVEC_BUILTIN_VEC_VMINSW },
6120 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuw", ALTIVEC_BUILTIN_VEC_VMINUW },
6121 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsh", ALTIVEC_BUILTIN_VEC_VMINSH },
6122 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminuh", ALTIVEC_BUILTIN_VEC_VMINUH },
6123 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminsb", ALTIVEC_BUILTIN_VEC_VMINSB },
6124 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vminub", ALTIVEC_BUILTIN_VEC_VMINUB },
6125 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mule", ALTIVEC_BUILTIN_VEC_MULE },
6126 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleub", ALTIVEC_BUILTIN_VEC_VMULEUB },
6127 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesb", ALTIVEC_BUILTIN_VEC_VMULESB },
6128 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuleuh", ALTIVEC_BUILTIN_VEC_VMULEUH },
6129 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulesh", ALTIVEC_BUILTIN_VEC_VMULESH },
6130 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mulo", ALTIVEC_BUILTIN_VEC_MULO },
6131 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosh", ALTIVEC_BUILTIN_VEC_VMULOSH },
6132 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulouh", ALTIVEC_BUILTIN_VEC_VMULOUH },
6133 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmulosb", ALTIVEC_BUILTIN_VEC_VMULOSB },
6134 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vmuloub", ALTIVEC_BUILTIN_VEC_VMULOUB },
6135 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_nor", ALTIVEC_BUILTIN_VEC_NOR },
6136 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_or", ALTIVEC_BUILTIN_VEC_OR },
6137 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_pack", ALTIVEC_BUILTIN_VEC_PACK },
6138 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwum", ALTIVEC_BUILTIN_VEC_VPKUWUM },
6139 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhum", ALTIVEC_BUILTIN_VEC_VPKUHUM },
6140 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packpx", ALTIVEC_BUILTIN_VEC_PACKPX },
6141 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packs", ALTIVEC_BUILTIN_VEC_PACKS },
6142 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswss", ALTIVEC_BUILTIN_VEC_VPKSWSS },
6143 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuwus", ALTIVEC_BUILTIN_VEC_VPKUWUS },
6144 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshss", ALTIVEC_BUILTIN_VEC_VPKSHSS },
6145 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkuhus", ALTIVEC_BUILTIN_VEC_VPKUHUS },
6146 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_packsu", ALTIVEC_BUILTIN_VEC_PACKSU },
6147 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkswus", ALTIVEC_BUILTIN_VEC_VPKSWUS },
6148 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vpkshus", ALTIVEC_BUILTIN_VEC_VPKSHUS },
6149 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rl", ALTIVEC_BUILTIN_VEC_RL },
6150 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlw", ALTIVEC_BUILTIN_VEC_VRLW },
6151 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlh", ALTIVEC_BUILTIN_VEC_VRLH },
6152 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vrlb", ALTIVEC_BUILTIN_VEC_VRLB },
6153 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sl", ALTIVEC_BUILTIN_VEC_SL },
6154 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslw", ALTIVEC_BUILTIN_VEC_VSLW },
6155 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslh", ALTIVEC_BUILTIN_VEC_VSLH },
6156 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vslb", ALTIVEC_BUILTIN_VEC_VSLB },
6157 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sll", ALTIVEC_BUILTIN_VEC_SLL },
6158 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_slo", ALTIVEC_BUILTIN_VEC_SLO },
6159 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sr", ALTIVEC_BUILTIN_VEC_SR },
6160 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrw", ALTIVEC_BUILTIN_VEC_VSRW },
6161 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrh", ALTIVEC_BUILTIN_VEC_VSRH },
6162 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrb", ALTIVEC_BUILTIN_VEC_VSRB },
6163 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sra", ALTIVEC_BUILTIN_VEC_SRA },
6164 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsraw", ALTIVEC_BUILTIN_VEC_VSRAW },
6165 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrah", ALTIVEC_BUILTIN_VEC_VSRAH },
6166 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsrab", ALTIVEC_BUILTIN_VEC_VSRAB },
6167 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_srl", ALTIVEC_BUILTIN_VEC_SRL },
6168 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sro", ALTIVEC_BUILTIN_VEC_SRO },
6169 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sub", ALTIVEC_BUILTIN_VEC_SUB },
6170 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubfp", ALTIVEC_BUILTIN_VEC_VSUBFP },
6171 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuwm", ALTIVEC_BUILTIN_VEC_VSUBUWM },
6172 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhm", ALTIVEC_BUILTIN_VEC_VSUBUHM },
6173 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububm", ALTIVEC_BUILTIN_VEC_VSUBUBM },
6174 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subc", ALTIVEC_BUILTIN_VEC_SUBC },
6175 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_subs", ALTIVEC_BUILTIN_VEC_SUBS },
6176 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsws", ALTIVEC_BUILTIN_VEC_VSUBSWS },
6177 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuws", ALTIVEC_BUILTIN_VEC_VSUBUWS },
6178 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubshs", ALTIVEC_BUILTIN_VEC_VSUBSHS },
6179 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubuhs", ALTIVEC_BUILTIN_VEC_VSUBUHS },
6180 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsubsbs", ALTIVEC_BUILTIN_VEC_VSUBSBS },
6181 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsububs", ALTIVEC_BUILTIN_VEC_VSUBUBS },
6182 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum4s", ALTIVEC_BUILTIN_VEC_SUM4S },
6183 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4shs", ALTIVEC_BUILTIN_VEC_VSUM4SHS },
6184 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4sbs", ALTIVEC_BUILTIN_VEC_VSUM4SBS },
6185 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vsum4ubs", ALTIVEC_BUILTIN_VEC_VSUM4UBS },
6186 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sum2s", ALTIVEC_BUILTIN_VEC_SUM2S },
6187 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_sums", ALTIVEC_BUILTIN_VEC_SUMS },
6188 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_xor", ALTIVEC_BUILTIN_VEC_XOR },
6190 /* Place holder, leave as first spe builtin. */
6191 { 0, CODE_FOR_spe_evaddw, "__builtin_spe_evaddw", SPE_BUILTIN_EVADDW },
6192 { 0, CODE_FOR_spe_evand, "__builtin_spe_evand", SPE_BUILTIN_EVAND },
6193 { 0, CODE_FOR_spe_evandc, "__builtin_spe_evandc", SPE_BUILTIN_EVANDC },
6194 { 0, CODE_FOR_spe_evdivws, "__builtin_spe_evdivws", SPE_BUILTIN_EVDIVWS },
6195 { 0, CODE_FOR_spe_evdivwu, "__builtin_spe_evdivwu", SPE_BUILTIN_EVDIVWU },
6196 { 0, CODE_FOR_spe_eveqv, "__builtin_spe_eveqv", SPE_BUILTIN_EVEQV },
6197 { 0, CODE_FOR_spe_evfsadd, "__builtin_spe_evfsadd", SPE_BUILTIN_EVFSADD },
6198 { 0, CODE_FOR_spe_evfsdiv, "__builtin_spe_evfsdiv", SPE_BUILTIN_EVFSDIV },
6199 { 0, CODE_FOR_spe_evfsmul, "__builtin_spe_evfsmul", SPE_BUILTIN_EVFSMUL },
6200 { 0, CODE_FOR_spe_evfssub, "__builtin_spe_evfssub", SPE_BUILTIN_EVFSSUB },
6201 { 0, CODE_FOR_spe_evmergehi, "__builtin_spe_evmergehi", SPE_BUILTIN_EVMERGEHI },
6202 { 0, CODE_FOR_spe_evmergehilo, "__builtin_spe_evmergehilo", SPE_BUILTIN_EVMERGEHILO },
6203 { 0, CODE_FOR_spe_evmergelo, "__builtin_spe_evmergelo", SPE_BUILTIN_EVMERGELO },
6204 { 0, CODE_FOR_spe_evmergelohi, "__builtin_spe_evmergelohi", SPE_BUILTIN_EVMERGELOHI },
6205 { 0, CODE_FOR_spe_evmhegsmfaa, "__builtin_spe_evmhegsmfaa", SPE_BUILTIN_EVMHEGSMFAA },
6206 { 0, CODE_FOR_spe_evmhegsmfan, "__builtin_spe_evmhegsmfan", SPE_BUILTIN_EVMHEGSMFAN },
6207 { 0, CODE_FOR_spe_evmhegsmiaa, "__builtin_spe_evmhegsmiaa", SPE_BUILTIN_EVMHEGSMIAA },
6208 { 0, CODE_FOR_spe_evmhegsmian, "__builtin_spe_evmhegsmian", SPE_BUILTIN_EVMHEGSMIAN },
6209 { 0, CODE_FOR_spe_evmhegumiaa, "__builtin_spe_evmhegumiaa", SPE_BUILTIN_EVMHEGUMIAA },
6210 { 0, CODE_FOR_spe_evmhegumian, "__builtin_spe_evmhegumian", SPE_BUILTIN_EVMHEGUMIAN },
6211 { 0, CODE_FOR_spe_evmhesmf, "__builtin_spe_evmhesmf", SPE_BUILTIN_EVMHESMF },
6212 { 0, CODE_FOR_spe_evmhesmfa, "__builtin_spe_evmhesmfa", SPE_BUILTIN_EVMHESMFA },
6213 { 0, CODE_FOR_spe_evmhesmfaaw, "__builtin_spe_evmhesmfaaw", SPE_BUILTIN_EVMHESMFAAW },
6214 { 0, CODE_FOR_spe_evmhesmfanw, "__builtin_spe_evmhesmfanw", SPE_BUILTIN_EVMHESMFANW },
6215 { 0, CODE_FOR_spe_evmhesmi, "__builtin_spe_evmhesmi", SPE_BUILTIN_EVMHESMI },
6216 { 0, CODE_FOR_spe_evmhesmia, "__builtin_spe_evmhesmia", SPE_BUILTIN_EVMHESMIA },
6217 { 0, CODE_FOR_spe_evmhesmiaaw, "__builtin_spe_evmhesmiaaw", SPE_BUILTIN_EVMHESMIAAW },
6218 { 0, CODE_FOR_spe_evmhesmianw, "__builtin_spe_evmhesmianw", SPE_BUILTIN_EVMHESMIANW },
6219 { 0, CODE_FOR_spe_evmhessf, "__builtin_spe_evmhessf", SPE_BUILTIN_EVMHESSF },
6220 { 0, CODE_FOR_spe_evmhessfa, "__builtin_spe_evmhessfa", SPE_BUILTIN_EVMHESSFA },
6221 { 0, CODE_FOR_spe_evmhessfaaw, "__builtin_spe_evmhessfaaw", SPE_BUILTIN_EVMHESSFAAW },
6222 { 0, CODE_FOR_spe_evmhessfanw, "__builtin_spe_evmhessfanw", SPE_BUILTIN_EVMHESSFANW },
6223 { 0, CODE_FOR_spe_evmhessiaaw, "__builtin_spe_evmhessiaaw", SPE_BUILTIN_EVMHESSIAAW },
6224 { 0, CODE_FOR_spe_evmhessianw, "__builtin_spe_evmhessianw", SPE_BUILTIN_EVMHESSIANW },
6225 { 0, CODE_FOR_spe_evmheumi, "__builtin_spe_evmheumi", SPE_BUILTIN_EVMHEUMI },
6226 { 0, CODE_FOR_spe_evmheumia, "__builtin_spe_evmheumia", SPE_BUILTIN_EVMHEUMIA },
6227 { 0, CODE_FOR_spe_evmheumiaaw, "__builtin_spe_evmheumiaaw", SPE_BUILTIN_EVMHEUMIAAW },
6228 { 0, CODE_FOR_spe_evmheumianw, "__builtin_spe_evmheumianw", SPE_BUILTIN_EVMHEUMIANW },
6229 { 0, CODE_FOR_spe_evmheusiaaw, "__builtin_spe_evmheusiaaw", SPE_BUILTIN_EVMHEUSIAAW },
6230 { 0, CODE_FOR_spe_evmheusianw, "__builtin_spe_evmheusianw", SPE_BUILTIN_EVMHEUSIANW },
6231 { 0, CODE_FOR_spe_evmhogsmfaa, "__builtin_spe_evmhogsmfaa", SPE_BUILTIN_EVMHOGSMFAA },
6232 { 0, CODE_FOR_spe_evmhogsmfan, "__builtin_spe_evmhogsmfan", SPE_BUILTIN_EVMHOGSMFAN },
6233 { 0, CODE_FOR_spe_evmhogsmiaa, "__builtin_spe_evmhogsmiaa", SPE_BUILTIN_EVMHOGSMIAA },
6234 { 0, CODE_FOR_spe_evmhogsmian, "__builtin_spe_evmhogsmian", SPE_BUILTIN_EVMHOGSMIAN },
6235 { 0, CODE_FOR_spe_evmhogumiaa, "__builtin_spe_evmhogumiaa", SPE_BUILTIN_EVMHOGUMIAA },
6236 { 0, CODE_FOR_spe_evmhogumian, "__builtin_spe_evmhogumian", SPE_BUILTIN_EVMHOGUMIAN },
6237 { 0, CODE_FOR_spe_evmhosmf, "__builtin_spe_evmhosmf", SPE_BUILTIN_EVMHOSMF },
6238 { 0, CODE_FOR_spe_evmhosmfa, "__builtin_spe_evmhosmfa", SPE_BUILTIN_EVMHOSMFA },
6239 { 0, CODE_FOR_spe_evmhosmfaaw, "__builtin_spe_evmhosmfaaw", SPE_BUILTIN_EVMHOSMFAAW },
6240 { 0, CODE_FOR_spe_evmhosmfanw, "__builtin_spe_evmhosmfanw", SPE_BUILTIN_EVMHOSMFANW },
6241 { 0, CODE_FOR_spe_evmhosmi, "__builtin_spe_evmhosmi", SPE_BUILTIN_EVMHOSMI },
6242 { 0, CODE_FOR_spe_evmhosmia, "__builtin_spe_evmhosmia", SPE_BUILTIN_EVMHOSMIA },
6243 { 0, CODE_FOR_spe_evmhosmiaaw, "__builtin_spe_evmhosmiaaw", SPE_BUILTIN_EVMHOSMIAAW },
6244 { 0, CODE_FOR_spe_evmhosmianw, "__builtin_spe_evmhosmianw", SPE_BUILTIN_EVMHOSMIANW },
6245 { 0, CODE_FOR_spe_evmhossf, "__builtin_spe_evmhossf", SPE_BUILTIN_EVMHOSSF },
6246 { 0, CODE_FOR_spe_evmhossfa, "__builtin_spe_evmhossfa", SPE_BUILTIN_EVMHOSSFA },
6247 { 0, CODE_FOR_spe_evmhossfaaw, "__builtin_spe_evmhossfaaw", SPE_BUILTIN_EVMHOSSFAAW },
6248 { 0, CODE_FOR_spe_evmhossfanw, "__builtin_spe_evmhossfanw", SPE_BUILTIN_EVMHOSSFANW },
6249 { 0, CODE_FOR_spe_evmhossiaaw, "__builtin_spe_evmhossiaaw", SPE_BUILTIN_EVMHOSSIAAW },
6250 { 0, CODE_FOR_spe_evmhossianw, "__builtin_spe_evmhossianw", SPE_BUILTIN_EVMHOSSIANW },
6251 { 0, CODE_FOR_spe_evmhoumi, "__builtin_spe_evmhoumi", SPE_BUILTIN_EVMHOUMI },
6252 { 0, CODE_FOR_spe_evmhoumia, "__builtin_spe_evmhoumia", SPE_BUILTIN_EVMHOUMIA },
6253 { 0, CODE_FOR_spe_evmhoumiaaw, "__builtin_spe_evmhoumiaaw", SPE_BUILTIN_EVMHOUMIAAW },
6254 { 0, CODE_FOR_spe_evmhoumianw, "__builtin_spe_evmhoumianw", SPE_BUILTIN_EVMHOUMIANW },
6255 { 0, CODE_FOR_spe_evmhousiaaw, "__builtin_spe_evmhousiaaw", SPE_BUILTIN_EVMHOUSIAAW },
6256 { 0, CODE_FOR_spe_evmhousianw, "__builtin_spe_evmhousianw", SPE_BUILTIN_EVMHOUSIANW },
6257 { 0, CODE_FOR_spe_evmwhsmf, "__builtin_spe_evmwhsmf", SPE_BUILTIN_EVMWHSMF },
6258 { 0, CODE_FOR_spe_evmwhsmfa, "__builtin_spe_evmwhsmfa", SPE_BUILTIN_EVMWHSMFA },
6259 { 0, CODE_FOR_spe_evmwhsmi, "__builtin_spe_evmwhsmi", SPE_BUILTIN_EVMWHSMI },
6260 { 0, CODE_FOR_spe_evmwhsmia, "__builtin_spe_evmwhsmia", SPE_BUILTIN_EVMWHSMIA },
6261 { 0, CODE_FOR_spe_evmwhssf, "__builtin_spe_evmwhssf", SPE_BUILTIN_EVMWHSSF },
6262 { 0, CODE_FOR_spe_evmwhssfa, "__builtin_spe_evmwhssfa", SPE_BUILTIN_EVMWHSSFA },
6263 { 0, CODE_FOR_spe_evmwhumi, "__builtin_spe_evmwhumi", SPE_BUILTIN_EVMWHUMI },
6264 { 0, CODE_FOR_spe_evmwhumia, "__builtin_spe_evmwhumia", SPE_BUILTIN_EVMWHUMIA },
6265 { 0, CODE_FOR_spe_evmwlsmiaaw, "__builtin_spe_evmwlsmiaaw", SPE_BUILTIN_EVMWLSMIAAW },
6266 { 0, CODE_FOR_spe_evmwlsmianw, "__builtin_spe_evmwlsmianw", SPE_BUILTIN_EVMWLSMIANW },
6267 { 0, CODE_FOR_spe_evmwlssiaaw, "__builtin_spe_evmwlssiaaw", SPE_BUILTIN_EVMWLSSIAAW },
6268 { 0, CODE_FOR_spe_evmwlssianw, "__builtin_spe_evmwlssianw", SPE_BUILTIN_EVMWLSSIANW },
6269 { 0, CODE_FOR_spe_evmwlumi, "__builtin_spe_evmwlumi", SPE_BUILTIN_EVMWLUMI },
6270 { 0, CODE_FOR_spe_evmwlumia, "__builtin_spe_evmwlumia", SPE_BUILTIN_EVMWLUMIA },
6271 { 0, CODE_FOR_spe_evmwlumiaaw, "__builtin_spe_evmwlumiaaw", SPE_BUILTIN_EVMWLUMIAAW },
6272 { 0, CODE_FOR_spe_evmwlumianw, "__builtin_spe_evmwlumianw", SPE_BUILTIN_EVMWLUMIANW },
6273 { 0, CODE_FOR_spe_evmwlusiaaw, "__builtin_spe_evmwlusiaaw", SPE_BUILTIN_EVMWLUSIAAW },
6274 { 0, CODE_FOR_spe_evmwlusianw, "__builtin_spe_evmwlusianw", SPE_BUILTIN_EVMWLUSIANW },
6275 { 0, CODE_FOR_spe_evmwsmf, "__builtin_spe_evmwsmf", SPE_BUILTIN_EVMWSMF },
6276 { 0, CODE_FOR_spe_evmwsmfa, "__builtin_spe_evmwsmfa", SPE_BUILTIN_EVMWSMFA },
6277 { 0, CODE_FOR_spe_evmwsmfaa, "__builtin_spe_evmwsmfaa", SPE_BUILTIN_EVMWSMFAA },
6278 { 0, CODE_FOR_spe_evmwsmfan, "__builtin_spe_evmwsmfan", SPE_BUILTIN_EVMWSMFAN },
6279 { 0, CODE_FOR_spe_evmwsmi, "__builtin_spe_evmwsmi", SPE_BUILTIN_EVMWSMI },
6280 { 0, CODE_FOR_spe_evmwsmia, "__builtin_spe_evmwsmia", SPE_BUILTIN_EVMWSMIA },
6281 { 0, CODE_FOR_spe_evmwsmiaa, "__builtin_spe_evmwsmiaa", SPE_BUILTIN_EVMWSMIAA },
6282 { 0, CODE_FOR_spe_evmwsmian, "__builtin_spe_evmwsmian", SPE_BUILTIN_EVMWSMIAN },
6283 { 0, CODE_FOR_spe_evmwssf, "__builtin_spe_evmwssf", SPE_BUILTIN_EVMWSSF },
6284 { 0, CODE_FOR_spe_evmwssfa, "__builtin_spe_evmwssfa", SPE_BUILTIN_EVMWSSFA },
6285 { 0, CODE_FOR_spe_evmwssfaa, "__builtin_spe_evmwssfaa", SPE_BUILTIN_EVMWSSFAA },
6286 { 0, CODE_FOR_spe_evmwssfan, "__builtin_spe_evmwssfan", SPE_BUILTIN_EVMWSSFAN },
6287 { 0, CODE_FOR_spe_evmwumi, "__builtin_spe_evmwumi", SPE_BUILTIN_EVMWUMI },
6288 { 0, CODE_FOR_spe_evmwumia, "__builtin_spe_evmwumia", SPE_BUILTIN_EVMWUMIA },
6289 { 0, CODE_FOR_spe_evmwumiaa, "__builtin_spe_evmwumiaa", SPE_BUILTIN_EVMWUMIAA },
6290 { 0, CODE_FOR_spe_evmwumian, "__builtin_spe_evmwumian", SPE_BUILTIN_EVMWUMIAN },
6291 { 0, CODE_FOR_spe_evnand, "__builtin_spe_evnand", SPE_BUILTIN_EVNAND },
6292 { 0, CODE_FOR_spe_evnor, "__builtin_spe_evnor", SPE_BUILTIN_EVNOR },
6293 { 0, CODE_FOR_spe_evor, "__builtin_spe_evor", SPE_BUILTIN_EVOR },
6294 { 0, CODE_FOR_spe_evorc, "__builtin_spe_evorc", SPE_BUILTIN_EVORC },
6295 { 0, CODE_FOR_spe_evrlw, "__builtin_spe_evrlw", SPE_BUILTIN_EVRLW },
6296 { 0, CODE_FOR_spe_evslw, "__builtin_spe_evslw", SPE_BUILTIN_EVSLW },
6297 { 0, CODE_FOR_spe_evsrws, "__builtin_spe_evsrws", SPE_BUILTIN_EVSRWS },
6298 { 0, CODE_FOR_spe_evsrwu, "__builtin_spe_evsrwu", SPE_BUILTIN_EVSRWU },
6299 { 0, CODE_FOR_spe_evsubfw, "__builtin_spe_evsubfw", SPE_BUILTIN_EVSUBFW },
6301 /* SPE binary operations expecting a 5-bit unsigned literal. */
6302 { 0, CODE_FOR_spe_evaddiw, "__builtin_spe_evaddiw", SPE_BUILTIN_EVADDIW },
6304 { 0, CODE_FOR_spe_evrlwi, "__builtin_spe_evrlwi", SPE_BUILTIN_EVRLWI },
6305 { 0, CODE_FOR_spe_evslwi, "__builtin_spe_evslwi", SPE_BUILTIN_EVSLWI },
6306 { 0, CODE_FOR_spe_evsrwis, "__builtin_spe_evsrwis", SPE_BUILTIN_EVSRWIS },
6307 { 0, CODE_FOR_spe_evsrwiu, "__builtin_spe_evsrwiu", SPE_BUILTIN_EVSRWIU },
6308 { 0, CODE_FOR_spe_evsubifw, "__builtin_spe_evsubifw", SPE_BUILTIN_EVSUBIFW },
6309 { 0, CODE_FOR_spe_evmwhssfaa, "__builtin_spe_evmwhssfaa", SPE_BUILTIN_EVMWHSSFAA },
6310 { 0, CODE_FOR_spe_evmwhssmaa, "__builtin_spe_evmwhssmaa", SPE_BUILTIN_EVMWHSSMAA },
6311 { 0, CODE_FOR_spe_evmwhsmfaa, "__builtin_spe_evmwhsmfaa", SPE_BUILTIN_EVMWHSMFAA },
6312 { 0, CODE_FOR_spe_evmwhsmiaa, "__builtin_spe_evmwhsmiaa", SPE_BUILTIN_EVMWHSMIAA },
6313 { 0, CODE_FOR_spe_evmwhusiaa, "__builtin_spe_evmwhusiaa", SPE_BUILTIN_EVMWHUSIAA },
6314 { 0, CODE_FOR_spe_evmwhumiaa, "__builtin_spe_evmwhumiaa", SPE_BUILTIN_EVMWHUMIAA },
6315 { 0, CODE_FOR_spe_evmwhssfan, "__builtin_spe_evmwhssfan", SPE_BUILTIN_EVMWHSSFAN },
6316 { 0, CODE_FOR_spe_evmwhssian, "__builtin_spe_evmwhssian", SPE_BUILTIN_EVMWHSSIAN },
6317 { 0, CODE_FOR_spe_evmwhsmfan, "__builtin_spe_evmwhsmfan", SPE_BUILTIN_EVMWHSMFAN },
6318 { 0, CODE_FOR_spe_evmwhsmian, "__builtin_spe_evmwhsmian", SPE_BUILTIN_EVMWHSMIAN },
6319 { 0, CODE_FOR_spe_evmwhusian, "__builtin_spe_evmwhusian", SPE_BUILTIN_EVMWHUSIAN },
6320 { 0, CODE_FOR_spe_evmwhumian, "__builtin_spe_evmwhumian", SPE_BUILTIN_EVMWHUMIAN },
6321 { 0, CODE_FOR_spe_evmwhgssfaa, "__builtin_spe_evmwhgssfaa", SPE_BUILTIN_EVMWHGSSFAA },
6322 { 0, CODE_FOR_spe_evmwhgsmfaa, "__builtin_spe_evmwhgsmfaa", SPE_BUILTIN_EVMWHGSMFAA },
6323 { 0, CODE_FOR_spe_evmwhgsmiaa, "__builtin_spe_evmwhgsmiaa", SPE_BUILTIN_EVMWHGSMIAA },
6324 { 0, CODE_FOR_spe_evmwhgumiaa, "__builtin_spe_evmwhgumiaa", SPE_BUILTIN_EVMWHGUMIAA },
6325 { 0, CODE_FOR_spe_evmwhgssfan, "__builtin_spe_evmwhgssfan", SPE_BUILTIN_EVMWHGSSFAN },
6326 { 0, CODE_FOR_spe_evmwhgsmfan, "__builtin_spe_evmwhgsmfan", SPE_BUILTIN_EVMWHGSMFAN },
6327 { 0, CODE_FOR_spe_evmwhgsmian, "__builtin_spe_evmwhgsmian", SPE_BUILTIN_EVMWHGSMIAN },
6328 { 0, CODE_FOR_spe_evmwhgumian, "__builtin_spe_evmwhgumian", SPE_BUILTIN_EVMWHGUMIAN },
6329 { 0, CODE_FOR_spe_brinc, "__builtin_spe_brinc", SPE_BUILTIN_BRINC },
6331 /* Place-holder. Leave as last binary SPE builtin. */
6332 { 0, CODE_FOR_xorv2si3, "__builtin_spe_evxor", SPE_BUILTIN_EVXOR }
6335 /* AltiVec predicates. */
6337 struct builtin_description_predicates
6339 const unsigned int mask;
6340 const enum insn_code icode;
6342 const char *const name;
6343 const enum rs6000_builtins code;
6346 static const struct builtin_description_predicates bdesc_altivec_preds[] =
6348 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpbfp.", "__builtin_altivec_vcmpbfp_p", ALTIVEC_BUILTIN_VCMPBFP_P },
6349 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpeqfp.", "__builtin_altivec_vcmpeqfp_p", ALTIVEC_BUILTIN_VCMPEQFP_P },
6350 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgefp.", "__builtin_altivec_vcmpgefp_p", ALTIVEC_BUILTIN_VCMPGEFP_P },
6351 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4sf, "*vcmpgtfp.", "__builtin_altivec_vcmpgtfp_p", ALTIVEC_BUILTIN_VCMPGTFP_P },
6352 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpequw.", "__builtin_altivec_vcmpequw_p", ALTIVEC_BUILTIN_VCMPEQUW_P },
6353 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtsw.", "__builtin_altivec_vcmpgtsw_p", ALTIVEC_BUILTIN_VCMPGTSW_P },
6354 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v4si, "*vcmpgtuw.", "__builtin_altivec_vcmpgtuw_p", ALTIVEC_BUILTIN_VCMPGTUW_P },
6355 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtuh.", "__builtin_altivec_vcmpgtuh_p", ALTIVEC_BUILTIN_VCMPGTUH_P },
6356 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpgtsh.", "__builtin_altivec_vcmpgtsh_p", ALTIVEC_BUILTIN_VCMPGTSH_P },
6357 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v8hi, "*vcmpequh.", "__builtin_altivec_vcmpequh_p", ALTIVEC_BUILTIN_VCMPEQUH_P },
6358 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpequb.", "__builtin_altivec_vcmpequb_p", ALTIVEC_BUILTIN_VCMPEQUB_P },
6359 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtsb.", "__builtin_altivec_vcmpgtsb_p", ALTIVEC_BUILTIN_VCMPGTSB_P },
6360 { MASK_ALTIVEC, CODE_FOR_altivec_predicate_v16qi, "*vcmpgtub.", "__builtin_altivec_vcmpgtub_p", ALTIVEC_BUILTIN_VCMPGTUB_P },
6362 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpeq_p", ALTIVEC_BUILTIN_VCMPEQ_P },
6363 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpgt_p", ALTIVEC_BUILTIN_VCMPGT_P },
6364 { MASK_ALTIVEC, 0, NULL, "__builtin_vec_vcmpge_p", ALTIVEC_BUILTIN_VCMPGE_P }
6367 /* SPE predicates. */
6368 static struct builtin_description bdesc_spe_predicates[] =
6370 /* Place-holder. Leave as first. */
6371 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evcmpeq", SPE_BUILTIN_EVCMPEQ },
6372 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evcmpgts", SPE_BUILTIN_EVCMPGTS },
6373 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evcmpgtu", SPE_BUILTIN_EVCMPGTU },
6374 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evcmplts", SPE_BUILTIN_EVCMPLTS },
6375 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evcmpltu", SPE_BUILTIN_EVCMPLTU },
6376 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evfscmpeq", SPE_BUILTIN_EVFSCMPEQ },
6377 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evfscmpgt", SPE_BUILTIN_EVFSCMPGT },
6378 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evfscmplt", SPE_BUILTIN_EVFSCMPLT },
6379 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evfststeq", SPE_BUILTIN_EVFSTSTEQ },
6380 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evfststgt", SPE_BUILTIN_EVFSTSTGT },
6381 /* Place-holder. Leave as last. */
6382 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evfststlt", SPE_BUILTIN_EVFSTSTLT },
6385 /* SPE evsel predicates. */
6386 static struct builtin_description bdesc_spe_evsel[] =
6388 /* Place-holder. Leave as first. */
6389 { 0, CODE_FOR_spe_evcmpgts, "__builtin_spe_evsel_gts", SPE_BUILTIN_EVSEL_CMPGTS },
6390 { 0, CODE_FOR_spe_evcmpgtu, "__builtin_spe_evsel_gtu", SPE_BUILTIN_EVSEL_CMPGTU },
6391 { 0, CODE_FOR_spe_evcmplts, "__builtin_spe_evsel_lts", SPE_BUILTIN_EVSEL_CMPLTS },
6392 { 0, CODE_FOR_spe_evcmpltu, "__builtin_spe_evsel_ltu", SPE_BUILTIN_EVSEL_CMPLTU },
6393 { 0, CODE_FOR_spe_evcmpeq, "__builtin_spe_evsel_eq", SPE_BUILTIN_EVSEL_CMPEQ },
6394 { 0, CODE_FOR_spe_evfscmpgt, "__builtin_spe_evsel_fsgt", SPE_BUILTIN_EVSEL_FSCMPGT },
6395 { 0, CODE_FOR_spe_evfscmplt, "__builtin_spe_evsel_fslt", SPE_BUILTIN_EVSEL_FSCMPLT },
6396 { 0, CODE_FOR_spe_evfscmpeq, "__builtin_spe_evsel_fseq", SPE_BUILTIN_EVSEL_FSCMPEQ },
6397 { 0, CODE_FOR_spe_evfststgt, "__builtin_spe_evsel_fststgt", SPE_BUILTIN_EVSEL_FSTSTGT },
6398 { 0, CODE_FOR_spe_evfststlt, "__builtin_spe_evsel_fststlt", SPE_BUILTIN_EVSEL_FSTSTLT },
6399 /* Place-holder. Leave as last. */
6400 { 0, CODE_FOR_spe_evfststeq, "__builtin_spe_evsel_fststeq", SPE_BUILTIN_EVSEL_FSTSTEQ },
6403 /* ABS* operations. */
6405 static const struct builtin_description bdesc_abs[] =
6407 { MASK_ALTIVEC, CODE_FOR_absv4si2, "__builtin_altivec_abs_v4si", ALTIVEC_BUILTIN_ABS_V4SI },
6408 { MASK_ALTIVEC, CODE_FOR_absv8hi2, "__builtin_altivec_abs_v8hi", ALTIVEC_BUILTIN_ABS_V8HI },
6409 { MASK_ALTIVEC, CODE_FOR_absv4sf2, "__builtin_altivec_abs_v4sf", ALTIVEC_BUILTIN_ABS_V4SF },
6410 { MASK_ALTIVEC, CODE_FOR_absv16qi2, "__builtin_altivec_abs_v16qi", ALTIVEC_BUILTIN_ABS_V16QI },
6411 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v4si, "__builtin_altivec_abss_v4si", ALTIVEC_BUILTIN_ABSS_V4SI },
6412 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v8hi, "__builtin_altivec_abss_v8hi", ALTIVEC_BUILTIN_ABSS_V8HI },
6413 { MASK_ALTIVEC, CODE_FOR_altivec_abss_v16qi, "__builtin_altivec_abss_v16qi", ALTIVEC_BUILTIN_ABSS_V16QI }
6416 /* Simple unary operations: VECb = foo (unsigned literal) or VECb =
6419 static struct builtin_description bdesc_1arg[] =
6421 { MASK_ALTIVEC, CODE_FOR_altivec_vexptefp, "__builtin_altivec_vexptefp", ALTIVEC_BUILTIN_VEXPTEFP },
6422 { MASK_ALTIVEC, CODE_FOR_altivec_vlogefp, "__builtin_altivec_vlogefp", ALTIVEC_BUILTIN_VLOGEFP },
6423 { MASK_ALTIVEC, CODE_FOR_altivec_vrefp, "__builtin_altivec_vrefp", ALTIVEC_BUILTIN_VREFP },
6424 { MASK_ALTIVEC, CODE_FOR_altivec_vrfim, "__builtin_altivec_vrfim", ALTIVEC_BUILTIN_VRFIM },
6425 { MASK_ALTIVEC, CODE_FOR_altivec_vrfin, "__builtin_altivec_vrfin", ALTIVEC_BUILTIN_VRFIN },
6426 { MASK_ALTIVEC, CODE_FOR_altivec_vrfip, "__builtin_altivec_vrfip", ALTIVEC_BUILTIN_VRFIP },
6427 { MASK_ALTIVEC, CODE_FOR_ftruncv4sf2, "__builtin_altivec_vrfiz", ALTIVEC_BUILTIN_VRFIZ },
6428 { MASK_ALTIVEC, CODE_FOR_altivec_vrsqrtefp, "__builtin_altivec_vrsqrtefp", ALTIVEC_BUILTIN_VRSQRTEFP },
6429 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisb, "__builtin_altivec_vspltisb", ALTIVEC_BUILTIN_VSPLTISB },
6430 { MASK_ALTIVEC, CODE_FOR_altivec_vspltish, "__builtin_altivec_vspltish", ALTIVEC_BUILTIN_VSPLTISH },
6431 { MASK_ALTIVEC, CODE_FOR_altivec_vspltisw, "__builtin_altivec_vspltisw", ALTIVEC_BUILTIN_VSPLTISW },
6432 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsb, "__builtin_altivec_vupkhsb", ALTIVEC_BUILTIN_VUPKHSB },
6433 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhpx, "__builtin_altivec_vupkhpx", ALTIVEC_BUILTIN_VUPKHPX },
6434 { MASK_ALTIVEC, CODE_FOR_altivec_vupkhsh, "__builtin_altivec_vupkhsh", ALTIVEC_BUILTIN_VUPKHSH },
6435 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsb, "__builtin_altivec_vupklsb", ALTIVEC_BUILTIN_VUPKLSB },
6436 { MASK_ALTIVEC, CODE_FOR_altivec_vupklpx, "__builtin_altivec_vupklpx", ALTIVEC_BUILTIN_VUPKLPX },
6437 { MASK_ALTIVEC, CODE_FOR_altivec_vupklsh, "__builtin_altivec_vupklsh", ALTIVEC_BUILTIN_VUPKLSH },
6439 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abs", ALTIVEC_BUILTIN_VEC_ABS },
6440 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_abss", ALTIVEC_BUILTIN_VEC_ABSS },
6441 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_ceil", ALTIVEC_BUILTIN_VEC_CEIL },
6442 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_expte", ALTIVEC_BUILTIN_VEC_EXPTE },
6443 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_floor", ALTIVEC_BUILTIN_VEC_FLOOR },
6444 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_loge", ALTIVEC_BUILTIN_VEC_LOGE },
6445 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_mtvscr", ALTIVEC_BUILTIN_VEC_MTVSCR },
6446 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_re", ALTIVEC_BUILTIN_VEC_RE },
6447 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_round", ALTIVEC_BUILTIN_VEC_ROUND },
6448 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_rsqrte", ALTIVEC_BUILTIN_VEC_RSQRTE },
6449 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_trunc", ALTIVEC_BUILTIN_VEC_TRUNC },
6450 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackh", ALTIVEC_BUILTIN_VEC_UNPACKH },
6451 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsh", ALTIVEC_BUILTIN_VEC_VUPKHSH },
6452 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhpx", ALTIVEC_BUILTIN_VEC_VUPKHPX },
6453 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupkhsb", ALTIVEC_BUILTIN_VEC_VUPKHSB },
6454 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_unpackl", ALTIVEC_BUILTIN_VEC_UNPACKL },
6455 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklpx", ALTIVEC_BUILTIN_VEC_VUPKLPX },
6456 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsh", ALTIVEC_BUILTIN_VEC_VUPKLSH },
6457 { MASK_ALTIVEC, CODE_FOR_nothing, "__builtin_vec_vupklsb", ALTIVEC_BUILTIN_VEC_VUPKLSB },
6459 /* The SPE unary builtins must start with SPE_BUILTIN_EVABS and
6460 end with SPE_BUILTIN_EVSUBFUSIAAW. */
6461 { 0, CODE_FOR_spe_evabs, "__builtin_spe_evabs", SPE_BUILTIN_EVABS },
6462 { 0, CODE_FOR_spe_evaddsmiaaw, "__builtin_spe_evaddsmiaaw", SPE_BUILTIN_EVADDSMIAAW },
6463 { 0, CODE_FOR_spe_evaddssiaaw, "__builtin_spe_evaddssiaaw", SPE_BUILTIN_EVADDSSIAAW },
6464 { 0, CODE_FOR_spe_evaddumiaaw, "__builtin_spe_evaddumiaaw", SPE_BUILTIN_EVADDUMIAAW },
6465 { 0, CODE_FOR_spe_evaddusiaaw, "__builtin_spe_evaddusiaaw", SPE_BUILTIN_EVADDUSIAAW },
6466 { 0, CODE_FOR_spe_evcntlsw, "__builtin_spe_evcntlsw", SPE_BUILTIN_EVCNTLSW },
6467 { 0, CODE_FOR_spe_evcntlzw, "__builtin_spe_evcntlzw", SPE_BUILTIN_EVCNTLZW },
6468 { 0, CODE_FOR_spe_evextsb, "__builtin_spe_evextsb", SPE_BUILTIN_EVEXTSB },
6469 { 0, CODE_FOR_spe_evextsh, "__builtin_spe_evextsh", SPE_BUILTIN_EVEXTSH },
6470 { 0, CODE_FOR_spe_evfsabs, "__builtin_spe_evfsabs", SPE_BUILTIN_EVFSABS },
6471 { 0, CODE_FOR_spe_evfscfsf, "__builtin_spe_evfscfsf", SPE_BUILTIN_EVFSCFSF },
6472 { 0, CODE_FOR_spe_evfscfsi, "__builtin_spe_evfscfsi", SPE_BUILTIN_EVFSCFSI },
6473 { 0, CODE_FOR_spe_evfscfuf, "__builtin_spe_evfscfuf", SPE_BUILTIN_EVFSCFUF },
6474 { 0, CODE_FOR_spe_evfscfui, "__builtin_spe_evfscfui", SPE_BUILTIN_EVFSCFUI },
6475 { 0, CODE_FOR_spe_evfsctsf, "__builtin_spe_evfsctsf", SPE_BUILTIN_EVFSCTSF },
6476 { 0, CODE_FOR_spe_evfsctsi, "__builtin_spe_evfsctsi", SPE_BUILTIN_EVFSCTSI },
6477 { 0, CODE_FOR_spe_evfsctsiz, "__builtin_spe_evfsctsiz", SPE_BUILTIN_EVFSCTSIZ },
6478 { 0, CODE_FOR_spe_evfsctuf, "__builtin_spe_evfsctuf", SPE_BUILTIN_EVFSCTUF },
6479 { 0, CODE_FOR_spe_evfsctui, "__builtin_spe_evfsctui", SPE_BUILTIN_EVFSCTUI },
6480 { 0, CODE_FOR_spe_evfsctuiz, "__builtin_spe_evfsctuiz", SPE_BUILTIN_EVFSCTUIZ },
6481 { 0, CODE_FOR_spe_evfsnabs, "__builtin_spe_evfsnabs", SPE_BUILTIN_EVFSNABS },
6482 { 0, CODE_FOR_spe_evfsneg, "__builtin_spe_evfsneg", SPE_BUILTIN_EVFSNEG },
6483 { 0, CODE_FOR_spe_evmra, "__builtin_spe_evmra", SPE_BUILTIN_EVMRA },
6484 { 0, CODE_FOR_negv2si2, "__builtin_spe_evneg", SPE_BUILTIN_EVNEG },
6485 { 0, CODE_FOR_spe_evrndw, "__builtin_spe_evrndw", SPE_BUILTIN_EVRNDW },
6486 { 0, CODE_FOR_spe_evsubfsmiaaw, "__builtin_spe_evsubfsmiaaw", SPE_BUILTIN_EVSUBFSMIAAW },
6487 { 0, CODE_FOR_spe_evsubfssiaaw, "__builtin_spe_evsubfssiaaw", SPE_BUILTIN_EVSUBFSSIAAW },
6488 { 0, CODE_FOR_spe_evsubfumiaaw, "__builtin_spe_evsubfumiaaw", SPE_BUILTIN_EVSUBFUMIAAW },
6490 /* Place-holder. Leave as last unary SPE builtin. */
6491 { 0, CODE_FOR_spe_evsubfusiaaw, "__builtin_spe_evsubfusiaaw", SPE_BUILTIN_EVSUBFUSIAAW }
6495 rs6000_expand_unop_builtin (enum insn_code icode, tree arglist, rtx target)
6498 tree arg0 = TREE_VALUE (arglist);
6499 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6500 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6501 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6503 if (icode == CODE_FOR_nothing)
6504 /* Builtin not supported on this processor. */
6507 /* If we got invalid arguments bail out before generating bad rtl. */
6508 if (arg0 == error_mark_node)
6511 if (icode == CODE_FOR_altivec_vspltisb
6512 || icode == CODE_FOR_altivec_vspltish
6513 || icode == CODE_FOR_altivec_vspltisw
6514 || icode == CODE_FOR_spe_evsplatfi
6515 || icode == CODE_FOR_spe_evsplati)
6517 /* Only allow 5-bit *signed* literals. */
6518 if (GET_CODE (op0) != CONST_INT
6519 || INTVAL (op0) > 15
6520 || INTVAL (op0) < -16)
6522 error ("argument 1 must be a 5-bit signed literal");
6528 || GET_MODE (target) != tmode
6529 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6530 target = gen_reg_rtx (tmode);
6532 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6533 op0 = copy_to_mode_reg (mode0, op0);
6535 pat = GEN_FCN (icode) (target, op0);
6544 altivec_expand_abs_builtin (enum insn_code icode, tree arglist, rtx target)
6546 rtx pat, scratch1, scratch2;
6547 tree arg0 = TREE_VALUE (arglist);
6548 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6549 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6550 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6552 /* If we have invalid arguments, bail out before generating bad rtl. */
6553 if (arg0 == error_mark_node)
6557 || GET_MODE (target) != tmode
6558 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6559 target = gen_reg_rtx (tmode);
6561 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6562 op0 = copy_to_mode_reg (mode0, op0);
6564 scratch1 = gen_reg_rtx (mode0);
6565 scratch2 = gen_reg_rtx (mode0);
6567 pat = GEN_FCN (icode) (target, op0, scratch1, scratch2);
6576 rs6000_expand_binop_builtin (enum insn_code icode, tree arglist, rtx target)
6579 tree arg0 = TREE_VALUE (arglist);
6580 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6581 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6582 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6583 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6584 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6585 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6587 if (icode == CODE_FOR_nothing)
6588 /* Builtin not supported on this processor. */
6591 /* If we got invalid arguments bail out before generating bad rtl. */
6592 if (arg0 == error_mark_node || arg1 == error_mark_node)
6595 if (icode == CODE_FOR_altivec_vcfux
6596 || icode == CODE_FOR_altivec_vcfsx
6597 || icode == CODE_FOR_altivec_vctsxs
6598 || icode == CODE_FOR_altivec_vctuxs
6599 || icode == CODE_FOR_altivec_vspltb
6600 || icode == CODE_FOR_altivec_vsplth
6601 || icode == CODE_FOR_altivec_vspltw
6602 || icode == CODE_FOR_spe_evaddiw
6603 || icode == CODE_FOR_spe_evldd
6604 || icode == CODE_FOR_spe_evldh
6605 || icode == CODE_FOR_spe_evldw
6606 || icode == CODE_FOR_spe_evlhhesplat
6607 || icode == CODE_FOR_spe_evlhhossplat
6608 || icode == CODE_FOR_spe_evlhhousplat
6609 || icode == CODE_FOR_spe_evlwhe
6610 || icode == CODE_FOR_spe_evlwhos
6611 || icode == CODE_FOR_spe_evlwhou
6612 || icode == CODE_FOR_spe_evlwhsplat
6613 || icode == CODE_FOR_spe_evlwwsplat
6614 || icode == CODE_FOR_spe_evrlwi
6615 || icode == CODE_FOR_spe_evslwi
6616 || icode == CODE_FOR_spe_evsrwis
6617 || icode == CODE_FOR_spe_evsubifw
6618 || icode == CODE_FOR_spe_evsrwiu)
6620 /* Only allow 5-bit unsigned literals. */
6622 if (TREE_CODE (arg1) != INTEGER_CST
6623 || TREE_INT_CST_LOW (arg1) & ~0x1f)
6625 error ("argument 2 must be a 5-bit unsigned literal");
6631 || GET_MODE (target) != tmode
6632 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6633 target = gen_reg_rtx (tmode);
6635 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6636 op0 = copy_to_mode_reg (mode0, op0);
6637 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6638 op1 = copy_to_mode_reg (mode1, op1);
6640 pat = GEN_FCN (icode) (target, op0, op1);
6649 altivec_expand_predicate_builtin (enum insn_code icode, const char *opcode,
6650 tree arglist, rtx target)
6653 tree cr6_form = TREE_VALUE (arglist);
6654 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
6655 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6656 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6657 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6658 enum machine_mode tmode = SImode;
6659 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6660 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6663 if (TREE_CODE (cr6_form) != INTEGER_CST)
6665 error ("argument 1 of __builtin_altivec_predicate must be a constant");
6669 cr6_form_int = TREE_INT_CST_LOW (cr6_form);
6671 gcc_assert (mode0 == mode1);
6673 /* If we have invalid arguments, bail out before generating bad rtl. */
6674 if (arg0 == error_mark_node || arg1 == error_mark_node)
6678 || GET_MODE (target) != tmode
6679 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6680 target = gen_reg_rtx (tmode);
6682 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6683 op0 = copy_to_mode_reg (mode0, op0);
6684 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6685 op1 = copy_to_mode_reg (mode1, op1);
6687 scratch = gen_reg_rtx (mode0);
6689 pat = GEN_FCN (icode) (scratch, op0, op1,
6690 gen_rtx_SYMBOL_REF (Pmode, opcode));
6695 /* The vec_any* and vec_all* predicates use the same opcodes for two
6696 different operations, but the bits in CR6 will be different
6697 depending on what information we want. So we have to play tricks
6698 with CR6 to get the right bits out.
6700 If you think this is disgusting, look at the specs for the
6701 AltiVec predicates. */
6703 switch (cr6_form_int)
6706 emit_insn (gen_cr6_test_for_zero (target));
6709 emit_insn (gen_cr6_test_for_zero_reverse (target));
6712 emit_insn (gen_cr6_test_for_lt (target));
6715 emit_insn (gen_cr6_test_for_lt_reverse (target));
6718 error ("argument 1 of __builtin_altivec_predicate is out of range");
6726 altivec_expand_lv_builtin (enum insn_code icode, tree arglist, rtx target)
6729 tree arg0 = TREE_VALUE (arglist);
6730 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6731 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6732 enum machine_mode mode0 = Pmode;
6733 enum machine_mode mode1 = Pmode;
6734 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6735 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6737 if (icode == CODE_FOR_nothing)
6738 /* Builtin not supported on this processor. */
6741 /* If we got invalid arguments bail out before generating bad rtl. */
6742 if (arg0 == error_mark_node || arg1 == error_mark_node)
6746 || GET_MODE (target) != tmode
6747 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6748 target = gen_reg_rtx (tmode);
6750 op1 = copy_to_mode_reg (mode1, op1);
6752 if (op0 == const0_rtx)
6754 addr = gen_rtx_MEM (tmode, op1);
6758 op0 = copy_to_mode_reg (mode0, op0);
6759 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op0, op1));
6762 pat = GEN_FCN (icode) (target, addr);
6772 spe_expand_stv_builtin (enum insn_code icode, tree arglist)
6774 tree arg0 = TREE_VALUE (arglist);
6775 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6776 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6777 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6778 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6779 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6781 enum machine_mode mode0 = insn_data[icode].operand[0].mode;
6782 enum machine_mode mode1 = insn_data[icode].operand[1].mode;
6783 enum machine_mode mode2 = insn_data[icode].operand[2].mode;
6785 /* Invalid arguments. Bail before doing anything stoopid! */
6786 if (arg0 == error_mark_node
6787 || arg1 == error_mark_node
6788 || arg2 == error_mark_node)
6791 if (! (*insn_data[icode].operand[2].predicate) (op0, mode2))
6792 op0 = copy_to_mode_reg (mode2, op0);
6793 if (! (*insn_data[icode].operand[0].predicate) (op1, mode0))
6794 op1 = copy_to_mode_reg (mode0, op1);
6795 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
6796 op2 = copy_to_mode_reg (mode1, op2);
6798 pat = GEN_FCN (icode) (op1, op2, op0);
6805 altivec_expand_stv_builtin (enum insn_code icode, tree arglist)
6807 tree arg0 = TREE_VALUE (arglist);
6808 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6809 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6810 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6811 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6812 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6814 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6815 enum machine_mode mode1 = Pmode;
6816 enum machine_mode mode2 = Pmode;
6818 /* Invalid arguments. Bail before doing anything stoopid! */
6819 if (arg0 == error_mark_node
6820 || arg1 == error_mark_node
6821 || arg2 == error_mark_node)
6824 if (! (*insn_data[icode].operand[1].predicate) (op0, tmode))
6825 op0 = copy_to_mode_reg (tmode, op0);
6827 op2 = copy_to_mode_reg (mode2, op2);
6829 if (op1 == const0_rtx)
6831 addr = gen_rtx_MEM (tmode, op2);
6835 op1 = copy_to_mode_reg (mode1, op1);
6836 addr = gen_rtx_MEM (tmode, gen_rtx_PLUS (Pmode, op1, op2));
6839 pat = GEN_FCN (icode) (addr, op0);
6846 rs6000_expand_ternop_builtin (enum insn_code icode, tree arglist, rtx target)
6849 tree arg0 = TREE_VALUE (arglist);
6850 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6851 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
6852 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6853 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6854 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
6855 enum machine_mode tmode = insn_data[icode].operand[0].mode;
6856 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
6857 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
6858 enum machine_mode mode2 = insn_data[icode].operand[3].mode;
6860 if (icode == CODE_FOR_nothing)
6861 /* Builtin not supported on this processor. */
6864 /* If we got invalid arguments bail out before generating bad rtl. */
6865 if (arg0 == error_mark_node
6866 || arg1 == error_mark_node
6867 || arg2 == error_mark_node)
6870 if (icode == CODE_FOR_altivec_vsldoi_v4sf
6871 || icode == CODE_FOR_altivec_vsldoi_v4si
6872 || icode == CODE_FOR_altivec_vsldoi_v8hi
6873 || icode == CODE_FOR_altivec_vsldoi_v16qi)
6875 /* Only allow 4-bit unsigned literals. */
6877 if (TREE_CODE (arg2) != INTEGER_CST
6878 || TREE_INT_CST_LOW (arg2) & ~0xf)
6880 error ("argument 3 must be a 4-bit unsigned literal");
6886 || GET_MODE (target) != tmode
6887 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6888 target = gen_reg_rtx (tmode);
6890 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6891 op0 = copy_to_mode_reg (mode0, op0);
6892 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
6893 op1 = copy_to_mode_reg (mode1, op1);
6894 if (! (*insn_data[icode].operand[3].predicate) (op2, mode2))
6895 op2 = copy_to_mode_reg (mode2, op2);
6897 pat = GEN_FCN (icode) (target, op0, op1, op2);
6905 /* Expand the lvx builtins. */
6907 altivec_expand_ld_builtin (tree exp, rtx target, bool *expandedp)
6909 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6910 tree arglist = TREE_OPERAND (exp, 1);
6911 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6913 enum machine_mode tmode, mode0;
6915 enum insn_code icode;
6919 case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
6920 icode = CODE_FOR_altivec_lvx_v16qi;
6922 case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
6923 icode = CODE_FOR_altivec_lvx_v8hi;
6925 case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
6926 icode = CODE_FOR_altivec_lvx_v4si;
6928 case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
6929 icode = CODE_FOR_altivec_lvx_v4sf;
6938 arg0 = TREE_VALUE (arglist);
6939 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6940 tmode = insn_data[icode].operand[0].mode;
6941 mode0 = insn_data[icode].operand[1].mode;
6944 || GET_MODE (target) != tmode
6945 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
6946 target = gen_reg_rtx (tmode);
6948 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
6949 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6951 pat = GEN_FCN (icode) (target, op0);
6958 /* Expand the stvx builtins. */
6960 altivec_expand_st_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
6963 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
6964 tree arglist = TREE_OPERAND (exp, 1);
6965 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
6967 enum machine_mode mode0, mode1;
6969 enum insn_code icode;
6973 case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
6974 icode = CODE_FOR_altivec_stvx_v16qi;
6976 case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
6977 icode = CODE_FOR_altivec_stvx_v8hi;
6979 case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
6980 icode = CODE_FOR_altivec_stvx_v4si;
6982 case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
6983 icode = CODE_FOR_altivec_stvx_v4sf;
6990 arg0 = TREE_VALUE (arglist);
6991 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
6992 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
6993 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
6994 mode0 = insn_data[icode].operand[0].mode;
6995 mode1 = insn_data[icode].operand[1].mode;
6997 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
6998 op0 = gen_rtx_MEM (mode0, copy_to_mode_reg (Pmode, op0));
6999 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7000 op1 = copy_to_mode_reg (mode1, op1);
7002 pat = GEN_FCN (icode) (op0, op1);
7010 /* Expand the dst builtins. */
7012 altivec_expand_dst_builtin (tree exp, rtx target ATTRIBUTE_UNUSED,
7015 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7016 tree arglist = TREE_OPERAND (exp, 1);
7017 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7018 tree arg0, arg1, arg2;
7019 enum machine_mode mode0, mode1, mode2;
7020 rtx pat, op0, op1, op2;
7021 struct builtin_description *d;
7026 /* Handle DST variants. */
7027 d = (struct builtin_description *) bdesc_dst;
7028 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
7029 if (d->code == fcode)
7031 arg0 = TREE_VALUE (arglist);
7032 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7033 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7034 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7035 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7036 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7037 mode0 = insn_data[d->icode].operand[0].mode;
7038 mode1 = insn_data[d->icode].operand[1].mode;
7039 mode2 = insn_data[d->icode].operand[2].mode;
7041 /* Invalid arguments, bail out before generating bad rtl. */
7042 if (arg0 == error_mark_node
7043 || arg1 == error_mark_node
7044 || arg2 == error_mark_node)
7049 if (TREE_CODE (arg2) != INTEGER_CST
7050 || TREE_INT_CST_LOW (arg2) & ~0x3)
7052 error ("argument to %qs must be a 2-bit unsigned literal", d->name);
7056 if (! (*insn_data[d->icode].operand[0].predicate) (op0, mode0))
7057 op0 = copy_to_mode_reg (Pmode, op0);
7058 if (! (*insn_data[d->icode].operand[1].predicate) (op1, mode1))
7059 op1 = copy_to_mode_reg (mode1, op1);
7061 pat = GEN_FCN (d->icode) (op0, op1, op2);
7071 /* Expand vec_init builtin. */
7073 altivec_expand_vec_init_builtin (tree type, tree arglist, rtx target)
7075 enum machine_mode tmode = TYPE_MODE (type);
7076 enum machine_mode inner_mode = GET_MODE_INNER (tmode);
7077 int i, n_elt = GET_MODE_NUNITS (tmode);
7078 rtvec v = rtvec_alloc (n_elt);
7080 gcc_assert (VECTOR_MODE_P (tmode));
7082 for (i = 0; i < n_elt; ++i, arglist = TREE_CHAIN (arglist))
7084 rtx x = expand_expr (TREE_VALUE (arglist), NULL_RTX, VOIDmode, 0);
7085 RTVEC_ELT (v, i) = gen_lowpart (inner_mode, x);
7088 gcc_assert (arglist == NULL);
7090 if (!target || !register_operand (target, tmode))
7091 target = gen_reg_rtx (tmode);
7093 rs6000_expand_vector_init (target, gen_rtx_PARALLEL (tmode, v));
7097 /* Return the integer constant in ARG. Constrain it to be in the range
7098 of the subparts of VEC_TYPE; issue an error if not. */
7101 get_element_number (tree vec_type, tree arg)
7103 unsigned HOST_WIDE_INT elt, max = TYPE_VECTOR_SUBPARTS (vec_type) - 1;
7105 if (!host_integerp (arg, 1)
7106 || (elt = tree_low_cst (arg, 1), elt > max))
7108 error ("selector must be an integer constant in the range 0..%wi", max);
7115 /* Expand vec_set builtin. */
7117 altivec_expand_vec_set_builtin (tree arglist)
7119 enum machine_mode tmode, mode1;
7120 tree arg0, arg1, arg2;
7124 arg0 = TREE_VALUE (arglist);
7125 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7126 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7128 tmode = TYPE_MODE (TREE_TYPE (arg0));
7129 mode1 = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7130 gcc_assert (VECTOR_MODE_P (tmode));
7132 op0 = expand_expr (arg0, NULL_RTX, tmode, 0);
7133 op1 = expand_expr (arg1, NULL_RTX, mode1, 0);
7134 elt = get_element_number (TREE_TYPE (arg0), arg2);
7136 if (GET_MODE (op1) != mode1 && GET_MODE (op1) != VOIDmode)
7137 op1 = convert_modes (mode1, GET_MODE (op1), op1, true);
7139 op0 = force_reg (tmode, op0);
7140 op1 = force_reg (mode1, op1);
7142 rs6000_expand_vector_set (op0, op1, elt);
7147 /* Expand vec_ext builtin. */
7149 altivec_expand_vec_ext_builtin (tree arglist, rtx target)
7151 enum machine_mode tmode, mode0;
7156 arg0 = TREE_VALUE (arglist);
7157 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7159 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7160 elt = get_element_number (TREE_TYPE (arg0), arg1);
7162 tmode = TYPE_MODE (TREE_TYPE (TREE_TYPE (arg0)));
7163 mode0 = TYPE_MODE (TREE_TYPE (arg0));
7164 gcc_assert (VECTOR_MODE_P (mode0));
7166 op0 = force_reg (mode0, op0);
7168 if (optimize || !target || !register_operand (target, tmode))
7169 target = gen_reg_rtx (tmode);
7171 rs6000_expand_vector_extract (target, op0, elt);
7176 /* Expand the builtin in EXP and store the result in TARGET. Store
7177 true in *EXPANDEDP if we found a builtin to expand. */
7179 altivec_expand_builtin (tree exp, rtx target, bool *expandedp)
7181 struct builtin_description *d;
7182 struct builtin_description_predicates *dp;
7184 enum insn_code icode;
7185 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7186 tree arglist = TREE_OPERAND (exp, 1);
7189 enum machine_mode tmode, mode0;
7190 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7192 if (fcode >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
7193 && fcode <= ALTIVEC_BUILTIN_OVERLOADED_LAST)
7196 error ("unresolved overload for Altivec builtin %qF", fndecl);
7200 target = altivec_expand_ld_builtin (exp, target, expandedp);
7204 target = altivec_expand_st_builtin (exp, target, expandedp);
7208 target = altivec_expand_dst_builtin (exp, target, expandedp);
7216 case ALTIVEC_BUILTIN_STVX:
7217 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvx, arglist);
7218 case ALTIVEC_BUILTIN_STVEBX:
7219 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvebx, arglist);
7220 case ALTIVEC_BUILTIN_STVEHX:
7221 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvehx, arglist);
7222 case ALTIVEC_BUILTIN_STVEWX:
7223 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvewx, arglist);
7224 case ALTIVEC_BUILTIN_STVXL:
7225 return altivec_expand_stv_builtin (CODE_FOR_altivec_stvxl, arglist);
7227 case ALTIVEC_BUILTIN_MFVSCR:
7228 icode = CODE_FOR_altivec_mfvscr;
7229 tmode = insn_data[icode].operand[0].mode;
7232 || GET_MODE (target) != tmode
7233 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7234 target = gen_reg_rtx (tmode);
7236 pat = GEN_FCN (icode) (target);
7242 case ALTIVEC_BUILTIN_MTVSCR:
7243 icode = CODE_FOR_altivec_mtvscr;
7244 arg0 = TREE_VALUE (arglist);
7245 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7246 mode0 = insn_data[icode].operand[0].mode;
7248 /* If we got invalid arguments bail out before generating bad rtl. */
7249 if (arg0 == error_mark_node)
7252 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7253 op0 = copy_to_mode_reg (mode0, op0);
7255 pat = GEN_FCN (icode) (op0);
7260 case ALTIVEC_BUILTIN_DSSALL:
7261 emit_insn (gen_altivec_dssall ());
7264 case ALTIVEC_BUILTIN_DSS:
7265 icode = CODE_FOR_altivec_dss;
7266 arg0 = TREE_VALUE (arglist);
7268 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7269 mode0 = insn_data[icode].operand[0].mode;
7271 /* If we got invalid arguments bail out before generating bad rtl. */
7272 if (arg0 == error_mark_node)
7275 if (TREE_CODE (arg0) != INTEGER_CST
7276 || TREE_INT_CST_LOW (arg0) & ~0x3)
7278 error ("argument to dss must be a 2-bit unsigned literal");
7282 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7283 op0 = copy_to_mode_reg (mode0, op0);
7285 emit_insn (gen_altivec_dss (op0));
7288 case ALTIVEC_BUILTIN_VEC_INIT_V4SI:
7289 case ALTIVEC_BUILTIN_VEC_INIT_V8HI:
7290 case ALTIVEC_BUILTIN_VEC_INIT_V16QI:
7291 case ALTIVEC_BUILTIN_VEC_INIT_V4SF:
7292 return altivec_expand_vec_init_builtin (TREE_TYPE (exp), arglist, target);
7294 case ALTIVEC_BUILTIN_VEC_SET_V4SI:
7295 case ALTIVEC_BUILTIN_VEC_SET_V8HI:
7296 case ALTIVEC_BUILTIN_VEC_SET_V16QI:
7297 case ALTIVEC_BUILTIN_VEC_SET_V4SF:
7298 return altivec_expand_vec_set_builtin (arglist);
7300 case ALTIVEC_BUILTIN_VEC_EXT_V4SI:
7301 case ALTIVEC_BUILTIN_VEC_EXT_V8HI:
7302 case ALTIVEC_BUILTIN_VEC_EXT_V16QI:
7303 case ALTIVEC_BUILTIN_VEC_EXT_V4SF:
7304 return altivec_expand_vec_ext_builtin (arglist, target);
7311 /* Expand abs* operations. */
7312 d = (struct builtin_description *) bdesc_abs;
7313 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
7314 if (d->code == fcode)
7315 return altivec_expand_abs_builtin (d->icode, arglist, target);
7317 /* Expand the AltiVec predicates. */
7318 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
7319 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
7320 if (dp->code == fcode)
7321 return altivec_expand_predicate_builtin (dp->icode, dp->opcode,
7324 /* LV* are funky. We initialized them differently. */
7327 case ALTIVEC_BUILTIN_LVSL:
7328 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsl,
7330 case ALTIVEC_BUILTIN_LVSR:
7331 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvsr,
7333 case ALTIVEC_BUILTIN_LVEBX:
7334 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvebx,
7336 case ALTIVEC_BUILTIN_LVEHX:
7337 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvehx,
7339 case ALTIVEC_BUILTIN_LVEWX:
7340 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvewx,
7342 case ALTIVEC_BUILTIN_LVXL:
7343 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvxl,
7345 case ALTIVEC_BUILTIN_LVX:
7346 return altivec_expand_lv_builtin (CODE_FOR_altivec_lvx,
7357 /* Binops that need to be initialized manually, but can be expanded
7358 automagically by rs6000_expand_binop_builtin. */
7359 static struct builtin_description bdesc_2arg_spe[] =
7361 { 0, CODE_FOR_spe_evlddx, "__builtin_spe_evlddx", SPE_BUILTIN_EVLDDX },
7362 { 0, CODE_FOR_spe_evldwx, "__builtin_spe_evldwx", SPE_BUILTIN_EVLDWX },
7363 { 0, CODE_FOR_spe_evldhx, "__builtin_spe_evldhx", SPE_BUILTIN_EVLDHX },
7364 { 0, CODE_FOR_spe_evlwhex, "__builtin_spe_evlwhex", SPE_BUILTIN_EVLWHEX },
7365 { 0, CODE_FOR_spe_evlwhoux, "__builtin_spe_evlwhoux", SPE_BUILTIN_EVLWHOUX },
7366 { 0, CODE_FOR_spe_evlwhosx, "__builtin_spe_evlwhosx", SPE_BUILTIN_EVLWHOSX },
7367 { 0, CODE_FOR_spe_evlwwsplatx, "__builtin_spe_evlwwsplatx", SPE_BUILTIN_EVLWWSPLATX },
7368 { 0, CODE_FOR_spe_evlwhsplatx, "__builtin_spe_evlwhsplatx", SPE_BUILTIN_EVLWHSPLATX },
7369 { 0, CODE_FOR_spe_evlhhesplatx, "__builtin_spe_evlhhesplatx", SPE_BUILTIN_EVLHHESPLATX },
7370 { 0, CODE_FOR_spe_evlhhousplatx, "__builtin_spe_evlhhousplatx", SPE_BUILTIN_EVLHHOUSPLATX },
7371 { 0, CODE_FOR_spe_evlhhossplatx, "__builtin_spe_evlhhossplatx", SPE_BUILTIN_EVLHHOSSPLATX },
7372 { 0, CODE_FOR_spe_evldd, "__builtin_spe_evldd", SPE_BUILTIN_EVLDD },
7373 { 0, CODE_FOR_spe_evldw, "__builtin_spe_evldw", SPE_BUILTIN_EVLDW },
7374 { 0, CODE_FOR_spe_evldh, "__builtin_spe_evldh", SPE_BUILTIN_EVLDH },
7375 { 0, CODE_FOR_spe_evlwhe, "__builtin_spe_evlwhe", SPE_BUILTIN_EVLWHE },
7376 { 0, CODE_FOR_spe_evlwhou, "__builtin_spe_evlwhou", SPE_BUILTIN_EVLWHOU },
7377 { 0, CODE_FOR_spe_evlwhos, "__builtin_spe_evlwhos", SPE_BUILTIN_EVLWHOS },
7378 { 0, CODE_FOR_spe_evlwwsplat, "__builtin_spe_evlwwsplat", SPE_BUILTIN_EVLWWSPLAT },
7379 { 0, CODE_FOR_spe_evlwhsplat, "__builtin_spe_evlwhsplat", SPE_BUILTIN_EVLWHSPLAT },
7380 { 0, CODE_FOR_spe_evlhhesplat, "__builtin_spe_evlhhesplat", SPE_BUILTIN_EVLHHESPLAT },
7381 { 0, CODE_FOR_spe_evlhhousplat, "__builtin_spe_evlhhousplat", SPE_BUILTIN_EVLHHOUSPLAT },
7382 { 0, CODE_FOR_spe_evlhhossplat, "__builtin_spe_evlhhossplat", SPE_BUILTIN_EVLHHOSSPLAT }
7385 /* Expand the builtin in EXP and store the result in TARGET. Store
7386 true in *EXPANDEDP if we found a builtin to expand.
7388 This expands the SPE builtins that are not simple unary and binary
7391 spe_expand_builtin (tree exp, rtx target, bool *expandedp)
7393 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7394 tree arglist = TREE_OPERAND (exp, 1);
7396 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7397 enum insn_code icode;
7398 enum machine_mode tmode, mode0;
7400 struct builtin_description *d;
7405 /* Syntax check for a 5-bit unsigned immediate. */
7408 case SPE_BUILTIN_EVSTDD:
7409 case SPE_BUILTIN_EVSTDH:
7410 case SPE_BUILTIN_EVSTDW:
7411 case SPE_BUILTIN_EVSTWHE:
7412 case SPE_BUILTIN_EVSTWHO:
7413 case SPE_BUILTIN_EVSTWWE:
7414 case SPE_BUILTIN_EVSTWWO:
7415 arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7416 if (TREE_CODE (arg1) != INTEGER_CST
7417 || TREE_INT_CST_LOW (arg1) & ~0x1f)
7419 error ("argument 2 must be a 5-bit unsigned literal");
7427 /* The evsplat*i instructions are not quite generic. */
7430 case SPE_BUILTIN_EVSPLATFI:
7431 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplatfi,
7433 case SPE_BUILTIN_EVSPLATI:
7434 return rs6000_expand_unop_builtin (CODE_FOR_spe_evsplati,
7440 d = (struct builtin_description *) bdesc_2arg_spe;
7441 for (i = 0; i < ARRAY_SIZE (bdesc_2arg_spe); ++i, ++d)
7442 if (d->code == fcode)
7443 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7445 d = (struct builtin_description *) bdesc_spe_predicates;
7446 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, ++d)
7447 if (d->code == fcode)
7448 return spe_expand_predicate_builtin (d->icode, arglist, target);
7450 d = (struct builtin_description *) bdesc_spe_evsel;
7451 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, ++d)
7452 if (d->code == fcode)
7453 return spe_expand_evsel_builtin (d->icode, arglist, target);
7457 case SPE_BUILTIN_EVSTDDX:
7458 return spe_expand_stv_builtin (CODE_FOR_spe_evstddx, arglist);
7459 case SPE_BUILTIN_EVSTDHX:
7460 return spe_expand_stv_builtin (CODE_FOR_spe_evstdhx, arglist);
7461 case SPE_BUILTIN_EVSTDWX:
7462 return spe_expand_stv_builtin (CODE_FOR_spe_evstdwx, arglist);
7463 case SPE_BUILTIN_EVSTWHEX:
7464 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhex, arglist);
7465 case SPE_BUILTIN_EVSTWHOX:
7466 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhox, arglist);
7467 case SPE_BUILTIN_EVSTWWEX:
7468 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwex, arglist);
7469 case SPE_BUILTIN_EVSTWWOX:
7470 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwox, arglist);
7471 case SPE_BUILTIN_EVSTDD:
7472 return spe_expand_stv_builtin (CODE_FOR_spe_evstdd, arglist);
7473 case SPE_BUILTIN_EVSTDH:
7474 return spe_expand_stv_builtin (CODE_FOR_spe_evstdh, arglist);
7475 case SPE_BUILTIN_EVSTDW:
7476 return spe_expand_stv_builtin (CODE_FOR_spe_evstdw, arglist);
7477 case SPE_BUILTIN_EVSTWHE:
7478 return spe_expand_stv_builtin (CODE_FOR_spe_evstwhe, arglist);
7479 case SPE_BUILTIN_EVSTWHO:
7480 return spe_expand_stv_builtin (CODE_FOR_spe_evstwho, arglist);
7481 case SPE_BUILTIN_EVSTWWE:
7482 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwe, arglist);
7483 case SPE_BUILTIN_EVSTWWO:
7484 return spe_expand_stv_builtin (CODE_FOR_spe_evstwwo, arglist);
7485 case SPE_BUILTIN_MFSPEFSCR:
7486 icode = CODE_FOR_spe_mfspefscr;
7487 tmode = insn_data[icode].operand[0].mode;
7490 || GET_MODE (target) != tmode
7491 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7492 target = gen_reg_rtx (tmode);
7494 pat = GEN_FCN (icode) (target);
7499 case SPE_BUILTIN_MTSPEFSCR:
7500 icode = CODE_FOR_spe_mtspefscr;
7501 arg0 = TREE_VALUE (arglist);
7502 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7503 mode0 = insn_data[icode].operand[0].mode;
7505 if (arg0 == error_mark_node)
7508 if (! (*insn_data[icode].operand[0].predicate) (op0, mode0))
7509 op0 = copy_to_mode_reg (mode0, op0);
7511 pat = GEN_FCN (icode) (op0);
7524 spe_expand_predicate_builtin (enum insn_code icode, tree arglist, rtx target)
7526 rtx pat, scratch, tmp;
7527 tree form = TREE_VALUE (arglist);
7528 tree arg0 = TREE_VALUE (TREE_CHAIN (arglist));
7529 tree arg1 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7530 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7531 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7532 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7533 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7537 if (TREE_CODE (form) != INTEGER_CST)
7539 error ("argument 1 of __builtin_spe_predicate must be a constant");
7543 form_int = TREE_INT_CST_LOW (form);
7545 gcc_assert (mode0 == mode1);
7547 if (arg0 == error_mark_node || arg1 == error_mark_node)
7551 || GET_MODE (target) != SImode
7552 || ! (*insn_data[icode].operand[0].predicate) (target, SImode))
7553 target = gen_reg_rtx (SImode);
7555 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7556 op0 = copy_to_mode_reg (mode0, op0);
7557 if (! (*insn_data[icode].operand[2].predicate) (op1, mode1))
7558 op1 = copy_to_mode_reg (mode1, op1);
7560 scratch = gen_reg_rtx (CCmode);
7562 pat = GEN_FCN (icode) (scratch, op0, op1);
7567 /* There are 4 variants for each predicate: _any_, _all_, _upper_,
7568 _lower_. We use one compare, but look in different bits of the
7569 CR for each variant.
7571 There are 2 elements in each SPE simd type (upper/lower). The CR
7572 bits are set as follows:
7574 BIT0 | BIT 1 | BIT 2 | BIT 3
7575 U | L | (U | L) | (U & L)
7577 So, for an "all" relationship, BIT 3 would be set.
7578 For an "any" relationship, BIT 2 would be set. Etc.
7580 Following traditional nomenclature, these bits map to:
7582 BIT0 | BIT 1 | BIT 2 | BIT 3
7585 Later, we will generate rtl to look in the LT/EQ/EQ/OV bits.
7590 /* All variant. OV bit. */
7592 /* We need to get to the OV bit, which is the ORDERED bit. We
7593 could generate (ordered:SI (reg:CC xx) (const_int 0)), but
7594 that's ugly and will make validate_condition_mode die.
7595 So let's just use another pattern. */
7596 emit_insn (gen_move_from_CR_ov_bit (target, scratch));
7598 /* Any variant. EQ bit. */
7602 /* Upper variant. LT bit. */
7606 /* Lower variant. GT bit. */
7611 error ("argument 1 of __builtin_spe_predicate is out of range");
7615 tmp = gen_rtx_fmt_ee (code, SImode, scratch, const0_rtx);
7616 emit_move_insn (target, tmp);
7621 /* The evsel builtins look like this:
7623 e = __builtin_spe_evsel_OP (a, b, c, d);
7627 e[upper] = a[upper] *OP* b[upper] ? c[upper] : d[upper];
7628 e[lower] = a[lower] *OP* b[lower] ? c[lower] : d[lower];
7632 spe_expand_evsel_builtin (enum insn_code icode, tree arglist, rtx target)
7635 tree arg0 = TREE_VALUE (arglist);
7636 tree arg1 = TREE_VALUE (TREE_CHAIN (arglist));
7637 tree arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
7638 tree arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
7639 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
7640 rtx op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
7641 rtx op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
7642 rtx op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
7643 enum machine_mode mode0 = insn_data[icode].operand[1].mode;
7644 enum machine_mode mode1 = insn_data[icode].operand[2].mode;
7646 gcc_assert (mode0 == mode1);
7648 if (arg0 == error_mark_node || arg1 == error_mark_node
7649 || arg2 == error_mark_node || arg3 == error_mark_node)
7653 || GET_MODE (target) != mode0
7654 || ! (*insn_data[icode].operand[0].predicate) (target, mode0))
7655 target = gen_reg_rtx (mode0);
7657 if (! (*insn_data[icode].operand[1].predicate) (op0, mode0))
7658 op0 = copy_to_mode_reg (mode0, op0);
7659 if (! (*insn_data[icode].operand[1].predicate) (op1, mode1))
7660 op1 = copy_to_mode_reg (mode0, op1);
7661 if (! (*insn_data[icode].operand[1].predicate) (op2, mode1))
7662 op2 = copy_to_mode_reg (mode0, op2);
7663 if (! (*insn_data[icode].operand[1].predicate) (op3, mode1))
7664 op3 = copy_to_mode_reg (mode0, op3);
7666 /* Generate the compare. */
7667 scratch = gen_reg_rtx (CCmode);
7668 pat = GEN_FCN (icode) (scratch, op0, op1);
7673 if (mode0 == V2SImode)
7674 emit_insn (gen_spe_evsel (target, op2, op3, scratch));
7676 emit_insn (gen_spe_evsel_fs (target, op2, op3, scratch));
7681 /* Expand an expression EXP that calls a built-in function,
7682 with result going to TARGET if that's convenient
7683 (and in mode MODE if that's convenient).
7684 SUBTARGET may be used as the target for computing one of EXP's operands.
7685 IGNORE is nonzero if the value is to be ignored. */
7688 rs6000_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
7689 enum machine_mode mode ATTRIBUTE_UNUSED,
7690 int ignore ATTRIBUTE_UNUSED)
7692 tree fndecl = TREE_OPERAND (TREE_OPERAND (exp, 0), 0);
7693 tree arglist = TREE_OPERAND (exp, 1);
7694 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
7695 struct builtin_description *d;
7700 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_LOAD
7701 || fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7703 int icode = (int) CODE_FOR_altivec_lvsr;
7704 enum machine_mode tmode = insn_data[icode].operand[0].mode;
7705 enum machine_mode mode = insn_data[icode].operand[1].mode;
7709 gcc_assert (TARGET_ALTIVEC);
7711 arg = TREE_VALUE (arglist);
7712 gcc_assert (TREE_CODE (TREE_TYPE (arg)) == POINTER_TYPE);
7713 op = expand_expr (arg, NULL_RTX, Pmode, EXPAND_NORMAL);
7714 addr = memory_address (mode, op);
7715 if (fcode == ALTIVEC_BUILTIN_MASK_FOR_STORE)
7719 /* For the load case need to negate the address. */
7720 op = gen_reg_rtx (GET_MODE (addr));
7721 emit_insn (gen_rtx_SET (VOIDmode, op,
7722 gen_rtx_NEG (GET_MODE (addr), addr)));
7724 op = gen_rtx_MEM (mode, op);
7727 || GET_MODE (target) != tmode
7728 || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
7729 target = gen_reg_rtx (tmode);
7731 /*pat = gen_altivec_lvsr (target, op);*/
7732 pat = GEN_FCN (icode) (target, op);
7742 ret = altivec_expand_builtin (exp, target, &success);
7749 ret = spe_expand_builtin (exp, target, &success);
7755 gcc_assert (TARGET_ALTIVEC || TARGET_SPE);
7757 /* Handle simple unary operations. */
7758 d = (struct builtin_description *) bdesc_1arg;
7759 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
7760 if (d->code == fcode)
7761 return rs6000_expand_unop_builtin (d->icode, arglist, target);
7763 /* Handle simple binary operations. */
7764 d = (struct builtin_description *) bdesc_2arg;
7765 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
7766 if (d->code == fcode)
7767 return rs6000_expand_binop_builtin (d->icode, arglist, target);
7769 /* Handle simple ternary operations. */
7770 d = (struct builtin_description *) bdesc_3arg;
7771 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
7772 if (d->code == fcode)
7773 return rs6000_expand_ternop_builtin (d->icode, arglist, target);
7779 build_opaque_vector_type (tree node, int nunits)
7781 node = copy_node (node);
7782 TYPE_MAIN_VARIANT (node) = node;
7783 return build_vector_type (node, nunits);
7787 rs6000_init_builtins (void)
7789 V2SI_type_node = build_vector_type (intSI_type_node, 2);
7790 V2SF_type_node = build_vector_type (float_type_node, 2);
7791 V4HI_type_node = build_vector_type (intHI_type_node, 4);
7792 V4SI_type_node = build_vector_type (intSI_type_node, 4);
7793 V4SF_type_node = build_vector_type (float_type_node, 4);
7794 V8HI_type_node = build_vector_type (intHI_type_node, 8);
7795 V16QI_type_node = build_vector_type (intQI_type_node, 16);
7797 unsigned_V16QI_type_node = build_vector_type (unsigned_intQI_type_node, 16);
7798 unsigned_V8HI_type_node = build_vector_type (unsigned_intHI_type_node, 8);
7799 unsigned_V4SI_type_node = build_vector_type (unsigned_intSI_type_node, 4);
7801 opaque_V2SF_type_node = build_opaque_vector_type (float_type_node, 2);
7802 opaque_V2SI_type_node = build_opaque_vector_type (intSI_type_node, 2);
7803 opaque_p_V2SI_type_node = build_pointer_type (opaque_V2SI_type_node);
7804 opaque_V4SI_type_node = copy_node (V4SI_type_node);
7806 /* The 'vector bool ...' types must be kept distinct from 'vector unsigned ...'
7807 types, especially in C++ land. Similarly, 'vector pixel' is distinct from
7808 'vector unsigned short'. */
7810 bool_char_type_node = build_distinct_type_copy (unsigned_intQI_type_node);
7811 bool_short_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7812 bool_int_type_node = build_distinct_type_copy (unsigned_intSI_type_node);
7813 pixel_type_node = build_distinct_type_copy (unsigned_intHI_type_node);
7815 long_integer_type_internal_node = long_integer_type_node;
7816 long_unsigned_type_internal_node = long_unsigned_type_node;
7817 intQI_type_internal_node = intQI_type_node;
7818 uintQI_type_internal_node = unsigned_intQI_type_node;
7819 intHI_type_internal_node = intHI_type_node;
7820 uintHI_type_internal_node = unsigned_intHI_type_node;
7821 intSI_type_internal_node = intSI_type_node;
7822 uintSI_type_internal_node = unsigned_intSI_type_node;
7823 float_type_internal_node = float_type_node;
7824 void_type_internal_node = void_type_node;
7826 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7827 get_identifier ("__bool char"),
7828 bool_char_type_node));
7829 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7830 get_identifier ("__bool short"),
7831 bool_short_type_node));
7832 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7833 get_identifier ("__bool int"),
7834 bool_int_type_node));
7835 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7836 get_identifier ("__pixel"),
7839 bool_V16QI_type_node = build_vector_type (bool_char_type_node, 16);
7840 bool_V8HI_type_node = build_vector_type (bool_short_type_node, 8);
7841 bool_V4SI_type_node = build_vector_type (bool_int_type_node, 4);
7842 pixel_V8HI_type_node = build_vector_type (pixel_type_node, 8);
7844 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7845 get_identifier ("__vector unsigned char"),
7846 unsigned_V16QI_type_node));
7847 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7848 get_identifier ("__vector signed char"),
7850 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7851 get_identifier ("__vector __bool char"),
7852 bool_V16QI_type_node));
7854 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7855 get_identifier ("__vector unsigned short"),
7856 unsigned_V8HI_type_node));
7857 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7858 get_identifier ("__vector signed short"),
7860 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7861 get_identifier ("__vector __bool short"),
7862 bool_V8HI_type_node));
7864 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7865 get_identifier ("__vector unsigned int"),
7866 unsigned_V4SI_type_node));
7867 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7868 get_identifier ("__vector signed int"),
7870 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7871 get_identifier ("__vector __bool int"),
7872 bool_V4SI_type_node));
7874 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7875 get_identifier ("__vector float"),
7877 (*lang_hooks.decls.pushdecl) (build_decl (TYPE_DECL,
7878 get_identifier ("__vector __pixel"),
7879 pixel_V8HI_type_node));
7882 spe_init_builtins ();
7884 altivec_init_builtins ();
7885 if (TARGET_ALTIVEC || TARGET_SPE)
7886 rs6000_common_init_builtins ();
7889 /* Search through a set of builtins and enable the mask bits.
7890 DESC is an array of builtins.
7891 SIZE is the total number of builtins.
7892 START is the builtin enum at which to start.
7893 END is the builtin enum at which to end. */
7895 enable_mask_for_builtins (struct builtin_description *desc, int size,
7896 enum rs6000_builtins start,
7897 enum rs6000_builtins end)
7901 for (i = 0; i < size; ++i)
7902 if (desc[i].code == start)
7908 for (; i < size; ++i)
7910 /* Flip all the bits on. */
7911 desc[i].mask = target_flags;
7912 if (desc[i].code == end)
7918 spe_init_builtins (void)
7920 tree endlink = void_list_node;
7921 tree puint_type_node = build_pointer_type (unsigned_type_node);
7922 tree pushort_type_node = build_pointer_type (short_unsigned_type_node);
7923 struct builtin_description *d;
7926 tree v2si_ftype_4_v2si
7927 = build_function_type
7928 (opaque_V2SI_type_node,
7929 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7930 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7931 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7932 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7935 tree v2sf_ftype_4_v2sf
7936 = build_function_type
7937 (opaque_V2SF_type_node,
7938 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7939 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7940 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7941 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7944 tree int_ftype_int_v2si_v2si
7945 = build_function_type
7947 tree_cons (NULL_TREE, integer_type_node,
7948 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7949 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7952 tree int_ftype_int_v2sf_v2sf
7953 = build_function_type
7955 tree_cons (NULL_TREE, integer_type_node,
7956 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7957 tree_cons (NULL_TREE, opaque_V2SF_type_node,
7960 tree void_ftype_v2si_puint_int
7961 = build_function_type (void_type_node,
7962 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7963 tree_cons (NULL_TREE, puint_type_node,
7964 tree_cons (NULL_TREE,
7968 tree void_ftype_v2si_puint_char
7969 = build_function_type (void_type_node,
7970 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7971 tree_cons (NULL_TREE, puint_type_node,
7972 tree_cons (NULL_TREE,
7976 tree void_ftype_v2si_pv2si_int
7977 = build_function_type (void_type_node,
7978 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7979 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7980 tree_cons (NULL_TREE,
7984 tree void_ftype_v2si_pv2si_char
7985 = build_function_type (void_type_node,
7986 tree_cons (NULL_TREE, opaque_V2SI_type_node,
7987 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
7988 tree_cons (NULL_TREE,
7993 = build_function_type (void_type_node,
7994 tree_cons (NULL_TREE, integer_type_node, endlink));
7997 = build_function_type (integer_type_node, endlink);
7999 tree v2si_ftype_pv2si_int
8000 = build_function_type (opaque_V2SI_type_node,
8001 tree_cons (NULL_TREE, opaque_p_V2SI_type_node,
8002 tree_cons (NULL_TREE, integer_type_node,
8005 tree v2si_ftype_puint_int
8006 = build_function_type (opaque_V2SI_type_node,
8007 tree_cons (NULL_TREE, puint_type_node,
8008 tree_cons (NULL_TREE, integer_type_node,
8011 tree v2si_ftype_pushort_int
8012 = build_function_type (opaque_V2SI_type_node,
8013 tree_cons (NULL_TREE, pushort_type_node,
8014 tree_cons (NULL_TREE, integer_type_node,
8017 tree v2si_ftype_signed_char
8018 = build_function_type (opaque_V2SI_type_node,
8019 tree_cons (NULL_TREE, signed_char_type_node,
8022 /* The initialization of the simple binary and unary builtins is
8023 done in rs6000_common_init_builtins, but we have to enable the
8024 mask bits here manually because we have run out of `target_flags'
8025 bits. We really need to redesign this mask business. */
8027 enable_mask_for_builtins ((struct builtin_description *) bdesc_2arg,
8028 ARRAY_SIZE (bdesc_2arg),
8031 enable_mask_for_builtins ((struct builtin_description *) bdesc_1arg,
8032 ARRAY_SIZE (bdesc_1arg),
8034 SPE_BUILTIN_EVSUBFUSIAAW);
8035 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_predicates,
8036 ARRAY_SIZE (bdesc_spe_predicates),
8037 SPE_BUILTIN_EVCMPEQ,
8038 SPE_BUILTIN_EVFSTSTLT);
8039 enable_mask_for_builtins ((struct builtin_description *) bdesc_spe_evsel,
8040 ARRAY_SIZE (bdesc_spe_evsel),
8041 SPE_BUILTIN_EVSEL_CMPGTS,
8042 SPE_BUILTIN_EVSEL_FSTSTEQ);
8044 (*lang_hooks.decls.pushdecl)
8045 (build_decl (TYPE_DECL, get_identifier ("__ev64_opaque__"),
8046 opaque_V2SI_type_node));
8048 /* Initialize irregular SPE builtins. */
8050 def_builtin (target_flags, "__builtin_spe_mtspefscr", void_ftype_int, SPE_BUILTIN_MTSPEFSCR);
8051 def_builtin (target_flags, "__builtin_spe_mfspefscr", int_ftype_void, SPE_BUILTIN_MFSPEFSCR);
8052 def_builtin (target_flags, "__builtin_spe_evstddx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDDX);
8053 def_builtin (target_flags, "__builtin_spe_evstdhx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDHX);
8054 def_builtin (target_flags, "__builtin_spe_evstdwx", void_ftype_v2si_pv2si_int, SPE_BUILTIN_EVSTDWX);
8055 def_builtin (target_flags, "__builtin_spe_evstwhex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHEX);
8056 def_builtin (target_flags, "__builtin_spe_evstwhox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWHOX);
8057 def_builtin (target_flags, "__builtin_spe_evstwwex", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWEX);
8058 def_builtin (target_flags, "__builtin_spe_evstwwox", void_ftype_v2si_puint_int, SPE_BUILTIN_EVSTWWOX);
8059 def_builtin (target_flags, "__builtin_spe_evstdd", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDD);
8060 def_builtin (target_flags, "__builtin_spe_evstdh", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDH);
8061 def_builtin (target_flags, "__builtin_spe_evstdw", void_ftype_v2si_pv2si_char, SPE_BUILTIN_EVSTDW);
8062 def_builtin (target_flags, "__builtin_spe_evstwhe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHE);
8063 def_builtin (target_flags, "__builtin_spe_evstwho", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWHO);
8064 def_builtin (target_flags, "__builtin_spe_evstwwe", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWE);
8065 def_builtin (target_flags, "__builtin_spe_evstwwo", void_ftype_v2si_puint_char, SPE_BUILTIN_EVSTWWO);
8066 def_builtin (target_flags, "__builtin_spe_evsplatfi", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATFI);
8067 def_builtin (target_flags, "__builtin_spe_evsplati", v2si_ftype_signed_char, SPE_BUILTIN_EVSPLATI);
8070 def_builtin (target_flags, "__builtin_spe_evlddx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDDX);
8071 def_builtin (target_flags, "__builtin_spe_evldwx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDWX);
8072 def_builtin (target_flags, "__builtin_spe_evldhx", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDHX);
8073 def_builtin (target_flags, "__builtin_spe_evlwhex", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHEX);
8074 def_builtin (target_flags, "__builtin_spe_evlwhoux", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOUX);
8075 def_builtin (target_flags, "__builtin_spe_evlwhosx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOSX);
8076 def_builtin (target_flags, "__builtin_spe_evlwwsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLATX);
8077 def_builtin (target_flags, "__builtin_spe_evlwhsplatx", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLATX);
8078 def_builtin (target_flags, "__builtin_spe_evlhhesplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLATX);
8079 def_builtin (target_flags, "__builtin_spe_evlhhousplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLATX);
8080 def_builtin (target_flags, "__builtin_spe_evlhhossplatx", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLATX);
8081 def_builtin (target_flags, "__builtin_spe_evldd", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDD);
8082 def_builtin (target_flags, "__builtin_spe_evldw", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDW);
8083 def_builtin (target_flags, "__builtin_spe_evldh", v2si_ftype_pv2si_int, SPE_BUILTIN_EVLDH);
8084 def_builtin (target_flags, "__builtin_spe_evlhhesplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHESPLAT);
8085 def_builtin (target_flags, "__builtin_spe_evlhhossplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOSSPLAT);
8086 def_builtin (target_flags, "__builtin_spe_evlhhousplat", v2si_ftype_pushort_int, SPE_BUILTIN_EVLHHOUSPLAT);
8087 def_builtin (target_flags, "__builtin_spe_evlwhe", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHE);
8088 def_builtin (target_flags, "__builtin_spe_evlwhos", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOS);
8089 def_builtin (target_flags, "__builtin_spe_evlwhou", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHOU);
8090 def_builtin (target_flags, "__builtin_spe_evlwhsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWHSPLAT);
8091 def_builtin (target_flags, "__builtin_spe_evlwwsplat", v2si_ftype_puint_int, SPE_BUILTIN_EVLWWSPLAT);
8094 d = (struct builtin_description *) bdesc_spe_predicates;
8095 for (i = 0; i < ARRAY_SIZE (bdesc_spe_predicates); ++i, d++)
8099 switch (insn_data[d->icode].operand[1].mode)
8102 type = int_ftype_int_v2si_v2si;
8105 type = int_ftype_int_v2sf_v2sf;
8111 def_builtin (d->mask, d->name, type, d->code);
8114 /* Evsel predicates. */
8115 d = (struct builtin_description *) bdesc_spe_evsel;
8116 for (i = 0; i < ARRAY_SIZE (bdesc_spe_evsel); ++i, d++)
8120 switch (insn_data[d->icode].operand[1].mode)
8123 type = v2si_ftype_4_v2si;
8126 type = v2sf_ftype_4_v2sf;
8132 def_builtin (d->mask, d->name, type, d->code);
8137 altivec_init_builtins (void)
8139 struct builtin_description *d;
8140 struct builtin_description_predicates *dp;
8144 tree pfloat_type_node = build_pointer_type (float_type_node);
8145 tree pint_type_node = build_pointer_type (integer_type_node);
8146 tree pshort_type_node = build_pointer_type (short_integer_type_node);
8147 tree pchar_type_node = build_pointer_type (char_type_node);
8149 tree pvoid_type_node = build_pointer_type (void_type_node);
8151 tree pcfloat_type_node = build_pointer_type (build_qualified_type (float_type_node, TYPE_QUAL_CONST));
8152 tree pcint_type_node = build_pointer_type (build_qualified_type (integer_type_node, TYPE_QUAL_CONST));
8153 tree pcshort_type_node = build_pointer_type (build_qualified_type (short_integer_type_node, TYPE_QUAL_CONST));
8154 tree pcchar_type_node = build_pointer_type (build_qualified_type (char_type_node, TYPE_QUAL_CONST));
8156 tree pcvoid_type_node = build_pointer_type (build_qualified_type (void_type_node, TYPE_QUAL_CONST));
8158 tree int_ftype_opaque
8159 = build_function_type_list (integer_type_node,
8160 opaque_V4SI_type_node, NULL_TREE);
8162 tree opaque_ftype_opaque_int
8163 = build_function_type_list (opaque_V4SI_type_node,
8164 opaque_V4SI_type_node, integer_type_node, NULL_TREE);
8165 tree opaque_ftype_opaque_opaque_int
8166 = build_function_type_list (opaque_V4SI_type_node,
8167 opaque_V4SI_type_node, opaque_V4SI_type_node,
8168 integer_type_node, NULL_TREE);
8169 tree int_ftype_int_opaque_opaque
8170 = build_function_type_list (integer_type_node,
8171 integer_type_node, opaque_V4SI_type_node,
8172 opaque_V4SI_type_node, NULL_TREE);
8173 tree int_ftype_int_v4si_v4si
8174 = build_function_type_list (integer_type_node,
8175 integer_type_node, V4SI_type_node,
8176 V4SI_type_node, NULL_TREE);
8177 tree v4sf_ftype_pcfloat
8178 = build_function_type_list (V4SF_type_node, pcfloat_type_node, NULL_TREE);
8179 tree void_ftype_pfloat_v4sf
8180 = build_function_type_list (void_type_node,
8181 pfloat_type_node, V4SF_type_node, NULL_TREE);
8182 tree v4si_ftype_pcint
8183 = build_function_type_list (V4SI_type_node, pcint_type_node, NULL_TREE);
8184 tree void_ftype_pint_v4si
8185 = build_function_type_list (void_type_node,
8186 pint_type_node, V4SI_type_node, NULL_TREE);
8187 tree v8hi_ftype_pcshort
8188 = build_function_type_list (V8HI_type_node, pcshort_type_node, NULL_TREE);
8189 tree void_ftype_pshort_v8hi
8190 = build_function_type_list (void_type_node,
8191 pshort_type_node, V8HI_type_node, NULL_TREE);
8192 tree v16qi_ftype_pcchar
8193 = build_function_type_list (V16QI_type_node, pcchar_type_node, NULL_TREE);
8194 tree void_ftype_pchar_v16qi
8195 = build_function_type_list (void_type_node,
8196 pchar_type_node, V16QI_type_node, NULL_TREE);
8197 tree void_ftype_v4si
8198 = build_function_type_list (void_type_node, V4SI_type_node, NULL_TREE);
8199 tree v8hi_ftype_void
8200 = build_function_type (V8HI_type_node, void_list_node);
8201 tree void_ftype_void
8202 = build_function_type (void_type_node, void_list_node);
8204 = build_function_type_list (void_type_node, integer_type_node, NULL_TREE);
8206 tree opaque_ftype_long_pcvoid
8207 = build_function_type_list (opaque_V4SI_type_node,
8208 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8209 tree v16qi_ftype_long_pcvoid
8210 = build_function_type_list (V16QI_type_node,
8211 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8212 tree v8hi_ftype_long_pcvoid
8213 = build_function_type_list (V8HI_type_node,
8214 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8215 tree v4si_ftype_long_pcvoid
8216 = build_function_type_list (V4SI_type_node,
8217 long_integer_type_node, pcvoid_type_node, NULL_TREE);
8219 tree void_ftype_opaque_long_pvoid
8220 = build_function_type_list (void_type_node,
8221 opaque_V4SI_type_node, long_integer_type_node,
8222 pvoid_type_node, NULL_TREE);
8223 tree void_ftype_v4si_long_pvoid
8224 = build_function_type_list (void_type_node,
8225 V4SI_type_node, long_integer_type_node,
8226 pvoid_type_node, NULL_TREE);
8227 tree void_ftype_v16qi_long_pvoid
8228 = build_function_type_list (void_type_node,
8229 V16QI_type_node, long_integer_type_node,
8230 pvoid_type_node, NULL_TREE);
8231 tree void_ftype_v8hi_long_pvoid
8232 = build_function_type_list (void_type_node,
8233 V8HI_type_node, long_integer_type_node,
8234 pvoid_type_node, NULL_TREE);
8235 tree int_ftype_int_v8hi_v8hi
8236 = build_function_type_list (integer_type_node,
8237 integer_type_node, V8HI_type_node,
8238 V8HI_type_node, NULL_TREE);
8239 tree int_ftype_int_v16qi_v16qi
8240 = build_function_type_list (integer_type_node,
8241 integer_type_node, V16QI_type_node,
8242 V16QI_type_node, NULL_TREE);
8243 tree int_ftype_int_v4sf_v4sf
8244 = build_function_type_list (integer_type_node,
8245 integer_type_node, V4SF_type_node,
8246 V4SF_type_node, NULL_TREE);
8247 tree v4si_ftype_v4si
8248 = build_function_type_list (V4SI_type_node, V4SI_type_node, NULL_TREE);
8249 tree v8hi_ftype_v8hi
8250 = build_function_type_list (V8HI_type_node, V8HI_type_node, NULL_TREE);
8251 tree v16qi_ftype_v16qi
8252 = build_function_type_list (V16QI_type_node, V16QI_type_node, NULL_TREE);
8253 tree v4sf_ftype_v4sf
8254 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8255 tree void_ftype_pcvoid_int_int
8256 = build_function_type_list (void_type_node,
8257 pcvoid_type_node, integer_type_node,
8258 integer_type_node, NULL_TREE);
8260 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4sf", v4sf_ftype_pcfloat,
8261 ALTIVEC_BUILTIN_LD_INTERNAL_4sf);
8262 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4sf", void_ftype_pfloat_v4sf,
8263 ALTIVEC_BUILTIN_ST_INTERNAL_4sf);
8264 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_4si", v4si_ftype_pcint,
8265 ALTIVEC_BUILTIN_LD_INTERNAL_4si);
8266 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_4si", void_ftype_pint_v4si,
8267 ALTIVEC_BUILTIN_ST_INTERNAL_4si);
8268 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_8hi", v8hi_ftype_pcshort,
8269 ALTIVEC_BUILTIN_LD_INTERNAL_8hi);
8270 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_8hi", void_ftype_pshort_v8hi,
8271 ALTIVEC_BUILTIN_ST_INTERNAL_8hi);
8272 def_builtin (MASK_ALTIVEC, "__builtin_altivec_ld_internal_16qi", v16qi_ftype_pcchar,
8273 ALTIVEC_BUILTIN_LD_INTERNAL_16qi);
8274 def_builtin (MASK_ALTIVEC, "__builtin_altivec_st_internal_16qi", void_ftype_pchar_v16qi,
8275 ALTIVEC_BUILTIN_ST_INTERNAL_16qi);
8276 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mtvscr", void_ftype_v4si, ALTIVEC_BUILTIN_MTVSCR);
8277 def_builtin (MASK_ALTIVEC, "__builtin_altivec_mfvscr", v8hi_ftype_void, ALTIVEC_BUILTIN_MFVSCR);
8278 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dssall", void_ftype_void, ALTIVEC_BUILTIN_DSSALL);
8279 def_builtin (MASK_ALTIVEC, "__builtin_altivec_dss", void_ftype_int, ALTIVEC_BUILTIN_DSS);
8280 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSL);
8281 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVSR);
8282 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEBX);
8283 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEHX);
8284 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVEWX);
8285 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvxl", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVXL);
8286 def_builtin (MASK_ALTIVEC, "__builtin_altivec_lvx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_LVX);
8287 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVX);
8288 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvewx", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVEWX);
8289 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvxl", void_ftype_v4si_long_pvoid, ALTIVEC_BUILTIN_STVXL);
8290 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvebx", void_ftype_v16qi_long_pvoid, ALTIVEC_BUILTIN_STVEBX);
8291 def_builtin (MASK_ALTIVEC, "__builtin_altivec_stvehx", void_ftype_v8hi_long_pvoid, ALTIVEC_BUILTIN_STVEHX);
8292 def_builtin (MASK_ALTIVEC, "__builtin_vec_ld", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LD);
8293 def_builtin (MASK_ALTIVEC, "__builtin_vec_lde", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDE);
8294 def_builtin (MASK_ALTIVEC, "__builtin_vec_ldl", opaque_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LDL);
8295 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsl", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSL);
8296 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvsr", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVSR);
8297 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvebx", v16qi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEBX);
8298 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvehx", v8hi_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEHX);
8299 def_builtin (MASK_ALTIVEC, "__builtin_vec_lvewx", v4si_ftype_long_pcvoid, ALTIVEC_BUILTIN_VEC_LVEWX);
8300 def_builtin (MASK_ALTIVEC, "__builtin_vec_st", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_ST);
8301 def_builtin (MASK_ALTIVEC, "__builtin_vec_ste", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STE);
8302 def_builtin (MASK_ALTIVEC, "__builtin_vec_stl", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STL);
8303 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvewx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEWX);
8304 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvebx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEBX);
8305 def_builtin (MASK_ALTIVEC, "__builtin_vec_stvehx", void_ftype_opaque_long_pvoid, ALTIVEC_BUILTIN_VEC_STVEHX);
8307 def_builtin (MASK_ALTIVEC, "__builtin_vec_step", int_ftype_opaque, ALTIVEC_BUILTIN_VEC_STEP);
8309 def_builtin (MASK_ALTIVEC, "__builtin_vec_sld", opaque_ftype_opaque_opaque_int, ALTIVEC_BUILTIN_VEC_SLD);
8310 def_builtin (MASK_ALTIVEC, "__builtin_vec_splat", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_SPLAT);
8311 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltw", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTW);
8312 def_builtin (MASK_ALTIVEC, "__builtin_vec_vsplth", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTH);
8313 def_builtin (MASK_ALTIVEC, "__builtin_vec_vspltb", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VSPLTB);
8314 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctf", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTF);
8315 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfsx", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFSX);
8316 def_builtin (MASK_ALTIVEC, "__builtin_vec_vcfux", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_VCFUX);
8317 def_builtin (MASK_ALTIVEC, "__builtin_vec_cts", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTS);
8318 def_builtin (MASK_ALTIVEC, "__builtin_vec_ctu", opaque_ftype_opaque_int, ALTIVEC_BUILTIN_VEC_CTU);
8320 /* Add the DST variants. */
8321 d = (struct builtin_description *) bdesc_dst;
8322 for (i = 0; i < ARRAY_SIZE (bdesc_dst); i++, d++)
8323 def_builtin (d->mask, d->name, void_ftype_pcvoid_int_int, d->code);
8325 /* Initialize the predicates. */
8326 dp = (struct builtin_description_predicates *) bdesc_altivec_preds;
8327 for (i = 0; i < ARRAY_SIZE (bdesc_altivec_preds); i++, dp++)
8329 enum machine_mode mode1;
8331 bool is_overloaded = dp->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8332 && dp->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8337 mode1 = insn_data[dp->icode].operand[1].mode;
8342 type = int_ftype_int_opaque_opaque;
8345 type = int_ftype_int_v4si_v4si;
8348 type = int_ftype_int_v8hi_v8hi;
8351 type = int_ftype_int_v16qi_v16qi;
8354 type = int_ftype_int_v4sf_v4sf;
8360 def_builtin (dp->mask, dp->name, type, dp->code);
8363 /* Initialize the abs* operators. */
8364 d = (struct builtin_description *) bdesc_abs;
8365 for (i = 0; i < ARRAY_SIZE (bdesc_abs); i++, d++)
8367 enum machine_mode mode0;
8370 mode0 = insn_data[d->icode].operand[0].mode;
8375 type = v4si_ftype_v4si;
8378 type = v8hi_ftype_v8hi;
8381 type = v16qi_ftype_v16qi;
8384 type = v4sf_ftype_v4sf;
8390 def_builtin (d->mask, d->name, type, d->code);
8397 /* Initialize target builtin that implements
8398 targetm.vectorize.builtin_mask_for_load. */
8400 decl = lang_hooks.builtin_function ("__builtin_altivec_mask_for_load",
8401 v16qi_ftype_long_pcvoid,
8402 ALTIVEC_BUILTIN_MASK_FOR_LOAD,
8404 tree_cons (get_identifier ("const"),
8405 NULL_TREE, NULL_TREE));
8406 /* Record the decl. Will be used by rs6000_builtin_mask_for_load. */
8407 altivec_builtin_mask_for_load = decl;
8410 /* Access to the vec_init patterns. */
8411 ftype = build_function_type_list (V4SI_type_node, integer_type_node,
8412 integer_type_node, integer_type_node,
8413 integer_type_node, NULL_TREE);
8414 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4si", ftype,
8415 ALTIVEC_BUILTIN_VEC_INIT_V4SI);
8417 ftype = build_function_type_list (V8HI_type_node, short_integer_type_node,
8418 short_integer_type_node,
8419 short_integer_type_node,
8420 short_integer_type_node,
8421 short_integer_type_node,
8422 short_integer_type_node,
8423 short_integer_type_node,
8424 short_integer_type_node, NULL_TREE);
8425 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v8hi", ftype,
8426 ALTIVEC_BUILTIN_VEC_INIT_V8HI);
8428 ftype = build_function_type_list (V16QI_type_node, char_type_node,
8429 char_type_node, char_type_node,
8430 char_type_node, char_type_node,
8431 char_type_node, char_type_node,
8432 char_type_node, char_type_node,
8433 char_type_node, char_type_node,
8434 char_type_node, char_type_node,
8435 char_type_node, char_type_node,
8436 char_type_node, NULL_TREE);
8437 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v16qi", ftype,
8438 ALTIVEC_BUILTIN_VEC_INIT_V16QI);
8440 ftype = build_function_type_list (V4SF_type_node, float_type_node,
8441 float_type_node, float_type_node,
8442 float_type_node, NULL_TREE);
8443 def_builtin (MASK_ALTIVEC, "__builtin_vec_init_v4sf", ftype,
8444 ALTIVEC_BUILTIN_VEC_INIT_V4SF);
8446 /* Access to the vec_set patterns. */
8447 ftype = build_function_type_list (V4SI_type_node, V4SI_type_node,
8449 integer_type_node, NULL_TREE);
8450 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4si", ftype,
8451 ALTIVEC_BUILTIN_VEC_SET_V4SI);
8453 ftype = build_function_type_list (V8HI_type_node, V8HI_type_node,
8455 integer_type_node, NULL_TREE);
8456 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v8hi", ftype,
8457 ALTIVEC_BUILTIN_VEC_SET_V8HI);
8459 ftype = build_function_type_list (V8HI_type_node, V16QI_type_node,
8461 integer_type_node, NULL_TREE);
8462 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v16qi", ftype,
8463 ALTIVEC_BUILTIN_VEC_SET_V16QI);
8465 ftype = build_function_type_list (V4SF_type_node, V4SF_type_node,
8467 integer_type_node, NULL_TREE);
8468 def_builtin (MASK_ALTIVEC, "__builtin_vec_set_v4sf", ftype,
8469 ALTIVEC_BUILTIN_VEC_SET_V4SF);
8471 /* Access to the vec_extract patterns. */
8472 ftype = build_function_type_list (intSI_type_node, V4SI_type_node,
8473 integer_type_node, NULL_TREE);
8474 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4si", ftype,
8475 ALTIVEC_BUILTIN_VEC_EXT_V4SI);
8477 ftype = build_function_type_list (intHI_type_node, V8HI_type_node,
8478 integer_type_node, NULL_TREE);
8479 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v8hi", ftype,
8480 ALTIVEC_BUILTIN_VEC_EXT_V8HI);
8482 ftype = build_function_type_list (intQI_type_node, V16QI_type_node,
8483 integer_type_node, NULL_TREE);
8484 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v16qi", ftype,
8485 ALTIVEC_BUILTIN_VEC_EXT_V16QI);
8487 ftype = build_function_type_list (float_type_node, V4SF_type_node,
8488 integer_type_node, NULL_TREE);
8489 def_builtin (MASK_ALTIVEC, "__builtin_vec_ext_v4sf", ftype,
8490 ALTIVEC_BUILTIN_VEC_EXT_V4SF);
8494 rs6000_common_init_builtins (void)
8496 struct builtin_description *d;
8499 tree v4sf_ftype_v4sf_v4sf_v16qi
8500 = build_function_type_list (V4SF_type_node,
8501 V4SF_type_node, V4SF_type_node,
8502 V16QI_type_node, NULL_TREE);
8503 tree v4si_ftype_v4si_v4si_v16qi
8504 = build_function_type_list (V4SI_type_node,
8505 V4SI_type_node, V4SI_type_node,
8506 V16QI_type_node, NULL_TREE);
8507 tree v8hi_ftype_v8hi_v8hi_v16qi
8508 = build_function_type_list (V8HI_type_node,
8509 V8HI_type_node, V8HI_type_node,
8510 V16QI_type_node, NULL_TREE);
8511 tree v16qi_ftype_v16qi_v16qi_v16qi
8512 = build_function_type_list (V16QI_type_node,
8513 V16QI_type_node, V16QI_type_node,
8514 V16QI_type_node, NULL_TREE);
8516 = build_function_type_list (V4SI_type_node, integer_type_node, NULL_TREE);
8518 = build_function_type_list (V8HI_type_node, integer_type_node, NULL_TREE);
8519 tree v16qi_ftype_int
8520 = build_function_type_list (V16QI_type_node, integer_type_node, NULL_TREE);
8521 tree v8hi_ftype_v16qi
8522 = build_function_type_list (V8HI_type_node, V16QI_type_node, NULL_TREE);
8523 tree v4sf_ftype_v4sf
8524 = build_function_type_list (V4SF_type_node, V4SF_type_node, NULL_TREE);
8526 tree v2si_ftype_v2si_v2si
8527 = build_function_type_list (opaque_V2SI_type_node,
8528 opaque_V2SI_type_node,
8529 opaque_V2SI_type_node, NULL_TREE);
8531 tree v2sf_ftype_v2sf_v2sf
8532 = build_function_type_list (opaque_V2SF_type_node,
8533 opaque_V2SF_type_node,
8534 opaque_V2SF_type_node, NULL_TREE);
8536 tree v2si_ftype_int_int
8537 = build_function_type_list (opaque_V2SI_type_node,
8538 integer_type_node, integer_type_node,
8541 tree opaque_ftype_opaque
8542 = build_function_type_list (opaque_V4SI_type_node,
8543 opaque_V4SI_type_node, NULL_TREE);
8545 tree v2si_ftype_v2si
8546 = build_function_type_list (opaque_V2SI_type_node,
8547 opaque_V2SI_type_node, NULL_TREE);
8549 tree v2sf_ftype_v2sf
8550 = build_function_type_list (opaque_V2SF_type_node,
8551 opaque_V2SF_type_node, NULL_TREE);
8553 tree v2sf_ftype_v2si
8554 = build_function_type_list (opaque_V2SF_type_node,
8555 opaque_V2SI_type_node, NULL_TREE);
8557 tree v2si_ftype_v2sf
8558 = build_function_type_list (opaque_V2SI_type_node,
8559 opaque_V2SF_type_node, NULL_TREE);
8561 tree v2si_ftype_v2si_char
8562 = build_function_type_list (opaque_V2SI_type_node,
8563 opaque_V2SI_type_node,
8564 char_type_node, NULL_TREE);
8566 tree v2si_ftype_int_char
8567 = build_function_type_list (opaque_V2SI_type_node,
8568 integer_type_node, char_type_node, NULL_TREE);
8570 tree v2si_ftype_char
8571 = build_function_type_list (opaque_V2SI_type_node,
8572 char_type_node, NULL_TREE);
8574 tree int_ftype_int_int
8575 = build_function_type_list (integer_type_node,
8576 integer_type_node, integer_type_node,
8579 tree opaque_ftype_opaque_opaque
8580 = build_function_type_list (opaque_V4SI_type_node,
8581 opaque_V4SI_type_node, opaque_V4SI_type_node, NULL_TREE);
8582 tree v4si_ftype_v4si_v4si
8583 = build_function_type_list (V4SI_type_node,
8584 V4SI_type_node, V4SI_type_node, NULL_TREE);
8585 tree v4sf_ftype_v4si_int
8586 = build_function_type_list (V4SF_type_node,
8587 V4SI_type_node, integer_type_node, NULL_TREE);
8588 tree v4si_ftype_v4sf_int
8589 = build_function_type_list (V4SI_type_node,
8590 V4SF_type_node, integer_type_node, NULL_TREE);
8591 tree v4si_ftype_v4si_int
8592 = build_function_type_list (V4SI_type_node,
8593 V4SI_type_node, integer_type_node, NULL_TREE);
8594 tree v8hi_ftype_v8hi_int
8595 = build_function_type_list (V8HI_type_node,
8596 V8HI_type_node, integer_type_node, NULL_TREE);
8597 tree v16qi_ftype_v16qi_int
8598 = build_function_type_list (V16QI_type_node,
8599 V16QI_type_node, integer_type_node, NULL_TREE);
8600 tree v16qi_ftype_v16qi_v16qi_int
8601 = build_function_type_list (V16QI_type_node,
8602 V16QI_type_node, V16QI_type_node,
8603 integer_type_node, NULL_TREE);
8604 tree v8hi_ftype_v8hi_v8hi_int
8605 = build_function_type_list (V8HI_type_node,
8606 V8HI_type_node, V8HI_type_node,
8607 integer_type_node, NULL_TREE);
8608 tree v4si_ftype_v4si_v4si_int
8609 = build_function_type_list (V4SI_type_node,
8610 V4SI_type_node, V4SI_type_node,
8611 integer_type_node, NULL_TREE);
8612 tree v4sf_ftype_v4sf_v4sf_int
8613 = build_function_type_list (V4SF_type_node,
8614 V4SF_type_node, V4SF_type_node,
8615 integer_type_node, NULL_TREE);
8616 tree v4sf_ftype_v4sf_v4sf
8617 = build_function_type_list (V4SF_type_node,
8618 V4SF_type_node, V4SF_type_node, NULL_TREE);
8619 tree opaque_ftype_opaque_opaque_opaque
8620 = build_function_type_list (opaque_V4SI_type_node,
8621 opaque_V4SI_type_node, opaque_V4SI_type_node,
8622 opaque_V4SI_type_node, NULL_TREE);
8623 tree v4sf_ftype_v4sf_v4sf_v4si
8624 = build_function_type_list (V4SF_type_node,
8625 V4SF_type_node, V4SF_type_node,
8626 V4SI_type_node, NULL_TREE);
8627 tree v4sf_ftype_v4sf_v4sf_v4sf
8628 = build_function_type_list (V4SF_type_node,
8629 V4SF_type_node, V4SF_type_node,
8630 V4SF_type_node, NULL_TREE);
8631 tree v4si_ftype_v4si_v4si_v4si
8632 = build_function_type_list (V4SI_type_node,
8633 V4SI_type_node, V4SI_type_node,
8634 V4SI_type_node, NULL_TREE);
8635 tree v8hi_ftype_v8hi_v8hi
8636 = build_function_type_list (V8HI_type_node,
8637 V8HI_type_node, V8HI_type_node, NULL_TREE);
8638 tree v8hi_ftype_v8hi_v8hi_v8hi
8639 = build_function_type_list (V8HI_type_node,
8640 V8HI_type_node, V8HI_type_node,
8641 V8HI_type_node, NULL_TREE);
8642 tree v4si_ftype_v8hi_v8hi_v4si
8643 = build_function_type_list (V4SI_type_node,
8644 V8HI_type_node, V8HI_type_node,
8645 V4SI_type_node, NULL_TREE);
8646 tree v4si_ftype_v16qi_v16qi_v4si
8647 = build_function_type_list (V4SI_type_node,
8648 V16QI_type_node, V16QI_type_node,
8649 V4SI_type_node, NULL_TREE);
8650 tree v16qi_ftype_v16qi_v16qi
8651 = build_function_type_list (V16QI_type_node,
8652 V16QI_type_node, V16QI_type_node, NULL_TREE);
8653 tree v4si_ftype_v4sf_v4sf
8654 = build_function_type_list (V4SI_type_node,
8655 V4SF_type_node, V4SF_type_node, NULL_TREE);
8656 tree v8hi_ftype_v16qi_v16qi
8657 = build_function_type_list (V8HI_type_node,
8658 V16QI_type_node, V16QI_type_node, NULL_TREE);
8659 tree v4si_ftype_v8hi_v8hi
8660 = build_function_type_list (V4SI_type_node,
8661 V8HI_type_node, V8HI_type_node, NULL_TREE);
8662 tree v8hi_ftype_v4si_v4si
8663 = build_function_type_list (V8HI_type_node,
8664 V4SI_type_node, V4SI_type_node, NULL_TREE);
8665 tree v16qi_ftype_v8hi_v8hi
8666 = build_function_type_list (V16QI_type_node,
8667 V8HI_type_node, V8HI_type_node, NULL_TREE);
8668 tree v4si_ftype_v16qi_v4si
8669 = build_function_type_list (V4SI_type_node,
8670 V16QI_type_node, V4SI_type_node, NULL_TREE);
8671 tree v4si_ftype_v16qi_v16qi
8672 = build_function_type_list (V4SI_type_node,
8673 V16QI_type_node, V16QI_type_node, NULL_TREE);
8674 tree v4si_ftype_v8hi_v4si
8675 = build_function_type_list (V4SI_type_node,
8676 V8HI_type_node, V4SI_type_node, NULL_TREE);
8677 tree v4si_ftype_v8hi
8678 = build_function_type_list (V4SI_type_node, V8HI_type_node, NULL_TREE);
8679 tree int_ftype_v4si_v4si
8680 = build_function_type_list (integer_type_node,
8681 V4SI_type_node, V4SI_type_node, NULL_TREE);
8682 tree int_ftype_v4sf_v4sf
8683 = build_function_type_list (integer_type_node,
8684 V4SF_type_node, V4SF_type_node, NULL_TREE);
8685 tree int_ftype_v16qi_v16qi
8686 = build_function_type_list (integer_type_node,
8687 V16QI_type_node, V16QI_type_node, NULL_TREE);
8688 tree int_ftype_v8hi_v8hi
8689 = build_function_type_list (integer_type_node,
8690 V8HI_type_node, V8HI_type_node, NULL_TREE);
8692 /* Add the simple ternary operators. */
8693 d = (struct builtin_description *) bdesc_3arg;
8694 for (i = 0; i < ARRAY_SIZE (bdesc_3arg); i++, d++)
8696 enum machine_mode mode0, mode1, mode2, mode3;
8698 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8699 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8710 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8713 mode0 = insn_data[d->icode].operand[0].mode;
8714 mode1 = insn_data[d->icode].operand[1].mode;
8715 mode2 = insn_data[d->icode].operand[2].mode;
8716 mode3 = insn_data[d->icode].operand[3].mode;
8719 /* When all four are of the same mode. */
8720 if (mode0 == mode1 && mode1 == mode2 && mode2 == mode3)
8725 type = opaque_ftype_opaque_opaque_opaque;
8728 type = v4si_ftype_v4si_v4si_v4si;
8731 type = v4sf_ftype_v4sf_v4sf_v4sf;
8734 type = v8hi_ftype_v8hi_v8hi_v8hi;
8737 type = v16qi_ftype_v16qi_v16qi_v16qi;
8743 else if (mode0 == mode1 && mode1 == mode2 && mode3 == V16QImode)
8748 type = v4si_ftype_v4si_v4si_v16qi;
8751 type = v4sf_ftype_v4sf_v4sf_v16qi;
8754 type = v8hi_ftype_v8hi_v8hi_v16qi;
8757 type = v16qi_ftype_v16qi_v16qi_v16qi;
8763 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode
8764 && mode3 == V4SImode)
8765 type = v4si_ftype_v16qi_v16qi_v4si;
8766 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode
8767 && mode3 == V4SImode)
8768 type = v4si_ftype_v8hi_v8hi_v4si;
8769 else if (mode0 == V4SFmode && mode1 == V4SFmode && mode2 == V4SFmode
8770 && mode3 == V4SImode)
8771 type = v4sf_ftype_v4sf_v4sf_v4si;
8773 /* vchar, vchar, vchar, 4 bit literal. */
8774 else if (mode0 == V16QImode && mode1 == mode0 && mode2 == mode0
8776 type = v16qi_ftype_v16qi_v16qi_int;
8778 /* vshort, vshort, vshort, 4 bit literal. */
8779 else if (mode0 == V8HImode && mode1 == mode0 && mode2 == mode0
8781 type = v8hi_ftype_v8hi_v8hi_int;
8783 /* vint, vint, vint, 4 bit literal. */
8784 else if (mode0 == V4SImode && mode1 == mode0 && mode2 == mode0
8786 type = v4si_ftype_v4si_v4si_int;
8788 /* vfloat, vfloat, vfloat, 4 bit literal. */
8789 else if (mode0 == V4SFmode && mode1 == mode0 && mode2 == mode0
8791 type = v4sf_ftype_v4sf_v4sf_int;
8796 def_builtin (d->mask, d->name, type, d->code);
8799 /* Add the simple binary operators. */
8800 d = (struct builtin_description *) bdesc_2arg;
8801 for (i = 0; i < ARRAY_SIZE (bdesc_2arg); i++, d++)
8803 enum machine_mode mode0, mode1, mode2;
8805 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8806 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8816 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8819 mode0 = insn_data[d->icode].operand[0].mode;
8820 mode1 = insn_data[d->icode].operand[1].mode;
8821 mode2 = insn_data[d->icode].operand[2].mode;
8824 /* When all three operands are of the same mode. */
8825 if (mode0 == mode1 && mode1 == mode2)
8830 type = opaque_ftype_opaque_opaque;
8833 type = v4sf_ftype_v4sf_v4sf;
8836 type = v4si_ftype_v4si_v4si;
8839 type = v16qi_ftype_v16qi_v16qi;
8842 type = v8hi_ftype_v8hi_v8hi;
8845 type = v2si_ftype_v2si_v2si;
8848 type = v2sf_ftype_v2sf_v2sf;
8851 type = int_ftype_int_int;
8858 /* A few other combos we really don't want to do manually. */
8860 /* vint, vfloat, vfloat. */
8861 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == V4SFmode)
8862 type = v4si_ftype_v4sf_v4sf;
8864 /* vshort, vchar, vchar. */
8865 else if (mode0 == V8HImode && mode1 == V16QImode && mode2 == V16QImode)
8866 type = v8hi_ftype_v16qi_v16qi;
8868 /* vint, vshort, vshort. */
8869 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V8HImode)
8870 type = v4si_ftype_v8hi_v8hi;
8872 /* vshort, vint, vint. */
8873 else if (mode0 == V8HImode && mode1 == V4SImode && mode2 == V4SImode)
8874 type = v8hi_ftype_v4si_v4si;
8876 /* vchar, vshort, vshort. */
8877 else if (mode0 == V16QImode && mode1 == V8HImode && mode2 == V8HImode)
8878 type = v16qi_ftype_v8hi_v8hi;
8880 /* vint, vchar, vint. */
8881 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V4SImode)
8882 type = v4si_ftype_v16qi_v4si;
8884 /* vint, vchar, vchar. */
8885 else if (mode0 == V4SImode && mode1 == V16QImode && mode2 == V16QImode)
8886 type = v4si_ftype_v16qi_v16qi;
8888 /* vint, vshort, vint. */
8889 else if (mode0 == V4SImode && mode1 == V8HImode && mode2 == V4SImode)
8890 type = v4si_ftype_v8hi_v4si;
8892 /* vint, vint, 5 bit literal. */
8893 else if (mode0 == V4SImode && mode1 == V4SImode && mode2 == QImode)
8894 type = v4si_ftype_v4si_int;
8896 /* vshort, vshort, 5 bit literal. */
8897 else if (mode0 == V8HImode && mode1 == V8HImode && mode2 == QImode)
8898 type = v8hi_ftype_v8hi_int;
8900 /* vchar, vchar, 5 bit literal. */
8901 else if (mode0 == V16QImode && mode1 == V16QImode && mode2 == QImode)
8902 type = v16qi_ftype_v16qi_int;
8904 /* vfloat, vint, 5 bit literal. */
8905 else if (mode0 == V4SFmode && mode1 == V4SImode && mode2 == QImode)
8906 type = v4sf_ftype_v4si_int;
8908 /* vint, vfloat, 5 bit literal. */
8909 else if (mode0 == V4SImode && mode1 == V4SFmode && mode2 == QImode)
8910 type = v4si_ftype_v4sf_int;
8912 else if (mode0 == V2SImode && mode1 == SImode && mode2 == SImode)
8913 type = v2si_ftype_int_int;
8915 else if (mode0 == V2SImode && mode1 == V2SImode && mode2 == QImode)
8916 type = v2si_ftype_v2si_char;
8918 else if (mode0 == V2SImode && mode1 == SImode && mode2 == QImode)
8919 type = v2si_ftype_int_char;
8924 gcc_assert (mode0 == SImode);
8928 type = int_ftype_v4si_v4si;
8931 type = int_ftype_v4sf_v4sf;
8934 type = int_ftype_v16qi_v16qi;
8937 type = int_ftype_v8hi_v8hi;
8944 def_builtin (d->mask, d->name, type, d->code);
8947 /* Add the simple unary operators. */
8948 d = (struct builtin_description *) bdesc_1arg;
8949 for (i = 0; i < ARRAY_SIZE (bdesc_1arg); i++, d++)
8951 enum machine_mode mode0, mode1;
8953 bool is_overloaded = d->code >= ALTIVEC_BUILTIN_OVERLOADED_FIRST
8954 && d->code <= ALTIVEC_BUILTIN_OVERLOADED_LAST;
8963 if (d->name == 0 || d->icode == CODE_FOR_nothing)
8966 mode0 = insn_data[d->icode].operand[0].mode;
8967 mode1 = insn_data[d->icode].operand[1].mode;
8970 if (mode0 == V4SImode && mode1 == QImode)
8971 type = v4si_ftype_int;
8972 else if (mode0 == V8HImode && mode1 == QImode)
8973 type = v8hi_ftype_int;
8974 else if (mode0 == V16QImode && mode1 == QImode)
8975 type = v16qi_ftype_int;
8976 else if (mode0 == VOIDmode && mode1 == VOIDmode)
8977 type = opaque_ftype_opaque;
8978 else if (mode0 == V4SFmode && mode1 == V4SFmode)
8979 type = v4sf_ftype_v4sf;
8980 else if (mode0 == V8HImode && mode1 == V16QImode)
8981 type = v8hi_ftype_v16qi;
8982 else if (mode0 == V4SImode && mode1 == V8HImode)
8983 type = v4si_ftype_v8hi;
8984 else if (mode0 == V2SImode && mode1 == V2SImode)
8985 type = v2si_ftype_v2si;
8986 else if (mode0 == V2SFmode && mode1 == V2SFmode)
8987 type = v2sf_ftype_v2sf;
8988 else if (mode0 == V2SFmode && mode1 == V2SImode)
8989 type = v2sf_ftype_v2si;
8990 else if (mode0 == V2SImode && mode1 == V2SFmode)
8991 type = v2si_ftype_v2sf;
8992 else if (mode0 == V2SImode && mode1 == QImode)
8993 type = v2si_ftype_char;
8997 def_builtin (d->mask, d->name, type, d->code);
9002 rs6000_init_libfuncs (void)
9004 if (!TARGET_HARD_FLOAT)
9007 if (DEFAULT_ABI != ABI_V4)
9009 if (TARGET_XCOFF && ! TARGET_POWER2 && ! TARGET_POWERPC)
9011 /* AIX library routines for float->int conversion. */
9012 set_conv_libfunc (sfix_optab, SImode, DFmode, "__itrunc");
9013 set_conv_libfunc (ufix_optab, SImode, DFmode, "__uitrunc");
9014 set_conv_libfunc (sfix_optab, SImode, TFmode, "_qitrunc");
9015 set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
9018 /* AIX/Darwin/64-bit Linux quad floating point routines. */
9019 if (!TARGET_XL_COMPAT)
9021 set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
9022 set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
9023 set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
9024 set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
9028 set_optab_libfunc (add_optab, TFmode, "_xlqadd");
9029 set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
9030 set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
9031 set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
9036 /* 32-bit SVR4 quad floating point routines. */
9038 set_optab_libfunc (add_optab, TFmode, "_q_add");
9039 set_optab_libfunc (sub_optab, TFmode, "_q_sub");
9040 set_optab_libfunc (neg_optab, TFmode, "_q_neg");
9041 set_optab_libfunc (smul_optab, TFmode, "_q_mul");
9042 set_optab_libfunc (sdiv_optab, TFmode, "_q_div");
9043 if (TARGET_PPC_GPOPT || TARGET_POWER2)
9044 set_optab_libfunc (sqrt_optab, TFmode, "_q_sqrt");
9046 set_optab_libfunc (eq_optab, TFmode, "_q_feq");
9047 set_optab_libfunc (ne_optab, TFmode, "_q_fne");
9048 set_optab_libfunc (gt_optab, TFmode, "_q_fgt");
9049 set_optab_libfunc (ge_optab, TFmode, "_q_fge");
9050 set_optab_libfunc (lt_optab, TFmode, "_q_flt");
9051 set_optab_libfunc (le_optab, TFmode, "_q_fle");
9053 set_conv_libfunc (sext_optab, TFmode, SFmode, "_q_stoq");
9054 set_conv_libfunc (sext_optab, TFmode, DFmode, "_q_dtoq");
9055 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_q_qtos");
9056 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_q_qtod");
9057 set_conv_libfunc (sfix_optab, SImode, TFmode, "_q_qtoi");
9058 set_conv_libfunc (ufix_optab, SImode, TFmode, "_q_qtou");
9059 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_q_itoq");
9064 /* Expand a block clear operation, and return 1 if successful. Return 0
9065 if we should let the compiler generate normal code.
9067 operands[0] is the destination
9068 operands[1] is the length
9069 operands[3] is the alignment */
9072 expand_block_clear (rtx operands[])
9074 rtx orig_dest = operands[0];
9075 rtx bytes_rtx = operands[1];
9076 rtx align_rtx = operands[3];
9077 bool constp = (GET_CODE (bytes_rtx) == CONST_INT);
9078 HOST_WIDE_INT align;
9079 HOST_WIDE_INT bytes;
9084 /* If this is not a fixed size move, just call memcpy */
9088 /* This must be a fixed size alignment */
9089 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9090 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9092 /* Anything to clear? */
9093 bytes = INTVAL (bytes_rtx);
9097 /* Use the builtin memset after a point, to avoid huge code bloat.
9098 When optimize_size, avoid any significant code bloat; calling
9099 memset is about 4 instructions, so allow for one instruction to
9100 load zero and three to do clearing. */
9101 if (TARGET_ALTIVEC && align >= 128)
9103 else if (TARGET_POWERPC64 && align >= 32)
9108 if (optimize_size && bytes > 3 * clear_step)
9110 if (! optimize_size && bytes > 8 * clear_step)
9113 for (offset = 0; bytes > 0; offset += clear_bytes, bytes -= clear_bytes)
9115 enum machine_mode mode = BLKmode;
9118 if (bytes >= 16 && TARGET_ALTIVEC && align >= 128)
9123 else if (bytes >= 8 && TARGET_POWERPC64
9124 /* 64-bit loads and stores require word-aligned
9126 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9131 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9132 { /* move 4 bytes */
9136 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9137 { /* move 2 bytes */
9141 else /* move 1 byte at a time */
9147 dest = adjust_address (orig_dest, mode, offset);
9149 emit_move_insn (dest, CONST0_RTX (mode));
9156 /* Expand a block move operation, and return 1 if successful. Return 0
9157 if we should let the compiler generate normal code.
9159 operands[0] is the destination
9160 operands[1] is the source
9161 operands[2] is the length
9162 operands[3] is the alignment */
9164 #define MAX_MOVE_REG 4
9167 expand_block_move (rtx operands[])
9169 rtx orig_dest = operands[0];
9170 rtx orig_src = operands[1];
9171 rtx bytes_rtx = operands[2];
9172 rtx align_rtx = operands[3];
9173 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
9178 rtx stores[MAX_MOVE_REG];
9181 /* If this is not a fixed size move, just call memcpy */
9185 /* This must be a fixed size alignment */
9186 gcc_assert (GET_CODE (align_rtx) == CONST_INT);
9187 align = INTVAL (align_rtx) * BITS_PER_UNIT;
9189 /* Anything to move? */
9190 bytes = INTVAL (bytes_rtx);
9194 /* store_one_arg depends on expand_block_move to handle at least the size of
9195 reg_parm_stack_space. */
9196 if (bytes > (TARGET_POWERPC64 ? 64 : 32))
9199 for (offset = 0; bytes > 0; offset += move_bytes, bytes -= move_bytes)
9202 rtx (*movmemsi) (rtx, rtx, rtx, rtx);
9203 rtx (*mov) (rtx, rtx);
9205 enum machine_mode mode = BLKmode;
9208 /* Altivec first, since it will be faster than a string move
9209 when it applies, and usually not significantly larger. */
9210 if (TARGET_ALTIVEC && bytes >= 16 && align >= 128)
9214 gen_func.mov = gen_movv4si;
9216 else if (TARGET_STRING
9217 && bytes > 24 /* move up to 32 bytes at a time */
9225 && ! fixed_regs[12])
9227 move_bytes = (bytes > 32) ? 32 : bytes;
9228 gen_func.movmemsi = gen_movmemsi_8reg;
9230 else if (TARGET_STRING
9231 && bytes > 16 /* move up to 24 bytes at a time */
9237 && ! fixed_regs[10])
9239 move_bytes = (bytes > 24) ? 24 : bytes;
9240 gen_func.movmemsi = gen_movmemsi_6reg;
9242 else if (TARGET_STRING
9243 && bytes > 8 /* move up to 16 bytes at a time */
9249 move_bytes = (bytes > 16) ? 16 : bytes;
9250 gen_func.movmemsi = gen_movmemsi_4reg;
9252 else if (bytes >= 8 && TARGET_POWERPC64
9253 /* 64-bit loads and stores require word-aligned
9255 && (align >= 64 || (!STRICT_ALIGNMENT && align >= 32)))
9259 gen_func.mov = gen_movdi;
9261 else if (TARGET_STRING && bytes > 4 && !TARGET_POWERPC64)
9262 { /* move up to 8 bytes at a time */
9263 move_bytes = (bytes > 8) ? 8 : bytes;
9264 gen_func.movmemsi = gen_movmemsi_2reg;
9266 else if (bytes >= 4 && (align >= 32 || !STRICT_ALIGNMENT))
9267 { /* move 4 bytes */
9270 gen_func.mov = gen_movsi;
9272 else if (bytes == 2 && (align >= 16 || !STRICT_ALIGNMENT))
9273 { /* move 2 bytes */
9276 gen_func.mov = gen_movhi;
9278 else if (TARGET_STRING && bytes > 1)
9279 { /* move up to 4 bytes at a time */
9280 move_bytes = (bytes > 4) ? 4 : bytes;
9281 gen_func.movmemsi = gen_movmemsi_1reg;
9283 else /* move 1 byte at a time */
9287 gen_func.mov = gen_movqi;
9290 src = adjust_address (orig_src, mode, offset);
9291 dest = adjust_address (orig_dest, mode, offset);
9293 if (mode != BLKmode)
9295 rtx tmp_reg = gen_reg_rtx (mode);
9297 emit_insn ((*gen_func.mov) (tmp_reg, src));
9298 stores[num_reg++] = (*gen_func.mov) (dest, tmp_reg);
9301 if (mode == BLKmode || num_reg >= MAX_MOVE_REG || bytes == move_bytes)
9304 for (i = 0; i < num_reg; i++)
9305 emit_insn (stores[i]);
9309 if (mode == BLKmode)
9311 /* Move the address into scratch registers. The movmemsi
9312 patterns require zero offset. */
9313 if (!REG_P (XEXP (src, 0)))
9315 rtx src_reg = copy_addr_to_reg (XEXP (src, 0));
9316 src = replace_equiv_address (src, src_reg);
9318 set_mem_size (src, GEN_INT (move_bytes));
9320 if (!REG_P (XEXP (dest, 0)))
9322 rtx dest_reg = copy_addr_to_reg (XEXP (dest, 0));
9323 dest = replace_equiv_address (dest, dest_reg);
9325 set_mem_size (dest, GEN_INT (move_bytes));
9327 emit_insn ((*gen_func.movmemsi) (dest, src,
9328 GEN_INT (move_bytes & 31),
9337 /* Return a string to perform a load_multiple operation.
9338 operands[0] is the vector.
9339 operands[1] is the source address.
9340 operands[2] is the first destination register. */
9343 rs6000_output_load_multiple (rtx operands[3])
9345 /* We have to handle the case where the pseudo used to contain the address
9346 is assigned to one of the output registers. */
9348 int words = XVECLEN (operands[0], 0);
9351 if (XVECLEN (operands[0], 0) == 1)
9352 return "{l|lwz} %2,0(%1)";
9354 for (i = 0; i < words; i++)
9355 if (refers_to_regno_p (REGNO (operands[2]) + i,
9356 REGNO (operands[2]) + i + 1, operands[1], 0))
9360 xop[0] = GEN_INT (4 * (words-1));
9361 xop[1] = operands[1];
9362 xop[2] = operands[2];
9363 output_asm_insn ("{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,%0(%1)", xop);
9368 xop[0] = GEN_INT (4 * (words-1));
9369 xop[1] = operands[1];
9370 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
9371 output_asm_insn ("{cal %1,4(%1)|addi %1,%1,4}\n\t{lsi|lswi} %2,%1,%0\n\t{l|lwz} %1,-4(%1)", xop);
9376 for (j = 0; j < words; j++)
9379 xop[0] = GEN_INT (j * 4);
9380 xop[1] = operands[1];
9381 xop[2] = gen_rtx_REG (SImode, REGNO (operands[2]) + j);
9382 output_asm_insn ("{l|lwz} %2,%0(%1)", xop);
9384 xop[0] = GEN_INT (i * 4);
9385 xop[1] = operands[1];
9386 output_asm_insn ("{l|lwz} %1,%0(%1)", xop);
9391 return "{lsi|lswi} %2,%1,%N0";
9395 /* A validation routine: say whether CODE, a condition code, and MODE
9396 match. The other alternatives either don't make sense or should
9397 never be generated. */
9400 validate_condition_mode (enum rtx_code code, enum machine_mode mode)
9402 gcc_assert ((GET_RTX_CLASS (code) == RTX_COMPARE
9403 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE)
9404 && GET_MODE_CLASS (mode) == MODE_CC);
9406 /* These don't make sense. */
9407 gcc_assert ((code != GT && code != LT && code != GE && code != LE)
9408 || mode != CCUNSmode);
9410 gcc_assert ((code != GTU && code != LTU && code != GEU && code != LEU)
9411 || mode == CCUNSmode);
9413 gcc_assert (mode == CCFPmode
9414 || (code != ORDERED && code != UNORDERED
9415 && code != UNEQ && code != LTGT
9416 && code != UNGT && code != UNLT
9417 && code != UNGE && code != UNLE));
9419 /* These should never be generated except for
9420 flag_finite_math_only. */
9421 gcc_assert (mode != CCFPmode
9422 || flag_finite_math_only
9423 || (code != LE && code != GE
9424 && code != UNEQ && code != LTGT
9425 && code != UNGT && code != UNLT));
9427 /* These are invalid; the information is not there. */
9428 gcc_assert (mode != CCEQmode || code == EQ || code == NE);
9432 /* Return 1 if ANDOP is a mask that has no bits on that are not in the
9433 mask required to convert the result of a rotate insn into a shift
9434 left insn of SHIFTOP bits. Both are known to be SImode CONST_INT. */
9437 includes_lshift_p (rtx shiftop, rtx andop)
9439 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9441 shift_mask <<= INTVAL (shiftop);
9443 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9446 /* Similar, but for right shift. */
9449 includes_rshift_p (rtx shiftop, rtx andop)
9451 unsigned HOST_WIDE_INT shift_mask = ~(unsigned HOST_WIDE_INT) 0;
9453 shift_mask >>= INTVAL (shiftop);
9455 return (INTVAL (andop) & 0xffffffff & ~shift_mask) == 0;
9458 /* Return 1 if ANDOP is a mask suitable for use with an rldic insn
9459 to perform a left shift. It must have exactly SHIFTOP least
9460 significant 0's, then one or more 1's, then zero or more 0's. */
9463 includes_rldic_lshift_p (rtx shiftop, rtx andop)
9465 if (GET_CODE (andop) == CONST_INT)
9467 HOST_WIDE_INT c, lsb, shift_mask;
9470 if (c == 0 || c == ~0)
9474 shift_mask <<= INTVAL (shiftop);
9476 /* Find the least significant one bit. */
9479 /* It must coincide with the LSB of the shift mask. */
9480 if (-lsb != shift_mask)
9483 /* Invert to look for the next transition (if any). */
9486 /* Remove the low group of ones (originally low group of zeros). */
9489 /* Again find the lsb, and check we have all 1's above. */
9493 else if (GET_CODE (andop) == CONST_DOUBLE
9494 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9496 HOST_WIDE_INT low, high, lsb;
9497 HOST_WIDE_INT shift_mask_low, shift_mask_high;
9499 low = CONST_DOUBLE_LOW (andop);
9500 if (HOST_BITS_PER_WIDE_INT < 64)
9501 high = CONST_DOUBLE_HIGH (andop);
9503 if ((low == 0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == 0))
9504 || (low == ~0 && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0)))
9507 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9509 shift_mask_high = ~0;
9510 if (INTVAL (shiftop) > 32)
9511 shift_mask_high <<= INTVAL (shiftop) - 32;
9515 if (-lsb != shift_mask_high || INTVAL (shiftop) < 32)
9522 return high == -lsb;
9525 shift_mask_low = ~0;
9526 shift_mask_low <<= INTVAL (shiftop);
9530 if (-lsb != shift_mask_low)
9533 if (HOST_BITS_PER_WIDE_INT < 64)
9538 if (HOST_BITS_PER_WIDE_INT < 64 && low == 0)
9541 return high == -lsb;
9545 return low == -lsb && (HOST_BITS_PER_WIDE_INT >= 64 || high == ~0);
9551 /* Return 1 if ANDOP is a mask suitable for use with an rldicr insn
9552 to perform a left shift. It must have SHIFTOP or more least
9553 significant 0's, with the remainder of the word 1's. */
9556 includes_rldicr_lshift_p (rtx shiftop, rtx andop)
9558 if (GET_CODE (andop) == CONST_INT)
9560 HOST_WIDE_INT c, lsb, shift_mask;
9563 shift_mask <<= INTVAL (shiftop);
9566 /* Find the least significant one bit. */
9569 /* It must be covered by the shift mask.
9570 This test also rejects c == 0. */
9571 if ((lsb & shift_mask) == 0)
9574 /* Check we have all 1's above the transition, and reject all 1's. */
9575 return c == -lsb && lsb != 1;
9577 else if (GET_CODE (andop) == CONST_DOUBLE
9578 && (GET_MODE (andop) == VOIDmode || GET_MODE (andop) == DImode))
9580 HOST_WIDE_INT low, lsb, shift_mask_low;
9582 low = CONST_DOUBLE_LOW (andop);
9584 if (HOST_BITS_PER_WIDE_INT < 64)
9586 HOST_WIDE_INT high, shift_mask_high;
9588 high = CONST_DOUBLE_HIGH (andop);
9592 shift_mask_high = ~0;
9593 if (INTVAL (shiftop) > 32)
9594 shift_mask_high <<= INTVAL (shiftop) - 32;
9598 if ((lsb & shift_mask_high) == 0)
9601 return high == -lsb;
9607 shift_mask_low = ~0;
9608 shift_mask_low <<= INTVAL (shiftop);
9612 if ((lsb & shift_mask_low) == 0)
9615 return low == -lsb && lsb != 1;
9621 /* Return 1 if operands will generate a valid arguments to rlwimi
9622 instruction for insert with right shift in 64-bit mode. The mask may
9623 not start on the first bit or stop on the last bit because wrap-around
9624 effects of instruction do not correspond to semantics of RTL insn. */
9627 insvdi_rshift_rlwimi_p (rtx sizeop, rtx startop, rtx shiftop)
9629 if (INTVAL (startop) < 64
9630 && INTVAL (startop) > 32
9631 && (INTVAL (sizeop) + INTVAL (startop) < 64)
9632 && (INTVAL (sizeop) + INTVAL (startop) > 33)
9633 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) < 96)
9634 && (INTVAL (sizeop) + INTVAL (startop) + INTVAL (shiftop) >= 64)
9635 && (64 - (INTVAL (shiftop) & 63)) >= INTVAL (sizeop))
9641 /* Return 1 if REGNO (reg1) == REGNO (reg2) - 1 making them candidates
9642 for lfq and stfq insns iff the registers are hard registers. */
9645 registers_ok_for_quad_peep (rtx reg1, rtx reg2)
9647 /* We might have been passed a SUBREG. */
9648 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
9651 /* We might have been passed non floating point registers. */
9652 if (!FP_REGNO_P (REGNO (reg1))
9653 || !FP_REGNO_P (REGNO (reg2)))
9656 return (REGNO (reg1) == REGNO (reg2) - 1);
9659 /* Return 1 if addr1 and addr2 are suitable for lfq or stfq insn.
9660 addr1 and addr2 must be in consecutive memory locations
9661 (addr2 == addr1 + 8). */
9664 mems_ok_for_quad_peep (rtx mem1, rtx mem2)
9667 unsigned int reg1, reg2;
9668 int offset1, offset2;
9670 /* The mems cannot be volatile. */
9671 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2))
9674 addr1 = XEXP (mem1, 0);
9675 addr2 = XEXP (mem2, 0);
9677 /* Extract an offset (if used) from the first addr. */
9678 if (GET_CODE (addr1) == PLUS)
9680 /* If not a REG, return zero. */
9681 if (GET_CODE (XEXP (addr1, 0)) != REG)
9685 reg1 = REGNO (XEXP (addr1, 0));
9686 /* The offset must be constant! */
9687 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
9689 offset1 = INTVAL (XEXP (addr1, 1));
9692 else if (GET_CODE (addr1) != REG)
9696 reg1 = REGNO (addr1);
9697 /* This was a simple (mem (reg)) expression. Offset is 0. */
9701 /* And now for the second addr. */
9702 if (GET_CODE (addr2) == PLUS)
9704 /* If not a REG, return zero. */
9705 if (GET_CODE (XEXP (addr2, 0)) != REG)
9709 reg2 = REGNO (XEXP (addr2, 0));
9710 /* The offset must be constant. */
9711 if (GET_CODE (XEXP (addr2, 1)) != CONST_INT)
9713 offset2 = INTVAL (XEXP (addr2, 1));
9716 else if (GET_CODE (addr2) != REG)
9720 reg2 = REGNO (addr2);
9721 /* This was a simple (mem (reg)) expression. Offset is 0. */
9725 /* Both of these must have the same base register. */
9729 /* The offset for the second addr must be 8 more than the first addr. */
9730 if (offset2 != offset1 + 8)
9733 /* All the tests passed. addr1 and addr2 are valid for lfq or stfq
9738 /* Return the register class of a scratch register needed to copy IN into
9739 or out of a register in CLASS in MODE. If it can be done directly,
9740 NO_REGS is returned. */
9743 secondary_reload_class (enum reg_class class,
9744 enum machine_mode mode ATTRIBUTE_UNUSED,
9749 if (TARGET_ELF || (DEFAULT_ABI == ABI_DARWIN
9751 && MACHOPIC_INDIRECT
9755 /* We cannot copy a symbolic operand directly into anything
9756 other than BASE_REGS for TARGET_ELF. So indicate that a
9757 register from BASE_REGS is needed as an intermediate
9760 On Darwin, pic addresses require a load from memory, which
9761 needs a base register. */
9762 if (class != BASE_REGS
9763 && (GET_CODE (in) == SYMBOL_REF
9764 || GET_CODE (in) == HIGH
9765 || GET_CODE (in) == LABEL_REF
9766 || GET_CODE (in) == CONST))
9770 if (GET_CODE (in) == REG)
9773 if (regno >= FIRST_PSEUDO_REGISTER)
9775 regno = true_regnum (in);
9776 if (regno >= FIRST_PSEUDO_REGISTER)
9780 else if (GET_CODE (in) == SUBREG)
9782 regno = true_regnum (in);
9783 if (regno >= FIRST_PSEUDO_REGISTER)
9789 /* We can place anything into GENERAL_REGS and can put GENERAL_REGS
9791 if (class == GENERAL_REGS || class == BASE_REGS
9792 || (regno >= 0 && INT_REGNO_P (regno)))
9795 /* Constants, memory, and FP registers can go into FP registers. */
9796 if ((regno == -1 || FP_REGNO_P (regno))
9797 && (class == FLOAT_REGS || class == NON_SPECIAL_REGS))
9800 /* Memory, and AltiVec registers can go into AltiVec registers. */
9801 if ((regno == -1 || ALTIVEC_REGNO_P (regno))
9802 && class == ALTIVEC_REGS)
9805 /* We can copy among the CR registers. */
9806 if ((class == CR_REGS || class == CR0_REGS)
9807 && regno >= 0 && CR_REGNO_P (regno))
9810 /* Otherwise, we need GENERAL_REGS. */
9811 return GENERAL_REGS;
9814 /* Given a comparison operation, return the bit number in CCR to test. We
9815 know this is a valid comparison.
9817 SCC_P is 1 if this is for an scc. That means that %D will have been
9818 used instead of %C, so the bits will be in different places.
9820 Return -1 if OP isn't a valid comparison for some reason. */
9823 ccr_bit (rtx op, int scc_p)
9825 enum rtx_code code = GET_CODE (op);
9826 enum machine_mode cc_mode;
9831 if (!COMPARISON_P (op))
9836 gcc_assert (GET_CODE (reg) == REG && CR_REGNO_P (REGNO (reg)));
9838 cc_mode = GET_MODE (reg);
9839 cc_regnum = REGNO (reg);
9840 base_bit = 4 * (cc_regnum - CR0_REGNO);
9842 validate_condition_mode (code, cc_mode);
9844 /* When generating a sCOND operation, only positive conditions are
9847 || code == EQ || code == GT || code == LT || code == UNORDERED
9848 || code == GTU || code == LTU);
9853 return scc_p ? base_bit + 3 : base_bit + 2;
9855 return base_bit + 2;
9856 case GT: case GTU: case UNLE:
9857 return base_bit + 1;
9858 case LT: case LTU: case UNGE:
9860 case ORDERED: case UNORDERED:
9861 return base_bit + 3;
9864 /* If scc, we will have done a cror to put the bit in the
9865 unordered position. So test that bit. For integer, this is ! LT
9866 unless this is an scc insn. */
9867 return scc_p ? base_bit + 3 : base_bit;
9870 return scc_p ? base_bit + 3 : base_bit + 1;
9877 /* Return the GOT register. */
9880 rs6000_got_register (rtx value ATTRIBUTE_UNUSED)
9882 /* The second flow pass currently (June 1999) can't update
9883 regs_ever_live without disturbing other parts of the compiler, so
9884 update it here to make the prolog/epilogue code happy. */
9885 if (no_new_pseudos && ! regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM])
9886 regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM] = 1;
9888 current_function_uses_pic_offset_table = 1;
9890 return pic_offset_table_rtx;
9893 /* Function to init struct machine_function.
9894 This will be called, via a pointer variable,
9895 from push_function_context. */
9897 static struct machine_function *
9898 rs6000_init_machine_status (void)
9900 return ggc_alloc_cleared (sizeof (machine_function));
9903 /* These macros test for integers and extract the low-order bits. */
9905 ((GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST_DOUBLE) \
9906 && GET_MODE (X) == VOIDmode)
9908 #define INT_LOWPART(X) \
9909 (GET_CODE (X) == CONST_INT ? INTVAL (X) : CONST_DOUBLE_LOW (X))
9915 unsigned long val = INT_LOWPART (op);
9917 /* If the high bit is zero, the value is the first 1 bit we find
9919 if ((val & 0x80000000) == 0)
9921 gcc_assert (val & 0xffffffff);
9924 while (((val <<= 1) & 0x80000000) == 0)
9929 /* If the high bit is set and the low bit is not, or the mask is all
9930 1's, the value is zero. */
9931 if ((val & 1) == 0 || (val & 0xffffffff) == 0xffffffff)
9934 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9937 while (((val >>= 1) & 1) != 0)
9947 unsigned long val = INT_LOWPART (op);
9949 /* If the low bit is zero, the value is the first 1 bit we find from
9953 gcc_assert (val & 0xffffffff);
9956 while (((val >>= 1) & 1) == 0)
9962 /* If the low bit is set and the high bit is not, or the mask is all
9963 1's, the value is 31. */
9964 if ((val & 0x80000000) == 0 || (val & 0xffffffff) == 0xffffffff)
9967 /* Otherwise we have a wrap-around mask. Look for the first 0 bit
9970 while (((val <<= 1) & 0x80000000) != 0)
9976 /* Locate some local-dynamic symbol still in use by this function
9977 so that we can print its name in some tls_ld pattern. */
9980 rs6000_get_some_local_dynamic_name (void)
9984 if (cfun->machine->some_ld_name)
9985 return cfun->machine->some_ld_name;
9987 for (insn = get_insns (); insn ; insn = NEXT_INSN (insn))
9989 && for_each_rtx (&PATTERN (insn),
9990 rs6000_get_some_local_dynamic_name_1, 0))
9991 return cfun->machine->some_ld_name;
9996 /* Helper function for rs6000_get_some_local_dynamic_name. */
9999 rs6000_get_some_local_dynamic_name_1 (rtx *px, void *data ATTRIBUTE_UNUSED)
10003 if (GET_CODE (x) == SYMBOL_REF)
10005 const char *str = XSTR (x, 0);
10006 if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
10008 cfun->machine->some_ld_name = str;
10016 /* Write out a function code label. */
10019 rs6000_output_function_entry (FILE *file, const char *fname)
10021 if (fname[0] != '.')
10023 switch (DEFAULT_ABI)
10026 gcc_unreachable ();
10032 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "L.");
10041 RS6000_OUTPUT_BASENAME (file, fname);
10043 assemble_name (file, fname);
10046 /* Print an operand. Recognize special options, documented below. */
10049 #define SMALL_DATA_RELOC ((rs6000_sdata == SDATA_EABI) ? "sda21" : "sdarel")
10050 #define SMALL_DATA_REG ((rs6000_sdata == SDATA_EABI) ? 0 : 13)
10052 #define SMALL_DATA_RELOC "sda21"
10053 #define SMALL_DATA_REG 0
10057 print_operand (FILE *file, rtx x, int code)
10061 unsigned HOST_WIDE_INT uval;
10066 /* Write out an instruction after the call which may be replaced
10067 with glue code by the loader. This depends on the AIX version. */
10068 asm_fprintf (file, RS6000_CALL_GLUE);
10071 /* %a is output_address. */
10074 /* If X is a constant integer whose low-order 5 bits are zero,
10075 write 'l'. Otherwise, write 'r'. This is a kludge to fix a bug
10076 in the AIX assembler where "sri" with a zero shift count
10077 writes a trash instruction. */
10078 if (GET_CODE (x) == CONST_INT && (INTVAL (x) & 31) == 0)
10085 /* If constant, low-order 16 bits of constant, unsigned.
10086 Otherwise, write normally. */
10088 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 0xffff);
10090 print_operand (file, x, 0);
10094 /* If the low-order bit is zero, write 'r'; otherwise, write 'l'
10095 for 64-bit mask direction. */
10096 putc (((INT_LOWPART (x) & 1) == 0 ? 'r' : 'l'), file);
10099 /* %c is output_addr_const if a CONSTANT_ADDRESS_P, otherwise
10103 /* X is a CR register. Print the number of the GT bit of the CR. */
10104 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10105 output_operand_lossage ("invalid %%E value");
10107 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 1);
10111 /* Like 'J' but get to the EQ bit. */
10112 gcc_assert (GET_CODE (x) == REG);
10114 /* Bit 1 is EQ bit. */
10115 i = 4 * (REGNO (x) - CR0_REGNO) + 2;
10117 fprintf (file, "%d", i);
10121 /* X is a CR register. Print the number of the EQ bit of the CR */
10122 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10123 output_operand_lossage ("invalid %%E value");
10125 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO) + 2);
10129 /* X is a CR register. Print the shift count needed to move it
10130 to the high-order four bits. */
10131 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10132 output_operand_lossage ("invalid %%f value");
10134 fprintf (file, "%d", 4 * (REGNO (x) - CR0_REGNO));
10138 /* Similar, but print the count for the rotate in the opposite
10140 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10141 output_operand_lossage ("invalid %%F value");
10143 fprintf (file, "%d", 32 - 4 * (REGNO (x) - CR0_REGNO));
10147 /* X is a constant integer. If it is negative, print "m",
10148 otherwise print "z". This is to make an aze or ame insn. */
10149 if (GET_CODE (x) != CONST_INT)
10150 output_operand_lossage ("invalid %%G value");
10151 else if (INTVAL (x) >= 0)
10158 /* If constant, output low-order five bits. Otherwise, write
10161 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 31);
10163 print_operand (file, x, 0);
10167 /* If constant, output low-order six bits. Otherwise, write
10170 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INT_LOWPART (x) & 63);
10172 print_operand (file, x, 0);
10176 /* Print `i' if this is a constant, else nothing. */
10182 /* Write the bit number in CCR for jump. */
10183 i = ccr_bit (x, 0);
10185 output_operand_lossage ("invalid %%j code");
10187 fprintf (file, "%d", i);
10191 /* Similar, but add one for shift count in rlinm for scc and pass
10192 scc flag to `ccr_bit'. */
10193 i = ccr_bit (x, 1);
10195 output_operand_lossage ("invalid %%J code");
10197 /* If we want bit 31, write a shift count of zero, not 32. */
10198 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10202 /* X must be a constant. Write the 1's complement of the
10205 output_operand_lossage ("invalid %%k value");
10207 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~ INT_LOWPART (x));
10211 /* X must be a symbolic constant on ELF. Write an
10212 expression suitable for an 'addi' that adds in the low 16
10213 bits of the MEM. */
10214 if (GET_CODE (x) != CONST)
10216 print_operand_address (file, x);
10217 fputs ("@l", file);
10221 if (GET_CODE (XEXP (x, 0)) != PLUS
10222 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
10223 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
10224 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
10225 output_operand_lossage ("invalid %%K value");
10226 print_operand_address (file, XEXP (XEXP (x, 0), 0));
10227 fputs ("@l", file);
10228 /* For GNU as, there must be a non-alphanumeric character
10229 between 'l' and the number. The '-' is added by
10230 print_operand() already. */
10231 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0)
10233 print_operand (file, XEXP (XEXP (x, 0), 1), 0);
10237 /* %l is output_asm_label. */
10240 /* Write second word of DImode or DFmode reference. Works on register
10241 or non-indexed memory only. */
10242 if (GET_CODE (x) == REG)
10243 fputs (reg_names[REGNO (x) + 1], file);
10244 else if (GET_CODE (x) == MEM)
10246 /* Handle possible auto-increment. Since it is pre-increment and
10247 we have already done it, we can just use an offset of word. */
10248 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10249 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10250 output_address (plus_constant (XEXP (XEXP (x, 0), 0),
10253 output_address (XEXP (adjust_address_nv (x, SImode,
10257 if (small_data_operand (x, GET_MODE (x)))
10258 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10259 reg_names[SMALL_DATA_REG]);
10264 /* MB value for a mask operand. */
10265 if (! mask_operand (x, SImode))
10266 output_operand_lossage ("invalid %%m value");
10268 fprintf (file, "%d", extract_MB (x));
10272 /* ME value for a mask operand. */
10273 if (! mask_operand (x, SImode))
10274 output_operand_lossage ("invalid %%M value");
10276 fprintf (file, "%d", extract_ME (x));
10279 /* %n outputs the negative of its operand. */
10282 /* Write the number of elements in the vector times 4. */
10283 if (GET_CODE (x) != PARALLEL)
10284 output_operand_lossage ("invalid %%N value");
10286 fprintf (file, "%d", XVECLEN (x, 0) * 4);
10290 /* Similar, but subtract 1 first. */
10291 if (GET_CODE (x) != PARALLEL)
10292 output_operand_lossage ("invalid %%O value");
10294 fprintf (file, "%d", (XVECLEN (x, 0) - 1) * 4);
10298 /* X is a CONST_INT that is a power of two. Output the logarithm. */
10300 || INT_LOWPART (x) < 0
10301 || (i = exact_log2 (INT_LOWPART (x))) < 0)
10302 output_operand_lossage ("invalid %%p value");
10304 fprintf (file, "%d", i);
10308 /* The operand must be an indirect memory reference. The result
10309 is the register name. */
10310 if (GET_CODE (x) != MEM || GET_CODE (XEXP (x, 0)) != REG
10311 || REGNO (XEXP (x, 0)) >= 32)
10312 output_operand_lossage ("invalid %%P value");
10314 fputs (reg_names[REGNO (XEXP (x, 0))], file);
10318 /* This outputs the logical code corresponding to a boolean
10319 expression. The expression may have one or both operands
10320 negated (if one, only the first one). For condition register
10321 logical operations, it will also treat the negated
10322 CR codes as NOTs, but not handle NOTs of them. */
10324 const char *const *t = 0;
10326 enum rtx_code code = GET_CODE (x);
10327 static const char * const tbl[3][3] = {
10328 { "and", "andc", "nor" },
10329 { "or", "orc", "nand" },
10330 { "xor", "eqv", "xor" } };
10334 else if (code == IOR)
10336 else if (code == XOR)
10339 output_operand_lossage ("invalid %%q value");
10341 if (GET_CODE (XEXP (x, 0)) != NOT)
10345 if (GET_CODE (XEXP (x, 1)) == NOT)
10363 /* X is a CR register. Print the mask for `mtcrf'. */
10364 if (GET_CODE (x) != REG || ! CR_REGNO_P (REGNO (x)))
10365 output_operand_lossage ("invalid %%R value");
10367 fprintf (file, "%d", 128 >> (REGNO (x) - CR0_REGNO));
10371 /* Low 5 bits of 32 - value */
10373 output_operand_lossage ("invalid %%s value");
10375 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INT_LOWPART (x)) & 31);
10379 /* PowerPC64 mask position. All 0's is excluded.
10380 CONST_INT 32-bit mask is considered sign-extended so any
10381 transition must occur within the CONST_INT, not on the boundary. */
10382 if (! mask_operand (x, DImode))
10383 output_operand_lossage ("invalid %%S value");
10385 uval = INT_LOWPART (x);
10387 if (uval & 1) /* Clear Left */
10389 #if HOST_BITS_PER_WIDE_INT > 64
10390 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10394 else /* Clear Right */
10397 #if HOST_BITS_PER_WIDE_INT > 64
10398 uval &= ((unsigned HOST_WIDE_INT) 1 << 64) - 1;
10404 gcc_assert (i >= 0);
10405 fprintf (file, "%d", i);
10409 /* Like 'J' but get to the OVERFLOW/UNORDERED bit. */
10410 gcc_assert (GET_CODE (x) == REG && GET_MODE (x) == CCmode);
10412 /* Bit 3 is OV bit. */
10413 i = 4 * (REGNO (x) - CR0_REGNO) + 3;
10415 /* If we want bit 31, write a shift count of zero, not 32. */
10416 fprintf (file, "%d", i == 31 ? 0 : i + 1);
10420 /* Print the symbolic name of a branch target register. */
10421 if (GET_CODE (x) != REG || (REGNO (x) != LINK_REGISTER_REGNUM
10422 && REGNO (x) != COUNT_REGISTER_REGNUM))
10423 output_operand_lossage ("invalid %%T value");
10424 else if (REGNO (x) == LINK_REGISTER_REGNUM)
10425 fputs (TARGET_NEW_MNEMONICS ? "lr" : "r", file);
10427 fputs ("ctr", file);
10431 /* High-order 16 bits of constant for use in unsigned operand. */
10433 output_operand_lossage ("invalid %%u value");
10435 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10436 (INT_LOWPART (x) >> 16) & 0xffff);
10440 /* High-order 16 bits of constant for use in signed operand. */
10442 output_operand_lossage ("invalid %%v value");
10444 fprintf (file, HOST_WIDE_INT_PRINT_HEX,
10445 (INT_LOWPART (x) >> 16) & 0xffff);
10449 /* Print `u' if this has an auto-increment or auto-decrement. */
10450 if (GET_CODE (x) == MEM
10451 && (GET_CODE (XEXP (x, 0)) == PRE_INC
10452 || GET_CODE (XEXP (x, 0)) == PRE_DEC))
10457 /* Print the trap code for this operand. */
10458 switch (GET_CODE (x))
10461 fputs ("eq", file); /* 4 */
10464 fputs ("ne", file); /* 24 */
10467 fputs ("lt", file); /* 16 */
10470 fputs ("le", file); /* 20 */
10473 fputs ("gt", file); /* 8 */
10476 fputs ("ge", file); /* 12 */
10479 fputs ("llt", file); /* 2 */
10482 fputs ("lle", file); /* 6 */
10485 fputs ("lgt", file); /* 1 */
10488 fputs ("lge", file); /* 5 */
10491 gcc_unreachable ();
10496 /* If constant, low-order 16 bits of constant, signed. Otherwise, write
10499 fprintf (file, HOST_WIDE_INT_PRINT_DEC,
10500 ((INT_LOWPART (x) & 0xffff) ^ 0x8000) - 0x8000);
10502 print_operand (file, x, 0);
10506 /* MB value for a PowerPC64 rldic operand. */
10507 val = (GET_CODE (x) == CONST_INT
10508 ? INTVAL (x) : CONST_DOUBLE_HIGH (x));
10513 for (i = 0; i < HOST_BITS_PER_WIDE_INT; i++)
10514 if ((val <<= 1) < 0)
10517 #if HOST_BITS_PER_WIDE_INT == 32
10518 if (GET_CODE (x) == CONST_INT && i >= 0)
10519 i += 32; /* zero-extend high-part was all 0's */
10520 else if (GET_CODE (x) == CONST_DOUBLE && i == 32)
10522 val = CONST_DOUBLE_LOW (x);
10528 for ( ; i < 64; i++)
10529 if ((val <<= 1) < 0)
10534 fprintf (file, "%d", i + 1);
10538 if (GET_CODE (x) == MEM
10539 && legitimate_indexed_address_p (XEXP (x, 0), 0))
10544 /* Like 'L', for third word of TImode */
10545 if (GET_CODE (x) == REG)
10546 fputs (reg_names[REGNO (x) + 2], file);
10547 else if (GET_CODE (x) == MEM)
10549 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10550 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10551 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 8));
10553 output_address (XEXP (adjust_address_nv (x, SImode, 8), 0));
10554 if (small_data_operand (x, GET_MODE (x)))
10555 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10556 reg_names[SMALL_DATA_REG]);
10561 /* X is a SYMBOL_REF. Write out the name preceded by a
10562 period and without any trailing data in brackets. Used for function
10563 names. If we are configured for System V (or the embedded ABI) on
10564 the PowerPC, do not emit the period, since those systems do not use
10565 TOCs and the like. */
10566 gcc_assert (GET_CODE (x) == SYMBOL_REF);
10568 /* Mark the decl as referenced so that cgraph will output the
10570 if (SYMBOL_REF_DECL (x))
10571 mark_decl_referenced (SYMBOL_REF_DECL (x));
10573 /* For macho, check to see if we need a stub. */
10576 const char *name = XSTR (x, 0);
10578 if (MACHOPIC_INDIRECT
10579 && machopic_classify_symbol (x) == MACHOPIC_UNDEFINED_FUNCTION)
10580 name = machopic_indirection_name (x, /*stub_p=*/true);
10582 assemble_name (file, name);
10584 else if (!DOT_SYMBOLS)
10585 assemble_name (file, XSTR (x, 0));
10587 rs6000_output_function_entry (file, XSTR (x, 0));
10591 /* Like 'L', for last word of TImode. */
10592 if (GET_CODE (x) == REG)
10593 fputs (reg_names[REGNO (x) + 3], file);
10594 else if (GET_CODE (x) == MEM)
10596 if (GET_CODE (XEXP (x, 0)) == PRE_INC
10597 || GET_CODE (XEXP (x, 0)) == PRE_DEC)
10598 output_address (plus_constant (XEXP (XEXP (x, 0), 0), 12));
10600 output_address (XEXP (adjust_address_nv (x, SImode, 12), 0));
10601 if (small_data_operand (x, GET_MODE (x)))
10602 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10603 reg_names[SMALL_DATA_REG]);
10607 /* Print AltiVec or SPE memory operand. */
10612 gcc_assert (GET_CODE (x) == MEM);
10618 /* Handle [reg]. */
10619 if (GET_CODE (tmp) == REG)
10621 fprintf (file, "0(%s)", reg_names[REGNO (tmp)]);
10624 /* Handle [reg+UIMM]. */
10625 else if (GET_CODE (tmp) == PLUS &&
10626 GET_CODE (XEXP (tmp, 1)) == CONST_INT)
10630 gcc_assert (GET_CODE (XEXP (tmp, 0)) == REG);
10632 x = INTVAL (XEXP (tmp, 1));
10633 fprintf (file, "%d(%s)", x, reg_names[REGNO (XEXP (tmp, 0))]);
10637 /* Fall through. Must be [reg+reg]. */
10640 && GET_CODE (tmp) == AND
10641 && GET_CODE (XEXP (tmp, 1)) == CONST_INT
10642 && INTVAL (XEXP (tmp, 1)) == -16)
10643 tmp = XEXP (tmp, 0);
10644 if (GET_CODE (tmp) == REG)
10645 fprintf (file, "0,%s", reg_names[REGNO (tmp)]);
10648 gcc_assert (GET_CODE (tmp) == PLUS
10649 && GET_CODE (XEXP (tmp, 1)) == REG);
10651 if (REGNO (XEXP (tmp, 0)) == 0)
10652 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 1)) ],
10653 reg_names[ REGNO (XEXP (tmp, 0)) ]);
10655 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (tmp, 0)) ],
10656 reg_names[ REGNO (XEXP (tmp, 1)) ]);
10662 if (GET_CODE (x) == REG)
10663 fprintf (file, "%s", reg_names[REGNO (x)]);
10664 else if (GET_CODE (x) == MEM)
10666 /* We need to handle PRE_INC and PRE_DEC here, since we need to
10667 know the width from the mode. */
10668 if (GET_CODE (XEXP (x, 0)) == PRE_INC)
10669 fprintf (file, "%d(%s)", GET_MODE_SIZE (GET_MODE (x)),
10670 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10671 else if (GET_CODE (XEXP (x, 0)) == PRE_DEC)
10672 fprintf (file, "%d(%s)", - GET_MODE_SIZE (GET_MODE (x)),
10673 reg_names[REGNO (XEXP (XEXP (x, 0), 0))]);
10675 output_address (XEXP (x, 0));
10678 output_addr_const (file, x);
10682 assemble_name (file, rs6000_get_some_local_dynamic_name ());
10686 output_operand_lossage ("invalid %%xn code");
10690 /* Print the address of an operand. */
10693 print_operand_address (FILE *file, rtx x)
10695 if (GET_CODE (x) == REG)
10696 fprintf (file, "0(%s)", reg_names[ REGNO (x) ]);
10697 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == CONST
10698 || GET_CODE (x) == LABEL_REF)
10700 output_addr_const (file, x);
10701 if (small_data_operand (x, GET_MODE (x)))
10702 fprintf (file, "@%s(%s)", SMALL_DATA_RELOC,
10703 reg_names[SMALL_DATA_REG]);
10705 gcc_assert (!TARGET_TOC);
10707 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == REG)
10709 if (REGNO (XEXP (x, 0)) == 0)
10710 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 1)) ],
10711 reg_names[ REGNO (XEXP (x, 0)) ]);
10713 fprintf (file, "%s,%s", reg_names[ REGNO (XEXP (x, 0)) ],
10714 reg_names[ REGNO (XEXP (x, 1)) ]);
10716 else if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
10717 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
10718 INTVAL (XEXP (x, 1)), reg_names[ REGNO (XEXP (x, 0)) ]);
10720 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10721 && CONSTANT_P (XEXP (x, 1)))
10723 output_addr_const (file, XEXP (x, 1));
10724 fprintf (file, "@l(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10728 else if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == REG
10729 && CONSTANT_P (XEXP (x, 1)))
10731 fprintf (file, "lo16(");
10732 output_addr_const (file, XEXP (x, 1));
10733 fprintf (file, ")(%s)", reg_names[ REGNO (XEXP (x, 0)) ]);
10736 else if (legitimate_constant_pool_address_p (x))
10738 if (TARGET_AIX && (!TARGET_ELF || !TARGET_MINIMAL_TOC))
10740 rtx contains_minus = XEXP (x, 1);
10744 /* Find the (minus (sym) (toc)) buried in X, and temporarily
10745 turn it into (sym) for output_addr_const. */
10746 while (GET_CODE (XEXP (contains_minus, 0)) != MINUS)
10747 contains_minus = XEXP (contains_minus, 0);
10749 minus = XEXP (contains_minus, 0);
10750 symref = XEXP (minus, 0);
10751 XEXP (contains_minus, 0) = symref;
10756 name = XSTR (symref, 0);
10757 newname = alloca (strlen (name) + sizeof ("@toc"));
10758 strcpy (newname, name);
10759 strcat (newname, "@toc");
10760 XSTR (symref, 0) = newname;
10762 output_addr_const (file, XEXP (x, 1));
10764 XSTR (symref, 0) = name;
10765 XEXP (contains_minus, 0) = minus;
10768 output_addr_const (file, XEXP (x, 1));
10770 fprintf (file, "(%s)", reg_names[REGNO (XEXP (x, 0))]);
10773 gcc_unreachable ();
10776 /* Target hook for assembling integer objects. The PowerPC version has
10777 to handle fixup entries for relocatable code if RELOCATABLE_NEEDS_FIXUP
10778 is defined. It also needs to handle DI-mode objects on 64-bit
10782 rs6000_assemble_integer (rtx x, unsigned int size, int aligned_p)
10784 #ifdef RELOCATABLE_NEEDS_FIXUP
10785 /* Special handling for SI values. */
10786 if (RELOCATABLE_NEEDS_FIXUP && size == 4 && aligned_p)
10788 extern int in_toc_section (void);
10789 static int recurse = 0;
10791 /* For -mrelocatable, we mark all addresses that need to be fixed up
10792 in the .fixup section. */
10793 if (TARGET_RELOCATABLE
10794 && !in_toc_section ()
10795 && !in_text_section ()
10796 && !in_unlikely_text_section ()
10798 && GET_CODE (x) != CONST_INT
10799 && GET_CODE (x) != CONST_DOUBLE
10805 ASM_GENERATE_INTERNAL_LABEL (buf, "LCP", fixuplabelno);
10807 ASM_OUTPUT_LABEL (asm_out_file, buf);
10808 fprintf (asm_out_file, "\t.long\t(");
10809 output_addr_const (asm_out_file, x);
10810 fprintf (asm_out_file, ")@fixup\n");
10811 fprintf (asm_out_file, "\t.section\t\".fixup\",\"aw\"\n");
10812 ASM_OUTPUT_ALIGN (asm_out_file, 2);
10813 fprintf (asm_out_file, "\t.long\t");
10814 assemble_name (asm_out_file, buf);
10815 fprintf (asm_out_file, "\n\t.previous\n");
10819 /* Remove initial .'s to turn a -mcall-aixdesc function
10820 address into the address of the descriptor, not the function
10822 else if (GET_CODE (x) == SYMBOL_REF
10823 && XSTR (x, 0)[0] == '.'
10824 && DEFAULT_ABI == ABI_AIX)
10826 const char *name = XSTR (x, 0);
10827 while (*name == '.')
10830 fprintf (asm_out_file, "\t.long\t%s\n", name);
10834 #endif /* RELOCATABLE_NEEDS_FIXUP */
10835 return default_assemble_integer (x, size, aligned_p);
10838 #ifdef HAVE_GAS_HIDDEN
10839 /* Emit an assembler directive to set symbol visibility for DECL to
10840 VISIBILITY_TYPE. */
10843 rs6000_assemble_visibility (tree decl, int vis)
10845 /* Functions need to have their entry point symbol visibility set as
10846 well as their descriptor symbol visibility. */
10847 if (DEFAULT_ABI == ABI_AIX
10849 && TREE_CODE (decl) == FUNCTION_DECL)
10851 static const char * const visibility_types[] = {
10852 NULL, "internal", "hidden", "protected"
10855 const char *name, *type;
10857 name = ((* targetm.strip_name_encoding)
10858 (IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl))));
10859 type = visibility_types[vis];
10861 fprintf (asm_out_file, "\t.%s\t%s\n", type, name);
10862 fprintf (asm_out_file, "\t.%s\t.%s\n", type, name);
10865 default_assemble_visibility (decl, vis);
10870 rs6000_reverse_condition (enum machine_mode mode, enum rtx_code code)
10872 /* Reversal of FP compares takes care -- an ordered compare
10873 becomes an unordered compare and vice versa. */
10874 if (mode == CCFPmode
10875 && (!flag_finite_math_only
10876 || code == UNLT || code == UNLE || code == UNGT || code == UNGE
10877 || code == UNEQ || code == LTGT))
10878 return reverse_condition_maybe_unordered (code);
10880 return reverse_condition (code);
10883 /* Generate a compare for CODE. Return a brand-new rtx that
10884 represents the result of the compare. */
10887 rs6000_generate_compare (enum rtx_code code)
10889 enum machine_mode comp_mode;
10890 rtx compare_result;
10892 if (rs6000_compare_fp_p)
10893 comp_mode = CCFPmode;
10894 else if (code == GTU || code == LTU
10895 || code == GEU || code == LEU)
10896 comp_mode = CCUNSmode;
10897 else if ((code == EQ || code == NE)
10898 && GET_CODE (rs6000_compare_op0) == SUBREG
10899 && GET_CODE (rs6000_compare_op1) == SUBREG
10900 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op0)
10901 && SUBREG_PROMOTED_UNSIGNED_P (rs6000_compare_op1))
10902 /* These are unsigned values, perhaps there will be a later
10903 ordering compare that can be shared with this one.
10904 Unfortunately we cannot detect the signedness of the operands
10905 for non-subregs. */
10906 comp_mode = CCUNSmode;
10908 comp_mode = CCmode;
10910 /* First, the compare. */
10911 compare_result = gen_reg_rtx (comp_mode);
10913 /* SPE FP compare instructions on the GPRs. Yuck! */
10914 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT)
10915 && rs6000_compare_fp_p)
10917 rtx cmp, or_result, compare_result2;
10918 enum machine_mode op_mode = GET_MODE (rs6000_compare_op0);
10920 if (op_mode == VOIDmode)
10921 op_mode = GET_MODE (rs6000_compare_op1);
10923 /* Note: The E500 comparison instructions set the GT bit (x +
10924 1), on success. This explains the mess. */
10928 case EQ: case UNEQ: case NE: case LTGT:
10932 cmp = flag_unsafe_math_optimizations
10933 ? gen_tstsfeq_gpr (compare_result, rs6000_compare_op0,
10934 rs6000_compare_op1)
10935 : gen_cmpsfeq_gpr (compare_result, rs6000_compare_op0,
10936 rs6000_compare_op1);
10940 cmp = flag_unsafe_math_optimizations
10941 ? gen_tstdfeq_gpr (compare_result, rs6000_compare_op0,
10942 rs6000_compare_op1)
10943 : gen_cmpdfeq_gpr (compare_result, rs6000_compare_op0,
10944 rs6000_compare_op1);
10948 gcc_unreachable ();
10952 case GT: case GTU: case UNGT: case UNGE: case GE: case GEU:
10956 cmp = flag_unsafe_math_optimizations
10957 ? gen_tstsfgt_gpr (compare_result, rs6000_compare_op0,
10958 rs6000_compare_op1)
10959 : gen_cmpsfgt_gpr (compare_result, rs6000_compare_op0,
10960 rs6000_compare_op1);
10964 cmp = flag_unsafe_math_optimizations
10965 ? gen_tstdfgt_gpr (compare_result, rs6000_compare_op0,
10966 rs6000_compare_op1)
10967 : gen_cmpdfgt_gpr (compare_result, rs6000_compare_op0,
10968 rs6000_compare_op1);
10972 gcc_unreachable ();
10976 case LT: case LTU: case UNLT: case UNLE: case LE: case LEU:
10980 cmp = flag_unsafe_math_optimizations
10981 ? gen_tstsflt_gpr (compare_result, rs6000_compare_op0,
10982 rs6000_compare_op1)
10983 : gen_cmpsflt_gpr (compare_result, rs6000_compare_op0,
10984 rs6000_compare_op1);
10988 cmp = flag_unsafe_math_optimizations
10989 ? gen_tstdflt_gpr (compare_result, rs6000_compare_op0,
10990 rs6000_compare_op1)
10991 : gen_cmpdflt_gpr (compare_result, rs6000_compare_op0,
10992 rs6000_compare_op1);
10996 gcc_unreachable ();
11000 gcc_unreachable ();
11003 /* Synthesize LE and GE from LT/GT || EQ. */
11004 if (code == LE || code == GE || code == LEU || code == GEU)
11010 case LE: code = LT; break;
11011 case GE: code = GT; break;
11012 case LEU: code = LT; break;
11013 case GEU: code = GT; break;
11014 default: gcc_unreachable ();
11017 compare_result2 = gen_reg_rtx (CCFPmode);
11023 cmp = flag_unsafe_math_optimizations
11024 ? gen_tstsfeq_gpr (compare_result2, rs6000_compare_op0,
11025 rs6000_compare_op1)
11026 : gen_cmpsfeq_gpr (compare_result2, rs6000_compare_op0,
11027 rs6000_compare_op1);
11031 cmp = flag_unsafe_math_optimizations
11032 ? gen_tstdfeq_gpr (compare_result2, rs6000_compare_op0,
11033 rs6000_compare_op1)
11034 : gen_cmpdfeq_gpr (compare_result2, rs6000_compare_op0,
11035 rs6000_compare_op1);
11039 gcc_unreachable ();
11043 /* OR them together. */
11044 or_result = gen_reg_rtx (CCFPmode);
11045 cmp = gen_e500_cr_ior_compare (or_result, compare_result,
11047 compare_result = or_result;
11052 if (code == NE || code == LTGT)
11062 /* Generate XLC-compatible TFmode compare as PARALLEL with extra
11063 CLOBBERs to match cmptf_internal2 pattern. */
11064 if (comp_mode == CCFPmode && TARGET_XL_COMPAT
11065 && GET_MODE (rs6000_compare_op0) == TFmode
11066 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN)
11067 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128)
11068 emit_insn (gen_rtx_PARALLEL (VOIDmode,
11070 gen_rtx_SET (VOIDmode,
11072 gen_rtx_COMPARE (comp_mode,
11073 rs6000_compare_op0,
11074 rs6000_compare_op1)),
11075 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11076 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11077 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11078 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11079 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11080 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11081 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)),
11082 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (DFmode)))));
11083 else if (GET_CODE (rs6000_compare_op1) == UNSPEC
11084 && XINT (rs6000_compare_op1, 1) == UNSPEC_SP_TEST)
11086 rtx op1 = XVECEXP (rs6000_compare_op1, 0, 0);
11087 comp_mode = CCEQmode;
11088 compare_result = gen_reg_rtx (CCEQmode);
11090 emit_insn (gen_stack_protect_testdi (compare_result,
11091 rs6000_compare_op0, op1));
11093 emit_insn (gen_stack_protect_testsi (compare_result,
11094 rs6000_compare_op0, op1));
11097 emit_insn (gen_rtx_SET (VOIDmode, compare_result,
11098 gen_rtx_COMPARE (comp_mode,
11099 rs6000_compare_op0,
11100 rs6000_compare_op1)));
11103 /* Some kinds of FP comparisons need an OR operation;
11104 under flag_finite_math_only we don't bother. */
11105 if (rs6000_compare_fp_p
11106 && !flag_finite_math_only
11107 && !(TARGET_HARD_FLOAT && TARGET_E500 && !TARGET_FPRS)
11108 && (code == LE || code == GE
11109 || code == UNEQ || code == LTGT
11110 || code == UNGT || code == UNLT))
11112 enum rtx_code or1, or2;
11113 rtx or1_rtx, or2_rtx, compare2_rtx;
11114 rtx or_result = gen_reg_rtx (CCEQmode);
11118 case LE: or1 = LT; or2 = EQ; break;
11119 case GE: or1 = GT; or2 = EQ; break;
11120 case UNEQ: or1 = UNORDERED; or2 = EQ; break;
11121 case LTGT: or1 = LT; or2 = GT; break;
11122 case UNGT: or1 = UNORDERED; or2 = GT; break;
11123 case UNLT: or1 = UNORDERED; or2 = LT; break;
11124 default: gcc_unreachable ();
11126 validate_condition_mode (or1, comp_mode);
11127 validate_condition_mode (or2, comp_mode);
11128 or1_rtx = gen_rtx_fmt_ee (or1, SImode, compare_result, const0_rtx);
11129 or2_rtx = gen_rtx_fmt_ee (or2, SImode, compare_result, const0_rtx);
11130 compare2_rtx = gen_rtx_COMPARE (CCEQmode,
11131 gen_rtx_IOR (SImode, or1_rtx, or2_rtx),
11133 emit_insn (gen_rtx_SET (VOIDmode, or_result, compare2_rtx));
11135 compare_result = or_result;
11139 validate_condition_mode (code, GET_MODE (compare_result));
11141 return gen_rtx_fmt_ee (code, VOIDmode, compare_result, const0_rtx);
11145 /* Emit the RTL for an sCOND pattern. */
11148 rs6000_emit_sCOND (enum rtx_code code, rtx result)
11151 enum machine_mode op_mode;
11152 enum rtx_code cond_code;
11154 condition_rtx = rs6000_generate_compare (code);
11155 cond_code = GET_CODE (condition_rtx);
11157 if (TARGET_E500 && rs6000_compare_fp_p
11158 && !TARGET_FPRS && TARGET_HARD_FLOAT)
11162 PUT_MODE (condition_rtx, SImode);
11163 t = XEXP (condition_rtx, 0);
11165 gcc_assert (cond_code == NE || cond_code == EQ);
11167 if (cond_code == NE)
11168 emit_insn (gen_e500_flip_gt_bit (t, t));
11170 emit_insn (gen_move_from_CR_gt_bit (result, t));
11174 if (cond_code == NE
11175 || cond_code == GE || cond_code == LE
11176 || cond_code == GEU || cond_code == LEU
11177 || cond_code == ORDERED || cond_code == UNGE || cond_code == UNLE)
11179 rtx not_result = gen_reg_rtx (CCEQmode);
11180 rtx not_op, rev_cond_rtx;
11181 enum machine_mode cc_mode;
11183 cc_mode = GET_MODE (XEXP (condition_rtx, 0));
11185 rev_cond_rtx = gen_rtx_fmt_ee (rs6000_reverse_condition (cc_mode, cond_code),
11186 SImode, XEXP (condition_rtx, 0), const0_rtx);
11187 not_op = gen_rtx_COMPARE (CCEQmode, rev_cond_rtx, const0_rtx);
11188 emit_insn (gen_rtx_SET (VOIDmode, not_result, not_op));
11189 condition_rtx = gen_rtx_EQ (VOIDmode, not_result, const0_rtx);
11192 op_mode = GET_MODE (rs6000_compare_op0);
11193 if (op_mode == VOIDmode)
11194 op_mode = GET_MODE (rs6000_compare_op1);
11196 if (TARGET_POWERPC64 && (op_mode == DImode || rs6000_compare_fp_p))
11198 PUT_MODE (condition_rtx, DImode);
11199 convert_move (result, condition_rtx, 0);
11203 PUT_MODE (condition_rtx, SImode);
11204 emit_insn (gen_rtx_SET (VOIDmode, result, condition_rtx));
11208 /* Emit a branch of kind CODE to location LOC. */
11211 rs6000_emit_cbranch (enum rtx_code code, rtx loc)
11213 rtx condition_rtx, loc_ref;
11215 condition_rtx = rs6000_generate_compare (code);
11216 loc_ref = gen_rtx_LABEL_REF (VOIDmode, loc);
11217 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
11218 gen_rtx_IF_THEN_ELSE (VOIDmode, condition_rtx,
11219 loc_ref, pc_rtx)));
11222 /* Return the string to output a conditional branch to LABEL, which is
11223 the operand number of the label, or -1 if the branch is really a
11224 conditional return.
11226 OP is the conditional expression. XEXP (OP, 0) is assumed to be a
11227 condition code register and its mode specifies what kind of
11228 comparison we made.
11230 REVERSED is nonzero if we should reverse the sense of the comparison.
11232 INSN is the insn. */
11235 output_cbranch (rtx op, const char *label, int reversed, rtx insn)
11237 static char string[64];
11238 enum rtx_code code = GET_CODE (op);
11239 rtx cc_reg = XEXP (op, 0);
11240 enum machine_mode mode = GET_MODE (cc_reg);
11241 int cc_regno = REGNO (cc_reg) - CR0_REGNO;
11242 int need_longbranch = label != NULL && get_attr_length (insn) == 8;
11243 int really_reversed = reversed ^ need_longbranch;
11249 validate_condition_mode (code, mode);
11251 /* Work out which way this really branches. We could use
11252 reverse_condition_maybe_unordered here always but this
11253 makes the resulting assembler clearer. */
11254 if (really_reversed)
11256 /* Reversal of FP compares takes care -- an ordered compare
11257 becomes an unordered compare and vice versa. */
11258 if (mode == CCFPmode)
11259 code = reverse_condition_maybe_unordered (code);
11261 code = reverse_condition (code);
11264 if ((TARGET_E500 && !TARGET_FPRS && TARGET_HARD_FLOAT) && mode == CCFPmode)
11266 /* The efscmp/tst* instructions twiddle bit 2, which maps nicely
11271 /* Opposite of GT. */
11280 gcc_unreachable ();
11286 /* Not all of these are actually distinct opcodes, but
11287 we distinguish them for clarity of the resulting assembler. */
11288 case NE: case LTGT:
11289 ccode = "ne"; break;
11290 case EQ: case UNEQ:
11291 ccode = "eq"; break;
11293 ccode = "ge"; break;
11294 case GT: case GTU: case UNGT:
11295 ccode = "gt"; break;
11297 ccode = "le"; break;
11298 case LT: case LTU: case UNLT:
11299 ccode = "lt"; break;
11300 case UNORDERED: ccode = "un"; break;
11301 case ORDERED: ccode = "nu"; break;
11302 case UNGE: ccode = "nl"; break;
11303 case UNLE: ccode = "ng"; break;
11305 gcc_unreachable ();
11308 /* Maybe we have a guess as to how likely the branch is.
11309 The old mnemonics don't have a way to specify this information. */
11311 note = find_reg_note (insn, REG_BR_PROB, NULL_RTX);
11312 if (note != NULL_RTX)
11314 /* PROB is the difference from 50%. */
11315 int prob = INTVAL (XEXP (note, 0)) - REG_BR_PROB_BASE / 2;
11317 /* Only hint for highly probable/improbable branches on newer
11318 cpus as static prediction overrides processor dynamic
11319 prediction. For older cpus we may as well always hint, but
11320 assume not taken for branches that are very close to 50% as a
11321 mispredicted taken branch is more expensive than a
11322 mispredicted not-taken branch. */
11323 if (rs6000_always_hint
11324 || abs (prob) > REG_BR_PROB_BASE / 100 * 48)
11326 if (abs (prob) > REG_BR_PROB_BASE / 20
11327 && ((prob > 0) ^ need_longbranch))
11335 s += sprintf (s, "{b%sr|b%slr%s} ", ccode, ccode, pred);
11337 s += sprintf (s, "{b%s|b%s%s} ", ccode, ccode, pred);
11339 /* We need to escape any '%' characters in the reg_names string.
11340 Assume they'd only be the first character.... */
11341 if (reg_names[cc_regno + CR0_REGNO][0] == '%')
11343 s += sprintf (s, "%s", reg_names[cc_regno + CR0_REGNO]);
11347 /* If the branch distance was too far, we may have to use an
11348 unconditional branch to go the distance. */
11349 if (need_longbranch)
11350 s += sprintf (s, ",$+8\n\tb %s", label);
11352 s += sprintf (s, ",%s", label);
11358 /* Return the string to flip the GT bit on a CR. */
11360 output_e500_flip_gt_bit (rtx dst, rtx src)
11362 static char string[64];
11365 gcc_assert (GET_CODE (dst) == REG && CR_REGNO_P (REGNO (dst))
11366 && GET_CODE (src) == REG && CR_REGNO_P (REGNO (src)));
11369 a = 4 * (REGNO (dst) - CR0_REGNO) + 1;
11370 b = 4 * (REGNO (src) - CR0_REGNO) + 1;
11372 sprintf (string, "crnot %d,%d", a, b);
11376 /* Return insn index for the vector compare instruction for given CODE,
11377 and DEST_MODE, OP_MODE. Return INSN_NOT_AVAILABLE if valid insn is
11381 get_vec_cmp_insn (enum rtx_code code,
11382 enum machine_mode dest_mode,
11383 enum machine_mode op_mode)
11385 if (!TARGET_ALTIVEC)
11386 return INSN_NOT_AVAILABLE;
11391 if (dest_mode == V16QImode && op_mode == V16QImode)
11392 return UNSPEC_VCMPEQUB;
11393 if (dest_mode == V8HImode && op_mode == V8HImode)
11394 return UNSPEC_VCMPEQUH;
11395 if (dest_mode == V4SImode && op_mode == V4SImode)
11396 return UNSPEC_VCMPEQUW;
11397 if (dest_mode == V4SImode && op_mode == V4SFmode)
11398 return UNSPEC_VCMPEQFP;
11401 if (dest_mode == V4SImode && op_mode == V4SFmode)
11402 return UNSPEC_VCMPGEFP;
11404 if (dest_mode == V16QImode && op_mode == V16QImode)
11405 return UNSPEC_VCMPGTSB;
11406 if (dest_mode == V8HImode && op_mode == V8HImode)
11407 return UNSPEC_VCMPGTSH;
11408 if (dest_mode == V4SImode && op_mode == V4SImode)
11409 return UNSPEC_VCMPGTSW;
11410 if (dest_mode == V4SImode && op_mode == V4SFmode)
11411 return UNSPEC_VCMPGTFP;
11414 if (dest_mode == V16QImode && op_mode == V16QImode)
11415 return UNSPEC_VCMPGTUB;
11416 if (dest_mode == V8HImode && op_mode == V8HImode)
11417 return UNSPEC_VCMPGTUH;
11418 if (dest_mode == V4SImode && op_mode == V4SImode)
11419 return UNSPEC_VCMPGTUW;
11424 return INSN_NOT_AVAILABLE;
11427 /* Emit vector compare for operands OP0 and OP1 using code RCODE.
11428 DMODE is expected destination mode. This is a recursive function. */
11431 rs6000_emit_vector_compare (enum rtx_code rcode,
11433 enum machine_mode dmode)
11437 enum machine_mode dest_mode;
11438 enum machine_mode op_mode = GET_MODE (op1);
11440 gcc_assert (TARGET_ALTIVEC);
11441 gcc_assert (GET_MODE (op0) == GET_MODE (op1));
11443 /* Floating point vector compare instructions uses destination V4SImode.
11444 Move destination to appropriate mode later. */
11445 if (dmode == V4SFmode)
11446 dest_mode = V4SImode;
11450 mask = gen_reg_rtx (dest_mode);
11451 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11453 if (vec_cmp_insn == INSN_NOT_AVAILABLE)
11455 bool swap_operands = false;
11456 bool try_again = false;
11461 swap_operands = true;
11466 swap_operands = true;
11470 /* Treat A != B as ~(A==B). */
11472 enum insn_code nor_code;
11473 rtx eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11476 nor_code = one_cmpl_optab->handlers[(int)dest_mode].insn_code;
11477 gcc_assert (nor_code != CODE_FOR_nothing);
11478 emit_insn (GEN_FCN (nor_code) (mask, eq_rtx));
11480 if (dmode != dest_mode)
11482 rtx temp = gen_reg_rtx (dest_mode);
11483 convert_move (temp, mask, 0);
11493 /* Try GT/GTU/LT/LTU OR EQ */
11496 enum insn_code ior_code;
11497 enum rtx_code new_code;
11518 gcc_unreachable ();
11521 c_rtx = rs6000_emit_vector_compare (new_code,
11522 op0, op1, dest_mode);
11523 eq_rtx = rs6000_emit_vector_compare (EQ, op0, op1,
11526 ior_code = ior_optab->handlers[(int)dest_mode].insn_code;
11527 gcc_assert (ior_code != CODE_FOR_nothing);
11528 emit_insn (GEN_FCN (ior_code) (mask, c_rtx, eq_rtx));
11529 if (dmode != dest_mode)
11531 rtx temp = gen_reg_rtx (dest_mode);
11532 convert_move (temp, mask, 0);
11539 gcc_unreachable ();
11544 vec_cmp_insn = get_vec_cmp_insn (rcode, dest_mode, op_mode);
11545 /* You only get two chances. */
11546 gcc_assert (vec_cmp_insn != INSN_NOT_AVAILABLE);
11558 emit_insn (gen_rtx_SET (VOIDmode, mask,
11559 gen_rtx_UNSPEC (dest_mode,
11560 gen_rtvec (2, op0, op1),
11562 if (dmode != dest_mode)
11564 rtx temp = gen_reg_rtx (dest_mode);
11565 convert_move (temp, mask, 0);
11571 /* Return vector select instruction for MODE. Return INSN_NOT_AVAILABLE, if
11572 valid insn doesn exist for given mode. */
11575 get_vsel_insn (enum machine_mode mode)
11580 return UNSPEC_VSEL4SI;
11583 return UNSPEC_VSEL4SF;
11586 return UNSPEC_VSEL8HI;
11589 return UNSPEC_VSEL16QI;
11592 return INSN_NOT_AVAILABLE;
11595 return INSN_NOT_AVAILABLE;
11598 /* Emit vector select insn where DEST is destination using
11599 operands OP1, OP2 and MASK. */
11602 rs6000_emit_vector_select (rtx dest, rtx op1, rtx op2, rtx mask)
11605 enum machine_mode dest_mode = GET_MODE (dest);
11606 int vsel_insn_index = get_vsel_insn (GET_MODE (dest));
11608 temp = gen_reg_rtx (dest_mode);
11610 /* For each vector element, select op1 when mask is 1 otherwise
11612 t = gen_rtx_SET (VOIDmode, temp,
11613 gen_rtx_UNSPEC (dest_mode,
11614 gen_rtvec (3, op2, op1, mask),
11617 emit_move_insn (dest, temp);
11621 /* Emit vector conditional expression.
11622 DEST is destination. OP1 and OP2 are two VEC_COND_EXPR operands.
11623 CC_OP0 and CC_OP1 are the two operands for the relation operation COND. */
11626 rs6000_emit_vector_cond_expr (rtx dest, rtx op1, rtx op2,
11627 rtx cond, rtx cc_op0, rtx cc_op1)
11629 enum machine_mode dest_mode = GET_MODE (dest);
11630 enum rtx_code rcode = GET_CODE (cond);
11633 if (!TARGET_ALTIVEC)
11636 /* Get the vector mask for the given relational operations. */
11637 mask = rs6000_emit_vector_compare (rcode, cc_op0, cc_op1, dest_mode);
11639 rs6000_emit_vector_select (dest, op1, op2, mask);
11644 /* Emit a conditional move: move TRUE_COND to DEST if OP of the
11645 operands of the last comparison is nonzero/true, FALSE_COND if it
11646 is zero/false. Return 0 if the hardware has no such operation. */
11649 rs6000_emit_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11651 enum rtx_code code = GET_CODE (op);
11652 rtx op0 = rs6000_compare_op0;
11653 rtx op1 = rs6000_compare_op1;
11654 REAL_VALUE_TYPE c1;
11655 enum machine_mode compare_mode = GET_MODE (op0);
11656 enum machine_mode result_mode = GET_MODE (dest);
11658 bool is_against_zero;
11660 /* These modes should always match. */
11661 if (GET_MODE (op1) != compare_mode
11662 /* In the isel case however, we can use a compare immediate, so
11663 op1 may be a small constant. */
11664 && (!TARGET_ISEL || !short_cint_operand (op1, VOIDmode)))
11666 if (GET_MODE (true_cond) != result_mode)
11668 if (GET_MODE (false_cond) != result_mode)
11671 /* First, work out if the hardware can do this at all, or
11672 if it's too slow.... */
11673 if (! rs6000_compare_fp_p)
11676 return rs6000_emit_int_cmove (dest, op, true_cond, false_cond);
11679 else if (TARGET_E500 && TARGET_HARD_FLOAT && !TARGET_FPRS
11680 && GET_MODE_CLASS (compare_mode) == MODE_FLOAT)
11683 is_against_zero = op1 == CONST0_RTX (compare_mode);
11685 /* A floating-point subtract might overflow, underflow, or produce
11686 an inexact result, thus changing the floating-point flags, so it
11687 can't be generated if we care about that. It's safe if one side
11688 of the construct is zero, since then no subtract will be
11690 if (GET_MODE_CLASS (compare_mode) == MODE_FLOAT
11691 && flag_trapping_math && ! is_against_zero)
11694 /* Eliminate half of the comparisons by switching operands, this
11695 makes the remaining code simpler. */
11696 if (code == UNLT || code == UNGT || code == UNORDERED || code == NE
11697 || code == LTGT || code == LT || code == UNLE)
11699 code = reverse_condition_maybe_unordered (code);
11701 true_cond = false_cond;
11705 /* UNEQ and LTGT take four instructions for a comparison with zero,
11706 it'll probably be faster to use a branch here too. */
11707 if (code == UNEQ && HONOR_NANS (compare_mode))
11710 if (GET_CODE (op1) == CONST_DOUBLE)
11711 REAL_VALUE_FROM_CONST_DOUBLE (c1, op1);
11713 /* We're going to try to implement comparisons by performing
11714 a subtract, then comparing against zero. Unfortunately,
11715 Inf - Inf is NaN which is not zero, and so if we don't
11716 know that the operand is finite and the comparison
11717 would treat EQ different to UNORDERED, we can't do it. */
11718 if (HONOR_INFINITIES (compare_mode)
11719 && code != GT && code != UNGE
11720 && (GET_CODE (op1) != CONST_DOUBLE || real_isinf (&c1))
11721 /* Constructs of the form (a OP b ? a : b) are safe. */
11722 && ((! rtx_equal_p (op0, false_cond) && ! rtx_equal_p (op1, false_cond))
11723 || (! rtx_equal_p (op0, true_cond)
11724 && ! rtx_equal_p (op1, true_cond))))
11727 /* At this point we know we can use fsel. */
11729 /* Reduce the comparison to a comparison against zero. */
11730 if (! is_against_zero)
11732 temp = gen_reg_rtx (compare_mode);
11733 emit_insn (gen_rtx_SET (VOIDmode, temp,
11734 gen_rtx_MINUS (compare_mode, op0, op1)));
11736 op1 = CONST0_RTX (compare_mode);
11739 /* If we don't care about NaNs we can reduce some of the comparisons
11740 down to faster ones. */
11741 if (! HONOR_NANS (compare_mode))
11747 true_cond = false_cond;
11760 /* Now, reduce everything down to a GE. */
11767 temp = gen_reg_rtx (compare_mode);
11768 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11773 temp = gen_reg_rtx (compare_mode);
11774 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_ABS (compare_mode, op0)));
11779 temp = gen_reg_rtx (compare_mode);
11780 emit_insn (gen_rtx_SET (VOIDmode, temp,
11781 gen_rtx_NEG (compare_mode,
11782 gen_rtx_ABS (compare_mode, op0))));
11787 /* a UNGE 0 <-> (a GE 0 || -a UNLT 0) */
11788 temp = gen_reg_rtx (result_mode);
11789 emit_insn (gen_rtx_SET (VOIDmode, temp,
11790 gen_rtx_IF_THEN_ELSE (result_mode,
11791 gen_rtx_GE (VOIDmode,
11793 true_cond, false_cond)));
11794 false_cond = true_cond;
11797 temp = gen_reg_rtx (compare_mode);
11798 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11803 /* a GT 0 <-> (a GE 0 && -a UNLT 0) */
11804 temp = gen_reg_rtx (result_mode);
11805 emit_insn (gen_rtx_SET (VOIDmode, temp,
11806 gen_rtx_IF_THEN_ELSE (result_mode,
11807 gen_rtx_GE (VOIDmode,
11809 true_cond, false_cond)));
11810 true_cond = false_cond;
11813 temp = gen_reg_rtx (compare_mode);
11814 emit_insn (gen_rtx_SET (VOIDmode, temp, gen_rtx_NEG (compare_mode, op0)));
11819 gcc_unreachable ();
11822 emit_insn (gen_rtx_SET (VOIDmode, dest,
11823 gen_rtx_IF_THEN_ELSE (result_mode,
11824 gen_rtx_GE (VOIDmode,
11826 true_cond, false_cond)));
11830 /* Same as above, but for ints (isel). */
11833 rs6000_emit_int_cmove (rtx dest, rtx op, rtx true_cond, rtx false_cond)
11835 rtx condition_rtx, cr;
11837 /* All isel implementations thus far are 32-bits. */
11838 if (GET_MODE (rs6000_compare_op0) != SImode)
11841 /* We still have to do the compare, because isel doesn't do a
11842 compare, it just looks at the CRx bits set by a previous compare
11844 condition_rtx = rs6000_generate_compare (GET_CODE (op));
11845 cr = XEXP (condition_rtx, 0);
11847 if (GET_MODE (cr) == CCmode)
11848 emit_insn (gen_isel_signed (dest, condition_rtx,
11849 true_cond, false_cond, cr));
11851 emit_insn (gen_isel_unsigned (dest, condition_rtx,
11852 true_cond, false_cond, cr));
11858 output_isel (rtx *operands)
11860 enum rtx_code code;
11862 code = GET_CODE (operands[1]);
11863 if (code == GE || code == GEU || code == LE || code == LEU || code == NE)
11865 PUT_CODE (operands[1], reverse_condition (code));
11866 return "isel %0,%3,%2,%j1";
11869 return "isel %0,%2,%3,%j1";
11873 rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1)
11875 enum machine_mode mode = GET_MODE (op0);
11879 if (code == SMAX || code == SMIN)
11884 if (code == SMAX || code == UMAX)
11885 target = emit_conditional_move (dest, c, op0, op1, mode,
11886 op0, op1, mode, 0);
11888 target = emit_conditional_move (dest, c, op0, op1, mode,
11889 op1, op0, mode, 0);
11890 gcc_assert (target);
11891 if (target != dest)
11892 emit_move_insn (dest, target);
11895 /* Emit instructions to perform a load-reserved/store-conditional operation.
11896 The operation performed is an atomic
11897 (set M (CODE:MODE M OP))
11898 If not NULL, BEFORE is atomically set to M before the operation, and
11899 AFTER is set to M after the operation (that is, (CODE:MODE M OP)).
11900 If SYNC_P then a memory barrier is emitted before the operation.
11901 Either OP or M may be wrapped in a NOT operation. */
11904 rs6000_emit_sync (enum rtx_code code, enum machine_mode mode,
11905 rtx m, rtx op, rtx before_param, rtx after_param,
11908 enum machine_mode used_mode;
11909 rtx the_op, set_before, set_after, set_atomic, cc_scratch, before, after;
11912 HOST_WIDE_INT imask = GET_MODE_MASK (mode);
11913 rtx shift = NULL_RTX;
11916 emit_insn (gen_memory_barrier ());
11918 if (GET_CODE (m) == NOT)
11919 used_m = XEXP (m, 0);
11923 /* If this is smaller than SImode, we'll have to use SImode with
11925 if (mode == QImode || mode == HImode)
11929 if (MEM_ALIGN (used_m) >= 32)
11932 if (BYTES_BIG_ENDIAN)
11933 ishift = GET_MODE_BITSIZE (SImode) - GET_MODE_BITSIZE (mode);
11935 shift = GEN_INT (ishift);
11939 rtx addrSI, aligned_addr;
11940 int shift_mask = mode == QImode ? 0x18 : 0x10;
11942 addrSI = force_reg (SImode, gen_lowpart_common (SImode,
11943 XEXP (used_m, 0)));
11944 shift = gen_reg_rtx (SImode);
11946 emit_insn (gen_rlwinm (shift, addrSI, GEN_INT (3),
11947 GEN_INT (shift_mask)));
11948 emit_insn (gen_xorsi3 (shift, shift, GEN_INT (shift_mask)));
11950 aligned_addr = expand_binop (Pmode, and_optab,
11952 GEN_INT (-4), NULL_RTX,
11953 1, OPTAB_LIB_WIDEN);
11954 used_m = change_address (used_m, SImode, aligned_addr);
11955 set_mem_align (used_m, 32);
11956 /* It's safe to keep the old alias set of USED_M, because
11957 the operation is atomic and only affects the original
11959 if (GET_CODE (m) == NOT)
11960 m = gen_rtx_NOT (SImode, used_m);
11965 if (GET_CODE (op) == NOT)
11967 oldop = lowpart_subreg (SImode, XEXP (op, 0), mode);
11968 oldop = gen_rtx_NOT (SImode, oldop);
11971 oldop = lowpart_subreg (SImode, op, mode);
11977 newop = expand_binop (SImode, and_optab,
11978 oldop, GEN_INT (imask), NULL_RTX,
11979 1, OPTAB_LIB_WIDEN);
11980 emit_insn (gen_ashlsi3 (newop, newop, shift));
11984 newop = expand_binop (SImode, ior_optab,
11985 oldop, GEN_INT (~imask), NULL_RTX,
11986 1, OPTAB_LIB_WIDEN);
11987 emit_insn (gen_rotlsi3 (newop, newop, shift));
11995 newop = expand_binop (SImode, and_optab,
11996 oldop, GEN_INT (imask), NULL_RTX,
11997 1, OPTAB_LIB_WIDEN);
11998 emit_insn (gen_ashlsi3 (newop, newop, shift));
12000 mask = gen_reg_rtx (SImode);
12001 emit_move_insn (mask, GEN_INT (imask));
12002 emit_insn (gen_ashlsi3 (mask, mask, shift));
12005 newop = gen_rtx_PLUS (SImode, m, newop);
12007 newop = gen_rtx_MINUS (SImode, m, newop);
12008 newop = gen_rtx_AND (SImode, newop, mask);
12009 newop = gen_rtx_IOR (SImode, newop,
12010 gen_rtx_AND (SImode,
12011 gen_rtx_NOT (SImode, mask),
12017 gcc_unreachable ();
12020 if (GET_CODE (m) == NOT)
12024 mask = gen_reg_rtx (SImode);
12025 emit_move_insn (mask, GEN_INT (imask));
12026 emit_insn (gen_ashlsi3 (mask, mask, shift));
12028 xorm = gen_rtx_XOR (SImode, used_m, mask);
12029 /* Depending on the value of 'op', the XOR or the operation might
12030 be able to be simplified away. */
12031 newop = simplify_gen_binary (code, SImode, xorm, newop);
12034 used_mode = SImode;
12035 before = gen_reg_rtx (used_mode);
12036 after = gen_reg_rtx (used_mode);
12041 before = before_param;
12042 after = after_param;
12044 if (before == NULL_RTX)
12045 before = gen_reg_rtx (used_mode);
12046 if (after == NULL_RTX)
12047 after = gen_reg_rtx (used_mode);
12050 if ((code == PLUS || code == MINUS || GET_CODE (m) == NOT)
12051 && used_mode != mode)
12052 the_op = op; /* Computed above. */
12053 else if (GET_CODE (op) == NOT && GET_CODE (m) != NOT)
12054 the_op = gen_rtx_fmt_ee (code, used_mode, op, m);
12056 the_op = gen_rtx_fmt_ee (code, used_mode, m, op);
12058 set_after = gen_rtx_SET (VOIDmode, after, the_op);
12059 set_before = gen_rtx_SET (VOIDmode, before, used_m);
12060 set_atomic = gen_rtx_SET (VOIDmode, used_m,
12061 gen_rtx_UNSPEC (used_mode,
12062 gen_rtvec (1, the_op),
12064 cc_scratch = gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (CCmode));
12066 if ((code == PLUS || code == MINUS) && used_mode != mode)
12067 vec = gen_rtvec (5, set_after, set_before, set_atomic, cc_scratch,
12068 gen_rtx_CLOBBER (VOIDmode, gen_rtx_SCRATCH (SImode)));
12070 vec = gen_rtvec (4, set_after, set_before, set_atomic, cc_scratch);
12071 emit_insn (gen_rtx_PARALLEL (VOIDmode, vec));
12073 /* Shift and mask the return values properly. */
12074 if (used_mode != mode && before_param)
12076 emit_insn (gen_lshrsi3 (before, before, shift));
12077 convert_move (before_param, before, 1);
12080 if (used_mode != mode && after_param)
12082 emit_insn (gen_lshrsi3 (after, after, shift));
12083 convert_move (after_param, after, 1);
12086 /* The previous sequence will end with a branch that's dependent on
12087 the conditional store, so placing an isync will ensure that no
12088 other instructions (especially, no load or store instructions)
12089 can start before the atomic operation completes. */
12091 emit_insn (gen_isync ());
12094 /* A subroutine of the atomic operation splitters. Jump to LABEL if
12095 COND is true. Mark the jump as unlikely to be taken. */
12098 emit_unlikely_jump (rtx cond, rtx label)
12100 rtx very_unlikely = GEN_INT (REG_BR_PROB_BASE / 100 - 1);
12103 x = gen_rtx_IF_THEN_ELSE (VOIDmode, cond, label, pc_rtx);
12104 x = emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx, x));
12105 REG_NOTES (x) = gen_rtx_EXPR_LIST (REG_BR_PROB, very_unlikely, NULL_RTX);
12108 /* A subroutine of the atomic operation splitters. Emit a load-locked
12109 instruction in MODE. */
12112 emit_load_locked (enum machine_mode mode, rtx reg, rtx mem)
12114 rtx (*fn) (rtx, rtx) = NULL;
12115 if (mode == SImode)
12116 fn = gen_load_locked_si;
12117 else if (mode == DImode)
12118 fn = gen_load_locked_di;
12119 emit_insn (fn (reg, mem));
12122 /* A subroutine of the atomic operation splitters. Emit a store-conditional
12123 instruction in MODE. */
12126 emit_store_conditional (enum machine_mode mode, rtx res, rtx mem, rtx val)
12128 rtx (*fn) (rtx, rtx, rtx) = NULL;
12129 if (mode == SImode)
12130 fn = gen_store_conditional_si;
12131 else if (mode == DImode)
12132 fn = gen_store_conditional_di;
12134 /* Emit sync before stwcx. to address PPC405 Erratum. */
12135 if (PPC405_ERRATUM77)
12136 emit_insn (gen_memory_barrier ());
12138 emit_insn (fn (res, mem, val));
12141 /* Expand an an atomic fetch-and-operate pattern. CODE is the binary operation
12142 to perform. MEM is the memory on which to operate. VAL is the second
12143 operand of the binary operator. BEFORE and AFTER are optional locations to
12144 return the value of MEM either before of after the operation. SCRATCH is
12145 a scratch register. */
12148 rs6000_split_atomic_op (enum rtx_code code, rtx mem, rtx val,
12149 rtx before, rtx after, rtx scratch)
12151 enum machine_mode mode = GET_MODE (mem);
12152 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12154 emit_insn (gen_memory_barrier ());
12156 label = gen_label_rtx ();
12157 emit_label (label);
12158 label = gen_rtx_LABEL_REF (VOIDmode, label);
12160 if (before == NULL_RTX)
12162 emit_load_locked (mode, before, mem);
12165 x = gen_rtx_AND (mode, gen_rtx_NOT (mode, before), val);
12166 else if (code == AND)
12167 x = gen_rtx_UNSPEC (mode, gen_rtvec (2, before, val), UNSPEC_AND);
12169 x = gen_rtx_fmt_ee (code, mode, before, val);
12171 if (after != NULL_RTX)
12172 emit_insn (gen_rtx_SET (VOIDmode, after, copy_rtx (x)));
12173 emit_insn (gen_rtx_SET (VOIDmode, scratch, x));
12175 emit_store_conditional (mode, cond, mem, scratch);
12177 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12178 emit_unlikely_jump (x, label);
12180 emit_insn (gen_isync ());
12183 /* Expand an atomic compare and swap operation. MEM is the memory on which
12184 to operate. OLDVAL is the old value to be compared. NEWVAL is the new
12185 value to be stored. SCRATCH is a scratch GPR. */
12188 rs6000_split_compare_and_swap (rtx retval, rtx mem, rtx oldval, rtx newval,
12191 enum machine_mode mode = GET_MODE (mem);
12192 rtx label1, label2, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12194 emit_insn (gen_memory_barrier ());
12196 label1 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12197 label2 = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12198 emit_label (XEXP (label1, 0));
12200 emit_load_locked (mode, retval, mem);
12202 x = gen_rtx_COMPARE (CCmode, retval, oldval);
12203 emit_insn (gen_rtx_SET (VOIDmode, cond, x));
12205 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12206 emit_unlikely_jump (x, label2);
12208 emit_move_insn (scratch, newval);
12209 emit_store_conditional (mode, cond, mem, scratch);
12211 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12212 emit_unlikely_jump (x, label1);
12214 emit_insn (gen_isync ());
12215 emit_label (XEXP (label2, 0));
12218 /* Expand an atomic test and set operation. MEM is the memory on which
12219 to operate. VAL is the value set. SCRATCH is a scratch GPR. */
12222 rs6000_split_lock_test_and_set (rtx retval, rtx mem, rtx val, rtx scratch)
12224 enum machine_mode mode = GET_MODE (mem);
12225 rtx label, x, cond = gen_rtx_REG (CCmode, CR0_REGNO);
12227 emit_insn (gen_memory_barrier ());
12229 label = gen_rtx_LABEL_REF (VOIDmode, gen_label_rtx ());
12230 emit_label (XEXP (label, 0));
12232 emit_load_locked (mode, retval, mem);
12233 emit_move_insn (scratch, val);
12234 emit_store_conditional (mode, cond, mem, scratch);
12236 x = gen_rtx_NE (VOIDmode, cond, const0_rtx);
12237 emit_unlikely_jump (x, label);
12239 emit_insn (gen_isync ());
12242 /* Emit instructions to move SRC to DST. Called by splitters for
12243 multi-register moves. It will emit at most one instruction for
12244 each register that is accessed; that is, it won't emit li/lis pairs
12245 (or equivalent for 64-bit code). One of SRC or DST must be a hard
12249 rs6000_split_multireg_move (rtx dst, rtx src)
12251 /* The register number of the first register being moved. */
12253 /* The mode that is to be moved. */
12254 enum machine_mode mode;
12255 /* The mode that the move is being done in, and its size. */
12256 enum machine_mode reg_mode;
12258 /* The number of registers that will be moved. */
12261 reg = REG_P (dst) ? REGNO (dst) : REGNO (src);
12262 mode = GET_MODE (dst);
12263 nregs = hard_regno_nregs[reg][mode];
12264 if (FP_REGNO_P (reg))
12266 else if (ALTIVEC_REGNO_P (reg))
12267 reg_mode = V16QImode;
12269 reg_mode = word_mode;
12270 reg_mode_size = GET_MODE_SIZE (reg_mode);
12272 gcc_assert (reg_mode_size * nregs == GET_MODE_SIZE (mode));
12274 if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst)))
12276 /* Move register range backwards, if we might have destructive
12279 for (i = nregs - 1; i >= 0; i--)
12280 emit_insn (gen_rtx_SET (VOIDmode,
12281 simplify_gen_subreg (reg_mode, dst, mode,
12282 i * reg_mode_size),
12283 simplify_gen_subreg (reg_mode, src, mode,
12284 i * reg_mode_size)));
12290 bool used_update = false;
12292 if (MEM_P (src) && INT_REGNO_P (reg))
12296 if (GET_CODE (XEXP (src, 0)) == PRE_INC
12297 || GET_CODE (XEXP (src, 0)) == PRE_DEC)
12300 breg = XEXP (XEXP (src, 0), 0);
12301 delta_rtx = (GET_CODE (XEXP (src, 0)) == PRE_INC
12302 ? GEN_INT (GET_MODE_SIZE (GET_MODE (src)))
12303 : GEN_INT (-GET_MODE_SIZE (GET_MODE (src))));
12304 emit_insn (TARGET_32BIT
12305 ? gen_addsi3 (breg, breg, delta_rtx)
12306 : gen_adddi3 (breg, breg, delta_rtx));
12307 src = gen_rtx_MEM (mode, breg);
12309 else if (! offsettable_memref_p (src))
12311 rtx newsrc, basereg;
12312 basereg = gen_rtx_REG (Pmode, reg);
12313 emit_insn (gen_rtx_SET (VOIDmode, basereg, XEXP (src, 0)));
12314 newsrc = gen_rtx_MEM (GET_MODE (src), basereg);
12315 MEM_COPY_ATTRIBUTES (newsrc, src);
12319 breg = XEXP (src, 0);
12320 if (GET_CODE (breg) == PLUS || GET_CODE (breg) == LO_SUM)
12321 breg = XEXP (breg, 0);
12323 /* If the base register we are using to address memory is
12324 also a destination reg, then change that register last. */
12326 && REGNO (breg) >= REGNO (dst)
12327 && REGNO (breg) < REGNO (dst) + nregs)
12328 j = REGNO (breg) - REGNO (dst);
12331 if (GET_CODE (dst) == MEM && INT_REGNO_P (reg))
12335 if (GET_CODE (XEXP (dst, 0)) == PRE_INC
12336 || GET_CODE (XEXP (dst, 0)) == PRE_DEC)
12339 breg = XEXP (XEXP (dst, 0), 0);
12340 delta_rtx = (GET_CODE (XEXP (dst, 0)) == PRE_INC
12341 ? GEN_INT (GET_MODE_SIZE (GET_MODE (dst)))
12342 : GEN_INT (-GET_MODE_SIZE (GET_MODE (dst))));
12344 /* We have to update the breg before doing the store.
12345 Use store with update, if available. */
12349 rtx nsrc = simplify_gen_subreg (reg_mode, src, mode, 0);
12350 emit_insn (TARGET_32BIT
12351 ? (TARGET_POWERPC64
12352 ? gen_movdi_si_update (breg, breg, delta_rtx, nsrc)
12353 : gen_movsi_update (breg, breg, delta_rtx, nsrc))
12354 : gen_movdi_di_update (breg, breg, delta_rtx, nsrc));
12355 used_update = true;
12358 emit_insn (TARGET_32BIT
12359 ? gen_addsi3 (breg, breg, delta_rtx)
12360 : gen_adddi3 (breg, breg, delta_rtx));
12361 dst = gen_rtx_MEM (mode, breg);
12364 gcc_assert (offsettable_memref_p (dst));
12367 for (i = 0; i < nregs; i++)
12369 /* Calculate index to next subword. */
12374 /* If compiler already emitted move of first word by
12375 store with update, no need to do anything. */
12376 if (j == 0 && used_update)
12379 emit_insn (gen_rtx_SET (VOIDmode,
12380 simplify_gen_subreg (reg_mode, dst, mode,
12381 j * reg_mode_size),
12382 simplify_gen_subreg (reg_mode, src, mode,
12383 j * reg_mode_size)));
12389 /* This page contains routines that are used to determine what the
12390 function prologue and epilogue code will do and write them out. */
12392 /* Return the first fixed-point register that is required to be
12393 saved. 32 if none. */
12396 first_reg_to_save (void)
12400 /* Find lowest numbered live register. */
12401 for (first_reg = 13; first_reg <= 31; first_reg++)
12402 if (regs_ever_live[first_reg]
12403 && (! call_used_regs[first_reg]
12404 || (first_reg == RS6000_PIC_OFFSET_TABLE_REGNUM
12405 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
12406 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)
12407 || (TARGET_TOC && TARGET_MINIMAL_TOC)))))
12412 && current_function_uses_pic_offset_table
12413 && first_reg > RS6000_PIC_OFFSET_TABLE_REGNUM)
12414 return RS6000_PIC_OFFSET_TABLE_REGNUM;
12420 /* Similar, for FP regs. */
12423 first_fp_reg_to_save (void)
12427 /* Find lowest numbered live register. */
12428 for (first_reg = 14 + 32; first_reg <= 63; first_reg++)
12429 if (regs_ever_live[first_reg])
12435 /* Similar, for AltiVec regs. */
12438 first_altivec_reg_to_save (void)
12442 /* Stack frame remains as is unless we are in AltiVec ABI. */
12443 if (! TARGET_ALTIVEC_ABI)
12444 return LAST_ALTIVEC_REGNO + 1;
12446 /* Find lowest numbered live register. */
12447 for (i = FIRST_ALTIVEC_REGNO + 20; i <= LAST_ALTIVEC_REGNO; ++i)
12448 if (regs_ever_live[i])
12454 /* Return a 32-bit mask of the AltiVec registers we need to set in
12455 VRSAVE. Bit n of the return value is 1 if Vn is live. The MSB in
12456 the 32-bit word is 0. */
12458 static unsigned int
12459 compute_vrsave_mask (void)
12461 unsigned int i, mask = 0;
12463 /* First, find out if we use _any_ altivec registers. */
12464 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
12465 if (regs_ever_live[i])
12466 mask |= ALTIVEC_REG_BIT (i);
12471 /* Next, remove the argument registers from the set. These must
12472 be in the VRSAVE mask set by the caller, so we don't need to add
12473 them in again. More importantly, the mask we compute here is
12474 used to generate CLOBBERs in the set_vrsave insn, and we do not
12475 wish the argument registers to die. */
12476 for (i = cfun->args_info.vregno - 1; i >= ALTIVEC_ARG_MIN_REG; --i)
12477 mask &= ~ALTIVEC_REG_BIT (i);
12479 /* Similarly, remove the return value from the set. */
12482 diddle_return_value (is_altivec_return_reg, &yes);
12484 mask &= ~ALTIVEC_REG_BIT (ALTIVEC_ARG_RETURN);
12490 /* For a very restricted set of circumstances, we can cut down the
12491 size of prologues/epilogues by calling our own save/restore-the-world
12495 compute_save_world_info (rs6000_stack_t *info_ptr)
12497 info_ptr->world_save_p = 1;
12498 info_ptr->world_save_p
12499 = (WORLD_SAVE_P (info_ptr)
12500 && DEFAULT_ABI == ABI_DARWIN
12501 && ! (current_function_calls_setjmp && flag_exceptions)
12502 && info_ptr->first_fp_reg_save == FIRST_SAVED_FP_REGNO
12503 && info_ptr->first_gp_reg_save == FIRST_SAVED_GP_REGNO
12504 && info_ptr->first_altivec_reg_save == FIRST_SAVED_ALTIVEC_REGNO
12505 && info_ptr->cr_save_p);
12507 /* This will not work in conjunction with sibcalls. Make sure there
12508 are none. (This check is expensive, but seldom executed.) */
12509 if (WORLD_SAVE_P (info_ptr))
12512 for ( insn = get_last_insn_anywhere (); insn; insn = PREV_INSN (insn))
12513 if ( GET_CODE (insn) == CALL_INSN
12514 && SIBLING_CALL_P (insn))
12516 info_ptr->world_save_p = 0;
12521 if (WORLD_SAVE_P (info_ptr))
12523 /* Even if we're not touching VRsave, make sure there's room on the
12524 stack for it, if it looks like we're calling SAVE_WORLD, which
12525 will attempt to save it. */
12526 info_ptr->vrsave_size = 4;
12528 /* "Save" the VRsave register too if we're saving the world. */
12529 if (info_ptr->vrsave_mask == 0)
12530 info_ptr->vrsave_mask = compute_vrsave_mask ();
12532 /* Because the Darwin register save/restore routines only handle
12533 F14 .. F31 and V20 .. V31 as per the ABI, perform a consistency
12535 gcc_assert (info_ptr->first_fp_reg_save >= FIRST_SAVED_FP_REGNO
12536 && (info_ptr->first_altivec_reg_save
12537 >= FIRST_SAVED_ALTIVEC_REGNO));
12544 is_altivec_return_reg (rtx reg, void *xyes)
12546 bool *yes = (bool *) xyes;
12547 if (REGNO (reg) == ALTIVEC_ARG_RETURN)
12552 /* Calculate the stack information for the current function. This is
12553 complicated by having two separate calling sequences, the AIX calling
12554 sequence and the V.4 calling sequence.
12556 AIX (and Darwin/Mac OS X) stack frames look like:
12558 SP----> +---------------------------------------+
12559 | back chain to caller | 0 0
12560 +---------------------------------------+
12561 | saved CR | 4 8 (8-11)
12562 +---------------------------------------+
12564 +---------------------------------------+
12565 | reserved for compilers | 12 24
12566 +---------------------------------------+
12567 | reserved for binders | 16 32
12568 +---------------------------------------+
12569 | saved TOC pointer | 20 40
12570 +---------------------------------------+
12571 | Parameter save area (P) | 24 48
12572 +---------------------------------------+
12573 | Alloca space (A) | 24+P etc.
12574 +---------------------------------------+
12575 | Local variable space (L) | 24+P+A
12576 +---------------------------------------+
12577 | Float/int conversion temporary (X) | 24+P+A+L
12578 +---------------------------------------+
12579 | Save area for AltiVec registers (W) | 24+P+A+L+X
12580 +---------------------------------------+
12581 | AltiVec alignment padding (Y) | 24+P+A+L+X+W
12582 +---------------------------------------+
12583 | Save area for VRSAVE register (Z) | 24+P+A+L+X+W+Y
12584 +---------------------------------------+
12585 | Save area for GP registers (G) | 24+P+A+X+L+X+W+Y+Z
12586 +---------------------------------------+
12587 | Save area for FP registers (F) | 24+P+A+X+L+X+W+Y+Z+G
12588 +---------------------------------------+
12589 old SP->| back chain to caller's caller |
12590 +---------------------------------------+
12592 The required alignment for AIX configurations is two words (i.e., 8
12596 V.4 stack frames look like:
12598 SP----> +---------------------------------------+
12599 | back chain to caller | 0
12600 +---------------------------------------+
12601 | caller's saved LR | 4
12602 +---------------------------------------+
12603 | Parameter save area (P) | 8
12604 +---------------------------------------+
12605 | Alloca space (A) | 8+P
12606 +---------------------------------------+
12607 | Varargs save area (V) | 8+P+A
12608 +---------------------------------------+
12609 | Local variable space (L) | 8+P+A+V
12610 +---------------------------------------+
12611 | Float/int conversion temporary (X) | 8+P+A+V+L
12612 +---------------------------------------+
12613 | Save area for AltiVec registers (W) | 8+P+A+V+L+X
12614 +---------------------------------------+
12615 | AltiVec alignment padding (Y) | 8+P+A+V+L+X+W
12616 +---------------------------------------+
12617 | Save area for VRSAVE register (Z) | 8+P+A+V+L+X+W+Y
12618 +---------------------------------------+
12619 | SPE: area for 64-bit GP registers |
12620 +---------------------------------------+
12621 | SPE alignment padding |
12622 +---------------------------------------+
12623 | saved CR (C) | 8+P+A+V+L+X+W+Y+Z
12624 +---------------------------------------+
12625 | Save area for GP registers (G) | 8+P+A+V+L+X+W+Y+Z+C
12626 +---------------------------------------+
12627 | Save area for FP registers (F) | 8+P+A+V+L+X+W+Y+Z+C+G
12628 +---------------------------------------+
12629 old SP->| back chain to caller's caller |
12630 +---------------------------------------+
12632 The required alignment for V.4 is 16 bytes, or 8 bytes if -meabi is
12633 given. (But note below and in sysv4.h that we require only 8 and
12634 may round up the size of our stack frame anyways. The historical
12635 reason is early versions of powerpc-linux which didn't properly
12636 align the stack at program startup. A happy side-effect is that
12637 -mno-eabi libraries can be used with -meabi programs.)
12639 The EABI configuration defaults to the V.4 layout. However,
12640 the stack alignment requirements may differ. If -mno-eabi is not
12641 given, the required stack alignment is 8 bytes; if -mno-eabi is
12642 given, the required alignment is 16 bytes. (But see V.4 comment
12645 #ifndef ABI_STACK_BOUNDARY
12646 #define ABI_STACK_BOUNDARY STACK_BOUNDARY
12649 static rs6000_stack_t *
12650 rs6000_stack_info (void)
12652 static rs6000_stack_t info, zero_info;
12653 rs6000_stack_t *info_ptr = &info;
12654 int reg_size = TARGET_32BIT ? 4 : 8;
12657 HOST_WIDE_INT non_fixed_size;
12659 /* Zero all fields portably. */
12664 /* Cache value so we don't rescan instruction chain over and over. */
12665 if (cfun->machine->insn_chain_scanned_p == 0)
12666 cfun->machine->insn_chain_scanned_p
12667 = spe_func_has_64bit_regs_p () + 1;
12668 info_ptr->spe_64bit_regs_used = cfun->machine->insn_chain_scanned_p - 1;
12671 /* Select which calling sequence. */
12672 info_ptr->abi = DEFAULT_ABI;
12674 /* Calculate which registers need to be saved & save area size. */
12675 info_ptr->first_gp_reg_save = first_reg_to_save ();
12676 /* Assume that we will have to save RS6000_PIC_OFFSET_TABLE_REGNUM,
12677 even if it currently looks like we won't. */
12678 if (((TARGET_TOC && TARGET_MINIMAL_TOC)
12679 || (flag_pic == 1 && DEFAULT_ABI == ABI_V4)
12680 || (flag_pic && DEFAULT_ABI == ABI_DARWIN))
12681 && info_ptr->first_gp_reg_save > RS6000_PIC_OFFSET_TABLE_REGNUM)
12682 info_ptr->gp_size = reg_size * (32 - RS6000_PIC_OFFSET_TABLE_REGNUM);
12684 info_ptr->gp_size = reg_size * (32 - info_ptr->first_gp_reg_save);
12686 /* For the SPE, we have an additional upper 32-bits on each GPR.
12687 Ideally we should save the entire 64-bits only when the upper
12688 half is used in SIMD instructions. Since we only record
12689 registers live (not the size they are used in), this proves
12690 difficult because we'd have to traverse the instruction chain at
12691 the right time, taking reload into account. This is a real pain,
12692 so we opt to save the GPRs in 64-bits always if but one register
12693 gets used in 64-bits. Otherwise, all the registers in the frame
12694 get saved in 32-bits.
12696 So... since when we save all GPRs (except the SP) in 64-bits, the
12697 traditional GP save area will be empty. */
12698 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12699 info_ptr->gp_size = 0;
12701 info_ptr->first_fp_reg_save = first_fp_reg_to_save ();
12702 info_ptr->fp_size = 8 * (64 - info_ptr->first_fp_reg_save);
12704 info_ptr->first_altivec_reg_save = first_altivec_reg_to_save ();
12705 info_ptr->altivec_size = 16 * (LAST_ALTIVEC_REGNO + 1
12706 - info_ptr->first_altivec_reg_save);
12708 /* Does this function call anything? */
12709 info_ptr->calls_p = (! current_function_is_leaf
12710 || cfun->machine->ra_needs_full_frame);
12712 /* Determine if we need to save the link register. */
12713 if (rs6000_ra_ever_killed ()
12714 || (DEFAULT_ABI == ABI_AIX
12715 && current_function_profile
12716 && !TARGET_PROFILE_KERNEL)
12717 #ifdef TARGET_RELOCATABLE
12718 || (TARGET_RELOCATABLE && (get_pool_size () != 0))
12720 || (info_ptr->first_fp_reg_save != 64
12721 && !FP_SAVE_INLINE (info_ptr->first_fp_reg_save))
12722 || info_ptr->first_altivec_reg_save <= LAST_ALTIVEC_REGNO
12723 || (DEFAULT_ABI == ABI_V4 && current_function_calls_alloca)
12724 || info_ptr->calls_p)
12726 info_ptr->lr_save_p = 1;
12727 regs_ever_live[LINK_REGISTER_REGNUM] = 1;
12730 /* Determine if we need to save the condition code registers. */
12731 if (regs_ever_live[CR2_REGNO]
12732 || regs_ever_live[CR3_REGNO]
12733 || regs_ever_live[CR4_REGNO])
12735 info_ptr->cr_save_p = 1;
12736 if (DEFAULT_ABI == ABI_V4)
12737 info_ptr->cr_size = reg_size;
12740 /* If the current function calls __builtin_eh_return, then we need
12741 to allocate stack space for registers that will hold data for
12742 the exception handler. */
12743 if (current_function_calls_eh_return)
12746 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
12749 /* SPE saves EH registers in 64-bits. */
12750 ehrd_size = i * (TARGET_SPE_ABI
12751 && info_ptr->spe_64bit_regs_used != 0
12752 ? UNITS_PER_SPE_WORD : UNITS_PER_WORD);
12757 /* Determine various sizes. */
12758 info_ptr->reg_size = reg_size;
12759 info_ptr->fixed_size = RS6000_SAVE_AREA;
12760 info_ptr->vars_size = RS6000_ALIGN (get_frame_size (), 8);
12761 info_ptr->parm_size = RS6000_ALIGN (current_function_outgoing_args_size,
12762 TARGET_ALTIVEC ? 16 : 8);
12763 if (FRAME_GROWS_DOWNWARD)
12764 info_ptr->vars_size
12765 += RS6000_ALIGN (info_ptr->fixed_size + info_ptr->vars_size
12766 + info_ptr->parm_size,
12767 ABI_STACK_BOUNDARY / BITS_PER_UNIT)
12768 - (info_ptr->fixed_size + info_ptr->vars_size
12769 + info_ptr->parm_size);
12771 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12772 info_ptr->spe_gp_size = 8 * (32 - info_ptr->first_gp_reg_save);
12774 info_ptr->spe_gp_size = 0;
12776 if (TARGET_ALTIVEC_ABI)
12777 info_ptr->vrsave_mask = compute_vrsave_mask ();
12779 info_ptr->vrsave_mask = 0;
12781 if (TARGET_ALTIVEC_VRSAVE && info_ptr->vrsave_mask)
12782 info_ptr->vrsave_size = 4;
12784 info_ptr->vrsave_size = 0;
12786 compute_save_world_info (info_ptr);
12788 /* Calculate the offsets. */
12789 switch (DEFAULT_ABI)
12793 gcc_unreachable ();
12797 info_ptr->fp_save_offset = - info_ptr->fp_size;
12798 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12800 if (TARGET_ALTIVEC_ABI)
12802 info_ptr->vrsave_save_offset
12803 = info_ptr->gp_save_offset - info_ptr->vrsave_size;
12805 /* Align stack so vector save area is on a quadword boundary. */
12806 if (info_ptr->altivec_size != 0)
12807 info_ptr->altivec_padding_size
12808 = 16 - (-info_ptr->vrsave_save_offset % 16);
12810 info_ptr->altivec_padding_size = 0;
12812 info_ptr->altivec_save_offset
12813 = info_ptr->vrsave_save_offset
12814 - info_ptr->altivec_padding_size
12815 - info_ptr->altivec_size;
12817 /* Adjust for AltiVec case. */
12818 info_ptr->ehrd_offset = info_ptr->altivec_save_offset - ehrd_size;
12821 info_ptr->ehrd_offset = info_ptr->gp_save_offset - ehrd_size;
12822 info_ptr->cr_save_offset = reg_size; /* first word when 64-bit. */
12823 info_ptr->lr_save_offset = 2*reg_size;
12827 info_ptr->fp_save_offset = - info_ptr->fp_size;
12828 info_ptr->gp_save_offset = info_ptr->fp_save_offset - info_ptr->gp_size;
12829 info_ptr->cr_save_offset = info_ptr->gp_save_offset - info_ptr->cr_size;
12831 if (TARGET_SPE_ABI && info_ptr->spe_64bit_regs_used != 0)
12833 /* Align stack so SPE GPR save area is aligned on a
12834 double-word boundary. */
12835 if (info_ptr->spe_gp_size != 0)
12836 info_ptr->spe_padding_size
12837 = 8 - (-info_ptr->cr_save_offset % 8);
12839 info_ptr->spe_padding_size = 0;
12841 info_ptr->spe_gp_save_offset
12842 = info_ptr->cr_save_offset
12843 - info_ptr->spe_padding_size
12844 - info_ptr->spe_gp_size;
12846 /* Adjust for SPE case. */
12847 info_ptr->toc_save_offset
12848 = info_ptr->spe_gp_save_offset - info_ptr->toc_size;
12850 else if (TARGET_ALTIVEC_ABI)
12852 info_ptr->vrsave_save_offset
12853 = info_ptr->cr_save_offset - info_ptr->vrsave_size;
12855 /* Align stack so vector save area is on a quadword boundary. */
12856 if (info_ptr->altivec_size != 0)
12857 info_ptr->altivec_padding_size
12858 = 16 - (-info_ptr->vrsave_save_offset % 16);
12860 info_ptr->altivec_padding_size = 0;
12862 info_ptr->altivec_save_offset
12863 = info_ptr->vrsave_save_offset
12864 - info_ptr->altivec_padding_size
12865 - info_ptr->altivec_size;
12867 /* Adjust for AltiVec case. */
12868 info_ptr->toc_save_offset
12869 = info_ptr->altivec_save_offset - info_ptr->toc_size;
12872 info_ptr->toc_save_offset = info_ptr->cr_save_offset - info_ptr->toc_size;
12873 info_ptr->ehrd_offset = info_ptr->toc_save_offset - ehrd_size;
12874 info_ptr->lr_save_offset = reg_size;
12878 save_align = (TARGET_ALTIVEC_ABI || DEFAULT_ABI == ABI_DARWIN) ? 16 : 8;
12879 info_ptr->save_size = RS6000_ALIGN (info_ptr->fp_size
12880 + info_ptr->gp_size
12881 + info_ptr->altivec_size
12882 + info_ptr->altivec_padding_size
12883 + info_ptr->spe_gp_size
12884 + info_ptr->spe_padding_size
12886 + info_ptr->cr_size
12887 + info_ptr->lr_size
12888 + info_ptr->vrsave_size
12889 + info_ptr->toc_size,
12892 non_fixed_size = (info_ptr->vars_size
12893 + info_ptr->parm_size
12894 + info_ptr->save_size);
12896 info_ptr->total_size = RS6000_ALIGN (non_fixed_size + info_ptr->fixed_size,
12897 ABI_STACK_BOUNDARY / BITS_PER_UNIT);
12899 /* Determine if we need to allocate any stack frame:
12901 For AIX we need to push the stack if a frame pointer is needed
12902 (because the stack might be dynamically adjusted), if we are
12903 debugging, if we make calls, or if the sum of fp_save, gp_save,
12904 and local variables are more than the space needed to save all
12905 non-volatile registers: 32-bit: 18*8 + 19*4 = 220 or 64-bit: 18*8
12906 + 18*8 = 288 (GPR13 reserved).
12908 For V.4 we don't have the stack cushion that AIX uses, but assume
12909 that the debugger can handle stackless frames. */
12911 if (info_ptr->calls_p)
12912 info_ptr->push_p = 1;
12914 else if (DEFAULT_ABI == ABI_V4)
12915 info_ptr->push_p = non_fixed_size != 0;
12917 else if (frame_pointer_needed)
12918 info_ptr->push_p = 1;
12920 else if (TARGET_XCOFF && write_symbols != NO_DEBUG)
12921 info_ptr->push_p = 1;
12924 info_ptr->push_p = non_fixed_size > (TARGET_32BIT ? 220 : 288);
12926 /* Zero offsets if we're not saving those registers. */
12927 if (info_ptr->fp_size == 0)
12928 info_ptr->fp_save_offset = 0;
12930 if (info_ptr->gp_size == 0)
12931 info_ptr->gp_save_offset = 0;
12933 if (! TARGET_ALTIVEC_ABI || info_ptr->altivec_size == 0)
12934 info_ptr->altivec_save_offset = 0;
12936 if (! TARGET_ALTIVEC_ABI || info_ptr->vrsave_mask == 0)
12937 info_ptr->vrsave_save_offset = 0;
12939 if (! TARGET_SPE_ABI
12940 || info_ptr->spe_64bit_regs_used == 0
12941 || info_ptr->spe_gp_size == 0)
12942 info_ptr->spe_gp_save_offset = 0;
12944 if (! info_ptr->lr_save_p)
12945 info_ptr->lr_save_offset = 0;
12947 if (! info_ptr->cr_save_p)
12948 info_ptr->cr_save_offset = 0;
12950 if (! info_ptr->toc_save_p)
12951 info_ptr->toc_save_offset = 0;
12956 /* Return true if the current function uses any GPRs in 64-bit SIMD
12960 spe_func_has_64bit_regs_p (void)
12964 /* Functions that save and restore all the call-saved registers will
12965 need to save/restore the registers in 64-bits. */
12966 if (current_function_calls_eh_return
12967 || current_function_calls_setjmp
12968 || current_function_has_nonlocal_goto)
12971 insns = get_insns ();
12973 for (insn = NEXT_INSN (insns); insn != NULL_RTX; insn = NEXT_INSN (insn))
12979 /* FIXME: This should be implemented with attributes...
12981 (set_attr "spe64" "true")....then,
12982 if (get_spe64(insn)) return true;
12984 It's the only reliable way to do the stuff below. */
12986 i = PATTERN (insn);
12987 if (GET_CODE (i) == SET)
12989 enum machine_mode mode = GET_MODE (SET_SRC (i));
12991 if (SPE_VECTOR_MODE (mode))
12993 if (TARGET_E500_DOUBLE && mode == DFmode)
13003 debug_stack_info (rs6000_stack_t *info)
13005 const char *abi_string;
13008 info = rs6000_stack_info ();
13010 fprintf (stderr, "\nStack information for function %s:\n",
13011 ((current_function_decl && DECL_NAME (current_function_decl))
13012 ? IDENTIFIER_POINTER (DECL_NAME (current_function_decl))
13017 default: abi_string = "Unknown"; break;
13018 case ABI_NONE: abi_string = "NONE"; break;
13019 case ABI_AIX: abi_string = "AIX"; break;
13020 case ABI_DARWIN: abi_string = "Darwin"; break;
13021 case ABI_V4: abi_string = "V.4"; break;
13024 fprintf (stderr, "\tABI = %5s\n", abi_string);
13026 if (TARGET_ALTIVEC_ABI)
13027 fprintf (stderr, "\tALTIVEC ABI extensions enabled.\n");
13029 if (TARGET_SPE_ABI)
13030 fprintf (stderr, "\tSPE ABI extensions enabled.\n");
13032 if (info->first_gp_reg_save != 32)
13033 fprintf (stderr, "\tfirst_gp_reg_save = %5d\n", info->first_gp_reg_save);
13035 if (info->first_fp_reg_save != 64)
13036 fprintf (stderr, "\tfirst_fp_reg_save = %5d\n", info->first_fp_reg_save);
13038 if (info->first_altivec_reg_save <= LAST_ALTIVEC_REGNO)
13039 fprintf (stderr, "\tfirst_altivec_reg_save = %5d\n",
13040 info->first_altivec_reg_save);
13042 if (info->lr_save_p)
13043 fprintf (stderr, "\tlr_save_p = %5d\n", info->lr_save_p);
13045 if (info->cr_save_p)
13046 fprintf (stderr, "\tcr_save_p = %5d\n", info->cr_save_p);
13048 if (info->toc_save_p)
13049 fprintf (stderr, "\ttoc_save_p = %5d\n", info->toc_save_p);
13051 if (info->vrsave_mask)
13052 fprintf (stderr, "\tvrsave_mask = 0x%x\n", info->vrsave_mask);
13055 fprintf (stderr, "\tpush_p = %5d\n", info->push_p);
13058 fprintf (stderr, "\tcalls_p = %5d\n", info->calls_p);
13060 if (info->gp_save_offset)
13061 fprintf (stderr, "\tgp_save_offset = %5d\n", info->gp_save_offset);
13063 if (info->fp_save_offset)
13064 fprintf (stderr, "\tfp_save_offset = %5d\n", info->fp_save_offset);
13066 if (info->altivec_save_offset)
13067 fprintf (stderr, "\taltivec_save_offset = %5d\n",
13068 info->altivec_save_offset);
13070 if (info->spe_gp_save_offset)
13071 fprintf (stderr, "\tspe_gp_save_offset = %5d\n",
13072 info->spe_gp_save_offset);
13074 if (info->vrsave_save_offset)
13075 fprintf (stderr, "\tvrsave_save_offset = %5d\n",
13076 info->vrsave_save_offset);
13078 if (info->lr_save_offset)
13079 fprintf (stderr, "\tlr_save_offset = %5d\n", info->lr_save_offset);
13081 if (info->cr_save_offset)
13082 fprintf (stderr, "\tcr_save_offset = %5d\n", info->cr_save_offset);
13084 if (info->toc_save_offset)
13085 fprintf (stderr, "\ttoc_save_offset = %5d\n", info->toc_save_offset);
13087 if (info->varargs_save_offset)
13088 fprintf (stderr, "\tvarargs_save_offset = %5d\n", info->varargs_save_offset);
13090 if (info->total_size)
13091 fprintf (stderr, "\ttotal_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13094 if (info->vars_size)
13095 fprintf (stderr, "\tvars_size = "HOST_WIDE_INT_PRINT_DEC"\n",
13098 if (info->parm_size)
13099 fprintf (stderr, "\tparm_size = %5d\n", info->parm_size);
13101 if (info->fixed_size)
13102 fprintf (stderr, "\tfixed_size = %5d\n", info->fixed_size);
13105 fprintf (stderr, "\tgp_size = %5d\n", info->gp_size);
13107 if (info->spe_gp_size)
13108 fprintf (stderr, "\tspe_gp_size = %5d\n", info->spe_gp_size);
13111 fprintf (stderr, "\tfp_size = %5d\n", info->fp_size);
13113 if (info->altivec_size)
13114 fprintf (stderr, "\taltivec_size = %5d\n", info->altivec_size);
13116 if (info->vrsave_size)
13117 fprintf (stderr, "\tvrsave_size = %5d\n", info->vrsave_size);
13119 if (info->altivec_padding_size)
13120 fprintf (stderr, "\taltivec_padding_size= %5d\n",
13121 info->altivec_padding_size);
13123 if (info->spe_padding_size)
13124 fprintf (stderr, "\tspe_padding_size = %5d\n",
13125 info->spe_padding_size);
13128 fprintf (stderr, "\tlr_size = %5d\n", info->lr_size);
13131 fprintf (stderr, "\tcr_size = %5d\n", info->cr_size);
13133 if (info->toc_size)
13134 fprintf (stderr, "\ttoc_size = %5d\n", info->toc_size);
13136 if (info->save_size)
13137 fprintf (stderr, "\tsave_size = %5d\n", info->save_size);
13139 if (info->reg_size != 4)
13140 fprintf (stderr, "\treg_size = %5d\n", info->reg_size);
13142 fprintf (stderr, "\n");
13146 rs6000_return_addr (int count, rtx frame)
13148 /* Currently we don't optimize very well between prolog and body
13149 code and for PIC code the code can be actually quite bad, so
13150 don't try to be too clever here. */
13151 if (count != 0 || (DEFAULT_ABI != ABI_AIX && flag_pic))
13153 cfun->machine->ra_needs_full_frame = 1;
13160 plus_constant (copy_to_reg
13161 (gen_rtx_MEM (Pmode,
13162 memory_address (Pmode, frame))),
13163 RETURN_ADDRESS_OFFSET)));
13166 cfun->machine->ra_need_lr = 1;
13167 return get_hard_reg_initial_val (Pmode, LINK_REGISTER_REGNUM);
13170 /* Say whether a function is a candidate for sibcall handling or not.
13171 We do not allow indirect calls to be optimized into sibling calls.
13172 Also, we can't do it if there are any vector parameters; there's
13173 nowhere to put the VRsave code so it works; note that functions with
13174 vector parameters are required to have a prototype, so the argument
13175 type info must be available here. (The tail recursion case can work
13176 with vector parameters, but there's no way to distinguish here.) */
13178 rs6000_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
13183 if (TARGET_ALTIVEC_VRSAVE)
13185 for (type = TYPE_ARG_TYPES (TREE_TYPE (decl));
13186 type; type = TREE_CHAIN (type))
13188 if (TREE_CODE (TREE_VALUE (type)) == VECTOR_TYPE)
13192 if (DEFAULT_ABI == ABI_DARWIN
13193 || (*targetm.binds_local_p) (decl))
13195 tree attr_list = TYPE_ATTRIBUTES (TREE_TYPE (decl));
13197 if (!lookup_attribute ("longcall", attr_list)
13198 || lookup_attribute ("shortcall", attr_list))
13205 /* NULL if INSN insn is valid within a low-overhead loop.
13206 Otherwise return why doloop cannot be applied.
13207 PowerPC uses the COUNT register for branch on table instructions. */
13209 static const char *
13210 rs6000_invalid_within_doloop (rtx insn)
13213 return "Function call in the loop.";
13216 && (GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
13217 || GET_CODE (PATTERN (insn)) == ADDR_VEC))
13218 return "Computed branch in the loop.";
13224 rs6000_ra_ever_killed (void)
13230 if (current_function_is_thunk)
13233 /* regs_ever_live has LR marked as used if any sibcalls are present,
13234 but this should not force saving and restoring in the
13235 pro/epilogue. Likewise, reg_set_between_p thinks a sibcall
13236 clobbers LR, so that is inappropriate. */
13238 /* Also, the prologue can generate a store into LR that
13239 doesn't really count, like this:
13242 bcl to set PIC register
13246 When we're called from the epilogue, we need to avoid counting
13247 this as a store. */
13249 push_topmost_sequence ();
13250 top = get_insns ();
13251 pop_topmost_sequence ();
13252 reg = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
13254 for (insn = NEXT_INSN (top); insn != NULL_RTX; insn = NEXT_INSN (insn))
13258 if (FIND_REG_INC_NOTE (insn, reg))
13260 else if (GET_CODE (insn) == CALL_INSN
13261 && !SIBLING_CALL_P (insn))
13263 else if (set_of (reg, insn) != NULL_RTX
13264 && !prologue_epilogue_contains (insn))
13271 /* Add a REG_MAYBE_DEAD note to the insn. */
13273 rs6000_maybe_dead (rtx insn)
13275 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
13280 /* Emit instructions needed to load the TOC register.
13281 This is only needed when TARGET_TOC, TARGET_MINIMAL_TOC, and there is
13282 a constant pool; or for SVR4 -fpic. */
13285 rs6000_emit_load_toc_table (int fromprolog)
13288 dest = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM);
13290 if (TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI != ABI_AIX && flag_pic)
13293 rtx lab, tmp1, tmp2, got, tempLR;
13295 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13296 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13298 got = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13300 got = rs6000_got_sym ();
13301 tmp1 = tmp2 = dest;
13304 tmp1 = gen_reg_rtx (Pmode);
13305 tmp2 = gen_reg_rtx (Pmode);
13307 tempLR = (fromprolog
13308 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13309 : gen_reg_rtx (Pmode));
13310 insn = emit_insn (gen_load_toc_v4_PIC_1 (tempLR, lab));
13312 rs6000_maybe_dead (insn);
13313 insn = emit_move_insn (tmp1, tempLR);
13315 rs6000_maybe_dead (insn);
13316 insn = emit_insn (gen_load_toc_v4_PIC_3b (tmp2, tmp1, got, lab));
13318 rs6000_maybe_dead (insn);
13319 insn = emit_insn (gen_load_toc_v4_PIC_3c (dest, tmp2, got, lab));
13321 rs6000_maybe_dead (insn);
13323 else if (TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 1)
13325 rtx tempLR = (fromprolog
13326 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13327 : gen_reg_rtx (Pmode));
13329 insn = emit_insn (gen_load_toc_v4_pic_si (tempLR));
13331 rs6000_maybe_dead (insn);
13332 insn = emit_move_insn (dest, tempLR);
13334 rs6000_maybe_dead (insn);
13336 else if (TARGET_ELF && DEFAULT_ABI != ABI_AIX && flag_pic == 2)
13339 rtx tempLR = (fromprolog
13340 ? gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM)
13341 : gen_reg_rtx (Pmode));
13342 rtx temp0 = (fromprolog
13343 ? gen_rtx_REG (Pmode, 0)
13344 : gen_reg_rtx (Pmode));
13350 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
13351 symF = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13353 ASM_GENERATE_INTERNAL_LABEL (buf, "LCL", rs6000_pic_labelno);
13354 symL = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13356 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_1 (tempLR,
13358 rs6000_maybe_dead (emit_move_insn (dest, tempLR));
13359 rs6000_maybe_dead (emit_insn (gen_load_toc_v4_PIC_2 (temp0, dest,
13367 tocsym = gen_rtx_SYMBOL_REF (Pmode, toc_label_name);
13368 emit_insn (gen_load_toc_v4_PIC_1b (tempLR, tocsym));
13369 emit_move_insn (dest, tempLR);
13370 emit_move_insn (temp0, gen_rtx_MEM (Pmode, dest));
13372 insn = emit_insn (gen_addsi3 (dest, temp0, dest));
13374 rs6000_maybe_dead (insn);
13376 else if (TARGET_ELF && !TARGET_AIX && flag_pic == 0 && TARGET_MINIMAL_TOC)
13378 /* This is for AIX code running in non-PIC ELF32. */
13381 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
13382 realsym = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf));
13384 insn = emit_insn (gen_elf_high (dest, realsym));
13386 rs6000_maybe_dead (insn);
13387 insn = emit_insn (gen_elf_low (dest, dest, realsym));
13389 rs6000_maybe_dead (insn);
13393 gcc_assert (DEFAULT_ABI == ABI_AIX);
13396 insn = emit_insn (gen_load_toc_aix_si (dest));
13398 insn = emit_insn (gen_load_toc_aix_di (dest));
13400 rs6000_maybe_dead (insn);
13404 /* Emit instructions to restore the link register after determining where
13405 its value has been stored. */
13408 rs6000_emit_eh_reg_restore (rtx source, rtx scratch)
13410 rs6000_stack_t *info = rs6000_stack_info ();
13413 operands[0] = source;
13414 operands[1] = scratch;
13416 if (info->lr_save_p)
13418 rtx frame_rtx = stack_pointer_rtx;
13419 HOST_WIDE_INT sp_offset = 0;
13422 if (frame_pointer_needed
13423 || current_function_calls_alloca
13424 || info->total_size > 32767)
13426 emit_move_insn (operands[1], gen_rtx_MEM (Pmode, frame_rtx));
13427 frame_rtx = operands[1];
13429 else if (info->push_p)
13430 sp_offset = info->total_size;
13432 tmp = plus_constant (frame_rtx, info->lr_save_offset + sp_offset);
13433 tmp = gen_rtx_MEM (Pmode, tmp);
13434 emit_move_insn (tmp, operands[0]);
13437 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM), operands[0]);
13440 static GTY(()) int set = -1;
13443 get_TOC_alias_set (void)
13446 set = new_alias_set ();
13450 /* This returns nonzero if the current function uses the TOC. This is
13451 determined by the presence of (use (unspec ... UNSPEC_TOC)), which
13452 is generated by the ABI_V4 load_toc_* patterns. */
13459 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
13462 rtx pat = PATTERN (insn);
13465 if (GET_CODE (pat) == PARALLEL)
13466 for (i = 0; i < XVECLEN (pat, 0); i++)
13468 rtx sub = XVECEXP (pat, 0, i);
13469 if (GET_CODE (sub) == USE)
13471 sub = XEXP (sub, 0);
13472 if (GET_CODE (sub) == UNSPEC
13473 && XINT (sub, 1) == UNSPEC_TOC)
13483 create_TOC_reference (rtx symbol)
13485 return gen_rtx_PLUS (Pmode,
13486 gen_rtx_REG (Pmode, TOC_REGISTER),
13487 gen_rtx_CONST (Pmode,
13488 gen_rtx_MINUS (Pmode, symbol,
13489 gen_rtx_SYMBOL_REF (Pmode, toc_label_name))));
13492 /* If _Unwind_* has been called from within the same module,
13493 toc register is not guaranteed to be saved to 40(1) on function
13494 entry. Save it there in that case. */
13497 rs6000_aix_emit_builtin_unwind_init (void)
13500 rtx stack_top = gen_reg_rtx (Pmode);
13501 rtx opcode_addr = gen_reg_rtx (Pmode);
13502 rtx opcode = gen_reg_rtx (SImode);
13503 rtx tocompare = gen_reg_rtx (SImode);
13504 rtx no_toc_save_needed = gen_label_rtx ();
13506 mem = gen_rtx_MEM (Pmode, hard_frame_pointer_rtx);
13507 emit_move_insn (stack_top, mem);
13509 mem = gen_rtx_MEM (Pmode,
13510 gen_rtx_PLUS (Pmode, stack_top,
13511 GEN_INT (2 * GET_MODE_SIZE (Pmode))));
13512 emit_move_insn (opcode_addr, mem);
13513 emit_move_insn (opcode, gen_rtx_MEM (SImode, opcode_addr));
13514 emit_move_insn (tocompare, gen_int_mode (TARGET_32BIT ? 0x80410014
13515 : 0xE8410028, SImode));
13517 do_compare_rtx_and_jump (opcode, tocompare, EQ, 1,
13518 SImode, NULL_RTX, NULL_RTX,
13519 no_toc_save_needed);
13521 mem = gen_rtx_MEM (Pmode,
13522 gen_rtx_PLUS (Pmode, stack_top,
13523 GEN_INT (5 * GET_MODE_SIZE (Pmode))));
13524 emit_move_insn (mem, gen_rtx_REG (Pmode, 2));
13525 emit_label (no_toc_save_needed);
13528 /* This ties together stack memory (MEM with an alias set of
13529 rs6000_sr_alias_set) and the change to the stack pointer. */
13532 rs6000_emit_stack_tie (void)
13534 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_REG (Pmode, STACK_POINTER_REGNUM));
13536 set_mem_alias_set (mem, rs6000_sr_alias_set);
13537 emit_insn (gen_stack_tie (mem));
13540 /* Emit the correct code for allocating stack space, as insns.
13541 If COPY_R12, make sure a copy of the old frame is left in r12.
13542 The generated code may use hard register 0 as a temporary. */
13545 rs6000_emit_allocate_stack (HOST_WIDE_INT size, int copy_r12)
13548 rtx stack_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13549 rtx tmp_reg = gen_rtx_REG (Pmode, 0);
13550 rtx todec = gen_int_mode (-size, Pmode);
13552 if (INTVAL (todec) != -size)
13554 warning (0, "stack frame too large");
13555 emit_insn (gen_trap ());
13559 if (current_function_limit_stack)
13561 if (REG_P (stack_limit_rtx)
13562 && REGNO (stack_limit_rtx) > 1
13563 && REGNO (stack_limit_rtx) <= 31)
13565 emit_insn (TARGET_32BIT
13566 ? gen_addsi3 (tmp_reg,
13569 : gen_adddi3 (tmp_reg,
13573 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13576 else if (GET_CODE (stack_limit_rtx) == SYMBOL_REF
13578 && DEFAULT_ABI == ABI_V4)
13580 rtx toload = gen_rtx_CONST (VOIDmode,
13581 gen_rtx_PLUS (Pmode,
13585 emit_insn (gen_elf_high (tmp_reg, toload));
13586 emit_insn (gen_elf_low (tmp_reg, tmp_reg, toload));
13587 emit_insn (gen_cond_trap (LTU, stack_reg, tmp_reg,
13591 warning (0, "stack limit expression is not supported");
13594 if (copy_r12 || ! TARGET_UPDATE)
13595 emit_move_insn (gen_rtx_REG (Pmode, 12), stack_reg);
13601 /* Need a note here so that try_split doesn't get confused. */
13602 if (get_last_insn () == NULL_RTX)
13603 emit_note (NOTE_INSN_DELETED);
13604 insn = emit_move_insn (tmp_reg, todec);
13605 try_split (PATTERN (insn), insn, 0);
13609 insn = emit_insn (TARGET_32BIT
13610 ? gen_movsi_update (stack_reg, stack_reg,
13612 : gen_movdi_di_update (stack_reg, stack_reg,
13613 todec, stack_reg));
13617 insn = emit_insn (TARGET_32BIT
13618 ? gen_addsi3 (stack_reg, stack_reg, todec)
13619 : gen_adddi3 (stack_reg, stack_reg, todec));
13620 emit_move_insn (gen_rtx_MEM (Pmode, stack_reg),
13621 gen_rtx_REG (Pmode, 12));
13624 RTX_FRAME_RELATED_P (insn) = 1;
13626 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13627 gen_rtx_SET (VOIDmode, stack_reg,
13628 gen_rtx_PLUS (Pmode, stack_reg,
13633 /* Add to 'insn' a note which is PATTERN (INSN) but with REG replaced
13634 with (plus:P (reg 1) VAL), and with REG2 replaced with RREG if REG2
13635 is not NULL. It would be nice if dwarf2out_frame_debug_expr could
13636 deduce these equivalences by itself so it wasn't necessary to hold
13637 its hand so much. */
13640 rs6000_frame_related (rtx insn, rtx reg, HOST_WIDE_INT val,
13641 rtx reg2, rtx rreg)
13645 /* copy_rtx will not make unique copies of registers, so we need to
13646 ensure we don't have unwanted sharing here. */
13648 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13651 reg = gen_raw_REG (GET_MODE (reg), REGNO (reg));
13653 real = copy_rtx (PATTERN (insn));
13655 if (reg2 != NULL_RTX)
13656 real = replace_rtx (real, reg2, rreg);
13658 real = replace_rtx (real, reg,
13659 gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode,
13660 STACK_POINTER_REGNUM),
13663 /* We expect that 'real' is either a SET or a PARALLEL containing
13664 SETs (and possibly other stuff). In a PARALLEL, all the SETs
13665 are important so they all have to be marked RTX_FRAME_RELATED_P. */
13667 if (GET_CODE (real) == SET)
13671 temp = simplify_rtx (SET_SRC (set));
13673 SET_SRC (set) = temp;
13674 temp = simplify_rtx (SET_DEST (set));
13676 SET_DEST (set) = temp;
13677 if (GET_CODE (SET_DEST (set)) == MEM)
13679 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13681 XEXP (SET_DEST (set), 0) = temp;
13688 gcc_assert (GET_CODE (real) == PARALLEL);
13689 for (i = 0; i < XVECLEN (real, 0); i++)
13690 if (GET_CODE (XVECEXP (real, 0, i)) == SET)
13692 rtx set = XVECEXP (real, 0, i);
13694 temp = simplify_rtx (SET_SRC (set));
13696 SET_SRC (set) = temp;
13697 temp = simplify_rtx (SET_DEST (set));
13699 SET_DEST (set) = temp;
13700 if (GET_CODE (SET_DEST (set)) == MEM)
13702 temp = simplify_rtx (XEXP (SET_DEST (set), 0));
13704 XEXP (SET_DEST (set), 0) = temp;
13706 RTX_FRAME_RELATED_P (set) = 1;
13711 real = spe_synthesize_frame_save (real);
13713 RTX_FRAME_RELATED_P (insn) = 1;
13714 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
13719 /* Given an SPE frame note, return a PARALLEL of SETs with the
13720 original note, plus a synthetic register save. */
13723 spe_synthesize_frame_save (rtx real)
13725 rtx synth, offset, reg, real2;
13727 if (GET_CODE (real) != SET
13728 || GET_MODE (SET_SRC (real)) != V2SImode)
13731 /* For the SPE, registers saved in 64-bits, get a PARALLEL for their
13732 frame related note. The parallel contains a set of the register
13733 being saved, and another set to a synthetic register (n+1200).
13734 This is so we can differentiate between 64-bit and 32-bit saves.
13735 Words cannot describe this nastiness. */
13737 gcc_assert (GET_CODE (SET_DEST (real)) == MEM
13738 && GET_CODE (XEXP (SET_DEST (real), 0)) == PLUS
13739 && GET_CODE (SET_SRC (real)) == REG);
13742 (set (mem (plus (reg x) (const y)))
13745 (set (mem (plus (reg x) (const y+4)))
13749 real2 = copy_rtx (real);
13750 PUT_MODE (SET_DEST (real2), SImode);
13751 reg = SET_SRC (real2);
13752 real2 = replace_rtx (real2, reg, gen_rtx_REG (SImode, REGNO (reg)));
13753 synth = copy_rtx (real2);
13755 if (BYTES_BIG_ENDIAN)
13757 offset = XEXP (XEXP (SET_DEST (real2), 0), 1);
13758 real2 = replace_rtx (real2, offset, GEN_INT (INTVAL (offset) + 4));
13761 reg = SET_SRC (synth);
13763 synth = replace_rtx (synth, reg,
13764 gen_rtx_REG (SImode, REGNO (reg) + 1200));
13766 offset = XEXP (XEXP (SET_DEST (synth), 0), 1);
13767 synth = replace_rtx (synth, offset,
13768 GEN_INT (INTVAL (offset)
13769 + (BYTES_BIG_ENDIAN ? 0 : 4)));
13771 RTX_FRAME_RELATED_P (synth) = 1;
13772 RTX_FRAME_RELATED_P (real2) = 1;
13773 if (BYTES_BIG_ENDIAN)
13774 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, synth, real2));
13776 real = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, real2, synth));
13781 /* Returns an insn that has a vrsave set operation with the
13782 appropriate CLOBBERs. */
13785 generate_set_vrsave (rtx reg, rs6000_stack_t *info, int epiloguep)
13788 rtx insn, clobs[TOTAL_ALTIVEC_REGS + 1];
13789 rtx vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
13792 = gen_rtx_SET (VOIDmode,
13794 gen_rtx_UNSPEC_VOLATILE (SImode,
13795 gen_rtvec (2, reg, vrsave),
13796 UNSPECV_SET_VRSAVE));
13800 /* We need to clobber the registers in the mask so the scheduler
13801 does not move sets to VRSAVE before sets of AltiVec registers.
13803 However, if the function receives nonlocal gotos, reload will set
13804 all call saved registers live. We will end up with:
13806 (set (reg 999) (mem))
13807 (parallel [ (set (reg vrsave) (unspec blah))
13808 (clobber (reg 999))])
13810 The clobber will cause the store into reg 999 to be dead, and
13811 flow will attempt to delete an epilogue insn. In this case, we
13812 need an unspec use/set of the register. */
13814 for (i = FIRST_ALTIVEC_REGNO; i <= LAST_ALTIVEC_REGNO; ++i)
13815 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
13817 if (!epiloguep || call_used_regs [i])
13818 clobs[nclobs++] = gen_rtx_CLOBBER (VOIDmode,
13819 gen_rtx_REG (V4SImode, i));
13822 rtx reg = gen_rtx_REG (V4SImode, i);
13825 = gen_rtx_SET (VOIDmode,
13827 gen_rtx_UNSPEC (V4SImode,
13828 gen_rtvec (1, reg), 27));
13832 insn = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nclobs));
13834 for (i = 0; i < nclobs; ++i)
13835 XVECEXP (insn, 0, i) = clobs[i];
13840 /* Save a register into the frame, and emit RTX_FRAME_RELATED_P notes.
13841 Save REGNO into [FRAME_REG + OFFSET] in mode MODE. */
13844 emit_frame_save (rtx frame_reg, rtx frame_ptr, enum machine_mode mode,
13845 unsigned int regno, int offset, HOST_WIDE_INT total_size)
13847 rtx reg, offset_rtx, insn, mem, addr, int_rtx;
13848 rtx replacea, replaceb;
13850 int_rtx = GEN_INT (offset);
13852 /* Some cases that need register indexed addressing. */
13853 if ((TARGET_ALTIVEC_ABI && ALTIVEC_VECTOR_MODE (mode))
13854 || (TARGET_E500_DOUBLE && mode == DFmode)
13856 && SPE_VECTOR_MODE (mode)
13857 && !SPE_CONST_OFFSET_OK (offset)))
13859 /* Whomever calls us must make sure r11 is available in the
13860 flow path of instructions in the prologue. */
13861 offset_rtx = gen_rtx_REG (Pmode, 11);
13862 emit_move_insn (offset_rtx, int_rtx);
13864 replacea = offset_rtx;
13865 replaceb = int_rtx;
13869 offset_rtx = int_rtx;
13870 replacea = NULL_RTX;
13871 replaceb = NULL_RTX;
13874 reg = gen_rtx_REG (mode, regno);
13875 addr = gen_rtx_PLUS (Pmode, frame_reg, offset_rtx);
13876 mem = gen_rtx_MEM (mode, addr);
13877 set_mem_alias_set (mem, rs6000_sr_alias_set);
13879 insn = emit_move_insn (mem, reg);
13881 rs6000_frame_related (insn, frame_ptr, total_size, replacea, replaceb);
13884 /* Emit an offset memory reference suitable for a frame store, while
13885 converting to a valid addressing mode. */
13888 gen_frame_mem_offset (enum machine_mode mode, rtx reg, int offset)
13890 rtx int_rtx, offset_rtx;
13892 int_rtx = GEN_INT (offset);
13894 if ((TARGET_SPE_ABI && SPE_VECTOR_MODE (mode))
13895 || (TARGET_E500_DOUBLE && mode == DFmode))
13897 offset_rtx = gen_rtx_REG (Pmode, FIXED_SCRATCH);
13898 emit_move_insn (offset_rtx, int_rtx);
13901 offset_rtx = int_rtx;
13903 return gen_rtx_MEM (mode, gen_rtx_PLUS (Pmode, reg, offset_rtx));
13906 /* Look for user-defined global regs. We should not save and restore these,
13907 and cannot use stmw/lmw if there are any in its range. */
13910 no_global_regs_above (int first_greg)
13913 for (i = 0; i < 32 - first_greg; i++)
13914 if (global_regs[first_greg + i])
13919 #ifndef TARGET_FIX_AND_CONTINUE
13920 #define TARGET_FIX_AND_CONTINUE 0
13923 /* Emit function prologue as insns. */
13926 rs6000_emit_prologue (void)
13928 rs6000_stack_t *info = rs6000_stack_info ();
13929 enum machine_mode reg_mode = Pmode;
13930 int reg_size = TARGET_32BIT ? 4 : 8;
13931 rtx sp_reg_rtx = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
13932 rtx frame_ptr_rtx = gen_rtx_REG (Pmode, 12);
13933 rtx frame_reg_rtx = sp_reg_rtx;
13934 rtx cr_save_rtx = NULL_RTX;
13936 int saving_FPRs_inline;
13937 int using_store_multiple;
13938 HOST_WIDE_INT sp_offset = 0;
13940 if (TARGET_FIX_AND_CONTINUE)
13942 /* gdb on darwin arranges to forward a function from the old
13943 address by modifying the first 5 instructions of the function
13944 to branch to the overriding function. This is necessary to
13945 permit function pointers that point to the old function to
13946 actually forward to the new function. */
13947 emit_insn (gen_nop ());
13948 emit_insn (gen_nop ());
13949 emit_insn (gen_nop ());
13950 emit_insn (gen_nop ());
13951 emit_insn (gen_nop ());
13954 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
13956 reg_mode = V2SImode;
13960 using_store_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
13961 && (!TARGET_SPE_ABI
13962 || info->spe_64bit_regs_used == 0)
13963 && info->first_gp_reg_save < 31
13964 && no_global_regs_above (info->first_gp_reg_save));
13965 saving_FPRs_inline = (info->first_fp_reg_save == 64
13966 || FP_SAVE_INLINE (info->first_fp_reg_save)
13967 || current_function_calls_eh_return
13968 || cfun->machine->ra_need_lr);
13970 /* For V.4, update stack before we do any saving and set back pointer. */
13972 && (DEFAULT_ABI == ABI_V4
13973 || current_function_calls_eh_return))
13975 if (info->total_size < 32767)
13976 sp_offset = info->total_size;
13978 frame_reg_rtx = frame_ptr_rtx;
13979 rs6000_emit_allocate_stack (info->total_size,
13980 (frame_reg_rtx != sp_reg_rtx
13981 && (info->cr_save_p
13983 || info->first_fp_reg_save < 64
13984 || info->first_gp_reg_save < 32
13986 if (frame_reg_rtx != sp_reg_rtx)
13987 rs6000_emit_stack_tie ();
13990 /* Handle world saves specially here. */
13991 if (WORLD_SAVE_P (info))
13997 /* save_world expects lr in r0. */
13998 if (info->lr_save_p)
14000 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14001 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14002 RTX_FRAME_RELATED_P (insn) = 1;
14005 /* The SAVE_WORLD and RESTORE_WORLD routines make a number of
14006 assumptions about the offsets of various bits of the stack
14008 gcc_assert (info->gp_save_offset == -220
14009 && info->fp_save_offset == -144
14010 && info->lr_save_offset == 8
14011 && info->cr_save_offset == 4
14014 && (!current_function_calls_eh_return
14015 || info->ehrd_offset == -432)
14016 && info->vrsave_save_offset == -224
14017 && info->altivec_save_offset == (-224 -16 -192));
14019 treg = gen_rtx_REG (SImode, 11);
14020 emit_move_insn (treg, GEN_INT (-info->total_size));
14022 /* SAVE_WORLD takes the caller's LR in R0 and the frame size
14023 in R11. It also clobbers R12, so beware! */
14025 /* Preserve CR2 for save_world prologues */
14027 sz += 32 - info->first_gp_reg_save;
14028 sz += 64 - info->first_fp_reg_save;
14029 sz += LAST_ALTIVEC_REGNO - info->first_altivec_reg_save + 1;
14030 p = rtvec_alloc (sz);
14032 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode,
14033 gen_rtx_REG (Pmode,
14034 LINK_REGISTER_REGNUM));
14035 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14036 gen_rtx_SYMBOL_REF (Pmode,
14038 /* We do floats first so that the instruction pattern matches
14040 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14042 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14043 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14044 GEN_INT (info->fp_save_offset
14045 + sp_offset + 8 * i));
14046 rtx mem = gen_rtx_MEM (DFmode, addr);
14047 set_mem_alias_set (mem, rs6000_sr_alias_set);
14049 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14051 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14053 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14054 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14055 GEN_INT (info->altivec_save_offset
14056 + sp_offset + 16 * i));
14057 rtx mem = gen_rtx_MEM (V4SImode, addr);
14058 set_mem_alias_set (mem, rs6000_sr_alias_set);
14060 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14062 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14064 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14065 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14066 GEN_INT (info->gp_save_offset
14067 + sp_offset + reg_size * i));
14068 rtx mem = gen_rtx_MEM (reg_mode, addr);
14069 set_mem_alias_set (mem, rs6000_sr_alias_set);
14071 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14075 /* CR register traditionally saved as CR2. */
14076 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14077 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14078 GEN_INT (info->cr_save_offset
14080 rtx mem = gen_rtx_MEM (reg_mode, addr);
14081 set_mem_alias_set (mem, rs6000_sr_alias_set);
14083 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, mem, reg);
14085 /* Prevent any attempt to delete the setting of r0 and treg! */
14086 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, gen_rtx_REG (Pmode, 0));
14087 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode, treg);
14088 RTVEC_ELT (p, j++) = gen_rtx_CLOBBER (VOIDmode, sp_reg_rtx);
14090 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14091 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14092 NULL_RTX, NULL_RTX);
14094 if (current_function_calls_eh_return)
14099 unsigned int regno = EH_RETURN_DATA_REGNO (i);
14100 if (regno == INVALID_REGNUM)
14102 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14103 info->ehrd_offset + sp_offset
14104 + reg_size * (int) i,
14110 /* Save AltiVec registers if needed. */
14111 if (!WORLD_SAVE_P (info) && TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14115 /* There should be a non inline version of this, for when we
14116 are saving lots of vector registers. */
14117 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14118 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14120 rtx areg, savereg, mem;
14123 offset = info->altivec_save_offset + sp_offset
14124 + 16 * (i - info->first_altivec_reg_save);
14126 savereg = gen_rtx_REG (V4SImode, i);
14128 areg = gen_rtx_REG (Pmode, 0);
14129 emit_move_insn (areg, GEN_INT (offset));
14131 /* AltiVec addressing mode is [reg+reg]. */
14132 mem = gen_rtx_MEM (V4SImode,
14133 gen_rtx_PLUS (Pmode, frame_reg_rtx, areg));
14135 set_mem_alias_set (mem, rs6000_sr_alias_set);
14137 insn = emit_move_insn (mem, savereg);
14139 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14140 areg, GEN_INT (offset));
14144 /* VRSAVE is a bit vector representing which AltiVec registers
14145 are used. The OS uses this to determine which vector
14146 registers to save on a context switch. We need to save
14147 VRSAVE on the stack frame, add whatever AltiVec registers we
14148 used in this function, and do the corresponding magic in the
14151 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14152 && info->vrsave_mask != 0)
14154 rtx reg, mem, vrsave;
14157 /* Get VRSAVE onto a GPR. Note that ABI_V4 might be using r12
14158 as frame_reg_rtx and r11 as the static chain pointer for
14159 nested functions. */
14160 reg = gen_rtx_REG (SImode, 0);
14161 vrsave = gen_rtx_REG (SImode, VRSAVE_REGNO);
14163 emit_insn (gen_get_vrsave_internal (reg));
14165 emit_insn (gen_rtx_SET (VOIDmode, reg, vrsave));
14167 if (!WORLD_SAVE_P (info))
14170 offset = info->vrsave_save_offset + sp_offset;
14172 = gen_rtx_MEM (SImode,
14173 gen_rtx_PLUS (Pmode, frame_reg_rtx, GEN_INT (offset)));
14174 set_mem_alias_set (mem, rs6000_sr_alias_set);
14175 insn = emit_move_insn (mem, reg);
14178 /* Include the registers in the mask. */
14179 emit_insn (gen_iorsi3 (reg, reg, GEN_INT ((int) info->vrsave_mask)));
14181 insn = emit_insn (generate_set_vrsave (reg, info, 0));
14184 /* If we use the link register, get it into r0. */
14185 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14187 insn = emit_move_insn (gen_rtx_REG (Pmode, 0),
14188 gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM));
14189 RTX_FRAME_RELATED_P (insn) = 1;
14192 /* If we need to save CR, put it into r12. */
14193 if (!WORLD_SAVE_P (info) && info->cr_save_p && frame_reg_rtx != frame_ptr_rtx)
14197 cr_save_rtx = gen_rtx_REG (SImode, 12);
14198 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14199 RTX_FRAME_RELATED_P (insn) = 1;
14200 /* Now, there's no way that dwarf2out_frame_debug_expr is going
14201 to understand '(unspec:SI [(reg:CC 68) ...] UNSPEC_MOVESI_FROM_CR)'.
14202 But that's OK. All we have to do is specify that _one_ condition
14203 code register is saved in this stack slot. The thrower's epilogue
14204 will then restore all the call-saved registers.
14205 We use CR2_REGNO (70) to be compatible with gcc-2.95 on Linux. */
14206 set = gen_rtx_SET (VOIDmode, cr_save_rtx,
14207 gen_rtx_REG (SImode, CR2_REGNO));
14208 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14213 /* Do any required saving of fpr's. If only one or two to save, do
14214 it ourselves. Otherwise, call function. */
14215 if (!WORLD_SAVE_P (info) && saving_FPRs_inline)
14218 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14219 if ((regs_ever_live[info->first_fp_reg_save+i]
14220 && ! call_used_regs[info->first_fp_reg_save+i]))
14221 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, DFmode,
14222 info->first_fp_reg_save + i,
14223 info->fp_save_offset + sp_offset + 8 * i,
14226 else if (!WORLD_SAVE_P (info) && info->first_fp_reg_save != 64)
14230 const char *alloc_rname;
14232 p = rtvec_alloc (2 + 64 - info->first_fp_reg_save);
14234 RTVEC_ELT (p, 0) = gen_rtx_CLOBBER (VOIDmode,
14235 gen_rtx_REG (Pmode,
14236 LINK_REGISTER_REGNUM));
14237 sprintf (rname, "%s%d%s", SAVE_FP_PREFIX,
14238 info->first_fp_reg_save - 32, SAVE_FP_SUFFIX);
14239 alloc_rname = ggc_strdup (rname);
14240 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
14241 gen_rtx_SYMBOL_REF (Pmode,
14243 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14245 rtx addr, reg, mem;
14246 reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14247 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14248 GEN_INT (info->fp_save_offset
14249 + sp_offset + 8*i));
14250 mem = gen_rtx_MEM (DFmode, addr);
14251 set_mem_alias_set (mem, rs6000_sr_alias_set);
14253 RTVEC_ELT (p, i + 2) = gen_rtx_SET (VOIDmode, mem, reg);
14255 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14256 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14257 NULL_RTX, NULL_RTX);
14260 /* Save GPRs. This is done as a PARALLEL if we are using
14261 the store-multiple instructions. */
14262 if (!WORLD_SAVE_P (info) && using_store_multiple)
14266 p = rtvec_alloc (32 - info->first_gp_reg_save);
14267 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14269 rtx addr, reg, mem;
14270 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14271 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14272 GEN_INT (info->gp_save_offset
14275 mem = gen_rtx_MEM (reg_mode, addr);
14276 set_mem_alias_set (mem, rs6000_sr_alias_set);
14278 RTVEC_ELT (p, i) = gen_rtx_SET (VOIDmode, mem, reg);
14280 insn = emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14281 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14282 NULL_RTX, NULL_RTX);
14284 else if (!WORLD_SAVE_P (info))
14287 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14288 if ((regs_ever_live[info->first_gp_reg_save + i]
14289 && (!call_used_regs[info->first_gp_reg_save + i]
14290 || (i + info->first_gp_reg_save
14291 == RS6000_PIC_OFFSET_TABLE_REGNUM
14292 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14293 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14294 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14295 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14297 rtx addr, reg, mem;
14298 reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14300 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14302 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14305 if (!SPE_CONST_OFFSET_OK (offset))
14307 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14308 emit_move_insn (b, GEN_INT (offset));
14311 b = GEN_INT (offset);
14313 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14314 mem = gen_rtx_MEM (V2SImode, addr);
14315 set_mem_alias_set (mem, rs6000_sr_alias_set);
14316 insn = emit_move_insn (mem, reg);
14318 if (GET_CODE (b) == CONST_INT)
14319 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14320 NULL_RTX, NULL_RTX);
14322 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14323 b, GEN_INT (offset));
14327 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14328 GEN_INT (info->gp_save_offset
14331 mem = gen_rtx_MEM (reg_mode, addr);
14332 set_mem_alias_set (mem, rs6000_sr_alias_set);
14334 insn = emit_move_insn (mem, reg);
14335 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14336 NULL_RTX, NULL_RTX);
14341 /* ??? There's no need to emit actual instructions here, but it's the
14342 easiest way to get the frame unwind information emitted. */
14343 if (!WORLD_SAVE_P (info) && current_function_calls_eh_return)
14345 unsigned int i, regno;
14347 /* In AIX ABI we need to pretend we save r2 here. */
14350 rtx addr, reg, mem;
14352 reg = gen_rtx_REG (reg_mode, 2);
14353 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14354 GEN_INT (sp_offset + 5 * reg_size));
14355 mem = gen_rtx_MEM (reg_mode, addr);
14356 set_mem_alias_set (mem, rs6000_sr_alias_set);
14358 insn = emit_move_insn (mem, reg);
14359 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14360 NULL_RTX, NULL_RTX);
14361 PATTERN (insn) = gen_blockage ();
14366 regno = EH_RETURN_DATA_REGNO (i);
14367 if (regno == INVALID_REGNUM)
14370 emit_frame_save (frame_reg_rtx, frame_ptr_rtx, reg_mode, regno,
14371 info->ehrd_offset + sp_offset
14372 + reg_size * (int) i,
14377 /* Save lr if we used it. */
14378 if (!WORLD_SAVE_P (info) && info->lr_save_p)
14380 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14381 GEN_INT (info->lr_save_offset + sp_offset));
14382 rtx reg = gen_rtx_REG (Pmode, 0);
14383 rtx mem = gen_rtx_MEM (Pmode, addr);
14384 /* This should not be of rs6000_sr_alias_set, because of
14385 __builtin_return_address. */
14387 insn = emit_move_insn (mem, reg);
14388 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14389 NULL_RTX, NULL_RTX);
14392 /* Save CR if we use any that must be preserved. */
14393 if (!WORLD_SAVE_P (info) && info->cr_save_p)
14395 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14396 GEN_INT (info->cr_save_offset + sp_offset));
14397 rtx mem = gen_rtx_MEM (SImode, addr);
14398 /* See the large comment above about why CR2_REGNO is used. */
14399 rtx magic_eh_cr_reg = gen_rtx_REG (SImode, CR2_REGNO);
14401 set_mem_alias_set (mem, rs6000_sr_alias_set);
14403 /* If r12 was used to hold the original sp, copy cr into r0 now
14405 if (REGNO (frame_reg_rtx) == 12)
14409 cr_save_rtx = gen_rtx_REG (SImode, 0);
14410 insn = emit_insn (gen_movesi_from_cr (cr_save_rtx));
14411 RTX_FRAME_RELATED_P (insn) = 1;
14412 set = gen_rtx_SET (VOIDmode, cr_save_rtx, magic_eh_cr_reg);
14413 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
14418 insn = emit_move_insn (mem, cr_save_rtx);
14420 rs6000_frame_related (insn, frame_ptr_rtx, info->total_size,
14421 NULL_RTX, NULL_RTX);
14424 /* Update stack and set back pointer unless this is V.4,
14425 for which it was done previously. */
14426 if (!WORLD_SAVE_P (info) && info->push_p
14427 && !(DEFAULT_ABI == ABI_V4 || current_function_calls_eh_return))
14428 rs6000_emit_allocate_stack (info->total_size, FALSE);
14430 /* Set frame pointer, if needed. */
14431 if (frame_pointer_needed)
14433 insn = emit_move_insn (gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
14435 RTX_FRAME_RELATED_P (insn) = 1;
14438 /* If we are using RS6000_PIC_OFFSET_TABLE_REGNUM, we need to set it up. */
14439 if ((TARGET_TOC && TARGET_MINIMAL_TOC && get_pool_size () != 0)
14440 || (DEFAULT_ABI == ABI_V4
14441 && (flag_pic == 1 || (flag_pic && TARGET_SECURE_PLT))
14442 && regs_ever_live[RS6000_PIC_OFFSET_TABLE_REGNUM]))
14444 /* If emit_load_toc_table will use the link register, we need to save
14445 it. We use R12 for this purpose because emit_load_toc_table
14446 can use register 0. This allows us to use a plain 'blr' to return
14447 from the procedure more often. */
14448 int save_LR_around_toc_setup = (TARGET_ELF
14449 && DEFAULT_ABI != ABI_AIX
14451 && ! info->lr_save_p
14452 && EDGE_COUNT (EXIT_BLOCK_PTR->preds) > 0);
14453 if (save_LR_around_toc_setup)
14455 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14457 insn = emit_move_insn (frame_ptr_rtx, lr);
14458 rs6000_maybe_dead (insn);
14459 RTX_FRAME_RELATED_P (insn) = 1;
14461 rs6000_emit_load_toc_table (TRUE);
14463 insn = emit_move_insn (lr, frame_ptr_rtx);
14464 rs6000_maybe_dead (insn);
14465 RTX_FRAME_RELATED_P (insn) = 1;
14468 rs6000_emit_load_toc_table (TRUE);
14472 if (DEFAULT_ABI == ABI_DARWIN
14473 && flag_pic && current_function_uses_pic_offset_table)
14475 rtx lr = gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM);
14476 rtx src = machopic_function_base_sym ();
14478 /* Save and restore LR locally around this call (in R0). */
14479 if (!info->lr_save_p)
14480 rs6000_maybe_dead (emit_move_insn (gen_rtx_REG (Pmode, 0), lr));
14482 rs6000_maybe_dead (emit_insn (gen_load_macho_picbase (lr, src)));
14484 insn = emit_move_insn (gen_rtx_REG (Pmode,
14485 RS6000_PIC_OFFSET_TABLE_REGNUM),
14487 rs6000_maybe_dead (insn);
14489 if (!info->lr_save_p)
14490 rs6000_maybe_dead (emit_move_insn (lr, gen_rtx_REG (Pmode, 0)));
14495 /* Write function prologue. */
14498 rs6000_output_function_prologue (FILE *file,
14499 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
14501 rs6000_stack_t *info = rs6000_stack_info ();
14503 if (TARGET_DEBUG_STACK)
14504 debug_stack_info (info);
14506 /* Write .extern for any function we will call to save and restore
14508 if (info->first_fp_reg_save < 64
14509 && !FP_SAVE_INLINE (info->first_fp_reg_save))
14510 fprintf (file, "\t.extern %s%d%s\n\t.extern %s%d%s\n",
14511 SAVE_FP_PREFIX, info->first_fp_reg_save - 32, SAVE_FP_SUFFIX,
14512 RESTORE_FP_PREFIX, info->first_fp_reg_save - 32,
14513 RESTORE_FP_SUFFIX);
14515 /* Write .extern for AIX common mode routines, if needed. */
14516 if (! TARGET_POWER && ! TARGET_POWERPC && ! common_mode_defined)
14518 fputs ("\t.extern __mulh\n", file);
14519 fputs ("\t.extern __mull\n", file);
14520 fputs ("\t.extern __divss\n", file);
14521 fputs ("\t.extern __divus\n", file);
14522 fputs ("\t.extern __quoss\n", file);
14523 fputs ("\t.extern __quous\n", file);
14524 common_mode_defined = 1;
14527 if (! HAVE_prologue)
14531 /* A NOTE_INSN_DELETED is supposed to be at the start and end of
14532 the "toplevel" insn chain. */
14533 emit_note (NOTE_INSN_DELETED);
14534 rs6000_emit_prologue ();
14535 emit_note (NOTE_INSN_DELETED);
14537 /* Expand INSN_ADDRESSES so final() doesn't crash. */
14541 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
14543 INSN_ADDRESSES_NEW (insn, addr);
14548 if (TARGET_DEBUG_STACK)
14549 debug_rtx_list (get_insns (), 100);
14550 final (get_insns (), file, FALSE);
14554 rs6000_pic_labelno++;
14557 /* Emit function epilogue as insns.
14559 At present, dwarf2out_frame_debug_expr doesn't understand
14560 register restores, so we don't bother setting RTX_FRAME_RELATED_P
14561 anywhere in the epilogue. Most of the insns below would in any case
14562 need special notes to explain where r11 is in relation to the stack. */
14565 rs6000_emit_epilogue (int sibcall)
14567 rs6000_stack_t *info;
14568 int restoring_FPRs_inline;
14569 int using_load_multiple;
14570 int using_mfcr_multiple;
14571 int use_backchain_to_restore_sp;
14573 rtx sp_reg_rtx = gen_rtx_REG (Pmode, 1);
14574 rtx frame_reg_rtx = sp_reg_rtx;
14575 enum machine_mode reg_mode = Pmode;
14576 int reg_size = TARGET_32BIT ? 4 : 8;
14579 info = rs6000_stack_info ();
14581 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14583 reg_mode = V2SImode;
14587 using_load_multiple = (TARGET_MULTIPLE && ! TARGET_POWERPC64
14588 && (!TARGET_SPE_ABI
14589 || info->spe_64bit_regs_used == 0)
14590 && info->first_gp_reg_save < 31
14591 && no_global_regs_above (info->first_gp_reg_save));
14592 restoring_FPRs_inline = (sibcall
14593 || current_function_calls_eh_return
14594 || info->first_fp_reg_save == 64
14595 || FP_SAVE_INLINE (info->first_fp_reg_save));
14596 use_backchain_to_restore_sp = (frame_pointer_needed
14597 || current_function_calls_alloca
14598 || info->total_size > 32767);
14599 using_mfcr_multiple = (rs6000_cpu == PROCESSOR_PPC601
14600 || rs6000_cpu == PROCESSOR_PPC603
14601 || rs6000_cpu == PROCESSOR_PPC750
14604 if (WORLD_SAVE_P (info))
14608 const char *alloc_rname;
14611 /* eh_rest_world_r10 will return to the location saved in the LR
14612 stack slot (which is not likely to be our caller.)
14613 Input: R10 -- stack adjustment. Clobbers R0, R11, R12, R7, R8.
14614 rest_world is similar, except any R10 parameter is ignored.
14615 The exception-handling stuff that was here in 2.95 is no
14616 longer necessary. */
14620 + 32 - info->first_gp_reg_save
14621 + LAST_ALTIVEC_REGNO + 1 - info->first_altivec_reg_save
14622 + 63 + 1 - info->first_fp_reg_save);
14624 strcpy (rname, ((current_function_calls_eh_return) ?
14625 "*eh_rest_world_r10" : "*rest_world"));
14626 alloc_rname = ggc_strdup (rname);
14629 RTVEC_ELT (p, j++) = gen_rtx_RETURN (VOIDmode);
14630 RTVEC_ELT (p, j++) = gen_rtx_USE (VOIDmode,
14631 gen_rtx_REG (Pmode,
14632 LINK_REGISTER_REGNUM));
14634 = gen_rtx_USE (VOIDmode, gen_rtx_SYMBOL_REF (Pmode, alloc_rname));
14635 /* The instruction pattern requires a clobber here;
14636 it is shared with the restVEC helper. */
14638 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 11));
14641 /* CR register traditionally saved as CR2. */
14642 rtx reg = gen_rtx_REG (reg_mode, CR2_REGNO);
14643 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14644 GEN_INT (info->cr_save_offset));
14645 rtx mem = gen_rtx_MEM (reg_mode, addr);
14646 set_mem_alias_set (mem, rs6000_sr_alias_set);
14648 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14651 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14653 rtx reg = gen_rtx_REG (reg_mode, info->first_gp_reg_save + i);
14654 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14655 GEN_INT (info->gp_save_offset
14657 rtx mem = gen_rtx_MEM (reg_mode, addr);
14658 set_mem_alias_set (mem, rs6000_sr_alias_set);
14660 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14662 for (i = 0; info->first_altivec_reg_save + i <= LAST_ALTIVEC_REGNO; i++)
14664 rtx reg = gen_rtx_REG (V4SImode, info->first_altivec_reg_save + i);
14665 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14666 GEN_INT (info->altivec_save_offset
14668 rtx mem = gen_rtx_MEM (V4SImode, addr);
14669 set_mem_alias_set (mem, rs6000_sr_alias_set);
14671 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14673 for (i = 0; info->first_fp_reg_save + i <= 63; i++)
14675 rtx reg = gen_rtx_REG (DFmode, info->first_fp_reg_save + i);
14676 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14677 GEN_INT (info->fp_save_offset
14679 rtx mem = gen_rtx_MEM (DFmode, addr);
14680 set_mem_alias_set (mem, rs6000_sr_alias_set);
14682 RTVEC_ELT (p, j++) = gen_rtx_SET (VOIDmode, reg, mem);
14685 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (Pmode, 0));
14687 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 12));
14689 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 7));
14691 = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 8));
14693 = gen_rtx_USE (VOIDmode, gen_rtx_REG (SImode, 10));
14694 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
14699 /* If we have a frame pointer, a call to alloca, or a large stack
14700 frame, restore the old stack pointer using the backchain. Otherwise,
14701 we know what size to update it with. */
14702 if (use_backchain_to_restore_sp)
14704 /* Under V.4, don't reset the stack pointer until after we're done
14705 loading the saved registers. */
14706 if (DEFAULT_ABI == ABI_V4)
14707 frame_reg_rtx = gen_rtx_REG (Pmode, 11);
14709 emit_move_insn (frame_reg_rtx,
14710 gen_rtx_MEM (Pmode, sp_reg_rtx));
14713 else if (info->push_p)
14715 if (DEFAULT_ABI == ABI_V4
14716 || current_function_calls_eh_return)
14717 sp_offset = info->total_size;
14720 emit_insn (TARGET_32BIT
14721 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14722 GEN_INT (info->total_size))
14723 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14724 GEN_INT (info->total_size)));
14728 /* Restore AltiVec registers if needed. */
14729 if (TARGET_ALTIVEC_ABI && info->altivec_size != 0)
14733 for (i = info->first_altivec_reg_save; i <= LAST_ALTIVEC_REGNO; ++i)
14734 if (info->vrsave_mask & ALTIVEC_REG_BIT (i))
14736 rtx addr, areg, mem;
14738 areg = gen_rtx_REG (Pmode, 0);
14740 (areg, GEN_INT (info->altivec_save_offset
14742 + 16 * (i - info->first_altivec_reg_save)));
14744 /* AltiVec addressing mode is [reg+reg]. */
14745 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, areg);
14746 mem = gen_rtx_MEM (V4SImode, addr);
14747 set_mem_alias_set (mem, rs6000_sr_alias_set);
14749 emit_move_insn (gen_rtx_REG (V4SImode, i), mem);
14753 /* Restore VRSAVE if needed. */
14754 if (TARGET_ALTIVEC && TARGET_ALTIVEC_VRSAVE
14755 && info->vrsave_mask != 0)
14757 rtx addr, mem, reg;
14759 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14760 GEN_INT (info->vrsave_save_offset + sp_offset));
14761 mem = gen_rtx_MEM (SImode, addr);
14762 set_mem_alias_set (mem, rs6000_sr_alias_set);
14763 reg = gen_rtx_REG (SImode, 12);
14764 emit_move_insn (reg, mem);
14766 emit_insn (generate_set_vrsave (reg, info, 1));
14769 /* Get the old lr if we saved it. */
14770 if (info->lr_save_p)
14772 rtx mem = gen_frame_mem_offset (Pmode, frame_reg_rtx,
14773 info->lr_save_offset + sp_offset);
14775 set_mem_alias_set (mem, rs6000_sr_alias_set);
14777 emit_move_insn (gen_rtx_REG (Pmode, 0), mem);
14780 /* Get the old cr if we saved it. */
14781 if (info->cr_save_p)
14783 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14784 GEN_INT (info->cr_save_offset + sp_offset));
14785 rtx mem = gen_rtx_MEM (SImode, addr);
14787 set_mem_alias_set (mem, rs6000_sr_alias_set);
14789 emit_move_insn (gen_rtx_REG (SImode, 12), mem);
14792 /* Set LR here to try to overlap restores below. */
14793 if (info->lr_save_p)
14794 emit_move_insn (gen_rtx_REG (Pmode, LINK_REGISTER_REGNUM),
14795 gen_rtx_REG (Pmode, 0));
14797 /* Load exception handler data registers, if needed. */
14798 if (current_function_calls_eh_return)
14800 unsigned int i, regno;
14804 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14805 GEN_INT (sp_offset + 5 * reg_size));
14806 rtx mem = gen_rtx_MEM (reg_mode, addr);
14808 set_mem_alias_set (mem, rs6000_sr_alias_set);
14810 emit_move_insn (gen_rtx_REG (reg_mode, 2), mem);
14817 regno = EH_RETURN_DATA_REGNO (i);
14818 if (regno == INVALID_REGNUM)
14821 mem = gen_frame_mem_offset (reg_mode, frame_reg_rtx,
14822 info->ehrd_offset + sp_offset
14823 + reg_size * (int) i);
14824 set_mem_alias_set (mem, rs6000_sr_alias_set);
14826 emit_move_insn (gen_rtx_REG (reg_mode, regno), mem);
14830 /* Restore GPRs. This is done as a PARALLEL if we are using
14831 the load-multiple instructions. */
14832 if (using_load_multiple)
14835 p = rtvec_alloc (32 - info->first_gp_reg_save);
14836 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14838 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14839 GEN_INT (info->gp_save_offset
14842 rtx mem = gen_rtx_MEM (reg_mode, addr);
14844 set_mem_alias_set (mem, rs6000_sr_alias_set);
14847 gen_rtx_SET (VOIDmode,
14848 gen_rtx_REG (reg_mode, info->first_gp_reg_save + i),
14851 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14854 for (i = 0; i < 32 - info->first_gp_reg_save; i++)
14855 if ((regs_ever_live[info->first_gp_reg_save + i]
14856 && (!call_used_regs[info->first_gp_reg_save + i]
14857 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14858 && TARGET_TOC && TARGET_MINIMAL_TOC)))
14859 || (i + info->first_gp_reg_save == RS6000_PIC_OFFSET_TABLE_REGNUM
14860 && ((DEFAULT_ABI == ABI_V4 && flag_pic != 0)
14861 || (DEFAULT_ABI == ABI_DARWIN && flag_pic))))
14863 rtx addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14864 GEN_INT (info->gp_save_offset
14867 rtx mem = gen_rtx_MEM (reg_mode, addr);
14869 /* Restore 64-bit quantities for SPE. */
14870 if (TARGET_SPE_ABI && info->spe_64bit_regs_used != 0)
14872 int offset = info->spe_gp_save_offset + sp_offset + 8 * i;
14875 if (!SPE_CONST_OFFSET_OK (offset))
14877 b = gen_rtx_REG (Pmode, FIXED_SCRATCH);
14878 emit_move_insn (b, GEN_INT (offset));
14881 b = GEN_INT (offset);
14883 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx, b);
14884 mem = gen_rtx_MEM (V2SImode, addr);
14887 set_mem_alias_set (mem, rs6000_sr_alias_set);
14889 emit_move_insn (gen_rtx_REG (reg_mode,
14890 info->first_gp_reg_save + i), mem);
14893 /* Restore fpr's if we need to do it without calling a function. */
14894 if (restoring_FPRs_inline)
14895 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
14896 if ((regs_ever_live[info->first_fp_reg_save+i]
14897 && ! call_used_regs[info->first_fp_reg_save+i]))
14900 addr = gen_rtx_PLUS (Pmode, frame_reg_rtx,
14901 GEN_INT (info->fp_save_offset
14904 mem = gen_rtx_MEM (DFmode, addr);
14905 set_mem_alias_set (mem, rs6000_sr_alias_set);
14907 emit_move_insn (gen_rtx_REG (DFmode,
14908 info->first_fp_reg_save + i),
14912 /* If we saved cr, restore it here. Just those that were used. */
14913 if (info->cr_save_p)
14915 rtx r12_rtx = gen_rtx_REG (SImode, 12);
14918 if (using_mfcr_multiple)
14920 for (i = 0; i < 8; i++)
14921 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14923 gcc_assert (count);
14926 if (using_mfcr_multiple && count > 1)
14931 p = rtvec_alloc (count);
14934 for (i = 0; i < 8; i++)
14935 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14937 rtvec r = rtvec_alloc (2);
14938 RTVEC_ELT (r, 0) = r12_rtx;
14939 RTVEC_ELT (r, 1) = GEN_INT (1 << (7-i));
14940 RTVEC_ELT (p, ndx) =
14941 gen_rtx_SET (VOIDmode, gen_rtx_REG (CCmode, CR0_REGNO+i),
14942 gen_rtx_UNSPEC (CCmode, r, UNSPEC_MOVESI_TO_CR));
14945 emit_insn (gen_rtx_PARALLEL (VOIDmode, p));
14946 gcc_assert (ndx == count);
14949 for (i = 0; i < 8; i++)
14950 if (regs_ever_live[CR0_REGNO+i] && ! call_used_regs[CR0_REGNO+i])
14952 emit_insn (gen_movsi_to_cr_one (gen_rtx_REG (CCmode,
14958 /* If this is V.4, unwind the stack pointer after all of the loads
14959 have been done. We need to emit a block here so that sched
14960 doesn't decide to move the sp change before the register restores
14961 (which may not have any obvious dependency on the stack). This
14962 doesn't hurt performance, because there is no scheduling that can
14963 be done after this point. */
14964 if (DEFAULT_ABI == ABI_V4
14965 || current_function_calls_eh_return)
14967 if (frame_reg_rtx != sp_reg_rtx)
14968 rs6000_emit_stack_tie ();
14970 if (use_backchain_to_restore_sp)
14972 emit_move_insn (sp_reg_rtx, frame_reg_rtx);
14974 else if (sp_offset != 0)
14976 emit_insn (TARGET_32BIT
14977 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx,
14978 GEN_INT (sp_offset))
14979 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx,
14980 GEN_INT (sp_offset)));
14984 if (current_function_calls_eh_return)
14986 rtx sa = EH_RETURN_STACKADJ_RTX;
14987 emit_insn (TARGET_32BIT
14988 ? gen_addsi3 (sp_reg_rtx, sp_reg_rtx, sa)
14989 : gen_adddi3 (sp_reg_rtx, sp_reg_rtx, sa));
14995 if (! restoring_FPRs_inline)
14996 p = rtvec_alloc (3 + 64 - info->first_fp_reg_save);
14998 p = rtvec_alloc (2);
15000 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
15001 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
15002 gen_rtx_REG (Pmode,
15003 LINK_REGISTER_REGNUM));
15005 /* If we have to restore more than two FP registers, branch to the
15006 restore function. It will return to our caller. */
15007 if (! restoring_FPRs_inline)
15011 const char *alloc_rname;
15013 sprintf (rname, "%s%d%s", RESTORE_FP_PREFIX,
15014 info->first_fp_reg_save - 32, RESTORE_FP_SUFFIX);
15015 alloc_rname = ggc_strdup (rname);
15016 RTVEC_ELT (p, 2) = gen_rtx_USE (VOIDmode,
15017 gen_rtx_SYMBOL_REF (Pmode,
15020 for (i = 0; i < 64 - info->first_fp_reg_save; i++)
15023 addr = gen_rtx_PLUS (Pmode, sp_reg_rtx,
15024 GEN_INT (info->fp_save_offset + 8*i));
15025 mem = gen_rtx_MEM (DFmode, addr);
15026 set_mem_alias_set (mem, rs6000_sr_alias_set);
15028 RTVEC_ELT (p, i+3) =
15029 gen_rtx_SET (VOIDmode,
15030 gen_rtx_REG (DFmode, info->first_fp_reg_save + i),
15035 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
15039 /* Write function epilogue. */
15042 rs6000_output_function_epilogue (FILE *file,
15043 HOST_WIDE_INT size ATTRIBUTE_UNUSED)
15045 rs6000_stack_t *info = rs6000_stack_info ();
15047 if (! HAVE_epilogue)
15049 rtx insn = get_last_insn ();
15050 /* If the last insn was a BARRIER, we don't have to write anything except
15051 the trace table. */
15052 if (GET_CODE (insn) == NOTE)
15053 insn = prev_nonnote_insn (insn);
15054 if (insn == 0 || GET_CODE (insn) != BARRIER)
15056 /* This is slightly ugly, but at least we don't have two
15057 copies of the epilogue-emitting code. */
15060 /* A NOTE_INSN_DELETED is supposed to be at the start
15061 and end of the "toplevel" insn chain. */
15062 emit_note (NOTE_INSN_DELETED);
15063 rs6000_emit_epilogue (FALSE);
15064 emit_note (NOTE_INSN_DELETED);
15066 /* Expand INSN_ADDRESSES so final() doesn't crash. */
15070 for (insn = get_insns (); insn != 0; insn = NEXT_INSN (insn))
15072 INSN_ADDRESSES_NEW (insn, addr);
15077 if (TARGET_DEBUG_STACK)
15078 debug_rtx_list (get_insns (), 100);
15079 final (get_insns (), file, FALSE);
15085 macho_branch_islands ();
15086 /* Mach-O doesn't support labels at the end of objects, so if
15087 it looks like we might want one, insert a NOP. */
15089 rtx insn = get_last_insn ();
15092 && NOTE_LINE_NUMBER (insn) != NOTE_INSN_DELETED_LABEL)
15093 insn = PREV_INSN (insn);
15097 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_DELETED_LABEL)))
15098 fputs ("\tnop\n", file);
15102 /* Output a traceback table here. See /usr/include/sys/debug.h for info
15105 We don't output a traceback table if -finhibit-size-directive was
15106 used. The documentation for -finhibit-size-directive reads
15107 ``don't output a @code{.size} assembler directive, or anything
15108 else that would cause trouble if the function is split in the
15109 middle, and the two halves are placed at locations far apart in
15110 memory.'' The traceback table has this property, since it
15111 includes the offset from the start of the function to the
15112 traceback table itself.
15114 System V.4 Powerpc's (and the embedded ABI derived from it) use a
15115 different traceback table. */
15116 if (DEFAULT_ABI == ABI_AIX && ! flag_inhibit_size_directive
15117 && rs6000_traceback != traceback_none)
15119 const char *fname = NULL;
15120 const char *language_string = lang_hooks.name;
15121 int fixed_parms = 0, float_parms = 0, parm_info = 0;
15123 int optional_tbtab;
15125 if (rs6000_traceback == traceback_full)
15126 optional_tbtab = 1;
15127 else if (rs6000_traceback == traceback_part)
15128 optional_tbtab = 0;
15130 optional_tbtab = !optimize_size && !TARGET_ELF;
15132 if (optional_tbtab)
15134 fname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
15135 while (*fname == '.') /* V.4 encodes . in the name */
15138 /* Need label immediately before tbtab, so we can compute
15139 its offset from the function start. */
15140 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15141 ASM_OUTPUT_LABEL (file, fname);
15144 /* The .tbtab pseudo-op can only be used for the first eight
15145 expressions, since it can't handle the possibly variable
15146 length fields that follow. However, if you omit the optional
15147 fields, the assembler outputs zeros for all optional fields
15148 anyways, giving each variable length field is minimum length
15149 (as defined in sys/debug.h). Thus we can not use the .tbtab
15150 pseudo-op at all. */
15152 /* An all-zero word flags the start of the tbtab, for debuggers
15153 that have to find it by searching forward from the entry
15154 point or from the current pc. */
15155 fputs ("\t.long 0\n", file);
15157 /* Tbtab format type. Use format type 0. */
15158 fputs ("\t.byte 0,", file);
15160 /* Language type. Unfortunately, there does not seem to be any
15161 official way to discover the language being compiled, so we
15162 use language_string.
15163 C is 0. Fortran is 1. Pascal is 2. Ada is 3. C++ is 9.
15164 Java is 13. Objective-C is 14. */
15165 if (! strcmp (language_string, "GNU C"))
15167 else if (! strcmp (language_string, "GNU F77")
15168 || ! strcmp (language_string, "GNU F95"))
15170 else if (! strcmp (language_string, "GNU Pascal"))
15172 else if (! strcmp (language_string, "GNU Ada"))
15174 else if (! strcmp (language_string, "GNU C++"))
15176 else if (! strcmp (language_string, "GNU Java"))
15178 else if (! strcmp (language_string, "GNU Objective-C"))
15181 gcc_unreachable ();
15182 fprintf (file, "%d,", i);
15184 /* 8 single bit fields: global linkage (not set for C extern linkage,
15185 apparently a PL/I convention?), out-of-line epilogue/prologue, offset
15186 from start of procedure stored in tbtab, internal function, function
15187 has controlled storage, function has no toc, function uses fp,
15188 function logs/aborts fp operations. */
15189 /* Assume that fp operations are used if any fp reg must be saved. */
15190 fprintf (file, "%d,",
15191 (optional_tbtab << 5) | ((info->first_fp_reg_save != 64) << 1));
15193 /* 6 bitfields: function is interrupt handler, name present in
15194 proc table, function calls alloca, on condition directives
15195 (controls stack walks, 3 bits), saves condition reg, saves
15197 /* The `function calls alloca' bit seems to be set whenever reg 31 is
15198 set up as a frame pointer, even when there is no alloca call. */
15199 fprintf (file, "%d,",
15200 ((optional_tbtab << 6)
15201 | ((optional_tbtab & frame_pointer_needed) << 5)
15202 | (info->cr_save_p << 1)
15203 | (info->lr_save_p)));
15205 /* 3 bitfields: saves backchain, fixup code, number of fpr saved
15207 fprintf (file, "%d,",
15208 (info->push_p << 7) | (64 - info->first_fp_reg_save));
15210 /* 2 bitfields: spare bits (2 bits), number of gpr saved (6 bits). */
15211 fprintf (file, "%d,", (32 - first_reg_to_save ()));
15213 if (optional_tbtab)
15215 /* Compute the parameter info from the function decl argument
15218 int next_parm_info_bit = 31;
15220 for (decl = DECL_ARGUMENTS (current_function_decl);
15221 decl; decl = TREE_CHAIN (decl))
15223 rtx parameter = DECL_INCOMING_RTL (decl);
15224 enum machine_mode mode = GET_MODE (parameter);
15226 if (GET_CODE (parameter) == REG)
15228 if (GET_MODE_CLASS (mode) == MODE_FLOAT)
15246 gcc_unreachable ();
15249 /* If only one bit will fit, don't or in this entry. */
15250 if (next_parm_info_bit > 0)
15251 parm_info |= (bits << (next_parm_info_bit - 1));
15252 next_parm_info_bit -= 2;
15256 fixed_parms += ((GET_MODE_SIZE (mode)
15257 + (UNITS_PER_WORD - 1))
15259 next_parm_info_bit -= 1;
15265 /* Number of fixed point parameters. */
15266 /* This is actually the number of words of fixed point parameters; thus
15267 an 8 byte struct counts as 2; and thus the maximum value is 8. */
15268 fprintf (file, "%d,", fixed_parms);
15270 /* 2 bitfields: number of floating point parameters (7 bits), parameters
15272 /* This is actually the number of fp registers that hold parameters;
15273 and thus the maximum value is 13. */
15274 /* Set parameters on stack bit if parameters are not in their original
15275 registers, regardless of whether they are on the stack? Xlc
15276 seems to set the bit when not optimizing. */
15277 fprintf (file, "%d\n", ((float_parms << 1) | (! optimize)));
15279 if (! optional_tbtab)
15282 /* Optional fields follow. Some are variable length. */
15284 /* Parameter types, left adjusted bit fields: 0 fixed, 10 single float,
15285 11 double float. */
15286 /* There is an entry for each parameter in a register, in the order that
15287 they occur in the parameter list. Any intervening arguments on the
15288 stack are ignored. If the list overflows a long (max possible length
15289 34 bits) then completely leave off all elements that don't fit. */
15290 /* Only emit this long if there was at least one parameter. */
15291 if (fixed_parms || float_parms)
15292 fprintf (file, "\t.long %d\n", parm_info);
15294 /* Offset from start of code to tb table. */
15295 fputs ("\t.long ", file);
15296 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LT");
15298 RS6000_OUTPUT_BASENAME (file, fname);
15300 assemble_name (file, fname);
15302 rs6000_output_function_entry (file, fname);
15305 /* Interrupt handler mask. */
15306 /* Omit this long, since we never set the interrupt handler bit
15309 /* Number of CTL (controlled storage) anchors. */
15310 /* Omit this long, since the has_ctl bit is never set above. */
15312 /* Displacement into stack of each CTL anchor. */
15313 /* Omit this list of longs, because there are no CTL anchors. */
15315 /* Length of function name. */
15318 fprintf (file, "\t.short %d\n", (int) strlen (fname));
15320 /* Function name. */
15321 assemble_string (fname, strlen (fname));
15323 /* Register for alloca automatic storage; this is always reg 31.
15324 Only emit this if the alloca bit was set above. */
15325 if (frame_pointer_needed)
15326 fputs ("\t.byte 31\n", file);
15328 fputs ("\t.align 2\n", file);
15332 /* A C compound statement that outputs the assembler code for a thunk
15333 function, used to implement C++ virtual function calls with
15334 multiple inheritance. The thunk acts as a wrapper around a virtual
15335 function, adjusting the implicit object parameter before handing
15336 control off to the real function.
15338 First, emit code to add the integer DELTA to the location that
15339 contains the incoming first argument. Assume that this argument
15340 contains a pointer, and is the one used to pass the `this' pointer
15341 in C++. This is the incoming argument *before* the function
15342 prologue, e.g. `%o0' on a sparc. The addition must preserve the
15343 values of all other incoming arguments.
15345 After the addition, emit code to jump to FUNCTION, which is a
15346 `FUNCTION_DECL'. This is a direct pure jump, not a call, and does
15347 not touch the return address. Hence returning from FUNCTION will
15348 return to whoever called the current `thunk'.
15350 The effect must be as if FUNCTION had been called directly with the
15351 adjusted first argument. This macro is responsible for emitting
15352 all of the code for a thunk function; output_function_prologue()
15353 and output_function_epilogue() are not invoked.
15355 The THUNK_FNDECL is redundant. (DELTA and FUNCTION have already
15356 been extracted from it.) It might possibly be useful on some
15357 targets, but probably not.
15359 If you do not define this macro, the target-independent code in the
15360 C++ frontend will generate a less efficient heavyweight thunk that
15361 calls FUNCTION instead of jumping to it. The generic approach does
15362 not support varargs. */
15365 rs6000_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
15366 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
15369 rtx this, insn, funexp;
15371 reload_completed = 1;
15372 epilogue_completed = 1;
15373 no_new_pseudos = 1;
15374 reset_block_changes ();
15376 /* Mark the end of the (empty) prologue. */
15377 emit_note (NOTE_INSN_PROLOGUE_END);
15379 /* Find the "this" pointer. If the function returns a structure,
15380 the structure return pointer is in r3. */
15381 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
15382 this = gen_rtx_REG (Pmode, 4);
15384 this = gen_rtx_REG (Pmode, 3);
15386 /* Apply the constant offset, if required. */
15389 rtx delta_rtx = GEN_INT (delta);
15390 emit_insn (TARGET_32BIT
15391 ? gen_addsi3 (this, this, delta_rtx)
15392 : gen_adddi3 (this, this, delta_rtx));
15395 /* Apply the offset from the vtable, if required. */
15398 rtx vcall_offset_rtx = GEN_INT (vcall_offset);
15399 rtx tmp = gen_rtx_REG (Pmode, 12);
15401 emit_move_insn (tmp, gen_rtx_MEM (Pmode, this));
15402 if (((unsigned HOST_WIDE_INT) vcall_offset) + 0x8000 >= 0x10000)
15404 emit_insn (TARGET_32BIT
15405 ? gen_addsi3 (tmp, tmp, vcall_offset_rtx)
15406 : gen_adddi3 (tmp, tmp, vcall_offset_rtx));
15407 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp));
15411 rtx loc = gen_rtx_PLUS (Pmode, tmp, vcall_offset_rtx);
15413 emit_move_insn (tmp, gen_rtx_MEM (Pmode, loc));
15415 emit_insn (TARGET_32BIT
15416 ? gen_addsi3 (this, this, tmp)
15417 : gen_adddi3 (this, this, tmp));
15420 /* Generate a tail call to the target function. */
15421 if (!TREE_USED (function))
15423 assemble_external (function);
15424 TREE_USED (function) = 1;
15426 funexp = XEXP (DECL_RTL (function), 0);
15427 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
15430 if (MACHOPIC_INDIRECT)
15431 funexp = machopic_indirect_call_target (funexp);
15434 /* gen_sibcall expects reload to convert scratch pseudo to LR so we must
15435 generate sibcall RTL explicitly. */
15436 insn = emit_call_insn (
15437 gen_rtx_PARALLEL (VOIDmode,
15439 gen_rtx_CALL (VOIDmode,
15440 funexp, const0_rtx),
15441 gen_rtx_USE (VOIDmode, const0_rtx),
15442 gen_rtx_USE (VOIDmode,
15443 gen_rtx_REG (SImode,
15444 LINK_REGISTER_REGNUM)),
15445 gen_rtx_RETURN (VOIDmode))));
15446 SIBLING_CALL_P (insn) = 1;
15449 /* Run just enough of rest_of_compilation to get the insns emitted.
15450 There's not really enough bulk here to make other passes such as
15451 instruction scheduling worth while. Note that use_thunk calls
15452 assemble_start_function and assemble_end_function. */
15453 insn = get_insns ();
15454 insn_locators_initialize ();
15455 shorten_branches (insn);
15456 final_start_function (insn, file, 1);
15457 final (insn, file, 1);
15458 final_end_function ();
15460 reload_completed = 0;
15461 epilogue_completed = 0;
15462 no_new_pseudos = 0;
15465 /* A quick summary of the various types of 'constant-pool tables'
15468 Target Flags Name One table per
15469 AIX (none) AIX TOC object file
15470 AIX -mfull-toc AIX TOC object file
15471 AIX -mminimal-toc AIX minimal TOC translation unit
15472 SVR4/EABI (none) SVR4 SDATA object file
15473 SVR4/EABI -fpic SVR4 pic object file
15474 SVR4/EABI -fPIC SVR4 PIC translation unit
15475 SVR4/EABI -mrelocatable EABI TOC function
15476 SVR4/EABI -maix AIX TOC object file
15477 SVR4/EABI -maix -mminimal-toc
15478 AIX minimal TOC translation unit
15480 Name Reg. Set by entries contains:
15481 made by addrs? fp? sum?
15483 AIX TOC 2 crt0 as Y option option
15484 AIX minimal TOC 30 prolog gcc Y Y option
15485 SVR4 SDATA 13 crt0 gcc N Y N
15486 SVR4 pic 30 prolog ld Y not yet N
15487 SVR4 PIC 30 prolog gcc Y option option
15488 EABI TOC 30 prolog gcc Y option option
15492 /* Hash functions for the hash table. */
15495 rs6000_hash_constant (rtx k)
15497 enum rtx_code code = GET_CODE (k);
15498 enum machine_mode mode = GET_MODE (k);
15499 unsigned result = (code << 3) ^ mode;
15500 const char *format;
15503 format = GET_RTX_FORMAT (code);
15504 flen = strlen (format);
15510 return result * 1231 + (unsigned) INSN_UID (XEXP (k, 0));
15513 if (mode != VOIDmode)
15514 return real_hash (CONST_DOUBLE_REAL_VALUE (k)) * result;
15526 for (; fidx < flen; fidx++)
15527 switch (format[fidx])
15532 const char *str = XSTR (k, fidx);
15533 len = strlen (str);
15534 result = result * 613 + len;
15535 for (i = 0; i < len; i++)
15536 result = result * 613 + (unsigned) str[i];
15541 result = result * 1231 + rs6000_hash_constant (XEXP (k, fidx));
15545 result = result * 613 + (unsigned) XINT (k, fidx);
15548 if (sizeof (unsigned) >= sizeof (HOST_WIDE_INT))
15549 result = result * 613 + (unsigned) XWINT (k, fidx);
15553 for (i = 0; i < sizeof (HOST_WIDE_INT) / sizeof (unsigned); i++)
15554 result = result * 613 + (unsigned) (XWINT (k, fidx)
15561 gcc_unreachable ();
15568 toc_hash_function (const void *hash_entry)
15570 const struct toc_hash_struct *thc =
15571 (const struct toc_hash_struct *) hash_entry;
15572 return rs6000_hash_constant (thc->key) ^ thc->key_mode;
15575 /* Compare H1 and H2 for equivalence. */
15578 toc_hash_eq (const void *h1, const void *h2)
15580 rtx r1 = ((const struct toc_hash_struct *) h1)->key;
15581 rtx r2 = ((const struct toc_hash_struct *) h2)->key;
15583 if (((const struct toc_hash_struct *) h1)->key_mode
15584 != ((const struct toc_hash_struct *) h2)->key_mode)
15587 return rtx_equal_p (r1, r2);
15590 /* These are the names given by the C++ front-end to vtables, and
15591 vtable-like objects. Ideally, this logic should not be here;
15592 instead, there should be some programmatic way of inquiring as
15593 to whether or not an object is a vtable. */
15595 #define VTABLE_NAME_P(NAME) \
15596 (strncmp ("_vt.", name, strlen ("_vt.")) == 0 \
15597 || strncmp ("_ZTV", name, strlen ("_ZTV")) == 0 \
15598 || strncmp ("_ZTT", name, strlen ("_ZTT")) == 0 \
15599 || strncmp ("_ZTI", name, strlen ("_ZTI")) == 0 \
15600 || strncmp ("_ZTC", name, strlen ("_ZTC")) == 0)
15603 rs6000_output_symbol_ref (FILE *file, rtx x)
15605 /* Currently C++ toc references to vtables can be emitted before it
15606 is decided whether the vtable is public or private. If this is
15607 the case, then the linker will eventually complain that there is
15608 a reference to an unknown section. Thus, for vtables only,
15609 we emit the TOC reference to reference the symbol and not the
15611 const char *name = XSTR (x, 0);
15613 if (VTABLE_NAME_P (name))
15615 RS6000_OUTPUT_BASENAME (file, name);
15618 assemble_name (file, name);
15621 /* Output a TOC entry. We derive the entry name from what is being
15625 output_toc (FILE *file, rtx x, int labelno, enum machine_mode mode)
15628 const char *name = buf;
15629 const char *real_name;
15633 gcc_assert (!TARGET_NO_TOC);
15635 /* When the linker won't eliminate them, don't output duplicate
15636 TOC entries (this happens on AIX if there is any kind of TOC,
15637 and on SVR4 under -fPIC or -mrelocatable). Don't do this for
15639 if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
15641 struct toc_hash_struct *h;
15644 /* Create toc_hash_table. This can't be done at OVERRIDE_OPTIONS
15645 time because GGC is not initialized at that point. */
15646 if (toc_hash_table == NULL)
15647 toc_hash_table = htab_create_ggc (1021, toc_hash_function,
15648 toc_hash_eq, NULL);
15650 h = ggc_alloc (sizeof (*h));
15652 h->key_mode = mode;
15653 h->labelno = labelno;
15655 found = htab_find_slot (toc_hash_table, h, 1);
15656 if (*found == NULL)
15658 else /* This is indeed a duplicate.
15659 Set this label equal to that label. */
15661 fputs ("\t.set ", file);
15662 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15663 fprintf (file, "%d,", labelno);
15664 ASM_OUTPUT_INTERNAL_LABEL_PREFIX (file, "LC");
15665 fprintf (file, "%d\n", ((*(const struct toc_hash_struct **)
15671 /* If we're going to put a double constant in the TOC, make sure it's
15672 aligned properly when strict alignment is on. */
15673 if (GET_CODE (x) == CONST_DOUBLE
15674 && STRICT_ALIGNMENT
15675 && GET_MODE_BITSIZE (mode) >= 64
15676 && ! (TARGET_NO_FP_IN_TOC && ! TARGET_MINIMAL_TOC)) {
15677 ASM_OUTPUT_ALIGN (file, 3);
15680 (*targetm.asm_out.internal_label) (file, "LC", labelno);
15682 /* Handle FP constants specially. Note that if we have a minimal
15683 TOC, things we put here aren't actually in the TOC, so we can allow
15685 if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == TFmode)
15687 REAL_VALUE_TYPE rv;
15690 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15691 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
15695 if (TARGET_MINIMAL_TOC)
15696 fputs (DOUBLE_INT_ASM_OP, file);
15698 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15699 k[0] & 0xffffffff, k[1] & 0xffffffff,
15700 k[2] & 0xffffffff, k[3] & 0xffffffff);
15701 fprintf (file, "0x%lx%08lx,0x%lx%08lx\n",
15702 k[0] & 0xffffffff, k[1] & 0xffffffff,
15703 k[2] & 0xffffffff, k[3] & 0xffffffff);
15708 if (TARGET_MINIMAL_TOC)
15709 fputs ("\t.long ", file);
15711 fprintf (file, "\t.tc FT_%lx_%lx_%lx_%lx[TC],",
15712 k[0] & 0xffffffff, k[1] & 0xffffffff,
15713 k[2] & 0xffffffff, k[3] & 0xffffffff);
15714 fprintf (file, "0x%lx,0x%lx,0x%lx,0x%lx\n",
15715 k[0] & 0xffffffff, k[1] & 0xffffffff,
15716 k[2] & 0xffffffff, k[3] & 0xffffffff);
15720 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
15722 REAL_VALUE_TYPE rv;
15725 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15726 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
15730 if (TARGET_MINIMAL_TOC)
15731 fputs (DOUBLE_INT_ASM_OP, file);
15733 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15734 k[0] & 0xffffffff, k[1] & 0xffffffff);
15735 fprintf (file, "0x%lx%08lx\n",
15736 k[0] & 0xffffffff, k[1] & 0xffffffff);
15741 if (TARGET_MINIMAL_TOC)
15742 fputs ("\t.long ", file);
15744 fprintf (file, "\t.tc FD_%lx_%lx[TC],",
15745 k[0] & 0xffffffff, k[1] & 0xffffffff);
15746 fprintf (file, "0x%lx,0x%lx\n",
15747 k[0] & 0xffffffff, k[1] & 0xffffffff);
15751 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
15753 REAL_VALUE_TYPE rv;
15756 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
15757 REAL_VALUE_TO_TARGET_SINGLE (rv, l);
15761 if (TARGET_MINIMAL_TOC)
15762 fputs (DOUBLE_INT_ASM_OP, file);
15764 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15765 fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
15770 if (TARGET_MINIMAL_TOC)
15771 fputs ("\t.long ", file);
15773 fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
15774 fprintf (file, "0x%lx\n", l & 0xffffffff);
15778 else if (GET_MODE (x) == VOIDmode
15779 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
15781 unsigned HOST_WIDE_INT low;
15782 HOST_WIDE_INT high;
15784 if (GET_CODE (x) == CONST_DOUBLE)
15786 low = CONST_DOUBLE_LOW (x);
15787 high = CONST_DOUBLE_HIGH (x);
15790 #if HOST_BITS_PER_WIDE_INT == 32
15793 high = (low & 0x80000000) ? ~0 : 0;
15797 low = INTVAL (x) & 0xffffffff;
15798 high = (HOST_WIDE_INT) INTVAL (x) >> 32;
15802 /* TOC entries are always Pmode-sized, but since this
15803 is a bigendian machine then if we're putting smaller
15804 integer constants in the TOC we have to pad them.
15805 (This is still a win over putting the constants in
15806 a separate constant pool, because then we'd have
15807 to have both a TOC entry _and_ the actual constant.)
15809 For a 32-bit target, CONST_INT values are loaded and shifted
15810 entirely within `low' and can be stored in one TOC entry. */
15812 /* It would be easy to make this work, but it doesn't now. */
15813 gcc_assert (!TARGET_64BIT || POINTER_SIZE >= GET_MODE_BITSIZE (mode));
15815 if (POINTER_SIZE > GET_MODE_BITSIZE (mode))
15817 #if HOST_BITS_PER_WIDE_INT == 32
15818 lshift_double (low, high, POINTER_SIZE - GET_MODE_BITSIZE (mode),
15819 POINTER_SIZE, &low, &high, 0);
15822 low <<= POINTER_SIZE - GET_MODE_BITSIZE (mode);
15823 high = (HOST_WIDE_INT) low >> 32;
15830 if (TARGET_MINIMAL_TOC)
15831 fputs (DOUBLE_INT_ASM_OP, file);
15833 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15834 (long) high & 0xffffffff, (long) low & 0xffffffff);
15835 fprintf (file, "0x%lx%08lx\n",
15836 (long) high & 0xffffffff, (long) low & 0xffffffff);
15841 if (POINTER_SIZE < GET_MODE_BITSIZE (mode))
15843 if (TARGET_MINIMAL_TOC)
15844 fputs ("\t.long ", file);
15846 fprintf (file, "\t.tc ID_%lx_%lx[TC],",
15847 (long) high & 0xffffffff, (long) low & 0xffffffff);
15848 fprintf (file, "0x%lx,0x%lx\n",
15849 (long) high & 0xffffffff, (long) low & 0xffffffff);
15853 if (TARGET_MINIMAL_TOC)
15854 fputs ("\t.long ", file);
15856 fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
15857 fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
15863 if (GET_CODE (x) == CONST)
15865 gcc_assert (GET_CODE (XEXP (x, 0)) == PLUS);
15867 base = XEXP (XEXP (x, 0), 0);
15868 offset = INTVAL (XEXP (XEXP (x, 0), 1));
15871 switch (GET_CODE (base))
15874 name = XSTR (base, 0);
15878 ASM_GENERATE_INTERNAL_LABEL (buf, "L",
15879 CODE_LABEL_NUMBER (XEXP (base, 0)));
15883 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (base));
15887 gcc_unreachable ();
15890 real_name = (*targetm.strip_name_encoding) (name);
15891 if (TARGET_MINIMAL_TOC)
15892 fputs (TARGET_32BIT ? "\t.long " : DOUBLE_INT_ASM_OP, file);
15895 fprintf (file, "\t.tc %s", real_name);
15898 fprintf (file, ".N%d", - offset);
15900 fprintf (file, ".P%d", offset);
15902 fputs ("[TC],", file);
15905 /* Currently C++ toc references to vtables can be emitted before it
15906 is decided whether the vtable is public or private. If this is
15907 the case, then the linker will eventually complain that there is
15908 a TOC reference to an unknown section. Thus, for vtables only,
15909 we emit the TOC reference to reference the symbol and not the
15911 if (VTABLE_NAME_P (name))
15913 RS6000_OUTPUT_BASENAME (file, name);
15915 fprintf (file, "%d", offset);
15916 else if (offset > 0)
15917 fprintf (file, "+%d", offset);
15920 output_addr_const (file, x);
15924 /* Output an assembler pseudo-op to write an ASCII string of N characters
15925 starting at P to FILE.
15927 On the RS/6000, we have to do this using the .byte operation and
15928 write out special characters outside the quoted string.
15929 Also, the assembler is broken; very long strings are truncated,
15930 so we must artificially break them up early. */
15933 output_ascii (FILE *file, const char *p, int n)
15936 int i, count_string;
15937 const char *for_string = "\t.byte \"";
15938 const char *for_decimal = "\t.byte ";
15939 const char *to_close = NULL;
15942 for (i = 0; i < n; i++)
15945 if (c >= ' ' && c < 0177)
15948 fputs (for_string, file);
15951 /* Write two quotes to get one. */
15959 for_decimal = "\"\n\t.byte ";
15963 if (count_string >= 512)
15965 fputs (to_close, file);
15967 for_string = "\t.byte \"";
15968 for_decimal = "\t.byte ";
15976 fputs (for_decimal, file);
15977 fprintf (file, "%d", c);
15979 for_string = "\n\t.byte \"";
15980 for_decimal = ", ";
15986 /* Now close the string if we have written one. Then end the line. */
15988 fputs (to_close, file);
15991 /* Generate a unique section name for FILENAME for a section type
15992 represented by SECTION_DESC. Output goes into BUF.
15994 SECTION_DESC can be any string, as long as it is different for each
15995 possible section type.
15997 We name the section in the same manner as xlc. The name begins with an
15998 underscore followed by the filename (after stripping any leading directory
15999 names) with the last period replaced by the string SECTION_DESC. If
16000 FILENAME does not contain a period, SECTION_DESC is appended to the end of
16004 rs6000_gen_section_name (char **buf, const char *filename,
16005 const char *section_desc)
16007 const char *q, *after_last_slash, *last_period = 0;
16011 after_last_slash = filename;
16012 for (q = filename; *q; q++)
16015 after_last_slash = q + 1;
16016 else if (*q == '.')
16020 len = strlen (after_last_slash) + strlen (section_desc) + 2;
16021 *buf = (char *) xmalloc (len);
16026 for (q = after_last_slash; *q; q++)
16028 if (q == last_period)
16030 strcpy (p, section_desc);
16031 p += strlen (section_desc);
16035 else if (ISALNUM (*q))
16039 if (last_period == 0)
16040 strcpy (p, section_desc);
16045 /* Emit profile function. */
16048 output_profile_hook (int labelno ATTRIBUTE_UNUSED)
16050 /* Non-standard profiling for kernels, which just saves LR then calls
16051 _mcount without worrying about arg saves. The idea is to change
16052 the function prologue as little as possible as it isn't easy to
16053 account for arg save/restore code added just for _mcount. */
16054 if (TARGET_PROFILE_KERNEL)
16057 if (DEFAULT_ABI == ABI_AIX)
16059 #ifndef NO_PROFILE_COUNTERS
16060 # define NO_PROFILE_COUNTERS 0
16062 if (NO_PROFILE_COUNTERS)
16063 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 0);
16067 const char *label_name;
16070 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16071 label_name = (*targetm.strip_name_encoding) (ggc_strdup (buf));
16072 fun = gen_rtx_SYMBOL_REF (Pmode, label_name);
16074 emit_library_call (init_one_libfunc (RS6000_MCOUNT), 0, VOIDmode, 1,
16078 else if (DEFAULT_ABI == ABI_DARWIN)
16080 const char *mcount_name = RS6000_MCOUNT;
16081 int caller_addr_regno = LINK_REGISTER_REGNUM;
16083 /* Be conservative and always set this, at least for now. */
16084 current_function_uses_pic_offset_table = 1;
16087 /* For PIC code, set up a stub and collect the caller's address
16088 from r0, which is where the prologue puts it. */
16089 if (MACHOPIC_INDIRECT
16090 && current_function_uses_pic_offset_table)
16091 caller_addr_regno = 0;
16093 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mcount_name),
16095 gen_rtx_REG (Pmode, caller_addr_regno), Pmode);
16099 /* Write function profiler code. */
16102 output_function_profiler (FILE *file, int labelno)
16106 switch (DEFAULT_ABI)
16109 gcc_unreachable ();
16114 warning (0, "no profiling of 64-bit code for this ABI");
16117 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno);
16118 fprintf (file, "\tmflr %s\n", reg_names[0]);
16119 if (NO_PROFILE_COUNTERS)
16121 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16122 reg_names[0], reg_names[1]);
16124 else if (TARGET_SECURE_PLT && flag_pic)
16126 asm_fprintf (file, "\tbcl 20,31,1f\n1:\n\t{st|stw} %s,4(%s)\n",
16127 reg_names[0], reg_names[1]);
16128 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16129 asm_fprintf (file, "\t{cau|addis} %s,%s,",
16130 reg_names[12], reg_names[12]);
16131 assemble_name (file, buf);
16132 asm_fprintf (file, "-1b@ha\n\t{cal|la} %s,", reg_names[0]);
16133 assemble_name (file, buf);
16134 asm_fprintf (file, "-1b@l(%s)\n", reg_names[12]);
16136 else if (flag_pic == 1)
16138 fputs ("\tbl _GLOBAL_OFFSET_TABLE_@local-4\n", file);
16139 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16140 reg_names[0], reg_names[1]);
16141 asm_fprintf (file, "\tmflr %s\n", reg_names[12]);
16142 asm_fprintf (file, "\t{l|lwz} %s,", reg_names[0]);
16143 assemble_name (file, buf);
16144 asm_fprintf (file, "@got(%s)\n", reg_names[12]);
16146 else if (flag_pic > 1)
16148 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16149 reg_names[0], reg_names[1]);
16150 /* Now, we need to get the address of the label. */
16151 fputs ("\tbcl 20,31,1f\n\t.long ", file);
16152 assemble_name (file, buf);
16153 fputs ("-.\n1:", file);
16154 asm_fprintf (file, "\tmflr %s\n", reg_names[11]);
16155 asm_fprintf (file, "\t{l|lwz} %s,0(%s)\n",
16156 reg_names[0], reg_names[11]);
16157 asm_fprintf (file, "\t{cax|add} %s,%s,%s\n",
16158 reg_names[0], reg_names[0], reg_names[11]);
16162 asm_fprintf (file, "\t{liu|lis} %s,", reg_names[12]);
16163 assemble_name (file, buf);
16164 fputs ("@ha\n", file);
16165 asm_fprintf (file, "\t{st|stw} %s,4(%s)\n",
16166 reg_names[0], reg_names[1]);
16167 asm_fprintf (file, "\t{cal|la} %s,", reg_names[0]);
16168 assemble_name (file, buf);
16169 asm_fprintf (file, "@l(%s)\n", reg_names[12]);
16172 /* ABI_V4 saves the static chain reg with ASM_OUTPUT_REG_PUSH. */
16173 fprintf (file, "\tbl %s%s\n",
16174 RS6000_MCOUNT, flag_pic ? "@plt" : "");
16179 if (!TARGET_PROFILE_KERNEL)
16181 /* Don't do anything, done in output_profile_hook (). */
16185 gcc_assert (!TARGET_32BIT);
16187 asm_fprintf (file, "\tmflr %s\n", reg_names[0]);
16188 asm_fprintf (file, "\tstd %s,16(%s)\n", reg_names[0], reg_names[1]);
16190 if (cfun->static_chain_decl != NULL)
16192 asm_fprintf (file, "\tstd %s,24(%s)\n",
16193 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16194 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16195 asm_fprintf (file, "\tld %s,24(%s)\n",
16196 reg_names[STATIC_CHAIN_REGNUM], reg_names[1]);
16199 fprintf (file, "\tbl %s\n", RS6000_MCOUNT);
16206 /* Power4 load update and store update instructions are cracked into a
16207 load or store and an integer insn which are executed in the same cycle.
16208 Branches have their own dispatch slot which does not count against the
16209 GCC issue rate, but it changes the program flow so there are no other
16210 instructions to issue in this cycle. */
16213 rs6000_variable_issue (FILE *stream ATTRIBUTE_UNUSED,
16214 int verbose ATTRIBUTE_UNUSED,
16215 rtx insn, int more)
16217 if (GET_CODE (PATTERN (insn)) == USE
16218 || GET_CODE (PATTERN (insn)) == CLOBBER)
16221 if (rs6000_sched_groups)
16223 if (is_microcoded_insn (insn))
16225 else if (is_cracked_insn (insn))
16226 return more > 2 ? more - 2 : 0;
16232 /* Adjust the cost of a scheduling dependency. Return the new cost of
16233 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
16236 rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
16238 if (! recog_memoized (insn))
16241 if (REG_NOTE_KIND (link) != 0)
16244 if (REG_NOTE_KIND (link) == 0)
16246 /* Data dependency; DEP_INSN writes a register that INSN reads
16247 some cycles later. */
16249 /* Separate a load from a narrower, dependent store. */
16250 if (rs6000_sched_groups
16251 && GET_CODE (PATTERN (insn)) == SET
16252 && GET_CODE (PATTERN (dep_insn)) == SET
16253 && GET_CODE (XEXP (PATTERN (insn), 1)) == MEM
16254 && GET_CODE (XEXP (PATTERN (dep_insn), 0)) == MEM
16255 && (GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (insn), 1)))
16256 > GET_MODE_SIZE (GET_MODE (XEXP (PATTERN (dep_insn), 0)))))
16259 switch (get_attr_type (insn))
16262 /* Tell the first scheduling pass about the latency between
16263 a mtctr and bctr (and mtlr and br/blr). The first
16264 scheduling pass will not know about this latency since
16265 the mtctr instruction, which has the latency associated
16266 to it, will be generated by reload. */
16267 return TARGET_POWER ? 5 : 4;
16269 /* Leave some extra cycles between a compare and its
16270 dependent branch, to inhibit expensive mispredicts. */
16271 if ((rs6000_cpu_attr == CPU_PPC603
16272 || rs6000_cpu_attr == CPU_PPC604
16273 || rs6000_cpu_attr == CPU_PPC604E
16274 || rs6000_cpu_attr == CPU_PPC620
16275 || rs6000_cpu_attr == CPU_PPC630
16276 || rs6000_cpu_attr == CPU_PPC750
16277 || rs6000_cpu_attr == CPU_PPC7400
16278 || rs6000_cpu_attr == CPU_PPC7450
16279 || rs6000_cpu_attr == CPU_POWER4
16280 || rs6000_cpu_attr == CPU_POWER5)
16281 && recog_memoized (dep_insn)
16282 && (INSN_CODE (dep_insn) >= 0)
16283 && (get_attr_type (dep_insn) == TYPE_CMP
16284 || get_attr_type (dep_insn) == TYPE_COMPARE
16285 || get_attr_type (dep_insn) == TYPE_DELAYED_COMPARE
16286 || get_attr_type (dep_insn) == TYPE_IMUL_COMPARE
16287 || get_attr_type (dep_insn) == TYPE_LMUL_COMPARE
16288 || get_attr_type (dep_insn) == TYPE_FPCOMPARE
16289 || get_attr_type (dep_insn) == TYPE_CR_LOGICAL
16290 || get_attr_type (dep_insn) == TYPE_DELAYED_CR))
16295 /* Fall out to return default cost. */
16301 /* The function returns a true if INSN is microcoded.
16302 Return false otherwise. */
16305 is_microcoded_insn (rtx insn)
16307 if (!insn || !INSN_P (insn)
16308 || GET_CODE (PATTERN (insn)) == USE
16309 || GET_CODE (PATTERN (insn)) == CLOBBER)
16312 if (rs6000_sched_groups)
16314 enum attr_type type = get_attr_type (insn);
16315 if (type == TYPE_LOAD_EXT_U
16316 || type == TYPE_LOAD_EXT_UX
16317 || type == TYPE_LOAD_UX
16318 || type == TYPE_STORE_UX
16319 || type == TYPE_MFCR)
16326 /* The function returns a nonzero value if INSN can be scheduled only
16327 as the first insn in a dispatch group ("dispatch-slot restricted").
16328 In this case, the returned value indicates how many dispatch slots
16329 the insn occupies (at the beginning of the group).
16330 Return 0 otherwise. */
16333 is_dispatch_slot_restricted (rtx insn)
16335 enum attr_type type;
16337 if (!rs6000_sched_groups)
16341 || insn == NULL_RTX
16342 || GET_CODE (insn) == NOTE
16343 || GET_CODE (PATTERN (insn)) == USE
16344 || GET_CODE (PATTERN (insn)) == CLOBBER)
16347 type = get_attr_type (insn);
16354 case TYPE_DELAYED_CR:
16355 case TYPE_CR_LOGICAL:
16368 if (rs6000_cpu == PROCESSOR_POWER5
16369 && is_cracked_insn (insn))
16375 /* The function returns true if INSN is cracked into 2 instructions
16376 by the processor (and therefore occupies 2 issue slots). */
16379 is_cracked_insn (rtx insn)
16381 if (!insn || !INSN_P (insn)
16382 || GET_CODE (PATTERN (insn)) == USE
16383 || GET_CODE (PATTERN (insn)) == CLOBBER)
16386 if (rs6000_sched_groups)
16388 enum attr_type type = get_attr_type (insn);
16389 if (type == TYPE_LOAD_U || type == TYPE_STORE_U
16390 || type == TYPE_FPLOAD_U || type == TYPE_FPSTORE_U
16391 || type == TYPE_FPLOAD_UX || type == TYPE_FPSTORE_UX
16392 || type == TYPE_LOAD_EXT || type == TYPE_DELAYED_CR
16393 || type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
16394 || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
16395 || type == TYPE_IDIV || type == TYPE_LDIV
16396 || type == TYPE_INSERT_WORD)
16403 /* The function returns true if INSN can be issued only from
16404 the branch slot. */
16407 is_branch_slot_insn (rtx insn)
16409 if (!insn || !INSN_P (insn)
16410 || GET_CODE (PATTERN (insn)) == USE
16411 || GET_CODE (PATTERN (insn)) == CLOBBER)
16414 if (rs6000_sched_groups)
16416 enum attr_type type = get_attr_type (insn);
16417 if (type == TYPE_BRANCH || type == TYPE_JMPREG)
16425 /* A C statement (sans semicolon) to update the integer scheduling
16426 priority INSN_PRIORITY (INSN). Increase the priority to execute the
16427 INSN earlier, reduce the priority to execute INSN later. Do not
16428 define this macro if you do not need to adjust the scheduling
16429 priorities of insns. */
16432 rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
16434 /* On machines (like the 750) which have asymmetric integer units,
16435 where one integer unit can do multiply and divides and the other
16436 can't, reduce the priority of multiply/divide so it is scheduled
16437 before other integer operations. */
16440 if (! INSN_P (insn))
16443 if (GET_CODE (PATTERN (insn)) == USE)
16446 switch (rs6000_cpu_attr) {
16448 switch (get_attr_type (insn))
16455 fprintf (stderr, "priority was %#x (%d) before adjustment\n",
16456 priority, priority);
16457 if (priority >= 0 && priority < 0x01000000)
16464 if (is_dispatch_slot_restricted (insn)
16465 && reload_completed
16466 && current_sched_info->sched_max_insns_priority
16467 && rs6000_sched_restricted_insns_priority)
16470 /* Prioritize insns that can be dispatched only in the first
16472 if (rs6000_sched_restricted_insns_priority == 1)
16473 /* Attach highest priority to insn. This means that in
16474 haifa-sched.c:ready_sort(), dispatch-slot restriction considerations
16475 precede 'priority' (critical path) considerations. */
16476 return current_sched_info->sched_max_insns_priority;
16477 else if (rs6000_sched_restricted_insns_priority == 2)
16478 /* Increase priority of insn by a minimal amount. This means that in
16479 haifa-sched.c:ready_sort(), only 'priority' (critical path)
16480 considerations precede dispatch-slot restriction considerations. */
16481 return (priority + 1);
16487 /* Return how many instructions the machine can issue per cycle. */
16490 rs6000_issue_rate (void)
16492 /* Use issue rate of 1 for first scheduling pass to decrease degradation. */
16493 if (!reload_completed)
16496 switch (rs6000_cpu_attr) {
16497 case CPU_RIOS1: /* ? */
16499 case CPU_PPC601: /* ? */
16522 /* Return how many instructions to look ahead for better insn
16526 rs6000_use_sched_lookahead (void)
16528 if (rs6000_cpu_attr == CPU_PPC8540)
16533 /* Determine is PAT refers to memory. */
16536 is_mem_ref (rtx pat)
16542 if (GET_CODE (pat) == MEM)
16545 /* Recursively process the pattern. */
16546 fmt = GET_RTX_FORMAT (GET_CODE (pat));
16548 for (i = GET_RTX_LENGTH (GET_CODE (pat)) - 1; i >= 0 && !ret; i--)
16551 ret |= is_mem_ref (XEXP (pat, i));
16552 else if (fmt[i] == 'E')
16553 for (j = XVECLEN (pat, i) - 1; j >= 0; j--)
16554 ret |= is_mem_ref (XVECEXP (pat, i, j));
16560 /* Determine if PAT is a PATTERN of a load insn. */
16563 is_load_insn1 (rtx pat)
16565 if (!pat || pat == NULL_RTX)
16568 if (GET_CODE (pat) == SET)
16569 return is_mem_ref (SET_SRC (pat));
16571 if (GET_CODE (pat) == PARALLEL)
16575 for (i = 0; i < XVECLEN (pat, 0); i++)
16576 if (is_load_insn1 (XVECEXP (pat, 0, i)))
16583 /* Determine if INSN loads from memory. */
16586 is_load_insn (rtx insn)
16588 if (!insn || !INSN_P (insn))
16591 if (GET_CODE (insn) == CALL_INSN)
16594 return is_load_insn1 (PATTERN (insn));
16597 /* Determine if PAT is a PATTERN of a store insn. */
16600 is_store_insn1 (rtx pat)
16602 if (!pat || pat == NULL_RTX)
16605 if (GET_CODE (pat) == SET)
16606 return is_mem_ref (SET_DEST (pat));
16608 if (GET_CODE (pat) == PARALLEL)
16612 for (i = 0; i < XVECLEN (pat, 0); i++)
16613 if (is_store_insn1 (XVECEXP (pat, 0, i)))
16620 /* Determine if INSN stores to memory. */
16623 is_store_insn (rtx insn)
16625 if (!insn || !INSN_P (insn))
16628 return is_store_insn1 (PATTERN (insn));
16631 /* Returns whether the dependence between INSN and NEXT is considered
16632 costly by the given target. */
16635 rs6000_is_costly_dependence (rtx insn, rtx next, rtx link, int cost,
16638 /* If the flag is not enabled - no dependence is considered costly;
16639 allow all dependent insns in the same group.
16640 This is the most aggressive option. */
16641 if (rs6000_sched_costly_dep == no_dep_costly)
16644 /* If the flag is set to 1 - a dependence is always considered costly;
16645 do not allow dependent instructions in the same group.
16646 This is the most conservative option. */
16647 if (rs6000_sched_costly_dep == all_deps_costly)
16650 if (rs6000_sched_costly_dep == store_to_load_dep_costly
16651 && is_load_insn (next)
16652 && is_store_insn (insn))
16653 /* Prevent load after store in the same group. */
16656 if (rs6000_sched_costly_dep == true_store_to_load_dep_costly
16657 && is_load_insn (next)
16658 && is_store_insn (insn)
16659 && (!link || (int) REG_NOTE_KIND (link) == 0))
16660 /* Prevent load after store in the same group if it is a true
16664 /* The flag is set to X; dependences with latency >= X are considered costly,
16665 and will not be scheduled in the same group. */
16666 if (rs6000_sched_costly_dep <= max_dep_latency
16667 && ((cost - distance) >= (int)rs6000_sched_costly_dep))
16673 /* Return the next insn after INSN that is found before TAIL is reached,
16674 skipping any "non-active" insns - insns that will not actually occupy
16675 an issue slot. Return NULL_RTX if such an insn is not found. */
16678 get_next_active_insn (rtx insn, rtx tail)
16682 if (!insn || insn == tail)
16685 next_insn = NEXT_INSN (insn);
16688 && next_insn != tail
16689 && (GET_CODE (next_insn) == NOTE
16690 || GET_CODE (PATTERN (next_insn)) == USE
16691 || GET_CODE (PATTERN (next_insn)) == CLOBBER))
16693 next_insn = NEXT_INSN (next_insn);
16696 if (!next_insn || next_insn == tail)
16702 /* Return whether the presence of INSN causes a dispatch group termination
16703 of group WHICH_GROUP.
16705 If WHICH_GROUP == current_group, this function will return true if INSN
16706 causes the termination of the current group (i.e, the dispatch group to
16707 which INSN belongs). This means that INSN will be the last insn in the
16708 group it belongs to.
16710 If WHICH_GROUP == previous_group, this function will return true if INSN
16711 causes the termination of the previous group (i.e, the dispatch group that
16712 precedes the group to which INSN belongs). This means that INSN will be
16713 the first insn in the group it belongs to). */
16716 insn_terminates_group_p (rtx insn, enum group_termination which_group)
16718 enum attr_type type;
16723 type = get_attr_type (insn);
16725 if (is_microcoded_insn (insn))
16728 if (which_group == current_group)
16730 if (is_branch_slot_insn (insn))
16734 else if (which_group == previous_group)
16736 if (is_dispatch_slot_restricted (insn))
16744 /* Return true if it is recommended to keep NEXT_INSN "far" (in a separate
16745 dispatch group) from the insns in GROUP_INSNS. Return false otherwise. */
16748 is_costly_group (rtx *group_insns, rtx next_insn)
16753 int issue_rate = rs6000_issue_rate ();
16755 for (i = 0; i < issue_rate; i++)
16757 rtx insn = group_insns[i];
16760 for (link = INSN_DEPEND (insn); link != 0; link = XEXP (link, 1))
16762 rtx next = XEXP (link, 0);
16763 if (next == next_insn)
16765 cost = insn_cost (insn, link, next_insn);
16766 if (rs6000_is_costly_dependence (insn, next_insn, link, cost, 0))
16775 /* Utility of the function redefine_groups.
16776 Check if it is too costly to schedule NEXT_INSN together with GROUP_INSNS
16777 in the same dispatch group. If so, insert nops before NEXT_INSN, in order
16778 to keep it "far" (in a separate group) from GROUP_INSNS, following
16779 one of the following schemes, depending on the value of the flag
16780 -minsert_sched_nops = X:
16781 (1) X == sched_finish_regroup_exact: insert exactly as many nops as needed
16782 in order to force NEXT_INSN into a separate group.
16783 (2) X < sched_finish_regroup_exact: insert exactly X nops.
16784 GROUP_END, CAN_ISSUE_MORE and GROUP_COUNT record the state after nop
16785 insertion (has a group just ended, how many vacant issue slots remain in the
16786 last group, and how many dispatch groups were encountered so far). */
16789 force_new_group (int sched_verbose, FILE *dump, rtx *group_insns,
16790 rtx next_insn, bool *group_end, int can_issue_more,
16795 int issue_rate = rs6000_issue_rate ();
16796 bool end = *group_end;
16799 if (next_insn == NULL_RTX)
16800 return can_issue_more;
16802 if (rs6000_sched_insert_nops > sched_finish_regroup_exact)
16803 return can_issue_more;
16805 force = is_costly_group (group_insns, next_insn);
16807 return can_issue_more;
16809 if (sched_verbose > 6)
16810 fprintf (dump,"force: group count = %d, can_issue_more = %d\n",
16811 *group_count ,can_issue_more);
16813 if (rs6000_sched_insert_nops == sched_finish_regroup_exact)
16816 can_issue_more = 0;
16818 /* Since only a branch can be issued in the last issue_slot, it is
16819 sufficient to insert 'can_issue_more - 1' nops if next_insn is not
16820 a branch. If next_insn is a branch, we insert 'can_issue_more' nops;
16821 in this case the last nop will start a new group and the branch
16822 will be forced to the new group. */
16823 if (can_issue_more && !is_branch_slot_insn (next_insn))
16826 while (can_issue_more > 0)
16829 emit_insn_before (nop, next_insn);
16837 if (rs6000_sched_insert_nops < sched_finish_regroup_exact)
16839 int n_nops = rs6000_sched_insert_nops;
16841 /* Nops can't be issued from the branch slot, so the effective
16842 issue_rate for nops is 'issue_rate - 1'. */
16843 if (can_issue_more == 0)
16844 can_issue_more = issue_rate;
16846 if (can_issue_more == 0)
16848 can_issue_more = issue_rate - 1;
16851 for (i = 0; i < issue_rate; i++)
16853 group_insns[i] = 0;
16860 emit_insn_before (nop, next_insn);
16861 if (can_issue_more == issue_rate - 1) /* new group begins */
16864 if (can_issue_more == 0)
16866 can_issue_more = issue_rate - 1;
16869 for (i = 0; i < issue_rate; i++)
16871 group_insns[i] = 0;
16877 /* Scale back relative to 'issue_rate' (instead of 'issue_rate - 1'). */
16880 /* Is next_insn going to start a new group? */
16883 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16884 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16885 || (can_issue_more < issue_rate &&
16886 insn_terminates_group_p (next_insn, previous_group)));
16887 if (*group_end && end)
16890 if (sched_verbose > 6)
16891 fprintf (dump, "done force: group count = %d, can_issue_more = %d\n",
16892 *group_count, can_issue_more);
16893 return can_issue_more;
16896 return can_issue_more;
16899 /* This function tries to synch the dispatch groups that the compiler "sees"
16900 with the dispatch groups that the processor dispatcher is expected to
16901 form in practice. It tries to achieve this synchronization by forcing the
16902 estimated processor grouping on the compiler (as opposed to the function
16903 'pad_goups' which tries to force the scheduler's grouping on the processor).
16905 The function scans the insn sequence between PREV_HEAD_INSN and TAIL and
16906 examines the (estimated) dispatch groups that will be formed by the processor
16907 dispatcher. It marks these group boundaries to reflect the estimated
16908 processor grouping, overriding the grouping that the scheduler had marked.
16909 Depending on the value of the flag '-minsert-sched-nops' this function can
16910 force certain insns into separate groups or force a certain distance between
16911 them by inserting nops, for example, if there exists a "costly dependence"
16914 The function estimates the group boundaries that the processor will form as
16915 follows: It keeps track of how many vacant issue slots are available after
16916 each insn. A subsequent insn will start a new group if one of the following
16918 - no more vacant issue slots remain in the current dispatch group.
16919 - only the last issue slot, which is the branch slot, is vacant, but the next
16920 insn is not a branch.
16921 - only the last 2 or less issue slots, including the branch slot, are vacant,
16922 which means that a cracked insn (which occupies two issue slots) can't be
16923 issued in this group.
16924 - less than 'issue_rate' slots are vacant, and the next insn always needs to
16925 start a new group. */
16928 redefine_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
16930 rtx insn, next_insn;
16932 int can_issue_more;
16935 int group_count = 0;
16939 issue_rate = rs6000_issue_rate ();
16940 group_insns = alloca (issue_rate * sizeof (rtx));
16941 for (i = 0; i < issue_rate; i++)
16943 group_insns[i] = 0;
16945 can_issue_more = issue_rate;
16947 insn = get_next_active_insn (prev_head_insn, tail);
16950 while (insn != NULL_RTX)
16952 slot = (issue_rate - can_issue_more);
16953 group_insns[slot] = insn;
16955 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
16956 if (insn_terminates_group_p (insn, current_group))
16957 can_issue_more = 0;
16959 next_insn = get_next_active_insn (insn, tail);
16960 if (next_insn == NULL_RTX)
16961 return group_count + 1;
16963 /* Is next_insn going to start a new group? */
16965 = (can_issue_more == 0
16966 || (can_issue_more == 1 && !is_branch_slot_insn (next_insn))
16967 || (can_issue_more <= 2 && is_cracked_insn (next_insn))
16968 || (can_issue_more < issue_rate &&
16969 insn_terminates_group_p (next_insn, previous_group)));
16971 can_issue_more = force_new_group (sched_verbose, dump, group_insns,
16972 next_insn, &group_end, can_issue_more,
16978 can_issue_more = 0;
16979 for (i = 0; i < issue_rate; i++)
16981 group_insns[i] = 0;
16985 if (GET_MODE (next_insn) == TImode && can_issue_more)
16986 PUT_MODE (next_insn, VOIDmode);
16987 else if (!can_issue_more && GET_MODE (next_insn) != TImode)
16988 PUT_MODE (next_insn, TImode);
16991 if (can_issue_more == 0)
16992 can_issue_more = issue_rate;
16995 return group_count;
16998 /* Scan the insn sequence between PREV_HEAD_INSN and TAIL and examine the
16999 dispatch group boundaries that the scheduler had marked. Pad with nops
17000 any dispatch groups which have vacant issue slots, in order to force the
17001 scheduler's grouping on the processor dispatcher. The function
17002 returns the number of dispatch groups found. */
17005 pad_groups (FILE *dump, int sched_verbose, rtx prev_head_insn, rtx tail)
17007 rtx insn, next_insn;
17010 int can_issue_more;
17012 int group_count = 0;
17014 /* Initialize issue_rate. */
17015 issue_rate = rs6000_issue_rate ();
17016 can_issue_more = issue_rate;
17018 insn = get_next_active_insn (prev_head_insn, tail);
17019 next_insn = get_next_active_insn (insn, tail);
17021 while (insn != NULL_RTX)
17024 rs6000_variable_issue (dump, sched_verbose, insn, can_issue_more);
17026 group_end = (next_insn == NULL_RTX || GET_MODE (next_insn) == TImode);
17028 if (next_insn == NULL_RTX)
17033 /* If the scheduler had marked group termination at this location
17034 (between insn and next_indn), and neither insn nor next_insn will
17035 force group termination, pad the group with nops to force group
17038 && (rs6000_sched_insert_nops == sched_finish_pad_groups)
17039 && !insn_terminates_group_p (insn, current_group)
17040 && !insn_terminates_group_p (next_insn, previous_group))
17042 if (!is_branch_slot_insn (next_insn))
17045 while (can_issue_more)
17048 emit_insn_before (nop, next_insn);
17053 can_issue_more = issue_rate;
17058 next_insn = get_next_active_insn (insn, tail);
17061 return group_count;
17064 /* The following function is called at the end of scheduling BB.
17065 After reload, it inserts nops at insn group bundling. */
17068 rs6000_sched_finish (FILE *dump, int sched_verbose)
17073 fprintf (dump, "=== Finishing schedule.\n");
17075 if (reload_completed && rs6000_sched_groups)
17077 if (rs6000_sched_insert_nops == sched_finish_none)
17080 if (rs6000_sched_insert_nops == sched_finish_pad_groups)
17081 n_groups = pad_groups (dump, sched_verbose,
17082 current_sched_info->prev_head,
17083 current_sched_info->next_tail);
17085 n_groups = redefine_groups (dump, sched_verbose,
17086 current_sched_info->prev_head,
17087 current_sched_info->next_tail);
17089 if (sched_verbose >= 6)
17091 fprintf (dump, "ngroups = %d\n", n_groups);
17092 print_rtl (dump, current_sched_info->prev_head);
17093 fprintf (dump, "Done finish_sched\n");
17098 /* Length in units of the trampoline for entering a nested function. */
17101 rs6000_trampoline_size (void)
17105 switch (DEFAULT_ABI)
17108 gcc_unreachable ();
17111 ret = (TARGET_32BIT) ? 12 : 24;
17116 ret = (TARGET_32BIT) ? 40 : 48;
17123 /* Emit RTL insns to initialize the variable parts of a trampoline.
17124 FNADDR is an RTX for the address of the function's pure code.
17125 CXT is an RTX for the static chain value for the function. */
17128 rs6000_initialize_trampoline (rtx addr, rtx fnaddr, rtx cxt)
17130 enum machine_mode pmode = Pmode;
17131 int regsize = (TARGET_32BIT) ? 4 : 8;
17132 rtx ctx_reg = force_reg (pmode, cxt);
17134 switch (DEFAULT_ABI)
17137 gcc_unreachable ();
17139 /* Macros to shorten the code expansions below. */
17140 #define MEM_DEREF(addr) gen_rtx_MEM (pmode, memory_address (pmode, addr))
17141 #define MEM_PLUS(addr,offset) \
17142 gen_rtx_MEM (pmode, memory_address (pmode, plus_constant (addr, offset)))
17144 /* Under AIX, just build the 3 word function descriptor */
17147 rtx fn_reg = gen_reg_rtx (pmode);
17148 rtx toc_reg = gen_reg_rtx (pmode);
17149 emit_move_insn (fn_reg, MEM_DEREF (fnaddr));
17150 emit_move_insn (toc_reg, MEM_PLUS (fnaddr, regsize));
17151 emit_move_insn (MEM_DEREF (addr), fn_reg);
17152 emit_move_insn (MEM_PLUS (addr, regsize), toc_reg);
17153 emit_move_insn (MEM_PLUS (addr, 2*regsize), ctx_reg);
17157 /* Under V.4/eabi/darwin, __trampoline_setup does the real work. */
17160 emit_library_call (gen_rtx_SYMBOL_REF (SImode, "__trampoline_setup"),
17161 FALSE, VOIDmode, 4,
17163 GEN_INT (rs6000_trampoline_size ()), SImode,
17173 /* Table of valid machine attributes. */
17175 const struct attribute_spec rs6000_attribute_table[] =
17177 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler } */
17178 { "altivec", 1, 1, false, true, false, rs6000_handle_altivec_attribute },
17179 { "longcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17180 { "shortcall", 0, 0, false, true, true, rs6000_handle_longcall_attribute },
17181 #ifdef SUBTARGET_ATTRIBUTE_TABLE
17182 SUBTARGET_ATTRIBUTE_TABLE,
17184 { NULL, 0, 0, false, false, false, NULL }
17187 /* Handle the "altivec" attribute. The attribute may have
17188 arguments as follows:
17190 __attribute__((altivec(vector__)))
17191 __attribute__((altivec(pixel__))) (always followed by 'unsigned short')
17192 __attribute__((altivec(bool__))) (always followed by 'unsigned')
17194 and may appear more than once (e.g., 'vector bool char') in a
17195 given declaration. */
17198 rs6000_handle_altivec_attribute (tree *node,
17199 tree name ATTRIBUTE_UNUSED,
17201 int flags ATTRIBUTE_UNUSED,
17202 bool *no_add_attrs)
17204 tree type = *node, result = NULL_TREE;
17205 enum machine_mode mode;
17208 = ((args && TREE_CODE (args) == TREE_LIST && TREE_VALUE (args)
17209 && TREE_CODE (TREE_VALUE (args)) == IDENTIFIER_NODE)
17210 ? *IDENTIFIER_POINTER (TREE_VALUE (args))
17213 while (POINTER_TYPE_P (type)
17214 || TREE_CODE (type) == FUNCTION_TYPE
17215 || TREE_CODE (type) == METHOD_TYPE
17216 || TREE_CODE (type) == ARRAY_TYPE)
17217 type = TREE_TYPE (type);
17219 mode = TYPE_MODE (type);
17221 /* Check for invalid AltiVec type qualifiers. */
17222 if (type == long_unsigned_type_node || type == long_integer_type_node)
17225 error ("use of %<long%> in AltiVec types is invalid for 64-bit code");
17226 else if (rs6000_warn_altivec_long)
17227 warning (0, "use of %<long%> in AltiVec types is deprecated; use %<int%>");
17229 else if (type == long_long_unsigned_type_node
17230 || type == long_long_integer_type_node)
17231 error ("use of %<long long%> in AltiVec types is invalid");
17232 else if (type == double_type_node)
17233 error ("use of %<double%> in AltiVec types is invalid");
17234 else if (type == long_double_type_node)
17235 error ("use of %<long double%> in AltiVec types is invalid");
17236 else if (type == boolean_type_node)
17237 error ("use of boolean types in AltiVec types is invalid");
17238 else if (TREE_CODE (type) == COMPLEX_TYPE)
17239 error ("use of %<complex%> in AltiVec types is invalid");
17241 switch (altivec_type)
17244 unsigned_p = TYPE_UNSIGNED (type);
17248 result = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node);
17251 result = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node);
17254 result = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node);
17256 case SFmode: result = V4SF_type_node; break;
17257 /* If the user says 'vector int bool', we may be handed the 'bool'
17258 attribute _before_ the 'vector' attribute, and so select the
17259 proper type in the 'b' case below. */
17260 case V4SImode: case V8HImode: case V16QImode: case V4SFmode:
17268 case SImode: case V4SImode: result = bool_V4SI_type_node; break;
17269 case HImode: case V8HImode: result = bool_V8HI_type_node; break;
17270 case QImode: case V16QImode: result = bool_V16QI_type_node;
17277 case V8HImode: result = pixel_V8HI_type_node;
17283 if (result && result != type && TYPE_READONLY (type))
17284 result = build_qualified_type (result, TYPE_QUAL_CONST);
17286 *no_add_attrs = true; /* No need to hang on to the attribute. */
17289 *node = reconstruct_complex_type (*node, result);
17294 /* AltiVec defines four built-in scalar types that serve as vector
17295 elements; we must teach the compiler how to mangle them. */
17297 static const char *
17298 rs6000_mangle_fundamental_type (tree type)
17300 if (type == bool_char_type_node) return "U6__boolc";
17301 if (type == bool_short_type_node) return "U6__bools";
17302 if (type == pixel_type_node) return "u7__pixel";
17303 if (type == bool_int_type_node) return "U6__booli";
17305 /* For all other types, use normal C++ mangling. */
17309 /* Handle a "longcall" or "shortcall" attribute; arguments as in
17310 struct attribute_spec.handler. */
17313 rs6000_handle_longcall_attribute (tree *node, tree name,
17314 tree args ATTRIBUTE_UNUSED,
17315 int flags ATTRIBUTE_UNUSED,
17316 bool *no_add_attrs)
17318 if (TREE_CODE (*node) != FUNCTION_TYPE
17319 && TREE_CODE (*node) != FIELD_DECL
17320 && TREE_CODE (*node) != TYPE_DECL)
17322 warning (OPT_Wattributes, "%qs attribute only applies to functions",
17323 IDENTIFIER_POINTER (name));
17324 *no_add_attrs = true;
17330 /* Set longcall attributes on all functions declared when
17331 rs6000_default_long_calls is true. */
17333 rs6000_set_default_type_attributes (tree type)
17335 if (rs6000_default_long_calls
17336 && (TREE_CODE (type) == FUNCTION_TYPE
17337 || TREE_CODE (type) == METHOD_TYPE))
17338 TYPE_ATTRIBUTES (type) = tree_cons (get_identifier ("longcall"),
17340 TYPE_ATTRIBUTES (type));
17343 /* Return a reference suitable for calling a function with the
17344 longcall attribute. */
17347 rs6000_longcall_ref (rtx call_ref)
17349 const char *call_name;
17352 if (GET_CODE (call_ref) != SYMBOL_REF)
17355 /* System V adds '.' to the internal name, so skip them. */
17356 call_name = XSTR (call_ref, 0);
17357 if (*call_name == '.')
17359 while (*call_name == '.')
17362 node = get_identifier (call_name);
17363 call_ref = gen_rtx_SYMBOL_REF (VOIDmode, IDENTIFIER_POINTER (node));
17366 return force_reg (Pmode, call_ref);
17369 #ifdef USING_ELFOS_H
17371 /* A C statement or statements to switch to the appropriate section
17372 for output of RTX in mode MODE. You can assume that RTX is some
17373 kind of constant in RTL. The argument MODE is redundant except in
17374 the case of a `const_int' rtx. Select the section by calling
17375 `text_section' or one of the alternatives for other sections.
17377 Do not define this macro if you put all constants in the read-only
17381 rs6000_elf_select_rtx_section (enum machine_mode mode, rtx x,
17382 unsigned HOST_WIDE_INT align)
17384 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
17387 default_elf_select_rtx_section (mode, x, align);
17390 /* A C statement or statements to switch to the appropriate
17391 section for output of DECL. DECL is either a `VAR_DECL' node
17392 or a constant of some sort. RELOC indicates whether forming
17393 the initial value of DECL requires link-time relocations. */
17396 rs6000_elf_select_section (tree decl, int reloc,
17397 unsigned HOST_WIDE_INT align)
17399 /* Pretend that we're always building for a shared library when
17400 ABI_AIX, because otherwise we end up with dynamic relocations
17401 in read-only sections. This happens for function pointers,
17402 references to vtables in typeinfo, and probably other cases. */
17403 default_elf_select_section_1 (decl, reloc, align,
17404 flag_pic || DEFAULT_ABI == ABI_AIX);
17407 /* A C statement to build up a unique section name, expressed as a
17408 STRING_CST node, and assign it to DECL_SECTION_NAME (decl).
17409 RELOC indicates whether the initial value of EXP requires
17410 link-time relocations. If you do not define this macro, GCC will use
17411 the symbol name prefixed by `.' as the section name. Note - this
17412 macro can now be called for uninitialized data items as well as
17413 initialized data and functions. */
17416 rs6000_elf_unique_section (tree decl, int reloc)
17418 /* As above, pretend that we're always building for a shared library
17419 when ABI_AIX, to avoid dynamic relocations in read-only sections. */
17420 default_unique_section_1 (decl, reloc,
17421 flag_pic || DEFAULT_ABI == ABI_AIX);
17424 /* For a SYMBOL_REF, set generic flags and then perform some
17425 target-specific processing.
17427 When the AIX ABI is requested on a non-AIX system, replace the
17428 function name with the real name (with a leading .) rather than the
17429 function descriptor name. This saves a lot of overriding code to
17430 read the prefixes. */
17433 rs6000_elf_encode_section_info (tree decl, rtx rtl, int first)
17435 default_encode_section_info (decl, rtl, first);
17438 && TREE_CODE (decl) == FUNCTION_DECL
17440 && DEFAULT_ABI == ABI_AIX)
17442 rtx sym_ref = XEXP (rtl, 0);
17443 size_t len = strlen (XSTR (sym_ref, 0));
17444 char *str = alloca (len + 2);
17446 memcpy (str + 1, XSTR (sym_ref, 0), len + 1);
17447 XSTR (sym_ref, 0) = ggc_alloc_string (str, len + 1);
17452 rs6000_elf_in_small_data_p (tree decl)
17454 if (rs6000_sdata == SDATA_NONE)
17457 /* We want to merge strings, so we never consider them small data. */
17458 if (TREE_CODE (decl) == STRING_CST)
17461 /* Functions are never in the small data area. */
17462 if (TREE_CODE (decl) == FUNCTION_DECL)
17465 if (TREE_CODE (decl) == VAR_DECL && DECL_SECTION_NAME (decl))
17467 const char *section = TREE_STRING_POINTER (DECL_SECTION_NAME (decl));
17468 if (strcmp (section, ".sdata") == 0
17469 || strcmp (section, ".sdata2") == 0
17470 || strcmp (section, ".sbss") == 0
17471 || strcmp (section, ".sbss2") == 0
17472 || strcmp (section, ".PPC.EMB.sdata0") == 0
17473 || strcmp (section, ".PPC.EMB.sbss0") == 0)
17478 HOST_WIDE_INT size = int_size_in_bytes (TREE_TYPE (decl));
17481 && (unsigned HOST_WIDE_INT) size <= g_switch_value
17482 /* If it's not public, and we're not going to reference it there,
17483 there's no need to put it in the small data section. */
17484 && (rs6000_sdata != SDATA_DATA || TREE_PUBLIC (decl)))
17491 #endif /* USING_ELFOS_H */
17494 /* Return a REG that occurs in ADDR with coefficient 1.
17495 ADDR can be effectively incremented by incrementing REG.
17497 r0 is special and we must not select it as an address
17498 register by this routine since our caller will try to
17499 increment the returned register via an "la" instruction. */
17502 find_addr_reg (rtx addr)
17504 while (GET_CODE (addr) == PLUS)
17506 if (GET_CODE (XEXP (addr, 0)) == REG
17507 && REGNO (XEXP (addr, 0)) != 0)
17508 addr = XEXP (addr, 0);
17509 else if (GET_CODE (XEXP (addr, 1)) == REG
17510 && REGNO (XEXP (addr, 1)) != 0)
17511 addr = XEXP (addr, 1);
17512 else if (CONSTANT_P (XEXP (addr, 0)))
17513 addr = XEXP (addr, 1);
17514 else if (CONSTANT_P (XEXP (addr, 1)))
17515 addr = XEXP (addr, 0);
17517 gcc_unreachable ();
17519 gcc_assert (GET_CODE (addr) == REG && REGNO (addr) != 0);
17524 rs6000_fatal_bad_address (rtx op)
17526 fatal_insn ("bad address", op);
17531 static tree branch_island_list = 0;
17533 /* Remember to generate a branch island for far calls to the given
17537 add_compiler_branch_island (tree label_name, tree function_name,
17540 tree branch_island = build_tree_list (function_name, label_name);
17541 TREE_TYPE (branch_island) = build_int_cst (NULL_TREE, line_number);
17542 TREE_CHAIN (branch_island) = branch_island_list;
17543 branch_island_list = branch_island;
17546 #define BRANCH_ISLAND_LABEL_NAME(BRANCH_ISLAND) TREE_VALUE (BRANCH_ISLAND)
17547 #define BRANCH_ISLAND_FUNCTION_NAME(BRANCH_ISLAND) TREE_PURPOSE (BRANCH_ISLAND)
17548 #define BRANCH_ISLAND_LINE_NUMBER(BRANCH_ISLAND) \
17549 TREE_INT_CST_LOW (TREE_TYPE (BRANCH_ISLAND))
17551 /* Generate far-jump branch islands for everything on the
17552 branch_island_list. Invoked immediately after the last instruction
17553 of the epilogue has been emitted; the branch-islands must be
17554 appended to, and contiguous with, the function body. Mach-O stubs
17555 are generated in machopic_output_stub(). */
17558 macho_branch_islands (void)
17561 tree branch_island;
17563 for (branch_island = branch_island_list;
17565 branch_island = TREE_CHAIN (branch_island))
17567 const char *label =
17568 IDENTIFIER_POINTER (BRANCH_ISLAND_LABEL_NAME (branch_island));
17570 IDENTIFIER_POINTER (BRANCH_ISLAND_FUNCTION_NAME (branch_island));
17571 char name_buf[512];
17572 /* Cheap copy of the details from the Darwin ASM_OUTPUT_LABELREF(). */
17573 if (name[0] == '*' || name[0] == '&')
17574 strcpy (name_buf, name+1);
17578 strcpy (name_buf+1, name);
17580 strcpy (tmp_buf, "\n");
17581 strcat (tmp_buf, label);
17582 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17583 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17584 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17585 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17588 strcat (tmp_buf, ":\n\tmflr r0\n\tbcl 20,31,");
17589 strcat (tmp_buf, label);
17590 strcat (tmp_buf, "_pic\n");
17591 strcat (tmp_buf, label);
17592 strcat (tmp_buf, "_pic:\n\tmflr r11\n");
17594 strcat (tmp_buf, "\taddis r11,r11,ha16(");
17595 strcat (tmp_buf, name_buf);
17596 strcat (tmp_buf, " - ");
17597 strcat (tmp_buf, label);
17598 strcat (tmp_buf, "_pic)\n");
17600 strcat (tmp_buf, "\tmtlr r0\n");
17602 strcat (tmp_buf, "\taddi r12,r11,lo16(");
17603 strcat (tmp_buf, name_buf);
17604 strcat (tmp_buf, " - ");
17605 strcat (tmp_buf, label);
17606 strcat (tmp_buf, "_pic)\n");
17608 strcat (tmp_buf, "\tmtctr r12\n\tbctr\n");
17612 strcat (tmp_buf, ":\nlis r12,hi16(");
17613 strcat (tmp_buf, name_buf);
17614 strcat (tmp_buf, ")\n\tori r12,r12,lo16(");
17615 strcat (tmp_buf, name_buf);
17616 strcat (tmp_buf, ")\n\tmtctr r12\n\tbctr");
17618 output_asm_insn (tmp_buf, 0);
17619 #if defined (DBX_DEBUGGING_INFO) || defined (XCOFF_DEBUGGING_INFO)
17620 if (write_symbols == DBX_DEBUG || write_symbols == XCOFF_DEBUG)
17621 dbxout_stabd (N_SLINE, BRANCH_ISLAND_LINE_NUMBER (branch_island));
17622 #endif /* DBX_DEBUGGING_INFO || XCOFF_DEBUGGING_INFO */
17625 branch_island_list = 0;
17628 /* NO_PREVIOUS_DEF checks in the link list whether the function name is
17629 already there or not. */
17632 no_previous_def (tree function_name)
17634 tree branch_island;
17635 for (branch_island = branch_island_list;
17637 branch_island = TREE_CHAIN (branch_island))
17638 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17643 /* GET_PREV_LABEL gets the label name from the previous definition of
17647 get_prev_label (tree function_name)
17649 tree branch_island;
17650 for (branch_island = branch_island_list;
17652 branch_island = TREE_CHAIN (branch_island))
17653 if (function_name == BRANCH_ISLAND_FUNCTION_NAME (branch_island))
17654 return BRANCH_ISLAND_LABEL_NAME (branch_island);
17658 /* INSN is either a function call or a millicode call. It may have an
17659 unconditional jump in its delay slot.
17661 CALL_DEST is the routine we are calling. */
17664 output_call (rtx insn, rtx *operands, int dest_operand_number,
17665 int cookie_operand_number)
17667 static char buf[256];
17668 if (GET_CODE (operands[dest_operand_number]) == SYMBOL_REF
17669 && (INTVAL (operands[cookie_operand_number]) & CALL_LONG))
17672 tree funname = get_identifier (XSTR (operands[dest_operand_number], 0));
17674 if (no_previous_def (funname))
17676 int line_number = 0;
17677 rtx label_rtx = gen_label_rtx ();
17678 char *label_buf, temp_buf[256];
17679 ASM_GENERATE_INTERNAL_LABEL (temp_buf, "L",
17680 CODE_LABEL_NUMBER (label_rtx));
17681 label_buf = temp_buf[0] == '*' ? temp_buf + 1 : temp_buf;
17682 labelname = get_identifier (label_buf);
17683 for (; insn && GET_CODE (insn) != NOTE; insn = PREV_INSN (insn));
17685 line_number = NOTE_LINE_NUMBER (insn);
17686 add_compiler_branch_island (labelname, funname, line_number);
17689 labelname = get_prev_label (funname);
17691 /* "jbsr foo, L42" is Mach-O for "Link as 'bl foo' if a 'bl'
17692 instruction will reach 'foo', otherwise link as 'bl L42'".
17693 "L42" should be a 'branch island', that will do a far jump to
17694 'foo'. Branch islands are generated in
17695 macho_branch_islands(). */
17696 sprintf (buf, "jbsr %%z%d,%.246s",
17697 dest_operand_number, IDENTIFIER_POINTER (labelname));
17700 sprintf (buf, "bl %%z%d", dest_operand_number);
17704 /* Generate PIC and indirect symbol stubs. */
17707 machopic_output_stub (FILE *file, const char *symb, const char *stub)
17709 unsigned int length;
17710 char *symbol_name, *lazy_ptr_name;
17711 char *local_label_0;
17712 static int label = 0;
17714 /* Lose our funky encoding stuff so it doesn't contaminate the stub. */
17715 symb = (*targetm.strip_name_encoding) (symb);
17718 length = strlen (symb);
17719 symbol_name = alloca (length + 32);
17720 GEN_SYMBOL_NAME_FOR_SYMBOL (symbol_name, symb, length);
17722 lazy_ptr_name = alloca (length + 32);
17723 GEN_LAZY_PTR_NAME_FOR_SYMBOL (lazy_ptr_name, symb, length);
17726 machopic_picsymbol_stub1_section ();
17728 machopic_symbol_stub1_section ();
17732 fprintf (file, "\t.align 5\n");
17734 fprintf (file, "%s:\n", stub);
17735 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17738 local_label_0 = alloca (sizeof ("\"L00000000000$spb\""));
17739 sprintf (local_label_0, "\"L%011d$spb\"", label);
17741 fprintf (file, "\tmflr r0\n");
17742 fprintf (file, "\tbcl 20,31,%s\n", local_label_0);
17743 fprintf (file, "%s:\n\tmflr r11\n", local_label_0);
17744 fprintf (file, "\taddis r11,r11,ha16(%s-%s)\n",
17745 lazy_ptr_name, local_label_0);
17746 fprintf (file, "\tmtlr r0\n");
17747 fprintf (file, "\t%s r12,lo16(%s-%s)(r11)\n",
17748 (TARGET_64BIT ? "ldu" : "lwzu"),
17749 lazy_ptr_name, local_label_0);
17750 fprintf (file, "\tmtctr r12\n");
17751 fprintf (file, "\tbctr\n");
17755 fprintf (file, "\t.align 4\n");
17757 fprintf (file, "%s:\n", stub);
17758 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17760 fprintf (file, "\tlis r11,ha16(%s)\n", lazy_ptr_name);
17761 fprintf (file, "\t%s r12,lo16(%s)(r11)\n",
17762 (TARGET_64BIT ? "ldu" : "lwzu"),
17764 fprintf (file, "\tmtctr r12\n");
17765 fprintf (file, "\tbctr\n");
17768 machopic_lazy_symbol_ptr_section ();
17769 fprintf (file, "%s:\n", lazy_ptr_name);
17770 fprintf (file, "\t.indirect_symbol %s\n", symbol_name);
17771 fprintf (file, "%sdyld_stub_binding_helper\n",
17772 (TARGET_64BIT ? DOUBLE_INT_ASM_OP : "\t.long\t"));
17775 /* Legitimize PIC addresses. If the address is already
17776 position-independent, we return ORIG. Newly generated
17777 position-independent addresses go into a reg. This is REG if non
17778 zero, otherwise we allocate register(s) as necessary. */
17780 #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
17783 rs6000_machopic_legitimize_pic_address (rtx orig, enum machine_mode mode,
17788 if (reg == NULL && ! reload_in_progress && ! reload_completed)
17789 reg = gen_reg_rtx (Pmode);
17791 if (GET_CODE (orig) == CONST)
17795 if (GET_CODE (XEXP (orig, 0)) == PLUS
17796 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
17799 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
17801 /* Use a different reg for the intermediate value, as
17802 it will be marked UNCHANGING. */
17803 reg_temp = no_new_pseudos ? reg : gen_reg_rtx (Pmode);
17804 base = rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 0),
17807 rs6000_machopic_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
17810 if (GET_CODE (offset) == CONST_INT)
17812 if (SMALL_INT (offset))
17813 return plus_constant (base, INTVAL (offset));
17814 else if (! reload_in_progress && ! reload_completed)
17815 offset = force_reg (Pmode, offset);
17818 rtx mem = force_const_mem (Pmode, orig);
17819 return machopic_legitimize_pic_address (mem, Pmode, reg);
17822 return gen_rtx_PLUS (Pmode, base, offset);
17825 /* Fall back on generic machopic code. */
17826 return machopic_legitimize_pic_address (orig, mode, reg);
17829 /* This is just a placeholder to make linking work without having to
17830 add this to the generic Darwin EXTRA_SECTIONS. If -mcall-aix is
17831 ever needed for Darwin (not too likely!) this would have to get a
17832 real definition. */
17839 /* Output a .machine directive for the Darwin assembler, and call
17840 the generic start_file routine. */
17843 rs6000_darwin_file_start (void)
17845 static const struct
17851 { "ppc64", "ppc64", MASK_64BIT },
17852 { "970", "ppc970", MASK_PPC_GPOPT | MASK_MFCRF | MASK_POWERPC64 },
17853 { "power4", "ppc970", 0 },
17854 { "G5", "ppc970", 0 },
17855 { "7450", "ppc7450", 0 },
17856 { "7400", "ppc7400", MASK_ALTIVEC },
17857 { "G4", "ppc7400", 0 },
17858 { "750", "ppc750", 0 },
17859 { "740", "ppc750", 0 },
17860 { "G3", "ppc750", 0 },
17861 { "604e", "ppc604e", 0 },
17862 { "604", "ppc604", 0 },
17863 { "603e", "ppc603", 0 },
17864 { "603", "ppc603", 0 },
17865 { "601", "ppc601", 0 },
17866 { NULL, "ppc", 0 } };
17867 const char *cpu_id = "";
17870 rs6000_file_start ();
17872 /* Determine the argument to -mcpu=. Default to G3 if not specified. */
17873 for (i = 0; i < ARRAY_SIZE (rs6000_select); i++)
17874 if (rs6000_select[i].set_arch_p && rs6000_select[i].string
17875 && rs6000_select[i].string[0] != '\0')
17876 cpu_id = rs6000_select[i].string;
17878 /* Look through the mapping array. Pick the first name that either
17879 matches the argument, has a bit set in IF_SET that is also set
17880 in the target flags, or has a NULL name. */
17883 while (mapping[i].arg != NULL
17884 && strcmp (mapping[i].arg, cpu_id) != 0
17885 && (mapping[i].if_set & target_flags) == 0)
17888 fprintf (asm_out_file, "\t.machine %s\n", mapping[i].name);
17891 #endif /* TARGET_MACHO */
17894 static unsigned int
17895 rs6000_elf_section_type_flags (tree decl, const char *name, int reloc)
17897 return default_section_type_flags_1 (decl, name, reloc,
17898 flag_pic || DEFAULT_ABI == ABI_AIX);
17901 /* Record an element in the table of global constructors. SYMBOL is
17902 a SYMBOL_REF of the function to be called; PRIORITY is a number
17903 between 0 and MAX_INIT_PRIORITY.
17905 This differs from default_named_section_asm_out_constructor in
17906 that we have special handling for -mrelocatable. */
17909 rs6000_elf_asm_out_constructor (rtx symbol, int priority)
17911 const char *section = ".ctors";
17914 if (priority != DEFAULT_INIT_PRIORITY)
17916 sprintf (buf, ".ctors.%.5u",
17917 /* Invert the numbering so the linker puts us in the proper
17918 order; constructors are run from right to left, and the
17919 linker sorts in increasing order. */
17920 MAX_INIT_PRIORITY - priority);
17924 named_section_flags (section, SECTION_WRITE);
17925 assemble_align (POINTER_SIZE);
17927 if (TARGET_RELOCATABLE)
17929 fputs ("\t.long (", asm_out_file);
17930 output_addr_const (asm_out_file, symbol);
17931 fputs (")@fixup\n", asm_out_file);
17934 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17938 rs6000_elf_asm_out_destructor (rtx symbol, int priority)
17940 const char *section = ".dtors";
17943 if (priority != DEFAULT_INIT_PRIORITY)
17945 sprintf (buf, ".dtors.%.5u",
17946 /* Invert the numbering so the linker puts us in the proper
17947 order; constructors are run from right to left, and the
17948 linker sorts in increasing order. */
17949 MAX_INIT_PRIORITY - priority);
17953 named_section_flags (section, SECTION_WRITE);
17954 assemble_align (POINTER_SIZE);
17956 if (TARGET_RELOCATABLE)
17958 fputs ("\t.long (", asm_out_file);
17959 output_addr_const (asm_out_file, symbol);
17960 fputs (")@fixup\n", asm_out_file);
17963 assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, POINTER_SIZE, 1);
17967 rs6000_elf_declare_function_name (FILE *file, const char *name, tree decl)
17971 fputs ("\t.section\t\".opd\",\"aw\"\n\t.align 3\n", file);
17972 ASM_OUTPUT_LABEL (file, name);
17973 fputs (DOUBLE_INT_ASM_OP, file);
17974 rs6000_output_function_entry (file, name);
17975 fputs (",.TOC.@tocbase,0\n\t.previous\n", file);
17978 fputs ("\t.size\t", file);
17979 assemble_name (file, name);
17980 fputs (",24\n\t.type\t.", file);
17981 assemble_name (file, name);
17982 fputs (",@function\n", file);
17983 if (TREE_PUBLIC (decl) && ! DECL_WEAK (decl))
17985 fputs ("\t.globl\t.", file);
17986 assemble_name (file, name);
17991 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
17992 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
17993 rs6000_output_function_entry (file, name);
17994 fputs (":\n", file);
17998 if (TARGET_RELOCATABLE
17999 && !TARGET_SECURE_PLT
18000 && (get_pool_size () != 0 || current_function_profile)
18005 (*targetm.asm_out.internal_label) (file, "LCL", rs6000_pic_labelno);
18007 ASM_GENERATE_INTERNAL_LABEL (buf, "LCTOC", 1);
18008 fprintf (file, "\t.long ");
18009 assemble_name (file, buf);
18011 ASM_GENERATE_INTERNAL_LABEL (buf, "LCF", rs6000_pic_labelno);
18012 assemble_name (file, buf);
18016 ASM_OUTPUT_TYPE_DIRECTIVE (file, name, "function");
18017 ASM_DECLARE_RESULT (file, DECL_RESULT (decl));
18019 if (DEFAULT_ABI == ABI_AIX)
18021 const char *desc_name, *orig_name;
18023 orig_name = (*targetm.strip_name_encoding) (name);
18024 desc_name = orig_name;
18025 while (*desc_name == '.')
18028 if (TREE_PUBLIC (decl))
18029 fprintf (file, "\t.globl %s\n", desc_name);
18031 fprintf (file, "%s\n", MINIMAL_TOC_SECTION_ASM_OP);
18032 fprintf (file, "%s:\n", desc_name);
18033 fprintf (file, "\t.long %s\n", orig_name);
18034 fputs ("\t.long _GLOBAL_OFFSET_TABLE_\n", file);
18035 if (DEFAULT_ABI == ABI_AIX)
18036 fputs ("\t.long 0\n", file);
18037 fprintf (file, "\t.previous\n");
18039 ASM_OUTPUT_LABEL (file, name);
18043 rs6000_elf_end_indicate_exec_stack (void)
18046 file_end_indicate_exec_stack ();
18052 rs6000_xcoff_asm_globalize_label (FILE *stream, const char *name)
18054 fputs (GLOBAL_ASM_OP, stream);
18055 RS6000_OUTPUT_BASENAME (stream, name);
18056 putc ('\n', stream);
18060 rs6000_xcoff_asm_named_section (const char *name, unsigned int flags,
18061 tree decl ATTRIBUTE_UNUSED)
18064 static const char * const suffix[3] = { "PR", "RO", "RW" };
18066 if (flags & SECTION_CODE)
18068 else if (flags & SECTION_WRITE)
18073 fprintf (asm_out_file, "\t.csect %s%s[%s],%u\n",
18074 (flags & SECTION_CODE) ? "." : "",
18075 name, suffix[smclass], flags & SECTION_ENTSIZE);
18079 rs6000_xcoff_select_section (tree decl, int reloc,
18080 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18082 if (decl_readonly_section_1 (decl, reloc, 1))
18084 if (TREE_PUBLIC (decl))
18085 read_only_data_section ();
18087 read_only_private_data_section ();
18091 if (TREE_PUBLIC (decl))
18094 private_data_section ();
18099 rs6000_xcoff_unique_section (tree decl, int reloc ATTRIBUTE_UNUSED)
18103 /* Use select_section for private and uninitialized data. */
18104 if (!TREE_PUBLIC (decl)
18105 || DECL_COMMON (decl)
18106 || DECL_INITIAL (decl) == NULL_TREE
18107 || DECL_INITIAL (decl) == error_mark_node
18108 || (flag_zero_initialized_in_bss
18109 && initializer_zerop (DECL_INITIAL (decl))))
18112 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl));
18113 name = (*targetm.strip_name_encoding) (name);
18114 DECL_SECTION_NAME (decl) = build_string (strlen (name), name);
18117 /* Select section for constant in constant pool.
18119 On RS/6000, all constants are in the private read-only data area.
18120 However, if this is being placed in the TOC it must be output as a
18124 rs6000_xcoff_select_rtx_section (enum machine_mode mode, rtx x,
18125 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
18127 if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (x, mode))
18130 read_only_private_data_section ();
18133 /* Remove any trailing [DS] or the like from the symbol name. */
18135 static const char *
18136 rs6000_xcoff_strip_name_encoding (const char *name)
18141 len = strlen (name);
18142 if (name[len - 1] == ']')
18143 return ggc_alloc_string (name, len - 4);
18148 /* Section attributes. AIX is always PIC. */
18150 static unsigned int
18151 rs6000_xcoff_section_type_flags (tree decl, const char *name, int reloc)
18153 unsigned int align;
18154 unsigned int flags = default_section_type_flags_1 (decl, name, reloc, 1);
18156 /* Align to at least UNIT size. */
18157 if (flags & SECTION_CODE)
18158 align = MIN_UNITS_PER_WORD;
18160 /* Increase alignment of large objects if not already stricter. */
18161 align = MAX ((DECL_ALIGN (decl) / BITS_PER_UNIT),
18162 int_size_in_bytes (TREE_TYPE (decl)) > MIN_UNITS_PER_WORD
18163 ? UNITS_PER_FP_WORD : MIN_UNITS_PER_WORD);
18165 return flags | (exact_log2 (align) & SECTION_ENTSIZE);
18168 /* Output at beginning of assembler file.
18170 Initialize the section names for the RS/6000 at this point.
18172 Specify filename, including full path, to assembler.
18174 We want to go into the TOC section so at least one .toc will be emitted.
18175 Also, in order to output proper .bs/.es pairs, we need at least one static
18176 [RW] section emitted.
18178 Finally, declare mcount when profiling to make the assembler happy. */
18181 rs6000_xcoff_file_start (void)
18183 rs6000_gen_section_name (&xcoff_bss_section_name,
18184 main_input_filename, ".bss_");
18185 rs6000_gen_section_name (&xcoff_private_data_section_name,
18186 main_input_filename, ".rw_");
18187 rs6000_gen_section_name (&xcoff_read_only_section_name,
18188 main_input_filename, ".ro_");
18190 fputs ("\t.file\t", asm_out_file);
18191 output_quoted_string (asm_out_file, main_input_filename);
18192 fputc ('\n', asm_out_file);
18193 if (write_symbols != NO_DEBUG)
18194 private_data_section ();
18197 fprintf (asm_out_file, "\t.extern %s\n", RS6000_MCOUNT);
18198 rs6000_file_start ();
18201 /* Output at end of assembler file.
18202 On the RS/6000, referencing data should automatically pull in text. */
18205 rs6000_xcoff_file_end (void)
18208 fputs ("_section_.text:\n", asm_out_file);
18210 fputs (TARGET_32BIT
18211 ? "\t.long _section_.text\n" : "\t.llong _section_.text\n",
18214 #endif /* TARGET_XCOFF */
18216 /* Compute a (partial) cost for rtx X. Return true if the complete
18217 cost has been computed, and false if subexpressions should be
18218 scanned. In either case, *TOTAL contains the cost result. */
18221 rs6000_rtx_costs (rtx x, int code, int outer_code, int *total)
18223 enum machine_mode mode = GET_MODE (x);
18227 /* On the RS/6000, if it is valid in the insn, it is free. */
18229 if (((outer_code == SET
18230 || outer_code == PLUS
18231 || outer_code == MINUS)
18232 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18233 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')))
18234 || (outer_code == AND
18235 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18236 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18237 mode == SImode ? 'L' : 'J'))
18238 || mask_operand (x, VOIDmode)))
18239 || ((outer_code == IOR || outer_code == XOR)
18240 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18241 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18242 mode == SImode ? 'L' : 'J'))))
18243 || outer_code == ASHIFT
18244 || outer_code == ASHIFTRT
18245 || outer_code == LSHIFTRT
18246 || outer_code == ROTATE
18247 || outer_code == ROTATERT
18248 || outer_code == ZERO_EXTRACT
18249 || (outer_code == MULT
18250 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18251 || ((outer_code == DIV || outer_code == UDIV
18252 || outer_code == MOD || outer_code == UMOD)
18253 && exact_log2 (INTVAL (x)) >= 0)
18254 || (outer_code == COMPARE
18255 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18256 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')))
18257 || (outer_code == EQ
18258 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'I')
18259 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18260 || (CONST_OK_FOR_LETTER_P (INTVAL (x),
18261 mode == SImode ? 'L' : 'J'))))
18262 || (outer_code == GTU
18263 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'I'))
18264 || (outer_code == LTU
18265 && CONST_OK_FOR_LETTER_P (INTVAL (x), 'P')))
18270 else if ((outer_code == PLUS
18271 && reg_or_add_cint_operand (x, VOIDmode))
18272 || (outer_code == MINUS
18273 && reg_or_sub_cint_operand (x, VOIDmode))
18274 || ((outer_code == SET
18275 || outer_code == IOR
18276 || outer_code == XOR)
18278 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) == 0))
18280 *total = COSTS_N_INSNS (1);
18287 && ((outer_code == AND
18288 && (CONST_OK_FOR_LETTER_P (INTVAL (x), 'K')
18289 || CONST_OK_FOR_LETTER_P (INTVAL (x), 'L')
18290 || mask_operand (x, DImode)))
18291 || ((outer_code == IOR || outer_code == XOR)
18292 && CONST_DOUBLE_HIGH (x) == 0
18293 && (CONST_DOUBLE_LOW (x)
18294 & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0)))
18299 else if (mode == DImode
18300 && (outer_code == SET
18301 || outer_code == IOR
18302 || outer_code == XOR)
18303 && CONST_DOUBLE_HIGH (x) == 0)
18305 *total = COSTS_N_INSNS (1);
18314 /* When optimizing for size, MEM should be slightly more expensive
18315 than generating address, e.g., (plus (reg) (const)).
18316 L1 cache latency is about two instructions. */
18317 *total = optimize_size ? COSTS_N_INSNS (1) + 1 : COSTS_N_INSNS (2);
18325 if (mode == DFmode)
18327 if (GET_CODE (XEXP (x, 0)) == MULT)
18329 /* FNMA accounted in outer NEG. */
18330 if (outer_code == NEG)
18331 *total = rs6000_cost->dmul - rs6000_cost->fp;
18333 *total = rs6000_cost->dmul;
18336 *total = rs6000_cost->fp;
18338 else if (mode == SFmode)
18340 /* FNMA accounted in outer NEG. */
18341 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18344 *total = rs6000_cost->fp;
18346 else if (GET_CODE (XEXP (x, 0)) == MULT)
18348 /* The rs6000 doesn't have shift-and-add instructions. */
18349 rs6000_rtx_costs (XEXP (x, 0), MULT, PLUS, total);
18350 *total += COSTS_N_INSNS (1);
18353 *total = COSTS_N_INSNS (1);
18357 if (mode == DFmode)
18359 if (GET_CODE (XEXP (x, 0)) == MULT)
18361 /* FNMA accounted in outer NEG. */
18362 if (outer_code == NEG)
18365 *total = rs6000_cost->dmul;
18368 *total = rs6000_cost->fp;
18370 else if (mode == SFmode)
18372 /* FNMA accounted in outer NEG. */
18373 if (outer_code == NEG && GET_CODE (XEXP (x, 0)) == MULT)
18376 *total = rs6000_cost->fp;
18378 else if (GET_CODE (XEXP (x, 0)) == MULT)
18380 /* The rs6000 doesn't have shift-and-sub instructions. */
18381 rs6000_rtx_costs (XEXP (x, 0), MULT, MINUS, total);
18382 *total += COSTS_N_INSNS (1);
18385 *total = COSTS_N_INSNS (1);
18389 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18390 && CONST_OK_FOR_LETTER_P (INTVAL (XEXP (x, 1)), 'I'))
18392 if (INTVAL (XEXP (x, 1)) >= -256
18393 && INTVAL (XEXP (x, 1)) <= 255)
18394 *total = rs6000_cost->mulsi_const9;
18396 *total = rs6000_cost->mulsi_const;
18398 /* FMA accounted in outer PLUS/MINUS. */
18399 else if ((mode == DFmode || mode == SFmode)
18400 && (outer_code == PLUS || outer_code == MINUS))
18402 else if (mode == DFmode)
18403 *total = rs6000_cost->dmul;
18404 else if (mode == SFmode)
18405 *total = rs6000_cost->fp;
18406 else if (mode == DImode)
18407 *total = rs6000_cost->muldi;
18409 *total = rs6000_cost->mulsi;
18414 if (FLOAT_MODE_P (mode))
18416 *total = mode == DFmode ? rs6000_cost->ddiv
18417 : rs6000_cost->sdiv;
18424 if (GET_CODE (XEXP (x, 1)) == CONST_INT
18425 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0)
18427 if (code == DIV || code == MOD)
18429 *total = COSTS_N_INSNS (2);
18432 *total = COSTS_N_INSNS (1);
18436 if (GET_MODE (XEXP (x, 1)) == DImode)
18437 *total = rs6000_cost->divdi;
18439 *total = rs6000_cost->divsi;
18441 /* Add in shift and subtract for MOD. */
18442 if (code == MOD || code == UMOD)
18443 *total += COSTS_N_INSNS (2);
18447 *total = COSTS_N_INSNS (4);
18451 if (outer_code == AND || outer_code == IOR || outer_code == XOR)
18462 *total = COSTS_N_INSNS (1);
18470 /* Handle mul_highpart. */
18471 if (outer_code == TRUNCATE
18472 && GET_CODE (XEXP (x, 0)) == MULT)
18474 if (mode == DImode)
18475 *total = rs6000_cost->muldi;
18477 *total = rs6000_cost->mulsi;
18480 else if (outer_code == AND)
18483 *total = COSTS_N_INSNS (1);
18488 if (GET_CODE (XEXP (x, 0)) == MEM)
18491 *total = COSTS_N_INSNS (1);
18497 if (!FLOAT_MODE_P (mode))
18499 *total = COSTS_N_INSNS (1);
18505 case UNSIGNED_FLOAT:
18508 case FLOAT_TRUNCATE:
18509 *total = rs6000_cost->fp;
18513 if (mode == DFmode)
18516 *total = rs6000_cost->fp;
18520 switch (XINT (x, 1))
18523 *total = rs6000_cost->fp;
18535 *total = COSTS_N_INSNS (1);
18538 else if (FLOAT_MODE_P (mode)
18539 && TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS)
18541 *total = rs6000_cost->fp;
18549 /* Carry bit requires mode == Pmode.
18550 NEG or PLUS already counted so only add one. */
18552 && (outer_code == NEG || outer_code == PLUS))
18554 *total = COSTS_N_INSNS (1);
18557 if (outer_code == SET)
18559 if (XEXP (x, 1) == const0_rtx)
18561 *total = COSTS_N_INSNS (2);
18564 else if (mode == Pmode)
18566 *total = COSTS_N_INSNS (3);
18575 if (outer_code == SET && (XEXP (x, 1) == const0_rtx))
18577 *total = COSTS_N_INSNS (2);
18581 if (outer_code == COMPARE)
18595 /* A C expression returning the cost of moving data from a register of class
18596 CLASS1 to one of CLASS2. */
18599 rs6000_register_move_cost (enum machine_mode mode,
18600 enum reg_class from, enum reg_class to)
18602 /* Moves from/to GENERAL_REGS. */
18603 if (reg_classes_intersect_p (to, GENERAL_REGS)
18604 || reg_classes_intersect_p (from, GENERAL_REGS))
18606 if (! reg_classes_intersect_p (to, GENERAL_REGS))
18609 if (from == FLOAT_REGS || from == ALTIVEC_REGS)
18610 return (rs6000_memory_move_cost (mode, from, 0)
18611 + rs6000_memory_move_cost (mode, GENERAL_REGS, 0));
18613 /* It's more expensive to move CR_REGS than CR0_REGS because of the
18615 else if (from == CR_REGS)
18619 /* A move will cost one instruction per GPR moved. */
18620 return 2 * hard_regno_nregs[0][mode];
18623 /* Moving between two similar registers is just one instruction. */
18624 else if (reg_classes_intersect_p (to, from))
18625 return mode == TFmode ? 4 : 2;
18627 /* Everything else has to go through GENERAL_REGS. */
18629 return (rs6000_register_move_cost (mode, GENERAL_REGS, to)
18630 + rs6000_register_move_cost (mode, from, GENERAL_REGS));
18633 /* A C expressions returning the cost of moving data of MODE from a register to
18637 rs6000_memory_move_cost (enum machine_mode mode, enum reg_class class,
18638 int in ATTRIBUTE_UNUSED)
18640 if (reg_classes_intersect_p (class, GENERAL_REGS))
18641 return 4 * hard_regno_nregs[0][mode];
18642 else if (reg_classes_intersect_p (class, FLOAT_REGS))
18643 return 4 * hard_regno_nregs[32][mode];
18644 else if (reg_classes_intersect_p (class, ALTIVEC_REGS))
18645 return 4 * hard_regno_nregs[FIRST_ALTIVEC_REGNO][mode];
18647 return 4 + rs6000_register_move_cost (mode, class, GENERAL_REGS);
18650 /* Newton-Raphson approximation of single-precision floating point divide n/d.
18651 Assumes no trapping math and finite arguments. */
18654 rs6000_emit_swdivsf (rtx res, rtx n, rtx d)
18656 rtx x0, e0, e1, y1, u0, v0, one;
18658 x0 = gen_reg_rtx (SFmode);
18659 e0 = gen_reg_rtx (SFmode);
18660 e1 = gen_reg_rtx (SFmode);
18661 y1 = gen_reg_rtx (SFmode);
18662 u0 = gen_reg_rtx (SFmode);
18663 v0 = gen_reg_rtx (SFmode);
18664 one = force_reg (SFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, SFmode));
18666 /* x0 = 1./d estimate */
18667 emit_insn (gen_rtx_SET (VOIDmode, x0,
18668 gen_rtx_UNSPEC (SFmode, gen_rtvec (1, d),
18670 /* e0 = 1. - d * x0 */
18671 emit_insn (gen_rtx_SET (VOIDmode, e0,
18672 gen_rtx_MINUS (SFmode, one,
18673 gen_rtx_MULT (SFmode, d, x0))));
18674 /* e1 = e0 + e0 * e0 */
18675 emit_insn (gen_rtx_SET (VOIDmode, e1,
18676 gen_rtx_PLUS (SFmode,
18677 gen_rtx_MULT (SFmode, e0, e0), e0)));
18678 /* y1 = x0 + e1 * x0 */
18679 emit_insn (gen_rtx_SET (VOIDmode, y1,
18680 gen_rtx_PLUS (SFmode,
18681 gen_rtx_MULT (SFmode, e1, x0), x0)));
18683 emit_insn (gen_rtx_SET (VOIDmode, u0,
18684 gen_rtx_MULT (SFmode, n, y1)));
18685 /* v0 = n - d * u0 */
18686 emit_insn (gen_rtx_SET (VOIDmode, v0,
18687 gen_rtx_MINUS (SFmode, n,
18688 gen_rtx_MULT (SFmode, d, u0))));
18689 /* res = u0 + v0 * y1 */
18690 emit_insn (gen_rtx_SET (VOIDmode, res,
18691 gen_rtx_PLUS (SFmode,
18692 gen_rtx_MULT (SFmode, v0, y1), u0)));
18695 /* Newton-Raphson approximation of double-precision floating point divide n/d.
18696 Assumes no trapping math and finite arguments. */
18699 rs6000_emit_swdivdf (rtx res, rtx n, rtx d)
18701 rtx x0, e0, e1, e2, y1, y2, y3, u0, v0, one;
18703 x0 = gen_reg_rtx (DFmode);
18704 e0 = gen_reg_rtx (DFmode);
18705 e1 = gen_reg_rtx (DFmode);
18706 e2 = gen_reg_rtx (DFmode);
18707 y1 = gen_reg_rtx (DFmode);
18708 y2 = gen_reg_rtx (DFmode);
18709 y3 = gen_reg_rtx (DFmode);
18710 u0 = gen_reg_rtx (DFmode);
18711 v0 = gen_reg_rtx (DFmode);
18712 one = force_reg (DFmode, CONST_DOUBLE_FROM_REAL_VALUE (dconst1, DFmode));
18714 /* x0 = 1./d estimate */
18715 emit_insn (gen_rtx_SET (VOIDmode, x0,
18716 gen_rtx_UNSPEC (DFmode, gen_rtvec (1, d),
18718 /* e0 = 1. - d * x0 */
18719 emit_insn (gen_rtx_SET (VOIDmode, e0,
18720 gen_rtx_MINUS (DFmode, one,
18721 gen_rtx_MULT (SFmode, d, x0))));
18722 /* y1 = x0 + e0 * x0 */
18723 emit_insn (gen_rtx_SET (VOIDmode, y1,
18724 gen_rtx_PLUS (DFmode,
18725 gen_rtx_MULT (DFmode, e0, x0), x0)));
18727 emit_insn (gen_rtx_SET (VOIDmode, e1,
18728 gen_rtx_MULT (DFmode, e0, e0)));
18729 /* y2 = y1 + e1 * y1 */
18730 emit_insn (gen_rtx_SET (VOIDmode, y2,
18731 gen_rtx_PLUS (DFmode,
18732 gen_rtx_MULT (DFmode, e1, y1), y1)));
18734 emit_insn (gen_rtx_SET (VOIDmode, e2,
18735 gen_rtx_MULT (DFmode, e1, e1)));
18736 /* y3 = y2 + e2 * y2 */
18737 emit_insn (gen_rtx_SET (VOIDmode, y3,
18738 gen_rtx_PLUS (DFmode,
18739 gen_rtx_MULT (DFmode, e2, y2), y2)));
18741 emit_insn (gen_rtx_SET (VOIDmode, u0,
18742 gen_rtx_MULT (DFmode, n, y3)));
18743 /* v0 = n - d * u0 */
18744 emit_insn (gen_rtx_SET (VOIDmode, v0,
18745 gen_rtx_MINUS (DFmode, n,
18746 gen_rtx_MULT (DFmode, d, u0))));
18747 /* res = u0 + v0 * y3 */
18748 emit_insn (gen_rtx_SET (VOIDmode, res,
18749 gen_rtx_PLUS (DFmode,
18750 gen_rtx_MULT (DFmode, v0, y3), u0)));
18753 /* Return an RTX representing where to find the function value of a
18754 function returning MODE. */
18756 rs6000_complex_function_value (enum machine_mode mode)
18758 unsigned int regno;
18760 enum machine_mode inner = GET_MODE_INNER (mode);
18761 unsigned int inner_bytes = GET_MODE_SIZE (inner);
18763 if (FLOAT_MODE_P (mode) && TARGET_HARD_FLOAT && TARGET_FPRS)
18764 regno = FP_ARG_RETURN;
18767 regno = GP_ARG_RETURN;
18769 /* 32-bit is OK since it'll go in r3/r4. */
18770 if (TARGET_32BIT && inner_bytes >= 4)
18771 return gen_rtx_REG (mode, regno);
18774 if (inner_bytes >= 8)
18775 return gen_rtx_REG (mode, regno);
18777 r1 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno),
18779 r2 = gen_rtx_EXPR_LIST (inner, gen_rtx_REG (inner, regno + 1),
18780 GEN_INT (inner_bytes));
18781 return gen_rtx_PARALLEL (mode, gen_rtvec (2, r1, r2));
18784 /* Define how to find the value returned by a function.
18785 VALTYPE is the data type of the value (as a tree).
18786 If the precise function being called is known, FUNC is its FUNCTION_DECL;
18787 otherwise, FUNC is 0.
18789 On the SPE, both FPs and vectors are returned in r3.
18791 On RS/6000 an integer value is in r3 and a floating-point value is in
18792 fp1, unless -msoft-float. */
18795 rs6000_function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
18797 enum machine_mode mode;
18798 unsigned int regno;
18800 /* Special handling for structs in darwin64. */
18801 if (rs6000_darwin64_abi
18802 && TYPE_MODE (valtype) == BLKmode
18803 && TREE_CODE (valtype) == RECORD_TYPE
18804 && int_size_in_bytes (valtype) > 0)
18806 CUMULATIVE_ARGS valcum;
18810 valcum.fregno = FP_ARG_MIN_REG;
18811 valcum.vregno = ALTIVEC_ARG_MIN_REG;
18812 /* Do a trial code generation as if this were going to be passed as
18813 an argument; if any part goes in memory, we return NULL. */
18814 valret = rs6000_darwin64_record_arg (&valcum, valtype, 1, true);
18817 /* Otherwise fall through to standard ABI rules. */
18820 if (TARGET_32BIT && TARGET_POWERPC64 && TYPE_MODE (valtype) == DImode)
18822 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18823 return gen_rtx_PARALLEL (DImode,
18825 gen_rtx_EXPR_LIST (VOIDmode,
18826 gen_rtx_REG (SImode, GP_ARG_RETURN),
18828 gen_rtx_EXPR_LIST (VOIDmode,
18829 gen_rtx_REG (SImode,
18830 GP_ARG_RETURN + 1),
18834 if ((INTEGRAL_TYPE_P (valtype)
18835 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
18836 || POINTER_TYPE_P (valtype))
18837 mode = TARGET_32BIT ? SImode : DImode;
18839 mode = TYPE_MODE (valtype);
18841 if (SCALAR_FLOAT_TYPE_P (valtype) && TARGET_HARD_FLOAT && TARGET_FPRS)
18842 regno = FP_ARG_RETURN;
18843 else if (TREE_CODE (valtype) == COMPLEX_TYPE
18844 && targetm.calls.split_complex_arg)
18845 return rs6000_complex_function_value (mode);
18846 else if (TREE_CODE (valtype) == VECTOR_TYPE
18847 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI
18848 && ALTIVEC_VECTOR_MODE (mode))
18849 regno = ALTIVEC_ARG_RETURN;
18850 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18851 && (mode == DFmode || mode == DCmode))
18852 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18854 regno = GP_ARG_RETURN;
18856 return gen_rtx_REG (mode, regno);
18859 /* Define how to find the value returned by a library function
18860 assuming the value has mode MODE. */
18862 rs6000_libcall_value (enum machine_mode mode)
18864 unsigned int regno;
18866 if (TARGET_32BIT && TARGET_POWERPC64 && mode == DImode)
18868 /* Long long return value need be split in -mpowerpc64, 32bit ABI. */
18869 return gen_rtx_PARALLEL (DImode,
18871 gen_rtx_EXPR_LIST (VOIDmode,
18872 gen_rtx_REG (SImode, GP_ARG_RETURN),
18874 gen_rtx_EXPR_LIST (VOIDmode,
18875 gen_rtx_REG (SImode,
18876 GP_ARG_RETURN + 1),
18880 if (GET_MODE_CLASS (mode) == MODE_FLOAT
18881 && TARGET_HARD_FLOAT && TARGET_FPRS)
18882 regno = FP_ARG_RETURN;
18883 else if (ALTIVEC_VECTOR_MODE (mode)
18884 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)
18885 regno = ALTIVEC_ARG_RETURN;
18886 else if (COMPLEX_MODE_P (mode) && targetm.calls.split_complex_arg)
18887 return rs6000_complex_function_value (mode);
18888 else if (TARGET_E500_DOUBLE && TARGET_HARD_FLOAT
18889 && (mode == DFmode || mode == DCmode))
18890 return spe_build_register_parallel (mode, GP_ARG_RETURN);
18892 regno = GP_ARG_RETURN;
18894 return gen_rtx_REG (mode, regno);
18897 /* Define the offset between two registers, FROM to be eliminated and its
18898 replacement TO, at the start of a routine. */
18900 rs6000_initial_elimination_offset (int from, int to)
18902 rs6000_stack_t *info = rs6000_stack_info ();
18903 HOST_WIDE_INT offset;
18905 if (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18906 offset = info->push_p ? 0 : -info->total_size;
18907 else if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18909 offset = info->push_p ? 0 : -info->total_size;
18910 if (FRAME_GROWS_DOWNWARD)
18911 offset += info->fixed_size + info->vars_size + info->parm_size;
18913 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18914 offset = FRAME_GROWS_DOWNWARD
18915 ? info->fixed_size + info->vars_size + info->parm_size
18917 else if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
18918 offset = info->total_size;
18919 else if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
18920 offset = info->push_p ? info->total_size : 0;
18921 else if (from == RS6000_PIC_OFFSET_TABLE_REGNUM)
18924 gcc_unreachable ();
18929 /* Return true if TYPE is a SPE or AltiVec opaque type. */
18932 rs6000_is_opaque_type (tree type)
18934 return (type == opaque_V2SI_type_node
18935 || type == opaque_V2SF_type_node
18936 || type == opaque_p_V2SI_type_node
18937 || type == opaque_V4SI_type_node);
18941 rs6000_dwarf_register_span (rtx reg)
18946 && (SPE_VECTOR_MODE (GET_MODE (reg))
18947 || (TARGET_E500_DOUBLE && GET_MODE (reg) == DFmode)))
18952 regno = REGNO (reg);
18954 /* The duality of the SPE register size wreaks all kinds of havoc.
18955 This is a way of distinguishing r0 in 32-bits from r0 in
18958 gen_rtx_PARALLEL (VOIDmode,
18961 gen_rtx_REG (SImode, regno + 1200),
18962 gen_rtx_REG (SImode, regno))
18964 gen_rtx_REG (SImode, regno),
18965 gen_rtx_REG (SImode, regno + 1200)));
18968 /* Map internal gcc register numbers to DWARF2 register numbers. */
18971 rs6000_dbx_register_number (unsigned int regno)
18973 if (regno <= 63 || write_symbols != DWARF2_DEBUG)
18975 if (regno == MQ_REGNO)
18977 if (regno == LINK_REGISTER_REGNUM)
18979 if (regno == COUNT_REGISTER_REGNUM)
18981 if (CR_REGNO_P (regno))
18982 return regno - CR0_REGNO + 86;
18983 if (regno == XER_REGNO)
18985 if (ALTIVEC_REGNO_P (regno))
18986 return regno - FIRST_ALTIVEC_REGNO + 1124;
18987 if (regno == VRSAVE_REGNO)
18989 if (regno == VSCR_REGNO)
18991 if (regno == SPE_ACC_REGNO)
18993 if (regno == SPEFSCR_REGNO)
18995 /* SPE high reg number. We get these values of regno from
18996 rs6000_dwarf_register_span. */
18997 gcc_assert (regno >= 1200 && regno < 1232);
19001 /* target hook eh_return_filter_mode */
19002 static enum machine_mode
19003 rs6000_eh_return_filter_mode (void)
19005 return TARGET_32BIT ? SImode : word_mode;
19008 /* Target hook for vector_mode_supported_p. */
19010 rs6000_vector_mode_supported_p (enum machine_mode mode)
19013 if (TARGET_SPE && SPE_VECTOR_MODE (mode))
19016 else if (TARGET_ALTIVEC && ALTIVEC_VECTOR_MODE (mode))
19023 /* Target hook for invalid_arg_for_unprototyped_fn. */
19024 static const char *
19025 invalid_arg_for_unprototyped_fn (tree typelist, tree funcdecl, tree val)
19027 return (!rs6000_darwin64_abi
19029 && TREE_CODE (TREE_TYPE (val)) == VECTOR_TYPE
19030 && (funcdecl == NULL_TREE
19031 || (TREE_CODE (funcdecl) == FUNCTION_DECL
19032 && DECL_BUILT_IN_CLASS (funcdecl) != BUILT_IN_MD)))
19033 ? N_("AltiVec argument passed to unprototyped function")
19037 /* For TARGET_SECURE_PLT 32-bit PIC code we can save PIC register
19038 setup by using __stack_chk_fail_local hidden function instead of
19039 calling __stack_chk_fail directly. Otherwise it is better to call
19040 __stack_chk_fail directly. */
19043 rs6000_stack_protect_fail (void)
19045 return (DEFAULT_ABI == ABI_V4 && TARGET_SECURE_PLT && flag_pic)
19046 ? default_hidden_stack_protect_fail ()
19047 : default_external_stack_protect_fail ();
19050 #include "gt-rs6000.h"