1 ;; Predicate definitions for POWER and PowerPC.
2 ;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc.
4 ;; This file is part of GCC.
6 ;; GCC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 3, or (at your option)
11 ;; GCC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GCC; see the file COPYING3. If not see
18 ;; <http://www.gnu.org/licenses/>.
20 ;; Return 1 for anything except PARALLEL.
21 (define_predicate "any_operand"
22 (match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem"))
24 ;; Return 1 for any PARALLEL.
25 (define_predicate "any_parallel_operand"
26 (match_code "parallel"))
28 ;; Return 1 if op is COUNT register.
29 (define_predicate "count_register_operand"
30 (and (match_code "reg")
31 (match_test "REGNO (op) == CTR_REGNO
32 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
34 ;; Return 1 if op is an Altivec register.
35 (define_predicate "altivec_register_operand"
36 (and (match_operand 0 "register_operand")
37 (match_test "GET_CODE (op) != REG
38 || ALTIVEC_REGNO_P (REGNO (op))
39 || REGNO (op) > LAST_VIRTUAL_REGISTER")))
41 ;; Return 1 if op is XER register.
42 (define_predicate "xer_operand"
43 (and (match_code "reg")
44 (match_test "XER_REGNO_P (REGNO (op))")))
46 ;; Return 1 if op is a signed 5-bit constant integer.
47 (define_predicate "s5bit_cint_operand"
48 (and (match_code "const_int")
49 (match_test "INTVAL (op) >= -16 && INTVAL (op) <= 15")))
51 ;; Return 1 if op is a unsigned 5-bit constant integer.
52 (define_predicate "u5bit_cint_operand"
53 (and (match_code "const_int")
54 (match_test "INTVAL (op) >= 0 && INTVAL (op) <= 31")))
56 ;; Return 1 if op is a signed 8-bit constant integer.
57 ;; Integer multiplication complete more quickly
58 (define_predicate "s8bit_cint_operand"
59 (and (match_code "const_int")
60 (match_test "INTVAL (op) >= -128 && INTVAL (op) <= 127")))
62 ;; Return 1 if op is a constant integer that can fit in a D field.
63 (define_predicate "short_cint_operand"
64 (and (match_code "const_int")
65 (match_test "satisfies_constraint_I (op)")))
67 ;; Return 1 if op is a constant integer that can fit in an unsigned D field.
68 (define_predicate "u_short_cint_operand"
69 (and (match_code "const_int")
70 (match_test "satisfies_constraint_K (op)")))
72 ;; Return 1 if op is a constant integer that cannot fit in a signed D field.
73 (define_predicate "non_short_cint_operand"
74 (and (match_code "const_int")
75 (match_test "(unsigned HOST_WIDE_INT)
76 (INTVAL (op) + 0x8000) >= 0x10000")))
78 ;; Return 1 if op is a positive constant integer that is an exact power of 2.
79 (define_predicate "exact_log2_cint_operand"
80 (and (match_code "const_int")
81 (match_test "INTVAL (op) > 0 && exact_log2 (INTVAL (op)) >= 0")))
83 ;; Return 1 if op is a register that is not special.
84 (define_predicate "gpc_reg_operand"
85 (and (match_operand 0 "register_operand")
86 (match_test "(GET_CODE (op) != REG
87 || (REGNO (op) >= ARG_POINTER_REGNUM
88 && !XER_REGNO_P (REGNO (op)))
89 || REGNO (op) < MQ_REGNO)
90 && !((TARGET_E500_DOUBLE || TARGET_SPE)
91 && invalid_e500_subreg (op, mode))")))
93 ;; Return 1 if op is a register that is a condition register field.
94 (define_predicate "cc_reg_operand"
95 (and (match_operand 0 "register_operand")
96 (match_test "GET_CODE (op) != REG
97 || REGNO (op) > LAST_VIRTUAL_REGISTER
98 || CR_REGNO_P (REGNO (op))")))
100 ;; Return 1 if op is a register that is a condition register field not cr0.
101 (define_predicate "cc_reg_not_cr0_operand"
102 (and (match_operand 0 "register_operand")
103 (match_test "GET_CODE (op) != REG
104 || REGNO (op) > LAST_VIRTUAL_REGISTER
105 || CR_REGNO_NOT_CR0_P (REGNO (op))")))
107 ;; Return 1 if op is a constant integer valid for D field
108 ;; or non-special register register.
109 (define_predicate "reg_or_short_operand"
110 (if_then_else (match_code "const_int")
111 (match_operand 0 "short_cint_operand")
112 (match_operand 0 "gpc_reg_operand")))
114 ;; Return 1 if op is a constant integer valid whose negation is valid for
115 ;; D field or non-special register register.
116 ;; Do not allow a constant zero because all patterns that call this
117 ;; predicate use "addic r1,r2,-const" to set carry when r2 is greater than
118 ;; or equal to const, which does not work for zero.
119 (define_predicate "reg_or_neg_short_operand"
120 (if_then_else (match_code "const_int")
121 (match_test "satisfies_constraint_P (op)
122 && INTVAL (op) != 0")
123 (match_operand 0 "gpc_reg_operand")))
125 ;; Return 1 if op is a constant integer valid for DS field
126 ;; or non-special register.
127 (define_predicate "reg_or_aligned_short_operand"
128 (if_then_else (match_code "const_int")
129 (and (match_operand 0 "short_cint_operand")
130 (match_test "!(INTVAL (op) & 3)"))
131 (match_operand 0 "gpc_reg_operand")))
133 ;; Return 1 if op is a constant integer whose high-order 16 bits are zero
134 ;; or non-special register.
135 (define_predicate "reg_or_u_short_operand"
136 (if_then_else (match_code "const_int")
137 (match_operand 0 "u_short_cint_operand")
138 (match_operand 0 "gpc_reg_operand")))
140 ;; Return 1 if op is any constant integer
141 ;; or non-special register.
142 (define_predicate "reg_or_cint_operand"
143 (ior (match_code "const_int")
144 (match_operand 0 "gpc_reg_operand")))
146 ;; Return 1 if op is a constant integer valid for addition
147 ;; or non-special register.
148 (define_predicate "reg_or_add_cint_operand"
149 (if_then_else (match_code "const_int")
150 (match_test "(HOST_BITS_PER_WIDE_INT == 32
151 && (mode == SImode || INTVAL (op) < 0x7fff8000))
152 || ((unsigned HOST_WIDE_INT) (INTVAL (op) + 0x80008000)
153 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
154 (match_operand 0 "gpc_reg_operand")))
156 ;; Return 1 if op is a constant integer valid for subtraction
157 ;; or non-special register.
158 (define_predicate "reg_or_sub_cint_operand"
159 (if_then_else (match_code "const_int")
160 (match_test "(HOST_BITS_PER_WIDE_INT == 32
161 && (mode == SImode || - INTVAL (op) < 0x7fff8000))
162 || ((unsigned HOST_WIDE_INT) (- INTVAL (op)
164 ? 0x80000000 : 0x80008000))
165 < (unsigned HOST_WIDE_INT) 0x100000000ll)")
166 (match_operand 0 "gpc_reg_operand")))
168 ;; Return 1 if op is any 32-bit unsigned constant integer
169 ;; or non-special register.
170 (define_predicate "reg_or_logical_cint_operand"
171 (if_then_else (match_code "const_int")
172 (match_test "(GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
174 || ((INTVAL (op) & GET_MODE_MASK (mode)
175 & (~ (unsigned HOST_WIDE_INT) 0xffffffff)) == 0)")
176 (if_then_else (match_code "const_double")
177 (match_test "GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
179 && CONST_DOUBLE_HIGH (op) == 0")
180 (match_operand 0 "gpc_reg_operand"))))
182 ;; Return 1 if operand is a CONST_DOUBLE that can be set in a register
183 ;; with no more than one instruction per word.
184 (define_predicate "easy_fp_constant"
185 (match_code "const_double")
190 if (GET_MODE (op) != mode
191 || (!SCALAR_FLOAT_MODE_P (mode) && mode != DImode))
194 /* Consider all constants with -msoft-float to be easy. */
195 if ((TARGET_SOFT_FLOAT || TARGET_E500_SINGLE
196 || (TARGET_HARD_FLOAT && (TARGET_SINGLE_FLOAT && ! TARGET_DOUBLE_FLOAT)))
200 if (DECIMAL_FLOAT_MODE_P (mode))
203 /* If we are using V.4 style PIC, consider all constants to be hard. */
204 if (flag_pic && DEFAULT_ABI == ABI_V4)
207 #ifdef TARGET_RELOCATABLE
208 /* Similarly if we are using -mrelocatable, consider all constants
210 if (TARGET_RELOCATABLE)
217 if (TARGET_E500_DOUBLE)
220 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
221 REAL_VALUE_TO_TARGET_LONG_DOUBLE (rv, k);
223 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
224 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1
225 && num_insns_constant_wide ((HOST_WIDE_INT) k[2]) == 1
226 && num_insns_constant_wide ((HOST_WIDE_INT) k[3]) == 1);
229 /* Force constants to memory before reload to utilize
230 compress_float_constant.
231 Avoid this when flag_unsafe_math_optimizations is enabled
232 because RDIV division to reciprocal optimization is not able
233 to regenerate the division. */
234 if (TARGET_E500_DOUBLE
235 || (!reload_in_progress && !reload_completed
236 && !flag_unsafe_math_optimizations))
239 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
240 REAL_VALUE_TO_TARGET_DOUBLE (rv, k);
242 return (num_insns_constant_wide ((HOST_WIDE_INT) k[0]) == 1
243 && num_insns_constant_wide ((HOST_WIDE_INT) k[1]) == 1);
246 /* The constant 0.f is easy. */
247 if (op == CONST0_RTX (SFmode))
250 /* Force constants to memory before reload to utilize
251 compress_float_constant.
252 Avoid this when flag_unsafe_math_optimizations is enabled
253 because RDIV division to reciprocal optimization is not able
254 to regenerate the division. */
255 if (!reload_in_progress && !reload_completed
256 && !flag_unsafe_math_optimizations)
259 REAL_VALUE_FROM_CONST_DOUBLE (rv, op);
260 REAL_VALUE_TO_TARGET_SINGLE (rv, k[0]);
262 return num_insns_constant_wide (k[0]) == 1;
265 return ((TARGET_POWERPC64
266 && GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_LOW (op) == 0)
267 || (num_insns_constant (op, DImode) <= 2));
277 ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
278 ;; vector register without using memory.
279 (define_predicate "easy_vector_constant"
280 (match_code "const_vector")
282 /* As the paired vectors are actually FPRs it seems that there is
283 no easy way to load a CONST_VECTOR without using memory. */
284 if (TARGET_PAIRED_FLOAT)
287 if (ALTIVEC_VECTOR_MODE (mode))
289 if (zero_constant (op, mode))
291 return easy_altivec_constant (op, mode);
294 if (SPE_VECTOR_MODE (mode))
297 if (zero_constant (op, mode))
299 if (GET_MODE_CLASS (mode) != MODE_VECTOR_INT)
302 /* Limit SPE vectors to 15 bits signed. These we can generate with:
307 I don't know how efficient it would be to allow bigger constants,
308 considering we'll have an extra 'ori' for every 'li'. I doubt 5
309 instructions is better than a 64-bit memory load, but I don't
310 have the e500 timing specs. */
311 if (mode == V2SImode)
313 cst = INTVAL (CONST_VECTOR_ELT (op, 0));
314 cst2 = INTVAL (CONST_VECTOR_ELT (op, 1));
315 return cst >= -0x7fff && cst <= 0x7fff
316 && cst2 >= -0x7fff && cst2 <= 0x7fff;
323 ;; Same as easy_vector_constant but only for EASY_VECTOR_15_ADD_SELF.
324 (define_predicate "easy_vector_constant_add_self"
325 (and (match_code "const_vector")
326 (and (match_test "TARGET_ALTIVEC")
327 (match_test "easy_altivec_constant (op, mode)")))
329 HOST_WIDE_INT val = const_vector_elt_as_int (op, GET_MODE_NUNITS (mode) - 1);
330 val = ((val & 0xff) ^ 0x80) - 0x80;
331 return EASY_VECTOR_15_ADD_SELF (val);
334 ;; Return 1 if operand is constant zero (scalars and vectors).
335 (define_predicate "zero_constant"
336 (and (match_code "const_int,const_double,const_vector")
337 (match_test "op == CONST0_RTX (mode)")))
339 ;; Return 1 if operand is 0.0.
340 ;; or non-special register register field no cr0
341 (define_predicate "zero_fp_constant"
342 (and (match_code "const_double")
343 (match_test "SCALAR_FLOAT_MODE_P (mode)
344 && op == CONST0_RTX (mode)")))
346 ;; Return 1 if the operand is in volatile memory. Note that during the
347 ;; RTL generation phase, memory_operand does not return TRUE for volatile
348 ;; memory references. So this function allows us to recognize volatile
349 ;; references where it's safe.
350 (define_predicate "volatile_mem_operand"
351 (and (and (match_code "mem")
352 (match_test "MEM_VOLATILE_P (op)"))
353 (if_then_else (match_test "reload_completed")
354 (match_operand 0 "memory_operand")
355 (if_then_else (match_test "reload_in_progress")
356 (match_test "strict_memory_address_p (mode, XEXP (op, 0))")
357 (match_test "memory_address_p (mode, XEXP (op, 0))")))))
359 ;; Return 1 if the operand is an offsettable memory operand.
360 (define_predicate "offsettable_mem_operand"
361 (and (match_operand 0 "memory_operand")
362 (match_test "GET_CODE (XEXP (op, 0)) != PRE_INC
363 && GET_CODE (XEXP (op, 0)) != PRE_DEC
364 && GET_CODE (XEXP (op, 0)) != PRE_MODIFY")))
366 ;; Return 1 if the operand is a memory operand with an address divisible by 4
367 (define_predicate "word_offset_memref_operand"
368 (and (match_operand 0 "memory_operand")
369 (match_test "GET_CODE (XEXP (op, 0)) != PLUS
370 || ! REG_P (XEXP (XEXP (op, 0), 0))
371 || GET_CODE (XEXP (XEXP (op, 0), 1)) != CONST_INT
372 || INTVAL (XEXP (XEXP (op, 0), 1)) % 4 == 0")))
374 ;; Return 1 if the operand is an indexed or indirect memory operand.
375 (define_predicate "indexed_or_indirect_operand"
380 && ALTIVEC_VECTOR_MODE (mode)
381 && GET_CODE (op) == AND
382 && GET_CODE (XEXP (op, 1)) == CONST_INT
383 && INTVAL (XEXP (op, 1)) == -16)
386 return indexed_or_indirect_address (op, mode);
389 ;; Return 1 if the operand is an indexed or indirect address.
390 (define_special_predicate "indexed_or_indirect_address"
391 (and (match_test "REG_P (op)
392 || (GET_CODE (op) == PLUS
393 /* Omit testing REG_P (XEXP (op, 0)). */
394 && REG_P (XEXP (op, 1)))")
395 (match_operand 0 "address_operand")))
397 ;; Used for the destination of the fix_truncdfsi2 expander.
398 ;; If stfiwx will be used, the result goes to memory; otherwise,
399 ;; we're going to emit a store and a load of a subreg, so the dest is a
401 (define_predicate "fix_trunc_dest_operand"
402 (if_then_else (match_test "! TARGET_E500_DOUBLE && TARGET_PPC_GFXOPT")
403 (match_operand 0 "memory_operand")
404 (match_operand 0 "gpc_reg_operand")))
406 ;; Return 1 if the operand is either a non-special register or can be used
407 ;; as the operand of a `mode' add insn.
408 (define_predicate "add_operand"
409 (if_then_else (match_code "const_int")
410 (match_test "satisfies_constraint_I (op)
411 || satisfies_constraint_L (op)")
412 (match_operand 0 "gpc_reg_operand")))
414 ;; Return 1 if OP is a constant but not a valid add_operand.
415 (define_predicate "non_add_cint_operand"
416 (and (match_code "const_int")
417 (match_test "!satisfies_constraint_I (op)
418 && !satisfies_constraint_L (op)")))
420 ;; Return 1 if the operand is a constant that can be used as the operand
422 (define_predicate "logical_const_operand"
423 (match_code "const_int,const_double")
425 HOST_WIDE_INT opl, oph;
427 if (GET_CODE (op) == CONST_INT)
429 opl = INTVAL (op) & GET_MODE_MASK (mode);
431 if (HOST_BITS_PER_WIDE_INT <= 32
432 && GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT && opl < 0)
435 else if (GET_CODE (op) == CONST_DOUBLE)
437 gcc_assert (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT);
439 opl = CONST_DOUBLE_LOW (op);
440 oph = CONST_DOUBLE_HIGH (op);
447 return ((opl & ~ (unsigned HOST_WIDE_INT) 0xffff) == 0
448 || (opl & ~ (unsigned HOST_WIDE_INT) 0xffff0000) == 0);
451 ;; Return 1 if the operand is a non-special register or a constant that
452 ;; can be used as the operand of an OR or XOR.
453 (define_predicate "logical_operand"
454 (ior (match_operand 0 "gpc_reg_operand")
455 (match_operand 0 "logical_const_operand")))
457 ;; Return 1 if op is a constant that is not a logical operand, but could
458 ;; be split into one.
459 (define_predicate "non_logical_cint_operand"
460 (and (match_code "const_int,const_double")
461 (and (not (match_operand 0 "logical_operand"))
462 (match_operand 0 "reg_or_logical_cint_operand"))))
464 ;; Return 1 if op is a constant that can be encoded in a 32-bit mask,
465 ;; suitable for use with rlwinm (no more than two 1->0 or 0->1
466 ;; transitions). Reject all ones and all zeros, since these should have
467 ;; been optimized away and confuse the making of MB and ME.
468 (define_predicate "mask_operand"
469 (match_code "const_int")
471 HOST_WIDE_INT c, lsb;
475 if (TARGET_POWERPC64)
477 /* Fail if the mask is not 32-bit. */
478 if (mode == DImode && (c & ~(unsigned HOST_WIDE_INT) 0xffffffff) != 0)
481 /* Fail if the mask wraps around because the upper 32-bits of the
482 mask will all be 1s, contrary to GCC's internal view. */
483 if ((c & 0x80000001) == 0x80000001)
487 /* We don't change the number of transitions by inverting,
488 so make sure we start with the LS bit zero. */
492 /* Reject all zeros or all ones. */
496 /* Find the first transition. */
499 /* Invert to look for a second transition. */
502 /* Erase first transition. */
505 /* Find the second transition (if any). */
508 /* Match if all the bits above are 1's (or c is zero). */
512 ;; Return 1 for the PowerPC64 rlwinm corner case.
513 (define_predicate "mask_operand_wrap"
514 (match_code "const_int")
516 HOST_WIDE_INT c, lsb;
520 if ((c & 0x80000001) != 0x80000001)
534 ;; Return 1 if the operand is a constant that is a PowerPC64 mask
535 ;; suitable for use with rldicl or rldicr (no more than one 1->0 or 0->1
536 ;; transition). Reject all zeros, since zero should have been
537 ;; optimized away and confuses the making of MB and ME.
538 (define_predicate "mask64_operand"
539 (match_code "const_int")
541 HOST_WIDE_INT c, lsb;
545 /* Reject all zeros. */
549 /* We don't change the number of transitions by inverting,
550 so make sure we start with the LS bit zero. */
554 /* Find the first transition. */
557 /* Match if all the bits above are 1's (or c is zero). */
561 ;; Like mask64_operand, but allow up to three transitions. This
562 ;; predicate is used by insn patterns that generate two rldicl or
563 ;; rldicr machine insns.
564 (define_predicate "mask64_2_operand"
565 (match_code "const_int")
567 HOST_WIDE_INT c, lsb;
571 /* Disallow all zeros. */
575 /* We don't change the number of transitions by inverting,
576 so make sure we start with the LS bit zero. */
580 /* Find the first transition. */
583 /* Invert to look for a second transition. */
586 /* Erase first transition. */
589 /* Find the second transition. */
592 /* Invert to look for a third transition. */
595 /* Erase second transition. */
598 /* Find the third transition (if any). */
601 /* Match if all the bits above are 1's (or c is zero). */
605 ;; Like and_operand, but also match constants that can be implemented
606 ;; with two rldicl or rldicr insns.
607 (define_predicate "and64_2_operand"
608 (ior (match_operand 0 "mask64_2_operand")
609 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
610 (match_operand 0 "gpc_reg_operand")
611 (match_operand 0 "logical_operand"))))
613 ;; Return 1 if the operand is either a non-special register or a
614 ;; constant that can be used as the operand of a logical AND.
615 (define_predicate "and_operand"
616 (ior (match_operand 0 "mask_operand")
617 (ior (and (match_test "TARGET_POWERPC64 && mode == DImode")
618 (match_operand 0 "mask64_operand"))
619 (if_then_else (match_test "fixed_regs[CR0_REGNO]")
620 (match_operand 0 "gpc_reg_operand")
621 (match_operand 0 "logical_operand")))))
623 ;; Return 1 if the operand is either a logical operand or a short cint operand.
624 (define_predicate "scc_eq_operand"
625 (ior (match_operand 0 "logical_operand")
626 (match_operand 0 "short_cint_operand")))
628 ;; Return 1 if the operand is a general non-special register or memory operand.
629 (define_predicate "reg_or_mem_operand"
630 (ior (match_operand 0 "memory_operand")
631 (ior (and (match_code "mem")
632 (match_test "macho_lo_sum_memory_operand (op, mode)"))
633 (ior (match_operand 0 "volatile_mem_operand")
634 (match_operand 0 "gpc_reg_operand")))))
636 ;; Return 1 if the operand is either an easy FP constant or memory or reg.
637 (define_predicate "reg_or_none500mem_operand"
638 (if_then_else (match_code "mem")
639 (and (match_test "!TARGET_E500_DOUBLE")
640 (ior (match_operand 0 "memory_operand")
641 (ior (match_test "macho_lo_sum_memory_operand (op, mode)")
642 (match_operand 0 "volatile_mem_operand"))))
643 (match_operand 0 "gpc_reg_operand")))
645 ;; Return 1 if the operand is CONST_DOUBLE 0, register or memory operand.
646 (define_predicate "zero_reg_mem_operand"
647 (ior (match_operand 0 "zero_fp_constant")
648 (match_operand 0 "reg_or_mem_operand")))
650 ;; Return 1 if the operand is a general register or memory operand without
651 ;; pre_inc or pre_dec or pre_modify, which produces invalid form of PowerPC
653 (define_predicate "lwa_operand"
654 (match_code "reg,subreg,mem")
658 if (reload_completed && GET_CODE (inner) == SUBREG)
659 inner = SUBREG_REG (inner);
661 return gpc_reg_operand (inner, mode)
662 || (memory_operand (inner, mode)
663 && GET_CODE (XEXP (inner, 0)) != PRE_INC
664 && GET_CODE (XEXP (inner, 0)) != PRE_DEC
665 && (GET_CODE (XEXP (inner, 0)) != PRE_MODIFY
666 || legitimate_indexed_address_p (XEXP (XEXP (inner, 0), 1), 0))
667 && (GET_CODE (XEXP (inner, 0)) != PLUS
668 || GET_CODE (XEXP (XEXP (inner, 0), 1)) != CONST_INT
669 || INTVAL (XEXP (XEXP (inner, 0), 1)) % 4 == 0));
672 ;; Return 1 if the operand, used inside a MEM, is a SYMBOL_REF.
673 (define_predicate "symbol_ref_operand"
674 (and (match_code "symbol_ref")
675 (match_test "(mode == VOIDmode || GET_MODE (op) == mode)
676 && (DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))")))
678 ;; Return 1 if op is an operand that can be loaded via the GOT.
679 ;; or non-special register register field no cr0
680 (define_predicate "got_operand"
681 (match_code "symbol_ref,const,label_ref"))
683 ;; Return 1 if op is a simple reference that can be loaded via the GOT,
684 ;; excluding labels involving addition.
685 (define_predicate "got_no_const_operand"
686 (match_code "symbol_ref,label_ref"))
688 ;; Return 1 if op is a SYMBOL_REF for a TLS symbol.
689 (define_predicate "rs6000_tls_symbol_ref"
690 (and (match_code "symbol_ref")
691 (match_test "RS6000_SYMBOL_REF_TLS_P (op)")))
693 ;; Return 1 if the operand, used inside a MEM, is a valid first argument
694 ;; to CALL. This is a SYMBOL_REF, a pseudo-register, LR or CTR.
695 (define_predicate "call_operand"
696 (if_then_else (match_code "reg")
697 (match_test "REGNO (op) == LR_REGNO
698 || REGNO (op) == CTR_REGNO
699 || REGNO (op) >= FIRST_PSEUDO_REGISTER")
700 (match_code "symbol_ref")))
702 ;; Return 1 if the operand is a SYMBOL_REF for a function known to be in
704 (define_predicate "current_file_function_operand"
705 (and (match_code "symbol_ref")
706 (match_test "(DEFAULT_ABI != ABI_AIX || SYMBOL_REF_FUNCTION_P (op))
707 && ((SYMBOL_REF_LOCAL_P (op)
708 && (DEFAULT_ABI != ABI_AIX
709 || !SYMBOL_REF_EXTERNAL_P (op)))
710 || (op == XEXP (DECL_RTL (current_function_decl),
713 ;; Return 1 if this operand is a valid input for a move insn.
714 (define_predicate "input_operand"
715 (match_code "label_ref,symbol_ref,const,high,reg,subreg,mem,
716 const_double,const_vector,const_int,plus")
718 /* Memory is always valid. */
719 if (memory_operand (op, mode))
722 /* For floating-point, easy constants are valid. */
723 if (SCALAR_FLOAT_MODE_P (mode)
725 && easy_fp_constant (op, mode))
728 /* Allow any integer constant. */
729 if (GET_MODE_CLASS (mode) == MODE_INT
730 && (GET_CODE (op) == CONST_INT
731 || GET_CODE (op) == CONST_DOUBLE))
734 /* Allow easy vector constants. */
735 if (GET_CODE (op) == CONST_VECTOR
736 && easy_vector_constant (op, mode))
739 /* Do not allow invalid E500 subregs. */
740 if ((TARGET_E500_DOUBLE || TARGET_SPE)
741 && GET_CODE (op) == SUBREG
742 && invalid_e500_subreg (op, mode))
745 /* For floating-point or multi-word mode, the only remaining valid type
747 if (SCALAR_FLOAT_MODE_P (mode)
748 || GET_MODE_SIZE (mode) > UNITS_PER_WORD)
749 return register_operand (op, mode);
751 /* The only cases left are integral modes one word or smaller (we
752 do not get called for MODE_CC values). These can be in any
754 if (register_operand (op, mode))
757 /* A SYMBOL_REF referring to the TOC is valid. */
758 if (legitimate_constant_pool_address_p (op))
761 /* A constant pool expression (relative to the TOC) is valid */
762 if (toc_relative_expr_p (op))
765 /* V.4 allows SYMBOL_REFs and CONSTs that are in the small data region
767 if (DEFAULT_ABI == ABI_V4
768 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)
769 && small_data_operand (op, Pmode))
775 ;; Return true if OP is an invalid SUBREG operation on the e500.
776 (define_predicate "rs6000_nonimmediate_operand"
777 (match_code "reg,subreg,mem")
779 if ((TARGET_E500_DOUBLE || TARGET_SPE)
780 && GET_CODE (op) == SUBREG
781 && invalid_e500_subreg (op, mode))
784 return nonimmediate_operand (op, mode);
787 ;; Return true if operand is boolean operator.
788 (define_predicate "boolean_operator"
789 (match_code "and,ior,xor"))
791 ;; Return true if operand is OR-form of boolean operator.
792 (define_predicate "boolean_or_operator"
793 (match_code "ior,xor"))
795 ;; Return true if operand is an equality operator.
796 (define_special_predicate "equality_operator"
797 (match_code "eq,ne"))
799 ;; Return true if operand is MIN or MAX operator.
800 (define_predicate "min_max_operator"
801 (match_code "smin,smax,umin,umax"))
803 ;; Return 1 if OP is a comparison operation that is valid for a branch
804 ;; instruction. We check the opcode against the mode of the CC value.
805 ;; validate_condition_mode is an assertion.
806 (define_predicate "branch_comparison_operator"
807 (and (match_operand 0 "comparison_operator")
808 (and (match_test "GET_MODE_CLASS (GET_MODE (XEXP (op, 0))) == MODE_CC")
809 (match_test "validate_condition_mode (GET_CODE (op),
810 GET_MODE (XEXP (op, 0))),
813 ;; Return 1 if OP is a comparison operation that is valid for an SCC insn --
814 ;; it must be a positive comparison.
815 (define_predicate "scc_comparison_operator"
816 (and (match_operand 0 "branch_comparison_operator")
817 (match_code "eq,lt,gt,ltu,gtu,unordered")))
819 ;; Return 1 if OP is a comparison operation that is valid for a branch
820 ;; insn, which is true if the corresponding bit in the CC register is set.
821 (define_predicate "branch_positive_comparison_operator"
822 (and (match_operand 0 "branch_comparison_operator")
823 (match_code "eq,lt,gt,ltu,gtu,unordered")))
825 ;; Return 1 is OP is a comparison operation that is valid for a trap insn.
826 (define_predicate "trap_comparison_operator"
827 (and (match_operand 0 "comparison_operator")
828 (match_code "eq,ne,le,lt,ge,gt,leu,ltu,geu,gtu")))
830 ;; Return 1 if OP is a load multiple operation, known to be a PARALLEL.
831 (define_predicate "load_multiple_operation"
832 (match_code "parallel")
834 int count = XVECLEN (op, 0);
835 unsigned int dest_regno;
839 /* Perform a quick check so we don't blow up below. */
841 || GET_CODE (XVECEXP (op, 0, 0)) != SET
842 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
843 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
846 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
847 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
849 for (i = 1; i < count; i++)
851 rtx elt = XVECEXP (op, 0, i);
853 if (GET_CODE (elt) != SET
854 || GET_CODE (SET_DEST (elt)) != REG
855 || GET_MODE (SET_DEST (elt)) != SImode
856 || REGNO (SET_DEST (elt)) != dest_regno + i
857 || GET_CODE (SET_SRC (elt)) != MEM
858 || GET_MODE (SET_SRC (elt)) != SImode
859 || GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
860 || ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
861 || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
862 || INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
869 ;; Return 1 if OP is a store multiple operation, known to be a PARALLEL.
870 ;; The second vector element is a CLOBBER.
871 (define_predicate "store_multiple_operation"
872 (match_code "parallel")
874 int count = XVECLEN (op, 0) - 1;
875 unsigned int src_regno;
879 /* Perform a quick check so we don't blow up below. */
881 || GET_CODE (XVECEXP (op, 0, 0)) != SET
882 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
883 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
886 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
887 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
889 for (i = 1; i < count; i++)
891 rtx elt = XVECEXP (op, 0, i + 1);
893 if (GET_CODE (elt) != SET
894 || GET_CODE (SET_SRC (elt)) != REG
895 || GET_MODE (SET_SRC (elt)) != SImode
896 || REGNO (SET_SRC (elt)) != src_regno + i
897 || GET_CODE (SET_DEST (elt)) != MEM
898 || GET_MODE (SET_DEST (elt)) != SImode
899 || GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
900 || ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
901 || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
902 || INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
909 ;; Return 1 if OP is valid for a save_world call in prologue, known to be
911 (define_predicate "save_world_operation"
912 (match_code "parallel")
917 int count = XVECLEN (op, 0);
923 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
924 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
927 for (i=1; i <= 18; i++)
929 elt = XVECEXP (op, 0, index++);
930 if (GET_CODE (elt) != SET
931 || GET_CODE (SET_DEST (elt)) != MEM
932 || ! memory_operand (SET_DEST (elt), DFmode)
933 || GET_CODE (SET_SRC (elt)) != REG
934 || GET_MODE (SET_SRC (elt)) != DFmode)
938 for (i=1; i <= 12; i++)
940 elt = XVECEXP (op, 0, index++);
941 if (GET_CODE (elt) != SET
942 || GET_CODE (SET_DEST (elt)) != MEM
943 || GET_CODE (SET_SRC (elt)) != REG
944 || GET_MODE (SET_SRC (elt)) != V4SImode)
948 for (i=1; i <= 19; i++)
950 elt = XVECEXP (op, 0, index++);
951 if (GET_CODE (elt) != SET
952 || GET_CODE (SET_DEST (elt)) != MEM
953 || ! memory_operand (SET_DEST (elt), Pmode)
954 || GET_CODE (SET_SRC (elt)) != REG
955 || GET_MODE (SET_SRC (elt)) != Pmode)
959 elt = XVECEXP (op, 0, index++);
960 if (GET_CODE (elt) != SET
961 || GET_CODE (SET_DEST (elt)) != MEM
962 || ! memory_operand (SET_DEST (elt), Pmode)
963 || GET_CODE (SET_SRC (elt)) != REG
964 || REGNO (SET_SRC (elt)) != CR2_REGNO
965 || GET_MODE (SET_SRC (elt)) != Pmode)
968 if (GET_CODE (XVECEXP (op, 0, index++)) != SET
969 || GET_CODE (XVECEXP (op, 0, index++)) != SET)
974 ;; Return 1 if OP is valid for a restore_world call in epilogue, known to be
976 (define_predicate "restore_world_operation"
977 (match_code "parallel")
982 int count = XVECLEN (op, 0);
988 if (GET_CODE (XVECEXP (op, 0, index++)) != RETURN
989 || GET_CODE (XVECEXP (op, 0, index++)) != USE
990 || GET_CODE (XVECEXP (op, 0, index++)) != USE
991 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER)
994 elt = XVECEXP (op, 0, index++);
995 if (GET_CODE (elt) != SET
996 || GET_CODE (SET_SRC (elt)) != MEM
997 || ! memory_operand (SET_SRC (elt), Pmode)
998 || GET_CODE (SET_DEST (elt)) != REG
999 || REGNO (SET_DEST (elt)) != CR2_REGNO
1000 || GET_MODE (SET_DEST (elt)) != Pmode)
1003 for (i=1; i <= 19; i++)
1005 elt = XVECEXP (op, 0, index++);
1006 if (GET_CODE (elt) != SET
1007 || GET_CODE (SET_SRC (elt)) != MEM
1008 || ! memory_operand (SET_SRC (elt), Pmode)
1009 || GET_CODE (SET_DEST (elt)) != REG
1010 || GET_MODE (SET_DEST (elt)) != Pmode)
1014 for (i=1; i <= 12; i++)
1016 elt = XVECEXP (op, 0, index++);
1017 if (GET_CODE (elt) != SET
1018 || GET_CODE (SET_SRC (elt)) != MEM
1019 || GET_CODE (SET_DEST (elt)) != REG
1020 || GET_MODE (SET_DEST (elt)) != V4SImode)
1024 for (i=1; i <= 18; i++)
1026 elt = XVECEXP (op, 0, index++);
1027 if (GET_CODE (elt) != SET
1028 || GET_CODE (SET_SRC (elt)) != MEM
1029 || ! memory_operand (SET_SRC (elt), DFmode)
1030 || GET_CODE (SET_DEST (elt)) != REG
1031 || GET_MODE (SET_DEST (elt)) != DFmode)
1035 if (GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1036 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1037 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1038 || GET_CODE (XVECEXP (op, 0, index++)) != CLOBBER
1039 || GET_CODE (XVECEXP (op, 0, index++)) != USE)
1044 ;; Return 1 if OP is valid for a vrsave call, known to be a PARALLEL.
1045 (define_predicate "vrsave_operation"
1046 (match_code "parallel")
1048 int count = XVECLEN (op, 0);
1049 unsigned int dest_regno, src_regno;
1053 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1054 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1055 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC_VOLATILE
1056 || XINT (SET_SRC (XVECEXP (op, 0, 0)), 1) != UNSPECV_SET_VRSAVE)
1059 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1060 src_regno = REGNO (XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 1));
1062 if (dest_regno != VRSAVE_REGNO || src_regno != VRSAVE_REGNO)
1065 for (i = 1; i < count; i++)
1067 rtx elt = XVECEXP (op, 0, i);
1069 if (GET_CODE (elt) != CLOBBER
1070 && GET_CODE (elt) != SET)
1077 ;; Return 1 if OP is valid for mfcr insn, known to be a PARALLEL.
1078 (define_predicate "mfcr_operation"
1079 (match_code "parallel")
1081 int count = XVECLEN (op, 0);
1084 /* Perform a quick check so we don't blow up below. */
1086 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1087 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1088 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1091 for (i = 0; i < count; i++)
1093 rtx exp = XVECEXP (op, 0, i);
1098 src_reg = XVECEXP (SET_SRC (exp), 0, 0);
1100 if (GET_CODE (src_reg) != REG
1101 || GET_MODE (src_reg) != CCmode
1102 || ! CR_REGNO_P (REGNO (src_reg)))
1105 if (GET_CODE (exp) != SET
1106 || GET_CODE (SET_DEST (exp)) != REG
1107 || GET_MODE (SET_DEST (exp)) != SImode
1108 || ! INT_REGNO_P (REGNO (SET_DEST (exp))))
1110 unspec = SET_SRC (exp);
1111 maskval = 1 << (MAX_CR_REGNO - REGNO (src_reg));
1113 if (GET_CODE (unspec) != UNSPEC
1114 || XINT (unspec, 1) != UNSPEC_MOVESI_FROM_CR
1115 || XVECLEN (unspec, 0) != 2
1116 || XVECEXP (unspec, 0, 0) != src_reg
1117 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1118 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1124 ;; Return 1 if OP is valid for mtcrf insn, known to be a PARALLEL.
1125 (define_predicate "mtcrf_operation"
1126 (match_code "parallel")
1128 int count = XVECLEN (op, 0);
1132 /* Perform a quick check so we don't blow up below. */
1134 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1135 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != UNSPEC
1136 || XVECLEN (SET_SRC (XVECEXP (op, 0, 0)), 0) != 2)
1138 src_reg = XVECEXP (SET_SRC (XVECEXP (op, 0, 0)), 0, 0);
1140 if (GET_CODE (src_reg) != REG
1141 || GET_MODE (src_reg) != SImode
1142 || ! INT_REGNO_P (REGNO (src_reg)))
1145 for (i = 0; i < count; i++)
1147 rtx exp = XVECEXP (op, 0, i);
1151 if (GET_CODE (exp) != SET
1152 || GET_CODE (SET_DEST (exp)) != REG
1153 || GET_MODE (SET_DEST (exp)) != CCmode
1154 || ! CR_REGNO_P (REGNO (SET_DEST (exp))))
1156 unspec = SET_SRC (exp);
1157 maskval = 1 << (MAX_CR_REGNO - REGNO (SET_DEST (exp)));
1159 if (GET_CODE (unspec) != UNSPEC
1160 || XINT (unspec, 1) != UNSPEC_MOVESI_TO_CR
1161 || XVECLEN (unspec, 0) != 2
1162 || XVECEXP (unspec, 0, 0) != src_reg
1163 || GET_CODE (XVECEXP (unspec, 0, 1)) != CONST_INT
1164 || INTVAL (XVECEXP (unspec, 0, 1)) != maskval)
1170 ;; Return 1 if OP is valid for lmw insn, known to be a PARALLEL.
1171 (define_predicate "lmw_operation"
1172 (match_code "parallel")
1174 int count = XVECLEN (op, 0);
1175 unsigned int dest_regno;
1177 unsigned int base_regno;
1178 HOST_WIDE_INT offset;
1181 /* Perform a quick check so we don't blow up below. */
1183 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1184 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
1185 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
1188 dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
1189 src_addr = XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0);
1192 || count != 32 - (int) dest_regno)
1195 if (legitimate_indirect_address_p (src_addr, 0))
1198 base_regno = REGNO (src_addr);
1199 if (base_regno == 0)
1202 else if (rs6000_legitimate_offset_address_p (SImode, src_addr, 0))
1204 offset = INTVAL (XEXP (src_addr, 1));
1205 base_regno = REGNO (XEXP (src_addr, 0));
1210 for (i = 0; i < count; i++)
1212 rtx elt = XVECEXP (op, 0, i);
1215 HOST_WIDE_INT newoffset;
1217 if (GET_CODE (elt) != SET
1218 || GET_CODE (SET_DEST (elt)) != REG
1219 || GET_MODE (SET_DEST (elt)) != SImode
1220 || REGNO (SET_DEST (elt)) != dest_regno + i
1221 || GET_CODE (SET_SRC (elt)) != MEM
1222 || GET_MODE (SET_SRC (elt)) != SImode)
1224 newaddr = XEXP (SET_SRC (elt), 0);
1225 if (legitimate_indirect_address_p (newaddr, 0))
1230 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1232 addr_reg = XEXP (newaddr, 0);
1233 newoffset = INTVAL (XEXP (newaddr, 1));
1237 if (REGNO (addr_reg) != base_regno
1238 || newoffset != offset + 4 * i)
1245 ;; Return 1 if OP is valid for stmw insn, known to be a PARALLEL.
1246 (define_predicate "stmw_operation"
1247 (match_code "parallel")
1249 int count = XVECLEN (op, 0);
1250 unsigned int src_regno;
1252 unsigned int base_regno;
1253 HOST_WIDE_INT offset;
1256 /* Perform a quick check so we don't blow up below. */
1258 || GET_CODE (XVECEXP (op, 0, 0)) != SET
1259 || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
1260 || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
1263 src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
1264 dest_addr = XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0);
1267 || count != 32 - (int) src_regno)
1270 if (legitimate_indirect_address_p (dest_addr, 0))
1273 base_regno = REGNO (dest_addr);
1274 if (base_regno == 0)
1277 else if (rs6000_legitimate_offset_address_p (SImode, dest_addr, 0))
1279 offset = INTVAL (XEXP (dest_addr, 1));
1280 base_regno = REGNO (XEXP (dest_addr, 0));
1285 for (i = 0; i < count; i++)
1287 rtx elt = XVECEXP (op, 0, i);
1290 HOST_WIDE_INT newoffset;
1292 if (GET_CODE (elt) != SET
1293 || GET_CODE (SET_SRC (elt)) != REG
1294 || GET_MODE (SET_SRC (elt)) != SImode
1295 || REGNO (SET_SRC (elt)) != src_regno + i
1296 || GET_CODE (SET_DEST (elt)) != MEM
1297 || GET_MODE (SET_DEST (elt)) != SImode)
1299 newaddr = XEXP (SET_DEST (elt), 0);
1300 if (legitimate_indirect_address_p (newaddr, 0))
1305 else if (rs6000_legitimate_offset_address_p (SImode, newaddr, 0))
1307 addr_reg = XEXP (newaddr, 0);
1308 newoffset = INTVAL (XEXP (newaddr, 1));
1312 if (REGNO (addr_reg) != base_regno
1313 || newoffset != offset + 4 * i)