2 ;; Copyright (C) 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify it
8 ;; under the terms of the GNU General Public License as published
9 ;; by the Free Software Foundation; either version 2, or (at your
10 ;; option) any later version.
12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 ;; License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING. If not, write to the
19 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 ;; MA 02110-1301, USA.
42 (UNSPEC_VMHRADDSHS 72)
92 (UNSPEC_VRSQRTEFP 157)
105 (UNSPEC_PREDICATE 173)
116 (UNSPEC_SET_VSCR 213)
117 (UNSPEC_GET_VRSAVE 214)
118 (UNSPEC_REALIGN_LOAD 215)
119 (UNSPEC_REDUC_PLUS 217)
121 (UNSPEC_VCOND_V4SI 301)
122 (UNSPEC_VCOND_V4SF 302)
123 (UNSPEC_VCOND_V8HI 303)
124 (UNSPEC_VCOND_V16QI 304)
125 (UNSPEC_VCONDU_V4SI 305)
126 (UNSPEC_VCONDU_V8HI 306)
127 (UNSPEC_VCONDU_V16QI 307)
131 [(UNSPECV_SET_VRSAVE 30)
139 (define_mode_macro VI [V4SI V8HI V16QI])
140 ;; Short vec in modes
141 (define_mode_macro VIshort [V8HI V16QI])
143 (define_mode_macro VF [V4SF])
144 ;; Vec modes, pity mode macros are not composable
145 (define_mode_macro V [V4SI V8HI V16QI V4SF])
147 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
149 ;; Generic LVX load instruction.
150 (define_insn "altivec_lvx_<mode>"
151 [(set (match_operand:V 0 "altivec_register_operand" "=v")
152 (match_operand:V 1 "memory_operand" "m"))]
155 [(set_attr "type" "vecload")])
157 ;; Generic STVX store instruction.
158 (define_insn "altivec_stvx_<mode>"
159 [(set (match_operand:V 0 "memory_operand" "=m")
160 (match_operand:V 1 "altivec_register_operand" "v"))]
163 [(set_attr "type" "vecstore")])
165 ;; Vector move instructions.
166 (define_expand "mov<mode>"
167 [(set (match_operand:V 0 "nonimmediate_operand" "")
168 (match_operand:V 1 "any_operand" ""))]
171 rs6000_emit_move (operands[0], operands[1], <MODE>mode);
175 (define_insn "*mov<mode>_internal"
176 [(set (match_operand:V 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
177 (match_operand:V 1 "input_operand" "v,m,v,r,o,r,W"))]
179 && (register_operand (operands[0], <MODE>mode)
180 || register_operand (operands[1], <MODE>mode))"
182 switch (which_alternative)
184 case 0: return "stvx %1,%y0";
185 case 1: return "lvx %0,%y1";
186 case 2: return "vor %0,%1,%1";
190 case 6: return output_vec_const_move (operands);
191 default: gcc_unreachable ();
194 [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
197 [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
198 (match_operand:V4SI 1 "input_operand" ""))]
199 "TARGET_ALTIVEC && reload_completed
200 && gpr_or_gpr_p (operands[0], operands[1])"
203 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
207 [(set (match_operand:V4SI 0 "altivec_register_operand" "")
208 (match_operand:V4SI 1 "easy_vector_constant_add_self" ""))]
209 "TARGET_ALTIVEC && reload_completed"
210 [(set (match_dup 0) (match_dup 3))
212 (plus:V4SI (match_dup 0)
215 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
219 [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
220 (match_operand:V8HI 1 "input_operand" ""))]
221 "TARGET_ALTIVEC && reload_completed
222 && gpr_or_gpr_p (operands[0], operands[1])"
224 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
227 [(set (match_operand:V8HI 0 "altivec_register_operand" "")
228 (match_operand:V8HI 1 "easy_vector_constant_add_self" ""))]
229 "TARGET_ALTIVEC && reload_completed"
230 [(set (match_dup 0) (match_dup 3))
232 (plus:V8HI (match_dup 0)
235 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
239 [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
240 (match_operand:V16QI 1 "input_operand" ""))]
241 "TARGET_ALTIVEC && reload_completed
242 && gpr_or_gpr_p (operands[0], operands[1])"
244 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
247 [(set (match_operand:V16QI 0 "altivec_register_operand" "")
248 (match_operand:V16QI 1 "easy_vector_constant_add_self" ""))]
249 "TARGET_ALTIVEC && reload_completed"
250 [(set (match_dup 0) (match_dup 3))
252 (plus:V16QI (match_dup 0)
255 operands[3] = gen_easy_vector_constant_add_self (operands[1]);
259 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
260 (match_operand:V4SF 1 "input_operand" ""))]
261 "TARGET_ALTIVEC && reload_completed
262 && gpr_or_gpr_p (operands[0], operands[1])"
265 rs6000_split_multireg_move (operands[0], operands[1]); DONE;
268 (define_insn "get_vrsave_internal"
269 [(set (match_operand:SI 0 "register_operand" "=r")
270 (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
274 return "mfspr %0,256";
276 return "mfvrsave %0";
278 [(set_attr "type" "*")])
280 (define_insn "*set_vrsave_internal"
281 [(match_parallel 0 "vrsave_operation"
283 (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
284 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
288 return "mtspr 256,%1";
290 return "mtvrsave %1";
292 [(set_attr "type" "*")])
294 (define_insn "*save_world"
295 [(match_parallel 0 "save_world_operation"
296 [(clobber (match_operand:SI 1 "register_operand" "=l"))
297 (use (match_operand:SI 2 "call_operand" "s"))])]
298 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
300 [(set_attr "type" "branch")
301 (set_attr "length" "4")])
303 (define_insn "*restore_world"
304 [(match_parallel 0 "restore_world_operation"
306 (use (match_operand:SI 1 "register_operand" "l"))
307 (use (match_operand:SI 2 "call_operand" "s"))
308 (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
309 "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
312 ;; Simple binary operations.
315 (define_insn "add<mode>3"
316 [(set (match_operand:VI 0 "register_operand" "=v")
317 (plus:VI (match_operand:VI 1 "register_operand" "v")
318 (match_operand:VI 2 "register_operand" "v")))]
320 "vaddu<VI_char>m %0,%1,%2"
321 [(set_attr "type" "vecsimple")])
323 (define_insn "addv4sf3"
324 [(set (match_operand:V4SF 0 "register_operand" "=v")
325 (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
326 (match_operand:V4SF 2 "register_operand" "v")))]
329 [(set_attr "type" "vecfloat")])
331 (define_insn "altivec_vaddcuw"
332 [(set (match_operand:V4SI 0 "register_operand" "=v")
333 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
334 (match_operand:V4SI 2 "register_operand" "v")]
338 [(set_attr "type" "vecsimple")])
340 (define_insn "altivec_vaddu<VI_char>s"
341 [(set (match_operand:VI 0 "register_operand" "=v")
342 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
343 (match_operand:VI 2 "register_operand" "v")]
345 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
347 "vaddu<VI_char>s %0,%1,%2"
348 [(set_attr "type" "vecsimple")])
350 (define_insn "altivec_vadds<VI_char>s"
351 [(set (match_operand:VI 0 "register_operand" "=v")
352 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
353 (match_operand:VI 2 "register_operand" "v")]
355 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
357 "vadds<VI_char>s %0,%1,%2"
358 [(set_attr "type" "vecsimple")])
361 (define_insn "sub<mode>3"
362 [(set (match_operand:VI 0 "register_operand" "=v")
363 (minus:VI (match_operand:VI 1 "register_operand" "v")
364 (match_operand:VI 2 "register_operand" "v")))]
366 "vsubu<VI_char>m %0,%1,%2"
367 [(set_attr "type" "vecsimple")])
369 (define_insn "subv4sf3"
370 [(set (match_operand:V4SF 0 "register_operand" "=v")
371 (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
372 (match_operand:V4SF 2 "register_operand" "v")))]
375 [(set_attr "type" "vecfloat")])
377 (define_insn "altivec_vsubcuw"
378 [(set (match_operand:V4SI 0 "register_operand" "=v")
379 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
380 (match_operand:V4SI 2 "register_operand" "v")]
384 [(set_attr "type" "vecsimple")])
386 (define_insn "altivec_vsubu<VI_char>s"
387 [(set (match_operand:VI 0 "register_operand" "=v")
388 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
389 (match_operand:VI 2 "register_operand" "v")]
391 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
393 "vsubu<VI_char>s %0,%1,%2"
394 [(set_attr "type" "vecsimple")])
396 (define_insn "altivec_vsubs<VI_char>s"
397 [(set (match_operand:VI 0 "register_operand" "=v")
398 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
399 (match_operand:VI 2 "register_operand" "v")]
401 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
403 "vsubs<VI_char>s %0,%1,%2"
404 [(set_attr "type" "vecsimple")])
407 (define_insn "altivec_vavgu<VI_char>"
408 [(set (match_operand:VI 0 "register_operand" "=v")
409 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
410 (match_operand:VI 2 "register_operand" "v")]
413 "vavgu<VI_char> %0,%1,%2"
414 [(set_attr "type" "vecsimple")])
416 (define_insn "altivec_vavgs<VI_char>"
417 [(set (match_operand:VI 0 "register_operand" "=v")
418 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
419 (match_operand:VI 2 "register_operand" "v")]
422 "vavgs<VI_char> %0,%1,%2"
423 [(set_attr "type" "vecsimple")])
425 (define_insn "altivec_vcmpbfp"
426 [(set (match_operand:V4SI 0 "register_operand" "=v")
427 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
428 (match_operand:V4SF 2 "register_operand" "v")]
432 [(set_attr "type" "veccmp")])
434 (define_insn "altivec_vcmpequb"
435 [(set (match_operand:V16QI 0 "register_operand" "=v")
436 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
437 (match_operand:V16QI 2 "register_operand" "v")]
441 [(set_attr "type" "vecsimple")])
443 (define_insn "altivec_vcmpequh"
444 [(set (match_operand:V8HI 0 "register_operand" "=v")
445 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
446 (match_operand:V8HI 2 "register_operand" "v")]
450 [(set_attr "type" "vecsimple")])
452 (define_insn "altivec_vcmpequw"
453 [(set (match_operand:V4SI 0 "register_operand" "=v")
454 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
455 (match_operand:V4SI 2 "register_operand" "v")]
459 [(set_attr "type" "vecsimple")])
461 (define_insn "altivec_vcmpeqfp"
462 [(set (match_operand:V4SI 0 "register_operand" "=v")
463 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
464 (match_operand:V4SF 2 "register_operand" "v")]
468 [(set_attr "type" "veccmp")])
470 (define_insn "altivec_vcmpgefp"
471 [(set (match_operand:V4SI 0 "register_operand" "=v")
472 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
473 (match_operand:V4SF 2 "register_operand" "v")]
477 [(set_attr "type" "veccmp")])
479 (define_insn "altivec_vcmpgtub"
480 [(set (match_operand:V16QI 0 "register_operand" "=v")
481 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
482 (match_operand:V16QI 2 "register_operand" "v")]
486 [(set_attr "type" "vecsimple")])
488 (define_insn "altivec_vcmpgtsb"
489 [(set (match_operand:V16QI 0 "register_operand" "=v")
490 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
491 (match_operand:V16QI 2 "register_operand" "v")]
495 [(set_attr "type" "vecsimple")])
497 (define_insn "altivec_vcmpgtuh"
498 [(set (match_operand:V8HI 0 "register_operand" "=v")
499 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
500 (match_operand:V8HI 2 "register_operand" "v")]
504 [(set_attr "type" "vecsimple")])
506 (define_insn "altivec_vcmpgtsh"
507 [(set (match_operand:V8HI 0 "register_operand" "=v")
508 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
509 (match_operand:V8HI 2 "register_operand" "v")]
513 [(set_attr "type" "vecsimple")])
515 (define_insn "altivec_vcmpgtuw"
516 [(set (match_operand:V4SI 0 "register_operand" "=v")
517 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
518 (match_operand:V4SI 2 "register_operand" "v")]
522 [(set_attr "type" "vecsimple")])
524 (define_insn "altivec_vcmpgtsw"
525 [(set (match_operand:V4SI 0 "register_operand" "=v")
526 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
527 (match_operand:V4SI 2 "register_operand" "v")]
531 [(set_attr "type" "vecsimple")])
533 (define_insn "altivec_vcmpgtfp"
534 [(set (match_operand:V4SI 0 "register_operand" "=v")
535 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
536 (match_operand:V4SF 2 "register_operand" "v")]
540 [(set_attr "type" "veccmp")])
542 ;; Fused multiply add
543 (define_insn "altivec_vmaddfp"
544 [(set (match_operand:V4SF 0 "register_operand" "=v")
545 (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
546 (match_operand:V4SF 2 "register_operand" "v"))
547 (match_operand:V4SF 3 "register_operand" "v")))]
549 "vmaddfp %0,%1,%2,%3"
550 [(set_attr "type" "vecfloat")])
552 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
554 (define_expand "mulv4sf3"
555 [(use (match_operand:V4SF 0 "register_operand" ""))
556 (use (match_operand:V4SF 1 "register_operand" ""))
557 (use (match_operand:V4SF 2 "register_operand" ""))]
558 "TARGET_ALTIVEC && TARGET_FUSED_MADD"
563 /* Generate [-0.0, -0.0, -0.0, -0.0]. */
564 neg0 = gen_reg_rtx (V4SFmode);
565 emit_insn (gen_altivec_vspltisw_v4sf (neg0, constm1_rtx));
566 emit_insn (gen_altivec_vslw_v4sf (neg0, neg0, neg0));
568 /* Use the multiply-add. */
569 emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
574 ;; 32 bit integer multiplication
575 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
576 ;; A_low = Operand_0 & 0xFFFF
577 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
578 ;; B_low = Operand_1 & 0xFFFF
579 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
581 ;; (define_insn "mulv4si3"
582 ;; [(set (match_operand:V4SI 0 "register_operand" "=v")
583 ;; (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
584 ;; (match_operand:V4SI 2 "register_operand" "v")))]
585 (define_expand "mulv4si3"
586 [(use (match_operand:V4SI 0 "register_operand" ""))
587 (use (match_operand:V4SI 1 "register_operand" ""))
588 (use (match_operand:V4SI 2 "register_operand" ""))]
601 zero = gen_reg_rtx (V4SImode);
602 emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
604 sixteen = gen_reg_rtx (V4SImode);
605 emit_insn (gen_altivec_vspltisw (sixteen, gen_rtx_CONST_INT (V4SImode, -16)));
607 swap = gen_reg_rtx (V4SImode);
608 emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
610 one = gen_reg_rtx (V8HImode);
611 convert_move (one, operands[1], 0);
613 two = gen_reg_rtx (V8HImode);
614 convert_move (two, operands[2], 0);
616 small_swap = gen_reg_rtx (V8HImode);
617 convert_move (small_swap, swap, 0);
619 low_product = gen_reg_rtx (V4SImode);
620 emit_insn (gen_altivec_vmulouh (low_product, one, two));
622 high_product = gen_reg_rtx (V4SImode);
623 emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
625 emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
627 emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
633 ;; Fused multiply subtract
634 (define_insn "altivec_vnmsubfp"
635 [(set (match_operand:V4SF 0 "register_operand" "=v")
636 (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
637 (match_operand:V4SF 2 "register_operand" "v"))
638 (match_operand:V4SF 3 "register_operand" "v"))))]
640 "vnmsubfp %0,%1,%2,%3"
641 [(set_attr "type" "vecfloat")])
643 (define_insn "altivec_vmsumu<VI_char>m"
644 [(set (match_operand:V4SI 0 "register_operand" "=v")
645 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
646 (match_operand:VIshort 2 "register_operand" "v")
647 (match_operand:V4SI 3 "register_operand" "v")]
650 "vmsumu<VI_char>m %0,%1,%2,%3"
651 [(set_attr "type" "veccomplex")])
653 (define_insn "altivec_vmsumm<VI_char>m"
654 [(set (match_operand:V4SI 0 "register_operand" "=v")
655 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
656 (match_operand:VIshort 2 "register_operand" "v")
657 (match_operand:V4SI 3 "register_operand" "v")]
660 "vmsumm<VI_char>m %0,%1,%2,%3"
661 [(set_attr "type" "veccomplex")])
663 (define_insn "altivec_vmsumshm"
664 [(set (match_operand:V4SI 0 "register_operand" "=v")
665 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
666 (match_operand:V8HI 2 "register_operand" "v")
667 (match_operand:V4SI 3 "register_operand" "v")]
670 "vmsumshm %0,%1,%2,%3"
671 [(set_attr "type" "veccomplex")])
673 (define_insn "altivec_vmsumuhs"
674 [(set (match_operand:V4SI 0 "register_operand" "=v")
675 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
676 (match_operand:V8HI 2 "register_operand" "v")
677 (match_operand:V4SI 3 "register_operand" "v")]
679 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
681 "vmsumuhs %0,%1,%2,%3"
682 [(set_attr "type" "veccomplex")])
684 (define_insn "altivec_vmsumshs"
685 [(set (match_operand:V4SI 0 "register_operand" "=v")
686 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
687 (match_operand:V8HI 2 "register_operand" "v")
688 (match_operand:V4SI 3 "register_operand" "v")]
690 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
692 "vmsumshs %0,%1,%2,%3"
693 [(set_attr "type" "veccomplex")])
697 (define_insn "umax<mode>3"
698 [(set (match_operand:VI 0 "register_operand" "=v")
699 (umax:VI (match_operand:VI 1 "register_operand" "v")
700 (match_operand:VI 2 "register_operand" "v")))]
702 "vmaxu<VI_char> %0,%1,%2"
703 [(set_attr "type" "vecsimple")])
705 (define_insn "smax<mode>3"
706 [(set (match_operand:VI 0 "register_operand" "=v")
707 (smax:VI (match_operand:VI 1 "register_operand" "v")
708 (match_operand:VI 2 "register_operand" "v")))]
710 "vmaxs<VI_char> %0,%1,%2"
711 [(set_attr "type" "vecsimple")])
713 (define_insn "smaxv4sf3"
714 [(set (match_operand:V4SF 0 "register_operand" "=v")
715 (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
716 (match_operand:V4SF 2 "register_operand" "v")))]
719 [(set_attr "type" "veccmp")])
721 (define_insn "umin<mode>3"
722 [(set (match_operand:VI 0 "register_operand" "=v")
723 (umin:VI (match_operand:VI 1 "register_operand" "v")
724 (match_operand:VI 2 "register_operand" "v")))]
726 "vminu<VI_char> %0,%1,%2"
727 [(set_attr "type" "vecsimple")])
729 (define_insn "smin<mode>3"
730 [(set (match_operand:VI 0 "register_operand" "=v")
731 (smin:VI (match_operand:VI 1 "register_operand" "v")
732 (match_operand:VI 2 "register_operand" "v")))]
734 "vmins<VI_char> %0,%1,%2"
735 [(set_attr "type" "vecsimple")])
737 (define_insn "sminv4sf3"
738 [(set (match_operand:V4SF 0 "register_operand" "=v")
739 (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
740 (match_operand:V4SF 2 "register_operand" "v")))]
743 [(set_attr "type" "veccmp")])
745 (define_insn "altivec_vmhaddshs"
746 [(set (match_operand:V8HI 0 "register_operand" "=v")
747 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
748 (match_operand:V8HI 2 "register_operand" "v")
749 (match_operand:V8HI 3 "register_operand" "v")]
751 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
753 "vmhaddshs %0,%1,%2,%3"
754 [(set_attr "type" "veccomplex")])
756 (define_insn "altivec_vmhraddshs"
757 [(set (match_operand:V8HI 0 "register_operand" "=v")
758 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
759 (match_operand:V8HI 2 "register_operand" "v")
760 (match_operand:V8HI 3 "register_operand" "v")]
762 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
764 "vmhraddshs %0,%1,%2,%3"
765 [(set_attr "type" "veccomplex")])
767 (define_insn "altivec_vmladduhm"
768 [(set (match_operand:V8HI 0 "register_operand" "=v")
769 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
770 (match_operand:V8HI 2 "register_operand" "v")
771 (match_operand:V8HI 3 "register_operand" "v")]
774 "vmladduhm %0,%1,%2,%3"
775 [(set_attr "type" "veccomplex")])
777 (define_insn "altivec_vmrghb"
778 [(set (match_operand:V16QI 0 "register_operand" "=v")
779 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
780 (parallel [(const_int 0)
796 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
797 (parallel [(const_int 8)
816 [(set_attr "type" "vecperm")])
818 (define_insn "altivec_vmrghh"
819 [(set (match_operand:V8HI 0 "register_operand" "=v")
820 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
821 (parallel [(const_int 0)
829 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
830 (parallel [(const_int 4)
841 [(set_attr "type" "vecperm")])
843 (define_insn "altivec_vmrghw"
844 [(set (match_operand:V4SI 0 "register_operand" "=v")
845 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
846 (parallel [(const_int 0)
850 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
851 (parallel [(const_int 2)
858 [(set_attr "type" "vecperm")])
860 (define_insn "altivec_vmrglb"
861 [(set (match_operand:V16QI 0 "register_operand" "=v")
862 (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
863 (parallel [(const_int 8)
879 (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
880 (parallel [(const_int 0)
899 [(set_attr "type" "vecperm")])
901 (define_insn "altivec_vmrglh"
902 [(set (match_operand:V8HI 0 "register_operand" "=v")
903 (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
904 (parallel [(const_int 4)
912 (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
913 (parallel [(const_int 0)
924 [(set_attr "type" "vecperm")])
926 (define_insn "altivec_vmrglw"
927 [(set (match_operand:V4SI 0 "register_operand" "=v")
928 (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
929 (parallel [(const_int 2)
933 (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
934 (parallel [(const_int 0)
941 [(set_attr "type" "vecperm")])
943 (define_insn "altivec_vmuleub"
944 [(set (match_operand:V8HI 0 "register_operand" "=v")
945 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
946 (match_operand:V16QI 2 "register_operand" "v")]
950 [(set_attr "type" "veccomplex")])
952 (define_insn "altivec_vmulesb"
953 [(set (match_operand:V8HI 0 "register_operand" "=v")
954 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
955 (match_operand:V16QI 2 "register_operand" "v")]
959 [(set_attr "type" "veccomplex")])
961 (define_insn "altivec_vmuleuh"
962 [(set (match_operand:V4SI 0 "register_operand" "=v")
963 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
964 (match_operand:V8HI 2 "register_operand" "v")]
968 [(set_attr "type" "veccomplex")])
970 (define_insn "altivec_vmulesh"
971 [(set (match_operand:V4SI 0 "register_operand" "=v")
972 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
973 (match_operand:V8HI 2 "register_operand" "v")]
977 [(set_attr "type" "veccomplex")])
979 (define_insn "altivec_vmuloub"
980 [(set (match_operand:V8HI 0 "register_operand" "=v")
981 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
982 (match_operand:V16QI 2 "register_operand" "v")]
986 [(set_attr "type" "veccomplex")])
988 (define_insn "altivec_vmulosb"
989 [(set (match_operand:V8HI 0 "register_operand" "=v")
990 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
991 (match_operand:V16QI 2 "register_operand" "v")]
995 [(set_attr "type" "veccomplex")])
997 (define_insn "altivec_vmulouh"
998 [(set (match_operand:V4SI 0 "register_operand" "=v")
999 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1000 (match_operand:V8HI 2 "register_operand" "v")]
1004 [(set_attr "type" "veccomplex")])
1006 (define_insn "altivec_vmulosh"
1007 [(set (match_operand:V4SI 0 "register_operand" "=v")
1008 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1009 (match_operand:V8HI 2 "register_operand" "v")]
1013 [(set_attr "type" "veccomplex")])
1018 (define_insn "and<mode>3"
1019 [(set (match_operand:VI 0 "register_operand" "=v")
1020 (and:VI (match_operand:VI 1 "register_operand" "v")
1021 (match_operand:VI 2 "register_operand" "v")))]
1024 [(set_attr "type" "vecsimple")])
1026 (define_insn "ior<mode>3"
1027 [(set (match_operand:VI 0 "register_operand" "=v")
1028 (ior:VI (match_operand:VI 1 "register_operand" "v")
1029 (match_operand:VI 2 "register_operand" "v")))]
1032 [(set_attr "type" "vecsimple")])
1034 (define_insn "xor<mode>3"
1035 [(set (match_operand:VI 0 "register_operand" "=v")
1036 (xor:VI (match_operand:VI 1 "register_operand" "v")
1037 (match_operand:VI 2 "register_operand" "v")))]
1040 [(set_attr "type" "vecsimple")])
1042 (define_insn "one_cmpl<mode>2"
1043 [(set (match_operand:VI 0 "register_operand" "=v")
1044 (not:VI (match_operand:VI 1 "register_operand" "v")))]
1047 [(set_attr "type" "vecsimple")])
1049 (define_insn "altivec_nor<mode>3"
1050 [(set (match_operand:VI 0 "register_operand" "=v")
1051 (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1052 (match_operand:VI 2 "register_operand" "v"))))]
1055 [(set_attr "type" "vecsimple")])
1057 (define_insn "andc<mode>3"
1058 [(set (match_operand:VI 0 "register_operand" "=v")
1059 (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1060 (match_operand:VI 1 "register_operand" "v")))]
1063 [(set_attr "type" "vecsimple")])
1065 (define_insn "*andc3_v4sf"
1066 [(set (match_operand:V4SF 0 "register_operand" "=v")
1067 (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1068 (match_operand:V4SF 1 "register_operand" "v")))]
1071 [(set_attr "type" "vecsimple")])
1073 (define_insn "altivec_vpkuhum"
1074 [(set (match_operand:V16QI 0 "register_operand" "=v")
1075 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1076 (match_operand:V8HI 2 "register_operand" "v")]
1080 [(set_attr "type" "vecperm")])
1082 (define_insn "altivec_vpkuwum"
1083 [(set (match_operand:V8HI 0 "register_operand" "=v")
1084 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1085 (match_operand:V4SI 2 "register_operand" "v")]
1089 [(set_attr "type" "vecperm")])
1091 (define_insn "altivec_vpkpx"
1092 [(set (match_operand:V8HI 0 "register_operand" "=v")
1093 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1094 (match_operand:V4SI 2 "register_operand" "v")]
1098 [(set_attr "type" "vecperm")])
1100 (define_insn "altivec_vpkuhss"
1101 [(set (match_operand:V16QI 0 "register_operand" "=v")
1102 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1103 (match_operand:V8HI 2 "register_operand" "v")]
1105 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1108 [(set_attr "type" "vecperm")])
1110 (define_insn "altivec_vpkshss"
1111 [(set (match_operand:V16QI 0 "register_operand" "=v")
1112 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1113 (match_operand:V8HI 2 "register_operand" "v")]
1115 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1118 [(set_attr "type" "vecperm")])
1120 (define_insn "altivec_vpkuwss"
1121 [(set (match_operand:V8HI 0 "register_operand" "=v")
1122 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1123 (match_operand:V4SI 2 "register_operand" "v")]
1125 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1128 [(set_attr "type" "vecperm")])
1130 (define_insn "altivec_vpkswss"
1131 [(set (match_operand:V8HI 0 "register_operand" "=v")
1132 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1133 (match_operand:V4SI 2 "register_operand" "v")]
1135 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1138 [(set_attr "type" "vecperm")])
1140 (define_insn "altivec_vpkuhus"
1141 [(set (match_operand:V16QI 0 "register_operand" "=v")
1142 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1143 (match_operand:V8HI 2 "register_operand" "v")]
1145 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1148 [(set_attr "type" "vecperm")])
1150 (define_insn "altivec_vpkshus"
1151 [(set (match_operand:V16QI 0 "register_operand" "=v")
1152 (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1153 (match_operand:V8HI 2 "register_operand" "v")]
1155 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1158 [(set_attr "type" "vecperm")])
1160 (define_insn "altivec_vpkuwus"
1161 [(set (match_operand:V8HI 0 "register_operand" "=v")
1162 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1163 (match_operand:V4SI 2 "register_operand" "v")]
1165 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1168 [(set_attr "type" "vecperm")])
1170 (define_insn "altivec_vpkswus"
1171 [(set (match_operand:V8HI 0 "register_operand" "=v")
1172 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1173 (match_operand:V4SI 2 "register_operand" "v")]
1175 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1178 [(set_attr "type" "vecperm")])
1180 (define_insn "altivec_vrl<VI_char>"
1181 [(set (match_operand:VI 0 "register_operand" "=v")
1182 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1183 (match_operand:VI 2 "register_operand" "v")]
1186 "vrl<VI_char> %0,%1,%2"
1187 [(set_attr "type" "vecsimple")])
1189 (define_insn "altivec_vsl<VI_char>"
1190 [(set (match_operand:VI 0 "register_operand" "=v")
1191 (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1192 (match_operand:VI 2 "register_operand" "v")]
1195 "vsl<VI_char> %0,%1,%2"
1196 [(set_attr "type" "vecsimple")])
1198 (define_insn "altivec_vslw_v4sf"
1199 [(set (match_operand:V4SF 0 "register_operand" "=v")
1200 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1201 (match_operand:V4SF 2 "register_operand" "v")]
1205 [(set_attr "type" "vecsimple")])
1207 (define_insn "altivec_vsl"
1208 [(set (match_operand:V4SI 0 "register_operand" "=v")
1209 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1210 (match_operand:V4SI 2 "register_operand" "v")]
1214 [(set_attr "type" "vecperm")])
1216 (define_insn "altivec_vslo"
1217 [(set (match_operand:V4SI 0 "register_operand" "=v")
1218 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1219 (match_operand:V4SI 2 "register_operand" "v")]
1223 [(set_attr "type" "vecperm")])
1225 (define_insn "lshr<mode>3"
1226 [(set (match_operand:VI 0 "register_operand" "=v")
1227 (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1228 (match_operand:VI 2 "register_operand" "v") ))]
1230 "vsr<VI_char> %0,%1,%2"
1231 [(set_attr "type" "vecsimple")])
1233 (define_insn "ashr<mode>3"
1234 [(set (match_operand:VI 0 "register_operand" "=v")
1235 (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1236 (match_operand:VI 2 "register_operand" "v") ))]
1238 "vsra<VI_char> %0,%1,%2"
1239 [(set_attr "type" "vecsimple")])
1241 (define_insn "altivec_vsr"
1242 [(set (match_operand:V4SI 0 "register_operand" "=v")
1243 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1244 (match_operand:V4SI 2 "register_operand" "v")]
1248 [(set_attr "type" "vecperm")])
1250 (define_insn "altivec_vsro"
1251 [(set (match_operand:V4SI 0 "register_operand" "=v")
1252 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1253 (match_operand:V4SI 2 "register_operand" "v")]
1257 [(set_attr "type" "vecperm")])
1259 (define_insn "altivec_vsum4ubs"
1260 [(set (match_operand:V4SI 0 "register_operand" "=v")
1261 (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1262 (match_operand:V4SI 2 "register_operand" "v")]
1264 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1267 [(set_attr "type" "veccomplex")])
1269 (define_insn "altivec_vsum4s<VI_char>s"
1270 [(set (match_operand:V4SI 0 "register_operand" "=v")
1271 (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1272 (match_operand:V4SI 2 "register_operand" "v")]
1274 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1276 "vsum4s<VI_char>s %0,%1,%2"
1277 [(set_attr "type" "veccomplex")])
1279 (define_insn "altivec_vsum2sws"
1280 [(set (match_operand:V4SI 0 "register_operand" "=v")
1281 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1282 (match_operand:V4SI 2 "register_operand" "v")]
1284 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1287 [(set_attr "type" "veccomplex")])
1289 (define_insn "altivec_vsumsws"
1290 [(set (match_operand:V4SI 0 "register_operand" "=v")
1291 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1292 (match_operand:V4SI 2 "register_operand" "v")]
1294 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1297 [(set_attr "type" "veccomplex")])
1299 (define_insn "altivec_vspltb"
1300 [(set (match_operand:V16QI 0 "register_operand" "=v")
1301 (vec_duplicate:V16QI
1302 (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1304 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1307 [(set_attr "type" "vecperm")])
1309 (define_insn "altivec_vsplth"
1310 [(set (match_operand:V8HI 0 "register_operand" "=v")
1312 (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1314 [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1317 [(set_attr "type" "vecperm")])
1319 (define_insn "altivec_vspltw"
1320 [(set (match_operand:V4SI 0 "register_operand" "=v")
1322 (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1324 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1327 [(set_attr "type" "vecperm")])
1329 (define_insn "*altivec_vspltsf"
1330 [(set (match_operand:V4SF 0 "register_operand" "=v")
1332 (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1334 [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1337 [(set_attr "type" "vecperm")])
1339 (define_insn "altivec_vspltis<VI_char>"
1340 [(set (match_operand:VI 0 "register_operand" "=v")
1342 (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1344 "vspltis<VI_char> %0,%1"
1345 [(set_attr "type" "vecperm")])
1347 (define_insn "altivec_vspltisw_v4sf"
1348 [(set (match_operand:V4SF 0 "register_operand" "=v")
1350 (float:SF (match_operand:QI 1 "s5bit_cint_operand" "i"))))]
1353 [(set_attr "type" "vecperm")])
1355 (define_insn "ftruncv4sf2"
1356 [(set (match_operand:V4SF 0 "register_operand" "=v")
1357 (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1360 [(set_attr "type" "vecfloat")])
1362 (define_insn "altivec_vperm_<mode>"
1363 [(set (match_operand:V 0 "register_operand" "=v")
1364 (unspec:V [(match_operand:V 1 "register_operand" "v")
1365 (match_operand:V 2 "register_operand" "v")
1366 (match_operand:V16QI 3 "register_operand" "v")]
1370 [(set_attr "type" "vecperm")])
1372 (define_insn "altivec_vrfip"
1373 [(set (match_operand:V4SF 0 "register_operand" "=v")
1374 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1378 [(set_attr "type" "vecfloat")])
1380 (define_insn "altivec_vrfin"
1381 [(set (match_operand:V4SF 0 "register_operand" "=v")
1382 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1386 [(set_attr "type" "vecfloat")])
1388 (define_insn "altivec_vrfim"
1389 [(set (match_operand:V4SF 0 "register_operand" "=v")
1390 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1394 [(set_attr "type" "vecfloat")])
1396 (define_insn "altivec_vcfux"
1397 [(set (match_operand:V4SF 0 "register_operand" "=v")
1398 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1399 (match_operand:QI 2 "immediate_operand" "i")]
1403 [(set_attr "type" "vecfloat")])
1405 (define_insn "altivec_vcfsx"
1406 [(set (match_operand:V4SF 0 "register_operand" "=v")
1407 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1408 (match_operand:QI 2 "immediate_operand" "i")]
1412 [(set_attr "type" "vecfloat")])
1414 (define_insn "altivec_vctuxs"
1415 [(set (match_operand:V4SI 0 "register_operand" "=v")
1416 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1417 (match_operand:QI 2 "immediate_operand" "i")]
1419 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1422 [(set_attr "type" "vecfloat")])
1424 (define_insn "altivec_vctsxs"
1425 [(set (match_operand:V4SI 0 "register_operand" "=v")
1426 (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1427 (match_operand:QI 2 "immediate_operand" "i")]
1429 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1432 [(set_attr "type" "vecfloat")])
1434 (define_insn "altivec_vlogefp"
1435 [(set (match_operand:V4SF 0 "register_operand" "=v")
1436 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1440 [(set_attr "type" "vecfloat")])
1442 (define_insn "altivec_vexptefp"
1443 [(set (match_operand:V4SF 0 "register_operand" "=v")
1444 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1448 [(set_attr "type" "vecfloat")])
1450 (define_insn "altivec_vrsqrtefp"
1451 [(set (match_operand:V4SF 0 "register_operand" "=v")
1452 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1456 [(set_attr "type" "vecfloat")])
1458 (define_insn "altivec_vrefp"
1459 [(set (match_operand:V4SF 0 "register_operand" "=v")
1460 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1464 [(set_attr "type" "vecfloat")])
1466 (define_expand "vcondv4si"
1467 [(set (match_operand:V4SI 0 "register_operand" "=v")
1468 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1469 (match_operand:V4SI 2 "register_operand" "v")
1470 (match_operand:V4SI 3 "comparison_operator" "")
1471 (match_operand:V4SI 4 "register_operand" "v")
1472 (match_operand:V4SI 5 "register_operand" "v")
1473 ] UNSPEC_VCOND_V4SI))]
1477 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1478 operands[3], operands[4], operands[5]))
1485 (define_expand "vconduv4si"
1486 [(set (match_operand:V4SI 0 "register_operand" "=v")
1487 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1488 (match_operand:V4SI 2 "register_operand" "v")
1489 (match_operand:V4SI 3 "comparison_operator" "")
1490 (match_operand:V4SI 4 "register_operand" "v")
1491 (match_operand:V4SI 5 "register_operand" "v")
1492 ] UNSPEC_VCONDU_V4SI))]
1496 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1497 operands[3], operands[4], operands[5]))
1504 (define_expand "vcondv4sf"
1505 [(set (match_operand:V4SF 0 "register_operand" "=v")
1506 (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1507 (match_operand:V4SF 2 "register_operand" "v")
1508 (match_operand:V4SF 3 "comparison_operator" "")
1509 (match_operand:V4SF 4 "register_operand" "v")
1510 (match_operand:V4SF 5 "register_operand" "v")
1511 ] UNSPEC_VCOND_V4SF))]
1515 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1516 operands[3], operands[4], operands[5]))
1523 (define_expand "vcondv8hi"
1524 [(set (match_operand:V4SF 0 "register_operand" "=v")
1525 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1526 (match_operand:V8HI 2 "register_operand" "v")
1527 (match_operand:V8HI 3 "comparison_operator" "")
1528 (match_operand:V8HI 4 "register_operand" "v")
1529 (match_operand:V8HI 5 "register_operand" "v")
1530 ] UNSPEC_VCOND_V8HI))]
1534 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1535 operands[3], operands[4], operands[5]))
1542 (define_expand "vconduv8hi"
1543 [(set (match_operand:V4SF 0 "register_operand" "=v")
1544 (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1545 (match_operand:V8HI 2 "register_operand" "v")
1546 (match_operand:V8HI 3 "comparison_operator" "")
1547 (match_operand:V8HI 4 "register_operand" "v")
1548 (match_operand:V8HI 5 "register_operand" "v")
1549 ] UNSPEC_VCONDU_V8HI))]
1553 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1554 operands[3], operands[4], operands[5]))
1561 (define_expand "vcondv16qi"
1562 [(set (match_operand:V4SF 0 "register_operand" "=v")
1563 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1564 (match_operand:V16QI 2 "register_operand" "v")
1565 (match_operand:V16QI 3 "comparison_operator" "")
1566 (match_operand:V16QI 4 "register_operand" "v")
1567 (match_operand:V16QI 5 "register_operand" "v")
1568 ] UNSPEC_VCOND_V16QI))]
1572 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1573 operands[3], operands[4], operands[5]))
1580 (define_expand "vconduv16qi"
1581 [(set (match_operand:V4SF 0 "register_operand" "=v")
1582 (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1583 (match_operand:V16QI 2 "register_operand" "v")
1584 (match_operand:V16QI 3 "comparison_operator" "")
1585 (match_operand:V16QI 4 "register_operand" "v")
1586 (match_operand:V16QI 5 "register_operand" "v")
1587 ] UNSPEC_VCONDU_V16QI))]
1591 if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1592 operands[3], operands[4], operands[5]))
1600 (define_insn "altivec_vsel_v4si"
1601 [(set (match_operand:V4SI 0 "register_operand" "=v")
1602 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1603 (match_operand:V4SI 2 "register_operand" "v")
1604 (match_operand:V4SI 3 "register_operand" "v")]
1608 [(set_attr "type" "vecperm")])
1610 (define_insn "altivec_vsel_v4sf"
1611 [(set (match_operand:V4SF 0 "register_operand" "=v")
1612 (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1613 (match_operand:V4SF 2 "register_operand" "v")
1614 (match_operand:V4SI 3 "register_operand" "v")]
1618 [(set_attr "type" "vecperm")])
1620 (define_insn "altivec_vsel_v8hi"
1621 [(set (match_operand:V8HI 0 "register_operand" "=v")
1622 (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1623 (match_operand:V8HI 2 "register_operand" "v")
1624 (match_operand:V8HI 3 "register_operand" "v")]
1628 [(set_attr "type" "vecperm")])
1630 (define_insn "altivec_vsel_v16qi"
1631 [(set (match_operand:V16QI 0 "register_operand" "=v")
1632 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1633 (match_operand:V16QI 2 "register_operand" "v")
1634 (match_operand:V16QI 3 "register_operand" "v")]
1638 [(set_attr "type" "vecperm")])
1640 (define_insn "altivec_vsldoi_<mode>"
1641 [(set (match_operand:V 0 "register_operand" "=v")
1642 (unspec:V [(match_operand:V 1 "register_operand" "v")
1643 (match_operand:V 2 "register_operand" "v")
1644 (match_operand:QI 3 "immediate_operand" "i")]
1647 "vsldoi %0,%1,%2,%3"
1648 [(set_attr "type" "vecperm")])
1650 (define_insn "altivec_vupkhsb"
1651 [(set (match_operand:V8HI 0 "register_operand" "=v")
1652 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1656 [(set_attr "type" "vecperm")])
1658 (define_insn "altivec_vupkhpx"
1659 [(set (match_operand:V4SI 0 "register_operand" "=v")
1660 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1664 [(set_attr "type" "vecperm")])
1666 (define_insn "altivec_vupkhsh"
1667 [(set (match_operand:V4SI 0 "register_operand" "=v")
1668 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1672 [(set_attr "type" "vecperm")])
1674 (define_insn "altivec_vupklsb"
1675 [(set (match_operand:V8HI 0 "register_operand" "=v")
1676 (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1680 [(set_attr "type" "vecperm")])
1682 (define_insn "altivec_vupklpx"
1683 [(set (match_operand:V4SI 0 "register_operand" "=v")
1684 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1688 [(set_attr "type" "vecperm")])
1690 (define_insn "altivec_vupklsh"
1691 [(set (match_operand:V4SI 0 "register_operand" "=v")
1692 (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1696 [(set_attr "type" "vecperm")])
1698 ;; AltiVec predicates.
1700 (define_expand "cr6_test_for_zero"
1701 [(set (match_operand:SI 0 "register_operand" "=r")
1707 (define_expand "cr6_test_for_zero_reverse"
1708 [(set (match_operand:SI 0 "register_operand" "=r")
1711 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1715 (define_expand "cr6_test_for_lt"
1716 [(set (match_operand:SI 0 "register_operand" "=r")
1722 (define_expand "cr6_test_for_lt_reverse"
1723 [(set (match_operand:SI 0 "register_operand" "=r")
1726 (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1730 ;; We can get away with generating the opcode on the fly (%3 below)
1731 ;; because all the predicates have the same scheduling parameters.
1733 (define_insn "altivec_predicate_<mode>"
1735 (unspec:CC [(match_operand:V 1 "register_operand" "v")
1736 (match_operand:V 2 "register_operand" "v")
1737 (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1738 (clobber (match_scratch:V 0 "=v"))]
1741 [(set_attr "type" "veccmp")])
1743 (define_insn "altivec_mtvscr"
1746 [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1749 [(set_attr "type" "vecsimple")])
1751 (define_insn "altivec_mfvscr"
1752 [(set (match_operand:V8HI 0 "register_operand" "=v")
1753 (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1756 [(set_attr "type" "vecsimple")])
1758 (define_insn "altivec_dssall"
1759 [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1762 [(set_attr "type" "vecsimple")])
1764 (define_insn "altivec_dss"
1765 [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1769 [(set_attr "type" "vecsimple")])
1771 (define_insn "altivec_dst"
1772 [(unspec [(match_operand 0 "register_operand" "b")
1773 (match_operand:SI 1 "register_operand" "r")
1774 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1775 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1777 [(set_attr "type" "vecsimple")])
1779 (define_insn "altivec_dstt"
1780 [(unspec [(match_operand 0 "register_operand" "b")
1781 (match_operand:SI 1 "register_operand" "r")
1782 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1783 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1785 [(set_attr "type" "vecsimple")])
1787 (define_insn "altivec_dstst"
1788 [(unspec [(match_operand 0 "register_operand" "b")
1789 (match_operand:SI 1 "register_operand" "r")
1790 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1791 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1793 [(set_attr "type" "vecsimple")])
1795 (define_insn "altivec_dststt"
1796 [(unspec [(match_operand 0 "register_operand" "b")
1797 (match_operand:SI 1 "register_operand" "r")
1798 (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1799 "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1801 [(set_attr "type" "vecsimple")])
1803 (define_insn "altivec_lvsl"
1804 [(set (match_operand:V16QI 0 "register_operand" "=v")
1805 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] UNSPEC_LVSL))]
1808 [(set_attr "type" "vecload")])
1810 (define_insn "altivec_lvsr"
1811 [(set (match_operand:V16QI 0 "register_operand" "=v")
1812 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] UNSPEC_LVSR))]
1815 [(set_attr "type" "vecload")])
1817 (define_expand "build_vector_mask_for_load"
1818 [(set (match_operand:V16QI 0 "register_operand" "=v")
1819 (unspec:V16QI [(match_operand 1 "memory_operand" "m")] UNSPEC_LVSR))]
1826 gcc_assert (GET_CODE (operands[1]) == MEM);
1828 addr = XEXP (operands[1], 0);
1829 temp = gen_reg_rtx (GET_MODE (addr));
1830 emit_insn (gen_rtx_SET (VOIDmode, temp,
1831 gen_rtx_NEG (GET_MODE (addr), addr)));
1832 emit_insn (gen_altivec_lvsr (operands[0],
1833 gen_rtx_MEM (GET_MODE (operands[1]), temp)));
1837 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1838 ;; identical rtl but different instructions-- and gcc gets confused.
1840 (define_insn "altivec_lve<VI_char>x"
1842 [(set (match_operand:VI 0 "register_operand" "=v")
1843 (match_operand:VI 1 "memory_operand" "m"))
1844 (unspec [(const_int 0)] UNSPEC_LVE)])]
1846 "lve<VI_char>x %0,%y1"
1847 [(set_attr "type" "vecload")])
1849 (define_insn "*altivec_lvesfx"
1851 [(set (match_operand:V4SF 0 "register_operand" "=v")
1852 (match_operand:V4SF 1 "memory_operand" "m"))
1853 (unspec [(const_int 0)] UNSPEC_LVE)])]
1856 [(set_attr "type" "vecload")])
1858 (define_insn "altivec_lvxl"
1860 [(set (match_operand:V4SI 0 "register_operand" "=v")
1861 (match_operand:V4SI 1 "memory_operand" "m"))
1862 (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1865 [(set_attr "type" "vecload")])
1867 (define_insn "altivec_lvx"
1868 [(set (match_operand:V4SI 0 "register_operand" "=v")
1869 (match_operand:V4SI 1 "memory_operand" "m"))]
1872 [(set_attr "type" "vecload")])
1874 (define_insn "altivec_stvx"
1876 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1877 (match_operand:V4SI 1 "register_operand" "v"))
1878 (unspec [(const_int 0)] UNSPEC_STVX)])]
1881 [(set_attr "type" "vecstore")])
1883 (define_insn "altivec_stvxl"
1885 [(set (match_operand:V4SI 0 "memory_operand" "=m")
1886 (match_operand:V4SI 1 "register_operand" "v"))
1887 (unspec [(const_int 0)] UNSPEC_STVXL)])]
1890 [(set_attr "type" "vecstore")])
1892 (define_insn "altivec_stve<VI_char>x"
1894 [(set (match_operand:VI 0 "memory_operand" "=m")
1895 (match_operand:VI 1 "register_operand" "v"))
1896 (unspec [(const_int 0)] UNSPEC_STVE)])]
1898 "stve<VI_char>x %1,%y0"
1899 [(set_attr "type" "vecstore")])
1901 (define_insn "*altivec_stvesfx"
1903 [(set (match_operand:V4SF 0 "memory_operand" "=m")
1904 (match_operand:V4SF 1 "register_operand" "v"))
1905 (unspec [(const_int 0)] UNSPEC_STVE)])]
1908 [(set_attr "type" "vecstore")])
1911 ;; vspltis? SCRATCH0,0
1912 ;; vsubu?m SCRATCH2,SCRATCH1,%1
1913 ;; vmaxs? %0,%1,SCRATCH2"
1914 (define_expand "abs<mode>2"
1915 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1917 (minus:VI (match_dup 2)
1918 (match_operand:VI 1 "register_operand" "v")))
1919 (set (match_operand:VI 0 "register_operand" "=v")
1920 (smax:VI (match_dup 1) (match_dup 3)))]
1923 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1924 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1928 ;; vspltisw SCRATCH1,-1
1929 ;; vslw SCRATCH2,SCRATCH1,SCRATCH1
1930 ;; vandc %0,%1,SCRATCH2
1931 (define_expand "absv4sf2"
1933 (vec_duplicate:V4SF (float:SF (const_int -1))))
1935 (unspec:V4SF [(match_dup 2) (match_dup 2)] UNSPEC_VSLW))
1936 (set (match_operand:V4SF 0 "register_operand" "=v")
1937 (and:V4SF (not:V4SF (match_dup 3))
1938 (match_operand:V4SF 1 "register_operand" "v")))]
1941 operands[2] = gen_reg_rtx (V4SFmode);
1942 operands[3] = gen_reg_rtx (V4SFmode);
1946 ;; vspltis? SCRATCH0,0
1947 ;; vsubs?s SCRATCH2,SCRATCH1,%1
1948 ;; vmaxs? %0,%1,SCRATCH2"
1949 (define_expand "altivec_abss_<mode>"
1950 [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1951 (parallel [(set (match_dup 3)
1952 (unspec:VI [(match_dup 2)
1953 (match_operand:VI 1 "register_operand" "v")]
1955 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
1956 (set (match_operand:VI 0 "register_operand" "=v")
1957 (smax:VI (match_dup 1) (match_dup 3)))]
1960 operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1961 operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1964 ;; Vector shift left in bits. Currently supported ony for shift
1965 ;; amounts that can be expressed as byte shifts (divisible by 8).
1966 ;; General shift amounts can be supported using vslo + vsl. We're
1967 ;; not expecting to see these yet (the vectorizer currently
1968 ;; generates only shifts divisible by byte_size).
1969 (define_expand "vec_shl_<mode>"
1970 [(set (match_operand:V 0 "register_operand" "=v")
1971 (unspec:V [(match_operand:V 1 "register_operand" "v")
1972 (match_operand:QI 2 "reg_or_short_operand" "")]
1977 rtx bitshift = operands[2];
1978 rtx byteshift = gen_reg_rtx (QImode);
1979 HOST_WIDE_INT bitshift_val;
1980 HOST_WIDE_INT byteshift_val;
1982 if (! CONSTANT_P (bitshift))
1984 bitshift_val = INTVAL (bitshift);
1985 if (bitshift_val & 0x7)
1987 byteshift_val = bitshift_val >> 3;
1988 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
1989 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
1994 ;; Vector shift left in bits. Currently supported ony for shift
1995 ;; amounts that can be expressed as byte shifts (divisible by 8).
1996 ;; General shift amounts can be supported using vsro + vsr. We're
1997 ;; not expecting to see these yet (the vectorizer currently
1998 ;; generates only shifts divisible by byte_size).
1999 (define_expand "vec_shr_<mode>"
2000 [(set (match_operand:V 0 "register_operand" "=v")
2001 (unspec:V [(match_operand:V 1 "register_operand" "v")
2002 (match_operand:QI 2 "reg_or_short_operand" "")]
2007 rtx bitshift = operands[2];
2008 rtx byteshift = gen_reg_rtx (QImode);
2009 HOST_WIDE_INT bitshift_val;
2010 HOST_WIDE_INT byteshift_val;
2012 if (! CONSTANT_P (bitshift))
2014 bitshift_val = INTVAL (bitshift);
2015 if (bitshift_val & 0x7)
2017 byteshift_val = 16 - (bitshift_val >> 3);
2018 byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2019 emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2024 (define_insn "altivec_vsumsws_nomode"
2025 [(set (match_operand 0 "register_operand" "=v")
2026 (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2027 (match_operand:V4SI 2 "register_operand" "v")]
2029 (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2032 [(set_attr "type" "veccomplex")])
2034 (define_expand "reduc_splus_<mode>"
2035 [(set (match_operand:VIshort 0 "register_operand" "=v")
2036 (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2037 UNSPEC_REDUC_PLUS))]
2041 rtx vzero = gen_reg_rtx (V4SImode);
2042 rtx vtmp1 = gen_reg_rtx (V4SImode);
2044 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2045 emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2046 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2050 (define_expand "reduc_uplus_v16qi"
2051 [(set (match_operand:V16QI 0 "register_operand" "=v")
2052 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2053 UNSPEC_REDUC_PLUS))]
2057 rtx vzero = gen_reg_rtx (V4SImode);
2058 rtx vtmp1 = gen_reg_rtx (V4SImode);
2060 emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2061 emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2062 emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2066 (define_insn "vec_realign_load_<mode>"
2067 [(set (match_operand:V 0 "register_operand" "=v")
2068 (unspec:V [(match_operand:V 1 "register_operand" "v")
2069 (match_operand:V 2 "register_operand" "v")
2070 (match_operand:V16QI 3 "register_operand" "v")]
2071 UNSPEC_REALIGN_LOAD))]
2074 [(set_attr "type" "vecperm")])