gcc/config/rs6000/altivec.md

   1 ;; AltiVec patterns.
   2 ;; Copyright (C) 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
   3 ;; Contributed by Aldy Hernandez (aldy@quesejoda.com)
   4
   5 ;; This file is part of GCC.
   6
   7 ;; GCC is free software; you can redistribute it and/or modify it
   8 ;; under the terms of the GNU General Public License as published
   9 ;; by the Free Software Foundation; either version 2, or (at your
  10 ;; option) any later version.
  11
  12 ;; GCC is distributed in the hope that it will be useful, but WITHOUT
  13 ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14 ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15 ;; License for more details.
  16
  17 ;; You should have received a copy of the GNU General Public License
  18 ;; along with GCC; see the file COPYING.  If not, write to the
  19 ;; Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20 ;; MA 02110-1301, USA.
  21
  22 (define_constants
  23   [(UNSPEC_VCMPBFP       50)
  24    (UNSPEC_VCMPEQUB      51)
  25    (UNSPEC_VCMPEQUH      52)
  26    (UNSPEC_VCMPEQUW      53)
  27    (UNSPEC_VCMPEQFP      54)
  28    (UNSPEC_VCMPGEFP      55)
  29    (UNSPEC_VCMPGTUB      56)
  30    (UNSPEC_VCMPGTSB      57)
  31    (UNSPEC_VCMPGTUH      58)
  32    (UNSPEC_VCMPGTSH      59)
  33    (UNSPEC_VCMPGTUW      60)
  34    (UNSPEC_VCMPGTSW      61)
  35    (UNSPEC_VCMPGTFP      62)
  36    (UNSPEC_VMSUMU        65)
  37    (UNSPEC_VMSUMM        66)
  38    (UNSPEC_VMSUMSHM      68)
  39    (UNSPEC_VMSUMUHS      69)
  40    (UNSPEC_VMSUMSHS      70)
  41    (UNSPEC_VMHADDSHS     71)
  42    (UNSPEC_VMHRADDSHS    72)
  43    (UNSPEC_VMLADDUHM     73)
  44    (UNSPEC_VADDCUW       75)
  45    (UNSPEC_VADDU         76)
  46    (UNSPEC_VADDS         77)
  47    (UNSPEC_VAVGU         80)
  48    (UNSPEC_VAVGS         81)
  49    (UNSPEC_VMULEUB       83)
  50    (UNSPEC_VMULESB       84)
  51    (UNSPEC_VMULEUH       85)
  52    (UNSPEC_VMULESH       86)
  53    (UNSPEC_VMULOUB       87)
  54    (UNSPEC_VMULOSB       88)
  55    (UNSPEC_VMULOUH       89)
  56    (UNSPEC_VMULOSH       90)
  57    (UNSPEC_VPKUHUM       93)
  58    (UNSPEC_VPKUWUM       94)
  59    (UNSPEC_VPKPX         95)
  60    (UNSPEC_VPKSHSS       97)
  61    (UNSPEC_VPKSWSS       99)
  62    (UNSPEC_VPKUHUS      100)
  63    (UNSPEC_VPKSHUS      101)
  64    (UNSPEC_VPKUWUS      102)
  65    (UNSPEC_VPKSWUS      103)
  66    (UNSPEC_VRL          104)
  67    (UNSPEC_VSL          107)
  68    (UNSPEC_VSLV4SI      110)
  69    (UNSPEC_VSLO         111)
  70    (UNSPEC_VSR          118)
  71    (UNSPEC_VSRO         119)
  72    (UNSPEC_VSUBCUW      124)
  73    (UNSPEC_VSUBU        125)
  74    (UNSPEC_VSUBS        126)
  75    (UNSPEC_VSUM4UBS     131)
  76    (UNSPEC_VSUM4S       132)
  77    (UNSPEC_VSUM2SWS     134)
  78    (UNSPEC_VSUMSWS      135)
  79    (UNSPEC_VPERM        144)
  80    (UNSPEC_VRFIP        148)
  81    (UNSPEC_VRFIN        149)
  82    (UNSPEC_VRFIM        150)
  83    (UNSPEC_VCFUX        151)
  84    (UNSPEC_VCFSX        152)
  85    (UNSPEC_VCTUXS       153)
  86    (UNSPEC_VCTSXS       154)
  87    (UNSPEC_VLOGEFP      155)
  88    (UNSPEC_VEXPTEFP     156)
  89    (UNSPEC_VRSQRTEFP    157)
  90    (UNSPEC_VREFP        158)
  91    (UNSPEC_VSEL4SI      159)
  92    (UNSPEC_VSEL4SF      160)
  93    (UNSPEC_VSEL8HI      161)
  94    (UNSPEC_VSEL16QI     162)
  95    (UNSPEC_VLSDOI       163)
  96    (UNSPEC_VUPKHSB      167)
  97    (UNSPEC_VUPKHPX      168)
  98    (UNSPEC_VUPKHSH      169)
  99    (UNSPEC_VUPKLSB      170)
 100    (UNSPEC_VUPKLPX      171)
 101    (UNSPEC_VUPKLSH      172)
 102    (UNSPEC_PREDICATE    173)
 103    (UNSPEC_DST          190)
 104    (UNSPEC_DSTT         191)
 105    (UNSPEC_DSTST        192)
 106    (UNSPEC_DSTSTT       193)
 107    (UNSPEC_LVSL         194)
 108    (UNSPEC_LVSR         195)
 109    (UNSPEC_LVE          196)
 110    (UNSPEC_STVX         201)
 111    (UNSPEC_STVXL        202)
 112    (UNSPEC_STVE         203)
 113    (UNSPEC_SET_VSCR     213)
 114    (UNSPEC_GET_VRSAVE   214)
 115    (UNSPEC_REALIGN_LOAD 215)
 116    (UNSPEC_REDUC_PLUS   217)
 117    (UNSPEC_VECSH        219)
 118    (UNSPEC_VCOND_V4SI   301)
 119    (UNSPEC_VCOND_V4SF   302)
 120    (UNSPEC_VCOND_V8HI   303)
 121    (UNSPEC_VCOND_V16QI  304)
 122    (UNSPEC_VCONDU_V4SI  305)
 123    (UNSPEC_VCONDU_V8HI  306)
 124    (UNSPEC_VCONDU_V16QI 307)
 125    (UNSPEC_VMULWHUB     308)
 126    (UNSPEC_VMULWLUB     309)
 127    (UNSPEC_VMULWHSB     310)
 128    (UNSPEC_VMULWLSB     311)
 129    (UNSPEC_VMULWHUH     312)
 130    (UNSPEC_VMULWLUH     313)
 131    (UNSPEC_VMULWHSH     314)
 132    (UNSPEC_VMULWLSH     315)
 133    (UNSPEC_VUPKHUB      316)
 134    (UNSPEC_VUPKHUH      317)
 135    (UNSPEC_VUPKLUB      318)
 136    (UNSPEC_VUPKLUH      319)
 137    (UNSPEC_VPERMSI      320)
 138    (UNSPEC_VPERMHI      321)
 139    ])
 140
 141 (define_constants
 142   [(UNSPECV_SET_VRSAVE   30)
 143    (UNSPECV_MTVSCR      186)
 144    (UNSPECV_MFVSCR      187)
 145    (UNSPECV_DSSALL      188)
 146    (UNSPECV_DSS         189)
 147   ])
 148
 149 ;; Vec int modes
 150 (define_mode_macro VI [V4SI V8HI V16QI])
 151 ;; Short vec in modes
 152 (define_mode_macro VIshort [V8HI V16QI])
 153 ;; Vec float modes
 154 (define_mode_macro VF [V4SF])
 155 ;; Vec modes, pity mode macros are not composable
 156 (define_mode_macro V [V4SI V8HI V16QI V4SF])
 157
 158 (define_mode_attr VI_char [(V4SI "w") (V8HI "h") (V16QI "b")])
 159
 160 ;; Generic LVX load instruction.
 161 (define_insn "altivec_lvx_<mode>"
 162   [(set (match_operand:V 0 "altivec_register_operand" "=v")
 163         (match_operand:V 1 "memory_operand" "Z"))]
 164   "TARGET_ALTIVEC"
 165   "lvx %0,%y1"
 166   [(set_attr "type" "vecload")])
 167
 168 ;; Generic STVX store instruction.
 169 (define_insn "altivec_stvx_<mode>"
 170   [(set (match_operand:V 0 "memory_operand" "=Z")
 171         (match_operand:V 1 "altivec_register_operand" "v"))]
 172   "TARGET_ALTIVEC"
 173   "stvx %1,%y0"
 174   [(set_attr "type" "vecstore")])
 175
 176 ;; Vector move instructions.
 177 (define_expand "mov<mode>"
 178   [(set (match_operand:V 0 "nonimmediate_operand" "")
 179         (match_operand:V 1 "any_operand" ""))]
 180   "TARGET_ALTIVEC"
 181 {
 182   rs6000_emit_move (operands[0], operands[1], <MODE>mode);
 183   DONE;
 184 })
 185
 186 (define_insn "*mov<mode>_internal"
 187   [(set (match_operand:V 0 "nonimmediate_operand" "=Z,v,v,o,r,r,v")
 188         (match_operand:V 1 "input_operand" "v,Z,v,r,o,r,W"))]
 189   "TARGET_ALTIVEC
 190    && (register_operand (operands[0], <MODE>mode)
 191        || register_operand (operands[1], <MODE>mode))"
 192 {
 193   switch (which_alternative)
 194     {
 195     case 0: return "stvx %1,%y0";
 196     case 1: return "lvx %0,%y1";
 197     case 2: return "vor %0,%1,%1";
 198     case 3: return "#";
 199     case 4: return "#";
 200     case 5: return "#";
 201     case 6: return output_vec_const_move (operands);
 202     default: gcc_unreachable ();
 203     }
 204 }
 205   [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
 206
 207 (define_split
 208   [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
 209         (match_operand:V4SI 1 "input_operand" ""))]
 210   "TARGET_ALTIVEC && reload_completed
 211    && gpr_or_gpr_p (operands[0], operands[1])"
 212   [(pc)]
 213 {
 214   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 215 })
 216
 217 (define_split
 218   [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
 219         (match_operand:V8HI 1 "input_operand" ""))]
 220   "TARGET_ALTIVEC && reload_completed
 221    && gpr_or_gpr_p (operands[0], operands[1])"
 222   [(pc)]
 223 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 224
 225 (define_split
 226   [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
 227         (match_operand:V16QI 1 "input_operand" ""))]
 228   "TARGET_ALTIVEC && reload_completed
 229    && gpr_or_gpr_p (operands[0], operands[1])"
 230   [(pc)]
 231 { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
 232
 233 (define_split
 234   [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
 235         (match_operand:V4SF 1 "input_operand" ""))]
 236   "TARGET_ALTIVEC && reload_completed
 237    && gpr_or_gpr_p (operands[0], operands[1])"
 238   [(pc)]
 239 {
 240   rs6000_split_multireg_move (operands[0], operands[1]); DONE;
 241 })
 242
 243 (define_split
 244   [(set (match_operand:VI 0 "altivec_register_operand" "")
 245         (match_operand:VI 1 "easy_vector_constant_add_self" ""))]
 246   "TARGET_ALTIVEC && reload_completed"
 247   [(set (match_dup 0) (match_dup 3))
 248    (set (match_dup 0) (plus:VI (match_dup 0)
 249                                (match_dup 0)))]
 250 {
 251   rtx dup = gen_easy_altivec_constant (operands[1]);
 252   rtx const_vec;
 253
 254   /* Divide the operand of the resulting VEC_DUPLICATE, and use
 255      simplify_rtx to make a CONST_VECTOR.  */
 256   XEXP (dup, 0) = simplify_const_binary_operation (ASHIFTRT, QImode,
 257                                                    XEXP (dup, 0), const1_rtx);
 258   const_vec = simplify_rtx (dup);
 259
 260   if (GET_MODE (const_vec) == <MODE>mode)
 261     operands[3] = const_vec;
 262   else
 263     operands[3] = gen_lowpart (<MODE>mode, const_vec);
 264 })
 265
 266 (define_insn "get_vrsave_internal"
 267   [(set (match_operand:SI 0 "register_operand" "=r")
 268         (unspec:SI [(reg:SI 109)] UNSPEC_GET_VRSAVE))]
 269   "TARGET_ALTIVEC"
 270 {
 271   if (TARGET_MACHO)
 272      return "mfspr %0,256";
 273   else
 274      return "mfvrsave %0";
 275 }
 276   [(set_attr "type" "*")])
 277
 278 (define_insn "*set_vrsave_internal"
 279   [(match_parallel 0 "vrsave_operation"
 280      [(set (reg:SI 109)
 281            (unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
 282                                 (reg:SI 109)] UNSPECV_SET_VRSAVE))])]
 283   "TARGET_ALTIVEC"
 284 {
 285   if (TARGET_MACHO)
 286     return "mtspr 256,%1";
 287   else
 288     return "mtvrsave %1";
 289 }
 290   [(set_attr "type" "*")])
 291
 292 (define_insn "*save_world"
 293  [(match_parallel 0 "save_world_operation"
 294                   [(clobber (match_operand:SI 1 "register_operand" "=l"))
 295                    (use (match_operand:SI 2 "call_operand" "s"))])]
 296  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 297  "bl %z2"
 298   [(set_attr "type" "branch")
 299    (set_attr "length" "4")])
 300
 301 (define_insn "*restore_world"
 302  [(match_parallel 0 "restore_world_operation"
 303                   [(return)
 304                    (use (match_operand:SI 1 "register_operand" "l"))
 305                    (use (match_operand:SI 2 "call_operand" "s"))
 306                    (clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
 307  "TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
 308  "b %z2")
 309
 310 ;; Simple binary operations.
 311
 312 ;; add
 313 (define_insn "add<mode>3"
 314   [(set (match_operand:VI 0 "register_operand" "=v")
 315         (plus:VI (match_operand:VI 1 "register_operand" "v")
 316                  (match_operand:VI 2 "register_operand" "v")))]
 317   "TARGET_ALTIVEC"
 318   "vaddu<VI_char>m %0,%1,%2"
 319   [(set_attr "type" "vecsimple")])
 320
 321 (define_insn "addv4sf3"
 322   [(set (match_operand:V4SF 0 "register_operand" "=v")
 323         (plus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 324                    (match_operand:V4SF 2 "register_operand" "v")))]
 325   "TARGET_ALTIVEC"
 326   "vaddfp %0,%1,%2"
 327   [(set_attr "type" "vecfloat")])
 328
 329 (define_insn "altivec_vaddcuw"
 330   [(set (match_operand:V4SI 0 "register_operand" "=v")
 331         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 332                       (match_operand:V4SI 2 "register_operand" "v")]
 333                      UNSPEC_VADDCUW))]
 334   "TARGET_ALTIVEC"
 335   "vaddcuw %0,%1,%2"
 336   [(set_attr "type" "vecsimple")])
 337
 338 (define_insn "altivec_vaddu<VI_char>s"
 339   [(set (match_operand:VI 0 "register_operand" "=v")
 340         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 341                     (match_operand:VI 2 "register_operand" "v")]
 342                    UNSPEC_VADDU))
 343    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 344   "TARGET_ALTIVEC"
 345   "vaddu<VI_char>s %0,%1,%2"
 346   [(set_attr "type" "vecsimple")])
 347
 348 (define_insn "altivec_vadds<VI_char>s"
 349   [(set (match_operand:VI 0 "register_operand" "=v")
 350         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 351                     (match_operand:VI 2 "register_operand" "v")]
 352                    UNSPEC_VADDS))
 353    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 354   "TARGET_ALTIVEC"
 355   "vadds<VI_char>s %0,%1,%2"
 356   [(set_attr "type" "vecsimple")])
 357
 358 ;; sub
 359 (define_insn "sub<mode>3"
 360   [(set (match_operand:VI 0 "register_operand" "=v")
 361         (minus:VI (match_operand:VI 1 "register_operand" "v")
 362                   (match_operand:VI 2 "register_operand" "v")))]
 363   "TARGET_ALTIVEC"
 364   "vsubu<VI_char>m %0,%1,%2"
 365   [(set_attr "type" "vecsimple")])
 366
 367 (define_insn "subv4sf3"
 368   [(set (match_operand:V4SF 0 "register_operand" "=v")
 369         (minus:V4SF (match_operand:V4SF 1 "register_operand" "v")
 370                     (match_operand:V4SF 2 "register_operand" "v")))]
 371   "TARGET_ALTIVEC"
 372   "vsubfp %0,%1,%2"
 373   [(set_attr "type" "vecfloat")])
 374
 375 (define_insn "altivec_vsubcuw"
 376   [(set (match_operand:V4SI 0 "register_operand" "=v")
 377         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 378                       (match_operand:V4SI 2 "register_operand" "v")]
 379                      UNSPEC_VSUBCUW))]
 380   "TARGET_ALTIVEC"
 381   "vsubcuw %0,%1,%2"
 382   [(set_attr "type" "vecsimple")])
 383
 384 (define_insn "altivec_vsubu<VI_char>s"
 385   [(set (match_operand:VI 0 "register_operand" "=v")
 386         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 387                     (match_operand:VI 2 "register_operand" "v")]
 388                    UNSPEC_VSUBU))
 389    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 390   "TARGET_ALTIVEC"
 391   "vsubu<VI_char>s %0,%1,%2"
 392   [(set_attr "type" "vecsimple")])
 393
 394 (define_insn "altivec_vsubs<VI_char>s"
 395   [(set (match_operand:VI 0 "register_operand" "=v")
 396         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 397                     (match_operand:VI 2 "register_operand" "v")]
 398                    UNSPEC_VSUBS))
 399    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 400   "TARGET_ALTIVEC"
 401   "vsubs<VI_char>s %0,%1,%2"
 402   [(set_attr "type" "vecsimple")])
 403
 404 ;;
 405 (define_insn "altivec_vavgu<VI_char>"
 406   [(set (match_operand:VI 0 "register_operand" "=v")
 407         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 408                     (match_operand:VI 2 "register_operand" "v")]
 409                    UNSPEC_VAVGU))]
 410   "TARGET_ALTIVEC"
 411   "vavgu<VI_char> %0,%1,%2"
 412   [(set_attr "type" "vecsimple")])
 413
 414 (define_insn "altivec_vavgs<VI_char>"
 415   [(set (match_operand:VI 0 "register_operand" "=v")
 416         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
 417                     (match_operand:VI 2 "register_operand" "v")]
 418                    UNSPEC_VAVGS))]
 419   "TARGET_ALTIVEC"
 420   "vavgs<VI_char> %0,%1,%2"
 421   [(set_attr "type" "vecsimple")])
 422
 423 (define_insn "altivec_vcmpbfp"
 424   [(set (match_operand:V4SI 0 "register_operand" "=v")
 425         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 426                       (match_operand:V4SF 2 "register_operand" "v")]
 427                       UNSPEC_VCMPBFP))]
 428   "TARGET_ALTIVEC"
 429   "vcmpbfp %0,%1,%2"
 430   [(set_attr "type" "veccmp")])
 431
 432 (define_insn "altivec_vcmpequb"
 433   [(set (match_operand:V16QI 0 "register_operand" "=v")
 434         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 435                        (match_operand:V16QI 2 "register_operand" "v")]
 436                        UNSPEC_VCMPEQUB))]
 437   "TARGET_ALTIVEC"
 438   "vcmpequb %0,%1,%2"
 439   [(set_attr "type" "vecsimple")])
 440
 441 (define_insn "altivec_vcmpequh"
 442   [(set (match_operand:V8HI 0 "register_operand" "=v")
 443         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 444                       (match_operand:V8HI 2 "register_operand" "v")]
 445                       UNSPEC_VCMPEQUH))]
 446   "TARGET_ALTIVEC"
 447   "vcmpequh %0,%1,%2"
 448   [(set_attr "type" "vecsimple")])
 449
 450 (define_insn "altivec_vcmpequw"
 451   [(set (match_operand:V4SI 0 "register_operand" "=v")
 452         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 453                       (match_operand:V4SI 2 "register_operand" "v")]
 454                       UNSPEC_VCMPEQUW))]
 455   "TARGET_ALTIVEC"
 456   "vcmpequw %0,%1,%2"
 457   [(set_attr "type" "vecsimple")])
 458
 459 (define_insn "altivec_vcmpeqfp"
 460   [(set (match_operand:V4SI 0 "register_operand" "=v")
 461         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 462                       (match_operand:V4SF 2 "register_operand" "v")]
 463                       UNSPEC_VCMPEQFP))]
 464   "TARGET_ALTIVEC"
 465   "vcmpeqfp %0,%1,%2"
 466   [(set_attr "type" "veccmp")])
 467
 468 (define_insn "altivec_vcmpgefp"
 469   [(set (match_operand:V4SI 0 "register_operand" "=v")
 470         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 471                       (match_operand:V4SF 2 "register_operand" "v")]
 472                      UNSPEC_VCMPGEFP))]
 473   "TARGET_ALTIVEC"
 474   "vcmpgefp %0,%1,%2"
 475   [(set_attr "type" "veccmp")])
 476
 477 (define_insn "altivec_vcmpgtub"
 478   [(set (match_operand:V16QI 0 "register_operand" "=v")
 479         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 480                        (match_operand:V16QI 2 "register_operand" "v")]
 481                       UNSPEC_VCMPGTUB))]
 482   "TARGET_ALTIVEC"
 483   "vcmpgtub %0,%1,%2"
 484   [(set_attr "type" "vecsimple")])
 485
 486 (define_insn "altivec_vcmpgtsb"
 487   [(set (match_operand:V16QI 0 "register_operand" "=v")
 488         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
 489                        (match_operand:V16QI 2 "register_operand" "v")]
 490                       UNSPEC_VCMPGTSB))]
 491   "TARGET_ALTIVEC"
 492   "vcmpgtsb %0,%1,%2"
 493   [(set_attr "type" "vecsimple")])
 494
 495 (define_insn "altivec_vcmpgtuh"
 496   [(set (match_operand:V8HI 0 "register_operand" "=v")
 497         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 498                       (match_operand:V8HI 2 "register_operand" "v")]
 499                      UNSPEC_VCMPGTUH))]
 500   "TARGET_ALTIVEC"
 501   "vcmpgtuh %0,%1,%2"
 502   [(set_attr "type" "vecsimple")])
 503
 504 (define_insn "altivec_vcmpgtsh"
 505   [(set (match_operand:V8HI 0 "register_operand" "=v")
 506         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 507                       (match_operand:V8HI 2 "register_operand" "v")]
 508                      UNSPEC_VCMPGTSH))]
 509   "TARGET_ALTIVEC"
 510   "vcmpgtsh %0,%1,%2"
 511   [(set_attr "type" "vecsimple")])
 512
 513 (define_insn "altivec_vcmpgtuw"
 514   [(set (match_operand:V4SI 0 "register_operand" "=v")
 515         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 516                       (match_operand:V4SI 2 "register_operand" "v")]
 517                      UNSPEC_VCMPGTUW))]
 518   "TARGET_ALTIVEC"
 519   "vcmpgtuw %0,%1,%2"
 520   [(set_attr "type" "vecsimple")])
 521
 522 (define_insn "altivec_vcmpgtsw"
 523   [(set (match_operand:V4SI 0 "register_operand" "=v")
 524         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
 525                       (match_operand:V4SI 2 "register_operand" "v")]
 526                      UNSPEC_VCMPGTSW))]
 527   "TARGET_ALTIVEC"
 528   "vcmpgtsw %0,%1,%2"
 529   [(set_attr "type" "vecsimple")])
 530
 531 (define_insn "altivec_vcmpgtfp"
 532   [(set (match_operand:V4SI 0 "register_operand" "=v")
 533         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
 534                       (match_operand:V4SF 2 "register_operand" "v")]
 535                      UNSPEC_VCMPGTFP))]
 536   "TARGET_ALTIVEC"
 537   "vcmpgtfp %0,%1,%2"
 538   [(set_attr "type" "veccmp")])
 539
 540 ;; Fused multiply add
 541 (define_insn "altivec_vmaddfp"
 542   [(set (match_operand:V4SF 0 "register_operand" "=v")
 543         (plus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 544                               (match_operand:V4SF 2 "register_operand" "v"))
 545                    (match_operand:V4SF 3 "register_operand" "v")))]
 546   "TARGET_ALTIVEC"
 547   "vmaddfp %0,%1,%2,%3"
 548   [(set_attr "type" "vecfloat")])
 549
 550 ;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
 551
 552 (define_expand "mulv4sf3"
 553   [(use (match_operand:V4SF 0 "register_operand" ""))
 554    (use (match_operand:V4SF 1 "register_operand" ""))
 555    (use (match_operand:V4SF 2 "register_operand" ""))]
 556   "TARGET_ALTIVEC && TARGET_FUSED_MADD"
 557   "
 558 {
 559   rtx neg0;
 560
 561   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
 562   neg0 = gen_reg_rtx (V4SImode);
 563   emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
 564   emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
 565
 566   /* Use the multiply-add.  */
 567   emit_insn (gen_altivec_vmaddfp (operands[0], operands[1], operands[2],
 568                                   gen_lowpart (V4SFmode, neg0)));
 569   DONE;
 570 }")
 571
 572 ;; 32 bit integer multiplication
 573 ;; A_high = Operand_0 & 0xFFFF0000 >> 16
 574 ;; A_low = Operand_0 & 0xFFFF
 575 ;; B_high = Operand_1 & 0xFFFF0000 >> 16
 576 ;; B_low = Operand_1 & 0xFFFF
 577 ;; result = A_low * B_low + (A_high * B_low + B_high * A_low) << 16
 578
 579 ;; (define_insn "mulv4si3"
 580 ;;   [(set (match_operand:V4SI 0 "register_operand" "=v")
 581 ;;         (mult:V4SI (match_operand:V4SI 1 "register_operand" "v")
 582 ;;                    (match_operand:V4SI 2 "register_operand" "v")))]
 583 (define_expand "mulv4si3"
 584   [(use (match_operand:V4SI 0 "register_operand" ""))
 585    (use (match_operand:V4SI 1 "register_operand" ""))
 586    (use (match_operand:V4SI 2 "register_operand" ""))]
 587    "TARGET_ALTIVEC"
 588    "
 589  {
 590    rtx zero;
 591    rtx swap;
 592    rtx small_swap;
 593    rtx sixteen;
 594    rtx one;
 595    rtx two;
 596    rtx low_product;
 597    rtx high_product;
 598
 599    zero = gen_reg_rtx (V4SImode);
 600    emit_insn (gen_altivec_vspltisw (zero, const0_rtx));
 601
 602    sixteen = gen_reg_rtx (V4SImode);
 603    emit_insn (gen_altivec_vspltisw (sixteen,  gen_rtx_CONST_INT (V4SImode, -16)));
 604
 605    swap = gen_reg_rtx (V4SImode);
 606    emit_insn (gen_altivec_vrlw (swap, operands[2], sixteen));
 607
 608    one = gen_reg_rtx (V8HImode);
 609    convert_move (one, operands[1], 0);
 610
 611    two = gen_reg_rtx (V8HImode);
 612    convert_move (two, operands[2], 0);
 613
 614    small_swap = gen_reg_rtx (V8HImode);
 615    convert_move (small_swap, swap, 0);
 616
 617    low_product = gen_reg_rtx (V4SImode);
 618    emit_insn (gen_altivec_vmulouh (low_product, one, two));
 619
 620    high_product = gen_reg_rtx (V4SImode);
 621    emit_insn (gen_altivec_vmsumuhm (high_product, one, small_swap, zero));
 622
 623    emit_insn (gen_altivec_vslw (high_product, high_product, sixteen));
 624
 625    emit_insn (gen_addv4si3 (operands[0], high_product, low_product));
 626
 627    DONE;
 628  }")
 629
 630
 631 ;; Fused multiply subtract
 632 (define_insn "altivec_vnmsubfp"
 633   [(set (match_operand:V4SF 0 "register_operand" "=v")
 634         (neg:V4SF (minus:V4SF (mult:V4SF (match_operand:V4SF 1 "register_operand" "v")
 635                                (match_operand:V4SF 2 "register_operand" "v"))
 636                     (match_operand:V4SF 3 "register_operand" "v"))))]
 637   "TARGET_ALTIVEC"
 638   "vnmsubfp %0,%1,%2,%3"
 639   [(set_attr "type" "vecfloat")])
 640
 641 (define_insn "altivec_vmsumu<VI_char>m"
 642   [(set (match_operand:V4SI 0 "register_operand" "=v")
 643         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 644                       (match_operand:VIshort 2 "register_operand" "v")
 645                       (match_operand:V4SI 3 "register_operand" "v")]
 646                      UNSPEC_VMSUMU))]
 647   "TARGET_ALTIVEC"
 648   "vmsumu<VI_char>m %0,%1,%2,%3"
 649   [(set_attr "type" "veccomplex")])
 650
 651 (define_insn "altivec_vmsumm<VI_char>m"
 652   [(set (match_operand:V4SI 0 "register_operand" "=v")
 653         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
 654                       (match_operand:VIshort 2 "register_operand" "v")
 655                       (match_operand:V4SI 3 "register_operand" "v")]
 656                      UNSPEC_VMSUMM))]
 657   "TARGET_ALTIVEC"
 658   "vmsumm<VI_char>m %0,%1,%2,%3"
 659   [(set_attr "type" "veccomplex")])
 660
 661 (define_insn "altivec_vmsumshm"
 662   [(set (match_operand:V4SI 0 "register_operand" "=v")
 663         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 664                       (match_operand:V8HI 2 "register_operand" "v")
 665                       (match_operand:V4SI 3 "register_operand" "v")]
 666                      UNSPEC_VMSUMSHM))]
 667   "TARGET_ALTIVEC"
 668   "vmsumshm %0,%1,%2,%3"
 669   [(set_attr "type" "veccomplex")])
 670
 671 (define_insn "altivec_vmsumuhs"
 672   [(set (match_operand:V4SI 0 "register_operand" "=v")
 673         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 674                       (match_operand:V8HI 2 "register_operand" "v")
 675                       (match_operand:V4SI 3 "register_operand" "v")]
 676                      UNSPEC_VMSUMUHS))
 677    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 678   "TARGET_ALTIVEC"
 679   "vmsumuhs %0,%1,%2,%3"
 680   [(set_attr "type" "veccomplex")])
 681
 682 (define_insn "altivec_vmsumshs"
 683   [(set (match_operand:V4SI 0 "register_operand" "=v")
 684         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 685                       (match_operand:V8HI 2 "register_operand" "v")
 686                       (match_operand:V4SI 3 "register_operand" "v")]
 687                      UNSPEC_VMSUMSHS))
 688    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 689   "TARGET_ALTIVEC"
 690   "vmsumshs %0,%1,%2,%3"
 691   [(set_attr "type" "veccomplex")])
 692
 693 ;; max
 694
 695 (define_insn "umax<mode>3"
 696   [(set (match_operand:VI 0 "register_operand" "=v")
 697         (umax:VI (match_operand:VI 1 "register_operand" "v")
 698                  (match_operand:VI 2 "register_operand" "v")))]
 699   "TARGET_ALTIVEC"
 700   "vmaxu<VI_char> %0,%1,%2"
 701   [(set_attr "type" "vecsimple")])
 702
 703 (define_insn "smax<mode>3"
 704   [(set (match_operand:VI 0 "register_operand" "=v")
 705         (smax:VI (match_operand:VI 1 "register_operand" "v")
 706                  (match_operand:VI 2 "register_operand" "v")))]
 707   "TARGET_ALTIVEC"
 708   "vmaxs<VI_char> %0,%1,%2"
 709   [(set_attr "type" "vecsimple")])
 710
 711 (define_insn "smaxv4sf3"
 712   [(set (match_operand:V4SF 0 "register_operand" "=v")
 713         (smax:V4SF (match_operand:V4SF 1 "register_operand" "v")
 714                    (match_operand:V4SF 2 "register_operand" "v")))]
 715   "TARGET_ALTIVEC"
 716   "vmaxfp %0,%1,%2"
 717   [(set_attr "type" "veccmp")])
 718
 719 (define_insn "umin<mode>3"
 720   [(set (match_operand:VI 0 "register_operand" "=v")
 721         (umin:VI (match_operand:VI 1 "register_operand" "v")
 722                  (match_operand:VI 2 "register_operand" "v")))]
 723   "TARGET_ALTIVEC"
 724   "vminu<VI_char> %0,%1,%2"
 725   [(set_attr "type" "vecsimple")])
 726
 727 (define_insn "smin<mode>3"
 728   [(set (match_operand:VI 0 "register_operand" "=v")
 729         (smin:VI (match_operand:VI 1 "register_operand" "v")
 730                  (match_operand:VI 2 "register_operand" "v")))]
 731   "TARGET_ALTIVEC"
 732   "vmins<VI_char> %0,%1,%2"
 733   [(set_attr "type" "vecsimple")])
 734
 735 (define_insn "sminv4sf3"
 736   [(set (match_operand:V4SF 0 "register_operand" "=v")
 737         (smin:V4SF (match_operand:V4SF 1 "register_operand" "v")
 738                    (match_operand:V4SF 2 "register_operand" "v")))]
 739   "TARGET_ALTIVEC"
 740   "vminfp %0,%1,%2"
 741   [(set_attr "type" "veccmp")])
 742
 743 (define_insn "altivec_vmhaddshs"
 744   [(set (match_operand:V8HI 0 "register_operand" "=v")
 745         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 746                       (match_operand:V8HI 2 "register_operand" "v")
 747                       (match_operand:V8HI 3 "register_operand" "v")]
 748                      UNSPEC_VMHADDSHS))
 749    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 750   "TARGET_ALTIVEC"
 751   "vmhaddshs %0,%1,%2,%3"
 752   [(set_attr "type" "veccomplex")])
 753
 754 (define_insn "altivec_vmhraddshs"
 755   [(set (match_operand:V8HI 0 "register_operand" "=v")
 756         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 757                       (match_operand:V8HI 2 "register_operand" "v")
 758                       (match_operand:V8HI 3 "register_operand" "v")]
 759                      UNSPEC_VMHRADDSHS))
 760    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
 761   "TARGET_ALTIVEC"
 762   "vmhraddshs %0,%1,%2,%3"
 763   [(set_attr "type" "veccomplex")])
 764
 765 (define_insn "altivec_vmladduhm"
 766   [(set (match_operand:V8HI 0 "register_operand" "=v")
 767         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
 768                       (match_operand:V8HI 2 "register_operand" "v")
 769                       (match_operand:V8HI 3 "register_operand" "v")]
 770                      UNSPEC_VMLADDUHM))]
 771   "TARGET_ALTIVEC"
 772   "vmladduhm %0,%1,%2,%3"
 773   [(set_attr "type" "veccomplex")])
 774
 775 (define_insn "altivec_vmrghb"
 776   [(set (match_operand:V16QI 0 "register_operand" "=v")
 777         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 778                                            (parallel [(const_int 0)
 779                                                       (const_int 8)
 780                                                       (const_int 1)
 781                                                       (const_int 9)
 782                                                       (const_int 2)
 783                                                       (const_int 10)
 784                                                       (const_int 3)
 785                                                       (const_int 11)
 786                                                       (const_int 4)
 787                                                       (const_int 12)
 788                                                       (const_int 5)
 789                                                       (const_int 13)
 790                                                       (const_int 6)
 791                                                       (const_int 14)
 792                                                       (const_int 7)
 793                                                       (const_int 15)]))
 794                         (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 795                                            (parallel [(const_int 8)
 796                                                       (const_int 0)
 797                                                       (const_int 9)
 798                                                       (const_int 1)
 799                                                       (const_int 10)
 800                                                       (const_int 2)
 801                                                       (const_int 11)
 802                                                       (const_int 3)
 803                                                       (const_int 12)
 804                                                       (const_int 4)
 805                                                       (const_int 13)
 806                                                       (const_int 5)
 807                                                       (const_int 14)
 808                                                       (const_int 6)
 809                                                       (const_int 15)
 810                                                       (const_int 7)]))
 811                       (const_int 21845)))]
 812   "TARGET_ALTIVEC"
 813   "vmrghb %0,%1,%2"
 814   [(set_attr "type" "vecperm")])
 815
 816 (define_insn "altivec_vmrghh"
 817   [(set (match_operand:V8HI 0 "register_operand" "=v")
 818         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 819                                            (parallel [(const_int 0)
 820                                                       (const_int 4)
 821                                                       (const_int 1)
 822                                                       (const_int 5)
 823                                                       (const_int 2)
 824                                                       (const_int 6)
 825                                                       (const_int 3)
 826                                                       (const_int 7)]))
 827                         (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 828                                            (parallel [(const_int 4)
 829                                                       (const_int 0)
 830                                                       (const_int 5)
 831                                                       (const_int 1)
 832                                                       (const_int 6)
 833                                                       (const_int 2)
 834                                                       (const_int 7)
 835                                                       (const_int 3)]))
 836                       (const_int 85)))]
 837   "TARGET_ALTIVEC"
 838   "vmrghh %0,%1,%2"
 839   [(set_attr "type" "vecperm")])
 840
 841 (define_insn "altivec_vmrghw"
 842   [(set (match_operand:V4SI 0 "register_operand" "=v")
 843         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 844                                          (parallel [(const_int 0)
 845                                                     (const_int 2)
 846                                                     (const_int 1)
 847                                                     (const_int 3)]))
 848                         (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 849                                          (parallel [(const_int 2)
 850                                                     (const_int 0)
 851                                                     (const_int 3)
 852                                                     (const_int 1)]))
 853                       (const_int 5)))]
 854   "TARGET_ALTIVEC"
 855   "vmrghw %0,%1,%2"
 856   [(set_attr "type" "vecperm")])
 857
 858 (define_insn "altivec_vmrglb"
 859   [(set (match_operand:V16QI 0 "register_operand" "=v")
 860         (vec_merge:V16QI (vec_select:V16QI (match_operand:V16QI 1 "register_operand" "v")
 861                                            (parallel [(const_int 8)
 862                                                       (const_int 0)
 863                                                       (const_int 9)
 864                                                       (const_int 1)
 865                                                       (const_int 10)
 866                                                       (const_int 2)
 867                                                       (const_int 11)
 868                                                       (const_int 3)
 869                                                       (const_int 12)
 870                                                       (const_int 4)
 871                                                       (const_int 13)
 872                                                       (const_int 5)
 873                                                       (const_int 14)
 874                                                       (const_int 6)
 875                                                       (const_int 15)
 876                                                       (const_int 7)]))
 877                       (vec_select:V16QI (match_operand:V16QI 2 "register_operand" "v")
 878                                            (parallel [(const_int 0)
 879                                                       (const_int 8)
 880                                                       (const_int 1)
 881                                                       (const_int 9)
 882                                                       (const_int 2)
 883                                                       (const_int 10)
 884                                                       (const_int 3)
 885                                                       (const_int 11)
 886                                                       (const_int 4)
 887                                                       (const_int 12)
 888                                                       (const_int 5)
 889                                                       (const_int 13)
 890                                                       (const_int 6)
 891                                                       (const_int 14)
 892                                                       (const_int 7)
 893                                                       (const_int 15)]))
 894                       (const_int 21845)))]
 895   "TARGET_ALTIVEC"
 896   "vmrglb %0,%1,%2"
 897   [(set_attr "type" "vecperm")])
 898
 899 (define_insn "altivec_vmrglh"
 900   [(set (match_operand:V8HI 0 "register_operand" "=v")
 901         (vec_merge:V8HI (vec_select:V8HI (match_operand:V8HI 1 "register_operand" "v")
 902                                            (parallel [(const_int 4)
 903                                                       (const_int 0)
 904                                                       (const_int 5)
 905                                                       (const_int 1)
 906                                                       (const_int 6)
 907                                                       (const_int 2)
 908                                                       (const_int 7)
 909                                                       (const_int 3)]))
 910                         (vec_select:V8HI (match_operand:V8HI 2 "register_operand" "v")
 911                                            (parallel [(const_int 0)
 912                                                       (const_int 4)
 913                                                       (const_int 1)
 914                                                       (const_int 5)
 915                                                       (const_int 2)
 916                                                       (const_int 6)
 917                                                       (const_int 3)
 918                                                       (const_int 7)]))
 919                       (const_int 85)))]
 920   "TARGET_ALTIVEC"
 921   "vmrglh %0,%1,%2"
 922   [(set_attr "type" "vecperm")])
 923
 924 (define_insn "altivec_vmrglw"
 925   [(set (match_operand:V4SI 0 "register_operand" "=v")
 926         (vec_merge:V4SI (vec_select:V4SI (match_operand:V4SI 1 "register_operand" "v")
 927                                          (parallel [(const_int 2)
 928                                                     (const_int 0)
 929                                                     (const_int 3)
 930                                                     (const_int 1)]))
 931                         (vec_select:V4SI (match_operand:V4SI 2 "register_operand" "v")
 932                                          (parallel [(const_int 0)
 933                                                     (const_int 2)
 934                                                     (const_int 1)
 935                                                     (const_int 3)]))
 936                       (const_int 5)))]
 937   "TARGET_ALTIVEC"
 938   "vmrglw %0,%1,%2"
 939   [(set_attr "type" "vecperm")])
 940
 941 (define_insn "altivec_vmuleub"
 942   [(set (match_operand:V8HI 0 "register_operand" "=v")
 943         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 944                       (match_operand:V16QI 2 "register_operand" "v")]
 945                      UNSPEC_VMULEUB))]
 946   "TARGET_ALTIVEC"
 947   "vmuleub %0,%1,%2"
 948   [(set_attr "type" "veccomplex")])
 949
 950 (define_insn "altivec_vmulesb"
 951   [(set (match_operand:V8HI 0 "register_operand" "=v")
 952         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 953                       (match_operand:V16QI 2 "register_operand" "v")]
 954                      UNSPEC_VMULESB))]
 955   "TARGET_ALTIVEC"
 956   "vmulesb %0,%1,%2"
 957   [(set_attr "type" "veccomplex")])
 958
 959 (define_insn "altivec_vmuleuh"
 960   [(set (match_operand:V4SI 0 "register_operand" "=v")
 961         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 962                       (match_operand:V8HI 2 "register_operand" "v")]
 963                      UNSPEC_VMULEUH))]
 964   "TARGET_ALTIVEC"
 965   "vmuleuh %0,%1,%2"
 966   [(set_attr "type" "veccomplex")])
 967
 968 (define_insn "altivec_vmulesh"
 969   [(set (match_operand:V4SI 0 "register_operand" "=v")
 970         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 971                       (match_operand:V8HI 2 "register_operand" "v")]
 972                      UNSPEC_VMULESH))]
 973   "TARGET_ALTIVEC"
 974   "vmulesh %0,%1,%2"
 975   [(set_attr "type" "veccomplex")])
 976
 977 (define_insn "altivec_vmuloub"
 978   [(set (match_operand:V8HI 0 "register_operand" "=v")
 979         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 980                       (match_operand:V16QI 2 "register_operand" "v")]
 981                      UNSPEC_VMULOUB))]
 982   "TARGET_ALTIVEC"
 983   "vmuloub %0,%1,%2"
 984   [(set_attr "type" "veccomplex")])
 985
 986 (define_insn "altivec_vmulosb"
 987   [(set (match_operand:V8HI 0 "register_operand" "=v")
 988         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
 989                       (match_operand:V16QI 2 "register_operand" "v")]
 990                      UNSPEC_VMULOSB))]
 991   "TARGET_ALTIVEC"
 992   "vmulosb %0,%1,%2"
 993   [(set_attr "type" "veccomplex")])
 994
 995 (define_insn "altivec_vmulouh"
 996   [(set (match_operand:V4SI 0 "register_operand" "=v")
 997         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
 998                       (match_operand:V8HI 2 "register_operand" "v")]
 999                      UNSPEC_VMULOUH))]
1000   "TARGET_ALTIVEC"
1001   "vmulouh %0,%1,%2"
1002   [(set_attr "type" "veccomplex")])
1003
1004 (define_insn "altivec_vmulosh"
1005   [(set (match_operand:V4SI 0 "register_operand" "=v")
1006         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
1007                       (match_operand:V8HI 2 "register_operand" "v")]
1008                      UNSPEC_VMULOSH))]
1009   "TARGET_ALTIVEC"
1010   "vmulosh %0,%1,%2"
1011   [(set_attr "type" "veccomplex")])
1012
1013
1014 ;; logical ops
1015
1016 (define_insn "and<mode>3"
1017   [(set (match_operand:VI 0 "register_operand" "=v")
1018         (and:VI (match_operand:VI 1 "register_operand" "v")
1019                 (match_operand:VI 2 "register_operand" "v")))]
1020   "TARGET_ALTIVEC"
1021   "vand %0,%1,%2"
1022   [(set_attr "type" "vecsimple")])
1023
1024 (define_insn "ior<mode>3"
1025   [(set (match_operand:VI 0 "register_operand" "=v")
1026         (ior:VI (match_operand:VI 1 "register_operand" "v")
1027                 (match_operand:VI 2 "register_operand" "v")))]
1028   "TARGET_ALTIVEC"
1029   "vor %0,%1,%2"
1030   [(set_attr "type" "vecsimple")])
1031
1032 (define_insn "xor<mode>3"
1033   [(set (match_operand:VI 0 "register_operand" "=v")
1034         (xor:VI (match_operand:VI 1 "register_operand" "v")
1035                 (match_operand:VI 2 "register_operand" "v")))]
1036   "TARGET_ALTIVEC"
1037   "vxor %0,%1,%2"
1038   [(set_attr "type" "vecsimple")])
1039
1040 (define_insn "xorv4sf3"
1041   [(set (match_operand:V4SF 0 "register_operand" "=v")
1042         (xor:V4SF (match_operand:V4SF 1 "register_operand" "v")
1043                   (match_operand:V4SF 2 "register_operand" "v")))]
1044   "TARGET_ALTIVEC"
1045   "vxor %0,%1,%2"
1046   [(set_attr "type" "vecsimple")])
1047
1048 (define_insn "one_cmpl<mode>2"
1049   [(set (match_operand:VI 0 "register_operand" "=v")
1050         (not:VI (match_operand:VI 1 "register_operand" "v")))]
1051   "TARGET_ALTIVEC"
1052   "vnor %0,%1,%1"
1053   [(set_attr "type" "vecsimple")])
1054
1055 (define_insn "altivec_nor<mode>3"
1056   [(set (match_operand:VI 0 "register_operand" "=v")
1057         (not:VI (ior:VI (match_operand:VI 1 "register_operand" "v")
1058                         (match_operand:VI 2 "register_operand" "v"))))]
1059   "TARGET_ALTIVEC"
1060   "vnor %0,%1,%2"
1061   [(set_attr "type" "vecsimple")])
1062
1063 (define_insn "andc<mode>3"
1064   [(set (match_operand:VI 0 "register_operand" "=v")
1065         (and:VI (not:VI (match_operand:VI 2 "register_operand" "v"))
1066                 (match_operand:VI 1 "register_operand" "v")))]
1067   "TARGET_ALTIVEC"
1068   "vandc %0,%1,%2"
1069   [(set_attr "type" "vecsimple")])
1070
1071 (define_insn "*andc3_v4sf"
1072   [(set (match_operand:V4SF 0 "register_operand" "=v")
1073         (and:V4SF (not:V4SF (match_operand:V4SF 2 "register_operand" "v"))
1074                   (match_operand:V4SF 1 "register_operand" "v")))]
1075   "TARGET_ALTIVEC"
1076   "vandc %0,%1,%2"
1077   [(set_attr "type" "vecsimple")])
1078
1079 (define_insn "altivec_vpkuhum"
1080   [(set (match_operand:V16QI 0 "register_operand" "=v")
1081         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1082                        (match_operand:V8HI 2 "register_operand" "v")]
1083                       UNSPEC_VPKUHUM))]
1084   "TARGET_ALTIVEC"
1085   "vpkuhum %0,%1,%2"
1086   [(set_attr "type" "vecperm")])
1087
1088 (define_insn "altivec_vpkuwum"
1089   [(set (match_operand:V8HI 0 "register_operand" "=v")
1090         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1091                       (match_operand:V4SI 2 "register_operand" "v")]
1092                      UNSPEC_VPKUWUM))]
1093   "TARGET_ALTIVEC"
1094   "vpkuwum %0,%1,%2"
1095   [(set_attr "type" "vecperm")])
1096
1097 (define_insn "altivec_vpkpx"
1098   [(set (match_operand:V8HI 0 "register_operand" "=v")
1099         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1100                       (match_operand:V4SI 2 "register_operand" "v")]
1101                      UNSPEC_VPKPX))]
1102   "TARGET_ALTIVEC"
1103   "vpkpx %0,%1,%2"
1104   [(set_attr "type" "vecperm")])
1105
1106 (define_insn "altivec_vpkshss"
1107   [(set (match_operand:V16QI 0 "register_operand" "=v")
1108         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1109                        (match_operand:V8HI 2 "register_operand" "v")]
1110                       UNSPEC_VPKSHSS))
1111    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1112   "TARGET_ALTIVEC"
1113   "vpkshss %0,%1,%2"
1114   [(set_attr "type" "vecperm")])
1115
1116 (define_insn "altivec_vpkswss"
1117   [(set (match_operand:V8HI 0 "register_operand" "=v")
1118         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1119                       (match_operand:V4SI 2 "register_operand" "v")]
1120                      UNSPEC_VPKSWSS))
1121    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1122   "TARGET_ALTIVEC"
1123   "vpkswss %0,%1,%2"
1124   [(set_attr "type" "vecperm")])
1125
1126 (define_insn "altivec_vpkuhus"
1127   [(set (match_operand:V16QI 0 "register_operand" "=v")
1128         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1129                        (match_operand:V8HI 2 "register_operand" "v")]
1130                       UNSPEC_VPKUHUS))
1131    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1132   "TARGET_ALTIVEC"
1133   "vpkuhus %0,%1,%2"
1134   [(set_attr "type" "vecperm")])
1135
1136 (define_insn "altivec_vpkshus"
1137   [(set (match_operand:V16QI 0 "register_operand" "=v")
1138         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
1139                        (match_operand:V8HI 2 "register_operand" "v")]
1140                       UNSPEC_VPKSHUS))
1141    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1142   "TARGET_ALTIVEC"
1143   "vpkshus %0,%1,%2"
1144   [(set_attr "type" "vecperm")])
1145
1146 (define_insn "altivec_vpkuwus"
1147   [(set (match_operand:V8HI 0 "register_operand" "=v")
1148         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1149                       (match_operand:V4SI 2 "register_operand" "v")]
1150                      UNSPEC_VPKUWUS))
1151    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1152   "TARGET_ALTIVEC"
1153   "vpkuwus %0,%1,%2"
1154   [(set_attr "type" "vecperm")])
1155
1156 (define_insn "altivec_vpkswus"
1157   [(set (match_operand:V8HI 0 "register_operand" "=v")
1158         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1159                       (match_operand:V4SI 2 "register_operand" "v")]
1160                      UNSPEC_VPKSWUS))
1161    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1162   "TARGET_ALTIVEC"
1163   "vpkswus %0,%1,%2"
1164   [(set_attr "type" "vecperm")])
1165
1166 (define_insn "altivec_vrl<VI_char>"
1167   [(set (match_operand:VI 0 "register_operand" "=v")
1168         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1169                     (match_operand:VI 2 "register_operand" "v")]
1170                    UNSPEC_VRL))]
1171   "TARGET_ALTIVEC"
1172   "vrl<VI_char> %0,%1,%2"
1173   [(set_attr "type" "vecsimple")])
1174
1175 (define_insn "altivec_vsl<VI_char>"
1176   [(set (match_operand:VI 0 "register_operand" "=v")
1177         (unspec:VI [(match_operand:VI 1 "register_operand" "v")
1178                     (match_operand:VI 2 "register_operand" "v")]
1179                    UNSPEC_VSL))]
1180   "TARGET_ALTIVEC"
1181   "vsl<VI_char> %0,%1,%2"
1182   [(set_attr "type" "vecsimple")])
1183
1184 (define_insn "altivec_vsl"
1185   [(set (match_operand:V4SI 0 "register_operand" "=v")
1186         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1187                       (match_operand:V4SI 2 "register_operand" "v")]
1188                      UNSPEC_VSLV4SI))]
1189   "TARGET_ALTIVEC"
1190   "vsl %0,%1,%2"
1191   [(set_attr "type" "vecperm")])
1192
1193 (define_insn "altivec_vslo"
1194   [(set (match_operand:V4SI 0 "register_operand" "=v")
1195         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1196                       (match_operand:V4SI 2 "register_operand" "v")]
1197                      UNSPEC_VSLO))]
1198   "TARGET_ALTIVEC"
1199   "vslo %0,%1,%2"
1200   [(set_attr "type" "vecperm")])
1201
1202 (define_insn "lshr<mode>3"
1203   [(set (match_operand:VI 0 "register_operand" "=v")
1204         (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
1205                     (match_operand:VI 2 "register_operand" "v") ))]
1206   "TARGET_ALTIVEC"
1207   "vsr<VI_char> %0,%1,%2"
1208   [(set_attr "type" "vecsimple")])
1209
1210 (define_insn "ashr<mode>3"
1211   [(set (match_operand:VI 0 "register_operand" "=v")
1212         (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
1213                     (match_operand:VI 2 "register_operand" "v") ))]
1214   "TARGET_ALTIVEC"
1215   "vsra<VI_char> %0,%1,%2"
1216   [(set_attr "type" "vecsimple")])
1217
1218 (define_insn "altivec_vsr"
1219   [(set (match_operand:V4SI 0 "register_operand" "=v")
1220         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1221                       (match_operand:V4SI 2 "register_operand" "v")]
1222                      UNSPEC_VSR))]
1223   "TARGET_ALTIVEC"
1224   "vsr %0,%1,%2"
1225   [(set_attr "type" "vecperm")])
1226
1227 (define_insn "altivec_vsro"
1228   [(set (match_operand:V4SI 0 "register_operand" "=v")
1229         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1230                       (match_operand:V4SI 2 "register_operand" "v")]
1231                      UNSPEC_VSRO))]
1232   "TARGET_ALTIVEC"
1233   "vsro %0,%1,%2"
1234   [(set_attr "type" "vecperm")])
1235
1236 (define_insn "altivec_vsum4ubs"
1237   [(set (match_operand:V4SI 0 "register_operand" "=v")
1238         (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")
1239                       (match_operand:V4SI 2 "register_operand" "v")]
1240                      UNSPEC_VSUM4UBS))
1241    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1242   "TARGET_ALTIVEC"
1243   "vsum4ubs %0,%1,%2"
1244   [(set_attr "type" "veccomplex")])
1245
1246 (define_insn "altivec_vsum4s<VI_char>s"
1247   [(set (match_operand:V4SI 0 "register_operand" "=v")
1248         (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
1249                       (match_operand:V4SI 2 "register_operand" "v")]
1250                      UNSPEC_VSUM4S))
1251    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1252   "TARGET_ALTIVEC"
1253   "vsum4s<VI_char>s %0,%1,%2"
1254   [(set_attr "type" "veccomplex")])
1255
1256 (define_insn "altivec_vsum2sws"
1257   [(set (match_operand:V4SI 0 "register_operand" "=v")
1258         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1259                       (match_operand:V4SI 2 "register_operand" "v")]
1260                      UNSPEC_VSUM2SWS))
1261    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1262   "TARGET_ALTIVEC"
1263   "vsum2sws %0,%1,%2"
1264   [(set_attr "type" "veccomplex")])
1265
1266 (define_insn "altivec_vsumsws"
1267   [(set (match_operand:V4SI 0 "register_operand" "=v")
1268         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1269                       (match_operand:V4SI 2 "register_operand" "v")]
1270                      UNSPEC_VSUMSWS))
1271    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1272   "TARGET_ALTIVEC"
1273   "vsumsws %0,%1,%2"
1274   [(set_attr "type" "veccomplex")])
1275
1276 (define_insn "altivec_vspltb"
1277   [(set (match_operand:V16QI 0 "register_operand" "=v")
1278         (vec_duplicate:V16QI
1279          (vec_select:QI (match_operand:V16QI 1 "register_operand" "v")
1280                         (parallel
1281                          [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1282   "TARGET_ALTIVEC"
1283   "vspltb %0,%1,%2"
1284   [(set_attr "type" "vecperm")])
1285
1286 (define_insn "altivec_vsplth"
1287   [(set (match_operand:V8HI 0 "register_operand" "=v")
1288         (vec_duplicate:V8HI
1289          (vec_select:HI (match_operand:V8HI 1 "register_operand" "v")
1290                         (parallel
1291                          [(match_operand:QI 2 "u5bit_cint_operand" "")]))))]
1292   "TARGET_ALTIVEC"
1293   "vsplth %0,%1,%2"
1294   [(set_attr "type" "vecperm")])
1295
1296 (define_insn "altivec_vspltw"
1297   [(set (match_operand:V4SI 0 "register_operand" "=v")
1298         (vec_duplicate:V4SI
1299          (vec_select:SI (match_operand:V4SI 1 "register_operand" "v")
1300                         (parallel
1301                          [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1302   "TARGET_ALTIVEC"
1303   "vspltw %0,%1,%2"
1304   [(set_attr "type" "vecperm")])
1305
1306 (define_insn "*altivec_vspltsf"
1307   [(set (match_operand:V4SF 0 "register_operand" "=v")
1308         (vec_duplicate:V4SF
1309          (vec_select:SF (match_operand:V4SF 1 "register_operand" "v")
1310                         (parallel
1311                          [(match_operand:QI 2 "u5bit_cint_operand" "i")]))))]
1312   "TARGET_ALTIVEC"
1313   "vspltw %0,%1,%2"
1314   [(set_attr "type" "vecperm")])
1315
1316 (define_insn "altivec_vspltis<VI_char>"
1317   [(set (match_operand:VI 0 "register_operand" "=v")
1318         (vec_duplicate:VI
1319          (match_operand:QI 1 "s5bit_cint_operand" "i")))]
1320   "TARGET_ALTIVEC"
1321   "vspltis<VI_char> %0,%1"
1322   [(set_attr "type" "vecperm")])
1323
1324 (define_insn "ftruncv4sf2"
1325   [(set (match_operand:V4SF 0 "register_operand" "=v")
1326         (fix:V4SF (match_operand:V4SF 1 "register_operand" "v")))]
1327   "TARGET_ALTIVEC"
1328   "vrfiz %0,%1"
1329   [(set_attr "type" "vecfloat")])
1330
1331 (define_insn "altivec_vperm_<mode>"
1332   [(set (match_operand:V 0 "register_operand" "=v")
1333         (unspec:V [(match_operand:V 1 "register_operand" "v")
1334                    (match_operand:V 2 "register_operand" "v")
1335                    (match_operand:V16QI 3 "register_operand" "v")]
1336                   UNSPEC_VPERM))]
1337   "TARGET_ALTIVEC"
1338   "vperm %0,%1,%2,%3"
1339   [(set_attr "type" "vecperm")])
1340
1341 (define_insn "altivec_vrfip"
1342   [(set (match_operand:V4SF 0 "register_operand" "=v")
1343         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1344                      UNSPEC_VRFIP))]
1345   "TARGET_ALTIVEC"
1346   "vrfip %0,%1"
1347   [(set_attr "type" "vecfloat")])
1348
1349 (define_insn "altivec_vrfin"
1350   [(set (match_operand:V4SF 0 "register_operand" "=v")
1351         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1352                      UNSPEC_VRFIN))]
1353   "TARGET_ALTIVEC"
1354   "vrfin %0,%1"
1355   [(set_attr "type" "vecfloat")])
1356
1357 (define_insn "altivec_vrfim"
1358   [(set (match_operand:V4SF 0 "register_operand" "=v")
1359         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1360                      UNSPEC_VRFIM))]
1361   "TARGET_ALTIVEC"
1362   "vrfim %0,%1"
1363   [(set_attr "type" "vecfloat")])
1364
1365 (define_insn "altivec_vcfux"
1366   [(set (match_operand:V4SF 0 "register_operand" "=v")
1367         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1368                       (match_operand:QI 2 "immediate_operand" "i")]
1369                      UNSPEC_VCFUX))]
1370   "TARGET_ALTIVEC"
1371   "vcfux %0,%1,%2"
1372   [(set_attr "type" "vecfloat")])
1373
1374 (define_insn "altivec_vcfsx"
1375   [(set (match_operand:V4SF 0 "register_operand" "=v")
1376         (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1377                       (match_operand:QI 2 "immediate_operand" "i")]
1378                      UNSPEC_VCFSX))]
1379   "TARGET_ALTIVEC"
1380   "vcfsx %0,%1,%2"
1381   [(set_attr "type" "vecfloat")])
1382
1383 (define_insn "altivec_vctuxs"
1384   [(set (match_operand:V4SI 0 "register_operand" "=v")
1385         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1386                       (match_operand:QI 2 "immediate_operand" "i")]
1387                      UNSPEC_VCTUXS))
1388    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1389   "TARGET_ALTIVEC"
1390   "vctuxs %0,%1,%2"
1391   [(set_attr "type" "vecfloat")])
1392
1393 (define_insn "altivec_vctsxs"
1394   [(set (match_operand:V4SI 0 "register_operand" "=v")
1395         (unspec:V4SI [(match_operand:V4SF 1 "register_operand" "v")
1396                       (match_operand:QI 2 "immediate_operand" "i")]
1397                      UNSPEC_VCTSXS))
1398    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
1399   "TARGET_ALTIVEC"
1400   "vctsxs %0,%1,%2"
1401   [(set_attr "type" "vecfloat")])
1402
1403 (define_insn "altivec_vlogefp"
1404   [(set (match_operand:V4SF 0 "register_operand" "=v")
1405         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1406                      UNSPEC_VLOGEFP))]
1407   "TARGET_ALTIVEC"
1408   "vlogefp %0,%1"
1409   [(set_attr "type" "vecfloat")])
1410
1411 (define_insn "altivec_vexptefp"
1412   [(set (match_operand:V4SF 0 "register_operand" "=v")
1413         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1414                      UNSPEC_VEXPTEFP))]
1415   "TARGET_ALTIVEC"
1416   "vexptefp %0,%1"
1417   [(set_attr "type" "vecfloat")])
1418
1419 (define_insn "altivec_vrsqrtefp"
1420   [(set (match_operand:V4SF 0 "register_operand" "=v")
1421         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1422                      UNSPEC_VRSQRTEFP))]
1423   "TARGET_ALTIVEC"
1424   "vrsqrtefp %0,%1"
1425   [(set_attr "type" "vecfloat")])
1426
1427 (define_insn "altivec_vrefp"
1428   [(set (match_operand:V4SF 0 "register_operand" "=v")
1429         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")]
1430                      UNSPEC_VREFP))]
1431   "TARGET_ALTIVEC"
1432   "vrefp %0,%1"
1433   [(set_attr "type" "vecfloat")])
1434
1435 (define_expand "vcondv4si"
1436         [(set (match_operand:V4SI 0 "register_operand" "=v")
1437               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1438                (match_operand:V4SI 2 "register_operand" "v")
1439                (match_operand:V4SI 3 "comparison_operator" "")
1440                (match_operand:V4SI 4 "register_operand" "v")
1441                (match_operand:V4SI 5 "register_operand" "v")
1442                ] UNSPEC_VCOND_V4SI))]
1443         "TARGET_ALTIVEC"
1444         "
1445 {
1446         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1447                                           operands[3], operands[4], operands[5]))
1448         DONE;
1449         else
1450         FAIL;
1451 }
1452         ")
1453
1454 (define_expand "vconduv4si"
1455         [(set (match_operand:V4SI 0 "register_operand" "=v")
1456               (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1457                (match_operand:V4SI 2 "register_operand" "v")
1458                (match_operand:V4SI 3 "comparison_operator" "")
1459                (match_operand:V4SI 4 "register_operand" "v")
1460                (match_operand:V4SI 5 "register_operand" "v")
1461                ] UNSPEC_VCONDU_V4SI))]
1462         "TARGET_ALTIVEC"
1463         "
1464 {
1465         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1466                                           operands[3], operands[4], operands[5]))
1467         DONE;
1468         else
1469         FAIL;
1470 }
1471         ")
1472
1473 (define_expand "vcondv4sf"
1474         [(set (match_operand:V4SF 0 "register_operand" "=v")
1475               (unspec:V4SF [(match_operand:V4SI 1 "register_operand" "v")
1476                (match_operand:V4SF 2 "register_operand" "v")
1477                (match_operand:V4SF 3 "comparison_operator" "")
1478                (match_operand:V4SF 4 "register_operand" "v")
1479                (match_operand:V4SF 5 "register_operand" "v")
1480                ] UNSPEC_VCOND_V4SF))]
1481         "TARGET_ALTIVEC"
1482         "
1483 {
1484         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1485                                           operands[3], operands[4], operands[5]))
1486         DONE;
1487         else
1488         FAIL;
1489 }
1490         ")
1491
1492 (define_expand "vcondv8hi"
1493         [(set (match_operand:V4SF 0 "register_operand" "=v")
1494               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1495                (match_operand:V8HI 2 "register_operand" "v")
1496                (match_operand:V8HI 3 "comparison_operator" "")
1497                (match_operand:V8HI 4 "register_operand" "v")
1498                (match_operand:V8HI 5 "register_operand" "v")
1499                ] UNSPEC_VCOND_V8HI))]
1500         "TARGET_ALTIVEC"
1501         "
1502 {
1503         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1504                                           operands[3], operands[4], operands[5]))
1505         DONE;
1506         else
1507         FAIL;
1508 }
1509         ")
1510
1511 (define_expand "vconduv8hi"
1512         [(set (match_operand:V4SF 0 "register_operand" "=v")
1513               (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
1514                (match_operand:V8HI 2 "register_operand" "v")
1515                (match_operand:V8HI 3 "comparison_operator" "")
1516                (match_operand:V8HI 4 "register_operand" "v")
1517                (match_operand:V8HI 5 "register_operand" "v")
1518                ] UNSPEC_VCONDU_V8HI))]
1519         "TARGET_ALTIVEC"
1520         "
1521 {
1522         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1523                                           operands[3], operands[4], operands[5]))
1524         DONE;
1525         else
1526         FAIL;
1527 }
1528         ")
1529
1530 (define_expand "vcondv16qi"
1531         [(set (match_operand:V4SF 0 "register_operand" "=v")
1532               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1533                (match_operand:V16QI 2 "register_operand" "v")
1534                (match_operand:V16QI 3 "comparison_operator" "")
1535                (match_operand:V16QI 4 "register_operand" "v")
1536                (match_operand:V16QI 5 "register_operand" "v")
1537                ] UNSPEC_VCOND_V16QI))]
1538         "TARGET_ALTIVEC"
1539         "
1540 {
1541         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1542                                           operands[3], operands[4], operands[5]))
1543         DONE;
1544         else
1545         FAIL;
1546 }
1547         ")
1548
1549 (define_expand "vconduv16qi"
1550         [(set (match_operand:V4SF 0 "register_operand" "=v")
1551               (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")
1552                (match_operand:V16QI 2 "register_operand" "v")
1553                (match_operand:V16QI 3 "comparison_operator" "")
1554                (match_operand:V16QI 4 "register_operand" "v")
1555                (match_operand:V16QI 5 "register_operand" "v")
1556                ] UNSPEC_VCONDU_V16QI))]
1557         "TARGET_ALTIVEC"
1558         "
1559 {
1560         if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
1561                                           operands[3], operands[4], operands[5]))
1562         DONE;
1563         else
1564         FAIL;
1565 }
1566         ")
1567
1568
1569 (define_insn "altivec_vsel_v4si"
1570   [(set (match_operand:V4SI 0 "register_operand" "=v")
1571         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
1572                       (match_operand:V4SI 2 "register_operand" "v")
1573                       (match_operand:V4SI 3 "register_operand" "v")]
1574                      UNSPEC_VSEL4SI))]
1575   "TARGET_ALTIVEC"
1576   "vsel %0,%1,%2,%3"
1577   [(set_attr "type" "vecperm")])
1578
1579 (define_insn "altivec_vsel_v4sf"
1580   [(set (match_operand:V4SF 0 "register_operand" "=v")
1581         (unspec:V4SF [(match_operand:V4SF 1 "register_operand" "v")
1582                       (match_operand:V4SF 2 "register_operand" "v")
1583                       (match_operand:V4SI 3 "register_operand" "v")]
1584                       UNSPEC_VSEL4SF))]
1585   "TARGET_ALTIVEC"
1586   "vsel %0,%1,%2,%3"
1587   [(set_attr "type" "vecperm")])
1588
1589 (define_insn "altivec_vsel_v8hi"
1590   [(set (match_operand:V8HI 0 "register_operand" "=v")
1591         (unspec:V8HI [(match_operand:V8HI 1 "register_operand" "v")
1592                       (match_operand:V8HI 2 "register_operand" "v")
1593                       (match_operand:V8HI 3 "register_operand" "v")]
1594                      UNSPEC_VSEL8HI))]
1595   "TARGET_ALTIVEC"
1596   "vsel %0,%1,%2,%3"
1597   [(set_attr "type" "vecperm")])
1598
1599 (define_insn "altivec_vsel_v16qi"
1600   [(set (match_operand:V16QI 0 "register_operand" "=v")
1601         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")
1602                        (match_operand:V16QI 2 "register_operand" "v")
1603                        (match_operand:V16QI 3 "register_operand" "v")]
1604                       UNSPEC_VSEL16QI))]
1605   "TARGET_ALTIVEC"
1606   "vsel %0,%1,%2,%3"
1607   [(set_attr "type" "vecperm")])
1608
1609 (define_insn "altivec_vsldoi_<mode>"
1610   [(set (match_operand:V 0 "register_operand" "=v")
1611         (unspec:V [(match_operand:V 1 "register_operand" "v")
1612                    (match_operand:V 2 "register_operand" "v")
1613                    (match_operand:QI 3 "immediate_operand" "i")]
1614                   UNSPEC_VLSDOI))]
1615   "TARGET_ALTIVEC"
1616   "vsldoi %0,%1,%2,%3"
1617   [(set_attr "type" "vecperm")])
1618
1619 (define_insn "altivec_vupkhsb"
1620   [(set (match_operand:V8HI 0 "register_operand" "=v")
1621         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1622                      UNSPEC_VUPKHSB))]
1623   "TARGET_ALTIVEC"
1624   "vupkhsb %0,%1"
1625   [(set_attr "type" "vecperm")])
1626
1627 (define_insn "altivec_vupkhpx"
1628   [(set (match_operand:V4SI 0 "register_operand" "=v")
1629         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1630                      UNSPEC_VUPKHPX))]
1631   "TARGET_ALTIVEC"
1632   "vupkhpx %0,%1"
1633   [(set_attr "type" "vecperm")])
1634
1635 (define_insn "altivec_vupkhsh"
1636   [(set (match_operand:V4SI 0 "register_operand" "=v")
1637         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1638                      UNSPEC_VUPKHSH))]
1639   "TARGET_ALTIVEC"
1640   "vupkhsh %0,%1"
1641   [(set_attr "type" "vecperm")])
1642
1643 (define_insn "altivec_vupklsb"
1644   [(set (match_operand:V8HI 0 "register_operand" "=v")
1645         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
1646                      UNSPEC_VUPKLSB))]
1647   "TARGET_ALTIVEC"
1648   "vupklsb %0,%1"
1649   [(set_attr "type" "vecperm")])
1650
1651 (define_insn "altivec_vupklpx"
1652   [(set (match_operand:V4SI 0 "register_operand" "=v")
1653         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1654                      UNSPEC_VUPKLPX))]
1655   "TARGET_ALTIVEC"
1656   "vupklpx %0,%1"
1657   [(set_attr "type" "vecperm")])
1658
1659 (define_insn "altivec_vupklsh"
1660   [(set (match_operand:V4SI 0 "register_operand" "=v")
1661         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
1662                      UNSPEC_VUPKLSH))]
1663   "TARGET_ALTIVEC"
1664   "vupklsh %0,%1"
1665   [(set_attr "type" "vecperm")])
1666
1667 ;; AltiVec predicates.
1668
1669 (define_expand "cr6_test_for_zero"
1670   [(set (match_operand:SI 0 "register_operand" "=r")
1671         (eq:SI (reg:CC 74)
1672                (const_int 0)))]
1673   "TARGET_ALTIVEC"
1674   "")
1675
1676 (define_expand "cr6_test_for_zero_reverse"
1677   [(set (match_operand:SI 0 "register_operand" "=r")
1678         (eq:SI (reg:CC 74)
1679                (const_int 0)))
1680    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1681   "TARGET_ALTIVEC"
1682   "")
1683
1684 (define_expand "cr6_test_for_lt"
1685   [(set (match_operand:SI 0 "register_operand" "=r")
1686         (lt:SI (reg:CC 74)
1687                (const_int 0)))]
1688   "TARGET_ALTIVEC"
1689   "")
1690
1691 (define_expand "cr6_test_for_lt_reverse"
1692   [(set (match_operand:SI 0 "register_operand" "=r")
1693         (lt:SI (reg:CC 74)
1694                (const_int 0)))
1695    (set (match_dup 0) (minus:SI (const_int 1) (match_dup 0)))]
1696   "TARGET_ALTIVEC"
1697   "")
1698
1699 ;; We can get away with generating the opcode on the fly (%3 below)
1700 ;; because all the predicates have the same scheduling parameters.
1701
1702 (define_insn "altivec_predicate_<mode>"
1703   [(set (reg:CC 74)
1704         (unspec:CC [(match_operand:V 1 "register_operand" "v")
1705                     (match_operand:V 2 "register_operand" "v")
1706                     (match_operand 3 "any_operand" "")] UNSPEC_PREDICATE))
1707    (clobber (match_scratch:V 0 "=v"))]
1708   "TARGET_ALTIVEC"
1709   "%3 %0,%1,%2"
1710 [(set_attr "type" "veccmp")])
1711
1712 (define_insn "altivec_mtvscr"
1713   [(set (reg:SI 110)
1714         (unspec_volatile:SI
1715          [(match_operand:V4SI 0 "register_operand" "v")] UNSPECV_MTVSCR))]
1716   "TARGET_ALTIVEC"
1717   "mtvscr %0"
1718   [(set_attr "type" "vecsimple")])
1719
1720 (define_insn "altivec_mfvscr"
1721   [(set (match_operand:V8HI 0 "register_operand" "=v")
1722         (unspec_volatile:V8HI [(reg:SI 110)] UNSPECV_MFVSCR))]
1723   "TARGET_ALTIVEC"
1724   "mfvscr %0"
1725   [(set_attr "type" "vecsimple")])
1726
1727 (define_insn "altivec_dssall"
1728   [(unspec_volatile [(const_int 0)] UNSPECV_DSSALL)]
1729   "TARGET_ALTIVEC"
1730   "dssall"
1731   [(set_attr "type" "vecsimple")])
1732
1733 (define_insn "altivec_dss"
1734   [(unspec_volatile [(match_operand:QI 0 "immediate_operand" "i")]
1735                     UNSPECV_DSS)]
1736   "TARGET_ALTIVEC"
1737   "dss %0"
1738   [(set_attr "type" "vecsimple")])
1739
1740 (define_insn "altivec_dst"
1741   [(unspec [(match_operand 0 "register_operand" "b")
1742             (match_operand:SI 1 "register_operand" "r")
1743             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DST)]
1744   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1745   "dst %0,%1,%2"
1746   [(set_attr "type" "vecsimple")])
1747
1748 (define_insn "altivec_dstt"
1749   [(unspec [(match_operand 0 "register_operand" "b")
1750             (match_operand:SI 1 "register_operand" "r")
1751             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTT)]
1752   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1753   "dstt %0,%1,%2"
1754   [(set_attr "type" "vecsimple")])
1755
1756 (define_insn "altivec_dstst"
1757   [(unspec [(match_operand 0 "register_operand" "b")
1758             (match_operand:SI 1 "register_operand" "r")
1759             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTST)]
1760   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1761   "dstst %0,%1,%2"
1762   [(set_attr "type" "vecsimple")])
1763
1764 (define_insn "altivec_dststt"
1765   [(unspec [(match_operand 0 "register_operand" "b")
1766             (match_operand:SI 1 "register_operand" "r")
1767             (match_operand:QI 2 "immediate_operand" "i")] UNSPEC_DSTSTT)]
1768   "TARGET_ALTIVEC && GET_MODE (operands[0]) == Pmode"
1769   "dststt %0,%1,%2"
1770   [(set_attr "type" "vecsimple")])
1771
1772 (define_insn "altivec_lvsl"
1773   [(set (match_operand:V16QI 0 "register_operand" "=v")
1774         (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSL))]
1775   "TARGET_ALTIVEC"
1776   "lvsl %0,%y1"
1777   [(set_attr "type" "vecload")])
1778
1779 (define_insn "altivec_lvsr"
1780   [(set (match_operand:V16QI 0 "register_operand" "=v")
1781         (unspec:V16QI [(match_operand 1 "memory_operand" "Z")] UNSPEC_LVSR))]
1782   "TARGET_ALTIVEC"
1783   "lvsr %0,%y1"
1784   [(set_attr "type" "vecload")])
1785
1786 (define_expand "build_vector_mask_for_load"
1787   [(set (match_operand:V16QI 0 "register_operand" "")
1788         (unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
1789   "TARGET_ALTIVEC"
1790   "
1791 {
1792   rtx addr;
1793   rtx temp;
1794
1795   gcc_assert (GET_CODE (operands[1]) == MEM);
1796
1797   addr = XEXP (operands[1], 0);
1798   temp = gen_reg_rtx (GET_MODE (addr));
1799   emit_insn (gen_rtx_SET (VOIDmode, temp,
1800                           gen_rtx_NEG (GET_MODE (addr), addr)));
1801   emit_insn (gen_altivec_lvsr (operands[0],
1802                                replace_equiv_address (operands[1], temp)));
1803   DONE;
1804 }")
1805
1806 ;; Parallel some of the LVE* and STV*'s with unspecs because some have
1807 ;; identical rtl but different instructions-- and gcc gets confused.
1808
1809 (define_insn "altivec_lve<VI_char>x"
1810   [(parallel
1811     [(set (match_operand:VI 0 "register_operand" "=v")
1812           (match_operand:VI 1 "memory_operand" "Z"))
1813      (unspec [(const_int 0)] UNSPEC_LVE)])]
1814   "TARGET_ALTIVEC"
1815   "lve<VI_char>x %0,%y1"
1816   [(set_attr "type" "vecload")])
1817
1818 (define_insn "*altivec_lvesfx"
1819   [(parallel
1820     [(set (match_operand:V4SF 0 "register_operand" "=v")
1821           (match_operand:V4SF 1 "memory_operand" "Z"))
1822      (unspec [(const_int 0)] UNSPEC_LVE)])]
1823   "TARGET_ALTIVEC"
1824   "lvewx %0,%y1"
1825   [(set_attr "type" "vecload")])
1826
1827 (define_insn "altivec_lvxl"
1828   [(parallel
1829     [(set (match_operand:V4SI 0 "register_operand" "=v")
1830           (match_operand:V4SI 1 "memory_operand" "Z"))
1831      (unspec [(const_int 0)] UNSPEC_SET_VSCR)])]
1832   "TARGET_ALTIVEC"
1833   "lvxl %0,%y1"
1834   [(set_attr "type" "vecload")])
1835
1836 (define_insn "altivec_lvx"
1837   [(set (match_operand:V4SI 0 "register_operand" "=v")
1838         (match_operand:V4SI 1 "memory_operand" "Z"))]
1839   "TARGET_ALTIVEC"
1840   "lvx %0,%y1"
1841   [(set_attr "type" "vecload")])
1842
1843 (define_insn "altivec_stvx"
1844   [(parallel
1845     [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1846           (match_operand:V4SI 1 "register_operand" "v"))
1847      (unspec [(const_int 0)] UNSPEC_STVX)])]
1848   "TARGET_ALTIVEC"
1849   "stvx %1,%y0"
1850   [(set_attr "type" "vecstore")])
1851
1852 (define_insn "altivec_stvxl"
1853   [(parallel
1854     [(set (match_operand:V4SI 0 "memory_operand" "=Z")
1855           (match_operand:V4SI 1 "register_operand" "v"))
1856      (unspec [(const_int 0)] UNSPEC_STVXL)])]
1857   "TARGET_ALTIVEC"
1858   "stvxl %1,%y0"
1859   [(set_attr "type" "vecstore")])
1860
1861 (define_insn "altivec_stve<VI_char>x"
1862   [(parallel
1863     [(set (match_operand:VI 0 "memory_operand" "=Z")
1864           (match_operand:VI 1 "register_operand" "v"))
1865      (unspec [(const_int 0)] UNSPEC_STVE)])]
1866   "TARGET_ALTIVEC"
1867   "stve<VI_char>x %1,%y0"
1868   [(set_attr "type" "vecstore")])
1869
1870 (define_insn "*altivec_stvesfx"
1871   [(parallel
1872     [(set (match_operand:V4SF 0 "memory_operand" "=Z")
1873           (match_operand:V4SF 1 "register_operand" "v"))
1874      (unspec [(const_int 0)] UNSPEC_STVE)])]
1875   "TARGET_ALTIVEC"
1876   "stvewx %1,%y0"
1877   [(set_attr "type" "vecstore")])
1878
1879 (define_expand "vec_init<mode>"
1880   [(match_operand:V 0 "register_operand" "")
1881    (match_operand 1 "" "")]
1882   "TARGET_ALTIVEC"
1883 {
1884   rs6000_expand_vector_init (operands[0], operands[1]);
1885   DONE;
1886 })
1887
1888 (define_expand "vec_setv4si"
1889   [(match_operand:V4SI 0 "register_operand" "")
1890    (match_operand:SI 1 "register_operand" "")
1891    (match_operand 2 "const_int_operand" "")]
1892   "TARGET_ALTIVEC"
1893 {
1894   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1895   DONE;
1896 })
1897
1898 (define_expand "vec_setv8hi"
1899   [(match_operand:V8HI 0 "register_operand" "")
1900    (match_operand:HI 1 "register_operand" "")
1901    (match_operand 2 "const_int_operand" "")]
1902   "TARGET_ALTIVEC"
1903 {
1904   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1905   DONE;
1906 })
1907
1908 (define_expand "vec_setv16qi"
1909   [(match_operand:V16QI 0 "register_operand" "")
1910    (match_operand:QI 1 "register_operand" "")
1911    (match_operand 2 "const_int_operand" "")]
1912   "TARGET_ALTIVEC"
1913 {
1914   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1915   DONE;
1916 })
1917
1918 (define_expand "vec_setv4sf"
1919   [(match_operand:V4SF 0 "register_operand" "")
1920    (match_operand:SF 1 "register_operand" "")
1921    (match_operand 2 "const_int_operand" "")]
1922   "TARGET_ALTIVEC"
1923 {
1924   rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
1925   DONE;
1926 })
1927
1928 (define_expand "vec_extractv4si"
1929   [(match_operand:SI 0 "register_operand" "")
1930    (match_operand:V4SI 1 "register_operand" "")
1931    (match_operand 2 "const_int_operand" "")]
1932   "TARGET_ALTIVEC"
1933 {
1934   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1935   DONE;
1936 })
1937
1938 (define_expand "vec_extractv8hi"
1939   [(match_operand:HI 0 "register_operand" "")
1940    (match_operand:V8HI 1 "register_operand" "")
1941    (match_operand 2 "const_int_operand" "")]
1942   "TARGET_ALTIVEC"
1943 {
1944   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1945   DONE;
1946 })
1947
1948 (define_expand "vec_extractv16qi"
1949   [(match_operand:QI 0 "register_operand" "")
1950    (match_operand:V16QI 1 "register_operand" "")
1951    (match_operand 2 "const_int_operand" "")]
1952   "TARGET_ALTIVEC"
1953 {
1954   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1955   DONE;
1956 })
1957
1958 (define_expand "vec_extractv4sf"
1959   [(match_operand:SF 0 "register_operand" "")
1960    (match_operand:V4SF 1 "register_operand" "")
1961    (match_operand 2 "const_int_operand" "")]
1962   "TARGET_ALTIVEC"
1963 {
1964   rs6000_expand_vector_extract (operands[0], operands[1], INTVAL (operands[2]));
1965   DONE;
1966 })
1967
1968 ;; Generate
1969 ;;    vspltis? SCRATCH0,0
1970 ;;    vsubu?m SCRATCH2,SCRATCH1,%1
1971 ;;    vmaxs? %0,%1,SCRATCH2"
1972 (define_expand "abs<mode>2"
1973   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
1974    (set (match_dup 3)
1975         (minus:VI (match_dup 2)
1976                   (match_operand:VI 1 "register_operand" "v")))
1977    (set (match_operand:VI 0 "register_operand" "=v")
1978         (smax:VI (match_dup 1) (match_dup 3)))]
1979   "TARGET_ALTIVEC"
1980 {
1981   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
1982   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
1983 })
1984
1985 ;; Generate
1986 ;;    vspltisw SCRATCH1,-1
1987 ;;    vslw SCRATCH2,SCRATCH1,SCRATCH1
1988 ;;    vandc %0,%1,SCRATCH2
1989 (define_expand "absv4sf2"
1990   [(set (match_dup 2)
1991         (vec_duplicate:V4SI (const_int -1)))
1992    (set (match_dup 3)
1993         (unspec:V4SI [(match_dup 2) (match_dup 2)] UNSPEC_VSL))
1994    (set (match_operand:V4SF 0 "register_operand" "=v")
1995         (and:V4SF (not:V4SF (subreg:V4SF (match_dup 3) 0))
1996                   (match_operand:V4SF 1 "register_operand" "v")))]
1997   "TARGET_ALTIVEC"
1998 {
1999   operands[2] = gen_reg_rtx (V4SImode);
2000   operands[3] = gen_reg_rtx (V4SImode);
2001 })
2002
2003 ;; Generate
2004 ;;    vspltis? SCRATCH0,0
2005 ;;    vsubs?s SCRATCH2,SCRATCH1,%1
2006 ;;    vmaxs? %0,%1,SCRATCH2"
2007 (define_expand "altivec_abss_<mode>"
2008   [(set (match_dup 2) (vec_duplicate:VI (const_int 0)))
2009    (parallel [(set (match_dup 3)
2010                    (unspec:VI [(match_dup 2)
2011                                (match_operand:VI 1 "register_operand" "v")]
2012                               UNSPEC_VSUBS))
2013               (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))])
2014    (set (match_operand:VI 0 "register_operand" "=v")
2015         (smax:VI (match_dup 1) (match_dup 3)))]
2016   "TARGET_ALTIVEC"
2017 {
2018   operands[2] = gen_reg_rtx (GET_MODE (operands[0]));
2019   operands[3] = gen_reg_rtx (GET_MODE (operands[0]));
2020 })
2021
2022 ;; Vector shift left in bits. Currently supported ony for shift
2023 ;; amounts that can be expressed as byte shifts (divisible by 8).
2024 ;; General shift amounts can be supported using vslo + vsl. We're
2025 ;; not expecting to see these yet (the vectorizer currently
2026 ;; generates only shifts divisible by byte_size).
2027 (define_expand "vec_shl_<mode>"
2028   [(set (match_operand:V 0 "register_operand" "=v")
2029         (unspec:V [(match_operand:V 1 "register_operand" "v")
2030                    (match_operand:QI 2 "reg_or_short_operand" "")]
2031                   UNSPEC_VECSH))]
2032   "TARGET_ALTIVEC"
2033   "
2034 {
2035   rtx bitshift = operands[2];
2036   rtx byteshift = gen_reg_rtx (QImode);
2037   HOST_WIDE_INT bitshift_val;
2038   HOST_WIDE_INT byteshift_val;
2039
2040   if (! CONSTANT_P (bitshift))
2041     FAIL;
2042   bitshift_val = INTVAL (bitshift);
2043   if (bitshift_val & 0x7)
2044     FAIL;
2045   byteshift_val = bitshift_val >> 3;
2046   byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2047   emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2048                                         byteshift));
2049   DONE;
2050 }")
2051
2052 ;; Vector shift left in bits. Currently supported ony for shift
2053 ;; amounts that can be expressed as byte shifts (divisible by 8).
2054 ;; General shift amounts can be supported using vsro + vsr. We're
2055 ;; not expecting to see these yet (the vectorizer currently
2056 ;; generates only shifts divisible by byte_size).
2057 (define_expand "vec_shr_<mode>"
2058   [(set (match_operand:V 0 "register_operand" "=v")
2059         (unspec:V [(match_operand:V 1 "register_operand" "v")
2060                    (match_operand:QI 2 "reg_or_short_operand" "")]
2061                   UNSPEC_VECSH))]
2062   "TARGET_ALTIVEC"
2063   "
2064 {
2065   rtx bitshift = operands[2];
2066   rtx byteshift = gen_reg_rtx (QImode);
2067   HOST_WIDE_INT bitshift_val;
2068   HOST_WIDE_INT byteshift_val;
2069
2070   if (! CONSTANT_P (bitshift))
2071     FAIL;
2072   bitshift_val = INTVAL (bitshift);
2073   if (bitshift_val & 0x7)
2074     FAIL;
2075   byteshift_val = 16 - (bitshift_val >> 3);
2076   byteshift = gen_rtx_CONST_INT (QImode, byteshift_val);
2077   emit_insn (gen_altivec_vsldoi_<mode> (operands[0], operands[1], operands[1],
2078                                         byteshift));
2079   DONE;
2080 }")
2081
2082 (define_insn "altivec_vsumsws_nomode"
2083   [(set (match_operand 0 "register_operand" "=v")
2084         (unspec:V4SI [(match_operand:V4SI 1 "register_operand" "v")
2085                       (match_operand:V4SI 2 "register_operand" "v")]
2086                      UNSPEC_VSUMSWS))
2087    (set (reg:SI 110) (unspec:SI [(const_int 0)] UNSPEC_SET_VSCR))]
2088   "TARGET_ALTIVEC"
2089   "vsumsws %0,%1,%2"
2090   [(set_attr "type" "veccomplex")])
2091
2092 (define_expand "reduc_splus_<mode>"
2093   [(set (match_operand:VIshort 0 "register_operand" "=v")
2094         (unspec:VIshort [(match_operand:VIshort 1 "register_operand" "v")]
2095                         UNSPEC_REDUC_PLUS))]
2096   "TARGET_ALTIVEC"
2097   "
2098 {
2099   rtx vzero = gen_reg_rtx (V4SImode);
2100   rtx vtmp1 = gen_reg_rtx (V4SImode);
2101
2102   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2103   emit_insn (gen_altivec_vsum4s<VI_char>s (vtmp1, operands[1], vzero));
2104   emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2105   DONE;
2106 }")
2107
2108 (define_expand "reduc_uplus_v16qi"
2109   [(set (match_operand:V16QI 0 "register_operand" "=v")
2110         (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")]
2111                       UNSPEC_REDUC_PLUS))]
2112   "TARGET_ALTIVEC"
2113   "
2114 {
2115   rtx vzero = gen_reg_rtx (V4SImode);
2116   rtx vtmp1 = gen_reg_rtx (V4SImode);
2117
2118   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2119   emit_insn (gen_altivec_vsum4ubs (vtmp1, operands[1], vzero));
2120   emit_insn (gen_altivec_vsumsws_nomode (operands[0], vtmp1, vzero));
2121   DONE;
2122 }")
2123
2124 (define_insn "vec_realign_load_<mode>"
2125   [(set (match_operand:V 0 "register_operand" "=v")
2126         (unspec:V [(match_operand:V 1 "register_operand" "v")
2127                    (match_operand:V 2 "register_operand" "v")
2128                    (match_operand:V16QI 3 "register_operand" "v")]
2129                   UNSPEC_REALIGN_LOAD))]
2130   "TARGET_ALTIVEC"
2131   "vperm %0,%1,%2,%3"
2132   [(set_attr "type" "vecperm")])
2133
2134 (define_expand "neg<mode>2"
2135   [(use (match_operand:VI 0 "register_operand" ""))
2136    (use (match_operand:VI 1 "register_operand" ""))]
2137   "TARGET_ALTIVEC"
2138   "
2139 {
2140   rtx vzero;
2141
2142   vzero = gen_reg_rtx (GET_MODE (operands[0]));
2143   emit_insn (gen_altivec_vspltis<VI_char> (vzero, const0_rtx));
2144   emit_insn (gen_sub<mode>3 (operands[0], vzero, operands[1]));
2145
2146   DONE;
2147 }")
2148
2149 (define_expand "udot_prod<mode>"
2150   [(set (match_operand:V4SI 0 "register_operand" "=v")
2151         (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2152                    (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")
2153                                  (match_operand:VIshort 2 "register_operand" "v")]
2154                                 UNSPEC_VMSUMU)))]
2155   "TARGET_ALTIVEC"
2156   "
2157 {
2158   emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], operands[2], operands[3]));
2159   DONE;
2160 }")
2161
2162 (define_expand "sdot_prodv8hi"
2163   [(set (match_operand:V4SI 0 "register_operand" "=v")
2164         (plus:V4SI (match_operand:V4SI 3 "register_operand" "v")
2165                    (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2166                                  (match_operand:V8HI 2 "register_operand" "v")]
2167                                 UNSPEC_VMSUMSHM)))]
2168   "TARGET_ALTIVEC"
2169   "
2170 {
2171   emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], operands[2], operands[3]));
2172   DONE;
2173 }")
2174
2175 (define_expand "widen_usum<mode>3"
2176   [(set (match_operand:V4SI 0 "register_operand" "=v")
2177         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2178                    (unspec:V4SI [(match_operand:VIshort 1 "register_operand" "v")]
2179                                 UNSPEC_VMSUMU)))]
2180   "TARGET_ALTIVEC"
2181   "
2182 {
2183   rtx vones = gen_reg_rtx (GET_MODE (operands[1]));
2184
2185   emit_insn (gen_altivec_vspltis<VI_char> (vones, const1_rtx));
2186   emit_insn (gen_altivec_vmsumu<VI_char>m (operands[0], operands[1], vones, operands[2]));
2187   DONE;
2188 }")
2189
2190 (define_expand "widen_ssumv16qi3"
2191   [(set (match_operand:V4SI 0 "register_operand" "=v")
2192         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2193                    (unspec:V4SI [(match_operand:V16QI 1 "register_operand" "v")]
2194                                 UNSPEC_VMSUMM)))]
2195   "TARGET_ALTIVEC"
2196   "
2197 {
2198   rtx vones = gen_reg_rtx (V16QImode);
2199
2200   emit_insn (gen_altivec_vspltisb (vones, const1_rtx));
2201   emit_insn (gen_altivec_vmsummbm (operands[0], operands[1], vones, operands[2]));
2202   DONE;
2203 }")
2204
2205 (define_expand "widen_ssumv8hi3"
2206   [(set (match_operand:V4SI 0 "register_operand" "=v")
2207         (plus:V4SI (match_operand:V4SI 2 "register_operand" "v")
2208                    (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2209                                 UNSPEC_VMSUMSHM)))]
2210   "TARGET_ALTIVEC"
2211   "
2212 {
2213   rtx vones = gen_reg_rtx (V8HImode);
2214
2215   emit_insn (gen_altivec_vspltish (vones, const1_rtx));
2216   emit_insn (gen_altivec_vmsumshm (operands[0], operands[1], vones, operands[2]));
2217   DONE;
2218 }")
2219
2220 (define_expand "vec_unpacks_hi_v16qi"
2221   [(set (match_operand:V8HI 0 "register_operand" "=v")
2222         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2223                      UNSPEC_VUPKHSB))]
2224   "TARGET_ALTIVEC"
2225   "
2226 {
2227   emit_insn (gen_altivec_vupkhsb (operands[0], operands[1]));
2228   DONE;
2229 }")
2230
2231 (define_expand "vec_unpacks_hi_v8hi"
2232   [(set (match_operand:V4SI 0 "register_operand" "=v")
2233         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2234                      UNSPEC_VUPKHSH))]
2235   "TARGET_ALTIVEC"
2236   "
2237 {
2238   emit_insn (gen_altivec_vupkhsh (operands[0], operands[1]));
2239   DONE;
2240 }")
2241
2242 (define_expand "vec_unpacks_lo_v16qi"
2243   [(set (match_operand:V8HI 0 "register_operand" "=v")
2244         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2245                      UNSPEC_VUPKLSB))]
2246   "TARGET_ALTIVEC"
2247   "
2248 {
2249   emit_insn (gen_altivec_vupklsb (operands[0], operands[1]));
2250   DONE;
2251 }")
2252
2253 (define_expand "vec_unpacks_lo_v8hi"
2254   [(set (match_operand:V4SI 0 "register_operand" "=v")
2255         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2256                      UNSPEC_VUPKLSH))]
2257   "TARGET_ALTIVEC"
2258   "
2259 {
2260   emit_insn (gen_altivec_vupklsh (operands[0], operands[1]));
2261   DONE;
2262 }")
2263
2264 (define_insn "vperm_v8hiv4si"
2265   [(set (match_operand:V4SI 0 "register_operand" "=v")
2266         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2267                    (match_operand:V4SI 2 "register_operand" "v")
2268                    (match_operand:V16QI 3 "register_operand" "v")]
2269                   UNSPEC_VPERMSI))]
2270   "TARGET_ALTIVEC"
2271   "vperm %0,%1,%2,%3"
2272   [(set_attr "type" "vecperm")])
2273
2274 (define_insn "vperm_v16qiv8hi"
2275   [(set (match_operand:V8HI 0 "register_operand" "=v")
2276         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2277                    (match_operand:V8HI 2 "register_operand" "v")
2278                    (match_operand:V16QI 3 "register_operand" "v")]
2279                   UNSPEC_VPERMHI))]
2280   "TARGET_ALTIVEC"
2281   "vperm %0,%1,%2,%3"
2282   [(set_attr "type" "vecperm")])
2283
2284
2285 (define_expand "vec_unpacku_hi_v16qi"
2286   [(set (match_operand:V8HI 0 "register_operand" "=v")
2287         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2288                      UNSPEC_VUPKHUB))]
2289   "TARGET_ALTIVEC"
2290   "
2291 {
2292   rtx vzero = gen_reg_rtx (V8HImode);
2293   rtx mask = gen_reg_rtx (V16QImode);
2294   rtvec v = rtvec_alloc (16);
2295
2296   emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2297
2298   RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2299   RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 0);
2300   RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2301   RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2302   RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2303   RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 2);
2304   RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2305   RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2306   RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2307   RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 4);
2308   RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2309   RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2310   RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2311   RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 6);
2312   RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2313   RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2314
2315   emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2316   emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2317   DONE;
2318 }")
2319
2320 (define_expand "vec_unpacku_hi_v8hi"
2321   [(set (match_operand:V4SI 0 "register_operand" "=v")
2322         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2323                      UNSPEC_VUPKHUH))]
2324   "TARGET_ALTIVEC"
2325   "
2326 {
2327   rtx vzero = gen_reg_rtx (V4SImode);
2328   rtx mask = gen_reg_rtx (V16QImode);
2329   rtvec v = rtvec_alloc (16);
2330
2331   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2332
2333   RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2334   RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2335   RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 0);
2336   RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 1);
2337   RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2338   RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2339   RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 2);
2340   RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 3);
2341   RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2342   RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2343   RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 4);
2344   RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 5);
2345   RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2346   RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2347   RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 6);
2348   RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 7);
2349
2350   emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2351   emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2352   DONE;
2353 }")
2354
2355 (define_expand "vec_unpacku_lo_v16qi"
2356   [(set (match_operand:V8HI 0 "register_operand" "=v")
2357         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")]
2358                      UNSPEC_VUPKLUB))]
2359   "TARGET_ALTIVEC"
2360   "
2361 {
2362   rtx vzero = gen_reg_rtx (V8HImode);
2363   rtx mask = gen_reg_rtx (V16QImode);
2364   rtvec v = rtvec_alloc (16);
2365
2366   emit_insn (gen_altivec_vspltish (vzero, const0_rtx));
2367
2368   RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2369   RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 8);
2370   RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 16);
2371   RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2372   RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2373   RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 10);
2374   RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 16);
2375   RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2376   RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2377   RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 12);
2378   RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 16);
2379   RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2380   RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2381   RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 14);
2382   RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 16);
2383   RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2384
2385   emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2386   emit_insn (gen_vperm_v16qiv8hi (operands[0], operands[1], vzero, mask));
2387   DONE;
2388 }")
2389
2390 (define_expand "vec_unpacku_lo_v8hi"
2391   [(set (match_operand:V4SI 0 "register_operand" "=v")
2392         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")]
2393                      UNSPEC_VUPKLUH))]
2394   "TARGET_ALTIVEC"
2395   "
2396 {
2397   rtx vzero = gen_reg_rtx (V4SImode);
2398   rtx mask = gen_reg_rtx (V16QImode);
2399   rtvec v = rtvec_alloc (16);
2400
2401   emit_insn (gen_altivec_vspltisw (vzero, const0_rtx));
2402
2403   RTVEC_ELT (v, 0) = gen_rtx_CONST_INT (QImode, 16);
2404   RTVEC_ELT (v, 1) = gen_rtx_CONST_INT (QImode, 17);
2405   RTVEC_ELT (v, 2) = gen_rtx_CONST_INT (QImode, 8);
2406   RTVEC_ELT (v, 3) = gen_rtx_CONST_INT (QImode, 9);
2407   RTVEC_ELT (v, 4) = gen_rtx_CONST_INT (QImode, 16);
2408   RTVEC_ELT (v, 5) = gen_rtx_CONST_INT (QImode, 17);
2409   RTVEC_ELT (v, 6) = gen_rtx_CONST_INT (QImode, 10);
2410   RTVEC_ELT (v, 7) = gen_rtx_CONST_INT (QImode, 11);
2411   RTVEC_ELT (v, 8) = gen_rtx_CONST_INT (QImode, 16);
2412   RTVEC_ELT (v, 9) = gen_rtx_CONST_INT (QImode, 17);
2413   RTVEC_ELT (v, 10) = gen_rtx_CONST_INT (QImode, 12);
2414   RTVEC_ELT (v, 11) = gen_rtx_CONST_INT (QImode, 13);
2415   RTVEC_ELT (v, 12) = gen_rtx_CONST_INT (QImode, 16);
2416   RTVEC_ELT (v, 13) = gen_rtx_CONST_INT (QImode, 17);
2417   RTVEC_ELT (v, 14) = gen_rtx_CONST_INT (QImode, 14);
2418   RTVEC_ELT (v, 15) = gen_rtx_CONST_INT (QImode, 15);
2419
2420   emit_insn (gen_vec_initv16qi (mask, gen_rtx_PARALLEL (V16QImode, v)));
2421   emit_insn (gen_vperm_v8hiv4si (operands[0], operands[1], vzero, mask));
2422   DONE;
2423 }")
2424
2425 (define_expand "vec_widen_umult_hi_v16qi"
2426   [(set (match_operand:V8HI 0 "register_operand" "=v")
2427         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2428                       (match_operand:V16QI 2 "register_operand" "v")]
2429                      UNSPEC_VMULWHUB))]
2430   "TARGET_ALTIVEC"
2431   "
2432 {
2433   rtx ve = gen_reg_rtx (V8HImode);
2434   rtx vo = gen_reg_rtx (V8HImode);
2435
2436   emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2437   emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2438   emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2439   DONE;
2440 }")
2441
2442 (define_expand "vec_widen_umult_lo_v16qi"
2443   [(set (match_operand:V8HI 0 "register_operand" "=v")
2444         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2445                       (match_operand:V16QI 2 "register_operand" "v")]
2446                      UNSPEC_VMULWLUB))]
2447   "TARGET_ALTIVEC"
2448   "
2449 {
2450   rtx ve = gen_reg_rtx (V8HImode);
2451   rtx vo = gen_reg_rtx (V8HImode);
2452
2453   emit_insn (gen_altivec_vmuleub (ve, operands[1], operands[2]));
2454   emit_insn (gen_altivec_vmuloub (vo, operands[1], operands[2]));
2455   emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2456   DONE;
2457 }")
2458
2459 (define_expand "vec_widen_smult_hi_v16qi"
2460   [(set (match_operand:V8HI 0 "register_operand" "=v")
2461         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2462                       (match_operand:V16QI 2 "register_operand" "v")]
2463                      UNSPEC_VMULWHSB))]
2464   "TARGET_ALTIVEC"
2465   "
2466 {
2467   rtx ve = gen_reg_rtx (V8HImode);
2468   rtx vo = gen_reg_rtx (V8HImode);
2469
2470   emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2471   emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2472   emit_insn (gen_altivec_vmrghh (operands[0], ve, vo));
2473   DONE;
2474 }")
2475
2476 (define_expand "vec_widen_smult_lo_v16qi"
2477   [(set (match_operand:V8HI 0 "register_operand" "=v")
2478         (unspec:V8HI [(match_operand:V16QI 1 "register_operand" "v")
2479                       (match_operand:V16QI 2 "register_operand" "v")]
2480                      UNSPEC_VMULWLSB))]
2481   "TARGET_ALTIVEC"
2482   "
2483 {
2484   rtx ve = gen_reg_rtx (V8HImode);
2485   rtx vo = gen_reg_rtx (V8HImode);
2486
2487   emit_insn (gen_altivec_vmulesb (ve, operands[1], operands[2]));
2488   emit_insn (gen_altivec_vmulosb (vo, operands[1], operands[2]));
2489   emit_insn (gen_altivec_vmrglh (operands[0], ve, vo));
2490   DONE;
2491 }")
2492
2493 (define_expand "vec_widen_umult_hi_v8hi"
2494   [(set (match_operand:V4SI 0 "register_operand" "=v")
2495         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2496                       (match_operand:V8HI 2 "register_operand" "v")]
2497                      UNSPEC_VMULWHUH))]
2498   "TARGET_ALTIVEC"
2499   "
2500 {
2501   rtx ve = gen_reg_rtx (V4SImode);
2502   rtx vo = gen_reg_rtx (V4SImode);
2503
2504   emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2505   emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2506   emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2507   DONE;
2508 }")
2509
2510 (define_expand "vec_widen_umult_lo_v8hi"
2511   [(set (match_operand:V4SI 0 "register_operand" "=v")
2512         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2513                       (match_operand:V8HI 2 "register_operand" "v")]
2514                      UNSPEC_VMULWLUH))]
2515   "TARGET_ALTIVEC"
2516   "
2517 {
2518   rtx ve = gen_reg_rtx (V4SImode);
2519   rtx vo = gen_reg_rtx (V4SImode);
2520
2521   emit_insn (gen_altivec_vmuleuh (ve, operands[1], operands[2]));
2522   emit_insn (gen_altivec_vmulouh (vo, operands[1], operands[2]));
2523   emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2524   DONE;
2525 }")
2526
2527 (define_expand "vec_widen_smult_hi_v8hi"
2528   [(set (match_operand:V4SI 0 "register_operand" "=v")
2529         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2530                       (match_operand:V8HI 2 "register_operand" "v")]
2531                      UNSPEC_VMULWHSH))]
2532   "TARGET_ALTIVEC"
2533   "
2534 {
2535   rtx ve = gen_reg_rtx (V4SImode);
2536   rtx vo = gen_reg_rtx (V4SImode);
2537
2538   emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2539   emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2540   emit_insn (gen_altivec_vmrghw (operands[0], ve, vo));
2541   DONE;
2542 }")
2543
2544 (define_expand "vec_widen_smult_lo_v8hi"
2545   [(set (match_operand:V4SI 0 "register_operand" "=v")
2546         (unspec:V4SI [(match_operand:V8HI 1 "register_operand" "v")
2547                       (match_operand:V8HI 2 "register_operand" "v")]
2548                      UNSPEC_VMULWLSH))]
2549   "TARGET_ALTIVEC"
2550   "
2551 {
2552   rtx ve = gen_reg_rtx (V4SImode);
2553   rtx vo = gen_reg_rtx (V4SImode);
2554
2555   emit_insn (gen_altivec_vmulesh (ve, operands[1], operands[2]));
2556   emit_insn (gen_altivec_vmulosh (vo, operands[1], operands[2]));
2557   emit_insn (gen_altivec_vmrglw (operands[0], ve, vo));
2558   DONE;
2559 }")
2560
2561 (define_expand "vec_pack_mod_v8hi"
2562   [(set (match_operand:V16QI 0 "register_operand" "=v")
2563         (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")
2564                        (match_operand:V8HI 2 "register_operand" "v")]
2565                       UNSPEC_VPKUHUM))]
2566   "TARGET_ALTIVEC"
2567   "
2568 {
2569   emit_insn (gen_altivec_vpkuhum (operands[0], operands[1], operands[2]));
2570   DONE;
2571 }")
2572
2573 (define_expand "vec_pack_mod_v4si"
2574   [(set (match_operand:V8HI 0 "register_operand" "=v")
2575         (unspec:V8HI [(match_operand:V4SI 1 "register_operand" "v")
2576                       (match_operand:V4SI 2 "register_operand" "v")]
2577                      UNSPEC_VPKUWUM))]
2578   "TARGET_ALTIVEC"
2579   "
2580 {
2581   emit_insn (gen_altivec_vpkuwum (operands[0], operands[1], operands[2]));
2582   DONE;
2583 }")
2584
2585 (define_expand "negv4sf2"
2586   [(use (match_operand:V4SF 0 "register_operand" ""))
2587    (use (match_operand:V4SF 1 "register_operand" ""))]
2588   "TARGET_ALTIVEC"
2589   "
2590 {
2591   rtx neg0;
2592
2593   /* Generate [-0.0, -0.0, -0.0, -0.0].  */
2594   neg0 = gen_reg_rtx (V4SImode);
2595   emit_insn (gen_altivec_vspltisw (neg0, constm1_rtx));
2596   emit_insn (gen_altivec_vslw (neg0, neg0, neg0));
2597
2598   /* XOR */
2599   emit_insn (gen_xorv4sf3 (operands[0],
2600                            gen_lowpart (V4SFmode, neg0), operands[1]));
2601
2602   DONE;
2603 }")