1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001,2008, 2009 Free Software Foundation, Inc.
3 Contributed by picoChip Designs Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "basic-block.h"
44 #include "integrate.h"
50 #include "target-def.h"
51 #include "langhooks.h"
55 #include "picochip-protos.h"
57 #include "insn-attr.h" /* For DFA state_t. */
58 #include "insn-config.h" /* Required by recog.h */
59 #include "insn-codes.h" /* For CODE_FOR_? */
60 #include "optabs.h" /* For GEN_FCN */
61 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
62 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
63 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
64 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
67 /* Target AE ISA information. */
68 enum picochip_dfa_type picochip_schedule_type;
70 bool picochip_has_mul_unit = false;
71 bool picochip_has_mac_unit = false;
73 /* targetm hook function prototypes. */
75 void picochip_asm_file_start (void);
76 void picochip_asm_file_end (void);
78 void picochip_init_libfuncs (void);
79 void picochip_reorg (void);
81 int picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum,
82 enum machine_mode mode,
83 tree type, bool named);
85 int picochip_sched_lookahead (void);
86 int picochip_sched_issue_rate (void);
87 int picochip_sched_adjust_cost (rtx insn, rtx link,
88 rtx dep_insn, int cost);
89 int picochip_sched_reorder (FILE * file, int verbose, rtx * ready,
90 int *n_readyp, int clock);
92 void picochip_init_builtins (void);
93 rtx picochip_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
95 bool picochip_rtx_costs (rtx x, int code, int outer_code, int* total);
96 bool picochip_return_in_memory(const_tree type,
97 const_tree fntype ATTRIBUTE_UNUSED);
99 rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
100 rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
101 bool outgoing ATTRIBUTE_UNUSED);
103 picochip_secondary_reload (bool in_p,
104 rtx x ATTRIBUTE_UNUSED,
105 enum reg_class cla ATTRIBUTE_UNUSED,
106 enum machine_mode mode,
107 secondary_reload_info *sri);
109 picochip_asm_named_section (const char *name,
110 unsigned int flags ATTRIBUTE_UNUSED,
111 tree decl ATTRIBUTE_UNUSED);
113 /* Lookup table mapping a register number to the earliest containing
114 class. Used by REGNO_REG_CLASS. */
115 const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER] =
117 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
118 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
119 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
120 GR_REGS, FRAME_REGS, PTR_REGS, CONST_REGS,
121 ACC_REGS, CC_REGS, GR_REGS, GR_REGS
124 /* picoChip register names. */
125 const char *picochip_regnames[] = REGISTER_NAMES;
127 /* Define the maximum number of registers which may be used to pass
128 * parameters to functions. */
129 #define MAX_CALL_PARAMETER_REGS 6
132 /* Target scheduling information. */
134 /* Determine whether we run our final scheduling pass or not. We always
135 avoid the normal second scheduling pass. */
136 int picochip_flag_schedule_insns2;
138 /* Check if variable tracking needs to be run. */
139 int picochip_flag_var_tracking;
141 /* This flag indicates whether the next instruction to be output is a
142 VLIW continuation instruction. It is used to communicate between
143 final_prescan_insn and asm_output_opcode. */
144 static int picochip_vliw_continuation = 0;
146 /* This variable is used to communicate the current instruction
147 between final_prescan_insn and functions such as asm_output_opcode,
148 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
149 current instruction. */
150 static rtx picochip_current_prescan_insn;
152 static bool picochip_is_delay_slot_pending = 0;
154 /* When final_prescan_insn is called, it computes information about
155 the current VLIW packet, and stores it in this structure. When
156 instructions are output, this state is used to make sure that the
157 instructions are output in the correct way (e.g., which ALU to use,
158 whether a macro branch was ever previously a real branch, etc.). */
161 int contains_pico_alu_insn;
162 int contains_non_cc_alu_insn;
163 int num_alu_insns_so_far;
165 /* Record how many instructions are contained in the packet. */
166 int num_insns_in_packet;
168 /* There was a case for this to be more than 1 */
169 int num_cfi_labels_deferred;
170 char cfi_label_name[2][256]; /* Used to record the name of a CFI label
171 emitted inside a VLIW packet. */
172 char lm_label_name[256]; /* Used to record the name of an LM label. */
175 struct vliw_state picochip_current_vliw_state;
177 /* Save/restore recog_data. */
178 static int picochip_saved_which_alternative;
179 static struct recog_data picochip_saved_recog_data;
181 /* Determine which ALU to use for the instruction in
182 picochip_current_prescan_insn. */
183 static char picochip_get_vliw_alu_id (void);
185 /* Initialize the GCC target structure. */
187 #undef TARGET_ASM_FUNCTION_PROLOGUE
188 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
190 #undef TARGET_ASM_FUNCTION_EPILOGUE
191 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
193 #undef TARGET_ASM_INTERNAL_LABEL
194 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
196 #undef TARGET_ASM_GLOBALIZE_LABEL
197 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
199 #undef TARGET_ASM_BYTE_OP
200 #define TARGET_ASM_BYTE_OP ".initByte "
201 #undef TARGET_ASM_ALIGNED_HI_OP
202 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
203 #undef TARGET_ASM_UNALIGNED_HI_OP
204 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
205 #undef TARGET_ASM_ALIGNED_SI_OP
206 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
207 #undef TARGET_ASM_UNALIGNED_SI_OP
208 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
210 #undef TARGET_INIT_BUILTINS
211 #define TARGET_INIT_BUILTINS picochip_init_builtins
213 #undef TARGET_EXPAND_BUILTIN
214 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
216 #undef TARGET_RTX_COSTS
217 #define TARGET_RTX_COSTS picochip_rtx_costs
219 #undef TARGET_SCHED_ISSUE_RATE
220 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
222 #undef TARGET_SCHED_REORDER
223 #define TARGET_SCHED_REORDER picochip_sched_reorder
225 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
226 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
227 picochip_sched_lookahead
229 #undef TARGET_SCHED_ADJUST_COST
230 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
232 #undef TARGET_ASM_NAMED_SECTION
233 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
235 #undef TARGET_HAVE_NAMED_SECTIONS
236 #define TARGET_HAVE_NAMED_SECTIONS 1
238 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
239 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
241 #undef TARGET_INIT_LIBFUNCS
242 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
244 #undef TARGET_ASM_FILE_START
245 #define TARGET_ASM_FILE_START picochip_asm_file_start
247 #undef TARGET_ASM_FILE_END
248 #define TARGET_ASM_FILE_END picochip_asm_file_end
250 #undef TARGET_MACHINE_DEPENDENT_REORG
251 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
253 #undef TARGET_ARG_PARTIAL_BYTES
254 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
256 #undef TARGET_PROMOTE_FUNCTION_ARGS
257 #define TARGET_PROMOTE_FUNCTION_ARGS hook_bool_const_tree_true
258 #undef TARGET_PROMOTE_FUNCTION_RETURN
259 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
260 #undef TARGET_PROMOTE_PROTOTYPES
261 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
263 /* Target support for Anchored Addresses optimization */
264 #undef TARGET_MIN_ANCHOR_OFFSET
265 #define TARGET_MIN_ANCHOR_OFFSET 0
266 #undef TARGET_MAX_ANCHOR_OFFSET
267 #define TARGET_MAX_ANCHOR_OFFSET 7
268 #undef TARGET_ASM_OUTPUT_ANCHOR
269 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
271 #undef TARGET_FUNCTION_VALUE
272 #define TARGET_FUNCTION_VALUE picochip_function_value
274 #undef TARGET_LIBGCC_CMP_RETURN_MODE
275 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
278 /* Loading and storing QImode values to and from memory
279 usually requires a scratch register. */
280 #undef TARGET_SECONDARY_RELOAD
281 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
282 #undef DONT_USE_BUILTIN_SETJMP
283 #define DONT_USE_BUILTIN_SETJMP 1
285 /* How Large Values are Returned */
287 #undef TARGET_RETURN_IN_MEMORY
288 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
290 struct gcc_target targetm = TARGET_INITIALIZER;
293 /* Only return a value in memory if it is greater than 4 bytes.
294 int_size_in_bytes returns -1 for variable size objects, which go in
295 memory always. The cast to unsigned makes -1 > 8. */
298 picochip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
300 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 4);
303 /* Allow certain command options to be overriden. */
305 picochip_override_options (void)
307 /* If we are optimizing for stack, dont let inliner to inline functions
308 that could potentially increase stack size.*/
309 if (flag_conserve_stack)
311 PARAM_VALUE (PARAM_LARGE_STACK_FRAME) = 0;
312 PARAM_VALUE (PARAM_STACK_FRAME_GROWTH) = 0;
314 /* The function call overhead on picochip is not very high. Let the
315 inliner know so its heuristics become more reasonable. */
316 PARAM_VALUE (PARAM_INLINE_CALL_COST) = 2;
318 /* Turn off the elimination of unused types. The elaborator
319 generates various interesting types to represent constants,
320 generics, and so on, and it is useful to retain this information
321 in the debug output. The increased size of the debug information
322 is not really an issue for us. */
323 flag_eliminate_unused_debug_types = 0;
325 /* Even if the user specifies a -fno-omit-frame-pointer on the
326 command line, we still want to go ahead and omit frame pointer
327 usages, since we dont really have a frame pointer register.
328 So, all accesses to FP need to be converted to accesses off
330 flag_omit_frame_pointer = 1;
332 /* Turning on anchored addresses by default. This is an optimization
333 that could decrease the code size by placing anchors in data and
334 accessing offsets from the anchor for file local data variables.
335 This isnt the default at O2 as yet. */
336 flag_section_anchors = 1;
338 /* Turn off the second scheduling pass, and move it to
339 picochip_reorg, to avoid having the second jump optimisation
340 trash the instruction modes (e.g., instructions are changed to
341 TImode to mark the beginning of cycles). Two types of DFA
342 scheduling are possible: space and speed. In both cases,
343 instructions are reordered to avoid stalls (e.g., memory loads
344 stall for one cycle). Speed scheduling will also enable VLIW
345 instruction packing. VLIW instructions use more code space, so
346 VLIW scheduling is disabled when scheduling for size. */
347 picochip_flag_schedule_insns2 = flag_schedule_insns_after_reload;
348 flag_schedule_insns_after_reload = 0;
349 if (picochip_flag_schedule_insns2)
353 picochip_schedule_type = DFA_TYPE_SPACE;
356 picochip_schedule_type = DFA_TYPE_SPEED;
357 flag_delayed_branch = 0;
362 picochip_schedule_type = DFA_TYPE_NONE;
364 /* Ensure that the debug level is always at least -g2. The flow
365 analyser works at its best if it always has debug
366 information. DWARF is non-intrusive, so it makes no difference to
367 code quality if debug is always enabled. */
368 if (debug_info_level < DINFO_LEVEL_NORMAL)
370 debug_info_level = DINFO_LEVEL_NORMAL;
371 write_symbols = DWARF2_DEBUG;
374 /* Options of the form -mae=mac, and so on will be substituted by
375 the compiler driver for the appropriate byte access and multiply
376 unit ISA options. Any unrecognised AE types will end up being
377 passed to the compiler, which should reject them as invalid. */
378 if (picochip_ae_type_string != NULL)
379 error ("invalid AE type specified (%s)\n", picochip_ae_type_string);
381 /* Override any specific capabilities of the instruction set. These
382 take precedence over any capabilities inferred from the AE type,
383 regardless of where the options appear on the command line. */
384 if (picochip_mul_type_string == NULL)
386 /* Default to MEM-type multiply, for historical compatibility. */
387 picochip_has_mac_unit = false;
388 picochip_has_mul_unit = true;
392 picochip_has_mac_unit = false;
393 picochip_has_mul_unit = false;
395 if (strcmp (picochip_mul_type_string, "mul") == 0)
396 picochip_has_mul_unit = true;
397 else if (strcmp (picochip_mul_type_string, "mac") == 0)
398 picochip_has_mac_unit = true;
399 else if (strcmp (picochip_mul_type_string, "none") == 0)
400 { /* Do nothing. Unit types already set to false. */ }
402 error ("Invalid mul type specified (%s) - expected mac, mul or none",
403 picochip_mul_type_string);
409 /* Initialise the library functions to handle arithmetic on some of
412 picochip_init_libfuncs (void)
415 set_optab_libfunc (ashr_optab, DImode, "__ashrdi3");
416 set_optab_libfunc (ashl_optab, DImode, "__ashldi3");
417 set_optab_libfunc (lshr_optab, DImode, "__lshrdi3");
419 /* 64-bit signed multiplication. */
420 set_optab_libfunc (smul_optab, DImode, "__muldi3");
422 /* Signed division */
423 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
424 set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
427 set_optab_libfunc (smod_optab, HImode, "__modhi3");
428 set_optab_libfunc (smod_optab, DImode, "__moddi3");
430 /* 32-bit count leading Zeros*/
431 set_optab_libfunc (clz_optab, SImode, "_clzsi2");
433 /* 64-bit comparison */
434 set_optab_libfunc (ucmp_optab, DImode, "__ucmpdi2");
435 set_optab_libfunc (cmp_optab, DImode, "__cmpdi2");
437 /* 64-bit addition and subtraction*/
438 set_optab_libfunc (add_optab, DImode, "_adddi3");
439 set_optab_libfunc (sub_optab, DImode, "_subdi3");
442 /* Return the register class for letter C. */
444 picochip_reg_class_from_letter (unsigned c)
462 pico_leaf_reg_alloc_order[] = LEAF_REG_ALLOC_ORDER;
464 pico_nonleaf_reg_alloc_order[] = REG_ALLOC_ORDER;
467 picochip_order_regs_for_local_alloc (void)
469 /* We change the order for leaf functions alone. We put r12 at
470 the end since using it will prevent us to combine stw/ldws to
471 stl/ldl and it gives no benefit. In non-leaf functions, we
472 would anyway saveup/restore r12, so it makes sense to use it.*/
474 if (leaf_function_p())
476 memcpy ((char *)reg_alloc_order, (const char *) pico_leaf_reg_alloc_order,
477 FIRST_PSEUDO_REGISTER * sizeof (int));
481 memcpy ((char *)reg_alloc_order, (const char *) pico_nonleaf_reg_alloc_order,
482 FIRST_PSEUDO_REGISTER * sizeof (int));
486 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
488 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value, unsigned c)
493 case 'I': /* 4 bits signed. */
494 return value + 8 < 16;
495 case 'J': /* 4 bits unsigned. */
497 case 'K': /* 8 bits signed. */
498 return value + 128 < 256;
499 case 'M': /* 4-bit magnitude. */
500 return abs (value) < 16;
501 case 'N': /* 10 bits signed. */
502 return value + 512 > 1024;
503 case 'O': /* 16 bits signed. */
504 return value + 32768 < 65536;
505 default: /* Unknown letter. */
510 /* Stack utility functions. */
512 picochip_return_addr_rtx(int count, rtx frameaddr ATTRIBUTE_UNUSED)
515 return gen_rtx_REG (Pmode, LINK_REGNUM);
521 /* Emit a set of parallel register expressions used to store
522 blockmode values to pass to functions. */
524 picochip_emit_register_parallel (int size_in_units, int offset)
528 rtx vector[MAX_CALL_PARAMETER_REGS];
532 /* Compute the base register, and number of required registers. */
533 base_reg = offset / 2;
534 num_regs = size_in_units / 2;
535 if (size_in_units % 2 == 1)
538 /* Emit a register for each part of the block mode value to be
539 passed in a register. */
540 for (i = 0; i < num_regs; i++)
541 vector[i] = gen_rtx_EXPR_LIST (VOIDmode,
542 gen_rtx_REG (HImode, base_reg + i),
544 result = gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (num_regs, vector));
550 /* Emit an instruction to allocate a suitable amount of space on the
551 stack, by decrementing the stack pointer. */
553 picochip_emit_stack_allocate (int adjustment)
556 rtx stack_pointer_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
558 /* Use an addition of a negative value. */
559 insn = emit_insn (gen_addhi3 (stack_pointer_reg, stack_pointer_reg,
560 GEN_INT (-adjustment)));
562 /* Make the instruction frame related. Also add an expression note,
563 so that the correct Dwarf information is generated (see documention
564 for RTX_FRAME_RELATED_P for more details). */
565 RTX_FRAME_RELATED_P (insn) = 1;
567 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
568 gen_rtx_SET (VOIDmode, stack_pointer_reg,
569 gen_rtx_PLUS (Pmode, stack_pointer_reg,
570 GEN_INT (-adjustment))),
575 /* Emit an instruction to save a register of the given mode. The
576 offset at which to save the register is given relative to the stack
579 picochip_emit_save_register (rtx reg, int offset)
581 rtx stack_pointer, address, mem, insn;
583 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
585 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
587 mem = gen_rtx_MEM (GET_MODE (reg), address);
589 insn = emit_move_insn (mem, reg);
590 RTX_FRAME_RELATED_P (insn) = 1;
592 /* For modes other than HImode, create a note explaining that
593 multiple registers have been saved. This allows the correct DWARF
594 call frame information to be generated. */
595 switch (GET_MODE (reg))
598 /* The RTL is sufficient to explain HImode register saves. */
602 /* SImode must be broken down into parallel HImode register saves. */
610 gen_rtx_PLUS (Pmode, stack_pointer,
612 gen_rtx_REG (HImode, REGNO (reg)));
613 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 0)) = 1;
616 gen_rtx_SET (HImode, gen_rtx_MEM (HImode,
621 gen_rtx_REG (HImode, REGNO (reg) + 1));
622 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 1)) = 1;
625 gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
626 gen_rtx_PARALLEL (VOIDmode, p),
634 ("unexpected mode %s encountered in picochip_emit_save_register\n",
635 GET_MODE_NAME (GET_MODE (reg)));
640 /* Emit an instruction to restore a register of the given mode. The
641 offset from which to restore the register is given relative to the
644 picochip_emit_restore_register (rtx reg, int offset)
646 rtx stack_pointer, address, mem, insn;
648 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
650 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
652 mem = gen_rtx_MEM (GET_MODE (reg), address);
654 insn = emit_move_insn (reg, mem);
658 /* Check that the given byte offset is aligned to the given number of
661 picochip_is_aligned (int byte_offset, int bit_alignment)
663 int byte_alignment = bit_alignment / BITS_PER_UNIT;
664 return (byte_offset % byte_alignment) == 0;
667 /*****************************************************************************
670 * The following section contains code which controls how the stack is
673 * The stack is laid out as follows (high addresses first):
676 * Pretend arguments (ARG PTR)
680 * Outgoing arguments (SP)
682 * The (constant) offsets of the different areas must be calculated
683 * relative to the stack area immediately below, and aligned
684 * appropriately. For example, the frame offset is computed by
685 * determining the offset of the special register area, adding the
686 * size of the special register area, and then aligning the resulting
687 * offset correctly. In turn, the special register offset is computed
688 * from the general register offset, and so on. This enables the
689 * different offsets to change size and alignment, without requiring
690 * the code for other offset calculations to be rewritten.
692 * The argument pointer, and the frame pointer are eliminated wherever
693 * possible, by replacing them with a constant offset from the stack
694 * pointer. In the rare cases where constant offsets from the stack
695 * pointer cannot be computed, another register will be allocated to
696 * serve as the argument pointer, or the frame pointer.
698 * The save registers are stored at small offsets from the caller, to
699 * enable the more efficient SP-based ISA instructions to be used.
701 ****************************************************************************/
703 /* Compute the size of an argument in units. */
705 picochip_compute_arg_size (tree type, enum machine_mode mode)
707 int type_size_in_units = 0;
710 type_size_in_units = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
712 type_size_in_units = GET_MODE_SIZE (mode);
714 return type_size_in_units;
718 /* Determine where the next outgoing arg should be placed. */
720 picochip_function_arg (CUMULATIVE_ARGS cum, int mode, tree type,
721 int named ATTRIBUTE_UNUSED)
724 int type_align_in_units = 0;
725 int type_size_in_units;
727 int offset_overflow = 0;
729 /* VOIDmode is passed when computing the second argument to a `call'
730 pattern. This can be ignored. */
731 if (mode == VOIDmode)
734 /* Compute the alignment and size of the parameter. */
735 type_align_in_units =
736 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
737 type_size_in_units = picochip_compute_arg_size (type, mode);
739 /* Compute the correct offset (i.e., ensure that the offset meets
740 the alignment requirements). */
741 offset_overflow = cum % type_align_in_units;
742 if (offset_overflow == 0)
745 new_offset = (cum - offset_overflow) + type_align_in_units;
749 printf ("Function arg:\n");
750 printf (" Type valid: %s\n", (type ? "yes" : "no"));
751 printf (" Cumulative Value: %d\n", cum);
752 printf (" Mode: %s\n", GET_MODE_NAME (mode));
753 printf (" Type size: %i units\n", type_size_in_units);
754 printf (" Alignment: %i units\n", type_align_in_units);
755 printf (" New offset: %i\n", new_offset);
759 /* If the new offset is outside the register space, return. */
760 if (new_offset >= MAX_CALL_PARAMETER_REGS * 2)
763 /* If the end of the argument is outside the register space, then
764 the argument must overlap the register space. Return the first
765 available register. */
766 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
767 return gen_rtx_REG (HImode, new_offset / 2);
769 /* Create a register of the required mode to hold the parameter. */
770 reg = new_offset / 2;
785 return gen_rtx_REG ((enum machine_mode) mode, reg);
789 /* Empty blockmode values can be passed as arguments (e.g.,
790 * empty structs). These require no registers
791 * whatsoever. Non-empty blockmode values are passed in a set
792 * of parallel registers. */
793 if (type_size_in_units == 0)
796 return picochip_emit_register_parallel (type_size_in_units, new_offset);
801 (0, "Defaulting to stack for %s register creation\n",
802 GET_MODE_NAME (mode));
810 /* Determine where the next incoming function argument will
811 appear. Normally, this works in exactly the same way as
812 picochip_function_arg, except when the function in question is a
813 varadic function. In this case, the incoming arguments all appear
814 to be passed on the stack (actually, some of the arguments are
815 passed in registers, which are then pushed onto the stack by the
816 function prologue). */
818 picochip_incoming_function_arg (CUMULATIVE_ARGS cum, int mode,
819 tree type, int named)
825 return picochip_function_arg (cum, mode, type, named);
829 /* Gives the alignment boundary, in bits, of an argument with the
832 picochip_get_function_arg_boundary (enum machine_mode mode)
837 align = STACK_BOUNDARY;
839 align = GET_MODE_ALIGNMENT (mode);
841 if (align < PARM_BOUNDARY)
842 align = PARM_BOUNDARY;
848 /* Compute partial registers. */
850 picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum, enum machine_mode mode,
851 tree type, bool named ATTRIBUTE_UNUSED)
853 int type_align_in_units = 0;
854 int type_size_in_units;
856 int offset_overflow = 0;
858 unsigned cum = *((unsigned *) p_cum);
860 /* VOIDmode is passed when computing the second argument to a `call'
861 pattern. This can be ignored. */
862 if (mode == VOIDmode)
865 /* Compute the alignment and size of the parameter. */
866 type_align_in_units =
867 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
868 type_size_in_units = picochip_compute_arg_size (type, mode);
870 /* Compute the correct offset (i.e., ensure that the offset meets
871 the alignment requirements). */
872 offset_overflow = cum % type_align_in_units;
873 if (offset_overflow == 0)
876 new_offset = (cum - offset_overflow) + type_align_in_units;
880 printf ("Partial function arg nregs:\n");
881 printf (" Type valid: %s\n", (type ? "yes" : "no"));
882 printf (" Cumulative Value: %d\n", cum);
883 printf (" Mode: %s\n", GET_MODE_NAME (mode));
884 printf (" Type size: %i units\n", type_size_in_units);
885 printf (" Alignment: %i units\n", type_align_in_units);
886 printf (" New offset: %i\n", new_offset);
890 /* If the new offset is outside the register space, return. */
891 if (new_offset >= (MAX_CALL_PARAMETER_REGS * 2))
894 /* If the end of the argument is outside the register space, then
895 the argument must overlap the register space. Return the number
896 of bytes which are passed in registers. */
897 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
898 return ((MAX_CALL_PARAMETER_REGS * 2) - new_offset);
904 /* Advance the cumulative args counter, returning the new counter. */
906 picochip_arg_advance (const CUMULATIVE_ARGS cum, int mode,
907 tree type, int named ATTRIBUTE_UNUSED)
909 int type_align_in_units = 0;
910 int type_size_in_units;
912 int offset_overflow = 0;
914 /* VOIDmode is passed when computing the second argument to a `call'
915 pattern. This can be ignored. */
916 if (mode == VOIDmode)
919 /* Compute the alignment and size of the parameter. */
920 type_align_in_units =
921 picochip_get_function_arg_boundary (mode) / BITS_PER_UNIT;
922 type_size_in_units = picochip_compute_arg_size (type, mode);
924 /* Compute the correct offset (i.e., ensure that the offset meets
925 the alignment requirements). */
926 offset_overflow = cum % type_align_in_units;
927 if (offset_overflow == 0)
930 new_offset = (cum - offset_overflow) + type_align_in_units;
932 /* Advance past the last argument. */
933 new_offset += type_size_in_units;
939 /* Determine whether a register needs saving/restoring. It does if it
940 is live in a function, and isn't a call-used register. */
942 picochip_reg_needs_saving (int reg_num)
944 return df_regs_ever_live_p(reg_num) && !call_used_regs[reg_num];
947 /* Compute and return offset of the main frame. */
949 picochip_frame_byte_offset (void)
951 gcc_assert(picochip_is_aligned
952 (crtl->outgoing_args_size, BITS_PER_WORD));
954 return crtl->outgoing_args_size;
957 /* Return the size of the main frame. */
959 picochip_frame_size_in_bytes (void)
961 int frame_size = get_frame_size();
962 int stack_align = STACK_BOUNDARY/BITS_PER_UNIT;
963 if (!picochip_is_aligned (frame_size, STACK_BOUNDARY))
964 frame_size = frame_size + (stack_align - frame_size%stack_align);
965 gcc_assert(picochip_is_aligned (frame_size, STACK_BOUNDARY));
969 /* Compute and return the size (in bytes) of the register save/restore
970 area for the current function. This only includes the general
971 purpose registers - the special purpose stack pointer and link
972 registers are not included in this area. */
974 picochip_save_area_size_in_bytes (void)
976 int num_regs_to_save = 0;
979 /* Read through all the registers, determining which need to be saved. */
980 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
982 if (picochip_reg_needs_saving (i))
983 num_regs_to_save += 1;
986 return num_regs_to_save * UNITS_PER_WORD;
990 /* Compute and return offset of the save area base. */
992 picochip_save_area_byte_offset (void)
994 int base_offset = (picochip_frame_byte_offset () +
995 picochip_frame_size_in_bytes ());
997 gcc_assert(picochip_is_aligned (base_offset, BITS_PER_WORD));
1003 /* Compute and return offset of the special register save area. This
1004 area can be found immediately above the normal save area. It must
1005 be aligned, to allow the registers to be saved and restored as a
1008 picochip_special_save_area_byte_offset (void)
1010 int byte_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
1011 int offset = (picochip_save_area_byte_offset () +
1012 picochip_save_area_size_in_bytes ());
1014 if ((offset % byte_alignment) != 0)
1015 offset = ((offset / byte_alignment) + 1) * byte_alignment;
1021 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1023 picochip_can_eliminate_link_sp_save (void)
1025 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1026 changing during optimizations phases. So, this function returns different
1027 values when called from initial_elimination_offset and then again when it
1028 is called from prologue/epilogue generation. This means that argument
1029 accesses become wrong. This wouldnt happen only if we were not using the
1030 stack at all. The following conditions ensures that.*/
1032 return (current_function_is_leaf &&
1033 !df_regs_ever_live_p(LINK_REGNUM) &&
1034 !df_regs_ever_live_p(STACK_POINTER_REGNUM) &&
1035 (picochip_special_save_area_byte_offset() == 0) &&
1036 (crtl->args.size == 0) &&
1037 (crtl->args.pretend_args_size == 0));
1040 /* Compute the size of the special reg save area (SP and LNK). If the
1041 SP/LNK registers don't need to be saved, this area can shrink to
1044 picochip_special_save_area_size_in_bytes (void)
1048 if (picochip_can_eliminate_link_sp_save ())
1051 return 2 * UNITS_PER_WORD;
1054 /* Return the number of pretend arguments. If this function is
1055 varadic, all the incoming arguments are effectively passed on the
1056 stack. If this function has real pretend arguments (caused by a
1057 value being passed partially on the stack and partially in
1058 registers), then return the number of registers used. */
1060 picochip_pretend_arg_area_size (void)
1063 if (crtl->args.pretend_args_size != 0)
1065 gcc_assert(crtl->args.pretend_args_size % 4 == 0);
1067 return crtl->args.pretend_args_size;
1069 else if (cfun->stdarg)
1076 /* Compute and return the offset of the pretend arguments. The pretend
1077 arguments are contiguous with the incoming arguments, and must be
1078 correctly aligned. */
1080 picochip_pretend_arg_area_byte_offset (void)
1082 int base_offset = 0;
1084 base_offset = (picochip_special_save_area_byte_offset () +
1085 picochip_special_save_area_size_in_bytes ());
1087 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1088 gcc_assert(picochip_is_aligned
1089 (base_offset + picochip_pretend_arg_area_size (), STACK_BOUNDARY));
1095 /* Compute and return the offset of the incoming arguments. If a
1096 static chain is in use, this will be passed just before the other
1097 arguments. This means that the pretend argument mechanism, used in
1098 variadic functions, doesn't work properly. Thus, static chains work
1099 on their own, as do variadic functions, but not the combination of
1100 the two. This isn't really a problem. */
1102 picochip_arg_area_byte_offset (void)
1104 int base_offset = (picochip_pretend_arg_area_byte_offset () +
1105 picochip_pretend_arg_area_size ());
1107 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1108 the alignment on a 32-bit boundary must be maintained. */
1109 if (cfun->static_chain_decl != NULL)
1111 gcc_assert (!cfun->stdarg);
1115 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1122 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED, int mode)
1125 /* Special case - only one register needed. */
1126 if (GET_MODE_CLASS (mode) == MODE_CC)
1129 /* We actually do not allocate acc0 ever. But, it seems like we need to
1130 make it look like a allocatable register for the dataflow checks to work
1131 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1136 /* General case - compute how much space in terms of units. */
1137 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1142 picochip_class_max_nregs (int class, int mode)
1144 int size = ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1146 if (class == ACC_REGS)
1149 if (GET_MODE_CLASS (mode) == MODE_CC)
1156 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1157 argument pointer) by replacing it with a constant offset from the
1158 main stack register. */
1160 initial_elimination_offset (int from, int to)
1162 int offset_from_sp = 0;
1164 if (FRAME_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1165 offset_from_sp = picochip_frame_byte_offset ();
1166 else if (ARG_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1167 offset_from_sp = picochip_pretend_arg_area_byte_offset ();
1171 return offset_from_sp;
1175 /* Compute and return the size of the incoming argument area. */
1177 picochip_arg_area_size_in_bytes (void)
1179 return crtl->args.size;
1182 /* Determine whether the given register is valid. When the strict mode
1183 is used, only hard registers are valid, otherwise any register is
1186 picochip_legitimate_address_register (rtx x, unsigned strict)
1189 /* Sanity check - non-registers shouldn't make it here, but... */
1190 if (REG != GET_CODE (x))
1194 return REGNO (x) < FIRST_NONHARD_REGISTER;
1200 /* Determine whether the given constant is in the range required for
1201 the given base register. */
1203 picochip_const_ok_for_base (enum machine_mode mode, int regno, int offset)
1205 HOST_WIDE_INT corrected_offset;
1207 if (GET_MODE_SIZE (mode) != 0)
1209 if (GET_MODE_SIZE(mode) <= 4)
1211 /* We used to allow incorrect offsets if strict is 0. But, this would
1212 then rely on reload doing the right thing. We have had problems
1213 there before, and on > 4.3 compiler, there are no benefits. */
1214 if (offset % GET_MODE_SIZE (mode) != 0)
1216 corrected_offset = offset / GET_MODE_SIZE (mode);
1220 if (offset % 4 != 0)
1222 corrected_offset = offset / 4;
1227 /* Default to the byte offset as supplied. */
1228 corrected_offset = offset;
1231 /* The offset from the base register can be different depending upon
1232 the base register. The stack/frame/argument pointer offsets can
1233 all be greater than a simple register-based offset. Note that the
1234 frame/argument pointer registers are actually eliminations of the
1235 stack pointer, so a value which is valid for an offset to, for
1236 example, the frame pointer, might be invalid for the stack
1237 pointer once the elimination has occurred. However, there is no
1238 need to handle this special case here, as the stack offset is
1239 always checked after elimination anyway, and the generated code
1240 seems to have identical performance. */
1241 if (regno == STACK_POINTER_REGNUM ||
1242 regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1243 return picochip_const_ok_for_letter_p (corrected_offset, 'K');
1245 return picochip_const_ok_for_letter_p (corrected_offset, 'J');
1249 /* Determine whether a given rtx is a legitimate address for machine_mode
1250 MODE. STRICT is non-zero if we're being strict - any pseudo that
1251 is not a hard register must be a memory reference. */
1253 picochip_legitimate_address_p (int mode, rtx x, unsigned strict)
1257 switch (GET_CODE (x))
1260 valid = picochip_legitimate_address_register (x, strict);
1265 rtx base = XEXP (x, 0);
1266 rtx offset = XEXP (x, 1);
1268 valid = (REG == GET_CODE (base) &&
1269 REGNO_OK_FOR_BASE_P (REGNO(base)) &&
1270 picochip_legitimate_address_register (base, strict) &&
1271 CONST_INT == GET_CODE (offset) &&
1272 picochip_const_ok_for_base (mode, REGNO (base),
1278 /* The user can select whether a symbol can be used as a memory
1279 address. Typically, this will decrease execution time (no
1280 register load is required first), but will increase code size
1281 (because the symbol will be used several times, rather than
1282 loaded once into a register.*/
1283 valid = TARGET_SYMBOL_AS_ADDRESS;
1288 /* A constant memory address must be a (plus (symbol_ref)
1289 (const_int)), and is only allowed when the symbols are
1290 permitted addresses. */
1291 rtx inner = XEXP (x, 0);
1293 valid = (TARGET_SYMBOL_AS_ADDRESS &&
1294 PLUS == GET_CODE (inner) &&
1295 SYMBOL_REF == GET_CODE (XEXP (inner, 0)) &&
1296 CONST_INT == GET_CODE (XEXP (inner, 1)));
1310 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1312 picochip_symbol_offset (rtx operand)
1315 return (PLUS == GET_CODE (operand) &&
1316 SYMBOL_REF == GET_CODE (XEXP (operand, 0)) &&
1317 CONST_INT == GET_CODE (XEXP (operand, 1)));
1321 /* Assembly output. */
1323 /* The format here should match the format used in the output of
1324 symbol_ref's elsewhere in this file. */
1326 picochip_output_label (FILE * stream, const char name[])
1328 int is_cfi_label = (strncmp (name, "picoMark_LCFI", 13) == 0);
1330 /* If VLIW scheduling is in use, any Call Frame Information labels
1331 generated inside a packet must have their output deferred until
1332 the end of the packet. */
1333 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1334 is_cfi_label && picochip_vliw_continuation)
1336 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1338 internal_error ("LCFI labels have already been deferred.");
1340 strcpy (picochip_current_vliw_state.cfi_label_name[
1341 picochip_current_vliw_state.num_cfi_labels_deferred], name);
1342 picochip_current_vliw_state.num_cfi_labels_deferred++;
1346 assemble_name (stream, name);
1348 if (strncmp (name, "picoMark_", 9) == 0)
1349 fprintf (stream, "=\n");
1351 fprintf (stream, ":\n");
1357 /* The format here should match the format used in the output of
1358 symbol_ref's elsewhere in this file. */
1360 picochip_output_labelref (FILE * stream, const char name[])
1362 fprintf (stream, "_%s", name);
1366 picochip_weaken_label (FILE * stream, const char name[])
1368 fprintf (stream, ".weak ");
1369 assemble_name (stream, name);
1370 fprintf (stream, "\n");
1373 /* Return true if the given label (or label prefix) denotes a marker
1374 label which should be emitted in the form LABEL= */
1376 picochip_is_marker_prefix (const char *prefix)
1378 return (strcmp (prefix, "L") != 0 && strcmp (prefix, "LC") != 0
1379 && strcmp (prefix, "LP") != 0);
1383 picochip_output_internal_label (FILE * stream, const char *prefix,
1387 /* Emit different types of label, based upon their prefix. They
1388 are handled differently to allow the assembler to ensure that
1389 branch target labels are properly aligned, while other labels
1390 will only serve as code markers, not branch targets. Aligning
1391 labels unnecessarily can result in much code wastage. */
1392 if (picochip_is_marker_prefix (prefix))
1394 /* Special label marker. If it appears in the middle of a VLIW
1395 packet, defer it until the end of the packet. There has
1396 never been a need to handle more than one lm label at a time. */
1397 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1398 (strcmp (prefix, "LM")) == 0 && picochip_vliw_continuation)
1400 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1401 internal_error ("LM label has already been deferred.");
1403 sprintf (picochip_current_vliw_state.lm_label_name,
1404 "picoMark_%s%ld", prefix, num);
1409 fprintf (stream, "_picoMark_%s%ld=\n", prefix, num);
1416 fprintf (stream, "_%s%ld:\n", prefix, num);
1422 picochip_generate_internal_label (char *str, const char *prefix, long num)
1424 /* Two types of internal label can be generated: branch target
1425 labels and code marker labels. Branch target labels must always
1426 be aligned (since code will execute at these
1427 points). Differentiate between the two by prepending markers with
1428 a unique prefix, which can later be used in output_label to
1429 figure out which label syntax to use. */
1430 if (picochip_is_marker_prefix (prefix))
1431 sprintf (str, "picoMark_%s%ld", prefix, num);
1433 sprintf (str, "%s%ld", prefix, num);
1438 picochip_asm_output_anchor (rtx symbol)
1440 fprintf (asm_out_file, ".offsetData _%s, ",XSTR (symbol, 0));
1441 fprintf (asm_out_file, "+ " HOST_WIDE_INT_PRINT_DEC"\n",SYMBOL_REF_BLOCK_OFFSET(symbol));
1445 picochip_output_aligned_common (FILE * stream, const char *name,
1446 unsigned size, unsigned alignment)
1449 fprintf (stream, ".commonData ");
1450 assemble_name (stream, name);
1451 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1452 picochip_output_global (stream, name);
1457 picochip_output_aligned_local (FILE * stream, const char *name,
1458 unsigned size, unsigned alignment)
1461 fprintf (stream, ".commonData ");
1462 assemble_name (stream, name);
1463 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1468 picochip_output_global (FILE * stream, const char *name)
1470 fprintf (stream, ".global ");
1471 assemble_name (stream, name);
1472 fprintf (stream, "\n");
1475 /* Output an assembly language string. Output as a sequence of decimal
1476 numbers, followed by the literal string to make it obvious what the
1477 numbers represent. */
1479 picochip_output_ascii (FILE * file, const char *str, int length)
1483 fprintf (file, ".ascii ");
1485 for (i = 0; i < length; ++i)
1487 fprintf (file, "16#%hhx# ", (char) (str[i]));
1490 fprintf (file, " ; ");
1492 for (i = 0; i < length; ++i)
1499 fprintf (file, "\\n");
1502 fprintf (file, "\\t");
1505 fprintf (file, "\\0");
1508 fprintf (file, "%c", c);
1513 fprintf (file, "\n");
1517 /* Output the beginning of an ASM file. */
1519 picochip_asm_file_start (void)
1521 default_file_start ();
1523 fprintf (asm_out_file, "// picoChip ASM file\n");
1524 fprintf (asm_out_file, "//.file \"%s\"\n", main_input_filename);
1526 fprintf (asm_out_file, "// Has byte access: %s\n",
1527 (TARGET_HAS_BYTE_ACCESS ? "Yes" : "No"));
1529 if (TARGET_HAS_MUL_UNIT)
1530 fprintf (asm_out_file, "// Has multiply: Yes (Multiply unit)\n");
1531 else if (TARGET_HAS_MAC_UNIT)
1532 fprintf (asm_out_file, "// Has multiply: Yes (Mac unit)\n");
1534 fprintf (asm_out_file, "// Has multiply: No\n");
1536 /* Variable tracking should be run after all optimizations which change order
1537 of insns. It also needs a valid CFG. This can't be done in
1538 picochip_override_options, because flag_var_tracking is finalized after
1540 picochip_flag_var_tracking = flag_var_tracking;
1541 flag_var_tracking = 0;
1544 /* Output the end of an ASM file. */
1546 picochip_asm_file_end (void)
1548 /* Include a segment end to make it easy for PERL scripts to grab
1549 segments. This is now done by assembler*/
1551 fprintf (asm_out_file, "// End of picoChip ASM file\n");
1555 /* Output frame debug information to the given stream. */
1557 picochip_output_frame_debug (FILE * file)
1561 if (current_function_is_leaf)
1562 fprintf (file, "\t\t// Leaf function\n");
1564 fprintf (file, "\t\t// Non-leaf function\n");
1566 if (picochip_can_eliminate_link_sp_save ())
1567 fprintf (file, "\t\t// Link/fp save/restore can be eliminated\n");
1569 if (cfun->static_chain_decl != NULL)
1570 fprintf (file, "\t\t// Static chain in use\n");
1572 fprintf (file, "\t\t// Incoming argument size: %d bytes\n",
1573 picochip_arg_area_size_in_bytes ());
1574 fprintf (file, "\t\t// Incoming arg offset: %d\n",
1575 picochip_arg_area_byte_offset ());
1576 fprintf (file, "\t\t// Pretend arg size: %d\n",
1577 picochip_pretend_arg_area_size ());
1578 fprintf (file, "\t\t// Pretend arg offset (ARGP): %d\n",
1579 picochip_pretend_arg_area_byte_offset ());
1580 fprintf (file, "\t\t// Special reg area size: %d bytes\n",
1581 picochip_special_save_area_size_in_bytes ());
1582 fprintf (file, "\t\t// Special reg area offset: %d\n",
1583 picochip_special_save_area_byte_offset ());
1585 /* Output which registers are saved. */
1586 fprintf (file, "\t\t// Saved regs: ");
1587 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1589 if (picochip_reg_needs_saving (i))
1590 fprintf (file, "%s ", picochip_regnames[i]);
1592 fprintf (file, "\t\t\n");
1594 fprintf (file, "\t\t// Save area size: %d bytes\n",
1595 picochip_save_area_size_in_bytes ());
1596 fprintf (file, "\t\t// Save area offset: %d\n",
1597 picochip_save_area_byte_offset ());
1599 fprintf (file, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1600 fprintf (file, "\t\t// Frame offset (FP): %d\n",
1601 picochip_frame_byte_offset ());
1603 fprintf (file, "\t\t// Outgoing argument area size: %d bytes\n",
1604 crtl->outgoing_args_size);
1608 /* Output picoChip function prologue. This contains human-readable
1609 information about the function. */
1611 picochip_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1613 /* Get the function's name, as described by its RTL. This may be
1614 different from the DECL_NAME name used in the source file. The
1615 real declaration name must be used, to ensure that the prologue
1616 emits the right information for the linker. */
1619 x = DECL_RTL (current_function_decl);
1620 gcc_assert (MEM_P (x));
1622 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1623 fnname = XSTR (x, 0);
1625 /* Note that the name of the function is given in the &_%s
1626 form. This matches the name of the function as used in labels,
1627 and function calls, and enables processCallGraph to match
1628 function calls to the name of the function, as defined here. */
1629 fprintf (file, "// picoChip Function Prologue : &_%s = %d bytes\n",
1630 fnname, picochip_arg_area_byte_offset ());
1632 picochip_output_frame_debug (file);
1633 fprintf (file, "\n");
1637 /* Output picoChip function epilogue. */
1639 picochip_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1644 x = DECL_RTL (current_function_decl);
1645 gcc_assert (MEM_P (x));
1647 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1648 fnname = XSTR (x, 0);
1649 fprintf (file, "\n// picoChip Function Epilogue : %s\n\n",
1653 /* Manipulate the asm output. Some machines only execute the code when
1654 there is actually a chance of needing it (e.g., FRV doesn't execute
1655 it if the scheduling pass wasn't used). We always execute it,
1656 simple to ensure that it is exercised more often, and bugs are more
1659 This function's prime reason for existence is to insert the VLIW
1660 separators where appropriate. The separators must be inserted
1661 before any comments which appear at the end of the file.
1665 picochip_asm_output_opcode (FILE * f, const char *ptr)
1669 /* Flag to specify when a VLIW continuation has been inserted onto
1670 the line. Continuations are either inserted before any comments,
1671 or before the end of the line is reached. The flag ensures that
1672 we don't insert continuations twice (i.e., at the comment and the
1674 int continuation_inserted = 0;
1676 /* If the instruction uses multiple lines (i.e., a new line
1677 character appears in the opcode), then ensure that no attempt is
1678 made to pack it into a VLIW. */
1679 if (strchr (ptr, '\n') != NULL && picochip_vliw_continuation)
1681 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s\n",
1685 /* If a delay slot is pending, output the directive to the assembler
1686 before the instruction. */
1687 if (picochip_is_delay_slot_pending)
1689 picochip_is_delay_slot_pending = 0;
1693 /* Keep going for entire opcode. All substitution performed ourselves. */
1698 /* Determine whether a VLIW continuation must be inserted before
1699 any comments, or the end of the opcode. A flag is set to show
1700 that we have inserted a continuation on this line, so that we
1701 don't try to insert another continuation when the end of the
1702 opcode is reached. The only other case for a continuation
1703 might have been a newline, but these aren't allowed in
1704 conjunction with VLIW continuations (see above code). */
1705 if (picochip_vliw_continuation &&
1706 !continuation_inserted &&
1707 ((c == '/' && (*ptr == '/')) || *ptr == '\0'))
1710 continuation_inserted = 1;
1713 /* Detect an explicit VLIW separator. */
1714 if (c == '%' && (*ptr == '|'))
1719 /* Detect the need for an ALU id operand. */
1720 else if (c == '%' && (*ptr == '#'))
1722 fputc (picochip_get_vliw_alu_id (), f);
1725 printf ("Generated ALU char at %s for insn %d\n", ptr,
1726 INSN_UID (picochip_current_prescan_insn));
1728 /* Skip past unwanted # */
1731 /* Detect the need for branch delay slot. */
1732 else if (c == '%' && (*ptr == '>'))
1734 /* Only emit delay slots (NOP's, or otherwise) when delay
1735 * slot scheduling has actually been enabled, otherwise VLIW
1736 * scheduling and delay slot scheduling output combine to
1737 * produce nasty effects. */
1738 if (flag_delayed_branch)
1740 if (dbr_sequence_length () == 0)
1741 fputs ("\n=->\tNOP", f);
1743 picochip_is_delay_slot_pending = 1;
1746 /* Skip past unwanted > */
1749 /* Detect any %digit specifiers. */
1750 else if (c == '%' && (*ptr >= '0' && *ptr <= '9'))
1753 picochip_print_operand (f, recog_data.operand[c], 0);
1754 while ((c = *ptr) >= '0' && c <= '9')
1757 /* Detect any %letterdigit specifiers. */
1758 else if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
1759 || (*ptr >= 'A' && *ptr <= 'Z')))
1761 int letter = *ptr++;
1768 output_asm_label (recog_data.operand[c]);
1772 output_address (recog_data.operand[c]);
1776 picochip_print_operand (f, recog_data.operand[c], letter);
1779 while ((c = *ptr) >= '0' && c <= '9')
1784 ("picochip_asm_output_opcode - can't output unknown operator %c\n",
1790 /* Reached the end of the packet. If any labels were deferred
1791 during output, emit them now. */
1792 if (!picochip_vliw_continuation)
1794 if (picochip_current_vliw_state.num_cfi_labels_deferred != 0)
1797 assemble_name (f, picochip_current_vliw_state.cfi_label_name[0]);
1799 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1802 assemble_name (f, picochip_current_vliw_state.cfi_label_name[1]);
1807 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1810 assemble_name (f, picochip_current_vliw_state.lm_label_name);
1815 /* Output an end-of-packet marker if requested. */
1816 if (!picochip_vliw_continuation &&
1817 TARGET_DEBUG && picochip_schedule_type == DFA_TYPE_SPEED)
1818 fprintf (f, "\n\t//-------------- End of VLIW packet -----------------");
1823 /* Function RTL expansion. */
1825 /* Expand the prologue into RTL. */
1827 picochip_expand_prologue (void)
1829 int stack_adjustment = 0;
1830 int special_save_offset = 0;
1831 int general_save_offset = 0;
1832 int reg_save_offset = 0;
1835 stack_adjustment = picochip_arg_area_byte_offset ();
1836 general_save_offset =
1837 -(stack_adjustment - picochip_save_area_byte_offset ());
1838 special_save_offset =
1839 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1841 /* Save the link registers. We could try to save just one register
1842 here. This would reduce the amount of stack space required.
1843 There hasnt been a good reason to do that so far. */
1844 if (!picochip_can_eliminate_link_sp_save ())
1845 picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
1846 special_save_offset);
1848 /* Save callee-save registers. */
1849 reg_save_offset = 0;
1850 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1852 if (picochip_reg_needs_saving (i))
1855 /* If this register is an even numbered register, and the
1856 next register also needs to be saved, use a SImode save,
1857 which does both in one instruction. Note that a special
1858 check is performed to ensure that the double word aligned
1859 store is valid (e.g., it is possible that r6, r8, r9 need
1860 to be saved, in which case once r6 has been saved, the
1861 stored offset is no longer aligned, and an STL/LDL
1862 instruction becomes invalid). Alternately, we could store all
1863 aligned registers first and then save the single one(s). */
1865 picochip_reg_needs_saving (i + 1) &&
1866 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1868 picochip_emit_save_register (gen_rtx_REG (SImode, i),
1869 general_save_offset +
1871 reg_save_offset += 2 * UNITS_PER_WORD;
1876 picochip_emit_save_register (gen_rtx_REG (HImode, i),
1877 general_save_offset +
1879 reg_save_offset += UNITS_PER_WORD;
1885 /* Emit a stack adjustment where required. */
1886 if (stack_adjustment != 0)
1887 picochip_emit_stack_allocate (stack_adjustment);
1889 /* If this function uses varadic arguments, write any unnamed
1890 registers to the stack. */
1893 int stdarg_offset = picochip_pretend_arg_area_byte_offset ();
1895 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
1896 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
1898 picochip_emit_save_register (gen_rtx_REG (SImode, 0), stdarg_offset);
1899 picochip_emit_save_register (gen_rtx_REG (SImode, 2),
1901 picochip_emit_save_register (gen_rtx_REG (SImode, 4),
1908 /* Expand the epilogue into RTL. */
1910 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED)
1912 int stack_adjustment = 0;
1913 int special_save_offset = 0;
1914 int general_save_offset = 0;
1915 int reg_save_offset = 0;
1917 int use_link_fp_restore_stack_adjust = 0; /* Default to using an explicit
1920 stack_adjustment = picochip_arg_area_byte_offset ();
1921 general_save_offset =
1922 -(stack_adjustment - picochip_save_area_byte_offset ());
1923 special_save_offset =
1924 -(stack_adjustment - picochip_special_save_area_byte_offset ());
1926 /* Emit a stack adjustment where required. */
1927 if (stack_adjustment != 0)
1929 /* If the link/fp is already being restored, and the offset to
1930 their save location is small enough, don't bother adjusting
1931 the stack explicitly. */
1932 if (picochip_special_save_area_byte_offset () < 512 &&
1933 !picochip_can_eliminate_link_sp_save ())
1934 use_link_fp_restore_stack_adjust = 1;
1936 /* Explicitly restore the stack. */
1937 picochip_emit_stack_allocate (-stack_adjustment);
1940 /* Restore the Link/FP registers. Only save the link register? */
1941 if (!picochip_can_eliminate_link_sp_save ())
1943 if (use_link_fp_restore_stack_adjust)
1944 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1945 picochip_special_save_area_byte_offset
1948 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
1949 special_save_offset);
1952 /* Restore callee-save registers. */
1953 reg_save_offset = 0;
1954 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1956 if (picochip_reg_needs_saving (i))
1959 /* If this register is an even numbered register, and the
1960 next register also needs to be saved, use a SImode save,
1961 which does both in one instruction. Note that a special
1962 check is performed to ensure that the double word aligned
1963 store is valid (e.g., it is possible that r6, r8, r9 need
1964 to be saved, in which case once r6 has been saved, the
1965 stored offset is no longer aligned, and an STL/LDL
1966 instruction becomes invalid). We could store all aligned
1967 registers first, and then save the single one(s). */
1969 picochip_reg_needs_saving (i + 1) &&
1970 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
1972 picochip_emit_restore_register (gen_rtx_REG (SImode, i),
1973 general_save_offset +
1975 reg_save_offset += 2 * UNITS_PER_WORD;
1980 picochip_emit_restore_register (gen_rtx_REG (HImode, i),
1981 general_save_offset +
1983 reg_save_offset += UNITS_PER_WORD;
1989 /* Emit a return instruction, which matches a (parallel
1990 [(return) (use r12)]) */
1993 p = rtvec_alloc (2);
1995 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
1996 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
1997 gen_rtx_REG (Pmode, LINK_REGNUM));
1998 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
2003 /* Assembly instruction output. */
2005 /* Test whether the given branch instruction is short, or long. Short
2006 * branches are equivalent to real branches, and may be DFA
2007 * scheduled. Long branches expand to a macro which is handled by the
2008 * elaborator, and cannot be scheduled. Occasionally, the branch
2009 * shortening pass, which is run after DFA scheduling, will change the
2010 * code layout and cause the short branch to be reverted into a long
2011 * branch. Instead of having to fix this up by emitting new assembly,
2012 * the short branch is emitted anyway. There is plenty of slack in the
2013 * calculation of long and short branches (10-bit offset, but only
2014 * 9-bits used in computation), so there is enough slack for this to
2017 picochip_is_short_branch (rtx insn)
2019 int isRealShortBranch = (get_attr_length(insn) == SHORT_BRANCH_LENGTH);
2021 return (isRealShortBranch ||
2022 (!isRealShortBranch &&
2023 picochip_current_vliw_state.num_insns_in_packet > 1));
2026 /* Output a compare-and-branch instruction (matching the cbranch
2029 picochip_output_cbranch (rtx operands[])
2032 if (HImode != GET_MODE (operands[1]) ||
2033 (HImode != GET_MODE (operands[2]) &&
2034 GET_CODE (operands[2]) != CONST_INT))
2036 internal_error ("%s: At least one operand can't be handled",
2040 /* Use the type of comparison to output the appropriate condition
2042 switch (GET_CODE (operands[0]))
2045 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2048 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2051 /* Reverse the operand order to be GE */
2052 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2055 /* Reverse operand order of GEU. */
2056 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2059 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2062 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2065 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2068 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2071 /* Reversed operand version of LT. */
2072 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2075 /* Reverse an LTU. */
2076 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2083 /* Output a compare-and-branch instruction (matching the cbranch
2084 pattern). This function is current unused since the cbranch
2085 split is disabled. The function is kept around so we can use
2086 it when we understand how to do cbranch split safely. */
2088 picochip_output_compare (rtx operands[])
2091 if (HImode != GET_MODE (operands[1]) ||
2092 (HImode != GET_MODE (operands[2]) &&
2093 GET_CODE (operands[2]) != CONST_INT))
2095 internal_error ("%s: At least one operand can't be handled",
2099 /* Use the type of comparison to output the appropriate condition
2101 int code = GET_CODE (operands[0]);
2105 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2108 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2111 /* Reverse the operand order to be GE */
2112 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2115 /* Reverse operand order of GEU. */
2116 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2119 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2122 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2125 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2128 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2131 /* Reversed operand version of LT. */
2132 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2135 /* Reverse an LTU. */
2136 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2143 /* Output the branch insn part of a compare-and-branch split. */
2145 picochip_output_branch (rtx operands[], rtx insn)
2148 int code = GET_CODE(operands[2]);
2149 if (picochip_is_short_branch (insn))
2151 /* Short branches can be output directly using the
2152 appropriate instruction. */
2156 return ("BNE %l0 %>");
2158 return ("BEQ %l0 %>");
2160 return ("BGE %l0 %>");
2162 return ("BHS %l0 %>");
2164 return ("BGE %l0 %>");
2166 return ("BHS %l0 %>");
2168 return ("BLT %l0 %>");
2170 return ("BLO %l0 %>");
2172 return ("BLT %l0 %>");
2174 return ("BLO %l0 %>");
2176 internal_error ("Unknown short branch in %s (type %d)\n",
2177 __FUNCTION__, (int) INTVAL (operands[1]));
2178 return "UNKNOWN_BRANCH";
2183 /* Long branches result in the emission of a special
2184 instruction, which the assembler expands into a suitable long
2187 /* Use the type of comparison to output the appropriate condition
2192 return ("JMPNE %l0 %>");
2194 return ("JMPEQ %l0 %>");
2196 return ("JMPGE %l0 %>");
2198 return ("JMPHS %l0 %>");
2200 return ("JMPGE %l0 %>");
2202 return ("JMPHS %l0 %>");
2204 return ("JMPLT %l0 %>");
2206 return ("JMPLO %l0 %>");
2208 return ("JMPLT %l0 %>");
2210 return ("JMPLO %l0 %>");
2213 internal_error ("Unknown long branch in %s (type %d)\n",
2214 __FUNCTION__, (int) INTVAL (operands[1]));
2215 return "UNKNOWN_BRANCH";
2221 /* Output a jump instruction. */
2223 picochip_output_jump (rtx insn)
2225 if (picochip_is_short_branch (insn))
2228 return "JMPRA %l0%>";
2232 picochip_output_put_array (int alternative, rtx operands[])
2234 /* Local output buffer. */
2237 int portArraySize = INTVAL(operands[1]);
2238 int portBaseIndex = INTVAL(operands[2]);
2240 if (alternative == 0)
2242 sprintf (buf, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2243 portArraySize, portBaseIndex);
2244 output_asm_insn (buf, operands);
2246 else if (alternative == 1)
2248 /* Constant port id. Emit a real instruction. */
2249 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2250 if (portIndex < portBaseIndex ||
2251 portIndex >= (portBaseIndex + portArraySize))
2253 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2254 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2256 sprintf(buf, "PUT R[0:1],%d", portIndex);
2257 output_asm_insn (buf, operands);
2262 /* Both alternatives output the insn directly. */
2266 const char *picochip_output_get_array (int alternative, rtx operands[])
2268 /* Local output buffer. */
2271 int portArraySize = INTVAL(operands[1]);
2272 int portBaseIndex = INTVAL(operands[2]);
2274 if (alternative == 0)
2276 sprintf (buf, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2277 portArraySize, portBaseIndex);
2278 output_asm_insn (buf, operands);
2280 else if (alternative == 1)
2282 /* Constant port id. Emit a real instruction. */
2283 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2284 if (portIndex < portBaseIndex ||
2285 portIndex >= (portBaseIndex + portArraySize))
2287 error ("GET uses port array index %d, which is out of range [%d..%d)",
2288 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2290 sprintf(buf, "GET %d,R[0:1]", portIndex);
2291 output_asm_insn (buf, operands);
2296 /* Both alternatives output the insn directly. */
2300 const char *picochip_output_testport_array (int alternative, rtx operands[])
2302 /* Local output buffer. */
2305 int portArraySize = INTVAL(operands[2]);
2306 int portBaseIndex = INTVAL(operands[3]);
2308 if (alternative == 0)
2310 sprintf (buf, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2311 portArraySize, portBaseIndex);
2312 output_asm_insn (buf, operands);
2314 else if (alternative == 1)
2316 /* Constant port id. Emit a real instruction. */
2317 int portIndex = INTVAL(operands[1]) + portBaseIndex;
2318 if (portIndex < portBaseIndex ||
2319 portIndex >= (portBaseIndex + portArraySize))
2321 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2322 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2324 sprintf(buf, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex);
2325 output_asm_insn (buf, operands);
2330 /* Both alternatives output the insn directly. */
2334 /* Output a comparison operand as a symbol (e.g., >). */
2336 picochip_print_comparison (FILE * file, rtx operand, int letter)
2341 /* Output just the comparison symbol. */
2342 switch (GET_CODE (operand))
2345 fprintf (file, "!=");
2348 fprintf (file, "==");
2351 fprintf (file, ">=");
2354 fprintf (file, ">={U}");
2357 fprintf (file, "<");
2360 fprintf (file, "<{U}");
2363 fprintf (file, "<=");
2366 fprintf (file, "<={U}");
2369 fprintf (file, ">");
2372 fprintf (file, ">{U}");
2380 /* Output the comparison formatted as operand,symbol,operand */
2381 rtx op0 = XEXP (operand, 0);
2382 rtx op1 = XEXP (operand, 1);
2384 picochip_print_operand (file, op0, 0);
2385 picochip_print_comparison (file, operand, 'i');
2386 picochip_print_operand (file, op1, 0);
2390 /* This function generates a memory address operand in the given
2391 mode. That is, if the address contains a constant offset, then the
2392 offset is divided by the required mode size to compute the
2393 mode specific offset. By default, picochip_print_operand_address calls
2394 this function using the natural mode of the operand, but special
2395 operand codes can be used to invoke the computation using an
2396 unnatural mode (e.g., compute the HI aligned address of an SI mode
2399 picochip_print_memory_address (FILE * file, rtx operand,
2400 enum machine_mode mode)
2402 rtx address = XEXP (operand, 0);
2405 if (MEM != GET_CODE (operand))
2406 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2411 printf ("picochip_print_memory_address: ");
2412 print_rtl (stdout, operand);
2416 switch (GET_CODE (address))
2420 /* Grab the address components. */
2421 rtx base = XEXP (address, 0);
2422 rtx offset = XEXP (address, 1);
2424 /* Only handle reg+const addresses */
2425 if (REG == GET_CODE (base) && CONST_INT == GET_CODE (offset))
2427 /* Sanity check. If an FP+offset address is given, ensure
2428 that the offset lies within the given frame, or a lower
2430 if (REGNO (base) == STACK_POINTER_REGNUM )
2431 gcc_assert (INTVAL (offset) <= (picochip_arg_area_byte_offset () +
2434 /* Print the base register - identical for all modes. */
2435 fprintf (file, "(");
2436 picochip_print_operand (file, base, 'r');
2437 fprintf (file, ")");
2439 /* Print the constant offset with compensation for the mode. */
2443 picochip_print_operand (file, offset, 'Q');
2447 picochip_print_operand (file, offset, 'H');
2452 picochip_print_operand (file, offset, 'S');
2456 picochip_print_operand (file, offset, 'D');
2470 picochip_print_operand (file, address, 's');
2479 inner = XEXP (address, 0);
2481 /* Sanity check - the CONST memory address must be a base+offset. */
2482 gcc_assert (PLUS == GET_CODE (inner));
2484 base = XEXP (inner, 0);
2485 offset = XEXP (inner, 1);
2487 fprintf (file, "&_%s%+d", XSTR (base, 0), XINT (offset, 0));
2493 /* Register operand. Provide a zero offset. */
2494 fprintf (file, "(");
2495 picochip_print_operand (file, address, 'r');
2496 fprintf (file, ")0");
2505 /* Output an operand. Formatting letters allow particular parts of
2506 the operand to be output. */
2508 picochip_print_operand (FILE * file, rtx operand, int letter)
2511 /* Handle special cases. */
2514 /* VLIW continuation, for explicit VLIW sequences. */
2516 fprintf (file, "\\");
2521 fputc (picochip_get_vliw_alu_id (), file);
2524 /* Delay slot specifier. */
2526 /* This should be handled in asm_output_opcode. */
2529 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2531 switch (GET_CODE (operand))
2534 fprintf (file, "AND");
2537 fprintf (file, "OR");
2540 fprintf (file, "XOR");
2543 fprintf (file, "ADD");
2546 fprintf (file, "SUB");
2553 /* Symbolic instructions (e.g., lshift becomes <<). */
2555 switch (GET_CODE (operand))
2558 fprintf (file, "&");
2561 fprintf (file, "|");
2564 fprintf (file, "^");
2567 fprintf (file, "+");
2570 fprintf (file, "-");
2573 fprintf (file, "UNKNOWN_INSN");
2578 default: /* Not a punctuation character - process as normal. */
2582 switch (GET_CODE (operand))
2588 /* Write a range of registers. */
2589 fprintf (file, "R[%d:%d]", REGNO (operand) + 1, REGNO (operand));
2593 /* The upper register of a pair is requested. */
2594 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 1]);
2598 /* The lower register of a pair is requested. Equivalent to the
2599 default, but included for completeness. */
2600 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2604 /* The 3rd register of a DI mode register. */
2605 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 2]);
2609 /* The 4th register of a DI mode register. */
2610 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 3]);
2614 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2619 /* A range of letters can be used to format integers. The
2620 letters Q/H/S are used to divide the constant by the width of
2621 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2622 to obtain the upper and lower 16-bits of a 32-bit
2623 constant. Where possible, signed numbers are used, since
2624 signed representations of numbers may be more compact (e.g.,
2625 65535 can be represented as -1, which fits into a small
2626 constant, whereas 65535 requires a large constant). */
2630 fprintf (file, "%ld", INTVAL (operand));
2634 fprintf (file, "%ld", INTVAL (operand) / 2);
2638 fprintf (file, "%ld", INTVAL (operand) / 4);
2642 fprintf (file, "%d", exact_log2 (INTVAL(operand)));
2646 fprintf (file, "%hi", (short) ((INTVAL (operand) >> 16) & 0xFFFF));
2650 fprintf (file, "%hi", (short) (INTVAL (operand) & 0xFFFF));
2654 fprintf (file, "%ld", INTVAL (operand));
2664 if (GET_MODE (operand) != SFmode)
2665 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2667 REAL_VALUE_FROM_CONST_DOUBLE (rv, operand);
2668 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
2673 fprintf (file, "%hi", (short) ((val >> 16) & 0xFFFF));
2677 fprintf (file, "%hi", (short) (val & 0xFFFF));
2685 /* Output a symbol. The output format must match that of
2686 picochip_output_label. */
2688 /* Ensure that the symbol is marked as referenced. Gcc can
2689 occasionally omit the function bodies when it believes them
2690 to be unreferenced. */
2691 if (SYMBOL_REF_DECL (operand))
2692 mark_decl_referenced (SYMBOL_REF_DECL (operand));
2693 fprintf (file, "&");
2694 assemble_name (file, XSTR (operand, 0));
2698 /* This format must match that of picochip_output_label. */
2699 fprintf (file, "&");
2700 output_asm_label (operand);
2705 rtx addr = XEXP (operand, 0);
2710 if (PLUS != GET_CODE (addr))
2711 fatal_insn ("Bad address, not (reg+disp):", addr);
2713 picochip_print_operand (file, XEXP (addr, 1), 0);
2717 /* Output a memory address in byte mode notation (i.e., the
2718 constant address (if any) is the actual byte address. */
2719 picochip_print_memory_address (file, operand, QImode);
2722 /* Output a constant offset of the given mode (i.e., divide
2723 the constant by the number of units in the mode to get the
2726 picochip_print_memory_address (file, operand, QImode);
2730 picochip_print_memory_address (file, operand, HImode);
2734 picochip_print_memory_address (file, operand, SImode);
2738 picochip_print_memory_address (file, operand, SFmode);
2742 if (PLUS != GET_CODE (addr))
2743 fatal_insn ("Bad address, not (reg+disp):", addr);
2745 picochip_print_operand (file, XEXP (addr, 0), 0);
2748 /* When the mem operand is (reg + big offset) which cannot
2749 be represented in an instruction as operand, the compiler
2750 automatically generates the instruction to put in (reg +
2751 big offset) into another register. In such cases, it
2752 returns '0' as the character. This needs to be handled
2756 if (REG != GET_CODE (addr))
2757 fatal_insn ("Bad address, not register:", addr);
2759 picochip_print_operand (file, addr, 0);
2763 fprintf (file, "Unknown mem operand - letter %c ",
2765 print_rtl (file, operand);
2773 rtx const_exp = XEXP (operand, 0);
2775 /* Handle constant offsets to symbol references. */
2776 if (PLUS == GET_CODE (const_exp) &&
2777 SYMBOL_REF == GET_CODE (XEXP (const_exp, 0)) &&
2778 CONST_INT == GET_CODE (XEXP (const_exp, 1)))
2781 picochip_print_operand (file, XEXP (const_exp, 0), 0);
2782 if (INTVAL (XEXP (const_exp, 1)) >= 0)
2783 fprintf (file, "+");
2784 /* else use the - from the operand (i.e., AP-2)) */
2786 picochip_print_operand (file, XEXP (const_exp, 1), letter);
2795 /* PLUS expressions are of the form (base + offset). Different
2796 options (analagous to those of memory PLUS expressions) are used
2797 to extract the base and offset components. */
2802 picochip_print_operand (file, XEXP (operand, 0), 0);
2806 picochip_print_operand (file, XEXP (operand, 1), 0);
2811 /* If the expression is composed entirely of constants,
2812 evaluate the result. This should only occur with the
2813 picoChip specific comms instructions, which are emitted as
2814 base+offset expressions. */
2815 if (CONST_INT == GET_CODE (XEXP (operand, 0)) &&
2816 CONST_INT == GET_CODE (XEXP (operand, 1)))
2818 HOST_WIDE_INT result = (XINT (XEXP (operand, 0), 0) +
2819 XINT (XEXP (operand, 1), 0));
2820 fprintf (file, "%ld", result);
2824 fprintf (file, "(");
2825 picochip_print_operand (file, XEXP (operand, 0), 0);
2826 fprintf (file, "+");
2827 picochip_print_operand (file, XEXP (operand, 1), 0);
2828 fprintf (file, ")");
2835 /* Comparison operations. */
2846 picochip_print_comparison (file, operand, letter);
2850 fprintf (stderr, "Unknown operand encountered in %s\n", __FUNCTION__);
2851 print_rtl (file, operand);
2858 /* Output an operand address */
2860 picochip_print_operand_address (FILE * file, rtx operand)
2863 switch (GET_CODE (operand))
2867 /* This format must match that of picochip_output_label. */
2868 assemble_name (file, XSTR (operand, 0));
2872 /* Note this format must match that of picochip_output_label. */
2873 fprintf (file, "_L%d", XINT (operand, 5));
2877 /* Pass on to a specialised memory address generator. */
2878 picochip_print_memory_address (file, operand, GET_MODE (operand));
2889 /* Scheduling functions. */
2891 /* Save some of the contents of recog_data. */
2893 picochip_save_recog_data (void)
2895 picochip_saved_which_alternative = which_alternative;
2896 memcpy (&picochip_saved_recog_data, &recog_data,
2897 sizeof (struct recog_data));
2900 /* Restore some of the contents of global variable recog_data. */
2902 picochip_restore_recog_data (void)
2904 which_alternative = picochip_saved_which_alternative;
2905 memcpy (&recog_data, &picochip_saved_recog_data,
2906 sizeof (struct recog_data));
2909 /* Ensure that no var tracking notes are emitted in the middle of a
2910 three-instruction bundle. */
2912 reorder_var_tracking_notes (void)
2918 rtx queue = NULL_RTX;
2920 for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
2922 next = NEXT_INSN (insn);
2926 /* Emit queued up notes before the first instruction of a bundle. */
2927 if (GET_MODE (insn) == TImode)
2931 rtx next_queue = PREV_INSN (queue);
2932 NEXT_INSN (PREV_INSN(insn)) = queue;
2933 PREV_INSN (queue) = PREV_INSN(insn);
2934 PREV_INSN (insn) = queue;
2935 NEXT_INSN (queue) = insn;
2940 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
2942 rtx prev = PREV_INSN (insn);
2943 PREV_INSN (next) = prev;
2944 NEXT_INSN (prev) = next;
2945 PREV_INSN (insn) = queue;
2952 /* Perform machine dependent operations on the rtl chain INSNS. */
2954 picochip_reorg (void)
2956 rtx insn, insn1, vliw_start;
2957 int vliw_insn_location = 0;
2959 /* We are freeing block_for_insn in the toplev to keep compatibility
2960 with old MDEP_REORGS that are not CFG based. Recompute it now. */
2961 compute_bb_for_insn ();
2966 if (picochip_schedule_type != DFA_TYPE_NONE)
2968 timevar_push (TV_SCHED2);
2970 /* Process the instruction list, computing the sizes of each
2971 instruction, and consequently branch distances. This can
2972 result in some branches becoming short enough to be treated
2973 as a real branch instruction, rather than an assembly branch
2974 macro which may expand into multiple instructions. The
2975 benefit of shortening branches is that real branch
2976 instructions can be properly DFA scheduled, whereas macro
2978 shorten_branches (get_insns ());
2980 /* Do control and data sched analysis again,
2981 and write some more of the results to dump file. */
2987 timevar_pop (TV_SCHED2);
2991 if (picochip_schedule_type == DFA_TYPE_SPEED)
2993 /* Whenever a VLIW packet is generated, all instructions in
2994 that packet must appear to come from the same source
2995 location. The following code finds all the VLIW packets,
2996 and tags their instructions with the location of the first
2997 instruction from the packet. Clearly this will result in
2998 strange behaviour when debugging the code, but since
2999 debugging and optimisation are being used in conjunction,
3000 strange behaviour is certain to occur anyway. */
3001 /* Slight bit of change. If the vliw set contains a branch
3002 or call instruction, we pick its location.*/
3003 for (insn = get_insns (); insn; insn = next_insn (insn))
3006 /* If this is the first instruction in the VLIW packet,
3007 extract its location. */
3008 if (GET_MODE (insn) == TImode)
3011 vliw_insn_location = INSN_LOCATOR (insn);
3013 if (JUMP_P (insn) || CALL_P(insn))
3015 vliw_insn_location = INSN_LOCATOR (insn);
3016 for (insn1 = vliw_start; insn1 != insn ; insn1 = next_insn (insn1))
3017 INSN_LOCATOR (insn1) = vliw_insn_location;
3019 /* Tag subsequent instructions with the same location. */
3021 INSN_LOCATOR (insn) = vliw_insn_location;
3027 /* Locate the note marking the end of the function's prologue. If
3028 the note appears in the middle of a VLIW packet, move the note to
3029 the end. This avoids unpleasant consequences such as trying to
3030 emit prologue markers (e.g., .loc/.file directives) in the middle
3032 if (picochip_schedule_type == DFA_TYPE_SPEED)
3034 rtx prologue_end_note = NULL;
3035 rtx last_insn_in_packet = NULL;
3037 for (insn = get_insns (); insn; insn = next_insn (insn))
3039 /* The prologue end must be moved to the end of the VLIW packet. */
3040 if (NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
3042 prologue_end_note = insn;
3047 /* Find the last instruction in this packet. */
3048 for (insn = prologue_end_note; insn; insn = next_real_insn (insn))
3050 if (GET_MODE (insn) == TImode)
3053 last_insn_in_packet = insn;
3056 if (last_insn_in_packet != NULL)
3058 rtx tmp_note = emit_note_after (NOTE_KIND(prologue_end_note), last_insn_in_packet);
3059 memcpy(&NOTE_DATA (tmp_note), &NOTE_DATA(prologue_end_note), sizeof(NOTE_DATA(prologue_end_note)));
3060 delete_insn (prologue_end_note);
3063 if (picochip_flag_var_tracking)
3065 timevar_push (TV_VAR_TRACKING);
3066 variable_tracking_main ();
3067 /* We also have to deal with variable tracking notes in the middle
3069 reorder_var_tracking_notes();
3070 timevar_pop (TV_VAR_TRACKING);
3074 /* Return the ALU character identifier for the current
3075 instruction. This will be 0 or 1. */
3077 picochip_get_vliw_alu_id (void)
3081 /* Always use ALU 0 if VLIW scheduling is disabled. */
3082 if (picochip_schedule_type != DFA_TYPE_SPEED)
3085 /* Get the attribute type of the instruction. Note that this can
3086 ruin the contents of recog_data, so save/restore around the
3088 picochip_save_recog_data ();
3089 attr_type = get_attr_type (picochip_current_prescan_insn);
3090 picochip_restore_recog_data ();
3092 if (picochip_current_vliw_state.contains_pico_alu_insn)
3095 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3096 else it must be the other ALU (either basic or nonCc)
3097 instruction which goes into 1. */
3098 if (attr_type == TYPE_PICOALU)
3104 else if (picochip_current_vliw_state.contains_non_cc_alu_insn)
3106 /* Is this the non CC instruction? If it is, then stuff it into
3107 ALU 1, else it must be a picoAlu or basicAlu, in which case
3108 it goes into ALU 0. */
3109 if (attr_type == TYPE_NONCCALU)
3116 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3117 whether an ALU instruction has already been scheduled in this
3119 switch (picochip_current_vliw_state.num_alu_insns_so_far)
3122 picochip_current_vliw_state.num_alu_insns_so_far++;
3126 picochip_current_vliw_state.num_alu_insns_so_far++;
3130 internal_error ("Too many ALU instructions emitted (%d)\n",
3131 picochip_current_vliw_state.num_alu_insns_so_far);
3138 /* Reset any information about the current VLIW packing status. */
3140 picochip_reset_vliw (rtx insn)
3142 rtx local_insn = insn;
3144 /* Nothing to do if VLIW scheduling isn't being used. */
3145 if (picochip_schedule_type != DFA_TYPE_SPEED)
3149 printf ("%s on insn %d\n", __FUNCTION__, INSN_UID (insn));
3152 picochip_current_vliw_state.contains_pico_alu_insn = 0;
3153 picochip_current_vliw_state.contains_non_cc_alu_insn = 0;
3154 picochip_current_vliw_state.num_alu_insns_so_far = 0;
3155 picochip_current_vliw_state.num_cfi_labels_deferred = 0;
3156 picochip_current_vliw_state.lm_label_name[0] = 0;
3157 picochip_current_vliw_state.num_insns_in_packet = 0;
3159 /* Read through the VLIW packet, classifying the instructions where
3164 if (NOTE_P (local_insn))
3166 local_insn = NEXT_INSN (local_insn);
3169 else if (!INSN_P (local_insn))
3173 /* It is an instruction, but is it ours? */
3174 if (INSN_CODE (local_insn) != -1)
3178 picochip_current_vliw_state.num_insns_in_packet += 1;
3180 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3181 get_attr_type function can overwrite the values in
3182 the recog_data global, hence this is saved and
3183 restored around the call. Not doing so results in
3184 asm_output_opcode being called with a different
3185 instruction to final_prescan_insn, which is fatal. */
3186 picochip_save_recog_data ();
3187 attr_type = get_attr_type (local_insn);
3188 picochip_restore_recog_data ();
3190 if (attr_type == TYPE_PICOALU)
3191 picochip_current_vliw_state.contains_pico_alu_insn = 1;
3192 if (attr_type == TYPE_NONCCALU)
3193 picochip_current_vliw_state.contains_non_cc_alu_insn = 1;
3198 /* Get the next instruction. */
3199 local_insn = NEXT_INSN (local_insn);
3201 /* Keep going while the next instruction is part of the same
3202 VLIW packet (i.e., its a valid instruction and doesn't mark
3203 the start of a new VLIW packet. */
3205 while (local_insn &&
3206 (GET_MODE (local_insn) != TImode) && (INSN_CODE (local_insn) != -1));
3211 picochip_sched_reorder (FILE * file, int verbose,
3212 rtx * ready ATTRIBUTE_UNUSED,
3213 int *n_readyp ATTRIBUTE_UNUSED, int clock)
3217 fprintf (file, ";;\tClock %d\n", clock);
3219 return picochip_sched_issue_rate ();
3224 picochip_sched_lookahead (void)
3226 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3232 picochip_sched_issue_rate (void)
3237 /* Adjust the scheduling cost between the two given instructions,
3238 which have the given dependency. */
3240 picochip_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3245 printf ("Sched Adjust Cost: %d->%d is %d\n",
3246 INSN_UID (insn), INSN_UID (dep_insn), cost);
3248 printf (" Dependency type:");
3249 switch (REG_NOTE_KIND (link))
3257 case REG_DEP_OUTPUT:
3258 printf ("OUTPUT\n");
3261 printf ("Unknown (%d)\n", REG_NOTE_KIND (link));
3265 /* Anti-dependencies are used to enforce the ordering between a
3266 * branch, and any subsequent instructions. For example:
3271 * The ADD instruction must execute after the branch, and this is
3272 * enforced using an anti-dependency. Unfortunately, VLIW machines
3273 * are happy to execute anti-dependent instructions in the same
3274 * cycle, which then results in a schedule like the following being
3277 * BNE someLabel \ ADD.0 r0,r1,r2
3279 * The instruction which would normally be conditionally executed
3280 * depending upon the outcome of the branch, is now unconditionally
3281 * executed every time. To prevent this happening, any
3282 * anti-dependencies between a branch and another instruction are
3283 * promoted to become real dependencies.
3285 if ((JUMP_P (dep_insn) || CALL_P(dep_insn)) && REG_NOTE_KIND (link) == REG_DEP_ANTI)
3289 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3290 INSN_UID (insn), INSN_UID (dep_insn));
3299 /* Return the minimum of the two values */
3301 minimum (int a, int b)
3307 /* I dont expect to get to this function with a==b.*/
3312 /* This function checks if the memory of the two stores are just off by 2 bytes.
3313 It returns the lower memory operand's index.*/
3316 memory_just_off (rtx opnd1, rtx opnd2)
3318 int offset1 = 0, offset2 = 0;
3321 if (GET_CODE(XEXP(opnd1, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1, 0),1)) == CONST_INT)
3323 offset1 = INTVAL(XEXP(XEXP(opnd1, 0), 1));
3324 reg1 = REGNO(XEXP(XEXP(opnd1, 0), 0));
3328 reg1 = REGNO(XEXP(opnd1, 0));
3330 if (GET_CODE(XEXP(opnd2, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2, 0), 1)) == CONST_INT)
3332 offset2 = INTVAL(XEXP(XEXP(opnd2, 0), 1));
3333 reg2 = REGNO(XEXP(XEXP(opnd2, 0), 0));
3337 reg2 = REGNO(XEXP(opnd2, 0));
3340 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3341 should be 4 byte aligned. We can currently guarentee that only if the base
3342 address is FP(R13) and the offset is aligned. */
3344 if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
3345 return (minimum(offset1, offset2) == offset1) ? 1:2;
3351 registers_just_off (rtx opnd1, rtx opnd2)
3354 reg1 = REGNO(opnd1);
3355 reg2 = REGNO(opnd2);
3356 if (abs(reg1-reg2) == 1 && minimum(reg1, reg2) % 2 == 0)
3357 return (minimum(reg1, reg2) == reg1)?1:2;
3361 /* Check to see if the two LDWs can be peepholed together into a LDL
3362 They can be if the registers getting loaded into are contiguous
3363 and the memory addresses are contiguous as well.
3367 can be merged together into
3371 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3372 aligned address. Only FP can be assumed to be 4 byte aligned.
3373 2. The progression of addresses and the register numbers should
3374 be similar. For eg., if you swap r2 and r3 in the above instructions,
3375 the resultant pair cannot be merged.
3379 ok_to_peephole_ldw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3381 int memtest=0,regtest=0;
3382 regtest = registers_just_off(opnd1,opnd3);
3386 memtest = memory_just_off(opnd0,opnd2);
3390 if (regtest == memtest)
3397 /* Similar to LDW peephole */
3399 ok_to_peephole_stw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3401 int memtest=0,regtest=0;
3402 regtest = registers_just_off(opnd1,opnd3);
3406 memtest = memory_just_off(opnd0,opnd2);
3410 if (regtest == memtest)
3418 /* Generate a SImode register with the register number that is the smaller of the two */
3420 gen_min_reg(rtx opnd1,rtx opnd2)
3422 return gen_rtx_REG (SImode, minimum(REGNO(opnd1),REGNO(opnd2)));
3425 /* Generate a SImode memory with the address that is the smaller of the two */
3427 gen_SImode_mem(rtx opnd1,rtx opnd2)
3429 int offset1=0,offset2=0;
3431 if (GET_CODE(XEXP(opnd1,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1,0),1)) == CONST_INT)
3433 offset1 = INTVAL(XEXP(XEXP(opnd1,0),1));
3434 reg = XEXP(XEXP(opnd1,0),0);
3438 reg = XEXP(opnd1,0);
3440 if (GET_CODE(XEXP(opnd2,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2,0),1)) == CONST_INT)
3442 offset2 = INTVAL(XEXP(XEXP(opnd2,0),1));
3444 rtx address = gen_rtx_PLUS (HImode, reg, GEN_INT(minimum(offset1,offset2)));
3445 return gen_rtx_MEM(SImode,address);
3449 picochip_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int* total)
3456 /* Need to penalize immediates that need to be encoded as long constants.*/
3457 if (code == CONST_INT && !(INTVAL (x) >= 0 && INTVAL (x) < 16))
3459 *total = COSTS_N_INSNS(1);
3467 *total = COSTS_N_INSNS (outer_code != MEM);
3472 /* if_then_else come out of cbranch instructions. It will get split into
3473 a condition code generating subtraction and a branch */
3474 *total = COSTS_N_INSNS (2);
3481 if (GET_MODE(x) == SImode)
3482 *total = COSTS_N_INSNS (2);
3483 if (GET_MODE(x) == DImode)
3484 *total = COSTS_N_INSNS (4);
3488 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3489 if (GET_MODE(x) == QImode && !TARGET_HAS_BYTE_ACCESS)
3490 *total = COSTS_N_INSNS (10);
3492 /* 64-bit accesses have to be done through 2 32-bit access */
3493 if (GET_MODE(x) == DImode)
3494 *total = COSTS_N_INSNS (2);
3500 /* SImode shifts are expensive */
3501 if (GET_MODE(x) == SImode)
3502 *total = COSTS_N_INSNS (10);
3504 /* Register shift by constant is cheap. */
3505 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3506 && GET_CODE(XEXP(x, 0)) == REG
3507 && GET_CODE(XEXP(x, 1)) == CONST_INT)
3508 *total = COSTS_N_INSNS (1);
3510 *total = COSTS_N_INSNS (4);
3517 /* Divisions are more expensive than the default 7*/
3518 if (GET_MODE(x) == SImode)
3519 *total = COSTS_N_INSNS (20);
3521 *total = COSTS_N_INSNS (12);
3526 /* Look for the simple cases of multiplying register*register or
3527 register*constant. */
3528 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3529 && ((GET_CODE(XEXP(x, 0)) == REG
3530 && (GET_CODE(XEXP(x, 1)) == REG || GET_CODE(XEXP(x,1)) == CONST_INT))
3531 || (GET_CODE(XEXP(x, 0)) == ZERO_EXTEND
3532 && GET_CODE(XEXP(XEXP(x, 0),0)) == REG
3533 && GET_CODE(XEXP(x, 1)) == ZERO_EXTEND
3534 && GET_CODE(XEXP(XEXP(x, 1),0)) == REG)))
3537 /* When optimising for size, multiplication by constant
3538 should be discouraged slightly over multiplication by a
3540 if (picochip_has_mac_unit)
3542 /* Single cycle multiplication, but the result must be
3543 loaded back into a general register afterwards. */
3544 *total = COSTS_N_INSNS(2);
3547 else if (picochip_has_mul_unit)
3549 /* Single cycle multiplication. */
3550 *total = COSTS_N_INSNS(1);
3553 /* Else no multiply available. Use default cost. */
3563 if (localTotal != 0)
3565 *total = localTotal;
3576 picochip_final_prescan_insn (rtx insn, rtx * opvec ATTRIBUTE_UNUSED,
3577 int num_operands ATTRIBUTE_UNUSED)
3581 picochip_current_prescan_insn = insn;
3584 printf ("Final prescan on INSN %d with mode %s\n",
3585 INSN_UID (insn), GET_MODE_NAME (GET_MODE (insn)));
3587 /* If this is the start of a new instruction cycle, or no scheduling
3588 is used, then reset the VLIW status. */
3589 if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
3590 picochip_reset_vliw (insn);
3592 /* No VLIW scheduling occured, so don't go any further. */
3593 if (picochip_schedule_type != DFA_TYPE_SPEED)
3596 /* Look for the next printable instruction. This loop terminates on
3597 any recognisable instruction, and on any unrecognisable
3598 instruction with TImode. */
3600 for (local_insn = NEXT_INSN (local_insn); local_insn;
3601 local_insn = NEXT_INSN (local_insn))
3603 if (NOTE_P (local_insn))
3605 else if (!INSN_P (local_insn))
3607 else if (GET_MODE (local_insn) == TImode
3608 || INSN_CODE (local_insn) != -1)
3612 /* Set the continuation flag if the next instruction can be packed
3613 with the current instruction (i.e., the next instruction is
3614 valid, and isn't the start of a new cycle). */
3615 picochip_vliw_continuation = (local_insn && INSN_P (local_insn) &&
3616 (GET_MODE (local_insn) != TImode));
3620 /* Builtin functions. */
3621 /* Given a builtin function taking 2 operands (i.e., target + source),
3622 emit the RTL for the underlying instruction. */
3624 picochip_expand_builtin_2op (enum insn_code icode, tree arglist, rtx target)
3628 enum machine_mode tmode, mode0;
3630 /* Grab the incoming argument and emit its RTL. */
3631 arg0 = TREE_VALUE (arglist);
3632 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3634 /* Determine the modes of the instruction operands. */
3635 tmode = insn_data[icode].operand[0].mode;
3636 mode0 = insn_data[icode].operand[1].mode;
3638 /* Ensure that the incoming argument RTL is in a register of the
3640 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3641 op0 = copy_to_mode_reg (mode0, op0);
3643 /* If there isn't a suitable target, emit a target register. */
3645 || GET_MODE (target) != tmode
3646 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3647 target = gen_reg_rtx (tmode);
3649 /* Emit and return the new instruction. */
3650 pat = GEN_FCN (icode) (target, op0);
3659 /* Given a builtin function taking 3 operands (i.e., target + two
3660 source), emit the RTL for the underlying instruction. */
3662 picochip_expand_builtin_3op (enum insn_code icode, tree arglist, rtx target)
3666 enum machine_mode tmode, mode0, mode1;
3668 /* Grab the function's arguments. */
3669 arg0 = TREE_VALUE (arglist);
3670 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3672 /* Emit rtl sequences for the function arguments. */
3673 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3674 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3676 /* Get the mode's of each of the instruction operands. */
3677 tmode = insn_data[icode].operand[0].mode;
3678 mode0 = insn_data[icode].operand[1].mode;
3679 mode1 = insn_data[icode].operand[2].mode;
3681 /* Ensure that each of the function argument rtl sequences are in a
3682 register of the correct mode. */
3683 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3684 op0 = copy_to_mode_reg (mode0, op0);
3685 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
3686 op1 = copy_to_mode_reg (mode1, op1);
3688 /* If no target has been given, create a register to use as the target. */
3690 || GET_MODE (target) != tmode
3691 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3692 target = gen_reg_rtx (tmode);
3694 /* Emit and return the new instruction. */
3695 pat = GEN_FCN (icode) (target, op0, op1);
3704 /* Expand a builtin function which takes two arguments, and returns a void. */
3706 picochip_expand_builtin_2opvoid (enum insn_code icode, tree arglist)
3710 enum machine_mode mode0, mode1;
3712 /* Grab the function's arguments. */
3713 arg0 = TREE_VALUE (arglist);
3714 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3716 /* Emit rtl sequences for the function arguments. */
3717 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3718 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3720 /* Get the mode's of each of the instruction operands. */
3721 mode0 = insn_data[icode].operand[0].mode;
3722 mode1 = insn_data[icode].operand[1].mode;
3724 /* Ensure that each of the function argument rtl sequences are in a
3725 register of the correct mode. */
3726 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
3727 op0 = copy_to_mode_reg (mode0, op0);
3728 if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
3729 op1 = copy_to_mode_reg (mode1, op1);
3731 /* Emit and return the new instruction. */
3732 pat = GEN_FCN (icode) (op0, op1);
3741 /* Expand an array get into the corresponding RTL. */
3743 picochip_expand_array_get (tree arglist, rtx target)
3745 tree arg0, arg1, arg2;
3746 rtx op0, op1, op2, pat;
3748 /* Grab the function's arguments. */
3749 arg0 = TREE_VALUE (arglist);
3750 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3751 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3753 /* Emit rtl sequences for the function arguments. */
3754 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3755 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3756 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3758 /* The second and third operands must be constant. Nothing else will
3760 if (CONST_INT != GET_CODE (op1))
3761 internal_error ("%s: Second source operand is not a constant",
3763 if (CONST_INT != GET_CODE (op2))
3764 internal_error ("%s: Third source operand is not a constant",
3767 /* If no target has been given, create a register to use as the target. */
3768 if (target == 0 || GET_MODE (target) != SImode)
3769 target = gen_reg_rtx (SImode);
3771 /* The first operand must be a HImode register or a constant. If it
3772 isn't, force it into a HImode register. */
3773 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3774 op0 = copy_to_mode_reg (HImode, op0);
3777 /* Emit and return the new instruction. */
3778 pat = gen_commsArrayGet (target, op0, op1, op2);
3785 /* Expand an array put into the corresponding RTL. */
3787 picochip_expand_array_put (tree arglist, rtx target)
3789 tree arg0, arg1, arg2, arg3;
3790 rtx op0, op1, op2, op3, pat;
3792 /* Grab the function's arguments. */
3793 arg0 = TREE_VALUE (arglist);
3794 arg1 = TREE_VALUE (arglist->common.chain);
3795 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3796 arg3 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (TREE_CHAIN (arglist))));
3798 /* Emit rtl sequences for the function arguments. */
3799 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3800 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3801 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3802 op3 = expand_expr (arg3, NULL_RTX, VOIDmode, 0);
3804 /* The first operand must be an SImode register. */
3805 if (GET_MODE (op0) != SImode || REG != GET_CODE (op0))
3806 op0 = copy_to_mode_reg (SImode, op0);
3808 /* The second (index) operand must be a HImode register, or a
3809 constant. If it isn't, force it into a HImode register. */
3810 if (GET_MODE (op1) != HImode || REG != GET_CODE (op1))
3811 op1 = copy_to_mode_reg (HImode, op1);
3813 /* The remaining operands must be constant. Nothing else will do. */
3814 if (CONST_INT != GET_CODE (op2))
3815 internal_error ("%s: Third source operand is not a constant",
3817 if (CONST_INT != GET_CODE (op3))
3818 internal_error ("%s: Fourth source operand is not a constant",
3821 /* Emit and return the new instruction. */
3822 pat = gen_commsArrayPut (op0, op1, op2, op3);
3829 /* Expand an array testport into the corresponding RTL. */
3831 picochip_expand_array_testport (tree arglist, rtx target)
3833 tree arg0, arg1, arg2;
3834 rtx op0, op1, op2, pat;
3836 /* Grab the function's arguments. */
3837 arg0 = TREE_VALUE (arglist);
3838 arg1 = TREE_VALUE (TREE_CHAIN (arglist));
3839 arg2 = TREE_VALUE (TREE_CHAIN (TREE_CHAIN (arglist)));
3841 /* Emit rtl sequences for the function arguments. */
3842 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3843 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, 0);
3844 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, 0);
3846 /* The first operand must be a HImode register, or a constant. If it
3847 isn't, force it into a HImode register. */
3848 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
3849 op0 = copy_to_mode_reg (HImode, op0);
3851 /* The second and third operands must be constant. Nothing else will
3853 if (CONST_INT != GET_CODE (op1))
3854 internal_error ("%s: Second source operand is not a constant",
3856 if (CONST_INT != GET_CODE (op2))
3857 internal_error ("%s: Third source operand is not a constant",
3860 /* If no target has been given, create a HImode register to use as
3862 if (target == 0 || GET_MODE (target) != HImode)
3863 target = gen_reg_rtx (HImode);
3865 /* Emit and return the new instruction. */
3866 pat = gen_commsArrayTestPort (target, op0, op1, op2);
3873 /* Generate a unique HALT instruction by giving the instruction a
3874 unique integer. This integer makes no difference to the assembly
3875 output (other than a comment indicating the supplied id), but the
3876 presence of the unique integer prevents the compiler from combining
3877 several different halt instructions into one instruction. This
3878 means that each use of the halt instruction is unique, which in
3879 turn means that assertions work as expected. */
3881 picochip_generate_halt (void)
3883 static int currentId = 0;
3884 rtx id = GEN_INT (currentId);
3888 emit_insn (gen_halt (id));
3890 /* A barrier is inserted to prevent the compiler from thinking that
3891 it has to continue execution after the HALT.*/
3894 rtx insns = get_insns();
3902 picochip_generate_profile (tree arglist)
3904 tree arg0 = TREE_VALUE (arglist);
3905 rtx op0 = expand_expr (arg0, NULL_RTX, VOIDmode, 0);
3908 emit_insn (gen_profile (op0));
3910 rtx insns = get_insns();
3918 /* Initialise the builtin functions. Start by initialising
3919 descriptions of different types of functions (e.g., void fn(int),
3920 int fn(void)), and then use these to define the builtins. */
3922 picochip_init_builtins (void)
3924 tree endlink = void_list_node;
3925 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
3926 tree unsigned_endlink = tree_cons (NULL_TREE, unsigned_type_node, endlink);
3927 tree long_endlink = tree_cons (NULL_TREE, long_integer_type_node, endlink);
3928 tree int_int_endlink =
3929 tree_cons (NULL_TREE, integer_type_node, int_endlink);
3930 tree int_int_int_endlink =
3931 tree_cons (NULL_TREE, integer_type_node, int_int_endlink);
3932 tree int_long_endlink =
3933 tree_cons (NULL_TREE, integer_type_node, long_endlink);
3934 tree pchar_type_node = build_pointer_type (char_type_node);
3935 tree long_int_int_int_endlink =
3936 tree_cons (NULL_TREE, long_integer_type_node, int_int_int_endlink);
3938 tree int_ftype_void, int_ftype_int, int_ftype_int_int, void_ftype_pchar;
3939 tree long_ftype_int, long_ftype_int_int, long_ftype_int_int_int;
3940 tree void_ftype_int_long, int_ftype_int_int_int,
3941 void_ftype_long_int_int_int;
3942 tree void_ftype_void, void_ftype_int, unsigned_ftype_unsigned;
3944 /* void func (void) */
3945 void_ftype_void = build_function_type (void_type_node, endlink);
3947 /* void func (void *) */
3949 = build_function_type (void_type_node,
3950 tree_cons (NULL_TREE, pchar_type_node, endlink));
3952 /* int func (void) */
3953 int_ftype_void = build_function_type (integer_type_node, endlink);
3955 /* void func (int) */
3956 void_ftype_int = build_function_type (void_type_node, int_endlink);
3958 /* int func (int) */
3959 int_ftype_int = build_function_type (integer_type_node, int_endlink);
3961 /* unsigned int func (unsigned int) */
3962 unsigned_ftype_unsigned = build_function_type (unsigned_type_node, unsigned_endlink);
3964 /* int func(int, int) */
3966 = build_function_type (integer_type_node, int_int_endlink);
3968 /* long func(int) */
3969 long_ftype_int = build_function_type (long_integer_type_node, int_endlink);
3971 /* long func(int, int) */
3973 = build_function_type (long_integer_type_node, int_int_endlink);
3975 /* long func(int, int, int) */
3976 long_ftype_int_int_int
3977 = build_function_type (long_integer_type_node, int_int_int_endlink);
3979 /* int func(int, int, int) */
3980 int_ftype_int_int_int
3981 = build_function_type (integer_type_node, int_int_int_endlink);
3983 /* void func(int, long) */
3985 = build_function_type (void_type_node, int_long_endlink);
3987 /* void func(long, int, int, int) */
3988 void_ftype_long_int_int_int
3989 = build_function_type (void_type_node, long_int_int_int_endlink);
3991 /* Initialise the sign-bit-count function. */
3992 add_builtin_function ("__builtin_sbc", int_ftype_int,
3993 PICOCHIP_BUILTIN_SBC, BUILT_IN_MD, NULL,
3995 add_builtin_function ("picoSbc", int_ftype_int, PICOCHIP_BUILTIN_SBC,
3996 BUILT_IN_MD, NULL, NULL_TREE);
3998 /* Initialise the bit reverse function. */
3999 add_builtin_function ("__builtin_profile", void_ftype_int,
4000 PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL,
4002 add_builtin_function ("picoProfile", void_ftype_int,
4003 PICOCHIP_BUILTIN_PROFILE, BUILT_IN_MD, NULL,
4006 /* Initialise the bit reverse function. */
4007 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned,
4008 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4010 add_builtin_function ("picoBrev", unsigned_ftype_unsigned,
4011 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4014 /* Initialise the byte swap function. */
4015 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned,
4016 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4018 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned,
4019 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4022 /* Initialise the ASRI function (note that while this can be coded
4023 using a signed shift in C, extra scratch registers are required,
4024 which we avoid by having a direct builtin to map to the
4026 add_builtin_function ("__builtin_asri", int_ftype_int_int,
4027 PICOCHIP_BUILTIN_ASRI, BUILT_IN_MD, NULL,
4030 /* Initialise saturating addition. */
4031 add_builtin_function ("__builtin_adds", int_ftype_int_int,
4032 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4034 add_builtin_function ("picoAdds", int_ftype_int_int,
4035 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4038 /* Initialise saturating subtraction. */
4039 add_builtin_function ("__builtin_subs", int_ftype_int_int,
4040 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4042 add_builtin_function ("picoSubs", int_ftype_int_int,
4043 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4046 /* Scalar comms builtins. */
4047 add_builtin_function ("__builtin_get", long_ftype_int,
4048 PICOCHIP_BUILTIN_GET, BUILT_IN_MD, NULL,
4050 add_builtin_function ("__builtin_put", void_ftype_int_long,
4051 PICOCHIP_BUILTIN_PUT, BUILT_IN_MD, NULL,
4053 add_builtin_function ("__builtin_testport", int_ftype_int,
4054 PICOCHIP_BUILTIN_TESTPORT, BUILT_IN_MD, NULL,
4057 /* Array comms builtins. */
4058 add_builtin_function ("__builtin_put_array",
4059 void_ftype_long_int_int_int,
4060 PICOCHIP_BUILTIN_PUT_ARRAY, BUILT_IN_MD, NULL,
4062 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int,
4063 PICOCHIP_BUILTIN_GET_ARRAY, BUILT_IN_MD, NULL,
4065 add_builtin_function ("__builtin_testport_array",
4066 int_ftype_int_int_int,
4067 PICOCHIP_BUILTIN_TESTPORT_ARRAY, BUILT_IN_MD,
4070 /* Halt instruction. Note that the builtin function is marked as
4071 having the attribute `noreturn' so that the compiler realises
4072 that the halt stops the program dead. */
4073 tree noreturn = tree_cons (get_identifier ("noreturn"), NULL, NULL);
4074 add_builtin_function ("__builtin_halt", void_ftype_void,
4075 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4077 add_builtin_function ("picoHalt", void_ftype_void,
4078 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4083 /* Expand a call to a builtin function. */
4085 picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
4086 enum machine_mode mode ATTRIBUTE_UNUSED,
4087 int ignore ATTRIBUTE_UNUSED)
4089 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4090 tree arglist = CALL_EXPR_ARGS(exp);
4091 int fcode = DECL_FUNCTION_CODE (fndecl);
4095 case PICOCHIP_BUILTIN_ASRI:
4096 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri, arglist,
4099 case PICOCHIP_BUILTIN_ADDS:
4100 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3, arglist,
4103 case PICOCHIP_BUILTIN_SUBS:
4104 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3, arglist,
4107 case PICOCHIP_BUILTIN_SBC:
4108 return picochip_expand_builtin_2op (CODE_FOR_sbc, arglist, target);
4110 case PICOCHIP_BUILTIN_BREV:
4111 return picochip_expand_builtin_2op (CODE_FOR_brev, arglist, target);
4113 case PICOCHIP_BUILTIN_BYTESWAP:
4114 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2, arglist, target);
4116 case PICOCHIP_BUILTIN_GET:
4117 return picochip_expand_builtin_2op (CODE_FOR_commsGet, arglist, target);
4119 case PICOCHIP_BUILTIN_PUT:
4120 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut, arglist);
4122 case PICOCHIP_BUILTIN_TESTPORT:
4123 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort, arglist,
4126 case PICOCHIP_BUILTIN_PUT_ARRAY:
4127 return picochip_expand_array_put (arglist, target);
4129 case PICOCHIP_BUILTIN_GET_ARRAY:
4130 return picochip_expand_array_get (arglist, target);
4132 case PICOCHIP_BUILTIN_TESTPORT_ARRAY:
4133 return picochip_expand_array_testport (arglist, target);
4135 case PICOCHIP_BUILTIN_HALT:
4136 return picochip_generate_halt ();
4138 case PICOCHIP_BUILTIN_PROFILE:
4139 return picochip_generate_profile (arglist);
4146 /* Should really do something sensible here. */
4150 /* Emit warnings. */
4152 picochip_warn_inefficient (const char *msg)
4154 if (TARGET_INEFFICIENT_WARNINGS)
4155 warning (OPT_minefficient_warnings,
4156 "%s (disable warning using -mno-inefficient-warnings)", msg);
4160 warn_of_byte_access (void)
4162 static int warned = 0;
4166 picochip_warn_inefficient
4167 ("byte access is synthesised - consider using MUL AE");
4174 picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
4175 bool outgoing ATTRIBUTE_UNUSED)
4177 enum machine_mode mode = TYPE_MODE (valtype);
4178 int unsignedp = TYPE_UNSIGNED (valtype);
4180 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4181 just as PROMOTE_MODE does. */
4182 mode = promote_mode (valtype, mode, &unsignedp, 1);
4184 return gen_rtx_REG (mode, 0);
4188 /* Check that the value of the given mode will fit in the register of
4191 picochip_hard_regno_mode_ok (int regno, enum machine_mode mode)
4194 if (GET_MODE_CLASS (mode) == MODE_CC)
4195 return regno == CC_REGNUM;
4197 /* If the CC register is being used, then only CC mode values are
4198 allowed (which have already been tested). */
4199 if (regno == CC_REGNUM || regno == ACC_REGNUM)
4202 /* Must be a valid register. */
4206 /* Modes QI and HI may be placed in any register except the CC. */
4207 if (mode == QImode || mode == HImode)
4210 /* DI must be in a quad register. */
4212 return (regno % 4 == 0);
4214 /* All other modes must be placed in a even numbered register. */
4215 return !(regno & 1);
4219 /* Extract the lower and upper components of a constant value. */
4222 picochip_get_low_const (rtx value)
4224 return gen_int_mode (INTVAL (value) & 0xFFFF, HImode);
4228 picochip_get_high_const (rtx value)
4230 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4231 return gen_int_mode ((INTVAL (value) >> 16) & 0xFFFF, HImode);
4235 /* Loading and storing QImode values to and from memory in a machine
4236 without byte access requires might require a scratch
4237 register. However, the scratch register might correspond to the
4238 register in which the value is being loaded. To ensure that a
4239 scratch register is supplied which is definitely different to the
4240 output register, request a register pair. This effectively gives a
4241 choice of two registers to choose from, so that we a guaranteed to
4242 get at least one register which is different to the output
4243 register. This trick is taken from the alpha implementation. */
4245 picochip_secondary_reload (bool in_p,
4246 rtx x ATTRIBUTE_UNUSED,
4247 enum reg_class cla ATTRIBUTE_UNUSED,
4248 enum machine_mode mode,
4249 secondary_reload_info *sri)
4251 if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
4254 sri->icode = CODE_FOR_reload_outqi;
4256 sri->icode = CODE_FOR_reload_inqi;
4259 /* We dont need to return a register class type when we need only a
4260 scratch register. It realizes the scratch register type by looking
4261 at the instruction definition for sri->icode. We only need to
4262 return the register type when we need intermediaries for copies.*/
4266 /* Return true if the given memory operand can be aligned to a
4267 word+offset memory reference (e.g., FP+3 can be converted into the
4268 memory operand FP+2, with the offset 1). */
4270 picochip_alignable_memory_operand (rtx mem_operand,
4271 enum machine_mode mode ATTRIBUTE_UNUSED)
4275 /* Not a mem operand. Refuse immediately. */
4276 if (MEM != GET_CODE (mem_operand))
4279 address = XEXP (mem_operand, 0);
4281 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4282 return ((PLUS == GET_CODE (address) &&
4283 REGNO (XEXP (address, 0)) == STACK_POINTER_REGNUM &&
4284 CONST_INT == GET_CODE (XEXP (address, 1)) &&
4285 picochip_const_ok_for_letter_p (INTVAL (XEXP (address, 1)), 'K'))
4286 || (REG == GET_CODE (address)
4287 && REGNO (address) == STACK_POINTER_REGNUM));
4291 /* Return true if the given memory reference is to a word aligned
4292 address. Currently this means it must be either SP, or
4293 SP+offset. We could replace this function with alignable
4294 memory references in the above function?. */
4296 picochip_word_aligned_memory_reference (rtx operand)
4300 /* The address must be the SP register, or a constant, aligned
4301 offset from SP which doesn't exceed the FP+offset
4303 return ((PLUS == GET_CODE (operand)
4304 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
4305 && picochip_is_aligned (INTVAL (XEXP (operand, 1)), 16)
4306 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand, 1)),
4308 || (REG == GET_CODE (operand)
4309 && REGNO (operand) == STACK_POINTER_REGNUM));
4313 /* Given an alignable memory location, convert the memory location
4314 into a HI mode access, storing the new memory reference in
4315 paligned_mem, and the number of bits by which to shift in pbitnum
4316 (i.e., given a reference to FP+3, this creates an aligned reference
4317 of FP+2, with an 8-bit shift). This code is a modification of that
4318 found in the Alpha port. */
4320 picochip_get_hi_aligned_mem (rtx ref, rtx * paligned_mem, rtx * pbitnum)
4323 HOST_WIDE_INT offset = 0;
4325 gcc_assert (GET_CODE (ref) == MEM);
4327 if (reload_in_progress && !memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
4329 base = find_replacement (&XEXP (ref, 0));
4331 gcc_assert(memory_address_p (GET_MODE (ref), base));
4335 base = XEXP (ref, 0);
4338 if (GET_CODE (base) == PLUS)
4340 offset += INTVAL (XEXP (base, 1));
4341 base = XEXP (base, 0);
4344 *paligned_mem = widen_memory_access (ref, HImode, (offset & ~1) - offset);
4351 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4355 *pbitnum = GEN_INT ((offset & 1) * 8);
4359 /* Return true if the given operand is an absolute address in memory
4360 (i.e., a symbolic offset). */
4362 picochip_absolute_memory_operand (rtx op,
4363 enum machine_mode mode ATTRIBUTE_UNUSED)
4366 if (MEM == GET_CODE (op))
4368 rtx address = XEXP (op, 0);
4370 /* Symbols are valid absolute addresses. */
4371 if (SYMBOL_REF == GET_CODE (address))
4374 /* Constant offsets to symbols are valid absolute addresses. */
4375 if (CONST == GET_CODE (address) &&
4376 PLUS == GET_CODE (XEXP (address, 0)) &&
4377 SYMBOL_REF == GET_CODE (XEXP (XEXP (address, 0), 0)) &&
4378 CONST_INT == GET_CODE (XEXP (XEXP (address, 0), 1)))
4385 /* Symbols are valid absolute addresses. */
4386 if (SYMBOL_REF == GET_CODE (XEXP (op, 0)))
4395 picochip_asm_named_section (const char *name,
4396 unsigned int flags ATTRIBUTE_UNUSED,
4397 tree decl ATTRIBUTE_UNUSED)
4399 fprintf (asm_out_file, ".section %s\n", name);
4403 /* Check if we can make a conditional copy instruction. This is emitted as an
4404 instruction to set the condition register, followed by an instruction which
4405 uses the condition registers to perform the conditional move. */
4407 picochip_check_conditional_copy (rtx * operands)
4410 rtx branch_op_0 = XEXP (operands[1], 0);
4411 rtx branch_op_1 = XEXP (operands[1], 1);
4413 /* Only HI mode conditional moves are currently allowed. Can we add
4415 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
4418 /* Is the comparison valid? Only allow operands which are registers
4419 if they are HImode. SI mode comparisons against 0 could be
4420 handled using logical operations (e.g., SIreg != 0 when low ||
4421 high). Need to find test cases to provoke this though (fixunssfdi
4422 in libgcc does, but is complicated). */
4423 if (GET_MODE (branch_op_0) != HImode ||
4424 !(register_operand (branch_op_0, GET_MODE (branch_op_0))))
4426 if (GET_MODE (branch_op_1) != HImode ||
4427 !(picochip_comparison_operand (branch_op_1, GET_MODE (branch_op_1))))