1 /* Subroutines used for code generation on picoChip processors.
2 Copyright (C) 2001, 2008, 2009, 2010 Free Software Foundation, Inc.
3 Contributed by Picochip Ltd. (http://www.picochip.com)
4 Maintained by Daniel Towner (daniel.towner@picochip.com) and
5 Hariharan Sandanagobalane (hariharan@picochip.com)
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not, see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
42 #include "basic-block.h"
43 #include "integrate.h"
44 #include "diagnostic-core.h"
49 #include "target-def.h"
50 #include "langhooks.h"
54 #include "picochip-protos.h"
56 #include "insn-attr.h" /* For DFA state_t. */
57 #include "insn-config.h" /* Required by recog.h */
58 #include "insn-codes.h" /* For CODE_FOR_? */
59 #include "optabs.h" /* For GEN_FCN */
60 #include "basic-block.h" /* UPDATE_LIFE_GLOBAL* for picochip_reorg. */
61 #include "timevar.h" /* For TV_SCHED2, in picochip_reorg. */
62 #include "libfuncs.h" /* For memcpy_libfuncs, etc. */
63 #include "df.h" /* For df_regs_ever_live_df_regs_ever_live_pp, etc. */
66 /* Target AE ISA information. */
67 enum picochip_dfa_type picochip_schedule_type;
69 bool picochip_has_mul_unit = false;
70 bool picochip_has_mac_unit = false;
72 /* targetm hook function prototypes. */
74 void picochip_asm_file_start (void);
75 void picochip_asm_file_end (void);
77 void picochip_init_libfuncs (void);
78 void picochip_reorg (void);
80 int picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum,
81 enum machine_mode mode,
82 tree type, bool named);
83 rtx picochip_function_arg (CUMULATIVE_ARGS * p_cum,
84 enum machine_mode mode,
85 const_tree type, bool named);
86 rtx picochip_incoming_function_arg (CUMULATIVE_ARGS * p_cum,
87 enum machine_mode mode,
88 const_tree type, bool named);
89 void picochip_arg_advance (CUMULATIVE_ARGS * p_cum, enum machine_mode mode,
90 const_tree type, bool named);
91 unsigned int picochip_function_arg_boundary (enum machine_mode mode,
94 int picochip_sched_lookahead (void);
95 int picochip_sched_issue_rate (void);
96 int picochip_sched_adjust_cost (rtx insn, rtx link,
97 rtx dep_insn, int cost);
98 int picochip_sched_reorder (FILE * file, int verbose, rtx * ready,
99 int *n_readyp, int clock);
101 void picochip_init_builtins (void);
102 rtx picochip_expand_builtin (tree, rtx, rtx, enum machine_mode, int);
104 bool picochip_rtx_costs (rtx x, int code, int outer_code, int* total, bool speed);
105 bool picochip_return_in_memory(const_tree type,
106 const_tree fntype ATTRIBUTE_UNUSED);
107 bool picochip_legitimate_address_p (enum machine_mode, rtx, bool);
108 rtx picochip_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
109 enum machine_mode mode);
110 int picochip_legitimize_reload_address (rtx *x, enum machine_mode mode,
111 int opnum, int type, int ind_levels);
113 rtx picochip_struct_value_rtx(tree fntype ATTRIBUTE_UNUSED, int incoming ATTRIBUTE_UNUSED);
114 rtx picochip_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED,
115 bool outgoing ATTRIBUTE_UNUSED);
117 picochip_secondary_reload (bool in_p,
118 rtx x ATTRIBUTE_UNUSED,
119 reg_class_t cla ATTRIBUTE_UNUSED,
120 enum machine_mode mode,
121 secondary_reload_info *sri);
123 picochip_asm_named_section (const char *name,
124 unsigned int flags ATTRIBUTE_UNUSED,
125 tree decl ATTRIBUTE_UNUSED);
127 static rtx picochip_static_chain (const_tree, bool);
129 static void picochip_option_override (void);
131 /* Lookup table mapping a register number to the earliest containing
132 class. Used by REGNO_REG_CLASS. */
133 const enum reg_class picochip_regno_reg_class[FIRST_PSEUDO_REGISTER] =
135 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
136 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
137 TWIN_REGS, TWIN_REGS, TWIN_REGS, TWIN_REGS,
138 GR_REGS, FRAME_REGS, PTR_REGS, CONST_REGS,
139 ACC_REGS, CC_REGS, GR_REGS, GR_REGS
142 /* picoChip register names. */
143 const char *picochip_regnames[] = REGISTER_NAMES;
145 /* Define the maximum number of registers which may be used to pass
146 * parameters to functions. */
147 #define MAX_CALL_PARAMETER_REGS 6
150 /* Target scheduling information. */
152 /* Determine whether we run our final scheduling pass or not. We always
153 avoid the normal second scheduling pass. */
154 int picochip_flag_schedule_insns2;
156 /* Check if variable tracking needs to be run. */
157 int picochip_flag_var_tracking;
159 /* This flag indicates whether the next instruction to be output is a
160 VLIW continuation instruction. It is used to communicate between
161 final_prescan_insn and asm_output_opcode. */
162 static int picochip_vliw_continuation = 0;
164 /* This variable is used to communicate the current instruction
165 between final_prescan_insn and functions such as asm_output_opcode,
166 and picochip_get_vliw_alu_id (which are otherwise unable to determine the
167 current instruction. */
168 static rtx picochip_current_prescan_insn;
170 static bool picochip_is_delay_slot_pending = 0;
172 /* When final_prescan_insn is called, it computes information about
173 the current VLIW packet, and stores it in this structure. When
174 instructions are output, this state is used to make sure that the
175 instructions are output in the correct way (e.g., which ALU to use,
176 whether a macro branch was ever previously a real branch, etc.). */
179 int contains_pico_alu_insn;
180 int contains_non_cc_alu_insn;
181 int num_alu_insns_so_far;
183 /* Record how many instructions are contained in the packet. */
184 int num_insns_in_packet;
186 /* There was a case for this to be more than 1 */
187 int num_cfi_labels_deferred;
188 char cfi_label_name[2][256]; /* Used to record the name of a CFI label
189 emitted inside a VLIW packet. */
190 char lm_label_name[256]; /* Used to record the name of an LM label. */
193 struct vliw_state picochip_current_vliw_state;
195 /* Save/restore recog_data. */
196 static int picochip_saved_which_alternative;
197 static struct recog_data picochip_saved_recog_data;
199 /* Determine which ALU to use for the instruction in
200 picochip_current_prescan_insn. */
201 static char picochip_get_vliw_alu_id (void);
203 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
204 static const struct default_options picochip_option_optimization_table[] =
206 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
207 { OPT_LEVELS_NONE, 0, NULL, 0 }
210 /* Initialize the GCC target structure. */
212 #undef TARGET_ASM_FUNCTION_PROLOGUE
213 #define TARGET_ASM_FUNCTION_PROLOGUE picochip_function_prologue
215 #undef TARGET_ASM_FUNCTION_EPILOGUE
216 #define TARGET_ASM_FUNCTION_EPILOGUE picochip_function_epilogue
218 #undef TARGET_ASM_INTERNAL_LABEL
219 #define TARGET_ASM_INTERNAL_LABEL picochip_output_internal_label
221 #undef TARGET_ASM_GLOBALIZE_LABEL
222 #define TARGET_ASM_GLOBALIZE_LABEL picochip_output_global
224 #undef TARGET_ASM_BYTE_OP
225 #define TARGET_ASM_BYTE_OP ".initByte "
226 #undef TARGET_ASM_ALIGNED_HI_OP
227 #define TARGET_ASM_ALIGNED_HI_OP ".initWord "
228 #undef TARGET_ASM_UNALIGNED_HI_OP
229 #define TARGET_ASM_UNALIGNED_HI_OP ".unalignedInitWord "
230 #undef TARGET_ASM_ALIGNED_SI_OP
231 #define TARGET_ASM_ALIGNED_SI_OP ".initLong "
232 #undef TARGET_ASM_UNALIGNED_SI_OP
233 #define TARGET_ASM_UNALIGNED_SI_OP ".unalignedInitLong "
235 #undef TARGET_INIT_BUILTINS
236 #define TARGET_INIT_BUILTINS picochip_init_builtins
238 #undef TARGET_EXPAND_BUILTIN
239 #define TARGET_EXPAND_BUILTIN picochip_expand_builtin
241 #undef TARGET_RTX_COSTS
242 #define TARGET_RTX_COSTS picochip_rtx_costs
244 #undef TARGET_SCHED_ISSUE_RATE
245 #define TARGET_SCHED_ISSUE_RATE picochip_sched_issue_rate
247 #undef TARGET_SCHED_REORDER
248 #define TARGET_SCHED_REORDER picochip_sched_reorder
250 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
251 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
252 picochip_sched_lookahead
254 #undef TARGET_SCHED_ADJUST_COST
255 #define TARGET_SCHED_ADJUST_COST picochip_sched_adjust_cost
257 #undef TARGET_ASM_NAMED_SECTION
258 #define TARGET_ASM_NAMED_SECTION picochip_asm_named_section
260 #undef TARGET_HAVE_NAMED_SECTIONS
261 #define TARGET_HAVE_NAMED_SECTIONS 1
263 #undef TARGET_HAVE_SWITCHABLE_BSS_SECTIONS
264 #define TARGET_HAVE_SWITCHABLE_BSS_SECTIONS 1
266 #undef TARGET_INIT_LIBFUNCS
267 #define TARGET_INIT_LIBFUNCS picochip_init_libfuncs
269 #undef TARGET_ASM_FILE_START
270 #define TARGET_ASM_FILE_START picochip_asm_file_start
272 #undef TARGET_ASM_FILE_END
273 #define TARGET_ASM_FILE_END picochip_asm_file_end
275 #undef TARGET_MACHINE_DEPENDENT_REORG
276 #define TARGET_MACHINE_DEPENDENT_REORG picochip_reorg
278 #undef TARGET_ARG_PARTIAL_BYTES
279 #define TARGET_ARG_PARTIAL_BYTES picochip_arg_partial_bytes
281 #undef TARGET_FUNCTION_ARG
282 #define TARGET_FUNCTION_ARG picochip_function_arg
284 #undef TARGET_FUNCTION_INCOMING_ARG
285 #define TARGET_FUNCTION_INCOMING_ARG picochip_incoming_function_arg
287 #undef TARGET_FUNCTION_ARG_ADVANCE
288 #define TARGET_FUNCTION_ARG_ADVANCE picochip_arg_advance
290 #undef TARGET_FUNCTION_ARG_BOUNDARY
291 #define TARGET_FUNCTION_ARG_BOUNDARY picochip_function_arg_boundary
293 #undef TARGET_PROMOTE_FUNCTION_MODE
294 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote
295 #undef TARGET_PROMOTE_PROTOTYPES
296 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
298 /* Target support for Anchored Addresses optimization */
299 #undef TARGET_MIN_ANCHOR_OFFSET
300 #define TARGET_MIN_ANCHOR_OFFSET 0
301 #undef TARGET_MAX_ANCHOR_OFFSET
302 #define TARGET_MAX_ANCHOR_OFFSET 7
303 #undef TARGET_ASM_OUTPUT_ANCHOR
304 #define TARGET_ASM_OUTPUT_ANCHOR picochip_asm_output_anchor
306 #undef TARGET_FUNCTION_VALUE
307 #define TARGET_FUNCTION_VALUE picochip_function_value
309 #undef TARGET_LIBGCC_CMP_RETURN_MODE
310 #define TARGET_LIBGCC_CMP_RETURN_MODE picochip_libgcc_cmp_return_mode
313 #undef TARGET_LEGITIMATE_ADDRESS_P
314 #define TARGET_LEGITIMATE_ADDRESS_P picochip_legitimate_address_p
316 #undef TARGET_LEGITIMIZE_ADDRESS
317 #define TARGET_LEGITIMIZE_ADDRESS picochip_legitimize_address
319 /* Loading and storing QImode values to and from memory
320 usually requires a scratch register. */
321 #undef TARGET_SECONDARY_RELOAD
322 #define TARGET_SECONDARY_RELOAD picochip_secondary_reload
323 #undef DONT_USE_BUILTIN_SETJMP
324 #define DONT_USE_BUILTIN_SETJMP 1
326 /* How Large Values are Returned */
328 #undef TARGET_RETURN_IN_MEMORY
329 #define TARGET_RETURN_IN_MEMORY picochip_return_in_memory
331 #undef TARGET_STATIC_CHAIN
332 #define TARGET_STATIC_CHAIN picochip_static_chain
334 #undef TARGET_OPTION_OVERRIDE
335 #define TARGET_OPTION_OVERRIDE picochip_option_override
337 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE
338 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE picochip_option_override
340 #undef TARGET_OPTION_OPTIMIZATION_TABLE
341 #define TARGET_OPTION_OPTIMIZATION_TABLE picochip_option_optimization_table
343 #undef TARGET_EXCEPT_UNWIND_INFO
344 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
346 struct gcc_target targetm = TARGET_INITIALIZER;
349 /* Only return a value in memory if it is greater than 4 bytes.
350 int_size_in_bytes returns -1 for variable size objects, which go in
351 memory always. The cast to unsigned makes -1 > 8. */
354 picochip_return_in_memory(const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
356 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 4);
359 /* Allow some options to be overriden. In particular, the 2nd
360 scheduling pass option is switched off, and a machine dependent
361 reorganisation ensures that it is run later on, after the second
362 jump optimisation. */
365 picochip_option_override (void)
367 /* If we are optimizing for stack, dont let inliner to inline functions
368 that could potentially increase stack size.*/
369 if (flag_conserve_stack)
371 maybe_set_param_value (PARAM_LARGE_STACK_FRAME, 0,
372 global_options.x_param_values,
373 global_options_set.x_param_values);
374 maybe_set_param_value (PARAM_STACK_FRAME_GROWTH, 0,
375 global_options.x_param_values,
376 global_options_set.x_param_values);
379 /* Turn off the elimination of unused types. The elaborator
380 generates various interesting types to represent constants,
381 generics, and so on, and it is useful to retain this information
382 in the debug output. The increased size of the debug information
383 is not really an issue for us. */
384 flag_eliminate_unused_debug_types = 0;
386 /* Even if the user specifies a -fno-omit-frame-pointer on the
387 command line, we still want to go ahead and omit frame pointer
388 usages, since we dont really have a frame pointer register.
389 So, all accesses to FP need to be converted to accesses off
391 flag_omit_frame_pointer = 1;
393 /* Turning on anchored addresses by default. This is an optimization
394 that could decrease the code size by placing anchors in data and
395 accessing offsets from the anchor for file local data variables.*/
397 flag_section_anchors = 1;
399 /* Turn off the second scheduling pass, and move it to
400 picochip_reorg, to avoid having the second jump optimisation
401 trash the instruction modes (e.g., instructions are changed to
402 TImode to mark the beginning of cycles). Two types of DFA
403 scheduling are possible: space and speed. In both cases,
404 instructions are reordered to avoid stalls (e.g., memory loads
405 stall for one cycle). Speed scheduling will also enable VLIW
406 instruction packing. VLIW instructions use more code space, so
407 VLIW scheduling is disabled when scheduling for size. */
408 picochip_flag_schedule_insns2 = flag_schedule_insns_after_reload;
409 flag_schedule_insns_after_reload = 0;
410 if (picochip_flag_schedule_insns2)
413 picochip_schedule_type = DFA_TYPE_SPACE;
416 picochip_schedule_type = DFA_TYPE_SPEED;
417 flag_delayed_branch = 0;
421 picochip_schedule_type = DFA_TYPE_NONE;
423 /* Ensure that the debug level is always at least -g2. The flow
424 analyser works at its best if it always has debug
425 information. DWARF is non-intrusive, so it makes no difference to
426 code quality if debug is always enabled. */
427 if (debug_info_level < DINFO_LEVEL_NORMAL)
429 debug_info_level = DINFO_LEVEL_NORMAL;
430 write_symbols = DWARF2_DEBUG;
433 /* Options of the form -mae=mac, and so on will be substituted by
434 the compiler driver for the appropriate byte access and multiply
435 unit ISA options. Any unrecognised AE types will end up being
436 passed to the compiler, which should reject them as invalid. */
437 if (picochip_ae_type_string != NULL)
438 error ("invalid AE type specified (%s)", picochip_ae_type_string);
440 /* Override any specific capabilities of the instruction set. These
441 take precedence over any capabilities inferred from the AE type,
442 regardless of where the options appear on the command line. */
443 if (picochip_mul_type_string == NULL)
445 /* Default to MEM-type multiply, for historical compatibility. */
446 picochip_has_mac_unit = false;
447 picochip_has_mul_unit = true;
451 picochip_has_mac_unit = false;
452 picochip_has_mul_unit = false;
454 if (strcmp (picochip_mul_type_string, "mul") == 0)
455 picochip_has_mul_unit = true;
456 else if (strcmp (picochip_mul_type_string, "mac") == 0)
457 picochip_has_mac_unit = true;
458 else if (strcmp (picochip_mul_type_string, "none") == 0)
459 { /* Do nothing. Unit types already set to false. */ }
461 error ("invalid mul type specified (%s) - expected mac, mul or none",
462 picochip_mul_type_string);
468 /* Initialise the library functions to handle arithmetic on some of
471 picochip_init_libfuncs (void)
474 set_optab_libfunc (ashr_optab, DImode, "__ashrdi3");
475 set_optab_libfunc (ashl_optab, DImode, "__ashldi3");
476 set_optab_libfunc (lshr_optab, DImode, "__lshrdi3");
478 /* 64-bit signed multiplication. */
479 set_optab_libfunc (smul_optab, DImode, "__muldi3");
481 /* Signed division */
482 set_optab_libfunc (sdiv_optab, HImode, "__divhi3");
483 set_optab_libfunc (sdiv_optab, DImode, "__divdi3");
486 set_optab_libfunc (smod_optab, HImode, "__modhi3");
487 set_optab_libfunc (smod_optab, DImode, "__moddi3");
489 /* 32-bit count leading Zeros*/
490 set_optab_libfunc (clz_optab, SImode, "_clzsi2");
492 /* 64-bit comparison */
493 set_optab_libfunc (ucmp_optab, DImode, "__ucmpdi2");
494 set_optab_libfunc (cmp_optab, DImode, "__cmpdi2");
496 /* 64-bit addition and subtraction*/
497 set_optab_libfunc (add_optab, DImode, "_adddi3");
498 set_optab_libfunc (sub_optab, DImode, "_subdi3");
501 /* Memcpy function */
503 picochip_expand_movmemhi (rtx *operands)
505 rtx src_addr_reg, dst_addr_reg, count_reg, src_mem, dst_mem, tmp_reg;
508 src_addr_reg = gen_reg_rtx(HImode);
509 dst_addr_reg = gen_reg_rtx(HImode);
510 count_reg = gen_reg_rtx(HImode);
511 emit_insn (gen_movhi (count_reg, operands[2]));
512 emit_insn (gen_movqi (src_addr_reg, XEXP(operands[1], 0)));
513 emit_insn (gen_movqi (dst_addr_reg, XEXP(operands[0], 0)));
514 gcc_assert (GET_CODE(count_reg) == REG);
515 start_label = gen_label_rtx ();
516 emit_label (start_label);
518 /* We can specialise the code for different alignments */
519 align = INTVAL(operands[3]);
520 size = INTVAL(operands[2]);
521 gcc_assert(align >= 0 && size >= 0);
524 if (size % 4 == 0 && align % 4 == 0)
526 src_mem = gen_rtx_MEM(SImode, src_addr_reg);
527 dst_mem = gen_rtx_MEM(SImode, dst_addr_reg);
528 tmp_reg = gen_reg_rtx(SImode);
529 emit_insn (gen_movsi (tmp_reg, src_mem));
530 emit_insn (gen_movsi (dst_mem, tmp_reg));
531 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, GEN_INT(4)));
532 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, GEN_INT(4)));
533 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-4)));
534 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
535 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
537 else if (size % 2 == 0 && align % 2 == 0)
539 src_mem = gen_rtx_MEM(HImode, src_addr_reg);
540 dst_mem = gen_rtx_MEM(HImode, dst_addr_reg);
541 tmp_reg = gen_reg_rtx(HImode);
542 emit_insn (gen_movhi (tmp_reg, src_mem));
543 emit_insn (gen_movhi (dst_mem, tmp_reg));
544 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, const2_rtx));
545 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, const2_rtx));
546 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-2)));
547 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
548 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
552 src_mem = gen_rtx_MEM(QImode, src_addr_reg);
553 dst_mem = gen_rtx_MEM(QImode, dst_addr_reg);
554 tmp_reg = gen_reg_rtx(QImode);
555 emit_insn (gen_movqi (tmp_reg, src_mem));
556 emit_insn (gen_movqi (dst_mem, tmp_reg));
557 emit_insn (gen_addhi3 (dst_addr_reg, dst_addr_reg, const1_rtx));
558 emit_insn (gen_addhi3 (src_addr_reg, src_addr_reg, const1_rtx));
559 emit_insn (gen_addhi3 (count_reg, count_reg, GEN_INT(-1)));
560 /* The sub instruction above generates cc, but we cannot just emit the branch.*/
561 emit_cmp_and_jump_insns (count_reg, const0_rtx, GT, 0, HImode, 0, start_label);
568 /* Return the register class for letter C. */
570 picochip_reg_class_from_letter (unsigned c)
588 pico_leaf_reg_alloc_order[] = LEAF_REG_ALLOC_ORDER;
590 pico_nonleaf_reg_alloc_order[] = REG_ALLOC_ORDER;
593 picochip_order_regs_for_local_alloc (void)
595 /* We change the order for leaf functions alone. We put r12 at
596 the end since using it will prevent us to combine stw/ldws to
597 stl/ldl and it gives no benefit. In non-leaf functions, we
598 would anyway saveup/restore r12, so it makes sense to use it.*/
600 if (leaf_function_p())
602 memcpy ((char *)reg_alloc_order, (const char *) pico_leaf_reg_alloc_order,
603 FIRST_PSEUDO_REGISTER * sizeof (int));
607 memcpy ((char *)reg_alloc_order, (const char *) pico_nonleaf_reg_alloc_order,
608 FIRST_PSEUDO_REGISTER * sizeof (int));
612 /* Check that VALUE (an INT_CST) is ok as a constant of type C. */
614 picochip_const_ok_for_letter_p (unsigned HOST_WIDE_INT value, unsigned c)
619 case 'I': /* 4 bits signed. */
620 return value + 8 < 16;
621 case 'J': /* 4 bits unsigned. */
623 case 'K': /* 8 bits signed. */
624 return value + 128 < 256;
625 case 'M': /* 4-bit magnitude. */
626 return abs (value) < 16;
627 case 'N': /* 10 bits signed. */
628 return value + 512 > 1024;
629 case 'O': /* 16 bits signed. */
630 return value + 32768 < 65536;
631 default: /* Unknown letter. */
636 /* Stack utility functions. */
638 picochip_return_addr_rtx(int count, rtx frameaddr ATTRIBUTE_UNUSED)
641 return gen_rtx_REG (Pmode, LINK_REGNUM);
647 /* Emit a set of parallel register expressions used to store
648 blockmode values to pass to functions. */
650 picochip_emit_register_parallel (int size_in_units, int offset)
654 rtx vector[MAX_CALL_PARAMETER_REGS];
658 /* Compute the base register, and number of required registers. */
659 base_reg = offset / 2;
660 num_regs = size_in_units / 2;
661 if (size_in_units % 2 == 1)
664 /* Emit a register for each part of the block mode value to be
665 passed in a register. */
666 for (i = 0; i < num_regs; i++)
667 vector[i] = gen_rtx_EXPR_LIST (VOIDmode,
668 gen_rtx_REG (HImode, base_reg + i),
670 result = gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (num_regs, vector));
676 /* Emit an instruction to allocate a suitable amount of space on the
677 stack, by decrementing the stack pointer. */
679 picochip_emit_stack_allocate (int adjustment)
682 rtx stack_pointer_reg = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
684 /* Use an addition of a negative value. */
685 insn = emit_insn (gen_addhi3 (stack_pointer_reg, stack_pointer_reg,
686 GEN_INT (-adjustment)));
688 /* Make the instruction frame related. Also add an expression note,
689 so that the correct Dwarf information is generated (see documention
690 for RTX_FRAME_RELATED_P for more details). */
691 RTX_FRAME_RELATED_P (insn) = 1;
692 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
693 gen_rtx_SET (VOIDmode, stack_pointer_reg,
694 gen_rtx_PLUS (Pmode, stack_pointer_reg,
695 GEN_INT (-adjustment))));
699 /* Emit an instruction to save a register of the given mode. The
700 offset at which to save the register is given relative to the stack
703 picochip_emit_save_register (rtx reg, int offset)
705 rtx stack_pointer, address, mem, insn;
707 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
709 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
711 mem = gen_rtx_MEM (GET_MODE (reg), address);
713 insn = emit_move_insn (mem, reg);
714 RTX_FRAME_RELATED_P (insn) = 1;
716 /* For modes other than HImode, create a note explaining that
717 multiple registers have been saved. This allows the correct DWARF
718 call frame information to be generated. */
719 switch (GET_MODE (reg))
722 /* The RTL is sufficient to explain HImode register saves. */
726 /* SImode must be broken down into parallel HImode register saves. */
734 gen_rtx_PLUS (Pmode, stack_pointer,
736 gen_rtx_REG (HImode, REGNO (reg)));
737 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 0)) = 1;
740 gen_rtx_SET (HImode, gen_rtx_MEM (HImode,
745 gen_rtx_REG (HImode, REGNO (reg) + 1));
746 RTX_FRAME_RELATED_P (RTVEC_ELT (p, 1)) = 1;
748 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
749 gen_rtx_PARALLEL (VOIDmode, p));
756 ("unexpected mode %s encountered in picochip_emit_save_register",
757 GET_MODE_NAME (GET_MODE (reg)));
762 /* Emit an instruction to restore a register of the given mode. The
763 offset from which to restore the register is given relative to the
766 picochip_emit_restore_register (rtx reg, int offset)
768 rtx stack_pointer, address, mem;
770 stack_pointer = gen_rtx_REG (Pmode, STACK_POINTER_REGNUM);
772 address = gen_rtx_PLUS (Pmode, stack_pointer, GEN_INT (offset));
774 mem = gen_rtx_MEM (GET_MODE (reg), address);
776 emit_move_insn (reg, mem);
780 /* Check that the given byte offset is aligned to the given number of
783 picochip_is_aligned (int byte_offset, int bit_alignment)
785 int byte_alignment = bit_alignment / BITS_PER_UNIT;
786 return (byte_offset % byte_alignment) == 0;
789 /*****************************************************************************
792 * The following section contains code which controls how the stack is
795 * The stack is laid out as follows (high addresses first):
798 * Pretend arguments (ARG PTR)
802 * Outgoing arguments (SP)
804 * The (constant) offsets of the different areas must be calculated
805 * relative to the stack area immediately below, and aligned
806 * appropriately. For example, the frame offset is computed by
807 * determining the offset of the special register area, adding the
808 * size of the special register area, and then aligning the resulting
809 * offset correctly. In turn, the special register offset is computed
810 * from the general register offset, and so on. This enables the
811 * different offsets to change size and alignment, without requiring
812 * the code for other offset calculations to be rewritten.
814 * The argument pointer, and the frame pointer are eliminated wherever
815 * possible, by replacing them with a constant offset from the stack
816 * pointer. In the rare cases where constant offsets from the stack
817 * pointer cannot be computed, another register will be allocated to
818 * serve as the argument pointer, or the frame pointer.
820 * The save registers are stored at small offsets from the caller, to
821 * enable the more efficient SP-based ISA instructions to be used.
823 ****************************************************************************/
825 /* Compute the size of an argument in units. */
827 picochip_compute_arg_size (const_tree type, enum machine_mode mode)
829 int type_size_in_units = 0;
832 type_size_in_units = tree_low_cst (TYPE_SIZE_UNIT (type), 1);
834 type_size_in_units = GET_MODE_SIZE (mode);
836 return type_size_in_units;
840 /* Determine where the next outgoing arg should be placed. */
842 picochip_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
843 const_tree type, bool named ATTRIBUTE_UNUSED)
846 int type_align_in_units = 0;
847 int type_size_in_units;
849 int offset_overflow = 0;
851 /* VOIDmode is passed when computing the second argument to a `call'
852 pattern. This can be ignored. */
853 if (mode == VOIDmode)
856 /* Compute the alignment and size of the parameter. */
857 type_align_in_units =
858 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
859 type_size_in_units = picochip_compute_arg_size (type, mode);
861 /* Compute the correct offset (i.e., ensure that the offset meets
862 the alignment requirements). */
863 offset_overflow = *cum % type_align_in_units;
864 if (offset_overflow == 0)
867 new_offset = (*cum - offset_overflow) + type_align_in_units;
871 printf ("Function arg:\n");
872 printf (" Type valid: %s\n", (type ? "yes" : "no"));
873 printf (" Cumulative Value: %d\n", *cum);
874 printf (" Mode: %s\n", GET_MODE_NAME (mode));
875 printf (" Type size: %i units\n", type_size_in_units);
876 printf (" Alignment: %i units\n", type_align_in_units);
877 printf (" New offset: %i\n", new_offset);
881 /* If the new offset is outside the register space, return. */
882 if (new_offset >= MAX_CALL_PARAMETER_REGS * 2)
885 /* If the end of the argument is outside the register space, then
886 the argument must overlap the register space. Return the first
887 available register. */
888 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
889 return gen_rtx_REG (HImode, new_offset / 2);
891 /* Create a register of the required mode to hold the parameter. */
892 reg = new_offset / 2;
907 return gen_rtx_REG (mode, reg);
911 /* Empty blockmode values can be passed as arguments (e.g.,
912 * empty structs). These require no registers
913 * whatsoever. Non-empty blockmode values are passed in a set
914 * of parallel registers. */
915 if (type_size_in_units == 0)
918 return picochip_emit_register_parallel (type_size_in_units, new_offset);
923 (0, "defaulting to stack for %s register creation",
924 GET_MODE_NAME (mode));
932 /* Determine where the next incoming function argument will
933 appear. Normally, this works in exactly the same way as
934 picochip_function_arg, except when the function in question is a
935 varadic function. In this case, the incoming arguments all appear
936 to be passed on the stack (actually, some of the arguments are
937 passed in registers, which are then pushed onto the stack by the
938 function prologue). */
940 picochip_incoming_function_arg (CUMULATIVE_ARGS *cum,
941 enum machine_mode mode,
942 const_tree type, bool named)
948 return picochip_function_arg (cum, mode, type, named);
952 /* Gives the alignment boundary, in bits, of an argument with the
955 picochip_function_arg_boundary (enum machine_mode mode,
956 const_tree type ATTRIBUTE_UNUSED)
961 align = STACK_BOUNDARY;
963 align = GET_MODE_ALIGNMENT (mode);
965 if (align < PARM_BOUNDARY)
966 align = PARM_BOUNDARY;
972 /* Compute partial registers. */
974 picochip_arg_partial_bytes (CUMULATIVE_ARGS * p_cum, enum machine_mode mode,
975 tree type, bool named ATTRIBUTE_UNUSED)
977 int type_align_in_units = 0;
978 int type_size_in_units;
980 int offset_overflow = 0;
982 unsigned cum = *((unsigned *) p_cum);
984 /* VOIDmode is passed when computing the second argument to a `call'
985 pattern. This can be ignored. */
986 if (mode == VOIDmode)
989 /* Compute the alignment and size of the parameter. */
990 type_align_in_units =
991 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
992 type_size_in_units = picochip_compute_arg_size (type, mode);
994 /* Compute the correct offset (i.e., ensure that the offset meets
995 the alignment requirements). */
996 offset_overflow = cum % type_align_in_units;
997 if (offset_overflow == 0)
1000 new_offset = (cum - offset_overflow) + type_align_in_units;
1004 printf ("Partial function arg nregs:\n");
1005 printf (" Type valid: %s\n", (type ? "yes" : "no"));
1006 printf (" Cumulative Value: %d\n", cum);
1007 printf (" Mode: %s\n", GET_MODE_NAME (mode));
1008 printf (" Type size: %i units\n", type_size_in_units);
1009 printf (" Alignment: %i units\n", type_align_in_units);
1010 printf (" New offset: %i\n", new_offset);
1014 /* If the new offset is outside the register space, return. */
1015 if (new_offset >= (MAX_CALL_PARAMETER_REGS * 2))
1018 /* If the end of the argument is outside the register space, then
1019 the argument must overlap the register space. Return the number
1020 of bytes which are passed in registers. */
1021 if ((new_offset + type_size_in_units) > (MAX_CALL_PARAMETER_REGS * 2))
1022 return ((MAX_CALL_PARAMETER_REGS * 2) - new_offset);
1028 /* Advance the cumulative args counter CUM. */
1030 picochip_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1031 const_tree type, bool named ATTRIBUTE_UNUSED)
1033 int type_align_in_units = 0;
1034 int type_size_in_units;
1036 int offset_overflow = 0;
1038 /* VOIDmode is passed when computing the second argument to a `call'
1039 pattern. This can be ignored. */
1040 if (mode == VOIDmode)
1043 /* Compute the alignment and size of the parameter. */
1044 type_align_in_units =
1045 picochip_function_arg_boundary (mode, type) / BITS_PER_UNIT;
1046 type_size_in_units = picochip_compute_arg_size (type, mode);
1048 /* Compute the correct offset (i.e., ensure that the offset meets
1049 the alignment requirements). */
1050 offset_overflow = *cum % type_align_in_units;
1051 if (offset_overflow == 0)
1054 new_offset = (*cum - offset_overflow) + type_align_in_units;
1056 /* Advance past the last argument. */
1057 new_offset += type_size_in_units;
1062 /* Determine whether a register needs saving/restoring. It does if it
1063 is live in a function, and isn't a call-used register. */
1065 picochip_reg_needs_saving (int reg_num)
1067 return df_regs_ever_live_p(reg_num) && !call_used_regs[reg_num];
1070 /* Compute and return offset of the main frame. */
1072 picochip_frame_byte_offset (void)
1074 gcc_assert(picochip_is_aligned
1075 (crtl->outgoing_args_size, BITS_PER_WORD));
1077 return crtl->outgoing_args_size;
1080 /* Return the size of the main frame. */
1082 picochip_frame_size_in_bytes (void)
1084 int frame_size = get_frame_size();
1085 int stack_align = STACK_BOUNDARY/BITS_PER_UNIT;
1086 if (!picochip_is_aligned (frame_size, STACK_BOUNDARY))
1087 frame_size = frame_size + (stack_align - frame_size%stack_align);
1088 gcc_assert(picochip_is_aligned (frame_size, STACK_BOUNDARY));
1092 /* Compute and return the size (in bytes) of the register save/restore
1093 area for the current function. This only includes the general
1094 purpose registers - the special purpose stack pointer and link
1095 registers are not included in this area. */
1097 picochip_save_area_size_in_bytes (void)
1099 int num_regs_to_save = 0;
1102 /* Read through all the registers, determining which need to be saved. */
1103 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1105 if (picochip_reg_needs_saving (i))
1106 num_regs_to_save += 1;
1109 return num_regs_to_save * UNITS_PER_WORD;
1113 /* Compute and return offset of the save area base. */
1115 picochip_save_area_byte_offset (void)
1117 int base_offset = (picochip_frame_byte_offset () +
1118 picochip_frame_size_in_bytes ());
1120 gcc_assert(picochip_is_aligned (base_offset, BITS_PER_WORD));
1126 /* Compute and return offset of the special register save area. This
1127 area can be found immediately above the normal save area. It must
1128 be aligned, to allow the registers to be saved and restored as a
1131 picochip_special_save_area_byte_offset (void)
1133 int byte_alignment = STACK_BOUNDARY / BITS_PER_UNIT;
1134 int offset = (picochip_save_area_byte_offset () +
1135 picochip_save_area_size_in_bytes ());
1137 if ((offset % byte_alignment) != 0)
1138 offset = ((offset / byte_alignment) + 1) * byte_alignment;
1144 /* Determine whether the LNK/SP register save/restores can be eliminated. */
1146 picochip_can_eliminate_link_sp_save (void)
1148 /* This deserves some reasoning. The df_regs_ever_live_p call keeps
1149 changing during optimizations phases. So, this function returns different
1150 values when called from initial_elimination_offset and then again when it
1151 is called from prologue/epilogue generation. This means that argument
1152 accesses become wrong. This wouldnt happen only if we were not using the
1153 stack at all. The following conditions ensures that.*/
1155 return (current_function_is_leaf &&
1156 !df_regs_ever_live_p(LINK_REGNUM) &&
1157 !df_regs_ever_live_p(STACK_POINTER_REGNUM) &&
1158 (picochip_special_save_area_byte_offset() == 0) &&
1159 (crtl->args.size == 0) &&
1160 (crtl->args.pretend_args_size == 0));
1163 /* Compute the size of the special reg save area (SP and LNK). If the
1164 SP/LNK registers don't need to be saved, this area can shrink to
1167 picochip_special_save_area_size_in_bytes (void)
1171 if (picochip_can_eliminate_link_sp_save ())
1174 return 2 * UNITS_PER_WORD;
1177 /* Return the number of pretend arguments. If this function is
1178 varadic, all the incoming arguments are effectively passed on the
1179 stack. If this function has real pretend arguments (caused by a
1180 value being passed partially on the stack and partially in
1181 registers), then return the number of registers used. */
1183 picochip_pretend_arg_area_size (void)
1186 if (crtl->args.pretend_args_size != 0)
1188 gcc_assert(crtl->args.pretend_args_size % 4 == 0);
1190 return crtl->args.pretend_args_size;
1192 else if (cfun->stdarg)
1199 /* Compute and return the offset of the pretend arguments. The pretend
1200 arguments are contiguous with the incoming arguments, and must be
1201 correctly aligned. */
1203 picochip_pretend_arg_area_byte_offset (void)
1205 int base_offset = 0;
1207 base_offset = (picochip_special_save_area_byte_offset () +
1208 picochip_special_save_area_size_in_bytes ());
1210 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1211 gcc_assert(picochip_is_aligned
1212 (base_offset + picochip_pretend_arg_area_size (), STACK_BOUNDARY));
1218 /* Compute and return the offset of the incoming arguments. If a
1219 static chain is in use, this will be passed just before the other
1220 arguments. This means that the pretend argument mechanism, used in
1221 variadic functions, doesn't work properly. Thus, static chains work
1222 on their own, as do variadic functions, but not the combination of
1223 the two. This isn't really a problem. */
1225 picochip_arg_area_byte_offset (void)
1227 int base_offset = (picochip_pretend_arg_area_byte_offset () +
1228 picochip_pretend_arg_area_size ());
1230 /* Add an extra 4 bytes - only an extra 16-bits are required, but
1231 the alignment on a 32-bit boundary must be maintained. */
1232 if (cfun->static_chain_decl != NULL)
1234 gcc_assert (!cfun->stdarg);
1238 gcc_assert(picochip_is_aligned (base_offset, STACK_BOUNDARY));
1245 picochip_regno_nregs (int regno ATTRIBUTE_UNUSED, int mode)
1248 /* Special case - only one register needed. */
1249 if (GET_MODE_CLASS (mode) == MODE_CC)
1252 /* We actually do not allocate acc0 ever. But, it seems like we need to
1253 make it look like a allocatable register for the dataflow checks to work
1254 properly. Note that hard_regno_mode_ok will always return 0 for acc0*/
1259 /* General case - compute how much space in terms of units. */
1260 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1265 picochip_class_max_nregs (int reg_class, int mode)
1267 int size = ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD);
1269 if (reg_class == ACC_REGS)
1272 if (GET_MODE_CLASS (mode) == MODE_CC)
1279 /* Eliminate a register that addresses the stack (e.g., frame pointer,
1280 argument pointer) by replacing it with a constant offset from the
1281 main stack register. */
1283 initial_elimination_offset (int from, int to)
1285 int offset_from_sp = 0;
1287 if (FRAME_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1288 offset_from_sp = picochip_frame_byte_offset ();
1289 else if (ARG_POINTER_REGNUM == from && STACK_POINTER_REGNUM == to)
1290 offset_from_sp = picochip_pretend_arg_area_byte_offset ();
1294 return offset_from_sp;
1298 /* Compute and return the size of the incoming argument area. */
1300 picochip_arg_area_size_in_bytes (void)
1302 return crtl->args.size;
1305 /* Determine whether the given register is valid. When the strict mode
1306 is used, only hard registers are valid, otherwise any register is
1309 picochip_legitimate_address_register (rtx x, unsigned strict)
1312 /* Sanity check - non-registers shouldn't make it here, but... */
1313 if (REG != GET_CODE (x))
1317 return REGNO (x) < FIRST_NONHARD_REGISTER;
1323 /* Determine whether the given constant is in the range required for
1324 the given base register. */
1326 picochip_const_ok_for_base (enum machine_mode mode, int regno, int offset)
1328 HOST_WIDE_INT corrected_offset;
1330 if (GET_MODE_SIZE (mode) != 0)
1332 if (GET_MODE_SIZE(mode) <= 4)
1334 /* We used to allow incorrect offsets if strict is 0. But, this would
1335 then rely on reload doing the right thing. We have had problems
1336 there before, and on > 4.3 compiler, there are no benefits. */
1337 if (offset % GET_MODE_SIZE (mode) != 0)
1339 corrected_offset = offset / GET_MODE_SIZE (mode);
1343 if (offset % 4 != 0)
1345 corrected_offset = offset / 4;
1350 /* Default to the byte offset as supplied. */
1351 corrected_offset = offset;
1354 /* The offset from the base register can be different depending upon
1355 the base register. The stack/frame/argument pointer offsets can
1356 all be greater than a simple register-based offset. Note that the
1357 frame/argument pointer registers are actually eliminations of the
1358 stack pointer, so a value which is valid for an offset to, for
1359 example, the frame pointer, might be invalid for the stack
1360 pointer once the elimination has occurred. However, there is no
1361 need to handle this special case here, as the stack offset is
1362 always checked after elimination anyway, and the generated code
1363 seems to have identical performance. */
1364 if (regno == STACK_POINTER_REGNUM ||
1365 regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
1366 return picochip_const_ok_for_letter_p (corrected_offset, 'K');
1368 return picochip_const_ok_for_letter_p (corrected_offset, 'J');
1372 /* Determine whether a given rtx is a legitimate address for machine_mode
1373 MODE. STRICT is non-zero if we're being strict - any pseudo that
1374 is not a hard register must be a memory reference. */
1376 picochip_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1380 switch (GET_CODE (x))
1383 valid = picochip_legitimate_address_register (x, strict);
1388 rtx base = XEXP (x, 0);
1389 rtx offset = XEXP (x, 1);
1390 if (strict && !REGNO_OK_FOR_BASE_P (REGNO(base)))
1396 valid = (REG == GET_CODE (base) &&
1397 picochip_legitimate_address_register (base, strict) &&
1398 CONST_INT == GET_CODE (offset) &&
1399 picochip_const_ok_for_base (mode, REGNO (base),
1405 /* The user can select whether a symbol can be used as a memory
1406 address. Typically, this will decrease execution time (no
1407 register load is required first), but will increase code size
1408 (because the symbol will be used several times, rather than
1409 loaded once into a register.*/
1410 valid = TARGET_SYMBOL_AS_ADDRESS;
1415 /* A constant memory address must be a (plus (symbol_ref)
1416 (const_int)), and is only allowed when the symbols are
1417 permitted addresses. */
1418 rtx inner = XEXP (x, 0);
1420 valid = (TARGET_SYMBOL_AS_ADDRESS &&
1421 PLUS == GET_CODE (inner) &&
1422 SYMBOL_REF == GET_CODE (XEXP (inner, 0)) &&
1423 CONST_INT == GET_CODE (XEXP (inner, 1)));
1437 /* For all memory operations, picochip allows a uconst4 offset value. It
1438 is hence beneficial to turn an
1439 addr = <reg + long_const>
1444 X = reg + long_const & FFF0
1445 diff = long_const - (long_const & FFF0)
1448 X can be reused in subsequent memory operations.
1451 picochip_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1452 enum machine_mode mode)
1459 /* Depending on mode, the offsets allowed are either 16/32/64.*/
1475 if (GET_CODE (x) == PLUS
1476 && GET_CODE (XEXP (x, 0)) == REG
1477 && GET_CODE (XEXP (x, 1)) == CONST_INT)
1479 int high_val, low_val, offset;
1480 offset = INTVAL (XEXP (x, 1));
1481 /* Ignore cases with negative offsets. */
1484 high_val = offset & mask_val;
1485 low_val = offset - high_val;
1488 rtx temp_reg = force_reg (Pmode, gen_rtx_PLUS (Pmode, XEXP (x, 0), GEN_INT(high_val)));
1489 x = gen_rtx_PLUS (Pmode, temp_reg, GEN_INT(low_val));
1496 /* For all memory operations, picochip allows a uconst4 offset value. It
1497 is hence beneficial to turn an
1498 addr = <reg + long_const>
1503 X = reg + long_const & FFF0
1504 diff = long_const - (long_const & FFF0)
1507 X can be reused in subsequent memory operations.
1510 picochip_legitimize_reload_address (rtx *x,
1511 enum machine_mode mode,
1512 int opnum, int type,
1513 int ind_levels ATTRIBUTE_UNUSED)
1517 if (picochip_symbol_offset(*x))
1519 *x = gen_rtx_CONST(mode, *x);
1525 /* We should recognise addresses that we created.*/
1526 if (GET_CODE (*x) == PLUS
1527 && GET_CODE (XEXP (*x, 0)) == PLUS
1528 && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
1529 && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
1530 && GET_CODE (XEXP (*x, 1)) == CONST_INT)
1532 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
1533 BASE_REG_CLASS, GET_MODE (*x), VOIDmode, 0, 0,
1534 opnum, (enum reload_type)type);
1538 /* Depending on mode, the offsets allowed are either 16/32/64. */
1554 if (GET_CODE (*x) == PLUS
1555 && GET_CODE (XEXP (*x, 0)) == REG
1556 && GET_CODE (XEXP (*x, 1)) == CONST_INT)
1558 int high_val, low_val, offset;
1559 offset = INTVAL (XEXP (*x, 1));
1560 /* Ignore cases with negative offsets. */
1563 high_val = offset & mask_val;
1564 low_val = offset - high_val;
1567 rtx temp_reg = gen_rtx_PLUS (Pmode, XEXP (*x, 0), GEN_INT(high_val));
1568 *x = gen_rtx_PLUS (Pmode, temp_reg, GEN_INT(low_val));
1569 push_reload (XEXP (*x, 0), NULL_RTX, &XEXP (*x, 0), NULL,
1570 BASE_REG_CLASS, GET_MODE (*x), VOIDmode, 0, 0,
1571 opnum, (enum reload_type)type);
1579 /* Detect an rtx which matches (plus (symbol_ref) (const_int)). */
1581 picochip_symbol_offset (rtx operand)
1584 return (PLUS == GET_CODE (operand) &&
1585 SYMBOL_REF == GET_CODE (XEXP (operand, 0)) &&
1586 CONST_INT == GET_CODE (XEXP (operand, 1)));
1590 /* Assembly output. */
1592 /* The format here should match the format used in the output of
1593 symbol_ref's elsewhere in this file. */
1595 picochip_output_label (FILE * stream, const char name[])
1597 int is_cfi_label = (strncmp (name, "picoMark_LCFI", 13) == 0);
1599 /* If VLIW scheduling is in use, any Call Frame Information labels
1600 generated inside a packet must have their output deferred until
1601 the end of the packet. */
1602 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1603 is_cfi_label && picochip_vliw_continuation)
1605 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1607 internal_error ("LCFI labels have already been deferred");
1609 strcpy (picochip_current_vliw_state.cfi_label_name[
1610 picochip_current_vliw_state.num_cfi_labels_deferred], name);
1611 picochip_current_vliw_state.num_cfi_labels_deferred++;
1615 assemble_name (stream, name);
1617 if (strncmp (name, "picoMark_", 9) == 0)
1618 fprintf (stream, "=\n");
1620 fprintf (stream, ":\n");
1626 /* The format here should match the format used in the output of
1627 symbol_ref's elsewhere in this file. */
1629 picochip_output_labelref (FILE * stream, const char name[])
1631 fprintf (stream, "_%s", name);
1635 picochip_weaken_label (FILE * stream, const char name[])
1637 fprintf (stream, ".weak ");
1638 assemble_name (stream, name);
1639 fprintf (stream, "\n");
1642 /* Return true if the given label (or label prefix) denotes a marker
1643 label which should be emitted in the form LABEL= */
1645 picochip_is_marker_prefix (const char *prefix)
1647 return (strcmp (prefix, "L") != 0 && strcmp (prefix, "LC") != 0
1648 && strcmp (prefix, "LP") != 0);
1652 picochip_output_internal_label (FILE * stream, const char *prefix,
1656 /* Emit different types of label, based upon their prefix. They
1657 are handled differently to allow the assembler to ensure that
1658 branch target labels are properly aligned, while other labels
1659 will only serve as code markers, not branch targets. Aligning
1660 labels unnecessarily can result in much code wastage. */
1661 if (picochip_is_marker_prefix (prefix))
1663 /* Special label marker. If it appears in the middle of a VLIW
1664 packet, defer it until the end of the packet. There has
1665 never been a need to handle more than one lm label at a time. */
1666 if (picochip_schedule_type == DFA_TYPE_SPEED &&
1667 (strcmp (prefix, "LM")) == 0 && picochip_vliw_continuation)
1669 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
1670 internal_error ("LM label has already been deferred");
1672 sprintf (picochip_current_vliw_state.lm_label_name,
1673 "picoMark_%s%ld", prefix, num);
1675 else if (picochip_schedule_type == DFA_TYPE_SPEED &&
1676 (strcmp (prefix, "LCFI")) == 0 && picochip_vliw_continuation)
1678 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
1680 internal_error ("LCFI labels have already been deferred.");
1682 sprintf(picochip_current_vliw_state.cfi_label_name[
1683 picochip_current_vliw_state.num_cfi_labels_deferred],
1684 "picoMark_%s%ld", prefix, num);
1685 picochip_current_vliw_state.num_cfi_labels_deferred++;
1690 fprintf (stream, "_picoMark_%s%ld=\n", prefix, num);
1697 fprintf (stream, "_%s%ld:\n", prefix, num);
1703 picochip_generate_internal_label (char *str, const char *prefix, long num)
1705 /* Two types of internal label can be generated: branch target
1706 labels and code marker labels. Branch target labels must always
1707 be aligned (since code will execute at these
1708 points). Differentiate between the two by prepending markers with
1709 a unique prefix, which can later be used in output_label to
1710 figure out which label syntax to use. */
1711 if (picochip_is_marker_prefix (prefix))
1712 sprintf (str, "picoMark_%s%ld", prefix, num);
1714 sprintf (str, "%s%ld", prefix, num);
1719 picochip_asm_output_anchor (rtx symbol)
1721 fprintf (asm_out_file, ".offsetData _%s, ",XSTR (symbol, 0));
1722 fprintf (asm_out_file, "+ " HOST_WIDE_INT_PRINT_DEC"\n",SYMBOL_REF_BLOCK_OFFSET(symbol));
1726 picochip_output_aligned_common (FILE * stream, const char *name,
1727 unsigned size, unsigned alignment)
1730 fprintf (stream, ".commonData ");
1731 assemble_name (stream, name);
1732 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1733 picochip_output_global (stream, name);
1738 picochip_output_aligned_local (FILE * stream, const char *name,
1739 unsigned size, unsigned alignment)
1742 fprintf (stream, ".commonData ");
1743 assemble_name (stream, name);
1744 fprintf (stream, ", %u, %u\n", size, alignment / 8);
1749 picochip_output_global (FILE * stream, const char *name)
1751 fprintf (stream, ".global ");
1752 assemble_name (stream, name);
1753 fprintf (stream, "\n");
1756 /* Output an assembly language string. Output as a sequence of decimal
1757 numbers, followed by the literal string to make it obvious what the
1758 numbers represent. */
1760 picochip_output_ascii (FILE * file, const char *str, int length)
1764 fprintf (file, ".ascii ");
1766 for (i = 0; i < length; ++i)
1768 fprintf (file, "16#%x# ", (char) (str[i]));
1771 fprintf (file, " ; ");
1773 for (i = 0; i < length; ++i)
1780 fprintf (file, "\\n");
1783 fprintf (file, "\\t");
1786 fprintf (file, "\\0");
1789 fprintf (file, "%c", c);
1794 fprintf (file, "\n");
1798 /* Output the beginning of an ASM file. */
1800 picochip_asm_file_start (void)
1802 default_file_start ();
1804 fprintf (asm_out_file, "// picoChip ASM file\n");
1805 fprintf (asm_out_file, "//.file \"%s\"\n", main_input_filename);
1807 fprintf (asm_out_file, "// Has byte access: %s\n",
1808 (TARGET_HAS_BYTE_ACCESS ? "Yes" : "No"));
1810 if (TARGET_HAS_MUL_UNIT)
1811 fprintf (asm_out_file, "// Has multiply: Yes (Multiply unit)\n");
1812 else if (TARGET_HAS_MAC_UNIT)
1813 fprintf (asm_out_file, "// Has multiply: Yes (Mac unit)\n");
1815 fprintf (asm_out_file, "// Has multiply: No\n");
1817 /* Variable tracking should be run after all optimizations which change order
1818 of insns. It also needs a valid CFG. This can't be done in
1819 picochip_option_override, because flag_var_tracking is finalized after
1821 picochip_flag_var_tracking = flag_var_tracking;
1822 flag_var_tracking = 0;
1825 /* Output the end of an ASM file. */
1827 picochip_asm_file_end (void)
1829 /* Include a segment end to make it easy for PERL scripts to grab
1830 segments. This is now done by assembler*/
1832 fprintf (asm_out_file, "// End of picoChip ASM file\n");
1836 /* Output frame debug information to the given stream. */
1838 picochip_output_frame_debug (FILE * file)
1842 if (current_function_is_leaf)
1843 fprintf (file, "\t\t// Leaf function\n");
1845 fprintf (file, "\t\t// Non-leaf function\n");
1847 if (picochip_can_eliminate_link_sp_save ())
1848 fprintf (file, "\t\t// Link/fp save/restore can be eliminated\n");
1850 if (cfun->static_chain_decl != NULL)
1851 fprintf (file, "\t\t// Static chain in use\n");
1853 fprintf (file, "\t\t// Incoming argument size: %d bytes\n",
1854 picochip_arg_area_size_in_bytes ());
1855 fprintf (file, "\t\t// Incoming arg offset: %d\n",
1856 picochip_arg_area_byte_offset ());
1857 fprintf (file, "\t\t// Pretend arg size: %d\n",
1858 picochip_pretend_arg_area_size ());
1859 fprintf (file, "\t\t// Pretend arg offset (ARGP): %d\n",
1860 picochip_pretend_arg_area_byte_offset ());
1861 fprintf (file, "\t\t// Special reg area size: %d bytes\n",
1862 picochip_special_save_area_size_in_bytes ());
1863 fprintf (file, "\t\t// Special reg area offset: %d\n",
1864 picochip_special_save_area_byte_offset ());
1866 /* Output which registers are saved. */
1867 fprintf (file, "\t\t// Saved regs: ");
1868 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1870 if (picochip_reg_needs_saving (i))
1871 fprintf (file, "%s ", picochip_regnames[i]);
1873 fprintf (file, "\t\t\n");
1875 fprintf (file, "\t\t// Save area size: %d bytes\n",
1876 picochip_save_area_size_in_bytes ());
1877 fprintf (file, "\t\t// Save area offset: %d\n",
1878 picochip_save_area_byte_offset ());
1880 fprintf (file, "\t\t// Frame size: %ld bytes\n", get_frame_size ());
1881 fprintf (file, "\t\t// Frame offset (FP): %d\n",
1882 picochip_frame_byte_offset ());
1884 fprintf (file, "\t\t// Outgoing argument area size: %d bytes\n",
1885 crtl->outgoing_args_size);
1889 /* Output picoChip function prologue. This contains human-readable
1890 information about the function. */
1892 picochip_function_prologue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1894 /* Get the function's name, as described by its RTL. This may be
1895 different from the DECL_NAME name used in the source file. The
1896 real declaration name must be used, to ensure that the prologue
1897 emits the right information for the linker. */
1900 x = DECL_RTL (current_function_decl);
1901 gcc_assert (MEM_P (x));
1903 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1904 fnname = XSTR (x, 0);
1906 /* Note that the name of the function is given in the &_%s
1907 form. This matches the name of the function as used in labels,
1908 and function calls, and enables processCallGraph to match
1909 function calls to the name of the function, as defined here. */
1910 fprintf (file, "// picoChip Function Prologue : &_%s = %d bytes\n",
1911 fnname, picochip_arg_area_byte_offset ());
1913 picochip_output_frame_debug (file);
1914 fprintf (file, "\n");
1918 /* Output picoChip function epilogue. */
1920 picochip_function_epilogue (FILE * file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
1925 x = DECL_RTL (current_function_decl);
1926 gcc_assert (MEM_P (x));
1928 gcc_assert (GET_CODE (x) == SYMBOL_REF);
1929 fnname = XSTR (x, 0);
1930 fprintf (file, "\n// picoChip Function Epilogue : %s\n\n",
1934 /* Manipulate the asm output. Some machines only execute the code when
1935 there is actually a chance of needing it (e.g., FRV doesn't execute
1936 it if the scheduling pass wasn't used). We always execute it,
1937 simple to ensure that it is exercised more often, and bugs are more
1940 This function's prime reason for existence is to insert the VLIW
1941 separators where appropriate. The separators must be inserted
1942 before any comments which appear at the end of the file.
1946 picochip_asm_output_opcode (FILE * f, const char *ptr)
1950 /* Flag to specify when a VLIW continuation has been inserted onto
1951 the line. Continuations are either inserted before any comments,
1952 or before the end of the line is reached. The flag ensures that
1953 we don't insert continuations twice (i.e., at the comment and the
1955 int continuation_inserted = 0;
1957 /* If the instruction uses multiple lines (i.e., a new line
1958 character appears in the opcode), then ensure that no attempt is
1959 made to pack it into a VLIW. */
1960 if (strchr (ptr, '\n') != NULL && picochip_vliw_continuation)
1962 ("picochip_asm_output_opcode - Found multiple lines in VLIW packet %s",
1966 /* If a delay slot is pending, output the directive to the assembler
1967 before the instruction. */
1968 if (picochip_is_delay_slot_pending)
1970 picochip_is_delay_slot_pending = 0;
1974 /* Keep going for entire opcode. All substitution performed ourselves. */
1979 /* Determine whether a VLIW continuation must be inserted before
1980 any comments, or the end of the opcode. A flag is set to show
1981 that we have inserted a continuation on this line, so that we
1982 don't try to insert another continuation when the end of the
1983 opcode is reached. The only other case for a continuation
1984 might have been a newline, but these aren't allowed in
1985 conjunction with VLIW continuations (see above code). */
1986 if (picochip_vliw_continuation &&
1987 !continuation_inserted &&
1988 ((c == '/' && (*ptr == '/')) || *ptr == '\0'))
1991 continuation_inserted = 1;
1994 /* Detect an explicit VLIW separator. */
1995 if (c == '%' && (*ptr == '|'))
2000 /* Detect the need for an ALU id operand. */
2001 else if (c == '%' && (*ptr == '#'))
2003 fputc (picochip_get_vliw_alu_id (), f);
2006 printf ("Generated ALU char at %s for insn %d\n", ptr,
2007 INSN_UID (picochip_current_prescan_insn));
2009 /* Skip past unwanted # */
2012 /* Detect the need for branch delay slot. */
2013 else if (c == '%' && (*ptr == '>'))
2015 /* Only emit delay slots (NOP's, or otherwise) when delay
2016 * slot scheduling has actually been enabled, otherwise VLIW
2017 * scheduling and delay slot scheduling output combine to
2018 * produce nasty effects. */
2019 if (flag_delayed_branch)
2021 if (dbr_sequence_length () == 0)
2022 fputs ("\n=->\tNOP", f);
2024 picochip_is_delay_slot_pending = 1;
2027 /* Skip past unwanted > */
2030 /* Detect any %digit specifiers. */
2031 else if (c == '%' && (*ptr >= '0' && *ptr <= '9'))
2034 picochip_print_operand (f, recog_data.operand[c], 0);
2035 while ((c = *ptr) >= '0' && c <= '9')
2038 /* Detect any %letterdigit specifiers. */
2039 else if (c == '%' && ((*ptr >= 'a' && *ptr <= 'z')
2040 || (*ptr >= 'A' && *ptr <= 'Z')))
2042 int letter = *ptr++;
2049 output_asm_label (recog_data.operand[c]);
2053 output_address (recog_data.operand[c]);
2057 picochip_print_operand (f, recog_data.operand[c], letter);
2060 while ((c = *ptr) >= '0' && c <= '9')
2065 ("picochip_asm_output_opcode - can%'t output unknown operator %c",
2071 /* Reached the end of the packet. If any labels were deferred
2072 during output, emit them now. */
2073 if (!picochip_vliw_continuation)
2075 if (picochip_current_vliw_state.num_cfi_labels_deferred != 0)
2078 assemble_name (f, picochip_current_vliw_state.cfi_label_name[0]);
2080 if (picochip_current_vliw_state.num_cfi_labels_deferred == 2)
2083 assemble_name (f, picochip_current_vliw_state.cfi_label_name[1]);
2088 if (strlen (picochip_current_vliw_state.lm_label_name) != 0)
2091 assemble_name (f, picochip_current_vliw_state.lm_label_name);
2096 /* Output an end-of-packet marker if requested. */
2097 if (!picochip_vliw_continuation &&
2098 TARGET_DEBUG && picochip_schedule_type == DFA_TYPE_SPEED)
2099 fprintf (f, "\n\t//-------------- End of VLIW packet -----------------");
2104 /* Function RTL expansion. */
2106 /* Expand the prologue into RTL. */
2108 picochip_expand_prologue (void)
2110 int stack_adjustment = 0;
2111 int special_save_offset = 0;
2112 int general_save_offset = 0;
2113 int reg_save_offset = 0;
2116 stack_adjustment = picochip_arg_area_byte_offset ();
2117 general_save_offset =
2118 -(stack_adjustment - picochip_save_area_byte_offset ());
2119 special_save_offset =
2120 -(stack_adjustment - picochip_special_save_area_byte_offset ());
2122 /* Save the link registers. We could try to save just one register
2123 here. This would reduce the amount of stack space required.
2124 There hasnt been a good reason to do that so far. */
2125 if (!picochip_can_eliminate_link_sp_save ())
2126 picochip_emit_save_register (gen_rtx_REG (SImode, LINK_REGNUM),
2127 special_save_offset);
2129 /* Save callee-save registers. */
2130 reg_save_offset = 0;
2131 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2133 if (picochip_reg_needs_saving (i))
2136 /* If this register is an even numbered register, and the
2137 next register also needs to be saved, use a SImode save,
2138 which does both in one instruction. Note that a special
2139 check is performed to ensure that the double word aligned
2140 store is valid (e.g., it is possible that r6, r8, r9 need
2141 to be saved, in which case once r6 has been saved, the
2142 stored offset is no longer aligned, and an STL/LDL
2143 instruction becomes invalid). Alternately, we could store all
2144 aligned registers first and then save the single one(s). */
2146 picochip_reg_needs_saving (i + 1) &&
2147 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
2149 picochip_emit_save_register (gen_rtx_REG (SImode, i),
2150 general_save_offset +
2152 reg_save_offset += 2 * UNITS_PER_WORD;
2157 picochip_emit_save_register (gen_rtx_REG (HImode, i),
2158 general_save_offset +
2160 reg_save_offset += UNITS_PER_WORD;
2166 /* Emit a stack adjustment where required. */
2167 if (stack_adjustment != 0)
2168 picochip_emit_stack_allocate (stack_adjustment);
2170 /* If this function uses varadic arguments, write any unnamed
2171 registers to the stack. */
2174 int stdarg_offset = picochip_pretend_arg_area_byte_offset ();
2176 /* Sanity check. The pretend argument offset should be 32-bit aligned. */
2177 gcc_assert(picochip_pretend_arg_area_byte_offset () % 4 == 0);
2179 picochip_emit_save_register (gen_rtx_REG (SImode, 0), stdarg_offset);
2180 picochip_emit_save_register (gen_rtx_REG (SImode, 2),
2182 picochip_emit_save_register (gen_rtx_REG (SImode, 4),
2189 /* Expand the epilogue into RTL. */
2191 picochip_expand_epilogue (int is_sibling_call ATTRIBUTE_UNUSED)
2193 int stack_adjustment = 0;
2194 int special_save_offset = 0;
2195 int general_save_offset = 0;
2196 int reg_save_offset = 0;
2198 int use_link_fp_restore_stack_adjust = 0; /* Default to using an explicit
2201 stack_adjustment = picochip_arg_area_byte_offset ();
2202 general_save_offset =
2203 -(stack_adjustment - picochip_save_area_byte_offset ());
2204 special_save_offset =
2205 -(stack_adjustment - picochip_special_save_area_byte_offset ());
2207 /* Emit a stack adjustment where required. */
2208 if (stack_adjustment != 0)
2210 /* If the link/fp is already being restored, and the offset to
2211 their save location is small enough, don't bother adjusting
2212 the stack explicitly. */
2213 if (picochip_special_save_area_byte_offset () < 512 &&
2214 !picochip_can_eliminate_link_sp_save ())
2215 use_link_fp_restore_stack_adjust = 1;
2217 /* Explicitly restore the stack. */
2218 picochip_emit_stack_allocate (-stack_adjustment);
2221 /* Restore the Link/FP registers. Only save the link register? */
2222 if (!picochip_can_eliminate_link_sp_save ())
2224 if (use_link_fp_restore_stack_adjust)
2225 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
2226 picochip_special_save_area_byte_offset
2229 picochip_emit_restore_register (gen_rtx_REG (SImode, LINK_REGNUM),
2230 special_save_offset);
2233 /* Restore callee-save registers. */
2234 reg_save_offset = 0;
2235 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
2237 if (picochip_reg_needs_saving (i))
2240 /* If this register is an even numbered register, and the
2241 next register also needs to be saved, use a SImode save,
2242 which does both in one instruction. Note that a special
2243 check is performed to ensure that the double word aligned
2244 store is valid (e.g., it is possible that r6, r8, r9 need
2245 to be saved, in which case once r6 has been saved, the
2246 stored offset is no longer aligned, and an STL/LDL
2247 instruction becomes invalid). We could store all aligned
2248 registers first, and then save the single one(s). */
2250 picochip_reg_needs_saving (i + 1) &&
2251 picochip_is_aligned (reg_save_offset, LONG_TYPE_SIZE))
2253 picochip_emit_restore_register (gen_rtx_REG (SImode, i),
2254 general_save_offset +
2256 reg_save_offset += 2 * UNITS_PER_WORD;
2261 picochip_emit_restore_register (gen_rtx_REG (HImode, i),
2262 general_save_offset +
2264 reg_save_offset += UNITS_PER_WORD;
2270 /* Emit a return instruction, which matches a (parallel
2271 [(return) (use r12)]) */
2274 p = rtvec_alloc (2);
2276 RTVEC_ELT (p, 0) = gen_rtx_RETURN (VOIDmode);
2277 RTVEC_ELT (p, 1) = gen_rtx_USE (VOIDmode,
2278 gen_rtx_REG (Pmode, LINK_REGNUM));
2279 emit_jump_insn (gen_rtx_PARALLEL (VOIDmode, p));
2284 /* Assembly instruction output. */
2286 /* Test whether the given branch instruction is short, or long. Short
2287 * branches are equivalent to real branches, and may be DFA
2288 * scheduled. Long branches expand to a macro which is handled by the
2289 * elaborator, and cannot be scheduled. Occasionally, the branch
2290 * shortening pass, which is run after DFA scheduling, will change the
2291 * code layout and cause the short branch to be reverted into a long
2292 * branch. Instead of having to fix this up by emitting new assembly,
2293 * the short branch is emitted anyway. There is plenty of slack in the
2294 * calculation of long and short branches (10-bit offset, but only
2295 * 9-bits used in computation), so there is enough slack for this to
2298 picochip_is_short_branch (rtx insn)
2300 int isRealShortBranch = (get_attr_length(insn) == SHORT_BRANCH_LENGTH);
2302 return (isRealShortBranch ||
2303 picochip_current_vliw_state.num_insns_in_packet > 1);
2306 /* Output a compare-and-branch instruction (matching the cbranch
2309 picochip_output_cbranch (rtx operands[])
2312 if (HImode != GET_MODE (operands[1]) ||
2313 (HImode != GET_MODE (operands[2]) &&
2314 GET_CODE (operands[2]) != CONST_INT))
2316 internal_error ("%s: at least one operand can%'t be handled",
2320 /* Use the type of comparison to output the appropriate condition
2322 switch (GET_CODE (operands[0]))
2325 return ("// if (%1 != %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPNE %l3");
2328 return ("// if (%1 == %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPEQ %l3");
2331 /* Reverse the operand order to be GE */
2332 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPGE %l3");
2335 /* Reverse operand order of GEU. */
2336 return ("// if (%1 <= %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPHS %l3");
2339 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPGE %l3");
2342 return ("// if (%1 >= %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPHS %l3");
2345 return ("// if (%1 < %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLT %l3");
2348 return ("// if (%1 <{U} %2) goto %l3\n\tSUB.%# %1,%2,r15\n\tJMPLO %l3");
2351 /* Reversed operand version of LT. */
2352 return ("// if (%1 > %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLT %l3");
2355 /* Reverse an LTU. */
2356 return ("// if (%1 >{U} %2) goto %l3\n\tSUB.%# %2,%1,r15\n\tJMPLO %l3");
2363 /* Output a compare-and-branch instruction (matching the cbranch
2364 pattern). This function is current unused since the cbranch
2365 split is disabled. The function is kept around so we can use
2366 it when we understand how to do cbranch split safely. */
2368 picochip_output_compare (rtx operands[])
2372 if (HImode != GET_MODE (operands[1]) ||
2373 (HImode != GET_MODE (operands[2]) &&
2374 GET_CODE (operands[2]) != CONST_INT))
2376 internal_error ("%s: at least one operand can%'t be handled",
2380 code = GET_CODE (operands[0]);
2381 /* Use the type of comparison to output the appropriate condition
2386 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2389 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2392 /* Reverse the operand order to be GE */
2393 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2396 /* Reverse operand order of GEU. */
2397 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2400 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2403 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2406 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2409 return ("SUB.%# %1,%2,r15\t// CC := (%0)");
2412 /* Reversed operand version of LT. */
2413 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2416 /* Reverse an LTU. */
2417 return ("SUB.%# %2,%1,r15\t// CC := (%0)");
2424 /* Output the branch insn part of a compare-and-branch split. */
2426 picochip_output_branch (rtx operands[], rtx insn)
2429 int code = GET_CODE(operands[2]);
2430 if (picochip_is_short_branch (insn))
2432 /* Short branches can be output directly using the
2433 appropriate instruction. */
2437 return ("BNE %l0 %>");
2439 return ("BEQ %l0 %>");
2441 return ("BGE %l0 %>");
2443 return ("BHS %l0 %>");
2445 return ("BGE %l0 %>");
2447 return ("BHS %l0 %>");
2449 return ("BLT %l0 %>");
2451 return ("BLO %l0 %>");
2453 return ("BLT %l0 %>");
2455 return ("BLO %l0 %>");
2457 internal_error ("unknown short branch in %s (type %d)",
2458 __FUNCTION__, (int) INTVAL (operands[1]));
2459 return "UNKNOWN_BRANCH";
2464 /* Long branches result in the emission of a special
2465 instruction, which the assembler expands into a suitable long
2468 /* Use the type of comparison to output the appropriate condition
2473 return ("JMPNE %l0 %>");
2475 return ("JMPEQ %l0 %>");
2477 return ("JMPGE %l0 %>");
2479 return ("JMPHS %l0 %>");
2481 return ("JMPGE %l0 %>");
2483 return ("JMPHS %l0 %>");
2485 return ("JMPLT %l0 %>");
2487 return ("JMPLO %l0 %>");
2489 return ("JMPLT %l0 %>");
2491 return ("JMPLO %l0 %>");
2494 internal_error ("unknown long branch in %s (type %d)",
2495 __FUNCTION__, (int) INTVAL (operands[1]));
2496 return "UNKNOWN_BRANCH";
2502 /* Output a jump instruction. */
2504 picochip_output_jump (rtx insn)
2506 if (picochip_is_short_branch (insn))
2509 return "JMPRA %l0%>";
2513 picochip_output_put_array (int alternative, rtx operands[])
2515 /* Local output buffer. */
2518 int portArraySize = INTVAL(operands[1]);
2519 int portBaseIndex = INTVAL(operands[2]);
2521 if (alternative == 0)
2523 sprintf (buf, "// Array put\n\tadd.0 [lsl %%0,2],&__commTable_put_%d_%d,lr\n\tjl (lr)",
2524 portArraySize, portBaseIndex);
2525 output_asm_insn (buf, operands);
2527 else if (alternative == 1)
2529 /* Constant port id. Emit a real instruction. */
2530 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2531 if (portIndex < portBaseIndex ||
2532 portIndex >= (portBaseIndex + portArraySize))
2534 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2535 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2537 sprintf(buf, "PUT R[0:1],%d", portIndex);
2538 output_asm_insn (buf, operands);
2543 /* Both alternatives output the insn directly. */
2547 const char *picochip_output_get_array (int alternative, rtx operands[])
2549 /* Local output buffer. */
2552 int portArraySize = INTVAL(operands[1]);
2553 int portBaseIndex = INTVAL(operands[2]);
2555 if (alternative == 0)
2557 sprintf (buf, "// Array get\n\tadd.0 [lsl %%0,2],&__commTable_get_%d_%d,lr\n\tjl (lr)",
2558 portArraySize, portBaseIndex);
2559 output_asm_insn (buf, operands);
2561 else if (alternative == 1)
2563 /* Constant port id. Emit a real instruction. */
2564 int portIndex = INTVAL(operands[0]) + portBaseIndex;
2565 if (portIndex < portBaseIndex ||
2566 portIndex >= (portBaseIndex + portArraySize))
2568 error ("GET uses port array index %d, which is out of range [%d..%d)",
2569 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2571 sprintf(buf, "GET %d,R[0:1]", portIndex);
2572 output_asm_insn (buf, operands);
2577 /* Both alternatives output the insn directly. */
2581 const char *picochip_output_testport_array (int alternative, rtx operands[])
2583 /* Local output buffer. */
2586 int portArraySize = INTVAL(operands[2]);
2587 int portBaseIndex = INTVAL(operands[3]);
2589 if (alternative == 0)
2591 sprintf (buf, "// Array tstport\n\tadd.0 [lsl %%1,2],&__commTable_tstport_%d_%d,lr\n\tjl (lr)\n=->\tcopy.0 0,%%0\n\tcopyeq 1,%%0",
2592 portArraySize, portBaseIndex);
2593 output_asm_insn (buf, operands);
2595 else if (alternative == 1)
2597 /* Constant port id. Emit a real instruction. */
2598 int portIndex = INTVAL(operands[1]) + portBaseIndex;
2599 if (portIndex < portBaseIndex ||
2600 portIndex >= (portBaseIndex + portArraySize))
2602 error ("PUT uses port array index %d, which is out of range [%d..%d)",
2603 portIndex, portBaseIndex, portBaseIndex + portArraySize);
2605 sprintf(buf, "copy.1 0,%%0 %%| TSTPORT %d\n\tcopyeq 1,%%0", portIndex);
2606 output_asm_insn (buf, operands);
2611 /* Both alternatives output the insn directly. */
2615 /* Output a comparison operand as a symbol (e.g., >). */
2617 picochip_print_comparison (FILE * file, rtx operand, int letter)
2622 /* Output just the comparison symbol. */
2623 switch (GET_CODE (operand))
2626 fprintf (file, "!=");
2629 fprintf (file, "==");
2632 fprintf (file, ">=");
2635 fprintf (file, ">={U}");
2638 fprintf (file, "<");
2641 fprintf (file, "<{U}");
2644 fprintf (file, "<=");
2647 fprintf (file, "<={U}");
2650 fprintf (file, ">");
2653 fprintf (file, ">{U}");
2661 /* Output the comparison formatted as operand,symbol,operand */
2662 rtx op0 = XEXP (operand, 0);
2663 rtx op1 = XEXP (operand, 1);
2665 picochip_print_operand (file, op0, 0);
2666 picochip_print_comparison (file, operand, 'i');
2667 picochip_print_operand (file, op1, 0);
2671 /* This function generates a memory address operand in the given
2672 mode. That is, if the address contains a constant offset, then the
2673 offset is divided by the required mode size to compute the
2674 mode specific offset. By default, picochip_print_operand_address calls
2675 this function using the natural mode of the operand, but special
2676 operand codes can be used to invoke the computation using an
2677 unnatural mode (e.g., compute the HI aligned address of an SI mode
2680 picochip_print_memory_address (FILE * file, rtx operand,
2681 enum machine_mode mode)
2683 rtx address = XEXP (operand, 0);
2686 if (MEM != GET_CODE (operand))
2687 fatal_insn ("picochip_print_memory_address - Operand isn't memory based",
2692 printf ("picochip_print_memory_address: ");
2693 print_rtl (stdout, operand);
2697 switch (GET_CODE (address))
2701 /* Grab the address components. */
2702 rtx base = XEXP (address, 0);
2703 rtx offset = XEXP (address, 1);
2705 /* Only handle reg+const addresses */
2706 if (REG == GET_CODE (base) && CONST_INT == GET_CODE (offset))
2708 /* Sanity check. If an FP+offset address is given, ensure
2709 that the offset lies within the given frame, or a lower
2711 if (REGNO (base) == STACK_POINTER_REGNUM )
2712 gcc_assert (INTVAL (offset) <= (picochip_arg_area_byte_offset () +
2715 /* Print the base register - identical for all modes. */
2716 fprintf (file, "(");
2717 picochip_print_operand (file, base, 'r');
2718 fprintf (file, ")");
2720 /* Print the constant offset with compensation for the mode. */
2724 picochip_print_operand (file, offset, 'Q');
2728 picochip_print_operand (file, offset, 'H');
2733 picochip_print_operand (file, offset, 'S');
2737 picochip_print_operand (file, offset, 'D');
2751 picochip_print_operand (file, address, 's');
2760 inner = XEXP (address, 0);
2762 /* Sanity check - the CONST memory address must be a base+offset. */
2763 gcc_assert (PLUS == GET_CODE (inner));
2765 base = XEXP (inner, 0);
2766 offset = XEXP (inner, 1);
2768 fprintf (file, "&_%s%+d", XSTR (base, 0), XINT (offset, 0));
2774 /* Register operand. Provide a zero offset. */
2775 fprintf (file, "(");
2776 picochip_print_operand (file, address, 'r');
2777 fprintf (file, ")0");
2786 /* Output an operand. Formatting letters allow particular parts of
2787 the operand to be output. */
2789 picochip_print_operand (FILE * file, rtx operand, int letter)
2792 /* Handle special cases. */
2795 /* VLIW continuation, for explicit VLIW sequences. */
2797 fprintf (file, "\\");
2802 fputc (picochip_get_vliw_alu_id (), file);
2805 /* Delay slot specifier. */
2807 /* This should be handled in asm_output_opcode. */
2810 /* Instruction mnemonics (e.g., lshift becomes LSL). */
2812 switch (GET_CODE (operand))
2815 fprintf (file, "AND");
2818 fprintf (file, "OR");
2821 fprintf (file, "XOR");
2824 fprintf (file, "ADD");
2827 fprintf (file, "SUB");
2834 /* Symbolic instructions (e.g., lshift becomes <<). */
2836 switch (GET_CODE (operand))
2839 fprintf (file, "&");
2842 fprintf (file, "|");
2845 fprintf (file, "^");
2848 fprintf (file, "+");
2851 fprintf (file, "-");
2854 fprintf (file, "UNKNOWN_INSN");
2859 default: /* Not a punctuation character - process as normal. */
2863 switch (GET_CODE (operand))
2869 /* Write a range of registers. */
2870 fprintf (file, "R[%d:%d]", REGNO (operand) + 1, REGNO (operand));
2874 /* The upper register of a pair is requested. */
2875 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 1]);
2879 /* The lower register of a pair is requested. Equivalent to the
2880 default, but included for completeness. */
2881 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2885 /* The 3rd register of a DI mode register. */
2886 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 2]);
2890 /* The 4th register of a DI mode register. */
2891 fprintf (file, "%s", picochip_regnames[REGNO (operand) + 3]);
2895 fprintf (file, "%s", picochip_regnames[REGNO (operand)]);
2900 /* A range of letters can be used to format integers. The
2901 letters Q/H/S are used to divide the constant by the width of
2902 QI/HI/SI mode integers in bytes. The U/L modifiers are used
2903 to obtain the upper and lower 16-bits of a 32-bit
2904 constant. Where possible, signed numbers are used, since
2905 signed representations of numbers may be more compact (e.g.,
2906 65535 can be represented as -1, which fits into a small
2907 constant, whereas 65535 requires a large constant). */
2911 fprintf (file, "%ld", INTVAL (operand));
2915 fprintf (file, "%ld", INTVAL (operand) / 2);
2919 fprintf (file, "%ld", INTVAL (operand) / 4);
2923 fprintf (file, "%d", exact_log2 (INTVAL(operand)));
2927 fprintf (file, "%hi", (short) ((INTVAL (operand) >> 16) & 0xFFFF));
2931 fprintf (file, "%hi", (short) (INTVAL (operand) & 0xFFFF));
2935 fprintf (file, "%ld", INTVAL (operand));
2945 if (GET_MODE (operand) != SFmode)
2946 fatal_insn ("Unknown mode in print_operand (CONST_DOUBLE) :",
2948 REAL_VALUE_FROM_CONST_DOUBLE (rv, operand);
2949 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
2954 fprintf (file, "%hi", (short) ((val >> 16) & 0xFFFF));
2958 fprintf (file, "%hi", (short) (val & 0xFFFF));
2966 /* Output a symbol. The output format must match that of
2967 picochip_output_label. */
2969 /* Ensure that the symbol is marked as referenced. Gcc can
2970 occasionally omit the function bodies when it believes them
2971 to be unreferenced. */
2972 if (SYMBOL_REF_DECL (operand))
2973 mark_decl_referenced (SYMBOL_REF_DECL (operand));
2974 fprintf (file, "&");
2975 assemble_name (file, XSTR (operand, 0));
2979 /* This format must match that of picochip_output_label. */
2980 fprintf (file, "&");
2981 output_asm_label (operand);
2986 rtx addr = XEXP (operand, 0);
2991 if (PLUS != GET_CODE (addr))
2992 fatal_insn ("Bad address, not (reg+disp):", addr);
2994 picochip_print_operand (file, XEXP (addr, 1), 0);
2998 /* Output a memory address in byte mode notation (i.e., the
2999 constant address (if any) is the actual byte address. */
3000 picochip_print_memory_address (file, operand, QImode);
3003 /* Output a constant offset of the given mode (i.e., divide
3004 the constant by the number of units in the mode to get the
3007 picochip_print_memory_address (file, operand, QImode);
3011 picochip_print_memory_address (file, operand, HImode);
3015 picochip_print_memory_address (file, operand, SImode);
3019 picochip_print_memory_address (file, operand, SFmode);
3023 if (PLUS != GET_CODE (addr))
3024 fatal_insn ("Bad address, not (reg+disp):", addr);
3026 picochip_print_operand (file, XEXP (addr, 0), 0);
3029 /* When the mem operand is (reg + big offset) which cannot
3030 be represented in an instruction as operand, the compiler
3031 automatically generates the instruction to put in (reg +
3032 big offset) into another register. In such cases, it
3033 returns '0' as the character. This needs to be handled
3037 if (REG != GET_CODE (addr))
3038 fatal_insn ("Bad address, not register:", addr);
3040 picochip_print_operand (file, addr, 0);
3044 fprintf (file, "Unknown mem operand - letter %c ",
3046 print_rtl (file, operand);
3054 rtx const_exp = XEXP (operand, 0);
3056 /* Handle constant offsets to symbol references. */
3057 if (PLUS == GET_CODE (const_exp) &&
3058 SYMBOL_REF == GET_CODE (XEXP (const_exp, 0)) &&
3059 CONST_INT == GET_CODE (XEXP (const_exp, 1)))
3062 picochip_print_operand (file, XEXP (const_exp, 0), 0);
3063 if (INTVAL (XEXP (const_exp, 1)) >= 0)
3064 fprintf (file, "+");
3065 /* else use the - from the operand (i.e., AP-2)) */
3067 picochip_print_operand (file, XEXP (const_exp, 1), letter);
3076 /* PLUS expressions are of the form (base + offset). Different
3077 options (analagous to those of memory PLUS expressions) are used
3078 to extract the base and offset components. */
3083 picochip_print_operand (file, XEXP (operand, 0), 0);
3087 picochip_print_operand (file, XEXP (operand, 1), 0);
3092 /* If the expression is composed entirely of constants,
3093 evaluate the result. This should only occur with the
3094 picoChip specific comms instructions, which are emitted as
3095 base+offset expressions. */
3096 if (CONST_INT == GET_CODE (XEXP (operand, 0)) &&
3097 CONST_INT == GET_CODE (XEXP (operand, 1)))
3099 HOST_WIDE_INT result = (XINT (XEXP (operand, 0), 0) +
3100 XINT (XEXP (operand, 1), 0));
3101 fprintf (file, "%ld", result);
3105 fprintf (file, "(");
3106 picochip_print_operand (file, XEXP (operand, 0), 0);
3107 fprintf (file, "+");
3108 picochip_print_operand (file, XEXP (operand, 1), 0);
3109 fprintf (file, ")");
3116 /* Comparison operations. */
3127 picochip_print_comparison (file, operand, letter);
3131 fprintf (stderr, "Unknown operand encountered in %s\n", __FUNCTION__);
3132 print_rtl (file, operand);
3139 /* Output an operand address */
3141 picochip_print_operand_address (FILE * file, rtx operand)
3144 switch (GET_CODE (operand))
3148 /* This format must match that of picochip_output_label. */
3149 assemble_name (file, XSTR (operand, 0));
3153 /* Note this format must match that of picochip_output_label. */
3154 fprintf (file, "_L%d", XINT (operand, 5));
3158 /* Pass on to a specialised memory address generator. */
3159 picochip_print_memory_address (file, operand, GET_MODE (operand));
3170 /* Scheduling functions. */
3172 /* Save some of the contents of recog_data. */
3174 picochip_save_recog_data (void)
3176 picochip_saved_which_alternative = which_alternative;
3177 memcpy (&picochip_saved_recog_data, &recog_data,
3178 sizeof (struct recog_data));
3181 /* Restore some of the contents of global variable recog_data. */
3183 picochip_restore_recog_data (void)
3185 which_alternative = picochip_saved_which_alternative;
3186 memcpy (&recog_data, &picochip_saved_recog_data,
3187 sizeof (struct recog_data));
3190 /* Ensure that no var tracking notes are emitted in the middle of a
3191 three-instruction bundle. */
3193 reorder_var_tracking_notes (void)
3199 rtx insn, next, last_insn = NULL_RTX;
3200 rtx queue = NULL_RTX;
3202 /* Iterate through the bb and find the last non-debug insn */
3203 for (insn = BB_HEAD (bb); insn != NEXT_INSN(BB_END (bb)); insn = NEXT_INSN(insn))
3205 if (NONDEBUG_INSN_P(insn))
3209 /* In all normal cases, queue up notes and emit them just before a TImode
3210 instruction. For the last instruction, emit the queued notes just after
3211 the last instruction. */
3212 for (insn = BB_HEAD (bb); insn != NEXT_INSN(BB_END (bb)); insn = next)
3214 next = NEXT_INSN (insn);
3216 if (insn == last_insn)
3220 rtx next_queue = PREV_INSN (queue);
3221 PREV_INSN (NEXT_INSN(insn)) = queue;
3222 NEXT_INSN(queue) = NEXT_INSN(insn);
3223 PREV_INSN(queue) = insn;
3224 NEXT_INSN(insn) = queue;
3227 /* There is no more to do for this bb. break*/
3230 else if (NONDEBUG_INSN_P (insn))
3232 /* Emit queued up notes before the first instruction of a bundle. */
3233 if (GET_MODE (insn) == TImode)
3237 rtx next_queue = PREV_INSN (queue);
3238 NEXT_INSN (PREV_INSN(insn)) = queue;
3239 PREV_INSN (queue) = PREV_INSN(insn);
3240 PREV_INSN (insn) = queue;
3241 NEXT_INSN (queue) = insn;
3246 else if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_VAR_LOCATION)
3248 rtx prev = PREV_INSN (insn);
3249 PREV_INSN (next) = prev;
3250 NEXT_INSN (prev) = next;
3251 PREV_INSN (insn) = queue;
3255 /* Make sure we are not dropping debug instructions.*/
3256 gcc_assert (queue == NULL_RTX);
3260 /* Perform machine dependent operations on the rtl chain INSNS. */
3262 picochip_reorg (void)
3264 rtx insn, insn1, vliw_start = NULL_RTX;
3265 int vliw_insn_location = 0;
3267 /* We are freeing block_for_insn in the toplev to keep compatibility
3268 with old MDEP_REORGS that are not CFG based. Recompute it now. */
3269 compute_bb_for_insn ();
3274 if (picochip_schedule_type != DFA_TYPE_NONE)
3276 timevar_push (TV_SCHED2);
3278 /* Process the instruction list, computing the sizes of each
3279 instruction, and consequently branch distances. This can
3280 result in some branches becoming short enough to be treated
3281 as a real branch instruction, rather than an assembly branch
3282 macro which may expand into multiple instructions. The
3283 benefit of shortening branches is that real branch
3284 instructions can be properly DFA scheduled, whereas macro
3286 shorten_branches (get_insns ());
3288 /* Do control and data sched analysis again,
3289 and write some more of the results to dump file. */
3295 timevar_pop (TV_SCHED2);
3299 if (picochip_schedule_type == DFA_TYPE_SPEED)
3301 /* Whenever a VLIW packet is generated, all instructions in
3302 that packet must appear to come from the same source
3303 location. The following code finds all the VLIW packets,
3304 and tags their instructions with the location of the first
3305 instruction from the packet. Clearly this will result in
3306 strange behaviour when debugging the code, but since
3307 debugging and optimisation are being used in conjunction,
3308 strange behaviour is certain to occur anyway. */
3309 /* Slight bit of change. If the vliw set contains a branch
3310 or call instruction, we pick its location.*/
3311 for (insn = get_insns (); insn; insn = next_real_insn (insn))
3314 /* If this is the first instruction in the VLIW packet,
3315 extract its location. */
3316 if (GET_MODE (insn) == TImode)
3319 vliw_insn_location = INSN_LOCATOR (insn);
3321 if (JUMP_P (insn) || CALL_P(insn))
3323 vliw_insn_location = INSN_LOCATOR (insn);
3324 for (insn1 = vliw_start; insn1 != insn ; insn1 = next_real_insn (insn1))
3325 INSN_LOCATOR (insn1) = vliw_insn_location;
3327 /* Tag subsequent instructions with the same location. */
3328 INSN_LOCATOR (insn) = vliw_insn_location;
3334 /* Locate the note marking the end of the function's prologue. If
3335 the note appears in the middle of a VLIW packet, move the note to
3336 the end. This avoids unpleasant consequences such as trying to
3337 emit prologue markers (e.g., .loc/.file directives) in the middle
3339 if (picochip_schedule_type == DFA_TYPE_SPEED)
3341 rtx prologue_end_note = NULL;
3342 rtx last_insn_in_packet = NULL;
3344 for (insn = get_insns (); insn; insn = next_insn (insn))
3346 /* The prologue end must be moved to the end of the VLIW packet. */
3347 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_PROLOGUE_END)
3349 prologue_end_note = insn;
3354 /* Find the last instruction in this packet. */
3355 for (insn = prologue_end_note; insn; insn = next_real_insn (insn))
3357 if (GET_MODE (insn) == TImode)
3360 last_insn_in_packet = insn;
3363 if (last_insn_in_packet != NULL)
3366 = emit_note_after ((enum insn_note) NOTE_KIND (prologue_end_note),
3367 last_insn_in_packet);
3368 memcpy(&NOTE_DATA (tmp_note), &NOTE_DATA(prologue_end_note), sizeof(NOTE_DATA(prologue_end_note)));
3369 delete_insn (prologue_end_note);
3372 if (picochip_flag_var_tracking)
3374 timevar_push (TV_VAR_TRACKING);
3375 variable_tracking_main ();
3376 /* We also have to deal with variable tracking notes in the middle
3378 reorder_var_tracking_notes();
3379 timevar_pop (TV_VAR_TRACKING);
3383 /* Return the ALU character identifier for the current
3384 instruction. This will be 0 or 1. */
3386 picochip_get_vliw_alu_id (void)
3390 /* Always use ALU 0 if VLIW scheduling is disabled. */
3391 if (picochip_schedule_type != DFA_TYPE_SPEED)
3394 /* Get the attribute type of the instruction. Note that this can
3395 ruin the contents of recog_data, so save/restore around the
3397 picochip_save_recog_data ();
3398 attr_type = get_attr_type (picochip_current_prescan_insn);
3399 picochip_restore_recog_data ();
3401 if (picochip_current_vliw_state.contains_pico_alu_insn)
3404 /* If this a picoAlu insn? If it is, then stuff it into ALU 0,
3405 else it must be the other ALU (either basic or nonCc)
3406 instruction which goes into 1. */
3407 if (attr_type == TYPE_PICOALU)
3413 else if (picochip_current_vliw_state.contains_non_cc_alu_insn)
3415 /* Is this the non CC instruction? If it is, then stuff it into
3416 ALU 1, else it must be a picoAlu or basicAlu, in which case
3417 it goes into ALU 0. */
3418 if (attr_type == TYPE_NONCCALU)
3425 /* No picoAlu/nonCc instructions in use, so purely dependent upon
3426 whether an ALU instruction has already been scheduled in this
3428 switch (picochip_current_vliw_state.num_alu_insns_so_far)
3431 picochip_current_vliw_state.num_alu_insns_so_far++;
3435 picochip_current_vliw_state.num_alu_insns_so_far++;
3439 internal_error ("too many ALU instructions emitted (%d)",
3440 picochip_current_vliw_state.num_alu_insns_so_far);
3447 /* Reset any information about the current VLIW packing status. */
3449 picochip_reset_vliw (rtx insn)
3451 rtx local_insn = insn;
3453 /* Nothing to do if VLIW scheduling isn't being used. */
3454 if (picochip_schedule_type != DFA_TYPE_SPEED)
3458 printf ("%s on insn %d\n", __FUNCTION__, INSN_UID (insn));
3461 picochip_current_vliw_state.contains_pico_alu_insn = 0;
3462 picochip_current_vliw_state.contains_non_cc_alu_insn = 0;
3463 picochip_current_vliw_state.num_alu_insns_so_far = 0;
3464 picochip_current_vliw_state.num_cfi_labels_deferred = 0;
3465 picochip_current_vliw_state.lm_label_name[0] = 0;
3466 picochip_current_vliw_state.num_insns_in_packet = 0;
3468 /* Read through the VLIW packet, classifying the instructions where
3473 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3475 local_insn = NEXT_INSN (local_insn);
3478 else if (!INSN_P (local_insn))
3482 /* It is an instruction, but is it ours? */
3483 if (INSN_CODE (local_insn) != -1)
3487 picochip_current_vliw_state.num_insns_in_packet += 1;
3489 /* Is it a picoAlu or nonCcAlu instruction? Note that the
3490 get_attr_type function can overwrite the values in
3491 the recog_data global, hence this is saved and
3492 restored around the call. Not doing so results in
3493 asm_output_opcode being called with a different
3494 instruction to final_prescan_insn, which is fatal. */
3495 picochip_save_recog_data ();
3496 attr_type = get_attr_type (local_insn);
3497 picochip_restore_recog_data ();
3499 if (attr_type == TYPE_PICOALU)
3500 picochip_current_vliw_state.contains_pico_alu_insn = 1;
3501 if (attr_type == TYPE_NONCCALU)
3502 picochip_current_vliw_state.contains_non_cc_alu_insn = 1;
3507 /* Get the next instruction. */
3508 local_insn = NEXT_INSN (local_insn);
3510 /* Keep going while the next instruction is part of the same
3511 VLIW packet (i.e., its a valid instruction and doesn't mark
3512 the start of a new VLIW packet. */
3514 while (local_insn &&
3515 (GET_MODE (local_insn) != TImode) && (INSN_CODE (local_insn) != -1));
3520 picochip_sched_reorder (FILE * file, int verbose,
3521 rtx * ready ATTRIBUTE_UNUSED,
3522 int *n_readyp ATTRIBUTE_UNUSED, int clock)
3526 fprintf (file, ";;\tClock %d\n", clock);
3528 return picochip_sched_issue_rate ();
3533 picochip_sched_lookahead (void)
3535 /* It should always be enough to lookahead by 2 insns. Only slot0/1 could
3541 picochip_sched_issue_rate (void)
3546 /* Adjust the scheduling cost between the two given instructions,
3547 which have the given dependency. */
3549 picochip_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
3554 printf ("Sched Adjust Cost: %d->%d is %d\n",
3555 INSN_UID (insn), INSN_UID (dep_insn), cost);
3557 printf (" Dependency type:");
3558 switch (REG_NOTE_KIND (link))
3566 case REG_DEP_OUTPUT:
3567 printf ("OUTPUT\n");
3570 printf ("Unknown (%d)\n", REG_NOTE_KIND (link));
3574 /* Anti-dependencies are used to enforce the ordering between a
3575 * branch, and any subsequent instructions. For example:
3580 * The ADD instruction must execute after the branch, and this is
3581 * enforced using an anti-dependency. Unfortunately, VLIW machines
3582 * are happy to execute anti-dependent instructions in the same
3583 * cycle, which then results in a schedule like the following being
3586 * BNE someLabel \ ADD.0 r0,r1,r2
3588 * The instruction which would normally be conditionally executed
3589 * depending upon the outcome of the branch, is now unconditionally
3590 * executed every time. To prevent this happening, any
3591 * anti-dependencies between a branch and another instruction are
3592 * promoted to become real dependencies.
3594 if ((JUMP_P (dep_insn) || CALL_P(dep_insn)) && REG_NOTE_KIND (link) == REG_DEP_ANTI)
3598 printf ("Promoting anti-dependency %d->%d to a true-dependency\n",
3599 INSN_UID (insn), INSN_UID (dep_insn));
3608 /* Return the minimum of the two values */
3610 minimum (int a, int b)
3616 /* I dont expect to get to this function with a==b.*/
3621 /* This function checks if the memory of the two stores are just off by 2 bytes.
3622 It returns the lower memory operand's index.*/
3625 memory_just_off (rtx opnd1, rtx opnd2)
3627 int offset1 = 0, offset2 = 0;
3630 if (GET_CODE(XEXP(opnd1, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1, 0),1)) == CONST_INT)
3632 offset1 = INTVAL(XEXP(XEXP(opnd1, 0), 1));
3633 reg1 = REGNO(XEXP(XEXP(opnd1, 0), 0));
3637 reg1 = REGNO(XEXP(opnd1, 0));
3639 if (GET_CODE(XEXP(opnd2, 0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2, 0), 1)) == CONST_INT)
3641 offset2 = INTVAL(XEXP(XEXP(opnd2, 0), 1));
3642 reg2 = REGNO(XEXP(XEXP(opnd2, 0), 0));
3646 reg2 = REGNO(XEXP(opnd2, 0));
3649 /* Peepholing 2 STW/LDWs has the restriction that the resulting STL/LDL's address
3650 should be 4 byte aligned. We can currently guarentee that only if the base
3651 address is FP(R13) and the offset is aligned. */
3653 if (reg1 == reg2 && reg1 == 13 && abs(offset1-offset2) == 2 && minimum(offset1, offset2) % 4 == 0)
3654 return (minimum(offset1, offset2) == offset1) ? 1:2;
3660 registers_just_off (rtx opnd1, rtx opnd2)
3663 reg1 = REGNO(opnd1);
3664 reg2 = REGNO(opnd2);
3665 if (abs(reg1-reg2) == 1 && minimum(reg1, reg2) % 2 == 0)
3666 return (minimum(reg1, reg2) == reg1)?1:2;
3670 /* Check to see if the two LDWs can be peepholed together into a LDL
3671 They can be if the registers getting loaded into are contiguous
3672 and the memory addresses are contiguous as well.
3676 can be merged together into
3680 1. The LDWs themselves only guarentee that r11 will be a 2-byte
3681 aligned address. Only FP can be assumed to be 4 byte aligned.
3682 2. The progression of addresses and the register numbers should
3683 be similar. For eg., if you swap r2 and r3 in the above instructions,
3684 the resultant pair cannot be merged.
3688 ok_to_peephole_ldw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3690 int memtest=0,regtest=0;
3691 regtest = registers_just_off(opnd1,opnd3);
3695 memtest = memory_just_off(opnd0,opnd2);
3699 if (regtest == memtest)
3706 /* Similar to LDW peephole */
3708 ok_to_peephole_stw(rtx opnd0, rtx opnd1, rtx opnd2, rtx opnd3)
3710 int memtest=0,regtest=0;
3711 regtest = registers_just_off(opnd1,opnd3);
3715 memtest = memory_just_off(opnd0,opnd2);
3719 if (regtest == memtest)
3727 /* Generate a SImode register with the register number that is the smaller of the two */
3729 gen_min_reg(rtx opnd1,rtx opnd2)
3731 return gen_rtx_REG (SImode, minimum(REGNO(opnd1),REGNO(opnd2)));
3734 /* Generate a SImode memory with the address that is the smaller of the two */
3736 gen_SImode_mem(rtx opnd1,rtx opnd2)
3738 int offset1=0,offset2=0;
3741 if (GET_CODE(XEXP(opnd1,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd1,0),1)) == CONST_INT)
3743 offset1 = INTVAL(XEXP(XEXP(opnd1,0),1));
3744 reg = XEXP(XEXP(opnd1,0),0);
3748 reg = XEXP(opnd1,0);
3750 if (GET_CODE(XEXP(opnd2,0)) == PLUS && GET_CODE(XEXP(XEXP(opnd2,0),1)) == CONST_INT)
3752 offset2 = INTVAL(XEXP(XEXP(opnd2,0),1));
3754 address = gen_rtx_PLUS (HImode, reg, GEN_INT(minimum(offset1,offset2)));
3755 return gen_rtx_MEM(SImode,address);
3759 picochip_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, int* total, bool speed)
3766 /* Need to penalize immediates that need to be encoded as long constants.*/
3767 if (code == CONST_INT && !(INTVAL (x) >= 0 && INTVAL (x) < 16))
3769 *total = COSTS_N_INSNS(1);
3777 *total = COSTS_N_INSNS (outer_code != MEM);
3782 /* if_then_else come out of cbranch instructions. It will get split into
3783 a condition code generating subtraction and a branch */
3784 *total = COSTS_N_INSNS (2);
3791 if (GET_MODE(x) == SImode)
3792 *total = COSTS_N_INSNS (2);
3793 if (GET_MODE(x) == DImode)
3794 *total = COSTS_N_INSNS (4);
3798 /* Byte Memory access on a NO_BYTE_ACCESS machine would be expensive */
3799 if (GET_MODE(x) == QImode && !TARGET_HAS_BYTE_ACCESS)
3800 *total = COSTS_N_INSNS (10);
3802 /* 64-bit accesses have to be done through 2 32-bit access */
3803 if (GET_MODE(x) == DImode)
3804 *total = COSTS_N_INSNS (2);
3810 /* SImode shifts are expensive */
3811 if (GET_MODE(x) == SImode)
3812 *total = COSTS_N_INSNS (10);
3814 /* Register shift by constant is cheap. */
3815 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3816 && GET_CODE(XEXP(x, 0)) == REG
3817 && GET_CODE(XEXP(x, 1)) == CONST_INT)
3818 *total = COSTS_N_INSNS (1);
3820 *total = COSTS_N_INSNS (4);
3827 /* Divisions are more expensive than the default 7*/
3828 if (GET_MODE(x) == SImode)
3829 *total = COSTS_N_INSNS (20);
3831 *total = COSTS_N_INSNS (12);
3836 /* Look for the simple cases of multiplying register*register or
3837 register*constant. */
3838 if ((GET_MODE(x) == QImode || GET_MODE(x) == HImode)
3839 && ((GET_CODE(XEXP(x, 0)) == REG
3840 && (GET_CODE(XEXP(x, 1)) == REG || GET_CODE(XEXP(x,1)) == CONST_INT))
3841 || (GET_CODE(XEXP(x, 0)) == ZERO_EXTEND
3842 && GET_CODE(XEXP(XEXP(x, 0),0)) == REG
3843 && GET_CODE(XEXP(x, 1)) == ZERO_EXTEND
3844 && GET_CODE(XEXP(XEXP(x, 1),0)) == REG)))
3847 /* When optimising for size, multiplication by constant
3848 should be discouraged slightly over multiplication by a
3850 if (picochip_has_mac_unit)
3852 /* Single cycle multiplication, but the result must be
3853 loaded back into a general register afterwards. */
3854 *total = COSTS_N_INSNS(2);
3857 else if (picochip_has_mul_unit)
3859 /* Single cycle multiplication. */
3860 *total = COSTS_N_INSNS(1);
3863 /* Else no multiply available. Use default cost. */
3873 if (localTotal != 0)
3875 *total = localTotal;
3886 picochip_final_prescan_insn (rtx insn, rtx * opvec ATTRIBUTE_UNUSED,
3887 int num_operands ATTRIBUTE_UNUSED)
3891 picochip_current_prescan_insn = insn;
3894 printf ("Final prescan on INSN %d with mode %s\n",
3895 INSN_UID (insn), GET_MODE_NAME (GET_MODE (insn)));
3897 /* If this is the start of a new instruction cycle, or no scheduling
3898 is used, then reset the VLIW status. */
3899 if (GET_MODE (insn) == TImode || !picochip_schedule_type == DFA_TYPE_SPEED)
3900 picochip_reset_vliw (insn);
3902 /* No VLIW scheduling occured, so don't go any further. */
3903 if (picochip_schedule_type != DFA_TYPE_SPEED)
3906 /* Look for the next printable instruction. This loop terminates on
3907 any recognisable instruction, and on any unrecognisable
3908 instruction with TImode. */
3910 for (local_insn = NEXT_INSN (local_insn); local_insn;
3911 local_insn = NEXT_INSN (local_insn))
3913 if (NOTE_P (local_insn) || DEBUG_INSN_P(local_insn))
3915 else if (!INSN_P (local_insn))
3917 else if (GET_MODE (local_insn) == TImode
3918 || INSN_CODE (local_insn) != -1)
3922 /* Set the continuation flag if the next instruction can be packed
3923 with the current instruction (i.e., the next instruction is
3924 valid, and isn't the start of a new cycle). */
3925 picochip_vliw_continuation = (local_insn && NONDEBUG_INSN_P (local_insn) &&
3926 (GET_MODE (local_insn) != TImode));
3930 /* Builtin functions. */
3931 /* Given a builtin function taking 2 operands (i.e., target + source),
3932 emit the RTL for the underlying instruction. */
3934 picochip_expand_builtin_2op (enum insn_code icode, tree call, rtx target)
3938 enum machine_mode tmode, mode0;
3940 /* Grab the incoming argument and emit its RTL. */
3941 arg0 = CALL_EXPR_ARG (call, 0);
3942 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3944 /* Determine the modes of the instruction operands. */
3945 tmode = insn_data[icode].operand[0].mode;
3946 mode0 = insn_data[icode].operand[1].mode;
3948 /* Ensure that the incoming argument RTL is in a register of the
3950 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3951 op0 = copy_to_mode_reg (mode0, op0);
3953 /* If there isn't a suitable target, emit a target register. */
3955 || GET_MODE (target) != tmode
3956 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
3957 target = gen_reg_rtx (tmode);
3959 /* Emit and return the new instruction. */
3960 pat = GEN_FCN (icode) (target, op0);
3969 /* Given a builtin function taking 3 operands (i.e., target + two
3970 source), emit the RTL for the underlying instruction. */
3972 picochip_expand_builtin_3op (enum insn_code icode, tree call, rtx target)
3976 enum machine_mode tmode, mode0, mode1;
3978 /* Grab the function's arguments. */
3979 arg0 = CALL_EXPR_ARG (call, 0);
3980 arg1 = CALL_EXPR_ARG (call, 1);
3982 /* Emit rtl sequences for the function arguments. */
3983 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3984 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
3986 /* Get the mode's of each of the instruction operands. */
3987 tmode = insn_data[icode].operand[0].mode;
3988 mode0 = insn_data[icode].operand[1].mode;
3989 mode1 = insn_data[icode].operand[2].mode;
3991 /* Ensure that each of the function argument rtl sequences are in a
3992 register of the correct mode. */
3993 if (!(*insn_data[icode].operand[1].predicate) (op0, mode0))
3994 op0 = copy_to_mode_reg (mode0, op0);
3995 if (!(*insn_data[icode].operand[2].predicate) (op1, mode1))
3996 op1 = copy_to_mode_reg (mode1, op1);
3998 /* If no target has been given, create a register to use as the target. */
4000 || GET_MODE (target) != tmode
4001 || !(*insn_data[icode].operand[0].predicate) (target, tmode))
4002 target = gen_reg_rtx (tmode);
4004 /* Emit and return the new instruction. */
4005 pat = GEN_FCN (icode) (target, op0, op1);
4014 /* Expand a builtin function which takes two arguments, and returns a void. */
4016 picochip_expand_builtin_2opvoid (enum insn_code icode, tree call)
4020 enum machine_mode mode0, mode1;
4022 /* Grab the function's arguments. */
4023 arg0 = CALL_EXPR_ARG (call, 0);
4024 arg1 = CALL_EXPR_ARG (call, 1);
4026 /* Emit rtl sequences for the function arguments. */
4027 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4028 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4030 /* Get the mode's of each of the instruction operands. */
4031 mode0 = insn_data[icode].operand[0].mode;
4032 mode1 = insn_data[icode].operand[1].mode;
4034 /* Ensure that each of the function argument rtl sequences are in a
4035 register of the correct mode. */
4036 if (!(*insn_data[icode].operand[0].predicate) (op0, mode0))
4037 op0 = copy_to_mode_reg (mode0, op0);
4038 if (!(*insn_data[icode].operand[1].predicate) (op1, mode1))
4039 op1 = copy_to_mode_reg (mode1, op1);
4041 /* Emit and return the new instruction. */
4042 pat = GEN_FCN (icode) (op0, op1);
4051 /* Expand an array get into the corresponding RTL. */
4053 picochip_expand_array_get (tree call, rtx target)
4055 tree arg0, arg1, arg2;
4056 rtx op0, op1, op2, pat;
4058 /* Grab the function's arguments. */
4059 arg0 = CALL_EXPR_ARG (call, 0);
4060 arg1 = CALL_EXPR_ARG (call, 1);
4061 arg2 = CALL_EXPR_ARG (call, 2) ;
4063 /* Emit rtl sequences for the function arguments. */
4064 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4065 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4066 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4068 /* The second and third operands must be constant. Nothing else will
4070 if (CONST_INT != GET_CODE (op1))
4071 internal_error ("%s: Second source operand is not a constant",
4073 if (CONST_INT != GET_CODE (op2))
4074 internal_error ("%s: Third source operand is not a constant",
4077 /* If no target has been given, create a register to use as the target. */
4078 if (target == 0 || GET_MODE (target) != SImode)
4079 target = gen_reg_rtx (SImode);
4081 /* The first operand must be a HImode register or a constant. If it
4082 isn't, force it into a HImode register. */
4083 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
4084 op0 = copy_to_mode_reg (HImode, op0);
4087 /* Emit and return the new instruction. */
4088 pat = gen_commsArrayGet (target, op0, op1, op2);
4095 /* Expand an array put into the corresponding RTL. */
4097 picochip_expand_array_put (tree call, rtx target)
4099 tree arg0, arg1, arg2, arg3;
4100 rtx op0, op1, op2, op3, pat;
4102 /* Grab the function's arguments. */
4103 arg0 = CALL_EXPR_ARG (call, 0);
4104 arg1 = CALL_EXPR_ARG (call, 1);
4105 arg2 = CALL_EXPR_ARG (call, 2);
4106 arg3 = CALL_EXPR_ARG (call, 3);
4108 /* Emit rtl sequences for the function arguments. */
4109 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4110 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4111 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4112 op3 = expand_expr (arg3, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4114 /* The first operand must be an SImode register. */
4115 if (GET_MODE (op0) != SImode || REG != GET_CODE (op0))
4116 op0 = copy_to_mode_reg (SImode, op0);
4118 /* The second (index) operand must be a HImode register, or a
4119 constant. If it isn't, force it into a HImode register. */
4120 if (GET_MODE (op1) != HImode || REG != GET_CODE (op1))
4121 op1 = copy_to_mode_reg (HImode, op1);
4123 /* The remaining operands must be constant. Nothing else will do. */
4124 if (CONST_INT != GET_CODE (op2))
4125 internal_error ("%s: Third source operand is not a constant",
4127 if (CONST_INT != GET_CODE (op3))
4128 internal_error ("%s: Fourth source operand is not a constant",
4131 /* Emit and return the new instruction. */
4132 pat = gen_commsArrayPut (op0, op1, op2, op3);
4139 /* Expand an array testport into the corresponding RTL. */
4141 picochip_expand_array_testport (tree call, rtx target)
4143 tree arg0, arg1, arg2;
4144 rtx op0, op1, op2, pat;
4146 /* Grab the function's arguments. */
4147 arg0 = CALL_EXPR_ARG (call, 0);
4148 arg1 = CALL_EXPR_ARG (call, 1);
4149 arg2 = CALL_EXPR_ARG (call, 2);
4151 /* Emit rtl sequences for the function arguments. */
4152 op0 = expand_expr (arg0, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4153 op1 = expand_expr (arg1, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4154 op2 = expand_expr (arg2, NULL_RTX, VOIDmode, EXPAND_NORMAL);
4156 /* The first operand must be a HImode register, or a constant. If it
4157 isn't, force it into a HImode register. */
4158 if (GET_MODE (op0) != HImode || REG != GET_CODE (op0))
4159 op0 = copy_to_mode_reg (HImode, op0);
4161 /* The second and third operands must be constant. Nothing else will
4163 if (CONST_INT != GET_CODE (op1))
4164 internal_error ("%s: Second source operand is not a constant",
4166 if (CONST_INT != GET_CODE (op2))
4167 internal_error ("%s: Third source operand is not a constant",
4170 /* If no target has been given, create a HImode register to use as
4172 if (target == 0 || GET_MODE (target) != HImode)
4173 target = gen_reg_rtx (HImode);
4175 /* Emit and return the new instruction. */
4176 pat = gen_commsArrayTestPort (target, op0, op1, op2);
4183 /* Generate a unique HALT instruction by giving the instruction a
4184 unique integer. This integer makes no difference to the assembly
4185 output (other than a comment indicating the supplied id), but the
4186 presence of the unique integer prevents the compiler from combining
4187 several different halt instructions into one instruction. This
4188 means that each use of the halt instruction is unique, which in
4189 turn means that assertions work as expected. */
4191 picochip_generate_halt (void)
4193 static int currentId = 0;
4195 rtx id = GEN_INT (currentId);
4199 emit_insn (gen_halt (id));
4201 /* A barrier is inserted to prevent the compiler from thinking that
4202 it has to continue execution after the HALT.*/
4205 insns = get_insns();
4212 /* Initialise the builtin functions. Start by initialising
4213 descriptions of different types of functions (e.g., void fn(int),
4214 int fn(void)), and then use these to define the builtins. */
4216 picochip_init_builtins (void)
4219 tree endlink = void_list_node;
4220 tree int_endlink = tree_cons (NULL_TREE, integer_type_node, endlink);
4221 tree unsigned_endlink = tree_cons (NULL_TREE, unsigned_type_node, endlink);
4222 tree long_endlink = tree_cons (NULL_TREE, long_integer_type_node, endlink);
4223 tree int_int_endlink =
4224 tree_cons (NULL_TREE, integer_type_node, int_endlink);
4225 tree int_int_int_endlink =
4226 tree_cons (NULL_TREE, integer_type_node, int_int_endlink);
4227 tree int_long_endlink =
4228 tree_cons (NULL_TREE, integer_type_node, long_endlink);
4229 tree long_int_int_int_endlink =
4230 tree_cons (NULL_TREE, long_integer_type_node, int_int_int_endlink);
4232 tree int_ftype_int, int_ftype_int_int;
4233 tree long_ftype_int, long_ftype_int_int_int;
4234 tree void_ftype_int_long, int_ftype_int_int_int,
4235 void_ftype_long_int_int_int;
4236 tree void_ftype_void, unsigned_ftype_unsigned;
4238 /* void func (void) */
4239 void_ftype_void = build_function_type (void_type_node, endlink);
4241 /* int func (int) */
4242 int_ftype_int = build_function_type (integer_type_node, int_endlink);
4244 /* unsigned int func (unsigned int) */
4245 unsigned_ftype_unsigned = build_function_type (unsigned_type_node, unsigned_endlink);
4247 /* int func(int, int) */
4249 = build_function_type (integer_type_node, int_int_endlink);
4251 /* long func(int) */
4252 long_ftype_int = build_function_type (long_integer_type_node, int_endlink);
4254 /* long func(int, int, int) */
4255 long_ftype_int_int_int
4256 = build_function_type (long_integer_type_node, int_int_int_endlink);
4258 /* int func(int, int, int) */
4259 int_ftype_int_int_int
4260 = build_function_type (integer_type_node, int_int_int_endlink);
4262 /* void func(int, long) */
4264 = build_function_type (void_type_node, int_long_endlink);
4266 /* void func(long, int, int, int) */
4267 void_ftype_long_int_int_int
4268 = build_function_type (void_type_node, long_int_int_int_endlink);
4270 /* Initialise the sign-bit-count function. */
4271 add_builtin_function ("__builtin_sbc", int_ftype_int,
4272 PICOCHIP_BUILTIN_SBC, BUILT_IN_MD, NULL,
4274 add_builtin_function ("picoSbc", int_ftype_int, PICOCHIP_BUILTIN_SBC,
4275 BUILT_IN_MD, NULL, NULL_TREE);
4277 /* Initialise the bit reverse function. */
4278 add_builtin_function ("__builtin_brev", unsigned_ftype_unsigned,
4279 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4281 add_builtin_function ("picoBrev", unsigned_ftype_unsigned,
4282 PICOCHIP_BUILTIN_BREV, BUILT_IN_MD, NULL,
4285 /* Initialise the byte swap function. */
4286 add_builtin_function ("__builtin_byteswap", unsigned_ftype_unsigned,
4287 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4289 add_builtin_function ("picoByteSwap", unsigned_ftype_unsigned,
4290 PICOCHIP_BUILTIN_BYTESWAP, BUILT_IN_MD, NULL,
4293 /* Initialise the ASRI function (note that while this can be coded
4294 using a signed shift in C, extra scratch registers are required,
4295 which we avoid by having a direct builtin to map to the
4297 add_builtin_function ("__builtin_asri", int_ftype_int_int,
4298 PICOCHIP_BUILTIN_ASRI, BUILT_IN_MD, NULL,
4301 /* Initialise saturating addition. */
4302 add_builtin_function ("__builtin_adds", int_ftype_int_int,
4303 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4305 add_builtin_function ("picoAdds", int_ftype_int_int,
4306 PICOCHIP_BUILTIN_ADDS, BUILT_IN_MD, NULL,
4309 /* Initialise saturating subtraction. */
4310 add_builtin_function ("__builtin_subs", int_ftype_int_int,
4311 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4313 add_builtin_function ("picoSubs", int_ftype_int_int,
4314 PICOCHIP_BUILTIN_SUBS, BUILT_IN_MD, NULL,
4317 /* Scalar comms builtins. */
4318 add_builtin_function ("__builtin_get", long_ftype_int,
4319 PICOCHIP_BUILTIN_GET, BUILT_IN_MD, NULL,
4321 add_builtin_function ("__builtin_put", void_ftype_int_long,
4322 PICOCHIP_BUILTIN_PUT, BUILT_IN_MD, NULL,
4324 add_builtin_function ("__builtin_testport", int_ftype_int,
4325 PICOCHIP_BUILTIN_TESTPORT, BUILT_IN_MD, NULL,
4328 /* Array comms builtins. */
4329 add_builtin_function ("__builtin_put_array",
4330 void_ftype_long_int_int_int,
4331 PICOCHIP_BUILTIN_PUT_ARRAY, BUILT_IN_MD, NULL,
4333 add_builtin_function ("__builtin_get_array", long_ftype_int_int_int,
4334 PICOCHIP_BUILTIN_GET_ARRAY, BUILT_IN_MD, NULL,
4336 add_builtin_function ("__builtin_testport_array",
4337 int_ftype_int_int_int,
4338 PICOCHIP_BUILTIN_TESTPORT_ARRAY, BUILT_IN_MD,
4341 /* Halt instruction. Note that the builtin function is marked as
4342 having the attribute `noreturn' so that the compiler realises
4343 that the halt stops the program dead. */
4344 noreturn = tree_cons (get_identifier ("noreturn"), NULL, NULL);
4345 add_builtin_function ("__builtin_halt", void_ftype_void,
4346 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4348 add_builtin_function ("picoHalt", void_ftype_void,
4349 PICOCHIP_BUILTIN_HALT, BUILT_IN_MD, NULL,
4354 /* Expand a call to a builtin function. */
4356 picochip_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
4357 enum machine_mode mode ATTRIBUTE_UNUSED,
4358 int ignore ATTRIBUTE_UNUSED)
4360 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
4361 int fcode = DECL_FUNCTION_CODE (fndecl);
4365 case PICOCHIP_BUILTIN_ASRI:
4366 return picochip_expand_builtin_3op (CODE_FOR_builtin_asri, exp,
4369 case PICOCHIP_BUILTIN_ADDS:
4370 return picochip_expand_builtin_3op (CODE_FOR_sataddhi3, exp,
4373 case PICOCHIP_BUILTIN_SUBS:
4374 return picochip_expand_builtin_3op (CODE_FOR_satsubhi3, exp,
4377 case PICOCHIP_BUILTIN_SBC:
4378 return picochip_expand_builtin_2op (CODE_FOR_sbc, exp, target);
4380 case PICOCHIP_BUILTIN_BREV:
4381 return picochip_expand_builtin_2op (CODE_FOR_brev, exp, target);
4383 case PICOCHIP_BUILTIN_BYTESWAP:
4384 return picochip_expand_builtin_2op (CODE_FOR_bswaphi2, exp, target);
4386 case PICOCHIP_BUILTIN_GET:
4387 return picochip_expand_builtin_2op (CODE_FOR_commsGet, exp, target);
4389 case PICOCHIP_BUILTIN_PUT:
4390 return picochip_expand_builtin_2opvoid (CODE_FOR_commsPut, exp);
4392 case PICOCHIP_BUILTIN_TESTPORT:
4393 return picochip_expand_builtin_2op (CODE_FOR_commsTestPort, exp,
4396 case PICOCHIP_BUILTIN_PUT_ARRAY:
4397 return picochip_expand_array_put (exp, target);
4399 case PICOCHIP_BUILTIN_GET_ARRAY:
4400 return picochip_expand_array_get (exp, target);
4402 case PICOCHIP_BUILTIN_TESTPORT_ARRAY:
4403 return picochip_expand_array_testport (exp, target);
4405 case PICOCHIP_BUILTIN_HALT:
4406 return picochip_generate_halt ();
4413 /* Should really do something sensible here. */
4417 /* Emit warnings. */
4419 picochip_warn_inefficient (const char *msg)
4421 if (TARGET_INEFFICIENT_WARNINGS)
4422 warning (OPT_minefficient_warnings,
4423 "%s (disable warning using -mno-inefficient-warnings)", msg);
4427 warn_of_byte_access (void)
4429 static int warned = 0;
4433 picochip_warn_inefficient
4434 ("byte access is synthesised - consider using MUL AE");
4441 picochip_function_value (const_tree valtype, const_tree func,
4442 bool outgoing ATTRIBUTE_UNUSED)
4444 enum machine_mode mode = TYPE_MODE (valtype);
4445 int unsignedp = TYPE_UNSIGNED (valtype);
4447 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
4448 just as PROMOTE_MODE does. */
4449 mode = promote_function_mode (valtype, mode, &unsignedp, func, 1);
4451 return gen_rtx_REG (mode, 0);
4455 /* Check that the value of the given mode will fit in the register of
4458 picochip_hard_regno_mode_ok (int regno, enum machine_mode mode)
4461 if (GET_MODE_CLASS (mode) == MODE_CC)
4462 return regno == CC_REGNUM;
4464 /* If the CC register is being used, then only CC mode values are
4465 allowed (which have already been tested). */
4466 if (regno == CC_REGNUM || regno == ACC_REGNUM)
4469 /* Must be a valid register. */
4473 /* Modes QI and HI may be placed in any register except the CC. */
4474 if (mode == QImode || mode == HImode)
4477 /* DI must be in a quad register. */
4479 return (regno % 4 == 0);
4481 /* All other modes must be placed in a even numbered register. */
4482 return !(regno & 1);
4486 /* Extract the lower and upper components of a constant value. */
4489 picochip_get_low_const (rtx value)
4491 return gen_int_mode (INTVAL (value) & 0xFFFF, HImode);
4495 picochip_get_high_const (rtx value)
4497 /*return GEN_INT ((((INTVAL (value) >> 16) & 0xFFFF) ^ 0x8000) - 0x8000); */
4498 return gen_int_mode ((INTVAL (value) >> 16) & 0xFFFF, HImode);
4502 /* Loading and storing QImode values to and from memory in a machine
4503 without byte access requires might require a scratch
4504 register. However, the scratch register might correspond to the
4505 register in which the value is being loaded. To ensure that a
4506 scratch register is supplied which is definitely different to the
4507 output register, request a register pair. This effectively gives a
4508 choice of two registers to choose from, so that we a guaranteed to
4509 get at least one register which is different to the output
4510 register. This trick is taken from the alpha implementation. */
4512 picochip_secondary_reload (bool in_p,
4513 rtx x ATTRIBUTE_UNUSED,
4514 reg_class_t cla ATTRIBUTE_UNUSED,
4515 enum machine_mode mode,
4516 secondary_reload_info *sri)
4518 if (mode == QImode && !TARGET_HAS_BYTE_ACCESS)
4521 sri->icode = CODE_FOR_reload_outqi;
4523 sri->icode = CODE_FOR_reload_inqi;
4526 /* We dont need to return a register class type when we need only a
4527 scratch register. It realizes the scratch register type by looking
4528 at the instruction definition for sri->icode. We only need to
4529 return the register type when we need intermediaries for copies.*/
4533 /* Return true if the given memory operand can be aligned to a
4534 word+offset memory reference (e.g., FP+3 can be converted into the
4535 memory operand FP+2, with the offset 1). */
4537 picochip_alignable_memory_operand (rtx mem_operand,
4538 enum machine_mode mode ATTRIBUTE_UNUSED)
4542 /* Not a mem operand. Refuse immediately. */
4543 if (MEM != GET_CODE (mem_operand))
4546 address = XEXP (mem_operand, 0);
4548 /* Return true if a PLUS of the SP and a (valid) constant, or SP itself. */
4549 return ((PLUS == GET_CODE (address) &&
4550 REGNO (XEXP (address, 0)) == STACK_POINTER_REGNUM &&
4551 CONST_INT == GET_CODE (XEXP (address, 1)) &&
4552 picochip_const_ok_for_letter_p (INTVAL (XEXP (address, 1)), 'K'))
4553 || (REG == GET_CODE (address)
4554 && REGNO (address) == STACK_POINTER_REGNUM));
4558 /* Return true if the given memory reference is to a word aligned
4559 address. Currently this means it must be either SP, or
4560 SP+offset. We could replace this function with alignable
4561 memory references in the above function?. */
4563 picochip_word_aligned_memory_reference (rtx operand)
4567 /* The address must be the SP register, or a constant, aligned
4568 offset from SP which doesn't exceed the FP+offset
4570 return ((PLUS == GET_CODE (operand)
4571 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
4572 && picochip_is_aligned (INTVAL (XEXP (operand, 1)), 16)
4573 && picochip_const_ok_for_letter_p (INTVAL (XEXP (operand, 1)),
4575 || (REG == GET_CODE (operand)
4576 && REGNO (operand) == STACK_POINTER_REGNUM));
4580 /* Given an alignable memory location, convert the memory location
4581 into a HI mode access, storing the new memory reference in
4582 paligned_mem, and the number of bits by which to shift in pbitnum
4583 (i.e., given a reference to FP+3, this creates an aligned reference
4584 of FP+2, with an 8-bit shift). This code is a modification of that
4585 found in the Alpha port. */
4587 picochip_get_hi_aligned_mem (rtx ref, rtx * paligned_mem, rtx * pbitnum)
4590 HOST_WIDE_INT offset = 0;
4592 gcc_assert (GET_CODE (ref) == MEM);
4594 if (reload_in_progress && !memory_address_p (GET_MODE (ref), XEXP (ref, 0)))
4596 base = find_replacement (&XEXP (ref, 0));
4598 gcc_assert(memory_address_p (GET_MODE (ref), base));
4602 base = XEXP (ref, 0);
4605 if (GET_CODE (base) == PLUS)
4607 offset += INTVAL (XEXP (base, 1));
4608 base = XEXP (base, 0);
4611 *paligned_mem = widen_memory_access (ref, HImode, (offset & ~1) - offset);
4618 ("Found non-zero offset in get_hi_aligned_mem - check that the correct value is being used (as this functionality hasn't been exploited yet).\n");
4622 *pbitnum = GEN_INT ((offset & 1) * 8);
4626 /* Return true if the given operand is an absolute address in memory
4627 (i.e., a symbolic offset). */
4629 picochip_absolute_memory_operand (rtx op,
4630 enum machine_mode mode ATTRIBUTE_UNUSED)
4633 if (MEM == GET_CODE (op))
4635 rtx address = XEXP (op, 0);
4637 /* Symbols are valid absolute addresses. */
4638 if (SYMBOL_REF == GET_CODE (address))
4641 /* Constant offsets to symbols are valid absolute addresses. */
4642 if (CONST == GET_CODE (address) &&
4643 PLUS == GET_CODE (XEXP (address, 0)) &&
4644 SYMBOL_REF == GET_CODE (XEXP (XEXP (address, 0), 0)) &&
4645 CONST_INT == GET_CODE (XEXP (XEXP (address, 0), 1)))
4652 /* Symbols are valid absolute addresses. */
4653 if (SYMBOL_REF == GET_CODE (XEXP (op, 0)))
4662 picochip_asm_named_section (const char *name,
4663 unsigned int flags ATTRIBUTE_UNUSED,
4664 tree decl ATTRIBUTE_UNUSED)
4666 fprintf (asm_out_file, ".section %s\n", name);
4670 /* Check if we can make a conditional copy instruction. This is emitted as an
4671 instruction to set the condition register, followed by an instruction which
4672 uses the condition registers to perform the conditional move. */
4674 picochip_check_conditional_copy (rtx * operands)
4677 rtx branch_op_0 = XEXP (operands[1], 0);
4678 rtx branch_op_1 = XEXP (operands[1], 1);
4680 /* Only HI mode conditional moves are currently allowed. Can we add
4682 if (GET_CODE (operands[1]) != EQ && GET_CODE (operands[1]) != NE)
4685 /* Is the comparison valid? Only allow operands which are registers
4686 if they are HImode. SI mode comparisons against 0 could be
4687 handled using logical operations (e.g., SIreg != 0 when low ||
4688 high). Need to find test cases to provoke this though (fixunssfdi
4689 in libgcc does, but is complicated). */
4690 if (register_operand(branch_op_0, GET_MODE(branch_op_0)) &&
4691 GET_MODE(branch_op_0) != HImode)
4693 if (register_operand(branch_op_1, GET_MODE(branch_op_1)) &&
4694 GET_MODE(branch_op_1) != HImode)
4703 picochip_static_chain (const_tree ARG_UNUSED (fndecl), bool incoming_p)
4707 addr = arg_pointer_rtx;
4709 addr = plus_constant (stack_pointer_rtx, -2 * UNITS_PER_WORD);
4710 return gen_frame_mem (Pmode, addr);