1 /* Definitions of target machine for GNU compiler, for the pdp-11
2 Copyright (C) 1994, 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2004
3 Free Software Foundation, Inc.
4 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
23 #define CONSTANT_POOL_BEFORE_FUNCTION 0
25 /* check whether load_fpu_reg or not */
26 #define LOAD_FPU_REG_P(x) ((x)>=8 && (x)<=11)
27 #define NO_LOAD_FPU_REG_P(x) ((x)==12 || (x)==13)
28 #define FPU_REG_P(x) (LOAD_FPU_REG_P(x) || NO_LOAD_FPU_REG_P(x))
29 #define CPU_REG_P(x) ((x)<8)
31 /* Names to predefine in the preprocessor for this target machine. */
33 #define TARGET_CPU_CPP_BUILTINS() \
36 builtin_define_std ("pdp11"); \
40 /* Print subsidiary information on the compiler version in use. */
41 #define TARGET_VERSION fprintf (stderr, " (pdp11)");
44 /* Generate DBX debugging information. */
46 /* #define DBX_DEBUGGING_INFO */
48 /* Run-time compilation parameters selecting different hardware subsets.
51 extern int target_flags;
53 /* Macro to define tables used to set the flags.
54 This is a list in braces of triplets in braces,
55 each triplet being { "NAME", VALUE, DOC }
56 where VALUE is the bits to set or minus the bits to clear and DOC
57 is the documentation for --help (NULL if intentionally undocumented).
58 An empty string NAME is used to identify the default VALUE. */
60 #define TARGET_SWITCHES \
61 { { "fpu", 1, N_("Use hardware floating point") }, \
62 { "soft-float", -1, N_("Do not use hardware floating point") }, \
63 /* return float result in ac0 */ \
64 { "ac0", 2, N_("Return floating point results in ac0") }, \
65 { "no-ac0", -2, N_("Return floating point results in memory") }, \
67 { "40", 4, N_("Generate code for an 11/40") }, \
68 { "no-40", -4, "" }, \
70 { "45", 8, N_("Generate code for an 11/45") }, \
71 { "no-45", -8, "" }, \
73 { "10", -12, N_("Generate code for an 11/10") }, \
74 /* use movstrhi for bcopy */ \
75 { "bcopy", 16, NULL }, \
76 { "bcopy-builtin", -16, NULL }, \
77 /* use 32 bit for int */ \
78 { "int32", 32, N_("Use 32 bit int") }, \
79 { "no-int16", 32, N_("Use 32 bit int") }, \
80 { "int16", -32, N_("Use 16 bit int") }, \
81 { "no-int32", -32, N_("Use 16 bit int") }, \
82 /* use 32 bit for float */ \
83 { "float32", 64, N_("Use 32 bit float") }, \
84 { "no-float64", 64, N_("Use 32 bit float") }, \
85 { "float64", -64, N_("Use 64 bit float") }, \
86 { "no-float32", -64, N_("Use 64 bit float") }, \
87 /* allow abshi pattern? - can trigger "optimizations" which make code SLOW! */\
88 { "abshi", 128, NULL }, \
89 { "no-abshi", -128, NULL }, \
90 /* is branching expensive - on a PDP, it's actually really cheap */ \
91 /* this is just to play around and check what code gcc generates */ \
92 { "branch-expensive", 256, NULL }, \
93 { "branch-cheap", -256, NULL }, \
94 /* split instruction and data memory? */ \
95 { "split", 1024, N_("Target has split I&D") }, \
96 { "no-split", -1024, N_("Target does not have split I&D") }, \
97 /* UNIX assembler syntax? */ \
98 { "unix-asm", 2048, N_("Use UNIX assembler syntax") }, \
99 { "dec-asm", -2048, N_("Use DEC assembler syntax") }, \
101 { "", TARGET_DEFAULT, NULL} \
104 #define TARGET_DEFAULT (1 | 8 | 128 | TARGET_UNIX_ASM_DEFAULT)
106 #define TARGET_FPU (target_flags & 1)
107 #define TARGET_SOFT_FLOAT (!TARGET_FPU)
109 #define TARGET_AC0 ((target_flags & 2) && TARGET_FPU)
110 #define TARGET_NO_AC0 (! TARGET_AC0)
112 #define TARGET_45 (target_flags & 8)
113 #define TARGET_40_PLUS ((target_flags & 4) || (target_flags & 8))
114 #define TARGET_10 (! TARGET_40_PLUS)
116 #define TARGET_BCOPY_BUILTIN (! (target_flags & 16))
118 #define TARGET_INT16 (! TARGET_INT32)
119 #define TARGET_INT32 (target_flags & 32)
121 #define TARGET_FLOAT32 (target_flags & 64)
122 #define TARGET_FLOAT64 (! TARGET_FLOAT32)
124 #define TARGET_ABSHI_BUILTIN (target_flags & 128)
126 #define TARGET_BRANCH_EXPENSIVE (target_flags & 256)
127 #define TARGET_BRANCH_CHEAP (!TARGET_BRANCH_EXPENSIVE)
129 #define TARGET_SPLIT (target_flags & 1024)
130 #define TARGET_NOSPLIT (! TARGET_SPLIT)
132 #define TARGET_UNIX_ASM (target_flags & 2048)
133 #define TARGET_UNIX_ASM_DEFAULT 0
135 #define ASSEMBLER_DIALECT (TARGET_UNIX_ASM ? 1 : 0)
140 #define SHORT_TYPE_SIZE 16
141 #define INT_TYPE_SIZE (TARGET_INT16 ? 16 : 32)
142 #define LONG_TYPE_SIZE 32
143 #define LONG_LONG_TYPE_SIZE 64
145 /* if we set FLOAT_TYPE_SIZE to 32, we could have the benefit
146 of saving core for huge arrays - the definitions are
147 already in md - but floats can never reside in
148 an FPU register - we keep the FPU in double float mode
150 #define FLOAT_TYPE_SIZE (TARGET_FLOAT32 ? 32 : 64)
151 #define DOUBLE_TYPE_SIZE 64
152 #define LONG_DOUBLE_TYPE_SIZE 64
154 /* machine types from ansi */
155 #define SIZE_TYPE "unsigned int" /* definition of size_t */
156 #define WCHAR_TYPE "int" /* or long int???? */
157 #define WCHAR_TYPE_SIZE 16
159 #define PTRDIFF_TYPE "int"
161 /* target machine storage layout */
163 /* Define this if most significant bit is lowest numbered
164 in instructions that operate on numbered bit-fields. */
165 #define BITS_BIG_ENDIAN 0
167 /* Define this if most significant byte of a word is the lowest numbered. */
168 #define BYTES_BIG_ENDIAN 0
170 /* Define this if most significant word of a multiword number is numbered. */
171 #define WORDS_BIG_ENDIAN 1
173 /* Width of a word, in units (bytes).
175 UNITS OR BYTES - seems like units */
176 #define UNITS_PER_WORD 2
178 /* Maximum sized of reasonable data type
179 DImode or Dfmode ...*/
180 #define MAX_FIXED_MODE_SIZE 64
182 /* Allocation boundary (in *bits*) for storing pointers in memory. */
183 #define POINTER_BOUNDARY 16
185 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
186 #define PARM_BOUNDARY 16
188 /* Boundary (in *bits*) on which stack pointer should be aligned. */
189 #define STACK_BOUNDARY 16
191 /* Allocation boundary (in *bits*) for the code of a function. */
192 #define FUNCTION_BOUNDARY 16
194 /* Alignment of field after `int : 0' in a structure. */
195 #define EMPTY_FIELD_BOUNDARY 16
197 /* No data type wants to be aligned rounder than this. */
198 #define BIGGEST_ALIGNMENT 16
200 /* Define this if move instructions will actually fail to work
201 when given unaligned data. */
202 #define STRICT_ALIGNMENT 1
204 /* Standard register usage. */
206 /* Number of actual hardware registers.
207 The hardware registers are assigned numbers for the compiler
208 from 0 to just below FIRST_PSEUDO_REGISTER.
209 All registers that the compiler knows about must be given numbers,
210 even those that are not normally considered general registers.
212 we have 8 integer registers, plus 6 float
213 (don't use scratch float !) */
215 #define FIRST_PSEUDO_REGISTER 14
217 /* 1 for registers that have pervasive standard uses
218 and are not available for the register allocator.
220 On the pdp, these are:
223 reg 5 = fp; not necessarily!
226 /* don't let them touch fp regs for the time being !*/
228 #define FIXED_REGISTERS \
229 {0, 0, 0, 0, 0, 0, 1, 1, \
234 /* 1 for registers not available across function calls.
235 These must include the FIXED_REGISTERS and also any
236 registers that can be used without being saved.
237 The latter must include the registers where values are returned
238 and the register where structure-value addresses are passed.
239 Aside from that, you can include as many other registers as you like. */
241 /* don't know about fp */
242 #define CALL_USED_REGISTERS \
243 {1, 1, 0, 0, 0, 0, 1, 1, \
247 /* Make sure everything's fine if we *don't* have an FPU.
248 This assumes that putting a register in fixed_regs will keep the
249 compiler's mitts completely off it. We don't bother to zero it out
250 of register classes. Also fix incompatible register naming with
253 #define CONDITIONAL_REGISTER_USAGE \
259 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); \
260 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
261 if (TEST_HARD_REG_BIT (x, i)) \
262 fixed_regs[i] = call_used_regs[i] = 1; \
266 call_used_regs[8] = 1; \
267 if (TARGET_UNIX_ASM) \
269 /* Change names of FPU registers for the UNIX assembler. */ \
270 reg_names[8] = "fr0"; \
271 reg_names[9] = "fr1"; \
272 reg_names[10] = "fr2"; \
273 reg_names[11] = "fr3"; \
274 reg_names[12] = "fr4"; \
275 reg_names[13] = "fr5"; \
279 /* Return number of consecutive hard regs needed starting at reg REGNO
280 to hold something of mode MODE.
281 This is ordinarily the length in words of a value of mode MODE
282 but can be less for certain modes in special long registers.
285 #define HARD_REGNO_NREGS(REGNO, MODE) \
287 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
291 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
292 On the pdp, the cpu registers can hold any mode - check alignment
294 FPU can only hold DF - simplifies life!
296 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
298 ((GET_MODE_BITSIZE(MODE) <= 16) \
299 || (GET_MODE_BITSIZE(MODE) == 32 && !((REGNO) & 1))) \
303 /* Value is 1 if it is a good idea to tie two pseudo registers
304 when one has mode MODE1 and one has mode MODE2.
305 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
306 for any hard reg, then this must be 0 for correct output. */
307 #define MODES_TIEABLE_P(MODE1, MODE2) 0
309 /* Specify the registers used for certain standard purposes.
310 The values of these macros are register numbers. */
312 /* the pdp11 pc overloaded on a register that the compiler knows about. */
315 /* Register to use for pushing function arguments. */
316 #define STACK_POINTER_REGNUM 6
318 /* Base register for access to local variables of the function. */
319 #define FRAME_POINTER_REGNUM 5
321 /* Value should be nonzero if functions must have frame pointers.
322 Zero means the frame pointer need not be set up (and parms
323 may be accessed via the stack pointer) in functions that seem suitable.
324 This is computed in `reload', in reload1.c.
327 #define FRAME_POINTER_REQUIRED 0
329 /* Base register for access to arguments of the function. */
330 #define ARG_POINTER_REGNUM 5
332 /* Register in which static-chain is passed to a function. */
333 /* ??? - i don't want to give up a reg for this! */
334 #define STATIC_CHAIN_REGNUM 4
336 /* Define the classes of registers for register constraints in the
337 machine description. Also define ranges of constants.
339 One of the classes must always be named ALL_REGS and include all hard regs.
340 If there is more than one class, another class must be named NO_REGS
341 and contain no registers.
343 The name GENERAL_REGS must be the name of a class (or an alias for
344 another name such as ALL_REGS). This is the class of registers
345 that is allowed by "g" or "r" in a register constraint.
346 Also, registers outside this class are allocated only when
347 instructions express preferences for them.
349 The classes must be numbered in nondecreasing order; that is,
350 a larger-numbered class must never be contained completely
351 in a smaller-numbered class.
353 For any two classes, it is very desirable that there be another
354 class that represents their union. */
356 /* The pdp has a couple of classes:
358 MUL_REGS are used for odd numbered regs, to use in 16 bit multiplication
359 (even numbered do 32 bit multiply)
360 LMUL_REGS long multiply registers (even numbered regs )
361 (don't need them, all 32 bit regs are even numbered!)
362 GENERAL_REGS is all cpu
363 LOAD_FPU_REGS is the first four cpu regs, they are easier to load
364 NO_LOAD_FPU_REGS is ac4 and ac5, currently - difficult to load them
365 FPU_REGS is all fpu regs
368 enum reg_class { NO_REGS, MUL_REGS, GENERAL_REGS, LOAD_FPU_REGS, NO_LOAD_FPU_REGS, FPU_REGS, ALL_REGS, LIM_REG_CLASSES };
370 #define N_REG_CLASSES (int) LIM_REG_CLASSES
372 /* have to allow this till cmpsi/tstsi are fixed in a better way !! */
373 #define SMALL_REGISTER_CLASSES 1
375 /* Since GENERAL_REGS is the same class as ALL_REGS,
376 don't give it a different class number; just make it an alias. */
378 /* #define GENERAL_REGS ALL_REGS */
380 /* Give names of register classes as strings for dump file. */
382 #define REG_CLASS_NAMES {"NO_REGS", "MUL_REGS", "GENERAL_REGS", "LOAD_FPU_REGS", "NO_LOAD_FPU_REGS", "FPU_REGS", "ALL_REGS" }
384 /* Define which registers fit in which classes.
385 This is an initializer for a vector of HARD_REG_SET
386 of length N_REG_CLASSES. */
388 #define REG_CLASS_CONTENTS {{0}, {0x00aa}, {0x00ff}, {0x0f00}, {0x3000}, {0x3f00}, {0x3fff}}
390 /* The same information, inverted:
391 Return the class number of the smallest class containing
392 reg number REGNO. This could be a conditional expression
393 or could index an array. */
395 #define REGNO_REG_CLASS(REGNO) \
396 ((REGNO)>=8?((REGNO)<=11?LOAD_FPU_REGS:NO_LOAD_FPU_REGS):(((REGNO)&1)?MUL_REGS:GENERAL_REGS))
399 /* The class value for index registers, and the one for base regs. */
400 #define INDEX_REG_CLASS GENERAL_REGS
401 #define BASE_REG_CLASS GENERAL_REGS
403 /* Get reg_class from a letter such as appears in the machine description. */
405 #define REG_CLASS_FROM_LETTER(C) \
406 ((C) == 'f' ? FPU_REGS : \
407 ((C) == 'd' ? MUL_REGS : \
408 ((C) == 'a' ? LOAD_FPU_REGS : NO_REGS)))
411 /* The letters I, J, K, L and M in a register constraint string
412 can be used to stand for particular ranges of immediate operands.
413 This macro defines what the ranges are.
414 C is the letter, and VALUE is a constant value.
415 Return 1 if VALUE is in the range specified by C.
419 K completely random 32 bit
420 L,M,N -1,1,0 respectively
421 O where doing shifts in sequence is faster than
425 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
426 ((C) == 'I' ? ((VALUE) & 0xffff0000) == 0 \
427 : (C) == 'J' ? ((VALUE) & 0x0000ffff) == 0 \
428 : (C) == 'K' ? (((VALUE) & 0xffff0000) != 0 \
429 && ((VALUE) & 0x0000ffff) != 0) \
430 : (C) == 'L' ? ((VALUE) == 1) \
431 : (C) == 'M' ? ((VALUE) == -1) \
432 : (C) == 'N' ? ((VALUE) == 0) \
433 : (C) == 'O' ? (abs(VALUE) >1 && abs(VALUE) <= 4) \
436 /* Similar, but for floating constants, and defining letters G and H.
437 Here VALUE is the CONST_DOUBLE rtx itself. */
439 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
440 ((C) == 'G' && XINT (VALUE, 0) == 0 && XINT (VALUE, 1) == 0)
443 /* Letters in the range `Q' through `U' may be defined in a
444 machine-dependent fashion to stand for arbitrary operand types.
445 The machine description macro `EXTRA_CONSTRAINT' is passed the
446 operand as its first argument and the constraint letter as its
449 `Q' is for memory references using take more than 1 instruction.
450 `R' is for memory references which take 1 word for the instruction. */
452 #define EXTRA_CONSTRAINT(OP,CODE) \
453 ((GET_CODE (OP) != MEM) ? 0 \
454 : !legitimate_address_p (GET_MODE (OP), XEXP (OP, 0)) ? 0 \
455 : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
456 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
459 /* Given an rtx X being reloaded into a reg required to be
460 in class CLASS, return the class of reg to actually use.
461 In general this is just CLASS; but on some machines
462 in some cases it is preferable to use a more restrictive class.
464 loading is easier into LOAD_FPU_REGS than FPU_REGS! */
466 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
467 (((CLASS) != FPU_REGS)?(CLASS):LOAD_FPU_REGS)
469 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,x) \
470 (((CLASS) == NO_LOAD_FPU_REGS && !(REG_P(x) && LOAD_FPU_REG_P(REGNO(x))))?LOAD_FPU_REGS:NO_REGS)
472 /* Return the maximum number of consecutive registers
473 needed to represent mode MODE in a register of class CLASS. */
474 #define CLASS_MAX_NREGS(CLASS, MODE) \
475 ((CLASS == GENERAL_REGS || CLASS == MUL_REGS)? \
476 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD): \
481 /* Stack layout; function entry, exit and calling. */
483 /* Define this if pushing a word on the stack
484 makes the stack pointer a smaller address. */
485 #define STACK_GROWS_DOWNWARD
487 /* Define this if the nominal address of the stack frame
488 is at the high-address end of the local variables;
489 that is, each additional local variable allocated
490 goes at a more negative offset in the frame.
492 #define FRAME_GROWS_DOWNWARD
494 /* Offset within stack frame to start allocating local variables at.
495 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
496 first local allocated. Otherwise, it is the offset to the BEGINNING
497 of the first local allocated. */
498 #define STARTING_FRAME_OFFSET 0
500 /* If we generate an insn to push BYTES bytes,
501 this says how many the stack pointer really advances by.
502 On the pdp11, the stack is on an even boundary */
503 #define PUSH_ROUNDING(BYTES) ((BYTES + 1) & ~1)
505 /* current_first_parm_offset stores the # of registers pushed on the
507 extern int current_first_parm_offset;
509 /* Offset of first parameter from the argument pointer register value.
510 For the pdp11, this is nonzero to account for the return address.
512 2 - frame pointer (always saved, even when not used!!!!)
513 -- chnage some day !!!:q!
516 #define FIRST_PARM_OFFSET(FNDECL) 4
518 /* Value is 1 if returning from a function call automatically
519 pops the arguments described by the number-of-args field in the call.
520 FUNDECL is the declaration node of the function (as a tree),
521 FUNTYPE is the data type of the function (as a tree),
522 or for a library call it is an identifier node for the subroutine name. */
524 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
526 /* Define how to find the value returned by a function.
527 VALTYPE is the data type of the value (as a tree).
528 If the precise function being called is known, FUNC is its FUNCTION_DECL;
529 otherwise, FUNC is 0. */
530 #define BASE_RETURN_VALUE_REG(MODE) \
531 ((MODE) == DFmode ? 8 : 0)
533 /* On the pdp11 the value is found in R0 (or ac0???
534 not without FPU!!!! ) */
536 #define FUNCTION_VALUE(VALTYPE, FUNC) \
537 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
539 /* and the called function leaves it in the first register.
540 Difference only on machines with register windows. */
542 #define FUNCTION_OUTGOING_VALUE(VALTYPE, FUNC) \
543 gen_rtx_REG (TYPE_MODE (VALTYPE), BASE_RETURN_VALUE_REG(TYPE_MODE(VALTYPE)))
545 /* Define how to find the value returned by a library function
546 assuming the value has mode MODE. */
548 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, BASE_RETURN_VALUE_REG(MODE))
550 /* 1 if N is a possible register number for a function value
551 as seen by the caller.
552 On the pdp, the first "output" reg is the only register thus used.
554 maybe ac0 ? - as option someday! */
556 #define FUNCTION_VALUE_REGNO_P(N) (((N) == 0) || (TARGET_AC0 && (N) == 8))
558 /* 1 if N is a possible register number for function argument passing.
561 #define FUNCTION_ARG_REGNO_P(N) 0
563 /* Define a data type for recording info about an argument list
564 during the scan of that argument list. This data type should
565 hold all necessary information about the function itself
566 and about the args processed so far, enough to enable macros
567 such as FUNCTION_ARG to determine where the next arg should go.
571 #define CUMULATIVE_ARGS int
573 /* Initialize a variable CUM of type CUMULATIVE_ARGS
574 for a call to a function whose data type is FNTYPE.
575 For a library call, FNTYPE is 0.
577 ...., the offset normally starts at 0, but starts at 1 word
578 when the function gets a structure-value-address as an
579 invisible first argument. */
581 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
584 /* Update the data in CUM to advance over an argument
585 of mode MODE and data type TYPE.
586 (TYPE is null for libcalls where that information may not be available.)
591 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
592 ((CUM) += ((MODE) != BLKmode \
593 ? (GET_MODE_SIZE (MODE)) \
594 : (int_size_in_bytes (TYPE))))
596 /* Determine where to put an argument to a function.
597 Value is zero to push the argument on the stack,
598 or a hard register in which to store the argument.
600 MODE is the argument's machine mode.
601 TYPE is the data type of the argument (as a tree).
602 This is null for libcalls where that information may
604 CUM is a variable of type CUMULATIVE_ARGS which gives info about
605 the preceding args and about the function being called.
606 NAMED is nonzero if this argument is a named parameter
607 (otherwise it is an extra parameter matching an ellipsis). */
609 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0
611 /* Define where a function finds its arguments.
612 This would be different from FUNCTION_ARG if we had register windows. */
614 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
615 FUNCTION_ARG (CUM, MODE, TYPE, NAMED)
618 /* For an arg passed partly in registers and partly in memory,
619 this is the number of registers used.
620 For args passed entirely in registers or entirely in memory, zero. */
622 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
624 /* Output assembler code to FILE to increment profiler label # LABELNO
625 for profiling a function entry. */
627 #define FUNCTION_PROFILER(FILE, LABELNO) \
630 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
631 the stack pointer does not matter. The value is tested only in
632 functions that have frame pointers.
633 No definition is equivalent to always zero. */
635 extern int may_call_alloca;
637 #define EXIT_IGNORE_STACK 1
639 #define INITIAL_FRAME_POINTER_OFFSET(DEPTH_VAR) \
642 offset = get_frame_size(); \
643 for (regno = 0; regno < 8; regno++) \
644 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
646 for (regno = 8; regno < 14; regno++) \
647 if (regs_ever_live[regno] && ! call_used_regs[regno]) \
649 /* offset -= 2; no fp on stack frame */ \
650 (DEPTH_VAR) = offset; \
654 /* Addressing modes, and classification of registers for them. */
656 #define HAVE_POST_INCREMENT 1
658 #define HAVE_PRE_DECREMENT 1
660 /* Macros to check register numbers against specific register classes. */
662 /* These assume that REGNO is a hard or pseudo reg number.
663 They give nonzero only if REGNO is a hard reg of the suitable class
664 or a pseudo reg currently allocated to a suitable hard reg.
665 Since they use reg_renumber, they are safe only once reg_renumber
666 has been allocated, which happens in local-alloc.c. */
668 #define REGNO_OK_FOR_INDEX_P(REGNO) \
669 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
670 #define REGNO_OK_FOR_BASE_P(REGNO) \
671 ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
673 /* Now macros that check whether X is a register and also,
674 strictly, whether it is in a specified class.
679 /* Maximum number of registers that can appear in a valid memory address. */
681 #define MAX_REGS_PER_ADDRESS 2
683 /* Recognize any constant value that is a valid address. */
685 #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
687 /* Nonzero if the constant value X is a legitimate general operand.
688 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
690 #define LEGITIMATE_CONSTANT_P(X) (TARGET_FPU? 1: !(GET_CODE(X) == CONST_DOUBLE))
692 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
693 and check its validity for a certain class.
694 We have two alternate definitions for each of them.
695 The usual definition accepts all pseudo regs; the other rejects
696 them unless they have been allocated suitable hard regs.
697 The symbol REG_OK_STRICT causes the latter definition to be used.
699 Most source files want to accept pseudo regs in the hope that
700 they will get allocated to the class that the insn wants them to be in.
701 Source files for reload pass need to be strict.
702 After reload, it makes no difference, since pseudo regs have
703 been eliminated by then. */
705 #ifndef REG_OK_STRICT
707 /* Nonzero if X is a hard reg that can be used as an index
708 or if it is a pseudo reg. */
709 #define REG_OK_FOR_INDEX_P(X) (1)
710 /* Nonzero if X is a hard reg that can be used as a base reg
711 or if it is a pseudo reg. */
712 #define REG_OK_FOR_BASE_P(X) (1)
716 /* Nonzero if X is a hard reg that can be used as an index. */
717 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
718 /* Nonzero if X is a hard reg that can be used as a base reg. */
719 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
723 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
724 that is a valid memory address for an instruction.
725 The MODE argument is the machine mode for the MEM expression
726 that wants to use this address.
730 #define GO_IF_LEGITIMATE_ADDRESS(mode, operand, ADDR) \
735 if (GET_CODE (operand) == REG \
736 && REG_OK_FOR_BASE_P(operand)) \
739 /* accept @#address */ \
740 if (CONSTANT_ADDRESS_P (operand)) \
744 if (GET_CODE (operand) == PLUS \
745 && GET_CODE (XEXP (operand, 0)) == REG \
746 && REG_OK_FOR_BASE_P (XEXP (operand, 0)) \
747 && CONSTANT_ADDRESS_P (XEXP (operand, 1))) \
751 if (GET_CODE (operand) == PRE_DEC \
752 && GET_CODE (XEXP (operand, 0)) == REG \
753 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
757 if (GET_CODE (operand) == POST_INC \
758 && GET_CODE (XEXP (operand, 0)) == REG \
759 && REG_OK_FOR_BASE_P (XEXP (operand, 0))) \
762 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ \
763 if (GET_CODE (operand) == PRE_MODIFY \
764 && GET_CODE (XEXP (operand, 0)) == REG \
765 && REGNO (XEXP (operand, 0)) == 6 \
766 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \
767 && GET_CODE (XEXP (xfoob, 0)) == REG \
768 && REGNO (XEXP (xfoob, 0)) == 6 \
769 && CONSTANT_P (XEXP (xfoob, 1)) \
770 && INTVAL (XEXP (xfoob,1)) == -2) \
773 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ \
774 if (GET_CODE (operand) == POST_MODIFY \
775 && GET_CODE (XEXP (operand, 0)) == REG \
776 && REGNO (XEXP (operand, 0)) == 6 \
777 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS \
778 && GET_CODE (XEXP (xfoob, 0)) == REG \
779 && REGNO (XEXP (xfoob, 0)) == 6 \
780 && CONSTANT_P (XEXP (xfoob, 1)) \
781 && INTVAL (XEXP (xfoob,1)) == 2) \
785 /* handle another level of indirection ! */ \
786 if (GET_CODE(operand) != MEM) \
789 xfoob = XEXP (operand, 0); \
791 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently */ \
792 /* also forbidden for float, because we have to handle this */ \
793 /* in output_move_double and/or output_move_quad() - we could */ \
794 /* do it, but currently it's not worth it!!! */ \
795 /* now that DFmode cannot go into CPU register file, */ \
796 /* maybe I should allow float ... */ \
797 /* but then I have to handle memory-to-memory moves in movdf ?? */ \
799 if (GET_MODE_BITSIZE(mode) > 16) \
802 /* accept @(R0) - which is @0(R0) */ \
803 if (GET_CODE (xfoob) == REG \
804 && REG_OK_FOR_BASE_P(xfoob)) \
807 /* accept @address */ \
808 if (CONSTANT_ADDRESS_P (xfoob)) \
811 /* accept @X(R0) */ \
812 if (GET_CODE (xfoob) == PLUS \
813 && GET_CODE (XEXP (xfoob, 0)) == REG \
814 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0)) \
815 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1))) \
818 /* accept @-(R0) */ \
819 if (GET_CODE (xfoob) == PRE_DEC \
820 && GET_CODE (XEXP (xfoob, 0)) == REG \
821 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
824 /* accept @(R0)+ */ \
825 if (GET_CODE (xfoob) == POST_INC \
826 && GET_CODE (XEXP (xfoob, 0)) == REG \
827 && REG_OK_FOR_BASE_P (XEXP (xfoob, 0))) \
830 /* anything else is invalid */ \
835 /* Try machine-dependent ways of modifying an illegitimate address
836 to be legitimate. If we find one, return the new, valid address.
837 This macro is used in only one place: `memory_address' in explow.c.
839 OLDX is the address as it was before break_out_memory_refs was called.
840 In some cases it is useful to look at this to decide what needs to be done.
842 MODE and WIN are passed so that this macro can use
843 GO_IF_LEGITIMATE_ADDRESS.
845 It is always safe for this macro to do nothing. It exists to recognize
846 opportunities to optimize the output. */
848 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
851 /* Go to LABEL if ADDR (a legitimate address expression)
852 has an effect that depends on the machine mode it is used for.
853 On the pdp this is for predec/postinc */
855 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
856 { if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) \
861 /* Specify the machine mode that this machine uses
862 for the index in the tablejump instruction. */
863 #define CASE_VECTOR_MODE HImode
865 /* Define this if a raw index is all that is needed for a
867 #define CASE_TAKES_INDEX_RAW
869 /* Define as C expression which evaluates to nonzero if the tablejump
870 instruction expects the table to contain offsets from the address of the
872 Do not define this if the table should contain absolute addresses. */
873 /* #define CASE_VECTOR_PC_RELATIVE 1 */
875 /* Define this as 1 if `char' should by default be signed; else as 0. */
876 #define DEFAULT_SIGNED_CHAR 1
878 /* Max number of bytes we can move from memory to memory
879 in one reasonably fast instruction.
884 /* Nonzero if access to memory by byte is slow and undesirable. -
886 #define SLOW_BYTE_ACCESS 0
888 /* Do not break .stabs pseudos into continuations. */
889 #define DBX_CONTIN_LENGTH 0
891 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
892 is done just by pretending it is already truncated. */
893 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
895 /* Give a comparison code (EQ, NE etc) and the first operand of a COMPARE,
896 return the mode to be used for the comparison. For floating-point, CCFPmode
899 #define SELECT_CC_MODE(OP,X,Y) \
900 (GET_MODE_CLASS(GET_MODE(X)) == MODE_FLOAT? CCFPmode : CCmode)
902 /* Specify the machine mode that pointers have.
903 After generation of rtl, the compiler makes no further distinction
904 between pointers and any other objects of this machine mode. */
907 /* A function address in a call instruction
908 is a word address (for indexing purposes)
909 so give the MEM rtx a word's mode. */
910 #define FUNCTION_MODE HImode
912 /* Define this if addresses of constant functions
913 shouldn't be put through pseudo regs where they can be cse'd.
914 Desirable on machines where ordinary constants are expensive
915 but a CALL with constant address is cheap. */
916 /* #define NO_FUNCTION_CSE */
919 /* cost of moving one register class to another */
920 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
921 register_move_cost (CLASS1, CLASS2)
923 /* Tell emit-rtl.c how to initialize special values on a per-function base. */
925 extern struct rtx_def *cc0_reg_rtx;
927 #define CC_STATUS_MDEP rtx
929 #define CC_STATUS_MDEP_INIT (cc_status.mdep = 0)
931 /* Tell final.c how to eliminate redundant test instructions. */
933 /* Here we define machine-dependent flags and fields in cc_status
934 (see `conditions.h'). */
936 #define CC_IN_FPU 04000
938 /* Do UPDATE_CC if EXP is a set, used in
941 floats only do compare correctly, else nullify ...
946 /* Store in cc_status the expressions
947 that the condition codes will describe
948 after execution of an instruction whose pattern is EXP.
949 Do not alter them if the instruction would not alter the cc's. */
951 #define NOTICE_UPDATE_CC(EXP, INSN) \
952 { if (GET_CODE (EXP) == SET) \
954 notice_update_cc_on_set(EXP, INSN); \
956 else if (GET_CODE (EXP) == PARALLEL \
957 && GET_CODE (XVECEXP (EXP, 0, 0)) == SET) \
959 notice_update_cc_on_set(XVECEXP (EXP, 0, 0), INSN); \
961 else if (GET_CODE (EXP) == CALL) \
962 { /* all bets are off */ CC_STATUS_INIT; } \
963 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG \
964 && cc_status.value2 \
965 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) \
967 printf ("here!\n"); \
968 cc_status.value2 = 0; \
972 /* Control the assembler format that we output. */
974 /* Output to assembler file text saying following lines
975 may contain character constants, extra white space, comments, etc. */
977 #define ASM_APP_ON ""
979 /* Output to assembler file text saying following lines
980 no longer contain unusual constructs. */
982 #define ASM_APP_OFF ""
984 /* Output before read-only data. */
986 #define TEXT_SECTION_ASM_OP "\t.text\n"
988 /* Output before writable data. */
990 #define DATA_SECTION_ASM_OP "\t.data\n"
992 /* How to refer to registers in assembler output.
993 This sequence is indexed by compiler's hard-register-number (see above). */
995 #define REGISTER_NAMES \
996 {"r0", "r1", "r2", "r3", "r4", "r5", "sp", "pc", \
997 "ac0", "ac1", "ac2", "ac3", "ac4", "ac5" }
999 /* Globalizing directive for a label. */
1000 #define GLOBAL_ASM_OP "\t.globl "
1002 /* The prefix to add to user-visible assembler symbols. */
1004 #define USER_LABEL_PREFIX "_"
1006 /* This is how to store into the string LABEL
1007 the symbol_ref name of an internal numbered label where
1008 PREFIX is the class of label and NUM is the number within the class.
1009 This is suitable for output with `assemble_name'. */
1011 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1012 sprintf (LABEL, "*%s_%lu", PREFIX, (unsigned long)(NUM))
1014 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1015 output_ascii (FILE, P, SIZE)
1017 /* This is how to output an element of a case-vector that is absolute. */
1019 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1020 fprintf (FILE, "\t%sL_%d\n", TARGET_UNIX_ASM ? "" : ".word ", VALUE)
1022 /* This is how to output an element of a case-vector that is relative.
1023 Don't define this if it is not supported. */
1025 /* #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) */
1027 /* This is how to output an assembler line
1028 that says to advance the location counter
1029 to a multiple of 2**LOG bytes.
1034 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1040 fprintf (FILE, "\t.even\n"); \
1046 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1047 fprintf (FILE, "\t.=.+ %#ho\n", (unsigned short)(SIZE))
1049 /* This says how to output an assembler line
1050 to define a global common symbol. */
1052 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1053 ( fprintf ((FILE), ".globl "), \
1054 assemble_name ((FILE), (NAME)), \
1055 fprintf ((FILE), "\n"), \
1056 assemble_name ((FILE), (NAME)), \
1057 fprintf ((FILE), ": .=.+ %#ho\n", (unsigned short)(ROUNDED)) \
1060 /* This says how to output an assembler line
1061 to define a local common symbol. */
1063 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1064 ( assemble_name ((FILE), (NAME)), \
1065 fprintf ((FILE), ":\t.=.+ %#ho\n", (unsigned short)(ROUNDED)))
1067 /* Print operand X (an rtx) in assembler syntax to file FILE.
1068 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1069 For `%' followed by punctuation, CODE is the punctuation and X is null.
1074 #define PRINT_OPERAND(FILE, X, CODE) \
1075 { if (CODE == '#') fprintf (FILE, "#"); \
1076 else if (GET_CODE (X) == REG) \
1077 fprintf (FILE, "%s", reg_names[REGNO (X)]); \
1078 else if (GET_CODE (X) == MEM) \
1079 output_address (XEXP (X, 0)); \
1080 else if (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != SImode) \
1082 real_to_decimal (buf, CONST_DOUBLE_REAL_VALUE (X), sizeof (buf), 0, 1); \
1083 fprintf (FILE, "$0F%s", buf); } \
1084 else { putc ('$', FILE); output_addr_const_pdp11 (FILE, X); }}
1086 /* Print a memory address as an operand to reference that memory location. */
1088 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1089 print_operand_address (FILE, ADDR)
1091 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1093 fprintf (FILE, "\tmov %s, -(sp)\n", reg_names[REGNO]) \
1096 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1098 fprintf (FILE, "\tmov (sp)+, %s\n", reg_names[REGNO]) \
1101 /* trampoline - how should i do it in separate i+d ?
1102 have some allocate_trampoline magic???
1104 the following should work for shared I/D: */
1106 /* lets see whether this works as trampoline:
1107 MV #STATIC, $4 0x940Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM
1108 JMP FUNCTION 0x0058 0x0000 <- FUNCTION
1111 #define TRAMPOLINE_TEMPLATE(FILE) \
1116 assemble_aligned_integer (2, GEN_INT (0x9400+STATIC_CHAIN_REGNUM)); \
1117 assemble_aligned_integer (2, const0_rtx); \
1118 assemble_aligned_integer (2, GEN_INT(0x0058)); \
1119 assemble_aligned_integer (2, const0_rtx); \
1122 #define TRAMPOLINE_SIZE 8
1123 #define TRAMPOLINE_ALIGNMENT 16
1125 /* Emit RTL insns to initialize the variable parts of a trampoline.
1126 FNADDR is an RTX for the address of the function's pure code.
1127 CXT is an RTX for the static chain value for the function. */
1129 #define INITIALIZE_TRAMPOLINE(TRAMP,FNADDR,CXT) \
1134 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 2)), CXT); \
1135 emit_move_insn (gen_rtx_MEM (HImode, plus_constant (TRAMP, 6)), FNADDR); \
1139 /* Some machines may desire to change what optimizations are
1140 performed for various optimization levels. This macro, if
1141 defined, is executed once just after the optimization level is
1142 determined and before the remainder of the command options have
1143 been parsed. Values set in this macro are used as the default
1144 values for the other command line options.
1146 LEVEL is the optimization level specified; 2 if -O2 is
1147 specified, 1 if -O is specified, and 0 if neither is specified. */
1149 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \
1154 flag_inline_functions = 1; \
1155 flag_omit_frame_pointer = 1; \
1156 /* flag_unroll_loops = 1; */ \
1160 /* there is no point in avoiding branches on a pdp,
1161 since branches are really cheap - I just want to find out
1162 how much difference the BRANCH_COST macro makes in code */
1163 #define BRANCH_COST (TARGET_BRANCH_CHEAP ? 0 : 1)
1166 #define COMPARE_FLAG_MODE HImode