1 /* Configuration for GCC-compiler for PA-RISC.
2 Copyright (C) 1999, 2000, 2003 Free Software Foundation, Inc.
4 This file is part of GCC.
6 GCC is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2, or (at your option)
11 GCC is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GCC; see the file COPYING. If not, write to
18 the Free Software Foundation, 59 Temple Place - Suite 330,
19 Boston, MA 02111-1307, USA. */
21 /* Standard register usage.
23 It is safe to refer to actual register numbers in this file. */
25 /* Number of actual hardware registers.
26 The hardware registers are assigned numbers for the compiler
27 from 0 to just below FIRST_PSEUDO_REGISTER.
28 All registers that the compiler knows about must be given numbers,
29 even those that are not normally considered general registers.
31 HP-PA 2.0w has 32 fullword registers and 32 floating point
32 registers. However, the floating point registers behave
33 differently: the left and right halves of registers are addressable
36 Due to limitations within GCC itself, we do not expose the left/right
37 half addressability when in wide mode. This is not a major performance
38 issue as using the halves independently triggers false dependency stalls
41 #define FIRST_PSEUDO_REGISTER 61 /* 32 general regs + 28 fp regs +
44 /* 1 for registers that have pervasive standard uses
45 and are not available for the register allocator.
47 On the HP-PA, these are:
48 Reg 0 = 0 (hardware). However, 0 is used for condition code,
50 Reg 1 = ADDIL target/Temporary (hardware).
51 Reg 2 = Return Pointer
53 Reg 4 = Frame Pointer (>8k varying frame with HP compilers only)
54 Reg 4-18 = Preserved Registers
55 Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme.
56 Reg 20-22 = Temporary Registers
57 Reg 23-26 = Temporary/Parameter Registers
58 Reg 27 = Global Data Pointer (hp)
59 Reg 28 = Temporary/Return Value register
60 Reg 29 = Temporary/Static Chain/Return Value register #2
61 Reg 30 = stack pointer
62 Reg 31 = Temporary/Millicode Return Pointer (hp)
64 Freg 0-3 = Status Registers -- Not known to the compiler.
65 Freg 4-7 = Arguments/Return Value
66 Freg 8-11 = Temporary Registers
67 Freg 12-21 = Preserved Registers
68 Freg 22-31 = Temporary Registers
72 #define FIXED_REGISTERS \
73 {0, 0, 0, 0, 0, 0, 0, 0, \
74 0, 0, 0, 0, 0, 0, 0, 0, \
75 0, 0, 0, 0, 0, 0, 0, 0, \
76 0, 0, 0, 1, 0, 0, 1, 0, \
78 0, 0, 0, 0, 0, 0, 0, 0, \
79 0, 0, 0, 0, 0, 0, 0, 0, \
80 0, 0, 0, 0, 0, 0, 0, 0, \
82 /* shift register */ \
85 /* 1 for registers not available across function calls.
86 These must include the FIXED_REGISTERS and also any
87 registers that can be used without being saved.
88 The latter must include the registers where values are returned
89 and the register where structure-value addresses are passed.
90 Aside from that, you can include as many other registers as you like. */
91 #define CALL_USED_REGISTERS \
92 {1, 1, 1, 0, 0, 0, 0, 0, \
93 0, 0, 0, 0, 0, 0, 0, 0, \
94 0, 0, 0, 1, 1, 1, 1, 1, \
95 1, 1, 1, 1, 1, 1, 1, 1, \
97 1, 1, 1, 1, 1, 1, 1, 1, \
98 0, 0, 0, 0, 0, 0, 0, 0, \
99 0, 0, 1, 1, 1, 1, 1, 1, \
101 /* shift register */ \
104 #define CONDITIONAL_REGISTER_USAGE \
107 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\
109 for (i = FP_REG_FIRST; i < FP_REG_LAST; i++)\
110 fixed_regs[i] = call_used_regs[i] = 1; \
113 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
116 /* Allocate the call used registers first. This should minimize
117 the number of registers that need to be saved (as call used
118 registers will generally not be allocated across a call).
120 Experimentation has shown slightly better results by allocating
123 FP registers are ordered so that all L registers are selected before
124 R registers. This works around a false dependency interlock on the
125 PA8000 when accessing the high and low parts of an FP register
128 #define REG_ALLOC_ORDER \
130 /* caller-saved fp regs. */ \
131 50, 51, 52, 53, 54, 55, 56, 57, \
132 58, 59, 36, 37, 38, 39, 32, 33, \
134 /* caller-saved general regs. */ \
135 19, 20, 21, 22, 23, 24, 25, 26, \
137 /* callee-saved fp regs. */ \
138 40, 41, 42, 43, 44, 45, 46, 47, \
140 /* callee-saved general regs. */ \
141 3, 4, 5, 6, 7, 8, 9, 10, \
142 11, 12, 13, 14, 15, 16, 17, 18, \
143 /* special registers. */ \
147 /* Return number of consecutive hard regs needed starting at reg REGNO
148 to hold something of mode MODE.
149 This is ordinarily the length in words of a value of mode MODE
150 but can be less for certain modes in special long registers.
152 For PA64, GPRs and FPRs hold 64 bits worth (we ignore the 32bit
153 addressability of the FPRs). ie, we pretend each register holds
154 precisely WORD_SIZE bits. */
155 #define HARD_REGNO_NREGS(REGNO, MODE) \
156 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
158 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
159 On the HP-PA, the cpu registers can hold any mode. We
160 force this to be an even register is it cannot hold the full mode. */
161 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
163 ? (MODE) == CCmode || (MODE) == CCFPmode \
164 /* Make wide modes be in aligned registers. */ \
165 : (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD \
166 || (GET_MODE_SIZE (MODE) <= 2 * UNITS_PER_WORD && ((REGNO) & 1) == 0)))
168 /* How to renumber registers for dbx and gdb.
170 Registers 0 - 31 remain unchanged.
172 Registers 32 - 60 are mapped to 72, 74, 76 ...
174 Register 88 is mapped to 32. */
176 #define DBX_REGISTER_NUMBER(REGNO) \
177 ((REGNO) <= 31 ? (REGNO) : \
178 ((REGNO) > 31 && (REGNO) <= 60 ? (REGNO - 32) * 2 + 72 : 32))
180 /* We must not use the DBX register numbers for the DWARF 2 CFA column
181 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER.
182 Instead use the identity mapping. */
183 #define DWARF_FRAME_REGNUM(REG) REG
185 /* Define the classes of registers for register constraints in the
186 machine description. Also define ranges of constants.
188 One of the classes must always be named ALL_REGS and include all hard regs.
189 If there is more than one class, another class must be named NO_REGS
190 and contain no registers.
192 The name GENERAL_REGS must be the name of a class (or an alias for
193 another name such as ALL_REGS). This is the class of registers
194 that is allowed by "g" or "r" in a register constraint.
195 Also, registers outside this class are allocated only when
196 instructions express preferences for them.
198 The classes must be numbered in nondecreasing order; that is,
199 a larger-numbered class must never be contained completely
200 in a smaller-numbered class.
202 For any two classes, it is very desirable that there be another
203 class that represents their union. */
205 /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs,
206 1.1 fp regs, and the high 1.1 fp regs, to which the operands of
207 fmpyadd and fmpysub are restricted. */
209 enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FPUPPER_REGS, FP_REGS,
210 GENERAL_OR_FP_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES};
212 #define N_REG_CLASSES (int) LIM_REG_CLASSES
214 /* Give names of register classes as strings for dump file. */
216 #define REG_CLASS_NAMES \
217 {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FPUPPER_REGS", "FP_REGS", \
218 "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"}
220 /* Define which registers fit in which classes.
221 This is an initializer for a vector of HARD_REG_SET
222 of length N_REG_CLASSES. Register 0, the "condition code" register,
225 #define REG_CLASS_CONTENTS \
226 {{0x00000000, 0x00000000}, /* NO_REGS */ \
227 {0x00000002, 0x00000000}, /* R1_REGS */ \
228 {0xfffffffe, 0x00000000}, /* GENERAL_REGS */ \
229 {0x00000000, 0x00000000}, /* FPUPPER_REGS */ \
230 {0x00000000, 0x0fffffff}, /* FP_REGS */ \
231 {0xfffffffe, 0x0fffffff}, /* GENERAL_OR_FP_REGS */ \
232 {0x00000000, 0x10000000}, /* SHIFT_REGS */ \
233 {0xfffffffe, 0x1fffffff}} /* ALL_REGS */
235 /* Defines invalid mode changes.
237 SImode loads to floating-point registers are not zero-extended.
238 The definition for LOAD_EXTEND_OP specifies that integer loads
239 narrower than BITS_PER_WORD will be zero-extended. As a result,
240 we inhibit changes from SImode unless they are to a mode that is
241 identical in size. */
243 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \
244 ((FROM) == SImode && GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \
245 ? reg_classes_intersect_p (CLASS, FP_REGS) : 0)
247 /* Return the class number of the smallest class containing
248 reg number REGNO. This could be a conditional expression
249 or could index an array. */
251 #define REGNO_REG_CLASS(REGNO) \
252 ((REGNO) == 0 ? NO_REGS \
253 : (REGNO) == 1 ? R1_REGS \
254 : (REGNO) < 32 ? GENERAL_REGS \
255 : (REGNO) < 60 ? FP_REGS \
259 /* Get reg_class from a letter such as appears in the machine description. */
260 /* Keep 'x' for backward compatibility with user asm. */
261 #define REG_CLASS_FROM_LETTER(C) \
262 ((C) == 'f' ? FP_REGS : \
263 (C) == 'y' ? FP_REGS : \
264 (C) == 'x' ? FP_REGS : \
265 (C) == 'q' ? SHIFT_REGS : \
266 (C) == 'a' ? R1_REGS : \
267 (C) == 'Z' ? ALL_REGS : NO_REGS)
270 /* Return the maximum number of consecutive registers
271 needed to represent mode MODE in a register of class CLASS. */
272 #define CLASS_MAX_NREGS(CLASS, MODE) \
273 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
275 /* 1 if N is a possible register number for function argument passing. */
277 #define FUNCTION_ARG_REGNO_P(N) \
278 ((((N) >= 19) && (N) <= 26) \
279 || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39))
281 /* How to refer to registers in assembler output.
282 This sequence is indexed by compiler's hard-register-number (see above). */
284 #define REGISTER_NAMES \
285 {"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \
286 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \
287 "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \
288 "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \
289 "%fr4", "%fr5", "%fr6", "%fr7", "%fr8", "%fr9", "%fr10", "%fr11", \
290 "%fr12", "%fr13", "%fr14", "%fr15", "%fr16", "%fr17", "%fr18", "%fr19", \
291 "%fr20", "%fr21", "%fr22", "%fr23", "%fr24", "%fr25", "%fr26", "%fr27", \
292 "%fr28", "%fr29", "%fr30", "%fr31", "SAR"}
294 #define ADDITIONAL_REGISTER_NAMES \
297 #define FP_SAVED_REG_LAST 49
298 #define FP_SAVED_REG_FIRST 40
299 #define FP_REG_STEP 1
300 #define FP_REG_FIRST 32
301 #define FP_REG_LAST 59