1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; millicode call delay slot description. Note it disallows delay slot
109 ;; when TARGET_PORTABLE_RUNTIME is true.
110 (define_delay (eq_attr "type" "milli")
111 [(and (eq_attr "in_call_delay" "true")
112 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0)))
115 ;; Return and other similar instructions.
116 (define_delay (eq_attr "type" "branch,parallel_branch")
117 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
119 ;; Floating point conditional branch delay slot description and
120 (define_delay (eq_attr "type" "fbranch")
121 [(eq_attr "in_branch_delay" "true")
122 (eq_attr "in_nullified_branch_delay" "true")
125 ;; Integer conditional branch delay slot description.
126 ;; Nullification of conditional branches on the PA is dependent on the
127 ;; direction of the branch. Forward branches nullify true and
128 ;; backward branches nullify false. If the direction is unknown
129 ;; then nullification is not allowed.
130 (define_delay (eq_attr "type" "cbranch")
131 [(eq_attr "in_branch_delay" "true")
132 (and (eq_attr "in_nullified_branch_delay" "true")
133 (attr_flag "forward"))
134 (and (eq_attr "in_nullified_branch_delay" "true")
135 (attr_flag "backward"))])
137 (define_delay (and (eq_attr "type" "uncond_branch")
138 (eq (symbol_ref "following_call (insn)")
140 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
142 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
143 ;; load: 2, fpload: 3
144 ;; store, fpstore: 3, no D-cache operations should be scheduled.
146 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
148 ;; Instruction Time Unit Minimum Distance (unit contention)
155 ;; fmpyadd 3 ALU,MPY 2
156 ;; fmpysub 3 ALU,MPY 2
157 ;; fmpycfxt 3 ALU,MPY 2
160 ;; fdiv,sgl 10 MPY 10
161 ;; fdiv,dbl 12 MPY 12
162 ;; fsqrt,sgl 14 MPY 14
163 ;; fsqrt,dbl 18 MPY 18
165 ;; We don't model fmpyadd/fmpysub properly as those instructions
166 ;; keep both the FP ALU and MPY units busy. Given that these
167 ;; processors are obsolete, I'm not going to spend the time to
168 ;; model those instructions correctly.
170 (define_automaton "pa700")
171 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
173 (define_insn_reservation "W0" 4
174 (and (eq_attr "type" "fpcc")
175 (eq_attr "cpu" "700"))
178 (define_insn_reservation "W1" 3
179 (and (eq_attr "type" "fpalu")
180 (eq_attr "cpu" "700"))
183 (define_insn_reservation "W2" 3
184 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
185 (eq_attr "cpu" "700"))
188 (define_insn_reservation "W3" 10
189 (and (eq_attr "type" "fpdivsgl")
190 (eq_attr "cpu" "700"))
193 (define_insn_reservation "W4" 12
194 (and (eq_attr "type" "fpdivdbl")
195 (eq_attr "cpu" "700"))
198 (define_insn_reservation "W5" 14
199 (and (eq_attr "type" "fpsqrtsgl")
200 (eq_attr "cpu" "700"))
203 (define_insn_reservation "W6" 18
204 (and (eq_attr "type" "fpsqrtdbl")
205 (eq_attr "cpu" "700"))
208 (define_insn_reservation "W7" 2
209 (and (eq_attr "type" "load,fpload")
210 (eq_attr "cpu" "700"))
213 (define_insn_reservation "W8" 3
214 (and (eq_attr "type" "store,fpstore")
215 (eq_attr "cpu" "700"))
218 (define_insn_reservation "W9" 1
219 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
220 (eq_attr "cpu" "700"))
223 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
224 ;; floating point computations with non-floating point computations (fp loads
225 ;; and stores are not fp computations).
227 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
228 ;; take two cycles, during which no Dcache operations should be scheduled.
229 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
230 ;; all have the same memory characteristics if one disregards cache misses.
232 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
234 ;; Instruction Time Unit Minimum Distance (unit contention)
241 ;; fmpyadd 2 ALU,MPY 1
242 ;; fmpysub 2 ALU,MPY 1
243 ;; fmpycfxt 2 ALU,MPY 1
247 ;; fdiv,dbl 15 DIV 15
249 ;; fsqrt,dbl 15 DIV 15
251 ;; We don't really model the FP ALU/MPY units properly (they are
252 ;; distinct subunits in the FP unit). However, there can never be
253 ;; a functional unit; conflict given the latency and issue rates
256 (define_automaton "pa7100")
257 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
259 (define_insn_reservation "X0" 2
260 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
261 (eq_attr "cpu" "7100"))
264 (define_insn_reservation "X1" 8
265 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
266 (eq_attr "cpu" "7100"))
267 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
269 (define_insn_reservation "X2" 15
270 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
271 (eq_attr "cpu" "7100"))
272 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
274 (define_insn_reservation "X3" 2
275 (and (eq_attr "type" "load,fpload")
276 (eq_attr "cpu" "7100"))
279 (define_insn_reservation "X4" 2
280 (and (eq_attr "type" "store,fpstore")
281 (eq_attr "cpu" "7100"))
282 "i_7100+mem_7100,mem_7100")
284 (define_insn_reservation "X5" 1
285 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
286 (eq_attr "cpu" "7100"))
289 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
291 ;; Instruction Time Unit Minimum Distance (unit contention)
298 ;; fmpyadd,sgl 2 ALU,MPY 1
299 ;; fmpyadd,dbl 3 ALU,MPY 2
300 ;; fmpysub,sgl 2 ALU,MPY 1
301 ;; fmpysub,dbl 3 ALU,MPY 2
302 ;; fmpycfxt,sgl 2 ALU,MPY 1
303 ;; fmpycfxt,dbl 3 ALU,MPY 2
308 ;; fdiv,dbl 15 DIV 15
310 ;; fsqrt,dbl 15 DIV 15
312 ;; The PA7200 is just like the PA7100LC except that there is
313 ;; no store-store penalty.
315 ;; The PA7300 is just like the PA7200 except that there is
316 ;; no store-load penalty.
318 ;; Note there are some aspects of the 7100LC we are not modeling
319 ;; at the moment. I'll be reviewing the 7100LC scheduling info
320 ;; shortly and updating this description.
326 ;; other issue modeling
328 (define_automaton "pa7100lc")
329 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
330 (define_cpu_unit "fpalu_7100lc,fpmul_7100lc" "pa7100lc")
331 (define_cpu_unit "mem_7100lc" "pa7100lc")
333 (define_insn_reservation "Y0" 2
334 (and (eq_attr "type" "fpcc,fpalu")
335 (eq_attr "cpu" "7100LC,7200,7300"))
336 "f_7100lc,fpalu_7100lc")
338 ;; Double precision multiplies lock the entire CPU for one
339 ;; cycle. There is no way to avoid this lock and trying to
340 ;; schedule around the lock is pointless and thus there is no
341 ;; value in trying to model this lock. Not modeling the lock
342 ;; allows for a smaller DFA and may reduce register pressure.
343 (define_insn_reservation "Y1" 2
344 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
345 (eq_attr "cpu" "7100LC,7200,7300"))
346 "f_7100lc,fpmul_7100lc")
348 ;; fp division and sqrt instructions lock the entire CPU for
349 ;; 7 cycles (single precision) or 14 cycles (double precision).
350 ;; There is no way to avoid this lock and trying to schedule
351 ;; around the lock is pointless and thus there is no value in
352 ;; trying to model this lock. Not modeling the lock allows
353 ;; for a smaller DFA and may reduce register pressure.
354 (define_insn_reservation "Y2" 1
355 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
356 (eq_attr "cpu" "7100LC,7200,7300"))
359 (define_insn_reservation "Y3" 2
360 (and (eq_attr "type" "load,fpload")
361 (eq_attr "cpu" "7100LC,7200,7300"))
362 "i1_7100lc+mem_7100lc")
364 (define_insn_reservation "Y4" 2
365 (and (eq_attr "type" "store,fpstore")
366 (eq_attr "cpu" "7100LC"))
367 "i1_7100lc+mem_7100lc,mem_7100lc")
369 (define_insn_reservation "Y5" 1
370 (and (eq_attr "type" "shift,nullshift")
371 (eq_attr "cpu" "7100LC,7200,7300"))
374 (define_insn_reservation "Y6" 1
375 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
376 (eq_attr "cpu" "7100LC,7200,7300"))
377 "(i0_7100lc|i1_7100lc)")
379 ;; The 7200 has a store-load penalty
380 (define_insn_reservation "Y7" 2
381 (and (eq_attr "type" "store,fpstore")
382 (eq_attr "cpu" "7200"))
383 "i1_7100lc,mem_7100lc")
385 ;; The 7300 has no penalty for store-store or store-load
386 (define_insn_reservation "Y8" 2
387 (and (eq_attr "type" "store,fpstore")
388 (eq_attr "cpu" "7300"))
391 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
392 ;; traditional architecture.
394 ;; The PA8000 has a large (56) entry reorder buffer that is split between
395 ;; memory and non-memory operations.
397 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
398 ;; the function units, with the exception of branches and multi-output
399 ;; instructions. The PA8000 can retire two non-memory operations per cycle
400 ;; and two memory operations per cycle, only one of which may be a store.
402 ;; Given the large reorder buffer, the processor can hide most latencies.
403 ;; According to HP, they've got the best results by scheduling for retirement
404 ;; bandwidth with limited latency scheduling for floating point operations.
405 ;; Latency for integer operations and memory references is ignored.
408 ;; We claim floating point operations have a 2 cycle latency and are
409 ;; fully pipelined, except for div and sqrt which are not pipelined and
410 ;; take from 17 to 31 cycles to complete.
412 ;; It's worth noting that there is no way to saturate all the functional
413 ;; units on the PA8000 as there is not enough issue bandwidth.
415 (define_automaton "pa8000")
416 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
417 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
418 (define_cpu_unit "store_8000" "pa8000")
419 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
420 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
421 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
422 (define_reservation "im_8000" "im0_8000 | im1_8000")
423 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
424 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
425 (define_reservation "f_8000" "f0_8000 | f1_8000")
426 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
428 ;; We can issue any two memops per cycle, but we can only retire
429 ;; one memory store per cycle. We assume that the reorder buffer
430 ;; will hide any memory latencies per HP's recommendation.
431 (define_insn_reservation "Z0" 0
433 (eq_attr "type" "load,fpload")
434 (eq_attr "cpu" "8000"))
437 (define_insn_reservation "Z1" 0
439 (eq_attr "type" "store,fpstore")
440 (eq_attr "cpu" "8000"))
441 "im_8000,rm_8000+store_8000")
443 ;; We can issue and retire two non-memory operations per cycle with
444 ;; a few exceptions (branches). This group catches those we want
445 ;; to assume have zero latency.
446 (define_insn_reservation "Z2" 0
448 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
449 (eq_attr "cpu" "8000"))
452 ;; Branches use both slots in the non-memory issue and
454 (define_insn_reservation "Z3" 0
456 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
457 (eq_attr "cpu" "8000"))
458 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
460 ;; We partial latency schedule the floating point units.
461 ;; They can issue/retire two at a time in the non-memory
462 ;; units. We fix their latency at 2 cycles and they
463 ;; are fully pipelined.
464 (define_insn_reservation "Z4" 1
466 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
467 (eq_attr "cpu" "8000"))
468 "inm_8000,f_8000,rnm_8000")
470 ;; The fdivsqrt units are not pipelined and have a very long latency.
471 ;; To keep the DFA from exploding, we do not show all the
472 ;; reservations for the divsqrt unit.
473 (define_insn_reservation "Z5" 17
475 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
476 (eq_attr "cpu" "8000"))
477 "inm_8000,fdivsqrt_8000*6,rnm_8000")
479 (define_insn_reservation "Z6" 31
481 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
482 (eq_attr "cpu" "8000"))
483 "inm_8000,fdivsqrt_8000*6,rnm_8000")
487 ;; Compare instructions.
488 ;; This controls RTL generation and register allocation.
490 ;; We generate RTL for comparisons and branches by having the cmpxx
491 ;; patterns store away the operands. Then, the scc and bcc patterns
492 ;; emit RTL for both the compare and the branch.
495 (define_expand "cmpdi"
497 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
498 (match_operand:DI 1 "register_operand" "")))]
503 hppa_compare_op0 = operands[0];
504 hppa_compare_op1 = operands[1];
505 hppa_branch_type = CMP_SI;
509 (define_expand "cmpsi"
511 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
512 (match_operand:SI 1 "arith5_operand" "")))]
516 hppa_compare_op0 = operands[0];
517 hppa_compare_op1 = operands[1];
518 hppa_branch_type = CMP_SI;
522 (define_expand "cmpsf"
524 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
525 (match_operand:SF 1 "reg_or_0_operand" "")))]
526 "! TARGET_SOFT_FLOAT"
529 hppa_compare_op0 = operands[0];
530 hppa_compare_op1 = operands[1];
531 hppa_branch_type = CMP_SF;
535 (define_expand "cmpdf"
537 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
538 (match_operand:DF 1 "reg_or_0_operand" "")))]
539 "! TARGET_SOFT_FLOAT"
542 hppa_compare_op0 = operands[0];
543 hppa_compare_op1 = operands[1];
544 hppa_branch_type = CMP_DF;
550 (match_operator:CCFP 2 "comparison_operator"
551 [(match_operand:SF 0 "reg_or_0_operand" "fG")
552 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
553 "! TARGET_SOFT_FLOAT"
554 "fcmp,sgl,%Y2 %f0,%f1"
555 [(set_attr "length" "4")
556 (set_attr "type" "fpcc")])
560 (match_operator:CCFP 2 "comparison_operator"
561 [(match_operand:DF 0 "reg_or_0_operand" "fG")
562 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
563 "! TARGET_SOFT_FLOAT"
564 "fcmp,dbl,%Y2 %f0,%f1"
565 [(set_attr "length" "4")
566 (set_attr "type" "fpcc")])
571 [(set (match_operand:SI 0 "register_operand" "")
577 /* fp scc patterns rarely match, and are not a win on the PA. */
578 if (hppa_branch_type != CMP_SI)
580 /* set up operands from compare. */
581 operands[1] = hppa_compare_op0;
582 operands[2] = hppa_compare_op1;
583 /* fall through and generate default code */
587 [(set (match_operand:SI 0 "register_operand" "")
593 /* fp scc patterns rarely match, and are not a win on the PA. */
594 if (hppa_branch_type != CMP_SI)
596 operands[1] = hppa_compare_op0;
597 operands[2] = hppa_compare_op1;
601 [(set (match_operand:SI 0 "register_operand" "")
607 /* fp scc patterns rarely match, and are not a win on the PA. */
608 if (hppa_branch_type != CMP_SI)
610 operands[1] = hppa_compare_op0;
611 operands[2] = hppa_compare_op1;
615 [(set (match_operand:SI 0 "register_operand" "")
621 /* fp scc patterns rarely match, and are not a win on the PA. */
622 if (hppa_branch_type != CMP_SI)
624 operands[1] = hppa_compare_op0;
625 operands[2] = hppa_compare_op1;
629 [(set (match_operand:SI 0 "register_operand" "")
635 /* fp scc patterns rarely match, and are not a win on the PA. */
636 if (hppa_branch_type != CMP_SI)
638 operands[1] = hppa_compare_op0;
639 operands[2] = hppa_compare_op1;
643 [(set (match_operand:SI 0 "register_operand" "")
649 /* fp scc patterns rarely match, and are not a win on the PA. */
650 if (hppa_branch_type != CMP_SI)
652 operands[1] = hppa_compare_op0;
653 operands[2] = hppa_compare_op1;
656 (define_expand "sltu"
657 [(set (match_operand:SI 0 "register_operand" "")
658 (ltu:SI (match_dup 1)
663 if (hppa_branch_type != CMP_SI)
665 operands[1] = hppa_compare_op0;
666 operands[2] = hppa_compare_op1;
669 (define_expand "sgtu"
670 [(set (match_operand:SI 0 "register_operand" "")
671 (gtu:SI (match_dup 1)
676 if (hppa_branch_type != CMP_SI)
678 operands[1] = hppa_compare_op0;
679 operands[2] = hppa_compare_op1;
682 (define_expand "sleu"
683 [(set (match_operand:SI 0 "register_operand" "")
684 (leu:SI (match_dup 1)
689 if (hppa_branch_type != CMP_SI)
691 operands[1] = hppa_compare_op0;
692 operands[2] = hppa_compare_op1;
695 (define_expand "sgeu"
696 [(set (match_operand:SI 0 "register_operand" "")
697 (geu:SI (match_dup 1)
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
708 ;; Instruction canonicalization puts immediate operands second, which
709 ;; is the reverse of what we want.
712 [(set (match_operand:SI 0 "register_operand" "=r")
713 (match_operator:SI 3 "comparison_operator"
714 [(match_operand:SI 1 "register_operand" "r")
715 (match_operand:SI 2 "arith11_operand" "rI")]))]
717 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
718 [(set_attr "type" "binary")
719 (set_attr "length" "8")])
722 [(set (match_operand:DI 0 "register_operand" "=r")
723 (match_operator:DI 3 "comparison_operator"
724 [(match_operand:DI 1 "register_operand" "r")
725 (match_operand:DI 2 "arith11_operand" "rI")]))]
727 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
728 [(set_attr "type" "binary")
729 (set_attr "length" "8")])
731 (define_insn "iorscc"
732 [(set (match_operand:SI 0 "register_operand" "=r")
733 (ior:SI (match_operator:SI 3 "comparison_operator"
734 [(match_operand:SI 1 "register_operand" "r")
735 (match_operand:SI 2 "arith11_operand" "rI")])
736 (match_operator:SI 6 "comparison_operator"
737 [(match_operand:SI 4 "register_operand" "r")
738 (match_operand:SI 5 "arith11_operand" "rI")])))]
740 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
741 [(set_attr "type" "binary")
742 (set_attr "length" "12")])
745 [(set (match_operand:DI 0 "register_operand" "=r")
746 (ior:DI (match_operator:DI 3 "comparison_operator"
747 [(match_operand:DI 1 "register_operand" "r")
748 (match_operand:DI 2 "arith11_operand" "rI")])
749 (match_operator:DI 6 "comparison_operator"
750 [(match_operand:DI 4 "register_operand" "r")
751 (match_operand:DI 5 "arith11_operand" "rI")])))]
753 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
754 [(set_attr "type" "binary")
755 (set_attr "length" "12")])
757 ;; Combiner patterns for common operations performed with the output
758 ;; from an scc insn (negscc and incscc).
759 (define_insn "negscc"
760 [(set (match_operand:SI 0 "register_operand" "=r")
761 (neg:SI (match_operator:SI 3 "comparison_operator"
762 [(match_operand:SI 1 "register_operand" "r")
763 (match_operand:SI 2 "arith11_operand" "rI")])))]
765 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
766 [(set_attr "type" "binary")
767 (set_attr "length" "8")])
770 [(set (match_operand:DI 0 "register_operand" "=r")
771 (neg:DI (match_operator:DI 3 "comparison_operator"
772 [(match_operand:DI 1 "register_operand" "r")
773 (match_operand:DI 2 "arith11_operand" "rI")])))]
775 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
776 [(set_attr "type" "binary")
777 (set_attr "length" "8")])
779 ;; Patterns for adding/subtracting the result of a boolean expression from
780 ;; a register. First we have special patterns that make use of the carry
781 ;; bit, and output only two instructions. For the cases we can't in
782 ;; general do in two instructions, the incscc pattern at the end outputs
783 ;; two or three instructions.
786 [(set (match_operand:SI 0 "register_operand" "=r")
787 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
788 (match_operand:SI 3 "arith11_operand" "rI"))
789 (match_operand:SI 1 "register_operand" "r")))]
791 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
792 [(set_attr "type" "binary")
793 (set_attr "length" "8")])
796 [(set (match_operand:DI 0 "register_operand" "=r")
797 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
798 (match_operand:DI 3 "arith11_operand" "rI"))
799 (match_operand:DI 1 "register_operand" "r")))]
801 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
802 [(set_attr "type" "binary")
803 (set_attr "length" "8")])
805 ; This need only accept registers for op3, since canonicalization
806 ; replaces geu with gtu when op3 is an integer.
808 [(set (match_operand:SI 0 "register_operand" "=r")
809 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
810 (match_operand:SI 3 "register_operand" "r"))
811 (match_operand:SI 1 "register_operand" "r")))]
813 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
814 [(set_attr "type" "binary")
815 (set_attr "length" "8")])
818 [(set (match_operand:DI 0 "register_operand" "=r")
819 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
820 (match_operand:DI 3 "register_operand" "r"))
821 (match_operand:DI 1 "register_operand" "r")))]
823 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
824 [(set_attr "type" "binary")
825 (set_attr "length" "8")])
827 ; Match only integers for op3 here. This is used as canonical form of the
828 ; geu pattern when op3 is an integer. Don't match registers since we can't
829 ; make better code than the general incscc pattern.
831 [(set (match_operand:SI 0 "register_operand" "=r")
832 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
833 (match_operand:SI 3 "int11_operand" "I"))
834 (match_operand:SI 1 "register_operand" "r")))]
836 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
837 [(set_attr "type" "binary")
838 (set_attr "length" "8")])
841 [(set (match_operand:DI 0 "register_operand" "=r")
842 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
843 (match_operand:DI 3 "int11_operand" "I"))
844 (match_operand:DI 1 "register_operand" "r")))]
846 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
847 [(set_attr "type" "binary")
848 (set_attr "length" "8")])
850 (define_insn "incscc"
851 [(set (match_operand:SI 0 "register_operand" "=r,r")
852 (plus:SI (match_operator:SI 4 "comparison_operator"
853 [(match_operand:SI 2 "register_operand" "r,r")
854 (match_operand:SI 3 "arith11_operand" "rI,rI")])
855 (match_operand:SI 1 "register_operand" "0,?r")))]
858 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
859 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
860 [(set_attr "type" "binary,binary")
861 (set_attr "length" "8,12")])
864 [(set (match_operand:DI 0 "register_operand" "=r,r")
865 (plus:DI (match_operator:DI 4 "comparison_operator"
866 [(match_operand:DI 2 "register_operand" "r,r")
867 (match_operand:DI 3 "arith11_operand" "rI,rI")])
868 (match_operand:DI 1 "register_operand" "0,?r")))]
871 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
872 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
873 [(set_attr "type" "binary,binary")
874 (set_attr "length" "8,12")])
877 [(set (match_operand:SI 0 "register_operand" "=r")
878 (minus:SI (match_operand:SI 1 "register_operand" "r")
879 (gtu:SI (match_operand:SI 2 "register_operand" "r")
880 (match_operand:SI 3 "arith11_operand" "rI"))))]
882 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
883 [(set_attr "type" "binary")
884 (set_attr "length" "8")])
887 [(set (match_operand:DI 0 "register_operand" "=r")
888 (minus:DI (match_operand:DI 1 "register_operand" "r")
889 (gtu:DI (match_operand:DI 2 "register_operand" "r")
890 (match_operand:DI 3 "arith11_operand" "rI"))))]
892 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
893 [(set_attr "type" "binary")
894 (set_attr "length" "8")])
897 [(set (match_operand:SI 0 "register_operand" "=r")
898 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
899 (gtu:SI (match_operand:SI 2 "register_operand" "r")
900 (match_operand:SI 3 "arith11_operand" "rI")))
901 (match_operand:SI 4 "register_operand" "r")))]
903 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
904 [(set_attr "type" "binary")
905 (set_attr "length" "8")])
908 [(set (match_operand:DI 0 "register_operand" "=r")
909 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
910 (gtu:DI (match_operand:DI 2 "register_operand" "r")
911 (match_operand:DI 3 "arith11_operand" "rI")))
912 (match_operand:DI 4 "register_operand" "r")))]
914 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
915 [(set_attr "type" "binary")
916 (set_attr "length" "8")])
918 ; This need only accept registers for op3, since canonicalization
919 ; replaces ltu with leu when op3 is an integer.
921 [(set (match_operand:SI 0 "register_operand" "=r")
922 (minus:SI (match_operand:SI 1 "register_operand" "r")
923 (ltu:SI (match_operand:SI 2 "register_operand" "r")
924 (match_operand:SI 3 "register_operand" "r"))))]
926 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
927 [(set_attr "type" "binary")
928 (set_attr "length" "8")])
931 [(set (match_operand:DI 0 "register_operand" "=r")
932 (minus:DI (match_operand:DI 1 "register_operand" "r")
933 (ltu:DI (match_operand:DI 2 "register_operand" "r")
934 (match_operand:DI 3 "register_operand" "r"))))]
936 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
937 [(set_attr "type" "binary")
938 (set_attr "length" "8")])
941 [(set (match_operand:SI 0 "register_operand" "=r")
942 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
943 (ltu:SI (match_operand:SI 2 "register_operand" "r")
944 (match_operand:SI 3 "register_operand" "r")))
945 (match_operand:SI 4 "register_operand" "r")))]
947 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
948 [(set_attr "type" "binary")
949 (set_attr "length" "8")])
952 [(set (match_operand:DI 0 "register_operand" "=r")
953 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
954 (ltu:DI (match_operand:DI 2 "register_operand" "r")
955 (match_operand:DI 3 "register_operand" "r")))
956 (match_operand:DI 4 "register_operand" "r")))]
958 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
959 [(set_attr "type" "binary")
960 (set_attr "length" "8")])
962 ; Match only integers for op3 here. This is used as canonical form of the
963 ; ltu pattern when op3 is an integer. Don't match registers since we can't
964 ; make better code than the general incscc pattern.
966 [(set (match_operand:SI 0 "register_operand" "=r")
967 (minus:SI (match_operand:SI 1 "register_operand" "r")
968 (leu:SI (match_operand:SI 2 "register_operand" "r")
969 (match_operand:SI 3 "int11_operand" "I"))))]
971 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
972 [(set_attr "type" "binary")
973 (set_attr "length" "8")])
976 [(set (match_operand:DI 0 "register_operand" "=r")
977 (minus:DI (match_operand:DI 1 "register_operand" "r")
978 (leu:DI (match_operand:DI 2 "register_operand" "r")
979 (match_operand:DI 3 "int11_operand" "I"))))]
981 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
982 [(set_attr "type" "binary")
983 (set_attr "length" "8")])
986 [(set (match_operand:SI 0 "register_operand" "=r")
987 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
988 (leu:SI (match_operand:SI 2 "register_operand" "r")
989 (match_operand:SI 3 "int11_operand" "I")))
990 (match_operand:SI 4 "register_operand" "r")))]
992 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
993 [(set_attr "type" "binary")
994 (set_attr "length" "8")])
997 [(set (match_operand:DI 0 "register_operand" "=r")
998 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
999 (leu:DI (match_operand:DI 2 "register_operand" "r")
1000 (match_operand:DI 3 "int11_operand" "I")))
1001 (match_operand:DI 4 "register_operand" "r")))]
1003 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1004 [(set_attr "type" "binary")
1005 (set_attr "length" "8")])
1007 (define_insn "decscc"
1008 [(set (match_operand:SI 0 "register_operand" "=r,r")
1009 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1010 (match_operator:SI 4 "comparison_operator"
1011 [(match_operand:SI 2 "register_operand" "r,r")
1012 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1015 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1016 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1017 [(set_attr "type" "binary,binary")
1018 (set_attr "length" "8,12")])
1021 [(set (match_operand:DI 0 "register_operand" "=r,r")
1022 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1023 (match_operator:DI 4 "comparison_operator"
1024 [(match_operand:DI 2 "register_operand" "r,r")
1025 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1028 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1029 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1030 [(set_attr "type" "binary,binary")
1031 (set_attr "length" "8,12")])
1033 ; Patterns for max and min. (There is no need for an earlyclobber in the
1034 ; last alternative since the middle alternative will match if op0 == op1.)
1036 (define_insn "sminsi3"
1037 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1038 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1039 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1042 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1043 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1044 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1045 [(set_attr "type" "multi,multi,multi")
1046 (set_attr "length" "8,8,8")])
1048 (define_insn "smindi3"
1049 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1050 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1051 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1054 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1055 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1056 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1057 [(set_attr "type" "multi,multi,multi")
1058 (set_attr "length" "8,8,8")])
1060 (define_insn "uminsi3"
1061 [(set (match_operand:SI 0 "register_operand" "=r,r")
1062 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1063 (match_operand:SI 2 "arith11_operand" "r,I")))]
1066 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1067 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1068 [(set_attr "type" "multi,multi")
1069 (set_attr "length" "8,8")])
1071 (define_insn "umindi3"
1072 [(set (match_operand:DI 0 "register_operand" "=r,r")
1073 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1074 (match_operand:DI 2 "arith11_operand" "r,I")))]
1077 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1078 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1079 [(set_attr "type" "multi,multi")
1080 (set_attr "length" "8,8")])
1082 (define_insn "smaxsi3"
1083 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1084 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1085 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1088 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1089 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1090 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1091 [(set_attr "type" "multi,multi,multi")
1092 (set_attr "length" "8,8,8")])
1094 (define_insn "smaxdi3"
1095 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1096 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1097 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1100 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1101 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1102 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1103 [(set_attr "type" "multi,multi,multi")
1104 (set_attr "length" "8,8,8")])
1106 (define_insn "umaxsi3"
1107 [(set (match_operand:SI 0 "register_operand" "=r,r")
1108 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1109 (match_operand:SI 2 "arith11_operand" "r,I")))]
1112 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1113 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1114 [(set_attr "type" "multi,multi")
1115 (set_attr "length" "8,8")])
1117 (define_insn "umaxdi3"
1118 [(set (match_operand:DI 0 "register_operand" "=r,r")
1119 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1120 (match_operand:DI 2 "arith11_operand" "r,I")))]
1123 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1124 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1125 [(set_attr "type" "multi,multi")
1126 (set_attr "length" "8,8")])
1128 (define_insn "abssi2"
1129 [(set (match_operand:SI 0 "register_operand" "=r")
1130 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1132 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1133 [(set_attr "type" "multi")
1134 (set_attr "length" "8")])
1136 (define_insn "absdi2"
1137 [(set (match_operand:DI 0 "register_operand" "=r")
1138 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1140 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1141 [(set_attr "type" "multi")
1142 (set_attr "length" "8")])
1144 ;;; Experimental conditional move patterns
1146 (define_expand "movsicc"
1147 [(set (match_operand:SI 0 "register_operand" "")
1149 (match_operator 1 "comparison_operator"
1152 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1153 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1157 enum rtx_code code = GET_CODE (operands[1]);
1159 if (hppa_branch_type != CMP_SI)
1162 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1163 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1166 /* operands[1] is currently the result of compare_from_rtx. We want to
1167 emit a compare of the original operands. */
1168 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1169 operands[4] = hppa_compare_op0;
1170 operands[5] = hppa_compare_op1;
1173 ;; We used to accept any register for op1.
1175 ;; However, it loses sometimes because the compiler will end up using
1176 ;; different registers for op0 and op1 in some critical cases. local-alloc
1177 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1179 ;; If/when global register allocation supports tying we should allow any
1180 ;; register for op1 again.
1182 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1184 (match_operator 2 "comparison_operator"
1185 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1186 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1187 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1191 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1192 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1193 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1194 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1195 [(set_attr "type" "multi,multi,multi,nullshift")
1196 (set_attr "length" "8,8,8,8")])
1199 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1201 (match_operator 5 "comparison_operator"
1202 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1203 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1204 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1205 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1208 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1209 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1210 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1211 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1212 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1213 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1214 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1215 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1216 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1217 (set_attr "length" "8,8,8,8,8,8,8,8")])
1219 (define_expand "movdicc"
1220 [(set (match_operand:DI 0 "register_operand" "")
1222 (match_operator 1 "comparison_operator"
1225 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1226 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1230 enum rtx_code code = GET_CODE (operands[1]);
1232 if (hppa_branch_type != CMP_SI)
1235 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1236 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1239 /* operands[1] is currently the result of compare_from_rtx. We want to
1240 emit a compare of the original operands. */
1241 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1242 operands[4] = hppa_compare_op0;
1243 operands[5] = hppa_compare_op1;
1246 ; We need the first constraint alternative in order to avoid
1247 ; earlyclobbers on all other alternatives.
1249 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1251 (match_operator 2 "comparison_operator"
1252 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1253 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1254 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1258 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1259 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1260 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1261 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1262 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1263 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1264 (set_attr "length" "8,8,8,8,8")])
1267 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1269 (match_operator 5 "comparison_operator"
1270 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1271 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1272 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1273 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1276 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1277 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1278 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1279 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1280 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1281 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1282 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1283 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1284 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1285 (set_attr "length" "8,8,8,8,8,8,8,8")])
1287 ;; Conditional Branches
1289 (define_expand "beq"
1291 (if_then_else (eq (match_dup 1) (match_dup 2))
1292 (label_ref (match_operand 0 "" ""))
1297 if (hppa_branch_type != CMP_SI)
1299 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1300 emit_bcond_fp (NE, operands[0]);
1303 /* set up operands from compare. */
1304 operands[1] = hppa_compare_op0;
1305 operands[2] = hppa_compare_op1;
1306 /* fall through and generate default code */
1309 (define_expand "bne"
1311 (if_then_else (ne (match_dup 1) (match_dup 2))
1312 (label_ref (match_operand 0 "" ""))
1317 if (hppa_branch_type != CMP_SI)
1319 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1320 emit_bcond_fp (NE, operands[0]);
1323 operands[1] = hppa_compare_op0;
1324 operands[2] = hppa_compare_op1;
1327 (define_expand "bgt"
1329 (if_then_else (gt (match_dup 1) (match_dup 2))
1330 (label_ref (match_operand 0 "" ""))
1335 if (hppa_branch_type != CMP_SI)
1337 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1338 emit_bcond_fp (NE, operands[0]);
1341 operands[1] = hppa_compare_op0;
1342 operands[2] = hppa_compare_op1;
1345 (define_expand "blt"
1347 (if_then_else (lt (match_dup 1) (match_dup 2))
1348 (label_ref (match_operand 0 "" ""))
1353 if (hppa_branch_type != CMP_SI)
1355 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1356 emit_bcond_fp (NE, operands[0]);
1359 operands[1] = hppa_compare_op0;
1360 operands[2] = hppa_compare_op1;
1363 (define_expand "bge"
1365 (if_then_else (ge (match_dup 1) (match_dup 2))
1366 (label_ref (match_operand 0 "" ""))
1371 if (hppa_branch_type != CMP_SI)
1373 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1374 emit_bcond_fp (NE, operands[0]);
1377 operands[1] = hppa_compare_op0;
1378 operands[2] = hppa_compare_op1;
1381 (define_expand "ble"
1383 (if_then_else (le (match_dup 1) (match_dup 2))
1384 (label_ref (match_operand 0 "" ""))
1389 if (hppa_branch_type != CMP_SI)
1391 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1392 emit_bcond_fp (NE, operands[0]);
1395 operands[1] = hppa_compare_op0;
1396 operands[2] = hppa_compare_op1;
1399 (define_expand "bgtu"
1401 (if_then_else (gtu (match_dup 1) (match_dup 2))
1402 (label_ref (match_operand 0 "" ""))
1407 if (hppa_branch_type != CMP_SI)
1409 operands[1] = hppa_compare_op0;
1410 operands[2] = hppa_compare_op1;
1413 (define_expand "bltu"
1415 (if_then_else (ltu (match_dup 1) (match_dup 2))
1416 (label_ref (match_operand 0 "" ""))
1421 if (hppa_branch_type != CMP_SI)
1423 operands[1] = hppa_compare_op0;
1424 operands[2] = hppa_compare_op1;
1427 (define_expand "bgeu"
1429 (if_then_else (geu (match_dup 1) (match_dup 2))
1430 (label_ref (match_operand 0 "" ""))
1435 if (hppa_branch_type != CMP_SI)
1437 operands[1] = hppa_compare_op0;
1438 operands[2] = hppa_compare_op1;
1441 (define_expand "bleu"
1443 (if_then_else (leu (match_dup 1) (match_dup 2))
1444 (label_ref (match_operand 0 "" ""))
1449 if (hppa_branch_type != CMP_SI)
1451 operands[1] = hppa_compare_op0;
1452 operands[2] = hppa_compare_op1;
1455 (define_expand "bltgt"
1457 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1458 (label_ref (match_operand 0 "" ""))
1463 if (hppa_branch_type == CMP_SI)
1465 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1466 emit_bcond_fp (NE, operands[0]);
1470 (define_expand "bunle"
1472 (if_then_else (unle (match_dup 1) (match_dup 2))
1473 (label_ref (match_operand 0 "" ""))
1478 if (hppa_branch_type == CMP_SI)
1480 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1481 emit_bcond_fp (NE, operands[0]);
1485 (define_expand "bunlt"
1487 (if_then_else (unlt (match_dup 1) (match_dup 2))
1488 (label_ref (match_operand 0 "" ""))
1493 if (hppa_branch_type == CMP_SI)
1495 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1496 emit_bcond_fp (NE, operands[0]);
1500 (define_expand "bunge"
1502 (if_then_else (unge (match_dup 1) (match_dup 2))
1503 (label_ref (match_operand 0 "" ""))
1508 if (hppa_branch_type == CMP_SI)
1510 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1511 emit_bcond_fp (NE, operands[0]);
1515 (define_expand "bungt"
1517 (if_then_else (ungt (match_dup 1) (match_dup 2))
1518 (label_ref (match_operand 0 "" ""))
1523 if (hppa_branch_type == CMP_SI)
1525 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1526 emit_bcond_fp (NE, operands[0]);
1530 (define_expand "buneq"
1532 (if_then_else (uneq (match_dup 1) (match_dup 2))
1533 (label_ref (match_operand 0 "" ""))
1538 if (hppa_branch_type == CMP_SI)
1540 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1541 emit_bcond_fp (NE, operands[0]);
1545 (define_expand "bunordered"
1547 (if_then_else (unordered (match_dup 1) (match_dup 2))
1548 (label_ref (match_operand 0 "" ""))
1553 if (hppa_branch_type == CMP_SI)
1555 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1556 emit_bcond_fp (NE, operands[0]);
1560 (define_expand "bordered"
1562 (if_then_else (ordered (match_dup 1) (match_dup 2))
1563 (label_ref (match_operand 0 "" ""))
1568 if (hppa_branch_type == CMP_SI)
1570 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1571 emit_bcond_fp (NE, operands[0]);
1575 ;; Match the branch patterns.
1578 ;; Note a long backward conditional branch with an annulled delay slot
1579 ;; has a length of 12.
1583 (match_operator 3 "comparison_operator"
1584 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1585 (match_operand:SI 2 "arith5_operand" "rL")])
1586 (label_ref (match_operand 0 "" ""))
1591 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1592 get_attr_length (insn), 0, insn);
1594 [(set_attr "type" "cbranch")
1595 (set (attr "length")
1596 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1599 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1602 (eq (symbol_ref "flag_pic") (const_int 0))
1606 ;; Match the negated branch.
1611 (match_operator 3 "comparison_operator"
1612 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1613 (match_operand:SI 2 "arith5_operand" "rL")])
1615 (label_ref (match_operand 0 "" ""))))]
1619 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1620 get_attr_length (insn), 1, insn);
1622 [(set_attr "type" "cbranch")
1623 (set (attr "length")
1624 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1627 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1630 (eq (symbol_ref "flag_pic") (const_int 0))
1637 (match_operator 3 "comparison_operator"
1638 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1639 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1640 (label_ref (match_operand 0 "" ""))
1645 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1646 get_attr_length (insn), 0, insn);
1648 [(set_attr "type" "cbranch")
1649 (set (attr "length")
1650 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1653 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1656 (eq (symbol_ref "flag_pic") (const_int 0))
1660 ;; Match the negated branch.
1665 (match_operator 3 "comparison_operator"
1666 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1667 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1669 (label_ref (match_operand 0 "" ""))))]
1673 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1674 get_attr_length (insn), 1, insn);
1676 [(set_attr "type" "cbranch")
1677 (set (attr "length")
1678 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1681 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1684 (eq (symbol_ref "flag_pic") (const_int 0))
1690 (match_operator 3 "cmpib_comparison_operator"
1691 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1692 (match_operand:DI 2 "arith5_operand" "rL")])
1693 (label_ref (match_operand 0 "" ""))
1698 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1699 get_attr_length (insn), 0, insn);
1701 [(set_attr "type" "cbranch")
1702 (set (attr "length")
1703 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1706 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1709 (eq (symbol_ref "flag_pic") (const_int 0))
1713 ;; Match the negated branch.
1718 (match_operator 3 "cmpib_comparison_operator"
1719 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1720 (match_operand:DI 2 "arith5_operand" "rL")])
1722 (label_ref (match_operand 0 "" ""))))]
1726 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1727 get_attr_length (insn), 1, insn);
1729 [(set_attr "type" "cbranch")
1730 (set (attr "length")
1731 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1734 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1737 (eq (symbol_ref "flag_pic") (const_int 0))
1741 ;; Branch on Bit patterns.
1745 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1747 (match_operand:SI 1 "uint5_operand" ""))
1749 (label_ref (match_operand 2 "" ""))
1754 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1755 get_attr_length (insn), 0, insn, 0);
1757 [(set_attr "type" "cbranch")
1758 (set (attr "length")
1759 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1767 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1769 (match_operand:DI 1 "uint32_operand" ""))
1771 (label_ref (match_operand 2 "" ""))
1776 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1777 get_attr_length (insn), 0, insn, 0);
1779 [(set_attr "type" "cbranch")
1780 (set (attr "length")
1781 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1789 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1791 (match_operand:SI 1 "uint5_operand" ""))
1794 (label_ref (match_operand 2 "" ""))))]
1798 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1799 get_attr_length (insn), 1, insn, 0);
1801 [(set_attr "type" "cbranch")
1802 (set (attr "length")
1803 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1811 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1813 (match_operand:DI 1 "uint32_operand" ""))
1816 (label_ref (match_operand 2 "" ""))))]
1820 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn, 0);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1833 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1835 (match_operand:SI 1 "uint5_operand" ""))
1837 (label_ref (match_operand 2 "" ""))
1842 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1843 get_attr_length (insn), 0, insn, 1);
1845 [(set_attr "type" "cbranch")
1846 (set (attr "length")
1847 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1855 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1857 (match_operand:DI 1 "uint32_operand" ""))
1859 (label_ref (match_operand 2 "" ""))
1864 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1865 get_attr_length (insn), 0, insn, 1);
1867 [(set_attr "type" "cbranch")
1868 (set (attr "length")
1869 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1877 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1879 (match_operand:SI 1 "uint5_operand" ""))
1882 (label_ref (match_operand 2 "" ""))))]
1886 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1887 get_attr_length (insn), 1, insn, 1);
1889 [(set_attr "type" "cbranch")
1890 (set (attr "length")
1891 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1899 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1901 (match_operand:DI 1 "uint32_operand" ""))
1904 (label_ref (match_operand 2 "" ""))))]
1908 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1909 get_attr_length (insn), 1, insn, 1);
1911 [(set_attr "type" "cbranch")
1912 (set (attr "length")
1913 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1918 ;; Branch on Variable Bit patterns.
1922 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1924 (match_operand:SI 1 "register_operand" "q"))
1926 (label_ref (match_operand 2 "" ""))
1931 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1932 get_attr_length (insn), 0, insn, 0);
1934 [(set_attr "type" "cbranch")
1935 (set (attr "length")
1936 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1944 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1946 (match_operand:DI 1 "register_operand" "q"))
1948 (label_ref (match_operand 2 "" ""))
1953 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1954 get_attr_length (insn), 0, insn, 0);
1956 [(set_attr "type" "cbranch")
1957 (set (attr "length")
1958 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1966 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1968 (match_operand:SI 1 "register_operand" "q"))
1971 (label_ref (match_operand 2 "" ""))))]
1975 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1976 get_attr_length (insn), 1, insn, 0);
1978 [(set_attr "type" "cbranch")
1979 (set (attr "length")
1980 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1988 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1990 (match_operand:DI 1 "register_operand" "q"))
1993 (label_ref (match_operand 2 "" ""))))]
1997 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
1998 get_attr_length (insn), 1, insn, 0);
2000 [(set_attr "type" "cbranch")
2001 (set (attr "length")
2002 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2010 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2012 (match_operand:SI 1 "register_operand" "q"))
2014 (label_ref (match_operand 2 "" ""))
2019 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2020 get_attr_length (insn), 0, insn, 1);
2022 [(set_attr "type" "cbranch")
2023 (set (attr "length")
2024 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2032 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2034 (match_operand:DI 1 "register_operand" "q"))
2036 (label_ref (match_operand 2 "" ""))
2041 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2042 get_attr_length (insn), 0, insn, 1);
2044 [(set_attr "type" "cbranch")
2045 (set (attr "length")
2046 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2054 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2056 (match_operand:SI 1 "register_operand" "q"))
2059 (label_ref (match_operand 2 "" ""))))]
2063 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2064 get_attr_length (insn), 1, insn, 1);
2066 [(set_attr "type" "cbranch")
2067 (set (attr "length")
2068 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2076 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2078 (match_operand:DI 1 "register_operand" "q"))
2081 (label_ref (match_operand 2 "" ""))))]
2085 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2086 get_attr_length (insn), 1, insn, 1);
2088 [(set_attr "type" "cbranch")
2089 (set (attr "length")
2090 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2095 ;; Floating point branches
2097 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2098 (label_ref (match_operand 0 "" ""))
2100 "! TARGET_SOFT_FLOAT"
2103 if (INSN_ANNULLED_BRANCH_P (insn))
2104 return \"ftest\;b,n %0\";
2106 return \"ftest\;b%* %0\";
2108 [(set_attr "type" "fbranch")
2109 (set_attr "length" "8")])
2112 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2114 (label_ref (match_operand 0 "" ""))))]
2115 "! TARGET_SOFT_FLOAT"
2118 if (INSN_ANNULLED_BRANCH_P (insn))
2119 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2121 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2123 [(set_attr "type" "fbranch")
2124 (set_attr "length" "12")])
2126 ;; Move instructions
2128 (define_expand "movsi"
2129 [(set (match_operand:SI 0 "general_operand" "")
2130 (match_operand:SI 1 "general_operand" ""))]
2134 if (emit_move_sequence (operands, SImode, 0))
2138 ;; Reloading an SImode or DImode value requires a scratch register if
2139 ;; going in to or out of float point registers.
2141 (define_expand "reload_insi"
2142 [(set (match_operand:SI 0 "register_operand" "=Z")
2143 (match_operand:SI 1 "non_hard_reg_operand" ""))
2144 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2148 if (emit_move_sequence (operands, SImode, operands[2]))
2151 /* We don't want the clobber emitted, so handle this ourselves. */
2152 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2156 (define_expand "reload_outsi"
2157 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2158 (match_operand:SI 1 "register_operand" "Z"))
2159 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2163 if (emit_move_sequence (operands, SImode, operands[2]))
2166 /* We don't want the clobber emitted, so handle this ourselves. */
2167 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2172 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2173 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
2174 (match_operand:SI 1 "move_operand"
2175 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
2176 "(register_operand (operands[0], SImode)
2177 || reg_or_0_operand (operands[1], SImode))
2178 && ! TARGET_SOFT_FLOAT"
2184 {zdepi|depwi,z} %Z1,%0
2191 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2192 (set_attr "pa_combine_type" "addmove")
2193 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2196 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2197 "=r,r,r,r,r,r,Q,*q")
2198 (match_operand:SI 1 "move_operand"
2199 "A,r,J,N,K,RQ,rM,rM"))]
2200 "(register_operand (operands[0], SImode)
2201 || reg_or_0_operand (operands[1], SImode))
2202 && TARGET_SOFT_FLOAT"
2208 {zdepi|depwi,z} %Z1,%0
2212 [(set_attr "type" "load,move,move,move,move,load,store,move")
2213 (set_attr "pa_combine_type" "addmove")
2214 (set_attr "length" "4,4,4,4,4,4,4,4")])
2217 [(set (match_operand:SI 0 "register_operand" "=r")
2218 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2219 (match_operand:SI 2 "register_operand" "r"))))]
2220 "! TARGET_DISABLE_INDEXING"
2221 "{ldwx|ldw} %2(%1),%0"
2222 [(set_attr "type" "load")
2223 (set_attr "length" "4")])
2226 [(set (match_operand:SI 0 "register_operand" "=r")
2227 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2228 (match_operand:SI 2 "basereg_operand" "r"))))]
2229 "! TARGET_DISABLE_INDEXING"
2230 "{ldwx|ldw} %1(%2),%0"
2231 [(set_attr "type" "load")
2232 (set_attr "length" "4")])
2234 ;; Load or store with base-register modification.
2236 (define_expand "pre_load"
2237 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2238 (mem (plus (match_operand 1 "register_operand" "")
2239 (match_operand 2 "pre_cint_operand" ""))))
2241 (plus (match_dup 1) (match_dup 2)))])]
2247 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2250 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2254 (define_insn "pre_ldw"
2255 [(set (match_operand:SI 0 "register_operand" "=r")
2256 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2257 (match_operand:SI 2 "pre_cint_operand" ""))))
2259 (plus:SI (match_dup 1) (match_dup 2)))]
2263 if (INTVAL (operands[2]) < 0)
2264 return \"{ldwm|ldw,mb} %2(%1),%0\";
2265 return \"{ldws|ldw},mb %2(%1),%0\";
2267 [(set_attr "type" "load")
2268 (set_attr "length" "4")])
2270 (define_insn "pre_ldd"
2271 [(set (match_operand:DI 0 "register_operand" "=r")
2272 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2273 (match_operand:DI 2 "pre_cint_operand" ""))))
2275 (plus:DI (match_dup 1) (match_dup 2)))]
2278 [(set_attr "type" "load")
2279 (set_attr "length" "4")])
2282 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2283 (match_operand:SI 1 "pre_cint_operand" "")))
2284 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2286 (plus:SI (match_dup 0) (match_dup 1)))]
2290 if (INTVAL (operands[1]) < 0)
2291 return \"{stwm|stw,mb} %r2,%1(%0)\";
2292 return \"{stws|stw},mb %r2,%1(%0)\";
2294 [(set_attr "type" "store")
2295 (set_attr "length" "4")])
2298 [(set (match_operand:SI 0 "register_operand" "=r")
2299 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2301 (plus:SI (match_dup 1)
2302 (match_operand:SI 2 "post_cint_operand" "")))]
2306 if (INTVAL (operands[2]) > 0)
2307 return \"{ldwm|ldw,ma} %2(%1),%0\";
2308 return \"{ldws|ldw},ma %2(%1),%0\";
2310 [(set_attr "type" "load")
2311 (set_attr "length" "4")])
2313 (define_expand "post_store"
2314 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2315 (match_operand 1 "reg_or_0_operand" ""))
2318 (match_operand 2 "post_cint_operand" "")))])]
2324 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2327 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2331 (define_insn "post_stw"
2332 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2333 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2335 (plus:SI (match_dup 0)
2336 (match_operand:SI 2 "post_cint_operand" "")))]
2340 if (INTVAL (operands[2]) > 0)
2341 return \"{stwm|stw,ma} %r1,%2(%0)\";
2342 return \"{stws|stw},ma %r1,%2(%0)\";
2344 [(set_attr "type" "store")
2345 (set_attr "length" "4")])
2347 (define_insn "post_std"
2348 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2349 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2351 (plus:DI (match_dup 0)
2352 (match_operand:DI 2 "post_cint_operand" "")))]
2355 [(set_attr "type" "store")
2356 (set_attr "length" "4")])
2358 ;; For loading the address of a label while generating PIC code.
2359 ;; Note since this pattern can be created at reload time (via movsi), all
2360 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2362 [(set (match_operand 0 "pmode_register_operand" "=a")
2363 (match_operand 1 "pic_label_operand" ""))]
2368 extern FILE *asm_out_file;
2370 xoperands[0] = operands[0];
2371 xoperands[1] = operands[1];
2372 if (TARGET_SOM || ! TARGET_GAS)
2373 xoperands[2] = gen_label_rtx ();
2375 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2376 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2377 if (TARGET_SOM || ! TARGET_GAS)
2378 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2379 CODE_LABEL_NUMBER (xoperands[2]));
2381 /* If we're trying to load the address of a label that happens to be
2382 close, then we can use a shorter sequence. */
2383 if (GET_CODE (operands[1]) == LABEL_REF
2384 && INSN_ADDRESSES_SET_P ()
2385 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2386 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2388 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2389 always non-negative. */
2390 if (TARGET_SOM || ! TARGET_GAS)
2391 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2393 output_asm_insn (\"ldo %1-$PIC_pcrel$0+8(%0),%0\", xoperands);
2397 if (TARGET_SOM || ! TARGET_GAS)
2399 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2400 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2404 output_asm_insn (\"addil L%%%1-$PIC_pcrel$0+8,%0\", xoperands);
2405 output_asm_insn (\"ldo R%%%1-$PIC_pcrel$0+12(%0),%0\",
2411 [(set_attr "type" "multi")
2412 (set_attr "length" "16")]) ; 12 or 16
2415 [(set (match_operand:SI 0 "register_operand" "=a")
2416 (plus:SI (match_operand:SI 1 "register_operand" "r")
2417 (high:SI (match_operand 2 "" ""))))]
2418 "symbolic_operand (operands[2], Pmode)
2419 && ! function_label_operand (operands[2], Pmode)
2422 [(set_attr "type" "binary")
2423 (set_attr "length" "4")])
2426 [(set (match_operand:DI 0 "register_operand" "=a")
2427 (plus:DI (match_operand:DI 1 "register_operand" "r")
2428 (high:DI (match_operand 2 "" ""))))]
2429 "symbolic_operand (operands[2], Pmode)
2430 && ! function_label_operand (operands[2], Pmode)
2434 [(set_attr "type" "binary")
2435 (set_attr "length" "4")])
2437 ;; Always use addil rather than ldil;add sequences. This allows the
2438 ;; HP linker to eliminate the dp relocation if the symbolic operand
2439 ;; lives in the TEXT space.
2441 [(set (match_operand:SI 0 "register_operand" "=a")
2442 (high:SI (match_operand 1 "" "")))]
2443 "symbolic_operand (operands[1], Pmode)
2444 && ! function_label_operand (operands[1], Pmode)
2445 && ! read_only_operand (operands[1], Pmode)
2449 if (TARGET_LONG_LOAD_STORE)
2450 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2452 return \"addil LR'%H1,%%r27\";
2454 [(set_attr "type" "binary")
2455 (set (attr "length")
2456 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2461 ;; This is for use in the prologue/epilogue code. We need it
2462 ;; to add large constants to a stack pointer or frame pointer.
2463 ;; Because of the additional %r1 pressure, we probably do not
2464 ;; want to use this in general code, so make it available
2465 ;; only after reload.
2467 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2468 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2469 (high:SI (match_operand 2 "const_int_operand" ""))))]
2473 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2474 [(set_attr "type" "binary,binary")
2475 (set_attr "length" "4,8")])
2478 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2479 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2480 (high:DI (match_operand 2 "const_int_operand" ""))))]
2481 "reload_completed && TARGET_64BIT"
2484 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2485 [(set_attr "type" "binary,binary")
2486 (set_attr "length" "4,8")])
2489 [(set (match_operand:SI 0 "register_operand" "=r")
2490 (high:SI (match_operand 1 "" "")))]
2491 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2492 && !is_function_label_plus_const (operands[1])"
2495 if (symbolic_operand (operands[1], Pmode))
2496 return \"ldil LR'%H1,%0\";
2498 return \"ldil L'%G1,%0\";
2500 [(set_attr "type" "move")
2501 (set_attr "length" "4")])
2504 [(set (match_operand:DI 0 "register_operand" "=r")
2505 (high:DI (match_operand 1 "const_int_operand" "")))]
2508 [(set_attr "type" "move")
2509 (set_attr "length" "4")])
2512 [(set (match_operand:DI 0 "register_operand" "=r")
2513 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2514 (match_operand:DI 2 "const_int_operand" "i")))]
2517 [(set_attr "type" "move")
2518 (set_attr "length" "4")])
2521 [(set (match_operand:SI 0 "register_operand" "=r")
2522 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2523 (match_operand:SI 2 "immediate_operand" "i")))]
2524 "!is_function_label_plus_const (operands[2])"
2527 if (flag_pic && symbolic_operand (operands[2], Pmode))
2529 else if (symbolic_operand (operands[2], Pmode))
2530 return \"ldo RR'%G2(%1),%0\";
2532 return \"ldo R'%G2(%1),%0\";
2534 [(set_attr "type" "move")
2535 (set_attr "length" "4")])
2537 ;; Now that a symbolic_address plus a constant is broken up early
2538 ;; in the compilation phase (for better CSE) we need a special
2539 ;; combiner pattern to load the symbolic address plus the constant
2540 ;; in only 2 instructions. (For cases where the symbolic address
2541 ;; was not a common subexpression.)
2543 [(set (match_operand:SI 0 "register_operand" "")
2544 (match_operand:SI 1 "symbolic_operand" ""))
2545 (clobber (match_operand:SI 2 "register_operand" ""))]
2546 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2547 [(set (match_dup 2) (high:SI (match_dup 1)))
2548 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2551 ;; hppa_legitimize_address goes to a great deal of trouble to
2552 ;; create addresses which use indexing. In some cases, this
2553 ;; is a lose because there isn't any store instructions which
2554 ;; allow indexed addresses (with integer register source).
2556 ;; These define_splits try to turn a 3 insn store into
2557 ;; a 2 insn store with some creative RTL rewriting.
2559 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2560 (match_operand:SI 1 "shadd_operand" ""))
2561 (plus:SI (match_operand:SI 2 "register_operand" "")
2562 (match_operand:SI 3 "const_int_operand" ""))))
2563 (match_operand:SI 4 "register_operand" ""))
2564 (clobber (match_operand:SI 5 "register_operand" ""))]
2566 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2568 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2572 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2573 (match_operand:SI 1 "shadd_operand" ""))
2574 (plus:SI (match_operand:SI 2 "register_operand" "")
2575 (match_operand:SI 3 "const_int_operand" ""))))
2576 (match_operand:HI 4 "register_operand" ""))
2577 (clobber (match_operand:SI 5 "register_operand" ""))]
2579 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2581 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2585 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2586 (match_operand:SI 1 "shadd_operand" ""))
2587 (plus:SI (match_operand:SI 2 "register_operand" "")
2588 (match_operand:SI 3 "const_int_operand" ""))))
2589 (match_operand:QI 4 "register_operand" ""))
2590 (clobber (match_operand:SI 5 "register_operand" ""))]
2592 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2594 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2597 (define_expand "movhi"
2598 [(set (match_operand:HI 0 "general_operand" "")
2599 (match_operand:HI 1 "general_operand" ""))]
2603 if (emit_move_sequence (operands, HImode, 0))
2608 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2609 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2610 "register_operand (operands[0], HImode)
2611 || reg_or_0_operand (operands[1], HImode)"
2616 {zdepi|depwi,z} %Z1,%0
2621 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2622 (set_attr "pa_combine_type" "addmove")
2623 (set_attr "length" "4,4,4,4,4,4,4,4")])
2626 [(set (match_operand:HI 0 "register_operand" "=r")
2627 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2628 (match_operand:SI 2 "register_operand" "r"))))]
2629 "! TARGET_DISABLE_INDEXING"
2630 "{ldhx|ldh} %2(%1),%0"
2631 [(set_attr "type" "load")
2632 (set_attr "length" "4")])
2635 [(set (match_operand:HI 0 "register_operand" "=r")
2636 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2637 (match_operand:SI 2 "basereg_operand" "r"))))]
2638 "! TARGET_DISABLE_INDEXING"
2639 "{ldhx|ldh} %1(%2),%0"
2640 [(set_attr "type" "load")
2641 (set_attr "length" "4")])
2643 ; Now zero extended variants.
2645 [(set (match_operand:SI 0 "register_operand" "=r")
2646 (zero_extend:SI (mem:HI
2648 (match_operand:SI 1 "basereg_operand" "r")
2649 (match_operand:SI 2 "register_operand" "r")))))]
2650 "! TARGET_DISABLE_INDEXING"
2651 "{ldhx|ldh} %2(%1),%0"
2652 [(set_attr "type" "load")
2653 (set_attr "length" "4")])
2656 [(set (match_operand:SI 0 "register_operand" "=r")
2657 (zero_extend:SI (mem:HI
2659 (match_operand:SI 1 "register_operand" "r")
2660 (match_operand:SI 2 "basereg_operand" "r")))))]
2661 "! TARGET_DISABLE_INDEXING"
2662 "{ldhx|ldh} %1(%2),%0"
2663 [(set_attr "type" "load")
2664 (set_attr "length" "4")])
2667 [(set (match_operand:HI 0 "register_operand" "=r")
2668 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2669 (match_operand:SI 2 "int5_operand" "L"))))
2671 (plus:SI (match_dup 1) (match_dup 2)))]
2673 "{ldhs|ldh},mb %2(%1),%0"
2674 [(set_attr "type" "load")
2675 (set_attr "length" "4")])
2677 ; And a zero extended variant.
2679 [(set (match_operand:SI 0 "register_operand" "=r")
2680 (zero_extend:SI (mem:HI
2682 (match_operand:SI 1 "register_operand" "+r")
2683 (match_operand:SI 2 "int5_operand" "L")))))
2685 (plus:SI (match_dup 1) (match_dup 2)))]
2687 "{ldhs|ldh},mb %2(%1),%0"
2688 [(set_attr "type" "load")
2689 (set_attr "length" "4")])
2692 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2693 (match_operand:SI 1 "int5_operand" "L")))
2694 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2696 (plus:SI (match_dup 0) (match_dup 1)))]
2698 "{sths|sth},mb %r2,%1(%0)"
2699 [(set_attr "type" "store")
2700 (set_attr "length" "4")])
2703 [(set (match_operand:HI 0 "register_operand" "=r")
2704 (plus:HI (match_operand:HI 1 "register_operand" "r")
2705 (match_operand 2 "const_int_operand" "J")))]
2708 [(set_attr "type" "binary")
2709 (set_attr "pa_combine_type" "addmove")
2710 (set_attr "length" "4")])
2712 (define_expand "movqi"
2713 [(set (match_operand:QI 0 "general_operand" "")
2714 (match_operand:QI 1 "general_operand" ""))]
2718 if (emit_move_sequence (operands, QImode, 0))
2723 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2724 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2725 "register_operand (operands[0], QImode)
2726 || reg_or_0_operand (operands[1], QImode)"
2731 {zdepi|depwi,z} %Z1,%0
2736 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2737 (set_attr "pa_combine_type" "addmove")
2738 (set_attr "length" "4,4,4,4,4,4,4,4")])
2741 [(set (match_operand:QI 0 "register_operand" "=r")
2742 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2743 (match_operand:SI 2 "register_operand" "r"))))]
2744 "! TARGET_DISABLE_INDEXING"
2745 "{ldbx|ldb} %2(%1),%0"
2746 [(set_attr "type" "load")
2747 (set_attr "length" "4")])
2750 [(set (match_operand:QI 0 "register_operand" "=r")
2751 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2752 (match_operand:SI 2 "basereg_operand" "r"))))]
2753 "! TARGET_DISABLE_INDEXING"
2754 "{ldbx|ldb} %1(%2),%0"
2755 [(set_attr "type" "load")
2756 (set_attr "length" "4")])
2758 ; Indexed byte load with zero extension to SImode or HImode.
2760 [(set (match_operand:SI 0 "register_operand" "=r")
2761 (zero_extend:SI (mem:QI
2763 (match_operand:SI 1 "basereg_operand" "r")
2764 (match_operand:SI 2 "register_operand" "r")))))]
2765 "! TARGET_DISABLE_INDEXING"
2766 "{ldbx|ldb} %2(%1),%0"
2767 [(set_attr "type" "load")
2768 (set_attr "length" "4")])
2771 [(set (match_operand:SI 0 "register_operand" "=r")
2772 (zero_extend:SI (mem:QI
2774 (match_operand:SI 1 "register_operand" "r")
2775 (match_operand:SI 2 "basereg_operand" "r")))))]
2776 "! TARGET_DISABLE_INDEXING"
2777 "{ldbx|ldb} %1(%2),%0"
2778 [(set_attr "type" "load")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:HI 0 "register_operand" "=r")
2783 (zero_extend:HI (mem:QI
2785 (match_operand:SI 1 "basereg_operand" "r")
2786 (match_operand:SI 2 "register_operand" "r")))))]
2787 "! TARGET_DISABLE_INDEXING"
2788 "{ldbx|ldb} %2(%1),%0"
2789 [(set_attr "type" "load")
2790 (set_attr "length" "4")])
2793 [(set (match_operand:HI 0 "register_operand" "=r")
2794 (zero_extend:HI (mem:QI
2796 (match_operand:SI 1 "register_operand" "r")
2797 (match_operand:SI 2 "basereg_operand" "r")))))]
2798 "! TARGET_DISABLE_INDEXING"
2799 "{ldbx|ldb} %1(%2),%0"
2800 [(set_attr "type" "load")
2801 (set_attr "length" "4")])
2804 [(set (match_operand:QI 0 "register_operand" "=r")
2805 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2806 (match_operand:SI 2 "int5_operand" "L"))))
2807 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2809 "{ldbs|ldb},mb %2(%1),%0"
2810 [(set_attr "type" "load")
2811 (set_attr "length" "4")])
2813 ; Now the same thing with zero extensions.
2815 [(set (match_operand:SI 0 "register_operand" "=r")
2816 (zero_extend:SI (mem:QI (plus:SI
2817 (match_operand:SI 1 "register_operand" "+r")
2818 (match_operand:SI 2 "int5_operand" "L")))))
2819 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2821 "{ldbs|ldb},mb %2(%1),%0"
2822 [(set_attr "type" "load")
2823 (set_attr "length" "4")])
2826 [(set (match_operand:HI 0 "register_operand" "=r")
2827 (zero_extend:HI (mem:QI (plus:SI
2828 (match_operand:SI 1 "register_operand" "+r")
2829 (match_operand:SI 2 "int5_operand" "L")))))
2830 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2832 "{ldbs|ldb},mb %2(%1),%0"
2833 [(set_attr "type" "load")
2834 (set_attr "length" "4")])
2837 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2838 (match_operand:SI 1 "int5_operand" "L")))
2839 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2841 (plus:SI (match_dup 0) (match_dup 1)))]
2843 "{stbs|stb},mb %r2,%1(%0)"
2844 [(set_attr "type" "store")
2845 (set_attr "length" "4")])
2847 ;; The definition of this insn does not really explain what it does,
2848 ;; but it should suffice
2849 ;; that anything generated as this insn will be recognized as one
2850 ;; and that it will not successfully combine with anything.
2851 (define_expand "movstrsi"
2852 [(parallel [(set (match_operand:BLK 0 "" "")
2853 (match_operand:BLK 1 "" ""))
2854 (clobber (match_dup 7))
2855 (clobber (match_dup 8))
2856 (clobber (match_dup 4))
2857 (clobber (match_dup 5))
2858 (clobber (match_dup 6))
2859 (use (match_operand:SI 2 "arith_operand" ""))
2860 (use (match_operand:SI 3 "const_int_operand" ""))])]
2866 /* HP provides very fast block move library routine for the PA;
2867 this routine includes:
2869 4x4 byte at a time block moves,
2870 1x4 byte at a time with alignment checked at runtime with
2871 attempts to align the source and destination as needed
2874 With that in mind, here's the heuristics to try and guess when
2875 the inlined block move will be better than the library block
2878 If the size isn't constant, then always use the library routines.
2880 If the size is large in respect to the known alignment, then use
2881 the library routines.
2883 If the size is small in repsect to the known alignment, then open
2884 code the copy (since that will lead to better scheduling).
2886 Else use the block move pattern. */
2888 /* Undetermined size, use the library routine. */
2889 if (GET_CODE (operands[2]) != CONST_INT)
2892 size = INTVAL (operands[2]);
2893 align = INTVAL (operands[3]);
2894 align = align > 4 ? 4 : align;
2896 /* If size/alignment > 8 (eg size is large in respect to alignment),
2897 then use the library routines. */
2898 if (size / align > 16)
2901 /* This does happen, but not often enough to worry much about. */
2902 if (size / align < MOVE_RATIO)
2905 /* Fall through means we're going to use our block move pattern. */
2907 = replace_equiv_address (operands[0],
2908 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
2910 = replace_equiv_address (operands[1],
2911 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
2912 operands[4] = gen_reg_rtx (SImode);
2913 operands[5] = gen_reg_rtx (SImode);
2914 operands[6] = gen_reg_rtx (SImode);
2915 operands[7] = XEXP (operands[0], 0);
2916 operands[8] = XEXP (operands[1], 0);
2919 ;; The operand constraints are written like this to support both compile-time
2920 ;; and run-time determined byte count. If the count is run-time determined,
2921 ;; the register with the byte count is clobbered by the copying code, and
2922 ;; therefore it is forced to operand 2. If the count is compile-time
2923 ;; determined, we need two scratch registers for the unrolled code.
2924 (define_insn "movstrsi_internal"
2925 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
2926 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
2927 (clobber (match_dup 0))
2928 (clobber (match_dup 1))
2929 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
2930 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
2931 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
2932 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
2933 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
2935 "* return output_block_move (operands, !which_alternative);"
2936 [(set_attr "type" "multi,multi")])
2938 ;; Floating point move insns
2940 ;; This pattern forces (set (reg:DF ...) (const_double ...))
2941 ;; to be reloaded by putting the constant into memory when
2942 ;; reg is a floating point register.
2944 ;; For integer registers we use ldil;ldo to set the appropriate
2947 ;; This must come before the movdf pattern, and it must be present
2948 ;; to handle obscure reloading cases.
2950 [(set (match_operand:DF 0 "register_operand" "=?r,f")
2951 (match_operand:DF 1 "" "?F,m"))]
2952 "GET_CODE (operands[1]) == CONST_DOUBLE
2953 && operands[1] != CONST0_RTX (DFmode)
2955 && ! TARGET_SOFT_FLOAT"
2956 "* return (which_alternative == 0 ? output_move_double (operands)
2957 : \"fldd%F1 %1,%0\");"
2958 [(set_attr "type" "move,fpload")
2959 (set_attr "length" "16,4")])
2961 (define_expand "movdf"
2962 [(set (match_operand:DF 0 "general_operand" "")
2963 (match_operand:DF 1 "general_operand" ""))]
2967 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
2968 operands[1] = force_const_mem (DFmode, operands[1]);
2970 if (emit_move_sequence (operands, DFmode, 0))
2974 ;; Reloading an SImode or DImode value requires a scratch register if
2975 ;; going in to or out of float point registers.
2977 (define_expand "reload_indf"
2978 [(set (match_operand:DF 0 "register_operand" "=Z")
2979 (match_operand:DF 1 "non_hard_reg_operand" ""))
2980 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2984 if (emit_move_sequence (operands, DFmode, operands[2]))
2987 /* We don't want the clobber emitted, so handle this ourselves. */
2988 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2992 (define_expand "reload_outdf"
2993 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
2994 (match_operand:DF 1 "register_operand" "Z"))
2995 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
2999 if (emit_move_sequence (operands, DFmode, operands[2]))
3002 /* We don't want the clobber emitted, so handle this ourselves. */
3003 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3008 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3009 "=f,*r,RQ,?o,?Q,f,*r,*r")
3010 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3011 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3012 "(register_operand (operands[0], DFmode)
3013 || reg_or_0_operand (operands[1], DFmode))
3014 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
3015 && GET_CODE (operands[0]) == MEM)
3017 && ! TARGET_SOFT_FLOAT"
3020 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3021 || operands[1] == CONST0_RTX (DFmode))
3022 return output_fp_move_double (operands);
3023 return output_move_double (operands);
3025 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3026 (set_attr "length" "4,8,4,8,16,4,8,16")])
3029 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3031 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3033 "(register_operand (operands[0], DFmode)
3034 || reg_or_0_operand (operands[1], DFmode))
3036 && TARGET_SOFT_FLOAT"
3039 return output_move_double (operands);
3041 [(set_attr "type" "move,store,store,load,load")
3042 (set_attr "length" "8,8,16,8,16")])
3045 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3046 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3047 (match_operand:DF 1 "move_operand"
3048 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3049 "(register_operand (operands[0], DFmode)
3050 || reg_or_0_operand (operands[1], DFmode))
3051 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3063 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3064 (set_attr "pa_combine_type" "addmove")
3065 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3068 [(set (match_operand:DF 0 "register_operand" "=fx")
3069 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3070 (match_operand:SI 2 "register_operand" "r"))))]
3071 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3072 "{flddx|fldd} %2(%1),%0"
3073 [(set_attr "type" "fpload")
3074 (set_attr "length" "4")])
3077 [(set (match_operand:DF 0 "register_operand" "=fx")
3078 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3079 (match_operand:SI 2 "basereg_operand" "r"))))]
3080 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3081 "{flddx|fldd} %1(%2),%0"
3082 [(set_attr "type" "fpload")
3083 (set_attr "length" "4")])
3086 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3087 (match_operand:SI 2 "register_operand" "r")))
3088 (match_operand:DF 0 "register_operand" "fx"))]
3089 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3090 "{fstdx|fstd} %0,%2(%1)"
3091 [(set_attr "type" "fpstore")
3092 (set_attr "length" "4")])
3095 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3096 (match_operand:SI 2 "basereg_operand" "r")))
3097 (match_operand:DF 0 "register_operand" "fx"))]
3098 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3099 "{fstdx|fstd} %0,%1(%2)"
3100 [(set_attr "type" "fpstore")
3101 (set_attr "length" "4")])
3103 (define_expand "movdi"
3104 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
3105 (match_operand:DI 1 "general_operand" ""))]
3109 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3110 operands[1] = force_const_mem (DImode, operands[1]);
3112 if (emit_move_sequence (operands, DImode, 0))
3116 (define_expand "reload_indi"
3117 [(set (match_operand:DI 0 "register_operand" "=Z")
3118 (match_operand:DI 1 "non_hard_reg_operand" ""))
3119 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3123 if (emit_move_sequence (operands, DImode, operands[2]))
3126 /* We don't want the clobber emitted, so handle this ourselves. */
3127 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3131 (define_expand "reload_outdi"
3132 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3133 (match_operand:DI 1 "register_operand" "Z"))
3134 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3138 if (emit_move_sequence (operands, DImode, operands[2]))
3141 /* We don't want the clobber emitted, so handle this ourselves. */
3142 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3147 [(set (match_operand:DI 0 "register_operand" "=r")
3148 (high:DI (match_operand 1 "" "")))]
3152 rtx op0 = operands[0];
3153 rtx op1 = operands[1];
3155 if (GET_CODE (op1) == CONST_INT)
3157 operands[0] = operand_subword (op0, 1, 0, DImode);
3158 output_asm_insn (\"ldil L'%1,%0\", operands);
3160 operands[0] = operand_subword (op0, 0, 0, DImode);
3161 if (INTVAL (op1) < 0)
3162 output_asm_insn (\"ldi -1,%0\", operands);
3164 output_asm_insn (\"ldi 0,%0\", operands);
3167 else if (GET_CODE (op1) == CONST_DOUBLE)
3169 operands[0] = operand_subword (op0, 1, 0, DImode);
3170 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3171 output_asm_insn (\"ldil L'%1,%0\", operands);
3173 operands[0] = operand_subword (op0, 0, 0, DImode);
3174 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3175 output_asm_insn (singlemove_string (operands), operands);
3181 [(set_attr "type" "move")
3182 (set_attr "length" "8")])
3185 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3186 "=r,o,Q,r,r,r,f,f,*TR")
3187 (match_operand:DI 1 "general_operand"
3188 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3189 "(register_operand (operands[0], DImode)
3190 || reg_or_0_operand (operands[1], DImode))
3192 && ! TARGET_SOFT_FLOAT"
3195 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3196 || (operands[1] == CONST0_RTX (DImode)))
3197 return output_fp_move_double (operands);
3198 return output_move_double (operands);
3200 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3201 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3204 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3205 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
3206 (match_operand:DI 1 "move_operand"
3207 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3208 "(register_operand (operands[0], DImode)
3209 || reg_or_0_operand (operands[1], DImode))
3210 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3223 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3224 (set_attr "pa_combine_type" "addmove")
3225 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
3228 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3230 (match_operand:DI 1 "general_operand"
3232 "(register_operand (operands[0], DImode)
3233 || reg_or_0_operand (operands[1], DImode))
3235 && TARGET_SOFT_FLOAT"
3238 return output_move_double (operands);
3240 [(set_attr "type" "move,store,store,load,load,multi")
3241 (set_attr "length" "8,8,16,8,16,16")])
3244 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3245 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3246 (match_operand:DI 2 "immediate_operand" "i,i")))]
3250 /* Don't output a 64 bit constant, since we can't trust the assembler to
3251 handle it correctly. */
3252 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3253 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3254 if (which_alternative == 1)
3255 output_asm_insn (\"copy %1,%0\", operands);
3256 return \"ldo R'%G2(%R1),%R0\";
3258 [(set_attr "type" "move,move")
3259 (set_attr "length" "4,8")])
3261 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3262 ;; to be reloaded by putting the constant into memory when
3263 ;; reg is a floating point register.
3265 ;; For integer registers we use ldil;ldo to set the appropriate
3268 ;; This must come before the movsf pattern, and it must be present
3269 ;; to handle obscure reloading cases.
3271 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3272 (match_operand:SF 1 "" "?F,m"))]
3273 "GET_CODE (operands[1]) == CONST_DOUBLE
3274 && operands[1] != CONST0_RTX (SFmode)
3275 && ! TARGET_SOFT_FLOAT"
3276 "* return (which_alternative == 0 ? singlemove_string (operands)
3277 : \" fldw%F1 %1,%0\");"
3278 [(set_attr "type" "move,fpload")
3279 (set_attr "length" "8,4")])
3281 (define_expand "movsf"
3282 [(set (match_operand:SF 0 "general_operand" "")
3283 (match_operand:SF 1 "general_operand" ""))]
3287 if (emit_move_sequence (operands, SFmode, 0))
3291 ;; Reloading an SImode or DImode value requires a scratch register if
3292 ;; going in to or out of float point registers.
3294 (define_expand "reload_insf"
3295 [(set (match_operand:SF 0 "register_operand" "=Z")
3296 (match_operand:SF 1 "non_hard_reg_operand" ""))
3297 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3301 if (emit_move_sequence (operands, SFmode, operands[2]))
3304 /* We don't want the clobber emitted, so handle this ourselves. */
3305 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3309 (define_expand "reload_outsf"
3310 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3311 (match_operand:SF 1 "register_operand" "Z"))
3312 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3316 if (emit_move_sequence (operands, SFmode, operands[2]))
3319 /* We don't want the clobber emitted, so handle this ourselves. */
3320 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3325 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3327 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3328 "fG,rG,RQ,RQ,f,rG"))]
3329 "(register_operand (operands[0], SFmode)
3330 || reg_or_0_operand (operands[1], SFmode))
3331 && ! TARGET_SOFT_FLOAT"
3339 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3340 (set_attr "pa_combine_type" "addmove")
3341 (set_attr "length" "4,4,4,4,4,4")])
3344 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3346 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3348 "(register_operand (operands[0], SFmode)
3349 || reg_or_0_operand (operands[1], SFmode))
3350 && TARGET_SOFT_FLOAT"
3355 [(set_attr "type" "move,load,store")
3356 (set_attr "pa_combine_type" "addmove")
3357 (set_attr "length" "4,4,4")])
3360 [(set (match_operand:SF 0 "register_operand" "=fx")
3361 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3362 (match_operand:SI 2 "register_operand" "r"))))]
3363 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3364 "{fldwx|fldw} %2(%1),%0"
3365 [(set_attr "type" "fpload")
3366 (set_attr "length" "4")])
3369 [(set (match_operand:SF 0 "register_operand" "=fx")
3370 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3371 (match_operand:SI 2 "basereg_operand" "r"))))]
3372 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3373 "{fldwx|fldw} %1(%2),%0"
3374 [(set_attr "type" "fpload")
3375 (set_attr "length" "4")])
3378 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3379 (match_operand:SI 2 "register_operand" "r")))
3380 (match_operand:SF 0 "register_operand" "fx"))]
3381 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3382 "{fstwx|fstw} %0,%2(%1)"
3383 [(set_attr "type" "fpstore")
3384 (set_attr "length" "4")])
3387 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3388 (match_operand:SI 2 "basereg_operand" "r")))
3389 (match_operand:SF 0 "register_operand" "fx"))]
3390 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3391 "{fstwx|fstw} %0,%1(%2)"
3392 [(set_attr "type" "fpstore")
3393 (set_attr "length" "4")])
3396 ;;- zero extension instructions
3397 ;; We have define_expand for zero extension patterns to make sure the
3398 ;; operands get loaded into registers. The define_insns accept
3399 ;; memory operands. This gives us better overall code than just
3400 ;; having a pattern that does or does not accept memory operands.
3402 (define_expand "zero_extendhisi2"
3403 [(set (match_operand:SI 0 "register_operand" "")
3405 (match_operand:HI 1 "register_operand" "")))]
3410 [(set (match_operand:SI 0 "register_operand" "=r,r")
3412 (match_operand:HI 1 "move_operand" "r,RQ")))]
3413 "GET_CODE (operands[1]) != CONST_INT"
3415 {extru|extrw,u} %1,31,16,%0
3417 [(set_attr "type" "shift,load")
3418 (set_attr "length" "4,4")])
3420 (define_expand "zero_extendqihi2"
3421 [(set (match_operand:HI 0 "register_operand" "")
3423 (match_operand:QI 1 "register_operand" "")))]
3428 [(set (match_operand:HI 0 "register_operand" "=r,r")
3430 (match_operand:QI 1 "move_operand" "r,RQ")))]
3431 "GET_CODE (operands[1]) != CONST_INT"
3433 {extru|extrw,u} %1,31,8,%0
3435 [(set_attr "type" "shift,load")
3436 (set_attr "length" "4,4")])
3438 (define_expand "zero_extendqisi2"
3439 [(set (match_operand:SI 0 "register_operand" "")
3441 (match_operand:QI 1 "register_operand" "")))]
3446 [(set (match_operand:SI 0 "register_operand" "=r,r")
3448 (match_operand:QI 1 "move_operand" "r,RQ")))]
3449 "GET_CODE (operands[1]) != CONST_INT"
3451 {extru|extrw,u} %1,31,8,%0
3453 [(set_attr "type" "shift,load")
3454 (set_attr "length" "4,4")])
3456 (define_insn "zero_extendqidi2"
3457 [(set (match_operand:DI 0 "register_operand" "=r")
3458 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3460 "extrd,u %1,63,8,%0"
3461 [(set_attr "type" "shift")
3462 (set_attr "length" "4")])
3464 (define_insn "zero_extendhidi2"
3465 [(set (match_operand:DI 0 "register_operand" "=r")
3466 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3468 "extrd,u %1,63,16,%0"
3469 [(set_attr "type" "shift")
3470 (set_attr "length" "4")])
3472 (define_insn "zero_extendsidi2"
3473 [(set (match_operand:DI 0 "register_operand" "=r")
3474 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3476 "extrd,u %1,63,32,%0"
3477 [(set_attr "type" "shift")
3478 (set_attr "length" "4")])
3480 ;;- sign extension instructions
3482 (define_insn "extendhisi2"
3483 [(set (match_operand:SI 0 "register_operand" "=r")
3484 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3486 "{extrs|extrw,s} %1,31,16,%0"
3487 [(set_attr "type" "shift")
3488 (set_attr "length" "4")])
3490 (define_insn "extendqihi2"
3491 [(set (match_operand:HI 0 "register_operand" "=r")
3492 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3494 "{extrs|extrw,s} %1,31,8,%0"
3495 [(set_attr "type" "shift")
3496 (set_attr "length" "4")])
3498 (define_insn "extendqisi2"
3499 [(set (match_operand:SI 0 "register_operand" "=r")
3500 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3502 "{extrs|extrw,s} %1,31,8,%0"
3503 [(set_attr "type" "shift")
3504 (set_attr "length" "4")])
3506 (define_insn "extendqidi2"
3507 [(set (match_operand:DI 0 "register_operand" "=r")
3508 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3510 "extrd,s %1,63,8,%0"
3511 [(set_attr "type" "shift")
3512 (set_attr "length" "4")])
3514 (define_insn "extendhidi2"
3515 [(set (match_operand:DI 0 "register_operand" "=r")
3516 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3518 "extrd,s %1,63,16,%0"
3519 [(set_attr "type" "shift")
3520 (set_attr "length" "4")])
3522 (define_insn "extendsidi2"
3523 [(set (match_operand:DI 0 "register_operand" "=r")
3524 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3526 "extrd,s %1,63,32,%0"
3527 [(set_attr "type" "shift")
3528 (set_attr "length" "4")])
3531 ;; Conversions between float and double.
3533 (define_insn "extendsfdf2"
3534 [(set (match_operand:DF 0 "register_operand" "=f")
3536 (match_operand:SF 1 "register_operand" "f")))]
3537 "! TARGET_SOFT_FLOAT"
3538 "{fcnvff|fcnv},sgl,dbl %1,%0"
3539 [(set_attr "type" "fpalu")
3540 (set_attr "length" "4")])
3542 (define_insn "truncdfsf2"
3543 [(set (match_operand:SF 0 "register_operand" "=f")
3545 (match_operand:DF 1 "register_operand" "f")))]
3546 "! TARGET_SOFT_FLOAT"
3547 "{fcnvff|fcnv},dbl,sgl %1,%0"
3548 [(set_attr "type" "fpalu")
3549 (set_attr "length" "4")])
3551 ;; Conversion between fixed point and floating point.
3552 ;; Note that among the fix-to-float insns
3553 ;; the ones that start with SImode come first.
3554 ;; That is so that an operand that is a CONST_INT
3555 ;; (and therefore lacks a specific machine mode).
3556 ;; will be recognized as SImode (which is always valid)
3557 ;; rather than as QImode or HImode.
3559 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3560 ;; to be reloaded by putting the constant into memory.
3561 ;; It must come before the more general floatsisf2 pattern.
3563 [(set (match_operand:SF 0 "register_operand" "=f")
3564 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3565 "! TARGET_SOFT_FLOAT"
3566 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3567 [(set_attr "type" "fpalu")
3568 (set_attr "length" "8")])
3570 (define_insn "floatsisf2"
3571 [(set (match_operand:SF 0 "register_operand" "=f")
3572 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3573 "! TARGET_SOFT_FLOAT"
3574 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3575 [(set_attr "type" "fpalu")
3576 (set_attr "length" "4")])
3578 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3579 ;; to be reloaded by putting the constant into memory.
3580 ;; It must come before the more general floatsidf2 pattern.
3582 [(set (match_operand:DF 0 "register_operand" "=f")
3583 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3584 "! TARGET_SOFT_FLOAT"
3585 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3586 [(set_attr "type" "fpalu")
3587 (set_attr "length" "8")])
3589 (define_insn "floatsidf2"
3590 [(set (match_operand:DF 0 "register_operand" "=f")
3591 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3592 "! TARGET_SOFT_FLOAT"
3593 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3594 [(set_attr "type" "fpalu")
3595 (set_attr "length" "4")])
3597 (define_expand "floatunssisf2"
3598 [(set (subreg:SI (match_dup 2) 4)
3599 (match_operand:SI 1 "register_operand" ""))
3600 (set (subreg:SI (match_dup 2) 0)
3602 (set (match_operand:SF 0 "register_operand" "")
3603 (float:SF (match_dup 2)))]
3604 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3609 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3612 operands[2] = gen_reg_rtx (DImode);
3615 (define_expand "floatunssidf2"
3616 [(set (subreg:SI (match_dup 2) 4)
3617 (match_operand:SI 1 "register_operand" ""))
3618 (set (subreg:SI (match_dup 2) 0)
3620 (set (match_operand:DF 0 "register_operand" "")
3621 (float:DF (match_dup 2)))]
3622 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3627 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3630 operands[2] = gen_reg_rtx (DImode);
3633 (define_insn "floatdisf2"
3634 [(set (match_operand:SF 0 "register_operand" "=f")
3635 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3636 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3637 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3638 [(set_attr "type" "fpalu")
3639 (set_attr "length" "4")])
3641 (define_insn "floatdidf2"
3642 [(set (match_operand:DF 0 "register_operand" "=f")
3643 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3644 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3645 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3646 [(set_attr "type" "fpalu")
3647 (set_attr "length" "4")])
3649 ;; Convert a float to an actual integer.
3650 ;; Truncation is performed as part of the conversion.
3652 (define_insn "fix_truncsfsi2"
3653 [(set (match_operand:SI 0 "register_operand" "=f")
3654 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3655 "! TARGET_SOFT_FLOAT"
3656 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3657 [(set_attr "type" "fpalu")
3658 (set_attr "length" "4")])
3660 (define_insn "fix_truncdfsi2"
3661 [(set (match_operand:SI 0 "register_operand" "=f")
3662 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3663 "! TARGET_SOFT_FLOAT"
3664 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3665 [(set_attr "type" "fpalu")
3666 (set_attr "length" "4")])
3668 (define_insn "fix_truncsfdi2"
3669 [(set (match_operand:DI 0 "register_operand" "=f")
3670 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3671 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3672 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3673 [(set_attr "type" "fpalu")
3674 (set_attr "length" "4")])
3676 (define_insn "fix_truncdfdi2"
3677 [(set (match_operand:DI 0 "register_operand" "=f")
3678 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3679 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3680 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3681 [(set_attr "type" "fpalu")
3682 (set_attr "length" "4")])
3684 (define_insn "floatunssidf2_pa20"
3685 [(set (match_operand:DF 0 "register_operand" "=f")
3686 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3687 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3689 [(set_attr "type" "fpalu")
3690 (set_attr "length" "4")])
3692 (define_insn "floatunssisf2_pa20"
3693 [(set (match_operand:SF 0 "register_operand" "=f")
3694 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3695 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3697 [(set_attr "type" "fpalu")
3698 (set_attr "length" "4")])
3700 (define_insn "floatunsdisf2"
3701 [(set (match_operand:SF 0 "register_operand" "=f")
3702 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3703 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3704 "fcnv,udw,sgl %1,%0"
3705 [(set_attr "type" "fpalu")
3706 (set_attr "length" "4")])
3708 (define_insn "floatunsdidf2"
3709 [(set (match_operand:DF 0 "register_operand" "=f")
3710 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3711 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3712 "fcnv,udw,dbl %1,%0"
3713 [(set_attr "type" "fpalu")
3714 (set_attr "length" "4")])
3716 (define_insn "fixuns_truncsfsi2"
3717 [(set (match_operand:SI 0 "register_operand" "=f")
3718 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3719 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3720 "fcnv,t,sgl,uw %1,%0"
3721 [(set_attr "type" "fpalu")
3722 (set_attr "length" "4")])
3724 (define_insn "fixuns_truncdfsi2"
3725 [(set (match_operand:SI 0 "register_operand" "=f")
3726 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3727 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3728 "fcnv,t,dbl,uw %1,%0"
3729 [(set_attr "type" "fpalu")
3730 (set_attr "length" "4")])
3732 (define_insn "fixuns_truncsfdi2"
3733 [(set (match_operand:DI 0 "register_operand" "=f")
3734 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3735 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3736 "fcnv,t,sgl,udw %1,%0"
3737 [(set_attr "type" "fpalu")
3738 (set_attr "length" "4")])
3740 (define_insn "fixuns_truncdfdi2"
3741 [(set (match_operand:DI 0 "register_operand" "=f")
3742 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3743 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3744 "fcnv,t,dbl,udw %1,%0"
3745 [(set_attr "type" "fpalu")
3746 (set_attr "length" "4")])
3748 ;;- arithmetic instructions
3750 (define_expand "adddi3"
3751 [(set (match_operand:DI 0 "register_operand" "")
3752 (plus:DI (match_operand:DI 1 "register_operand" "")
3753 (match_operand:DI 2 "arith_operand" "")))]
3757 ;; We allow arith_operand for operands2, even though strictly speaking it
3758 ;; we would prefer to us arith11_operand since that's what the hardware
3759 ;; can actually support.
3761 ;; But the price of the extra reload in that case is worth the simplicity
3762 ;; we get by allowing a trivial adddi3 expander to be used for both
3766 [(set (match_operand:DI 0 "register_operand" "=r")
3767 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3768 (match_operand:DI 2 "arith_operand" "rI")))]
3772 if (GET_CODE (operands[2]) == CONST_INT)
3774 if (INTVAL (operands[2]) >= 0)
3775 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3777 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3780 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3782 [(set_attr "type" "binary")
3783 (set_attr "length" "8")])
3786 [(set (match_operand:DI 0 "register_operand" "=r,r")
3787 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3788 (match_operand:DI 2 "arith_operand" "r,J")))]
3791 {addl|add,l} %1,%2,%0
3793 [(set_attr "type" "binary,binary")
3794 (set_attr "pa_combine_type" "addmove")
3795 (set_attr "length" "4,4")])
3798 [(set (match_operand:DI 0 "register_operand" "=r")
3799 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3800 (match_operand:DI 2 "register_operand" "r")))]
3803 [(set_attr "type" "binary")
3804 (set_attr "length" "4")])
3807 [(set (match_operand:SI 0 "register_operand" "=r")
3808 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3809 (match_operand:SI 2 "register_operand" "r")))]
3812 [(set_attr "type" "binary")
3813 (set_attr "length" "4")])
3815 ;; define_splits to optimize cases of adding a constant integer
3816 ;; to a register when the constant does not fit in 14 bits. */
3818 [(set (match_operand:SI 0 "register_operand" "")
3819 (plus:SI (match_operand:SI 1 "register_operand" "")
3820 (match_operand:SI 2 "const_int_operand" "")))
3821 (clobber (match_operand:SI 4 "register_operand" ""))]
3822 "! cint_ok_for_move (INTVAL (operands[2]))
3823 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3824 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3825 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3828 int val = INTVAL (operands[2]);
3829 int low = (val < 0) ? -0x2000 : 0x1fff;
3830 int rest = val - low;
3832 operands[2] = GEN_INT (rest);
3833 operands[3] = GEN_INT (low);
3837 [(set (match_operand:SI 0 "register_operand" "")
3838 (plus:SI (match_operand:SI 1 "register_operand" "")
3839 (match_operand:SI 2 "const_int_operand" "")))
3840 (clobber (match_operand:SI 4 "register_operand" ""))]
3841 "! cint_ok_for_move (INTVAL (operands[2]))"
3842 [(set (match_dup 4) (match_dup 2))
3843 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3847 HOST_WIDE_INT intval = INTVAL (operands[2]);
3849 /* Try dividing the constant by 2, then 4, and finally 8 to see
3850 if we can get a constant which can be loaded into a register
3851 in a single instruction (cint_ok_for_move).
3853 If that fails, try to negate the constant and subtract it
3854 from our input operand. */
3855 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3857 operands[2] = GEN_INT (intval / 2);
3858 operands[3] = GEN_INT (2);
3860 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3862 operands[2] = GEN_INT (intval / 4);
3863 operands[3] = GEN_INT (4);
3865 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3867 operands[2] = GEN_INT (intval / 8);
3868 operands[3] = GEN_INT (8);
3870 else if (cint_ok_for_move (-intval))
3872 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3873 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3880 (define_insn "addsi3"
3881 [(set (match_operand:SI 0 "register_operand" "=r,r")
3882 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3883 (match_operand:SI 2 "arith_operand" "r,J")))]
3886 {addl|add,l} %1,%2,%0
3888 [(set_attr "type" "binary,binary")
3889 (set_attr "pa_combine_type" "addmove")
3890 (set_attr "length" "4,4")])
3892 (define_expand "subdi3"
3893 [(set (match_operand:DI 0 "register_operand" "")
3894 (minus:DI (match_operand:DI 1 "register_operand" "")
3895 (match_operand:DI 2 "register_operand" "")))]
3900 [(set (match_operand:DI 0 "register_operand" "=r")
3901 (minus:DI (match_operand:DI 1 "register_operand" "r")
3902 (match_operand:DI 2 "register_operand" "r")))]
3904 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3905 [(set_attr "type" "binary")
3906 (set_attr "length" "8")])
3909 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3910 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3911 (match_operand:DI 2 "register_operand" "r,r,r")))]
3917 [(set_attr "type" "binary,binary,move")
3918 (set_attr "length" "4,4,4")])
3920 (define_expand "subsi3"
3921 [(set (match_operand:SI 0 "register_operand" "")
3922 (minus:SI (match_operand:SI 1 "arith11_operand" "")
3923 (match_operand:SI 2 "register_operand" "")))]
3928 [(set (match_operand:SI 0 "register_operand" "=r,r")
3929 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
3930 (match_operand:SI 2 "register_operand" "r,r")))]
3935 [(set_attr "type" "binary,binary")
3936 (set_attr "length" "4,4")])
3939 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
3940 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
3941 (match_operand:SI 2 "register_operand" "r,r,r")))]
3947 [(set_attr "type" "binary,binary,move")
3948 (set_attr "length" "4,4,4")])
3950 ;; Clobbering a "register_operand" instead of a match_scratch
3951 ;; in operand3 of millicode calls avoids spilling %r1 and
3952 ;; produces better code.
3954 ;; The mulsi3 insns set up registers for the millicode call.
3955 (define_expand "mulsi3"
3956 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
3957 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
3958 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
3959 (clobber (match_dup 3))
3960 (clobber (reg:SI 26))
3961 (clobber (reg:SI 25))
3962 (clobber (match_dup 4))])
3963 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
3967 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
3968 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
3970 rtx scratch = gen_reg_rtx (DImode);
3971 operands[1] = force_reg (SImode, operands[1]);
3972 operands[2] = force_reg (SImode, operands[2]);
3973 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
3974 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
3975 gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode))));
3978 operands[3] = gen_reg_rtx (SImode);
3981 (define_insn "umulsidi3"
3982 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3983 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3984 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
3985 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
3987 [(set_attr "type" "fpmuldbl")
3988 (set_attr "length" "4")])
3991 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
3992 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
3993 (match_operand:DI 2 "uint32_operand" "f")))]
3994 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
3996 [(set_attr "type" "fpmuldbl")
3997 (set_attr "length" "4")])
4000 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4001 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4002 (match_operand:DI 2 "uint32_operand" "f")))]
4003 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
4005 [(set_attr "type" "fpmuldbl")
4006 (set_attr "length" "4")])
4009 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4010 (clobber (match_operand:SI 0 "register_operand" "=a"))
4011 (clobber (reg:SI 26))
4012 (clobber (reg:SI 25))
4013 (clobber (reg:SI 31))]
4015 "* return output_mul_insn (0, insn);"
4016 [(set_attr "type" "milli")
4017 (set (attr "length")
4019 ;; Target (or stub) within reach
4020 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4022 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4027 (ne (symbol_ref "flag_pic")
4031 ;; Out of reach PORTABLE_RUNTIME
4032 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4036 ;; Out of reach, can use ble
4040 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4041 (clobber (match_operand:SI 0 "register_operand" "=a"))
4042 (clobber (reg:SI 26))
4043 (clobber (reg:SI 25))
4044 (clobber (reg:SI 2))]
4046 "* return output_mul_insn (0, insn);"
4047 [(set_attr "type" "milli")
4048 (set (attr "length") (const_int 4))])
4050 (define_expand "muldi3"
4051 [(set (match_operand:DI 0 "register_operand" "")
4052 (mult:DI (match_operand:DI 1 "register_operand" "")
4053 (match_operand:DI 2 "register_operand" "")))]
4054 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4057 rtx low_product = gen_reg_rtx (DImode);
4058 rtx cross_product1 = gen_reg_rtx (DImode);
4059 rtx cross_product2 = gen_reg_rtx (DImode);
4060 rtx cross_scratch = gen_reg_rtx (DImode);
4061 rtx cross_product = gen_reg_rtx (DImode);
4062 rtx op1l, op1r, op2l, op2r;
4063 rtx op1shifted, op2shifted;
4065 op1shifted = gen_reg_rtx (DImode);
4066 op2shifted = gen_reg_rtx (DImode);
4067 op1l = gen_reg_rtx (SImode);
4068 op1r = gen_reg_rtx (SImode);
4069 op2l = gen_reg_rtx (SImode);
4070 op2r = gen_reg_rtx (SImode);
4072 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
4074 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
4076 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
4077 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
4078 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
4079 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
4081 /* Emit multiplies for the cross products. */
4082 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
4083 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
4085 /* Emit a multiply for the low sub-word. */
4086 emit_insn (gen_umulsidi3 (low_product, op2r, op1r));
4088 /* Sum the cross products and shift them into proper position. */
4089 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
4090 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
4092 /* Add the cross product to the low product and store the result
4093 into the output operand . */
4094 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
4098 ;;; Division and mod.
4099 (define_expand "divsi3"
4100 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4101 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4102 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
4103 (clobber (match_dup 3))
4104 (clobber (match_dup 4))
4105 (clobber (reg:SI 26))
4106 (clobber (reg:SI 25))
4107 (clobber (match_dup 5))])
4108 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4112 operands[3] = gen_reg_rtx (SImode);
4115 operands[5] = gen_rtx_REG (SImode, 2);
4116 operands[4] = operands[5];
4120 operands[5] = gen_rtx_REG (SImode, 31);
4121 operands[4] = gen_reg_rtx (SImode);
4123 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
4129 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4130 (clobber (match_operand:SI 1 "register_operand" "=a"))
4131 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4132 (clobber (reg:SI 26))
4133 (clobber (reg:SI 25))
4134 (clobber (reg:SI 31))]
4137 return output_div_insn (operands, 0, insn);"
4138 [(set_attr "type" "milli")
4139 (set (attr "length")
4141 ;; Target (or stub) within reach
4142 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4144 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4149 (ne (symbol_ref "flag_pic")
4153 ;; Out of reach PORTABLE_RUNTIME
4154 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4158 ;; Out of reach, can use ble
4163 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4164 (clobber (match_operand:SI 1 "register_operand" "=a"))
4165 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4166 (clobber (reg:SI 26))
4167 (clobber (reg:SI 25))
4168 (clobber (reg:SI 2))]
4171 return output_div_insn (operands, 0, insn);"
4172 [(set_attr "type" "milli")
4173 (set (attr "length") (const_int 4))])
4175 (define_expand "udivsi3"
4176 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4177 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4178 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
4179 (clobber (match_dup 3))
4180 (clobber (match_dup 4))
4181 (clobber (reg:SI 26))
4182 (clobber (reg:SI 25))
4183 (clobber (match_dup 5))])
4184 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4188 operands[3] = gen_reg_rtx (SImode);
4191 operands[5] = gen_rtx_REG (SImode, 2);
4192 operands[4] = operands[5];
4196 operands[5] = gen_rtx_REG (SImode, 31);
4197 operands[4] = gen_reg_rtx (SImode);
4199 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4205 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4206 (clobber (match_operand:SI 1 "register_operand" "=a"))
4207 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4208 (clobber (reg:SI 26))
4209 (clobber (reg:SI 25))
4210 (clobber (reg:SI 31))]
4213 return output_div_insn (operands, 1, insn);"
4214 [(set_attr "type" "milli")
4215 (set (attr "length")
4217 ;; Target (or stub) within reach
4218 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4220 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4225 (ne (symbol_ref "flag_pic")
4229 ;; Out of reach PORTABLE_RUNTIME
4230 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4234 ;; Out of reach, can use ble
4239 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4240 (clobber (match_operand:SI 1 "register_operand" "=a"))
4241 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4242 (clobber (reg:SI 26))
4243 (clobber (reg:SI 25))
4244 (clobber (reg:SI 2))]
4247 return output_div_insn (operands, 1, insn);"
4248 [(set_attr "type" "milli")
4249 (set (attr "length") (const_int 4))])
4251 (define_expand "modsi3"
4252 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4253 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4254 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4255 (clobber (match_dup 3))
4256 (clobber (match_dup 4))
4257 (clobber (reg:SI 26))
4258 (clobber (reg:SI 25))
4259 (clobber (match_dup 5))])
4260 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4266 operands[5] = gen_rtx_REG (SImode, 2);
4267 operands[4] = operands[5];
4271 operands[5] = gen_rtx_REG (SImode, 31);
4272 operands[4] = gen_reg_rtx (SImode);
4274 operands[3] = gen_reg_rtx (SImode);
4278 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4279 (clobber (match_operand:SI 0 "register_operand" "=a"))
4280 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4281 (clobber (reg:SI 26))
4282 (clobber (reg:SI 25))
4283 (clobber (reg:SI 31))]
4286 return output_mod_insn (0, insn);"
4287 [(set_attr "type" "milli")
4288 (set (attr "length")
4290 ;; Target (or stub) within reach
4291 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4293 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4298 (ne (symbol_ref "flag_pic")
4302 ;; Out of reach PORTABLE_RUNTIME
4303 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4307 ;; Out of reach, can use ble
4311 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4312 (clobber (match_operand:SI 0 "register_operand" "=a"))
4313 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4314 (clobber (reg:SI 26))
4315 (clobber (reg:SI 25))
4316 (clobber (reg:SI 2))]
4319 return output_mod_insn (0, insn);"
4320 [(set_attr "type" "milli")
4321 (set (attr "length") (const_int 4))])
4323 (define_expand "umodsi3"
4324 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4325 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4326 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4327 (clobber (match_dup 3))
4328 (clobber (match_dup 4))
4329 (clobber (reg:SI 26))
4330 (clobber (reg:SI 25))
4331 (clobber (match_dup 5))])
4332 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4338 operands[5] = gen_rtx_REG (SImode, 2);
4339 operands[4] = operands[5];
4343 operands[5] = gen_rtx_REG (SImode, 31);
4344 operands[4] = gen_reg_rtx (SImode);
4346 operands[3] = gen_reg_rtx (SImode);
4350 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4351 (clobber (match_operand:SI 0 "register_operand" "=a"))
4352 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4353 (clobber (reg:SI 26))
4354 (clobber (reg:SI 25))
4355 (clobber (reg:SI 31))]
4358 return output_mod_insn (1, insn);"
4359 [(set_attr "type" "milli")
4360 (set (attr "length")
4362 ;; Target (or stub) within reach
4363 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
4365 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
4370 (ne (symbol_ref "flag_pic")
4374 ;; Out of reach PORTABLE_RUNTIME
4375 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
4379 ;; Out of reach, can use ble
4383 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4384 (clobber (match_operand:SI 0 "register_operand" "=a"))
4385 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4386 (clobber (reg:SI 26))
4387 (clobber (reg:SI 25))
4388 (clobber (reg:SI 2))]
4391 return output_mod_insn (1, insn);"
4392 [(set_attr "type" "milli")
4393 (set (attr "length") (const_int 4))])
4395 ;;- and instructions
4396 ;; We define DImode `and` so with DImode `not` we can get
4397 ;; DImode `andn`. Other combinations are possible.
4399 (define_expand "anddi3"
4400 [(set (match_operand:DI 0 "register_operand" "")
4401 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4402 (match_operand:DI 2 "arith_double_operand" "")))]
4406 if (! register_operand (operands[1], DImode)
4407 || ! register_operand (operands[2], DImode))
4408 /* Let GCC break this into word-at-a-time operations. */
4413 [(set (match_operand:DI 0 "register_operand" "=r")
4414 (and:DI (match_operand:DI 1 "register_operand" "%r")
4415 (match_operand:DI 2 "register_operand" "r")))]
4417 "and %1,%2,%0\;and %R1,%R2,%R0"
4418 [(set_attr "type" "binary")
4419 (set_attr "length" "8")])
4422 [(set (match_operand:DI 0 "register_operand" "=r,r")
4423 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4424 (match_operand:DI 2 "and_operand" "rO,P")))]
4426 "* return output_64bit_and (operands); "
4427 [(set_attr "type" "binary")
4428 (set_attr "length" "4")])
4430 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4431 ; constant with ldil;ldo.
4432 (define_insn "andsi3"
4433 [(set (match_operand:SI 0 "register_operand" "=r,r")
4434 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4435 (match_operand:SI 2 "and_operand" "rO,P")))]
4437 "* return output_and (operands); "
4438 [(set_attr "type" "binary,shift")
4439 (set_attr "length" "4,4")])
4442 [(set (match_operand:DI 0 "register_operand" "=r")
4443 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4444 (match_operand:DI 2 "register_operand" "r")))]
4446 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4447 [(set_attr "type" "binary")
4448 (set_attr "length" "8")])
4451 [(set (match_operand:DI 0 "register_operand" "=r")
4452 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4453 (match_operand:DI 2 "register_operand" "r")))]
4456 [(set_attr "type" "binary")
4457 (set_attr "length" "4")])
4460 [(set (match_operand:SI 0 "register_operand" "=r")
4461 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4462 (match_operand:SI 2 "register_operand" "r")))]
4465 [(set_attr "type" "binary")
4466 (set_attr "length" "4")])
4468 (define_expand "iordi3"
4469 [(set (match_operand:DI 0 "register_operand" "")
4470 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4471 (match_operand:DI 2 "arith_double_operand" "")))]
4475 if (! register_operand (operands[1], DImode)
4476 || ! register_operand (operands[2], DImode))
4477 /* Let GCC break this into word-at-a-time operations. */
4482 [(set (match_operand:DI 0 "register_operand" "=r")
4483 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4484 (match_operand:DI 2 "register_operand" "r")))]
4486 "or %1,%2,%0\;or %R1,%R2,%R0"
4487 [(set_attr "type" "binary")
4488 (set_attr "length" "8")])
4491 [(set (match_operand:DI 0 "register_operand" "=r,r")
4492 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4493 (match_operand:DI 2 "ior_operand" "M,i")))]
4495 "* return output_64bit_ior (operands); "
4496 [(set_attr "type" "binary,shift")
4497 (set_attr "length" "4,4")])
4500 [(set (match_operand:DI 0 "register_operand" "=r")
4501 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4502 (match_operand:DI 2 "register_operand" "r")))]
4505 [(set_attr "type" "binary")
4506 (set_attr "length" "4")])
4508 ;; Need a define_expand because we've run out of CONST_OK... characters.
4509 (define_expand "iorsi3"
4510 [(set (match_operand:SI 0 "register_operand" "")
4511 (ior:SI (match_operand:SI 1 "register_operand" "")
4512 (match_operand:SI 2 "arith32_operand" "")))]
4516 if (! (ior_operand (operands[2], SImode)
4517 || register_operand (operands[2], SImode)))
4518 operands[2] = force_reg (SImode, operands[2]);
4522 [(set (match_operand:SI 0 "register_operand" "=r,r")
4523 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4524 (match_operand:SI 2 "ior_operand" "M,i")))]
4526 "* return output_ior (operands); "
4527 [(set_attr "type" "binary,shift")
4528 (set_attr "length" "4,4")])
4531 [(set (match_operand:SI 0 "register_operand" "=r")
4532 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4533 (match_operand:SI 2 "register_operand" "r")))]
4536 [(set_attr "type" "binary")
4537 (set_attr "length" "4")])
4539 (define_expand "xordi3"
4540 [(set (match_operand:DI 0 "register_operand" "")
4541 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4542 (match_operand:DI 2 "arith_double_operand" "")))]
4546 if (! register_operand (operands[1], DImode)
4547 || ! register_operand (operands[2], DImode))
4548 /* Let GCC break this into word-at-a-time operations. */
4553 [(set (match_operand:DI 0 "register_operand" "=r")
4554 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4555 (match_operand:DI 2 "register_operand" "r")))]
4557 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4558 [(set_attr "type" "binary")
4559 (set_attr "length" "8")])
4562 [(set (match_operand:DI 0 "register_operand" "=r")
4563 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4564 (match_operand:DI 2 "register_operand" "r")))]
4567 [(set_attr "type" "binary")
4568 (set_attr "length" "4")])
4570 (define_insn "xorsi3"
4571 [(set (match_operand:SI 0 "register_operand" "=r")
4572 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4573 (match_operand:SI 2 "register_operand" "r")))]
4576 [(set_attr "type" "binary")
4577 (set_attr "length" "4")])
4579 (define_expand "negdi2"
4580 [(set (match_operand:DI 0 "register_operand" "")
4581 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4586 [(set (match_operand:DI 0 "register_operand" "=r")
4587 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4589 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4590 [(set_attr "type" "unary")
4591 (set_attr "length" "8")])
4594 [(set (match_operand:DI 0 "register_operand" "=r")
4595 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4598 [(set_attr "type" "unary")
4599 (set_attr "length" "4")])
4601 (define_insn "negsi2"
4602 [(set (match_operand:SI 0 "register_operand" "=r")
4603 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4606 [(set_attr "type" "unary")
4607 (set_attr "length" "4")])
4609 (define_expand "one_cmpldi2"
4610 [(set (match_operand:DI 0 "register_operand" "")
4611 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4615 if (! register_operand (operands[1], DImode))
4620 [(set (match_operand:DI 0 "register_operand" "=r")
4621 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4623 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4624 [(set_attr "type" "unary")
4625 (set_attr "length" "8")])
4628 [(set (match_operand:DI 0 "register_operand" "=r")
4629 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4632 [(set_attr "type" "unary")
4633 (set_attr "length" "4")])
4635 (define_insn "one_cmplsi2"
4636 [(set (match_operand:SI 0 "register_operand" "=r")
4637 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4640 [(set_attr "type" "unary")
4641 (set_attr "length" "4")])
4643 ;; Floating point arithmetic instructions.
4645 (define_insn "adddf3"
4646 [(set (match_operand:DF 0 "register_operand" "=f")
4647 (plus:DF (match_operand:DF 1 "register_operand" "f")
4648 (match_operand:DF 2 "register_operand" "f")))]
4649 "! TARGET_SOFT_FLOAT"
4651 [(set_attr "type" "fpalu")
4652 (set_attr "pa_combine_type" "faddsub")
4653 (set_attr "length" "4")])
4655 (define_insn "addsf3"
4656 [(set (match_operand:SF 0 "register_operand" "=f")
4657 (plus:SF (match_operand:SF 1 "register_operand" "f")
4658 (match_operand:SF 2 "register_operand" "f")))]
4659 "! TARGET_SOFT_FLOAT"
4661 [(set_attr "type" "fpalu")
4662 (set_attr "pa_combine_type" "faddsub")
4663 (set_attr "length" "4")])
4665 (define_insn "subdf3"
4666 [(set (match_operand:DF 0 "register_operand" "=f")
4667 (minus:DF (match_operand:DF 1 "register_operand" "f")
4668 (match_operand:DF 2 "register_operand" "f")))]
4669 "! TARGET_SOFT_FLOAT"
4671 [(set_attr "type" "fpalu")
4672 (set_attr "pa_combine_type" "faddsub")
4673 (set_attr "length" "4")])
4675 (define_insn "subsf3"
4676 [(set (match_operand:SF 0 "register_operand" "=f")
4677 (minus:SF (match_operand:SF 1 "register_operand" "f")
4678 (match_operand:SF 2 "register_operand" "f")))]
4679 "! TARGET_SOFT_FLOAT"
4681 [(set_attr "type" "fpalu")
4682 (set_attr "pa_combine_type" "faddsub")
4683 (set_attr "length" "4")])
4685 (define_insn "muldf3"
4686 [(set (match_operand:DF 0 "register_operand" "=f")
4687 (mult:DF (match_operand:DF 1 "register_operand" "f")
4688 (match_operand:DF 2 "register_operand" "f")))]
4689 "! TARGET_SOFT_FLOAT"
4691 [(set_attr "type" "fpmuldbl")
4692 (set_attr "pa_combine_type" "fmpy")
4693 (set_attr "length" "4")])
4695 (define_insn "mulsf3"
4696 [(set (match_operand:SF 0 "register_operand" "=f")
4697 (mult:SF (match_operand:SF 1 "register_operand" "f")
4698 (match_operand:SF 2 "register_operand" "f")))]
4699 "! TARGET_SOFT_FLOAT"
4701 [(set_attr "type" "fpmulsgl")
4702 (set_attr "pa_combine_type" "fmpy")
4703 (set_attr "length" "4")])
4705 (define_insn "divdf3"
4706 [(set (match_operand:DF 0 "register_operand" "=f")
4707 (div:DF (match_operand:DF 1 "register_operand" "f")
4708 (match_operand:DF 2 "register_operand" "f")))]
4709 "! TARGET_SOFT_FLOAT"
4711 [(set_attr "type" "fpdivdbl")
4712 (set_attr "length" "4")])
4714 (define_insn "divsf3"
4715 [(set (match_operand:SF 0 "register_operand" "=f")
4716 (div:SF (match_operand:SF 1 "register_operand" "f")
4717 (match_operand:SF 2 "register_operand" "f")))]
4718 "! TARGET_SOFT_FLOAT"
4720 [(set_attr "type" "fpdivsgl")
4721 (set_attr "length" "4")])
4723 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
4724 ;; negation can be done by subtracting from plus zero. However, this
4725 ;; violates the IEEE standard when negating plus and minus zero.
4726 (define_expand "negdf2"
4727 [(parallel [(set (match_operand:DF 0 "register_operand" "")
4728 (neg:DF (match_operand:DF 1 "register_operand" "")))
4729 (use (match_dup 2))])]
4730 "! TARGET_SOFT_FLOAT"
4732 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4733 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
4736 operands[2] = force_reg (DFmode, immed_real_const_1 (dconstm1, DFmode));
4737 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
4742 (define_insn "negdf2_fast"
4743 [(set (match_operand:DF 0 "register_operand" "=f")
4744 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4745 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4749 return \"fneg,dbl %1,%0\";
4751 return \"fsub,dbl %%fr0,%1,%0\";
4753 [(set_attr "type" "fpalu")
4754 (set_attr "length" "4")])
4756 (define_expand "negsf2"
4757 [(parallel [(set (match_operand:SF 0 "register_operand" "")
4758 (neg:SF (match_operand:SF 1 "register_operand" "")))
4759 (use (match_dup 2))])]
4760 "! TARGET_SOFT_FLOAT"
4762 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4763 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
4766 operands[2] = force_reg (SFmode, immed_real_const_1 (dconstm1, SFmode));
4767 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
4772 (define_insn "negsf2_fast"
4773 [(set (match_operand:SF 0 "register_operand" "=f")
4774 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4775 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4779 return \"fneg,sgl %1,%0\";
4781 return \"fsub,sgl %%fr0,%1,%0\";
4783 [(set_attr "type" "fpalu")
4784 (set_attr "length" "4")])
4786 (define_insn "absdf2"
4787 [(set (match_operand:DF 0 "register_operand" "=f")
4788 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4789 "! TARGET_SOFT_FLOAT"
4791 [(set_attr "type" "fpalu")
4792 (set_attr "length" "4")])
4794 (define_insn "abssf2"
4795 [(set (match_operand:SF 0 "register_operand" "=f")
4796 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4797 "! TARGET_SOFT_FLOAT"
4799 [(set_attr "type" "fpalu")
4800 (set_attr "length" "4")])
4802 (define_insn "sqrtdf2"
4803 [(set (match_operand:DF 0 "register_operand" "=f")
4804 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4805 "! TARGET_SOFT_FLOAT"
4807 [(set_attr "type" "fpsqrtdbl")
4808 (set_attr "length" "4")])
4810 (define_insn "sqrtsf2"
4811 [(set (match_operand:SF 0 "register_operand" "=f")
4812 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4813 "! TARGET_SOFT_FLOAT"
4815 [(set_attr "type" "fpsqrtsgl")
4816 (set_attr "length" "4")])
4818 ;; PA 2.0 floating point instructions
4822 [(set (match_operand:DF 0 "register_operand" "=f")
4823 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4824 (match_operand:DF 2 "register_operand" "f"))
4825 (match_operand:DF 3 "register_operand" "f")))]
4826 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4827 "fmpyfadd,dbl %1,%2,%3,%0"
4828 [(set_attr "type" "fpmuldbl")
4829 (set_attr "length" "4")])
4832 [(set (match_operand:DF 0 "register_operand" "=f")
4833 (plus:DF (match_operand:DF 1 "register_operand" "f")
4834 (mult:DF (match_operand:DF 2 "register_operand" "f")
4835 (match_operand:DF 3 "register_operand" "f"))))]
4836 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4837 "fmpyfadd,dbl %2,%3,%1,%0"
4838 [(set_attr "type" "fpmuldbl")
4839 (set_attr "length" "4")])
4842 [(set (match_operand:SF 0 "register_operand" "=f")
4843 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4844 (match_operand:SF 2 "register_operand" "f"))
4845 (match_operand:SF 3 "register_operand" "f")))]
4846 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4847 "fmpyfadd,sgl %1,%2,%3,%0"
4848 [(set_attr "type" "fpmulsgl")
4849 (set_attr "length" "4")])
4852 [(set (match_operand:SF 0 "register_operand" "=f")
4853 (plus:SF (match_operand:SF 1 "register_operand" "f")
4854 (mult:SF (match_operand:SF 2 "register_operand" "f")
4855 (match_operand:SF 3 "register_operand" "f"))))]
4856 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4857 "fmpyfadd,sgl %2,%3,%1,%0"
4858 [(set_attr "type" "fpmulsgl")
4859 (set_attr "length" "4")])
4861 ; fmpynfadd patterns
4863 [(set (match_operand:DF 0 "register_operand" "=f")
4864 (minus:DF (match_operand:DF 1 "register_operand" "f")
4865 (mult:DF (match_operand:DF 2 "register_operand" "f")
4866 (match_operand:DF 3 "register_operand" "f"))))]
4867 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4868 "fmpynfadd,dbl %2,%3,%1,%0"
4869 [(set_attr "type" "fpmuldbl")
4870 (set_attr "length" "4")])
4873 [(set (match_operand:SF 0 "register_operand" "=f")
4874 (minus:SF (match_operand:SF 1 "register_operand" "f")
4875 (mult:SF (match_operand:SF 2 "register_operand" "f")
4876 (match_operand:SF 3 "register_operand" "f"))))]
4877 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4878 "fmpynfadd,sgl %2,%3,%1,%0"
4879 [(set_attr "type" "fpmulsgl")
4880 (set_attr "length" "4")])
4884 [(set (match_operand:DF 0 "register_operand" "=f")
4885 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4886 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4888 [(set_attr "type" "fpalu")
4889 (set_attr "length" "4")])
4892 [(set (match_operand:SF 0 "register_operand" "=f")
4893 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4894 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4896 [(set_attr "type" "fpalu")
4897 (set_attr "length" "4")])
4899 ;; Generating a fused multiply sequence is a win for this case as it will
4900 ;; reduce the latency for the fused case without impacting the plain
4903 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4904 ;; perform two operations with the result of the first feeding the second.
4906 [(set (match_operand:DF 0 "register_operand" "=f")
4907 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4908 (match_operand:DF 2 "register_operand" "f"))
4909 (match_operand:DF 3 "register_operand" "f")))
4910 (set (match_operand:DF 4 "register_operand" "=&f")
4911 (mult:DF (match_dup 1) (match_dup 2)))]
4912 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4913 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4914 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4916 [(set_attr "type" "fpmuldbl")
4917 (set_attr "length" "8")])
4919 ;; We want to split this up during scheduling since we want both insns
4920 ;; to schedule independently.
4922 [(set (match_operand:DF 0 "register_operand" "")
4923 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4924 (match_operand:DF 2 "register_operand" ""))
4925 (match_operand:DF 3 "register_operand" "")))
4926 (set (match_operand:DF 4 "register_operand" "")
4927 (mult:DF (match_dup 1) (match_dup 2)))]
4928 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4929 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4930 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4935 [(set (match_operand:SF 0 "register_operand" "=f")
4936 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4937 (match_operand:SF 2 "register_operand" "f"))
4938 (match_operand:SF 3 "register_operand" "f")))
4939 (set (match_operand:SF 4 "register_operand" "=&f")
4940 (mult:SF (match_dup 1) (match_dup 2)))]
4941 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4942 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4943 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4945 [(set_attr "type" "fpmuldbl")
4946 (set_attr "length" "8")])
4948 ;; We want to split this up during scheduling since we want both insns
4949 ;; to schedule independently.
4951 [(set (match_operand:SF 0 "register_operand" "")
4952 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
4953 (match_operand:SF 2 "register_operand" ""))
4954 (match_operand:SF 3 "register_operand" "")))
4955 (set (match_operand:SF 4 "register_operand" "")
4956 (mult:SF (match_dup 1) (match_dup 2)))]
4957 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4958 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4959 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
4963 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
4966 [(set (match_operand:DF 0 "register_operand" "=f")
4967 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4968 (match_operand:DF 2 "register_operand" "f"))))]
4969 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4970 "fmpynfadd,dbl %1,%2,%%fr0,%0"
4971 [(set_attr "type" "fpmuldbl")
4972 (set_attr "length" "4")])
4975 [(set (match_operand:SF 0 "register_operand" "=f")
4976 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4977 (match_operand:SF 2 "register_operand" "f"))))]
4978 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4979 "fmpynfadd,sgl %1,%2,%%fr0,%0"
4980 [(set_attr "type" "fpmuldbl")
4981 (set_attr "length" "4")])
4984 [(set (match_operand:DF 0 "register_operand" "=f")
4985 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4986 (match_operand:DF 2 "register_operand" "f"))))
4987 (set (match_operand:DF 3 "register_operand" "=&f")
4988 (mult:DF (match_dup 1) (match_dup 2)))]
4989 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4990 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4991 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4993 [(set_attr "type" "fpmuldbl")
4994 (set_attr "length" "8")])
4997 [(set (match_operand:DF 0 "register_operand" "")
4998 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4999 (match_operand:DF 2 "register_operand" ""))))
5000 (set (match_operand:DF 3 "register_operand" "")
5001 (mult:DF (match_dup 1) (match_dup 2)))]
5002 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5003 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
5004 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
5008 [(set (match_operand:SF 0 "register_operand" "=f")
5009 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5010 (match_operand:SF 2 "register_operand" "f"))))
5011 (set (match_operand:SF 3 "register_operand" "=&f")
5012 (mult:SF (match_dup 1) (match_dup 2)))]
5013 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5014 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5015 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5017 [(set_attr "type" "fpmuldbl")
5018 (set_attr "length" "8")])
5021 [(set (match_operand:SF 0 "register_operand" "")
5022 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5023 (match_operand:SF 2 "register_operand" ""))))
5024 (set (match_operand:SF 3 "register_operand" "")
5025 (mult:SF (match_dup 1) (match_dup 2)))]
5026 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5027 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5028 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5031 ;; Now fused multiplies with the result of the multiply negated.
5033 [(set (match_operand:DF 0 "register_operand" "=f")
5034 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5035 (match_operand:DF 2 "register_operand" "f")))
5036 (match_operand:DF 3 "register_operand" "f")))]
5037 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5038 "fmpynfadd,dbl %1,%2,%3,%0"
5039 [(set_attr "type" "fpmuldbl")
5040 (set_attr "length" "4")])
5043 [(set (match_operand:SF 0 "register_operand" "=f")
5044 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5045 (match_operand:SF 2 "register_operand" "f")))
5046 (match_operand:SF 3 "register_operand" "f")))]
5047 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5048 "fmpynfadd,sgl %1,%2,%3,%0"
5049 [(set_attr "type" "fpmuldbl")
5050 (set_attr "length" "4")])
5053 [(set (match_operand:DF 0 "register_operand" "=f")
5054 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5055 (match_operand:DF 2 "register_operand" "f")))
5056 (match_operand:DF 3 "register_operand" "f")))
5057 (set (match_operand:DF 4 "register_operand" "=&f")
5058 (mult:DF (match_dup 1) (match_dup 2)))]
5059 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5060 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5061 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5063 [(set_attr "type" "fpmuldbl")
5064 (set_attr "length" "8")])
5067 [(set (match_operand:DF 0 "register_operand" "")
5068 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5069 (match_operand:DF 2 "register_operand" "")))
5070 (match_operand:DF 3 "register_operand" "")))
5071 (set (match_operand:DF 4 "register_operand" "")
5072 (mult:DF (match_dup 1) (match_dup 2)))]
5073 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5074 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5075 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
5080 [(set (match_operand:SF 0 "register_operand" "=f")
5081 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5082 (match_operand:SF 2 "register_operand" "f")))
5083 (match_operand:SF 3 "register_operand" "f")))
5084 (set (match_operand:SF 4 "register_operand" "=&f")
5085 (mult:SF (match_dup 1) (match_dup 2)))]
5086 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5087 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5088 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5090 [(set_attr "type" "fpmuldbl")
5091 (set_attr "length" "8")])
5094 [(set (match_operand:SF 0 "register_operand" "")
5095 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5096 (match_operand:SF 2 "register_operand" "")))
5097 (match_operand:SF 3 "register_operand" "")))
5098 (set (match_operand:SF 4 "register_operand" "")
5099 (mult:SF (match_dup 1) (match_dup 2)))]
5100 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5101 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5102 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
5107 [(set (match_operand:DF 0 "register_operand" "=f")
5108 (minus:DF (match_operand:DF 3 "register_operand" "f")
5109 (mult:DF (match_operand:DF 1 "register_operand" "f")
5110 (match_operand:DF 2 "register_operand" "f"))))
5111 (set (match_operand:DF 4 "register_operand" "=&f")
5112 (mult:DF (match_dup 1) (match_dup 2)))]
5113 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5114 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5115 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5117 [(set_attr "type" "fpmuldbl")
5118 (set_attr "length" "8")])
5121 [(set (match_operand:DF 0 "register_operand" "")
5122 (minus:DF (match_operand:DF 3 "register_operand" "")
5123 (mult:DF (match_operand:DF 1 "register_operand" "")
5124 (match_operand:DF 2 "register_operand" ""))))
5125 (set (match_operand:DF 4 "register_operand" "")
5126 (mult:DF (match_dup 1) (match_dup 2)))]
5127 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5128 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5129 (set (match_dup 0) (minus:DF (match_dup 3)
5130 (mult:DF (match_dup 1) (match_dup 2))))]
5134 [(set (match_operand:SF 0 "register_operand" "=f")
5135 (minus:SF (match_operand:SF 3 "register_operand" "f")
5136 (mult:SF (match_operand:SF 1 "register_operand" "f")
5137 (match_operand:SF 2 "register_operand" "f"))))
5138 (set (match_operand:SF 4 "register_operand" "=&f")
5139 (mult:SF (match_dup 1) (match_dup 2)))]
5140 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5141 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5142 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5144 [(set_attr "type" "fpmuldbl")
5145 (set_attr "length" "8")])
5148 [(set (match_operand:SF 0 "register_operand" "")
5149 (minus:SF (match_operand:SF 3 "register_operand" "")
5150 (mult:SF (match_operand:SF 1 "register_operand" "")
5151 (match_operand:SF 2 "register_operand" ""))))
5152 (set (match_operand:SF 4 "register_operand" "")
5153 (mult:SF (match_dup 1) (match_dup 2)))]
5154 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5155 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5156 (set (match_dup 0) (minus:SF (match_dup 3)
5157 (mult:SF (match_dup 1) (match_dup 2))))]
5161 [(set (match_operand:DF 0 "register_operand" "=f")
5162 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5163 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5164 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5165 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5167 [(set_attr "type" "fpalu")
5168 (set_attr "length" "8")])
5171 [(set (match_operand:DF 0 "register_operand" "")
5172 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
5173 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
5174 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5175 [(set (match_dup 2) (abs:DF (match_dup 1)))
5176 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
5180 [(set (match_operand:SF 0 "register_operand" "=f")
5181 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5182 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5183 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5184 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5186 [(set_attr "type" "fpalu")
5187 (set_attr "length" "8")])
5190 [(set (match_operand:SF 0 "register_operand" "")
5191 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
5192 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
5193 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5194 [(set (match_dup 2) (abs:SF (match_dup 1)))
5195 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
5198 ;;- Shift instructions
5200 ;; Optimized special case of shifting.
5203 [(set (match_operand:SI 0 "register_operand" "=r")
5204 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5208 [(set_attr "type" "load")
5209 (set_attr "length" "4")])
5212 [(set (match_operand:SI 0 "register_operand" "=r")
5213 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5217 [(set_attr "type" "load")
5218 (set_attr "length" "4")])
5221 [(set (match_operand:SI 0 "register_operand" "=r")
5222 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
5223 (match_operand:SI 3 "shadd_operand" ""))
5224 (match_operand:SI 1 "register_operand" "r")))]
5226 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
5227 [(set_attr "type" "binary")
5228 (set_attr "length" "4")])
5231 [(set (match_operand:DI 0 "register_operand" "=r")
5232 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
5233 (match_operand:DI 3 "shadd_operand" ""))
5234 (match_operand:DI 1 "register_operand" "r")))]
5236 "shladd,l %2,%O3,%1,%0"
5237 [(set_attr "type" "binary")
5238 (set_attr "length" "4")])
5240 (define_expand "ashlsi3"
5241 [(set (match_operand:SI 0 "register_operand" "")
5242 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
5243 (match_operand:SI 2 "arith32_operand" "")))]
5247 if (GET_CODE (operands[2]) != CONST_INT)
5249 rtx temp = gen_reg_rtx (SImode);
5250 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5251 if (GET_CODE (operands[1]) == CONST_INT)
5252 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
5254 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
5257 /* Make sure both inputs are not constants,
5258 there are no patterns for that. */
5259 operands[1] = force_reg (SImode, operands[1]);
5263 [(set (match_operand:SI 0 "register_operand" "=r")
5264 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5265 (match_operand:SI 2 "const_int_operand" "n")))]
5267 "{zdep|depw,z} %1,%P2,%L2,%0"
5268 [(set_attr "type" "shift")
5269 (set_attr "length" "4")])
5271 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5272 ; Doing it like this makes slightly better code since reload can
5273 ; replace a register with a known value in range -16..15 with a
5274 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5275 ; but since we have no more CONST_OK... characters, that is not
5277 (define_insn "zvdep32"
5278 [(set (match_operand:SI 0 "register_operand" "=r,r")
5279 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5280 (minus:SI (const_int 31)
5281 (match_operand:SI 2 "register_operand" "q,q"))))]
5284 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5285 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5286 [(set_attr "type" "shift,shift")
5287 (set_attr "length" "4,4")])
5289 (define_insn "zvdep_imm32"
5290 [(set (match_operand:SI 0 "register_operand" "=r")
5291 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5292 (minus:SI (const_int 31)
5293 (match_operand:SI 2 "register_operand" "q"))))]
5297 int x = INTVAL (operands[1]);
5298 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5299 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5300 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5302 [(set_attr "type" "shift")
5303 (set_attr "length" "4")])
5305 (define_insn "vdepi_ior"
5306 [(set (match_operand:SI 0 "register_operand" "=r")
5307 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5308 (minus:SI (const_int 31)
5309 (match_operand:SI 2 "register_operand" "q")))
5310 (match_operand:SI 3 "register_operand" "0")))]
5311 ; accept ...0001...1, can this be generalized?
5312 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5315 int x = INTVAL (operands[1]);
5316 operands[2] = GEN_INT (exact_log2 (x + 1));
5317 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5319 [(set_attr "type" "shift")
5320 (set_attr "length" "4")])
5322 (define_insn "vdepi_and"
5323 [(set (match_operand:SI 0 "register_operand" "=r")
5324 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5325 (minus:SI (const_int 31)
5326 (match_operand:SI 2 "register_operand" "q")))
5327 (match_operand:SI 3 "register_operand" "0")))]
5328 ; this can be generalized...!
5329 "INTVAL (operands[1]) == -2"
5332 int x = INTVAL (operands[1]);
5333 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5334 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5336 [(set_attr "type" "shift")
5337 (set_attr "length" "4")])
5339 (define_expand "ashldi3"
5340 [(set (match_operand:DI 0 "register_operand" "")
5341 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5342 (match_operand:DI 2 "arith32_operand" "")))]
5346 if (GET_CODE (operands[2]) != CONST_INT)
5348 rtx temp = gen_reg_rtx (DImode);
5349 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5350 if (GET_CODE (operands[1]) == CONST_INT)
5351 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5353 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5356 /* Make sure both inputs are not constants,
5357 there are no patterns for that. */
5358 operands[1] = force_reg (DImode, operands[1]);
5362 [(set (match_operand:DI 0 "register_operand" "=r")
5363 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5364 (match_operand:DI 2 "const_int_operand" "n")))]
5366 "depd,z %1,%p2,%Q2,%0"
5367 [(set_attr "type" "shift")
5368 (set_attr "length" "4")])
5370 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5371 ; Doing it like this makes slightly better code since reload can
5372 ; replace a register with a known value in range -16..15 with a
5373 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5374 ; but since we have no more CONST_OK... characters, that is not
5376 (define_insn "zvdep64"
5377 [(set (match_operand:DI 0 "register_operand" "=r,r")
5378 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5379 (minus:DI (const_int 63)
5380 (match_operand:DI 2 "register_operand" "q,q"))))]
5383 depd,z %1,%%sar,64,%0
5384 depdi,z %1,%%sar,64,%0"
5385 [(set_attr "type" "shift,shift")
5386 (set_attr "length" "4,4")])
5388 (define_insn "zvdep_imm64"
5389 [(set (match_operand:DI 0 "register_operand" "=r")
5390 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5391 (minus:DI (const_int 63)
5392 (match_operand:DI 2 "register_operand" "q"))))]
5396 int x = INTVAL (operands[1]);
5397 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5398 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5399 return \"depdi,z %1,%%sar,%2,%0\";
5401 [(set_attr "type" "shift")
5402 (set_attr "length" "4")])
5405 [(set (match_operand:DI 0 "register_operand" "=r")
5406 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5407 (minus:DI (const_int 63)
5408 (match_operand:DI 2 "register_operand" "q")))
5409 (match_operand:DI 3 "register_operand" "0")))]
5410 ; accept ...0001...1, can this be generalized?
5411 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5414 int x = INTVAL (operands[1]);
5415 operands[2] = GEN_INT (exact_log2 (x + 1));
5416 return \"depdi -1,%%sar,%2,%0\";
5418 [(set_attr "type" "shift")
5419 (set_attr "length" "4")])
5422 [(set (match_operand:DI 0 "register_operand" "=r")
5423 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5424 (minus:DI (const_int 63)
5425 (match_operand:DI 2 "register_operand" "q")))
5426 (match_operand:DI 3 "register_operand" "0")))]
5427 ; this can be generalized...!
5428 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5431 int x = INTVAL (operands[1]);
5432 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5433 return \"depdi 0,%%sar,%2,%0\";
5435 [(set_attr "type" "shift")
5436 (set_attr "length" "4")])
5438 (define_expand "ashrsi3"
5439 [(set (match_operand:SI 0 "register_operand" "")
5440 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5441 (match_operand:SI 2 "arith32_operand" "")))]
5445 if (GET_CODE (operands[2]) != CONST_INT)
5447 rtx temp = gen_reg_rtx (SImode);
5448 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5449 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5455 [(set (match_operand:SI 0 "register_operand" "=r")
5456 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5457 (match_operand:SI 2 "const_int_operand" "n")))]
5459 "{extrs|extrw,s} %1,%P2,%L2,%0"
5460 [(set_attr "type" "shift")
5461 (set_attr "length" "4")])
5463 (define_insn "vextrs32"
5464 [(set (match_operand:SI 0 "register_operand" "=r")
5465 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5466 (minus:SI (const_int 31)
5467 (match_operand:SI 2 "register_operand" "q"))))]
5469 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5470 [(set_attr "type" "shift")
5471 (set_attr "length" "4")])
5473 (define_expand "ashrdi3"
5474 [(set (match_operand:DI 0 "register_operand" "")
5475 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5476 (match_operand:DI 2 "arith32_operand" "")))]
5480 if (GET_CODE (operands[2]) != CONST_INT)
5482 rtx temp = gen_reg_rtx (DImode);
5483 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5484 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5490 [(set (match_operand:DI 0 "register_operand" "=r")
5491 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5492 (match_operand:DI 2 "const_int_operand" "n")))]
5494 "extrd,s %1,%p2,%Q2,%0"
5495 [(set_attr "type" "shift")
5496 (set_attr "length" "4")])
5498 (define_insn "vextrs64"
5499 [(set (match_operand:DI 0 "register_operand" "=r")
5500 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5501 (minus:DI (const_int 63)
5502 (match_operand:DI 2 "register_operand" "q"))))]
5504 "extrd,s %1,%%sar,64,%0"
5505 [(set_attr "type" "shift")
5506 (set_attr "length" "4")])
5508 (define_insn "lshrsi3"
5509 [(set (match_operand:SI 0 "register_operand" "=r,r")
5510 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5511 (match_operand:SI 2 "arith32_operand" "q,n")))]
5514 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5515 {extru|extrw,u} %1,%P2,%L2,%0"
5516 [(set_attr "type" "shift")
5517 (set_attr "length" "4")])
5519 (define_insn "lshrdi3"
5520 [(set (match_operand:DI 0 "register_operand" "=r,r")
5521 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5522 (match_operand:DI 2 "arith32_operand" "q,n")))]
5525 shrpd %%r0,%1,%%sar,%0
5526 extrd,u %1,%p2,%Q2,%0"
5527 [(set_attr "type" "shift")
5528 (set_attr "length" "4")])
5530 (define_insn "rotrsi3"
5531 [(set (match_operand:SI 0 "register_operand" "=r,r")
5532 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5533 (match_operand:SI 2 "arith32_operand" "q,n")))]
5537 if (GET_CODE (operands[2]) == CONST_INT)
5539 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5540 return \"{shd|shrpw} %1,%1,%2,%0\";
5543 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5545 [(set_attr "type" "shift")
5546 (set_attr "length" "4")])
5548 (define_expand "rotlsi3"
5549 [(set (match_operand:SI 0 "register_operand" "")
5550 (rotate:SI (match_operand:SI 1 "register_operand" "")
5551 (match_operand:SI 2 "arith32_operand" "")))]
5555 if (GET_CODE (operands[2]) != CONST_INT)
5557 rtx temp = gen_reg_rtx (SImode);
5558 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5559 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5562 /* Else expand normally. */
5566 [(set (match_operand:SI 0 "register_operand" "=r")
5567 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5568 (match_operand:SI 2 "const_int_operand" "n")))]
5572 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5573 return \"{shd|shrpw} %1,%1,%2,%0\";
5575 [(set_attr "type" "shift")
5576 (set_attr "length" "4")])
5579 [(set (match_operand:SI 0 "register_operand" "=r")
5580 (match_operator:SI 5 "plus_xor_ior_operator"
5581 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5582 (match_operand:SI 3 "const_int_operand" "n"))
5583 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5584 (match_operand:SI 4 "const_int_operand" "n"))]))]
5585 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5586 "{shd|shrpw} %1,%2,%4,%0"
5587 [(set_attr "type" "shift")
5588 (set_attr "length" "4")])
5591 [(set (match_operand:SI 0 "register_operand" "=r")
5592 (match_operator:SI 5 "plus_xor_ior_operator"
5593 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5594 (match_operand:SI 4 "const_int_operand" "n"))
5595 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5596 (match_operand:SI 3 "const_int_operand" "n"))]))]
5597 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5598 "{shd|shrpw} %1,%2,%4,%0"
5599 [(set_attr "type" "shift")
5600 (set_attr "length" "4")])
5603 [(set (match_operand:SI 0 "register_operand" "=r")
5604 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5605 (match_operand:SI 2 "const_int_operand" ""))
5606 (match_operand:SI 3 "const_int_operand" "")))]
5607 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5610 int cnt = INTVAL (operands[2]) & 31;
5611 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5612 operands[2] = GEN_INT (31 - cnt);
5613 return \"{zdep|depw,z} %1,%2,%3,%0\";
5615 [(set_attr "type" "shift")
5616 (set_attr "length" "4")])
5618 ;; Unconditional and other jump instructions.
5620 ;; This can only be used in a leaf function, so we do
5621 ;; not need to use the PIC register when generating PIC code.
5622 (define_insn "return"
5626 "hppa_can_use_return_insn_p ()"
5630 return \"bve%* (%%r2)\";
5631 return \"bv%* %%r0(%%r2)\";
5633 [(set_attr "type" "branch")
5634 (set_attr "length" "4")])
5636 ;; Emit a different pattern for functions which have non-trivial
5637 ;; epilogues so as not to confuse jump and reorg.
5638 (define_insn "return_internal"
5646 return \"bve%* (%%r2)\";
5647 return \"bv%* %%r0(%%r2)\";
5649 [(set_attr "type" "branch")
5650 (set_attr "length" "4")])
5652 ;; Use the PIC register to ensure it's restored after a
5653 ;; call in PIC mode.
5654 (define_insn "return_internal_pic"
5656 (use (match_operand 0 "register_operand" "r"))
5658 "flag_pic && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM"
5662 return \"bve%* (%%r2)\";
5663 return \"bv%* %%r0(%%r2)\";
5665 [(set_attr "type" "branch")
5666 (set_attr "length" "4")])
5668 ;; Use the PIC register to ensure it's restored after a
5669 ;; call in PIC mode. This is used for eh returns which
5670 ;; bypass the return stub.
5671 (define_insn "return_external_pic"
5673 (use (match_operand 0 "register_operand" "r"))
5675 (clobber (reg:SI 1))]
5677 && current_function_calls_eh_return
5678 && true_regnum (operands[0]) == PIC_OFFSET_TABLE_REGNUM"
5679 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
5680 [(set_attr "type" "branch")
5681 (set_attr "length" "12")])
5683 (define_expand "prologue"
5686 "hppa_expand_prologue ();DONE;")
5688 (define_expand "sibcall_epilogue"
5693 hppa_expand_epilogue ();
5697 (define_expand "epilogue"
5702 /* Try to use the trivial return first. Else use the full
5704 if (hppa_can_use_return_insn_p ())
5705 emit_jump_insn (gen_return ());
5710 hppa_expand_epilogue ();
5713 rtx pic = gen_rtx_REG (word_mode, PIC_OFFSET_TABLE_REGNUM);
5715 /* EH returns bypass the normal return stub. Thus, we must do an
5716 interspace branch to return from functions that call eh_return.
5717 This is only a problem for returns from shared code. */
5718 if (current_function_calls_eh_return)
5719 x = gen_return_external_pic (pic);
5721 x = gen_return_internal_pic (pic);
5724 x = gen_return_internal ();
5730 ;; Special because we use the value placed in %r2 by the bl instruction
5731 ;; from within its delay slot to set the value for the 2nd parameter to
5733 (define_insn "call_profiler"
5734 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5735 (match_operand 1 "" ""))
5736 (use (match_operand 2 "" ""))
5739 (clobber (reg:SI 2))]
5745 output_arg_descriptor (insn);
5747 xoperands[0] = operands[0];
5748 xoperands[1] = operands[2];
5749 xoperands[2] = gen_label_rtx ();
5750 output_asm_insn (\"{bl|b,l} %0,%%r2\;ldo %1-%2(%%r2),%%r25\", xoperands);
5752 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5753 CODE_LABEL_NUMBER (xoperands[2]));
5756 [(set_attr "type" "multi")
5757 (set_attr "length" "8")])
5759 (define_insn "blockage"
5760 [(unspec_volatile [(const_int 2)] 0)]
5763 [(set_attr "length" "0")])
5766 [(set (pc) (label_ref (match_operand 0 "" "")))]
5770 extern int optimize;
5772 if (GET_MODE (insn) == SImode)
5775 /* An unconditional branch which can reach its target. */
5776 if (get_attr_length (insn) != 24
5777 && get_attr_length (insn) != 16)
5780 /* An unconditional branch which can not reach its target.
5782 We need to be able to use %r1 as a scratch register; however,
5783 we can never be sure whether or not it's got a live value in
5784 it. Therefore, we must restore its original value after the
5787 To make matters worse, we don't have a stack slot which we
5788 can always clobber. sp-12/sp-16 shouldn't ever have a live
5789 value during a non-optimizing compilation, so we use those
5790 slots for now. We don't support very long branches when
5791 optimizing -- they should be quite rare when optimizing.
5793 Really the way to go long term is a register scavenger; goto
5794 the target of the jump and find a register which we can use
5795 as a scratch to hold the value in %r1. */
5797 /* We don't know how to register scavenge yet. */
5801 /* First store %r1 into the stack. */
5802 output_asm_insn (\"stw %%r1,-16(%%r30)\", operands);
5804 /* Now load the target address into %r1 and do an indirect jump
5805 to the value specified in %r1. Be careful to generate PIC
5810 xoperands[0] = operands[0];
5811 if (TARGET_SOM || ! TARGET_GAS)
5813 xoperands[1] = gen_label_rtx ();
5815 output_asm_insn (\"{bl|b,l} .+8,%%r1\\n\\taddil L'%l0-%l1,%%r1\",
5817 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5818 CODE_LABEL_NUMBER (xoperands[1]));
5819 output_asm_insn (\"ldo R'%l0-%l1(%%r1),%%r1\", xoperands);
5823 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
5824 output_asm_insn (\"addil L'%l0-$PIC_pcrel$0+4,%%r1\", xoperands);
5825 output_asm_insn (\"ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1\", xoperands);
5827 output_asm_insn (\"bv %%r0(%%r1)\", xoperands);
5830 output_asm_insn (\"ldil L'%l0,%%r1\\n\\tbe R'%l0(%%sr4,%%r1)\", operands);;
5832 /* And restore the value of %r1 in the delay slot. We're not optimizing,
5833 so we know nothing else can be in the delay slot. */
5834 return \"ldw -16(%%r30),%%r1\";
5836 [(set_attr "type" "uncond_branch")
5837 (set_attr "pa_combine_type" "uncond_branch")
5838 (set (attr "length")
5839 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5840 (if_then_else (lt (abs (minus (match_dup 0)
5841 (plus (pc) (const_int 8))))
5845 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5847 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5852 ;; Subroutines of "casesi".
5853 ;; operand 0 is index
5854 ;; operand 1 is the minimum bound
5855 ;; operand 2 is the maximum bound - minimum bound + 1
5856 ;; operand 3 is CODE_LABEL for the table;
5857 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5859 (define_expand "casesi"
5860 [(match_operand:SI 0 "general_operand" "")
5861 (match_operand:SI 1 "const_int_operand" "")
5862 (match_operand:SI 2 "const_int_operand" "")
5863 (match_operand 3 "" "")
5864 (match_operand 4 "" "")]
5868 if (GET_CODE (operands[0]) != REG)
5869 operands[0] = force_reg (SImode, operands[0]);
5871 if (operands[1] != const0_rtx)
5873 rtx reg = gen_reg_rtx (SImode);
5875 operands[1] = GEN_INT (-INTVAL (operands[1]));
5876 if (!INT_14_BITS (operands[1]))
5877 operands[1] = force_reg (SImode, operands[1]);
5878 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5883 /* In 64bit mode we must make sure to wipe the upper bits of the register
5884 just in case the addition overflowed or we had random bits in the
5885 high part of the register. */
5888 rtx reg = gen_reg_rtx (DImode);
5889 emit_insn (gen_extendsidi2 (reg, operands[0]));
5890 operands[0] = gen_rtx_SUBREG (SImode, reg, 4);
5893 if (!INT_5_BITS (operands[2]))
5894 operands[2] = force_reg (SImode, operands[2]);
5896 emit_insn (gen_cmpsi (operands[0], operands[2]));
5897 emit_jump_insn (gen_bgtu (operands[4]));
5898 if (TARGET_BIG_SWITCH)
5900 rtx temp = gen_reg_rtx (SImode);
5901 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5904 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5908 (define_insn "casesi0"
5910 (mem:SI (plus:SI (pc)
5911 (match_operand:SI 0 "register_operand" "r")))
5912 (label_ref (match_operand 1 "" ""))))]
5915 [(set_attr "type" "multi")
5916 (set_attr "length" "8")])
5918 ;; Need nops for the calls because execution is supposed to continue
5919 ;; past; we don't want to nullify an instruction that we need.
5920 ;;- jump to subroutine
5922 (define_expand "call"
5923 [(parallel [(call (match_operand:SI 0 "" "")
5924 (match_operand 1 "" ""))
5925 (clobber (reg:SI 2))])]
5932 if (TARGET_PORTABLE_RUNTIME)
5933 op = force_reg (SImode, XEXP (operands[0], 0));
5935 op = XEXP (operands[0], 0);
5938 emit_move_insn (arg_pointer_rtx,
5939 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5942 /* Use two different patterns for calls to explicitly named functions
5943 and calls through function pointers. This is necessary as these two
5944 types of calls use different calling conventions, and CSE might try
5945 to change the named call into an indirect call in some cases (using
5946 two patterns keeps CSE from performing this optimization). */
5947 if (GET_CODE (op) == SYMBOL_REF)
5948 call_insn = emit_call_insn (gen_call_internal_symref (op, operands[1]));
5949 else if (TARGET_64BIT)
5951 rtx tmpreg = force_reg (word_mode, op);
5952 call_insn = emit_call_insn (gen_call_internal_reg_64bit (tmpreg,
5957 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5958 emit_move_insn (tmpreg, force_reg (word_mode, op));
5959 call_insn = emit_call_insn (gen_call_internal_reg (operands[1]));
5964 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
5966 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
5968 /* After each call we must restore the PIC register, even if it
5969 doesn't appear to be used. */
5970 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
5975 (define_insn "call_internal_symref"
5976 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5977 (match_operand 1 "" "i"))
5978 (clobber (reg:SI 2))
5979 (use (const_int 0))]
5980 "! TARGET_PORTABLE_RUNTIME"
5983 output_arg_descriptor (insn);
5984 return output_call (insn, operands[0], 0);
5986 [(set_attr "type" "call")
5987 (set (attr "length")
5988 ;; If we're sure that we can either reach the target or that the
5989 ;; linker can use a long-branch stub, then the length is at most
5992 ;; For long-calls the length will be at most 68 bytes (non-pic)
5993 ;; or 84 bytes (pic). */
5994 ;; Else we have to use a long-call;
5995 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
5998 (if_then_else (eq (symbol_ref "flag_pic")
6003 (define_insn "call_internal_reg_64bit"
6004 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6005 (match_operand 1 "" "i"))
6006 (clobber (reg:SI 2))
6007 (use (const_int 1))]
6011 /* ??? Needs more work. Length computation, split into multiple insns,
6012 do not use %r22 directly, expose delay slot. */
6013 return \"ldd 16(%0),%%r2\;ldd 24(%0),%%r27\;bve,l (%%r2),%%r2\;nop\";
6015 [(set_attr "type" "dyncall")
6016 (set (attr "length") (const_int 16))])
6018 (define_insn "call_internal_reg"
6019 [(call (mem:SI (reg:SI 22))
6020 (match_operand 0 "" "i"))
6021 (clobber (reg:SI 2))
6022 (use (const_int 1))]
6028 /* First the special case for kernels, level 0 systems, etc. */
6029 if (TARGET_FAST_INDIRECT_CALLS)
6030 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
6032 /* Now the normal case -- we can reach $$dyncall directly or
6033 we're sure that we can get there via a long-branch stub.
6035 No need to check target flags as the length uniquely identifies
6036 the remaining cases. */
6037 if (get_attr_length (insn) == 8)
6038 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
6040 /* Long millicode call, but we are not generating PIC or portable runtime
6042 if (get_attr_length (insn) == 12)
6043 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
6045 /* Long millicode call for portable runtime. */
6046 if (get_attr_length (insn) == 20)
6047 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
6049 /* If we're generating PIC code. */
6050 xoperands[0] = operands[0];
6051 if (TARGET_SOM || ! TARGET_GAS)
6052 xoperands[1] = gen_label_rtx ();
6053 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
6054 if (TARGET_SOM || ! TARGET_GAS)
6056 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
6057 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6058 CODE_LABEL_NUMBER (xoperands[1]));
6059 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
6063 output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands);
6064 output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\",
6067 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
6068 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
6071 [(set_attr "type" "dyncall")
6072 (set (attr "length")
6074 ;; First FAST_INDIRECT_CALLS
6075 (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS")
6079 ;; Target (or stub) within reach
6080 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6082 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6087 (ne (symbol_ref "flag_pic")
6091 ;; Out of reach PORTABLE_RUNTIME
6092 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
6096 ;; Out of reach, can use ble
6099 (define_expand "call_value"
6100 [(parallel [(set (match_operand 0 "" "")
6101 (call (match_operand:SI 1 "" "")
6102 (match_operand 2 "" "")))
6103 (clobber (reg:SI 2))])]
6110 if (TARGET_PORTABLE_RUNTIME)
6111 op = force_reg (word_mode, XEXP (operands[1], 0));
6113 op = XEXP (operands[1], 0);
6116 emit_move_insn (arg_pointer_rtx,
6117 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6120 /* Use two different patterns for calls to explicitly named functions
6121 and calls through function pointers. This is necessary as these two
6122 types of calls use different calling conventions, and CSE might try
6123 to change the named call into an indirect call in some cases (using
6124 two patterns keeps CSE from performing this optimization). */
6125 if (GET_CODE (op) == SYMBOL_REF)
6126 call_insn = emit_call_insn (gen_call_value_internal_symref (operands[0],
6129 else if (TARGET_64BIT)
6131 rtx tmpreg = force_reg (word_mode, op);
6133 = emit_call_insn (gen_call_value_internal_reg_64bit (operands[0],
6139 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6140 emit_move_insn (tmpreg, force_reg (word_mode, op));
6141 call_insn = emit_call_insn (gen_call_value_internal_reg (operands[0],
6146 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6148 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6150 /* After each call we must restore the PIC register, even if it
6151 doesn't appear to be used. */
6152 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6157 (define_insn "call_value_internal_symref"
6158 [(set (match_operand 0 "" "=rf")
6159 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6160 (match_operand 2 "" "i")))
6161 (clobber (reg:SI 2))
6162 (use (const_int 0))]
6163 ;;- Don't use operand 1 for most machines.
6164 "! TARGET_PORTABLE_RUNTIME"
6167 output_arg_descriptor (insn);
6168 return output_call (insn, operands[1], 0);
6170 [(set_attr "type" "call")
6171 (set (attr "length")
6172 ;; If we're sure that we can either reach the target or that the
6173 ;; linker can use a long-branch stub, then the length is at most
6176 ;; For long-calls the length will be at most 68 bytes (non-pic)
6177 ;; or 84 bytes (pic). */
6178 ;; Else we have to use a long-call;
6179 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6182 (if_then_else (eq (symbol_ref "flag_pic")
6187 (define_insn "call_value_internal_reg_64bit"
6188 [(set (match_operand 0 "" "=rf")
6189 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6190 (match_operand 2 "" "i")))
6191 (clobber (reg:SI 2))
6192 (use (const_int 1))]
6196 /* ??? Needs more work. Length computation, split into multiple insns,
6197 do not use %r22 directly, expose delay slot. */
6198 return \"ldd 16(%1),%%r2\;ldd 24(%1),%%r27\;bve,l (%%r2),%%r2\;nop\";
6200 [(set_attr "type" "dyncall")
6201 (set (attr "length") (const_int 16))])
6203 (define_insn "call_value_internal_reg"
6204 [(set (match_operand 0 "" "=rf")
6205 (call (mem:SI (reg:SI 22))
6206 (match_operand 1 "" "i")))
6207 (clobber (reg:SI 2))
6208 (use (const_int 1))]
6214 /* First the special case for kernels, level 0 systems, etc. */
6215 if (TARGET_FAST_INDIRECT_CALLS)
6216 return \"ble 0(%%sr4,%%r22)\;copy %%r31,%%r2\";
6218 /* Now the normal case -- we can reach $$dyncall directly or
6219 we're sure that we can get there via a long-branch stub.
6221 No need to check target flags as the length uniquely identifies
6222 the remaining cases. */
6223 if (get_attr_length (insn) == 8)
6224 return \".CALL\\tARGW0=GR\;{bl|b,l} $$dyncall,%%r31\;copy %%r31,%%r2\";
6226 /* Long millicode call, but we are not generating PIC or portable runtime
6228 if (get_attr_length (insn) == 12)
6229 return \".CALL\\tARGW0=GR\;ldil L%%$$dyncall,%%r2\;ble R%%$$dyncall(%%sr4,%%r2)\;copy %%r31,%%r2\";
6231 /* Long millicode call for portable runtime. */
6232 if (get_attr_length (insn) == 20)
6233 return \"ldil L%%$$dyncall,%%r31\;ldo R%%$$dyncall(%%r31),%%r31\;blr %%r0,%%r2\;bv,n %%r0(%%r31)\;nop\";
6235 /* If we're generating PIC code. */
6236 xoperands[0] = operands[1];
6237 if (TARGET_SOM || ! TARGET_GAS)
6238 xoperands[1] = gen_label_rtx ();
6239 output_asm_insn (\"{bl|b,l} .+8,%%r1\", xoperands);
6240 if (TARGET_SOM || ! TARGET_GAS)
6242 output_asm_insn (\"addil L%%$$dyncall-%1,%%r1\", xoperands);
6243 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
6244 CODE_LABEL_NUMBER (xoperands[1]));
6245 output_asm_insn (\"ldo R%%$$dyncall-%1(%%r1),%%r1\", xoperands);
6249 output_asm_insn (\"addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1\", xoperands);
6250 output_asm_insn (\"ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1\",
6253 output_asm_insn (\"blr %%r0,%%r2\", xoperands);
6254 output_asm_insn (\"bv,n %%r0(%%r1)\\n\\tnop\", xoperands);
6257 [(set_attr "type" "dyncall")
6258 (set (attr "length")
6260 ;; First FAST_INDIRECT_CALLS
6261 (ne (symbol_ref "TARGET_FAST_INDIRECT_CALLS")
6265 ;; Target (or stub) within reach
6266 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
6268 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
6273 (ne (symbol_ref "flag_pic")
6277 ;; Out of reach PORTABLE_RUNTIME
6278 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
6282 ;; Out of reach, can use ble
6285 ;; Call subroutine returning any type.
6287 (define_expand "untyped_call"
6288 [(parallel [(call (match_operand 0 "" "")
6290 (match_operand 1 "" "")
6291 (match_operand 2 "" "")])]
6297 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6299 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6301 rtx set = XVECEXP (operands[2], 0, i);
6302 emit_move_insn (SET_DEST (set), SET_SRC (set));
6305 /* The optimizer does not know that the call sets the function value
6306 registers we stored in the result block. We avoid problems by
6307 claiming that all hard registers are used and clobbered at this
6309 emit_insn (gen_blockage ());
6314 (define_expand "sibcall"
6315 [(parallel [(call (match_operand:SI 0 "" "")
6316 (match_operand 1 "" ""))
6317 (clobber (reg:SI 0))])]
6318 "! TARGET_PORTABLE_RUNTIME"
6324 op = XEXP (operands[0], 0);
6326 /* We do not allow indirect sibling calls. */
6327 call_insn = emit_call_insn (gen_sibcall_internal_symref (op, operands[1]));
6331 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6333 /* After each call we must restore the PIC register, even if it
6334 doesn't appear to be used. */
6335 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6340 (define_insn "sibcall_internal_symref"
6341 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6342 (match_operand 1 "" "i"))
6343 (clobber (reg:SI 0))
6345 (use (const_int 0))]
6346 "! TARGET_PORTABLE_RUNTIME"
6349 output_arg_descriptor (insn);
6350 return output_call (insn, operands[0], 1);
6352 [(set_attr "type" "call")
6353 (set (attr "length")
6354 ;; If we're sure that we can either reach the target or that the
6355 ;; linker can use a long-branch stub, then the length is at most
6358 ;; For long-calls the length will be at most 68 bytes (non-pic)
6359 ;; or 84 bytes (pic). */
6360 ;; Else we have to use a long-call;
6361 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6364 (if_then_else (eq (symbol_ref "flag_pic")
6369 (define_expand "sibcall_value"
6370 [(parallel [(set (match_operand 0 "" "")
6371 (call (match_operand:SI 1 "" "")
6372 (match_operand 2 "" "")))
6373 (clobber (reg:SI 0))])]
6374 "! TARGET_PORTABLE_RUNTIME"
6380 op = XEXP (operands[1], 0);
6382 /* We do not allow indirect sibling calls. */
6383 call_insn = emit_call_insn (gen_sibcall_value_internal_symref (operands[0],
6388 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6390 /* After each call we must restore the PIC register, even if it
6391 doesn't appear to be used. */
6392 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
6397 (define_insn "sibcall_value_internal_symref"
6398 [(set (match_operand 0 "" "=rf")
6399 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6400 (match_operand 2 "" "i")))
6401 (clobber (reg:SI 0))
6403 (use (const_int 0))]
6404 ;;- Don't use operand 1 for most machines.
6405 "! TARGET_PORTABLE_RUNTIME"
6408 output_arg_descriptor (insn);
6409 return output_call (insn, operands[1], 1);
6411 [(set_attr "type" "call")
6412 (set (attr "length")
6413 ;; If we're sure that we can either reach the target or that the
6414 ;; linker can use a long-branch stub, then the length is at most
6417 ;; For long-calls the length will be at most 68 bytes (non-pic)
6418 ;; or 84 bytes (pic). */
6419 ;; Else we have to use a long-call;
6420 (if_then_else (lt (plus (symbol_ref "total_code_bytes") (pc))
6423 (if_then_else (eq (symbol_ref "flag_pic")
6432 [(set_attr "type" "move")
6433 (set_attr "length" "4")])
6435 ;; These are just placeholders so we know where branch tables
6437 (define_insn "begin_brtab"
6442 /* Only GAS actually supports this pseudo-op. */
6444 return \".begin_brtab\";
6448 [(set_attr "type" "move")
6449 (set_attr "length" "0")])
6451 (define_insn "end_brtab"
6456 /* Only GAS actually supports this pseudo-op. */
6458 return \".end_brtab\";
6462 [(set_attr "type" "move")
6463 (set_attr "length" "0")])
6465 ;;; EH does longjmp's from and within the data section. Thus,
6466 ;;; an interspace branch is required for the longjmp implementation.
6467 ;;; Registers r1 and r2 are used as scratch registers for the jump.
6468 (define_expand "interspace_jump"
6470 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6471 (clobber (match_dup 1))])]
6475 operands[1] = gen_rtx_REG (word_mode, 2);
6479 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6480 (clobber (reg:SI 2))]
6482 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6483 [(set_attr "type" "branch")
6484 (set_attr "length" "12")])
6487 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
6488 (clobber (reg:DI 2))]
6490 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
6491 [(set_attr "type" "branch")
6492 (set_attr "length" "12")])
6494 (define_expand "builtin_longjmp"
6495 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
6499 /* The elements of the buffer are, in order: */
6500 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
6501 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
6502 POINTER_SIZE / BITS_PER_UNIT));
6503 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
6504 (POINTER_SIZE * 2) / BITS_PER_UNIT));
6505 rtx pv = gen_rtx_REG (Pmode, 1);
6507 /* This bit is the same as expand_builtin_longjmp. */
6508 emit_move_insn (hard_frame_pointer_rtx, fp);
6509 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
6510 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
6511 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
6513 /* Load the label we are jumping through into r1 so that we know
6514 where to look for it when we get back to setjmp's function for
6515 restoring the gp. */
6516 emit_move_insn (pv, lab);
6518 /* Prevent the insns above from being scheduled into the delay slot
6519 of the interspace jump because the space register could change. */
6520 emit_insn (gen_blockage ());
6522 emit_jump_insn (gen_interspace_jump (pv));
6527 ;;; Hope this is only within a function...
6528 (define_insn "indirect_jump"
6529 [(set (pc) (match_operand 0 "register_operand" "r"))]
6530 "GET_MODE (operands[0]) == word_mode"
6532 [(set_attr "type" "branch")
6533 (set_attr "length" "4")])
6535 (define_expand "extzv"
6536 [(set (match_operand 0 "register_operand" "")
6537 (zero_extract (match_operand 1 "register_operand" "")
6538 (match_operand 2 "uint32_operand" "")
6539 (match_operand 3 "uint32_operand" "")))]
6544 emit_insn (gen_extzv_64 (operands[0], operands[1],
6545 operands[2], operands[3]));
6547 emit_insn (gen_extzv_32 (operands[0], operands[1],
6548 operands[2], operands[3]));
6552 (define_insn "extzv_32"
6553 [(set (match_operand:SI 0 "register_operand" "=r")
6554 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6555 (match_operand:SI 2 "uint5_operand" "")
6556 (match_operand:SI 3 "uint5_operand" "")))]
6558 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
6559 [(set_attr "type" "shift")
6560 (set_attr "length" "4")])
6563 [(set (match_operand:SI 0 "register_operand" "=r")
6564 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
6566 (match_operand:SI 2 "register_operand" "q")))]
6568 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
6569 [(set_attr "type" "shift")
6570 (set_attr "length" "4")])
6572 (define_insn "extzv_64"
6573 [(set (match_operand:DI 0 "register_operand" "=r")
6574 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6575 (match_operand:DI 2 "uint32_operand" "")
6576 (match_operand:DI 3 "uint32_operand" "")))]
6578 "extrd,u %1,%3+%2-1,%2,%0"
6579 [(set_attr "type" "shift")
6580 (set_attr "length" "4")])
6583 [(set (match_operand:DI 0 "register_operand" "=r")
6584 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
6586 (match_operand:DI 2 "register_operand" "q")))]
6588 "extrd,u %1,%%sar,1,%0"
6589 [(set_attr "type" "shift")
6590 (set_attr "length" "4")])
6592 (define_expand "extv"
6593 [(set (match_operand 0 "register_operand" "")
6594 (sign_extract (match_operand 1 "register_operand" "")
6595 (match_operand 2 "uint32_operand" "")
6596 (match_operand 3 "uint32_operand" "")))]
6601 emit_insn (gen_extv_64 (operands[0], operands[1],
6602 operands[2], operands[3]));
6604 emit_insn (gen_extv_32 (operands[0], operands[1],
6605 operands[2], operands[3]));
6609 (define_insn "extv_32"
6610 [(set (match_operand:SI 0 "register_operand" "=r")
6611 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6612 (match_operand:SI 2 "uint5_operand" "")
6613 (match_operand:SI 3 "uint5_operand" "")))]
6615 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
6616 [(set_attr "type" "shift")
6617 (set_attr "length" "4")])
6620 [(set (match_operand:SI 0 "register_operand" "=r")
6621 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
6623 (match_operand:SI 2 "register_operand" "q")))]
6625 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
6626 [(set_attr "type" "shift")
6627 (set_attr "length" "4")])
6629 (define_insn "extv_64"
6630 [(set (match_operand:DI 0 "register_operand" "=r")
6631 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6632 (match_operand:DI 2 "uint32_operand" "")
6633 (match_operand:DI 3 "uint32_operand" "")))]
6635 "extrd,s %1,%3+%2-1,%2,%0"
6636 [(set_attr "type" "shift")
6637 (set_attr "length" "4")])
6640 [(set (match_operand:DI 0 "register_operand" "=r")
6641 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
6643 (match_operand:DI 2 "register_operand" "q")))]
6645 "extrd,s %1,%%sar,1,%0"
6646 [(set_attr "type" "shift")
6647 (set_attr "length" "4")])
6649 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
6650 (define_expand "insv"
6651 [(set (zero_extract (match_operand 0 "register_operand" "")
6652 (match_operand 1 "uint32_operand" "")
6653 (match_operand 2 "uint32_operand" ""))
6654 (match_operand 3 "arith5_operand" ""))]
6659 emit_insn (gen_insv_64 (operands[0], operands[1],
6660 operands[2], operands[3]));
6662 emit_insn (gen_insv_32 (operands[0], operands[1],
6663 operands[2], operands[3]));
6667 (define_insn "insv_32"
6668 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
6669 (match_operand:SI 1 "uint5_operand" "")
6670 (match_operand:SI 2 "uint5_operand" ""))
6671 (match_operand:SI 3 "arith5_operand" "r,L"))]
6674 {dep|depw} %3,%2+%1-1,%1,%0
6675 {depi|depwi} %3,%2+%1-1,%1,%0"
6676 [(set_attr "type" "shift,shift")
6677 (set_attr "length" "4,4")])
6679 ;; Optimize insertion of const_int values of type 1...1xxxx.
6681 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
6682 (match_operand:SI 1 "uint5_operand" "")
6683 (match_operand:SI 2 "uint5_operand" ""))
6684 (match_operand:SI 3 "const_int_operand" ""))]
6685 "(INTVAL (operands[3]) & 0x10) != 0 &&
6686 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6689 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6690 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
6692 [(set_attr "type" "shift")
6693 (set_attr "length" "4")])
6695 (define_insn "insv_64"
6696 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
6697 (match_operand:DI 1 "uint32_operand" "")
6698 (match_operand:DI 2 "uint32_operand" ""))
6699 (match_operand:DI 3 "arith32_operand" "r,L"))]
6702 depd %3,%2+%1-1,%1,%0
6703 depdi %3,%2+%1-1,%1,%0"
6704 [(set_attr "type" "shift,shift")
6705 (set_attr "length" "4,4")])
6707 ;; Optimize insertion of const_int values of type 1...1xxxx.
6709 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
6710 (match_operand:DI 1 "uint32_operand" "")
6711 (match_operand:DI 2 "uint32_operand" ""))
6712 (match_operand:DI 3 "const_int_operand" ""))]
6713 "(INTVAL (operands[3]) & 0x10) != 0
6715 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
6718 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
6719 return \"depdi %3,%2+%1-1,%1,%0\";
6721 [(set_attr "type" "shift")
6722 (set_attr "length" "4")])
6725 [(set (match_operand:DI 0 "register_operand" "=r")
6726 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
6729 "depd,z %1,31,32,%0"
6730 [(set_attr "type" "shift")
6731 (set_attr "length" "4")])
6733 ;; This insn is used for some loop tests, typically loops reversed when
6734 ;; strength reduction is used. It is actually created when the instruction
6735 ;; combination phase combines the special loop test. Since this insn
6736 ;; is both a jump insn and has an output, it must deal with its own
6737 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
6738 ;; to not choose the register alternatives in the event a reload is needed.
6739 (define_insn "decrement_and_branch_until_zero"
6742 (match_operator 2 "comparison_operator"
6744 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
6745 (match_operand:SI 1 "int5_operand" "L,L,L"))
6747 (label_ref (match_operand 3 "" ""))
6750 (plus:SI (match_dup 0) (match_dup 1)))
6751 (clobber (match_scratch:SI 4 "=X,r,r"))]
6753 "* return output_dbra (operands, insn, which_alternative); "
6754 ;; Do not expect to understand this the first time through.
6755 [(set_attr "type" "cbranch,multi,multi")
6756 (set (attr "length")
6757 (if_then_else (eq_attr "alternative" "0")
6758 ;; Loop counter in register case
6759 ;; Short branch has length of 4
6760 ;; Long branch has length of 8
6761 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6766 ;; Loop counter in FP reg case.
6767 ;; Extra goo to deal with additional reload insns.
6768 (if_then_else (eq_attr "alternative" "1")
6769 (if_then_else (lt (match_dup 3) (pc))
6771 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
6776 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6780 ;; Loop counter in memory case.
6781 ;; Extra goo to deal with additional reload insns.
6782 (if_then_else (lt (match_dup 3) (pc))
6784 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6789 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6792 (const_int 16))))))])
6797 (match_operator 2 "movb_comparison_operator"
6798 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6799 (label_ref (match_operand 3 "" ""))
6801 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
6804 "* return output_movb (operands, insn, which_alternative, 0); "
6805 ;; Do not expect to understand this the first time through.
6806 [(set_attr "type" "cbranch,multi,multi,multi")
6807 (set (attr "length")
6808 (if_then_else (eq_attr "alternative" "0")
6809 ;; Loop counter in register case
6810 ;; Short branch has length of 4
6811 ;; Long branch has length of 8
6812 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6817 ;; Loop counter in FP reg case.
6818 ;; Extra goo to deal with additional reload insns.
6819 (if_then_else (eq_attr "alternative" "1")
6820 (if_then_else (lt (match_dup 3) (pc))
6822 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6827 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6831 ;; Loop counter in memory or sar case.
6832 ;; Extra goo to deal with additional reload insns.
6834 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6837 (const_int 12)))))])
6839 ;; Handle negated branch.
6843 (match_operator 2 "movb_comparison_operator"
6844 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
6846 (label_ref (match_operand 3 "" ""))))
6847 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
6850 "* return output_movb (operands, insn, which_alternative, 1); "
6851 ;; Do not expect to understand this the first time through.
6852 [(set_attr "type" "cbranch,multi,multi,multi")
6853 (set (attr "length")
6854 (if_then_else (eq_attr "alternative" "0")
6855 ;; Loop counter in register case
6856 ;; Short branch has length of 4
6857 ;; Long branch has length of 8
6858 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6863 ;; Loop counter in FP reg case.
6864 ;; Extra goo to deal with additional reload insns.
6865 (if_then_else (eq_attr "alternative" "1")
6866 (if_then_else (lt (match_dup 3) (pc))
6868 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
6873 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6877 ;; Loop counter in memory or SAR case.
6878 ;; Extra goo to deal with additional reload insns.
6880 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6883 (const_int 12)))))])
6886 [(set (pc) (label_ref (match_operand 3 "" "" )))
6887 (set (match_operand:SI 0 "ireg_operand" "=r")
6888 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
6889 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
6890 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
6893 return output_parallel_addb (operands, get_attr_length (insn));
6895 [(set_attr "type" "parallel_branch")
6896 (set (attr "length")
6897 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
6903 [(set (pc) (label_ref (match_operand 2 "" "" )))
6904 (set (match_operand:SF 0 "ireg_operand" "=r")
6905 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
6909 return output_parallel_movb (operands, get_attr_length (insn));
6911 [(set_attr "type" "parallel_branch")
6912 (set (attr "length")
6913 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6919 [(set (pc) (label_ref (match_operand 2 "" "" )))
6920 (set (match_operand:SI 0 "ireg_operand" "=r")
6921 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
6925 return output_parallel_movb (operands, get_attr_length (insn));
6927 [(set_attr "type" "parallel_branch")
6928 (set (attr "length")
6929 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6935 [(set (pc) (label_ref (match_operand 2 "" "" )))
6936 (set (match_operand:HI 0 "ireg_operand" "=r")
6937 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
6941 return output_parallel_movb (operands, get_attr_length (insn));
6943 [(set_attr "type" "parallel_branch")
6944 (set (attr "length")
6945 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6951 [(set (pc) (label_ref (match_operand 2 "" "" )))
6952 (set (match_operand:QI 0 "ireg_operand" "=r")
6953 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
6957 return output_parallel_movb (operands, get_attr_length (insn));
6959 [(set_attr "type" "parallel_branch")
6960 (set (attr "length")
6961 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
6967 [(set (match_operand 0 "register_operand" "=f")
6968 (mult (match_operand 1 "register_operand" "f")
6969 (match_operand 2 "register_operand" "f")))
6970 (set (match_operand 3 "register_operand" "+f")
6971 (plus (match_operand 4 "register_operand" "f")
6972 (match_operand 5 "register_operand" "f")))]
6973 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
6974 && reload_completed && fmpyaddoperands (operands)"
6977 if (GET_MODE (operands[0]) == DFmode)
6979 if (rtx_equal_p (operands[3], operands[5]))
6980 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
6982 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
6986 if (rtx_equal_p (operands[3], operands[5]))
6987 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
6989 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
6992 [(set_attr "type" "fpalu")
6993 (set_attr "length" "4")])
6996 [(set (match_operand 3 "register_operand" "+f")
6997 (plus (match_operand 4 "register_operand" "f")
6998 (match_operand 5 "register_operand" "f")))
6999 (set (match_operand 0 "register_operand" "=f")
7000 (mult (match_operand 1 "register_operand" "f")
7001 (match_operand 2 "register_operand" "f")))]
7002 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7003 && reload_completed && fmpyaddoperands (operands)"
7006 if (GET_MODE (operands[0]) == DFmode)
7008 if (rtx_equal_p (operands[3], operands[5]))
7009 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7011 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7015 if (rtx_equal_p (operands[3], operands[5]))
7016 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7018 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7021 [(set_attr "type" "fpalu")
7022 (set_attr "length" "4")])
7025 [(set (match_operand 0 "register_operand" "=f")
7026 (mult (match_operand 1 "register_operand" "f")
7027 (match_operand 2 "register_operand" "f")))
7028 (set (match_operand 3 "register_operand" "+f")
7029 (minus (match_operand 4 "register_operand" "f")
7030 (match_operand 5 "register_operand" "f")))]
7031 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7032 && reload_completed && fmpysuboperands (operands)"
7035 if (GET_MODE (operands[0]) == DFmode)
7036 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7038 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7040 [(set_attr "type" "fpalu")
7041 (set_attr "length" "4")])
7044 [(set (match_operand 3 "register_operand" "+f")
7045 (minus (match_operand 4 "register_operand" "f")
7046 (match_operand 5 "register_operand" "f")))
7047 (set (match_operand 0 "register_operand" "=f")
7048 (mult (match_operand 1 "register_operand" "f")
7049 (match_operand 2 "register_operand" "f")))]
7050 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7051 && reload_completed && fmpysuboperands (operands)"
7054 if (GET_MODE (operands[0]) == DFmode)
7055 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7057 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7059 [(set_attr "type" "fpalu")
7060 (set_attr "length" "4")])
7062 ;; Clean up turds left by reload.
7064 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
7065 (match_operand 1 "register_operand" "fr"))
7066 (set (match_operand 2 "register_operand" "fr")
7068 "! TARGET_SOFT_FLOAT
7069 && GET_CODE (operands[0]) == MEM
7070 && ! MEM_VOLATILE_P (operands[0])
7071 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7072 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7073 && GET_MODE (operands[0]) == DFmode
7074 && GET_CODE (operands[1]) == REG
7075 && GET_CODE (operands[2]) == REG
7076 && ! side_effects_p (XEXP (operands[0], 0))
7077 && REGNO_REG_CLASS (REGNO (operands[1]))
7078 == REGNO_REG_CLASS (REGNO (operands[2]))"
7083 if (FP_REG_P (operands[1]))
7084 output_asm_insn (output_fp_move_double (operands), operands);
7086 output_asm_insn (output_move_double (operands), operands);
7088 if (rtx_equal_p (operands[1], operands[2]))
7091 xoperands[0] = operands[2];
7092 xoperands[1] = operands[1];
7094 if (FP_REG_P (xoperands[1]))
7095 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7097 output_asm_insn (output_move_double (xoperands), xoperands);
7103 [(set (match_operand 0 "register_operand" "fr")
7104 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
7105 (set (match_operand 2 "register_operand" "fr")
7107 "! TARGET_SOFT_FLOAT
7108 && GET_CODE (operands[1]) == MEM
7109 && ! MEM_VOLATILE_P (operands[1])
7110 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7111 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7112 && GET_MODE (operands[0]) == DFmode
7113 && GET_CODE (operands[0]) == REG
7114 && GET_CODE (operands[2]) == REG
7115 && ! side_effects_p (XEXP (operands[1], 0))
7116 && REGNO_REG_CLASS (REGNO (operands[0]))
7117 == REGNO_REG_CLASS (REGNO (operands[2]))"
7122 if (FP_REG_P (operands[0]))
7123 output_asm_insn (output_fp_move_double (operands), operands);
7125 output_asm_insn (output_move_double (operands), operands);
7127 xoperands[0] = operands[2];
7128 xoperands[1] = operands[0];
7130 if (FP_REG_P (xoperands[1]))
7131 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7133 output_asm_insn (output_move_double (xoperands), xoperands);
7138 ;; Flush the I and D cache line found at the address in operand 0.
7139 ;; This is used by the trampoline code for nested functions.
7140 ;; So long as the trampoline itself is less than 32 bytes this
7143 (define_insn "dcacheflush"
7144 [(unspec_volatile [(const_int 1)] 0)
7145 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7146 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
7148 "fdc 0(%0)\;fdc 0(%1)\;sync"
7149 [(set_attr "type" "multi")
7150 (set_attr "length" "12")])
7152 (define_insn "icacheflush"
7153 [(unspec_volatile [(const_int 2)] 0)
7154 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7155 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
7156 (use (match_operand 2 "pmode_register_operand" "r"))
7157 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
7158 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
7160 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
7161 [(set_attr "type" "multi")
7162 (set_attr "length" "52")])
7164 ;; An out-of-line prologue.
7165 (define_insn "outline_prologue_call"
7166 [(unspec_volatile [(const_int 0)] 0)
7167 (clobber (reg:SI 31))
7168 (clobber (reg:SI 22))
7169 (clobber (reg:SI 21))
7170 (clobber (reg:SI 20))
7171 (clobber (reg:SI 19))
7172 (clobber (reg:SI 1))]
7176 extern int frame_pointer_needed;
7178 /* We need two different versions depending on whether or not we
7179 need a frame pointer. Also note that we return to the instruction
7180 immediately after the branch rather than two instructions after the
7181 break as normally is the case. */
7182 if (frame_pointer_needed)
7184 /* Must import the magic millicode routine(s). */
7185 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
7187 if (TARGET_PORTABLE_RUNTIME)
7189 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
7190 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
7194 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
7198 /* Must import the magic millicode routine(s). */
7199 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
7201 if (TARGET_PORTABLE_RUNTIME)
7203 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
7204 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
7207 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
7211 [(set_attr "type" "multi")
7212 (set_attr "length" "8")])
7214 ;; An out-of-line epilogue.
7215 (define_insn "outline_epilogue_call"
7216 [(unspec_volatile [(const_int 1)] 0)
7219 (clobber (reg:SI 31))
7220 (clobber (reg:SI 22))
7221 (clobber (reg:SI 21))
7222 (clobber (reg:SI 20))
7223 (clobber (reg:SI 19))
7224 (clobber (reg:SI 2))
7225 (clobber (reg:SI 1))]
7229 extern int frame_pointer_needed;
7231 /* We need two different versions depending on whether or not we
7232 need a frame pointer. Also note that we return to the instruction
7233 immediately after the branch rather than two instructions after the
7234 break as normally is the case. */
7235 if (frame_pointer_needed)
7237 /* Must import the magic millicode routine. */
7238 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
7240 /* The out-of-line prologue will make sure we return to the right
7242 if (TARGET_PORTABLE_RUNTIME)
7244 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
7245 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
7249 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
7253 /* Must import the magic millicode routine. */
7254 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
7256 /* The out-of-line prologue will make sure we return to the right
7258 if (TARGET_PORTABLE_RUNTIME)
7260 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
7261 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
7264 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
7268 [(set_attr "type" "multi")
7269 (set_attr "length" "8")])
7271 ;; Given a function pointer, canonicalize it so it can be
7272 ;; reliably compared to another function pointer. */
7273 (define_expand "canonicalize_funcptr_for_compare"
7274 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
7275 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7276 (clobber (match_dup 2))
7277 (clobber (reg:SI 26))
7278 (clobber (reg:SI 22))
7279 (clobber (reg:SI 31))])
7280 (set (match_operand:SI 0 "register_operand" "")
7282 "! TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && !TARGET_ELF32"
7285 operands[2] = gen_reg_rtx (SImode);
7286 if (GET_CODE (operands[1]) != REG)
7288 rtx tmp = gen_reg_rtx (Pmode);
7289 emit_move_insn (tmp, operands[1]);
7295 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7296 (clobber (match_operand:SI 0 "register_operand" "=a"))
7297 (clobber (reg:SI 26))
7298 (clobber (reg:SI 22))
7299 (clobber (reg:SI 31))]
7303 /* Must import the magic millicode routine. */
7304 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
7306 /* This is absolutely amazing.
7308 First, copy our input parameter into %r29 just in case we don't
7309 need to call $$sh_func_adrs. */
7310 output_asm_insn (\"copy %%r26,%%r29\", NULL);
7312 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
7313 we use %r26 unchanged. */
7314 if (get_attr_length (insn) == 32)
7315 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+24\", NULL);
7316 else if (get_attr_length (insn) == 40)
7317 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+32\", NULL);
7318 else if (get_attr_length (insn) == 44)
7319 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+36\", NULL);
7321 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\;{comib|cmpib},<>,n 2,%%r31,.+20\", NULL);
7323 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
7324 4096, then we use %r26 unchanged. */
7325 if (get_attr_length (insn) == 32)
7326 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+16\",
7328 else if (get_attr_length (insn) == 40)
7329 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+24\",
7331 else if (get_attr_length (insn) == 44)
7332 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+28\",
7335 output_asm_insn (\"ldi 4096,%%r31\;{comb|cmpb},<<,n %%r26,%%r31,.+12\",
7338 /* Else call $$sh_func_adrs to extract the function's real add24. */
7339 return output_millicode_call (insn,
7340 gen_rtx_SYMBOL_REF (SImode,
7341 \"$$sh_func_adrs\"));
7343 [(set_attr "type" "multi")
7344 (set (attr "length")
7346 ;; Target (or stub) within reach
7347 (and (lt (plus (symbol_ref "total_code_bytes") (pc))
7349 (eq (symbol_ref "TARGET_PORTABLE_RUNTIME")
7354 (ne (symbol_ref "flag_pic")
7358 ;; Out of reach PORTABLE_RUNTIME
7359 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME")
7363 ;; Out of reach, can use ble
7366 ;; On the PA, the PIC register is call clobbered, so it must
7367 ;; be saved & restored around calls by the caller. If the call
7368 ;; doesn't return normally (nonlocal goto, or an exception is
7369 ;; thrown), then the code at the exception handler label must
7370 ;; restore the PIC register.
7371 (define_expand "exception_receiver"
7376 /* Restore the PIC register using hppa_pic_save_rtx (). The
7377 PIC register is not saved in the frame in 64-bit ABI. */
7378 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
7382 (define_expand "builtin_setjmp_receiver"
7383 [(label_ref (match_operand 0 "" ""))]
7387 /* Restore the PIC register. Hopefully, this will always be from
7388 a stack slot. The only registers that are valid after a
7389 builtin_longjmp are the stack and frame pointers. */
7390 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());