1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 ;; Boston, MA 02110-1301, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
47 [(UNSPECV_BLOCKAGE 0) ; blockage
48 (UNSPECV_DCACHE 1) ; dcacheflush
49 (UNSPECV_ICACHE 2) ; icacheflush
50 (UNSPECV_OPC 3) ; outline_prologue_call
51 (UNSPECV_OEC 4) ; outline_epilogue_call
52 (UNSPECV_LONGJMP 5) ; builtin_longjmp
55 ;; Maximum pc-relative branch offsets.
57 ;; These numbers are a bit smaller than the maximum allowable offsets
58 ;; so that a few instructions may be inserted before the actual branch.
61 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
62 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
65 ;; Insn type. Used to default other attribute values.
67 ;; type "unary" insns have one input operand (1) and one output operand (0)
68 ;; type "binary" insns have two input operands (1,2) and one output (0)
71 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
72 (const_string "binary"))
74 (define_attr "pa_combine_type"
75 "fmpy,faddsub,uncond_branch,addmove,none"
76 (const_string "none"))
78 ;; Processor type (for scheduling, not code generation) -- this attribute
79 ;; must exactly match the processor_type enumeration in pa.h.
81 ;; FIXME: Add 800 scheduling for completeness?
83 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
85 ;; Length (in # of bytes).
86 (define_attr "length" ""
87 (cond [(eq_attr "type" "load,fpload")
88 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
89 (const_int 8) (const_int 4))
91 (eq_attr "type" "store,fpstore")
92 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
93 (const_int 8) (const_int 4))
95 (eq_attr "type" "binary,shift,nullshift")
96 (if_then_else (match_operand 2 "arith_operand" "")
97 (const_int 4) (const_int 12))
99 (eq_attr "type" "move,unary,shift,nullshift")
100 (if_then_else (match_operand 1 "arith_operand" "")
101 (const_int 4) (const_int 8))]
105 (define_asm_attributes
106 [(set_attr "length" "4")
107 (set_attr "type" "multi")])
109 ;; Attributes for instruction and branch scheduling
111 ;; For conditional branches.
112 (define_attr "in_branch_delay" "false,true"
113 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
114 (eq_attr "length" "4"))
115 (const_string "true")
116 (const_string "false")))
118 ;; Disallow instructions which use the FPU since they will tie up the FPU
119 ;; even if the instruction is nullified.
120 (define_attr "in_nullified_branch_delay" "false,true"
121 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
122 (eq_attr "length" "4"))
123 (const_string "true")
124 (const_string "false")))
126 ;; For calls and millicode calls. Allow unconditional branches in the
128 (define_attr "in_call_delay" "false,true"
129 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
130 (eq_attr "length" "4"))
131 (const_string "true")
132 (eq_attr "type" "uncond_branch")
133 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
135 (const_string "true")
136 (const_string "false"))]
137 (const_string "false")))
140 ;; Call delay slot description.
141 (define_delay (eq_attr "type" "call")
142 [(eq_attr "in_call_delay" "true") (nil) (nil)])
144 ;; Millicode call delay slot description.
145 (define_delay (eq_attr "type" "milli")
146 [(eq_attr "in_call_delay" "true") (nil) (nil)])
148 ;; Return and other similar instructions.
149 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
150 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
152 ;; Floating point conditional branch delay slot description.
153 (define_delay (eq_attr "type" "fbranch")
154 [(eq_attr "in_branch_delay" "true")
155 (eq_attr "in_nullified_branch_delay" "true")
158 ;; Integer conditional branch delay slot description.
159 ;; Nullification of conditional branches on the PA is dependent on the
160 ;; direction of the branch. Forward branches nullify true and
161 ;; backward branches nullify false. If the direction is unknown
162 ;; then nullification is not allowed.
163 (define_delay (eq_attr "type" "cbranch")
164 [(eq_attr "in_branch_delay" "true")
165 (and (eq_attr "in_nullified_branch_delay" "true")
166 (attr_flag "forward"))
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "backward"))])
170 (define_delay (and (eq_attr "type" "uncond_branch")
171 (eq (symbol_ref "following_call (insn)")
173 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
175 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
176 ;; load: 2, fpload: 3
177 ;; store, fpstore: 3, no D-cache operations should be scheduled.
179 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
181 ;; Instruction Time Unit Minimum Distance (unit contention)
188 ;; fmpyadd 3 ALU,MPY 2
189 ;; fmpysub 3 ALU,MPY 2
190 ;; fmpycfxt 3 ALU,MPY 2
193 ;; fdiv,sgl 10 MPY 10
194 ;; fdiv,dbl 12 MPY 12
195 ;; fsqrt,sgl 14 MPY 14
196 ;; fsqrt,dbl 18 MPY 18
198 ;; We don't model fmpyadd/fmpysub properly as those instructions
199 ;; keep both the FP ALU and MPY units busy. Given that these
200 ;; processors are obsolete, I'm not going to spend the time to
201 ;; model those instructions correctly.
203 (define_automaton "pa700")
204 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
206 (define_insn_reservation "W0" 4
207 (and (eq_attr "type" "fpcc")
208 (eq_attr "cpu" "700"))
211 (define_insn_reservation "W1" 3
212 (and (eq_attr "type" "fpalu")
213 (eq_attr "cpu" "700"))
216 (define_insn_reservation "W2" 3
217 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
218 (eq_attr "cpu" "700"))
221 (define_insn_reservation "W3" 10
222 (and (eq_attr "type" "fpdivsgl")
223 (eq_attr "cpu" "700"))
226 (define_insn_reservation "W4" 12
227 (and (eq_attr "type" "fpdivdbl")
228 (eq_attr "cpu" "700"))
231 (define_insn_reservation "W5" 14
232 (and (eq_attr "type" "fpsqrtsgl")
233 (eq_attr "cpu" "700"))
236 (define_insn_reservation "W6" 18
237 (and (eq_attr "type" "fpsqrtdbl")
238 (eq_attr "cpu" "700"))
241 (define_insn_reservation "W7" 2
242 (and (eq_attr "type" "load")
243 (eq_attr "cpu" "700"))
246 (define_insn_reservation "W8" 2
247 (and (eq_attr "type" "fpload")
248 (eq_attr "cpu" "700"))
251 (define_insn_reservation "W9" 3
252 (and (eq_attr "type" "store")
253 (eq_attr "cpu" "700"))
256 (define_insn_reservation "W10" 3
257 (and (eq_attr "type" "fpstore")
258 (eq_attr "cpu" "700"))
261 (define_insn_reservation "W11" 1
262 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
263 (eq_attr "cpu" "700"))
266 ;; We have a bypass for all computations in the FP unit which feed an
267 ;; FP store as long as the sizes are the same.
268 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
269 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
270 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
271 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
272 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
274 ;; We have an "anti-bypass" for FP loads which feed an FP store.
275 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
277 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
278 ;; floating point computations with non-floating point computations (fp loads
279 ;; and stores are not fp computations).
281 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
282 ;; take two cycles, during which no Dcache operations should be scheduled.
283 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
284 ;; all have the same memory characteristics if one disregards cache misses.
286 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
287 ;; There's no value in modeling the ALU and MUL separately though
288 ;; since there can never be a functional unit conflict given the
289 ;; latency and issue rates for those units.
292 ;; Instruction Time Unit Minimum Distance (unit contention)
299 ;; fmpyadd 2 ALU,MPY 1
300 ;; fmpysub 2 ALU,MPY 1
301 ;; fmpycfxt 2 ALU,MPY 1
305 ;; fdiv,dbl 15 DIV 15
307 ;; fsqrt,dbl 15 DIV 15
309 (define_automaton "pa7100")
310 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
312 (define_insn_reservation "X0" 2
313 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
314 (eq_attr "cpu" "7100"))
317 (define_insn_reservation "X1" 8
318 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
319 (eq_attr "cpu" "7100"))
320 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
322 (define_insn_reservation "X2" 15
323 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
324 (eq_attr "cpu" "7100"))
325 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
327 (define_insn_reservation "X3" 2
328 (and (eq_attr "type" "load")
329 (eq_attr "cpu" "7100"))
332 (define_insn_reservation "X4" 2
333 (and (eq_attr "type" "fpload")
334 (eq_attr "cpu" "7100"))
337 (define_insn_reservation "X5" 2
338 (and (eq_attr "type" "store")
339 (eq_attr "cpu" "7100"))
340 "i_7100+mem_7100,mem_7100")
342 (define_insn_reservation "X6" 2
343 (and (eq_attr "type" "fpstore")
344 (eq_attr "cpu" "7100"))
345 "i_7100+mem_7100,mem_7100")
347 (define_insn_reservation "X7" 1
348 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
349 (eq_attr "cpu" "7100"))
352 ;; We have a bypass for all computations in the FP unit which feed an
353 ;; FP store as long as the sizes are the same.
354 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
355 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
356 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
358 ;; We have an "anti-bypass" for FP loads which feed an FP store.
359 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
361 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
362 ;; There's no value in modeling the ALU and MUL separately though
363 ;; since there can never be a functional unit conflict that
364 ;; can be avoided given the latency, issue rates and mandatory
365 ;; one cycle cpu-wide lock for a double precision fp multiply.
368 ;; Instruction Time Unit Minimum Distance (unit contention)
375 ;; fmpyadd,sgl 2 ALU,MPY 1
376 ;; fmpyadd,dbl 3 ALU,MPY 2
377 ;; fmpysub,sgl 2 ALU,MPY 1
378 ;; fmpysub,dbl 3 ALU,MPY 2
379 ;; fmpycfxt,sgl 2 ALU,MPY 1
380 ;; fmpycfxt,dbl 3 ALU,MPY 2
385 ;; fdiv,dbl 15 DIV 15
387 ;; fsqrt,dbl 15 DIV 15
389 ;; The PA7200 is just like the PA7100LC except that there is
390 ;; no store-store penalty.
392 ;; The PA7300 is just like the PA7200 except that there is
393 ;; no store-load penalty.
395 ;; Note there are some aspects of the 7100LC we are not modeling
396 ;; at the moment. I'll be reviewing the 7100LC scheduling info
397 ;; shortly and updating this description.
401 ;; other issue modeling
403 (define_automaton "pa7100lc")
404 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
405 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
406 (define_cpu_unit "mem_7100lc" "pa7100lc")
408 ;; Double precision multiplies lock the entire CPU for one
409 ;; cycle. There is no way to avoid this lock and trying to
410 ;; schedule around the lock is pointless and thus there is no
411 ;; value in trying to model this lock.
413 ;; Not modeling the lock allows us to treat fp multiplies just
414 ;; like any other FP alu instruction. It allows for a smaller
415 ;; DFA and may reduce register pressure.
416 (define_insn_reservation "Y0" 2
417 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
418 (eq_attr "cpu" "7100LC,7200,7300"))
419 "f_7100lc,fpmac_7100lc")
421 ;; fp division and sqrt instructions lock the entire CPU for
422 ;; 7 cycles (single precision) or 14 cycles (double precision).
423 ;; There is no way to avoid this lock and trying to schedule
424 ;; around the lock is pointless and thus there is no value in
425 ;; trying to model this lock. Not modeling the lock allows
426 ;; for a smaller DFA and may reduce register pressure.
427 (define_insn_reservation "Y1" 1
428 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
429 (eq_attr "cpu" "7100LC,7200,7300"))
432 (define_insn_reservation "Y2" 2
433 (and (eq_attr "type" "load")
434 (eq_attr "cpu" "7100LC,7200,7300"))
435 "i1_7100lc+mem_7100lc")
437 (define_insn_reservation "Y3" 2
438 (and (eq_attr "type" "fpload")
439 (eq_attr "cpu" "7100LC,7200,7300"))
440 "i1_7100lc+mem_7100lc")
442 (define_insn_reservation "Y4" 2
443 (and (eq_attr "type" "store")
444 (eq_attr "cpu" "7100LC"))
445 "i1_7100lc+mem_7100lc,mem_7100lc")
447 (define_insn_reservation "Y5" 2
448 (and (eq_attr "type" "fpstore")
449 (eq_attr "cpu" "7100LC"))
450 "i1_7100lc+mem_7100lc,mem_7100lc")
452 (define_insn_reservation "Y6" 1
453 (and (eq_attr "type" "shift,nullshift")
454 (eq_attr "cpu" "7100LC,7200,7300"))
457 (define_insn_reservation "Y7" 1
458 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
459 (eq_attr "cpu" "7100LC,7200,7300"))
460 "(i0_7100lc|i1_7100lc)")
462 ;; The 7200 has a store-load penalty
463 (define_insn_reservation "Y8" 2
464 (and (eq_attr "type" "store")
465 (eq_attr "cpu" "7200"))
466 "i1_7100lc,mem_7100lc")
468 (define_insn_reservation "Y9" 2
469 (and (eq_attr "type" "fpstore")
470 (eq_attr "cpu" "7200"))
471 "i1_7100lc,mem_7100lc")
473 ;; The 7300 has no penalty for store-store or store-load
474 (define_insn_reservation "Y10" 2
475 (and (eq_attr "type" "store")
476 (eq_attr "cpu" "7300"))
479 (define_insn_reservation "Y11" 2
480 (and (eq_attr "type" "fpstore")
481 (eq_attr "cpu" "7300"))
484 ;; We have an "anti-bypass" for FP loads which feed an FP store.
485 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
487 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
488 ;; traditional architecture.
490 ;; The PA8000 has a large (56) entry reorder buffer that is split between
491 ;; memory and non-memory operations.
493 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
494 ;; the function units, with the exception of branches and multi-output
495 ;; instructions. The PA8000 can retire two non-memory operations per cycle
496 ;; and two memory operations per cycle, only one of which may be a store.
498 ;; Given the large reorder buffer, the processor can hide most latencies.
499 ;; According to HP, they've got the best results by scheduling for retirement
500 ;; bandwidth with limited latency scheduling for floating point operations.
501 ;; Latency for integer operations and memory references is ignored.
504 ;; We claim floating point operations have a 2 cycle latency and are
505 ;; fully pipelined, except for div and sqrt which are not pipelined and
506 ;; take from 17 to 31 cycles to complete.
508 ;; It's worth noting that there is no way to saturate all the functional
509 ;; units on the PA8000 as there is not enough issue bandwidth.
511 (define_automaton "pa8000")
512 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
513 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
514 (define_cpu_unit "store_8000" "pa8000")
515 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
516 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
517 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
518 (define_reservation "im_8000" "im0_8000 | im1_8000")
519 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
520 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
521 (define_reservation "f_8000" "f0_8000 | f1_8000")
522 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
524 ;; We can issue any two memops per cycle, but we can only retire
525 ;; one memory store per cycle. We assume that the reorder buffer
526 ;; will hide any memory latencies per HP's recommendation.
527 (define_insn_reservation "Z0" 0
529 (eq_attr "type" "load,fpload")
530 (eq_attr "cpu" "8000"))
533 (define_insn_reservation "Z1" 0
535 (eq_attr "type" "store,fpstore")
536 (eq_attr "cpu" "8000"))
537 "im_8000,rm_8000+store_8000")
539 ;; We can issue and retire two non-memory operations per cycle with
540 ;; a few exceptions (branches). This group catches those we want
541 ;; to assume have zero latency.
542 (define_insn_reservation "Z2" 0
544 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
545 (eq_attr "cpu" "8000"))
548 ;; Branches use both slots in the non-memory issue and
550 (define_insn_reservation "Z3" 0
552 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
553 (eq_attr "cpu" "8000"))
554 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
556 ;; We partial latency schedule the floating point units.
557 ;; They can issue/retire two at a time in the non-memory
558 ;; units. We fix their latency at 2 cycles and they
559 ;; are fully pipelined.
560 (define_insn_reservation "Z4" 1
562 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
563 (eq_attr "cpu" "8000"))
564 "inm_8000,f_8000,rnm_8000")
566 ;; The fdivsqrt units are not pipelined and have a very long latency.
567 ;; To keep the DFA from exploding, we do not show all the
568 ;; reservations for the divsqrt unit.
569 (define_insn_reservation "Z5" 17
571 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
572 (eq_attr "cpu" "8000"))
573 "inm_8000,fdivsqrt_8000*6,rnm_8000")
575 (define_insn_reservation "Z6" 31
577 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
578 (eq_attr "cpu" "8000"))
579 "inm_8000,fdivsqrt_8000*6,rnm_8000")
581 (include "predicates.md")
583 ;; Compare instructions.
584 ;; This controls RTL generation and register allocation.
586 ;; We generate RTL for comparisons and branches by having the cmpxx
587 ;; patterns store away the operands. Then, the scc and bcc patterns
588 ;; emit RTL for both the compare and the branch.
591 (define_expand "cmpdi"
593 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
594 (match_operand:DI 1 "register_operand" "")))]
599 hppa_compare_op0 = operands[0];
600 hppa_compare_op1 = operands[1];
601 hppa_branch_type = CMP_SI;
605 (define_expand "cmpsi"
607 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
608 (match_operand:SI 1 "arith5_operand" "")))]
612 hppa_compare_op0 = operands[0];
613 hppa_compare_op1 = operands[1];
614 hppa_branch_type = CMP_SI;
618 (define_expand "cmpsf"
620 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
621 (match_operand:SF 1 "reg_or_0_operand" "")))]
622 "! TARGET_SOFT_FLOAT"
625 hppa_compare_op0 = operands[0];
626 hppa_compare_op1 = operands[1];
627 hppa_branch_type = CMP_SF;
631 (define_expand "cmpdf"
633 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
634 (match_operand:DF 1 "reg_or_0_operand" "")))]
635 "! TARGET_SOFT_FLOAT"
638 hppa_compare_op0 = operands[0];
639 hppa_compare_op1 = operands[1];
640 hppa_branch_type = CMP_DF;
646 (match_operator:CCFP 2 "comparison_operator"
647 [(match_operand:SF 0 "reg_or_0_operand" "fG")
648 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,sgl,%Y2 %f0,%f1"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
656 (match_operator:CCFP 2 "comparison_operator"
657 [(match_operand:DF 0 "reg_or_0_operand" "fG")
658 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
659 "! TARGET_SOFT_FLOAT"
660 "fcmp,dbl,%Y2 %f0,%f1"
661 [(set_attr "length" "4")
662 (set_attr "type" "fpcc")])
664 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
665 ;; placeholders. This is necessary in rare situations when a
666 ;; placeholder is re-emitted (see PR 8705).
668 (define_expand "movccfp"
670 (match_operand 0 "const_int_operand" ""))]
671 "! TARGET_SOFT_FLOAT"
674 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
678 ;; The following patterns are optimization placeholders. In almost
679 ;; all cases, the user of the condition code will be simplified and the
680 ;; original condition code setting insn should be eliminated.
682 (define_insn "*movccfp0"
685 "! TARGET_SOFT_FLOAT"
686 "fcmp,dbl,= %%fr0,%%fr0"
687 [(set_attr "length" "4")
688 (set_attr "type" "fpcc")])
690 (define_insn "*movccfp1"
693 "! TARGET_SOFT_FLOAT"
694 "fcmp,dbl,!= %%fr0,%%fr0"
695 [(set_attr "length" "4")
696 (set_attr "type" "fpcc")])
701 [(set (match_operand:SI 0 "register_operand" "")
707 /* fp scc patterns rarely match, and are not a win on the PA. */
708 if (hppa_branch_type != CMP_SI)
710 /* set up operands from compare. */
711 operands[1] = hppa_compare_op0;
712 operands[2] = hppa_compare_op1;
713 /* fall through and generate default code */
717 [(set (match_operand:SI 0 "register_operand" "")
723 /* fp scc patterns rarely match, and are not a win on the PA. */
724 if (hppa_branch_type != CMP_SI)
726 operands[1] = hppa_compare_op0;
727 operands[2] = hppa_compare_op1;
731 [(set (match_operand:SI 0 "register_operand" "")
737 /* fp scc patterns rarely match, and are not a win on the PA. */
738 if (hppa_branch_type != CMP_SI)
740 operands[1] = hppa_compare_op0;
741 operands[2] = hppa_compare_op1;
745 [(set (match_operand:SI 0 "register_operand" "")
751 /* fp scc patterns rarely match, and are not a win on the PA. */
752 if (hppa_branch_type != CMP_SI)
754 operands[1] = hppa_compare_op0;
755 operands[2] = hppa_compare_op1;
759 [(set (match_operand:SI 0 "register_operand" "")
765 /* fp scc patterns rarely match, and are not a win on the PA. */
766 if (hppa_branch_type != CMP_SI)
768 operands[1] = hppa_compare_op0;
769 operands[2] = hppa_compare_op1;
773 [(set (match_operand:SI 0 "register_operand" "")
779 /* fp scc patterns rarely match, and are not a win on the PA. */
780 if (hppa_branch_type != CMP_SI)
782 operands[1] = hppa_compare_op0;
783 operands[2] = hppa_compare_op1;
786 (define_expand "sltu"
787 [(set (match_operand:SI 0 "register_operand" "")
788 (ltu:SI (match_dup 1)
793 if (hppa_branch_type != CMP_SI)
795 operands[1] = hppa_compare_op0;
796 operands[2] = hppa_compare_op1;
799 (define_expand "sgtu"
800 [(set (match_operand:SI 0 "register_operand" "")
801 (gtu:SI (match_dup 1)
806 if (hppa_branch_type != CMP_SI)
808 operands[1] = hppa_compare_op0;
809 operands[2] = hppa_compare_op1;
812 (define_expand "sleu"
813 [(set (match_operand:SI 0 "register_operand" "")
814 (leu:SI (match_dup 1)
819 if (hppa_branch_type != CMP_SI)
821 operands[1] = hppa_compare_op0;
822 operands[2] = hppa_compare_op1;
825 (define_expand "sgeu"
826 [(set (match_operand:SI 0 "register_operand" "")
827 (geu:SI (match_dup 1)
832 if (hppa_branch_type != CMP_SI)
834 operands[1] = hppa_compare_op0;
835 operands[2] = hppa_compare_op1;
838 ;; Instruction canonicalization puts immediate operands second, which
839 ;; is the reverse of what we want.
842 [(set (match_operand:SI 0 "register_operand" "=r")
843 (match_operator:SI 3 "comparison_operator"
844 [(match_operand:SI 1 "register_operand" "r")
845 (match_operand:SI 2 "arith11_operand" "rI")]))]
847 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "8")])
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (match_operator:DI 3 "comparison_operator"
854 [(match_operand:DI 1 "register_operand" "r")
855 (match_operand:DI 2 "arith11_operand" "rI")]))]
857 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
858 [(set_attr "type" "binary")
859 (set_attr "length" "8")])
861 (define_insn "iorscc"
862 [(set (match_operand:SI 0 "register_operand" "=r")
863 (ior:SI (match_operator:SI 3 "comparison_operator"
864 [(match_operand:SI 1 "register_operand" "r")
865 (match_operand:SI 2 "arith11_operand" "rI")])
866 (match_operator:SI 6 "comparison_operator"
867 [(match_operand:SI 4 "register_operand" "r")
868 (match_operand:SI 5 "arith11_operand" "rI")])))]
870 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
871 [(set_attr "type" "binary")
872 (set_attr "length" "12")])
875 [(set (match_operand:DI 0 "register_operand" "=r")
876 (ior:DI (match_operator:DI 3 "comparison_operator"
877 [(match_operand:DI 1 "register_operand" "r")
878 (match_operand:DI 2 "arith11_operand" "rI")])
879 (match_operator:DI 6 "comparison_operator"
880 [(match_operand:DI 4 "register_operand" "r")
881 (match_operand:DI 5 "arith11_operand" "rI")])))]
883 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
884 [(set_attr "type" "binary")
885 (set_attr "length" "12")])
887 ;; Combiner patterns for common operations performed with the output
888 ;; from an scc insn (negscc and incscc).
889 (define_insn "negscc"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (neg:SI (match_operator:SI 3 "comparison_operator"
892 [(match_operand:SI 1 "register_operand" "r")
893 (match_operand:SI 2 "arith11_operand" "rI")])))]
895 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
900 [(set (match_operand:DI 0 "register_operand" "=r")
901 (neg:DI (match_operator:DI 3 "comparison_operator"
902 [(match_operand:DI 1 "register_operand" "r")
903 (match_operand:DI 2 "arith11_operand" "rI")])))]
905 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
906 [(set_attr "type" "binary")
907 (set_attr "length" "8")])
909 ;; Patterns for adding/subtracting the result of a boolean expression from
910 ;; a register. First we have special patterns that make use of the carry
911 ;; bit, and output only two instructions. For the cases we can't in
912 ;; general do in two instructions, the incscc pattern at the end outputs
913 ;; two or three instructions.
916 [(set (match_operand:SI 0 "register_operand" "=r")
917 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
918 (match_operand:SI 3 "arith11_operand" "rI"))
919 (match_operand:SI 1 "register_operand" "r")))]
921 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
922 [(set_attr "type" "binary")
923 (set_attr "length" "8")])
926 [(set (match_operand:DI 0 "register_operand" "=r")
927 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
928 (match_operand:DI 3 "arith11_operand" "rI"))
929 (match_operand:DI 1 "register_operand" "r")))]
931 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
932 [(set_attr "type" "binary")
933 (set_attr "length" "8")])
935 ; This need only accept registers for op3, since canonicalization
936 ; replaces geu with gtu when op3 is an integer.
938 [(set (match_operand:SI 0 "register_operand" "=r")
939 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
940 (match_operand:SI 3 "register_operand" "r"))
941 (match_operand:SI 1 "register_operand" "r")))]
943 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "8")])
948 [(set (match_operand:DI 0 "register_operand" "=r")
949 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
950 (match_operand:DI 3 "register_operand" "r"))
951 (match_operand:DI 1 "register_operand" "r")))]
953 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
954 [(set_attr "type" "binary")
955 (set_attr "length" "8")])
957 ; Match only integers for op3 here. This is used as canonical form of the
958 ; geu pattern when op3 is an integer. Don't match registers since we can't
959 ; make better code than the general incscc pattern.
961 [(set (match_operand:SI 0 "register_operand" "=r")
962 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
963 (match_operand:SI 3 "int11_operand" "I"))
964 (match_operand:SI 1 "register_operand" "r")))]
966 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
967 [(set_attr "type" "binary")
968 (set_attr "length" "8")])
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
973 (match_operand:DI 3 "int11_operand" "I"))
974 (match_operand:DI 1 "register_operand" "r")))]
976 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
980 (define_insn "incscc"
981 [(set (match_operand:SI 0 "register_operand" "=r,r")
982 (plus:SI (match_operator:SI 4 "comparison_operator"
983 [(match_operand:SI 2 "register_operand" "r,r")
984 (match_operand:SI 3 "arith11_operand" "rI,rI")])
985 (match_operand:SI 1 "register_operand" "0,?r")))]
988 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
989 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
990 [(set_attr "type" "binary,binary")
991 (set_attr "length" "8,12")])
994 [(set (match_operand:DI 0 "register_operand" "=r,r")
995 (plus:DI (match_operator:DI 4 "comparison_operator"
996 [(match_operand:DI 2 "register_operand" "r,r")
997 (match_operand:DI 3 "arith11_operand" "rI,rI")])
998 (match_operand:DI 1 "register_operand" "0,?r")))]
1001 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1002 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1003 [(set_attr "type" "binary,binary")
1004 (set_attr "length" "8,12")])
1007 [(set (match_operand:SI 0 "register_operand" "=r")
1008 (minus:SI (match_operand:SI 1 "register_operand" "r")
1009 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1010 (match_operand:SI 3 "arith11_operand" "rI"))))]
1012 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1013 [(set_attr "type" "binary")
1014 (set_attr "length" "8")])
1017 [(set (match_operand:DI 0 "register_operand" "=r")
1018 (minus:DI (match_operand:DI 1 "register_operand" "r")
1019 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1020 (match_operand:DI 3 "arith11_operand" "rI"))))]
1022 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1023 [(set_attr "type" "binary")
1024 (set_attr "length" "8")])
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1029 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1030 (match_operand:SI 3 "arith11_operand" "rI")))
1031 (match_operand:SI 4 "register_operand" "r")))]
1033 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1034 [(set_attr "type" "binary")
1035 (set_attr "length" "8")])
1038 [(set (match_operand:DI 0 "register_operand" "=r")
1039 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1040 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1041 (match_operand:DI 3 "arith11_operand" "rI")))
1042 (match_operand:DI 4 "register_operand" "r")))]
1044 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1045 [(set_attr "type" "binary")
1046 (set_attr "length" "8")])
1048 ; This need only accept registers for op3, since canonicalization
1049 ; replaces ltu with leu when op3 is an integer.
1051 [(set (match_operand:SI 0 "register_operand" "=r")
1052 (minus:SI (match_operand:SI 1 "register_operand" "r")
1053 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1054 (match_operand:SI 3 "register_operand" "r"))))]
1056 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1057 [(set_attr "type" "binary")
1058 (set_attr "length" "8")])
1061 [(set (match_operand:DI 0 "register_operand" "=r")
1062 (minus:DI (match_operand:DI 1 "register_operand" "r")
1063 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1064 (match_operand:DI 3 "register_operand" "r"))))]
1066 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1067 [(set_attr "type" "binary")
1068 (set_attr "length" "8")])
1071 [(set (match_operand:SI 0 "register_operand" "=r")
1072 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1073 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1074 (match_operand:SI 3 "register_operand" "r")))
1075 (match_operand:SI 4 "register_operand" "r")))]
1077 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1078 [(set_attr "type" "binary")
1079 (set_attr "length" "8")])
1082 [(set (match_operand:DI 0 "register_operand" "=r")
1083 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1084 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1085 (match_operand:DI 3 "register_operand" "r")))
1086 (match_operand:DI 4 "register_operand" "r")))]
1088 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1089 [(set_attr "type" "binary")
1090 (set_attr "length" "8")])
1092 ; Match only integers for op3 here. This is used as canonical form of the
1093 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1094 ; make better code than the general incscc pattern.
1096 [(set (match_operand:SI 0 "register_operand" "=r")
1097 (minus:SI (match_operand:SI 1 "register_operand" "r")
1098 (leu:SI (match_operand:SI 2 "register_operand" "r")
1099 (match_operand:SI 3 "int11_operand" "I"))))]
1101 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1102 [(set_attr "type" "binary")
1103 (set_attr "length" "8")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (minus:DI (match_operand:DI 1 "register_operand" "r")
1108 (leu:DI (match_operand:DI 2 "register_operand" "r")
1109 (match_operand:DI 3 "int11_operand" "I"))))]
1111 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1112 [(set_attr "type" "binary")
1113 (set_attr "length" "8")])
1116 [(set (match_operand:SI 0 "register_operand" "=r")
1117 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1118 (leu:SI (match_operand:SI 2 "register_operand" "r")
1119 (match_operand:SI 3 "int11_operand" "I")))
1120 (match_operand:SI 4 "register_operand" "r")))]
1122 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1123 [(set_attr "type" "binary")
1124 (set_attr "length" "8")])
1127 [(set (match_operand:DI 0 "register_operand" "=r")
1128 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1129 (leu:DI (match_operand:DI 2 "register_operand" "r")
1130 (match_operand:DI 3 "int11_operand" "I")))
1131 (match_operand:DI 4 "register_operand" "r")))]
1133 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1134 [(set_attr "type" "binary")
1135 (set_attr "length" "8")])
1137 (define_insn "decscc"
1138 [(set (match_operand:SI 0 "register_operand" "=r,r")
1139 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1140 (match_operator:SI 4 "comparison_operator"
1141 [(match_operand:SI 2 "register_operand" "r,r")
1142 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1145 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1146 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1147 [(set_attr "type" "binary,binary")
1148 (set_attr "length" "8,12")])
1151 [(set (match_operand:DI 0 "register_operand" "=r,r")
1152 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1153 (match_operator:DI 4 "comparison_operator"
1154 [(match_operand:DI 2 "register_operand" "r,r")
1155 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1158 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1159 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1160 [(set_attr "type" "binary,binary")
1161 (set_attr "length" "8,12")])
1163 ; Patterns for max and min. (There is no need for an earlyclobber in the
1164 ; last alternative since the middle alternative will match if op0 == op1.)
1166 (define_insn "sminsi3"
1167 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1168 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1169 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1172 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1173 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1174 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1175 [(set_attr "type" "multi,multi,multi")
1176 (set_attr "length" "8,8,8")])
1178 (define_insn "smindi3"
1179 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1180 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1181 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1184 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1185 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1186 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1187 [(set_attr "type" "multi,multi,multi")
1188 (set_attr "length" "8,8,8")])
1190 (define_insn "uminsi3"
1191 [(set (match_operand:SI 0 "register_operand" "=r,r")
1192 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1193 (match_operand:SI 2 "arith11_operand" "r,I")))]
1196 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1197 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1198 [(set_attr "type" "multi,multi")
1199 (set_attr "length" "8,8")])
1201 (define_insn "umindi3"
1202 [(set (match_operand:DI 0 "register_operand" "=r,r")
1203 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1204 (match_operand:DI 2 "arith11_operand" "r,I")))]
1207 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1208 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1209 [(set_attr "type" "multi,multi")
1210 (set_attr "length" "8,8")])
1212 (define_insn "smaxsi3"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1214 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1215 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1218 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1219 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1220 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1221 [(set_attr "type" "multi,multi,multi")
1222 (set_attr "length" "8,8,8")])
1224 (define_insn "smaxdi3"
1225 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1226 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1227 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1230 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1231 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1232 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1233 [(set_attr "type" "multi,multi,multi")
1234 (set_attr "length" "8,8,8")])
1236 (define_insn "umaxsi3"
1237 [(set (match_operand:SI 0 "register_operand" "=r,r")
1238 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1239 (match_operand:SI 2 "arith11_operand" "r,I")))]
1242 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1243 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1244 [(set_attr "type" "multi,multi")
1245 (set_attr "length" "8,8")])
1247 (define_insn "umaxdi3"
1248 [(set (match_operand:DI 0 "register_operand" "=r,r")
1249 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1250 (match_operand:DI 2 "arith11_operand" "r,I")))]
1253 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1254 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1255 [(set_attr "type" "multi,multi")
1256 (set_attr "length" "8,8")])
1258 (define_insn "abssi2"
1259 [(set (match_operand:SI 0 "register_operand" "=r")
1260 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1262 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1263 [(set_attr "type" "multi")
1264 (set_attr "length" "8")])
1266 (define_insn "absdi2"
1267 [(set (match_operand:DI 0 "register_operand" "=r")
1268 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1270 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1271 [(set_attr "type" "multi")
1272 (set_attr "length" "8")])
1274 ;;; Experimental conditional move patterns
1276 (define_expand "movsicc"
1277 [(set (match_operand:SI 0 "register_operand" "")
1279 (match_operator 1 "comparison_operator"
1282 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1283 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1287 enum rtx_code code = GET_CODE (operands[1]);
1289 if (hppa_branch_type != CMP_SI)
1292 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1293 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1296 /* operands[1] is currently the result of compare_from_rtx. We want to
1297 emit a compare of the original operands. */
1298 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1299 operands[4] = hppa_compare_op0;
1300 operands[5] = hppa_compare_op1;
1303 ;; We used to accept any register for op1.
1305 ;; However, it loses sometimes because the compiler will end up using
1306 ;; different registers for op0 and op1 in some critical cases. local-alloc
1307 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1309 ;; If/when global register allocation supports tying we should allow any
1310 ;; register for op1 again.
1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1314 (match_operator 2 "comparison_operator"
1315 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1316 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1317 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1321 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1322 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1323 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1324 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1325 [(set_attr "type" "multi,multi,multi,nullshift")
1326 (set_attr "length" "8,8,8,8")])
1329 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1331 (match_operator 5 "comparison_operator"
1332 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1333 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1334 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1335 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1338 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1339 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1340 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1341 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1342 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1343 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1344 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1345 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1346 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1347 (set_attr "length" "8,8,8,8,8,8,8,8")])
1349 (define_expand "movdicc"
1350 [(set (match_operand:DI 0 "register_operand" "")
1352 (match_operator 1 "comparison_operator"
1355 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1356 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1360 enum rtx_code code = GET_CODE (operands[1]);
1362 if (hppa_branch_type != CMP_SI)
1365 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1366 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1369 /* operands[1] is currently the result of compare_from_rtx. We want to
1370 emit a compare of the original operands. */
1371 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1372 operands[4] = hppa_compare_op0;
1373 operands[5] = hppa_compare_op1;
1376 ; We need the first constraint alternative in order to avoid
1377 ; earlyclobbers on all other alternatives.
1379 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1381 (match_operator 2 "comparison_operator"
1382 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1383 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1384 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1388 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1389 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1390 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1391 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1392 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1393 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1394 (set_attr "length" "8,8,8,8,8")])
1397 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1399 (match_operator 5 "comparison_operator"
1400 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1401 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1402 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1403 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1406 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1407 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1408 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1409 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1410 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1411 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1412 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1413 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1414 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1415 (set_attr "length" "8,8,8,8,8,8,8,8")])
1417 ;; Conditional Branches
1419 (define_expand "beq"
1421 (if_then_else (eq (match_dup 1) (match_dup 2))
1422 (label_ref (match_operand 0 "" ""))
1427 if (hppa_branch_type != CMP_SI)
1429 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1430 emit_bcond_fp (NE, operands[0]);
1433 /* set up operands from compare. */
1434 operands[1] = hppa_compare_op0;
1435 operands[2] = hppa_compare_op1;
1436 /* fall through and generate default code */
1439 (define_expand "bne"
1441 (if_then_else (ne (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bgt"
1459 (if_then_else (gt (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "blt"
1477 (if_then_else (lt (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bge"
1495 (if_then_else (ge (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1504 emit_bcond_fp (NE, operands[0]);
1507 operands[1] = hppa_compare_op0;
1508 operands[2] = hppa_compare_op1;
1511 (define_expand "ble"
1513 (if_then_else (le (match_dup 1) (match_dup 2))
1514 (label_ref (match_operand 0 "" ""))
1519 if (hppa_branch_type != CMP_SI)
1521 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1522 emit_bcond_fp (NE, operands[0]);
1525 operands[1] = hppa_compare_op0;
1526 operands[2] = hppa_compare_op1;
1529 (define_expand "bgtu"
1531 (if_then_else (gtu (match_dup 1) (match_dup 2))
1532 (label_ref (match_operand 0 "" ""))
1537 if (hppa_branch_type != CMP_SI)
1539 operands[1] = hppa_compare_op0;
1540 operands[2] = hppa_compare_op1;
1543 (define_expand "bltu"
1545 (if_then_else (ltu (match_dup 1) (match_dup 2))
1546 (label_ref (match_operand 0 "" ""))
1551 if (hppa_branch_type != CMP_SI)
1553 operands[1] = hppa_compare_op0;
1554 operands[2] = hppa_compare_op1;
1557 (define_expand "bgeu"
1559 (if_then_else (geu (match_dup 1) (match_dup 2))
1560 (label_ref (match_operand 0 "" ""))
1565 if (hppa_branch_type != CMP_SI)
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1571 (define_expand "bleu"
1573 (if_then_else (leu (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1579 if (hppa_branch_type != CMP_SI)
1581 operands[1] = hppa_compare_op0;
1582 operands[2] = hppa_compare_op1;
1585 (define_expand "bltgt"
1587 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1588 (label_ref (match_operand 0 "" ""))
1593 if (hppa_branch_type == CMP_SI)
1595 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1596 emit_bcond_fp (NE, operands[0]);
1600 (define_expand "bunle"
1602 (if_then_else (unle (match_dup 1) (match_dup 2))
1603 (label_ref (match_operand 0 "" ""))
1608 if (hppa_branch_type == CMP_SI)
1610 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1611 emit_bcond_fp (NE, operands[0]);
1615 (define_expand "bunlt"
1617 (if_then_else (unlt (match_dup 1) (match_dup 2))
1618 (label_ref (match_operand 0 "" ""))
1623 if (hppa_branch_type == CMP_SI)
1625 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1626 emit_bcond_fp (NE, operands[0]);
1630 (define_expand "bunge"
1632 (if_then_else (unge (match_dup 1) (match_dup 2))
1633 (label_ref (match_operand 0 "" ""))
1638 if (hppa_branch_type == CMP_SI)
1640 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1641 emit_bcond_fp (NE, operands[0]);
1645 (define_expand "bungt"
1647 (if_then_else (ungt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1653 if (hppa_branch_type == CMP_SI)
1655 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1660 (define_expand "buneq"
1662 (if_then_else (uneq (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1668 if (hppa_branch_type == CMP_SI)
1670 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1675 (define_expand "bunordered"
1677 (if_then_else (unordered (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1683 if (hppa_branch_type == CMP_SI)
1685 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1690 (define_expand "bordered"
1692 (if_then_else (ordered (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1698 if (hppa_branch_type == CMP_SI)
1700 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1705 ;; Match the branch patterns.
1708 ;; Note a long backward conditional branch with an annulled delay slot
1709 ;; has a length of 12.
1713 (match_operator 3 "comparison_operator"
1714 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1715 (match_operand:SI 2 "arith5_operand" "rL")])
1716 (label_ref (match_operand 0 "" ""))
1721 return output_cbranch (operands, 0, insn);
1723 [(set_attr "type" "cbranch")
1724 (set (attr "length")
1725 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1726 (const_int MAX_12BIT_OFFSET))
1728 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1729 (const_int MAX_17BIT_OFFSET))
1731 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1733 (eq (symbol_ref "flag_pic") (const_int 0))
1737 ;; Match the negated branch.
1742 (match_operator 3 "comparison_operator"
1743 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1744 (match_operand:SI 2 "arith5_operand" "rL")])
1746 (label_ref (match_operand 0 "" ""))))]
1750 return output_cbranch (operands, 1, insn);
1752 [(set_attr "type" "cbranch")
1753 (set (attr "length")
1754 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1755 (const_int MAX_12BIT_OFFSET))
1757 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1758 (const_int MAX_17BIT_OFFSET))
1760 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1762 (eq (symbol_ref "flag_pic") (const_int 0))
1769 (match_operator 3 "comparison_operator"
1770 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1771 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1772 (label_ref (match_operand 0 "" ""))
1777 return output_cbranch (operands, 0, insn);
1779 [(set_attr "type" "cbranch")
1780 (set (attr "length")
1781 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1782 (const_int MAX_12BIT_OFFSET))
1784 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1785 (const_int MAX_17BIT_OFFSET))
1787 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1789 (eq (symbol_ref "flag_pic") (const_int 0))
1793 ;; Match the negated branch.
1798 (match_operator 3 "comparison_operator"
1799 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1800 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1802 (label_ref (match_operand 0 "" ""))))]
1806 return output_cbranch (operands, 1, insn);
1808 [(set_attr "type" "cbranch")
1809 (set (attr "length")
1810 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1811 (const_int MAX_12BIT_OFFSET))
1813 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1814 (const_int MAX_17BIT_OFFSET))
1816 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1818 (eq (symbol_ref "flag_pic") (const_int 0))
1824 (match_operator 3 "cmpib_comparison_operator"
1825 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1826 (match_operand:DI 2 "arith5_operand" "rL")])
1827 (label_ref (match_operand 0 "" ""))
1832 return output_cbranch (operands, 0, insn);
1834 [(set_attr "type" "cbranch")
1835 (set (attr "length")
1836 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1837 (const_int MAX_12BIT_OFFSET))
1839 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1840 (const_int MAX_17BIT_OFFSET))
1842 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1844 (eq (symbol_ref "flag_pic") (const_int 0))
1848 ;; Match the negated branch.
1853 (match_operator 3 "cmpib_comparison_operator"
1854 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1855 (match_operand:DI 2 "arith5_operand" "rL")])
1857 (label_ref (match_operand 0 "" ""))))]
1861 return output_cbranch (operands, 1, insn);
1863 [(set_attr "type" "cbranch")
1864 (set (attr "length")
1865 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1866 (const_int MAX_12BIT_OFFSET))
1868 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1869 (const_int MAX_17BIT_OFFSET))
1871 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1873 (eq (symbol_ref "flag_pic") (const_int 0))
1877 ;; Branch on Bit patterns.
1881 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1883 (match_operand:SI 1 "uint5_operand" ""))
1885 (label_ref (match_operand 2 "" ""))
1890 return output_bb (operands, 0, insn, 0);
1892 [(set_attr "type" "cbranch")
1893 (set (attr "length")
1894 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1895 (const_int MAX_12BIT_OFFSET))
1897 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1898 (const_int MAX_17BIT_OFFSET))
1900 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1902 (eq (symbol_ref "flag_pic") (const_int 0))
1909 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1911 (match_operand:DI 1 "uint32_operand" ""))
1913 (label_ref (match_operand 2 "" ""))
1918 return output_bb (operands, 0, insn, 0);
1920 [(set_attr "type" "cbranch")
1921 (set (attr "length")
1922 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1923 (const_int MAX_12BIT_OFFSET))
1925 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1926 (const_int MAX_17BIT_OFFSET))
1928 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1930 (eq (symbol_ref "flag_pic") (const_int 0))
1937 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1939 (match_operand:SI 1 "uint5_operand" ""))
1942 (label_ref (match_operand 2 "" ""))))]
1946 return output_bb (operands, 1, insn, 0);
1948 [(set_attr "type" "cbranch")
1949 (set (attr "length")
1950 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1951 (const_int MAX_12BIT_OFFSET))
1953 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1954 (const_int MAX_17BIT_OFFSET))
1956 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1958 (eq (symbol_ref "flag_pic") (const_int 0))
1965 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1967 (match_operand:DI 1 "uint32_operand" ""))
1970 (label_ref (match_operand 2 "" ""))))]
1974 return output_bb (operands, 1, insn, 0);
1976 [(set_attr "type" "cbranch")
1977 (set (attr "length")
1978 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1979 (const_int MAX_12BIT_OFFSET))
1981 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1982 (const_int MAX_17BIT_OFFSET))
1984 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1986 (eq (symbol_ref "flag_pic") (const_int 0))
1993 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1995 (match_operand:SI 1 "uint5_operand" ""))
1997 (label_ref (match_operand 2 "" ""))
2002 return output_bb (operands, 0, insn, 1);
2004 [(set_attr "type" "cbranch")
2005 (set (attr "length")
2006 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2007 (const_int MAX_12BIT_OFFSET))
2009 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2010 (const_int MAX_17BIT_OFFSET))
2012 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2014 (eq (symbol_ref "flag_pic") (const_int 0))
2021 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2023 (match_operand:DI 1 "uint32_operand" ""))
2025 (label_ref (match_operand 2 "" ""))
2030 return output_bb (operands, 0, insn, 1);
2032 [(set_attr "type" "cbranch")
2033 (set (attr "length")
2034 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2035 (const_int MAX_12BIT_OFFSET))
2037 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (const_int MAX_17BIT_OFFSET))
2040 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2042 (eq (symbol_ref "flag_pic") (const_int 0))
2049 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2051 (match_operand:SI 1 "uint5_operand" ""))
2054 (label_ref (match_operand 2 "" ""))))]
2058 return output_bb (operands, 1, insn, 1);
2060 [(set_attr "type" "cbranch")
2061 (set (attr "length")
2062 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2063 (const_int MAX_12BIT_OFFSET))
2065 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2066 (const_int MAX_17BIT_OFFSET))
2068 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2070 (eq (symbol_ref "flag_pic") (const_int 0))
2077 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2079 (match_operand:DI 1 "uint32_operand" ""))
2082 (label_ref (match_operand 2 "" ""))))]
2086 return output_bb (operands, 1, insn, 1);
2088 [(set_attr "type" "cbranch")
2089 (set (attr "length")
2090 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2091 (const_int MAX_12BIT_OFFSET))
2093 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2094 (const_int MAX_17BIT_OFFSET))
2096 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2098 (eq (symbol_ref "flag_pic") (const_int 0))
2102 ;; Branch on Variable Bit patterns.
2106 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2108 (match_operand:SI 1 "register_operand" "q"))
2110 (label_ref (match_operand 2 "" ""))
2115 return output_bvb (operands, 0, insn, 0);
2117 [(set_attr "type" "cbranch")
2118 (set (attr "length")
2119 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2120 (const_int MAX_12BIT_OFFSET))
2122 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_17BIT_OFFSET))
2125 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2127 (eq (symbol_ref "flag_pic") (const_int 0))
2134 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2136 (match_operand:DI 1 "register_operand" "q"))
2138 (label_ref (match_operand 2 "" ""))
2143 return output_bvb (operands, 0, insn, 0);
2145 [(set_attr "type" "cbranch")
2146 (set (attr "length")
2147 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (const_int MAX_12BIT_OFFSET))
2150 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_17BIT_OFFSET))
2153 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2155 (eq (symbol_ref "flag_pic") (const_int 0))
2162 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2164 (match_operand:SI 1 "register_operand" "q"))
2167 (label_ref (match_operand 2 "" ""))))]
2171 return output_bvb (operands, 1, insn, 0);
2173 [(set_attr "type" "cbranch")
2174 (set (attr "length")
2175 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2176 (const_int MAX_12BIT_OFFSET))
2178 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2179 (const_int MAX_17BIT_OFFSET))
2181 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2183 (eq (symbol_ref "flag_pic") (const_int 0))
2190 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2192 (match_operand:DI 1 "register_operand" "q"))
2195 (label_ref (match_operand 2 "" ""))))]
2199 return output_bvb (operands, 1, insn, 0);
2201 [(set_attr "type" "cbranch")
2202 (set (attr "length")
2203 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2204 (const_int MAX_12BIT_OFFSET))
2206 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2207 (const_int MAX_17BIT_OFFSET))
2209 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2211 (eq (symbol_ref "flag_pic") (const_int 0))
2218 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2220 (match_operand:SI 1 "register_operand" "q"))
2222 (label_ref (match_operand 2 "" ""))
2227 return output_bvb (operands, 0, insn, 1);
2229 [(set_attr "type" "cbranch")
2230 (set (attr "length")
2231 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2232 (const_int MAX_12BIT_OFFSET))
2234 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2235 (const_int MAX_17BIT_OFFSET))
2237 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2239 (eq (symbol_ref "flag_pic") (const_int 0))
2246 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2248 (match_operand:DI 1 "register_operand" "q"))
2250 (label_ref (match_operand 2 "" ""))
2255 return output_bvb (operands, 0, insn, 1);
2257 [(set_attr "type" "cbranch")
2258 (set (attr "length")
2259 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2260 (const_int MAX_12BIT_OFFSET))
2262 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2263 (const_int MAX_17BIT_OFFSET))
2265 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2267 (eq (symbol_ref "flag_pic") (const_int 0))
2274 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2276 (match_operand:SI 1 "register_operand" "q"))
2279 (label_ref (match_operand 2 "" ""))))]
2283 return output_bvb (operands, 1, insn, 1);
2285 [(set_attr "type" "cbranch")
2286 (set (attr "length")
2287 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2288 (const_int MAX_12BIT_OFFSET))
2290 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2291 (const_int MAX_17BIT_OFFSET))
2293 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2295 (eq (symbol_ref "flag_pic") (const_int 0))
2302 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2304 (match_operand:DI 1 "register_operand" "q"))
2307 (label_ref (match_operand 2 "" ""))))]
2311 return output_bvb (operands, 1, insn, 1);
2313 [(set_attr "type" "cbranch")
2314 (set (attr "length")
2315 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2316 (const_int MAX_12BIT_OFFSET))
2318 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2319 (const_int MAX_17BIT_OFFSET))
2321 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2323 (eq (symbol_ref "flag_pic") (const_int 0))
2327 ;; Floating point branches
2329 ;; ??? Nullification is handled differently from other branches.
2330 ;; If nullification is specified, the delay slot is nullified on any
2331 ;; taken branch regardless of branch direction.
2333 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2334 (label_ref (match_operand 0 "" ""))
2336 "!TARGET_SOFT_FLOAT"
2339 int length = get_attr_length (insn);
2341 int nullify, xdelay;
2344 return \"ftest\;b%* %l0\";
2346 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2350 xoperands[0] = GEN_INT (length - 8);
2356 xoperands[0] = GEN_INT (length - 4);
2360 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2362 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2363 return output_lbranch (operands[0], insn, xdelay);
2365 [(set_attr "type" "fbranch")
2366 (set (attr "length")
2367 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2368 (const_int MAX_17BIT_OFFSET))
2370 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2372 (eq (symbol_ref "flag_pic") (const_int 0))
2377 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2379 (label_ref (match_operand 0 "" ""))))]
2380 "!TARGET_SOFT_FLOAT"
2383 int length = get_attr_length (insn);
2385 int nullify, xdelay;
2388 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2390 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2394 xoperands[0] = GEN_INT (length - 4);
2400 xoperands[0] = GEN_INT (length);
2404 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2406 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2407 return output_lbranch (operands[0], insn, xdelay);
2409 [(set_attr "type" "fbranch")
2410 (set (attr "length")
2411 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2412 (const_int MAX_17BIT_OFFSET))
2414 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2416 (eq (symbol_ref "flag_pic") (const_int 0))
2420 ;; Move instructions
2422 (define_expand "movsi"
2423 [(set (match_operand:SI 0 "general_operand" "")
2424 (match_operand:SI 1 "general_operand" ""))]
2428 if (emit_move_sequence (operands, SImode, 0))
2432 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2433 (define_expand "reload_insi_r1"
2434 [(set (match_operand:SI 0 "register_operand" "=Z")
2435 (match_operand:SI 1 "non_hard_reg_operand" ""))
2436 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2440 if (emit_move_sequence (operands, SImode, operands[2]))
2443 /* We don't want the clobber emitted, so handle this ourselves. */
2444 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2448 ;; Handle SImode input reloads requiring a general register as a
2449 ;; scratch register.
2450 (define_expand "reload_insi"
2451 [(set (match_operand:SI 0 "register_operand" "=Z")
2452 (match_operand:SI 1 "non_hard_reg_operand" ""))
2453 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2457 if (emit_move_sequence (operands, SImode, operands[2]))
2460 /* We don't want the clobber emitted, so handle this ourselves. */
2461 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2465 ;; Handle SImode output reloads requiring a general register as a
2466 ;; scratch register.
2467 (define_expand "reload_outsi"
2468 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2469 (match_operand:SI 1 "register_operand" "Z"))
2470 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2474 if (emit_move_sequence (operands, SImode, operands[2]))
2477 /* We don't want the clobber emitted, so handle this ourselves. */
2478 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2483 [(set (match_operand:SI 0 "move_dest_operand"
2484 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,!r,!f")
2485 (match_operand:SI 1 "move_src_operand"
2486 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,!f,!r"))]
2487 "(register_operand (operands[0], SImode)
2488 || reg_or_0_operand (operands[1], SImode))
2489 && !TARGET_SOFT_FLOAT
2496 {zdepi|depwi,z} %Z1,%0
2500 {mfctl|mfctl,w} %%sar,%0
2504 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2505 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2506 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,move,move")
2507 (set_attr "pa_combine_type" "addmove")
2508 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2511 [(set (match_operand:SI 0 "move_dest_operand"
2512 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2513 (match_operand:SI 1 "move_src_operand"
2514 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2515 "(register_operand (operands[0], SImode)
2516 || reg_or_0_operand (operands[1], SImode))
2517 && !TARGET_SOFT_FLOAT
2524 {zdepi|depwi,z} %Z1,%0
2528 {mfctl|mfctl,w} %%sar,%0
2532 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2533 (set_attr "pa_combine_type" "addmove")
2534 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2537 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2538 (match_operand:SI 1 "register_operand" "f"))]
2540 && !TARGET_DISABLE_INDEXING
2541 && reload_completed"
2543 [(set_attr "type" "fpstore")
2544 (set_attr "pa_combine_type" "addmove")
2545 (set_attr "length" "4")])
2547 ; Rewrite RTL using an indexed store. This will allow the insn that
2548 ; computes the address to be deleted if the register it sets is dead.
2550 [(set (match_operand:SI 0 "register_operand" "")
2551 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2553 (match_operand:SI 2 "register_operand" "")))
2554 (set (mem:SI (match_dup 0))
2555 (match_operand:SI 3 "register_operand" ""))]
2557 && !TARGET_DISABLE_INDEXING
2558 && REG_OK_FOR_BASE_P (operands[2])
2559 && FP_REGNO_P (REGNO (operands[3]))"
2560 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2562 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2567 [(set (match_operand:SI 0 "register_operand" "")
2568 (plus:SI (match_operand:SI 2 "register_operand" "")
2569 (mult:SI (match_operand:SI 1 "register_operand" "")
2571 (set (mem:SI (match_dup 0))
2572 (match_operand:SI 3 "register_operand" ""))]
2574 && !TARGET_DISABLE_INDEXING
2575 && REG_OK_FOR_BASE_P (operands[2])
2576 && FP_REGNO_P (REGNO (operands[3]))"
2577 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2579 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2584 [(set (match_operand:DI 0 "register_operand" "")
2585 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2587 (match_operand:DI 2 "register_operand" "")))
2588 (set (mem:SI (match_dup 0))
2589 (match_operand:SI 3 "register_operand" ""))]
2591 && !TARGET_DISABLE_INDEXING
2593 && REG_OK_FOR_BASE_P (operands[2])
2594 && FP_REGNO_P (REGNO (operands[3]))"
2595 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2597 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2602 [(set (match_operand:DI 0 "register_operand" "")
2603 (plus:DI (match_operand:DI 2 "register_operand" "")
2604 (mult:DI (match_operand:DI 1 "register_operand" "")
2606 (set (mem:SI (match_dup 0))
2607 (match_operand:SI 3 "register_operand" ""))]
2609 && !TARGET_DISABLE_INDEXING
2611 && REG_OK_FOR_BASE_P (operands[2])
2612 && FP_REGNO_P (REGNO (operands[3]))"
2613 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2615 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2620 [(set (match_operand:SI 0 "register_operand" "")
2621 (plus:SI (match_operand:SI 1 "register_operand" "")
2622 (match_operand:SI 2 "register_operand" "")))
2623 (set (mem:SI (match_dup 0))
2624 (match_operand:SI 3 "register_operand" ""))]
2626 && !TARGET_DISABLE_INDEXING
2627 && TARGET_NO_SPACE_REGS
2628 && REG_OK_FOR_INDEX_P (operands[1])
2629 && REG_OK_FOR_BASE_P (operands[2])
2630 && FP_REGNO_P (REGNO (operands[3]))"
2631 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2633 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2637 [(set (match_operand:SI 0 "register_operand" "")
2638 (plus:SI (match_operand:SI 1 "register_operand" "")
2639 (match_operand:SI 2 "register_operand" "")))
2640 (set (mem:SI (match_dup 0))
2641 (match_operand:SI 3 "register_operand" ""))]
2643 && !TARGET_DISABLE_INDEXING
2644 && TARGET_NO_SPACE_REGS
2645 && REG_OK_FOR_BASE_P (operands[1])
2646 && REG_OK_FOR_INDEX_P (operands[2])
2647 && FP_REGNO_P (REGNO (operands[3]))"
2648 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2650 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (plus:DI (match_operand:DI 1 "register_operand" "")
2656 (match_operand:DI 2 "register_operand" "")))
2657 (set (mem:SI (match_dup 0))
2658 (match_operand:SI 3 "register_operand" ""))]
2660 && !TARGET_DISABLE_INDEXING
2662 && TARGET_NO_SPACE_REGS
2663 && REG_OK_FOR_INDEX_P (operands[1])
2664 && REG_OK_FOR_BASE_P (operands[2])
2665 && FP_REGNO_P (REGNO (operands[3]))"
2666 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2668 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2672 [(set (match_operand:DI 0 "register_operand" "")
2673 (plus:DI (match_operand:DI 1 "register_operand" "")
2674 (match_operand:DI 2 "register_operand" "")))
2675 (set (mem:SI (match_dup 0))
2676 (match_operand:SI 3 "register_operand" ""))]
2678 && !TARGET_DISABLE_INDEXING
2680 && TARGET_NO_SPACE_REGS
2681 && REG_OK_FOR_BASE_P (operands[1])
2682 && REG_OK_FOR_INDEX_P (operands[2])
2683 && FP_REGNO_P (REGNO (operands[3]))"
2684 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2686 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2690 [(set (match_operand:SI 0 "move_dest_operand"
2691 "=r,r,r,r,r,r,Q,!*q,!r")
2692 (match_operand:SI 1 "move_src_operand"
2693 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2694 "(register_operand (operands[0], SImode)
2695 || reg_or_0_operand (operands[1], SImode))
2696 && TARGET_SOFT_FLOAT"
2702 {zdepi|depwi,z} %Z1,%0
2706 {mfctl|mfctl,w} %%sar,%0"
2707 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2708 (set_attr "pa_combine_type" "addmove")
2709 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2711 ;; Load or store with base-register modification.
2713 [(set (match_operand:SI 0 "register_operand" "=r")
2714 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2715 (match_operand:DI 2 "int5_operand" "L"))))
2717 (plus:DI (match_dup 1) (match_dup 2)))]
2720 [(set_attr "type" "load")
2721 (set_attr "length" "4")])
2723 ; And a zero extended variant.
2725 [(set (match_operand:DI 0 "register_operand" "=r")
2726 (zero_extend:DI (mem:SI
2728 (match_operand:DI 1 "register_operand" "+r")
2729 (match_operand:DI 2 "int5_operand" "L")))))
2731 (plus:DI (match_dup 1) (match_dup 2)))]
2734 [(set_attr "type" "load")
2735 (set_attr "length" "4")])
2737 (define_expand "pre_load"
2738 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2739 (mem (plus (match_operand 1 "register_operand" "")
2740 (match_operand 2 "pre_cint_operand" ""))))
2742 (plus (match_dup 1) (match_dup 2)))])]
2748 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2751 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2755 (define_insn "pre_ldw"
2756 [(set (match_operand:SI 0 "register_operand" "=r")
2757 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2758 (match_operand:SI 2 "pre_cint_operand" ""))))
2760 (plus:SI (match_dup 1) (match_dup 2)))]
2764 if (INTVAL (operands[2]) < 0)
2765 return \"{ldwm|ldw,mb} %2(%1),%0\";
2766 return \"{ldws|ldw},mb %2(%1),%0\";
2768 [(set_attr "type" "load")
2769 (set_attr "length" "4")])
2771 (define_insn "pre_ldd"
2772 [(set (match_operand:DI 0 "register_operand" "=r")
2773 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2774 (match_operand:DI 2 "pre_cint_operand" ""))))
2776 (plus:DI (match_dup 1) (match_dup 2)))]
2779 [(set_attr "type" "load")
2780 (set_attr "length" "4")])
2783 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2784 (match_operand:SI 1 "pre_cint_operand" "")))
2785 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2787 (plus:SI (match_dup 0) (match_dup 1)))]
2791 if (INTVAL (operands[1]) < 0)
2792 return \"{stwm|stw,mb} %r2,%1(%0)\";
2793 return \"{stws|stw},mb %r2,%1(%0)\";
2795 [(set_attr "type" "store")
2796 (set_attr "length" "4")])
2799 [(set (match_operand:SI 0 "register_operand" "=r")
2800 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2802 (plus:SI (match_dup 1)
2803 (match_operand:SI 2 "post_cint_operand" "")))]
2807 if (INTVAL (operands[2]) > 0)
2808 return \"{ldwm|ldw,ma} %2(%1),%0\";
2809 return \"{ldws|ldw},ma %2(%1),%0\";
2811 [(set_attr "type" "load")
2812 (set_attr "length" "4")])
2814 (define_expand "post_store"
2815 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2816 (match_operand 1 "reg_or_0_operand" ""))
2819 (match_operand 2 "post_cint_operand" "")))])]
2825 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2828 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2832 (define_insn "post_stw"
2833 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2834 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2836 (plus:SI (match_dup 0)
2837 (match_operand:SI 2 "post_cint_operand" "")))]
2841 if (INTVAL (operands[2]) > 0)
2842 return \"{stwm|stw,ma} %r1,%2(%0)\";
2843 return \"{stws|stw},ma %r1,%2(%0)\";
2845 [(set_attr "type" "store")
2846 (set_attr "length" "4")])
2848 (define_insn "post_std"
2849 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2850 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2852 (plus:DI (match_dup 0)
2853 (match_operand:DI 2 "post_cint_operand" "")))]
2856 [(set_attr "type" "store")
2857 (set_attr "length" "4")])
2859 ;; For loading the address of a label while generating PIC code.
2860 ;; Note since this pattern can be created at reload time (via movsi), all
2861 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2863 [(set (match_operand 0 "pmode_register_operand" "=a")
2864 (match_operand 1 "pic_label_operand" ""))]
2870 xoperands[0] = operands[0];
2871 xoperands[1] = operands[1];
2872 xoperands[2] = gen_label_rtx ();
2874 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2875 CODE_LABEL_NUMBER (xoperands[2]));
2876 output_asm_insn (\"mfia %0\", xoperands);
2878 /* If we're trying to load the address of a label that happens to be
2879 close, then we can use a shorter sequence. */
2880 if (GET_CODE (operands[1]) == LABEL_REF
2881 && !LABEL_REF_NONLOCAL_P (operands[1])
2882 && INSN_ADDRESSES_SET_P ()
2883 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2884 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2885 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2888 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2889 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2893 [(set_attr "type" "multi")
2894 (set_attr "length" "12")]) ; 8 or 12
2897 [(set (match_operand 0 "pmode_register_operand" "=a")
2898 (match_operand 1 "pic_label_operand" ""))]
2904 xoperands[0] = operands[0];
2905 xoperands[1] = operands[1];
2906 xoperands[2] = gen_label_rtx ();
2908 output_asm_insn (\"bl .+8,%0\", xoperands);
2909 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2910 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2911 CODE_LABEL_NUMBER (xoperands[2]));
2913 /* If we're trying to load the address of a label that happens to be
2914 close, then we can use a shorter sequence. */
2915 if (GET_CODE (operands[1]) == LABEL_REF
2916 && !LABEL_REF_NONLOCAL_P (operands[1])
2917 && INSN_ADDRESSES_SET_P ()
2918 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2919 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2920 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2923 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2924 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2928 [(set_attr "type" "multi")
2929 (set_attr "length" "16")]) ; 12 or 16
2932 [(set (match_operand:SI 0 "register_operand" "=a")
2933 (plus:SI (match_operand:SI 1 "register_operand" "r")
2934 (high:SI (match_operand 2 "" ""))))]
2935 "symbolic_operand (operands[2], Pmode)
2936 && ! function_label_operand (operands[2], Pmode)
2939 [(set_attr "type" "binary")
2940 (set_attr "length" "4")])
2943 [(set (match_operand:DI 0 "register_operand" "=a")
2944 (plus:DI (match_operand:DI 1 "register_operand" "r")
2945 (high:DI (match_operand 2 "" ""))))]
2946 "symbolic_operand (operands[2], Pmode)
2947 && ! function_label_operand (operands[2], Pmode)
2951 [(set_attr "type" "binary")
2952 (set_attr "length" "4")])
2954 ;; Always use addil rather than ldil;add sequences. This allows the
2955 ;; HP linker to eliminate the dp relocation if the symbolic operand
2956 ;; lives in the TEXT space.
2958 [(set (match_operand:SI 0 "register_operand" "=a")
2959 (high:SI (match_operand 1 "" "")))]
2960 "symbolic_operand (operands[1], Pmode)
2961 && ! function_label_operand (operands[1], Pmode)
2962 && ! read_only_operand (operands[1], Pmode)
2966 if (TARGET_LONG_LOAD_STORE)
2967 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2969 return \"addil LR'%H1,%%r27\";
2971 [(set_attr "type" "binary")
2972 (set (attr "length")
2973 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2978 ;; This is for use in the prologue/epilogue code. We need it
2979 ;; to add large constants to a stack pointer or frame pointer.
2980 ;; Because of the additional %r1 pressure, we probably do not
2981 ;; want to use this in general code, so make it available
2982 ;; only after reload.
2984 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2985 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2986 (high:SI (match_operand 2 "const_int_operand" ""))))]
2990 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2991 [(set_attr "type" "binary,binary")
2992 (set_attr "length" "4,8")])
2995 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2996 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2997 (high:DI (match_operand 2 "const_int_operand" ""))))]
2998 "reload_completed && TARGET_64BIT"
3001 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3002 [(set_attr "type" "binary,binary")
3003 (set_attr "length" "4,8")])
3006 [(set (match_operand:SI 0 "register_operand" "=r")
3007 (high:SI (match_operand 1 "" "")))]
3008 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3009 && !is_function_label_plus_const (operands[1])"
3012 if (symbolic_operand (operands[1], Pmode))
3013 return \"ldil LR'%H1,%0\";
3015 return \"ldil L'%G1,%0\";
3017 [(set_attr "type" "move")
3018 (set_attr "length" "4")])
3021 [(set (match_operand:DI 0 "register_operand" "=r")
3022 (high:DI (match_operand 1 "const_int_operand" "")))]
3025 [(set_attr "type" "move")
3026 (set_attr "length" "4")])
3029 [(set (match_operand:DI 0 "register_operand" "=r")
3030 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3031 (match_operand:DI 2 "const_int_operand" "i")))]
3034 [(set_attr "type" "move")
3035 (set_attr "length" "4")])
3038 [(set (match_operand:SI 0 "register_operand" "=r")
3039 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3040 (match_operand:SI 2 "immediate_operand" "i")))]
3041 "!is_function_label_plus_const (operands[2])"
3044 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3046 if (symbolic_operand (operands[2], Pmode))
3047 return \"ldo RR'%G2(%1),%0\";
3049 return \"ldo R'%G2(%1),%0\";
3051 [(set_attr "type" "move")
3052 (set_attr "length" "4")])
3054 ;; Now that a symbolic_address plus a constant is broken up early
3055 ;; in the compilation phase (for better CSE) we need a special
3056 ;; combiner pattern to load the symbolic address plus the constant
3057 ;; in only 2 instructions. (For cases where the symbolic address
3058 ;; was not a common subexpression.)
3060 [(set (match_operand:SI 0 "register_operand" "")
3061 (match_operand:SI 1 "symbolic_operand" ""))
3062 (clobber (match_operand:SI 2 "register_operand" ""))]
3063 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3064 [(set (match_dup 2) (high:SI (match_dup 1)))
3065 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3068 ;; hppa_legitimize_address goes to a great deal of trouble to
3069 ;; create addresses which use indexing. In some cases, this
3070 ;; is a lose because there isn't any store instructions which
3071 ;; allow indexed addresses (with integer register source).
3073 ;; These define_splits try to turn a 3 insn store into
3074 ;; a 2 insn store with some creative RTL rewriting.
3076 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3077 (match_operand:SI 1 "shadd_operand" ""))
3078 (plus:SI (match_operand:SI 2 "register_operand" "")
3079 (match_operand:SI 3 "const_int_operand" ""))))
3080 (match_operand:SI 4 "register_operand" ""))
3081 (clobber (match_operand:SI 5 "register_operand" ""))]
3083 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3085 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3089 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3090 (match_operand:SI 1 "shadd_operand" ""))
3091 (plus:SI (match_operand:SI 2 "register_operand" "")
3092 (match_operand:SI 3 "const_int_operand" ""))))
3093 (match_operand:HI 4 "register_operand" ""))
3094 (clobber (match_operand:SI 5 "register_operand" ""))]
3096 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3098 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3102 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3103 (match_operand:SI 1 "shadd_operand" ""))
3104 (plus:SI (match_operand:SI 2 "register_operand" "")
3105 (match_operand:SI 3 "const_int_operand" ""))))
3106 (match_operand:QI 4 "register_operand" ""))
3107 (clobber (match_operand:SI 5 "register_operand" ""))]
3109 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3111 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3114 (define_expand "movhi"
3115 [(set (match_operand:HI 0 "general_operand" "")
3116 (match_operand:HI 1 "general_operand" ""))]
3120 if (emit_move_sequence (operands, HImode, 0))
3125 [(set (match_operand:HI 0 "move_dest_operand"
3126 "=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
3127 (match_operand:HI 1 "move_src_operand"
3128 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
3129 "(register_operand (operands[0], HImode)
3130 || reg_or_0_operand (operands[1], HImode))
3131 && !TARGET_SOFT_FLOAT
3137 {zdepi|depwi,z} %Z1,%0
3141 {mfctl|mfctl,w} %sar,%0
3143 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3144 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3145 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3146 (set_attr "pa_combine_type" "addmove")
3147 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3150 [(set (match_operand:HI 0 "move_dest_operand"
3151 "=r,r,r,r,r,Q,!*q,!r,!*f")
3152 (match_operand:HI 1 "move_src_operand"
3153 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3154 "(register_operand (operands[0], HImode)
3155 || reg_or_0_operand (operands[1], HImode))
3156 && !TARGET_SOFT_FLOAT
3162 {zdepi|depwi,z} %Z1,%0
3166 {mfctl|mfctl,w} %sar,%0
3168 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3169 (set_attr "pa_combine_type" "addmove")
3170 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3173 [(set (match_operand:HI 0 "move_dest_operand"
3174 "=r,r,r,r,r,Q,!*q,!r")
3175 (match_operand:HI 1 "move_src_operand"
3176 "r,J,N,K,RQ,rM,!rM,!*q"))]
3177 "(register_operand (operands[0], HImode)
3178 || reg_or_0_operand (operands[1], HImode))
3179 && TARGET_SOFT_FLOAT"
3184 {zdepi|depwi,z} %Z1,%0
3188 {mfctl|mfctl,w} %sar,%0"
3189 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3190 (set_attr "pa_combine_type" "addmove")
3191 (set_attr "length" "4,4,4,4,4,4,4,4")])
3194 [(set (match_operand:HI 0 "register_operand" "=r")
3195 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3196 (match_operand:SI 2 "int5_operand" "L"))))
3198 (plus:SI (match_dup 1) (match_dup 2)))]
3200 "{ldhs|ldh},mb %2(%1),%0"
3201 [(set_attr "type" "load")
3202 (set_attr "length" "4")])
3205 [(set (match_operand:HI 0 "register_operand" "=r")
3206 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3207 (match_operand:DI 2 "int5_operand" "L"))))
3209 (plus:DI (match_dup 1) (match_dup 2)))]
3212 [(set_attr "type" "load")
3213 (set_attr "length" "4")])
3215 ; And a zero extended variant.
3217 [(set (match_operand:DI 0 "register_operand" "=r")
3218 (zero_extend:DI (mem:HI
3220 (match_operand:DI 1 "register_operand" "+r")
3221 (match_operand:DI 2 "int5_operand" "L")))))
3223 (plus:DI (match_dup 1) (match_dup 2)))]
3226 [(set_attr "type" "load")
3227 (set_attr "length" "4")])
3230 [(set (match_operand:SI 0 "register_operand" "=r")
3231 (zero_extend:SI (mem:HI
3233 (match_operand:SI 1 "register_operand" "+r")
3234 (match_operand:SI 2 "int5_operand" "L")))))
3236 (plus:SI (match_dup 1) (match_dup 2)))]
3238 "{ldhs|ldh},mb %2(%1),%0"
3239 [(set_attr "type" "load")
3240 (set_attr "length" "4")])
3243 [(set (match_operand:SI 0 "register_operand" "=r")
3244 (zero_extend:SI (mem:HI
3246 (match_operand:DI 1 "register_operand" "+r")
3247 (match_operand:DI 2 "int5_operand" "L")))))
3249 (plus:DI (match_dup 1) (match_dup 2)))]
3252 [(set_attr "type" "load")
3253 (set_attr "length" "4")])
3256 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3257 (match_operand:SI 1 "int5_operand" "L")))
3258 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3260 (plus:SI (match_dup 0) (match_dup 1)))]
3262 "{sths|sth},mb %r2,%1(%0)"
3263 [(set_attr "type" "store")
3264 (set_attr "length" "4")])
3267 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3268 (match_operand:DI 1 "int5_operand" "L")))
3269 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3271 (plus:DI (match_dup 0) (match_dup 1)))]
3274 [(set_attr "type" "store")
3275 (set_attr "length" "4")])
3278 [(set (match_operand:HI 0 "register_operand" "=r")
3279 (plus:HI (match_operand:HI 1 "register_operand" "r")
3280 (match_operand 2 "const_int_operand" "J")))]
3283 [(set_attr "type" "binary")
3284 (set_attr "pa_combine_type" "addmove")
3285 (set_attr "length" "4")])
3287 (define_expand "movqi"
3288 [(set (match_operand:QI 0 "general_operand" "")
3289 (match_operand:QI 1 "general_operand" ""))]
3293 if (emit_move_sequence (operands, QImode, 0))
3298 [(set (match_operand:QI 0 "move_dest_operand"
3299 "=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
3300 (match_operand:QI 1 "move_src_operand"
3301 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
3302 "(register_operand (operands[0], QImode)
3303 || reg_or_0_operand (operands[1], QImode))
3304 && !TARGET_SOFT_FLOAT
3310 {zdepi|depwi,z} %Z1,%0
3314 {mfctl|mfctl,w} %%sar,%0
3316 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3317 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3318 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3319 (set_attr "pa_combine_type" "addmove")
3320 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3323 [(set (match_operand:QI 0 "move_dest_operand"
3324 "=r,r,r,r,r,Q,!*q,!r,!*f")
3325 (match_operand:QI 1 "move_src_operand"
3326 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3327 "(register_operand (operands[0], QImode)
3328 || reg_or_0_operand (operands[1], QImode))
3329 && !TARGET_SOFT_FLOAT
3335 {zdepi|depwi,z} %Z1,%0
3339 {mfctl|mfctl,w} %%sar,%0
3341 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3342 (set_attr "pa_combine_type" "addmove")
3343 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3346 [(set (match_operand:QI 0 "move_dest_operand"
3347 "=r,r,r,r,r,Q,!*q,!r")
3348 (match_operand:QI 1 "move_src_operand"
3349 "r,J,N,K,RQ,rM,!rM,!*q"))]
3350 "(register_operand (operands[0], QImode)
3351 || reg_or_0_operand (operands[1], QImode))
3352 && TARGET_SOFT_FLOAT"
3357 {zdepi|depwi,z} %Z1,%0
3361 {mfctl|mfctl,w} %%sar,%0"
3362 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3363 (set_attr "pa_combine_type" "addmove")
3364 (set_attr "length" "4,4,4,4,4,4,4,4")])
3367 [(set (match_operand:QI 0 "register_operand" "=r")
3368 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3369 (match_operand:SI 2 "int5_operand" "L"))))
3370 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3372 "{ldbs|ldb},mb %2(%1),%0"
3373 [(set_attr "type" "load")
3374 (set_attr "length" "4")])
3377 [(set (match_operand:QI 0 "register_operand" "=r")
3378 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3379 (match_operand:DI 2 "int5_operand" "L"))))
3380 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3383 [(set_attr "type" "load")
3384 (set_attr "length" "4")])
3386 ; Now the same thing with zero extensions.
3388 [(set (match_operand:DI 0 "register_operand" "=r")
3389 (zero_extend:DI (mem:QI (plus:DI
3390 (match_operand:DI 1 "register_operand" "+r")
3391 (match_operand:DI 2 "int5_operand" "L")))))
3392 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3395 [(set_attr "type" "load")
3396 (set_attr "length" "4")])
3399 [(set (match_operand:SI 0 "register_operand" "=r")
3400 (zero_extend:SI (mem:QI (plus:SI
3401 (match_operand:SI 1 "register_operand" "+r")
3402 (match_operand:SI 2 "int5_operand" "L")))))
3403 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3405 "{ldbs|ldb},mb %2(%1),%0"
3406 [(set_attr "type" "load")
3407 (set_attr "length" "4")])
3410 [(set (match_operand:SI 0 "register_operand" "=r")
3411 (zero_extend:SI (mem:QI (plus:DI
3412 (match_operand:DI 1 "register_operand" "+r")
3413 (match_operand:DI 2 "int5_operand" "L")))))
3414 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3417 [(set_attr "type" "load")
3418 (set_attr "length" "4")])
3421 [(set (match_operand:HI 0 "register_operand" "=r")
3422 (zero_extend:HI (mem:QI (plus:SI
3423 (match_operand:SI 1 "register_operand" "+r")
3424 (match_operand:SI 2 "int5_operand" "L")))))
3425 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3427 "{ldbs|ldb},mb %2(%1),%0"
3428 [(set_attr "type" "load")
3429 (set_attr "length" "4")])
3432 [(set (match_operand:HI 0 "register_operand" "=r")
3433 (zero_extend:HI (mem:QI (plus:DI
3434 (match_operand:DI 1 "register_operand" "+r")
3435 (match_operand:DI 2 "int5_operand" "L")))))
3436 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3439 [(set_attr "type" "load")
3440 (set_attr "length" "4")])
3443 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3444 (match_operand:SI 1 "int5_operand" "L")))
3445 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3447 (plus:SI (match_dup 0) (match_dup 1)))]
3449 "{stbs|stb},mb %r2,%1(%0)"
3450 [(set_attr "type" "store")
3451 (set_attr "length" "4")])
3454 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3455 (match_operand:DI 1 "int5_operand" "L")))
3456 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3458 (plus:DI (match_dup 0) (match_dup 1)))]
3461 [(set_attr "type" "store")
3462 (set_attr "length" "4")])
3464 ;; The definition of this insn does not really explain what it does,
3465 ;; but it should suffice that anything generated as this insn will be
3466 ;; recognized as a movmemsi operation, and that it will not successfully
3467 ;; combine with anything.
3468 (define_expand "movmemsi"
3469 [(parallel [(set (match_operand:BLK 0 "" "")
3470 (match_operand:BLK 1 "" ""))
3471 (clobber (match_dup 4))
3472 (clobber (match_dup 5))
3473 (clobber (match_dup 6))
3474 (clobber (match_dup 7))
3475 (clobber (match_dup 8))
3476 (use (match_operand:SI 2 "arith_operand" ""))
3477 (use (match_operand:SI 3 "const_int_operand" ""))])]
3478 "!TARGET_64BIT && optimize > 0"
3483 /* HP provides very fast block move library routine for the PA;
3484 this routine includes:
3486 4x4 byte at a time block moves,
3487 1x4 byte at a time with alignment checked at runtime with
3488 attempts to align the source and destination as needed
3491 With that in mind, here's the heuristics to try and guess when
3492 the inlined block move will be better than the library block
3495 If the size isn't constant, then always use the library routines.
3497 If the size is large in respect to the known alignment, then use
3498 the library routines.
3500 If the size is small in respect to the known alignment, then open
3501 code the copy (since that will lead to better scheduling).
3503 Else use the block move pattern. */
3505 /* Undetermined size, use the library routine. */
3506 if (GET_CODE (operands[2]) != CONST_INT)
3509 size = INTVAL (operands[2]);
3510 align = INTVAL (operands[3]);
3511 align = align > 4 ? 4 : align;
3513 /* If size/alignment is large, then use the library routines. */
3514 if (size / align > 16)
3517 /* This does happen, but not often enough to worry much about. */
3518 if (size / align < MOVE_RATIO)
3521 /* Fall through means we're going to use our block move pattern. */
3523 = replace_equiv_address (operands[0],
3524 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3526 = replace_equiv_address (operands[1],
3527 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3528 operands[4] = gen_reg_rtx (SImode);
3529 operands[5] = gen_reg_rtx (SImode);
3530 operands[6] = gen_reg_rtx (SImode);
3531 operands[7] = gen_reg_rtx (SImode);
3532 operands[8] = gen_reg_rtx (SImode);
3535 ;; The operand constraints are written like this to support both compile-time
3536 ;; and run-time determined byte counts. The expander and output_block_move
3537 ;; only support compile-time determined counts at this time.
3539 ;; If the count is run-time determined, the register with the byte count
3540 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3542 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3543 ;; broke this semantic for pseudo registers. We can't use match_scratch
3544 ;; as this requires two registers in the class R1_REGS when the MEMs for
3545 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3546 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3547 ;; respectively. We then split or peephole optimize after reload.
3548 (define_insn "movmemsi_prereload"
3549 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3550 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3551 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3552 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3553 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3554 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3555 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3556 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3557 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3560 [(set_attr "type" "multi,multi")])
3563 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3564 (match_operand:BLK 1 "memory_operand" ""))
3565 (clobber (match_operand:SI 2 "register_operand" ""))
3566 (clobber (match_operand:SI 3 "register_operand" ""))
3567 (clobber (match_operand:SI 6 "register_operand" ""))
3568 (clobber (match_operand:SI 7 "register_operand" ""))
3569 (clobber (match_operand:SI 8 "register_operand" ""))
3570 (use (match_operand:SI 4 "arith_operand" ""))
3571 (use (match_operand:SI 5 "const_int_operand" ""))])]
3572 "!TARGET_64BIT && reload_completed && !flag_peephole2
3573 && GET_CODE (operands[0]) == MEM
3574 && register_operand (XEXP (operands[0], 0), SImode)
3575 && GET_CODE (operands[1]) == MEM
3576 && register_operand (XEXP (operands[1], 0), SImode)"
3577 [(set (match_dup 7) (match_dup 9))
3578 (set (match_dup 8) (match_dup 10))
3579 (parallel [(set (match_dup 0) (match_dup 1))
3580 (clobber (match_dup 2))
3581 (clobber (match_dup 3))
3582 (clobber (match_dup 6))
3583 (clobber (match_dup 7))
3584 (clobber (match_dup 8))
3590 operands[9] = XEXP (operands[0], 0);
3591 operands[10] = XEXP (operands[1], 0);
3592 operands[0] = replace_equiv_address (operands[0], operands[7]);
3593 operands[1] = replace_equiv_address (operands[1], operands[8]);
3597 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3598 (match_operand:BLK 1 "memory_operand" ""))
3599 (clobber (match_operand:SI 2 "register_operand" ""))
3600 (clobber (match_operand:SI 3 "register_operand" ""))
3601 (clobber (match_operand:SI 6 "register_operand" ""))
3602 (clobber (match_operand:SI 7 "register_operand" ""))
3603 (clobber (match_operand:SI 8 "register_operand" ""))
3604 (use (match_operand:SI 4 "arith_operand" ""))
3605 (use (match_operand:SI 5 "const_int_operand" ""))])]
3607 && GET_CODE (operands[0]) == MEM
3608 && register_operand (XEXP (operands[0], 0), SImode)
3609 && GET_CODE (operands[1]) == MEM
3610 && register_operand (XEXP (operands[1], 0), SImode)"
3611 [(parallel [(set (match_dup 0) (match_dup 1))
3612 (clobber (match_dup 2))
3613 (clobber (match_dup 3))
3614 (clobber (match_dup 6))
3615 (clobber (match_dup 7))
3616 (clobber (match_dup 8))
3622 rtx addr = XEXP (operands[0], 0);
3623 if (dead_or_set_p (curr_insn, addr))
3627 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3628 operands[0] = replace_equiv_address (operands[0], operands[7]);
3631 addr = XEXP (operands[1], 0);
3632 if (dead_or_set_p (curr_insn, addr))
3636 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3637 operands[1] = replace_equiv_address (operands[1], operands[8]);
3641 (define_insn "movmemsi_postreload"
3642 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3643 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3644 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3645 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3646 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3647 (clobber (match_dup 0))
3648 (clobber (match_dup 1))
3649 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3650 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3652 "!TARGET_64BIT && reload_completed"
3653 "* return output_block_move (operands, !which_alternative);"
3654 [(set_attr "type" "multi,multi")])
3656 (define_expand "movmemdi"
3657 [(parallel [(set (match_operand:BLK 0 "" "")
3658 (match_operand:BLK 1 "" ""))
3659 (clobber (match_dup 4))
3660 (clobber (match_dup 5))
3661 (clobber (match_dup 6))
3662 (clobber (match_dup 7))
3663 (clobber (match_dup 8))
3664 (use (match_operand:DI 2 "arith_operand" ""))
3665 (use (match_operand:DI 3 "const_int_operand" ""))])]
3666 "TARGET_64BIT && optimize > 0"
3671 /* HP provides very fast block move library routine for the PA;
3672 this routine includes:
3674 4x4 byte at a time block moves,
3675 1x4 byte at a time with alignment checked at runtime with
3676 attempts to align the source and destination as needed
3679 With that in mind, here's the heuristics to try and guess when
3680 the inlined block move will be better than the library block
3683 If the size isn't constant, then always use the library routines.
3685 If the size is large in respect to the known alignment, then use
3686 the library routines.
3688 If the size is small in respect to the known alignment, then open
3689 code the copy (since that will lead to better scheduling).
3691 Else use the block move pattern. */
3693 /* Undetermined size, use the library routine. */
3694 if (GET_CODE (operands[2]) != CONST_INT)
3697 size = INTVAL (operands[2]);
3698 align = INTVAL (operands[3]);
3699 align = align > 8 ? 8 : align;
3701 /* If size/alignment is large, then use the library routines. */
3702 if (size / align > 16)
3705 /* This does happen, but not often enough to worry much about. */
3706 if (size / align < MOVE_RATIO)
3709 /* Fall through means we're going to use our block move pattern. */
3711 = replace_equiv_address (operands[0],
3712 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3714 = replace_equiv_address (operands[1],
3715 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3716 operands[4] = gen_reg_rtx (DImode);
3717 operands[5] = gen_reg_rtx (DImode);
3718 operands[6] = gen_reg_rtx (DImode);
3719 operands[7] = gen_reg_rtx (DImode);
3720 operands[8] = gen_reg_rtx (DImode);
3723 ;; The operand constraints are written like this to support both compile-time
3724 ;; and run-time determined byte counts. The expander and output_block_move
3725 ;; only support compile-time determined counts at this time.
3727 ;; If the count is run-time determined, the register with the byte count
3728 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3730 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3731 ;; broke this semantic for pseudo registers. We can't use match_scratch
3732 ;; as this requires two registers in the class R1_REGS when the MEMs for
3733 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3734 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3735 ;; respectively. We then split or peephole optimize after reload.
3736 (define_insn "movmemdi_prereload"
3737 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3738 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3739 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3740 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3741 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3742 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3743 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3744 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3745 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3748 [(set_attr "type" "multi,multi")])
3751 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3752 (match_operand:BLK 1 "memory_operand" ""))
3753 (clobber (match_operand:DI 2 "register_operand" ""))
3754 (clobber (match_operand:DI 3 "register_operand" ""))
3755 (clobber (match_operand:DI 6 "register_operand" ""))
3756 (clobber (match_operand:DI 7 "register_operand" ""))
3757 (clobber (match_operand:DI 8 "register_operand" ""))
3758 (use (match_operand:DI 4 "arith_operand" ""))
3759 (use (match_operand:DI 5 "const_int_operand" ""))])]
3760 "TARGET_64BIT && reload_completed && !flag_peephole2
3761 && GET_CODE (operands[0]) == MEM
3762 && register_operand (XEXP (operands[0], 0), DImode)
3763 && GET_CODE (operands[1]) == MEM
3764 && register_operand (XEXP (operands[1], 0), DImode)"
3765 [(set (match_dup 7) (match_dup 9))
3766 (set (match_dup 8) (match_dup 10))
3767 (parallel [(set (match_dup 0) (match_dup 1))
3768 (clobber (match_dup 2))
3769 (clobber (match_dup 3))
3770 (clobber (match_dup 6))
3771 (clobber (match_dup 7))
3772 (clobber (match_dup 8))
3778 operands[9] = XEXP (operands[0], 0);
3779 operands[10] = XEXP (operands[1], 0);
3780 operands[0] = replace_equiv_address (operands[0], operands[7]);
3781 operands[1] = replace_equiv_address (operands[1], operands[8]);
3785 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3786 (match_operand:BLK 1 "memory_operand" ""))
3787 (clobber (match_operand:DI 2 "register_operand" ""))
3788 (clobber (match_operand:DI 3 "register_operand" ""))
3789 (clobber (match_operand:DI 6 "register_operand" ""))
3790 (clobber (match_operand:DI 7 "register_operand" ""))
3791 (clobber (match_operand:DI 8 "register_operand" ""))
3792 (use (match_operand:DI 4 "arith_operand" ""))
3793 (use (match_operand:DI 5 "const_int_operand" ""))])]
3795 && GET_CODE (operands[0]) == MEM
3796 && register_operand (XEXP (operands[0], 0), DImode)
3797 && GET_CODE (operands[1]) == MEM
3798 && register_operand (XEXP (operands[1], 0), DImode)"
3799 [(parallel [(set (match_dup 0) (match_dup 1))
3800 (clobber (match_dup 2))
3801 (clobber (match_dup 3))
3802 (clobber (match_dup 6))
3803 (clobber (match_dup 7))
3804 (clobber (match_dup 8))
3810 rtx addr = XEXP (operands[0], 0);
3811 if (dead_or_set_p (curr_insn, addr))
3815 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3816 operands[0] = replace_equiv_address (operands[0], operands[7]);
3819 addr = XEXP (operands[1], 0);
3820 if (dead_or_set_p (curr_insn, addr))
3824 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3825 operands[1] = replace_equiv_address (operands[1], operands[8]);
3829 (define_insn "movmemdi_postreload"
3830 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3831 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3832 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3833 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3834 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3835 (clobber (match_dup 0))
3836 (clobber (match_dup 1))
3837 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3838 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3840 "TARGET_64BIT && reload_completed"
3841 "* return output_block_move (operands, !which_alternative);"
3842 [(set_attr "type" "multi,multi")])
3844 (define_expand "setmemsi"
3845 [(parallel [(set (match_operand:BLK 0 "" "")
3846 (match_operand 2 "const_int_operand" ""))
3847 (clobber (match_dup 4))
3848 (clobber (match_dup 5))
3849 (use (match_operand:SI 1 "arith_operand" ""))
3850 (use (match_operand:SI 3 "const_int_operand" ""))])]
3851 "!TARGET_64BIT && optimize > 0"
3856 /* If value to set is not zero, use the library routine. */
3857 if (operands[2] != const0_rtx)
3860 /* Undetermined size, use the library routine. */
3861 if (GET_CODE (operands[1]) != CONST_INT)
3864 size = INTVAL (operands[1]);
3865 align = INTVAL (operands[3]);
3866 align = align > 4 ? 4 : align;
3868 /* If size/alignment is large, then use the library routines. */
3869 if (size / align > 16)
3872 /* This does happen, but not often enough to worry much about. */
3873 if (size / align < MOVE_RATIO)
3876 /* Fall through means we're going to use our block clear pattern. */
3878 = replace_equiv_address (operands[0],
3879 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3880 operands[4] = gen_reg_rtx (SImode);
3881 operands[5] = gen_reg_rtx (SImode);
3884 (define_insn "clrmemsi_prereload"
3885 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3887 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3888 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3889 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3890 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3893 [(set_attr "type" "multi,multi")])
3896 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3898 (clobber (match_operand:SI 1 "register_operand" ""))
3899 (clobber (match_operand:SI 4 "register_operand" ""))
3900 (use (match_operand:SI 2 "arith_operand" ""))
3901 (use (match_operand:SI 3 "const_int_operand" ""))])]
3902 "!TARGET_64BIT && reload_completed && !flag_peephole2
3903 && GET_CODE (operands[0]) == MEM
3904 && register_operand (XEXP (operands[0], 0), SImode)"
3905 [(set (match_dup 4) (match_dup 5))
3906 (parallel [(set (match_dup 0) (const_int 0))
3907 (clobber (match_dup 1))
3908 (clobber (match_dup 4))
3914 operands[5] = XEXP (operands[0], 0);
3915 operands[0] = replace_equiv_address (operands[0], operands[4]);
3919 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3921 (clobber (match_operand:SI 1 "register_operand" ""))
3922 (clobber (match_operand:SI 4 "register_operand" ""))
3923 (use (match_operand:SI 2 "arith_operand" ""))
3924 (use (match_operand:SI 3 "const_int_operand" ""))])]
3926 && GET_CODE (operands[0]) == MEM
3927 && register_operand (XEXP (operands[0], 0), SImode)"
3928 [(parallel [(set (match_dup 0) (const_int 0))
3929 (clobber (match_dup 1))
3930 (clobber (match_dup 4))
3936 rtx addr = XEXP (operands[0], 0);
3937 if (dead_or_set_p (curr_insn, addr))
3941 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3942 operands[0] = replace_equiv_address (operands[0], operands[4]);
3946 (define_insn "clrmemsi_postreload"
3947 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3949 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3950 (clobber (match_dup 0))
3951 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3952 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3954 "!TARGET_64BIT && reload_completed"
3955 "* return output_block_clear (operands, !which_alternative);"
3956 [(set_attr "type" "multi,multi")])
3958 (define_expand "setmemdi"
3959 [(parallel [(set (match_operand:BLK 0 "" "")
3960 (match_operand 2 "const_int_operand" ""))
3961 (clobber (match_dup 4))
3962 (clobber (match_dup 5))
3963 (use (match_operand:DI 1 "arith_operand" ""))
3964 (use (match_operand:DI 3 "const_int_operand" ""))])]
3965 "TARGET_64BIT && optimize > 0"
3970 /* If value to set is not zero, use the library routine. */
3971 if (operands[2] != const0_rtx)
3974 /* Undetermined size, use the library routine. */
3975 if (GET_CODE (operands[1]) != CONST_INT)
3978 size = INTVAL (operands[1]);
3979 align = INTVAL (operands[3]);
3980 align = align > 8 ? 8 : align;
3982 /* If size/alignment is large, then use the library routines. */
3983 if (size / align > 16)
3986 /* This does happen, but not often enough to worry much about. */
3987 if (size / align < MOVE_RATIO)
3990 /* Fall through means we're going to use our block clear pattern. */
3992 = replace_equiv_address (operands[0],
3993 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3994 operands[4] = gen_reg_rtx (DImode);
3995 operands[5] = gen_reg_rtx (DImode);
3998 (define_insn "clrmemdi_prereload"
3999 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
4001 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4002 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
4003 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4004 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
4007 [(set_attr "type" "multi,multi")])
4010 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4012 (clobber (match_operand:DI 1 "register_operand" ""))
4013 (clobber (match_operand:DI 4 "register_operand" ""))
4014 (use (match_operand:DI 2 "arith_operand" ""))
4015 (use (match_operand:DI 3 "const_int_operand" ""))])]
4016 "TARGET_64BIT && reload_completed && !flag_peephole2
4017 && GET_CODE (operands[0]) == MEM
4018 && register_operand (XEXP (operands[0], 0), DImode)"
4019 [(set (match_dup 4) (match_dup 5))
4020 (parallel [(set (match_dup 0) (const_int 0))
4021 (clobber (match_dup 1))
4022 (clobber (match_dup 4))
4028 operands[5] = XEXP (operands[0], 0);
4029 operands[0] = replace_equiv_address (operands[0], operands[4]);
4033 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4035 (clobber (match_operand:DI 1 "register_operand" ""))
4036 (clobber (match_operand:DI 4 "register_operand" ""))
4037 (use (match_operand:DI 2 "arith_operand" ""))
4038 (use (match_operand:DI 3 "const_int_operand" ""))])]
4040 && GET_CODE (operands[0]) == MEM
4041 && register_operand (XEXP (operands[0], 0), DImode)"
4042 [(parallel [(set (match_dup 0) (const_int 0))
4043 (clobber (match_dup 1))
4044 (clobber (match_dup 4))
4050 rtx addr = XEXP (operands[0], 0);
4051 if (dead_or_set_p (curr_insn, addr))
4055 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4056 operands[0] = replace_equiv_address (operands[0], operands[4]);
4060 (define_insn "clrmemdi_postreload"
4061 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4063 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4064 (clobber (match_dup 0))
4065 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4066 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4068 "TARGET_64BIT && reload_completed"
4069 "* return output_block_clear (operands, !which_alternative);"
4070 [(set_attr "type" "multi,multi")])
4072 ;; Floating point move insns
4074 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4075 ;; to be reloaded by putting the constant into memory when
4076 ;; reg is a floating point register.
4078 ;; For integer registers we use ldil;ldo to set the appropriate
4081 ;; This must come before the movdf pattern, and it must be present
4082 ;; to handle obscure reloading cases.
4084 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4085 (match_operand:DF 1 "" "?F,m"))]
4086 "GET_CODE (operands[1]) == CONST_DOUBLE
4087 && operands[1] != CONST0_RTX (DFmode)
4089 && !TARGET_SOFT_FLOAT"
4090 "* return (which_alternative == 0 ? output_move_double (operands)
4091 : \"fldd%F1 %1,%0\");"
4092 [(set_attr "type" "move,fpload")
4093 (set_attr "length" "16,4")])
4095 (define_expand "movdf"
4096 [(set (match_operand:DF 0 "general_operand" "")
4097 (match_operand:DF 1 "general_operand" ""))]
4101 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
4102 operands[1] = force_const_mem (DFmode, operands[1]);
4104 if (emit_move_sequence (operands, DFmode, 0))
4108 ;; Handle DFmode input reloads requiring a general register as a
4109 ;; scratch register.
4110 (define_expand "reload_indf"
4111 [(set (match_operand:DF 0 "register_operand" "=Z")
4112 (match_operand:DF 1 "non_hard_reg_operand" ""))
4113 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4117 if (emit_move_sequence (operands, DFmode, operands[2]))
4120 /* We don't want the clobber emitted, so handle this ourselves. */
4121 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4125 ;; Handle DFmode output reloads requiring a general register as a
4126 ;; scratch register.
4127 (define_expand "reload_outdf"
4128 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4129 (match_operand:DF 1 "register_operand" "Z"))
4130 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4134 if (emit_move_sequence (operands, DFmode, operands[2]))
4137 /* We don't want the clobber emitted, so handle this ourselves. */
4138 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4143 [(set (match_operand:DF 0 "move_dest_operand"
4144 "=f,*r,Q,?o,?Q,f,*r,*r,!r,!f")
4145 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4146 "fG,*rG,f,*r,*r,RQ,o,RQ,!f,!r"))]
4147 "(register_operand (operands[0], DFmode)
4148 || reg_or_0_operand (operands[1], DFmode))
4149 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4150 && GET_CODE (operands[0]) == MEM)
4152 && !TARGET_SOFT_FLOAT"
4155 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4156 || operands[1] == CONST0_RTX (DFmode))
4157 && !(REG_P (operands[0]) && REG_P (operands[1])
4158 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4159 return output_fp_move_double (operands);
4160 return output_move_double (operands);
4162 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,move,move")
4163 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4166 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4167 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4169 && !TARGET_DISABLE_INDEXING
4170 && reload_completed"
4172 [(set_attr "type" "fpstore")
4173 (set_attr "pa_combine_type" "addmove")
4174 (set_attr "length" "4")])
4177 [(set (match_operand:SI 0 "register_operand" "")
4178 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4180 (match_operand:SI 2 "register_operand" "")))
4181 (set (mem:DF (match_dup 0))
4182 (match_operand:DF 3 "register_operand" ""))]
4184 && !TARGET_DISABLE_INDEXING
4185 && REG_OK_FOR_BASE_P (operands[2])
4186 && FP_REGNO_P (REGNO (operands[3]))"
4187 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4189 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4194 [(set (match_operand:SI 0 "register_operand" "")
4195 (plus:SI (match_operand:SI 2 "register_operand" "")
4196 (mult:SI (match_operand:SI 1 "register_operand" "")
4198 (set (mem:DF (match_dup 0))
4199 (match_operand:DF 3 "register_operand" ""))]
4201 && !TARGET_DISABLE_INDEXING
4202 && REG_OK_FOR_BASE_P (operands[2])
4203 && FP_REGNO_P (REGNO (operands[3]))"
4204 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4206 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4211 [(set (match_operand:DI 0 "register_operand" "")
4212 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4214 (match_operand:DI 2 "register_operand" "")))
4215 (set (mem:DF (match_dup 0))
4216 (match_operand:DF 3 "register_operand" ""))]
4218 && !TARGET_DISABLE_INDEXING
4220 && REG_OK_FOR_BASE_P (operands[2])
4221 && FP_REGNO_P (REGNO (operands[3]))"
4222 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4224 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4229 [(set (match_operand:DI 0 "register_operand" "")
4230 (plus:DI (match_operand:DI 2 "register_operand" "")
4231 (mult:DI (match_operand:DI 1 "register_operand" "")
4233 (set (mem:DF (match_dup 0))
4234 (match_operand:DF 3 "register_operand" ""))]
4236 && !TARGET_DISABLE_INDEXING
4238 && REG_OK_FOR_BASE_P (operands[2])
4239 && FP_REGNO_P (REGNO (operands[3]))"
4240 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4242 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4247 [(set (match_operand:SI 0 "register_operand" "")
4248 (plus:SI (match_operand:SI 1 "register_operand" "")
4249 (match_operand:SI 2 "register_operand" "")))
4250 (set (mem:DF (match_dup 0))
4251 (match_operand:DF 3 "register_operand" ""))]
4253 && !TARGET_DISABLE_INDEXING
4254 && TARGET_NO_SPACE_REGS
4255 && REG_OK_FOR_INDEX_P (operands[1])
4256 && REG_OK_FOR_BASE_P (operands[2])
4257 && FP_REGNO_P (REGNO (operands[3]))"
4258 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4260 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4264 [(set (match_operand:SI 0 "register_operand" "")
4265 (plus:SI (match_operand:SI 1 "register_operand" "")
4266 (match_operand:SI 2 "register_operand" "")))
4267 (set (mem:DF (match_dup 0))
4268 (match_operand:DF 3 "register_operand" ""))]
4270 && !TARGET_DISABLE_INDEXING
4271 && TARGET_NO_SPACE_REGS
4272 && REG_OK_FOR_BASE_P (operands[1])
4273 && REG_OK_FOR_INDEX_P (operands[2])
4274 && FP_REGNO_P (REGNO (operands[3]))"
4275 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4277 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4281 [(set (match_operand:DI 0 "register_operand" "")
4282 (plus:DI (match_operand:DI 1 "register_operand" "")
4283 (match_operand:DI 2 "register_operand" "")))
4284 (set (mem:DF (match_dup 0))
4285 (match_operand:DF 3 "register_operand" ""))]
4287 && !TARGET_DISABLE_INDEXING
4289 && TARGET_NO_SPACE_REGS
4290 && REG_OK_FOR_INDEX_P (operands[1])
4291 && REG_OK_FOR_BASE_P (operands[2])
4292 && FP_REGNO_P (REGNO (operands[3]))"
4293 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4295 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4299 [(set (match_operand:DI 0 "register_operand" "")
4300 (plus:DI (match_operand:DI 1 "register_operand" "")
4301 (match_operand:DI 2 "register_operand" "")))
4302 (set (mem:DF (match_dup 0))
4303 (match_operand:DF 3 "register_operand" ""))]
4305 && !TARGET_DISABLE_INDEXING
4307 && TARGET_NO_SPACE_REGS
4308 && REG_OK_FOR_BASE_P (operands[1])
4309 && REG_OK_FOR_INDEX_P (operands[2])
4310 && FP_REGNO_P (REGNO (operands[3]))"
4311 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4313 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4317 [(set (match_operand:DF 0 "move_dest_operand"
4318 "=r,?o,?Q,r,r,!r,!f")
4319 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4320 "rG,r,r,o,RQ,!f,!r"))]
4321 "(register_operand (operands[0], DFmode)
4322 || reg_or_0_operand (operands[1], DFmode))
4324 && TARGET_SOFT_FLOAT"
4327 return output_move_double (operands);
4329 [(set_attr "type" "move,store,store,load,load,move,move")
4330 (set_attr "length" "8,8,16,8,16,12,12")])
4333 [(set (match_operand:DF 0 "move_dest_operand"
4334 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4335 (match_operand:DF 1 "move_src_operand"
4336 "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
4337 "(register_operand (operands[0], DFmode)
4338 || reg_or_0_operand (operands[1], DFmode))
4339 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4350 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4351 (set_attr "pa_combine_type" "addmove")
4352 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4355 (define_expand "movdi"
4356 [(set (match_operand:DI 0 "general_operand" "")
4357 (match_operand:DI 1 "general_operand" ""))]
4361 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
4362 operands[1] = force_const_mem (DImode, operands[1]);
4364 if (emit_move_sequence (operands, DImode, 0))
4368 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4369 (define_expand "reload_indi_r1"
4370 [(set (match_operand:DI 0 "register_operand" "=Z")
4371 (match_operand:DI 1 "non_hard_reg_operand" ""))
4372 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4376 if (emit_move_sequence (operands, DImode, operands[2]))
4379 /* We don't want the clobber emitted, so handle this ourselves. */
4380 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4384 ;; Handle DImode input reloads requiring a general register as a
4385 ;; scratch register.
4386 (define_expand "reload_indi"
4387 [(set (match_operand:DI 0 "register_operand" "=Z")
4388 (match_operand:DI 1 "non_hard_reg_operand" ""))
4389 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4393 if (emit_move_sequence (operands, DImode, operands[2]))
4396 /* We don't want the clobber emitted, so handle this ourselves. */
4397 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4401 ;; Handle DImode output reloads requiring a general register as a
4402 ;; scratch register.
4403 (define_expand "reload_outdi"
4404 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4405 (match_operand:DI 1 "register_operand" "Z"))
4406 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4410 if (emit_move_sequence (operands, DImode, operands[2]))
4413 /* We don't want the clobber emitted, so handle this ourselves. */
4414 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4419 [(set (match_operand:DI 0 "register_operand" "=r")
4420 (high:DI (match_operand 1 "" "")))]
4424 rtx op0 = operands[0];
4425 rtx op1 = operands[1];
4427 switch (GET_CODE (op1))
4430 operands[0] = operand_subword (op0, 1, 0, DImode);
4431 output_asm_insn (\"ldil L'%1,%0\", operands);
4433 operands[0] = operand_subword (op0, 0, 0, DImode);
4434 if (INTVAL (op1) < 0)
4435 output_asm_insn (\"ldi -1,%0\", operands);
4437 output_asm_insn (\"ldi 0,%0\", operands);
4441 operands[0] = operand_subword (op0, 1, 0, DImode);
4442 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4443 output_asm_insn (\"ldil L'%1,%0\", operands);
4445 operands[0] = operand_subword (op0, 0, 0, DImode);
4446 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4447 output_asm_insn (singlemove_string (operands), operands);
4455 [(set_attr "type" "move")
4456 (set_attr "length" "8")])
4459 [(set (match_operand:DI 0 "move_dest_operand"
4460 "=r,o,Q,r,r,r,*f,*f,T,!r,!f")
4461 (match_operand:DI 1 "general_operand"
4462 "rM,r,r,o*R,Q,i,*fM,RT,*f,!f,!r"))]
4463 "(register_operand (operands[0], DImode)
4464 || reg_or_0_operand (operands[1], DImode))
4466 && !TARGET_SOFT_FLOAT"
4469 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4470 || operands[1] == CONST0_RTX (DFmode))
4471 && !(REG_P (operands[0]) && REG_P (operands[1])
4472 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4473 return output_fp_move_double (operands);
4474 return output_move_double (operands);
4477 "move,store,store,load,load,multi,fpalu,fpload,fpstore,move,move")
4478 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4481 [(set (match_operand:DI 0 "move_dest_operand"
4482 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4483 (match_operand:DI 1 "move_src_operand"
4484 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4485 "(register_operand (operands[0], DImode)
4486 || reg_or_0_operand (operands[1], DImode))
4487 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4497 {mfctl|mfctl,w} %%sar,%0
4501 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4502 (set_attr "pa_combine_type" "addmove")
4503 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4506 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4507 (match_operand:DI 1 "register_operand" "f"))]
4510 && !TARGET_DISABLE_INDEXING
4511 && reload_completed"
4513 [(set_attr "type" "fpstore")
4514 (set_attr "pa_combine_type" "addmove")
4515 (set_attr "length" "4")])
4518 [(set (match_operand:DI 0 "register_operand" "")
4519 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4521 (match_operand:DI 2 "register_operand" "")))
4522 (set (mem:DI (match_dup 0))
4523 (match_operand:DI 3 "register_operand" ""))]
4525 && !TARGET_DISABLE_INDEXING
4527 && REG_OK_FOR_BASE_P (operands[2])
4528 && FP_REGNO_P (REGNO (operands[3]))"
4529 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4531 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4536 [(set (match_operand:DI 0 "register_operand" "")
4537 (plus:DI (match_operand:DI 2 "register_operand" "")
4538 (mult:DI (match_operand:DI 1 "register_operand" "")
4540 (set (mem:DI (match_dup 0))
4541 (match_operand:DI 3 "register_operand" ""))]
4543 && !TARGET_DISABLE_INDEXING
4545 && REG_OK_FOR_BASE_P (operands[2])
4546 && FP_REGNO_P (REGNO (operands[3]))"
4547 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4549 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4554 [(set (match_operand:DI 0 "register_operand" "")
4555 (plus:DI (match_operand:DI 1 "register_operand" "")
4556 (match_operand:DI 2 "register_operand" "")))
4557 (set (mem:DI (match_dup 0))
4558 (match_operand:DI 3 "register_operand" ""))]
4560 && !TARGET_DISABLE_INDEXING
4562 && TARGET_NO_SPACE_REGS
4563 && REG_OK_FOR_INDEX_P (operands[1])
4564 && REG_OK_FOR_BASE_P (operands[2])
4565 && FP_REGNO_P (REGNO (operands[3]))"
4566 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4568 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4572 [(set (match_operand:DI 0 "register_operand" "")
4573 (plus:DI (match_operand:DI 1 "register_operand" "")
4574 (match_operand:DI 2 "register_operand" "")))
4575 (set (mem:DI (match_dup 0))
4576 (match_operand:DI 3 "register_operand" ""))]
4578 && !TARGET_DISABLE_INDEXING
4580 && TARGET_NO_SPACE_REGS
4581 && REG_OK_FOR_BASE_P (operands[1])
4582 && REG_OK_FOR_INDEX_P (operands[2])
4583 && FP_REGNO_P (REGNO (operands[3]))"
4584 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4586 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4590 [(set (match_operand:DI 0 "move_dest_operand"
4592 (match_operand:DI 1 "general_operand"
4594 "(register_operand (operands[0], DImode)
4595 || reg_or_0_operand (operands[1], DImode))
4597 && TARGET_SOFT_FLOAT"
4600 return output_move_double (operands);
4602 [(set_attr "type" "move,store,store,load,load,multi")
4603 (set_attr "length" "8,8,16,8,16,16")])
4606 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4607 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4608 (match_operand:DI 2 "immediate_operand" "i,i")))]
4612 /* Don't output a 64 bit constant, since we can't trust the assembler to
4613 handle it correctly. */
4614 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4615 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4616 if (which_alternative == 1)
4617 output_asm_insn (\"copy %1,%0\", operands);
4618 return \"ldo R'%G2(%R1),%R0\";
4620 [(set_attr "type" "move,move")
4621 (set_attr "length" "4,8")])
4623 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4624 ;; to be reloaded by putting the constant into memory when
4625 ;; reg is a floating point register.
4627 ;; For integer registers we use ldil;ldo to set the appropriate
4630 ;; This must come before the movsf pattern, and it must be present
4631 ;; to handle obscure reloading cases.
4633 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4634 (match_operand:SF 1 "" "?F,m"))]
4635 "GET_CODE (operands[1]) == CONST_DOUBLE
4636 && operands[1] != CONST0_RTX (SFmode)
4637 && ! TARGET_SOFT_FLOAT"
4638 "* return (which_alternative == 0 ? singlemove_string (operands)
4639 : \" fldw%F1 %1,%0\");"
4640 [(set_attr "type" "move,fpload")
4641 (set_attr "length" "8,4")])
4643 (define_expand "movsf"
4644 [(set (match_operand:SF 0 "general_operand" "")
4645 (match_operand:SF 1 "general_operand" ""))]
4649 if (emit_move_sequence (operands, SFmode, 0))
4653 ;; Handle SFmode input reloads requiring a general register as a
4654 ;; scratch register.
4655 (define_expand "reload_insf"
4656 [(set (match_operand:SF 0 "register_operand" "=Z")
4657 (match_operand:SF 1 "non_hard_reg_operand" ""))
4658 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4662 if (emit_move_sequence (operands, SFmode, operands[2]))
4665 /* We don't want the clobber emitted, so handle this ourselves. */
4666 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4670 ;; Handle SFmode output reloads requiring a general register as a
4671 ;; scratch register.
4672 (define_expand "reload_outsf"
4673 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4674 (match_operand:SF 1 "register_operand" "Z"))
4675 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4679 if (emit_move_sequence (operands, SFmode, operands[2]))
4682 /* We don't want the clobber emitted, so handle this ourselves. */
4683 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4688 [(set (match_operand:SF 0 "move_dest_operand"
4689 "=f,!*r,f,*r,Q,Q,!r,!f")
4690 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4691 "fG,!*rG,RQ,RQ,f,*rG,!f,!r"))]
4692 "(register_operand (operands[0], SFmode)
4693 || reg_or_0_operand (operands[1], SFmode))
4694 && !TARGET_SOFT_FLOAT
4703 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4704 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4705 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,move,move")
4706 (set_attr "pa_combine_type" "addmove")
4707 (set_attr "length" "4,4,4,4,4,4,8,8")])
4710 [(set (match_operand:SF 0 "move_dest_operand"
4712 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4713 "fG,!*rG,RQ,RQ,f,*rG"))]
4714 "(register_operand (operands[0], SFmode)
4715 || reg_or_0_operand (operands[1], SFmode))
4716 && !TARGET_SOFT_FLOAT
4725 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4726 (set_attr "pa_combine_type" "addmove")
4727 (set_attr "length" "4,4,4,4,4,4")])
4730 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4731 (match_operand:SF 1 "register_operand" "f"))]
4733 && !TARGET_DISABLE_INDEXING
4734 && reload_completed"
4736 [(set_attr "type" "fpstore")
4737 (set_attr "pa_combine_type" "addmove")
4738 (set_attr "length" "4")])
4741 [(set (match_operand:SI 0 "register_operand" "")
4742 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4744 (match_operand:SI 2 "register_operand" "")))
4745 (set (mem:SF (match_dup 0))
4746 (match_operand:SF 3 "register_operand" ""))]
4748 && !TARGET_DISABLE_INDEXING
4749 && REG_OK_FOR_BASE_P (operands[2])
4750 && FP_REGNO_P (REGNO (operands[3]))"
4751 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4753 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4758 [(set (match_operand:SI 0 "register_operand" "")
4759 (plus:SI (match_operand:SI 2 "register_operand" "")
4760 (mult:SI (match_operand:SI 1 "register_operand" "")
4762 (set (mem:SF (match_dup 0))
4763 (match_operand:SF 3 "register_operand" ""))]
4765 && !TARGET_DISABLE_INDEXING
4766 && REG_OK_FOR_BASE_P (operands[2])
4767 && FP_REGNO_P (REGNO (operands[3]))"
4768 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4770 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4775 [(set (match_operand:DI 0 "register_operand" "")
4776 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4778 (match_operand:DI 2 "register_operand" "")))
4779 (set (mem:SF (match_dup 0))
4780 (match_operand:SF 3 "register_operand" ""))]
4782 && !TARGET_DISABLE_INDEXING
4784 && REG_OK_FOR_BASE_P (operands[2])
4785 && FP_REGNO_P (REGNO (operands[3]))"
4786 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4788 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4793 [(set (match_operand:DI 0 "register_operand" "")
4794 (plus:DI (match_operand:DI 2 "register_operand" "")
4795 (mult:DI (match_operand:DI 1 "register_operand" "")
4797 (set (mem:SF (match_dup 0))
4798 (match_operand:SF 3 "register_operand" ""))]
4800 && !TARGET_DISABLE_INDEXING
4802 && REG_OK_FOR_BASE_P (operands[2])
4803 && FP_REGNO_P (REGNO (operands[3]))"
4804 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4806 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4811 [(set (match_operand:SI 0 "register_operand" "")
4812 (plus:SI (match_operand:SI 1 "register_operand" "")
4813 (match_operand:SI 2 "register_operand" "")))
4814 (set (mem:SF (match_dup 0))
4815 (match_operand:SF 3 "register_operand" ""))]
4817 && !TARGET_DISABLE_INDEXING
4818 && TARGET_NO_SPACE_REGS
4819 && REG_OK_FOR_INDEX_P (operands[1])
4820 && REG_OK_FOR_BASE_P (operands[2])
4821 && FP_REGNO_P (REGNO (operands[3]))"
4822 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4824 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4828 [(set (match_operand:SI 0 "register_operand" "")
4829 (plus:SI (match_operand:SI 1 "register_operand" "")
4830 (match_operand:SI 2 "register_operand" "")))
4831 (set (mem:SF (match_dup 0))
4832 (match_operand:SF 3 "register_operand" ""))]
4834 && !TARGET_DISABLE_INDEXING
4835 && TARGET_NO_SPACE_REGS
4836 && REG_OK_FOR_BASE_P (operands[1])
4837 && REG_OK_FOR_INDEX_P (operands[2])
4838 && FP_REGNO_P (REGNO (operands[3]))"
4839 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4841 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4845 [(set (match_operand:DI 0 "register_operand" "")
4846 (plus:DI (match_operand:DI 1 "register_operand" "")
4847 (match_operand:DI 2 "register_operand" "")))
4848 (set (mem:SF (match_dup 0))
4849 (match_operand:SF 3 "register_operand" ""))]
4851 && !TARGET_DISABLE_INDEXING
4853 && TARGET_NO_SPACE_REGS
4854 && REG_OK_FOR_INDEX_P (operands[1])
4855 && REG_OK_FOR_BASE_P (operands[2])
4856 && FP_REGNO_P (REGNO (operands[3]))"
4857 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4859 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4863 [(set (match_operand:DI 0 "register_operand" "")
4864 (plus:DI (match_operand:DI 1 "register_operand" "")
4865 (match_operand:DI 2 "register_operand" "")))
4866 (set (mem:SF (match_dup 0))
4867 (match_operand:SF 3 "register_operand" ""))]
4869 && !TARGET_DISABLE_INDEXING
4871 && TARGET_NO_SPACE_REGS
4872 && REG_OK_FOR_BASE_P (operands[1])
4873 && REG_OK_FOR_INDEX_P (operands[2])
4874 && FP_REGNO_P (REGNO (operands[3]))"
4875 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4877 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4881 [(set (match_operand:SF 0 "move_dest_operand"
4883 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4885 "(register_operand (operands[0], SFmode)
4886 || reg_or_0_operand (operands[1], SFmode))
4887 && TARGET_SOFT_FLOAT"
4892 [(set_attr "type" "move,load,store")
4893 (set_attr "pa_combine_type" "addmove")
4894 (set_attr "length" "4,4,4")])
4898 ;;- zero extension instructions
4899 ;; We have define_expand for zero extension patterns to make sure the
4900 ;; operands get loaded into registers. The define_insns accept
4901 ;; memory operands. This gives us better overall code than just
4902 ;; having a pattern that does or does not accept memory operands.
4904 (define_expand "zero_extendqihi2"
4905 [(set (match_operand:HI 0 "register_operand" "")
4907 (match_operand:QI 1 "register_operand" "")))]
4912 [(set (match_operand:HI 0 "register_operand" "=r,r")
4914 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4915 "GET_CODE (operands[1]) != CONST_INT"
4917 {extru|extrw,u} %1,31,8,%0
4919 [(set_attr "type" "shift,load")
4920 (set_attr "length" "4,4")])
4922 (define_expand "zero_extendqisi2"
4923 [(set (match_operand:SI 0 "register_operand" "")
4925 (match_operand:QI 1 "register_operand" "")))]
4930 [(set (match_operand:SI 0 "register_operand" "=r,r")
4932 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4933 "GET_CODE (operands[1]) != CONST_INT"
4935 {extru|extrw,u} %1,31,8,%0
4937 [(set_attr "type" "shift,load")
4938 (set_attr "length" "4,4")])
4940 (define_expand "zero_extendhisi2"
4941 [(set (match_operand:SI 0 "register_operand" "")
4943 (match_operand:HI 1 "register_operand" "")))]
4948 [(set (match_operand:SI 0 "register_operand" "=r,r")
4950 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4951 "GET_CODE (operands[1]) != CONST_INT"
4953 {extru|extrw,u} %1,31,16,%0
4955 [(set_attr "type" "shift,load")
4956 (set_attr "length" "4,4")])
4958 (define_expand "zero_extendqidi2"
4959 [(set (match_operand:DI 0 "register_operand" "")
4961 (match_operand:QI 1 "register_operand" "")))]
4966 [(set (match_operand:DI 0 "register_operand" "=r,r")
4968 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4969 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4973 [(set_attr "type" "shift,load")
4974 (set_attr "length" "4,4")])
4976 (define_expand "zero_extendhidi2"
4977 [(set (match_operand:DI 0 "register_operand" "")
4979 (match_operand:HI 1 "register_operand" "")))]
4984 [(set (match_operand:DI 0 "register_operand" "=r,r")
4986 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4987 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4991 [(set_attr "type" "shift,load")
4992 (set_attr "length" "4,4")])
4994 (define_expand "zero_extendsidi2"
4995 [(set (match_operand:DI 0 "register_operand" "")
4997 (match_operand:SI 1 "register_operand" "")))]
5002 [(set (match_operand:DI 0 "register_operand" "=r,r")
5004 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5005 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5009 [(set_attr "type" "shift,load")
5010 (set_attr "length" "4,4")])
5012 ;;- sign extension instructions
5014 (define_insn "extendhisi2"
5015 [(set (match_operand:SI 0 "register_operand" "=r")
5016 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5018 "{extrs|extrw,s} %1,31,16,%0"
5019 [(set_attr "type" "shift")
5020 (set_attr "length" "4")])
5022 (define_insn "extendqihi2"
5023 [(set (match_operand:HI 0 "register_operand" "=r")
5024 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5026 "{extrs|extrw,s} %1,31,8,%0"
5027 [(set_attr "type" "shift")
5028 (set_attr "length" "4")])
5030 (define_insn "extendqisi2"
5031 [(set (match_operand:SI 0 "register_operand" "=r")
5032 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5034 "{extrs|extrw,s} %1,31,8,%0"
5035 [(set_attr "type" "shift")
5036 (set_attr "length" "4")])
5038 (define_insn "extendqidi2"
5039 [(set (match_operand:DI 0 "register_operand" "=r")
5040 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5042 "extrd,s %1,63,8,%0"
5043 [(set_attr "type" "shift")
5044 (set_attr "length" "4")])
5046 (define_insn "extendhidi2"
5047 [(set (match_operand:DI 0 "register_operand" "=r")
5048 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5050 "extrd,s %1,63,16,%0"
5051 [(set_attr "type" "shift")
5052 (set_attr "length" "4")])
5054 (define_insn "extendsidi2"
5055 [(set (match_operand:DI 0 "register_operand" "=r")
5056 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5058 "extrd,s %1,63,32,%0"
5059 [(set_attr "type" "shift")
5060 (set_attr "length" "4")])
5063 ;; Conversions between float and double.
5065 (define_insn "extendsfdf2"
5066 [(set (match_operand:DF 0 "register_operand" "=f")
5068 (match_operand:SF 1 "register_operand" "f")))]
5069 "! TARGET_SOFT_FLOAT"
5070 "{fcnvff|fcnv},sgl,dbl %1,%0"
5071 [(set_attr "type" "fpalu")
5072 (set_attr "length" "4")])
5074 (define_insn "truncdfsf2"
5075 [(set (match_operand:SF 0 "register_operand" "=f")
5077 (match_operand:DF 1 "register_operand" "f")))]
5078 "! TARGET_SOFT_FLOAT"
5079 "{fcnvff|fcnv},dbl,sgl %1,%0"
5080 [(set_attr "type" "fpalu")
5081 (set_attr "length" "4")])
5083 ;; Conversion between fixed point and floating point.
5084 ;; Note that among the fix-to-float insns
5085 ;; the ones that start with SImode come first.
5086 ;; That is so that an operand that is a CONST_INT
5087 ;; (and therefore lacks a specific machine mode).
5088 ;; will be recognized as SImode (which is always valid)
5089 ;; rather than as QImode or HImode.
5091 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5092 ;; to be reloaded by putting the constant into memory.
5093 ;; It must come before the more general floatsisf2 pattern.
5095 [(set (match_operand:SF 0 "register_operand" "=f")
5096 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5097 "! TARGET_SOFT_FLOAT"
5098 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5099 [(set_attr "type" "fpalu")
5100 (set_attr "length" "8")])
5102 (define_insn "floatsisf2"
5103 [(set (match_operand:SF 0 "register_operand" "=f")
5104 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5105 "! TARGET_SOFT_FLOAT"
5106 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5107 [(set_attr "type" "fpalu")
5108 (set_attr "length" "4")])
5110 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5111 ;; to be reloaded by putting the constant into memory.
5112 ;; It must come before the more general floatsidf2 pattern.
5114 [(set (match_operand:DF 0 "register_operand" "=f")
5115 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5116 "! TARGET_SOFT_FLOAT"
5117 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5118 [(set_attr "type" "fpalu")
5119 (set_attr "length" "8")])
5121 (define_insn "floatsidf2"
5122 [(set (match_operand:DF 0 "register_operand" "=f")
5123 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5124 "! TARGET_SOFT_FLOAT"
5125 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5126 [(set_attr "type" "fpalu")
5127 (set_attr "length" "4")])
5129 (define_expand "floatunssisf2"
5130 [(set (subreg:SI (match_dup 2) 4)
5131 (match_operand:SI 1 "register_operand" ""))
5132 (set (subreg:SI (match_dup 2) 0)
5134 (set (match_operand:SF 0 "register_operand" "")
5135 (float:SF (match_dup 2)))]
5136 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5141 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5144 operands[2] = gen_reg_rtx (DImode);
5147 (define_expand "floatunssidf2"
5148 [(set (subreg:SI (match_dup 2) 4)
5149 (match_operand:SI 1 "register_operand" ""))
5150 (set (subreg:SI (match_dup 2) 0)
5152 (set (match_operand:DF 0 "register_operand" "")
5153 (float:DF (match_dup 2)))]
5154 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5159 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5162 operands[2] = gen_reg_rtx (DImode);
5165 (define_insn "floatdisf2"
5166 [(set (match_operand:SF 0 "register_operand" "=f")
5167 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5168 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5169 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5170 [(set_attr "type" "fpalu")
5171 (set_attr "length" "4")])
5173 (define_insn "floatdidf2"
5174 [(set (match_operand:DF 0 "register_operand" "=f")
5175 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5176 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5177 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5178 [(set_attr "type" "fpalu")
5179 (set_attr "length" "4")])
5181 ;; Convert a float to an actual integer.
5182 ;; Truncation is performed as part of the conversion.
5184 (define_insn "fix_truncsfsi2"
5185 [(set (match_operand:SI 0 "register_operand" "=f")
5186 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5187 "! TARGET_SOFT_FLOAT"
5188 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5189 [(set_attr "type" "fpalu")
5190 (set_attr "length" "4")])
5192 (define_insn "fix_truncdfsi2"
5193 [(set (match_operand:SI 0 "register_operand" "=f")
5194 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5195 "! TARGET_SOFT_FLOAT"
5196 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5197 [(set_attr "type" "fpalu")
5198 (set_attr "length" "4")])
5200 (define_insn "fix_truncsfdi2"
5201 [(set (match_operand:DI 0 "register_operand" "=f")
5202 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5203 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5204 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5205 [(set_attr "type" "fpalu")
5206 (set_attr "length" "4")])
5208 (define_insn "fix_truncdfdi2"
5209 [(set (match_operand:DI 0 "register_operand" "=f")
5210 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5211 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5212 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5213 [(set_attr "type" "fpalu")
5214 (set_attr "length" "4")])
5216 (define_insn "floatunssidf2_pa20"
5217 [(set (match_operand:DF 0 "register_operand" "=f")
5218 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5219 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5221 [(set_attr "type" "fpalu")
5222 (set_attr "length" "4")])
5224 (define_insn "floatunssisf2_pa20"
5225 [(set (match_operand:SF 0 "register_operand" "=f")
5226 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5227 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5229 [(set_attr "type" "fpalu")
5230 (set_attr "length" "4")])
5232 (define_insn "floatunsdisf2"
5233 [(set (match_operand:SF 0 "register_operand" "=f")
5234 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5235 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5236 "fcnv,udw,sgl %1,%0"
5237 [(set_attr "type" "fpalu")
5238 (set_attr "length" "4")])
5240 (define_insn "floatunsdidf2"
5241 [(set (match_operand:DF 0 "register_operand" "=f")
5242 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5243 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5244 "fcnv,udw,dbl %1,%0"
5245 [(set_attr "type" "fpalu")
5246 (set_attr "length" "4")])
5248 (define_insn "fixuns_truncsfsi2"
5249 [(set (match_operand:SI 0 "register_operand" "=f")
5250 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5251 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5252 "fcnv,t,sgl,uw %1,%0"
5253 [(set_attr "type" "fpalu")
5254 (set_attr "length" "4")])
5256 (define_insn "fixuns_truncdfsi2"
5257 [(set (match_operand:SI 0 "register_operand" "=f")
5258 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5259 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5260 "fcnv,t,dbl,uw %1,%0"
5261 [(set_attr "type" "fpalu")
5262 (set_attr "length" "4")])
5264 (define_insn "fixuns_truncsfdi2"
5265 [(set (match_operand:DI 0 "register_operand" "=f")
5266 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5267 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5268 "fcnv,t,sgl,udw %1,%0"
5269 [(set_attr "type" "fpalu")
5270 (set_attr "length" "4")])
5272 (define_insn "fixuns_truncdfdi2"
5273 [(set (match_operand:DI 0 "register_operand" "=f")
5274 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5275 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5276 "fcnv,t,dbl,udw %1,%0"
5277 [(set_attr "type" "fpalu")
5278 (set_attr "length" "4")])
5280 ;;- arithmetic instructions
5282 (define_expand "adddi3"
5283 [(set (match_operand:DI 0 "register_operand" "")
5284 (plus:DI (match_operand:DI 1 "register_operand" "")
5285 (match_operand:DI 2 "adddi3_operand" "")))]
5290 [(set (match_operand:DI 0 "register_operand" "=r")
5291 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5292 (match_operand:DI 2 "arith11_operand" "rI")))]
5296 if (GET_CODE (operands[2]) == CONST_INT)
5298 if (INTVAL (operands[2]) >= 0)
5299 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5301 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5304 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5306 [(set_attr "type" "binary")
5307 (set_attr "length" "8")])
5310 [(set (match_operand:DI 0 "register_operand" "=r,r")
5311 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5312 (match_operand:DI 2 "arith_operand" "r,J")))]
5317 [(set_attr "type" "binary,binary")
5318 (set_attr "pa_combine_type" "addmove")
5319 (set_attr "length" "4,4")])
5322 [(set (match_operand:DI 0 "register_operand" "=r")
5323 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5324 (match_operand:DI 2 "register_operand" "r")))]
5327 [(set_attr "type" "binary")
5328 (set_attr "length" "4")])
5331 [(set (match_operand:SI 0 "register_operand" "=r")
5332 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5333 (match_operand:SI 2 "register_operand" "r")))]
5336 [(set_attr "type" "binary")
5337 (set_attr "length" "4")])
5339 ;; define_splits to optimize cases of adding a constant integer
5340 ;; to a register when the constant does not fit in 14 bits. */
5342 [(set (match_operand:SI 0 "register_operand" "")
5343 (plus:SI (match_operand:SI 1 "register_operand" "")
5344 (match_operand:SI 2 "const_int_operand" "")))
5345 (clobber (match_operand:SI 4 "register_operand" ""))]
5346 "! cint_ok_for_move (INTVAL (operands[2]))
5347 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5348 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5349 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5352 int val = INTVAL (operands[2]);
5353 int low = (val < 0) ? -0x2000 : 0x1fff;
5354 int rest = val - low;
5356 operands[2] = GEN_INT (rest);
5357 operands[3] = GEN_INT (low);
5361 [(set (match_operand:SI 0 "register_operand" "")
5362 (plus:SI (match_operand:SI 1 "register_operand" "")
5363 (match_operand:SI 2 "const_int_operand" "")))
5364 (clobber (match_operand:SI 4 "register_operand" ""))]
5365 "! cint_ok_for_move (INTVAL (operands[2]))"
5366 [(set (match_dup 4) (match_dup 2))
5367 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5371 HOST_WIDE_INT intval = INTVAL (operands[2]);
5373 /* Try dividing the constant by 2, then 4, and finally 8 to see
5374 if we can get a constant which can be loaded into a register
5375 in a single instruction (cint_ok_for_move).
5377 If that fails, try to negate the constant and subtract it
5378 from our input operand. */
5379 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5381 operands[2] = GEN_INT (intval / 2);
5382 operands[3] = const2_rtx;
5384 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5386 operands[2] = GEN_INT (intval / 4);
5387 operands[3] = GEN_INT (4);
5389 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5391 operands[2] = GEN_INT (intval / 8);
5392 operands[3] = GEN_INT (8);
5394 else if (cint_ok_for_move (-intval))
5396 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5397 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5404 (define_insn "addsi3"
5405 [(set (match_operand:SI 0 "register_operand" "=r,r")
5406 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5407 (match_operand:SI 2 "arith_operand" "r,J")))]
5410 {addl|add,l} %1,%2,%0
5412 [(set_attr "type" "binary,binary")
5413 (set_attr "pa_combine_type" "addmove")
5414 (set_attr "length" "4,4")])
5416 (define_expand "subdi3"
5417 [(set (match_operand:DI 0 "register_operand" "")
5418 (minus:DI (match_operand:DI 1 "register_operand" "")
5419 (match_operand:DI 2 "register_operand" "")))]
5424 [(set (match_operand:DI 0 "register_operand" "=r")
5425 (minus:DI (match_operand:DI 1 "register_operand" "r")
5426 (match_operand:DI 2 "register_operand" "r")))]
5428 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
5429 [(set_attr "type" "binary")
5430 (set_attr "length" "8")])
5433 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5434 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5435 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5441 [(set_attr "type" "binary,binary,move")
5442 (set_attr "length" "4,4,4")])
5444 (define_expand "subsi3"
5445 [(set (match_operand:SI 0 "register_operand" "")
5446 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5447 (match_operand:SI 2 "register_operand" "")))]
5452 [(set (match_operand:SI 0 "register_operand" "=r,r")
5453 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5454 (match_operand:SI 2 "register_operand" "r,r")))]
5459 [(set_attr "type" "binary,binary")
5460 (set_attr "length" "4,4")])
5463 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5464 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5465 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5471 [(set_attr "type" "binary,binary,move")
5472 (set_attr "length" "4,4,4")])
5474 ;; Clobbering a "register_operand" instead of a match_scratch
5475 ;; in operand3 of millicode calls avoids spilling %r1 and
5476 ;; produces better code.
5478 ;; The mulsi3 insns set up registers for the millicode call.
5479 (define_expand "mulsi3"
5480 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5481 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5482 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5483 (clobber (match_dup 3))
5484 (clobber (reg:SI 26))
5485 (clobber (reg:SI 25))
5486 (clobber (match_dup 4))])
5487 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5491 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5492 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5494 rtx scratch = gen_reg_rtx (DImode);
5495 operands[1] = force_reg (SImode, operands[1]);
5496 operands[2] = force_reg (SImode, operands[2]);
5497 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5498 emit_insn (gen_movsi (operands[0],
5499 gen_rtx_SUBREG (SImode, scratch,
5500 GET_MODE_SIZE (SImode))));
5503 operands[3] = gen_reg_rtx (SImode);
5506 (define_insn "umulsidi3"
5507 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5508 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5509 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5510 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5512 [(set_attr "type" "fpmuldbl")
5513 (set_attr "length" "4")])
5516 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5517 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5518 (match_operand:DI 2 "uint32_operand" "f")))]
5519 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5521 [(set_attr "type" "fpmuldbl")
5522 (set_attr "length" "4")])
5525 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5526 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5527 (match_operand:DI 2 "uint32_operand" "f")))]
5528 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5530 [(set_attr "type" "fpmuldbl")
5531 (set_attr "length" "4")])
5534 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5535 (clobber (match_operand:SI 0 "register_operand" "=a"))
5536 (clobber (reg:SI 26))
5537 (clobber (reg:SI 25))
5538 (clobber (reg:SI 31))]
5540 "* return output_mul_insn (0, insn);"
5541 [(set_attr "type" "milli")
5542 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5545 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5546 (clobber (match_operand:SI 0 "register_operand" "=a"))
5547 (clobber (reg:SI 26))
5548 (clobber (reg:SI 25))
5549 (clobber (reg:SI 2))]
5551 "* return output_mul_insn (0, insn);"
5552 [(set_attr "type" "milli")
5553 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5555 (define_expand "muldi3"
5556 [(set (match_operand:DI 0 "register_operand" "")
5557 (mult:DI (match_operand:DI 1 "register_operand" "")
5558 (match_operand:DI 2 "register_operand" "")))]
5559 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5562 rtx low_product = gen_reg_rtx (DImode);
5563 rtx cross_product1 = gen_reg_rtx (DImode);
5564 rtx cross_product2 = gen_reg_rtx (DImode);
5565 rtx cross_scratch = gen_reg_rtx (DImode);
5566 rtx cross_product = gen_reg_rtx (DImode);
5567 rtx op1l, op1r, op2l, op2r;
5568 rtx op1shifted, op2shifted;
5570 op1shifted = gen_reg_rtx (DImode);
5571 op2shifted = gen_reg_rtx (DImode);
5572 op1l = gen_reg_rtx (SImode);
5573 op1r = gen_reg_rtx (SImode);
5574 op2l = gen_reg_rtx (SImode);
5575 op2r = gen_reg_rtx (SImode);
5577 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5579 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5581 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5582 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5583 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5584 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5586 /* Emit multiplies for the cross products. */
5587 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5588 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5590 /* Emit a multiply for the low sub-word. */
5591 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5593 /* Sum the cross products and shift them into proper position. */
5594 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5595 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5597 /* Add the cross product to the low product and store the result
5598 into the output operand . */
5599 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5603 ;;; Division and mod.
5604 (define_expand "divsi3"
5605 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5606 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5607 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5608 (clobber (match_dup 3))
5609 (clobber (match_dup 4))
5610 (clobber (reg:SI 26))
5611 (clobber (reg:SI 25))
5612 (clobber (match_dup 5))])
5613 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5617 operands[3] = gen_reg_rtx (SImode);
5620 operands[5] = gen_rtx_REG (SImode, 2);
5621 operands[4] = operands[5];
5625 operands[5] = gen_rtx_REG (SImode, 31);
5626 operands[4] = gen_reg_rtx (SImode);
5628 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5634 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5635 (clobber (match_operand:SI 1 "register_operand" "=a"))
5636 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5637 (clobber (reg:SI 26))
5638 (clobber (reg:SI 25))
5639 (clobber (reg:SI 31))]
5642 return output_div_insn (operands, 0, insn);"
5643 [(set_attr "type" "milli")
5644 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5648 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5649 (clobber (match_operand:SI 1 "register_operand" "=a"))
5650 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5651 (clobber (reg:SI 26))
5652 (clobber (reg:SI 25))
5653 (clobber (reg:SI 2))]
5656 return output_div_insn (operands, 0, insn);"
5657 [(set_attr "type" "milli")
5658 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5660 (define_expand "udivsi3"
5661 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5662 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5663 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5664 (clobber (match_dup 3))
5665 (clobber (match_dup 4))
5666 (clobber (reg:SI 26))
5667 (clobber (reg:SI 25))
5668 (clobber (match_dup 5))])
5669 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5673 operands[3] = gen_reg_rtx (SImode);
5677 operands[5] = gen_rtx_REG (SImode, 2);
5678 operands[4] = operands[5];
5682 operands[5] = gen_rtx_REG (SImode, 31);
5683 operands[4] = gen_reg_rtx (SImode);
5685 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5691 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5692 (clobber (match_operand:SI 1 "register_operand" "=a"))
5693 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5694 (clobber (reg:SI 26))
5695 (clobber (reg:SI 25))
5696 (clobber (reg:SI 31))]
5699 return output_div_insn (operands, 1, insn);"
5700 [(set_attr "type" "milli")
5701 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5705 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5706 (clobber (match_operand:SI 1 "register_operand" "=a"))
5707 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5708 (clobber (reg:SI 26))
5709 (clobber (reg:SI 25))
5710 (clobber (reg:SI 2))]
5713 return output_div_insn (operands, 1, insn);"
5714 [(set_attr "type" "milli")
5715 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5717 (define_expand "modsi3"
5718 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5719 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5720 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5721 (clobber (match_dup 3))
5722 (clobber (match_dup 4))
5723 (clobber (reg:SI 26))
5724 (clobber (reg:SI 25))
5725 (clobber (match_dup 5))])
5726 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5732 operands[5] = gen_rtx_REG (SImode, 2);
5733 operands[4] = operands[5];
5737 operands[5] = gen_rtx_REG (SImode, 31);
5738 operands[4] = gen_reg_rtx (SImode);
5740 operands[3] = gen_reg_rtx (SImode);
5744 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5745 (clobber (match_operand:SI 0 "register_operand" "=a"))
5746 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5747 (clobber (reg:SI 26))
5748 (clobber (reg:SI 25))
5749 (clobber (reg:SI 31))]
5752 return output_mod_insn (0, insn);"
5753 [(set_attr "type" "milli")
5754 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5757 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5758 (clobber (match_operand:SI 0 "register_operand" "=a"))
5759 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5760 (clobber (reg:SI 26))
5761 (clobber (reg:SI 25))
5762 (clobber (reg:SI 2))]
5765 return output_mod_insn (0, insn);"
5766 [(set_attr "type" "milli")
5767 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5769 (define_expand "umodsi3"
5770 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5771 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5772 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5773 (clobber (match_dup 3))
5774 (clobber (match_dup 4))
5775 (clobber (reg:SI 26))
5776 (clobber (reg:SI 25))
5777 (clobber (match_dup 5))])
5778 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5784 operands[5] = gen_rtx_REG (SImode, 2);
5785 operands[4] = operands[5];
5789 operands[5] = gen_rtx_REG (SImode, 31);
5790 operands[4] = gen_reg_rtx (SImode);
5792 operands[3] = gen_reg_rtx (SImode);
5796 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5797 (clobber (match_operand:SI 0 "register_operand" "=a"))
5798 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5799 (clobber (reg:SI 26))
5800 (clobber (reg:SI 25))
5801 (clobber (reg:SI 31))]
5804 return output_mod_insn (1, insn);"
5805 [(set_attr "type" "milli")
5806 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5809 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5810 (clobber (match_operand:SI 0 "register_operand" "=a"))
5811 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5812 (clobber (reg:SI 26))
5813 (clobber (reg:SI 25))
5814 (clobber (reg:SI 2))]
5817 return output_mod_insn (1, insn);"
5818 [(set_attr "type" "milli")
5819 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5821 ;;- and instructions
5822 ;; We define DImode `and` so with DImode `not` we can get
5823 ;; DImode `andn`. Other combinations are possible.
5825 (define_expand "anddi3"
5826 [(set (match_operand:DI 0 "register_operand" "")
5827 (and:DI (match_operand:DI 1 "register_operand" "")
5828 (match_operand:DI 2 "and_operand" "")))]
5832 /* Both operands must be register operands. */
5833 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5838 [(set (match_operand:DI 0 "register_operand" "=r")
5839 (and:DI (match_operand:DI 1 "register_operand" "%r")
5840 (match_operand:DI 2 "register_operand" "r")))]
5842 "and %1,%2,%0\;and %R1,%R2,%R0"
5843 [(set_attr "type" "binary")
5844 (set_attr "length" "8")])
5847 [(set (match_operand:DI 0 "register_operand" "=r,r")
5848 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5849 (match_operand:DI 2 "and_operand" "rO,P")))]
5851 "* return output_64bit_and (operands); "
5852 [(set_attr "type" "binary")
5853 (set_attr "length" "4")])
5855 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5856 ; constant with ldil;ldo.
5857 (define_insn "andsi3"
5858 [(set (match_operand:SI 0 "register_operand" "=r,r")
5859 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5860 (match_operand:SI 2 "and_operand" "rO,P")))]
5862 "* return output_and (operands); "
5863 [(set_attr "type" "binary,shift")
5864 (set_attr "length" "4,4")])
5867 [(set (match_operand:DI 0 "register_operand" "=r")
5868 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5869 (match_operand:DI 2 "register_operand" "r")))]
5871 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5872 [(set_attr "type" "binary")
5873 (set_attr "length" "8")])
5876 [(set (match_operand:DI 0 "register_operand" "=r")
5877 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5878 (match_operand:DI 2 "register_operand" "r")))]
5881 [(set_attr "type" "binary")
5882 (set_attr "length" "4")])
5885 [(set (match_operand:SI 0 "register_operand" "=r")
5886 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5887 (match_operand:SI 2 "register_operand" "r")))]
5890 [(set_attr "type" "binary")
5891 (set_attr "length" "4")])
5893 (define_expand "iordi3"
5894 [(set (match_operand:DI 0 "register_operand" "")
5895 (ior:DI (match_operand:DI 1 "register_operand" "")
5896 (match_operand:DI 2 "ior_operand" "")))]
5900 /* Both operands must be register operands. */
5901 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
5906 [(set (match_operand:DI 0 "register_operand" "=r")
5907 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5908 (match_operand:DI 2 "register_operand" "r")))]
5910 "or %1,%2,%0\;or %R1,%R2,%R0"
5911 [(set_attr "type" "binary")
5912 (set_attr "length" "8")])
5915 [(set (match_operand:DI 0 "register_operand" "=r,r")
5916 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5917 (match_operand:DI 2 "ior_operand" "M,i")))]
5919 "* return output_64bit_ior (operands); "
5920 [(set_attr "type" "binary,shift")
5921 (set_attr "length" "4,4")])
5924 [(set (match_operand:DI 0 "register_operand" "=r")
5925 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5926 (match_operand:DI 2 "register_operand" "r")))]
5929 [(set_attr "type" "binary")
5930 (set_attr "length" "4")])
5932 ;; Need a define_expand because we've run out of CONST_OK... characters.
5933 (define_expand "iorsi3"
5934 [(set (match_operand:SI 0 "register_operand" "")
5935 (ior:SI (match_operand:SI 1 "register_operand" "")
5936 (match_operand:SI 2 "arith32_operand" "")))]
5940 if (! (ior_operand (operands[2], SImode)
5941 || register_operand (operands[2], SImode)))
5942 operands[2] = force_reg (SImode, operands[2]);
5946 [(set (match_operand:SI 0 "register_operand" "=r,r")
5947 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5948 (match_operand:SI 2 "ior_operand" "M,i")))]
5950 "* return output_ior (operands); "
5951 [(set_attr "type" "binary,shift")
5952 (set_attr "length" "4,4")])
5955 [(set (match_operand:SI 0 "register_operand" "=r")
5956 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5957 (match_operand:SI 2 "register_operand" "r")))]
5960 [(set_attr "type" "binary")
5961 (set_attr "length" "4")])
5963 (define_expand "xordi3"
5964 [(set (match_operand:DI 0 "register_operand" "")
5965 (xor:DI (match_operand:DI 1 "register_operand" "")
5966 (match_operand:DI 2 "register_operand" "")))]
5973 [(set (match_operand:DI 0 "register_operand" "=r")
5974 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5975 (match_operand:DI 2 "register_operand" "r")))]
5977 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5978 [(set_attr "type" "binary")
5979 (set_attr "length" "8")])
5982 [(set (match_operand:DI 0 "register_operand" "=r")
5983 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5984 (match_operand:DI 2 "register_operand" "r")))]
5987 [(set_attr "type" "binary")
5988 (set_attr "length" "4")])
5990 (define_insn "xorsi3"
5991 [(set (match_operand:SI 0 "register_operand" "=r")
5992 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5993 (match_operand:SI 2 "register_operand" "r")))]
5996 [(set_attr "type" "binary")
5997 (set_attr "length" "4")])
5999 (define_expand "negdi2"
6000 [(set (match_operand:DI 0 "register_operand" "")
6001 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6006 [(set (match_operand:DI 0 "register_operand" "=r")
6007 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6009 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6010 [(set_attr "type" "unary")
6011 (set_attr "length" "8")])
6014 [(set (match_operand:DI 0 "register_operand" "=r")
6015 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6018 [(set_attr "type" "unary")
6019 (set_attr "length" "4")])
6021 (define_insn "negsi2"
6022 [(set (match_operand:SI 0 "register_operand" "=r")
6023 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6026 [(set_attr "type" "unary")
6027 (set_attr "length" "4")])
6029 (define_expand "one_cmpldi2"
6030 [(set (match_operand:DI 0 "register_operand" "")
6031 (not:DI (match_operand:DI 1 "register_operand" "")))]
6038 [(set (match_operand:DI 0 "register_operand" "=r")
6039 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6041 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6042 [(set_attr "type" "unary")
6043 (set_attr "length" "8")])
6046 [(set (match_operand:DI 0 "register_operand" "=r")
6047 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6050 [(set_attr "type" "unary")
6051 (set_attr "length" "4")])
6053 (define_insn "one_cmplsi2"
6054 [(set (match_operand:SI 0 "register_operand" "=r")
6055 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6058 [(set_attr "type" "unary")
6059 (set_attr "length" "4")])
6061 ;; Floating point arithmetic instructions.
6063 (define_insn "adddf3"
6064 [(set (match_operand:DF 0 "register_operand" "=f")
6065 (plus:DF (match_operand:DF 1 "register_operand" "f")
6066 (match_operand:DF 2 "register_operand" "f")))]
6067 "! TARGET_SOFT_FLOAT"
6069 [(set_attr "type" "fpalu")
6070 (set_attr "pa_combine_type" "faddsub")
6071 (set_attr "length" "4")])
6073 (define_insn "addsf3"
6074 [(set (match_operand:SF 0 "register_operand" "=f")
6075 (plus:SF (match_operand:SF 1 "register_operand" "f")
6076 (match_operand:SF 2 "register_operand" "f")))]
6077 "! TARGET_SOFT_FLOAT"
6079 [(set_attr "type" "fpalu")
6080 (set_attr "pa_combine_type" "faddsub")
6081 (set_attr "length" "4")])
6083 (define_insn "subdf3"
6084 [(set (match_operand:DF 0 "register_operand" "=f")
6085 (minus:DF (match_operand:DF 1 "register_operand" "f")
6086 (match_operand:DF 2 "register_operand" "f")))]
6087 "! TARGET_SOFT_FLOAT"
6089 [(set_attr "type" "fpalu")
6090 (set_attr "pa_combine_type" "faddsub")
6091 (set_attr "length" "4")])
6093 (define_insn "subsf3"
6094 [(set (match_operand:SF 0 "register_operand" "=f")
6095 (minus:SF (match_operand:SF 1 "register_operand" "f")
6096 (match_operand:SF 2 "register_operand" "f")))]
6097 "! TARGET_SOFT_FLOAT"
6099 [(set_attr "type" "fpalu")
6100 (set_attr "pa_combine_type" "faddsub")
6101 (set_attr "length" "4")])
6103 (define_insn "muldf3"
6104 [(set (match_operand:DF 0 "register_operand" "=f")
6105 (mult:DF (match_operand:DF 1 "register_operand" "f")
6106 (match_operand:DF 2 "register_operand" "f")))]
6107 "! TARGET_SOFT_FLOAT"
6109 [(set_attr "type" "fpmuldbl")
6110 (set_attr "pa_combine_type" "fmpy")
6111 (set_attr "length" "4")])
6113 (define_insn "mulsf3"
6114 [(set (match_operand:SF 0 "register_operand" "=f")
6115 (mult:SF (match_operand:SF 1 "register_operand" "f")
6116 (match_operand:SF 2 "register_operand" "f")))]
6117 "! TARGET_SOFT_FLOAT"
6119 [(set_attr "type" "fpmulsgl")
6120 (set_attr "pa_combine_type" "fmpy")
6121 (set_attr "length" "4")])
6123 (define_insn "divdf3"
6124 [(set (match_operand:DF 0 "register_operand" "=f")
6125 (div:DF (match_operand:DF 1 "register_operand" "f")
6126 (match_operand:DF 2 "register_operand" "f")))]
6127 "! TARGET_SOFT_FLOAT"
6129 [(set_attr "type" "fpdivdbl")
6130 (set_attr "length" "4")])
6132 (define_insn "divsf3"
6133 [(set (match_operand:SF 0 "register_operand" "=f")
6134 (div:SF (match_operand:SF 1 "register_operand" "f")
6135 (match_operand:SF 2 "register_operand" "f")))]
6136 "! TARGET_SOFT_FLOAT"
6138 [(set_attr "type" "fpdivsgl")
6139 (set_attr "length" "4")])
6141 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6142 ;; negation can be done by subtracting from plus zero. However, this
6143 ;; violates the IEEE standard when negating plus and minus zero.
6144 (define_expand "negdf2"
6145 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6146 (neg:DF (match_operand:DF 1 "register_operand" "")))
6147 (use (match_dup 2))])]
6148 "! TARGET_SOFT_FLOAT"
6150 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6151 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6154 operands[2] = force_reg (DFmode,
6155 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6156 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6161 (define_insn "negdf2_fast"
6162 [(set (match_operand:DF 0 "register_operand" "=f")
6163 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6164 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6168 return \"fneg,dbl %1,%0\";
6170 return \"fsub,dbl %%fr0,%1,%0\";
6172 [(set_attr "type" "fpalu")
6173 (set_attr "length" "4")])
6175 (define_expand "negsf2"
6176 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6177 (neg:SF (match_operand:SF 1 "register_operand" "")))
6178 (use (match_dup 2))])]
6179 "! TARGET_SOFT_FLOAT"
6181 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6182 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6185 operands[2] = force_reg (SFmode,
6186 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6187 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6192 (define_insn "negsf2_fast"
6193 [(set (match_operand:SF 0 "register_operand" "=f")
6194 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6195 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6199 return \"fneg,sgl %1,%0\";
6201 return \"fsub,sgl %%fr0,%1,%0\";
6203 [(set_attr "type" "fpalu")
6204 (set_attr "length" "4")])
6206 (define_insn "absdf2"
6207 [(set (match_operand:DF 0 "register_operand" "=f")
6208 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6209 "! TARGET_SOFT_FLOAT"
6211 [(set_attr "type" "fpalu")
6212 (set_attr "length" "4")])
6214 (define_insn "abssf2"
6215 [(set (match_operand:SF 0 "register_operand" "=f")
6216 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6217 "! TARGET_SOFT_FLOAT"
6219 [(set_attr "type" "fpalu")
6220 (set_attr "length" "4")])
6222 (define_insn "sqrtdf2"
6223 [(set (match_operand:DF 0 "register_operand" "=f")
6224 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6225 "! TARGET_SOFT_FLOAT"
6227 [(set_attr "type" "fpsqrtdbl")
6228 (set_attr "length" "4")])
6230 (define_insn "sqrtsf2"
6231 [(set (match_operand:SF 0 "register_operand" "=f")
6232 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6233 "! TARGET_SOFT_FLOAT"
6235 [(set_attr "type" "fpsqrtsgl")
6236 (set_attr "length" "4")])
6238 ;; PA 2.0 floating point instructions
6242 [(set (match_operand:DF 0 "register_operand" "=f")
6243 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6244 (match_operand:DF 2 "register_operand" "f"))
6245 (match_operand:DF 3 "register_operand" "f")))]
6246 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6247 "fmpyfadd,dbl %1,%2,%3,%0"
6248 [(set_attr "type" "fpmuldbl")
6249 (set_attr "length" "4")])
6252 [(set (match_operand:DF 0 "register_operand" "=f")
6253 (plus:DF (match_operand:DF 1 "register_operand" "f")
6254 (mult:DF (match_operand:DF 2 "register_operand" "f")
6255 (match_operand:DF 3 "register_operand" "f"))))]
6256 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6257 "fmpyfadd,dbl %2,%3,%1,%0"
6258 [(set_attr "type" "fpmuldbl")
6259 (set_attr "length" "4")])
6262 [(set (match_operand:SF 0 "register_operand" "=f")
6263 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6264 (match_operand:SF 2 "register_operand" "f"))
6265 (match_operand:SF 3 "register_operand" "f")))]
6266 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6267 "fmpyfadd,sgl %1,%2,%3,%0"
6268 [(set_attr "type" "fpmulsgl")
6269 (set_attr "length" "4")])
6272 [(set (match_operand:SF 0 "register_operand" "=f")
6273 (plus:SF (match_operand:SF 1 "register_operand" "f")
6274 (mult:SF (match_operand:SF 2 "register_operand" "f")
6275 (match_operand:SF 3 "register_operand" "f"))))]
6276 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6277 "fmpyfadd,sgl %2,%3,%1,%0"
6278 [(set_attr "type" "fpmulsgl")
6279 (set_attr "length" "4")])
6281 ; fmpynfadd patterns
6283 [(set (match_operand:DF 0 "register_operand" "=f")
6284 (minus:DF (match_operand:DF 1 "register_operand" "f")
6285 (mult:DF (match_operand:DF 2 "register_operand" "f")
6286 (match_operand:DF 3 "register_operand" "f"))))]
6287 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6288 "fmpynfadd,dbl %2,%3,%1,%0"
6289 [(set_attr "type" "fpmuldbl")
6290 (set_attr "length" "4")])
6293 [(set (match_operand:SF 0 "register_operand" "=f")
6294 (minus:SF (match_operand:SF 1 "register_operand" "f")
6295 (mult:SF (match_operand:SF 2 "register_operand" "f")
6296 (match_operand:SF 3 "register_operand" "f"))))]
6297 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6298 "fmpynfadd,sgl %2,%3,%1,%0"
6299 [(set_attr "type" "fpmulsgl")
6300 (set_attr "length" "4")])
6304 [(set (match_operand:DF 0 "register_operand" "=f")
6305 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6306 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6308 [(set_attr "type" "fpalu")
6309 (set_attr "length" "4")])
6312 [(set (match_operand:SF 0 "register_operand" "=f")
6313 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6314 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6316 [(set_attr "type" "fpalu")
6317 (set_attr "length" "4")])
6319 ;; Generating a fused multiply sequence is a win for this case as it will
6320 ;; reduce the latency for the fused case without impacting the plain
6323 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6324 ;; perform two operations with the result of the first feeding the second.
6326 [(set (match_operand:DF 0 "register_operand" "=f")
6327 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6328 (match_operand:DF 2 "register_operand" "f"))
6329 (match_operand:DF 3 "register_operand" "f")))
6330 (set (match_operand:DF 4 "register_operand" "=&f")
6331 (mult:DF (match_dup 1) (match_dup 2)))]
6332 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6333 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6334 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6336 [(set_attr "type" "fpmuldbl")
6337 (set_attr "length" "8")])
6339 ;; We want to split this up during scheduling since we want both insns
6340 ;; to schedule independently.
6342 [(set (match_operand:DF 0 "register_operand" "")
6343 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6344 (match_operand:DF 2 "register_operand" ""))
6345 (match_operand:DF 3 "register_operand" "")))
6346 (set (match_operand:DF 4 "register_operand" "")
6347 (mult:DF (match_dup 1) (match_dup 2)))]
6348 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6349 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6350 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6355 [(set (match_operand:SF 0 "register_operand" "=f")
6356 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6357 (match_operand:SF 2 "register_operand" "f"))
6358 (match_operand:SF 3 "register_operand" "f")))
6359 (set (match_operand:SF 4 "register_operand" "=&f")
6360 (mult:SF (match_dup 1) (match_dup 2)))]
6361 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6362 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6363 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6365 [(set_attr "type" "fpmuldbl")
6366 (set_attr "length" "8")])
6368 ;; We want to split this up during scheduling since we want both insns
6369 ;; to schedule independently.
6371 [(set (match_operand:SF 0 "register_operand" "")
6372 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6373 (match_operand:SF 2 "register_operand" ""))
6374 (match_operand:SF 3 "register_operand" "")))
6375 (set (match_operand:SF 4 "register_operand" "")
6376 (mult:SF (match_dup 1) (match_dup 2)))]
6377 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6378 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6379 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6383 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6386 [(set (match_operand:DF 0 "register_operand" "=f")
6387 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6388 (match_operand:DF 2 "register_operand" "f"))))]
6389 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6390 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6391 [(set_attr "type" "fpmuldbl")
6392 (set_attr "length" "4")])
6395 [(set (match_operand:SF 0 "register_operand" "=f")
6396 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6397 (match_operand:SF 2 "register_operand" "f"))))]
6398 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6399 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6400 [(set_attr "type" "fpmuldbl")
6401 (set_attr "length" "4")])
6404 [(set (match_operand:DF 0 "register_operand" "=f")
6405 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6406 (match_operand:DF 2 "register_operand" "f"))))
6407 (set (match_operand:DF 3 "register_operand" "=&f")
6408 (mult:DF (match_dup 1) (match_dup 2)))]
6409 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6410 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6411 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6413 [(set_attr "type" "fpmuldbl")
6414 (set_attr "length" "8")])
6417 [(set (match_operand:DF 0 "register_operand" "")
6418 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6419 (match_operand:DF 2 "register_operand" ""))))
6420 (set (match_operand:DF 3 "register_operand" "")
6421 (mult:DF (match_dup 1) (match_dup 2)))]
6422 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6423 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6424 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6428 [(set (match_operand:SF 0 "register_operand" "=f")
6429 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6430 (match_operand:SF 2 "register_operand" "f"))))
6431 (set (match_operand:SF 3 "register_operand" "=&f")
6432 (mult:SF (match_dup 1) (match_dup 2)))]
6433 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6434 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6435 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6437 [(set_attr "type" "fpmuldbl")
6438 (set_attr "length" "8")])
6441 [(set (match_operand:SF 0 "register_operand" "")
6442 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6443 (match_operand:SF 2 "register_operand" ""))))
6444 (set (match_operand:SF 3 "register_operand" "")
6445 (mult:SF (match_dup 1) (match_dup 2)))]
6446 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6447 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6448 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6451 ;; Now fused multiplies with the result of the multiply negated.
6453 [(set (match_operand:DF 0 "register_operand" "=f")
6454 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6455 (match_operand:DF 2 "register_operand" "f")))
6456 (match_operand:DF 3 "register_operand" "f")))]
6457 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6458 "fmpynfadd,dbl %1,%2,%3,%0"
6459 [(set_attr "type" "fpmuldbl")
6460 (set_attr "length" "4")])
6463 [(set (match_operand:SF 0 "register_operand" "=f")
6464 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6465 (match_operand:SF 2 "register_operand" "f")))
6466 (match_operand:SF 3 "register_operand" "f")))]
6467 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6468 "fmpynfadd,sgl %1,%2,%3,%0"
6469 [(set_attr "type" "fpmuldbl")
6470 (set_attr "length" "4")])
6473 [(set (match_operand:DF 0 "register_operand" "=f")
6474 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6475 (match_operand:DF 2 "register_operand" "f")))
6476 (match_operand:DF 3 "register_operand" "f")))
6477 (set (match_operand:DF 4 "register_operand" "=&f")
6478 (mult:DF (match_dup 1) (match_dup 2)))]
6479 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6480 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6481 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6483 [(set_attr "type" "fpmuldbl")
6484 (set_attr "length" "8")])
6487 [(set (match_operand:DF 0 "register_operand" "")
6488 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6489 (match_operand:DF 2 "register_operand" "")))
6490 (match_operand:DF 3 "register_operand" "")))
6491 (set (match_operand:DF 4 "register_operand" "")
6492 (mult:DF (match_dup 1) (match_dup 2)))]
6493 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6494 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6495 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6500 [(set (match_operand:SF 0 "register_operand" "=f")
6501 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6502 (match_operand:SF 2 "register_operand" "f")))
6503 (match_operand:SF 3 "register_operand" "f")))
6504 (set (match_operand:SF 4 "register_operand" "=&f")
6505 (mult:SF (match_dup 1) (match_dup 2)))]
6506 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6507 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6508 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6510 [(set_attr "type" "fpmuldbl")
6511 (set_attr "length" "8")])
6514 [(set (match_operand:SF 0 "register_operand" "")
6515 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6516 (match_operand:SF 2 "register_operand" "")))
6517 (match_operand:SF 3 "register_operand" "")))
6518 (set (match_operand:SF 4 "register_operand" "")
6519 (mult:SF (match_dup 1) (match_dup 2)))]
6520 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6521 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6522 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6527 [(set (match_operand:DF 0 "register_operand" "=f")
6528 (minus:DF (match_operand:DF 3 "register_operand" "f")
6529 (mult:DF (match_operand:DF 1 "register_operand" "f")
6530 (match_operand:DF 2 "register_operand" "f"))))
6531 (set (match_operand:DF 4 "register_operand" "=&f")
6532 (mult:DF (match_dup 1) (match_dup 2)))]
6533 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6534 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6535 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6537 [(set_attr "type" "fpmuldbl")
6538 (set_attr "length" "8")])
6541 [(set (match_operand:DF 0 "register_operand" "")
6542 (minus:DF (match_operand:DF 3 "register_operand" "")
6543 (mult:DF (match_operand:DF 1 "register_operand" "")
6544 (match_operand:DF 2 "register_operand" ""))))
6545 (set (match_operand:DF 4 "register_operand" "")
6546 (mult:DF (match_dup 1) (match_dup 2)))]
6547 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6548 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6549 (set (match_dup 0) (minus:DF (match_dup 3)
6550 (mult:DF (match_dup 1) (match_dup 2))))]
6554 [(set (match_operand:SF 0 "register_operand" "=f")
6555 (minus:SF (match_operand:SF 3 "register_operand" "f")
6556 (mult:SF (match_operand:SF 1 "register_operand" "f")
6557 (match_operand:SF 2 "register_operand" "f"))))
6558 (set (match_operand:SF 4 "register_operand" "=&f")
6559 (mult:SF (match_dup 1) (match_dup 2)))]
6560 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6561 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6562 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6564 [(set_attr "type" "fpmuldbl")
6565 (set_attr "length" "8")])
6568 [(set (match_operand:SF 0 "register_operand" "")
6569 (minus:SF (match_operand:SF 3 "register_operand" "")
6570 (mult:SF (match_operand:SF 1 "register_operand" "")
6571 (match_operand:SF 2 "register_operand" ""))))
6572 (set (match_operand:SF 4 "register_operand" "")
6573 (mult:SF (match_dup 1) (match_dup 2)))]
6574 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6575 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6576 (set (match_dup 0) (minus:SF (match_dup 3)
6577 (mult:SF (match_dup 1) (match_dup 2))))]
6581 [(set (match_operand:DF 0 "register_operand" "=f")
6582 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6583 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6584 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6585 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6587 [(set_attr "type" "fpalu")
6588 (set_attr "length" "8")])
6591 [(set (match_operand:DF 0 "register_operand" "")
6592 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6593 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6594 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6595 [(set (match_dup 2) (abs:DF (match_dup 1)))
6596 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6600 [(set (match_operand:SF 0 "register_operand" "=f")
6601 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6602 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6603 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6604 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6606 [(set_attr "type" "fpalu")
6607 (set_attr "length" "8")])
6610 [(set (match_operand:SF 0 "register_operand" "")
6611 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6612 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6613 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6614 [(set (match_dup 2) (abs:SF (match_dup 1)))
6615 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6618 ;;- Shift instructions
6620 ;; Optimized special case of shifting.
6623 [(set (match_operand:SI 0 "register_operand" "=r")
6624 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6628 [(set_attr "type" "load")
6629 (set_attr "length" "4")])
6632 [(set (match_operand:SI 0 "register_operand" "=r")
6633 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6637 [(set_attr "type" "load")
6638 (set_attr "length" "4")])
6641 [(set (match_operand:SI 0 "register_operand" "=r")
6642 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6643 (match_operand:SI 3 "shadd_operand" ""))
6644 (match_operand:SI 1 "register_operand" "r")))]
6646 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6647 [(set_attr "type" "binary")
6648 (set_attr "length" "4")])
6651 [(set (match_operand:DI 0 "register_operand" "=r")
6652 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6653 (match_operand:DI 3 "shadd_operand" ""))
6654 (match_operand:DI 1 "register_operand" "r")))]
6656 "shladd,l %2,%O3,%1,%0"
6657 [(set_attr "type" "binary")
6658 (set_attr "length" "4")])
6660 (define_expand "ashlsi3"
6661 [(set (match_operand:SI 0 "register_operand" "")
6662 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6663 (match_operand:SI 2 "arith32_operand" "")))]
6667 if (GET_CODE (operands[2]) != CONST_INT)
6669 rtx temp = gen_reg_rtx (SImode);
6670 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6671 if (GET_CODE (operands[1]) == CONST_INT)
6672 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6674 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6677 /* Make sure both inputs are not constants,
6678 there are no patterns for that. */
6679 operands[1] = force_reg (SImode, operands[1]);
6683 [(set (match_operand:SI 0 "register_operand" "=r")
6684 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6685 (match_operand:SI 2 "const_int_operand" "n")))]
6687 "{zdep|depw,z} %1,%P2,%L2,%0"
6688 [(set_attr "type" "shift")
6689 (set_attr "length" "4")])
6691 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6692 ; Doing it like this makes slightly better code since reload can
6693 ; replace a register with a known value in range -16..15 with a
6694 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6695 ; but since we have no more CONST_OK... characters, that is not
6697 (define_insn "zvdep32"
6698 [(set (match_operand:SI 0 "register_operand" "=r,r")
6699 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6700 (minus:SI (const_int 31)
6701 (match_operand:SI 2 "register_operand" "q,q"))))]
6704 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6705 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6706 [(set_attr "type" "shift,shift")
6707 (set_attr "length" "4,4")])
6709 (define_insn "zvdep_imm32"
6710 [(set (match_operand:SI 0 "register_operand" "=r")
6711 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6712 (minus:SI (const_int 31)
6713 (match_operand:SI 2 "register_operand" "q"))))]
6717 int x = INTVAL (operands[1]);
6718 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6719 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6720 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6722 [(set_attr "type" "shift")
6723 (set_attr "length" "4")])
6725 (define_insn "vdepi_ior"
6726 [(set (match_operand:SI 0 "register_operand" "=r")
6727 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6728 (minus:SI (const_int 31)
6729 (match_operand:SI 2 "register_operand" "q")))
6730 (match_operand:SI 3 "register_operand" "0")))]
6731 ; accept ...0001...1, can this be generalized?
6732 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6735 int x = INTVAL (operands[1]);
6736 operands[2] = GEN_INT (exact_log2 (x + 1));
6737 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6739 [(set_attr "type" "shift")
6740 (set_attr "length" "4")])
6742 (define_insn "vdepi_and"
6743 [(set (match_operand:SI 0 "register_operand" "=r")
6744 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6745 (minus:SI (const_int 31)
6746 (match_operand:SI 2 "register_operand" "q")))
6747 (match_operand:SI 3 "register_operand" "0")))]
6748 ; this can be generalized...!
6749 "INTVAL (operands[1]) == -2"
6752 int x = INTVAL (operands[1]);
6753 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6754 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6756 [(set_attr "type" "shift")
6757 (set_attr "length" "4")])
6759 (define_expand "ashldi3"
6760 [(set (match_operand:DI 0 "register_operand" "")
6761 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6762 (match_operand:DI 2 "arith32_operand" "")))]
6766 if (GET_CODE (operands[2]) != CONST_INT)
6768 rtx temp = gen_reg_rtx (DImode);
6769 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6770 if (GET_CODE (operands[1]) == CONST_INT)
6771 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6773 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6776 /* Make sure both inputs are not constants,
6777 there are no patterns for that. */
6778 operands[1] = force_reg (DImode, operands[1]);
6782 [(set (match_operand:DI 0 "register_operand" "=r")
6783 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6784 (match_operand:DI 2 "const_int_operand" "n")))]
6786 "depd,z %1,%p2,%Q2,%0"
6787 [(set_attr "type" "shift")
6788 (set_attr "length" "4")])
6790 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6791 ; Doing it like this makes slightly better code since reload can
6792 ; replace a register with a known value in range -16..15 with a
6793 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6794 ; but since we have no more CONST_OK... characters, that is not
6796 (define_insn "zvdep64"
6797 [(set (match_operand:DI 0 "register_operand" "=r,r")
6798 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6799 (minus:DI (const_int 63)
6800 (match_operand:DI 2 "register_operand" "q,q"))))]
6803 depd,z %1,%%sar,64,%0
6804 depdi,z %1,%%sar,64,%0"
6805 [(set_attr "type" "shift,shift")
6806 (set_attr "length" "4,4")])
6808 (define_insn "zvdep_imm64"
6809 [(set (match_operand:DI 0 "register_operand" "=r")
6810 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6811 (minus:DI (const_int 63)
6812 (match_operand:DI 2 "register_operand" "q"))))]
6816 int x = INTVAL (operands[1]);
6817 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6818 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6819 return \"depdi,z %1,%%sar,%2,%0\";
6821 [(set_attr "type" "shift")
6822 (set_attr "length" "4")])
6825 [(set (match_operand:DI 0 "register_operand" "=r")
6826 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6827 (minus:DI (const_int 63)
6828 (match_operand:DI 2 "register_operand" "q")))
6829 (match_operand:DI 3 "register_operand" "0")))]
6830 ; accept ...0001...1, can this be generalized?
6831 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6834 int x = INTVAL (operands[1]);
6835 operands[2] = GEN_INT (exact_log2 (x + 1));
6836 return \"depdi -1,%%sar,%2,%0\";
6838 [(set_attr "type" "shift")
6839 (set_attr "length" "4")])
6842 [(set (match_operand:DI 0 "register_operand" "=r")
6843 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6844 (minus:DI (const_int 63)
6845 (match_operand:DI 2 "register_operand" "q")))
6846 (match_operand:DI 3 "register_operand" "0")))]
6847 ; this can be generalized...!
6848 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6851 int x = INTVAL (operands[1]);
6852 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6853 return \"depdi 0,%%sar,%2,%0\";
6855 [(set_attr "type" "shift")
6856 (set_attr "length" "4")])
6858 (define_expand "ashrsi3"
6859 [(set (match_operand:SI 0 "register_operand" "")
6860 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6861 (match_operand:SI 2 "arith32_operand" "")))]
6865 if (GET_CODE (operands[2]) != CONST_INT)
6867 rtx temp = gen_reg_rtx (SImode);
6868 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6869 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6875 [(set (match_operand:SI 0 "register_operand" "=r")
6876 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6877 (match_operand:SI 2 "const_int_operand" "n")))]
6879 "{extrs|extrw,s} %1,%P2,%L2,%0"
6880 [(set_attr "type" "shift")
6881 (set_attr "length" "4")])
6883 (define_insn "vextrs32"
6884 [(set (match_operand:SI 0 "register_operand" "=r")
6885 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6886 (minus:SI (const_int 31)
6887 (match_operand:SI 2 "register_operand" "q"))))]
6889 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6890 [(set_attr "type" "shift")
6891 (set_attr "length" "4")])
6893 (define_expand "ashrdi3"
6894 [(set (match_operand:DI 0 "register_operand" "")
6895 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6896 (match_operand:DI 2 "arith32_operand" "")))]
6900 if (GET_CODE (operands[2]) != CONST_INT)
6902 rtx temp = gen_reg_rtx (DImode);
6903 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6904 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6910 [(set (match_operand:DI 0 "register_operand" "=r")
6911 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6912 (match_operand:DI 2 "const_int_operand" "n")))]
6914 "extrd,s %1,%p2,%Q2,%0"
6915 [(set_attr "type" "shift")
6916 (set_attr "length" "4")])
6918 (define_insn "vextrs64"
6919 [(set (match_operand:DI 0 "register_operand" "=r")
6920 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6921 (minus:DI (const_int 63)
6922 (match_operand:DI 2 "register_operand" "q"))))]
6924 "extrd,s %1,%%sar,64,%0"
6925 [(set_attr "type" "shift")
6926 (set_attr "length" "4")])
6928 (define_insn "lshrsi3"
6929 [(set (match_operand:SI 0 "register_operand" "=r,r")
6930 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6931 (match_operand:SI 2 "arith32_operand" "q,n")))]
6934 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6935 {extru|extrw,u} %1,%P2,%L2,%0"
6936 [(set_attr "type" "shift")
6937 (set_attr "length" "4")])
6939 (define_insn "lshrdi3"
6940 [(set (match_operand:DI 0 "register_operand" "=r,r")
6941 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6942 (match_operand:DI 2 "arith32_operand" "q,n")))]
6945 shrpd %%r0,%1,%%sar,%0
6946 extrd,u %1,%p2,%Q2,%0"
6947 [(set_attr "type" "shift")
6948 (set_attr "length" "4")])
6950 (define_insn "rotrsi3"
6951 [(set (match_operand:SI 0 "register_operand" "=r,r")
6952 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6953 (match_operand:SI 2 "arith32_operand" "q,n")))]
6957 if (GET_CODE (operands[2]) == CONST_INT)
6959 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6960 return \"{shd|shrpw} %1,%1,%2,%0\";
6963 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6965 [(set_attr "type" "shift")
6966 (set_attr "length" "4")])
6968 (define_expand "rotlsi3"
6969 [(set (match_operand:SI 0 "register_operand" "")
6970 (rotate:SI (match_operand:SI 1 "register_operand" "")
6971 (match_operand:SI 2 "arith32_operand" "")))]
6975 if (GET_CODE (operands[2]) != CONST_INT)
6977 rtx temp = gen_reg_rtx (SImode);
6978 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6979 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6982 /* Else expand normally. */
6986 [(set (match_operand:SI 0 "register_operand" "=r")
6987 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6988 (match_operand:SI 2 "const_int_operand" "n")))]
6992 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6993 return \"{shd|shrpw} %1,%1,%2,%0\";
6995 [(set_attr "type" "shift")
6996 (set_attr "length" "4")])
6999 [(set (match_operand:SI 0 "register_operand" "=r")
7000 (match_operator:SI 5 "plus_xor_ior_operator"
7001 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7002 (match_operand:SI 3 "const_int_operand" "n"))
7003 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7004 (match_operand:SI 4 "const_int_operand" "n"))]))]
7005 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7006 "{shd|shrpw} %1,%2,%4,%0"
7007 [(set_attr "type" "shift")
7008 (set_attr "length" "4")])
7011 [(set (match_operand:SI 0 "register_operand" "=r")
7012 (match_operator:SI 5 "plus_xor_ior_operator"
7013 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7014 (match_operand:SI 4 "const_int_operand" "n"))
7015 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7016 (match_operand:SI 3 "const_int_operand" "n"))]))]
7017 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7018 "{shd|shrpw} %1,%2,%4,%0"
7019 [(set_attr "type" "shift")
7020 (set_attr "length" "4")])
7023 [(set (match_operand:SI 0 "register_operand" "=r")
7024 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7025 (match_operand:SI 2 "const_int_operand" ""))
7026 (match_operand:SI 3 "const_int_operand" "")))]
7027 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
7030 int cnt = INTVAL (operands[2]) & 31;
7031 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7032 operands[2] = GEN_INT (31 - cnt);
7033 return \"{zdep|depw,z} %1,%2,%3,%0\";
7035 [(set_attr "type" "shift")
7036 (set_attr "length" "4")])
7038 ;; Unconditional and other jump instructions.
7040 ;; This can only be used in a leaf function, so we do
7041 ;; not need to use the PIC register when generating PIC code.
7042 (define_insn "return"
7046 "hppa_can_use_return_insn_p ()"
7050 return \"bve%* (%%r2)\";
7051 return \"bv%* %%r0(%%r2)\";
7053 [(set_attr "type" "branch")
7054 (set_attr "length" "4")])
7056 ;; Emit a different pattern for functions which have non-trivial
7057 ;; epilogues so as not to confuse jump and reorg.
7058 (define_insn "return_internal"
7066 return \"bve%* (%%r2)\";
7067 return \"bv%* %%r0(%%r2)\";
7069 [(set_attr "type" "branch")
7070 (set_attr "length" "4")])
7072 ;; This is used for eh returns which bypass the return stub.
7073 (define_insn "return_external_pic"
7075 (clobber (reg:SI 1))
7077 "!TARGET_NO_SPACE_REGS
7079 && flag_pic && current_function_calls_eh_return"
7080 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7081 [(set_attr "type" "branch")
7082 (set_attr "length" "12")])
7084 (define_expand "prologue"
7087 "hppa_expand_prologue ();DONE;")
7089 (define_expand "sibcall_epilogue"
7094 hppa_expand_epilogue ();
7098 (define_expand "epilogue"
7103 /* Try to use the trivial return first. Else use the full
7105 if (hppa_can_use_return_insn_p ())
7106 emit_jump_insn (gen_return ());
7111 hppa_expand_epilogue ();
7113 /* EH returns bypass the normal return stub. Thus, we must do an
7114 interspace branch to return from functions that call eh_return.
7115 This is only a problem for returns from shared code on ports
7116 using space registers. */
7117 if (!TARGET_NO_SPACE_REGS
7119 && flag_pic && current_function_calls_eh_return)
7120 x = gen_return_external_pic ();
7122 x = gen_return_internal ();
7129 ; Used by hppa_profile_hook to load the starting address of the current
7130 ; function; operand 1 contains the address of the label in operand 3
7131 (define_insn "load_offset_label_address"
7132 [(set (match_operand:SI 0 "register_operand" "=r")
7133 (plus:SI (match_operand:SI 1 "register_operand" "r")
7134 (minus:SI (match_operand:SI 2 "" "")
7135 (label_ref:SI (match_operand 3 "" "")))))]
7138 [(set_attr "type" "multi")
7139 (set_attr "length" "4")])
7141 ; Output a code label and load its address.
7142 (define_insn "lcla1"
7143 [(set (match_operand:SI 0 "register_operand" "=r")
7144 (label_ref:SI (match_operand 1 "" "")))
7149 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7150 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7151 CODE_LABEL_NUMBER (operands[1]));
7154 [(set_attr "type" "multi")
7155 (set_attr "length" "8")])
7157 (define_insn "lcla2"
7158 [(set (match_operand:SI 0 "register_operand" "=r")
7159 (label_ref:SI (match_operand 1 "" "")))
7164 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7165 CODE_LABEL_NUMBER (operands[1]));
7168 [(set_attr "type" "move")
7169 (set_attr "length" "4")])
7171 (define_insn "blockage"
7172 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7175 [(set_attr "length" "0")])
7178 [(set (pc) (label_ref (match_operand 0 "" "")))]
7182 /* An unconditional branch which can reach its target. */
7183 if (get_attr_length (insn) < 16)
7186 return output_lbranch (operands[0], insn, 1);
7188 [(set_attr "type" "uncond_branch")
7189 (set_attr "pa_combine_type" "uncond_branch")
7190 (set (attr "length")
7191 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7192 (if_then_else (lt (abs (minus (match_dup 0)
7193 (plus (pc) (const_int 8))))
7194 (const_int MAX_12BIT_OFFSET))
7197 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7198 (const_int MAX_17BIT_OFFSET))
7200 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7202 (eq (symbol_ref "flag_pic") (const_int 0))
7206 ;;; Hope this is only within a function...
7207 (define_insn "indirect_jump"
7208 [(set (pc) (match_operand 0 "register_operand" "r"))]
7209 "GET_MODE (operands[0]) == word_mode"
7211 [(set_attr "type" "branch")
7212 (set_attr "length" "4")])
7214 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7215 ;;; SOM target doesn't allow branching to a label inside a function.
7216 ;;; We also don't correctly compute branch distances for labels
7217 ;;; outside the current function. Thus, we use an indirect jump can't
7218 ;;; be optimized to a direct jump for all targets. We assume that
7219 ;;; the branch target is in the same space (i.e., nested function
7220 ;;; jumping to a label in an outer function in the same translation
7222 (define_expand "nonlocal_goto"
7223 [(use (match_operand 0 "general_operand" ""))
7224 (use (match_operand 1 "general_operand" ""))
7225 (use (match_operand 2 "general_operand" ""))
7226 (use (match_operand 3 "general_operand" ""))]
7229 rtx lab = operands[1];
7230 rtx stack = operands[2];
7231 rtx fp = operands[3];
7233 lab = copy_to_reg (lab);
7235 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7236 gen_rtx_MEM (BLKmode,
7237 gen_rtx_SCRATCH (VOIDmode))));
7238 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7239 gen_rtx_MEM (BLKmode,
7240 hard_frame_pointer_rtx)));
7242 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7243 instead of the hard_frame_pointer_rtx in the save area. As a
7244 result, an extra instruction is needed to adjust for the offset
7245 of the virtual stack variables and the frame pointer. */
7246 if (GET_CODE (fp) != REG)
7247 fp = force_reg (Pmode, fp);
7248 emit_move_insn (virtual_stack_vars_rtx, fp);
7250 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7252 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7253 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7255 /* Nonlocal goto jumps are only used between functions in the same
7256 translation unit. Thus, we can avoid the extra overhead of an
7258 emit_jump_insn (gen_indirect_goto (lab));
7263 (define_insn "indirect_goto"
7264 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7265 "GET_MODE (operands[0]) == word_mode"
7267 [(set_attr "type" "branch")
7268 (set_attr "length" "4")])
7270 ;;; This jump is used in branch tables where the insn length is fixed.
7271 ;;; The length of this insn is adjusted if the delay slot is not filled.
7272 (define_insn "short_jump"
7273 [(set (pc) (label_ref (match_operand 0 "" "")))
7277 [(set_attr "type" "btable_branch")
7278 (set_attr "length" "4")])
7280 ;; Subroutines of "casesi".
7281 ;; operand 0 is index
7282 ;; operand 1 is the minimum bound
7283 ;; operand 2 is the maximum bound - minimum bound + 1
7284 ;; operand 3 is CODE_LABEL for the table;
7285 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7287 (define_expand "casesi"
7288 [(match_operand:SI 0 "general_operand" "")
7289 (match_operand:SI 1 "const_int_operand" "")
7290 (match_operand:SI 2 "const_int_operand" "")
7291 (match_operand 3 "" "")
7292 (match_operand 4 "" "")]
7296 if (GET_CODE (operands[0]) != REG)
7297 operands[0] = force_reg (SImode, operands[0]);
7299 if (operands[1] != const0_rtx)
7301 rtx index = gen_reg_rtx (SImode);
7303 operands[1] = GEN_INT (-INTVAL (operands[1]));
7304 if (!INT_14_BITS (operands[1]))
7305 operands[1] = force_reg (SImode, operands[1]);
7306 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7307 operands[0] = index;
7310 /* In 64bit mode we must make sure to wipe the upper bits of the register
7311 just in case the addition overflowed or we had random bits in the
7312 high part of the register. */
7315 rtx index = gen_reg_rtx (DImode);
7317 emit_insn (gen_extendsidi2 (index, operands[0]));
7318 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7321 if (!INT_5_BITS (operands[2]))
7322 operands[2] = force_reg (SImode, operands[2]);
7324 /* This branch prevents us finding an insn for the delay slot of the
7325 following vectored branch. It might be possible to use the delay
7326 slot if an index value of -1 was used to transfer to the out-of-range
7327 label. In order to do this, we would have to output the -1 vector
7328 element after the delay insn. The casesi output code would have to
7329 check if the casesi insn is in a delay branch sequence and output
7330 the delay insn if one is found. If this was done, then it might
7331 then be worthwhile to split the casesi patterns to improve scheduling.
7332 However, it's not clear that all this extra complexity is worth
7334 emit_insn (gen_cmpsi (operands[0], operands[2]));
7335 emit_jump_insn (gen_bgtu (operands[4]));
7337 if (TARGET_BIG_SWITCH)
7341 rtx tmp1 = gen_reg_rtx (DImode);
7342 rtx tmp2 = gen_reg_rtx (DImode);
7344 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
7349 rtx tmp1 = gen_reg_rtx (SImode);
7353 rtx tmp2 = gen_reg_rtx (SImode);
7355 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
7359 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
7363 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7367 ;;; The rtl for this pattern doesn't accurately describe what the insn
7368 ;;; actually does, particularly when case-vector elements are exploded
7369 ;;; in pa_reorg. However, the initial SET in these patterns must show
7370 ;;; the connection of the insn to the following jump table.
7371 (define_insn "casesi0"
7372 [(set (pc) (mem:SI (plus:SI
7373 (mult:SI (match_operand:SI 0 "register_operand" "r")
7375 (label_ref (match_operand 1 "" "")))))]
7377 "blr,n %0,%%r0\;nop"
7378 [(set_attr "type" "multi")
7379 (set_attr "length" "8")])
7381 ;;; 32-bit code, absolute branch table.
7382 (define_insn "casesi32"
7383 [(set (pc) (mem:SI (plus:SI
7384 (mult:SI (match_operand:SI 0 "register_operand" "r")
7386 (label_ref (match_operand 1 "" "")))))
7387 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
7388 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7389 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7390 [(set_attr "type" "multi")
7391 (set_attr "length" "16")])
7393 ;;; 32-bit code, relative branch table.
7394 (define_insn "casesi32p"
7395 [(set (pc) (mem:SI (plus:SI
7396 (mult:SI (match_operand:SI 0 "register_operand" "r")
7398 (label_ref (match_operand 1 "" "")))))
7399 (clobber (match_operand:SI 2 "register_operand" "=&a"))
7400 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
7401 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7402 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7403 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7404 [(set_attr "type" "multi")
7405 (set (attr "length")
7406 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7410 ;;; 64-bit code, 32-bit relative branch table.
7411 (define_insn "casesi64p"
7412 [(set (pc) (mem:DI (plus:DI
7413 (mult:DI (sign_extend:DI
7414 (match_operand:SI 0 "register_operand" "r"))
7416 (label_ref (match_operand 1 "" "")))))
7417 (clobber (match_operand:DI 2 "register_operand" "=&r"))
7418 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
7419 "TARGET_64BIT && TARGET_BIG_SWITCH"
7420 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7421 add,l %2,%3,%3\;bv,n %%r0(%3)"
7422 [(set_attr "type" "multi")
7423 (set_attr "length" "24")])
7427 ;;- jump to subroutine
7429 (define_expand "call"
7430 [(parallel [(call (match_operand:SI 0 "" "")
7431 (match_operand 1 "" ""))
7432 (clobber (reg:SI 2))])]
7437 rtx nb = operands[1];
7439 if (TARGET_PORTABLE_RUNTIME)
7440 op = force_reg (SImode, XEXP (operands[0], 0));
7442 op = XEXP (operands[0], 0);
7446 if (!virtuals_instantiated)
7447 emit_move_insn (arg_pointer_rtx,
7448 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7452 /* The loop pass can generate new libcalls after the virtual
7453 registers are instantiated when fpregs are disabled because
7454 the only method that we have for doing DImode multiplication
7455 is with a libcall. This could be trouble if we haven't
7456 allocated enough space for the outgoing arguments. */
7457 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7459 emit_move_insn (arg_pointer_rtx,
7460 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7461 GEN_INT (STACK_POINTER_OFFSET + 64)));
7465 /* Use two different patterns for calls to explicitly named functions
7466 and calls through function pointers. This is necessary as these two
7467 types of calls use different calling conventions, and CSE might try
7468 to change the named call into an indirect call in some cases (using
7469 two patterns keeps CSE from performing this optimization).
7471 We now use even more call patterns as there was a subtle bug in
7472 attempting to restore the pic register after a call using a simple
7473 move insn. During reload, a instruction involving a pseudo register
7474 with no explicit dependence on the PIC register can be converted
7475 to an equivalent load from memory using the PIC register. If we
7476 emit a simple move to restore the PIC register in the initial rtl
7477 generation, then it can potentially be repositioned during scheduling.
7478 and an instruction that eventually uses the PIC register may end up
7479 between the call and the PIC register restore.
7481 This only worked because there is a post call group of instructions
7482 that are scheduled with the call. These instructions are included
7483 in the same basic block as the call. However, calls can throw in
7484 C++ code and a basic block has to terminate at the call if the call
7485 can throw. This results in the PIC register restore being scheduled
7486 independently from the call. So, we now hide the save and restore
7487 of the PIC register in the call pattern until after reload. Then,
7488 we split the moves out. A small side benefit is that we now don't
7489 need to have a use of the PIC register in the return pattern and
7490 the final save/restore operation is not needed.
7492 I elected to just clobber %r4 in the PIC patterns and use it instead
7493 of trying to force hppa_pic_save_rtx () to a callee saved register.
7494 This might have required a new register class and constraint. It
7495 was also simpler to just handle the restore from a register than a
7499 if (GET_CODE (op) == SYMBOL_REF)
7500 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7503 op = force_reg (word_mode, op);
7504 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7509 if (GET_CODE (op) == SYMBOL_REF)
7512 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7514 call_insn = emit_call_insn (gen_call_symref (op, nb));
7518 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7520 emit_move_insn (tmpreg, force_reg (word_mode, op));
7522 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7524 call_insn = emit_call_insn (gen_call_reg (nb));
7531 ;; We use function calls to set the attribute length of calls and millicode
7532 ;; calls. This is necessary because of the large variety of call sequences.
7533 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7534 ;; we need the same calculation in several places, maintenance becomes a
7537 ;; However, this has a subtle impact on branch shortening. When the
7538 ;; expression used to set the length attribute of an instruction depends
7539 ;; on a relative address (e.g., pc or a branch address), genattrtab
7540 ;; notes that the insn's length is variable, and attempts to determine a
7541 ;; worst-case default length and code to compute an insn's current length.
7543 ;; The use of a function call hides the variable dependence of our calls
7544 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7545 ;; as variable and it only generates code for the default case using our
7546 ;; function call. Because of this, calls and millicode calls have a fixed
7547 ;; length in the branch shortening pass, and some branches will use a longer
7548 ;; code sequence than necessary. However, the length of any given call
7549 ;; will still reflect its final code location and it may be shorter than
7550 ;; the initial length estimate.
7552 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7553 ;; in the set. However, when genattrtab hits a function call in its attempt
7554 ;; to compute the default length, it marks the result as unknown and sets
7555 ;; the default result to MAX_INT ;-( One possible fix that would allow
7556 ;; calls to participate in branch shortening would be to make the call to
7557 ;; insn_default_length a target option. Then, we could massage unknown
7558 ;; results. Another fix might be to change genattrtab so that it just does
7559 ;; the call in the variable case as it already does for the fixed case.
7561 (define_insn "call_symref"
7562 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7563 (match_operand 1 "" "i"))
7564 (clobber (reg:SI 1))
7565 (clobber (reg:SI 2))
7566 (use (const_int 0))]
7567 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7570 output_arg_descriptor (insn);
7571 return output_call (insn, operands[0], 0);
7573 [(set_attr "type" "call")
7574 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7576 (define_insn "call_symref_pic"
7577 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7578 (match_operand 1 "" "i"))
7579 (clobber (reg:SI 1))
7580 (clobber (reg:SI 2))
7581 (clobber (reg:SI 4))
7583 (use (const_int 0))]
7584 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7587 output_arg_descriptor (insn);
7588 return output_call (insn, operands[0], 0);
7590 [(set_attr "type" "call")
7591 (set (attr "length")
7592 (plus (symbol_ref "attr_length_call (insn, 0)")
7593 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7595 ;; Split out the PIC register save and restore after reload. This is
7596 ;; done only if the function returns. As the split is done after reload,
7597 ;; there are some situations in which we unnecessarily save and restore
7598 ;; %r4. This happens when there is a single call and the PIC register
7599 ;; is "dead" after the call. This isn't easy to fix as the usage of
7600 ;; the PIC register isn't completely determined until the reload pass.
7602 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7603 (match_operand 1 "" ""))
7604 (clobber (reg:SI 1))
7605 (clobber (reg:SI 2))
7606 (clobber (reg:SI 4))
7608 (use (const_int 0))])]
7609 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7611 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7612 [(set (reg:SI 4) (reg:SI 19))
7613 (parallel [(call (mem:SI (match_dup 0))
7615 (clobber (reg:SI 1))
7616 (clobber (reg:SI 2))
7618 (use (const_int 0))])
7619 (set (reg:SI 19) (reg:SI 4))]
7622 ;; Remove the clobber of register 4 when optimizing. This has to be
7623 ;; done with a peephole optimization rather than a split because the
7624 ;; split sequence for a call must be longer than one instruction.
7626 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7627 (match_operand 1 "" ""))
7628 (clobber (reg:SI 1))
7629 (clobber (reg:SI 2))
7630 (clobber (reg:SI 4))
7632 (use (const_int 0))])]
7633 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7634 [(parallel [(call (mem:SI (match_dup 0))
7636 (clobber (reg:SI 1))
7637 (clobber (reg:SI 2))
7639 (use (const_int 0))])]
7642 (define_insn "*call_symref_pic_post_reload"
7643 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7644 (match_operand 1 "" "i"))
7645 (clobber (reg:SI 1))
7646 (clobber (reg:SI 2))
7648 (use (const_int 0))]
7649 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7652 output_arg_descriptor (insn);
7653 return output_call (insn, operands[0], 0);
7655 [(set_attr "type" "call")
7656 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7658 ;; This pattern is split if it is necessary to save and restore the
7660 (define_insn "call_symref_64bit"
7661 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7662 (match_operand 1 "" "i"))
7663 (clobber (reg:DI 1))
7664 (clobber (reg:DI 2))
7665 (clobber (reg:DI 4))
7668 (use (const_int 0))]
7672 output_arg_descriptor (insn);
7673 return output_call (insn, operands[0], 0);
7675 [(set_attr "type" "call")
7676 (set (attr "length")
7677 (plus (symbol_ref "attr_length_call (insn, 0)")
7678 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7680 ;; Split out the PIC register save and restore after reload. This is
7681 ;; done only if the function returns. As the split is done after reload,
7682 ;; there are some situations in which we unnecessarily save and restore
7683 ;; %r4. This happens when there is a single call and the PIC register
7684 ;; is "dead" after the call. This isn't easy to fix as the usage of
7685 ;; the PIC register isn't completely determined until the reload pass.
7687 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7688 (match_operand 1 "" ""))
7689 (clobber (reg:DI 1))
7690 (clobber (reg:DI 2))
7691 (clobber (reg:DI 4))
7694 (use (const_int 0))])]
7697 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7698 [(set (reg:DI 4) (reg:DI 27))
7699 (parallel [(call (mem:SI (match_dup 0))
7701 (clobber (reg:DI 1))
7702 (clobber (reg:DI 2))
7705 (use (const_int 0))])
7706 (set (reg:DI 27) (reg:DI 4))]
7709 ;; Remove the clobber of register 4 when optimizing. This has to be
7710 ;; done with a peephole optimization rather than a split because the
7711 ;; split sequence for a call must be longer than one instruction.
7713 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7714 (match_operand 1 "" ""))
7715 (clobber (reg:DI 1))
7716 (clobber (reg:DI 2))
7717 (clobber (reg:DI 4))
7720 (use (const_int 0))])]
7721 "TARGET_64BIT && reload_completed"
7722 [(parallel [(call (mem:SI (match_dup 0))
7724 (clobber (reg:DI 1))
7725 (clobber (reg:DI 2))
7728 (use (const_int 0))])]
7731 (define_insn "*call_symref_64bit_post_reload"
7732 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7733 (match_operand 1 "" "i"))
7734 (clobber (reg:DI 1))
7735 (clobber (reg:DI 2))
7738 (use (const_int 0))]
7742 output_arg_descriptor (insn);
7743 return output_call (insn, operands[0], 0);
7745 [(set_attr "type" "call")
7746 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7748 (define_insn "call_reg"
7749 [(call (mem:SI (reg:SI 22))
7750 (match_operand 0 "" "i"))
7751 (clobber (reg:SI 1))
7752 (clobber (reg:SI 2))
7753 (use (const_int 1))]
7757 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7759 [(set_attr "type" "dyncall")
7760 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7762 ;; This pattern is split if it is necessary to save and restore the
7764 (define_insn "call_reg_pic"
7765 [(call (mem:SI (reg:SI 22))
7766 (match_operand 0 "" "i"))
7767 (clobber (reg:SI 1))
7768 (clobber (reg:SI 2))
7769 (clobber (reg:SI 4))
7771 (use (const_int 1))]
7775 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7777 [(set_attr "type" "dyncall")
7778 (set (attr "length")
7779 (plus (symbol_ref "attr_length_indirect_call (insn)")
7780 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7782 ;; Split out the PIC register save and restore after reload. This is
7783 ;; done only if the function returns. As the split is done after reload,
7784 ;; there are some situations in which we unnecessarily save and restore
7785 ;; %r4. This happens when there is a single call and the PIC register
7786 ;; is "dead" after the call. This isn't easy to fix as the usage of
7787 ;; the PIC register isn't completely determined until the reload pass.
7789 [(parallel [(call (mem:SI (reg:SI 22))
7790 (match_operand 0 "" ""))
7791 (clobber (reg:SI 1))
7792 (clobber (reg:SI 2))
7793 (clobber (reg:SI 4))
7795 (use (const_int 1))])]
7798 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7799 [(set (reg:SI 4) (reg:SI 19))
7800 (parallel [(call (mem:SI (reg:SI 22))
7802 (clobber (reg:SI 1))
7803 (clobber (reg:SI 2))
7805 (use (const_int 1))])
7806 (set (reg:SI 19) (reg:SI 4))]
7809 ;; Remove the clobber of register 4 when optimizing. This has to be
7810 ;; done with a peephole optimization rather than a split because the
7811 ;; split sequence for a call must be longer than one instruction.
7813 [(parallel [(call (mem:SI (reg:SI 22))
7814 (match_operand 0 "" ""))
7815 (clobber (reg:SI 1))
7816 (clobber (reg:SI 2))
7817 (clobber (reg:SI 4))
7819 (use (const_int 1))])]
7820 "!TARGET_64BIT && reload_completed"
7821 [(parallel [(call (mem:SI (reg:SI 22))
7823 (clobber (reg:SI 1))
7824 (clobber (reg:SI 2))
7826 (use (const_int 1))])]
7829 (define_insn "*call_reg_pic_post_reload"
7830 [(call (mem:SI (reg:SI 22))
7831 (match_operand 0 "" "i"))
7832 (clobber (reg:SI 1))
7833 (clobber (reg:SI 2))
7835 (use (const_int 1))]
7839 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7841 [(set_attr "type" "dyncall")
7842 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7844 ;; This pattern is split if it is necessary to save and restore the
7846 (define_insn "call_reg_64bit"
7847 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7848 (match_operand 1 "" "i"))
7849 (clobber (reg:DI 2))
7850 (clobber (reg:DI 4))
7853 (use (const_int 1))]
7857 return output_indirect_call (insn, operands[0]);
7859 [(set_attr "type" "dyncall")
7860 (set (attr "length")
7861 (plus (symbol_ref "attr_length_indirect_call (insn)")
7862 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7864 ;; Split out the PIC register save and restore after reload. This is
7865 ;; done only if the function returns. As the split is done after reload,
7866 ;; there are some situations in which we unnecessarily save and restore
7867 ;; %r4. This happens when there is a single call and the PIC register
7868 ;; is "dead" after the call. This isn't easy to fix as the usage of
7869 ;; the PIC register isn't completely determined until the reload pass.
7871 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7872 (match_operand 1 "" ""))
7873 (clobber (reg:DI 2))
7874 (clobber (reg:DI 4))
7877 (use (const_int 1))])]
7880 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7881 [(set (reg:DI 4) (reg:DI 27))
7882 (parallel [(call (mem:SI (match_dup 0))
7884 (clobber (reg:DI 2))
7887 (use (const_int 1))])
7888 (set (reg:DI 27) (reg:DI 4))]
7891 ;; Remove the clobber of register 4 when optimizing. This has to be
7892 ;; done with a peephole optimization rather than a split because the
7893 ;; split sequence for a call must be longer than one instruction.
7895 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7896 (match_operand 1 "" ""))
7897 (clobber (reg:DI 2))
7898 (clobber (reg:DI 4))
7901 (use (const_int 1))])]
7902 "TARGET_64BIT && reload_completed"
7903 [(parallel [(call (mem:SI (match_dup 0))
7905 (clobber (reg:DI 2))
7908 (use (const_int 1))])]
7911 (define_insn "*call_reg_64bit_post_reload"
7912 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7913 (match_operand 1 "" "i"))
7914 (clobber (reg:DI 2))
7917 (use (const_int 1))]
7921 return output_indirect_call (insn, operands[0]);
7923 [(set_attr "type" "dyncall")
7924 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7926 (define_expand "call_value"
7927 [(parallel [(set (match_operand 0 "" "")
7928 (call (match_operand:SI 1 "" "")
7929 (match_operand 2 "" "")))
7930 (clobber (reg:SI 2))])]
7935 rtx dst = operands[0];
7936 rtx nb = operands[2];
7938 if (TARGET_PORTABLE_RUNTIME)
7939 op = force_reg (SImode, XEXP (operands[1], 0));
7941 op = XEXP (operands[1], 0);
7945 if (!virtuals_instantiated)
7946 emit_move_insn (arg_pointer_rtx,
7947 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7951 /* The loop pass can generate new libcalls after the virtual
7952 registers are instantiated when fpregs are disabled because
7953 the only method that we have for doing DImode multiplication
7954 is with a libcall. This could be trouble if we haven't
7955 allocated enough space for the outgoing arguments. */
7956 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7958 emit_move_insn (arg_pointer_rtx,
7959 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7960 GEN_INT (STACK_POINTER_OFFSET + 64)));
7964 /* Use two different patterns for calls to explicitly named functions
7965 and calls through function pointers. This is necessary as these two
7966 types of calls use different calling conventions, and CSE might try
7967 to change the named call into an indirect call in some cases (using
7968 two patterns keeps CSE from performing this optimization).
7970 We now use even more call patterns as there was a subtle bug in
7971 attempting to restore the pic register after a call using a simple
7972 move insn. During reload, a instruction involving a pseudo register
7973 with no explicit dependence on the PIC register can be converted
7974 to an equivalent load from memory using the PIC register. If we
7975 emit a simple move to restore the PIC register in the initial rtl
7976 generation, then it can potentially be repositioned during scheduling.
7977 and an instruction that eventually uses the PIC register may end up
7978 between the call and the PIC register restore.
7980 This only worked because there is a post call group of instructions
7981 that are scheduled with the call. These instructions are included
7982 in the same basic block as the call. However, calls can throw in
7983 C++ code and a basic block has to terminate at the call if the call
7984 can throw. This results in the PIC register restore being scheduled
7985 independently from the call. So, we now hide the save and restore
7986 of the PIC register in the call pattern until after reload. Then,
7987 we split the moves out. A small side benefit is that we now don't
7988 need to have a use of the PIC register in the return pattern and
7989 the final save/restore operation is not needed.
7991 I elected to just clobber %r4 in the PIC patterns and use it instead
7992 of trying to force hppa_pic_save_rtx () to a callee saved register.
7993 This might have required a new register class and constraint. It
7994 was also simpler to just handle the restore from a register than a
7998 if (GET_CODE (op) == SYMBOL_REF)
7999 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8002 op = force_reg (word_mode, op);
8003 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8008 if (GET_CODE (op) == SYMBOL_REF)
8011 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8013 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8017 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8019 emit_move_insn (tmpreg, force_reg (word_mode, op));
8021 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8023 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8030 (define_insn "call_val_symref"
8031 [(set (match_operand 0 "" "")
8032 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8033 (match_operand 2 "" "i")))
8034 (clobber (reg:SI 1))
8035 (clobber (reg:SI 2))
8036 (use (const_int 0))]
8037 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8040 output_arg_descriptor (insn);
8041 return output_call (insn, operands[1], 0);
8043 [(set_attr "type" "call")
8044 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8046 (define_insn "call_val_symref_pic"
8047 [(set (match_operand 0 "" "")
8048 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8049 (match_operand 2 "" "i")))
8050 (clobber (reg:SI 1))
8051 (clobber (reg:SI 2))
8052 (clobber (reg:SI 4))
8054 (use (const_int 0))]
8055 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8058 output_arg_descriptor (insn);
8059 return output_call (insn, operands[1], 0);
8061 [(set_attr "type" "call")
8062 (set (attr "length")
8063 (plus (symbol_ref "attr_length_call (insn, 0)")
8064 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8066 ;; Split out the PIC register save and restore after reload. This is
8067 ;; done only if the function returns. As the split is done after reload,
8068 ;; there are some situations in which we unnecessarily save and restore
8069 ;; %r4. This happens when there is a single call and the PIC register
8070 ;; is "dead" after the call. This isn't easy to fix as the usage of
8071 ;; the PIC register isn't completely determined until the reload pass.
8073 [(parallel [(set (match_operand 0 "" "")
8074 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8075 (match_operand 2 "" "")))
8076 (clobber (reg:SI 1))
8077 (clobber (reg:SI 2))
8078 (clobber (reg:SI 4))
8080 (use (const_int 0))])]
8081 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8083 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8084 [(set (reg:SI 4) (reg:SI 19))
8085 (parallel [(set (match_dup 0)
8086 (call (mem:SI (match_dup 1))
8088 (clobber (reg:SI 1))
8089 (clobber (reg:SI 2))
8091 (use (const_int 0))])
8092 (set (reg:SI 19) (reg:SI 4))]
8095 ;; Remove the clobber of register 4 when optimizing. This has to be
8096 ;; done with a peephole optimization rather than a split because the
8097 ;; split sequence for a call must be longer than one instruction.
8099 [(parallel [(set (match_operand 0 "" "")
8100 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8101 (match_operand 2 "" "")))
8102 (clobber (reg:SI 1))
8103 (clobber (reg:SI 2))
8104 (clobber (reg:SI 4))
8106 (use (const_int 0))])]
8107 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8108 [(parallel [(set (match_dup 0)
8109 (call (mem:SI (match_dup 1))
8111 (clobber (reg:SI 1))
8112 (clobber (reg:SI 2))
8114 (use (const_int 0))])]
8117 (define_insn "*call_val_symref_pic_post_reload"
8118 [(set (match_operand 0 "" "")
8119 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8120 (match_operand 2 "" "i")))
8121 (clobber (reg:SI 1))
8122 (clobber (reg:SI 2))
8124 (use (const_int 0))]
8125 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8128 output_arg_descriptor (insn);
8129 return output_call (insn, operands[1], 0);
8131 [(set_attr "type" "call")
8132 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8134 ;; This pattern is split if it is necessary to save and restore the
8136 (define_insn "call_val_symref_64bit"
8137 [(set (match_operand 0 "" "")
8138 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8139 (match_operand 2 "" "i")))
8140 (clobber (reg:DI 1))
8141 (clobber (reg:DI 2))
8142 (clobber (reg:DI 4))
8145 (use (const_int 0))]
8149 output_arg_descriptor (insn);
8150 return output_call (insn, operands[1], 0);
8152 [(set_attr "type" "call")
8153 (set (attr "length")
8154 (plus (symbol_ref "attr_length_call (insn, 0)")
8155 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8157 ;; Split out the PIC register save and restore after reload. This is
8158 ;; done only if the function returns. As the split is done after reload,
8159 ;; there are some situations in which we unnecessarily save and restore
8160 ;; %r4. This happens when there is a single call and the PIC register
8161 ;; is "dead" after the call. This isn't easy to fix as the usage of
8162 ;; the PIC register isn't completely determined until the reload pass.
8164 [(parallel [(set (match_operand 0 "" "")
8165 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8166 (match_operand 2 "" "")))
8167 (clobber (reg:DI 1))
8168 (clobber (reg:DI 2))
8169 (clobber (reg:DI 4))
8172 (use (const_int 0))])]
8175 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8176 [(set (reg:DI 4) (reg:DI 27))
8177 (parallel [(set (match_dup 0)
8178 (call (mem:SI (match_dup 1))
8180 (clobber (reg:DI 1))
8181 (clobber (reg:DI 2))
8184 (use (const_int 0))])
8185 (set (reg:DI 27) (reg:DI 4))]
8188 ;; Remove the clobber of register 4 when optimizing. This has to be
8189 ;; done with a peephole optimization rather than a split because the
8190 ;; split sequence for a call must be longer than one instruction.
8192 [(parallel [(set (match_operand 0 "" "")
8193 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8194 (match_operand 2 "" "")))
8195 (clobber (reg:DI 1))
8196 (clobber (reg:DI 2))
8197 (clobber (reg:DI 4))
8200 (use (const_int 0))])]
8201 "TARGET_64BIT && reload_completed"
8202 [(parallel [(set (match_dup 0)
8203 (call (mem:SI (match_dup 1))
8205 (clobber (reg:DI 1))
8206 (clobber (reg:DI 2))
8209 (use (const_int 0))])]
8212 (define_insn "*call_val_symref_64bit_post_reload"
8213 [(set (match_operand 0 "" "")
8214 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8215 (match_operand 2 "" "i")))
8216 (clobber (reg:DI 1))
8217 (clobber (reg:DI 2))
8220 (use (const_int 0))]
8224 output_arg_descriptor (insn);
8225 return output_call (insn, operands[1], 0);
8227 [(set_attr "type" "call")
8228 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8230 (define_insn "call_val_reg"
8231 [(set (match_operand 0 "" "")
8232 (call (mem:SI (reg:SI 22))
8233 (match_operand 1 "" "i")))
8234 (clobber (reg:SI 1))
8235 (clobber (reg:SI 2))
8236 (use (const_int 1))]
8240 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8242 [(set_attr "type" "dyncall")
8243 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8245 ;; This pattern is split if it is necessary to save and restore the
8247 (define_insn "call_val_reg_pic"
8248 [(set (match_operand 0 "" "")
8249 (call (mem:SI (reg:SI 22))
8250 (match_operand 1 "" "i")))
8251 (clobber (reg:SI 1))
8252 (clobber (reg:SI 2))
8253 (clobber (reg:SI 4))
8255 (use (const_int 1))]
8259 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8261 [(set_attr "type" "dyncall")
8262 (set (attr "length")
8263 (plus (symbol_ref "attr_length_indirect_call (insn)")
8264 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8266 ;; Split out the PIC register save and restore after reload. This is
8267 ;; done only if the function returns. As the split is done after reload,
8268 ;; there are some situations in which we unnecessarily save and restore
8269 ;; %r4. This happens when there is a single call and the PIC register
8270 ;; is "dead" after the call. This isn't easy to fix as the usage of
8271 ;; the PIC register isn't completely determined until the reload pass.
8273 [(parallel [(set (match_operand 0 "" "")
8274 (call (mem:SI (reg:SI 22))
8275 (match_operand 1 "" "")))
8276 (clobber (reg:SI 1))
8277 (clobber (reg:SI 2))
8278 (clobber (reg:SI 4))
8280 (use (const_int 1))])]
8283 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8284 [(set (reg:SI 4) (reg:SI 19))
8285 (parallel [(set (match_dup 0)
8286 (call (mem:SI (reg:SI 22))
8288 (clobber (reg:SI 1))
8289 (clobber (reg:SI 2))
8291 (use (const_int 1))])
8292 (set (reg:SI 19) (reg:SI 4))]
8295 ;; Remove the clobber of register 4 when optimizing. This has to be
8296 ;; done with a peephole optimization rather than a split because the
8297 ;; split sequence for a call must be longer than one instruction.
8299 [(parallel [(set (match_operand 0 "" "")
8300 (call (mem:SI (reg:SI 22))
8301 (match_operand 1 "" "")))
8302 (clobber (reg:SI 1))
8303 (clobber (reg:SI 2))
8304 (clobber (reg:SI 4))
8306 (use (const_int 1))])]
8307 "!TARGET_64BIT && reload_completed"
8308 [(parallel [(set (match_dup 0)
8309 (call (mem:SI (reg:SI 22))
8311 (clobber (reg:SI 1))
8312 (clobber (reg:SI 2))
8314 (use (const_int 1))])]
8317 (define_insn "*call_val_reg_pic_post_reload"
8318 [(set (match_operand 0 "" "")
8319 (call (mem:SI (reg:SI 22))
8320 (match_operand 1 "" "i")))
8321 (clobber (reg:SI 1))
8322 (clobber (reg:SI 2))
8324 (use (const_int 1))]
8328 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8330 [(set_attr "type" "dyncall")
8331 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8333 ;; This pattern is split if it is necessary to save and restore the
8335 (define_insn "call_val_reg_64bit"
8336 [(set (match_operand 0 "" "")
8337 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8338 (match_operand 2 "" "i")))
8339 (clobber (reg:DI 2))
8340 (clobber (reg:DI 4))
8343 (use (const_int 1))]
8347 return output_indirect_call (insn, operands[1]);
8349 [(set_attr "type" "dyncall")
8350 (set (attr "length")
8351 (plus (symbol_ref "attr_length_indirect_call (insn)")
8352 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8354 ;; Split out the PIC register save and restore after reload. This is
8355 ;; done only if the function returns. As the split is done after reload,
8356 ;; there are some situations in which we unnecessarily save and restore
8357 ;; %r4. This happens when there is a single call and the PIC register
8358 ;; is "dead" after the call. This isn't easy to fix as the usage of
8359 ;; the PIC register isn't completely determined until the reload pass.
8361 [(parallel [(set (match_operand 0 "" "")
8362 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8363 (match_operand 2 "" "")))
8364 (clobber (reg:DI 2))
8365 (clobber (reg:DI 4))
8368 (use (const_int 1))])]
8371 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8372 [(set (reg:DI 4) (reg:DI 27))
8373 (parallel [(set (match_dup 0)
8374 (call (mem:SI (match_dup 1))
8376 (clobber (reg:DI 2))
8379 (use (const_int 1))])
8380 (set (reg:DI 27) (reg:DI 4))]
8383 ;; Remove the clobber of register 4 when optimizing. This has to be
8384 ;; done with a peephole optimization rather than a split because the
8385 ;; split sequence for a call must be longer than one instruction.
8387 [(parallel [(set (match_operand 0 "" "")
8388 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8389 (match_operand 2 "" "")))
8390 (clobber (reg:DI 2))
8391 (clobber (reg:DI 4))
8394 (use (const_int 1))])]
8395 "TARGET_64BIT && reload_completed"
8396 [(parallel [(set (match_dup 0)
8397 (call (mem:SI (match_dup 1))
8399 (clobber (reg:DI 2))
8402 (use (const_int 1))])]
8405 (define_insn "*call_val_reg_64bit_post_reload"
8406 [(set (match_operand 0 "" "")
8407 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8408 (match_operand 2 "" "i")))
8409 (clobber (reg:DI 2))
8412 (use (const_int 1))]
8416 return output_indirect_call (insn, operands[1]);
8418 [(set_attr "type" "dyncall")
8419 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8421 ;; Call subroutine returning any type.
8423 (define_expand "untyped_call"
8424 [(parallel [(call (match_operand 0 "" "")
8426 (match_operand 1 "" "")
8427 (match_operand 2 "" "")])]
8433 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8435 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8437 rtx set = XVECEXP (operands[2], 0, i);
8438 emit_move_insn (SET_DEST (set), SET_SRC (set));
8441 /* The optimizer does not know that the call sets the function value
8442 registers we stored in the result block. We avoid problems by
8443 claiming that all hard registers are used and clobbered at this
8445 emit_insn (gen_blockage ());
8450 (define_expand "sibcall"
8451 [(call (match_operand:SI 0 "" "")
8452 (match_operand 1 "" ""))]
8453 "!TARGET_PORTABLE_RUNTIME"
8457 rtx nb = operands[1];
8459 op = XEXP (operands[0], 0);
8463 if (!virtuals_instantiated)
8464 emit_move_insn (arg_pointer_rtx,
8465 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8469 /* The loop pass can generate new libcalls after the virtual
8470 registers are instantiated when fpregs are disabled because
8471 the only method that we have for doing DImode multiplication
8472 is with a libcall. This could be trouble if we haven't
8473 allocated enough space for the outgoing arguments. */
8474 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8476 emit_move_insn (arg_pointer_rtx,
8477 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8478 GEN_INT (STACK_POINTER_OFFSET + 64)));
8482 /* Indirect sibling calls are not allowed. */
8484 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8486 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8488 call_insn = emit_call_insn (call_insn);
8491 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8493 /* We don't have to restore the PIC register. */
8495 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8500 (define_insn "sibcall_internal_symref"
8501 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8502 (match_operand 1 "" "i"))
8503 (clobber (reg:SI 1))
8505 (use (const_int 0))]
8506 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8509 output_arg_descriptor (insn);
8510 return output_call (insn, operands[0], 1);
8512 [(set_attr "type" "call")
8513 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8515 (define_insn "sibcall_internal_symref_64bit"
8516 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8517 (match_operand 1 "" "i"))
8518 (clobber (reg:DI 1))
8520 (use (const_int 0))]
8524 output_arg_descriptor (insn);
8525 return output_call (insn, operands[0], 1);
8527 [(set_attr "type" "call")
8528 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8530 (define_expand "sibcall_value"
8531 [(set (match_operand 0 "" "")
8532 (call (match_operand:SI 1 "" "")
8533 (match_operand 2 "" "")))]
8534 "!TARGET_PORTABLE_RUNTIME"
8538 rtx nb = operands[1];
8540 op = XEXP (operands[1], 0);
8544 if (!virtuals_instantiated)
8545 emit_move_insn (arg_pointer_rtx,
8546 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8550 /* The loop pass can generate new libcalls after the virtual
8551 registers are instantiated when fpregs are disabled because
8552 the only method that we have for doing DImode multiplication
8553 is with a libcall. This could be trouble if we haven't
8554 allocated enough space for the outgoing arguments. */
8555 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8557 emit_move_insn (arg_pointer_rtx,
8558 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8559 GEN_INT (STACK_POINTER_OFFSET + 64)));
8563 /* Indirect sibling calls are not allowed. */
8566 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8569 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8571 call_insn = emit_call_insn (call_insn);
8574 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8576 /* We don't have to restore the PIC register. */
8578 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8583 (define_insn "sibcall_value_internal_symref"
8584 [(set (match_operand 0 "" "")
8585 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8586 (match_operand 2 "" "i")))
8587 (clobber (reg:SI 1))
8589 (use (const_int 0))]
8590 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8593 output_arg_descriptor (insn);
8594 return output_call (insn, operands[1], 1);
8596 [(set_attr "type" "call")
8597 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8599 (define_insn "sibcall_value_internal_symref_64bit"
8600 [(set (match_operand 0 "" "")
8601 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8602 (match_operand 2 "" "i")))
8603 (clobber (reg:DI 1))
8605 (use (const_int 0))]
8609 output_arg_descriptor (insn);
8610 return output_call (insn, operands[1], 1);
8612 [(set_attr "type" "call")
8613 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8619 [(set_attr "type" "move")
8620 (set_attr "length" "4")])
8622 ;; These are just placeholders so we know where branch tables
8624 (define_insn "begin_brtab"
8629 /* Only GAS actually supports this pseudo-op. */
8631 return \".begin_brtab\";
8635 [(set_attr "type" "move")
8636 (set_attr "length" "0")])
8638 (define_insn "end_brtab"
8643 /* Only GAS actually supports this pseudo-op. */
8645 return \".end_brtab\";
8649 [(set_attr "type" "move")
8650 (set_attr "length" "0")])
8652 ;;; EH does longjmp's from and within the data section. Thus,
8653 ;;; an interspace branch is required for the longjmp implementation.
8654 ;;; Registers r1 and r2 are used as scratch registers for the jump
8656 (define_expand "interspace_jump"
8658 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8659 (clobber (match_dup 1))])]
8663 operands[1] = gen_rtx_REG (word_mode, 2);
8667 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8668 (clobber (reg:SI 2))]
8669 "TARGET_PA_20 && !TARGET_64BIT"
8671 [(set_attr "type" "branch")
8672 (set_attr "length" "4")])
8675 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8676 (clobber (reg:SI 2))]
8677 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8679 [(set_attr "type" "branch")
8680 (set_attr "length" "4")])
8683 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8684 (clobber (reg:SI 2))]
8686 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8687 [(set_attr "type" "branch")
8688 (set_attr "length" "12")])
8691 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8692 (clobber (reg:DI 2))]
8695 [(set_attr "type" "branch")
8696 (set_attr "length" "4")])
8698 (define_expand "builtin_longjmp"
8699 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8703 /* The elements of the buffer are, in order: */
8704 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8705 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8706 POINTER_SIZE / BITS_PER_UNIT));
8707 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8708 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8709 rtx pv = gen_rtx_REG (Pmode, 1);
8711 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8712 gen_rtx_MEM (BLKmode,
8713 gen_rtx_SCRATCH (VOIDmode))));
8714 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8715 gen_rtx_MEM (BLKmode,
8716 hard_frame_pointer_rtx)));
8718 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8719 instead of the hard_frame_pointer_rtx in the save area. We need
8720 to adjust for the offset between these two values when we have
8721 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8722 pattern, the receiver performs the adjustment. */
8723 #ifdef HAVE_nonlocal_goto
8724 if (HAVE_nonlocal_goto)
8725 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8728 emit_move_insn (hard_frame_pointer_rtx, fp);
8730 /* This bit is the same as expand_builtin_longjmp. */
8731 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8732 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8733 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8735 /* Load the label we are jumping through into r1 so that we know
8736 where to look for it when we get back to setjmp's function for
8737 restoring the gp. */
8738 emit_move_insn (pv, lab);
8740 /* Prevent the insns above from being scheduled into the delay slot
8741 of the interspace jump because the space register could change. */
8742 emit_insn (gen_blockage ());
8744 emit_jump_insn (gen_interspace_jump (pv));
8749 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8750 (define_expand "extzv"
8751 [(set (match_operand 0 "register_operand" "")
8752 (zero_extract (match_operand 1 "register_operand" "")
8753 (match_operand 2 "uint32_operand" "")
8754 (match_operand 3 "uint32_operand" "")))]
8758 HOST_WIDE_INT len = INTVAL (operands[2]);
8759 HOST_WIDE_INT pos = INTVAL (operands[3]);
8761 /* PA extraction insns don't support zero length bitfields or fields
8762 extending beyond the left or right-most bits. Also, we reject lengths
8763 equal to a word as they are better handled by the move patterns. */
8764 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8767 /* From mips.md: extract_bit_field doesn't verify that our source
8768 matches the predicate, so check it again here. */
8769 if (!register_operand (operands[1], VOIDmode))
8773 emit_insn (gen_extzv_64 (operands[0], operands[1],
8774 operands[2], operands[3]));
8776 emit_insn (gen_extzv_32 (operands[0], operands[1],
8777 operands[2], operands[3]));
8781 (define_insn "extzv_32"
8782 [(set (match_operand:SI 0 "register_operand" "=r")
8783 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8784 (match_operand:SI 2 "uint5_operand" "")
8785 (match_operand:SI 3 "uint5_operand" "")))]
8787 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8788 [(set_attr "type" "shift")
8789 (set_attr "length" "4")])
8792 [(set (match_operand:SI 0 "register_operand" "=r")
8793 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8795 (match_operand:SI 2 "register_operand" "q")))]
8797 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8798 [(set_attr "type" "shift")
8799 (set_attr "length" "4")])
8801 (define_insn "extzv_64"
8802 [(set (match_operand:DI 0 "register_operand" "=r")
8803 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8804 (match_operand:DI 2 "uint32_operand" "")
8805 (match_operand:DI 3 "uint32_operand" "")))]
8807 "extrd,u %1,%3+%2-1,%2,%0"
8808 [(set_attr "type" "shift")
8809 (set_attr "length" "4")])
8812 [(set (match_operand:DI 0 "register_operand" "=r")
8813 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8815 (match_operand:DI 2 "register_operand" "q")))]
8817 "extrd,u %1,%%sar,1,%0"
8818 [(set_attr "type" "shift")
8819 (set_attr "length" "4")])
8821 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8822 (define_expand "extv"
8823 [(set (match_operand 0 "register_operand" "")
8824 (sign_extract (match_operand 1 "register_operand" "")
8825 (match_operand 2 "uint32_operand" "")
8826 (match_operand 3 "uint32_operand" "")))]
8830 HOST_WIDE_INT len = INTVAL (operands[2]);
8831 HOST_WIDE_INT pos = INTVAL (operands[3]);
8833 /* PA extraction insns don't support zero length bitfields or fields
8834 extending beyond the left or right-most bits. Also, we reject lengths
8835 equal to a word as they are better handled by the move patterns. */
8836 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8839 /* From mips.md: extract_bit_field doesn't verify that our source
8840 matches the predicate, so check it again here. */
8841 if (!register_operand (operands[1], VOIDmode))
8845 emit_insn (gen_extv_64 (operands[0], operands[1],
8846 operands[2], operands[3]));
8848 emit_insn (gen_extv_32 (operands[0], operands[1],
8849 operands[2], operands[3]));
8853 (define_insn "extv_32"
8854 [(set (match_operand:SI 0 "register_operand" "=r")
8855 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8856 (match_operand:SI 2 "uint5_operand" "")
8857 (match_operand:SI 3 "uint5_operand" "")))]
8859 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8860 [(set_attr "type" "shift")
8861 (set_attr "length" "4")])
8864 [(set (match_operand:SI 0 "register_operand" "=r")
8865 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8867 (match_operand:SI 2 "register_operand" "q")))]
8869 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8870 [(set_attr "type" "shift")
8871 (set_attr "length" "4")])
8873 (define_insn "extv_64"
8874 [(set (match_operand:DI 0 "register_operand" "=r")
8875 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8876 (match_operand:DI 2 "uint32_operand" "")
8877 (match_operand:DI 3 "uint32_operand" "")))]
8879 "extrd,s %1,%3+%2-1,%2,%0"
8880 [(set_attr "type" "shift")
8881 (set_attr "length" "4")])
8884 [(set (match_operand:DI 0 "register_operand" "=r")
8885 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8887 (match_operand:DI 2 "register_operand" "q")))]
8889 "extrd,s %1,%%sar,1,%0"
8890 [(set_attr "type" "shift")
8891 (set_attr "length" "4")])
8893 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8894 (define_expand "insv"
8895 [(set (zero_extract (match_operand 0 "register_operand" "")
8896 (match_operand 1 "uint32_operand" "")
8897 (match_operand 2 "uint32_operand" ""))
8898 (match_operand 3 "arith5_operand" ""))]
8902 HOST_WIDE_INT len = INTVAL (operands[1]);
8903 HOST_WIDE_INT pos = INTVAL (operands[2]);
8905 /* PA insertion insns don't support zero length bitfields or fields
8906 extending beyond the left or right-most bits. Also, we reject lengths
8907 equal to a word as they are better handled by the move patterns. */
8908 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8911 /* From mips.md: insert_bit_field doesn't verify that our destination
8912 matches the predicate, so check it again here. */
8913 if (!register_operand (operands[0], VOIDmode))
8917 emit_insn (gen_insv_64 (operands[0], operands[1],
8918 operands[2], operands[3]));
8920 emit_insn (gen_insv_32 (operands[0], operands[1],
8921 operands[2], operands[3]));
8925 (define_insn "insv_32"
8926 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8927 (match_operand:SI 1 "uint5_operand" "")
8928 (match_operand:SI 2 "uint5_operand" ""))
8929 (match_operand:SI 3 "arith5_operand" "r,L"))]
8932 {dep|depw} %3,%2+%1-1,%1,%0
8933 {depi|depwi} %3,%2+%1-1,%1,%0"
8934 [(set_attr "type" "shift,shift")
8935 (set_attr "length" "4,4")])
8937 ;; Optimize insertion of const_int values of type 1...1xxxx.
8939 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8940 (match_operand:SI 1 "uint5_operand" "")
8941 (match_operand:SI 2 "uint5_operand" ""))
8942 (match_operand:SI 3 "const_int_operand" ""))]
8943 "(INTVAL (operands[3]) & 0x10) != 0 &&
8944 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8947 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8948 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8950 [(set_attr "type" "shift")
8951 (set_attr "length" "4")])
8953 (define_insn "insv_64"
8954 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8955 (match_operand:DI 1 "uint32_operand" "")
8956 (match_operand:DI 2 "uint32_operand" ""))
8957 (match_operand:DI 3 "arith32_operand" "r,L"))]
8960 depd %3,%2+%1-1,%1,%0
8961 depdi %3,%2+%1-1,%1,%0"
8962 [(set_attr "type" "shift,shift")
8963 (set_attr "length" "4,4")])
8965 ;; Optimize insertion of const_int values of type 1...1xxxx.
8967 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8968 (match_operand:DI 1 "uint32_operand" "")
8969 (match_operand:DI 2 "uint32_operand" ""))
8970 (match_operand:DI 3 "const_int_operand" ""))]
8971 "(INTVAL (operands[3]) & 0x10) != 0
8973 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8976 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8977 return \"depdi %3,%2+%1-1,%1,%0\";
8979 [(set_attr "type" "shift")
8980 (set_attr "length" "4")])
8983 [(set (match_operand:DI 0 "register_operand" "=r")
8984 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8987 "depd,z %1,31,32,%0"
8988 [(set_attr "type" "shift")
8989 (set_attr "length" "4")])
8991 ;; This insn is used for some loop tests, typically loops reversed when
8992 ;; strength reduction is used. It is actually created when the instruction
8993 ;; combination phase combines the special loop test. Since this insn
8994 ;; is both a jump insn and has an output, it must deal with its own
8995 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8996 ;; to not choose the register alternatives in the event a reload is needed.
8997 (define_insn "decrement_and_branch_until_zero"
9000 (match_operator 2 "comparison_operator"
9002 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9003 (match_operand:SI 1 "int5_operand" "L,L,L"))
9005 (label_ref (match_operand 3 "" ""))
9008 (plus:SI (match_dup 0) (match_dup 1)))
9009 (clobber (match_scratch:SI 4 "=X,r,r"))]
9011 "* return output_dbra (operands, insn, which_alternative); "
9012 ;; Do not expect to understand this the first time through.
9013 [(set_attr "type" "cbranch,multi,multi")
9014 (set (attr "length")
9015 (if_then_else (eq_attr "alternative" "0")
9016 ;; Loop counter in register case
9017 ;; Short branch has length of 4
9018 ;; Long branch has length of 8, 20, 24 or 28
9019 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9020 (const_int MAX_12BIT_OFFSET))
9022 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9023 (const_int MAX_17BIT_OFFSET))
9025 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9027 (eq (symbol_ref "flag_pic") (const_int 0))
9031 ;; Loop counter in FP reg case.
9032 ;; Extra goo to deal with additional reload insns.
9033 (if_then_else (eq_attr "alternative" "1")
9034 (if_then_else (lt (match_dup 3) (pc))
9035 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9036 (const_int MAX_12BIT_OFFSET))
9038 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9039 (const_int MAX_17BIT_OFFSET))
9041 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9043 (eq (symbol_ref "flag_pic") (const_int 0))
9046 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9047 (const_int MAX_12BIT_OFFSET))
9049 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9050 (const_int MAX_17BIT_OFFSET))
9052 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9054 (eq (symbol_ref "flag_pic") (const_int 0))
9058 ;; Loop counter in memory case.
9059 ;; Extra goo to deal with additional reload insns.
9060 (if_then_else (lt (match_dup 3) (pc))
9061 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9062 (const_int MAX_12BIT_OFFSET))
9064 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9065 (const_int MAX_17BIT_OFFSET))
9067 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9069 (eq (symbol_ref "flag_pic") (const_int 0))
9072 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9073 (const_int MAX_12BIT_OFFSET))
9075 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9076 (const_int MAX_17BIT_OFFSET))
9078 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9080 (eq (symbol_ref "flag_pic") (const_int 0))
9082 (const_int 36))))))])
9087 (match_operator 2 "movb_comparison_operator"
9088 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9089 (label_ref (match_operand 3 "" ""))
9091 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9094 "* return output_movb (operands, insn, which_alternative, 0); "
9095 ;; Do not expect to understand this the first time through.
9096 [(set_attr "type" "cbranch,multi,multi,multi")
9097 (set (attr "length")
9098 (if_then_else (eq_attr "alternative" "0")
9099 ;; Loop counter in register case
9100 ;; Short branch has length of 4
9101 ;; Long branch has length of 8, 20, 24 or 28
9102 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9103 (const_int MAX_12BIT_OFFSET))
9105 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9106 (const_int MAX_17BIT_OFFSET))
9108 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9110 (eq (symbol_ref "flag_pic") (const_int 0))
9114 ;; Loop counter in FP reg case.
9115 ;; Extra goo to deal with additional reload insns.
9116 (if_then_else (eq_attr "alternative" "1")
9117 (if_then_else (lt (match_dup 3) (pc))
9118 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9119 (const_int MAX_12BIT_OFFSET))
9121 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9122 (const_int MAX_17BIT_OFFSET))
9124 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9126 (eq (symbol_ref "flag_pic") (const_int 0))
9129 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9130 (const_int MAX_12BIT_OFFSET))
9132 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9133 (const_int MAX_17BIT_OFFSET))
9135 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9137 (eq (symbol_ref "flag_pic") (const_int 0))
9141 ;; Loop counter in memory or sar case.
9142 ;; Extra goo to deal with additional reload insns.
9143 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9144 (const_int MAX_12BIT_OFFSET))
9146 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9147 (const_int MAX_17BIT_OFFSET))
9149 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9151 (eq (symbol_ref "flag_pic") (const_int 0))
9153 (const_int 32)))))])
9155 ;; Handle negated branch.
9159 (match_operator 2 "movb_comparison_operator"
9160 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9162 (label_ref (match_operand 3 "" ""))))
9163 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9166 "* return output_movb (operands, insn, which_alternative, 1); "
9167 ;; Do not expect to understand this the first time through.
9168 [(set_attr "type" "cbranch,multi,multi,multi")
9169 (set (attr "length")
9170 (if_then_else (eq_attr "alternative" "0")
9171 ;; Loop counter in register case
9172 ;; Short branch has length of 4
9173 ;; Long branch has length of 8
9174 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9175 (const_int MAX_12BIT_OFFSET))
9177 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9178 (const_int MAX_17BIT_OFFSET))
9180 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9182 (eq (symbol_ref "flag_pic") (const_int 0))
9186 ;; Loop counter in FP reg case.
9187 ;; Extra goo to deal with additional reload insns.
9188 (if_then_else (eq_attr "alternative" "1")
9189 (if_then_else (lt (match_dup 3) (pc))
9190 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9191 (const_int MAX_12BIT_OFFSET))
9193 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9194 (const_int MAX_17BIT_OFFSET))
9196 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9198 (eq (symbol_ref "flag_pic") (const_int 0))
9201 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9202 (const_int MAX_12BIT_OFFSET))
9204 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9205 (const_int MAX_17BIT_OFFSET))
9207 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9209 (eq (symbol_ref "flag_pic") (const_int 0))
9213 ;; Loop counter in memory or SAR case.
9214 ;; Extra goo to deal with additional reload insns.
9215 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9216 (const_int MAX_12BIT_OFFSET))
9218 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9219 (const_int MAX_17BIT_OFFSET))
9221 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9223 (eq (symbol_ref "flag_pic") (const_int 0))
9225 (const_int 32)))))])
9228 [(set (pc) (label_ref (match_operand 3 "" "" )))
9229 (set (match_operand:SI 0 "ireg_operand" "=r")
9230 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9231 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9232 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9235 return output_parallel_addb (operands, insn);
9237 [(set_attr "type" "parallel_branch")
9238 (set (attr "length")
9239 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9240 (const_int MAX_12BIT_OFFSET))
9242 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9243 (const_int MAX_17BIT_OFFSET))
9245 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9247 (eq (symbol_ref "flag_pic") (const_int 0))
9252 [(set (pc) (label_ref (match_operand 2 "" "" )))
9253 (set (match_operand:SF 0 "ireg_operand" "=r")
9254 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9258 return output_parallel_movb (operands, insn);
9260 [(set_attr "type" "parallel_branch")
9261 (set (attr "length")
9262 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9263 (const_int MAX_12BIT_OFFSET))
9265 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9266 (const_int MAX_17BIT_OFFSET))
9268 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9270 (eq (symbol_ref "flag_pic") (const_int 0))
9275 [(set (pc) (label_ref (match_operand 2 "" "" )))
9276 (set (match_operand:SI 0 "ireg_operand" "=r")
9277 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9281 return output_parallel_movb (operands, insn);
9283 [(set_attr "type" "parallel_branch")
9284 (set (attr "length")
9285 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9286 (const_int MAX_12BIT_OFFSET))
9288 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9289 (const_int MAX_17BIT_OFFSET))
9291 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9293 (eq (symbol_ref "flag_pic") (const_int 0))
9298 [(set (pc) (label_ref (match_operand 2 "" "" )))
9299 (set (match_operand:HI 0 "ireg_operand" "=r")
9300 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9304 return output_parallel_movb (operands, insn);
9306 [(set_attr "type" "parallel_branch")
9307 (set (attr "length")
9308 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9309 (const_int MAX_12BIT_OFFSET))
9311 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9312 (const_int MAX_17BIT_OFFSET))
9314 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9316 (eq (symbol_ref "flag_pic") (const_int 0))
9321 [(set (pc) (label_ref (match_operand 2 "" "" )))
9322 (set (match_operand:QI 0 "ireg_operand" "=r")
9323 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9327 return output_parallel_movb (operands, insn);
9329 [(set_attr "type" "parallel_branch")
9330 (set (attr "length")
9331 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9332 (const_int MAX_12BIT_OFFSET))
9334 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9335 (const_int MAX_17BIT_OFFSET))
9337 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9339 (eq (symbol_ref "flag_pic") (const_int 0))
9344 [(set (match_operand 0 "register_operand" "=f")
9345 (mult (match_operand 1 "register_operand" "f")
9346 (match_operand 2 "register_operand" "f")))
9347 (set (match_operand 3 "register_operand" "+f")
9348 (plus (match_operand 4 "register_operand" "f")
9349 (match_operand 5 "register_operand" "f")))]
9350 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9351 && reload_completed && fmpyaddoperands (operands)"
9354 if (GET_MODE (operands[0]) == DFmode)
9356 if (rtx_equal_p (operands[3], operands[5]))
9357 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9359 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9363 if (rtx_equal_p (operands[3], operands[5]))
9364 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9366 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9369 [(set_attr "type" "fpalu")
9370 (set_attr "length" "4")])
9373 [(set (match_operand 3 "register_operand" "+f")
9374 (plus (match_operand 4 "register_operand" "f")
9375 (match_operand 5 "register_operand" "f")))
9376 (set (match_operand 0 "register_operand" "=f")
9377 (mult (match_operand 1 "register_operand" "f")
9378 (match_operand 2 "register_operand" "f")))]
9379 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9380 && reload_completed && fmpyaddoperands (operands)"
9383 if (GET_MODE (operands[0]) == DFmode)
9385 if (rtx_equal_p (operands[3], operands[5]))
9386 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9388 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9392 if (rtx_equal_p (operands[3], operands[5]))
9393 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9395 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9398 [(set_attr "type" "fpalu")
9399 (set_attr "length" "4")])
9402 [(set (match_operand 0 "register_operand" "=f")
9403 (mult (match_operand 1 "register_operand" "f")
9404 (match_operand 2 "register_operand" "f")))
9405 (set (match_operand 3 "register_operand" "+f")
9406 (minus (match_operand 4 "register_operand" "f")
9407 (match_operand 5 "register_operand" "f")))]
9408 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9409 && reload_completed && fmpysuboperands (operands)"
9412 if (GET_MODE (operands[0]) == DFmode)
9413 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9415 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9417 [(set_attr "type" "fpalu")
9418 (set_attr "length" "4")])
9421 [(set (match_operand 3 "register_operand" "+f")
9422 (minus (match_operand 4 "register_operand" "f")
9423 (match_operand 5 "register_operand" "f")))
9424 (set (match_operand 0 "register_operand" "=f")
9425 (mult (match_operand 1 "register_operand" "f")
9426 (match_operand 2 "register_operand" "f")))]
9427 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9428 && reload_completed && fmpysuboperands (operands)"
9431 if (GET_MODE (operands[0]) == DFmode)
9432 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9434 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9436 [(set_attr "type" "fpalu")
9437 (set_attr "length" "4")])
9439 ;; Flush the I and D cache lines from the start address (operand0)
9440 ;; to the end address (operand1). No lines are flushed if the end
9441 ;; address is less than the start address (unsigned).
9443 ;; Because the range of memory flushed is variable and the size of
9444 ;; a MEM can only be a CONST_INT, the patterns specify that they
9445 ;; perform an unspecified volatile operation on all memory.
9447 ;; The address range for an icache flush must lie within a single
9448 ;; space on targets with non-equivalent space registers.
9450 ;; This is used by the trampoline code for nested functions.
9452 ;; Operand 0 contains the start address.
9453 ;; Operand 1 contains the end address.
9454 ;; Operand 2 contains the line length to use.
9455 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9456 (define_insn "dcacheflush"
9458 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9459 (use (match_operand 0 "pmode_register_operand" "r"))
9460 (use (match_operand 1 "pmode_register_operand" "r"))
9461 (use (match_operand 2 "pmode_register_operand" "r"))
9462 (clobber (match_scratch 3 "=&0"))]
9467 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9469 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9471 [(set_attr "type" "multi")
9472 (set_attr "length" "12")])
9474 (define_insn "icacheflush"
9476 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9477 (use (match_operand 0 "pmode_register_operand" "r"))
9478 (use (match_operand 1 "pmode_register_operand" "r"))
9479 (use (match_operand 2 "pmode_register_operand" "r"))
9480 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9481 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9482 (clobber (match_scratch 5 "=&0"))]
9487 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9489 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9491 [(set_attr "type" "multi")
9492 (set_attr "length" "52")])
9494 ;; An out-of-line prologue.
9495 (define_insn "outline_prologue_call"
9496 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9497 (clobber (reg:SI 31))
9498 (clobber (reg:SI 22))
9499 (clobber (reg:SI 21))
9500 (clobber (reg:SI 20))
9501 (clobber (reg:SI 19))
9502 (clobber (reg:SI 1))]
9506 extern int frame_pointer_needed;
9508 /* We need two different versions depending on whether or not we
9509 need a frame pointer. Also note that we return to the instruction
9510 immediately after the branch rather than two instructions after the
9511 break as normally is the case. */
9512 if (frame_pointer_needed)
9514 /* Must import the magic millicode routine(s). */
9515 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9517 if (TARGET_PORTABLE_RUNTIME)
9519 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9520 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9524 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9528 /* Must import the magic millicode routine(s). */
9529 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9531 if (TARGET_PORTABLE_RUNTIME)
9533 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9534 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9537 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9541 [(set_attr "type" "multi")
9542 (set_attr "length" "8")])
9544 ;; An out-of-line epilogue.
9545 (define_insn "outline_epilogue_call"
9546 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9549 (clobber (reg:SI 31))
9550 (clobber (reg:SI 22))
9551 (clobber (reg:SI 21))
9552 (clobber (reg:SI 20))
9553 (clobber (reg:SI 19))
9554 (clobber (reg:SI 2))
9555 (clobber (reg:SI 1))]
9559 extern int frame_pointer_needed;
9561 /* We need two different versions depending on whether or not we
9562 need a frame pointer. Also note that we return to the instruction
9563 immediately after the branch rather than two instructions after the
9564 break as normally is the case. */
9565 if (frame_pointer_needed)
9567 /* Must import the magic millicode routine. */
9568 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9570 /* The out-of-line prologue will make sure we return to the right
9572 if (TARGET_PORTABLE_RUNTIME)
9574 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9575 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9579 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9583 /* Must import the magic millicode routine. */
9584 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9586 /* The out-of-line prologue will make sure we return to the right
9588 if (TARGET_PORTABLE_RUNTIME)
9590 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9591 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9594 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9598 [(set_attr "type" "multi")
9599 (set_attr "length" "8")])
9601 ;; Given a function pointer, canonicalize it so it can be
9602 ;; reliably compared to another function pointer. */
9603 (define_expand "canonicalize_funcptr_for_compare"
9604 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9605 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9606 (clobber (match_dup 2))
9607 (clobber (reg:SI 26))
9608 (clobber (reg:SI 22))
9609 (clobber (reg:SI 31))])
9610 (set (match_operand:SI 0 "register_operand" "")
9612 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9617 rtx canonicalize_funcptr_for_compare_libfunc
9618 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9620 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9621 operands[0], LCT_NORMAL, Pmode,
9622 1, operands[1], Pmode);
9626 operands[2] = gen_reg_rtx (SImode);
9627 if (GET_CODE (operands[1]) != REG)
9629 rtx tmp = gen_reg_rtx (Pmode);
9630 emit_move_insn (tmp, operands[1]);
9635 (define_insn "*$$sh_func_adrs"
9636 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9637 (clobber (match_operand:SI 0 "register_operand" "=a"))
9638 (clobber (reg:SI 26))
9639 (clobber (reg:SI 22))
9640 (clobber (reg:SI 31))]
9644 int length = get_attr_length (insn);
9647 xoperands[0] = GEN_INT (length - 8);
9648 xoperands[1] = GEN_INT (length - 16);
9650 /* Must import the magic millicode routine. */
9651 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9653 /* This is absolutely amazing.
9655 First, copy our input parameter into %r29 just in case we don't
9656 need to call $$sh_func_adrs. */
9657 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9658 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9660 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9661 we use %r26 unchanged. */
9662 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9663 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9665 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9666 4096, then again we use %r26 unchanged. */
9667 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9669 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9670 return output_millicode_call (insn,
9671 gen_rtx_SYMBOL_REF (SImode,
9672 \"$$sh_func_adrs\"));
9674 [(set_attr "type" "multi")
9675 (set (attr "length")
9676 (plus (symbol_ref "attr_length_millicode_call (insn)")
9679 ;; On the PA, the PIC register is call clobbered, so it must
9680 ;; be saved & restored around calls by the caller. If the call
9681 ;; doesn't return normally (nonlocal goto, or an exception is
9682 ;; thrown), then the code at the exception handler label must
9683 ;; restore the PIC register.
9684 (define_expand "exception_receiver"
9689 /* On the 64-bit port, we need a blockage because there is
9690 confusion regarding the dependence of the restore on the
9691 frame pointer. As a result, the frame pointer and pic
9692 register restores sometimes are interchanged erroneously. */
9694 emit_insn (gen_blockage ());
9695 /* Restore the PIC register using hppa_pic_save_rtx (). The
9696 PIC register is not saved in the frame in 64-bit ABI. */
9697 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9698 emit_insn (gen_blockage ());
9702 (define_expand "builtin_setjmp_receiver"
9703 [(label_ref (match_operand 0 "" ""))]
9708 emit_insn (gen_blockage ());
9709 /* Restore the PIC register. Hopefully, this will always be from
9710 a stack slot. The only registers that are valid after a
9711 builtin_longjmp are the stack and frame pointers. */
9712 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9713 emit_insn (gen_blockage ());
9717 ;; Allocate new stack space and update the saved stack pointer in the
9718 ;; frame marker. The HP C compilers also copy additional words in the
9719 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9720 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9721 ;; currently don't copy these values.
9723 ;; Since the copy of the frame marker can't be done atomically, I
9724 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9725 ;; The HP compilers appear to raise the stack and copy the frame
9726 ;; marker in a strict instruction sequence. This suggests that the
9727 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9728 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9729 ;; as GAS doesn't support it, or try to keep the instructions emitted
9730 ;; here in strict sequence.
9731 (define_expand "allocate_stack"
9732 [(match_operand 0 "" "")
9733 (match_operand 1 "" "")]
9739 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9740 in operand 0 before adjusting the stack. */
9741 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9742 anti_adjust_stack (operands[1]);
9743 if (TARGET_HPUX_UNWIND_LIBRARY)
9745 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9746 GEN_INT (TARGET_64BIT ? -8 : -4));
9747 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9749 if (!TARGET_64BIT && flag_pic)
9751 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9752 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9757 (define_expand "prefetch"
9758 [(match_operand 0 "address_operand" "")
9759 (match_operand 1 "const_int_operand" "")
9760 (match_operand 2 "const_int_operand" "")]
9763 int locality = INTVAL (operands[2]);
9765 gcc_assert (locality >= 0 && locality <= 3);
9767 /* Change operand[0] to a MEM as we don't have the infrastructure
9768 to output all the supported address modes for ldw/ldd when we use
9769 the address directly. However, we do have it for MEMs. */
9770 operands[0] = gen_rtx_MEM (QImode, operands[0]);
9772 /* If the address isn't valid for the prefetch, replace it. */
9775 if (!prefetch_nocc_operand (operands[0], QImode))
9777 = replace_equiv_address (operands[0],
9778 copy_to_mode_reg (Pmode,
9779 XEXP (operands[0], 0)));
9780 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
9784 if (!prefetch_cc_operand (operands[0], QImode))
9786 = replace_equiv_address (operands[0],
9787 copy_to_mode_reg (Pmode,
9788 XEXP (operands[0], 0)));
9789 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
9794 (define_insn "prefetch_cc"
9795 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
9796 (match_operand:SI 1 "const_int_operand" "n")
9797 (match_operand:SI 2 "const_int_operand" "n"))]
9798 "TARGET_PA_20 && operands[2] == const0_rtx"
9800 /* The SL cache-control completor indicates good spatial locality but
9801 poor temporal locality. The ldw instruction with a target of general
9802 register 0 prefetches a cache line for a read. The ldd instruction
9803 prefetches a cache line for a write. */
9804 static const char * const instr[2] = {
9805 "ldw%M0,sl %0,%%r0",
9808 int read_or_write = INTVAL (operands[1]);
9810 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9812 return instr [read_or_write];
9814 [(set_attr "type" "load")
9815 (set_attr "length" "4")])
9817 (define_insn "prefetch_nocc"
9818 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
9819 (match_operand:SI 1 "const_int_operand" "n,n")
9820 (match_operand:SI 2 "const_int_operand" "n,n"))]
9821 "TARGET_PA_20 && operands[2] != const0_rtx"
9823 /* The ldw instruction with a target of general register 0 prefetches
9824 a cache line for a read. The ldd instruction prefetches a cache line
9826 static const char * const instr[2][2] = {
9836 int read_or_write = INTVAL (operands[1]);
9838 gcc_assert (which_alternative == 0 || which_alternative == 1);
9839 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
9841 return instr [which_alternative][read_or_write];
9843 [(set_attr "type" "load")
9844 (set_attr "length" "4")])
9848 (define_insn "tgd_load"
9849 [(set (match_operand:SI 0 "register_operand" "=r")
9850 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
9851 (clobber (reg:SI 1))]
9856 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
9858 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
9860 [(set_attr "type" "multi")
9861 (set_attr "length" "8")])
9863 (define_insn "tld_load"
9864 [(set (match_operand:SI 0 "register_operand" "=r")
9865 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
9866 (clobber (reg:SI 1))]
9871 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
9873 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
9875 [(set_attr "type" "multi")
9876 (set_attr "length" "8")])
9878 (define_insn "tld_offset_load"
9879 [(set (match_operand:SI 0 "register_operand" "=r")
9880 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
9882 (match_operand:SI 2 "register_operand" "r")))
9883 (clobber (reg:SI 1))]
9887 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
9889 [(set_attr "type" "multi")
9890 (set_attr "length" "8")])
9892 (define_insn "tp_load"
9893 [(set (match_operand:SI 0 "register_operand" "=r")
9894 (unspec:SI [(const_int 0)] UNSPEC_TP))]
9896 "{mfctl|mfctl,w} %%cr27,%0"
9897 [(set_attr "type" "multi")
9898 (set_attr "length" "4")])
9900 (define_insn "tie_load"
9901 [(set (match_operand:SI 0 "register_operand" "=r")
9902 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
9903 (clobber (reg:SI 1))]
9908 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
9910 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
9912 [(set_attr "type" "multi")
9913 (set_attr "length" "8")])
9915 (define_insn "tle_load"
9916 [(set (match_operand:SI 0 "register_operand" "=r")
9917 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
9919 (match_operand:SI 2 "register_operand" "r")))
9920 (clobber (reg:SI 1))]
9922 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
9923 [(set_attr "type" "multi")
9924 (set_attr "length" "8")])