1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
22 ;; Boston, MA 02110-1301, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Uses of UNSPEC in this file:
32 [(UNSPEC_CFFC 0) ; canonicalize_funcptr_for_compare
33 (UNSPEC_GOTO 1) ; indirect_goto
34 (UNSPEC_DLTIND14R 2) ;
47 [(UNSPECV_BLOCKAGE 0) ; blockage
48 (UNSPECV_DCACHE 1) ; dcacheflush
49 (UNSPECV_ICACHE 2) ; icacheflush
50 (UNSPECV_OPC 3) ; outline_prologue_call
51 (UNSPECV_OEC 4) ; outline_epilogue_call
52 (UNSPECV_LONGJMP 5) ; builtin_longjmp
55 ;; Maximum pc-relative branch offsets.
57 ;; These numbers are a bit smaller than the maximum allowable offsets
58 ;; so that a few instructions may be inserted before the actual branch.
61 [(MAX_12BIT_OFFSET 8184) ; 12-bit branch
62 (MAX_17BIT_OFFSET 262100) ; 17-bit branch
65 ;; Insn type. Used to default other attribute values.
67 ;; type "unary" insns have one input operand (1) and one output operand (0)
68 ;; type "binary" insns have two input operands (1,2) and one output (0)
71 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
72 (const_string "binary"))
74 (define_attr "pa_combine_type"
75 "fmpy,faddsub,uncond_branch,addmove,none"
76 (const_string "none"))
78 ;; Processor type (for scheduling, not code generation) -- this attribute
79 ;; must exactly match the processor_type enumeration in pa.h.
81 ;; FIXME: Add 800 scheduling for completeness?
83 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
85 ;; Length (in # of bytes).
86 (define_attr "length" ""
87 (cond [(eq_attr "type" "load,fpload")
88 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
89 (const_int 8) (const_int 4))
91 (eq_attr "type" "store,fpstore")
92 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
93 (const_int 8) (const_int 4))
95 (eq_attr "type" "binary,shift,nullshift")
96 (if_then_else (match_operand 2 "arith_operand" "")
97 (const_int 4) (const_int 12))
99 (eq_attr "type" "move,unary,shift,nullshift")
100 (if_then_else (match_operand 1 "arith_operand" "")
101 (const_int 4) (const_int 8))]
105 (define_asm_attributes
106 [(set_attr "length" "4")
107 (set_attr "type" "multi")])
109 ;; Attributes for instruction and branch scheduling
111 ;; For conditional branches.
112 (define_attr "in_branch_delay" "false,true"
113 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
114 (eq_attr "length" "4"))
115 (const_string "true")
116 (const_string "false")))
118 ;; Disallow instructions which use the FPU since they will tie up the FPU
119 ;; even if the instruction is nullified.
120 (define_attr "in_nullified_branch_delay" "false,true"
121 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
122 (eq_attr "length" "4"))
123 (const_string "true")
124 (const_string "false")))
126 ;; For calls and millicode calls. Allow unconditional branches in the
128 (define_attr "in_call_delay" "false,true"
129 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
130 (eq_attr "length" "4"))
131 (const_string "true")
132 (eq_attr "type" "uncond_branch")
133 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
135 (const_string "true")
136 (const_string "false"))]
137 (const_string "false")))
140 ;; Call delay slot description.
141 (define_delay (eq_attr "type" "call")
142 [(eq_attr "in_call_delay" "true") (nil) (nil)])
144 ;; Millicode call delay slot description.
145 (define_delay (eq_attr "type" "milli")
146 [(eq_attr "in_call_delay" "true") (nil) (nil)])
148 ;; Return and other similar instructions.
149 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
150 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
152 ;; Floating point conditional branch delay slot description.
153 (define_delay (eq_attr "type" "fbranch")
154 [(eq_attr "in_branch_delay" "true")
155 (eq_attr "in_nullified_branch_delay" "true")
158 ;; Integer conditional branch delay slot description.
159 ;; Nullification of conditional branches on the PA is dependent on the
160 ;; direction of the branch. Forward branches nullify true and
161 ;; backward branches nullify false. If the direction is unknown
162 ;; then nullification is not allowed.
163 (define_delay (eq_attr "type" "cbranch")
164 [(eq_attr "in_branch_delay" "true")
165 (and (eq_attr "in_nullified_branch_delay" "true")
166 (attr_flag "forward"))
167 (and (eq_attr "in_nullified_branch_delay" "true")
168 (attr_flag "backward"))])
170 (define_delay (and (eq_attr "type" "uncond_branch")
171 (eq (symbol_ref "following_call (insn)")
173 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
175 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
176 ;; load: 2, fpload: 3
177 ;; store, fpstore: 3, no D-cache operations should be scheduled.
179 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
181 ;; Instruction Time Unit Minimum Distance (unit contention)
188 ;; fmpyadd 3 ALU,MPY 2
189 ;; fmpysub 3 ALU,MPY 2
190 ;; fmpycfxt 3 ALU,MPY 2
193 ;; fdiv,sgl 10 MPY 10
194 ;; fdiv,dbl 12 MPY 12
195 ;; fsqrt,sgl 14 MPY 14
196 ;; fsqrt,dbl 18 MPY 18
198 ;; We don't model fmpyadd/fmpysub properly as those instructions
199 ;; keep both the FP ALU and MPY units busy. Given that these
200 ;; processors are obsolete, I'm not going to spend the time to
201 ;; model those instructions correctly.
203 (define_automaton "pa700")
204 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
206 (define_insn_reservation "W0" 4
207 (and (eq_attr "type" "fpcc")
208 (eq_attr "cpu" "700"))
211 (define_insn_reservation "W1" 3
212 (and (eq_attr "type" "fpalu")
213 (eq_attr "cpu" "700"))
216 (define_insn_reservation "W2" 3
217 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
218 (eq_attr "cpu" "700"))
221 (define_insn_reservation "W3" 10
222 (and (eq_attr "type" "fpdivsgl")
223 (eq_attr "cpu" "700"))
226 (define_insn_reservation "W4" 12
227 (and (eq_attr "type" "fpdivdbl")
228 (eq_attr "cpu" "700"))
231 (define_insn_reservation "W5" 14
232 (and (eq_attr "type" "fpsqrtsgl")
233 (eq_attr "cpu" "700"))
236 (define_insn_reservation "W6" 18
237 (and (eq_attr "type" "fpsqrtdbl")
238 (eq_attr "cpu" "700"))
241 (define_insn_reservation "W7" 2
242 (and (eq_attr "type" "load")
243 (eq_attr "cpu" "700"))
246 (define_insn_reservation "W8" 2
247 (and (eq_attr "type" "fpload")
248 (eq_attr "cpu" "700"))
251 (define_insn_reservation "W9" 3
252 (and (eq_attr "type" "store")
253 (eq_attr "cpu" "700"))
256 (define_insn_reservation "W10" 3
257 (and (eq_attr "type" "fpstore")
258 (eq_attr "cpu" "700"))
261 (define_insn_reservation "W11" 1
262 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
263 (eq_attr "cpu" "700"))
266 ;; We have a bypass for all computations in the FP unit which feed an
267 ;; FP store as long as the sizes are the same.
268 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
269 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
270 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
271 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
272 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
274 ;; We have an "anti-bypass" for FP loads which feed an FP store.
275 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
277 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
278 ;; floating point computations with non-floating point computations (fp loads
279 ;; and stores are not fp computations).
281 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
282 ;; take two cycles, during which no Dcache operations should be scheduled.
283 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
284 ;; all have the same memory characteristics if one disregards cache misses.
286 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
287 ;; There's no value in modeling the ALU and MUL separately though
288 ;; since there can never be a functional unit conflict given the
289 ;; latency and issue rates for those units.
292 ;; Instruction Time Unit Minimum Distance (unit contention)
299 ;; fmpyadd 2 ALU,MPY 1
300 ;; fmpysub 2 ALU,MPY 1
301 ;; fmpycfxt 2 ALU,MPY 1
305 ;; fdiv,dbl 15 DIV 15
307 ;; fsqrt,dbl 15 DIV 15
309 (define_automaton "pa7100")
310 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
312 (define_insn_reservation "X0" 2
313 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
314 (eq_attr "cpu" "7100"))
317 (define_insn_reservation "X1" 8
318 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
319 (eq_attr "cpu" "7100"))
320 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
322 (define_insn_reservation "X2" 15
323 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
324 (eq_attr "cpu" "7100"))
325 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
327 (define_insn_reservation "X3" 2
328 (and (eq_attr "type" "load")
329 (eq_attr "cpu" "7100"))
332 (define_insn_reservation "X4" 2
333 (and (eq_attr "type" "fpload")
334 (eq_attr "cpu" "7100"))
337 (define_insn_reservation "X5" 2
338 (and (eq_attr "type" "store")
339 (eq_attr "cpu" "7100"))
340 "i_7100+mem_7100,mem_7100")
342 (define_insn_reservation "X6" 2
343 (and (eq_attr "type" "fpstore")
344 (eq_attr "cpu" "7100"))
345 "i_7100+mem_7100,mem_7100")
347 (define_insn_reservation "X7" 1
348 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
349 (eq_attr "cpu" "7100"))
352 ;; We have a bypass for all computations in the FP unit which feed an
353 ;; FP store as long as the sizes are the same.
354 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
355 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
356 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
358 ;; We have an "anti-bypass" for FP loads which feed an FP store.
359 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
361 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
362 ;; There's no value in modeling the ALU and MUL separately though
363 ;; since there can never be a functional unit conflict that
364 ;; can be avoided given the latency, issue rates and mandatory
365 ;; one cycle cpu-wide lock for a double precision fp multiply.
368 ;; Instruction Time Unit Minimum Distance (unit contention)
375 ;; fmpyadd,sgl 2 ALU,MPY 1
376 ;; fmpyadd,dbl 3 ALU,MPY 2
377 ;; fmpysub,sgl 2 ALU,MPY 1
378 ;; fmpysub,dbl 3 ALU,MPY 2
379 ;; fmpycfxt,sgl 2 ALU,MPY 1
380 ;; fmpycfxt,dbl 3 ALU,MPY 2
385 ;; fdiv,dbl 15 DIV 15
387 ;; fsqrt,dbl 15 DIV 15
389 ;; The PA7200 is just like the PA7100LC except that there is
390 ;; no store-store penalty.
392 ;; The PA7300 is just like the PA7200 except that there is
393 ;; no store-load penalty.
395 ;; Note there are some aspects of the 7100LC we are not modeling
396 ;; at the moment. I'll be reviewing the 7100LC scheduling info
397 ;; shortly and updating this description.
401 ;; other issue modeling
403 (define_automaton "pa7100lc")
404 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
405 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
406 (define_cpu_unit "mem_7100lc" "pa7100lc")
408 ;; Double precision multiplies lock the entire CPU for one
409 ;; cycle. There is no way to avoid this lock and trying to
410 ;; schedule around the lock is pointless and thus there is no
411 ;; value in trying to model this lock.
413 ;; Not modeling the lock allows us to treat fp multiplies just
414 ;; like any other FP alu instruction. It allows for a smaller
415 ;; DFA and may reduce register pressure.
416 (define_insn_reservation "Y0" 2
417 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
418 (eq_attr "cpu" "7100LC,7200,7300"))
419 "f_7100lc,fpmac_7100lc")
421 ;; fp division and sqrt instructions lock the entire CPU for
422 ;; 7 cycles (single precision) or 14 cycles (double precision).
423 ;; There is no way to avoid this lock and trying to schedule
424 ;; around the lock is pointless and thus there is no value in
425 ;; trying to model this lock. Not modeling the lock allows
426 ;; for a smaller DFA and may reduce register pressure.
427 (define_insn_reservation "Y1" 1
428 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
429 (eq_attr "cpu" "7100LC,7200,7300"))
432 (define_insn_reservation "Y2" 2
433 (and (eq_attr "type" "load")
434 (eq_attr "cpu" "7100LC,7200,7300"))
435 "i1_7100lc+mem_7100lc")
437 (define_insn_reservation "Y3" 2
438 (and (eq_attr "type" "fpload")
439 (eq_attr "cpu" "7100LC,7200,7300"))
440 "i1_7100lc+mem_7100lc")
442 (define_insn_reservation "Y4" 2
443 (and (eq_attr "type" "store")
444 (eq_attr "cpu" "7100LC"))
445 "i1_7100lc+mem_7100lc,mem_7100lc")
447 (define_insn_reservation "Y5" 2
448 (and (eq_attr "type" "fpstore")
449 (eq_attr "cpu" "7100LC"))
450 "i1_7100lc+mem_7100lc,mem_7100lc")
452 (define_insn_reservation "Y6" 1
453 (and (eq_attr "type" "shift,nullshift")
454 (eq_attr "cpu" "7100LC,7200,7300"))
457 (define_insn_reservation "Y7" 1
458 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
459 (eq_attr "cpu" "7100LC,7200,7300"))
460 "(i0_7100lc|i1_7100lc)")
462 ;; The 7200 has a store-load penalty
463 (define_insn_reservation "Y8" 2
464 (and (eq_attr "type" "store")
465 (eq_attr "cpu" "7200"))
466 "i1_7100lc,mem_7100lc")
468 (define_insn_reservation "Y9" 2
469 (and (eq_attr "type" "fpstore")
470 (eq_attr "cpu" "7200"))
471 "i1_7100lc,mem_7100lc")
473 ;; The 7300 has no penalty for store-store or store-load
474 (define_insn_reservation "Y10" 2
475 (and (eq_attr "type" "store")
476 (eq_attr "cpu" "7300"))
479 (define_insn_reservation "Y11" 2
480 (and (eq_attr "type" "fpstore")
481 (eq_attr "cpu" "7300"))
484 ;; We have an "anti-bypass" for FP loads which feed an FP store.
485 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
487 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
488 ;; traditional architecture.
490 ;; The PA8000 has a large (56) entry reorder buffer that is split between
491 ;; memory and non-memory operations.
493 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
494 ;; the function units, with the exception of branches and multi-output
495 ;; instructions. The PA8000 can retire two non-memory operations per cycle
496 ;; and two memory operations per cycle, only one of which may be a store.
498 ;; Given the large reorder buffer, the processor can hide most latencies.
499 ;; According to HP, they've got the best results by scheduling for retirement
500 ;; bandwidth with limited latency scheduling for floating point operations.
501 ;; Latency for integer operations and memory references is ignored.
504 ;; We claim floating point operations have a 2 cycle latency and are
505 ;; fully pipelined, except for div and sqrt which are not pipelined and
506 ;; take from 17 to 31 cycles to complete.
508 ;; It's worth noting that there is no way to saturate all the functional
509 ;; units on the PA8000 as there is not enough issue bandwidth.
511 (define_automaton "pa8000")
512 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
513 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
514 (define_cpu_unit "store_8000" "pa8000")
515 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
516 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
517 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
518 (define_reservation "im_8000" "im0_8000 | im1_8000")
519 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
520 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
521 (define_reservation "f_8000" "f0_8000 | f1_8000")
522 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
524 ;; We can issue any two memops per cycle, but we can only retire
525 ;; one memory store per cycle. We assume that the reorder buffer
526 ;; will hide any memory latencies per HP's recommendation.
527 (define_insn_reservation "Z0" 0
529 (eq_attr "type" "load,fpload")
530 (eq_attr "cpu" "8000"))
533 (define_insn_reservation "Z1" 0
535 (eq_attr "type" "store,fpstore")
536 (eq_attr "cpu" "8000"))
537 "im_8000,rm_8000+store_8000")
539 ;; We can issue and retire two non-memory operations per cycle with
540 ;; a few exceptions (branches). This group catches those we want
541 ;; to assume have zero latency.
542 (define_insn_reservation "Z2" 0
544 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
545 (eq_attr "cpu" "8000"))
548 ;; Branches use both slots in the non-memory issue and
550 (define_insn_reservation "Z3" 0
552 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
553 (eq_attr "cpu" "8000"))
554 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
556 ;; We partial latency schedule the floating point units.
557 ;; They can issue/retire two at a time in the non-memory
558 ;; units. We fix their latency at 2 cycles and they
559 ;; are fully pipelined.
560 (define_insn_reservation "Z4" 1
562 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
563 (eq_attr "cpu" "8000"))
564 "inm_8000,f_8000,rnm_8000")
566 ;; The fdivsqrt units are not pipelined and have a very long latency.
567 ;; To keep the DFA from exploding, we do not show all the
568 ;; reservations for the divsqrt unit.
569 (define_insn_reservation "Z5" 17
571 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
572 (eq_attr "cpu" "8000"))
573 "inm_8000,fdivsqrt_8000*6,rnm_8000")
575 (define_insn_reservation "Z6" 31
577 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
578 (eq_attr "cpu" "8000"))
579 "inm_8000,fdivsqrt_8000*6,rnm_8000")
581 (include "predicates.md")
583 ;; Compare instructions.
584 ;; This controls RTL generation and register allocation.
586 ;; We generate RTL for comparisons and branches by having the cmpxx
587 ;; patterns store away the operands. Then, the scc and bcc patterns
588 ;; emit RTL for both the compare and the branch.
591 (define_expand "cmpdi"
593 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
594 (match_operand:DI 1 "register_operand" "")))]
599 hppa_compare_op0 = operands[0];
600 hppa_compare_op1 = operands[1];
601 hppa_branch_type = CMP_SI;
605 (define_expand "cmpsi"
607 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
608 (match_operand:SI 1 "arith5_operand" "")))]
612 hppa_compare_op0 = operands[0];
613 hppa_compare_op1 = operands[1];
614 hppa_branch_type = CMP_SI;
618 (define_expand "cmpsf"
620 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
621 (match_operand:SF 1 "reg_or_0_operand" "")))]
622 "! TARGET_SOFT_FLOAT"
625 hppa_compare_op0 = operands[0];
626 hppa_compare_op1 = operands[1];
627 hppa_branch_type = CMP_SF;
631 (define_expand "cmpdf"
633 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
634 (match_operand:DF 1 "reg_or_0_operand" "")))]
635 "! TARGET_SOFT_FLOAT"
638 hppa_compare_op0 = operands[0];
639 hppa_compare_op1 = operands[1];
640 hppa_branch_type = CMP_DF;
646 (match_operator:CCFP 2 "comparison_operator"
647 [(match_operand:SF 0 "reg_or_0_operand" "fG")
648 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,sgl,%Y2 %f0,%f1"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
656 (match_operator:CCFP 2 "comparison_operator"
657 [(match_operand:DF 0 "reg_or_0_operand" "fG")
658 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
659 "! TARGET_SOFT_FLOAT"
660 "fcmp,dbl,%Y2 %f0,%f1"
661 [(set_attr "length" "4")
662 (set_attr "type" "fpcc")])
664 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
665 ;; placeholders. This is necessary in rare situations when a
666 ;; placeholder is re-emitted (see PR 8705).
668 (define_expand "movccfp"
670 (match_operand 0 "const_int_operand" ""))]
671 "! TARGET_SOFT_FLOAT"
674 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
678 ;; The following patterns are optimization placeholders. In almost
679 ;; all cases, the user of the condition code will be simplified and the
680 ;; original condition code setting insn should be eliminated.
682 (define_insn "*movccfp0"
685 "! TARGET_SOFT_FLOAT"
686 "fcmp,dbl,= %%fr0,%%fr0"
687 [(set_attr "length" "4")
688 (set_attr "type" "fpcc")])
690 (define_insn "*movccfp1"
693 "! TARGET_SOFT_FLOAT"
694 "fcmp,dbl,!= %%fr0,%%fr0"
695 [(set_attr "length" "4")
696 (set_attr "type" "fpcc")])
701 [(set (match_operand:SI 0 "register_operand" "")
707 /* fp scc patterns rarely match, and are not a win on the PA. */
708 if (hppa_branch_type != CMP_SI)
710 /* set up operands from compare. */
711 operands[1] = hppa_compare_op0;
712 operands[2] = hppa_compare_op1;
713 /* fall through and generate default code */
717 [(set (match_operand:SI 0 "register_operand" "")
723 /* fp scc patterns rarely match, and are not a win on the PA. */
724 if (hppa_branch_type != CMP_SI)
726 operands[1] = hppa_compare_op0;
727 operands[2] = hppa_compare_op1;
731 [(set (match_operand:SI 0 "register_operand" "")
737 /* fp scc patterns rarely match, and are not a win on the PA. */
738 if (hppa_branch_type != CMP_SI)
740 operands[1] = hppa_compare_op0;
741 operands[2] = hppa_compare_op1;
745 [(set (match_operand:SI 0 "register_operand" "")
751 /* fp scc patterns rarely match, and are not a win on the PA. */
752 if (hppa_branch_type != CMP_SI)
754 operands[1] = hppa_compare_op0;
755 operands[2] = hppa_compare_op1;
759 [(set (match_operand:SI 0 "register_operand" "")
765 /* fp scc patterns rarely match, and are not a win on the PA. */
766 if (hppa_branch_type != CMP_SI)
768 operands[1] = hppa_compare_op0;
769 operands[2] = hppa_compare_op1;
773 [(set (match_operand:SI 0 "register_operand" "")
779 /* fp scc patterns rarely match, and are not a win on the PA. */
780 if (hppa_branch_type != CMP_SI)
782 operands[1] = hppa_compare_op0;
783 operands[2] = hppa_compare_op1;
786 (define_expand "sltu"
787 [(set (match_operand:SI 0 "register_operand" "")
788 (ltu:SI (match_dup 1)
793 if (hppa_branch_type != CMP_SI)
795 operands[1] = hppa_compare_op0;
796 operands[2] = hppa_compare_op1;
799 (define_expand "sgtu"
800 [(set (match_operand:SI 0 "register_operand" "")
801 (gtu:SI (match_dup 1)
806 if (hppa_branch_type != CMP_SI)
808 operands[1] = hppa_compare_op0;
809 operands[2] = hppa_compare_op1;
812 (define_expand "sleu"
813 [(set (match_operand:SI 0 "register_operand" "")
814 (leu:SI (match_dup 1)
819 if (hppa_branch_type != CMP_SI)
821 operands[1] = hppa_compare_op0;
822 operands[2] = hppa_compare_op1;
825 (define_expand "sgeu"
826 [(set (match_operand:SI 0 "register_operand" "")
827 (geu:SI (match_dup 1)
832 if (hppa_branch_type != CMP_SI)
834 operands[1] = hppa_compare_op0;
835 operands[2] = hppa_compare_op1;
838 ;; Instruction canonicalization puts immediate operands second, which
839 ;; is the reverse of what we want.
842 [(set (match_operand:SI 0 "register_operand" "=r")
843 (match_operator:SI 3 "comparison_operator"
844 [(match_operand:SI 1 "register_operand" "r")
845 (match_operand:SI 2 "arith11_operand" "rI")]))]
847 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "8")])
852 [(set (match_operand:DI 0 "register_operand" "=r")
853 (match_operator:DI 3 "comparison_operator"
854 [(match_operand:DI 1 "register_operand" "r")
855 (match_operand:DI 2 "arith11_operand" "rI")]))]
857 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
858 [(set_attr "type" "binary")
859 (set_attr "length" "8")])
861 (define_insn "iorscc"
862 [(set (match_operand:SI 0 "register_operand" "=r")
863 (ior:SI (match_operator:SI 3 "comparison_operator"
864 [(match_operand:SI 1 "register_operand" "r")
865 (match_operand:SI 2 "arith11_operand" "rI")])
866 (match_operator:SI 6 "comparison_operator"
867 [(match_operand:SI 4 "register_operand" "r")
868 (match_operand:SI 5 "arith11_operand" "rI")])))]
870 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
871 [(set_attr "type" "binary")
872 (set_attr "length" "12")])
875 [(set (match_operand:DI 0 "register_operand" "=r")
876 (ior:DI (match_operator:DI 3 "comparison_operator"
877 [(match_operand:DI 1 "register_operand" "r")
878 (match_operand:DI 2 "arith11_operand" "rI")])
879 (match_operator:DI 6 "comparison_operator"
880 [(match_operand:DI 4 "register_operand" "r")
881 (match_operand:DI 5 "arith11_operand" "rI")])))]
883 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
884 [(set_attr "type" "binary")
885 (set_attr "length" "12")])
887 ;; Combiner patterns for common operations performed with the output
888 ;; from an scc insn (negscc and incscc).
889 (define_insn "negscc"
890 [(set (match_operand:SI 0 "register_operand" "=r")
891 (neg:SI (match_operator:SI 3 "comparison_operator"
892 [(match_operand:SI 1 "register_operand" "r")
893 (match_operand:SI 2 "arith11_operand" "rI")])))]
895 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
900 [(set (match_operand:DI 0 "register_operand" "=r")
901 (neg:DI (match_operator:DI 3 "comparison_operator"
902 [(match_operand:DI 1 "register_operand" "r")
903 (match_operand:DI 2 "arith11_operand" "rI")])))]
905 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
906 [(set_attr "type" "binary")
907 (set_attr "length" "8")])
909 ;; Patterns for adding/subtracting the result of a boolean expression from
910 ;; a register. First we have special patterns that make use of the carry
911 ;; bit, and output only two instructions. For the cases we can't in
912 ;; general do in two instructions, the incscc pattern at the end outputs
913 ;; two or three instructions.
916 [(set (match_operand:SI 0 "register_operand" "=r")
917 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
918 (match_operand:SI 3 "arith11_operand" "rI"))
919 (match_operand:SI 1 "register_operand" "r")))]
921 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
922 [(set_attr "type" "binary")
923 (set_attr "length" "8")])
926 [(set (match_operand:DI 0 "register_operand" "=r")
927 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
928 (match_operand:DI 3 "arith11_operand" "rI"))
929 (match_operand:DI 1 "register_operand" "r")))]
931 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
932 [(set_attr "type" "binary")
933 (set_attr "length" "8")])
935 ; This need only accept registers for op3, since canonicalization
936 ; replaces geu with gtu when op3 is an integer.
938 [(set (match_operand:SI 0 "register_operand" "=r")
939 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
940 (match_operand:SI 3 "register_operand" "r"))
941 (match_operand:SI 1 "register_operand" "r")))]
943 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
944 [(set_attr "type" "binary")
945 (set_attr "length" "8")])
948 [(set (match_operand:DI 0 "register_operand" "=r")
949 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
950 (match_operand:DI 3 "register_operand" "r"))
951 (match_operand:DI 1 "register_operand" "r")))]
953 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
954 [(set_attr "type" "binary")
955 (set_attr "length" "8")])
957 ; Match only integers for op3 here. This is used as canonical form of the
958 ; geu pattern when op3 is an integer. Don't match registers since we can't
959 ; make better code than the general incscc pattern.
961 [(set (match_operand:SI 0 "register_operand" "=r")
962 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
963 (match_operand:SI 3 "int11_operand" "I"))
964 (match_operand:SI 1 "register_operand" "r")))]
966 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
967 [(set_attr "type" "binary")
968 (set_attr "length" "8")])
971 [(set (match_operand:DI 0 "register_operand" "=r")
972 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
973 (match_operand:DI 3 "int11_operand" "I"))
974 (match_operand:DI 1 "register_operand" "r")))]
976 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
980 (define_insn "incscc"
981 [(set (match_operand:SI 0 "register_operand" "=r,r")
982 (plus:SI (match_operator:SI 4 "comparison_operator"
983 [(match_operand:SI 2 "register_operand" "r,r")
984 (match_operand:SI 3 "arith11_operand" "rI,rI")])
985 (match_operand:SI 1 "register_operand" "0,?r")))]
988 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
989 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
990 [(set_attr "type" "binary,binary")
991 (set_attr "length" "8,12")])
994 [(set (match_operand:DI 0 "register_operand" "=r,r")
995 (plus:DI (match_operator:DI 4 "comparison_operator"
996 [(match_operand:DI 2 "register_operand" "r,r")
997 (match_operand:DI 3 "arith11_operand" "rI,rI")])
998 (match_operand:DI 1 "register_operand" "0,?r")))]
1001 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
1002 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
1003 [(set_attr "type" "binary,binary")
1004 (set_attr "length" "8,12")])
1007 [(set (match_operand:SI 0 "register_operand" "=r")
1008 (minus:SI (match_operand:SI 1 "register_operand" "r")
1009 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1010 (match_operand:SI 3 "arith11_operand" "rI"))))]
1012 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1013 [(set_attr "type" "binary")
1014 (set_attr "length" "8")])
1017 [(set (match_operand:DI 0 "register_operand" "=r")
1018 (minus:DI (match_operand:DI 1 "register_operand" "r")
1019 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1020 (match_operand:DI 3 "arith11_operand" "rI"))))]
1022 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
1023 [(set_attr "type" "binary")
1024 (set_attr "length" "8")])
1027 [(set (match_operand:SI 0 "register_operand" "=r")
1028 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1029 (gtu:SI (match_operand:SI 2 "register_operand" "r")
1030 (match_operand:SI 3 "arith11_operand" "rI")))
1031 (match_operand:SI 4 "register_operand" "r")))]
1033 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1034 [(set_attr "type" "binary")
1035 (set_attr "length" "8")])
1038 [(set (match_operand:DI 0 "register_operand" "=r")
1039 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1040 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1041 (match_operand:DI 3 "arith11_operand" "rI")))
1042 (match_operand:DI 4 "register_operand" "r")))]
1044 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1045 [(set_attr "type" "binary")
1046 (set_attr "length" "8")])
1048 ; This need only accept registers for op3, since canonicalization
1049 ; replaces ltu with leu when op3 is an integer.
1051 [(set (match_operand:SI 0 "register_operand" "=r")
1052 (minus:SI (match_operand:SI 1 "register_operand" "r")
1053 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1054 (match_operand:SI 3 "register_operand" "r"))))]
1056 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1057 [(set_attr "type" "binary")
1058 (set_attr "length" "8")])
1061 [(set (match_operand:DI 0 "register_operand" "=r")
1062 (minus:DI (match_operand:DI 1 "register_operand" "r")
1063 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1064 (match_operand:DI 3 "register_operand" "r"))))]
1066 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1067 [(set_attr "type" "binary")
1068 (set_attr "length" "8")])
1071 [(set (match_operand:SI 0 "register_operand" "=r")
1072 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1073 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1074 (match_operand:SI 3 "register_operand" "r")))
1075 (match_operand:SI 4 "register_operand" "r")))]
1077 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1078 [(set_attr "type" "binary")
1079 (set_attr "length" "8")])
1082 [(set (match_operand:DI 0 "register_operand" "=r")
1083 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1084 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1085 (match_operand:DI 3 "register_operand" "r")))
1086 (match_operand:DI 4 "register_operand" "r")))]
1088 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1089 [(set_attr "type" "binary")
1090 (set_attr "length" "8")])
1092 ; Match only integers for op3 here. This is used as canonical form of the
1093 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1094 ; make better code than the general incscc pattern.
1096 [(set (match_operand:SI 0 "register_operand" "=r")
1097 (minus:SI (match_operand:SI 1 "register_operand" "r")
1098 (leu:SI (match_operand:SI 2 "register_operand" "r")
1099 (match_operand:SI 3 "int11_operand" "I"))))]
1101 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1102 [(set_attr "type" "binary")
1103 (set_attr "length" "8")])
1106 [(set (match_operand:DI 0 "register_operand" "=r")
1107 (minus:DI (match_operand:DI 1 "register_operand" "r")
1108 (leu:DI (match_operand:DI 2 "register_operand" "r")
1109 (match_operand:DI 3 "int11_operand" "I"))))]
1111 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1112 [(set_attr "type" "binary")
1113 (set_attr "length" "8")])
1116 [(set (match_operand:SI 0 "register_operand" "=r")
1117 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1118 (leu:SI (match_operand:SI 2 "register_operand" "r")
1119 (match_operand:SI 3 "int11_operand" "I")))
1120 (match_operand:SI 4 "register_operand" "r")))]
1122 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1123 [(set_attr "type" "binary")
1124 (set_attr "length" "8")])
1127 [(set (match_operand:DI 0 "register_operand" "=r")
1128 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1129 (leu:DI (match_operand:DI 2 "register_operand" "r")
1130 (match_operand:DI 3 "int11_operand" "I")))
1131 (match_operand:DI 4 "register_operand" "r")))]
1133 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1134 [(set_attr "type" "binary")
1135 (set_attr "length" "8")])
1137 (define_insn "decscc"
1138 [(set (match_operand:SI 0 "register_operand" "=r,r")
1139 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1140 (match_operator:SI 4 "comparison_operator"
1141 [(match_operand:SI 2 "register_operand" "r,r")
1142 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1145 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1146 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1147 [(set_attr "type" "binary,binary")
1148 (set_attr "length" "8,12")])
1151 [(set (match_operand:DI 0 "register_operand" "=r,r")
1152 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1153 (match_operator:DI 4 "comparison_operator"
1154 [(match_operand:DI 2 "register_operand" "r,r")
1155 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1158 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1159 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1160 [(set_attr "type" "binary,binary")
1161 (set_attr "length" "8,12")])
1163 ; Patterns for max and min. (There is no need for an earlyclobber in the
1164 ; last alternative since the middle alternative will match if op0 == op1.)
1166 (define_insn "sminsi3"
1167 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1168 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1169 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1172 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1173 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1174 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1175 [(set_attr "type" "multi,multi,multi")
1176 (set_attr "length" "8,8,8")])
1178 (define_insn "smindi3"
1179 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1180 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1181 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1184 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1185 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1186 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1187 [(set_attr "type" "multi,multi,multi")
1188 (set_attr "length" "8,8,8")])
1190 (define_insn "uminsi3"
1191 [(set (match_operand:SI 0 "register_operand" "=r,r")
1192 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1193 (match_operand:SI 2 "arith11_operand" "r,I")))]
1196 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1197 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1198 [(set_attr "type" "multi,multi")
1199 (set_attr "length" "8,8")])
1201 (define_insn "umindi3"
1202 [(set (match_operand:DI 0 "register_operand" "=r,r")
1203 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1204 (match_operand:DI 2 "arith11_operand" "r,I")))]
1207 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1208 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1209 [(set_attr "type" "multi,multi")
1210 (set_attr "length" "8,8")])
1212 (define_insn "smaxsi3"
1213 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1214 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1215 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1218 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1219 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1220 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1221 [(set_attr "type" "multi,multi,multi")
1222 (set_attr "length" "8,8,8")])
1224 (define_insn "smaxdi3"
1225 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1226 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1227 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1230 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1231 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1232 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1233 [(set_attr "type" "multi,multi,multi")
1234 (set_attr "length" "8,8,8")])
1236 (define_insn "umaxsi3"
1237 [(set (match_operand:SI 0 "register_operand" "=r,r")
1238 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1239 (match_operand:SI 2 "arith11_operand" "r,I")))]
1242 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1243 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1244 [(set_attr "type" "multi,multi")
1245 (set_attr "length" "8,8")])
1247 (define_insn "umaxdi3"
1248 [(set (match_operand:DI 0 "register_operand" "=r,r")
1249 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1250 (match_operand:DI 2 "arith11_operand" "r,I")))]
1253 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1254 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1255 [(set_attr "type" "multi,multi")
1256 (set_attr "length" "8,8")])
1258 (define_insn "abssi2"
1259 [(set (match_operand:SI 0 "register_operand" "=r")
1260 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1262 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1263 [(set_attr "type" "multi")
1264 (set_attr "length" "8")])
1266 (define_insn "absdi2"
1267 [(set (match_operand:DI 0 "register_operand" "=r")
1268 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1270 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1271 [(set_attr "type" "multi")
1272 (set_attr "length" "8")])
1274 ;;; Experimental conditional move patterns
1276 (define_expand "movsicc"
1277 [(set (match_operand:SI 0 "register_operand" "")
1279 (match_operator 1 "comparison_operator"
1282 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1283 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1287 enum rtx_code code = GET_CODE (operands[1]);
1289 if (hppa_branch_type != CMP_SI)
1292 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1293 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1296 /* operands[1] is currently the result of compare_from_rtx. We want to
1297 emit a compare of the original operands. */
1298 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1299 operands[4] = hppa_compare_op0;
1300 operands[5] = hppa_compare_op1;
1303 ;; We used to accept any register for op1.
1305 ;; However, it loses sometimes because the compiler will end up using
1306 ;; different registers for op0 and op1 in some critical cases. local-alloc
1307 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1309 ;; If/when global register allocation supports tying we should allow any
1310 ;; register for op1 again.
1312 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1314 (match_operator 2 "comparison_operator"
1315 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1316 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1317 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1321 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1322 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1323 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1324 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1325 [(set_attr "type" "multi,multi,multi,nullshift")
1326 (set_attr "length" "8,8,8,8")])
1329 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1331 (match_operator 5 "comparison_operator"
1332 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1333 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1334 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1335 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1338 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1339 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1340 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1341 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1342 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1343 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1344 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1345 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1346 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1347 (set_attr "length" "8,8,8,8,8,8,8,8")])
1349 (define_expand "movdicc"
1350 [(set (match_operand:DI 0 "register_operand" "")
1352 (match_operator 1 "comparison_operator"
1355 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1356 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1360 enum rtx_code code = GET_CODE (operands[1]);
1362 if (hppa_branch_type != CMP_SI)
1365 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1366 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1369 /* operands[1] is currently the result of compare_from_rtx. We want to
1370 emit a compare of the original operands. */
1371 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1372 operands[4] = hppa_compare_op0;
1373 operands[5] = hppa_compare_op1;
1376 ; We need the first constraint alternative in order to avoid
1377 ; earlyclobbers on all other alternatives.
1379 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1381 (match_operator 2 "comparison_operator"
1382 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1383 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1384 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1388 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1389 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1390 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1391 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1392 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1393 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1394 (set_attr "length" "8,8,8,8,8")])
1397 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1399 (match_operator 5 "comparison_operator"
1400 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1401 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1402 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1403 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1406 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1407 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1408 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1409 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1410 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1411 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1412 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1413 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1414 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1415 (set_attr "length" "8,8,8,8,8,8,8,8")])
1417 ;; Conditional Branches
1419 (define_expand "beq"
1421 (if_then_else (eq (match_dup 1) (match_dup 2))
1422 (label_ref (match_operand 0 "" ""))
1427 if (hppa_branch_type != CMP_SI)
1429 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1430 emit_bcond_fp (NE, operands[0]);
1433 /* set up operands from compare. */
1434 operands[1] = hppa_compare_op0;
1435 operands[2] = hppa_compare_op1;
1436 /* fall through and generate default code */
1439 (define_expand "bne"
1441 (if_then_else (ne (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bgt"
1459 (if_then_else (gt (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "blt"
1477 (if_then_else (lt (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bge"
1495 (if_then_else (ge (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1504 emit_bcond_fp (NE, operands[0]);
1507 operands[1] = hppa_compare_op0;
1508 operands[2] = hppa_compare_op1;
1511 (define_expand "ble"
1513 (if_then_else (le (match_dup 1) (match_dup 2))
1514 (label_ref (match_operand 0 "" ""))
1519 if (hppa_branch_type != CMP_SI)
1521 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1522 emit_bcond_fp (NE, operands[0]);
1525 operands[1] = hppa_compare_op0;
1526 operands[2] = hppa_compare_op1;
1529 (define_expand "bgtu"
1531 (if_then_else (gtu (match_dup 1) (match_dup 2))
1532 (label_ref (match_operand 0 "" ""))
1537 if (hppa_branch_type != CMP_SI)
1539 operands[1] = hppa_compare_op0;
1540 operands[2] = hppa_compare_op1;
1543 (define_expand "bltu"
1545 (if_then_else (ltu (match_dup 1) (match_dup 2))
1546 (label_ref (match_operand 0 "" ""))
1551 if (hppa_branch_type != CMP_SI)
1553 operands[1] = hppa_compare_op0;
1554 operands[2] = hppa_compare_op1;
1557 (define_expand "bgeu"
1559 (if_then_else (geu (match_dup 1) (match_dup 2))
1560 (label_ref (match_operand 0 "" ""))
1565 if (hppa_branch_type != CMP_SI)
1567 operands[1] = hppa_compare_op0;
1568 operands[2] = hppa_compare_op1;
1571 (define_expand "bleu"
1573 (if_then_else (leu (match_dup 1) (match_dup 2))
1574 (label_ref (match_operand 0 "" ""))
1579 if (hppa_branch_type != CMP_SI)
1581 operands[1] = hppa_compare_op0;
1582 operands[2] = hppa_compare_op1;
1585 (define_expand "bltgt"
1587 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1588 (label_ref (match_operand 0 "" ""))
1593 if (hppa_branch_type == CMP_SI)
1595 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1596 emit_bcond_fp (NE, operands[0]);
1600 (define_expand "bunle"
1602 (if_then_else (unle (match_dup 1) (match_dup 2))
1603 (label_ref (match_operand 0 "" ""))
1608 if (hppa_branch_type == CMP_SI)
1610 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1611 emit_bcond_fp (NE, operands[0]);
1615 (define_expand "bunlt"
1617 (if_then_else (unlt (match_dup 1) (match_dup 2))
1618 (label_ref (match_operand 0 "" ""))
1623 if (hppa_branch_type == CMP_SI)
1625 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1626 emit_bcond_fp (NE, operands[0]);
1630 (define_expand "bunge"
1632 (if_then_else (unge (match_dup 1) (match_dup 2))
1633 (label_ref (match_operand 0 "" ""))
1638 if (hppa_branch_type == CMP_SI)
1640 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1641 emit_bcond_fp (NE, operands[0]);
1645 (define_expand "bungt"
1647 (if_then_else (ungt (match_dup 1) (match_dup 2))
1648 (label_ref (match_operand 0 "" ""))
1653 if (hppa_branch_type == CMP_SI)
1655 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1656 emit_bcond_fp (NE, operands[0]);
1660 (define_expand "buneq"
1662 (if_then_else (uneq (match_dup 1) (match_dup 2))
1663 (label_ref (match_operand 0 "" ""))
1668 if (hppa_branch_type == CMP_SI)
1670 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1671 emit_bcond_fp (NE, operands[0]);
1675 (define_expand "bunordered"
1677 (if_then_else (unordered (match_dup 1) (match_dup 2))
1678 (label_ref (match_operand 0 "" ""))
1683 if (hppa_branch_type == CMP_SI)
1685 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1686 emit_bcond_fp (NE, operands[0]);
1690 (define_expand "bordered"
1692 (if_then_else (ordered (match_dup 1) (match_dup 2))
1693 (label_ref (match_operand 0 "" ""))
1698 if (hppa_branch_type == CMP_SI)
1700 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1701 emit_bcond_fp (NE, operands[0]);
1705 ;; Match the branch patterns.
1708 ;; Note a long backward conditional branch with an annulled delay slot
1709 ;; has a length of 12.
1713 (match_operator 3 "comparison_operator"
1714 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1715 (match_operand:SI 2 "arith5_operand" "rL")])
1716 (label_ref (match_operand 0 "" ""))
1721 return output_cbranch (operands, 0, insn);
1723 [(set_attr "type" "cbranch")
1724 (set (attr "length")
1725 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1726 (const_int MAX_12BIT_OFFSET))
1728 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1729 (const_int MAX_17BIT_OFFSET))
1731 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1733 (eq (symbol_ref "flag_pic") (const_int 0))
1737 ;; Match the negated branch.
1742 (match_operator 3 "comparison_operator"
1743 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1744 (match_operand:SI 2 "arith5_operand" "rL")])
1746 (label_ref (match_operand 0 "" ""))))]
1750 return output_cbranch (operands, 1, insn);
1752 [(set_attr "type" "cbranch")
1753 (set (attr "length")
1754 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1755 (const_int MAX_12BIT_OFFSET))
1757 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1758 (const_int MAX_17BIT_OFFSET))
1760 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1762 (eq (symbol_ref "flag_pic") (const_int 0))
1769 (match_operator 3 "comparison_operator"
1770 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1771 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1772 (label_ref (match_operand 0 "" ""))
1777 return output_cbranch (operands, 0, insn);
1779 [(set_attr "type" "cbranch")
1780 (set (attr "length")
1781 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1782 (const_int MAX_12BIT_OFFSET))
1784 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1785 (const_int MAX_17BIT_OFFSET))
1787 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1789 (eq (symbol_ref "flag_pic") (const_int 0))
1793 ;; Match the negated branch.
1798 (match_operator 3 "comparison_operator"
1799 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1800 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1802 (label_ref (match_operand 0 "" ""))))]
1806 return output_cbranch (operands, 1, insn);
1808 [(set_attr "type" "cbranch")
1809 (set (attr "length")
1810 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1811 (const_int MAX_12BIT_OFFSET))
1813 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1814 (const_int MAX_17BIT_OFFSET))
1816 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1818 (eq (symbol_ref "flag_pic") (const_int 0))
1824 (match_operator 3 "cmpib_comparison_operator"
1825 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1826 (match_operand:DI 2 "arith5_operand" "rL")])
1827 (label_ref (match_operand 0 "" ""))
1832 return output_cbranch (operands, 0, insn);
1834 [(set_attr "type" "cbranch")
1835 (set (attr "length")
1836 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1837 (const_int MAX_12BIT_OFFSET))
1839 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1840 (const_int MAX_17BIT_OFFSET))
1842 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1844 (eq (symbol_ref "flag_pic") (const_int 0))
1848 ;; Match the negated branch.
1853 (match_operator 3 "cmpib_comparison_operator"
1854 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1855 (match_operand:DI 2 "arith5_operand" "rL")])
1857 (label_ref (match_operand 0 "" ""))))]
1861 return output_cbranch (operands, 1, insn);
1863 [(set_attr "type" "cbranch")
1864 (set (attr "length")
1865 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1866 (const_int MAX_12BIT_OFFSET))
1868 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1869 (const_int MAX_17BIT_OFFSET))
1871 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1873 (eq (symbol_ref "flag_pic") (const_int 0))
1877 ;; Branch on Bit patterns.
1881 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1883 (match_operand:SI 1 "uint5_operand" ""))
1885 (label_ref (match_operand 2 "" ""))
1890 return output_bb (operands, 0, insn, 0);
1892 [(set_attr "type" "cbranch")
1893 (set (attr "length")
1894 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1895 (const_int MAX_12BIT_OFFSET))
1897 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1898 (const_int MAX_17BIT_OFFSET))
1900 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1902 (eq (symbol_ref "flag_pic") (const_int 0))
1909 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1911 (match_operand:DI 1 "uint32_operand" ""))
1913 (label_ref (match_operand 2 "" ""))
1918 return output_bb (operands, 0, insn, 0);
1920 [(set_attr "type" "cbranch")
1921 (set (attr "length")
1922 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1923 (const_int MAX_12BIT_OFFSET))
1925 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1926 (const_int MAX_17BIT_OFFSET))
1928 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1930 (eq (symbol_ref "flag_pic") (const_int 0))
1937 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1939 (match_operand:SI 1 "uint5_operand" ""))
1942 (label_ref (match_operand 2 "" ""))))]
1946 return output_bb (operands, 1, insn, 0);
1948 [(set_attr "type" "cbranch")
1949 (set (attr "length")
1950 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1951 (const_int MAX_12BIT_OFFSET))
1953 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1954 (const_int MAX_17BIT_OFFSET))
1956 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1958 (eq (symbol_ref "flag_pic") (const_int 0))
1965 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1967 (match_operand:DI 1 "uint32_operand" ""))
1970 (label_ref (match_operand 2 "" ""))))]
1974 return output_bb (operands, 1, insn, 0);
1976 [(set_attr "type" "cbranch")
1977 (set (attr "length")
1978 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1979 (const_int MAX_12BIT_OFFSET))
1981 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1982 (const_int MAX_17BIT_OFFSET))
1984 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
1986 (eq (symbol_ref "flag_pic") (const_int 0))
1993 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1995 (match_operand:SI 1 "uint5_operand" ""))
1997 (label_ref (match_operand 2 "" ""))
2002 return output_bb (operands, 0, insn, 1);
2004 [(set_attr "type" "cbranch")
2005 (set (attr "length")
2006 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2007 (const_int MAX_12BIT_OFFSET))
2009 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2010 (const_int MAX_17BIT_OFFSET))
2012 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2014 (eq (symbol_ref "flag_pic") (const_int 0))
2021 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2023 (match_operand:DI 1 "uint32_operand" ""))
2025 (label_ref (match_operand 2 "" ""))
2030 return output_bb (operands, 0, insn, 1);
2032 [(set_attr "type" "cbranch")
2033 (set (attr "length")
2034 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2035 (const_int MAX_12BIT_OFFSET))
2037 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (const_int MAX_17BIT_OFFSET))
2040 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2042 (eq (symbol_ref "flag_pic") (const_int 0))
2049 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2051 (match_operand:SI 1 "uint5_operand" ""))
2054 (label_ref (match_operand 2 "" ""))))]
2058 return output_bb (operands, 1, insn, 1);
2060 [(set_attr "type" "cbranch")
2061 (set (attr "length")
2062 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2063 (const_int MAX_12BIT_OFFSET))
2065 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2066 (const_int MAX_17BIT_OFFSET))
2068 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2070 (eq (symbol_ref "flag_pic") (const_int 0))
2077 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2079 (match_operand:DI 1 "uint32_operand" ""))
2082 (label_ref (match_operand 2 "" ""))))]
2086 return output_bb (operands, 1, insn, 1);
2088 [(set_attr "type" "cbranch")
2089 (set (attr "length")
2090 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2091 (const_int MAX_12BIT_OFFSET))
2093 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2094 (const_int MAX_17BIT_OFFSET))
2096 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2098 (eq (symbol_ref "flag_pic") (const_int 0))
2102 ;; Branch on Variable Bit patterns.
2106 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2108 (match_operand:SI 1 "register_operand" "q"))
2110 (label_ref (match_operand 2 "" ""))
2115 return output_bvb (operands, 0, insn, 0);
2117 [(set_attr "type" "cbranch")
2118 (set (attr "length")
2119 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2120 (const_int MAX_12BIT_OFFSET))
2122 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2123 (const_int MAX_17BIT_OFFSET))
2125 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2127 (eq (symbol_ref "flag_pic") (const_int 0))
2134 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2136 (match_operand:DI 1 "register_operand" "q"))
2138 (label_ref (match_operand 2 "" ""))
2143 return output_bvb (operands, 0, insn, 0);
2145 [(set_attr "type" "cbranch")
2146 (set (attr "length")
2147 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (const_int MAX_12BIT_OFFSET))
2150 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2151 (const_int MAX_17BIT_OFFSET))
2153 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2155 (eq (symbol_ref "flag_pic") (const_int 0))
2162 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2164 (match_operand:SI 1 "register_operand" "q"))
2167 (label_ref (match_operand 2 "" ""))))]
2171 return output_bvb (operands, 1, insn, 0);
2173 [(set_attr "type" "cbranch")
2174 (set (attr "length")
2175 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2176 (const_int MAX_12BIT_OFFSET))
2178 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2179 (const_int MAX_17BIT_OFFSET))
2181 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2183 (eq (symbol_ref "flag_pic") (const_int 0))
2190 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2192 (match_operand:DI 1 "register_operand" "q"))
2195 (label_ref (match_operand 2 "" ""))))]
2199 return output_bvb (operands, 1, insn, 0);
2201 [(set_attr "type" "cbranch")
2202 (set (attr "length")
2203 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2204 (const_int MAX_12BIT_OFFSET))
2206 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2207 (const_int MAX_17BIT_OFFSET))
2209 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2211 (eq (symbol_ref "flag_pic") (const_int 0))
2218 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2220 (match_operand:SI 1 "register_operand" "q"))
2222 (label_ref (match_operand 2 "" ""))
2227 return output_bvb (operands, 0, insn, 1);
2229 [(set_attr "type" "cbranch")
2230 (set (attr "length")
2231 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2232 (const_int MAX_12BIT_OFFSET))
2234 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2235 (const_int MAX_17BIT_OFFSET))
2237 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2239 (eq (symbol_ref "flag_pic") (const_int 0))
2246 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2248 (match_operand:DI 1 "register_operand" "q"))
2250 (label_ref (match_operand 2 "" ""))
2255 return output_bvb (operands, 0, insn, 1);
2257 [(set_attr "type" "cbranch")
2258 (set (attr "length")
2259 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2260 (const_int MAX_12BIT_OFFSET))
2262 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2263 (const_int MAX_17BIT_OFFSET))
2265 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2267 (eq (symbol_ref "flag_pic") (const_int 0))
2274 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2276 (match_operand:SI 1 "register_operand" "q"))
2279 (label_ref (match_operand 2 "" ""))))]
2283 return output_bvb (operands, 1, insn, 1);
2285 [(set_attr "type" "cbranch")
2286 (set (attr "length")
2287 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2288 (const_int MAX_12BIT_OFFSET))
2290 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2291 (const_int MAX_17BIT_OFFSET))
2293 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2295 (eq (symbol_ref "flag_pic") (const_int 0))
2302 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2304 (match_operand:DI 1 "register_operand" "q"))
2307 (label_ref (match_operand 2 "" ""))))]
2311 return output_bvb (operands, 1, insn, 1);
2313 [(set_attr "type" "cbranch")
2314 (set (attr "length")
2315 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2316 (const_int MAX_12BIT_OFFSET))
2318 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2319 (const_int MAX_17BIT_OFFSET))
2321 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2323 (eq (symbol_ref "flag_pic") (const_int 0))
2327 ;; Floating point branches
2329 ;; ??? Nullification is handled differently from other branches.
2330 ;; If nullification is specified, the delay slot is nullified on any
2331 ;; taken branch regardless of branch direction.
2333 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2334 (label_ref (match_operand 0 "" ""))
2336 "!TARGET_SOFT_FLOAT"
2339 int length = get_attr_length (insn);
2341 int nullify, xdelay;
2344 return \"ftest\;b%* %l0\";
2346 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2350 xoperands[0] = GEN_INT (length - 8);
2356 xoperands[0] = GEN_INT (length - 4);
2360 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b,n .+%0\", xoperands);
2362 output_asm_insn (\"ftest\;add,tr %%r0,%%r0,%%r0\;b .+%0\", xoperands);
2363 return output_lbranch (operands[0], insn, xdelay);
2365 [(set_attr "type" "fbranch")
2366 (set (attr "length")
2367 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2368 (const_int MAX_17BIT_OFFSET))
2370 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2372 (eq (symbol_ref "flag_pic") (const_int 0))
2377 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2379 (label_ref (match_operand 0 "" ""))))]
2380 "!TARGET_SOFT_FLOAT"
2383 int length = get_attr_length (insn);
2385 int nullify, xdelay;
2388 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2390 if (dbr_sequence_length () == 0 || INSN_ANNULLED_BRANCH_P (insn))
2394 xoperands[0] = GEN_INT (length - 4);
2400 xoperands[0] = GEN_INT (length);
2404 output_asm_insn (\"ftest\;b,n .+%0\", xoperands);
2406 output_asm_insn (\"ftest\;b .+%0\", xoperands);
2407 return output_lbranch (operands[0], insn, xdelay);
2409 [(set_attr "type" "fbranch")
2410 (set (attr "length")
2411 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
2412 (const_int MAX_17BIT_OFFSET))
2414 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
2416 (eq (symbol_ref "flag_pic") (const_int 0))
2420 ;; Move instructions
2422 (define_expand "movsi"
2423 [(set (match_operand:SI 0 "general_operand" "")
2424 (match_operand:SI 1 "general_operand" ""))]
2428 if (emit_move_sequence (operands, SImode, 0))
2432 ;; Handle SImode input reloads requiring %r1 as a scratch register.
2433 (define_expand "reload_insi_r1"
2434 [(set (match_operand:SI 0 "register_operand" "=Z")
2435 (match_operand:SI 1 "non_hard_reg_operand" ""))
2436 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
2440 if (emit_move_sequence (operands, SImode, operands[2]))
2443 /* We don't want the clobber emitted, so handle this ourselves. */
2444 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2448 ;; Handle SImode input reloads requiring a general register as a
2449 ;; scratch register.
2450 (define_expand "reload_insi"
2451 [(set (match_operand:SI 0 "register_operand" "=Z")
2452 (match_operand:SI 1 "non_hard_reg_operand" ""))
2453 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2457 if (emit_move_sequence (operands, SImode, operands[2]))
2460 /* We don't want the clobber emitted, so handle this ourselves. */
2461 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2465 ;; Handle SImode output reloads requiring a general register as a
2466 ;; scratch register.
2467 (define_expand "reload_outsi"
2468 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2469 (match_operand:SI 1 "register_operand" "Z"))
2470 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2474 if (emit_move_sequence (operands, SImode, operands[2]))
2477 /* We don't want the clobber emitted, so handle this ourselves. */
2478 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2483 [(set (match_operand:SI 0 "move_dest_operand"
2484 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T,!r,!f")
2485 (match_operand:SI 1 "move_src_operand"
2486 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f,!f,!r"))]
2487 "(register_operand (operands[0], SImode)
2488 || reg_or_0_operand (operands[1], SImode))
2489 && !TARGET_SOFT_FLOAT
2496 {zdepi|depwi,z} %Z1,%0
2500 {mfctl|mfctl,w} %%sar,%0
2504 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
2505 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
2506 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore,move,move")
2507 (set_attr "pa_combine_type" "addmove")
2508 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,8,8")])
2511 [(set (match_operand:SI 0 "move_dest_operand"
2512 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2513 (match_operand:SI 1 "move_src_operand"
2514 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2515 "(register_operand (operands[0], SImode)
2516 || reg_or_0_operand (operands[1], SImode))
2517 && !TARGET_SOFT_FLOAT
2524 {zdepi|depwi,z} %Z1,%0
2528 {mfctl|mfctl,w} %%sar,%0
2532 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2533 (set_attr "pa_combine_type" "addmove")
2534 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2537 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2538 (match_operand:SI 1 "register_operand" "f"))]
2540 && !TARGET_DISABLE_INDEXING
2541 && reload_completed"
2543 [(set_attr "type" "fpstore")
2544 (set_attr "pa_combine_type" "addmove")
2545 (set_attr "length" "4")])
2547 ; Rewrite RTL using an indexed store. This will allow the insn that
2548 ; computes the address to be deleted if the register it sets is dead.
2550 [(set (match_operand:SI 0 "register_operand" "")
2551 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2553 (match_operand:SI 2 "register_operand" "")))
2554 (set (mem:SI (match_dup 0))
2555 (match_operand:SI 3 "register_operand" ""))]
2557 && !TARGET_DISABLE_INDEXING
2558 && REG_OK_FOR_BASE_P (operands[2])
2559 && FP_REGNO_P (REGNO (operands[3]))"
2560 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2562 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2567 [(set (match_operand:SI 0 "register_operand" "")
2568 (plus:SI (match_operand:SI 2 "register_operand" "")
2569 (mult:SI (match_operand:SI 1 "register_operand" "")
2571 (set (mem:SI (match_dup 0))
2572 (match_operand:SI 3 "register_operand" ""))]
2574 && !TARGET_DISABLE_INDEXING
2575 && REG_OK_FOR_BASE_P (operands[2])
2576 && FP_REGNO_P (REGNO (operands[3]))"
2577 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2579 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2584 [(set (match_operand:DI 0 "register_operand" "")
2585 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2587 (match_operand:DI 2 "register_operand" "")))
2588 (set (mem:SI (match_dup 0))
2589 (match_operand:SI 3 "register_operand" ""))]
2591 && !TARGET_DISABLE_INDEXING
2593 && REG_OK_FOR_BASE_P (operands[2])
2594 && FP_REGNO_P (REGNO (operands[3]))"
2595 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2597 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2602 [(set (match_operand:DI 0 "register_operand" "")
2603 (plus:DI (match_operand:DI 2 "register_operand" "")
2604 (mult:DI (match_operand:DI 1 "register_operand" "")
2606 (set (mem:SI (match_dup 0))
2607 (match_operand:SI 3 "register_operand" ""))]
2609 && !TARGET_DISABLE_INDEXING
2611 && REG_OK_FOR_BASE_P (operands[2])
2612 && FP_REGNO_P (REGNO (operands[3]))"
2613 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2615 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2620 [(set (match_operand:SI 0 "register_operand" "")
2621 (plus:SI (match_operand:SI 1 "register_operand" "")
2622 (match_operand:SI 2 "register_operand" "")))
2623 (set (mem:SI (match_dup 0))
2624 (match_operand:SI 3 "register_operand" ""))]
2626 && !TARGET_DISABLE_INDEXING
2627 && TARGET_NO_SPACE_REGS
2628 && REG_OK_FOR_INDEX_P (operands[1])
2629 && REG_OK_FOR_BASE_P (operands[2])
2630 && FP_REGNO_P (REGNO (operands[3]))"
2631 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2633 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2637 [(set (match_operand:SI 0 "register_operand" "")
2638 (plus:SI (match_operand:SI 1 "register_operand" "")
2639 (match_operand:SI 2 "register_operand" "")))
2640 (set (mem:SI (match_dup 0))
2641 (match_operand:SI 3 "register_operand" ""))]
2643 && !TARGET_DISABLE_INDEXING
2644 && TARGET_NO_SPACE_REGS
2645 && REG_OK_FOR_BASE_P (operands[1])
2646 && REG_OK_FOR_INDEX_P (operands[2])
2647 && FP_REGNO_P (REGNO (operands[3]))"
2648 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2650 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2654 [(set (match_operand:DI 0 "register_operand" "")
2655 (plus:DI (match_operand:DI 1 "register_operand" "")
2656 (match_operand:DI 2 "register_operand" "")))
2657 (set (mem:SI (match_dup 0))
2658 (match_operand:SI 3 "register_operand" ""))]
2660 && !TARGET_DISABLE_INDEXING
2662 && TARGET_NO_SPACE_REGS
2663 && REG_OK_FOR_INDEX_P (operands[1])
2664 && REG_OK_FOR_BASE_P (operands[2])
2665 && FP_REGNO_P (REGNO (operands[3]))"
2666 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2668 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2672 [(set (match_operand:DI 0 "register_operand" "")
2673 (plus:DI (match_operand:DI 1 "register_operand" "")
2674 (match_operand:DI 2 "register_operand" "")))
2675 (set (mem:SI (match_dup 0))
2676 (match_operand:SI 3 "register_operand" ""))]
2678 && !TARGET_DISABLE_INDEXING
2680 && TARGET_NO_SPACE_REGS
2681 && REG_OK_FOR_BASE_P (operands[1])
2682 && REG_OK_FOR_INDEX_P (operands[2])
2683 && FP_REGNO_P (REGNO (operands[3]))"
2684 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2686 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2690 [(set (match_operand:SI 0 "move_dest_operand"
2691 "=r,r,r,r,r,r,Q,!*q,!r")
2692 (match_operand:SI 1 "move_src_operand"
2693 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2694 "(register_operand (operands[0], SImode)
2695 || reg_or_0_operand (operands[1], SImode))
2696 && TARGET_SOFT_FLOAT"
2702 {zdepi|depwi,z} %Z1,%0
2706 {mfctl|mfctl,w} %%sar,%0"
2707 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2708 (set_attr "pa_combine_type" "addmove")
2709 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2711 ;; Load or store with base-register modification.
2713 [(set (match_operand:SI 0 "register_operand" "=r")
2714 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2715 (match_operand:DI 2 "int5_operand" "L"))))
2717 (plus:DI (match_dup 1) (match_dup 2)))]
2720 [(set_attr "type" "load")
2721 (set_attr "length" "4")])
2723 ; And a zero extended variant.
2725 [(set (match_operand:DI 0 "register_operand" "=r")
2726 (zero_extend:DI (mem:SI
2728 (match_operand:DI 1 "register_operand" "+r")
2729 (match_operand:DI 2 "int5_operand" "L")))))
2731 (plus:DI (match_dup 1) (match_dup 2)))]
2734 [(set_attr "type" "load")
2735 (set_attr "length" "4")])
2737 (define_expand "pre_load"
2738 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2739 (mem (plus (match_operand 1 "register_operand" "")
2740 (match_operand 2 "pre_cint_operand" ""))))
2742 (plus (match_dup 1) (match_dup 2)))])]
2748 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2751 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2755 (define_insn "pre_ldw"
2756 [(set (match_operand:SI 0 "register_operand" "=r")
2757 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2758 (match_operand:SI 2 "pre_cint_operand" ""))))
2760 (plus:SI (match_dup 1) (match_dup 2)))]
2764 if (INTVAL (operands[2]) < 0)
2765 return \"{ldwm|ldw,mb} %2(%1),%0\";
2766 return \"{ldws|ldw},mb %2(%1),%0\";
2768 [(set_attr "type" "load")
2769 (set_attr "length" "4")])
2771 (define_insn "pre_ldd"
2772 [(set (match_operand:DI 0 "register_operand" "=r")
2773 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2774 (match_operand:DI 2 "pre_cint_operand" ""))))
2776 (plus:DI (match_dup 1) (match_dup 2)))]
2779 [(set_attr "type" "load")
2780 (set_attr "length" "4")])
2783 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2784 (match_operand:SI 1 "pre_cint_operand" "")))
2785 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2787 (plus:SI (match_dup 0) (match_dup 1)))]
2791 if (INTVAL (operands[1]) < 0)
2792 return \"{stwm|stw,mb} %r2,%1(%0)\";
2793 return \"{stws|stw},mb %r2,%1(%0)\";
2795 [(set_attr "type" "store")
2796 (set_attr "length" "4")])
2799 [(set (match_operand:SI 0 "register_operand" "=r")
2800 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2802 (plus:SI (match_dup 1)
2803 (match_operand:SI 2 "post_cint_operand" "")))]
2807 if (INTVAL (operands[2]) > 0)
2808 return \"{ldwm|ldw,ma} %2(%1),%0\";
2809 return \"{ldws|ldw},ma %2(%1),%0\";
2811 [(set_attr "type" "load")
2812 (set_attr "length" "4")])
2814 (define_expand "post_store"
2815 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2816 (match_operand 1 "reg_or_0_operand" ""))
2819 (match_operand 2 "post_cint_operand" "")))])]
2825 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2828 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2832 (define_insn "post_stw"
2833 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2834 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2836 (plus:SI (match_dup 0)
2837 (match_operand:SI 2 "post_cint_operand" "")))]
2841 if (INTVAL (operands[2]) > 0)
2842 return \"{stwm|stw,ma} %r1,%2(%0)\";
2843 return \"{stws|stw},ma %r1,%2(%0)\";
2845 [(set_attr "type" "store")
2846 (set_attr "length" "4")])
2848 (define_insn "post_std"
2849 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2850 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2852 (plus:DI (match_dup 0)
2853 (match_operand:DI 2 "post_cint_operand" "")))]
2856 [(set_attr "type" "store")
2857 (set_attr "length" "4")])
2859 ;; For loading the address of a label while generating PIC code.
2860 ;; Note since this pattern can be created at reload time (via movsi), all
2861 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2863 [(set (match_operand 0 "pmode_register_operand" "=a")
2864 (match_operand 1 "pic_label_operand" ""))]
2870 xoperands[0] = operands[0];
2871 xoperands[1] = operands[1];
2872 xoperands[2] = gen_label_rtx ();
2874 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2875 CODE_LABEL_NUMBER (xoperands[2]));
2876 output_asm_insn (\"mfia %0\", xoperands);
2878 /* If we're trying to load the address of a label that happens to be
2879 close, then we can use a shorter sequence. */
2880 if (GET_CODE (operands[1]) == LABEL_REF
2881 && !LABEL_REF_NONLOCAL_P (operands[1])
2882 && INSN_ADDRESSES_SET_P ()
2883 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2884 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2885 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2888 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2889 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2893 [(set_attr "type" "multi")
2894 (set_attr "length" "12")]) ; 8 or 12
2897 [(set (match_operand 0 "pmode_register_operand" "=a")
2898 (match_operand 1 "pic_label_operand" ""))]
2904 xoperands[0] = operands[0];
2905 xoperands[1] = operands[1];
2906 xoperands[2] = gen_label_rtx ();
2908 output_asm_insn (\"bl .+8,%0\", xoperands);
2909 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2910 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2911 CODE_LABEL_NUMBER (xoperands[2]));
2913 /* If we're trying to load the address of a label that happens to be
2914 close, then we can use a shorter sequence. */
2915 if (GET_CODE (operands[1]) == LABEL_REF
2916 && !LABEL_REF_NONLOCAL_P (operands[1])
2917 && INSN_ADDRESSES_SET_P ()
2918 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2919 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2920 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2923 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2924 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2928 [(set_attr "type" "multi")
2929 (set_attr "length" "16")]) ; 12 or 16
2932 [(set (match_operand:SI 0 "register_operand" "=a")
2933 (plus:SI (match_operand:SI 1 "register_operand" "r")
2934 (high:SI (match_operand 2 "" ""))))]
2935 "symbolic_operand (operands[2], Pmode)
2936 && ! function_label_operand (operands[2], Pmode)
2939 [(set_attr "type" "binary")
2940 (set_attr "length" "4")])
2943 [(set (match_operand:DI 0 "register_operand" "=a")
2944 (plus:DI (match_operand:DI 1 "register_operand" "r")
2945 (high:DI (match_operand 2 "" ""))))]
2946 "symbolic_operand (operands[2], Pmode)
2947 && ! function_label_operand (operands[2], Pmode)
2951 [(set_attr "type" "binary")
2952 (set_attr "length" "4")])
2954 ;; Always use addil rather than ldil;add sequences. This allows the
2955 ;; HP linker to eliminate the dp relocation if the symbolic operand
2956 ;; lives in the TEXT space.
2958 [(set (match_operand:SI 0 "register_operand" "=a")
2959 (high:SI (match_operand 1 "" "")))]
2960 "symbolic_operand (operands[1], Pmode)
2961 && ! function_label_operand (operands[1], Pmode)
2962 && ! read_only_operand (operands[1], Pmode)
2966 if (TARGET_LONG_LOAD_STORE)
2967 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2969 return \"addil LR'%H1,%%r27\";
2971 [(set_attr "type" "binary")
2972 (set (attr "length")
2973 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2978 ;; This is for use in the prologue/epilogue code. We need it
2979 ;; to add large constants to a stack pointer or frame pointer.
2980 ;; Because of the additional %r1 pressure, we probably do not
2981 ;; want to use this in general code, so make it available
2982 ;; only after reload.
2984 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2985 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2986 (high:SI (match_operand 2 "const_int_operand" ""))))]
2990 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2991 [(set_attr "type" "binary,binary")
2992 (set_attr "length" "4,8")])
2995 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2996 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2997 (high:DI (match_operand 2 "const_int_operand" ""))))]
2998 "reload_completed && TARGET_64BIT"
3001 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
3002 [(set_attr "type" "binary,binary")
3003 (set_attr "length" "4,8")])
3006 [(set (match_operand:SI 0 "register_operand" "=r")
3007 (high:SI (match_operand 1 "" "")))]
3008 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
3009 && !is_function_label_plus_const (operands[1])"
3012 if (symbolic_operand (operands[1], Pmode))
3013 return \"ldil LR'%H1,%0\";
3015 return \"ldil L'%G1,%0\";
3017 [(set_attr "type" "move")
3018 (set_attr "length" "4")])
3021 [(set (match_operand:DI 0 "register_operand" "=r")
3022 (high:DI (match_operand 1 "const_int_operand" "")))]
3025 [(set_attr "type" "move")
3026 (set_attr "length" "4")])
3029 [(set (match_operand:DI 0 "register_operand" "=r")
3030 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
3031 (match_operand:DI 2 "const_int_operand" "i")))]
3034 [(set_attr "type" "move")
3035 (set_attr "length" "4")])
3038 [(set (match_operand:SI 0 "register_operand" "=r")
3039 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
3040 (match_operand:SI 2 "immediate_operand" "i")))]
3041 "!is_function_label_plus_const (operands[2])"
3044 gcc_assert (!flag_pic || !symbolic_operand (operands[2], Pmode));
3046 if (symbolic_operand (operands[2], Pmode))
3047 return \"ldo RR'%G2(%1),%0\";
3049 return \"ldo R'%G2(%1),%0\";
3051 [(set_attr "type" "move")
3052 (set_attr "length" "4")])
3054 ;; Now that a symbolic_address plus a constant is broken up early
3055 ;; in the compilation phase (for better CSE) we need a special
3056 ;; combiner pattern to load the symbolic address plus the constant
3057 ;; in only 2 instructions. (For cases where the symbolic address
3058 ;; was not a common subexpression.)
3060 [(set (match_operand:SI 0 "register_operand" "")
3061 (match_operand:SI 1 "symbolic_operand" ""))
3062 (clobber (match_operand:SI 2 "register_operand" ""))]
3063 "! (flag_pic && pic_label_operand (operands[1], SImode))"
3064 [(set (match_dup 2) (high:SI (match_dup 1)))
3065 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
3068 ;; hppa_legitimize_address goes to a great deal of trouble to
3069 ;; create addresses which use indexing. In some cases, this
3070 ;; is a lose because there isn't any store instructions which
3071 ;; allow indexed addresses (with integer register source).
3073 ;; These define_splits try to turn a 3 insn store into
3074 ;; a 2 insn store with some creative RTL rewriting.
3076 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3077 (match_operand:SI 1 "shadd_operand" ""))
3078 (plus:SI (match_operand:SI 2 "register_operand" "")
3079 (match_operand:SI 3 "const_int_operand" ""))))
3080 (match_operand:SI 4 "register_operand" ""))
3081 (clobber (match_operand:SI 5 "register_operand" ""))]
3083 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3085 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3089 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3090 (match_operand:SI 1 "shadd_operand" ""))
3091 (plus:SI (match_operand:SI 2 "register_operand" "")
3092 (match_operand:SI 3 "const_int_operand" ""))))
3093 (match_operand:HI 4 "register_operand" ""))
3094 (clobber (match_operand:SI 5 "register_operand" ""))]
3096 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3098 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3102 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
3103 (match_operand:SI 1 "shadd_operand" ""))
3104 (plus:SI (match_operand:SI 2 "register_operand" "")
3105 (match_operand:SI 3 "const_int_operand" ""))))
3106 (match_operand:QI 4 "register_operand" ""))
3107 (clobber (match_operand:SI 5 "register_operand" ""))]
3109 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
3111 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
3114 (define_expand "movhi"
3115 [(set (match_operand:HI 0 "general_operand" "")
3116 (match_operand:HI 1 "general_operand" ""))]
3120 if (emit_move_sequence (operands, HImode, 0))
3125 [(set (match_operand:HI 0 "move_dest_operand"
3126 "=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
3127 (match_operand:HI 1 "move_src_operand"
3128 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
3129 "(register_operand (operands[0], HImode)
3130 || reg_or_0_operand (operands[1], HImode))
3131 && !TARGET_SOFT_FLOAT
3137 {zdepi|depwi,z} %Z1,%0
3141 {mfctl|mfctl,w} %sar,%0
3143 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3144 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3145 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3146 (set_attr "pa_combine_type" "addmove")
3147 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3150 [(set (match_operand:HI 0 "move_dest_operand"
3151 "=r,r,r,r,r,Q,!*q,!r,!*f")
3152 (match_operand:HI 1 "move_src_operand"
3153 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3154 "(register_operand (operands[0], HImode)
3155 || reg_or_0_operand (operands[1], HImode))
3156 && !TARGET_SOFT_FLOAT
3162 {zdepi|depwi,z} %Z1,%0
3166 {mfctl|mfctl,w} %sar,%0
3168 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3169 (set_attr "pa_combine_type" "addmove")
3170 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3173 [(set (match_operand:HI 0 "move_dest_operand"
3174 "=r,r,r,r,r,Q,!*q,!r")
3175 (match_operand:HI 1 "move_src_operand"
3176 "r,J,N,K,RQ,rM,!rM,!*q"))]
3177 "(register_operand (operands[0], HImode)
3178 || reg_or_0_operand (operands[1], HImode))
3179 && TARGET_SOFT_FLOAT"
3184 {zdepi|depwi,z} %Z1,%0
3188 {mfctl|mfctl,w} %sar,%0"
3189 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3190 (set_attr "pa_combine_type" "addmove")
3191 (set_attr "length" "4,4,4,4,4,4,4,4")])
3194 [(set (match_operand:HI 0 "register_operand" "=r")
3195 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3196 (match_operand:SI 2 "int5_operand" "L"))))
3198 (plus:SI (match_dup 1) (match_dup 2)))]
3200 "{ldhs|ldh},mb %2(%1),%0"
3201 [(set_attr "type" "load")
3202 (set_attr "length" "4")])
3205 [(set (match_operand:HI 0 "register_operand" "=r")
3206 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3207 (match_operand:DI 2 "int5_operand" "L"))))
3209 (plus:DI (match_dup 1) (match_dup 2)))]
3212 [(set_attr "type" "load")
3213 (set_attr "length" "4")])
3215 ; And a zero extended variant.
3217 [(set (match_operand:DI 0 "register_operand" "=r")
3218 (zero_extend:DI (mem:HI
3220 (match_operand:DI 1 "register_operand" "+r")
3221 (match_operand:DI 2 "int5_operand" "L")))))
3223 (plus:DI (match_dup 1) (match_dup 2)))]
3226 [(set_attr "type" "load")
3227 (set_attr "length" "4")])
3230 [(set (match_operand:SI 0 "register_operand" "=r")
3231 (zero_extend:SI (mem:HI
3233 (match_operand:SI 1 "register_operand" "+r")
3234 (match_operand:SI 2 "int5_operand" "L")))))
3236 (plus:SI (match_dup 1) (match_dup 2)))]
3238 "{ldhs|ldh},mb %2(%1),%0"
3239 [(set_attr "type" "load")
3240 (set_attr "length" "4")])
3243 [(set (match_operand:SI 0 "register_operand" "=r")
3244 (zero_extend:SI (mem:HI
3246 (match_operand:DI 1 "register_operand" "+r")
3247 (match_operand:DI 2 "int5_operand" "L")))))
3249 (plus:DI (match_dup 1) (match_dup 2)))]
3252 [(set_attr "type" "load")
3253 (set_attr "length" "4")])
3256 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3257 (match_operand:SI 1 "int5_operand" "L")))
3258 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3260 (plus:SI (match_dup 0) (match_dup 1)))]
3262 "{sths|sth},mb %r2,%1(%0)"
3263 [(set_attr "type" "store")
3264 (set_attr "length" "4")])
3267 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3268 (match_operand:DI 1 "int5_operand" "L")))
3269 (match_operand:HI 2 "reg_or_0_operand" "rM"))
3271 (plus:DI (match_dup 0) (match_dup 1)))]
3274 [(set_attr "type" "store")
3275 (set_attr "length" "4")])
3278 [(set (match_operand:HI 0 "register_operand" "=r")
3279 (plus:HI (match_operand:HI 1 "register_operand" "r")
3280 (match_operand 2 "const_int_operand" "J")))]
3283 [(set_attr "type" "binary")
3284 (set_attr "pa_combine_type" "addmove")
3285 (set_attr "length" "4")])
3287 (define_expand "movqi"
3288 [(set (match_operand:QI 0 "general_operand" "")
3289 (match_operand:QI 1 "general_operand" ""))]
3293 if (emit_move_sequence (operands, QImode, 0))
3298 [(set (match_operand:QI 0 "move_dest_operand"
3299 "=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
3300 (match_operand:QI 1 "move_src_operand"
3301 "r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
3302 "(register_operand (operands[0], QImode)
3303 || reg_or_0_operand (operands[1], QImode))
3304 && !TARGET_SOFT_FLOAT
3310 {zdepi|depwi,z} %Z1,%0
3314 {mfctl|mfctl,w} %%sar,%0
3316 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
3317 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
3318 [(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
3319 (set_attr "pa_combine_type" "addmove")
3320 (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
3323 [(set (match_operand:QI 0 "move_dest_operand"
3324 "=r,r,r,r,r,Q,!*q,!r,!*f")
3325 (match_operand:QI 1 "move_src_operand"
3326 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
3327 "(register_operand (operands[0], QImode)
3328 || reg_or_0_operand (operands[1], QImode))
3329 && !TARGET_SOFT_FLOAT
3335 {zdepi|depwi,z} %Z1,%0
3339 {mfctl|mfctl,w} %%sar,%0
3341 [(set_attr "type" "move,move,move,shift,load,store,move,move,move")
3342 (set_attr "pa_combine_type" "addmove")
3343 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3346 [(set (match_operand:QI 0 "move_dest_operand"
3347 "=r,r,r,r,r,Q,!*q,!r")
3348 (match_operand:QI 1 "move_src_operand"
3349 "r,J,N,K,RQ,rM,!rM,!*q"))]
3350 "(register_operand (operands[0], QImode)
3351 || reg_or_0_operand (operands[1], QImode))
3352 && TARGET_SOFT_FLOAT"
3357 {zdepi|depwi,z} %Z1,%0
3361 {mfctl|mfctl,w} %%sar,%0"
3362 [(set_attr "type" "move,move,move,shift,load,store,move,move")
3363 (set_attr "pa_combine_type" "addmove")
3364 (set_attr "length" "4,4,4,4,4,4,4,4")])
3367 [(set (match_operand:QI 0 "register_operand" "=r")
3368 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3369 (match_operand:SI 2 "int5_operand" "L"))))
3370 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3372 "{ldbs|ldb},mb %2(%1),%0"
3373 [(set_attr "type" "load")
3374 (set_attr "length" "4")])
3377 [(set (match_operand:QI 0 "register_operand" "=r")
3378 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3379 (match_operand:DI 2 "int5_operand" "L"))))
3380 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3383 [(set_attr "type" "load")
3384 (set_attr "length" "4")])
3386 ; Now the same thing with zero extensions.
3388 [(set (match_operand:DI 0 "register_operand" "=r")
3389 (zero_extend:DI (mem:QI (plus:DI
3390 (match_operand:DI 1 "register_operand" "+r")
3391 (match_operand:DI 2 "int5_operand" "L")))))
3392 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3395 [(set_attr "type" "load")
3396 (set_attr "length" "4")])
3399 [(set (match_operand:SI 0 "register_operand" "=r")
3400 (zero_extend:SI (mem:QI (plus:SI
3401 (match_operand:SI 1 "register_operand" "+r")
3402 (match_operand:SI 2 "int5_operand" "L")))))
3403 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3405 "{ldbs|ldb},mb %2(%1),%0"
3406 [(set_attr "type" "load")
3407 (set_attr "length" "4")])
3410 [(set (match_operand:SI 0 "register_operand" "=r")
3411 (zero_extend:SI (mem:QI (plus:DI
3412 (match_operand:DI 1 "register_operand" "+r")
3413 (match_operand:DI 2 "int5_operand" "L")))))
3414 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3417 [(set_attr "type" "load")
3418 (set_attr "length" "4")])
3421 [(set (match_operand:HI 0 "register_operand" "=r")
3422 (zero_extend:HI (mem:QI (plus:SI
3423 (match_operand:SI 1 "register_operand" "+r")
3424 (match_operand:SI 2 "int5_operand" "L")))))
3425 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3427 "{ldbs|ldb},mb %2(%1),%0"
3428 [(set_attr "type" "load")
3429 (set_attr "length" "4")])
3432 [(set (match_operand:HI 0 "register_operand" "=r")
3433 (zero_extend:HI (mem:QI (plus:DI
3434 (match_operand:DI 1 "register_operand" "+r")
3435 (match_operand:DI 2 "int5_operand" "L")))))
3436 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3439 [(set_attr "type" "load")
3440 (set_attr "length" "4")])
3443 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3444 (match_operand:SI 1 "int5_operand" "L")))
3445 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3447 (plus:SI (match_dup 0) (match_dup 1)))]
3449 "{stbs|stb},mb %r2,%1(%0)"
3450 [(set_attr "type" "store")
3451 (set_attr "length" "4")])
3454 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3455 (match_operand:DI 1 "int5_operand" "L")))
3456 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3458 (plus:DI (match_dup 0) (match_dup 1)))]
3461 [(set_attr "type" "store")
3462 (set_attr "length" "4")])
3464 ;; The definition of this insn does not really explain what it does,
3465 ;; but it should suffice that anything generated as this insn will be
3466 ;; recognized as a movmemsi operation, and that it will not successfully
3467 ;; combine with anything.
3468 (define_expand "movmemsi"
3469 [(parallel [(set (match_operand:BLK 0 "" "")
3470 (match_operand:BLK 1 "" ""))
3471 (clobber (match_dup 4))
3472 (clobber (match_dup 5))
3473 (clobber (match_dup 6))
3474 (clobber (match_dup 7))
3475 (clobber (match_dup 8))
3476 (use (match_operand:SI 2 "arith_operand" ""))
3477 (use (match_operand:SI 3 "const_int_operand" ""))])]
3478 "!TARGET_64BIT && optimize > 0"
3483 /* HP provides very fast block move library routine for the PA;
3484 this routine includes:
3486 4x4 byte at a time block moves,
3487 1x4 byte at a time with alignment checked at runtime with
3488 attempts to align the source and destination as needed
3491 With that in mind, here's the heuristics to try and guess when
3492 the inlined block move will be better than the library block
3495 If the size isn't constant, then always use the library routines.
3497 If the size is large in respect to the known alignment, then use
3498 the library routines.
3500 If the size is small in respect to the known alignment, then open
3501 code the copy (since that will lead to better scheduling).
3503 Else use the block move pattern. */
3505 /* Undetermined size, use the library routine. */
3506 if (GET_CODE (operands[2]) != CONST_INT)
3509 size = INTVAL (operands[2]);
3510 align = INTVAL (operands[3]);
3511 align = align > 4 ? 4 : align;
3513 /* If size/alignment is large, then use the library routines. */
3514 if (size / align > 16)
3517 /* This does happen, but not often enough to worry much about. */
3518 if (size / align < MOVE_RATIO)
3521 /* Fall through means we're going to use our block move pattern. */
3523 = replace_equiv_address (operands[0],
3524 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3526 = replace_equiv_address (operands[1],
3527 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3528 operands[4] = gen_reg_rtx (SImode);
3529 operands[5] = gen_reg_rtx (SImode);
3530 operands[6] = gen_reg_rtx (SImode);
3531 operands[7] = gen_reg_rtx (SImode);
3532 operands[8] = gen_reg_rtx (SImode);
3535 ;; The operand constraints are written like this to support both compile-time
3536 ;; and run-time determined byte counts. The expander and output_block_move
3537 ;; only support compile-time determined counts at this time.
3539 ;; If the count is run-time determined, the register with the byte count
3540 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3542 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3543 ;; broke this semantic for pseudo registers. We can't use match_scratch
3544 ;; as this requires two registers in the class R1_REGS when the MEMs for
3545 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3546 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3547 ;; respectively. We then split or peephole optimize after reload.
3548 (define_insn "movmemsi_prereload"
3549 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3550 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3551 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3552 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3553 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3554 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3555 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3556 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3557 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3560 [(set_attr "type" "multi,multi")])
3563 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3564 (match_operand:BLK 1 "memory_operand" ""))
3565 (clobber (match_operand:SI 2 "register_operand" ""))
3566 (clobber (match_operand:SI 3 "register_operand" ""))
3567 (clobber (match_operand:SI 6 "register_operand" ""))
3568 (clobber (match_operand:SI 7 "register_operand" ""))
3569 (clobber (match_operand:SI 8 "register_operand" ""))
3570 (use (match_operand:SI 4 "arith_operand" ""))
3571 (use (match_operand:SI 5 "const_int_operand" ""))])]
3572 "!TARGET_64BIT && reload_completed && !flag_peephole2
3573 && GET_CODE (operands[0]) == MEM
3574 && register_operand (XEXP (operands[0], 0), SImode)
3575 && GET_CODE (operands[1]) == MEM
3576 && register_operand (XEXP (operands[1], 0), SImode)"
3577 [(set (match_dup 7) (match_dup 9))
3578 (set (match_dup 8) (match_dup 10))
3579 (parallel [(set (match_dup 0) (match_dup 1))
3580 (clobber (match_dup 2))
3581 (clobber (match_dup 3))
3582 (clobber (match_dup 6))
3583 (clobber (match_dup 7))
3584 (clobber (match_dup 8))
3590 operands[9] = XEXP (operands[0], 0);
3591 operands[10] = XEXP (operands[1], 0);
3592 operands[0] = replace_equiv_address (operands[0], operands[7]);
3593 operands[1] = replace_equiv_address (operands[1], operands[8]);
3597 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3598 (match_operand:BLK 1 "memory_operand" ""))
3599 (clobber (match_operand:SI 2 "register_operand" ""))
3600 (clobber (match_operand:SI 3 "register_operand" ""))
3601 (clobber (match_operand:SI 6 "register_operand" ""))
3602 (clobber (match_operand:SI 7 "register_operand" ""))
3603 (clobber (match_operand:SI 8 "register_operand" ""))
3604 (use (match_operand:SI 4 "arith_operand" ""))
3605 (use (match_operand:SI 5 "const_int_operand" ""))])]
3607 && GET_CODE (operands[0]) == MEM
3608 && register_operand (XEXP (operands[0], 0), SImode)
3609 && GET_CODE (operands[1]) == MEM
3610 && register_operand (XEXP (operands[1], 0), SImode)"
3611 [(parallel [(set (match_dup 0) (match_dup 1))
3612 (clobber (match_dup 2))
3613 (clobber (match_dup 3))
3614 (clobber (match_dup 6))
3615 (clobber (match_dup 7))
3616 (clobber (match_dup 8))
3622 rtx addr = XEXP (operands[0], 0);
3623 if (dead_or_set_p (curr_insn, addr))
3627 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3628 operands[0] = replace_equiv_address (operands[0], operands[7]);
3631 addr = XEXP (operands[1], 0);
3632 if (dead_or_set_p (curr_insn, addr))
3636 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3637 operands[1] = replace_equiv_address (operands[1], operands[8]);
3641 (define_insn "movmemsi_postreload"
3642 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3643 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3644 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3645 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3646 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3647 (clobber (match_dup 0))
3648 (clobber (match_dup 1))
3649 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3650 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3652 "!TARGET_64BIT && reload_completed"
3653 "* return output_block_move (operands, !which_alternative);"
3654 [(set_attr "type" "multi,multi")])
3656 (define_expand "movmemdi"
3657 [(parallel [(set (match_operand:BLK 0 "" "")
3658 (match_operand:BLK 1 "" ""))
3659 (clobber (match_dup 4))
3660 (clobber (match_dup 5))
3661 (clobber (match_dup 6))
3662 (clobber (match_dup 7))
3663 (clobber (match_dup 8))
3664 (use (match_operand:DI 2 "arith_operand" ""))
3665 (use (match_operand:DI 3 "const_int_operand" ""))])]
3666 "TARGET_64BIT && optimize > 0"
3671 /* HP provides very fast block move library routine for the PA;
3672 this routine includes:
3674 4x4 byte at a time block moves,
3675 1x4 byte at a time with alignment checked at runtime with
3676 attempts to align the source and destination as needed
3679 With that in mind, here's the heuristics to try and guess when
3680 the inlined block move will be better than the library block
3683 If the size isn't constant, then always use the library routines.
3685 If the size is large in respect to the known alignment, then use
3686 the library routines.
3688 If the size is small in respect to the known alignment, then open
3689 code the copy (since that will lead to better scheduling).
3691 Else use the block move pattern. */
3693 /* Undetermined size, use the library routine. */
3694 if (GET_CODE (operands[2]) != CONST_INT)
3697 size = INTVAL (operands[2]);
3698 align = INTVAL (operands[3]);
3699 align = align > 8 ? 8 : align;
3701 /* If size/alignment is large, then use the library routines. */
3702 if (size / align > 16)
3705 /* This does happen, but not often enough to worry much about. */
3706 if (size / align < MOVE_RATIO)
3709 /* Fall through means we're going to use our block move pattern. */
3711 = replace_equiv_address (operands[0],
3712 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3714 = replace_equiv_address (operands[1],
3715 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3716 operands[4] = gen_reg_rtx (DImode);
3717 operands[5] = gen_reg_rtx (DImode);
3718 operands[6] = gen_reg_rtx (DImode);
3719 operands[7] = gen_reg_rtx (DImode);
3720 operands[8] = gen_reg_rtx (DImode);
3723 ;; The operand constraints are written like this to support both compile-time
3724 ;; and run-time determined byte counts. The expander and output_block_move
3725 ;; only support compile-time determined counts at this time.
3727 ;; If the count is run-time determined, the register with the byte count
3728 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3730 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3731 ;; broke this semantic for pseudo registers. We can't use match_scratch
3732 ;; as this requires two registers in the class R1_REGS when the MEMs for
3733 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3734 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3735 ;; respectively. We then split or peephole optimize after reload.
3736 (define_insn "movmemdi_prereload"
3737 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3738 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3739 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3740 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3741 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3742 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3743 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3744 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3745 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3748 [(set_attr "type" "multi,multi")])
3751 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3752 (match_operand:BLK 1 "memory_operand" ""))
3753 (clobber (match_operand:DI 2 "register_operand" ""))
3754 (clobber (match_operand:DI 3 "register_operand" ""))
3755 (clobber (match_operand:DI 6 "register_operand" ""))
3756 (clobber (match_operand:DI 7 "register_operand" ""))
3757 (clobber (match_operand:DI 8 "register_operand" ""))
3758 (use (match_operand:DI 4 "arith_operand" ""))
3759 (use (match_operand:DI 5 "const_int_operand" ""))])]
3760 "TARGET_64BIT && reload_completed && !flag_peephole2
3761 && GET_CODE (operands[0]) == MEM
3762 && register_operand (XEXP (operands[0], 0), DImode)
3763 && GET_CODE (operands[1]) == MEM
3764 && register_operand (XEXP (operands[1], 0), DImode)"
3765 [(set (match_dup 7) (match_dup 9))
3766 (set (match_dup 8) (match_dup 10))
3767 (parallel [(set (match_dup 0) (match_dup 1))
3768 (clobber (match_dup 2))
3769 (clobber (match_dup 3))
3770 (clobber (match_dup 6))
3771 (clobber (match_dup 7))
3772 (clobber (match_dup 8))
3778 operands[9] = XEXP (operands[0], 0);
3779 operands[10] = XEXP (operands[1], 0);
3780 operands[0] = replace_equiv_address (operands[0], operands[7]);
3781 operands[1] = replace_equiv_address (operands[1], operands[8]);
3785 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3786 (match_operand:BLK 1 "memory_operand" ""))
3787 (clobber (match_operand:DI 2 "register_operand" ""))
3788 (clobber (match_operand:DI 3 "register_operand" ""))
3789 (clobber (match_operand:DI 6 "register_operand" ""))
3790 (clobber (match_operand:DI 7 "register_operand" ""))
3791 (clobber (match_operand:DI 8 "register_operand" ""))
3792 (use (match_operand:DI 4 "arith_operand" ""))
3793 (use (match_operand:DI 5 "const_int_operand" ""))])]
3795 && GET_CODE (operands[0]) == MEM
3796 && register_operand (XEXP (operands[0], 0), DImode)
3797 && GET_CODE (operands[1]) == MEM
3798 && register_operand (XEXP (operands[1], 0), DImode)"
3799 [(parallel [(set (match_dup 0) (match_dup 1))
3800 (clobber (match_dup 2))
3801 (clobber (match_dup 3))
3802 (clobber (match_dup 6))
3803 (clobber (match_dup 7))
3804 (clobber (match_dup 8))
3810 rtx addr = XEXP (operands[0], 0);
3811 if (dead_or_set_p (curr_insn, addr))
3815 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3816 operands[0] = replace_equiv_address (operands[0], operands[7]);
3819 addr = XEXP (operands[1], 0);
3820 if (dead_or_set_p (curr_insn, addr))
3824 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3825 operands[1] = replace_equiv_address (operands[1], operands[8]);
3829 (define_insn "movmemdi_postreload"
3830 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3831 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3832 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3833 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3834 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3835 (clobber (match_dup 0))
3836 (clobber (match_dup 1))
3837 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3838 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3840 "TARGET_64BIT && reload_completed"
3841 "* return output_block_move (operands, !which_alternative);"
3842 [(set_attr "type" "multi,multi")])
3844 (define_expand "setmemsi"
3845 [(parallel [(set (match_operand:BLK 0 "" "")
3846 (match_operand 2 "const_int_operand" ""))
3847 (clobber (match_dup 4))
3848 (clobber (match_dup 5))
3849 (use (match_operand:SI 1 "arith_operand" ""))
3850 (use (match_operand:SI 3 "const_int_operand" ""))])]
3851 "!TARGET_64BIT && optimize > 0"
3856 /* If value to set is not zero, use the library routine. */
3857 if (operands[2] != const0_rtx)
3860 /* Undetermined size, use the library routine. */
3861 if (GET_CODE (operands[1]) != CONST_INT)
3864 size = INTVAL (operands[1]);
3865 align = INTVAL (operands[3]);
3866 align = align > 4 ? 4 : align;
3868 /* If size/alignment is large, then use the library routines. */
3869 if (size / align > 16)
3872 /* This does happen, but not often enough to worry much about. */
3873 if (size / align < MOVE_RATIO)
3876 /* Fall through means we're going to use our block clear pattern. */
3878 = replace_equiv_address (operands[0],
3879 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3880 operands[4] = gen_reg_rtx (SImode);
3881 operands[5] = gen_reg_rtx (SImode);
3884 (define_insn "clrmemsi_prereload"
3885 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3887 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3888 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3889 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3890 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3893 [(set_attr "type" "multi,multi")])
3896 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3898 (clobber (match_operand:SI 1 "register_operand" ""))
3899 (clobber (match_operand:SI 4 "register_operand" ""))
3900 (use (match_operand:SI 2 "arith_operand" ""))
3901 (use (match_operand:SI 3 "const_int_operand" ""))])]
3902 "!TARGET_64BIT && reload_completed && !flag_peephole2
3903 && GET_CODE (operands[0]) == MEM
3904 && register_operand (XEXP (operands[0], 0), SImode)"
3905 [(set (match_dup 4) (match_dup 5))
3906 (parallel [(set (match_dup 0) (const_int 0))
3907 (clobber (match_dup 1))
3908 (clobber (match_dup 4))
3914 operands[5] = XEXP (operands[0], 0);
3915 operands[0] = replace_equiv_address (operands[0], operands[4]);
3919 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3921 (clobber (match_operand:SI 1 "register_operand" ""))
3922 (clobber (match_operand:SI 4 "register_operand" ""))
3923 (use (match_operand:SI 2 "arith_operand" ""))
3924 (use (match_operand:SI 3 "const_int_operand" ""))])]
3926 && GET_CODE (operands[0]) == MEM
3927 && register_operand (XEXP (operands[0], 0), SImode)"
3928 [(parallel [(set (match_dup 0) (const_int 0))
3929 (clobber (match_dup 1))
3930 (clobber (match_dup 4))
3936 rtx addr = XEXP (operands[0], 0);
3937 if (dead_or_set_p (curr_insn, addr))
3941 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3942 operands[0] = replace_equiv_address (operands[0], operands[4]);
3946 (define_insn "clrmemsi_postreload"
3947 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3949 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3950 (clobber (match_dup 0))
3951 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3952 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3954 "!TARGET_64BIT && reload_completed"
3955 "* return output_block_clear (operands, !which_alternative);"
3956 [(set_attr "type" "multi,multi")])
3958 (define_expand "setmemdi"
3959 [(parallel [(set (match_operand:BLK 0 "" "")
3960 (match_operand 2 "const_int_operand" ""))
3961 (clobber (match_dup 4))
3962 (clobber (match_dup 5))
3963 (use (match_operand:DI 1 "arith_operand" ""))
3964 (use (match_operand:DI 3 "const_int_operand" ""))])]
3965 "TARGET_64BIT && optimize > 0"
3970 /* If value to set is not zero, use the library routine. */
3971 if (operands[2] != const0_rtx)
3974 /* Undetermined size, use the library routine. */
3975 if (GET_CODE (operands[1]) != CONST_INT)
3978 size = INTVAL (operands[1]);
3979 align = INTVAL (operands[3]);
3980 align = align > 8 ? 8 : align;
3982 /* If size/alignment is large, then use the library routines. */
3983 if (size / align > 16)
3986 /* This does happen, but not often enough to worry much about. */
3987 if (size / align < MOVE_RATIO)
3990 /* Fall through means we're going to use our block clear pattern. */
3992 = replace_equiv_address (operands[0],
3993 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3994 operands[4] = gen_reg_rtx (DImode);
3995 operands[5] = gen_reg_rtx (DImode);
3998 (define_insn "clrmemdi_prereload"
3999 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
4001 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4002 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
4003 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4004 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
4007 [(set_attr "type" "multi,multi")])
4010 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4012 (clobber (match_operand:DI 1 "register_operand" ""))
4013 (clobber (match_operand:DI 4 "register_operand" ""))
4014 (use (match_operand:DI 2 "arith_operand" ""))
4015 (use (match_operand:DI 3 "const_int_operand" ""))])]
4016 "TARGET_64BIT && reload_completed && !flag_peephole2
4017 && GET_CODE (operands[0]) == MEM
4018 && register_operand (XEXP (operands[0], 0), DImode)"
4019 [(set (match_dup 4) (match_dup 5))
4020 (parallel [(set (match_dup 0) (const_int 0))
4021 (clobber (match_dup 1))
4022 (clobber (match_dup 4))
4028 operands[5] = XEXP (operands[0], 0);
4029 operands[0] = replace_equiv_address (operands[0], operands[4]);
4033 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
4035 (clobber (match_operand:DI 1 "register_operand" ""))
4036 (clobber (match_operand:DI 4 "register_operand" ""))
4037 (use (match_operand:DI 2 "arith_operand" ""))
4038 (use (match_operand:DI 3 "const_int_operand" ""))])]
4040 && GET_CODE (operands[0]) == MEM
4041 && register_operand (XEXP (operands[0], 0), DImode)"
4042 [(parallel [(set (match_dup 0) (const_int 0))
4043 (clobber (match_dup 1))
4044 (clobber (match_dup 4))
4050 rtx addr = XEXP (operands[0], 0);
4051 if (dead_or_set_p (curr_insn, addr))
4055 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
4056 operands[0] = replace_equiv_address (operands[0], operands[4]);
4060 (define_insn "clrmemdi_postreload"
4061 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
4063 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
4064 (clobber (match_dup 0))
4065 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
4066 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
4068 "TARGET_64BIT && reload_completed"
4069 "* return output_block_clear (operands, !which_alternative);"
4070 [(set_attr "type" "multi,multi")])
4072 ;; Floating point move insns
4074 ;; This pattern forces (set (reg:DF ...) (const_double ...))
4075 ;; to be reloaded by putting the constant into memory when
4076 ;; reg is a floating point register.
4078 ;; For integer registers we use ldil;ldo to set the appropriate
4081 ;; This must come before the movdf pattern, and it must be present
4082 ;; to handle obscure reloading cases.
4084 [(set (match_operand:DF 0 "register_operand" "=?r,f")
4085 (match_operand:DF 1 "" "?F,m"))]
4086 "GET_CODE (operands[1]) == CONST_DOUBLE
4087 && operands[1] != CONST0_RTX (DFmode)
4089 && !TARGET_SOFT_FLOAT"
4090 "* return (which_alternative == 0 ? output_move_double (operands)
4091 : \"fldd%F1 %1,%0\");"
4092 [(set_attr "type" "move,fpload")
4093 (set_attr "length" "16,4")])
4095 (define_expand "movdf"
4096 [(set (match_operand:DF 0 "general_operand" "")
4097 (match_operand:DF 1 "general_operand" ""))]
4102 && GET_CODE (operands[1]) == CONST_DOUBLE
4103 && operands[1] != CONST0_RTX (DFmode))
4105 /* We rely on reload to legitimize the insn generated after
4106 we force the CONST_DOUBLE to memory. This doesn't happen
4107 if OPERANDS[0] is a hard register. */
4108 if (REG_P (operands[0]) && HARD_REGISTER_P (operands[0]))
4111 operands[1] = force_const_mem (DFmode, operands[1]);
4114 if (emit_move_sequence (operands, DFmode, 0))
4118 ;; Handle DFmode input reloads requiring a general register as a
4119 ;; scratch register.
4120 (define_expand "reload_indf"
4121 [(set (match_operand:DF 0 "register_operand" "=Z")
4122 (match_operand:DF 1 "non_hard_reg_operand" ""))
4123 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4127 if (emit_move_sequence (operands, DFmode, operands[2]))
4130 /* We don't want the clobber emitted, so handle this ourselves. */
4131 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4135 ;; Handle DFmode output reloads requiring a general register as a
4136 ;; scratch register.
4137 (define_expand "reload_outdf"
4138 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
4139 (match_operand:DF 1 "register_operand" "Z"))
4140 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
4144 if (emit_move_sequence (operands, DFmode, operands[2]))
4147 /* We don't want the clobber emitted, so handle this ourselves. */
4148 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4153 [(set (match_operand:DF 0 "move_dest_operand"
4154 "=f,*r,Q,?o,?Q,f,*r,*r,!r,!f")
4155 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4156 "fG,*rG,f,*r,*r,RQ,o,RQ,!f,!r"))]
4157 "(register_operand (operands[0], DFmode)
4158 || reg_or_0_operand (operands[1], DFmode))
4159 && !(GET_CODE (operands[1]) == CONST_DOUBLE
4160 && GET_CODE (operands[0]) == MEM)
4162 && !TARGET_SOFT_FLOAT"
4165 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4166 || operands[1] == CONST0_RTX (DFmode))
4167 && !(REG_P (operands[0]) && REG_P (operands[1])
4168 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4169 return output_fp_move_double (operands);
4170 return output_move_double (operands);
4172 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load,move,move")
4173 (set_attr "length" "4,8,4,8,16,4,8,16,12,12")])
4176 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
4177 (match_operand:DF 1 "reg_or_0_operand" "f"))]
4179 && !TARGET_DISABLE_INDEXING
4180 && reload_completed"
4182 [(set_attr "type" "fpstore")
4183 (set_attr "pa_combine_type" "addmove")
4184 (set_attr "length" "4")])
4187 [(set (match_operand:SI 0 "register_operand" "")
4188 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4190 (match_operand:SI 2 "register_operand" "")))
4191 (set (mem:DF (match_dup 0))
4192 (match_operand:DF 3 "register_operand" ""))]
4194 && !TARGET_DISABLE_INDEXING
4195 && REG_OK_FOR_BASE_P (operands[2])
4196 && FP_REGNO_P (REGNO (operands[3]))"
4197 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4199 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4204 [(set (match_operand:SI 0 "register_operand" "")
4205 (plus:SI (match_operand:SI 2 "register_operand" "")
4206 (mult:SI (match_operand:SI 1 "register_operand" "")
4208 (set (mem:DF (match_dup 0))
4209 (match_operand:DF 3 "register_operand" ""))]
4211 && !TARGET_DISABLE_INDEXING
4212 && REG_OK_FOR_BASE_P (operands[2])
4213 && FP_REGNO_P (REGNO (operands[3]))"
4214 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
4216 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
4221 [(set (match_operand:DI 0 "register_operand" "")
4222 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4224 (match_operand:DI 2 "register_operand" "")))
4225 (set (mem:DF (match_dup 0))
4226 (match_operand:DF 3 "register_operand" ""))]
4228 && !TARGET_DISABLE_INDEXING
4230 && REG_OK_FOR_BASE_P (operands[2])
4231 && FP_REGNO_P (REGNO (operands[3]))"
4232 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4234 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4239 [(set (match_operand:DI 0 "register_operand" "")
4240 (plus:DI (match_operand:DI 2 "register_operand" "")
4241 (mult:DI (match_operand:DI 1 "register_operand" "")
4243 (set (mem:DF (match_dup 0))
4244 (match_operand:DF 3 "register_operand" ""))]
4246 && !TARGET_DISABLE_INDEXING
4248 && REG_OK_FOR_BASE_P (operands[2])
4249 && FP_REGNO_P (REGNO (operands[3]))"
4250 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4252 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4257 [(set (match_operand:SI 0 "register_operand" "")
4258 (plus:SI (match_operand:SI 1 "register_operand" "")
4259 (match_operand:SI 2 "register_operand" "")))
4260 (set (mem:DF (match_dup 0))
4261 (match_operand:DF 3 "register_operand" ""))]
4263 && !TARGET_DISABLE_INDEXING
4264 && TARGET_NO_SPACE_REGS
4265 && REG_OK_FOR_INDEX_P (operands[1])
4266 && REG_OK_FOR_BASE_P (operands[2])
4267 && FP_REGNO_P (REGNO (operands[3]))"
4268 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
4270 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4274 [(set (match_operand:SI 0 "register_operand" "")
4275 (plus:SI (match_operand:SI 1 "register_operand" "")
4276 (match_operand:SI 2 "register_operand" "")))
4277 (set (mem:DF (match_dup 0))
4278 (match_operand:DF 3 "register_operand" ""))]
4280 && !TARGET_DISABLE_INDEXING
4281 && TARGET_NO_SPACE_REGS
4282 && REG_OK_FOR_BASE_P (operands[1])
4283 && REG_OK_FOR_INDEX_P (operands[2])
4284 && FP_REGNO_P (REGNO (operands[3]))"
4285 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
4287 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4291 [(set (match_operand:DI 0 "register_operand" "")
4292 (plus:DI (match_operand:DI 1 "register_operand" "")
4293 (match_operand:DI 2 "register_operand" "")))
4294 (set (mem:DF (match_dup 0))
4295 (match_operand:DF 3 "register_operand" ""))]
4297 && !TARGET_DISABLE_INDEXING
4299 && TARGET_NO_SPACE_REGS
4300 && REG_OK_FOR_INDEX_P (operands[1])
4301 && REG_OK_FOR_BASE_P (operands[2])
4302 && FP_REGNO_P (REGNO (operands[3]))"
4303 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
4305 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4309 [(set (match_operand:DI 0 "register_operand" "")
4310 (plus:DI (match_operand:DI 1 "register_operand" "")
4311 (match_operand:DI 2 "register_operand" "")))
4312 (set (mem:DF (match_dup 0))
4313 (match_operand:DF 3 "register_operand" ""))]
4315 && !TARGET_DISABLE_INDEXING
4317 && TARGET_NO_SPACE_REGS
4318 && REG_OK_FOR_BASE_P (operands[1])
4319 && REG_OK_FOR_INDEX_P (operands[2])
4320 && FP_REGNO_P (REGNO (operands[3]))"
4321 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
4323 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4327 [(set (match_operand:DF 0 "move_dest_operand"
4328 "=r,?o,?Q,r,r,!r,!f")
4329 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
4330 "rG,r,r,o,RQ,!f,!r"))]
4331 "(register_operand (operands[0], DFmode)
4332 || reg_or_0_operand (operands[1], DFmode))
4334 && TARGET_SOFT_FLOAT"
4337 return output_move_double (operands);
4339 [(set_attr "type" "move,store,store,load,load,move,move")
4340 (set_attr "length" "8,8,16,8,16,12,12")])
4343 [(set (match_operand:DF 0 "move_dest_operand"
4344 "=!*r,*r,*r,*r,*r,Q,f,f,T")
4345 (match_operand:DF 1 "move_src_operand"
4346 "!*r,J,N,K,RQ,*rM,fM,RT,f"))]
4347 "(register_operand (operands[0], DFmode)
4348 || reg_or_0_operand (operands[1], DFmode))
4349 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4360 [(set_attr "type" "move,move,move,shift,load,store,fpalu,fpload,fpstore")
4361 (set_attr "pa_combine_type" "addmove")
4362 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
4365 (define_expand "movdi"
4366 [(set (match_operand:DI 0 "general_operand" "")
4367 (match_operand:DI 1 "general_operand" ""))]
4371 /* Except for zero, we don't support loading a CONST_INT directly
4372 to a hard floating-point register since a scratch register is
4373 needed for the operation. While the operation could be handled
4374 before no_new_pseudos is true, the simplest solution is to fail. */
4376 && GET_CODE (operands[1]) == CONST_INT
4377 && operands[1] != CONST0_RTX (DImode)
4378 && REG_P (operands[0])
4379 && HARD_REGISTER_P (operands[0])
4380 && REGNO (operands[0]) >= 32)
4383 if (emit_move_sequence (operands, DImode, 0))
4387 ;; Handle DImode input reloads requiring %r1 as a scratch register.
4388 (define_expand "reload_indi_r1"
4389 [(set (match_operand:DI 0 "register_operand" "=Z")
4390 (match_operand:DI 1 "non_hard_reg_operand" ""))
4391 (clobber (match_operand:SI 2 "register_operand" "=&a"))]
4395 if (emit_move_sequence (operands, DImode, operands[2]))
4398 /* We don't want the clobber emitted, so handle this ourselves. */
4399 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4403 ;; Handle DImode input reloads requiring a general register as a
4404 ;; scratch register.
4405 (define_expand "reload_indi"
4406 [(set (match_operand:DI 0 "register_operand" "=Z")
4407 (match_operand:DI 1 "non_hard_reg_operand" ""))
4408 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4412 if (emit_move_sequence (operands, DImode, operands[2]))
4415 /* We don't want the clobber emitted, so handle this ourselves. */
4416 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4420 ;; Handle DImode output reloads requiring a general register as a
4421 ;; scratch register.
4422 (define_expand "reload_outdi"
4423 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4424 (match_operand:DI 1 "register_operand" "Z"))
4425 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4429 if (emit_move_sequence (operands, DImode, operands[2]))
4432 /* We don't want the clobber emitted, so handle this ourselves. */
4433 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4438 [(set (match_operand:DI 0 "register_operand" "=r")
4439 (high:DI (match_operand 1 "" "")))]
4443 rtx op0 = operands[0];
4444 rtx op1 = operands[1];
4446 switch (GET_CODE (op1))
4449 #if HOST_BITS_PER_WIDE_INT <= 32
4450 operands[0] = operand_subword (op0, 1, 0, DImode);
4451 output_asm_insn (\"ldil L'%1,%0\", operands);
4453 operands[0] = operand_subword (op0, 0, 0, DImode);
4454 if (INTVAL (op1) < 0)
4455 output_asm_insn (\"ldi -1,%0\", operands);
4457 output_asm_insn (\"ldi 0,%0\", operands);
4459 operands[0] = operand_subword (op0, 1, 0, DImode);
4460 operands[1] = GEN_INT (INTVAL (op1) & 0xffffffff);
4461 output_asm_insn (\"ldil L'%1,%0\", operands);
4463 operands[0] = operand_subword (op0, 0, 0, DImode);
4464 operands[1] = GEN_INT (INTVAL (op1) >> 32);
4465 output_asm_insn (singlemove_string (operands), operands);
4470 operands[0] = operand_subword (op0, 1, 0, DImode);
4471 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4472 output_asm_insn (\"ldil L'%1,%0\", operands);
4474 operands[0] = operand_subword (op0, 0, 0, DImode);
4475 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4476 output_asm_insn (singlemove_string (operands), operands);
4484 [(set_attr "type" "move")
4485 (set_attr "length" "12")])
4488 [(set (match_operand:DI 0 "move_dest_operand"
4489 "=r,o,Q,r,r,r,*f,*f,T,!r,!f")
4490 (match_operand:DI 1 "general_operand"
4491 "rM,r,r,o*R,Q,i,*fM,RT,*f,!f,!r"))]
4492 "(register_operand (operands[0], DImode)
4493 || reg_or_0_operand (operands[1], DImode))
4495 && !TARGET_SOFT_FLOAT"
4498 if ((FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4499 || operands[1] == CONST0_RTX (DFmode))
4500 && !(REG_P (operands[0]) && REG_P (operands[1])
4501 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1])))
4502 return output_fp_move_double (operands);
4503 return output_move_double (operands);
4506 "move,store,store,load,load,multi,fpalu,fpload,fpstore,move,move")
4507 (set_attr "length" "8,8,16,8,16,16,4,4,4,12,12")])
4510 [(set (match_operand:DI 0 "move_dest_operand"
4511 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4512 (match_operand:DI 1 "move_src_operand"
4513 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4514 "(register_operand (operands[0], DImode)
4515 || reg_or_0_operand (operands[1], DImode))
4516 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4526 {mfctl|mfctl,w} %%sar,%0
4530 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4531 (set_attr "pa_combine_type" "addmove")
4532 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4535 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4536 (match_operand:DI 1 "register_operand" "f"))]
4539 && !TARGET_DISABLE_INDEXING
4540 && reload_completed"
4542 [(set_attr "type" "fpstore")
4543 (set_attr "pa_combine_type" "addmove")
4544 (set_attr "length" "4")])
4547 [(set (match_operand:DI 0 "register_operand" "")
4548 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4550 (match_operand:DI 2 "register_operand" "")))
4551 (set (mem:DI (match_dup 0))
4552 (match_operand:DI 3 "register_operand" ""))]
4554 && !TARGET_DISABLE_INDEXING
4556 && REG_OK_FOR_BASE_P (operands[2])
4557 && FP_REGNO_P (REGNO (operands[3]))"
4558 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4560 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4565 [(set (match_operand:DI 0 "register_operand" "")
4566 (plus:DI (match_operand:DI 2 "register_operand" "")
4567 (mult:DI (match_operand:DI 1 "register_operand" "")
4569 (set (mem:DI (match_dup 0))
4570 (match_operand:DI 3 "register_operand" ""))]
4572 && !TARGET_DISABLE_INDEXING
4574 && REG_OK_FOR_BASE_P (operands[2])
4575 && FP_REGNO_P (REGNO (operands[3]))"
4576 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4578 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4583 [(set (match_operand:DI 0 "register_operand" "")
4584 (plus:DI (match_operand:DI 1 "register_operand" "")
4585 (match_operand:DI 2 "register_operand" "")))
4586 (set (mem:DI (match_dup 0))
4587 (match_operand:DI 3 "register_operand" ""))]
4589 && !TARGET_DISABLE_INDEXING
4591 && TARGET_NO_SPACE_REGS
4592 && REG_OK_FOR_INDEX_P (operands[1])
4593 && REG_OK_FOR_BASE_P (operands[2])
4594 && FP_REGNO_P (REGNO (operands[3]))"
4595 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4597 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4601 [(set (match_operand:DI 0 "register_operand" "")
4602 (plus:DI (match_operand:DI 1 "register_operand" "")
4603 (match_operand:DI 2 "register_operand" "")))
4604 (set (mem:DI (match_dup 0))
4605 (match_operand:DI 3 "register_operand" ""))]
4607 && !TARGET_DISABLE_INDEXING
4609 && TARGET_NO_SPACE_REGS
4610 && REG_OK_FOR_BASE_P (operands[1])
4611 && REG_OK_FOR_INDEX_P (operands[2])
4612 && FP_REGNO_P (REGNO (operands[3]))"
4613 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4615 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4619 [(set (match_operand:DI 0 "move_dest_operand"
4621 (match_operand:DI 1 "general_operand"
4623 "(register_operand (operands[0], DImode)
4624 || reg_or_0_operand (operands[1], DImode))
4626 && TARGET_SOFT_FLOAT"
4629 return output_move_double (operands);
4631 [(set_attr "type" "move,store,store,load,load,multi")
4632 (set_attr "length" "8,8,16,8,16,16")])
4635 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4636 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4637 (match_operand:DI 2 "immediate_operand" "i,i")))]
4641 /* Don't output a 64 bit constant, since we can't trust the assembler to
4642 handle it correctly. */
4643 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4644 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4645 else if (HOST_BITS_PER_WIDE_INT > 32
4646 && GET_CODE (operands[2]) == CONST_INT)
4647 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
4648 if (which_alternative == 1)
4649 output_asm_insn (\"copy %1,%0\", operands);
4650 return \"ldo R'%G2(%R1),%R0\";
4652 [(set_attr "type" "move,move")
4653 (set_attr "length" "4,8")])
4655 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4656 ;; to be reloaded by putting the constant into memory when
4657 ;; reg is a floating point register.
4659 ;; For integer registers we use ldil;ldo to set the appropriate
4662 ;; This must come before the movsf pattern, and it must be present
4663 ;; to handle obscure reloading cases.
4665 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4666 (match_operand:SF 1 "" "?F,m"))]
4667 "GET_CODE (operands[1]) == CONST_DOUBLE
4668 && operands[1] != CONST0_RTX (SFmode)
4669 && ! TARGET_SOFT_FLOAT"
4670 "* return (which_alternative == 0 ? singlemove_string (operands)
4671 : \" fldw%F1 %1,%0\");"
4672 [(set_attr "type" "move,fpload")
4673 (set_attr "length" "8,4")])
4675 (define_expand "movsf"
4676 [(set (match_operand:SF 0 "general_operand" "")
4677 (match_operand:SF 1 "general_operand" ""))]
4681 if (emit_move_sequence (operands, SFmode, 0))
4685 ;; Handle SFmode input reloads requiring a general register as a
4686 ;; scratch register.
4687 (define_expand "reload_insf"
4688 [(set (match_operand:SF 0 "register_operand" "=Z")
4689 (match_operand:SF 1 "non_hard_reg_operand" ""))
4690 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4694 if (emit_move_sequence (operands, SFmode, operands[2]))
4697 /* We don't want the clobber emitted, so handle this ourselves. */
4698 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4702 ;; Handle SFmode output reloads requiring a general register as a
4703 ;; scratch register.
4704 (define_expand "reload_outsf"
4705 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4706 (match_operand:SF 1 "register_operand" "Z"))
4707 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4711 if (emit_move_sequence (operands, SFmode, operands[2]))
4714 /* We don't want the clobber emitted, so handle this ourselves. */
4715 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4720 [(set (match_operand:SF 0 "move_dest_operand"
4721 "=f,!*r,f,*r,Q,Q,!r,!f")
4722 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4723 "fG,!*rG,RQ,RQ,f,*rG,!f,!r"))]
4724 "(register_operand (operands[0], SFmode)
4725 || reg_or_0_operand (operands[1], SFmode))
4726 && !TARGET_SOFT_FLOAT
4735 {fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
4736 {stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
4737 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store,move,move")
4738 (set_attr "pa_combine_type" "addmove")
4739 (set_attr "length" "4,4,4,4,4,4,8,8")])
4742 [(set (match_operand:SF 0 "move_dest_operand"
4744 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4745 "fG,!*rG,RQ,RQ,f,*rG"))]
4746 "(register_operand (operands[0], SFmode)
4747 || reg_or_0_operand (operands[1], SFmode))
4748 && !TARGET_SOFT_FLOAT
4757 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4758 (set_attr "pa_combine_type" "addmove")
4759 (set_attr "length" "4,4,4,4,4,4")])
4762 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4763 (match_operand:SF 1 "register_operand" "f"))]
4765 && !TARGET_DISABLE_INDEXING
4766 && reload_completed"
4768 [(set_attr "type" "fpstore")
4769 (set_attr "pa_combine_type" "addmove")
4770 (set_attr "length" "4")])
4773 [(set (match_operand:SI 0 "register_operand" "")
4774 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4776 (match_operand:SI 2 "register_operand" "")))
4777 (set (mem:SF (match_dup 0))
4778 (match_operand:SF 3 "register_operand" ""))]
4780 && !TARGET_DISABLE_INDEXING
4781 && REG_OK_FOR_BASE_P (operands[2])
4782 && FP_REGNO_P (REGNO (operands[3]))"
4783 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4785 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4790 [(set (match_operand:SI 0 "register_operand" "")
4791 (plus:SI (match_operand:SI 2 "register_operand" "")
4792 (mult:SI (match_operand:SI 1 "register_operand" "")
4794 (set (mem:SF (match_dup 0))
4795 (match_operand:SF 3 "register_operand" ""))]
4797 && !TARGET_DISABLE_INDEXING
4798 && REG_OK_FOR_BASE_P (operands[2])
4799 && FP_REGNO_P (REGNO (operands[3]))"
4800 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4802 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4807 [(set (match_operand:DI 0 "register_operand" "")
4808 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4810 (match_operand:DI 2 "register_operand" "")))
4811 (set (mem:SF (match_dup 0))
4812 (match_operand:SF 3 "register_operand" ""))]
4814 && !TARGET_DISABLE_INDEXING
4816 && REG_OK_FOR_BASE_P (operands[2])
4817 && FP_REGNO_P (REGNO (operands[3]))"
4818 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4820 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4825 [(set (match_operand:DI 0 "register_operand" "")
4826 (plus:DI (match_operand:DI 2 "register_operand" "")
4827 (mult:DI (match_operand:DI 1 "register_operand" "")
4829 (set (mem:SF (match_dup 0))
4830 (match_operand:SF 3 "register_operand" ""))]
4832 && !TARGET_DISABLE_INDEXING
4834 && REG_OK_FOR_BASE_P (operands[2])
4835 && FP_REGNO_P (REGNO (operands[3]))"
4836 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4838 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4843 [(set (match_operand:SI 0 "register_operand" "")
4844 (plus:SI (match_operand:SI 1 "register_operand" "")
4845 (match_operand:SI 2 "register_operand" "")))
4846 (set (mem:SF (match_dup 0))
4847 (match_operand:SF 3 "register_operand" ""))]
4849 && !TARGET_DISABLE_INDEXING
4850 && TARGET_NO_SPACE_REGS
4851 && REG_OK_FOR_INDEX_P (operands[1])
4852 && REG_OK_FOR_BASE_P (operands[2])
4853 && FP_REGNO_P (REGNO (operands[3]))"
4854 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4856 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4860 [(set (match_operand:SI 0 "register_operand" "")
4861 (plus:SI (match_operand:SI 1 "register_operand" "")
4862 (match_operand:SI 2 "register_operand" "")))
4863 (set (mem:SF (match_dup 0))
4864 (match_operand:SF 3 "register_operand" ""))]
4866 && !TARGET_DISABLE_INDEXING
4867 && TARGET_NO_SPACE_REGS
4868 && REG_OK_FOR_BASE_P (operands[1])
4869 && REG_OK_FOR_INDEX_P (operands[2])
4870 && FP_REGNO_P (REGNO (operands[3]))"
4871 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4873 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4877 [(set (match_operand:DI 0 "register_operand" "")
4878 (plus:DI (match_operand:DI 1 "register_operand" "")
4879 (match_operand:DI 2 "register_operand" "")))
4880 (set (mem:SF (match_dup 0))
4881 (match_operand:SF 3 "register_operand" ""))]
4883 && !TARGET_DISABLE_INDEXING
4885 && TARGET_NO_SPACE_REGS
4886 && REG_OK_FOR_INDEX_P (operands[1])
4887 && REG_OK_FOR_BASE_P (operands[2])
4888 && FP_REGNO_P (REGNO (operands[3]))"
4889 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4891 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4895 [(set (match_operand:DI 0 "register_operand" "")
4896 (plus:DI (match_operand:DI 1 "register_operand" "")
4897 (match_operand:DI 2 "register_operand" "")))
4898 (set (mem:SF (match_dup 0))
4899 (match_operand:SF 3 "register_operand" ""))]
4901 && !TARGET_DISABLE_INDEXING
4903 && TARGET_NO_SPACE_REGS
4904 && REG_OK_FOR_BASE_P (operands[1])
4905 && REG_OK_FOR_INDEX_P (operands[2])
4906 && FP_REGNO_P (REGNO (operands[3]))"
4907 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4909 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4913 [(set (match_operand:SF 0 "move_dest_operand"
4915 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4917 "(register_operand (operands[0], SFmode)
4918 || reg_or_0_operand (operands[1], SFmode))
4919 && TARGET_SOFT_FLOAT"
4924 [(set_attr "type" "move,load,store")
4925 (set_attr "pa_combine_type" "addmove")
4926 (set_attr "length" "4,4,4")])
4930 ;;- zero extension instructions
4931 ;; We have define_expand for zero extension patterns to make sure the
4932 ;; operands get loaded into registers. The define_insns accept
4933 ;; memory operands. This gives us better overall code than just
4934 ;; having a pattern that does or does not accept memory operands.
4936 (define_expand "zero_extendqihi2"
4937 [(set (match_operand:HI 0 "register_operand" "")
4939 (match_operand:QI 1 "register_operand" "")))]
4944 [(set (match_operand:HI 0 "register_operand" "=r,r")
4946 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4947 "GET_CODE (operands[1]) != CONST_INT"
4949 {extru|extrw,u} %1,31,8,%0
4951 [(set_attr "type" "shift,load")
4952 (set_attr "length" "4,4")])
4954 (define_expand "zero_extendqisi2"
4955 [(set (match_operand:SI 0 "register_operand" "")
4957 (match_operand:QI 1 "register_operand" "")))]
4962 [(set (match_operand:SI 0 "register_operand" "=r,r")
4964 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4965 "GET_CODE (operands[1]) != CONST_INT"
4967 {extru|extrw,u} %1,31,8,%0
4969 [(set_attr "type" "shift,load")
4970 (set_attr "length" "4,4")])
4972 (define_expand "zero_extendhisi2"
4973 [(set (match_operand:SI 0 "register_operand" "")
4975 (match_operand:HI 1 "register_operand" "")))]
4980 [(set (match_operand:SI 0 "register_operand" "=r,r")
4982 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4983 "GET_CODE (operands[1]) != CONST_INT"
4985 {extru|extrw,u} %1,31,16,%0
4987 [(set_attr "type" "shift,load")
4988 (set_attr "length" "4,4")])
4990 (define_expand "zero_extendqidi2"
4991 [(set (match_operand:DI 0 "register_operand" "")
4993 (match_operand:QI 1 "register_operand" "")))]
4998 [(set (match_operand:DI 0 "register_operand" "=r,r")
5000 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
5001 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5005 [(set_attr "type" "shift,load")
5006 (set_attr "length" "4,4")])
5008 (define_expand "zero_extendhidi2"
5009 [(set (match_operand:DI 0 "register_operand" "")
5011 (match_operand:HI 1 "register_operand" "")))]
5016 [(set (match_operand:DI 0 "register_operand" "=r,r")
5018 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
5019 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5023 [(set_attr "type" "shift,load")
5024 (set_attr "length" "4,4")])
5026 (define_expand "zero_extendsidi2"
5027 [(set (match_operand:DI 0 "register_operand" "")
5029 (match_operand:SI 1 "register_operand" "")))]
5034 [(set (match_operand:DI 0 "register_operand" "=r,r")
5036 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
5037 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
5041 [(set_attr "type" "shift,load")
5042 (set_attr "length" "4,4")])
5044 ;;- sign extension instructions
5046 (define_insn "extendhisi2"
5047 [(set (match_operand:SI 0 "register_operand" "=r")
5048 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
5050 "{extrs|extrw,s} %1,31,16,%0"
5051 [(set_attr "type" "shift")
5052 (set_attr "length" "4")])
5054 (define_insn "extendqihi2"
5055 [(set (match_operand:HI 0 "register_operand" "=r")
5056 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
5058 "{extrs|extrw,s} %1,31,8,%0"
5059 [(set_attr "type" "shift")
5060 (set_attr "length" "4")])
5062 (define_insn "extendqisi2"
5063 [(set (match_operand:SI 0 "register_operand" "=r")
5064 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
5066 "{extrs|extrw,s} %1,31,8,%0"
5067 [(set_attr "type" "shift")
5068 (set_attr "length" "4")])
5070 (define_insn "extendqidi2"
5071 [(set (match_operand:DI 0 "register_operand" "=r")
5072 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
5074 "extrd,s %1,63,8,%0"
5075 [(set_attr "type" "shift")
5076 (set_attr "length" "4")])
5078 (define_insn "extendhidi2"
5079 [(set (match_operand:DI 0 "register_operand" "=r")
5080 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
5082 "extrd,s %1,63,16,%0"
5083 [(set_attr "type" "shift")
5084 (set_attr "length" "4")])
5086 (define_insn "extendsidi2"
5087 [(set (match_operand:DI 0 "register_operand" "=r")
5088 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
5090 "extrd,s %1,63,32,%0"
5091 [(set_attr "type" "shift")
5092 (set_attr "length" "4")])
5095 ;; Conversions between float and double.
5097 (define_insn "extendsfdf2"
5098 [(set (match_operand:DF 0 "register_operand" "=f")
5100 (match_operand:SF 1 "register_operand" "f")))]
5101 "! TARGET_SOFT_FLOAT"
5102 "{fcnvff|fcnv},sgl,dbl %1,%0"
5103 [(set_attr "type" "fpalu")
5104 (set_attr "length" "4")])
5106 (define_insn "truncdfsf2"
5107 [(set (match_operand:SF 0 "register_operand" "=f")
5109 (match_operand:DF 1 "register_operand" "f")))]
5110 "! TARGET_SOFT_FLOAT"
5111 "{fcnvff|fcnv},dbl,sgl %1,%0"
5112 [(set_attr "type" "fpalu")
5113 (set_attr "length" "4")])
5115 ;; Conversion between fixed point and floating point.
5116 ;; Note that among the fix-to-float insns
5117 ;; the ones that start with SImode come first.
5118 ;; That is so that an operand that is a CONST_INT
5119 ;; (and therefore lacks a specific machine mode).
5120 ;; will be recognized as SImode (which is always valid)
5121 ;; rather than as QImode or HImode.
5123 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
5124 ;; to be reloaded by putting the constant into memory.
5125 ;; It must come before the more general floatsisf2 pattern.
5127 [(set (match_operand:SF 0 "register_operand" "=f")
5128 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
5129 "! TARGET_SOFT_FLOAT"
5130 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
5131 [(set_attr "type" "fpalu")
5132 (set_attr "length" "8")])
5134 (define_insn "floatsisf2"
5135 [(set (match_operand:SF 0 "register_operand" "=f")
5136 (float:SF (match_operand:SI 1 "register_operand" "f")))]
5137 "! TARGET_SOFT_FLOAT"
5138 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
5139 [(set_attr "type" "fpalu")
5140 (set_attr "length" "4")])
5142 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
5143 ;; to be reloaded by putting the constant into memory.
5144 ;; It must come before the more general floatsidf2 pattern.
5146 [(set (match_operand:DF 0 "register_operand" "=f")
5147 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
5148 "! TARGET_SOFT_FLOAT"
5149 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
5150 [(set_attr "type" "fpalu")
5151 (set_attr "length" "8")])
5153 (define_insn "floatsidf2"
5154 [(set (match_operand:DF 0 "register_operand" "=f")
5155 (float:DF (match_operand:SI 1 "register_operand" "f")))]
5156 "! TARGET_SOFT_FLOAT"
5157 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
5158 [(set_attr "type" "fpalu")
5159 (set_attr "length" "4")])
5161 (define_expand "floatunssisf2"
5162 [(set (subreg:SI (match_dup 2) 4)
5163 (match_operand:SI 1 "register_operand" ""))
5164 (set (subreg:SI (match_dup 2) 0)
5166 (set (match_operand:SF 0 "register_operand" "")
5167 (float:SF (match_dup 2)))]
5168 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5173 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
5176 operands[2] = gen_reg_rtx (DImode);
5179 (define_expand "floatunssidf2"
5180 [(set (subreg:SI (match_dup 2) 4)
5181 (match_operand:SI 1 "register_operand" ""))
5182 (set (subreg:SI (match_dup 2) 0)
5184 (set (match_operand:DF 0 "register_operand" "")
5185 (float:DF (match_dup 2)))]
5186 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5191 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
5194 operands[2] = gen_reg_rtx (DImode);
5197 (define_insn "floatdisf2"
5198 [(set (match_operand:SF 0 "register_operand" "=f")
5199 (float:SF (match_operand:DI 1 "register_operand" "f")))]
5200 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5201 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
5202 [(set_attr "type" "fpalu")
5203 (set_attr "length" "4")])
5205 (define_insn "floatdidf2"
5206 [(set (match_operand:DF 0 "register_operand" "=f")
5207 (float:DF (match_operand:DI 1 "register_operand" "f")))]
5208 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5209 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
5210 [(set_attr "type" "fpalu")
5211 (set_attr "length" "4")])
5213 ;; Convert a float to an actual integer.
5214 ;; Truncation is performed as part of the conversion.
5216 (define_insn "fix_truncsfsi2"
5217 [(set (match_operand:SI 0 "register_operand" "=f")
5218 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5219 "! TARGET_SOFT_FLOAT"
5220 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
5221 [(set_attr "type" "fpalu")
5222 (set_attr "length" "4")])
5224 (define_insn "fix_truncdfsi2"
5225 [(set (match_operand:SI 0 "register_operand" "=f")
5226 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5227 "! TARGET_SOFT_FLOAT"
5228 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
5229 [(set_attr "type" "fpalu")
5230 (set_attr "length" "4")])
5232 (define_insn "fix_truncsfdi2"
5233 [(set (match_operand:DI 0 "register_operand" "=f")
5234 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5235 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5236 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
5237 [(set_attr "type" "fpalu")
5238 (set_attr "length" "4")])
5240 (define_insn "fix_truncdfdi2"
5241 [(set (match_operand:DI 0 "register_operand" "=f")
5242 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5243 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
5244 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
5245 [(set_attr "type" "fpalu")
5246 (set_attr "length" "4")])
5248 (define_insn "floatunssidf2_pa20"
5249 [(set (match_operand:DF 0 "register_operand" "=f")
5250 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
5251 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5253 [(set_attr "type" "fpalu")
5254 (set_attr "length" "4")])
5256 (define_insn "floatunssisf2_pa20"
5257 [(set (match_operand:SF 0 "register_operand" "=f")
5258 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
5259 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5261 [(set_attr "type" "fpalu")
5262 (set_attr "length" "4")])
5264 (define_insn "floatunsdisf2"
5265 [(set (match_operand:SF 0 "register_operand" "=f")
5266 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
5267 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5268 "fcnv,udw,sgl %1,%0"
5269 [(set_attr "type" "fpalu")
5270 (set_attr "length" "4")])
5272 (define_insn "floatunsdidf2"
5273 [(set (match_operand:DF 0 "register_operand" "=f")
5274 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
5275 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5276 "fcnv,udw,dbl %1,%0"
5277 [(set_attr "type" "fpalu")
5278 (set_attr "length" "4")])
5280 (define_insn "fixuns_truncsfsi2"
5281 [(set (match_operand:SI 0 "register_operand" "=f")
5282 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5283 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5284 "fcnv,t,sgl,uw %1,%0"
5285 [(set_attr "type" "fpalu")
5286 (set_attr "length" "4")])
5288 (define_insn "fixuns_truncdfsi2"
5289 [(set (match_operand:SI 0 "register_operand" "=f")
5290 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5291 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5292 "fcnv,t,dbl,uw %1,%0"
5293 [(set_attr "type" "fpalu")
5294 (set_attr "length" "4")])
5296 (define_insn "fixuns_truncsfdi2"
5297 [(set (match_operand:DI 0 "register_operand" "=f")
5298 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
5299 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5300 "fcnv,t,sgl,udw %1,%0"
5301 [(set_attr "type" "fpalu")
5302 (set_attr "length" "4")])
5304 (define_insn "fixuns_truncdfdi2"
5305 [(set (match_operand:DI 0 "register_operand" "=f")
5306 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
5307 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5308 "fcnv,t,dbl,udw %1,%0"
5309 [(set_attr "type" "fpalu")
5310 (set_attr "length" "4")])
5312 ;;- arithmetic instructions
5314 (define_expand "adddi3"
5315 [(set (match_operand:DI 0 "register_operand" "")
5316 (plus:DI (match_operand:DI 1 "register_operand" "")
5317 (match_operand:DI 2 "adddi3_operand" "")))]
5322 [(set (match_operand:DI 0 "register_operand" "=r")
5323 (plus:DI (match_operand:DI 1 "register_operand" "%r")
5324 (match_operand:DI 2 "arith11_operand" "rI")))]
5328 if (GET_CODE (operands[2]) == CONST_INT)
5330 if (INTVAL (operands[2]) >= 0)
5331 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
5333 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
5336 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
5338 [(set_attr "type" "binary")
5339 (set_attr "length" "8")])
5342 [(set (match_operand:DI 0 "register_operand" "=r,r")
5343 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
5344 (match_operand:DI 2 "arith_operand" "r,J")))]
5349 [(set_attr "type" "binary,binary")
5350 (set_attr "pa_combine_type" "addmove")
5351 (set_attr "length" "4,4")])
5354 [(set (match_operand:DI 0 "register_operand" "=r")
5355 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5356 (match_operand:DI 2 "register_operand" "r")))]
5359 [(set_attr "type" "binary")
5360 (set_attr "length" "4")])
5363 [(set (match_operand:SI 0 "register_operand" "=r")
5364 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5365 (match_operand:SI 2 "register_operand" "r")))]
5368 [(set_attr "type" "binary")
5369 (set_attr "length" "4")])
5371 (define_expand "addvdi3"
5372 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5373 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "")
5374 (match_operand:DI 2 "arith11_operand" "")))
5375 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5376 (sign_extend:TI (match_dup 2)))
5377 (sign_extend:TI (plus:DI (match_dup 1)
5384 [(set (match_operand:DI 0 "register_operand" "=r,r")
5385 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM")
5386 (match_operand:DI 2 "arith11_operand" "r,I")))
5387 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5388 (sign_extend:TI (match_dup 2)))
5389 (sign_extend:TI (plus:DI (match_dup 1)
5395 addi,tsv,* %2,%1,%0"
5396 [(set_attr "type" "binary,binary")
5397 (set_attr "length" "4,4")])
5400 [(set (match_operand:DI 0 "register_operand" "=r")
5401 (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM")
5402 (match_operand:DI 2 "arith11_operand" "rI")))
5403 (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1))
5404 (sign_extend:TI (match_dup 2)))
5405 (sign_extend:TI (plus:DI (match_dup 1)
5411 if (GET_CODE (operands[2]) == CONST_INT)
5413 if (INTVAL (operands[2]) >= 0)
5414 return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
5416 return \"addi %2,%R1,%R0\;{subbo|sub,b,tsv} %1,%%r0,%0\";
5419 return \"add %R2,%R1,%R0\;{addco|add,c,tsv} %2,%1,%0\";
5421 [(set_attr "type" "binary")
5422 (set_attr "length" "8")])
5424 ;; define_splits to optimize cases of adding a constant integer
5425 ;; to a register when the constant does not fit in 14 bits. */
5427 [(set (match_operand:SI 0 "register_operand" "")
5428 (plus:SI (match_operand:SI 1 "register_operand" "")
5429 (match_operand:SI 2 "const_int_operand" "")))
5430 (clobber (match_operand:SI 4 "register_operand" ""))]
5431 "! cint_ok_for_move (INTVAL (operands[2]))
5432 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
5433 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
5434 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
5437 int val = INTVAL (operands[2]);
5438 int low = (val < 0) ? -0x2000 : 0x1fff;
5439 int rest = val - low;
5441 operands[2] = GEN_INT (rest);
5442 operands[3] = GEN_INT (low);
5446 [(set (match_operand:SI 0 "register_operand" "")
5447 (plus:SI (match_operand:SI 1 "register_operand" "")
5448 (match_operand:SI 2 "const_int_operand" "")))
5449 (clobber (match_operand:SI 4 "register_operand" ""))]
5450 "! cint_ok_for_move (INTVAL (operands[2]))"
5451 [(set (match_dup 4) (match_dup 2))
5452 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
5456 HOST_WIDE_INT intval = INTVAL (operands[2]);
5458 /* Try dividing the constant by 2, then 4, and finally 8 to see
5459 if we can get a constant which can be loaded into a register
5460 in a single instruction (cint_ok_for_move).
5462 If that fails, try to negate the constant and subtract it
5463 from our input operand. */
5464 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
5466 operands[2] = GEN_INT (intval / 2);
5467 operands[3] = const2_rtx;
5469 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
5471 operands[2] = GEN_INT (intval / 4);
5472 operands[3] = GEN_INT (4);
5474 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
5476 operands[2] = GEN_INT (intval / 8);
5477 operands[3] = GEN_INT (8);
5479 else if (cint_ok_for_move (-intval))
5481 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
5482 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
5489 (define_insn "addsi3"
5490 [(set (match_operand:SI 0 "register_operand" "=r,r")
5491 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
5492 (match_operand:SI 2 "arith_operand" "r,J")))]
5495 {addl|add,l} %1,%2,%0
5497 [(set_attr "type" "binary,binary")
5498 (set_attr "pa_combine_type" "addmove")
5499 (set_attr "length" "4,4")])
5501 (define_insn "addvsi3"
5502 [(set (match_operand:SI 0 "register_operand" "=r,r")
5503 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rM,rM")
5504 (match_operand:SI 2 "arith11_operand" "r,I")))
5505 (trap_if (ne (plus:DI (sign_extend:DI (match_dup 1))
5506 (sign_extend:DI (match_dup 2)))
5507 (sign_extend:DI (plus:SI (match_dup 1)
5512 {addo|add,tsv} %2,%1,%0
5513 {addio|addi,tsv} %2,%1,%0"
5514 [(set_attr "type" "binary,binary")
5515 (set_attr "length" "4,4")])
5517 (define_expand "subdi3"
5518 [(set (match_operand:DI 0 "register_operand" "")
5519 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5520 (match_operand:DI 2 "reg_or_0_operand" "")))]
5525 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5526 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5527 (match_operand:DI 2 "reg_or_0_operand" "rM,rM,!rM")))]
5533 [(set_attr "type" "binary,binary,move")
5534 (set_attr "length" "4,4,4")])
5537 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5538 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5539 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))]
5543 if (GET_CODE (operands[1]) == CONST_INT)
5545 if (INTVAL (operands[1]) >= 0)
5546 return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
5548 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subb|sub,b} %0,%2,%0\";
5551 return \"sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0\";
5553 [(set_attr "type" "binary")
5554 (set (attr "length")
5555 (if_then_else (eq_attr "alternative" "0")
5557 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5562 (define_expand "subvdi3"
5563 [(parallel [(set (match_operand:DI 0 "register_operand" "")
5564 (minus:DI (match_operand:DI 1 "arith11_operand" "")
5565 (match_operand:DI 2 "reg_or_0_operand" "")))
5566 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5567 (sign_extend:TI (match_dup 2)))
5568 (sign_extend:TI (minus:DI (match_dup 1)
5575 [(set (match_operand:DI 0 "register_operand" "=r,r")
5576 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5577 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5578 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5579 (sign_extend:TI (match_dup 2)))
5580 (sign_extend:TI (minus:DI (match_dup 1)
5585 {subo|sub,tsv} %1,%2,%0
5586 {subio|subi,tsv} %1,%2,%0"
5587 [(set_attr "type" "binary,binary")
5588 (set_attr "length" "4,4")])
5591 [(set (match_operand:DI 0 "register_operand" "=r,&r")
5592 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I")
5593 (match_operand:DI 2 "reg_or_0_operand" "rM,rM")))
5594 (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1))
5595 (sign_extend:TI (match_dup 2)))
5596 (sign_extend:TI (minus:DI (match_dup 1)
5602 if (GET_CODE (operands[1]) == CONST_INT)
5604 if (INTVAL (operands[1]) >= 0)
5605 return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
5607 return \"ldi -1,%0\;subi %1,%R2,%R0\;{subbo|sub,b,tsv} %0,%2,%0\";
5610 return \"sub %R1,%R2,%R0\;{subbo|sub,b,tsv} %1,%2,%0\";
5612 [(set_attr "type" "binary,binary")
5613 (set (attr "length")
5614 (if_then_else (eq_attr "alternative" "0")
5616 (if_then_else (ge (symbol_ref "INTVAL (operands[1])")
5621 (define_expand "subsi3"
5622 [(set (match_operand:SI 0 "register_operand" "")
5623 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5624 (match_operand:SI 2 "register_operand" "")))]
5629 [(set (match_operand:SI 0 "register_operand" "=r,r")
5630 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5631 (match_operand:SI 2 "register_operand" "r,r")))]
5636 [(set_attr "type" "binary,binary")
5637 (set_attr "length" "4,4")])
5640 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5641 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5642 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5648 [(set_attr "type" "binary,binary,move")
5649 (set_attr "length" "4,4,4")])
5651 (define_insn "subvsi3"
5652 [(set (match_operand:SI 0 "register_operand" "=r,r")
5653 (minus:SI (match_operand:SI 1 "arith11_operand" "rM,I")
5654 (match_operand:SI 2 "reg_or_0_operand" "rM,rM")))
5655 (trap_if (ne (minus:DI (sign_extend:DI (match_dup 1))
5656 (sign_extend:DI (match_dup 2)))
5657 (sign_extend:DI (minus:SI (match_dup 1)
5662 {subo|sub,tsv} %1,%2,%0
5663 {subio|subi,tsv} %1,%2,%0"
5664 [(set_attr "type" "binary,binary")
5665 (set_attr "length" "4,4")])
5667 ;; Clobbering a "register_operand" instead of a match_scratch
5668 ;; in operand3 of millicode calls avoids spilling %r1 and
5669 ;; produces better code.
5671 ;; The mulsi3 insns set up registers for the millicode call.
5672 (define_expand "mulsi3"
5673 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5674 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5675 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5676 (clobber (match_dup 3))
5677 (clobber (reg:SI 26))
5678 (clobber (reg:SI 25))
5679 (clobber (match_dup 4))])
5680 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5684 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5685 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5687 rtx scratch = gen_reg_rtx (DImode);
5688 operands[1] = force_reg (SImode, operands[1]);
5689 operands[2] = force_reg (SImode, operands[2]);
5690 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5691 emit_insn (gen_movsi (operands[0],
5692 gen_rtx_SUBREG (SImode, scratch,
5693 GET_MODE_SIZE (SImode))));
5696 operands[3] = gen_reg_rtx (SImode);
5699 (define_insn "umulsidi3"
5700 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5701 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5702 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5703 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5705 [(set_attr "type" "fpmuldbl")
5706 (set_attr "length" "4")])
5709 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5710 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5711 (match_operand:DI 2 "uint32_operand" "f")))]
5712 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5714 [(set_attr "type" "fpmuldbl")
5715 (set_attr "length" "4")])
5718 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5719 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5720 (match_operand:DI 2 "uint32_operand" "f")))]
5721 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5723 [(set_attr "type" "fpmuldbl")
5724 (set_attr "length" "4")])
5727 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5728 (clobber (match_operand:SI 0 "register_operand" "=a"))
5729 (clobber (reg:SI 26))
5730 (clobber (reg:SI 25))
5731 (clobber (reg:SI 31))]
5733 "* return output_mul_insn (0, insn);"
5734 [(set_attr "type" "milli")
5735 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5738 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5739 (clobber (match_operand:SI 0 "register_operand" "=a"))
5740 (clobber (reg:SI 26))
5741 (clobber (reg:SI 25))
5742 (clobber (reg:SI 2))]
5744 "* return output_mul_insn (0, insn);"
5745 [(set_attr "type" "milli")
5746 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5748 (define_expand "muldi3"
5749 [(set (match_operand:DI 0 "register_operand" "")
5750 (mult:DI (match_operand:DI 1 "register_operand" "")
5751 (match_operand:DI 2 "register_operand" "")))]
5752 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5755 rtx low_product = gen_reg_rtx (DImode);
5756 rtx cross_product1 = gen_reg_rtx (DImode);
5757 rtx cross_product2 = gen_reg_rtx (DImode);
5758 rtx cross_scratch = gen_reg_rtx (DImode);
5759 rtx cross_product = gen_reg_rtx (DImode);
5760 rtx op1l, op1r, op2l, op2r;
5761 rtx op1shifted, op2shifted;
5763 op1shifted = gen_reg_rtx (DImode);
5764 op2shifted = gen_reg_rtx (DImode);
5765 op1l = gen_reg_rtx (SImode);
5766 op1r = gen_reg_rtx (SImode);
5767 op2l = gen_reg_rtx (SImode);
5768 op2r = gen_reg_rtx (SImode);
5770 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5772 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5774 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5775 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5776 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5777 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5779 /* Emit multiplies for the cross products. */
5780 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5781 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5783 /* Emit a multiply for the low sub-word. */
5784 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5786 /* Sum the cross products and shift them into proper position. */
5787 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5788 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5790 /* Add the cross product to the low product and store the result
5791 into the output operand . */
5792 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5796 ;;; Division and mod.
5797 (define_expand "divsi3"
5798 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5799 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5800 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5801 (clobber (match_dup 3))
5802 (clobber (match_dup 4))
5803 (clobber (reg:SI 26))
5804 (clobber (reg:SI 25))
5805 (clobber (match_dup 5))])
5806 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5810 operands[3] = gen_reg_rtx (SImode);
5813 operands[5] = gen_rtx_REG (SImode, 2);
5814 operands[4] = operands[5];
5818 operands[5] = gen_rtx_REG (SImode, 31);
5819 operands[4] = gen_reg_rtx (SImode);
5821 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5827 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5828 (clobber (match_operand:SI 1 "register_operand" "=a"))
5829 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5830 (clobber (reg:SI 26))
5831 (clobber (reg:SI 25))
5832 (clobber (reg:SI 31))]
5835 return output_div_insn (operands, 0, insn);"
5836 [(set_attr "type" "milli")
5837 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5841 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5842 (clobber (match_operand:SI 1 "register_operand" "=a"))
5843 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5844 (clobber (reg:SI 26))
5845 (clobber (reg:SI 25))
5846 (clobber (reg:SI 2))]
5849 return output_div_insn (operands, 0, insn);"
5850 [(set_attr "type" "milli")
5851 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5853 (define_expand "udivsi3"
5854 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5855 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5856 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5857 (clobber (match_dup 3))
5858 (clobber (match_dup 4))
5859 (clobber (reg:SI 26))
5860 (clobber (reg:SI 25))
5861 (clobber (match_dup 5))])
5862 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5866 operands[3] = gen_reg_rtx (SImode);
5870 operands[5] = gen_rtx_REG (SImode, 2);
5871 operands[4] = operands[5];
5875 operands[5] = gen_rtx_REG (SImode, 31);
5876 operands[4] = gen_reg_rtx (SImode);
5878 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5884 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5885 (clobber (match_operand:SI 1 "register_operand" "=a"))
5886 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5887 (clobber (reg:SI 26))
5888 (clobber (reg:SI 25))
5889 (clobber (reg:SI 31))]
5892 return output_div_insn (operands, 1, insn);"
5893 [(set_attr "type" "milli")
5894 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5898 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5899 (clobber (match_operand:SI 1 "register_operand" "=a"))
5900 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5901 (clobber (reg:SI 26))
5902 (clobber (reg:SI 25))
5903 (clobber (reg:SI 2))]
5906 return output_div_insn (operands, 1, insn);"
5907 [(set_attr "type" "milli")
5908 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5910 (define_expand "modsi3"
5911 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5912 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5913 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5914 (clobber (match_dup 3))
5915 (clobber (match_dup 4))
5916 (clobber (reg:SI 26))
5917 (clobber (reg:SI 25))
5918 (clobber (match_dup 5))])
5919 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5925 operands[5] = gen_rtx_REG (SImode, 2);
5926 operands[4] = operands[5];
5930 operands[5] = gen_rtx_REG (SImode, 31);
5931 operands[4] = gen_reg_rtx (SImode);
5933 operands[3] = gen_reg_rtx (SImode);
5937 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5938 (clobber (match_operand:SI 0 "register_operand" "=a"))
5939 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5940 (clobber (reg:SI 26))
5941 (clobber (reg:SI 25))
5942 (clobber (reg:SI 31))]
5945 return output_mod_insn (0, insn);"
5946 [(set_attr "type" "milli")
5947 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5950 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5951 (clobber (match_operand:SI 0 "register_operand" "=a"))
5952 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5953 (clobber (reg:SI 26))
5954 (clobber (reg:SI 25))
5955 (clobber (reg:SI 2))]
5958 return output_mod_insn (0, insn);"
5959 [(set_attr "type" "milli")
5960 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5962 (define_expand "umodsi3"
5963 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5964 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5965 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5966 (clobber (match_dup 3))
5967 (clobber (match_dup 4))
5968 (clobber (reg:SI 26))
5969 (clobber (reg:SI 25))
5970 (clobber (match_dup 5))])
5971 (set (match_operand:SI 0 "move_dest_operand" "") (reg:SI 29))]
5977 operands[5] = gen_rtx_REG (SImode, 2);
5978 operands[4] = operands[5];
5982 operands[5] = gen_rtx_REG (SImode, 31);
5983 operands[4] = gen_reg_rtx (SImode);
5985 operands[3] = gen_reg_rtx (SImode);
5989 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5990 (clobber (match_operand:SI 0 "register_operand" "=a"))
5991 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5992 (clobber (reg:SI 26))
5993 (clobber (reg:SI 25))
5994 (clobber (reg:SI 31))]
5997 return output_mod_insn (1, insn);"
5998 [(set_attr "type" "milli")
5999 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6002 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
6003 (clobber (match_operand:SI 0 "register_operand" "=a"))
6004 (clobber (match_operand:SI 1 "register_operand" "=&r"))
6005 (clobber (reg:SI 26))
6006 (clobber (reg:SI 25))
6007 (clobber (reg:SI 2))]
6010 return output_mod_insn (1, insn);"
6011 [(set_attr "type" "milli")
6012 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
6014 ;;- and instructions
6015 ;; We define DImode `and` so with DImode `not` we can get
6016 ;; DImode `andn`. Other combinations are possible.
6018 (define_expand "anddi3"
6019 [(set (match_operand:DI 0 "register_operand" "")
6020 (and:DI (match_operand:DI 1 "register_operand" "")
6021 (match_operand:DI 2 "and_operand" "")))]
6025 /* Both operands must be register operands. */
6026 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6031 [(set (match_operand:DI 0 "register_operand" "=r")
6032 (and:DI (match_operand:DI 1 "register_operand" "%r")
6033 (match_operand:DI 2 "register_operand" "r")))]
6035 "and %1,%2,%0\;and %R1,%R2,%R0"
6036 [(set_attr "type" "binary")
6037 (set_attr "length" "8")])
6040 [(set (match_operand:DI 0 "register_operand" "=r,r")
6041 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
6042 (match_operand:DI 2 "and_operand" "rO,P")))]
6044 "* return output_64bit_and (operands); "
6045 [(set_attr "type" "binary")
6046 (set_attr "length" "4")])
6048 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
6049 ; constant with ldil;ldo.
6050 (define_insn "andsi3"
6051 [(set (match_operand:SI 0 "register_operand" "=r,r")
6052 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
6053 (match_operand:SI 2 "and_operand" "rO,P")))]
6055 "* return output_and (operands); "
6056 [(set_attr "type" "binary,shift")
6057 (set_attr "length" "4,4")])
6060 [(set (match_operand:DI 0 "register_operand" "=r")
6061 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6062 (match_operand:DI 2 "register_operand" "r")))]
6064 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
6065 [(set_attr "type" "binary")
6066 (set_attr "length" "8")])
6069 [(set (match_operand:DI 0 "register_operand" "=r")
6070 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
6071 (match_operand:DI 2 "register_operand" "r")))]
6074 [(set_attr "type" "binary")
6075 (set_attr "length" "4")])
6078 [(set (match_operand:SI 0 "register_operand" "=r")
6079 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
6080 (match_operand:SI 2 "register_operand" "r")))]
6083 [(set_attr "type" "binary")
6084 (set_attr "length" "4")])
6086 (define_expand "iordi3"
6087 [(set (match_operand:DI 0 "register_operand" "")
6088 (ior:DI (match_operand:DI 1 "register_operand" "")
6089 (match_operand:DI 2 "ior_operand" "")))]
6093 /* Both operands must be register operands. */
6094 if (!TARGET_64BIT && !register_operand (operands[2], DImode))
6099 [(set (match_operand:DI 0 "register_operand" "=r")
6100 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6101 (match_operand:DI 2 "register_operand" "r")))]
6103 "or %1,%2,%0\;or %R1,%R2,%R0"
6104 [(set_attr "type" "binary")
6105 (set_attr "length" "8")])
6108 [(set (match_operand:DI 0 "register_operand" "=r,r")
6109 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
6110 (match_operand:DI 2 "ior_operand" "M,i")))]
6112 "* return output_64bit_ior (operands); "
6113 [(set_attr "type" "binary,shift")
6114 (set_attr "length" "4,4")])
6117 [(set (match_operand:DI 0 "register_operand" "=r")
6118 (ior:DI (match_operand:DI 1 "register_operand" "%r")
6119 (match_operand:DI 2 "register_operand" "r")))]
6122 [(set_attr "type" "binary")
6123 (set_attr "length" "4")])
6125 ;; Need a define_expand because we've run out of CONST_OK... characters.
6126 (define_expand "iorsi3"
6127 [(set (match_operand:SI 0 "register_operand" "")
6128 (ior:SI (match_operand:SI 1 "register_operand" "")
6129 (match_operand:SI 2 "arith32_operand" "")))]
6133 if (! (ior_operand (operands[2], SImode)
6134 || register_operand (operands[2], SImode)))
6135 operands[2] = force_reg (SImode, operands[2]);
6139 [(set (match_operand:SI 0 "register_operand" "=r,r")
6140 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
6141 (match_operand:SI 2 "ior_operand" "M,i")))]
6143 "* return output_ior (operands); "
6144 [(set_attr "type" "binary,shift")
6145 (set_attr "length" "4,4")])
6148 [(set (match_operand:SI 0 "register_operand" "=r")
6149 (ior:SI (match_operand:SI 1 "register_operand" "%r")
6150 (match_operand:SI 2 "register_operand" "r")))]
6153 [(set_attr "type" "binary")
6154 (set_attr "length" "4")])
6156 (define_expand "xordi3"
6157 [(set (match_operand:DI 0 "register_operand" "")
6158 (xor:DI (match_operand:DI 1 "register_operand" "")
6159 (match_operand:DI 2 "register_operand" "")))]
6166 [(set (match_operand:DI 0 "register_operand" "=r")
6167 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6168 (match_operand:DI 2 "register_operand" "r")))]
6170 "xor %1,%2,%0\;xor %R1,%R2,%R0"
6171 [(set_attr "type" "binary")
6172 (set_attr "length" "8")])
6175 [(set (match_operand:DI 0 "register_operand" "=r")
6176 (xor:DI (match_operand:DI 1 "register_operand" "%r")
6177 (match_operand:DI 2 "register_operand" "r")))]
6180 [(set_attr "type" "binary")
6181 (set_attr "length" "4")])
6183 (define_insn "xorsi3"
6184 [(set (match_operand:SI 0 "register_operand" "=r")
6185 (xor:SI (match_operand:SI 1 "register_operand" "%r")
6186 (match_operand:SI 2 "register_operand" "r")))]
6189 [(set_attr "type" "binary")
6190 (set_attr "length" "4")])
6192 (define_expand "negdi2"
6193 [(set (match_operand:DI 0 "register_operand" "")
6194 (neg:DI (match_operand:DI 1 "register_operand" "")))]
6199 [(set (match_operand:DI 0 "register_operand" "=r")
6200 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6202 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
6203 [(set_attr "type" "unary")
6204 (set_attr "length" "8")])
6207 [(set (match_operand:DI 0 "register_operand" "=r")
6208 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
6211 [(set_attr "type" "unary")
6212 (set_attr "length" "4")])
6214 (define_expand "negvdi2"
6215 [(parallel [(set (match_operand:DI 0 "register_operand" "")
6216 (neg:DI (match_operand:DI 1 "register_operand" "")))
6217 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6218 (sign_extend:TI (neg:DI (match_dup 1))))
6224 [(set (match_operand:DI 0 "register_operand" "=r")
6225 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6226 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6227 (sign_extend:TI (neg:DI (match_dup 1))))
6230 "sub %%r0,%R1,%R0\;{subbo|sub,b,tsv} %%r0,%1,%0"
6231 [(set_attr "type" "unary")
6232 (set_attr "length" "8")])
6235 [(set (match_operand:DI 0 "register_operand" "=r")
6236 (neg:DI (match_operand:DI 1 "register_operand" "r")))
6237 (trap_if (ne (neg:TI (sign_extend:TI (match_dup 1)))
6238 (sign_extend:TI (neg:DI (match_dup 1))))
6241 "sub,tsv %%r0,%1,%0"
6242 [(set_attr "type" "unary")
6243 (set_attr "length" "4")])
6245 (define_insn "negsi2"
6246 [(set (match_operand:SI 0 "register_operand" "=r")
6247 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
6250 [(set_attr "type" "unary")
6251 (set_attr "length" "4")])
6253 (define_insn "negvsi2"
6254 [(set (match_operand:SI 0 "register_operand" "=r")
6255 (neg:SI (match_operand:SI 1 "register_operand" "r")))
6256 (trap_if (ne (neg:DI (sign_extend:DI (match_dup 1)))
6257 (sign_extend:DI (neg:SI (match_dup 1))))
6260 "{subo|sub,tsv} %%r0,%1,%0"
6261 [(set_attr "type" "unary")
6262 (set_attr "length" "4")])
6264 (define_expand "one_cmpldi2"
6265 [(set (match_operand:DI 0 "register_operand" "")
6266 (not:DI (match_operand:DI 1 "register_operand" "")))]
6273 [(set (match_operand:DI 0 "register_operand" "=r")
6274 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6276 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
6277 [(set_attr "type" "unary")
6278 (set_attr "length" "8")])
6281 [(set (match_operand:DI 0 "register_operand" "=r")
6282 (not:DI (match_operand:DI 1 "register_operand" "r")))]
6285 [(set_attr "type" "unary")
6286 (set_attr "length" "4")])
6288 (define_insn "one_cmplsi2"
6289 [(set (match_operand:SI 0 "register_operand" "=r")
6290 (not:SI (match_operand:SI 1 "register_operand" "r")))]
6293 [(set_attr "type" "unary")
6294 (set_attr "length" "4")])
6296 ;; Floating point arithmetic instructions.
6298 (define_insn "adddf3"
6299 [(set (match_operand:DF 0 "register_operand" "=f")
6300 (plus:DF (match_operand:DF 1 "register_operand" "f")
6301 (match_operand:DF 2 "register_operand" "f")))]
6302 "! TARGET_SOFT_FLOAT"
6304 [(set_attr "type" "fpalu")
6305 (set_attr "pa_combine_type" "faddsub")
6306 (set_attr "length" "4")])
6308 (define_insn "addsf3"
6309 [(set (match_operand:SF 0 "register_operand" "=f")
6310 (plus:SF (match_operand:SF 1 "register_operand" "f")
6311 (match_operand:SF 2 "register_operand" "f")))]
6312 "! TARGET_SOFT_FLOAT"
6314 [(set_attr "type" "fpalu")
6315 (set_attr "pa_combine_type" "faddsub")
6316 (set_attr "length" "4")])
6318 (define_insn "subdf3"
6319 [(set (match_operand:DF 0 "register_operand" "=f")
6320 (minus:DF (match_operand:DF 1 "register_operand" "f")
6321 (match_operand:DF 2 "register_operand" "f")))]
6322 "! TARGET_SOFT_FLOAT"
6324 [(set_attr "type" "fpalu")
6325 (set_attr "pa_combine_type" "faddsub")
6326 (set_attr "length" "4")])
6328 (define_insn "subsf3"
6329 [(set (match_operand:SF 0 "register_operand" "=f")
6330 (minus:SF (match_operand:SF 1 "register_operand" "f")
6331 (match_operand:SF 2 "register_operand" "f")))]
6332 "! TARGET_SOFT_FLOAT"
6334 [(set_attr "type" "fpalu")
6335 (set_attr "pa_combine_type" "faddsub")
6336 (set_attr "length" "4")])
6338 (define_insn "muldf3"
6339 [(set (match_operand:DF 0 "register_operand" "=f")
6340 (mult:DF (match_operand:DF 1 "register_operand" "f")
6341 (match_operand:DF 2 "register_operand" "f")))]
6342 "! TARGET_SOFT_FLOAT"
6344 [(set_attr "type" "fpmuldbl")
6345 (set_attr "pa_combine_type" "fmpy")
6346 (set_attr "length" "4")])
6348 (define_insn "mulsf3"
6349 [(set (match_operand:SF 0 "register_operand" "=f")
6350 (mult:SF (match_operand:SF 1 "register_operand" "f")
6351 (match_operand:SF 2 "register_operand" "f")))]
6352 "! TARGET_SOFT_FLOAT"
6354 [(set_attr "type" "fpmulsgl")
6355 (set_attr "pa_combine_type" "fmpy")
6356 (set_attr "length" "4")])
6358 (define_insn "divdf3"
6359 [(set (match_operand:DF 0 "register_operand" "=f")
6360 (div:DF (match_operand:DF 1 "register_operand" "f")
6361 (match_operand:DF 2 "register_operand" "f")))]
6362 "! TARGET_SOFT_FLOAT"
6364 [(set_attr "type" "fpdivdbl")
6365 (set_attr "length" "4")])
6367 (define_insn "divsf3"
6368 [(set (match_operand:SF 0 "register_operand" "=f")
6369 (div:SF (match_operand:SF 1 "register_operand" "f")
6370 (match_operand:SF 2 "register_operand" "f")))]
6371 "! TARGET_SOFT_FLOAT"
6373 [(set_attr "type" "fpdivsgl")
6374 (set_attr "length" "4")])
6376 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
6377 ;; negation can be done by subtracting from plus zero. However, this
6378 ;; violates the IEEE standard when negating plus and minus zero.
6379 (define_expand "negdf2"
6380 [(parallel [(set (match_operand:DF 0 "register_operand" "")
6381 (neg:DF (match_operand:DF 1 "register_operand" "")))
6382 (use (match_dup 2))])]
6383 "! TARGET_SOFT_FLOAT"
6385 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6386 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
6389 operands[2] = force_reg (DFmode,
6390 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
6391 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
6396 (define_insn "negdf2_fast"
6397 [(set (match_operand:DF 0 "register_operand" "=f")
6398 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
6399 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6403 return \"fneg,dbl %1,%0\";
6405 return \"fsub,dbl %%fr0,%1,%0\";
6407 [(set_attr "type" "fpalu")
6408 (set_attr "length" "4")])
6410 (define_expand "negsf2"
6411 [(parallel [(set (match_operand:SF 0 "register_operand" "")
6412 (neg:SF (match_operand:SF 1 "register_operand" "")))
6413 (use (match_dup 2))])]
6414 "! TARGET_SOFT_FLOAT"
6416 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
6417 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
6420 operands[2] = force_reg (SFmode,
6421 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
6422 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
6427 (define_insn "negsf2_fast"
6428 [(set (match_operand:SF 0 "register_operand" "=f")
6429 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
6430 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
6434 return \"fneg,sgl %1,%0\";
6436 return \"fsub,sgl %%fr0,%1,%0\";
6438 [(set_attr "type" "fpalu")
6439 (set_attr "length" "4")])
6441 (define_insn "absdf2"
6442 [(set (match_operand:DF 0 "register_operand" "=f")
6443 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
6444 "! TARGET_SOFT_FLOAT"
6446 [(set_attr "type" "fpalu")
6447 (set_attr "length" "4")])
6449 (define_insn "abssf2"
6450 [(set (match_operand:SF 0 "register_operand" "=f")
6451 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
6452 "! TARGET_SOFT_FLOAT"
6454 [(set_attr "type" "fpalu")
6455 (set_attr "length" "4")])
6457 (define_insn "sqrtdf2"
6458 [(set (match_operand:DF 0 "register_operand" "=f")
6459 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
6460 "! TARGET_SOFT_FLOAT"
6462 [(set_attr "type" "fpsqrtdbl")
6463 (set_attr "length" "4")])
6465 (define_insn "sqrtsf2"
6466 [(set (match_operand:SF 0 "register_operand" "=f")
6467 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
6468 "! TARGET_SOFT_FLOAT"
6470 [(set_attr "type" "fpsqrtsgl")
6471 (set_attr "length" "4")])
6473 ;; PA 2.0 floating point instructions
6477 [(set (match_operand:DF 0 "register_operand" "=f")
6478 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6479 (match_operand:DF 2 "register_operand" "f"))
6480 (match_operand:DF 3 "register_operand" "f")))]
6481 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6482 "fmpyfadd,dbl %1,%2,%3,%0"
6483 [(set_attr "type" "fpmuldbl")
6484 (set_attr "length" "4")])
6487 [(set (match_operand:DF 0 "register_operand" "=f")
6488 (plus:DF (match_operand:DF 1 "register_operand" "f")
6489 (mult:DF (match_operand:DF 2 "register_operand" "f")
6490 (match_operand:DF 3 "register_operand" "f"))))]
6491 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6492 "fmpyfadd,dbl %2,%3,%1,%0"
6493 [(set_attr "type" "fpmuldbl")
6494 (set_attr "length" "4")])
6497 [(set (match_operand:SF 0 "register_operand" "=f")
6498 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6499 (match_operand:SF 2 "register_operand" "f"))
6500 (match_operand:SF 3 "register_operand" "f")))]
6501 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6502 "fmpyfadd,sgl %1,%2,%3,%0"
6503 [(set_attr "type" "fpmulsgl")
6504 (set_attr "length" "4")])
6507 [(set (match_operand:SF 0 "register_operand" "=f")
6508 (plus:SF (match_operand:SF 1 "register_operand" "f")
6509 (mult:SF (match_operand:SF 2 "register_operand" "f")
6510 (match_operand:SF 3 "register_operand" "f"))))]
6511 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6512 "fmpyfadd,sgl %2,%3,%1,%0"
6513 [(set_attr "type" "fpmulsgl")
6514 (set_attr "length" "4")])
6516 ; fmpynfadd patterns
6518 [(set (match_operand:DF 0 "register_operand" "=f")
6519 (minus:DF (match_operand:DF 1 "register_operand" "f")
6520 (mult:DF (match_operand:DF 2 "register_operand" "f")
6521 (match_operand:DF 3 "register_operand" "f"))))]
6522 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6523 "fmpynfadd,dbl %2,%3,%1,%0"
6524 [(set_attr "type" "fpmuldbl")
6525 (set_attr "length" "4")])
6528 [(set (match_operand:SF 0 "register_operand" "=f")
6529 (minus:SF (match_operand:SF 1 "register_operand" "f")
6530 (mult:SF (match_operand:SF 2 "register_operand" "f")
6531 (match_operand:SF 3 "register_operand" "f"))))]
6532 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6533 "fmpynfadd,sgl %2,%3,%1,%0"
6534 [(set_attr "type" "fpmulsgl")
6535 (set_attr "length" "4")])
6539 [(set (match_operand:DF 0 "register_operand" "=f")
6540 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
6541 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6543 [(set_attr "type" "fpalu")
6544 (set_attr "length" "4")])
6547 [(set (match_operand:SF 0 "register_operand" "=f")
6548 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
6549 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
6551 [(set_attr "type" "fpalu")
6552 (set_attr "length" "4")])
6554 ;; Generating a fused multiply sequence is a win for this case as it will
6555 ;; reduce the latency for the fused case without impacting the plain
6558 ;; Similar possibilities exist for fnegabs, shadd and other insns which
6559 ;; perform two operations with the result of the first feeding the second.
6561 [(set (match_operand:DF 0 "register_operand" "=f")
6562 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6563 (match_operand:DF 2 "register_operand" "f"))
6564 (match_operand:DF 3 "register_operand" "f")))
6565 (set (match_operand:DF 4 "register_operand" "=&f")
6566 (mult:DF (match_dup 1) (match_dup 2)))]
6567 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6568 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6569 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6571 [(set_attr "type" "fpmuldbl")
6572 (set_attr "length" "8")])
6574 ;; We want to split this up during scheduling since we want both insns
6575 ;; to schedule independently.
6577 [(set (match_operand:DF 0 "register_operand" "")
6578 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6579 (match_operand:DF 2 "register_operand" ""))
6580 (match_operand:DF 3 "register_operand" "")))
6581 (set (match_operand:DF 4 "register_operand" "")
6582 (mult:DF (match_dup 1) (match_dup 2)))]
6583 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6584 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6585 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
6590 [(set (match_operand:SF 0 "register_operand" "=f")
6591 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6592 (match_operand:SF 2 "register_operand" "f"))
6593 (match_operand:SF 3 "register_operand" "f")))
6594 (set (match_operand:SF 4 "register_operand" "=&f")
6595 (mult:SF (match_dup 1) (match_dup 2)))]
6596 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6597 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6598 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6600 [(set_attr "type" "fpmuldbl")
6601 (set_attr "length" "8")])
6603 ;; We want to split this up during scheduling since we want both insns
6604 ;; to schedule independently.
6606 [(set (match_operand:SF 0 "register_operand" "")
6607 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6608 (match_operand:SF 2 "register_operand" ""))
6609 (match_operand:SF 3 "register_operand" "")))
6610 (set (match_operand:SF 4 "register_operand" "")
6611 (mult:SF (match_dup 1) (match_dup 2)))]
6612 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6613 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6614 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
6618 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
6621 [(set (match_operand:DF 0 "register_operand" "=f")
6622 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6623 (match_operand:DF 2 "register_operand" "f"))))]
6624 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6625 "fmpynfadd,dbl %1,%2,%%fr0,%0"
6626 [(set_attr "type" "fpmuldbl")
6627 (set_attr "length" "4")])
6630 [(set (match_operand:SF 0 "register_operand" "=f")
6631 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6632 (match_operand:SF 2 "register_operand" "f"))))]
6633 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6634 "fmpynfadd,sgl %1,%2,%%fr0,%0"
6635 [(set_attr "type" "fpmuldbl")
6636 (set_attr "length" "4")])
6639 [(set (match_operand:DF 0 "register_operand" "=f")
6640 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6641 (match_operand:DF 2 "register_operand" "f"))))
6642 (set (match_operand:DF 3 "register_operand" "=&f")
6643 (mult:DF (match_dup 1) (match_dup 2)))]
6644 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6645 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6646 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6648 [(set_attr "type" "fpmuldbl")
6649 (set_attr "length" "8")])
6652 [(set (match_operand:DF 0 "register_operand" "")
6653 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6654 (match_operand:DF 2 "register_operand" ""))))
6655 (set (match_operand:DF 3 "register_operand" "")
6656 (mult:DF (match_dup 1) (match_dup 2)))]
6657 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6658 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6659 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6663 [(set (match_operand:SF 0 "register_operand" "=f")
6664 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6665 (match_operand:SF 2 "register_operand" "f"))))
6666 (set (match_operand:SF 3 "register_operand" "=&f")
6667 (mult:SF (match_dup 1) (match_dup 2)))]
6668 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6669 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6670 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6672 [(set_attr "type" "fpmuldbl")
6673 (set_attr "length" "8")])
6676 [(set (match_operand:SF 0 "register_operand" "")
6677 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6678 (match_operand:SF 2 "register_operand" ""))))
6679 (set (match_operand:SF 3 "register_operand" "")
6680 (mult:SF (match_dup 1) (match_dup 2)))]
6681 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6682 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6683 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6686 ;; Now fused multiplies with the result of the multiply negated.
6688 [(set (match_operand:DF 0 "register_operand" "=f")
6689 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6690 (match_operand:DF 2 "register_operand" "f")))
6691 (match_operand:DF 3 "register_operand" "f")))]
6692 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6693 "fmpynfadd,dbl %1,%2,%3,%0"
6694 [(set_attr "type" "fpmuldbl")
6695 (set_attr "length" "4")])
6698 [(set (match_operand:SF 0 "register_operand" "=f")
6699 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6700 (match_operand:SF 2 "register_operand" "f")))
6701 (match_operand:SF 3 "register_operand" "f")))]
6702 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6703 "fmpynfadd,sgl %1,%2,%3,%0"
6704 [(set_attr "type" "fpmuldbl")
6705 (set_attr "length" "4")])
6708 [(set (match_operand:DF 0 "register_operand" "=f")
6709 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6710 (match_operand:DF 2 "register_operand" "f")))
6711 (match_operand:DF 3 "register_operand" "f")))
6712 (set (match_operand:DF 4 "register_operand" "=&f")
6713 (mult:DF (match_dup 1) (match_dup 2)))]
6714 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6715 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6716 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6718 [(set_attr "type" "fpmuldbl")
6719 (set_attr "length" "8")])
6722 [(set (match_operand:DF 0 "register_operand" "")
6723 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6724 (match_operand:DF 2 "register_operand" "")))
6725 (match_operand:DF 3 "register_operand" "")))
6726 (set (match_operand:DF 4 "register_operand" "")
6727 (mult:DF (match_dup 1) (match_dup 2)))]
6728 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6729 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6730 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6735 [(set (match_operand:SF 0 "register_operand" "=f")
6736 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6737 (match_operand:SF 2 "register_operand" "f")))
6738 (match_operand:SF 3 "register_operand" "f")))
6739 (set (match_operand:SF 4 "register_operand" "=&f")
6740 (mult:SF (match_dup 1) (match_dup 2)))]
6741 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6742 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6743 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6745 [(set_attr "type" "fpmuldbl")
6746 (set_attr "length" "8")])
6749 [(set (match_operand:SF 0 "register_operand" "")
6750 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6751 (match_operand:SF 2 "register_operand" "")))
6752 (match_operand:SF 3 "register_operand" "")))
6753 (set (match_operand:SF 4 "register_operand" "")
6754 (mult:SF (match_dup 1) (match_dup 2)))]
6755 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6756 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6757 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6762 [(set (match_operand:DF 0 "register_operand" "=f")
6763 (minus:DF (match_operand:DF 3 "register_operand" "f")
6764 (mult:DF (match_operand:DF 1 "register_operand" "f")
6765 (match_operand:DF 2 "register_operand" "f"))))
6766 (set (match_operand:DF 4 "register_operand" "=&f")
6767 (mult:DF (match_dup 1) (match_dup 2)))]
6768 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6769 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6770 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6772 [(set_attr "type" "fpmuldbl")
6773 (set_attr "length" "8")])
6776 [(set (match_operand:DF 0 "register_operand" "")
6777 (minus:DF (match_operand:DF 3 "register_operand" "")
6778 (mult:DF (match_operand:DF 1 "register_operand" "")
6779 (match_operand:DF 2 "register_operand" ""))))
6780 (set (match_operand:DF 4 "register_operand" "")
6781 (mult:DF (match_dup 1) (match_dup 2)))]
6782 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6783 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6784 (set (match_dup 0) (minus:DF (match_dup 3)
6785 (mult:DF (match_dup 1) (match_dup 2))))]
6789 [(set (match_operand:SF 0 "register_operand" "=f")
6790 (minus:SF (match_operand:SF 3 "register_operand" "f")
6791 (mult:SF (match_operand:SF 1 "register_operand" "f")
6792 (match_operand:SF 2 "register_operand" "f"))))
6793 (set (match_operand:SF 4 "register_operand" "=&f")
6794 (mult:SF (match_dup 1) (match_dup 2)))]
6795 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6796 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6797 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6799 [(set_attr "type" "fpmuldbl")
6800 (set_attr "length" "8")])
6803 [(set (match_operand:SF 0 "register_operand" "")
6804 (minus:SF (match_operand:SF 3 "register_operand" "")
6805 (mult:SF (match_operand:SF 1 "register_operand" "")
6806 (match_operand:SF 2 "register_operand" ""))))
6807 (set (match_operand:SF 4 "register_operand" "")
6808 (mult:SF (match_dup 1) (match_dup 2)))]
6809 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6810 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6811 (set (match_dup 0) (minus:SF (match_dup 3)
6812 (mult:SF (match_dup 1) (match_dup 2))))]
6816 [(set (match_operand:DF 0 "register_operand" "=f")
6817 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6818 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6819 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6820 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6822 [(set_attr "type" "fpalu")
6823 (set_attr "length" "8")])
6826 [(set (match_operand:DF 0 "register_operand" "")
6827 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6828 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6829 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6830 [(set (match_dup 2) (abs:DF (match_dup 1)))
6831 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6835 [(set (match_operand:SF 0 "register_operand" "=f")
6836 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6837 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6838 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6839 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6841 [(set_attr "type" "fpalu")
6842 (set_attr "length" "8")])
6845 [(set (match_operand:SF 0 "register_operand" "")
6846 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6847 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6848 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6849 [(set (match_dup 2) (abs:SF (match_dup 1)))
6850 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6853 ;;- Shift instructions
6855 ;; Optimized special case of shifting.
6858 [(set (match_operand:SI 0 "register_operand" "=r")
6859 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6863 [(set_attr "type" "load")
6864 (set_attr "length" "4")])
6867 [(set (match_operand:SI 0 "register_operand" "=r")
6868 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6872 [(set_attr "type" "load")
6873 (set_attr "length" "4")])
6876 [(set (match_operand:SI 0 "register_operand" "=r")
6877 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6878 (match_operand:SI 3 "shadd_operand" ""))
6879 (match_operand:SI 1 "register_operand" "r")))]
6881 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6882 [(set_attr "type" "binary")
6883 (set_attr "length" "4")])
6886 [(set (match_operand:DI 0 "register_operand" "=r")
6887 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6888 (match_operand:DI 3 "shadd_operand" ""))
6889 (match_operand:DI 1 "register_operand" "r")))]
6891 "shladd,l %2,%O3,%1,%0"
6892 [(set_attr "type" "binary")
6893 (set_attr "length" "4")])
6895 (define_expand "ashlsi3"
6896 [(set (match_operand:SI 0 "register_operand" "")
6897 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6898 (match_operand:SI 2 "arith32_operand" "")))]
6902 if (GET_CODE (operands[2]) != CONST_INT)
6904 rtx temp = gen_reg_rtx (SImode);
6905 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6906 if (GET_CODE (operands[1]) == CONST_INT)
6907 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6909 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6912 /* Make sure both inputs are not constants,
6913 there are no patterns for that. */
6914 operands[1] = force_reg (SImode, operands[1]);
6918 [(set (match_operand:SI 0 "register_operand" "=r")
6919 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6920 (match_operand:SI 2 "const_int_operand" "n")))]
6922 "{zdep|depw,z} %1,%P2,%L2,%0"
6923 [(set_attr "type" "shift")
6924 (set_attr "length" "4")])
6926 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6927 ; Doing it like this makes slightly better code since reload can
6928 ; replace a register with a known value in range -16..15 with a
6929 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6930 ; but since we have no more CONST_OK... characters, that is not
6932 (define_insn "zvdep32"
6933 [(set (match_operand:SI 0 "register_operand" "=r,r")
6934 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6935 (minus:SI (const_int 31)
6936 (match_operand:SI 2 "register_operand" "q,q"))))]
6939 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6940 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6941 [(set_attr "type" "shift,shift")
6942 (set_attr "length" "4,4")])
6944 (define_insn "zvdep_imm32"
6945 [(set (match_operand:SI 0 "register_operand" "=r")
6946 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6947 (minus:SI (const_int 31)
6948 (match_operand:SI 2 "register_operand" "q"))))]
6952 int x = INTVAL (operands[1]);
6953 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6954 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6955 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6957 [(set_attr "type" "shift")
6958 (set_attr "length" "4")])
6960 (define_insn "vdepi_ior"
6961 [(set (match_operand:SI 0 "register_operand" "=r")
6962 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6963 (minus:SI (const_int 31)
6964 (match_operand:SI 2 "register_operand" "q")))
6965 (match_operand:SI 3 "register_operand" "0")))]
6966 ; accept ...0001...1, can this be generalized?
6967 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6970 int x = INTVAL (operands[1]);
6971 operands[2] = GEN_INT (exact_log2 (x + 1));
6972 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6974 [(set_attr "type" "shift")
6975 (set_attr "length" "4")])
6977 (define_insn "vdepi_and"
6978 [(set (match_operand:SI 0 "register_operand" "=r")
6979 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6980 (minus:SI (const_int 31)
6981 (match_operand:SI 2 "register_operand" "q")))
6982 (match_operand:SI 3 "register_operand" "0")))]
6983 ; this can be generalized...!
6984 "INTVAL (operands[1]) == -2"
6987 int x = INTVAL (operands[1]);
6988 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6989 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6991 [(set_attr "type" "shift")
6992 (set_attr "length" "4")])
6994 (define_expand "ashldi3"
6995 [(set (match_operand:DI 0 "register_operand" "")
6996 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6997 (match_operand:DI 2 "arith32_operand" "")))]
7001 if (GET_CODE (operands[2]) != CONST_INT)
7003 rtx temp = gen_reg_rtx (DImode);
7004 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7005 if (GET_CODE (operands[1]) == CONST_INT)
7006 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
7008 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
7011 /* Make sure both inputs are not constants,
7012 there are no patterns for that. */
7013 operands[1] = force_reg (DImode, operands[1]);
7017 [(set (match_operand:DI 0 "register_operand" "=r")
7018 (ashift:DI (match_operand:DI 1 "register_operand" "r")
7019 (match_operand:DI 2 "const_int_operand" "n")))]
7021 "depd,z %1,%p2,%Q2,%0"
7022 [(set_attr "type" "shift")
7023 (set_attr "length" "4")])
7025 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
7026 ; Doing it like this makes slightly better code since reload can
7027 ; replace a register with a known value in range -16..15 with a
7028 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
7029 ; but since we have no more CONST_OK... characters, that is not
7031 (define_insn "zvdep64"
7032 [(set (match_operand:DI 0 "register_operand" "=r,r")
7033 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
7034 (minus:DI (const_int 63)
7035 (match_operand:DI 2 "register_operand" "q,q"))))]
7038 depd,z %1,%%sar,64,%0
7039 depdi,z %1,%%sar,64,%0"
7040 [(set_attr "type" "shift,shift")
7041 (set_attr "length" "4,4")])
7043 (define_insn "zvdep_imm64"
7044 [(set (match_operand:DI 0 "register_operand" "=r")
7045 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
7046 (minus:DI (const_int 63)
7047 (match_operand:DI 2 "register_operand" "q"))))]
7051 int x = INTVAL (operands[1]);
7052 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
7053 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
7054 return \"depdi,z %1,%%sar,%2,%0\";
7056 [(set_attr "type" "shift")
7057 (set_attr "length" "4")])
7060 [(set (match_operand:DI 0 "register_operand" "=r")
7061 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
7062 (minus:DI (const_int 63)
7063 (match_operand:DI 2 "register_operand" "q")))
7064 (match_operand:DI 3 "register_operand" "0")))]
7065 ; accept ...0001...1, can this be generalized?
7066 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
7069 int x = INTVAL (operands[1]);
7070 operands[2] = GEN_INT (exact_log2 (x + 1));
7071 return \"depdi -1,%%sar,%2,%0\";
7073 [(set_attr "type" "shift")
7074 (set_attr "length" "4")])
7077 [(set (match_operand:DI 0 "register_operand" "=r")
7078 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
7079 (minus:DI (const_int 63)
7080 (match_operand:DI 2 "register_operand" "q")))
7081 (match_operand:DI 3 "register_operand" "0")))]
7082 ; this can be generalized...!
7083 "TARGET_64BIT && INTVAL (operands[1]) == -2"
7086 int x = INTVAL (operands[1]);
7087 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
7088 return \"depdi 0,%%sar,%2,%0\";
7090 [(set_attr "type" "shift")
7091 (set_attr "length" "4")])
7093 (define_expand "ashrsi3"
7094 [(set (match_operand:SI 0 "register_operand" "")
7095 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
7096 (match_operand:SI 2 "arith32_operand" "")))]
7100 if (GET_CODE (operands[2]) != CONST_INT)
7102 rtx temp = gen_reg_rtx (SImode);
7103 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
7104 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
7110 [(set (match_operand:SI 0 "register_operand" "=r")
7111 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7112 (match_operand:SI 2 "const_int_operand" "n")))]
7114 "{extrs|extrw,s} %1,%P2,%L2,%0"
7115 [(set_attr "type" "shift")
7116 (set_attr "length" "4")])
7118 (define_insn "vextrs32"
7119 [(set (match_operand:SI 0 "register_operand" "=r")
7120 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
7121 (minus:SI (const_int 31)
7122 (match_operand:SI 2 "register_operand" "q"))))]
7124 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
7125 [(set_attr "type" "shift")
7126 (set_attr "length" "4")])
7128 (define_expand "ashrdi3"
7129 [(set (match_operand:DI 0 "register_operand" "")
7130 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
7131 (match_operand:DI 2 "arith32_operand" "")))]
7135 if (GET_CODE (operands[2]) != CONST_INT)
7137 rtx temp = gen_reg_rtx (DImode);
7138 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
7139 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
7145 [(set (match_operand:DI 0 "register_operand" "=r")
7146 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7147 (match_operand:DI 2 "const_int_operand" "n")))]
7149 "extrd,s %1,%p2,%Q2,%0"
7150 [(set_attr "type" "shift")
7151 (set_attr "length" "4")])
7153 (define_insn "vextrs64"
7154 [(set (match_operand:DI 0 "register_operand" "=r")
7155 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
7156 (minus:DI (const_int 63)
7157 (match_operand:DI 2 "register_operand" "q"))))]
7159 "extrd,s %1,%%sar,64,%0"
7160 [(set_attr "type" "shift")
7161 (set_attr "length" "4")])
7163 (define_insn "lshrsi3"
7164 [(set (match_operand:SI 0 "register_operand" "=r,r")
7165 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
7166 (match_operand:SI 2 "arith32_operand" "q,n")))]
7169 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
7170 {extru|extrw,u} %1,%P2,%L2,%0"
7171 [(set_attr "type" "shift")
7172 (set_attr "length" "4")])
7174 (define_insn "lshrdi3"
7175 [(set (match_operand:DI 0 "register_operand" "=r,r")
7176 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
7177 (match_operand:DI 2 "arith32_operand" "q,n")))]
7180 shrpd %%r0,%1,%%sar,%0
7181 extrd,u %1,%p2,%Q2,%0"
7182 [(set_attr "type" "shift")
7183 (set_attr "length" "4")])
7185 (define_insn "rotrsi3"
7186 [(set (match_operand:SI 0 "register_operand" "=r,r")
7187 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
7188 (match_operand:SI 2 "arith32_operand" "q,n")))]
7192 if (GET_CODE (operands[2]) == CONST_INT)
7194 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
7195 return \"{shd|shrpw} %1,%1,%2,%0\";
7198 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
7200 [(set_attr "type" "shift")
7201 (set_attr "length" "4")])
7203 (define_expand "rotlsi3"
7204 [(set (match_operand:SI 0 "register_operand" "")
7205 (rotate:SI (match_operand:SI 1 "register_operand" "")
7206 (match_operand:SI 2 "arith32_operand" "")))]
7210 if (GET_CODE (operands[2]) != CONST_INT)
7212 rtx temp = gen_reg_rtx (SImode);
7213 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
7214 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
7217 /* Else expand normally. */
7221 [(set (match_operand:SI 0 "register_operand" "=r")
7222 (rotate:SI (match_operand:SI 1 "register_operand" "r")
7223 (match_operand:SI 2 "const_int_operand" "n")))]
7227 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
7228 return \"{shd|shrpw} %1,%1,%2,%0\";
7230 [(set_attr "type" "shift")
7231 (set_attr "length" "4")])
7234 [(set (match_operand:SI 0 "register_operand" "=r")
7235 (match_operator:SI 5 "plus_xor_ior_operator"
7236 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
7237 (match_operand:SI 3 "const_int_operand" "n"))
7238 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7239 (match_operand:SI 4 "const_int_operand" "n"))]))]
7240 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7241 "{shd|shrpw} %1,%2,%4,%0"
7242 [(set_attr "type" "shift")
7243 (set_attr "length" "4")])
7246 [(set (match_operand:SI 0 "register_operand" "=r")
7247 (match_operator:SI 5 "plus_xor_ior_operator"
7248 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
7249 (match_operand:SI 4 "const_int_operand" "n"))
7250 (ashift:SI (match_operand:SI 1 "register_operand" "r")
7251 (match_operand:SI 3 "const_int_operand" "n"))]))]
7252 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
7253 "{shd|shrpw} %1,%2,%4,%0"
7254 [(set_attr "type" "shift")
7255 (set_attr "length" "4")])
7258 [(set (match_operand:SI 0 "register_operand" "=r")
7259 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
7260 (match_operand:SI 2 "const_int_operand" ""))
7261 (match_operand:SI 3 "const_int_operand" "")))]
7262 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
7265 int cnt = INTVAL (operands[2]) & 31;
7266 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
7267 operands[2] = GEN_INT (31 - cnt);
7268 return \"{zdep|depw,z} %1,%2,%3,%0\";
7270 [(set_attr "type" "shift")
7271 (set_attr "length" "4")])
7273 ;; Unconditional and other jump instructions.
7275 ;; This can only be used in a leaf function, so we do
7276 ;; not need to use the PIC register when generating PIC code.
7277 (define_insn "return"
7281 "hppa_can_use_return_insn_p ()"
7285 return \"bve%* (%%r2)\";
7286 return \"bv%* %%r0(%%r2)\";
7288 [(set_attr "type" "branch")
7289 (set_attr "length" "4")])
7291 ;; Emit a different pattern for functions which have non-trivial
7292 ;; epilogues so as not to confuse jump and reorg.
7293 (define_insn "return_internal"
7301 return \"bve%* (%%r2)\";
7302 return \"bv%* %%r0(%%r2)\";
7304 [(set_attr "type" "branch")
7305 (set_attr "length" "4")])
7307 ;; This is used for eh returns which bypass the return stub.
7308 (define_insn "return_external_pic"
7310 (clobber (reg:SI 1))
7312 "!TARGET_NO_SPACE_REGS
7314 && flag_pic && current_function_calls_eh_return"
7315 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
7316 [(set_attr "type" "branch")
7317 (set_attr "length" "12")])
7319 (define_expand "prologue"
7322 "hppa_expand_prologue ();DONE;")
7324 (define_expand "sibcall_epilogue"
7329 hppa_expand_epilogue ();
7333 (define_expand "epilogue"
7338 /* Try to use the trivial return first. Else use the full
7340 if (hppa_can_use_return_insn_p ())
7341 emit_jump_insn (gen_return ());
7346 hppa_expand_epilogue ();
7348 /* EH returns bypass the normal return stub. Thus, we must do an
7349 interspace branch to return from functions that call eh_return.
7350 This is only a problem for returns from shared code on ports
7351 using space registers. */
7352 if (!TARGET_NO_SPACE_REGS
7354 && flag_pic && current_function_calls_eh_return)
7355 x = gen_return_external_pic ();
7357 x = gen_return_internal ();
7364 ; Used by hppa_profile_hook to load the starting address of the current
7365 ; function; operand 1 contains the address of the label in operand 3
7366 (define_insn "load_offset_label_address"
7367 [(set (match_operand:SI 0 "register_operand" "=r")
7368 (plus:SI (match_operand:SI 1 "register_operand" "r")
7369 (minus:SI (match_operand:SI 2 "" "")
7370 (label_ref:SI (match_operand 3 "" "")))))]
7373 [(set_attr "type" "multi")
7374 (set_attr "length" "4")])
7376 ; Output a code label and load its address.
7377 (define_insn "lcla1"
7378 [(set (match_operand:SI 0 "register_operand" "=r")
7379 (label_ref:SI (match_operand 1 "" "")))
7384 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
7385 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7386 CODE_LABEL_NUMBER (operands[1]));
7389 [(set_attr "type" "multi")
7390 (set_attr "length" "8")])
7392 (define_insn "lcla2"
7393 [(set (match_operand:SI 0 "register_operand" "=r")
7394 (label_ref:SI (match_operand 1 "" "")))
7399 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
7400 CODE_LABEL_NUMBER (operands[1]));
7403 [(set_attr "type" "move")
7404 (set_attr "length" "4")])
7406 (define_insn "blockage"
7407 [(unspec_volatile [(const_int 2)] UNSPECV_BLOCKAGE)]
7410 [(set_attr "length" "0")])
7413 [(set (pc) (label_ref (match_operand 0 "" "")))]
7417 /* An unconditional branch which can reach its target. */
7418 if (get_attr_length (insn) < 16)
7421 return output_lbranch (operands[0], insn, 1);
7423 [(set_attr "type" "uncond_branch")
7424 (set_attr "pa_combine_type" "uncond_branch")
7425 (set (attr "length")
7426 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
7427 (if_then_else (lt (abs (minus (match_dup 0)
7428 (plus (pc) (const_int 8))))
7429 (const_int MAX_12BIT_OFFSET))
7432 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
7433 (const_int MAX_17BIT_OFFSET))
7435 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
7437 (eq (symbol_ref "flag_pic") (const_int 0))
7441 ;;; Hope this is only within a function...
7442 (define_insn "indirect_jump"
7443 [(set (pc) (match_operand 0 "register_operand" "r"))]
7444 "GET_MODE (operands[0]) == word_mode"
7446 [(set_attr "type" "branch")
7447 (set_attr "length" "4")])
7449 ;;; An indirect jump can be optimized to a direct jump. GAS for the
7450 ;;; SOM target doesn't allow branching to a label inside a function.
7451 ;;; We also don't correctly compute branch distances for labels
7452 ;;; outside the current function. Thus, we use an indirect jump can't
7453 ;;; be optimized to a direct jump for all targets. We assume that
7454 ;;; the branch target is in the same space (i.e., nested function
7455 ;;; jumping to a label in an outer function in the same translation
7457 (define_expand "nonlocal_goto"
7458 [(use (match_operand 0 "general_operand" ""))
7459 (use (match_operand 1 "general_operand" ""))
7460 (use (match_operand 2 "general_operand" ""))
7461 (use (match_operand 3 "general_operand" ""))]
7464 rtx lab = operands[1];
7465 rtx stack = operands[2];
7466 rtx fp = operands[3];
7468 lab = copy_to_reg (lab);
7470 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7471 gen_rtx_MEM (BLKmode,
7472 gen_rtx_SCRATCH (VOIDmode))));
7473 emit_insn (gen_rtx_CLOBBER (VOIDmode,
7474 gen_rtx_MEM (BLKmode,
7475 hard_frame_pointer_rtx)));
7477 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
7478 instead of the hard_frame_pointer_rtx in the save area. As a
7479 result, an extra instruction is needed to adjust for the offset
7480 of the virtual stack variables and the frame pointer. */
7481 if (GET_CODE (fp) != REG)
7482 fp = force_reg (Pmode, fp);
7483 emit_move_insn (virtual_stack_vars_rtx, fp);
7485 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7487 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7488 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7490 /* Nonlocal goto jumps are only used between functions in the same
7491 translation unit. Thus, we can avoid the extra overhead of an
7493 emit_jump_insn (gen_indirect_goto (lab));
7498 (define_insn "indirect_goto"
7499 [(unspec [(match_operand 0 "register_operand" "=r")] UNSPEC_GOTO)]
7500 "GET_MODE (operands[0]) == word_mode"
7502 [(set_attr "type" "branch")
7503 (set_attr "length" "4")])
7505 ;;; This jump is used in branch tables where the insn length is fixed.
7506 ;;; The length of this insn is adjusted if the delay slot is not filled.
7507 (define_insn "short_jump"
7508 [(set (pc) (label_ref (match_operand 0 "" "")))
7512 [(set_attr "type" "btable_branch")
7513 (set_attr "length" "4")])
7515 ;; Subroutines of "casesi".
7516 ;; operand 0 is index
7517 ;; operand 1 is the minimum bound
7518 ;; operand 2 is the maximum bound - minimum bound + 1
7519 ;; operand 3 is CODE_LABEL for the table;
7520 ;; operand 4 is the CODE_LABEL to go to if index out of range.
7522 (define_expand "casesi"
7523 [(match_operand:SI 0 "general_operand" "")
7524 (match_operand:SI 1 "const_int_operand" "")
7525 (match_operand:SI 2 "const_int_operand" "")
7526 (match_operand 3 "" "")
7527 (match_operand 4 "" "")]
7531 if (GET_CODE (operands[0]) != REG)
7532 operands[0] = force_reg (SImode, operands[0]);
7534 if (operands[1] != const0_rtx)
7536 rtx index = gen_reg_rtx (SImode);
7538 operands[1] = GEN_INT (-INTVAL (operands[1]));
7539 if (!INT_14_BITS (operands[1]))
7540 operands[1] = force_reg (SImode, operands[1]);
7541 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
7542 operands[0] = index;
7545 /* In 64bit mode we must make sure to wipe the upper bits of the register
7546 just in case the addition overflowed or we had random bits in the
7547 high part of the register. */
7550 rtx index = gen_reg_rtx (DImode);
7552 emit_insn (gen_extendsidi2 (index, operands[0]));
7553 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
7556 if (!INT_5_BITS (operands[2]))
7557 operands[2] = force_reg (SImode, operands[2]);
7559 /* This branch prevents us finding an insn for the delay slot of the
7560 following vectored branch. It might be possible to use the delay
7561 slot if an index value of -1 was used to transfer to the out-of-range
7562 label. In order to do this, we would have to output the -1 vector
7563 element after the delay insn. The casesi output code would have to
7564 check if the casesi insn is in a delay branch sequence and output
7565 the delay insn if one is found. If this was done, then it might
7566 then be worthwhile to split the casesi patterns to improve scheduling.
7567 However, it's not clear that all this extra complexity is worth
7569 emit_insn (gen_cmpsi (operands[0], operands[2]));
7570 emit_jump_insn (gen_bgtu (operands[4]));
7572 if (TARGET_BIG_SWITCH)
7576 rtx tmp1 = gen_reg_rtx (DImode);
7577 rtx tmp2 = gen_reg_rtx (DImode);
7579 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
7584 rtx tmp1 = gen_reg_rtx (SImode);
7588 rtx tmp2 = gen_reg_rtx (SImode);
7590 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
7594 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
7598 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
7602 ;;; The rtl for this pattern doesn't accurately describe what the insn
7603 ;;; actually does, particularly when case-vector elements are exploded
7604 ;;; in pa_reorg. However, the initial SET in these patterns must show
7605 ;;; the connection of the insn to the following jump table.
7606 (define_insn "casesi0"
7607 [(set (pc) (mem:SI (plus:SI
7608 (mult:SI (match_operand:SI 0 "register_operand" "r")
7610 (label_ref (match_operand 1 "" "")))))]
7612 "blr,n %0,%%r0\;nop"
7613 [(set_attr "type" "multi")
7614 (set_attr "length" "8")])
7616 ;;; 32-bit code, absolute branch table.
7617 (define_insn "casesi32"
7618 [(set (pc) (mem:SI (plus:SI
7619 (mult:SI (match_operand:SI 0 "register_operand" "r")
7621 (label_ref (match_operand 1 "" "")))))
7622 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
7623 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7624 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
7625 [(set_attr "type" "multi")
7626 (set_attr "length" "16")])
7628 ;;; 32-bit code, relative branch table.
7629 (define_insn "casesi32p"
7630 [(set (pc) (mem:SI (plus:SI
7631 (mult:SI (match_operand:SI 0 "register_operand" "r")
7633 (label_ref (match_operand 1 "" "")))))
7634 (clobber (match_operand:SI 2 "register_operand" "=&a"))
7635 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
7636 "!TARGET_64BIT && TARGET_BIG_SWITCH"
7637 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
7638 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
7639 [(set_attr "type" "multi")
7640 (set (attr "length")
7641 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
7645 ;;; 64-bit code, 32-bit relative branch table.
7646 (define_insn "casesi64p"
7647 [(set (pc) (mem:DI (plus:DI
7648 (mult:DI (sign_extend:DI
7649 (match_operand:SI 0 "register_operand" "r"))
7651 (label_ref (match_operand 1 "" "")))))
7652 (clobber (match_operand:DI 2 "register_operand" "=&r"))
7653 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
7654 "TARGET_64BIT && TARGET_BIG_SWITCH"
7655 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
7656 add,l %2,%3,%3\;bv,n %%r0(%3)"
7657 [(set_attr "type" "multi")
7658 (set_attr "length" "24")])
7662 ;;- jump to subroutine
7664 (define_expand "call"
7665 [(parallel [(call (match_operand:SI 0 "" "")
7666 (match_operand 1 "" ""))
7667 (clobber (reg:SI 2))])]
7672 rtx nb = operands[1];
7674 if (TARGET_PORTABLE_RUNTIME)
7675 op = force_reg (SImode, XEXP (operands[0], 0));
7677 op = XEXP (operands[0], 0);
7681 if (!virtuals_instantiated)
7682 emit_move_insn (arg_pointer_rtx,
7683 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7687 /* The loop pass can generate new libcalls after the virtual
7688 registers are instantiated when fpregs are disabled because
7689 the only method that we have for doing DImode multiplication
7690 is with a libcall. This could be trouble if we haven't
7691 allocated enough space for the outgoing arguments. */
7692 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
7694 emit_move_insn (arg_pointer_rtx,
7695 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7696 GEN_INT (STACK_POINTER_OFFSET + 64)));
7700 /* Use two different patterns for calls to explicitly named functions
7701 and calls through function pointers. This is necessary as these two
7702 types of calls use different calling conventions, and CSE might try
7703 to change the named call into an indirect call in some cases (using
7704 two patterns keeps CSE from performing this optimization).
7706 We now use even more call patterns as there was a subtle bug in
7707 attempting to restore the pic register after a call using a simple
7708 move insn. During reload, a instruction involving a pseudo register
7709 with no explicit dependence on the PIC register can be converted
7710 to an equivalent load from memory using the PIC register. If we
7711 emit a simple move to restore the PIC register in the initial rtl
7712 generation, then it can potentially be repositioned during scheduling.
7713 and an instruction that eventually uses the PIC register may end up
7714 between the call and the PIC register restore.
7716 This only worked because there is a post call group of instructions
7717 that are scheduled with the call. These instructions are included
7718 in the same basic block as the call. However, calls can throw in
7719 C++ code and a basic block has to terminate at the call if the call
7720 can throw. This results in the PIC register restore being scheduled
7721 independently from the call. So, we now hide the save and restore
7722 of the PIC register in the call pattern until after reload. Then,
7723 we split the moves out. A small side benefit is that we now don't
7724 need to have a use of the PIC register in the return pattern and
7725 the final save/restore operation is not needed.
7727 I elected to just clobber %r4 in the PIC patterns and use it instead
7728 of trying to force hppa_pic_save_rtx () to a callee saved register.
7729 This might have required a new register class and constraint. It
7730 was also simpler to just handle the restore from a register than a
7734 if (GET_CODE (op) == SYMBOL_REF)
7735 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7738 op = force_reg (word_mode, op);
7739 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7744 if (GET_CODE (op) == SYMBOL_REF)
7747 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7749 call_insn = emit_call_insn (gen_call_symref (op, nb));
7753 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7755 emit_move_insn (tmpreg, force_reg (word_mode, op));
7757 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7759 call_insn = emit_call_insn (gen_call_reg (nb));
7766 ;; We use function calls to set the attribute length of calls and millicode
7767 ;; calls. This is necessary because of the large variety of call sequences.
7768 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7769 ;; we need the same calculation in several places, maintenance becomes a
7772 ;; However, this has a subtle impact on branch shortening. When the
7773 ;; expression used to set the length attribute of an instruction depends
7774 ;; on a relative address (e.g., pc or a branch address), genattrtab
7775 ;; notes that the insn's length is variable, and attempts to determine a
7776 ;; worst-case default length and code to compute an insn's current length.
7778 ;; The use of a function call hides the variable dependence of our calls
7779 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7780 ;; as variable and it only generates code for the default case using our
7781 ;; function call. Because of this, calls and millicode calls have a fixed
7782 ;; length in the branch shortening pass, and some branches will use a longer
7783 ;; code sequence than necessary. However, the length of any given call
7784 ;; will still reflect its final code location and it may be shorter than
7785 ;; the initial length estimate.
7787 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7788 ;; in the set. However, when genattrtab hits a function call in its attempt
7789 ;; to compute the default length, it marks the result as unknown and sets
7790 ;; the default result to MAX_INT ;-( One possible fix that would allow
7791 ;; calls to participate in branch shortening would be to make the call to
7792 ;; insn_default_length a target option. Then, we could massage unknown
7793 ;; results. Another fix might be to change genattrtab so that it just does
7794 ;; the call in the variable case as it already does for the fixed case.
7796 (define_insn "call_symref"
7797 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7798 (match_operand 1 "" "i"))
7799 (clobber (reg:SI 1))
7800 (clobber (reg:SI 2))
7801 (use (const_int 0))]
7802 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7805 output_arg_descriptor (insn);
7806 return output_call (insn, operands[0], 0);
7808 [(set_attr "type" "call")
7809 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7811 (define_insn "call_symref_pic"
7812 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7813 (match_operand 1 "" "i"))
7814 (clobber (reg:SI 1))
7815 (clobber (reg:SI 2))
7816 (clobber (reg:SI 4))
7818 (use (const_int 0))]
7819 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7822 output_arg_descriptor (insn);
7823 return output_call (insn, operands[0], 0);
7825 [(set_attr "type" "call")
7826 (set (attr "length")
7827 (plus (symbol_ref "attr_length_call (insn, 0)")
7828 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7830 ;; Split out the PIC register save and restore after reload. This is
7831 ;; done only if the function returns. As the split is done after reload,
7832 ;; there are some situations in which we unnecessarily save and restore
7833 ;; %r4. This happens when there is a single call and the PIC register
7834 ;; is "dead" after the call. This isn't easy to fix as the usage of
7835 ;; the PIC register isn't completely determined until the reload pass.
7837 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7838 (match_operand 1 "" ""))
7839 (clobber (reg:SI 1))
7840 (clobber (reg:SI 2))
7841 (clobber (reg:SI 4))
7843 (use (const_int 0))])]
7844 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7846 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7847 [(set (reg:SI 4) (reg:SI 19))
7848 (parallel [(call (mem:SI (match_dup 0))
7850 (clobber (reg:SI 1))
7851 (clobber (reg:SI 2))
7853 (use (const_int 0))])
7854 (set (reg:SI 19) (reg:SI 4))]
7857 ;; Remove the clobber of register 4 when optimizing. This has to be
7858 ;; done with a peephole optimization rather than a split because the
7859 ;; split sequence for a call must be longer than one instruction.
7861 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7862 (match_operand 1 "" ""))
7863 (clobber (reg:SI 1))
7864 (clobber (reg:SI 2))
7865 (clobber (reg:SI 4))
7867 (use (const_int 0))])]
7868 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7869 [(parallel [(call (mem:SI (match_dup 0))
7871 (clobber (reg:SI 1))
7872 (clobber (reg:SI 2))
7874 (use (const_int 0))])]
7877 (define_insn "*call_symref_pic_post_reload"
7878 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7879 (match_operand 1 "" "i"))
7880 (clobber (reg:SI 1))
7881 (clobber (reg:SI 2))
7883 (use (const_int 0))]
7884 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7887 output_arg_descriptor (insn);
7888 return output_call (insn, operands[0], 0);
7890 [(set_attr "type" "call")
7891 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7893 ;; This pattern is split if it is necessary to save and restore the
7895 (define_insn "call_symref_64bit"
7896 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7897 (match_operand 1 "" "i"))
7898 (clobber (reg:DI 1))
7899 (clobber (reg:DI 2))
7900 (clobber (reg:DI 4))
7903 (use (const_int 0))]
7907 output_arg_descriptor (insn);
7908 return output_call (insn, operands[0], 0);
7910 [(set_attr "type" "call")
7911 (set (attr "length")
7912 (plus (symbol_ref "attr_length_call (insn, 0)")
7913 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7915 ;; Split out the PIC register save and restore after reload. This is
7916 ;; done only if the function returns. As the split is done after reload,
7917 ;; there are some situations in which we unnecessarily save and restore
7918 ;; %r4. This happens when there is a single call and the PIC register
7919 ;; is "dead" after the call. This isn't easy to fix as the usage of
7920 ;; the PIC register isn't completely determined until the reload pass.
7922 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7923 (match_operand 1 "" ""))
7924 (clobber (reg:DI 1))
7925 (clobber (reg:DI 2))
7926 (clobber (reg:DI 4))
7929 (use (const_int 0))])]
7932 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7933 [(set (reg:DI 4) (reg:DI 27))
7934 (parallel [(call (mem:SI (match_dup 0))
7936 (clobber (reg:DI 1))
7937 (clobber (reg:DI 2))
7940 (use (const_int 0))])
7941 (set (reg:DI 27) (reg:DI 4))]
7944 ;; Remove the clobber of register 4 when optimizing. This has to be
7945 ;; done with a peephole optimization rather than a split because the
7946 ;; split sequence for a call must be longer than one instruction.
7948 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7949 (match_operand 1 "" ""))
7950 (clobber (reg:DI 1))
7951 (clobber (reg:DI 2))
7952 (clobber (reg:DI 4))
7955 (use (const_int 0))])]
7956 "TARGET_64BIT && reload_completed"
7957 [(parallel [(call (mem:SI (match_dup 0))
7959 (clobber (reg:DI 1))
7960 (clobber (reg:DI 2))
7963 (use (const_int 0))])]
7966 (define_insn "*call_symref_64bit_post_reload"
7967 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7968 (match_operand 1 "" "i"))
7969 (clobber (reg:DI 1))
7970 (clobber (reg:DI 2))
7973 (use (const_int 0))]
7977 output_arg_descriptor (insn);
7978 return output_call (insn, operands[0], 0);
7980 [(set_attr "type" "call")
7981 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7983 (define_insn "call_reg"
7984 [(call (mem:SI (reg:SI 22))
7985 (match_operand 0 "" "i"))
7986 (clobber (reg:SI 1))
7987 (clobber (reg:SI 2))
7988 (use (const_int 1))]
7992 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7994 [(set_attr "type" "dyncall")
7995 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7997 ;; This pattern is split if it is necessary to save and restore the
7999 (define_insn "call_reg_pic"
8000 [(call (mem:SI (reg:SI 22))
8001 (match_operand 0 "" "i"))
8002 (clobber (reg:SI 1))
8003 (clobber (reg:SI 2))
8004 (clobber (reg:SI 4))
8006 (use (const_int 1))]
8010 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8012 [(set_attr "type" "dyncall")
8013 (set (attr "length")
8014 (plus (symbol_ref "attr_length_indirect_call (insn)")
8015 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8017 ;; Split out the PIC register save and restore after reload. This is
8018 ;; done only if the function returns. As the split is done after reload,
8019 ;; there are some situations in which we unnecessarily save and restore
8020 ;; %r4. This happens when there is a single call and the PIC register
8021 ;; is "dead" after the call. This isn't easy to fix as the usage of
8022 ;; the PIC register isn't completely determined until the reload pass.
8024 [(parallel [(call (mem:SI (reg:SI 22))
8025 (match_operand 0 "" ""))
8026 (clobber (reg:SI 1))
8027 (clobber (reg:SI 2))
8028 (clobber (reg:SI 4))
8030 (use (const_int 1))])]
8033 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8034 [(set (reg:SI 4) (reg:SI 19))
8035 (parallel [(call (mem:SI (reg:SI 22))
8037 (clobber (reg:SI 1))
8038 (clobber (reg:SI 2))
8040 (use (const_int 1))])
8041 (set (reg:SI 19) (reg:SI 4))]
8044 ;; Remove the clobber of register 4 when optimizing. This has to be
8045 ;; done with a peephole optimization rather than a split because the
8046 ;; split sequence for a call must be longer than one instruction.
8048 [(parallel [(call (mem:SI (reg:SI 22))
8049 (match_operand 0 "" ""))
8050 (clobber (reg:SI 1))
8051 (clobber (reg:SI 2))
8052 (clobber (reg:SI 4))
8054 (use (const_int 1))])]
8055 "!TARGET_64BIT && reload_completed"
8056 [(parallel [(call (mem:SI (reg:SI 22))
8058 (clobber (reg:SI 1))
8059 (clobber (reg:SI 2))
8061 (use (const_int 1))])]
8064 (define_insn "*call_reg_pic_post_reload"
8065 [(call (mem:SI (reg:SI 22))
8066 (match_operand 0 "" "i"))
8067 (clobber (reg:SI 1))
8068 (clobber (reg:SI 2))
8070 (use (const_int 1))]
8074 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8076 [(set_attr "type" "dyncall")
8077 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8079 ;; This pattern is split if it is necessary to save and restore the
8081 (define_insn "call_reg_64bit"
8082 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8083 (match_operand 1 "" "i"))
8084 (clobber (reg:DI 2))
8085 (clobber (reg:DI 4))
8088 (use (const_int 1))]
8092 return output_indirect_call (insn, operands[0]);
8094 [(set_attr "type" "dyncall")
8095 (set (attr "length")
8096 (plus (symbol_ref "attr_length_indirect_call (insn)")
8097 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8099 ;; Split out the PIC register save and restore after reload. This is
8100 ;; done only if the function returns. As the split is done after reload,
8101 ;; there are some situations in which we unnecessarily save and restore
8102 ;; %r4. This happens when there is a single call and the PIC register
8103 ;; is "dead" after the call. This isn't easy to fix as the usage of
8104 ;; the PIC register isn't completely determined until the reload pass.
8106 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8107 (match_operand 1 "" ""))
8108 (clobber (reg:DI 2))
8109 (clobber (reg:DI 4))
8112 (use (const_int 1))])]
8115 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8116 [(set (reg:DI 4) (reg:DI 27))
8117 (parallel [(call (mem:SI (match_dup 0))
8119 (clobber (reg:DI 2))
8122 (use (const_int 1))])
8123 (set (reg:DI 27) (reg:DI 4))]
8126 ;; Remove the clobber of register 4 when optimizing. This has to be
8127 ;; done with a peephole optimization rather than a split because the
8128 ;; split sequence for a call must be longer than one instruction.
8130 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
8131 (match_operand 1 "" ""))
8132 (clobber (reg:DI 2))
8133 (clobber (reg:DI 4))
8136 (use (const_int 1))])]
8137 "TARGET_64BIT && reload_completed"
8138 [(parallel [(call (mem:SI (match_dup 0))
8140 (clobber (reg:DI 2))
8143 (use (const_int 1))])]
8146 (define_insn "*call_reg_64bit_post_reload"
8147 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
8148 (match_operand 1 "" "i"))
8149 (clobber (reg:DI 2))
8152 (use (const_int 1))]
8156 return output_indirect_call (insn, operands[0]);
8158 [(set_attr "type" "dyncall")
8159 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8161 (define_expand "call_value"
8162 [(parallel [(set (match_operand 0 "" "")
8163 (call (match_operand:SI 1 "" "")
8164 (match_operand 2 "" "")))
8165 (clobber (reg:SI 2))])]
8170 rtx dst = operands[0];
8171 rtx nb = operands[2];
8173 if (TARGET_PORTABLE_RUNTIME)
8174 op = force_reg (SImode, XEXP (operands[1], 0));
8176 op = XEXP (operands[1], 0);
8180 if (!virtuals_instantiated)
8181 emit_move_insn (arg_pointer_rtx,
8182 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8186 /* The loop pass can generate new libcalls after the virtual
8187 registers are instantiated when fpregs are disabled because
8188 the only method that we have for doing DImode multiplication
8189 is with a libcall. This could be trouble if we haven't
8190 allocated enough space for the outgoing arguments. */
8191 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8193 emit_move_insn (arg_pointer_rtx,
8194 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8195 GEN_INT (STACK_POINTER_OFFSET + 64)));
8199 /* Use two different patterns for calls to explicitly named functions
8200 and calls through function pointers. This is necessary as these two
8201 types of calls use different calling conventions, and CSE might try
8202 to change the named call into an indirect call in some cases (using
8203 two patterns keeps CSE from performing this optimization).
8205 We now use even more call patterns as there was a subtle bug in
8206 attempting to restore the pic register after a call using a simple
8207 move insn. During reload, a instruction involving a pseudo register
8208 with no explicit dependence on the PIC register can be converted
8209 to an equivalent load from memory using the PIC register. If we
8210 emit a simple move to restore the PIC register in the initial rtl
8211 generation, then it can potentially be repositioned during scheduling.
8212 and an instruction that eventually uses the PIC register may end up
8213 between the call and the PIC register restore.
8215 This only worked because there is a post call group of instructions
8216 that are scheduled with the call. These instructions are included
8217 in the same basic block as the call. However, calls can throw in
8218 C++ code and a basic block has to terminate at the call if the call
8219 can throw. This results in the PIC register restore being scheduled
8220 independently from the call. So, we now hide the save and restore
8221 of the PIC register in the call pattern until after reload. Then,
8222 we split the moves out. A small side benefit is that we now don't
8223 need to have a use of the PIC register in the return pattern and
8224 the final save/restore operation is not needed.
8226 I elected to just clobber %r4 in the PIC patterns and use it instead
8227 of trying to force hppa_pic_save_rtx () to a callee saved register.
8228 This might have required a new register class and constraint. It
8229 was also simpler to just handle the restore from a register than a
8233 if (GET_CODE (op) == SYMBOL_REF)
8234 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
8237 op = force_reg (word_mode, op);
8238 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
8243 if (GET_CODE (op) == SYMBOL_REF)
8246 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
8248 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
8252 rtx tmpreg = gen_rtx_REG (word_mode, 22);
8254 emit_move_insn (tmpreg, force_reg (word_mode, op));
8256 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
8258 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
8265 (define_insn "call_val_symref"
8266 [(set (match_operand 0 "" "")
8267 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8268 (match_operand 2 "" "i")))
8269 (clobber (reg:SI 1))
8270 (clobber (reg:SI 2))
8271 (use (const_int 0))]
8272 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8275 output_arg_descriptor (insn);
8276 return output_call (insn, operands[1], 0);
8278 [(set_attr "type" "call")
8279 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8281 (define_insn "call_val_symref_pic"
8282 [(set (match_operand 0 "" "")
8283 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8284 (match_operand 2 "" "i")))
8285 (clobber (reg:SI 1))
8286 (clobber (reg:SI 2))
8287 (clobber (reg:SI 4))
8289 (use (const_int 0))]
8290 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8293 output_arg_descriptor (insn);
8294 return output_call (insn, operands[1], 0);
8296 [(set_attr "type" "call")
8297 (set (attr "length")
8298 (plus (symbol_ref "attr_length_call (insn, 0)")
8299 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8301 ;; Split out the PIC register save and restore after reload. This is
8302 ;; done only if the function returns. As the split is done after reload,
8303 ;; there are some situations in which we unnecessarily save and restore
8304 ;; %r4. This happens when there is a single call and the PIC register
8305 ;; is "dead" after the call. This isn't easy to fix as the usage of
8306 ;; the PIC register isn't completely determined until the reload pass.
8308 [(parallel [(set (match_operand 0 "" "")
8309 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8310 (match_operand 2 "" "")))
8311 (clobber (reg:SI 1))
8312 (clobber (reg:SI 2))
8313 (clobber (reg:SI 4))
8315 (use (const_int 0))])]
8316 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
8318 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8319 [(set (reg:SI 4) (reg:SI 19))
8320 (parallel [(set (match_dup 0)
8321 (call (mem:SI (match_dup 1))
8323 (clobber (reg:SI 1))
8324 (clobber (reg:SI 2))
8326 (use (const_int 0))])
8327 (set (reg:SI 19) (reg:SI 4))]
8330 ;; Remove the clobber of register 4 when optimizing. This has to be
8331 ;; done with a peephole optimization rather than a split because the
8332 ;; split sequence for a call must be longer than one instruction.
8334 [(parallel [(set (match_operand 0 "" "")
8335 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8336 (match_operand 2 "" "")))
8337 (clobber (reg:SI 1))
8338 (clobber (reg:SI 2))
8339 (clobber (reg:SI 4))
8341 (use (const_int 0))])]
8342 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
8343 [(parallel [(set (match_dup 0)
8344 (call (mem:SI (match_dup 1))
8346 (clobber (reg:SI 1))
8347 (clobber (reg:SI 2))
8349 (use (const_int 0))])]
8352 (define_insn "*call_val_symref_pic_post_reload"
8353 [(set (match_operand 0 "" "")
8354 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8355 (match_operand 2 "" "i")))
8356 (clobber (reg:SI 1))
8357 (clobber (reg:SI 2))
8359 (use (const_int 0))]
8360 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8363 output_arg_descriptor (insn);
8364 return output_call (insn, operands[1], 0);
8366 [(set_attr "type" "call")
8367 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8369 ;; This pattern is split if it is necessary to save and restore the
8371 (define_insn "call_val_symref_64bit"
8372 [(set (match_operand 0 "" "")
8373 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8374 (match_operand 2 "" "i")))
8375 (clobber (reg:DI 1))
8376 (clobber (reg:DI 2))
8377 (clobber (reg:DI 4))
8380 (use (const_int 0))]
8384 output_arg_descriptor (insn);
8385 return output_call (insn, operands[1], 0);
8387 [(set_attr "type" "call")
8388 (set (attr "length")
8389 (plus (symbol_ref "attr_length_call (insn, 0)")
8390 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8392 ;; Split out the PIC register save and restore after reload. This is
8393 ;; done only if the function returns. As the split is done after reload,
8394 ;; there are some situations in which we unnecessarily save and restore
8395 ;; %r4. This happens when there is a single call and the PIC register
8396 ;; is "dead" after the call. This isn't easy to fix as the usage of
8397 ;; the PIC register isn't completely determined until the reload pass.
8399 [(parallel [(set (match_operand 0 "" "")
8400 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8401 (match_operand 2 "" "")))
8402 (clobber (reg:DI 1))
8403 (clobber (reg:DI 2))
8404 (clobber (reg:DI 4))
8407 (use (const_int 0))])]
8410 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8411 [(set (reg:DI 4) (reg:DI 27))
8412 (parallel [(set (match_dup 0)
8413 (call (mem:SI (match_dup 1))
8415 (clobber (reg:DI 1))
8416 (clobber (reg:DI 2))
8419 (use (const_int 0))])
8420 (set (reg:DI 27) (reg:DI 4))]
8423 ;; Remove the clobber of register 4 when optimizing. This has to be
8424 ;; done with a peephole optimization rather than a split because the
8425 ;; split sequence for a call must be longer than one instruction.
8427 [(parallel [(set (match_operand 0 "" "")
8428 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8429 (match_operand 2 "" "")))
8430 (clobber (reg:DI 1))
8431 (clobber (reg:DI 2))
8432 (clobber (reg:DI 4))
8435 (use (const_int 0))])]
8436 "TARGET_64BIT && reload_completed"
8437 [(parallel [(set (match_dup 0)
8438 (call (mem:SI (match_dup 1))
8440 (clobber (reg:DI 1))
8441 (clobber (reg:DI 2))
8444 (use (const_int 0))])]
8447 (define_insn "*call_val_symref_64bit_post_reload"
8448 [(set (match_operand 0 "" "")
8449 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8450 (match_operand 2 "" "i")))
8451 (clobber (reg:DI 1))
8452 (clobber (reg:DI 2))
8455 (use (const_int 0))]
8459 output_arg_descriptor (insn);
8460 return output_call (insn, operands[1], 0);
8462 [(set_attr "type" "call")
8463 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
8465 (define_insn "call_val_reg"
8466 [(set (match_operand 0 "" "")
8467 (call (mem:SI (reg:SI 22))
8468 (match_operand 1 "" "i")))
8469 (clobber (reg:SI 1))
8470 (clobber (reg:SI 2))
8471 (use (const_int 1))]
8475 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8477 [(set_attr "type" "dyncall")
8478 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8480 ;; This pattern is split if it is necessary to save and restore the
8482 (define_insn "call_val_reg_pic"
8483 [(set (match_operand 0 "" "")
8484 (call (mem:SI (reg:SI 22))
8485 (match_operand 1 "" "i")))
8486 (clobber (reg:SI 1))
8487 (clobber (reg:SI 2))
8488 (clobber (reg:SI 4))
8490 (use (const_int 1))]
8494 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8496 [(set_attr "type" "dyncall")
8497 (set (attr "length")
8498 (plus (symbol_ref "attr_length_indirect_call (insn)")
8499 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8501 ;; Split out the PIC register save and restore after reload. This is
8502 ;; done only if the function returns. As the split is done after reload,
8503 ;; there are some situations in which we unnecessarily save and restore
8504 ;; %r4. This happens when there is a single call and the PIC register
8505 ;; is "dead" after the call. This isn't easy to fix as the usage of
8506 ;; the PIC register isn't completely determined until the reload pass.
8508 [(parallel [(set (match_operand 0 "" "")
8509 (call (mem:SI (reg:SI 22))
8510 (match_operand 1 "" "")))
8511 (clobber (reg:SI 1))
8512 (clobber (reg:SI 2))
8513 (clobber (reg:SI 4))
8515 (use (const_int 1))])]
8518 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8519 [(set (reg:SI 4) (reg:SI 19))
8520 (parallel [(set (match_dup 0)
8521 (call (mem:SI (reg:SI 22))
8523 (clobber (reg:SI 1))
8524 (clobber (reg:SI 2))
8526 (use (const_int 1))])
8527 (set (reg:SI 19) (reg:SI 4))]
8530 ;; Remove the clobber of register 4 when optimizing. This has to be
8531 ;; done with a peephole optimization rather than a split because the
8532 ;; split sequence for a call must be longer than one instruction.
8534 [(parallel [(set (match_operand 0 "" "")
8535 (call (mem:SI (reg:SI 22))
8536 (match_operand 1 "" "")))
8537 (clobber (reg:SI 1))
8538 (clobber (reg:SI 2))
8539 (clobber (reg:SI 4))
8541 (use (const_int 1))])]
8542 "!TARGET_64BIT && reload_completed"
8543 [(parallel [(set (match_dup 0)
8544 (call (mem:SI (reg:SI 22))
8546 (clobber (reg:SI 1))
8547 (clobber (reg:SI 2))
8549 (use (const_int 1))])]
8552 (define_insn "*call_val_reg_pic_post_reload"
8553 [(set (match_operand 0 "" "")
8554 (call (mem:SI (reg:SI 22))
8555 (match_operand 1 "" "i")))
8556 (clobber (reg:SI 1))
8557 (clobber (reg:SI 2))
8559 (use (const_int 1))]
8563 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
8565 [(set_attr "type" "dyncall")
8566 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8568 ;; This pattern is split if it is necessary to save and restore the
8570 (define_insn "call_val_reg_64bit"
8571 [(set (match_operand 0 "" "")
8572 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8573 (match_operand 2 "" "i")))
8574 (clobber (reg:DI 2))
8575 (clobber (reg:DI 4))
8578 (use (const_int 1))]
8582 return output_indirect_call (insn, operands[1]);
8584 [(set_attr "type" "dyncall")
8585 (set (attr "length")
8586 (plus (symbol_ref "attr_length_indirect_call (insn)")
8587 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
8589 ;; Split out the PIC register save and restore after reload. This is
8590 ;; done only if the function returns. As the split is done after reload,
8591 ;; there are some situations in which we unnecessarily save and restore
8592 ;; %r4. This happens when there is a single call and the PIC register
8593 ;; is "dead" after the call. This isn't easy to fix as the usage of
8594 ;; the PIC register isn't completely determined until the reload pass.
8596 [(parallel [(set (match_operand 0 "" "")
8597 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8598 (match_operand 2 "" "")))
8599 (clobber (reg:DI 2))
8600 (clobber (reg:DI 4))
8603 (use (const_int 1))])]
8606 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
8607 [(set (reg:DI 4) (reg:DI 27))
8608 (parallel [(set (match_dup 0)
8609 (call (mem:SI (match_dup 1))
8611 (clobber (reg:DI 2))
8614 (use (const_int 1))])
8615 (set (reg:DI 27) (reg:DI 4))]
8618 ;; Remove the clobber of register 4 when optimizing. This has to be
8619 ;; done with a peephole optimization rather than a split because the
8620 ;; split sequence for a call must be longer than one instruction.
8622 [(parallel [(set (match_operand 0 "" "")
8623 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
8624 (match_operand 2 "" "")))
8625 (clobber (reg:DI 2))
8626 (clobber (reg:DI 4))
8629 (use (const_int 1))])]
8630 "TARGET_64BIT && reload_completed"
8631 [(parallel [(set (match_dup 0)
8632 (call (mem:SI (match_dup 1))
8634 (clobber (reg:DI 2))
8637 (use (const_int 1))])]
8640 (define_insn "*call_val_reg_64bit_post_reload"
8641 [(set (match_operand 0 "" "")
8642 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
8643 (match_operand 2 "" "i")))
8644 (clobber (reg:DI 2))
8647 (use (const_int 1))]
8651 return output_indirect_call (insn, operands[1]);
8653 [(set_attr "type" "dyncall")
8654 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
8656 ;; Call subroutine returning any type.
8658 (define_expand "untyped_call"
8659 [(parallel [(call (match_operand 0 "" "")
8661 (match_operand 1 "" "")
8662 (match_operand 2 "" "")])]
8668 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
8670 for (i = 0; i < XVECLEN (operands[2], 0); i++)
8672 rtx set = XVECEXP (operands[2], 0, i);
8673 emit_move_insn (SET_DEST (set), SET_SRC (set));
8676 /* The optimizer does not know that the call sets the function value
8677 registers we stored in the result block. We avoid problems by
8678 claiming that all hard registers are used and clobbered at this
8680 emit_insn (gen_blockage ());
8685 (define_expand "sibcall"
8686 [(call (match_operand:SI 0 "" "")
8687 (match_operand 1 "" ""))]
8688 "!TARGET_PORTABLE_RUNTIME"
8692 rtx nb = operands[1];
8694 op = XEXP (operands[0], 0);
8698 if (!virtuals_instantiated)
8699 emit_move_insn (arg_pointer_rtx,
8700 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8704 /* The loop pass can generate new libcalls after the virtual
8705 registers are instantiated when fpregs are disabled because
8706 the only method that we have for doing DImode multiplication
8707 is with a libcall. This could be trouble if we haven't
8708 allocated enough space for the outgoing arguments. */
8709 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8711 emit_move_insn (arg_pointer_rtx,
8712 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8713 GEN_INT (STACK_POINTER_OFFSET + 64)));
8717 /* Indirect sibling calls are not allowed. */
8719 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8721 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8723 call_insn = emit_call_insn (call_insn);
8726 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8728 /* We don't have to restore the PIC register. */
8730 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8735 (define_insn "sibcall_internal_symref"
8736 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8737 (match_operand 1 "" "i"))
8738 (clobber (reg:SI 1))
8740 (use (const_int 0))]
8741 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8744 output_arg_descriptor (insn);
8745 return output_call (insn, operands[0], 1);
8747 [(set_attr "type" "call")
8748 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8750 (define_insn "sibcall_internal_symref_64bit"
8751 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8752 (match_operand 1 "" "i"))
8753 (clobber (reg:DI 1))
8755 (use (const_int 0))]
8759 output_arg_descriptor (insn);
8760 return output_call (insn, operands[0], 1);
8762 [(set_attr "type" "call")
8763 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8765 (define_expand "sibcall_value"
8766 [(set (match_operand 0 "" "")
8767 (call (match_operand:SI 1 "" "")
8768 (match_operand 2 "" "")))]
8769 "!TARGET_PORTABLE_RUNTIME"
8773 rtx nb = operands[1];
8775 op = XEXP (operands[1], 0);
8779 if (!virtuals_instantiated)
8780 emit_move_insn (arg_pointer_rtx,
8781 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8785 /* The loop pass can generate new libcalls after the virtual
8786 registers are instantiated when fpregs are disabled because
8787 the only method that we have for doing DImode multiplication
8788 is with a libcall. This could be trouble if we haven't
8789 allocated enough space for the outgoing arguments. */
8790 gcc_assert (INTVAL (nb) <= current_function_outgoing_args_size);
8792 emit_move_insn (arg_pointer_rtx,
8793 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8794 GEN_INT (STACK_POINTER_OFFSET + 64)));
8798 /* Indirect sibling calls are not allowed. */
8801 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8804 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8806 call_insn = emit_call_insn (call_insn);
8809 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8811 /* We don't have to restore the PIC register. */
8813 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8818 (define_insn "sibcall_value_internal_symref"
8819 [(set (match_operand 0 "" "")
8820 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8821 (match_operand 2 "" "i")))
8822 (clobber (reg:SI 1))
8824 (use (const_int 0))]
8825 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8828 output_arg_descriptor (insn);
8829 return output_call (insn, operands[1], 1);
8831 [(set_attr "type" "call")
8832 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8834 (define_insn "sibcall_value_internal_symref_64bit"
8835 [(set (match_operand 0 "" "")
8836 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8837 (match_operand 2 "" "i")))
8838 (clobber (reg:DI 1))
8840 (use (const_int 0))]
8844 output_arg_descriptor (insn);
8845 return output_call (insn, operands[1], 1);
8847 [(set_attr "type" "call")
8848 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8854 [(set_attr "type" "move")
8855 (set_attr "length" "4")])
8857 ;; These are just placeholders so we know where branch tables
8859 (define_insn "begin_brtab"
8864 /* Only GAS actually supports this pseudo-op. */
8866 return \".begin_brtab\";
8870 [(set_attr "type" "move")
8871 (set_attr "length" "0")])
8873 (define_insn "end_brtab"
8878 /* Only GAS actually supports this pseudo-op. */
8880 return \".end_brtab\";
8884 [(set_attr "type" "move")
8885 (set_attr "length" "0")])
8887 ;;; EH does longjmp's from and within the data section. Thus,
8888 ;;; an interspace branch is required for the longjmp implementation.
8889 ;;; Registers r1 and r2 are used as scratch registers for the jump
8891 (define_expand "interspace_jump"
8893 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8894 (clobber (match_dup 1))])]
8898 operands[1] = gen_rtx_REG (word_mode, 2);
8902 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8903 (clobber (reg:SI 2))]
8904 "TARGET_PA_20 && !TARGET_64BIT"
8906 [(set_attr "type" "branch")
8907 (set_attr "length" "4")])
8910 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8911 (clobber (reg:SI 2))]
8912 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8914 [(set_attr "type" "branch")
8915 (set_attr "length" "4")])
8918 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8919 (clobber (reg:SI 2))]
8921 "ldsid (%%sr0,%0),%%r2\;mtsp %%r2,%%sr0\;be%* 0(%%sr0,%0)"
8922 [(set_attr "type" "branch")
8923 (set_attr "length" "12")])
8926 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8927 (clobber (reg:DI 2))]
8930 [(set_attr "type" "branch")
8931 (set_attr "length" "4")])
8933 (define_expand "builtin_longjmp"
8934 [(unspec_volatile [(match_operand 0 "register_operand" "r")] UNSPECV_LONGJMP)]
8938 /* The elements of the buffer are, in order: */
8939 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8940 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8941 POINTER_SIZE / BITS_PER_UNIT));
8942 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8943 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8944 rtx pv = gen_rtx_REG (Pmode, 1);
8946 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8947 gen_rtx_MEM (BLKmode,
8948 gen_rtx_SCRATCH (VOIDmode))));
8949 emit_insn (gen_rtx_CLOBBER (VOIDmode,
8950 gen_rtx_MEM (BLKmode,
8951 hard_frame_pointer_rtx)));
8953 /* Restore the frame pointer. The virtual_stack_vars_rtx is saved
8954 instead of the hard_frame_pointer_rtx in the save area. We need
8955 to adjust for the offset between these two values when we have
8956 a nonlocal_goto pattern. When we don't have a nonlocal_goto
8957 pattern, the receiver performs the adjustment. */
8958 #ifdef HAVE_nonlocal_goto
8959 if (HAVE_nonlocal_goto)
8960 emit_move_insn (virtual_stack_vars_rtx, force_reg (Pmode, fp));
8963 emit_move_insn (hard_frame_pointer_rtx, fp);
8965 /* This bit is the same as expand_builtin_longjmp. */
8966 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8967 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8968 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8970 /* Load the label we are jumping through into r1 so that we know
8971 where to look for it when we get back to setjmp's function for
8972 restoring the gp. */
8973 emit_move_insn (pv, lab);
8975 /* Prevent the insns above from being scheduled into the delay slot
8976 of the interspace jump because the space register could change. */
8977 emit_insn (gen_blockage ());
8979 emit_jump_insn (gen_interspace_jump (pv));
8984 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8985 (define_expand "extzv"
8986 [(set (match_operand 0 "register_operand" "")
8987 (zero_extract (match_operand 1 "register_operand" "")
8988 (match_operand 2 "uint32_operand" "")
8989 (match_operand 3 "uint32_operand" "")))]
8993 HOST_WIDE_INT len = INTVAL (operands[2]);
8994 HOST_WIDE_INT pos = INTVAL (operands[3]);
8996 /* PA extraction insns don't support zero length bitfields or fields
8997 extending beyond the left or right-most bits. Also, we reject lengths
8998 equal to a word as they are better handled by the move patterns. */
8999 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9002 /* From mips.md: extract_bit_field doesn't verify that our source
9003 matches the predicate, so check it again here. */
9004 if (!register_operand (operands[1], VOIDmode))
9008 emit_insn (gen_extzv_64 (operands[0], operands[1],
9009 operands[2], operands[3]));
9011 emit_insn (gen_extzv_32 (operands[0], operands[1],
9012 operands[2], operands[3]));
9016 (define_insn "extzv_32"
9017 [(set (match_operand:SI 0 "register_operand" "=r")
9018 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9019 (match_operand:SI 2 "uint5_operand" "")
9020 (match_operand:SI 3 "uint5_operand" "")))]
9022 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
9023 [(set_attr "type" "shift")
9024 (set_attr "length" "4")])
9027 [(set (match_operand:SI 0 "register_operand" "=r")
9028 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
9030 (match_operand:SI 2 "register_operand" "q")))]
9032 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
9033 [(set_attr "type" "shift")
9034 (set_attr "length" "4")])
9036 (define_insn "extzv_64"
9037 [(set (match_operand:DI 0 "register_operand" "=r")
9038 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9039 (match_operand:DI 2 "uint32_operand" "")
9040 (match_operand:DI 3 "uint32_operand" "")))]
9042 "extrd,u %1,%3+%2-1,%2,%0"
9043 [(set_attr "type" "shift")
9044 (set_attr "length" "4")])
9047 [(set (match_operand:DI 0 "register_operand" "=r")
9048 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
9050 (match_operand:DI 2 "register_operand" "q")))]
9052 "extrd,u %1,%%sar,1,%0"
9053 [(set_attr "type" "shift")
9054 (set_attr "length" "4")])
9056 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
9057 (define_expand "extv"
9058 [(set (match_operand 0 "register_operand" "")
9059 (sign_extract (match_operand 1 "register_operand" "")
9060 (match_operand 2 "uint32_operand" "")
9061 (match_operand 3 "uint32_operand" "")))]
9065 HOST_WIDE_INT len = INTVAL (operands[2]);
9066 HOST_WIDE_INT pos = INTVAL (operands[3]);
9068 /* PA extraction insns don't support zero length bitfields or fields
9069 extending beyond the left or right-most bits. Also, we reject lengths
9070 equal to a word as they are better handled by the move patterns. */
9071 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9074 /* From mips.md: extract_bit_field doesn't verify that our source
9075 matches the predicate, so check it again here. */
9076 if (!register_operand (operands[1], VOIDmode))
9080 emit_insn (gen_extv_64 (operands[0], operands[1],
9081 operands[2], operands[3]));
9083 emit_insn (gen_extv_32 (operands[0], operands[1],
9084 operands[2], operands[3]));
9088 (define_insn "extv_32"
9089 [(set (match_operand:SI 0 "register_operand" "=r")
9090 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9091 (match_operand:SI 2 "uint5_operand" "")
9092 (match_operand:SI 3 "uint5_operand" "")))]
9094 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
9095 [(set_attr "type" "shift")
9096 (set_attr "length" "4")])
9099 [(set (match_operand:SI 0 "register_operand" "=r")
9100 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
9102 (match_operand:SI 2 "register_operand" "q")))]
9104 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
9105 [(set_attr "type" "shift")
9106 (set_attr "length" "4")])
9108 (define_insn "extv_64"
9109 [(set (match_operand:DI 0 "register_operand" "=r")
9110 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9111 (match_operand:DI 2 "uint32_operand" "")
9112 (match_operand:DI 3 "uint32_operand" "")))]
9114 "extrd,s %1,%3+%2-1,%2,%0"
9115 [(set_attr "type" "shift")
9116 (set_attr "length" "4")])
9119 [(set (match_operand:DI 0 "register_operand" "=r")
9120 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
9122 (match_operand:DI 2 "register_operand" "q")))]
9124 "extrd,s %1,%%sar,1,%0"
9125 [(set_attr "type" "shift")
9126 (set_attr "length" "4")])
9128 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
9129 (define_expand "insv"
9130 [(set (zero_extract (match_operand 0 "register_operand" "")
9131 (match_operand 1 "uint32_operand" "")
9132 (match_operand 2 "uint32_operand" ""))
9133 (match_operand 3 "arith5_operand" ""))]
9137 HOST_WIDE_INT len = INTVAL (operands[1]);
9138 HOST_WIDE_INT pos = INTVAL (operands[2]);
9140 /* PA insertion insns don't support zero length bitfields or fields
9141 extending beyond the left or right-most bits. Also, we reject lengths
9142 equal to a word as they are better handled by the move patterns. */
9143 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
9146 /* From mips.md: insert_bit_field doesn't verify that our destination
9147 matches the predicate, so check it again here. */
9148 if (!register_operand (operands[0], VOIDmode))
9152 emit_insn (gen_insv_64 (operands[0], operands[1],
9153 operands[2], operands[3]));
9155 emit_insn (gen_insv_32 (operands[0], operands[1],
9156 operands[2], operands[3]));
9160 (define_insn "insv_32"
9161 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
9162 (match_operand:SI 1 "uint5_operand" "")
9163 (match_operand:SI 2 "uint5_operand" ""))
9164 (match_operand:SI 3 "arith5_operand" "r,L"))]
9167 {dep|depw} %3,%2+%1-1,%1,%0
9168 {depi|depwi} %3,%2+%1-1,%1,%0"
9169 [(set_attr "type" "shift,shift")
9170 (set_attr "length" "4,4")])
9172 ;; Optimize insertion of const_int values of type 1...1xxxx.
9174 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
9175 (match_operand:SI 1 "uint5_operand" "")
9176 (match_operand:SI 2 "uint5_operand" ""))
9177 (match_operand:SI 3 "const_int_operand" ""))]
9178 "(INTVAL (operands[3]) & 0x10) != 0 &&
9179 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9182 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9183 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
9185 [(set_attr "type" "shift")
9186 (set_attr "length" "4")])
9188 (define_insn "insv_64"
9189 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
9190 (match_operand:DI 1 "uint32_operand" "")
9191 (match_operand:DI 2 "uint32_operand" ""))
9192 (match_operand:DI 3 "arith32_operand" "r,L"))]
9195 depd %3,%2+%1-1,%1,%0
9196 depdi %3,%2+%1-1,%1,%0"
9197 [(set_attr "type" "shift,shift")
9198 (set_attr "length" "4,4")])
9200 ;; Optimize insertion of const_int values of type 1...1xxxx.
9202 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
9203 (match_operand:DI 1 "uint32_operand" "")
9204 (match_operand:DI 2 "uint32_operand" ""))
9205 (match_operand:DI 3 "const_int_operand" ""))]
9206 "(INTVAL (operands[3]) & 0x10) != 0
9208 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
9211 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
9212 return \"depdi %3,%2+%1-1,%1,%0\";
9214 [(set_attr "type" "shift")
9215 (set_attr "length" "4")])
9218 [(set (match_operand:DI 0 "register_operand" "=r")
9219 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
9222 "depd,z %1,31,32,%0"
9223 [(set_attr "type" "shift")
9224 (set_attr "length" "4")])
9226 ;; This insn is used for some loop tests, typically loops reversed when
9227 ;; strength reduction is used. It is actually created when the instruction
9228 ;; combination phase combines the special loop test. Since this insn
9229 ;; is both a jump insn and has an output, it must deal with its own
9230 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
9231 ;; to not choose the register alternatives in the event a reload is needed.
9232 (define_insn "decrement_and_branch_until_zero"
9235 (match_operator 2 "comparison_operator"
9237 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
9238 (match_operand:SI 1 "int5_operand" "L,L,L"))
9240 (label_ref (match_operand 3 "" ""))
9243 (plus:SI (match_dup 0) (match_dup 1)))
9244 (clobber (match_scratch:SI 4 "=X,r,r"))]
9246 "* return output_dbra (operands, insn, which_alternative); "
9247 ;; Do not expect to understand this the first time through.
9248 [(set_attr "type" "cbranch,multi,multi")
9249 (set (attr "length")
9250 (if_then_else (eq_attr "alternative" "0")
9251 ;; Loop counter in register case
9252 ;; Short branch has length of 4
9253 ;; Long branch has length of 8, 20, 24 or 28
9254 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9255 (const_int MAX_12BIT_OFFSET))
9257 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9258 (const_int MAX_17BIT_OFFSET))
9260 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9262 (eq (symbol_ref "flag_pic") (const_int 0))
9266 ;; Loop counter in FP reg case.
9267 ;; Extra goo to deal with additional reload insns.
9268 (if_then_else (eq_attr "alternative" "1")
9269 (if_then_else (lt (match_dup 3) (pc))
9270 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9271 (const_int MAX_12BIT_OFFSET))
9273 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
9274 (const_int MAX_17BIT_OFFSET))
9276 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9278 (eq (symbol_ref "flag_pic") (const_int 0))
9281 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9282 (const_int MAX_12BIT_OFFSET))
9284 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9285 (const_int MAX_17BIT_OFFSET))
9287 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9289 (eq (symbol_ref "flag_pic") (const_int 0))
9293 ;; Loop counter in memory case.
9294 ;; Extra goo to deal with additional reload insns.
9295 (if_then_else (lt (match_dup 3) (pc))
9296 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9297 (const_int MAX_12BIT_OFFSET))
9299 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9300 (const_int MAX_17BIT_OFFSET))
9302 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9304 (eq (symbol_ref "flag_pic") (const_int 0))
9307 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9308 (const_int MAX_12BIT_OFFSET))
9310 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9311 (const_int MAX_17BIT_OFFSET))
9313 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9315 (eq (symbol_ref "flag_pic") (const_int 0))
9317 (const_int 36))))))])
9322 (match_operator 2 "movb_comparison_operator"
9323 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9324 (label_ref (match_operand 3 "" ""))
9326 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9329 "* return output_movb (operands, insn, which_alternative, 0); "
9330 ;; Do not expect to understand this the first time through.
9331 [(set_attr "type" "cbranch,multi,multi,multi")
9332 (set (attr "length")
9333 (if_then_else (eq_attr "alternative" "0")
9334 ;; Loop counter in register case
9335 ;; Short branch has length of 4
9336 ;; Long branch has length of 8, 20, 24 or 28
9337 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9338 (const_int MAX_12BIT_OFFSET))
9340 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9341 (const_int MAX_17BIT_OFFSET))
9343 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9345 (eq (symbol_ref "flag_pic") (const_int 0))
9349 ;; Loop counter in FP reg case.
9350 ;; Extra goo to deal with additional reload insns.
9351 (if_then_else (eq_attr "alternative" "1")
9352 (if_then_else (lt (match_dup 3) (pc))
9353 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9354 (const_int MAX_12BIT_OFFSET))
9356 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9357 (const_int MAX_17BIT_OFFSET))
9359 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9361 (eq (symbol_ref "flag_pic") (const_int 0))
9364 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9365 (const_int MAX_12BIT_OFFSET))
9367 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9368 (const_int MAX_17BIT_OFFSET))
9370 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9372 (eq (symbol_ref "flag_pic") (const_int 0))
9376 ;; Loop counter in memory or sar case.
9377 ;; Extra goo to deal with additional reload insns.
9378 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9379 (const_int MAX_12BIT_OFFSET))
9381 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9382 (const_int MAX_17BIT_OFFSET))
9384 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9386 (eq (symbol_ref "flag_pic") (const_int 0))
9388 (const_int 32)))))])
9390 ;; Handle negated branch.
9394 (match_operator 2 "movb_comparison_operator"
9395 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
9397 (label_ref (match_operand 3 "" ""))))
9398 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
9401 "* return output_movb (operands, insn, which_alternative, 1); "
9402 ;; Do not expect to understand this the first time through.
9403 [(set_attr "type" "cbranch,multi,multi,multi")
9404 (set (attr "length")
9405 (if_then_else (eq_attr "alternative" "0")
9406 ;; Loop counter in register case
9407 ;; Short branch has length of 4
9408 ;; Long branch has length of 8
9409 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9410 (const_int MAX_12BIT_OFFSET))
9412 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9413 (const_int MAX_17BIT_OFFSET))
9415 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9417 (eq (symbol_ref "flag_pic") (const_int 0))
9421 ;; Loop counter in FP reg case.
9422 ;; Extra goo to deal with additional reload insns.
9423 (if_then_else (eq_attr "alternative" "1")
9424 (if_then_else (lt (match_dup 3) (pc))
9425 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9426 (const_int MAX_12BIT_OFFSET))
9428 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
9429 (const_int MAX_17BIT_OFFSET))
9431 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9433 (eq (symbol_ref "flag_pic") (const_int 0))
9436 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9437 (const_int MAX_12BIT_OFFSET))
9439 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9440 (const_int MAX_17BIT_OFFSET))
9442 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9444 (eq (symbol_ref "flag_pic") (const_int 0))
9448 ;; Loop counter in memory or SAR case.
9449 ;; Extra goo to deal with additional reload insns.
9450 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9451 (const_int MAX_12BIT_OFFSET))
9453 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9454 (const_int MAX_17BIT_OFFSET))
9456 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9458 (eq (symbol_ref "flag_pic") (const_int 0))
9460 (const_int 32)))))])
9463 [(set (pc) (label_ref (match_operand 3 "" "" )))
9464 (set (match_operand:SI 0 "ireg_operand" "=r")
9465 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
9466 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
9467 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
9470 return output_parallel_addb (operands, insn);
9472 [(set_attr "type" "parallel_branch")
9473 (set (attr "length")
9474 (cond [(lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9475 (const_int MAX_12BIT_OFFSET))
9477 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
9478 (const_int MAX_17BIT_OFFSET))
9480 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9482 (eq (symbol_ref "flag_pic") (const_int 0))
9487 [(set (pc) (label_ref (match_operand 2 "" "" )))
9488 (set (match_operand:SF 0 "ireg_operand" "=r")
9489 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
9493 return output_parallel_movb (operands, insn);
9495 [(set_attr "type" "parallel_branch")
9496 (set (attr "length")
9497 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9498 (const_int MAX_12BIT_OFFSET))
9500 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9501 (const_int MAX_17BIT_OFFSET))
9503 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9505 (eq (symbol_ref "flag_pic") (const_int 0))
9510 [(set (pc) (label_ref (match_operand 2 "" "" )))
9511 (set (match_operand:SI 0 "ireg_operand" "=r")
9512 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
9516 return output_parallel_movb (operands, insn);
9518 [(set_attr "type" "parallel_branch")
9519 (set (attr "length")
9520 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9521 (const_int MAX_12BIT_OFFSET))
9523 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9524 (const_int MAX_17BIT_OFFSET))
9526 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9528 (eq (symbol_ref "flag_pic") (const_int 0))
9533 [(set (pc) (label_ref (match_operand 2 "" "" )))
9534 (set (match_operand:HI 0 "ireg_operand" "=r")
9535 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
9539 return output_parallel_movb (operands, insn);
9541 [(set_attr "type" "parallel_branch")
9542 (set (attr "length")
9543 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9544 (const_int MAX_12BIT_OFFSET))
9546 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9547 (const_int MAX_17BIT_OFFSET))
9549 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9551 (eq (symbol_ref "flag_pic") (const_int 0))
9556 [(set (pc) (label_ref (match_operand 2 "" "" )))
9557 (set (match_operand:QI 0 "ireg_operand" "=r")
9558 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
9562 return output_parallel_movb (operands, insn);
9564 [(set_attr "type" "parallel_branch")
9565 (set (attr "length")
9566 (cond [(lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9567 (const_int MAX_12BIT_OFFSET))
9569 (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
9570 (const_int MAX_17BIT_OFFSET))
9572 (ne (symbol_ref "TARGET_PORTABLE_RUNTIME") (const_int 0))
9574 (eq (symbol_ref "flag_pic") (const_int 0))
9579 [(set (match_operand 0 "register_operand" "=f")
9580 (mult (match_operand 1 "register_operand" "f")
9581 (match_operand 2 "register_operand" "f")))
9582 (set (match_operand 3 "register_operand" "+f")
9583 (plus (match_operand 4 "register_operand" "f")
9584 (match_operand 5 "register_operand" "f")))]
9585 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9586 && reload_completed && fmpyaddoperands (operands)"
9589 if (GET_MODE (operands[0]) == DFmode)
9591 if (rtx_equal_p (operands[3], operands[5]))
9592 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9594 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9598 if (rtx_equal_p (operands[3], operands[5]))
9599 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9601 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9604 [(set_attr "type" "fpalu")
9605 (set_attr "length" "4")])
9608 [(set (match_operand 3 "register_operand" "+f")
9609 (plus (match_operand 4 "register_operand" "f")
9610 (match_operand 5 "register_operand" "f")))
9611 (set (match_operand 0 "register_operand" "=f")
9612 (mult (match_operand 1 "register_operand" "f")
9613 (match_operand 2 "register_operand" "f")))]
9614 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9615 && reload_completed && fmpyaddoperands (operands)"
9618 if (GET_MODE (operands[0]) == DFmode)
9620 if (rtx_equal_p (operands[3], operands[5]))
9621 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
9623 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
9627 if (rtx_equal_p (operands[3], operands[5]))
9628 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
9630 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
9633 [(set_attr "type" "fpalu")
9634 (set_attr "length" "4")])
9637 [(set (match_operand 0 "register_operand" "=f")
9638 (mult (match_operand 1 "register_operand" "f")
9639 (match_operand 2 "register_operand" "f")))
9640 (set (match_operand 3 "register_operand" "+f")
9641 (minus (match_operand 4 "register_operand" "f")
9642 (match_operand 5 "register_operand" "f")))]
9643 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9644 && reload_completed && fmpysuboperands (operands)"
9647 if (GET_MODE (operands[0]) == DFmode)
9648 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9650 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9652 [(set_attr "type" "fpalu")
9653 (set_attr "length" "4")])
9656 [(set (match_operand 3 "register_operand" "+f")
9657 (minus (match_operand 4 "register_operand" "f")
9658 (match_operand 5 "register_operand" "f")))
9659 (set (match_operand 0 "register_operand" "=f")
9660 (mult (match_operand 1 "register_operand" "f")
9661 (match_operand 2 "register_operand" "f")))]
9662 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
9663 && reload_completed && fmpysuboperands (operands)"
9666 if (GET_MODE (operands[0]) == DFmode)
9667 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
9669 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
9671 [(set_attr "type" "fpalu")
9672 (set_attr "length" "4")])
9674 ;; Flush the I and D cache lines from the start address (operand0)
9675 ;; to the end address (operand1). No lines are flushed if the end
9676 ;; address is less than the start address (unsigned).
9678 ;; Because the range of memory flushed is variable and the size of
9679 ;; a MEM can only be a CONST_INT, the patterns specify that they
9680 ;; perform an unspecified volatile operation on all memory.
9682 ;; The address range for an icache flush must lie within a single
9683 ;; space on targets with non-equivalent space registers.
9685 ;; This is used by the trampoline code for nested functions.
9687 ;; Operand 0 contains the start address.
9688 ;; Operand 1 contains the end address.
9689 ;; Operand 2 contains the line length to use.
9690 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
9691 (define_insn "dcacheflush"
9693 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_DCACHE)
9694 (use (match_operand 0 "pmode_register_operand" "r"))
9695 (use (match_operand 1 "pmode_register_operand" "r"))
9696 (use (match_operand 2 "pmode_register_operand" "r"))
9697 (clobber (match_scratch 3 "=&0"))]
9702 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9704 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
9706 [(set_attr "type" "multi")
9707 (set_attr "length" "12")])
9709 (define_insn "icacheflush"
9711 (unspec_volatile [(mem:BLK (scratch))] UNSPECV_ICACHE)
9712 (use (match_operand 0 "pmode_register_operand" "r"))
9713 (use (match_operand 1 "pmode_register_operand" "r"))
9714 (use (match_operand 2 "pmode_register_operand" "r"))
9715 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
9716 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
9717 (clobber (match_scratch 5 "=&0"))]
9722 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9724 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
9726 [(set_attr "type" "multi")
9727 (set_attr "length" "52")])
9729 ;; An out-of-line prologue.
9730 (define_insn "outline_prologue_call"
9731 [(unspec_volatile [(const_int 0)] UNSPECV_OPC)
9732 (clobber (reg:SI 31))
9733 (clobber (reg:SI 22))
9734 (clobber (reg:SI 21))
9735 (clobber (reg:SI 20))
9736 (clobber (reg:SI 19))
9737 (clobber (reg:SI 1))]
9741 extern int frame_pointer_needed;
9743 /* We need two different versions depending on whether or not we
9744 need a frame pointer. Also note that we return to the instruction
9745 immediately after the branch rather than two instructions after the
9746 break as normally is the case. */
9747 if (frame_pointer_needed)
9749 /* Must import the magic millicode routine(s). */
9750 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
9752 if (TARGET_PORTABLE_RUNTIME)
9754 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
9755 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9759 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9763 /* Must import the magic millicode routine(s). */
9764 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9766 if (TARGET_PORTABLE_RUNTIME)
9768 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9769 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9772 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9776 [(set_attr "type" "multi")
9777 (set_attr "length" "8")])
9779 ;; An out-of-line epilogue.
9780 (define_insn "outline_epilogue_call"
9781 [(unspec_volatile [(const_int 1)] UNSPECV_OEC)
9784 (clobber (reg:SI 31))
9785 (clobber (reg:SI 22))
9786 (clobber (reg:SI 21))
9787 (clobber (reg:SI 20))
9788 (clobber (reg:SI 19))
9789 (clobber (reg:SI 2))
9790 (clobber (reg:SI 1))]
9794 extern int frame_pointer_needed;
9796 /* We need two different versions depending on whether or not we
9797 need a frame pointer. Also note that we return to the instruction
9798 immediately after the branch rather than two instructions after the
9799 break as normally is the case. */
9800 if (frame_pointer_needed)
9802 /* Must import the magic millicode routine. */
9803 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9805 /* The out-of-line prologue will make sure we return to the right
9807 if (TARGET_PORTABLE_RUNTIME)
9809 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9810 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9814 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9818 /* Must import the magic millicode routine. */
9819 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9821 /* The out-of-line prologue will make sure we return to the right
9823 if (TARGET_PORTABLE_RUNTIME)
9825 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9826 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9829 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9833 [(set_attr "type" "multi")
9834 (set_attr "length" "8")])
9836 ;; Given a function pointer, canonicalize it so it can be
9837 ;; reliably compared to another function pointer. */
9838 (define_expand "canonicalize_funcptr_for_compare"
9839 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9840 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9841 (clobber (match_dup 2))
9842 (clobber (reg:SI 26))
9843 (clobber (reg:SI 22))
9844 (clobber (reg:SI 31))])
9845 (set (match_operand:SI 0 "register_operand" "")
9847 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9852 rtx canonicalize_funcptr_for_compare_libfunc
9853 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9855 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9856 operands[0], LCT_NORMAL, Pmode,
9857 1, operands[1], Pmode);
9861 operands[2] = gen_reg_rtx (SImode);
9862 if (GET_CODE (operands[1]) != REG)
9864 rtx tmp = gen_reg_rtx (Pmode);
9865 emit_move_insn (tmp, operands[1]);
9870 (define_insn "*$$sh_func_adrs"
9871 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] UNSPEC_CFFC))
9872 (clobber (match_operand:SI 0 "register_operand" "=a"))
9873 (clobber (reg:SI 26))
9874 (clobber (reg:SI 22))
9875 (clobber (reg:SI 31))]
9879 int length = get_attr_length (insn);
9882 xoperands[0] = GEN_INT (length - 8);
9883 xoperands[1] = GEN_INT (length - 16);
9885 /* Must import the magic millicode routine. */
9886 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9888 /* This is absolutely amazing.
9890 First, copy our input parameter into %r29 just in case we don't
9891 need to call $$sh_func_adrs. */
9892 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9893 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9895 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9896 we use %r26 unchanged. */
9897 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9898 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9900 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9901 4096, then again we use %r26 unchanged. */
9902 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9904 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9905 return output_millicode_call (insn,
9906 gen_rtx_SYMBOL_REF (SImode,
9907 \"$$sh_func_adrs\"));
9909 [(set_attr "type" "multi")
9910 (set (attr "length")
9911 (plus (symbol_ref "attr_length_millicode_call (insn)")
9914 ;; On the PA, the PIC register is call clobbered, so it must
9915 ;; be saved & restored around calls by the caller. If the call
9916 ;; doesn't return normally (nonlocal goto, or an exception is
9917 ;; thrown), then the code at the exception handler label must
9918 ;; restore the PIC register.
9919 (define_expand "exception_receiver"
9924 /* On the 64-bit port, we need a blockage because there is
9925 confusion regarding the dependence of the restore on the
9926 frame pointer. As a result, the frame pointer and pic
9927 register restores sometimes are interchanged erroneously. */
9929 emit_insn (gen_blockage ());
9930 /* Restore the PIC register using hppa_pic_save_rtx (). The
9931 PIC register is not saved in the frame in 64-bit ABI. */
9932 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9933 emit_insn (gen_blockage ());
9937 (define_expand "builtin_setjmp_receiver"
9938 [(label_ref (match_operand 0 "" ""))]
9943 emit_insn (gen_blockage ());
9944 /* Restore the PIC register. Hopefully, this will always be from
9945 a stack slot. The only registers that are valid after a
9946 builtin_longjmp are the stack and frame pointers. */
9947 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9948 emit_insn (gen_blockage ());
9952 ;; Allocate new stack space and update the saved stack pointer in the
9953 ;; frame marker. The HP C compilers also copy additional words in the
9954 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9955 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9956 ;; currently don't copy these values.
9958 ;; Since the copy of the frame marker can't be done atomically, I
9959 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9960 ;; The HP compilers appear to raise the stack and copy the frame
9961 ;; marker in a strict instruction sequence. This suggests that the
9962 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9963 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9964 ;; as GAS doesn't support it, or try to keep the instructions emitted
9965 ;; here in strict sequence.
9966 (define_expand "allocate_stack"
9967 [(match_operand 0 "" "")
9968 (match_operand 1 "" "")]
9974 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9975 in operand 0 before adjusting the stack. */
9976 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9977 anti_adjust_stack (operands[1]);
9978 if (TARGET_HPUX_UNWIND_LIBRARY)
9980 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9981 GEN_INT (TARGET_64BIT ? -8 : -4));
9982 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9984 if (!TARGET_64BIT && flag_pic)
9986 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9987 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
9992 (define_expand "prefetch"
9993 [(match_operand 0 "address_operand" "")
9994 (match_operand 1 "const_int_operand" "")
9995 (match_operand 2 "const_int_operand" "")]
9998 int locality = INTVAL (operands[2]);
10000 gcc_assert (locality >= 0 && locality <= 3);
10002 /* Change operand[0] to a MEM as we don't have the infrastructure
10003 to output all the supported address modes for ldw/ldd when we use
10004 the address directly. However, we do have it for MEMs. */
10005 operands[0] = gen_rtx_MEM (QImode, operands[0]);
10007 /* If the address isn't valid for the prefetch, replace it. */
10010 if (!prefetch_nocc_operand (operands[0], QImode))
10012 = replace_equiv_address (operands[0],
10013 copy_to_mode_reg (Pmode,
10014 XEXP (operands[0], 0)));
10015 emit_insn (gen_prefetch_nocc (operands[0], operands[1], operands[2]));
10019 if (!prefetch_cc_operand (operands[0], QImode))
10021 = replace_equiv_address (operands[0],
10022 copy_to_mode_reg (Pmode,
10023 XEXP (operands[0], 0)));
10024 emit_insn (gen_prefetch_cc (operands[0], operands[1], operands[2]));
10029 (define_insn "prefetch_cc"
10030 [(prefetch (match_operand:QI 0 "prefetch_cc_operand" "RW")
10031 (match_operand:SI 1 "const_int_operand" "n")
10032 (match_operand:SI 2 "const_int_operand" "n"))]
10033 "TARGET_PA_20 && operands[2] == const0_rtx"
10035 /* The SL cache-control completor indicates good spatial locality but
10036 poor temporal locality. The ldw instruction with a target of general
10037 register 0 prefetches a cache line for a read. The ldd instruction
10038 prefetches a cache line for a write. */
10039 static const char * const instr[2] = {
10040 "ldw%M0,sl %0,%%r0",
10041 "ldd%M0,sl %0,%%r0"
10043 int read_or_write = INTVAL (operands[1]);
10045 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10047 return instr [read_or_write];
10049 [(set_attr "type" "load")
10050 (set_attr "length" "4")])
10052 (define_insn "prefetch_nocc"
10053 [(prefetch (match_operand:QI 0 "prefetch_nocc_operand" "A,RQ")
10054 (match_operand:SI 1 "const_int_operand" "n,n")
10055 (match_operand:SI 2 "const_int_operand" "n,n"))]
10056 "TARGET_PA_20 && operands[2] != const0_rtx"
10058 /* The ldw instruction with a target of general register 0 prefetches
10059 a cache line for a read. The ldd instruction prefetches a cache line
10061 static const char * const instr[2][2] = {
10071 int read_or_write = INTVAL (operands[1]);
10073 gcc_assert (which_alternative == 0 || which_alternative == 1);
10074 gcc_assert (read_or_write >= 0 && read_or_write <= 1);
10076 return instr [which_alternative][read_or_write];
10078 [(set_attr "type" "load")
10079 (set_attr "length" "4")])
10083 (define_insn "tgd_load"
10084 [(set (match_operand:SI 0 "register_operand" "=r")
10085 (unspec:SI [(match_operand 1 "tgd_symbolic_operand" "")] UNSPEC_TLSGD))
10086 (clobber (reg:SI 1))]
10091 return \"addil LT'%1-$tls_gdidx$,%%r19\;ldo RT'%1-$tls_gdidx$(%%r1),%0\";
10093 return \"addil LR'%1-$tls_gdidx$,%%r27\;ldo RR'%1-$tls_gdidx$(%%r1),%0\";
10095 [(set_attr "type" "multi")
10096 (set_attr "length" "8")])
10098 (define_insn "tld_load"
10099 [(set (match_operand:SI 0 "register_operand" "=r")
10100 (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")] UNSPEC_TLSLDM))
10101 (clobber (reg:SI 1))]
10106 return \"addil LT'%1-$tls_ldidx$,%%r19\;ldo RT'%1-$tls_ldidx$(%%r1),%0\";
10108 return \"addil LR'%1-$tls_ldidx$,%%r27\;ldo RR'%1-$tls_ldidx$(%%r1),%0\";
10110 [(set_attr "type" "multi")
10111 (set_attr "length" "8")])
10113 (define_insn "tld_offset_load"
10114 [(set (match_operand:SI 0 "register_operand" "=r")
10115 (plus:SI (unspec:SI [(match_operand 1 "tld_symbolic_operand" "")]
10117 (match_operand:SI 2 "register_operand" "r")))
10118 (clobber (reg:SI 1))]
10122 return \"addil LR'%1-$tls_dtpoff$,%2\;ldo RR'%1-$tls_dtpoff$(%%r1),%0\";
10124 [(set_attr "type" "multi")
10125 (set_attr "length" "8")])
10127 (define_insn "tp_load"
10128 [(set (match_operand:SI 0 "register_operand" "=r")
10129 (unspec:SI [(const_int 0)] UNSPEC_TP))]
10132 [(set_attr "type" "multi")
10133 (set_attr "length" "4")])
10135 (define_insn "tie_load"
10136 [(set (match_operand:SI 0 "register_operand" "=r")
10137 (unspec:SI [(match_operand 1 "tie_symbolic_operand" "")] UNSPEC_TLSIE))
10138 (clobber (reg:SI 1))]
10143 return \"addil LT'%1-$tls_ieoff$,%%r19\;ldw RT'%1-$tls_ieoff$(%%r1),%0\";
10145 return \"addil LR'%1-$tls_ieoff$,%%r27\;ldw RR'%1-$tls_ieoff$(%%r1),%0\";
10147 [(set_attr "type" "multi")
10148 (set_attr "length" "8")])
10150 (define_insn "tle_load"
10151 [(set (match_operand:SI 0 "register_operand" "=r")
10152 (plus:SI (unspec:SI [(match_operand 1 "tle_symbolic_operand" "")]
10154 (match_operand:SI 2 "register_operand" "r")))
10155 (clobber (reg:SI 1))]
10157 "addil LR'%1-$tls_leoff$,%2\;ldo RR'%1-$tls_leoff$(%%r1),%0"
10158 [(set_attr "type" "multi")
10159 (set_attr "length" "8")])