1 ;;- Machine description for HP PA-RISC architecture for GCC compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003, 2004 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GCC.
9 ;; GCC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GCC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GCC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "btable_branch,branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,btable_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "move_dest_operand"
2267 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
2268 (match_operand:SI 1 "move_src_operand"
2269 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && !TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2282 {mfctl|mfctl,w} %%sar,%0
2286 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
2287 (set_attr "pa_combine_type" "addmove")
2288 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
2291 [(set (match_operand:SI 0 "indexed_memory_operand" "=R")
2292 (match_operand:SI 1 "register_operand" "f"))]
2294 && !TARGET_DISABLE_INDEXING
2295 && reload_completed"
2297 [(set_attr "type" "fpstore")
2298 (set_attr "pa_combine_type" "addmove")
2299 (set_attr "length" "4")])
2301 ; Rewrite RTL using an indexed store. This will allow the insn that
2302 ; computes the address to be deleted if the register it sets is dead.
2304 [(set (match_operand:SI 0 "register_operand" "")
2305 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
2307 (match_operand:SI 2 "register_operand" "")))
2308 (set (mem:SI (match_dup 0))
2309 (match_operand:SI 3 "register_operand" ""))]
2311 && REG_OK_FOR_BASE_P (operands[2])
2312 && FP_REGNO_P (REGNO (operands[3]))"
2313 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2315 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2320 [(set (match_operand:SI 0 "register_operand" "")
2321 (plus:SI (match_operand:SI 2 "register_operand" "")
2322 (mult:SI (match_operand:SI 1 "register_operand" "")
2324 (set (mem:SI (match_dup 0))
2325 (match_operand:SI 3 "register_operand" ""))]
2327 && REG_OK_FOR_BASE_P (operands[2])
2328 && FP_REGNO_P (REGNO (operands[3]))"
2329 [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
2331 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
2336 [(set (match_operand:DI 0 "register_operand" "")
2337 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
2339 (match_operand:DI 2 "register_operand" "")))
2340 (set (mem:SI (match_dup 0))
2341 (match_operand:SI 3 "register_operand" ""))]
2344 && REG_OK_FOR_BASE_P (operands[2])
2345 && FP_REGNO_P (REGNO (operands[3]))"
2346 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2348 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2353 [(set (match_operand:DI 0 "register_operand" "")
2354 (plus:DI (match_operand:DI 2 "register_operand" "")
2355 (mult:DI (match_operand:DI 1 "register_operand" "")
2357 (set (mem:SI (match_dup 0))
2358 (match_operand:SI 3 "register_operand" ""))]
2361 && REG_OK_FOR_BASE_P (operands[2])
2362 && FP_REGNO_P (REGNO (operands[3]))"
2363 [(set (mem:SI (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
2365 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
2370 [(set (match_operand:SI 0 "register_operand" "")
2371 (plus:SI (match_operand:SI 1 "register_operand" "")
2372 (match_operand:SI 2 "register_operand" "")))
2373 (set (mem:SI (match_dup 0))
2374 (match_operand:SI 3 "register_operand" ""))]
2376 && REG_OK_FOR_BASE_P (operands[1])
2377 && (TARGET_NO_SPACE_REGS
2378 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2379 && FP_REGNO_P (REGNO (operands[3]))"
2380 [(set (mem:SI (plus:SI (match_dup 1) (match_dup 2)))
2382 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
2386 [(set (match_operand:SI 0 "register_operand" "")
2387 (plus:SI (match_operand:SI 1 "register_operand" "")
2388 (match_operand:SI 2 "register_operand" "")))
2389 (set (mem:SI (match_dup 0))
2390 (match_operand:SI 3 "register_operand" ""))]
2392 && REG_OK_FOR_BASE_P (operands[2])
2393 && (TARGET_NO_SPACE_REGS
2394 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2395 && FP_REGNO_P (REGNO (operands[3]))"
2396 [(set (mem:SI (plus:SI (match_dup 2) (match_dup 1)))
2398 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
2402 [(set (match_operand:DI 0 "register_operand" "")
2403 (plus:DI (match_operand:DI 1 "register_operand" "")
2404 (match_operand:DI 2 "register_operand" "")))
2405 (set (mem:SI (match_dup 0))
2406 (match_operand:SI 3 "register_operand" ""))]
2409 && REG_OK_FOR_BASE_P (operands[1])
2410 && (TARGET_NO_SPACE_REGS
2411 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
2412 && FP_REGNO_P (REGNO (operands[3]))"
2413 [(set (mem:SI (plus:DI (match_dup 1) (match_dup 2)))
2415 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
2419 [(set (match_operand:DI 0 "register_operand" "")
2420 (plus:DI (match_operand:DI 1 "register_operand" "")
2421 (match_operand:DI 2 "register_operand" "")))
2422 (set (mem:SI (match_dup 0))
2423 (match_operand:SI 3 "register_operand" ""))]
2426 && REG_OK_FOR_BASE_P (operands[2])
2427 && (TARGET_NO_SPACE_REGS
2428 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
2429 && FP_REGNO_P (REGNO (operands[3]))"
2430 [(set (mem:SI (plus:DI (match_dup 2) (match_dup 1)))
2432 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
2436 [(set (match_operand:SI 0 "move_dest_operand"
2437 "=r,r,r,r,r,r,Q,!*q,!r")
2438 (match_operand:SI 1 "move_src_operand"
2439 "A,r,J,N,K,RQ,rM,!rM,!*q"))]
2440 "(register_operand (operands[0], SImode)
2441 || reg_or_0_operand (operands[1], SImode))
2442 && TARGET_SOFT_FLOAT"
2448 {zdepi|depwi,z} %Z1,%0
2452 {mfctl|mfctl,w} %%sar,%0"
2453 [(set_attr "type" "load,move,move,move,move,load,store,move,move")
2454 (set_attr "pa_combine_type" "addmove")
2455 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2457 ;; Load or store with base-register modification.
2459 [(set (match_operand:SI 0 "register_operand" "=r")
2460 (mem:SI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2461 (match_operand:DI 2 "int5_operand" "L"))))
2463 (plus:DI (match_dup 1) (match_dup 2)))]
2466 [(set_attr "type" "load")
2467 (set_attr "length" "4")])
2469 ; And a zero extended variant.
2471 [(set (match_operand:DI 0 "register_operand" "=r")
2472 (zero_extend:DI (mem:SI
2474 (match_operand:DI 1 "register_operand" "+r")
2475 (match_operand:DI 2 "int5_operand" "L")))))
2477 (plus:DI (match_dup 1) (match_dup 2)))]
2480 [(set_attr "type" "load")
2481 (set_attr "length" "4")])
2483 (define_expand "pre_load"
2484 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2485 (mem (plus (match_operand 1 "register_operand" "")
2486 (match_operand 2 "pre_cint_operand" ""))))
2488 (plus (match_dup 1) (match_dup 2)))])]
2494 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2497 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2501 (define_insn "pre_ldw"
2502 [(set (match_operand:SI 0 "register_operand" "=r")
2503 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2504 (match_operand:SI 2 "pre_cint_operand" ""))))
2506 (plus:SI (match_dup 1) (match_dup 2)))]
2510 if (INTVAL (operands[2]) < 0)
2511 return \"{ldwm|ldw,mb} %2(%1),%0\";
2512 return \"{ldws|ldw},mb %2(%1),%0\";
2514 [(set_attr "type" "load")
2515 (set_attr "length" "4")])
2517 (define_insn "pre_ldd"
2518 [(set (match_operand:DI 0 "register_operand" "=r")
2519 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2520 (match_operand:DI 2 "pre_cint_operand" ""))))
2522 (plus:DI (match_dup 1) (match_dup 2)))]
2525 [(set_attr "type" "load")
2526 (set_attr "length" "4")])
2529 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2530 (match_operand:SI 1 "pre_cint_operand" "")))
2531 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2533 (plus:SI (match_dup 0) (match_dup 1)))]
2537 if (INTVAL (operands[1]) < 0)
2538 return \"{stwm|stw,mb} %r2,%1(%0)\";
2539 return \"{stws|stw},mb %r2,%1(%0)\";
2541 [(set_attr "type" "store")
2542 (set_attr "length" "4")])
2545 [(set (match_operand:SI 0 "register_operand" "=r")
2546 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2548 (plus:SI (match_dup 1)
2549 (match_operand:SI 2 "post_cint_operand" "")))]
2553 if (INTVAL (operands[2]) > 0)
2554 return \"{ldwm|ldw,ma} %2(%1),%0\";
2555 return \"{ldws|ldw},ma %2(%1),%0\";
2557 [(set_attr "type" "load")
2558 (set_attr "length" "4")])
2560 (define_expand "post_store"
2561 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2562 (match_operand 1 "reg_or_0_operand" ""))
2565 (match_operand 2 "post_cint_operand" "")))])]
2571 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2574 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2578 (define_insn "post_stw"
2579 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2580 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2582 (plus:SI (match_dup 0)
2583 (match_operand:SI 2 "post_cint_operand" "")))]
2587 if (INTVAL (operands[2]) > 0)
2588 return \"{stwm|stw,ma} %r1,%2(%0)\";
2589 return \"{stws|stw},ma %r1,%2(%0)\";
2591 [(set_attr "type" "store")
2592 (set_attr "length" "4")])
2594 (define_insn "post_std"
2595 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2596 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2598 (plus:DI (match_dup 0)
2599 (match_operand:DI 2 "post_cint_operand" "")))]
2602 [(set_attr "type" "store")
2603 (set_attr "length" "4")])
2605 ;; For loading the address of a label while generating PIC code.
2606 ;; Note since this pattern can be created at reload time (via movsi), all
2607 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2609 [(set (match_operand 0 "pmode_register_operand" "=a")
2610 (match_operand 1 "pic_label_operand" ""))]
2616 xoperands[0] = operands[0];
2617 xoperands[1] = operands[1];
2618 xoperands[2] = gen_label_rtx ();
2620 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2621 CODE_LABEL_NUMBER (xoperands[2]));
2622 output_asm_insn (\"mfia %0\", xoperands);
2624 /* If we're trying to load the address of a label that happens to be
2625 close, then we can use a shorter sequence. */
2626 if (GET_CODE (operands[1]) == LABEL_REF
2627 && INSN_ADDRESSES_SET_P ()
2628 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2629 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2630 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2633 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2634 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2638 [(set_attr "type" "multi")
2639 (set_attr "length" "12")]) ; 8 or 12
2642 [(set (match_operand 0 "pmode_register_operand" "=a")
2643 (match_operand 1 "pic_label_operand" ""))]
2649 xoperands[0] = operands[0];
2650 xoperands[1] = operands[1];
2651 xoperands[2] = gen_label_rtx ();
2653 output_asm_insn (\"bl .+8,%0\", xoperands);
2654 output_asm_insn (\"depi 0,31,2,%0\", xoperands);
2655 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2656 CODE_LABEL_NUMBER (xoperands[2]));
2658 /* If we're trying to load the address of a label that happens to be
2659 close, then we can use a shorter sequence. */
2660 if (GET_CODE (operands[1]) == LABEL_REF
2661 && INSN_ADDRESSES_SET_P ()
2662 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2663 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2664 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2667 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2668 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2672 [(set_attr "type" "multi")
2673 (set_attr "length" "16")]) ; 12 or 16
2676 [(set (match_operand:SI 0 "register_operand" "=a")
2677 (plus:SI (match_operand:SI 1 "register_operand" "r")
2678 (high:SI (match_operand 2 "" ""))))]
2679 "symbolic_operand (operands[2], Pmode)
2680 && ! function_label_operand (operands[2], Pmode)
2683 [(set_attr "type" "binary")
2684 (set_attr "length" "4")])
2687 [(set (match_operand:DI 0 "register_operand" "=a")
2688 (plus:DI (match_operand:DI 1 "register_operand" "r")
2689 (high:DI (match_operand 2 "" ""))))]
2690 "symbolic_operand (operands[2], Pmode)
2691 && ! function_label_operand (operands[2], Pmode)
2695 [(set_attr "type" "binary")
2696 (set_attr "length" "4")])
2698 ;; Always use addil rather than ldil;add sequences. This allows the
2699 ;; HP linker to eliminate the dp relocation if the symbolic operand
2700 ;; lives in the TEXT space.
2702 [(set (match_operand:SI 0 "register_operand" "=a")
2703 (high:SI (match_operand 1 "" "")))]
2704 "symbolic_operand (operands[1], Pmode)
2705 && ! function_label_operand (operands[1], Pmode)
2706 && ! read_only_operand (operands[1], Pmode)
2710 if (TARGET_LONG_LOAD_STORE)
2711 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2713 return \"addil LR'%H1,%%r27\";
2715 [(set_attr "type" "binary")
2716 (set (attr "length")
2717 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2722 ;; This is for use in the prologue/epilogue code. We need it
2723 ;; to add large constants to a stack pointer or frame pointer.
2724 ;; Because of the additional %r1 pressure, we probably do not
2725 ;; want to use this in general code, so make it available
2726 ;; only after reload.
2728 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2729 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2730 (high:SI (match_operand 2 "const_int_operand" ""))))]
2734 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2735 [(set_attr "type" "binary,binary")
2736 (set_attr "length" "4,8")])
2739 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2740 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2741 (high:DI (match_operand 2 "const_int_operand" ""))))]
2742 "reload_completed && TARGET_64BIT"
2745 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2746 [(set_attr "type" "binary,binary")
2747 (set_attr "length" "4,8")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (high:SI (match_operand 1 "" "")))]
2752 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2753 && !is_function_label_plus_const (operands[1])"
2756 if (symbolic_operand (operands[1], Pmode))
2757 return \"ldil LR'%H1,%0\";
2759 return \"ldil L'%G1,%0\";
2761 [(set_attr "type" "move")
2762 (set_attr "length" "4")])
2765 [(set (match_operand:DI 0 "register_operand" "=r")
2766 (high:DI (match_operand 1 "const_int_operand" "")))]
2769 [(set_attr "type" "move")
2770 (set_attr "length" "4")])
2773 [(set (match_operand:DI 0 "register_operand" "=r")
2774 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2775 (match_operand:DI 2 "const_int_operand" "i")))]
2778 [(set_attr "type" "move")
2779 (set_attr "length" "4")])
2782 [(set (match_operand:SI 0 "register_operand" "=r")
2783 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2784 (match_operand:SI 2 "immediate_operand" "i")))]
2785 "!is_function_label_plus_const (operands[2])"
2788 if (flag_pic && symbolic_operand (operands[2], Pmode))
2790 else if (symbolic_operand (operands[2], Pmode))
2791 return \"ldo RR'%G2(%1),%0\";
2793 return \"ldo R'%G2(%1),%0\";
2795 [(set_attr "type" "move")
2796 (set_attr "length" "4")])
2798 ;; Now that a symbolic_address plus a constant is broken up early
2799 ;; in the compilation phase (for better CSE) we need a special
2800 ;; combiner pattern to load the symbolic address plus the constant
2801 ;; in only 2 instructions. (For cases where the symbolic address
2802 ;; was not a common subexpression.)
2804 [(set (match_operand:SI 0 "register_operand" "")
2805 (match_operand:SI 1 "symbolic_operand" ""))
2806 (clobber (match_operand:SI 2 "register_operand" ""))]
2807 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2808 [(set (match_dup 2) (high:SI (match_dup 1)))
2809 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2812 ;; hppa_legitimize_address goes to a great deal of trouble to
2813 ;; create addresses which use indexing. In some cases, this
2814 ;; is a lose because there isn't any store instructions which
2815 ;; allow indexed addresses (with integer register source).
2817 ;; These define_splits try to turn a 3 insn store into
2818 ;; a 2 insn store with some creative RTL rewriting.
2820 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2821 (match_operand:SI 1 "shadd_operand" ""))
2822 (plus:SI (match_operand:SI 2 "register_operand" "")
2823 (match_operand:SI 3 "const_int_operand" ""))))
2824 (match_operand:SI 4 "register_operand" ""))
2825 (clobber (match_operand:SI 5 "register_operand" ""))]
2827 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2829 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2833 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2834 (match_operand:SI 1 "shadd_operand" ""))
2835 (plus:SI (match_operand:SI 2 "register_operand" "")
2836 (match_operand:SI 3 "const_int_operand" ""))))
2837 (match_operand:HI 4 "register_operand" ""))
2838 (clobber (match_operand:SI 5 "register_operand" ""))]
2840 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2842 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2846 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2847 (match_operand:SI 1 "shadd_operand" ""))
2848 (plus:SI (match_operand:SI 2 "register_operand" "")
2849 (match_operand:SI 3 "const_int_operand" ""))))
2850 (match_operand:QI 4 "register_operand" ""))
2851 (clobber (match_operand:SI 5 "register_operand" ""))]
2853 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2855 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2858 (define_expand "movhi"
2859 [(set (match_operand:HI 0 "general_operand" "")
2860 (match_operand:HI 1 "general_operand" ""))]
2864 if (emit_move_sequence (operands, HImode, 0))
2869 [(set (match_operand:HI 0 "move_dest_operand"
2870 "=r,r,r,r,r,Q,!*q,!r,!*f")
2871 (match_operand:HI 1 "move_src_operand"
2872 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2873 "register_operand (operands[0], HImode)
2874 || reg_or_0_operand (operands[1], HImode)"
2879 {zdepi|depwi,z} %Z1,%0
2885 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
2886 (set_attr "pa_combine_type" "addmove")
2887 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
2890 [(set (match_operand:HI 0 "register_operand" "=r")
2891 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2892 (match_operand:SI 2 "int5_operand" "L"))))
2894 (plus:SI (match_dup 1) (match_dup 2)))]
2896 "{ldhs|ldh},mb %2(%1),%0"
2897 [(set_attr "type" "load")
2898 (set_attr "length" "4")])
2901 [(set (match_operand:HI 0 "register_operand" "=r")
2902 (mem:HI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2903 (match_operand:DI 2 "int5_operand" "L"))))
2905 (plus:DI (match_dup 1) (match_dup 2)))]
2908 [(set_attr "type" "load")
2909 (set_attr "length" "4")])
2911 ; And a zero extended variant.
2913 [(set (match_operand:DI 0 "register_operand" "=r")
2914 (zero_extend:DI (mem:HI
2916 (match_operand:DI 1 "register_operand" "+r")
2917 (match_operand:DI 2 "int5_operand" "L")))))
2919 (plus:DI (match_dup 1) (match_dup 2)))]
2922 [(set_attr "type" "load")
2923 (set_attr "length" "4")])
2926 [(set (match_operand:SI 0 "register_operand" "=r")
2927 (zero_extend:SI (mem:HI
2929 (match_operand:SI 1 "register_operand" "+r")
2930 (match_operand:SI 2 "int5_operand" "L")))))
2932 (plus:SI (match_dup 1) (match_dup 2)))]
2934 "{ldhs|ldh},mb %2(%1),%0"
2935 [(set_attr "type" "load")
2936 (set_attr "length" "4")])
2939 [(set (match_operand:SI 0 "register_operand" "=r")
2940 (zero_extend:SI (mem:HI
2942 (match_operand:DI 1 "register_operand" "+r")
2943 (match_operand:DI 2 "int5_operand" "L")))))
2945 (plus:DI (match_dup 1) (match_dup 2)))]
2948 [(set_attr "type" "load")
2949 (set_attr "length" "4")])
2952 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2953 (match_operand:SI 1 "int5_operand" "L")))
2954 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2956 (plus:SI (match_dup 0) (match_dup 1)))]
2958 "{sths|sth},mb %r2,%1(%0)"
2959 [(set_attr "type" "store")
2960 (set_attr "length" "4")])
2963 [(set (mem:HI (plus:DI (match_operand:DI 0 "register_operand" "+r")
2964 (match_operand:DI 1 "int5_operand" "L")))
2965 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2967 (plus:DI (match_dup 0) (match_dup 1)))]
2970 [(set_attr "type" "store")
2971 (set_attr "length" "4")])
2974 [(set (match_operand:HI 0 "register_operand" "=r")
2975 (plus:HI (match_operand:HI 1 "register_operand" "r")
2976 (match_operand 2 "const_int_operand" "J")))]
2979 [(set_attr "type" "binary")
2980 (set_attr "pa_combine_type" "addmove")
2981 (set_attr "length" "4")])
2983 (define_expand "movqi"
2984 [(set (match_operand:QI 0 "general_operand" "")
2985 (match_operand:QI 1 "general_operand" ""))]
2989 if (emit_move_sequence (operands, QImode, 0))
2994 [(set (match_operand:QI 0 "move_dest_operand"
2995 "=r,r,r,r,r,Q,!*q,!r,!*f")
2996 (match_operand:QI 1 "move_src_operand"
2997 "r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
2998 "register_operand (operands[0], QImode)
2999 || reg_or_0_operand (operands[1], QImode)"
3004 {zdepi|depwi,z} %Z1,%0
3008 {mfctl|mfctl,w} %%sar,%0
3010 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu")
3011 (set_attr "pa_combine_type" "addmove")
3012 (set_attr "length" "4,4,4,4,4,4,4,4,4")])
3015 [(set (match_operand:QI 0 "register_operand" "=r")
3016 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
3017 (match_operand:SI 2 "int5_operand" "L"))))
3018 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3020 "{ldbs|ldb},mb %2(%1),%0"
3021 [(set_attr "type" "load")
3022 (set_attr "length" "4")])
3025 [(set (match_operand:QI 0 "register_operand" "=r")
3026 (mem:QI (plus:DI (match_operand:DI 1 "register_operand" "+r")
3027 (match_operand:DI 2 "int5_operand" "L"))))
3028 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3031 [(set_attr "type" "load")
3032 (set_attr "length" "4")])
3034 ; Now the same thing with zero extensions.
3036 [(set (match_operand:DI 0 "register_operand" "=r")
3037 (zero_extend:DI (mem:QI (plus:DI
3038 (match_operand:DI 1 "register_operand" "+r")
3039 (match_operand:DI 2 "int5_operand" "L")))))
3040 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3043 [(set_attr "type" "load")
3044 (set_attr "length" "4")])
3047 [(set (match_operand:SI 0 "register_operand" "=r")
3048 (zero_extend:SI (mem:QI (plus:SI
3049 (match_operand:SI 1 "register_operand" "+r")
3050 (match_operand:SI 2 "int5_operand" "L")))))
3051 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3053 "{ldbs|ldb},mb %2(%1),%0"
3054 [(set_attr "type" "load")
3055 (set_attr "length" "4")])
3058 [(set (match_operand:SI 0 "register_operand" "=r")
3059 (zero_extend:SI (mem:QI (plus:DI
3060 (match_operand:DI 1 "register_operand" "+r")
3061 (match_operand:DI 2 "int5_operand" "L")))))
3062 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3065 [(set_attr "type" "load")
3066 (set_attr "length" "4")])
3069 [(set (match_operand:HI 0 "register_operand" "=r")
3070 (zero_extend:HI (mem:QI (plus:SI
3071 (match_operand:SI 1 "register_operand" "+r")
3072 (match_operand:SI 2 "int5_operand" "L")))))
3073 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
3075 "{ldbs|ldb},mb %2(%1),%0"
3076 [(set_attr "type" "load")
3077 (set_attr "length" "4")])
3080 [(set (match_operand:HI 0 "register_operand" "=r")
3081 (zero_extend:HI (mem:QI (plus:DI
3082 (match_operand:DI 1 "register_operand" "+r")
3083 (match_operand:DI 2 "int5_operand" "L")))))
3084 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 2)))]
3087 [(set_attr "type" "load")
3088 (set_attr "length" "4")])
3091 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
3092 (match_operand:SI 1 "int5_operand" "L")))
3093 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3095 (plus:SI (match_dup 0) (match_dup 1)))]
3097 "{stbs|stb},mb %r2,%1(%0)"
3098 [(set_attr "type" "store")
3099 (set_attr "length" "4")])
3102 [(set (mem:QI (plus:DI (match_operand:DI 0 "register_operand" "+r")
3103 (match_operand:DI 1 "int5_operand" "L")))
3104 (match_operand:QI 2 "reg_or_0_operand" "rM"))
3106 (plus:DI (match_dup 0) (match_dup 1)))]
3109 [(set_attr "type" "store")
3110 (set_attr "length" "4")])
3112 ;; The definition of this insn does not really explain what it does,
3113 ;; but it should suffice that anything generated as this insn will be
3114 ;; recognized as a movstrsi operation, and that it will not successfully
3115 ;; combine with anything.
3116 (define_expand "movstrsi"
3117 [(parallel [(set (match_operand:BLK 0 "" "")
3118 (match_operand:BLK 1 "" ""))
3119 (clobber (match_dup 4))
3120 (clobber (match_dup 5))
3121 (clobber (match_dup 6))
3122 (clobber (match_dup 7))
3123 (clobber (match_dup 8))
3124 (use (match_operand:SI 2 "arith_operand" ""))
3125 (use (match_operand:SI 3 "const_int_operand" ""))])]
3126 "!TARGET_64BIT && optimize > 0"
3131 /* HP provides very fast block move library routine for the PA;
3132 this routine includes:
3134 4x4 byte at a time block moves,
3135 1x4 byte at a time with alignment checked at runtime with
3136 attempts to align the source and destination as needed
3139 With that in mind, here's the heuristics to try and guess when
3140 the inlined block move will be better than the library block
3143 If the size isn't constant, then always use the library routines.
3145 If the size is large in respect to the known alignment, then use
3146 the library routines.
3148 If the size is small in respect to the known alignment, then open
3149 code the copy (since that will lead to better scheduling).
3151 Else use the block move pattern. */
3153 /* Undetermined size, use the library routine. */
3154 if (GET_CODE (operands[2]) != CONST_INT)
3157 size = INTVAL (operands[2]);
3158 align = INTVAL (operands[3]);
3159 align = align > 4 ? 4 : align;
3161 /* If size/alignment is large, then use the library routines. */
3162 if (size / align > 16)
3165 /* This does happen, but not often enough to worry much about. */
3166 if (size / align < MOVE_RATIO)
3169 /* Fall through means we're going to use our block move pattern. */
3171 = replace_equiv_address (operands[0],
3172 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3174 = replace_equiv_address (operands[1],
3175 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3176 operands[4] = gen_reg_rtx (SImode);
3177 operands[5] = gen_reg_rtx (SImode);
3178 operands[6] = gen_reg_rtx (SImode);
3179 operands[7] = gen_reg_rtx (SImode);
3180 operands[8] = gen_reg_rtx (SImode);
3183 ;; The operand constraints are written like this to support both compile-time
3184 ;; and run-time determined byte counts. The expander and output_block_move
3185 ;; only support compile-time determined counts at this time.
3187 ;; If the count is run-time determined, the register with the byte count
3188 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3190 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3191 ;; broke this semantic for pseudo registers. We can't use match_scratch
3192 ;; as this requires two registers in the class R1_REGS when the MEMs for
3193 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3194 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3195 ;; respectively. We then split or peephole optimize after reload.
3196 (define_insn "movstrsi_prereload"
3197 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3198 (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
3199 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3200 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3201 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3202 (clobber (match_operand:SI 7 "register_operand" "=&r,&r")) ;item tmp3
3203 (clobber (match_operand:SI 8 "register_operand" "=&r,&r")) ;item tmp4
3204 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3205 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3208 [(set_attr "type" "multi,multi")])
3211 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3212 (match_operand:BLK 1 "memory_operand" ""))
3213 (clobber (match_operand:SI 2 "register_operand" ""))
3214 (clobber (match_operand:SI 3 "register_operand" ""))
3215 (clobber (match_operand:SI 6 "register_operand" ""))
3216 (clobber (match_operand:SI 7 "register_operand" ""))
3217 (clobber (match_operand:SI 8 "register_operand" ""))
3218 (use (match_operand:SI 4 "arith_operand" ""))
3219 (use (match_operand:SI 5 "const_int_operand" ""))])]
3220 "!TARGET_64BIT && reload_completed && !flag_peephole2
3221 && GET_CODE (operands[0]) == MEM
3222 && register_operand (XEXP (operands[0], 0), SImode)
3223 && GET_CODE (operands[1]) == MEM
3224 && register_operand (XEXP (operands[1], 0), SImode)"
3225 [(set (match_dup 7) (match_dup 9))
3226 (set (match_dup 8) (match_dup 10))
3227 (parallel [(set (match_dup 0) (match_dup 1))
3228 (clobber (match_dup 2))
3229 (clobber (match_dup 3))
3230 (clobber (match_dup 6))
3231 (clobber (match_dup 7))
3232 (clobber (match_dup 8))
3238 operands[9] = XEXP (operands[0], 0);
3239 operands[10] = XEXP (operands[1], 0);
3240 operands[0] = replace_equiv_address (operands[0], operands[7]);
3241 operands[1] = replace_equiv_address (operands[1], operands[8]);
3245 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3246 (match_operand:BLK 1 "memory_operand" ""))
3247 (clobber (match_operand:SI 2 "register_operand" ""))
3248 (clobber (match_operand:SI 3 "register_operand" ""))
3249 (clobber (match_operand:SI 6 "register_operand" ""))
3250 (clobber (match_operand:SI 7 "register_operand" ""))
3251 (clobber (match_operand:SI 8 "register_operand" ""))
3252 (use (match_operand:SI 4 "arith_operand" ""))
3253 (use (match_operand:SI 5 "const_int_operand" ""))])]
3255 && GET_CODE (operands[0]) == MEM
3256 && register_operand (XEXP (operands[0], 0), SImode)
3257 && GET_CODE (operands[1]) == MEM
3258 && register_operand (XEXP (operands[1], 0), SImode)"
3259 [(parallel [(set (match_dup 0) (match_dup 1))
3260 (clobber (match_dup 2))
3261 (clobber (match_dup 3))
3262 (clobber (match_dup 6))
3263 (clobber (match_dup 7))
3264 (clobber (match_dup 8))
3270 rtx addr = XEXP (operands[0], 0);
3271 if (dead_or_set_p (curr_insn, addr))
3275 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3276 operands[0] = replace_equiv_address (operands[0], operands[7]);
3279 addr = XEXP (operands[1], 0);
3280 if (dead_or_set_p (curr_insn, addr))
3284 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3285 operands[1] = replace_equiv_address (operands[1], operands[8]);
3289 (define_insn "movstrsi_postreload"
3290 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3291 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3292 (clobber (match_operand:SI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3293 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp1
3294 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3295 (clobber (match_dup 0))
3296 (clobber (match_dup 1))
3297 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3298 (use (match_operand:SI 5 "const_int_operand" "n,n")) ;alignment
3300 "!TARGET_64BIT && reload_completed"
3301 "* return output_block_move (operands, !which_alternative);"
3302 [(set_attr "type" "multi,multi")])
3304 (define_expand "movstrdi"
3305 [(parallel [(set (match_operand:BLK 0 "" "")
3306 (match_operand:BLK 1 "" ""))
3307 (clobber (match_dup 4))
3308 (clobber (match_dup 5))
3309 (clobber (match_dup 6))
3310 (clobber (match_dup 7))
3311 (clobber (match_dup 8))
3312 (use (match_operand:DI 2 "arith_operand" ""))
3313 (use (match_operand:DI 3 "const_int_operand" ""))])]
3314 "TARGET_64BIT && optimize > 0"
3319 /* HP provides very fast block move library routine for the PA;
3320 this routine includes:
3322 4x4 byte at a time block moves,
3323 1x4 byte at a time with alignment checked at runtime with
3324 attempts to align the source and destination as needed
3327 With that in mind, here's the heuristics to try and guess when
3328 the inlined block move will be better than the library block
3331 If the size isn't constant, then always use the library routines.
3333 If the size is large in respect to the known alignment, then use
3334 the library routines.
3336 If the size is small in respect to the known alignment, then open
3337 code the copy (since that will lead to better scheduling).
3339 Else use the block move pattern. */
3341 /* Undetermined size, use the library routine. */
3342 if (GET_CODE (operands[2]) != CONST_INT)
3345 size = INTVAL (operands[2]);
3346 align = INTVAL (operands[3]);
3347 align = align > 8 ? 8 : align;
3349 /* If size/alignment is large, then use the library routines. */
3350 if (size / align > 16)
3353 /* This does happen, but not often enough to worry much about. */
3354 if (size / align < MOVE_RATIO)
3357 /* Fall through means we're going to use our block move pattern. */
3359 = replace_equiv_address (operands[0],
3360 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3362 = replace_equiv_address (operands[1],
3363 copy_to_mode_reg (DImode, XEXP (operands[1], 0)));
3364 operands[4] = gen_reg_rtx (DImode);
3365 operands[5] = gen_reg_rtx (DImode);
3366 operands[6] = gen_reg_rtx (DImode);
3367 operands[7] = gen_reg_rtx (DImode);
3368 operands[8] = gen_reg_rtx (DImode);
3371 ;; The operand constraints are written like this to support both compile-time
3372 ;; and run-time determined byte counts. The expander and output_block_move
3373 ;; only support compile-time determined counts at this time.
3375 ;; If the count is run-time determined, the register with the byte count
3376 ;; is clobbered by the copying code, and therefore it is forced to operand 2.
3378 ;; We used to clobber operands 0 and 1. However, a change to regrename.c
3379 ;; broke this semantic for pseudo registers. We can't use match_scratch
3380 ;; as this requires two registers in the class R1_REGS when the MEMs for
3381 ;; operands 0 and 1 are both equivalent to symbolic MEMs. Thus, we are
3382 ;; forced to internally copy operands 0 and 1 to operands 7 and 8,
3383 ;; respectively. We then split or peephole optimize after reload.
3384 (define_insn "movstrdi_prereload"
3385 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3386 (mem:BLK (match_operand:DI 1 "register_operand" "r,r")))
3387 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3388 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3389 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3390 (clobber (match_operand:DI 7 "register_operand" "=&r,&r")) ;item tmp3
3391 (clobber (match_operand:DI 8 "register_operand" "=&r,&r")) ;item tmp4
3392 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3393 (use (match_operand:DI 5 "const_int_operand" "n,n"))] ;alignment
3396 [(set_attr "type" "multi,multi")])
3399 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3400 (match_operand:BLK 1 "memory_operand" ""))
3401 (clobber (match_operand:DI 2 "register_operand" ""))
3402 (clobber (match_operand:DI 3 "register_operand" ""))
3403 (clobber (match_operand:DI 6 "register_operand" ""))
3404 (clobber (match_operand:DI 7 "register_operand" ""))
3405 (clobber (match_operand:DI 8 "register_operand" ""))
3406 (use (match_operand:DI 4 "arith_operand" ""))
3407 (use (match_operand:DI 5 "const_int_operand" ""))])]
3408 "TARGET_64BIT && reload_completed && !flag_peephole2
3409 && GET_CODE (operands[0]) == MEM
3410 && register_operand (XEXP (operands[0], 0), DImode)
3411 && GET_CODE (operands[1]) == MEM
3412 && register_operand (XEXP (operands[1], 0), DImode)"
3413 [(set (match_dup 7) (match_dup 9))
3414 (set (match_dup 8) (match_dup 10))
3415 (parallel [(set (match_dup 0) (match_dup 1))
3416 (clobber (match_dup 2))
3417 (clobber (match_dup 3))
3418 (clobber (match_dup 6))
3419 (clobber (match_dup 7))
3420 (clobber (match_dup 8))
3426 operands[9] = XEXP (operands[0], 0);
3427 operands[10] = XEXP (operands[1], 0);
3428 operands[0] = replace_equiv_address (operands[0], operands[7]);
3429 operands[1] = replace_equiv_address (operands[1], operands[8]);
3433 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3434 (match_operand:BLK 1 "memory_operand" ""))
3435 (clobber (match_operand:DI 2 "register_operand" ""))
3436 (clobber (match_operand:DI 3 "register_operand" ""))
3437 (clobber (match_operand:DI 6 "register_operand" ""))
3438 (clobber (match_operand:DI 7 "register_operand" ""))
3439 (clobber (match_operand:DI 8 "register_operand" ""))
3440 (use (match_operand:DI 4 "arith_operand" ""))
3441 (use (match_operand:DI 5 "const_int_operand" ""))])]
3443 && GET_CODE (operands[0]) == MEM
3444 && register_operand (XEXP (operands[0], 0), DImode)
3445 && GET_CODE (operands[1]) == MEM
3446 && register_operand (XEXP (operands[1], 0), DImode)"
3447 [(parallel [(set (match_dup 0) (match_dup 1))
3448 (clobber (match_dup 2))
3449 (clobber (match_dup 3))
3450 (clobber (match_dup 6))
3451 (clobber (match_dup 7))
3452 (clobber (match_dup 8))
3458 rtx addr = XEXP (operands[0], 0);
3459 if (dead_or_set_p (curr_insn, addr))
3463 emit_insn (gen_rtx_SET (VOIDmode, operands[7], addr));
3464 operands[0] = replace_equiv_address (operands[0], operands[7]);
3467 addr = XEXP (operands[1], 0);
3468 if (dead_or_set_p (curr_insn, addr))
3472 emit_insn (gen_rtx_SET (VOIDmode, operands[8], addr));
3473 operands[1] = replace_equiv_address (operands[1], operands[8]);
3477 (define_insn "movstrdi_postreload"
3478 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3479 (mem:BLK (match_operand:DI 1 "register_operand" "+r,r")))
3480 (clobber (match_operand:DI 2 "register_operand" "=&r,&r")) ;loop cnt/tmp
3481 (clobber (match_operand:DI 3 "register_operand" "=&r,&r")) ;item tmp1
3482 (clobber (match_operand:DI 6 "register_operand" "=&r,&r")) ;item tmp2
3483 (clobber (match_dup 0))
3484 (clobber (match_dup 1))
3485 (use (match_operand:DI 4 "arith_operand" "J,2")) ;byte count
3486 (use (match_operand:DI 5 "const_int_operand" "n,n")) ;alignment
3488 "TARGET_64BIT && reload_completed"
3489 "* return output_block_move (operands, !which_alternative);"
3490 [(set_attr "type" "multi,multi")])
3492 (define_expand "clrstrsi"
3493 [(parallel [(set (match_operand:BLK 0 "" "")
3495 (clobber (match_dup 3))
3496 (clobber (match_dup 4))
3497 (use (match_operand:SI 1 "arith_operand" ""))
3498 (use (match_operand:SI 2 "const_int_operand" ""))])]
3499 "!TARGET_64BIT && optimize > 0"
3504 /* Undetermined size, use the library routine. */
3505 if (GET_CODE (operands[1]) != CONST_INT)
3508 size = INTVAL (operands[1]);
3509 align = INTVAL (operands[2]);
3510 align = align > 4 ? 4 : align;
3512 /* If size/alignment is large, then use the library routines. */
3513 if (size / align > 16)
3516 /* This does happen, but not often enough to worry much about. */
3517 if (size / align < MOVE_RATIO)
3520 /* Fall through means we're going to use our block clear pattern. */
3522 = replace_equiv_address (operands[0],
3523 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3524 operands[3] = gen_reg_rtx (SImode);
3525 operands[4] = gen_reg_rtx (SImode);
3528 (define_insn "clrstrsi_prereload"
3529 [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
3531 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3532 (clobber (match_operand:SI 4 "register_operand" "=&r,&r")) ;tmp1
3533 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3534 (use (match_operand:SI 3 "const_int_operand" "n,n"))] ;alignment
3537 [(set_attr "type" "multi,multi")])
3540 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3542 (clobber (match_operand:SI 1 "register_operand" ""))
3543 (clobber (match_operand:SI 4 "register_operand" ""))
3544 (use (match_operand:SI 2 "arith_operand" ""))
3545 (use (match_operand:SI 3 "const_int_operand" ""))])]
3546 "!TARGET_64BIT && reload_completed && !flag_peephole2
3547 && GET_CODE (operands[0]) == MEM
3548 && register_operand (XEXP (operands[0], 0), SImode)"
3549 [(set (match_dup 4) (match_dup 5))
3550 (parallel [(set (match_dup 0) (const_int 0))
3551 (clobber (match_dup 1))
3552 (clobber (match_dup 4))
3558 operands[5] = XEXP (operands[0], 0);
3559 operands[0] = replace_equiv_address (operands[0], operands[4]);
3563 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3565 (clobber (match_operand:SI 1 "register_operand" ""))
3566 (clobber (match_operand:SI 4 "register_operand" ""))
3567 (use (match_operand:SI 2 "arith_operand" ""))
3568 (use (match_operand:SI 3 "const_int_operand" ""))])]
3570 && GET_CODE (operands[0]) == MEM
3571 && register_operand (XEXP (operands[0], 0), SImode)"
3572 [(parallel [(set (match_dup 0) (const_int 0))
3573 (clobber (match_dup 1))
3574 (clobber (match_dup 4))
3580 rtx addr = XEXP (operands[0], 0);
3581 if (dead_or_set_p (curr_insn, addr))
3585 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3586 operands[0] = replace_equiv_address (operands[0], operands[4]);
3590 (define_insn "clrstrsi_postreload"
3591 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3593 (clobber (match_operand:SI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3594 (clobber (match_dup 0))
3595 (use (match_operand:SI 2 "arith_operand" "J,1")) ;byte count
3596 (use (match_operand:SI 3 "const_int_operand" "n,n")) ;alignment
3598 "!TARGET_64BIT && reload_completed"
3599 "* return output_block_clear (operands, !which_alternative);"
3600 [(set_attr "type" "multi,multi")])
3602 (define_expand "clrstrdi"
3603 [(parallel [(set (match_operand:BLK 0 "" "")
3605 (clobber (match_dup 3))
3606 (clobber (match_dup 4))
3607 (use (match_operand:DI 1 "arith_operand" ""))
3608 (use (match_operand:DI 2 "const_int_operand" ""))])]
3609 "TARGET_64BIT && optimize > 0"
3614 /* Undetermined size, use the library routine. */
3615 if (GET_CODE (operands[1]) != CONST_INT)
3618 size = INTVAL (operands[1]);
3619 align = INTVAL (operands[2]);
3620 align = align > 8 ? 8 : align;
3622 /* If size/alignment is large, then use the library routines. */
3623 if (size / align > 16)
3626 /* This does happen, but not often enough to worry much about. */
3627 if (size / align < MOVE_RATIO)
3630 /* Fall through means we're going to use our block clear pattern. */
3632 = replace_equiv_address (operands[0],
3633 copy_to_mode_reg (DImode, XEXP (operands[0], 0)));
3634 operands[3] = gen_reg_rtx (DImode);
3635 operands[4] = gen_reg_rtx (DImode);
3638 (define_insn "clrstrdi_prereload"
3639 [(set (mem:BLK (match_operand:DI 0 "register_operand" "r,r"))
3641 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3642 (clobber (match_operand:DI 4 "register_operand" "=&r,&r")) ;item tmp1
3643 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3644 (use (match_operand:DI 3 "const_int_operand" "n,n"))] ;alignment
3647 [(set_attr "type" "multi,multi")])
3650 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3652 (clobber (match_operand:DI 1 "register_operand" ""))
3653 (clobber (match_operand:DI 4 "register_operand" ""))
3654 (use (match_operand:DI 2 "arith_operand" ""))
3655 (use (match_operand:DI 3 "const_int_operand" ""))])]
3656 "TARGET_64BIT && reload_completed && !flag_peephole2
3657 && GET_CODE (operands[0]) == MEM
3658 && register_operand (XEXP (operands[0], 0), DImode)"
3659 [(set (match_dup 4) (match_dup 5))
3660 (parallel [(set (match_dup 0) (const_int 0))
3661 (clobber (match_dup 1))
3662 (clobber (match_dup 4))
3668 operands[5] = XEXP (operands[0], 0);
3669 operands[0] = replace_equiv_address (operands[0], operands[4]);
3673 [(parallel [(set (match_operand:BLK 0 "memory_operand" "")
3675 (clobber (match_operand:DI 1 "register_operand" ""))
3676 (clobber (match_operand:DI 4 "register_operand" ""))
3677 (use (match_operand:DI 2 "arith_operand" ""))
3678 (use (match_operand:DI 3 "const_int_operand" ""))])]
3680 && GET_CODE (operands[0]) == MEM
3681 && register_operand (XEXP (operands[0], 0), DImode)"
3682 [(parallel [(set (match_dup 0) (const_int 0))
3683 (clobber (match_dup 1))
3684 (clobber (match_dup 4))
3690 rtx addr = XEXP (operands[0], 0);
3691 if (dead_or_set_p (curr_insn, addr))
3695 emit_insn (gen_rtx_SET (VOIDmode, operands[4], addr));
3696 operands[0] = replace_equiv_address (operands[0], operands[4]);
3700 (define_insn "clrstrdi_postreload"
3701 [(set (mem:BLK (match_operand:DI 0 "register_operand" "+r,r"))
3703 (clobber (match_operand:DI 1 "register_operand" "=&r,&r")) ;loop cnt/tmp
3704 (clobber (match_dup 0))
3705 (use (match_operand:DI 2 "arith_operand" "J,1")) ;byte count
3706 (use (match_operand:DI 3 "const_int_operand" "n,n")) ;alignment
3708 "TARGET_64BIT && reload_completed"
3709 "* return output_block_clear (operands, !which_alternative);"
3710 [(set_attr "type" "multi,multi")])
3712 ;; Floating point move insns
3714 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3715 ;; to be reloaded by putting the constant into memory when
3716 ;; reg is a floating point register.
3718 ;; For integer registers we use ldil;ldo to set the appropriate
3721 ;; This must come before the movdf pattern, and it must be present
3722 ;; to handle obscure reloading cases.
3724 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3725 (match_operand:DF 1 "" "?F,m"))]
3726 "GET_CODE (operands[1]) == CONST_DOUBLE
3727 && operands[1] != CONST0_RTX (DFmode)
3729 && !TARGET_SOFT_FLOAT"
3730 "* return (which_alternative == 0 ? output_move_double (operands)
3731 : \"fldd%F1 %1,%0\");"
3732 [(set_attr "type" "move,fpload")
3733 (set_attr "length" "16,4")])
3735 (define_expand "movdf"
3736 [(set (match_operand:DF 0 "general_operand" "")
3737 (match_operand:DF 1 "general_operand" ""))]
3741 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3742 operands[1] = force_const_mem (DFmode, operands[1]);
3744 if (emit_move_sequence (operands, DFmode, 0))
3748 ;; Reloading an SImode or DImode value requires a scratch register if
3749 ;; going in to or out of float point registers.
3751 (define_expand "reload_indf"
3752 [(set (match_operand:DF 0 "register_operand" "=Z")
3753 (match_operand:DF 1 "non_hard_reg_operand" ""))
3754 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3758 if (emit_move_sequence (operands, DFmode, operands[2]))
3761 /* We don't want the clobber emitted, so handle this ourselves. */
3762 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3766 (define_expand "reload_outdf"
3767 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3768 (match_operand:DF 1 "register_operand" "Z"))
3769 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3773 if (emit_move_sequence (operands, DFmode, operands[2]))
3776 /* We don't want the clobber emitted, so handle this ourselves. */
3777 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3782 [(set (match_operand:DF 0 "move_dest_operand"
3783 "=f,*r,Q,?o,?Q,f,*r,*r")
3784 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3785 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3786 "(register_operand (operands[0], DFmode)
3787 || reg_or_0_operand (operands[1], DFmode))
3788 && !(GET_CODE (operands[1]) == CONST_DOUBLE
3789 && GET_CODE (operands[0]) == MEM)
3791 && !TARGET_SOFT_FLOAT"
3794 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3795 || operands[1] == CONST0_RTX (DFmode))
3796 return output_fp_move_double (operands);
3797 return output_move_double (operands);
3799 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3800 (set_attr "length" "4,8,4,8,16,4,8,16")])
3803 [(set (match_operand:DF 0 "indexed_memory_operand" "=R")
3804 (match_operand:DF 1 "reg_or_0_operand" "f"))]
3806 && !TARGET_DISABLE_INDEXING
3807 && reload_completed"
3809 [(set_attr "type" "fpstore")
3810 (set_attr "pa_combine_type" "addmove")
3811 (set_attr "length" "4")])
3814 [(set (match_operand:SI 0 "register_operand" "")
3815 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
3817 (match_operand:SI 2 "register_operand" "")))
3818 (set (mem:DF (match_dup 0))
3819 (match_operand:DF 3 "register_operand" ""))]
3821 && REG_OK_FOR_BASE_P (operands[2])
3822 && FP_REGNO_P (REGNO (operands[3]))"
3823 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3825 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3830 [(set (match_operand:SI 0 "register_operand" "")
3831 (plus:SI (match_operand:SI 2 "register_operand" "")
3832 (mult:SI (match_operand:SI 1 "register_operand" "")
3834 (set (mem:DF (match_dup 0))
3835 (match_operand:DF 3 "register_operand" ""))]
3837 && REG_OK_FOR_BASE_P (operands[2])
3838 && FP_REGNO_P (REGNO (operands[3]))"
3839 [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
3841 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 8))
3846 [(set (match_operand:DI 0 "register_operand" "")
3847 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
3849 (match_operand:DI 2 "register_operand" "")))
3850 (set (mem:DF (match_dup 0))
3851 (match_operand:DF 3 "register_operand" ""))]
3854 && REG_OK_FOR_BASE_P (operands[2])
3855 && FP_REGNO_P (REGNO (operands[3]))"
3856 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3858 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3863 [(set (match_operand:DI 0 "register_operand" "")
3864 (plus:DI (match_operand:DI 2 "register_operand" "")
3865 (mult:DI (match_operand:DI 1 "register_operand" "")
3867 (set (mem:DF (match_dup 0))
3868 (match_operand:DF 3 "register_operand" ""))]
3871 && REG_OK_FOR_BASE_P (operands[2])
3872 && FP_REGNO_P (REGNO (operands[3]))"
3873 [(set (mem:DF (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
3875 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
3880 [(set (match_operand:SI 0 "register_operand" "")
3881 (plus:SI (match_operand:SI 1 "register_operand" "")
3882 (match_operand:SI 2 "register_operand" "")))
3883 (set (mem:DF (match_dup 0))
3884 (match_operand:DF 3 "register_operand" ""))]
3886 && REG_OK_FOR_BASE_P (operands[1])
3887 && (TARGET_NO_SPACE_REGS
3888 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3889 && FP_REGNO_P (REGNO (operands[3]))"
3890 [(set (mem:DF (plus:SI (match_dup 1) (match_dup 2)))
3892 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
3896 [(set (match_operand:SI 0 "register_operand" "")
3897 (plus:SI (match_operand:SI 1 "register_operand" "")
3898 (match_operand:SI 2 "register_operand" "")))
3899 (set (mem:DF (match_dup 0))
3900 (match_operand:DF 3 "register_operand" ""))]
3902 && REG_OK_FOR_BASE_P (operands[2])
3903 && (TARGET_NO_SPACE_REGS
3904 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3905 && FP_REGNO_P (REGNO (operands[3]))"
3906 [(set (mem:DF (plus:SI (match_dup 2) (match_dup 1)))
3908 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
3912 [(set (match_operand:DI 0 "register_operand" "")
3913 (plus:DI (match_operand:DI 1 "register_operand" "")
3914 (match_operand:DI 2 "register_operand" "")))
3915 (set (mem:DF (match_dup 0))
3916 (match_operand:DF 3 "register_operand" ""))]
3919 && REG_OK_FOR_BASE_P (operands[1])
3920 && (TARGET_NO_SPACE_REGS
3921 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
3922 && FP_REGNO_P (REGNO (operands[3]))"
3923 [(set (mem:DF (plus:DI (match_dup 1) (match_dup 2)))
3925 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
3929 [(set (match_operand:DI 0 "register_operand" "")
3930 (plus:DI (match_operand:DI 1 "register_operand" "")
3931 (match_operand:DI 2 "register_operand" "")))
3932 (set (mem:DF (match_dup 0))
3933 (match_operand:DF 3 "register_operand" ""))]
3936 && REG_OK_FOR_BASE_P (operands[2])
3937 && (TARGET_NO_SPACE_REGS
3938 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
3939 && FP_REGNO_P (REGNO (operands[3]))"
3940 [(set (mem:DF (plus:DI (match_dup 2) (match_dup 1)))
3942 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
3946 [(set (match_operand:DF 0 "move_dest_operand"
3948 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3950 "(register_operand (operands[0], DFmode)
3951 || reg_or_0_operand (operands[1], DFmode))
3953 && TARGET_SOFT_FLOAT"
3956 return output_move_double (operands);
3958 [(set_attr "type" "move,store,store,load,load")
3959 (set_attr "length" "8,8,16,8,16")])
3962 [(set (match_operand:DF 0 "move_dest_operand"
3963 "=!*r,*r,*r,*r,*r,Q,!*q,!r,f,f,T")
3964 (match_operand:DF 1 "move_src_operand"
3965 "!*r,J,N,K,RQ,*rM,!*rM,!*q,fM,RT,f"))]
3966 "(register_operand (operands[0], DFmode)
3967 || reg_or_0_operand (operands[1], DFmode))
3968 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
3977 {mfctl|mfctl,w} %%sar,%0
3981 [(set_attr "type" "move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
3982 (set_attr "pa_combine_type" "addmove")
3983 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
3986 (define_expand "movdi"
3987 [(set (match_operand:DI 0 "general_operand" "")
3988 (match_operand:DI 1 "general_operand" ""))]
3992 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3993 operands[1] = force_const_mem (DImode, operands[1]);
3995 if (emit_move_sequence (operands, DImode, 0))
3999 (define_expand "reload_indi"
4000 [(set (match_operand:DI 0 "register_operand" "=Z")
4001 (match_operand:DI 1 "non_hard_reg_operand" ""))
4002 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4006 if (emit_move_sequence (operands, DImode, operands[2]))
4009 /* We don't want the clobber emitted, so handle this ourselves. */
4010 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4014 (define_expand "reload_outdi"
4015 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
4016 (match_operand:DI 1 "register_operand" "Z"))
4017 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
4021 if (emit_move_sequence (operands, DImode, operands[2]))
4024 /* We don't want the clobber emitted, so handle this ourselves. */
4025 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4030 [(set (match_operand:DI 0 "register_operand" "=r")
4031 (high:DI (match_operand 1 "" "")))]
4035 rtx op0 = operands[0];
4036 rtx op1 = operands[1];
4038 if (GET_CODE (op1) == CONST_INT)
4040 operands[0] = operand_subword (op0, 1, 0, DImode);
4041 output_asm_insn (\"ldil L'%1,%0\", operands);
4043 operands[0] = operand_subword (op0, 0, 0, DImode);
4044 if (INTVAL (op1) < 0)
4045 output_asm_insn (\"ldi -1,%0\", operands);
4047 output_asm_insn (\"ldi 0,%0\", operands);
4050 else if (GET_CODE (op1) == CONST_DOUBLE)
4052 operands[0] = operand_subword (op0, 1, 0, DImode);
4053 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
4054 output_asm_insn (\"ldil L'%1,%0\", operands);
4056 operands[0] = operand_subword (op0, 0, 0, DImode);
4057 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
4058 output_asm_insn (singlemove_string (operands), operands);
4064 [(set_attr "type" "move")
4065 (set_attr "length" "8")])
4068 [(set (match_operand:DI 0 "move_dest_operand"
4069 "=r,o,Q,r,r,r,*f,*f,T")
4070 (match_operand:DI 1 "general_operand"
4071 "rM,r,r,o*R,Q,i,*fM,RT,*f"))]
4072 "(register_operand (operands[0], DImode)
4073 || reg_or_0_operand (operands[1], DImode))
4075 && !TARGET_SOFT_FLOAT"
4078 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
4079 || (operands[1] == CONST0_RTX (DImode)))
4080 return output_fp_move_double (operands);
4081 return output_move_double (operands);
4083 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
4084 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
4087 [(set (match_operand:DI 0 "move_dest_operand"
4088 "=r,r,r,r,r,r,Q,!*q,!r,!*f,*f,T")
4089 (match_operand:DI 1 "move_src_operand"
4090 "A,r,J,N,K,RQ,rM,!rM,!*q,!*fM,RT,*f"))]
4091 "(register_operand (operands[0], DImode)
4092 || reg_or_0_operand (operands[1], DImode))
4093 && !TARGET_SOFT_FLOAT && TARGET_64BIT"
4103 {mfctl|mfctl,w} %%sar,%0
4107 [(set_attr "type" "load,move,move,move,shift,load,store,move,move,fpalu,fpload,fpstore")
4108 (set_attr "pa_combine_type" "addmove")
4109 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4")])
4112 [(set (match_operand:DI 0 "indexed_memory_operand" "=R")
4113 (match_operand:DI 1 "register_operand" "f"))]
4116 && !TARGET_DISABLE_INDEXING
4117 && reload_completed"
4119 [(set_attr "type" "fpstore")
4120 (set_attr "pa_combine_type" "addmove")
4121 (set_attr "length" "4")])
4124 [(set (match_operand:DI 0 "register_operand" "")
4125 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4127 (match_operand:DI 2 "register_operand" "")))
4128 (set (mem:DI (match_dup 0))
4129 (match_operand:DI 3 "register_operand" ""))]
4132 && REG_OK_FOR_BASE_P (operands[2])
4133 && FP_REGNO_P (REGNO (operands[3]))"
4134 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4136 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4141 [(set (match_operand:DI 0 "register_operand" "")
4142 (plus:DI (match_operand:DI 2 "register_operand" "")
4143 (mult:DI (match_operand:DI 1 "register_operand" "")
4145 (set (mem:DI (match_dup 0))
4146 (match_operand:DI 3 "register_operand" ""))]
4149 && REG_OK_FOR_BASE_P (operands[2])
4150 && FP_REGNO_P (REGNO (operands[3]))"
4151 [(set (mem:DI (plus:DI (mult:DI (match_dup 1) (const_int 8)) (match_dup 2)))
4153 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 8))
4158 [(set (match_operand:DI 0 "register_operand" "")
4159 (plus:DI (match_operand:DI 1 "register_operand" "")
4160 (match_operand:DI 2 "register_operand" "")))
4161 (set (mem:DI (match_dup 0))
4162 (match_operand:DI 3 "register_operand" ""))]
4165 && REG_OK_FOR_BASE_P (operands[1])
4166 && (TARGET_NO_SPACE_REGS
4167 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4168 && FP_REGNO_P (REGNO (operands[3]))"
4169 [(set (mem:DI (plus:DI (match_dup 1) (match_dup 2)))
4171 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4175 [(set (match_operand:DI 0 "register_operand" "")
4176 (plus:DI (match_operand:DI 1 "register_operand" "")
4177 (match_operand:DI 2 "register_operand" "")))
4178 (set (mem:DI (match_dup 0))
4179 (match_operand:DI 3 "register_operand" ""))]
4182 && REG_OK_FOR_BASE_P (operands[2])
4183 && (TARGET_NO_SPACE_REGS
4184 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4185 && FP_REGNO_P (REGNO (operands[3]))"
4186 [(set (mem:DI (plus:DI (match_dup 2) (match_dup 1)))
4188 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4192 [(set (match_operand:DI 0 "move_dest_operand"
4194 (match_operand:DI 1 "general_operand"
4196 "(register_operand (operands[0], DImode)
4197 || reg_or_0_operand (operands[1], DImode))
4199 && TARGET_SOFT_FLOAT"
4202 return output_move_double (operands);
4204 [(set_attr "type" "move,store,store,load,load,multi")
4205 (set_attr "length" "8,8,16,8,16,16")])
4208 [(set (match_operand:DI 0 "register_operand" "=r,&r")
4209 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
4210 (match_operand:DI 2 "immediate_operand" "i,i")))]
4214 /* Don't output a 64 bit constant, since we can't trust the assembler to
4215 handle it correctly. */
4216 if (GET_CODE (operands[2]) == CONST_DOUBLE)
4217 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
4218 if (which_alternative == 1)
4219 output_asm_insn (\"copy %1,%0\", operands);
4220 return \"ldo R'%G2(%R1),%R0\";
4222 [(set_attr "type" "move,move")
4223 (set_attr "length" "4,8")])
4225 ;; This pattern forces (set (reg:SF ...) (const_double ...))
4226 ;; to be reloaded by putting the constant into memory when
4227 ;; reg is a floating point register.
4229 ;; For integer registers we use ldil;ldo to set the appropriate
4232 ;; This must come before the movsf pattern, and it must be present
4233 ;; to handle obscure reloading cases.
4235 [(set (match_operand:SF 0 "register_operand" "=?r,f")
4236 (match_operand:SF 1 "" "?F,m"))]
4237 "GET_CODE (operands[1]) == CONST_DOUBLE
4238 && operands[1] != CONST0_RTX (SFmode)
4239 && ! TARGET_SOFT_FLOAT"
4240 "* return (which_alternative == 0 ? singlemove_string (operands)
4241 : \" fldw%F1 %1,%0\");"
4242 [(set_attr "type" "move,fpload")
4243 (set_attr "length" "8,4")])
4245 (define_expand "movsf"
4246 [(set (match_operand:SF 0 "general_operand" "")
4247 (match_operand:SF 1 "general_operand" ""))]
4251 if (emit_move_sequence (operands, SFmode, 0))
4255 ;; Reloading an SImode or DImode value requires a scratch register if
4256 ;; going in to or out of float point registers.
4258 (define_expand "reload_insf"
4259 [(set (match_operand:SF 0 "register_operand" "=Z")
4260 (match_operand:SF 1 "non_hard_reg_operand" ""))
4261 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4265 if (emit_move_sequence (operands, SFmode, operands[2]))
4268 /* We don't want the clobber emitted, so handle this ourselves. */
4269 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4273 (define_expand "reload_outsf"
4274 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
4275 (match_operand:SF 1 "register_operand" "Z"))
4276 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
4280 if (emit_move_sequence (operands, SFmode, operands[2]))
4283 /* We don't want the clobber emitted, so handle this ourselves. */
4284 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
4289 [(set (match_operand:SF 0 "move_dest_operand"
4291 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4292 "fG,!*rG,RQ,RQ,f,*rG"))]
4293 "(register_operand (operands[0], SFmode)
4294 || reg_or_0_operand (operands[1], SFmode))
4295 && !TARGET_SOFT_FLOAT"
4303 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
4304 (set_attr "pa_combine_type" "addmove")
4305 (set_attr "length" "4,4,4,4,4,4")])
4308 [(set (match_operand:SF 0 "indexed_memory_operand" "=R")
4309 (match_operand:SF 1 "register_operand" "f"))]
4311 && !TARGET_DISABLE_INDEXING
4312 && reload_completed"
4314 [(set_attr "type" "fpstore")
4315 (set_attr "pa_combine_type" "addmove")
4316 (set_attr "length" "4")])
4319 [(set (match_operand:SI 0 "register_operand" "")
4320 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "")
4322 (match_operand:SI 2 "register_operand" "")))
4323 (set (mem:SF (match_dup 0))
4324 (match_operand:SF 3 "register_operand" ""))]
4326 && REG_OK_FOR_BASE_P (operands[2])
4327 && FP_REGNO_P (REGNO (operands[3]))"
4328 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4330 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4335 [(set (match_operand:SI 0 "register_operand" "")
4336 (plus:SI (match_operand:SI 2 "register_operand" "")
4337 (mult:SI (match_operand:SI 1 "register_operand" "")
4339 (set (mem:SF (match_dup 0))
4340 (match_operand:SF 3 "register_operand" ""))]
4342 && REG_OK_FOR_BASE_P (operands[2])
4343 && FP_REGNO_P (REGNO (operands[3]))"
4344 [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
4346 (set (match_dup 0) (plus:SI (mult:SI (match_dup 1) (const_int 4))
4351 [(set (match_operand:DI 0 "register_operand" "")
4352 (plus:DI (mult:DI (match_operand:DI 1 "register_operand" "")
4354 (match_operand:DI 2 "register_operand" "")))
4355 (set (mem:SF (match_dup 0))
4356 (match_operand:SF 3 "register_operand" ""))]
4359 && REG_OK_FOR_BASE_P (operands[2])
4360 && FP_REGNO_P (REGNO (operands[3]))"
4361 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4363 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4368 [(set (match_operand:DI 0 "register_operand" "")
4369 (plus:DI (match_operand:DI 2 "register_operand" "")
4370 (mult:DI (match_operand:DI 1 "register_operand" "")
4372 (set (mem:SF (match_dup 0))
4373 (match_operand:SF 3 "register_operand" ""))]
4376 && REG_OK_FOR_BASE_P (operands[2])
4377 && FP_REGNO_P (REGNO (operands[3]))"
4378 [(set (mem:SF (plus:DI (mult:DI (match_dup 1) (const_int 4)) (match_dup 2)))
4380 (set (match_dup 0) (plus:DI (mult:DI (match_dup 1) (const_int 4))
4385 [(set (match_operand:SI 0 "register_operand" "")
4386 (plus:SI (match_operand:SI 1 "register_operand" "")
4387 (match_operand:SI 2 "register_operand" "")))
4388 (set (mem:SF (match_dup 0))
4389 (match_operand:SF 3 "register_operand" ""))]
4391 && REG_OK_FOR_BASE_P (operands[1])
4392 && (TARGET_NO_SPACE_REGS
4393 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4394 && FP_REGNO_P (REGNO (operands[3]))"
4395 [(set (mem:SF (plus:SI (match_dup 1) (match_dup 2)))
4397 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))]
4401 [(set (match_operand:SI 0 "register_operand" "")
4402 (plus:SI (match_operand:SI 1 "register_operand" "")
4403 (match_operand:SI 2 "register_operand" "")))
4404 (set (mem:SF (match_dup 0))
4405 (match_operand:SF 3 "register_operand" ""))]
4407 && REG_OK_FOR_BASE_P (operands[2])
4408 && (TARGET_NO_SPACE_REGS
4409 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4410 && FP_REGNO_P (REGNO (operands[3]))"
4411 [(set (mem:SF (plus:SI (match_dup 2) (match_dup 1)))
4413 (set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
4417 [(set (match_operand:DI 0 "register_operand" "")
4418 (plus:DI (match_operand:DI 1 "register_operand" "")
4419 (match_operand:DI 2 "register_operand" "")))
4420 (set (mem:SF (match_dup 0))
4421 (match_operand:SF 3 "register_operand" ""))]
4424 && REG_OK_FOR_BASE_P (operands[1])
4425 && (TARGET_NO_SPACE_REGS
4426 || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
4427 && FP_REGNO_P (REGNO (operands[3]))"
4428 [(set (mem:SF (plus:DI (match_dup 1) (match_dup 2)))
4430 (set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))]
4434 [(set (match_operand:DI 0 "register_operand" "")
4435 (plus:DI (match_operand:DI 1 "register_operand" "")
4436 (match_operand:DI 2 "register_operand" "")))
4437 (set (mem:SF (match_dup 0))
4438 (match_operand:SF 3 "register_operand" ""))]
4441 && REG_OK_FOR_BASE_P (operands[2])
4442 && (TARGET_NO_SPACE_REGS
4443 || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
4444 && FP_REGNO_P (REGNO (operands[3]))"
4445 [(set (mem:SF (plus:DI (match_dup 2) (match_dup 1)))
4447 (set (match_dup 0) (plus:DI (match_dup 2) (match_dup 1)))]
4451 [(set (match_operand:SF 0 "move_dest_operand"
4453 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
4455 "(register_operand (operands[0], SFmode)
4456 || reg_or_0_operand (operands[1], SFmode))
4457 && TARGET_SOFT_FLOAT"
4462 [(set_attr "type" "move,load,store")
4463 (set_attr "pa_combine_type" "addmove")
4464 (set_attr "length" "4,4,4")])
4468 ;;- zero extension instructions
4469 ;; We have define_expand for zero extension patterns to make sure the
4470 ;; operands get loaded into registers. The define_insns accept
4471 ;; memory operands. This gives us better overall code than just
4472 ;; having a pattern that does or does not accept memory operands.
4474 (define_expand "zero_extendqihi2"
4475 [(set (match_operand:HI 0 "register_operand" "")
4477 (match_operand:QI 1 "register_operand" "")))]
4482 [(set (match_operand:HI 0 "register_operand" "=r,r")
4484 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4485 "GET_CODE (operands[1]) != CONST_INT"
4487 {extru|extrw,u} %1,31,8,%0
4489 [(set_attr "type" "shift,load")
4490 (set_attr "length" "4,4")])
4492 (define_expand "zero_extendqisi2"
4493 [(set (match_operand:SI 0 "register_operand" "")
4495 (match_operand:QI 1 "register_operand" "")))]
4500 [(set (match_operand:SI 0 "register_operand" "=r,r")
4502 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4503 "GET_CODE (operands[1]) != CONST_INT"
4505 {extru|extrw,u} %1,31,8,%0
4507 [(set_attr "type" "shift,load")
4508 (set_attr "length" "4,4")])
4510 (define_expand "zero_extendhisi2"
4511 [(set (match_operand:SI 0 "register_operand" "")
4513 (match_operand:HI 1 "register_operand" "")))]
4518 [(set (match_operand:SI 0 "register_operand" "=r,r")
4520 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4521 "GET_CODE (operands[1]) != CONST_INT"
4523 {extru|extrw,u} %1,31,16,%0
4525 [(set_attr "type" "shift,load")
4526 (set_attr "length" "4,4")])
4528 (define_expand "zero_extendqidi2"
4529 [(set (match_operand:DI 0 "register_operand" "")
4531 (match_operand:QI 1 "register_operand" "")))]
4536 [(set (match_operand:DI 0 "register_operand" "=r,r")
4538 (match_operand:QI 1 "move_src_operand" "r,RQ")))]
4539 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4543 [(set_attr "type" "shift,load")
4544 (set_attr "length" "4,4")])
4546 (define_expand "zero_extendhidi2"
4547 [(set (match_operand:DI 0 "register_operand" "")
4549 (match_operand:HI 1 "register_operand" "")))]
4554 [(set (match_operand:DI 0 "register_operand" "=r,r")
4556 (match_operand:HI 1 "move_src_operand" "r,RQ")))]
4557 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4561 [(set_attr "type" "shift,load")
4562 (set_attr "length" "4,4")])
4564 (define_expand "zero_extendsidi2"
4565 [(set (match_operand:DI 0 "register_operand" "")
4567 (match_operand:SI 1 "register_operand" "")))]
4572 [(set (match_operand:DI 0 "register_operand" "=r,r")
4574 (match_operand:SI 1 "move_src_operand" "r,RQ")))]
4575 "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
4579 [(set_attr "type" "shift,load")
4580 (set_attr "length" "4,4")])
4582 ;;- sign extension instructions
4584 (define_insn "extendhisi2"
4585 [(set (match_operand:SI 0 "register_operand" "=r")
4586 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
4588 "{extrs|extrw,s} %1,31,16,%0"
4589 [(set_attr "type" "shift")
4590 (set_attr "length" "4")])
4592 (define_insn "extendqihi2"
4593 [(set (match_operand:HI 0 "register_operand" "=r")
4594 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
4596 "{extrs|extrw,s} %1,31,8,%0"
4597 [(set_attr "type" "shift")
4598 (set_attr "length" "4")])
4600 (define_insn "extendqisi2"
4601 [(set (match_operand:SI 0 "register_operand" "=r")
4602 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
4604 "{extrs|extrw,s} %1,31,8,%0"
4605 [(set_attr "type" "shift")
4606 (set_attr "length" "4")])
4608 (define_insn "extendqidi2"
4609 [(set (match_operand:DI 0 "register_operand" "=r")
4610 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
4612 "extrd,s %1,63,8,%0"
4613 [(set_attr "type" "shift")
4614 (set_attr "length" "4")])
4616 (define_insn "extendhidi2"
4617 [(set (match_operand:DI 0 "register_operand" "=r")
4618 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
4620 "extrd,s %1,63,16,%0"
4621 [(set_attr "type" "shift")
4622 (set_attr "length" "4")])
4624 (define_insn "extendsidi2"
4625 [(set (match_operand:DI 0 "register_operand" "=r")
4626 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
4628 "extrd,s %1,63,32,%0"
4629 [(set_attr "type" "shift")
4630 (set_attr "length" "4")])
4633 ;; Conversions between float and double.
4635 (define_insn "extendsfdf2"
4636 [(set (match_operand:DF 0 "register_operand" "=f")
4638 (match_operand:SF 1 "register_operand" "f")))]
4639 "! TARGET_SOFT_FLOAT"
4640 "{fcnvff|fcnv},sgl,dbl %1,%0"
4641 [(set_attr "type" "fpalu")
4642 (set_attr "length" "4")])
4644 (define_insn "truncdfsf2"
4645 [(set (match_operand:SF 0 "register_operand" "=f")
4647 (match_operand:DF 1 "register_operand" "f")))]
4648 "! TARGET_SOFT_FLOAT"
4649 "{fcnvff|fcnv},dbl,sgl %1,%0"
4650 [(set_attr "type" "fpalu")
4651 (set_attr "length" "4")])
4653 ;; Conversion between fixed point and floating point.
4654 ;; Note that among the fix-to-float insns
4655 ;; the ones that start with SImode come first.
4656 ;; That is so that an operand that is a CONST_INT
4657 ;; (and therefore lacks a specific machine mode).
4658 ;; will be recognized as SImode (which is always valid)
4659 ;; rather than as QImode or HImode.
4661 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
4662 ;; to be reloaded by putting the constant into memory.
4663 ;; It must come before the more general floatsisf2 pattern.
4665 [(set (match_operand:SF 0 "register_operand" "=f")
4666 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
4667 "! TARGET_SOFT_FLOAT"
4668 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
4669 [(set_attr "type" "fpalu")
4670 (set_attr "length" "8")])
4672 (define_insn "floatsisf2"
4673 [(set (match_operand:SF 0 "register_operand" "=f")
4674 (float:SF (match_operand:SI 1 "register_operand" "f")))]
4675 "! TARGET_SOFT_FLOAT"
4676 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
4677 [(set_attr "type" "fpalu")
4678 (set_attr "length" "4")])
4680 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
4681 ;; to be reloaded by putting the constant into memory.
4682 ;; It must come before the more general floatsidf2 pattern.
4684 [(set (match_operand:DF 0 "register_operand" "=f")
4685 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
4686 "! TARGET_SOFT_FLOAT"
4687 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
4688 [(set_attr "type" "fpalu")
4689 (set_attr "length" "8")])
4691 (define_insn "floatsidf2"
4692 [(set (match_operand:DF 0 "register_operand" "=f")
4693 (float:DF (match_operand:SI 1 "register_operand" "f")))]
4694 "! TARGET_SOFT_FLOAT"
4695 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
4696 [(set_attr "type" "fpalu")
4697 (set_attr "length" "4")])
4699 (define_expand "floatunssisf2"
4700 [(set (subreg:SI (match_dup 2) 4)
4701 (match_operand:SI 1 "register_operand" ""))
4702 (set (subreg:SI (match_dup 2) 0)
4704 (set (match_operand:SF 0 "register_operand" "")
4705 (float:SF (match_dup 2)))]
4706 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4711 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
4714 operands[2] = gen_reg_rtx (DImode);
4717 (define_expand "floatunssidf2"
4718 [(set (subreg:SI (match_dup 2) 4)
4719 (match_operand:SI 1 "register_operand" ""))
4720 (set (subreg:SI (match_dup 2) 0)
4722 (set (match_operand:DF 0 "register_operand" "")
4723 (float:DF (match_dup 2)))]
4724 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4729 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
4732 operands[2] = gen_reg_rtx (DImode);
4735 (define_insn "floatdisf2"
4736 [(set (match_operand:SF 0 "register_operand" "=f")
4737 (float:SF (match_operand:DI 1 "register_operand" "f")))]
4738 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4739 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
4740 [(set_attr "type" "fpalu")
4741 (set_attr "length" "4")])
4743 (define_insn "floatdidf2"
4744 [(set (match_operand:DF 0 "register_operand" "=f")
4745 (float:DF (match_operand:DI 1 "register_operand" "f")))]
4746 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4747 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
4748 [(set_attr "type" "fpalu")
4749 (set_attr "length" "4")])
4751 ;; Convert a float to an actual integer.
4752 ;; Truncation is performed as part of the conversion.
4754 (define_insn "fix_truncsfsi2"
4755 [(set (match_operand:SI 0 "register_operand" "=f")
4756 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4757 "! TARGET_SOFT_FLOAT"
4758 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
4759 [(set_attr "type" "fpalu")
4760 (set_attr "length" "4")])
4762 (define_insn "fix_truncdfsi2"
4763 [(set (match_operand:SI 0 "register_operand" "=f")
4764 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4765 "! TARGET_SOFT_FLOAT"
4766 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
4767 [(set_attr "type" "fpalu")
4768 (set_attr "length" "4")])
4770 (define_insn "fix_truncsfdi2"
4771 [(set (match_operand:DI 0 "register_operand" "=f")
4772 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4773 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4774 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
4775 [(set_attr "type" "fpalu")
4776 (set_attr "length" "4")])
4778 (define_insn "fix_truncdfdi2"
4779 [(set (match_operand:DI 0 "register_operand" "=f")
4780 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4781 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
4782 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
4783 [(set_attr "type" "fpalu")
4784 (set_attr "length" "4")])
4786 (define_insn "floatunssidf2_pa20"
4787 [(set (match_operand:DF 0 "register_operand" "=f")
4788 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
4789 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4791 [(set_attr "type" "fpalu")
4792 (set_attr "length" "4")])
4794 (define_insn "floatunssisf2_pa20"
4795 [(set (match_operand:SF 0 "register_operand" "=f")
4796 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
4797 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4799 [(set_attr "type" "fpalu")
4800 (set_attr "length" "4")])
4802 (define_insn "floatunsdisf2"
4803 [(set (match_operand:SF 0 "register_operand" "=f")
4804 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
4805 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4806 "fcnv,udw,sgl %1,%0"
4807 [(set_attr "type" "fpalu")
4808 (set_attr "length" "4")])
4810 (define_insn "floatunsdidf2"
4811 [(set (match_operand:DF 0 "register_operand" "=f")
4812 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
4813 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4814 "fcnv,udw,dbl %1,%0"
4815 [(set_attr "type" "fpalu")
4816 (set_attr "length" "4")])
4818 (define_insn "fixuns_truncsfsi2"
4819 [(set (match_operand:SI 0 "register_operand" "=f")
4820 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4821 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4822 "fcnv,t,sgl,uw %1,%0"
4823 [(set_attr "type" "fpalu")
4824 (set_attr "length" "4")])
4826 (define_insn "fixuns_truncdfsi2"
4827 [(set (match_operand:SI 0 "register_operand" "=f")
4828 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4829 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4830 "fcnv,t,dbl,uw %1,%0"
4831 [(set_attr "type" "fpalu")
4832 (set_attr "length" "4")])
4834 (define_insn "fixuns_truncsfdi2"
4835 [(set (match_operand:DI 0 "register_operand" "=f")
4836 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
4837 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4838 "fcnv,t,sgl,udw %1,%0"
4839 [(set_attr "type" "fpalu")
4840 (set_attr "length" "4")])
4842 (define_insn "fixuns_truncdfdi2"
4843 [(set (match_operand:DI 0 "register_operand" "=f")
4844 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
4845 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4846 "fcnv,t,dbl,udw %1,%0"
4847 [(set_attr "type" "fpalu")
4848 (set_attr "length" "4")])
4850 ;;- arithmetic instructions
4852 (define_expand "adddi3"
4853 [(set (match_operand:DI 0 "register_operand" "")
4854 (plus:DI (match_operand:DI 1 "register_operand" "")
4855 (match_operand:DI 2 "adddi3_operand" "")))]
4860 [(set (match_operand:DI 0 "register_operand" "=r")
4861 (plus:DI (match_operand:DI 1 "register_operand" "%r")
4862 (match_operand:DI 2 "arith11_operand" "rI")))]
4866 if (GET_CODE (operands[2]) == CONST_INT)
4868 if (INTVAL (operands[2]) >= 0)
4869 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
4871 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
4874 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
4876 [(set_attr "type" "binary")
4877 (set_attr "length" "8")])
4880 [(set (match_operand:DI 0 "register_operand" "=r,r")
4881 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
4882 (match_operand:DI 2 "arith_operand" "r,J")))]
4887 [(set_attr "type" "binary,binary")
4888 (set_attr "pa_combine_type" "addmove")
4889 (set_attr "length" "4,4")])
4892 [(set (match_operand:DI 0 "register_operand" "=r")
4893 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4894 (match_operand:DI 2 "register_operand" "r")))]
4897 [(set_attr "type" "binary")
4898 (set_attr "length" "4")])
4901 [(set (match_operand:SI 0 "register_operand" "=r")
4902 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4903 (match_operand:SI 2 "register_operand" "r")))]
4906 [(set_attr "type" "binary")
4907 (set_attr "length" "4")])
4909 ;; define_splits to optimize cases of adding a constant integer
4910 ;; to a register when the constant does not fit in 14 bits. */
4912 [(set (match_operand:SI 0 "register_operand" "")
4913 (plus:SI (match_operand:SI 1 "register_operand" "")
4914 (match_operand:SI 2 "const_int_operand" "")))
4915 (clobber (match_operand:SI 4 "register_operand" ""))]
4916 "! cint_ok_for_move (INTVAL (operands[2]))
4917 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
4918 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
4919 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
4922 int val = INTVAL (operands[2]);
4923 int low = (val < 0) ? -0x2000 : 0x1fff;
4924 int rest = val - low;
4926 operands[2] = GEN_INT (rest);
4927 operands[3] = GEN_INT (low);
4931 [(set (match_operand:SI 0 "register_operand" "")
4932 (plus:SI (match_operand:SI 1 "register_operand" "")
4933 (match_operand:SI 2 "const_int_operand" "")))
4934 (clobber (match_operand:SI 4 "register_operand" ""))]
4935 "! cint_ok_for_move (INTVAL (operands[2]))"
4936 [(set (match_dup 4) (match_dup 2))
4937 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
4941 HOST_WIDE_INT intval = INTVAL (operands[2]);
4943 /* Try dividing the constant by 2, then 4, and finally 8 to see
4944 if we can get a constant which can be loaded into a register
4945 in a single instruction (cint_ok_for_move).
4947 If that fails, try to negate the constant and subtract it
4948 from our input operand. */
4949 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
4951 operands[2] = GEN_INT (intval / 2);
4952 operands[3] = const2_rtx;
4954 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
4956 operands[2] = GEN_INT (intval / 4);
4957 operands[3] = GEN_INT (4);
4959 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
4961 operands[2] = GEN_INT (intval / 8);
4962 operands[3] = GEN_INT (8);
4964 else if (cint_ok_for_move (-intval))
4966 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
4967 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
4974 (define_insn "addsi3"
4975 [(set (match_operand:SI 0 "register_operand" "=r,r")
4976 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
4977 (match_operand:SI 2 "arith_operand" "r,J")))]
4980 {addl|add,l} %1,%2,%0
4982 [(set_attr "type" "binary,binary")
4983 (set_attr "pa_combine_type" "addmove")
4984 (set_attr "length" "4,4")])
4986 (define_expand "subdi3"
4987 [(set (match_operand:DI 0 "register_operand" "")
4988 (minus:DI (match_operand:DI 1 "register_operand" "")
4989 (match_operand:DI 2 "register_operand" "")))]
4994 [(set (match_operand:DI 0 "register_operand" "=r")
4995 (minus:DI (match_operand:DI 1 "register_operand" "r")
4996 (match_operand:DI 2 "register_operand" "r")))]
4998 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
4999 [(set_attr "type" "binary")
5000 (set_attr "length" "8")])
5003 [(set (match_operand:DI 0 "register_operand" "=r,r,!q")
5004 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,!U")
5005 (match_operand:DI 2 "register_operand" "r,r,!r")))]
5011 [(set_attr "type" "binary,binary,move")
5012 (set_attr "length" "4,4,4")])
5014 (define_expand "subsi3"
5015 [(set (match_operand:SI 0 "register_operand" "")
5016 (minus:SI (match_operand:SI 1 "arith11_operand" "")
5017 (match_operand:SI 2 "register_operand" "")))]
5022 [(set (match_operand:SI 0 "register_operand" "=r,r")
5023 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
5024 (match_operand:SI 2 "register_operand" "r,r")))]
5029 [(set_attr "type" "binary,binary")
5030 (set_attr "length" "4,4")])
5033 [(set (match_operand:SI 0 "register_operand" "=r,r,!q")
5034 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,!S")
5035 (match_operand:SI 2 "register_operand" "r,r,!r")))]
5041 [(set_attr "type" "binary,binary,move")
5042 (set_attr "length" "4,4,4")])
5044 ;; Clobbering a "register_operand" instead of a match_scratch
5045 ;; in operand3 of millicode calls avoids spilling %r1 and
5046 ;; produces better code.
5048 ;; The mulsi3 insns set up registers for the millicode call.
5049 (define_expand "mulsi3"
5050 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5051 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5052 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5053 (clobber (match_dup 3))
5054 (clobber (reg:SI 26))
5055 (clobber (reg:SI 25))
5056 (clobber (match_dup 4))])
5057 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5061 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5062 if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
5064 rtx scratch = gen_reg_rtx (DImode);
5065 operands[1] = force_reg (SImode, operands[1]);
5066 operands[2] = force_reg (SImode, operands[2]);
5067 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
5068 emit_insn (gen_movsi (operands[0],
5069 gen_rtx_SUBREG (SImode, scratch,
5070 GET_MODE_SIZE (SImode))));
5073 operands[3] = gen_reg_rtx (SImode);
5076 (define_insn "umulsidi3"
5077 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5078 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5079 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
5080 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5082 [(set_attr "type" "fpmuldbl")
5083 (set_attr "length" "4")])
5086 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5087 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5088 (match_operand:DI 2 "uint32_operand" "f")))]
5089 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
5091 [(set_attr "type" "fpmuldbl")
5092 (set_attr "length" "4")])
5095 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
5096 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
5097 (match_operand:DI 2 "uint32_operand" "f")))]
5098 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
5100 [(set_attr "type" "fpmuldbl")
5101 (set_attr "length" "4")])
5104 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5105 (clobber (match_operand:SI 0 "register_operand" "=a"))
5106 (clobber (reg:SI 26))
5107 (clobber (reg:SI 25))
5108 (clobber (reg:SI 31))]
5110 "* return output_mul_insn (0, insn);"
5111 [(set_attr "type" "milli")
5112 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5115 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
5116 (clobber (match_operand:SI 0 "register_operand" "=a"))
5117 (clobber (reg:SI 26))
5118 (clobber (reg:SI 25))
5119 (clobber (reg:SI 2))]
5121 "* return output_mul_insn (0, insn);"
5122 [(set_attr "type" "milli")
5123 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5125 (define_expand "muldi3"
5126 [(set (match_operand:DI 0 "register_operand" "")
5127 (mult:DI (match_operand:DI 1 "register_operand" "")
5128 (match_operand:DI 2 "register_operand" "")))]
5129 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
5132 rtx low_product = gen_reg_rtx (DImode);
5133 rtx cross_product1 = gen_reg_rtx (DImode);
5134 rtx cross_product2 = gen_reg_rtx (DImode);
5135 rtx cross_scratch = gen_reg_rtx (DImode);
5136 rtx cross_product = gen_reg_rtx (DImode);
5137 rtx op1l, op1r, op2l, op2r;
5138 rtx op1shifted, op2shifted;
5140 op1shifted = gen_reg_rtx (DImode);
5141 op2shifted = gen_reg_rtx (DImode);
5142 op1l = gen_reg_rtx (SImode);
5143 op1r = gen_reg_rtx (SImode);
5144 op2l = gen_reg_rtx (SImode);
5145 op2r = gen_reg_rtx (SImode);
5147 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
5149 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
5151 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
5152 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
5153 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
5154 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
5156 /* Emit multiplies for the cross products. */
5157 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
5158 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
5160 /* Emit a multiply for the low sub-word. */
5161 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
5163 /* Sum the cross products and shift them into proper position. */
5164 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
5165 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
5167 /* Add the cross product to the low product and store the result
5168 into the output operand . */
5169 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
5173 ;;; Division and mod.
5174 (define_expand "divsi3"
5175 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5176 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5177 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
5178 (clobber (match_dup 3))
5179 (clobber (match_dup 4))
5180 (clobber (reg:SI 26))
5181 (clobber (reg:SI 25))
5182 (clobber (match_dup 5))])
5183 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5187 operands[3] = gen_reg_rtx (SImode);
5190 operands[5] = gen_rtx_REG (SImode, 2);
5191 operands[4] = operands[5];
5195 operands[5] = gen_rtx_REG (SImode, 31);
5196 operands[4] = gen_reg_rtx (SImode);
5198 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
5204 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5205 (clobber (match_operand:SI 1 "register_operand" "=a"))
5206 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5207 (clobber (reg:SI 26))
5208 (clobber (reg:SI 25))
5209 (clobber (reg:SI 31))]
5212 return output_div_insn (operands, 0, insn);"
5213 [(set_attr "type" "milli")
5214 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5218 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5219 (clobber (match_operand:SI 1 "register_operand" "=a"))
5220 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5221 (clobber (reg:SI 26))
5222 (clobber (reg:SI 25))
5223 (clobber (reg:SI 2))]
5226 return output_div_insn (operands, 0, insn);"
5227 [(set_attr "type" "milli")
5228 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5230 (define_expand "udivsi3"
5231 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5232 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5233 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
5234 (clobber (match_dup 3))
5235 (clobber (match_dup 4))
5236 (clobber (reg:SI 26))
5237 (clobber (reg:SI 25))
5238 (clobber (match_dup 5))])
5239 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5243 operands[3] = gen_reg_rtx (SImode);
5247 operands[5] = gen_rtx_REG (SImode, 2);
5248 operands[4] = operands[5];
5252 operands[5] = gen_rtx_REG (SImode, 31);
5253 operands[4] = gen_reg_rtx (SImode);
5255 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
5261 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5262 (clobber (match_operand:SI 1 "register_operand" "=a"))
5263 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5264 (clobber (reg:SI 26))
5265 (clobber (reg:SI 25))
5266 (clobber (reg:SI 31))]
5269 return output_div_insn (operands, 1, insn);"
5270 [(set_attr "type" "milli")
5271 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5275 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
5276 (clobber (match_operand:SI 1 "register_operand" "=a"))
5277 (clobber (match_operand:SI 2 "register_operand" "=&r"))
5278 (clobber (reg:SI 26))
5279 (clobber (reg:SI 25))
5280 (clobber (reg:SI 2))]
5283 return output_div_insn (operands, 1, insn);"
5284 [(set_attr "type" "milli")
5285 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5287 (define_expand "modsi3"
5288 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5289 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5290 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5291 (clobber (match_dup 3))
5292 (clobber (match_dup 4))
5293 (clobber (reg:SI 26))
5294 (clobber (reg:SI 25))
5295 (clobber (match_dup 5))])
5296 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5302 operands[5] = gen_rtx_REG (SImode, 2);
5303 operands[4] = operands[5];
5307 operands[5] = gen_rtx_REG (SImode, 31);
5308 operands[4] = gen_reg_rtx (SImode);
5310 operands[3] = gen_reg_rtx (SImode);
5314 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5315 (clobber (match_operand:SI 0 "register_operand" "=a"))
5316 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5317 (clobber (reg:SI 26))
5318 (clobber (reg:SI 25))
5319 (clobber (reg:SI 31))]
5322 return output_mod_insn (0, insn);"
5323 [(set_attr "type" "milli")
5324 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5327 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
5328 (clobber (match_operand:SI 0 "register_operand" "=a"))
5329 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5330 (clobber (reg:SI 26))
5331 (clobber (reg:SI 25))
5332 (clobber (reg:SI 2))]
5335 return output_mod_insn (0, insn);"
5336 [(set_attr "type" "milli")
5337 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5339 (define_expand "umodsi3"
5340 [(set (reg:SI 26) (match_operand:SI 1 "move_src_operand" ""))
5341 (set (reg:SI 25) (match_operand:SI 2 "move_src_operand" ""))
5342 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5343 (clobber (match_dup 3))
5344 (clobber (match_dup 4))
5345 (clobber (reg:SI 26))
5346 (clobber (reg:SI 25))
5347 (clobber (match_dup 5))])
5348 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
5354 operands[5] = gen_rtx_REG (SImode, 2);
5355 operands[4] = operands[5];
5359 operands[5] = gen_rtx_REG (SImode, 31);
5360 operands[4] = gen_reg_rtx (SImode);
5362 operands[3] = gen_reg_rtx (SImode);
5366 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5367 (clobber (match_operand:SI 0 "register_operand" "=a"))
5368 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5369 (clobber (reg:SI 26))
5370 (clobber (reg:SI 25))
5371 (clobber (reg:SI 31))]
5374 return output_mod_insn (1, insn);"
5375 [(set_attr "type" "milli")
5376 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5379 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
5380 (clobber (match_operand:SI 0 "register_operand" "=a"))
5381 (clobber (match_operand:SI 1 "register_operand" "=&r"))
5382 (clobber (reg:SI 26))
5383 (clobber (reg:SI 25))
5384 (clobber (reg:SI 2))]
5387 return output_mod_insn (1, insn);"
5388 [(set_attr "type" "milli")
5389 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
5391 ;;- and instructions
5392 ;; We define DImode `and` so with DImode `not` we can get
5393 ;; DImode `andn`. Other combinations are possible.
5395 (define_expand "anddi3"
5396 [(set (match_operand:DI 0 "register_operand" "")
5397 (and:DI (match_operand:DI 1 "and_operand" "")
5398 (match_operand:DI 2 "and_operand" "")))]
5404 /* One operand must be a register operand. */
5405 if (!register_operand (operands[1], DImode)
5406 && !register_operand (operands[2], DImode))
5411 /* Both operands must be register operands. */
5412 if (!register_operand (operands[1], DImode)
5413 || !register_operand (operands[2], DImode))
5419 [(set (match_operand:DI 0 "register_operand" "=r")
5420 (and:DI (match_operand:DI 1 "register_operand" "%r")
5421 (match_operand:DI 2 "register_operand" "r")))]
5423 "and %1,%2,%0\;and %R1,%R2,%R0"
5424 [(set_attr "type" "binary")
5425 (set_attr "length" "8")])
5428 [(set (match_operand:DI 0 "register_operand" "=r,r")
5429 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
5430 (match_operand:DI 2 "and_operand" "rO,P")))]
5432 "* return output_64bit_and (operands); "
5433 [(set_attr "type" "binary")
5434 (set_attr "length" "4")])
5436 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
5437 ; constant with ldil;ldo.
5438 (define_insn "andsi3"
5439 [(set (match_operand:SI 0 "register_operand" "=r,r")
5440 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
5441 (match_operand:SI 2 "and_operand" "rO,P")))]
5443 "* return output_and (operands); "
5444 [(set_attr "type" "binary,shift")
5445 (set_attr "length" "4,4")])
5448 [(set (match_operand:DI 0 "register_operand" "=r")
5449 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5450 (match_operand:DI 2 "register_operand" "r")))]
5452 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
5453 [(set_attr "type" "binary")
5454 (set_attr "length" "8")])
5457 [(set (match_operand:DI 0 "register_operand" "=r")
5458 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
5459 (match_operand:DI 2 "register_operand" "r")))]
5462 [(set_attr "type" "binary")
5463 (set_attr "length" "4")])
5466 [(set (match_operand:SI 0 "register_operand" "=r")
5467 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
5468 (match_operand:SI 2 "register_operand" "r")))]
5471 [(set_attr "type" "binary")
5472 (set_attr "length" "4")])
5474 (define_expand "iordi3"
5475 [(set (match_operand:DI 0 "register_operand" "")
5476 (ior:DI (match_operand:DI 1 "ior_operand" "")
5477 (match_operand:DI 2 "ior_operand" "")))]
5483 /* One operand must be a register operand. */
5484 if (!register_operand (operands[1], DImode)
5485 && !register_operand (operands[2], DImode))
5490 /* Both operands must be register operands. */
5491 if (!register_operand (operands[1], DImode)
5492 || !register_operand (operands[2], DImode))
5498 [(set (match_operand:DI 0 "register_operand" "=r")
5499 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5500 (match_operand:DI 2 "register_operand" "r")))]
5502 "or %1,%2,%0\;or %R1,%R2,%R0"
5503 [(set_attr "type" "binary")
5504 (set_attr "length" "8")])
5507 [(set (match_operand:DI 0 "register_operand" "=r,r")
5508 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
5509 (match_operand:DI 2 "ior_operand" "M,i")))]
5511 "* return output_64bit_ior (operands); "
5512 [(set_attr "type" "binary,shift")
5513 (set_attr "length" "4,4")])
5516 [(set (match_operand:DI 0 "register_operand" "=r")
5517 (ior:DI (match_operand:DI 1 "register_operand" "%r")
5518 (match_operand:DI 2 "register_operand" "r")))]
5521 [(set_attr "type" "binary")
5522 (set_attr "length" "4")])
5524 ;; Need a define_expand because we've run out of CONST_OK... characters.
5525 (define_expand "iorsi3"
5526 [(set (match_operand:SI 0 "register_operand" "")
5527 (ior:SI (match_operand:SI 1 "register_operand" "")
5528 (match_operand:SI 2 "arith32_operand" "")))]
5532 if (! (ior_operand (operands[2], SImode)
5533 || register_operand (operands[2], SImode)))
5534 operands[2] = force_reg (SImode, operands[2]);
5538 [(set (match_operand:SI 0 "register_operand" "=r,r")
5539 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
5540 (match_operand:SI 2 "ior_operand" "M,i")))]
5542 "* return output_ior (operands); "
5543 [(set_attr "type" "binary,shift")
5544 (set_attr "length" "4,4")])
5547 [(set (match_operand:SI 0 "register_operand" "=r")
5548 (ior:SI (match_operand:SI 1 "register_operand" "%r")
5549 (match_operand:SI 2 "register_operand" "r")))]
5552 [(set_attr "type" "binary")
5553 (set_attr "length" "4")])
5555 (define_expand "xordi3"
5556 [(set (match_operand:DI 0 "register_operand" "")
5557 (xor:DI (match_operand:DI 1 "register_operand" "")
5558 (match_operand:DI 2 "register_operand" "")))]
5565 [(set (match_operand:DI 0 "register_operand" "=r")
5566 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5567 (match_operand:DI 2 "register_operand" "r")))]
5569 "xor %1,%2,%0\;xor %R1,%R2,%R0"
5570 [(set_attr "type" "binary")
5571 (set_attr "length" "8")])
5574 [(set (match_operand:DI 0 "register_operand" "=r")
5575 (xor:DI (match_operand:DI 1 "register_operand" "%r")
5576 (match_operand:DI 2 "register_operand" "r")))]
5579 [(set_attr "type" "binary")
5580 (set_attr "length" "4")])
5582 (define_insn "xorsi3"
5583 [(set (match_operand:SI 0 "register_operand" "=r")
5584 (xor:SI (match_operand:SI 1 "register_operand" "%r")
5585 (match_operand:SI 2 "register_operand" "r")))]
5588 [(set_attr "type" "binary")
5589 (set_attr "length" "4")])
5591 (define_expand "negdi2"
5592 [(set (match_operand:DI 0 "register_operand" "")
5593 (neg:DI (match_operand:DI 1 "register_operand" "")))]
5598 [(set (match_operand:DI 0 "register_operand" "=r")
5599 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5601 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
5602 [(set_attr "type" "unary")
5603 (set_attr "length" "8")])
5606 [(set (match_operand:DI 0 "register_operand" "=r")
5607 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
5610 [(set_attr "type" "unary")
5611 (set_attr "length" "4")])
5613 (define_insn "negsi2"
5614 [(set (match_operand:SI 0 "register_operand" "=r")
5615 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
5618 [(set_attr "type" "unary")
5619 (set_attr "length" "4")])
5621 (define_expand "one_cmpldi2"
5622 [(set (match_operand:DI 0 "register_operand" "")
5623 (not:DI (match_operand:DI 1 "register_operand" "")))]
5630 [(set (match_operand:DI 0 "register_operand" "=r")
5631 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5633 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
5634 [(set_attr "type" "unary")
5635 (set_attr "length" "8")])
5638 [(set (match_operand:DI 0 "register_operand" "=r")
5639 (not:DI (match_operand:DI 1 "register_operand" "r")))]
5642 [(set_attr "type" "unary")
5643 (set_attr "length" "4")])
5645 (define_insn "one_cmplsi2"
5646 [(set (match_operand:SI 0 "register_operand" "=r")
5647 (not:SI (match_operand:SI 1 "register_operand" "r")))]
5650 [(set_attr "type" "unary")
5651 (set_attr "length" "4")])
5653 ;; Floating point arithmetic instructions.
5655 (define_insn "adddf3"
5656 [(set (match_operand:DF 0 "register_operand" "=f")
5657 (plus:DF (match_operand:DF 1 "register_operand" "f")
5658 (match_operand:DF 2 "register_operand" "f")))]
5659 "! TARGET_SOFT_FLOAT"
5661 [(set_attr "type" "fpalu")
5662 (set_attr "pa_combine_type" "faddsub")
5663 (set_attr "length" "4")])
5665 (define_insn "addsf3"
5666 [(set (match_operand:SF 0 "register_operand" "=f")
5667 (plus:SF (match_operand:SF 1 "register_operand" "f")
5668 (match_operand:SF 2 "register_operand" "f")))]
5669 "! TARGET_SOFT_FLOAT"
5671 [(set_attr "type" "fpalu")
5672 (set_attr "pa_combine_type" "faddsub")
5673 (set_attr "length" "4")])
5675 (define_insn "subdf3"
5676 [(set (match_operand:DF 0 "register_operand" "=f")
5677 (minus:DF (match_operand:DF 1 "register_operand" "f")
5678 (match_operand:DF 2 "register_operand" "f")))]
5679 "! TARGET_SOFT_FLOAT"
5681 [(set_attr "type" "fpalu")
5682 (set_attr "pa_combine_type" "faddsub")
5683 (set_attr "length" "4")])
5685 (define_insn "subsf3"
5686 [(set (match_operand:SF 0 "register_operand" "=f")
5687 (minus:SF (match_operand:SF 1 "register_operand" "f")
5688 (match_operand:SF 2 "register_operand" "f")))]
5689 "! TARGET_SOFT_FLOAT"
5691 [(set_attr "type" "fpalu")
5692 (set_attr "pa_combine_type" "faddsub")
5693 (set_attr "length" "4")])
5695 (define_insn "muldf3"
5696 [(set (match_operand:DF 0 "register_operand" "=f")
5697 (mult:DF (match_operand:DF 1 "register_operand" "f")
5698 (match_operand:DF 2 "register_operand" "f")))]
5699 "! TARGET_SOFT_FLOAT"
5701 [(set_attr "type" "fpmuldbl")
5702 (set_attr "pa_combine_type" "fmpy")
5703 (set_attr "length" "4")])
5705 (define_insn "mulsf3"
5706 [(set (match_operand:SF 0 "register_operand" "=f")
5707 (mult:SF (match_operand:SF 1 "register_operand" "f")
5708 (match_operand:SF 2 "register_operand" "f")))]
5709 "! TARGET_SOFT_FLOAT"
5711 [(set_attr "type" "fpmulsgl")
5712 (set_attr "pa_combine_type" "fmpy")
5713 (set_attr "length" "4")])
5715 (define_insn "divdf3"
5716 [(set (match_operand:DF 0 "register_operand" "=f")
5717 (div:DF (match_operand:DF 1 "register_operand" "f")
5718 (match_operand:DF 2 "register_operand" "f")))]
5719 "! TARGET_SOFT_FLOAT"
5721 [(set_attr "type" "fpdivdbl")
5722 (set_attr "length" "4")])
5724 (define_insn "divsf3"
5725 [(set (match_operand:SF 0 "register_operand" "=f")
5726 (div:SF (match_operand:SF 1 "register_operand" "f")
5727 (match_operand:SF 2 "register_operand" "f")))]
5728 "! TARGET_SOFT_FLOAT"
5730 [(set_attr "type" "fpdivsgl")
5731 (set_attr "length" "4")])
5733 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
5734 ;; negation can be done by subtracting from plus zero. However, this
5735 ;; violates the IEEE standard when negating plus and minus zero.
5736 (define_expand "negdf2"
5737 [(parallel [(set (match_operand:DF 0 "register_operand" "")
5738 (neg:DF (match_operand:DF 1 "register_operand" "")))
5739 (use (match_dup 2))])]
5740 "! TARGET_SOFT_FLOAT"
5742 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5743 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
5746 operands[2] = force_reg (DFmode,
5747 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
5748 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
5753 (define_insn "negdf2_fast"
5754 [(set (match_operand:DF 0 "register_operand" "=f")
5755 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
5756 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5760 return \"fneg,dbl %1,%0\";
5762 return \"fsub,dbl %%fr0,%1,%0\";
5764 [(set_attr "type" "fpalu")
5765 (set_attr "length" "4")])
5767 (define_expand "negsf2"
5768 [(parallel [(set (match_operand:SF 0 "register_operand" "")
5769 (neg:SF (match_operand:SF 1 "register_operand" "")))
5770 (use (match_dup 2))])]
5771 "! TARGET_SOFT_FLOAT"
5773 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
5774 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
5777 operands[2] = force_reg (SFmode,
5778 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
5779 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
5784 (define_insn "negsf2_fast"
5785 [(set (match_operand:SF 0 "register_operand" "=f")
5786 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
5787 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
5791 return \"fneg,sgl %1,%0\";
5793 return \"fsub,sgl %%fr0,%1,%0\";
5795 [(set_attr "type" "fpalu")
5796 (set_attr "length" "4")])
5798 (define_insn "absdf2"
5799 [(set (match_operand:DF 0 "register_operand" "=f")
5800 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
5801 "! TARGET_SOFT_FLOAT"
5803 [(set_attr "type" "fpalu")
5804 (set_attr "length" "4")])
5806 (define_insn "abssf2"
5807 [(set (match_operand:SF 0 "register_operand" "=f")
5808 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
5809 "! TARGET_SOFT_FLOAT"
5811 [(set_attr "type" "fpalu")
5812 (set_attr "length" "4")])
5814 (define_insn "sqrtdf2"
5815 [(set (match_operand:DF 0 "register_operand" "=f")
5816 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
5817 "! TARGET_SOFT_FLOAT"
5819 [(set_attr "type" "fpsqrtdbl")
5820 (set_attr "length" "4")])
5822 (define_insn "sqrtsf2"
5823 [(set (match_operand:SF 0 "register_operand" "=f")
5824 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
5825 "! TARGET_SOFT_FLOAT"
5827 [(set_attr "type" "fpsqrtsgl")
5828 (set_attr "length" "4")])
5830 ;; PA 2.0 floating point instructions
5834 [(set (match_operand:DF 0 "register_operand" "=f")
5835 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5836 (match_operand:DF 2 "register_operand" "f"))
5837 (match_operand:DF 3 "register_operand" "f")))]
5838 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5839 "fmpyfadd,dbl %1,%2,%3,%0"
5840 [(set_attr "type" "fpmuldbl")
5841 (set_attr "length" "4")])
5844 [(set (match_operand:DF 0 "register_operand" "=f")
5845 (plus:DF (match_operand:DF 1 "register_operand" "f")
5846 (mult:DF (match_operand:DF 2 "register_operand" "f")
5847 (match_operand:DF 3 "register_operand" "f"))))]
5848 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5849 "fmpyfadd,dbl %2,%3,%1,%0"
5850 [(set_attr "type" "fpmuldbl")
5851 (set_attr "length" "4")])
5854 [(set (match_operand:SF 0 "register_operand" "=f")
5855 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5856 (match_operand:SF 2 "register_operand" "f"))
5857 (match_operand:SF 3 "register_operand" "f")))]
5858 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5859 "fmpyfadd,sgl %1,%2,%3,%0"
5860 [(set_attr "type" "fpmulsgl")
5861 (set_attr "length" "4")])
5864 [(set (match_operand:SF 0 "register_operand" "=f")
5865 (plus:SF (match_operand:SF 1 "register_operand" "f")
5866 (mult:SF (match_operand:SF 2 "register_operand" "f")
5867 (match_operand:SF 3 "register_operand" "f"))))]
5868 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5869 "fmpyfadd,sgl %2,%3,%1,%0"
5870 [(set_attr "type" "fpmulsgl")
5871 (set_attr "length" "4")])
5873 ; fmpynfadd patterns
5875 [(set (match_operand:DF 0 "register_operand" "=f")
5876 (minus:DF (match_operand:DF 1 "register_operand" "f")
5877 (mult:DF (match_operand:DF 2 "register_operand" "f")
5878 (match_operand:DF 3 "register_operand" "f"))))]
5879 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5880 "fmpynfadd,dbl %2,%3,%1,%0"
5881 [(set_attr "type" "fpmuldbl")
5882 (set_attr "length" "4")])
5885 [(set (match_operand:SF 0 "register_operand" "=f")
5886 (minus:SF (match_operand:SF 1 "register_operand" "f")
5887 (mult:SF (match_operand:SF 2 "register_operand" "f")
5888 (match_operand:SF 3 "register_operand" "f"))))]
5889 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5890 "fmpynfadd,sgl %2,%3,%1,%0"
5891 [(set_attr "type" "fpmulsgl")
5892 (set_attr "length" "4")])
5896 [(set (match_operand:DF 0 "register_operand" "=f")
5897 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
5898 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5900 [(set_attr "type" "fpalu")
5901 (set_attr "length" "4")])
5904 [(set (match_operand:SF 0 "register_operand" "=f")
5905 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
5906 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
5908 [(set_attr "type" "fpalu")
5909 (set_attr "length" "4")])
5911 ;; Generating a fused multiply sequence is a win for this case as it will
5912 ;; reduce the latency for the fused case without impacting the plain
5915 ;; Similar possibilities exist for fnegabs, shadd and other insns which
5916 ;; perform two operations with the result of the first feeding the second.
5918 [(set (match_operand:DF 0 "register_operand" "=f")
5919 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5920 (match_operand:DF 2 "register_operand" "f"))
5921 (match_operand:DF 3 "register_operand" "f")))
5922 (set (match_operand:DF 4 "register_operand" "=&f")
5923 (mult:DF (match_dup 1) (match_dup 2)))]
5924 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5925 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5926 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5928 [(set_attr "type" "fpmuldbl")
5929 (set_attr "length" "8")])
5931 ;; We want to split this up during scheduling since we want both insns
5932 ;; to schedule independently.
5934 [(set (match_operand:DF 0 "register_operand" "")
5935 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5936 (match_operand:DF 2 "register_operand" ""))
5937 (match_operand:DF 3 "register_operand" "")))
5938 (set (match_operand:DF 4 "register_operand" "")
5939 (mult:DF (match_dup 1) (match_dup 2)))]
5940 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5941 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5942 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
5947 [(set (match_operand:SF 0 "register_operand" "=f")
5948 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5949 (match_operand:SF 2 "register_operand" "f"))
5950 (match_operand:SF 3 "register_operand" "f")))
5951 (set (match_operand:SF 4 "register_operand" "=&f")
5952 (mult:SF (match_dup 1) (match_dup 2)))]
5953 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5954 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5955 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5957 [(set_attr "type" "fpmuldbl")
5958 (set_attr "length" "8")])
5960 ;; We want to split this up during scheduling since we want both insns
5961 ;; to schedule independently.
5963 [(set (match_operand:SF 0 "register_operand" "")
5964 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5965 (match_operand:SF 2 "register_operand" ""))
5966 (match_operand:SF 3 "register_operand" "")))
5967 (set (match_operand:SF 4 "register_operand" "")
5968 (mult:SF (match_dup 1) (match_dup 2)))]
5969 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5970 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5971 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
5975 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
5978 [(set (match_operand:DF 0 "register_operand" "=f")
5979 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5980 (match_operand:DF 2 "register_operand" "f"))))]
5981 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5982 "fmpynfadd,dbl %1,%2,%%fr0,%0"
5983 [(set_attr "type" "fpmuldbl")
5984 (set_attr "length" "4")])
5987 [(set (match_operand:SF 0 "register_operand" "=f")
5988 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5989 (match_operand:SF 2 "register_operand" "f"))))]
5990 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5991 "fmpynfadd,sgl %1,%2,%%fr0,%0"
5992 [(set_attr "type" "fpmuldbl")
5993 (set_attr "length" "4")])
5996 [(set (match_operand:DF 0 "register_operand" "=f")
5997 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5998 (match_operand:DF 2 "register_operand" "f"))))
5999 (set (match_operand:DF 3 "register_operand" "=&f")
6000 (mult:DF (match_dup 1) (match_dup 2)))]
6001 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6002 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6003 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6005 [(set_attr "type" "fpmuldbl")
6006 (set_attr "length" "8")])
6009 [(set (match_operand:DF 0 "register_operand" "")
6010 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6011 (match_operand:DF 2 "register_operand" ""))))
6012 (set (match_operand:DF 3 "register_operand" "")
6013 (mult:DF (match_dup 1) (match_dup 2)))]
6014 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6015 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
6016 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
6020 [(set (match_operand:SF 0 "register_operand" "=f")
6021 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6022 (match_operand:SF 2 "register_operand" "f"))))
6023 (set (match_operand:SF 3 "register_operand" "=&f")
6024 (mult:SF (match_dup 1) (match_dup 2)))]
6025 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6026 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
6027 || reg_overlap_mentioned_p (operands[3], operands[2])))"
6029 [(set_attr "type" "fpmuldbl")
6030 (set_attr "length" "8")])
6033 [(set (match_operand:SF 0 "register_operand" "")
6034 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6035 (match_operand:SF 2 "register_operand" ""))))
6036 (set (match_operand:SF 3 "register_operand" "")
6037 (mult:SF (match_dup 1) (match_dup 2)))]
6038 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6039 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
6040 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
6043 ;; Now fused multiplies with the result of the multiply negated.
6045 [(set (match_operand:DF 0 "register_operand" "=f")
6046 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6047 (match_operand:DF 2 "register_operand" "f")))
6048 (match_operand:DF 3 "register_operand" "f")))]
6049 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6050 "fmpynfadd,dbl %1,%2,%3,%0"
6051 [(set_attr "type" "fpmuldbl")
6052 (set_attr "length" "4")])
6055 [(set (match_operand:SF 0 "register_operand" "=f")
6056 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6057 (match_operand:SF 2 "register_operand" "f")))
6058 (match_operand:SF 3 "register_operand" "f")))]
6059 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6060 "fmpynfadd,sgl %1,%2,%3,%0"
6061 [(set_attr "type" "fpmuldbl")
6062 (set_attr "length" "4")])
6065 [(set (match_operand:DF 0 "register_operand" "=f")
6066 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
6067 (match_operand:DF 2 "register_operand" "f")))
6068 (match_operand:DF 3 "register_operand" "f")))
6069 (set (match_operand:DF 4 "register_operand" "=&f")
6070 (mult:DF (match_dup 1) (match_dup 2)))]
6071 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6072 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6073 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6075 [(set_attr "type" "fpmuldbl")
6076 (set_attr "length" "8")])
6079 [(set (match_operand:DF 0 "register_operand" "")
6080 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
6081 (match_operand:DF 2 "register_operand" "")))
6082 (match_operand:DF 3 "register_operand" "")))
6083 (set (match_operand:DF 4 "register_operand" "")
6084 (mult:DF (match_dup 1) (match_dup 2)))]
6085 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6086 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6087 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
6092 [(set (match_operand:SF 0 "register_operand" "=f")
6093 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
6094 (match_operand:SF 2 "register_operand" "f")))
6095 (match_operand:SF 3 "register_operand" "f")))
6096 (set (match_operand:SF 4 "register_operand" "=&f")
6097 (mult:SF (match_dup 1) (match_dup 2)))]
6098 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6099 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6100 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6102 [(set_attr "type" "fpmuldbl")
6103 (set_attr "length" "8")])
6106 [(set (match_operand:SF 0 "register_operand" "")
6107 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
6108 (match_operand:SF 2 "register_operand" "")))
6109 (match_operand:SF 3 "register_operand" "")))
6110 (set (match_operand:SF 4 "register_operand" "")
6111 (mult:SF (match_dup 1) (match_dup 2)))]
6112 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6113 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6114 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
6119 [(set (match_operand:DF 0 "register_operand" "=f")
6120 (minus:DF (match_operand:DF 3 "register_operand" "f")
6121 (mult:DF (match_operand:DF 1 "register_operand" "f")
6122 (match_operand:DF 2 "register_operand" "f"))))
6123 (set (match_operand:DF 4 "register_operand" "=&f")
6124 (mult:DF (match_dup 1) (match_dup 2)))]
6125 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6126 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6127 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6129 [(set_attr "type" "fpmuldbl")
6130 (set_attr "length" "8")])
6133 [(set (match_operand:DF 0 "register_operand" "")
6134 (minus:DF (match_operand:DF 3 "register_operand" "")
6135 (mult:DF (match_operand:DF 1 "register_operand" "")
6136 (match_operand:DF 2 "register_operand" ""))))
6137 (set (match_operand:DF 4 "register_operand" "")
6138 (mult:DF (match_dup 1) (match_dup 2)))]
6139 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6140 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
6141 (set (match_dup 0) (minus:DF (match_dup 3)
6142 (mult:DF (match_dup 1) (match_dup 2))))]
6146 [(set (match_operand:SF 0 "register_operand" "=f")
6147 (minus:SF (match_operand:SF 3 "register_operand" "f")
6148 (mult:SF (match_operand:SF 1 "register_operand" "f")
6149 (match_operand:SF 2 "register_operand" "f"))))
6150 (set (match_operand:SF 4 "register_operand" "=&f")
6151 (mult:SF (match_dup 1) (match_dup 2)))]
6152 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6153 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
6154 || reg_overlap_mentioned_p (operands[4], operands[2])))"
6156 [(set_attr "type" "fpmuldbl")
6157 (set_attr "length" "8")])
6160 [(set (match_operand:SF 0 "register_operand" "")
6161 (minus:SF (match_operand:SF 3 "register_operand" "")
6162 (mult:SF (match_operand:SF 1 "register_operand" "")
6163 (match_operand:SF 2 "register_operand" ""))))
6164 (set (match_operand:SF 4 "register_operand" "")
6165 (mult:SF (match_dup 1) (match_dup 2)))]
6166 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6167 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
6168 (set (match_dup 0) (minus:SF (match_dup 3)
6169 (mult:SF (match_dup 1) (match_dup 2))))]
6173 [(set (match_operand:DF 0 "register_operand" "=f")
6174 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
6175 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
6176 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6177 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6179 [(set_attr "type" "fpalu")
6180 (set_attr "length" "8")])
6183 [(set (match_operand:DF 0 "register_operand" "")
6184 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
6185 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
6186 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6187 [(set (match_dup 2) (abs:DF (match_dup 1)))
6188 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
6192 [(set (match_operand:SF 0 "register_operand" "=f")
6193 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
6194 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
6195 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
6196 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
6198 [(set_attr "type" "fpalu")
6199 (set_attr "length" "8")])
6202 [(set (match_operand:SF 0 "register_operand" "")
6203 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
6204 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
6205 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
6206 [(set (match_dup 2) (abs:SF (match_dup 1)))
6207 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
6210 ;;- Shift instructions
6212 ;; Optimized special case of shifting.
6215 [(set (match_operand:SI 0 "register_operand" "=r")
6216 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6220 [(set_attr "type" "load")
6221 (set_attr "length" "4")])
6224 [(set (match_operand:SI 0 "register_operand" "=r")
6225 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
6229 [(set_attr "type" "load")
6230 (set_attr "length" "4")])
6233 [(set (match_operand:SI 0 "register_operand" "=r")
6234 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
6235 (match_operand:SI 3 "shadd_operand" ""))
6236 (match_operand:SI 1 "register_operand" "r")))]
6238 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
6239 [(set_attr "type" "binary")
6240 (set_attr "length" "4")])
6243 [(set (match_operand:DI 0 "register_operand" "=r")
6244 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
6245 (match_operand:DI 3 "shadd_operand" ""))
6246 (match_operand:DI 1 "register_operand" "r")))]
6248 "shladd,l %2,%O3,%1,%0"
6249 [(set_attr "type" "binary")
6250 (set_attr "length" "4")])
6252 (define_expand "ashlsi3"
6253 [(set (match_operand:SI 0 "register_operand" "")
6254 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
6255 (match_operand:SI 2 "arith32_operand" "")))]
6259 if (GET_CODE (operands[2]) != CONST_INT)
6261 rtx temp = gen_reg_rtx (SImode);
6262 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6263 if (GET_CODE (operands[1]) == CONST_INT)
6264 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
6266 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
6269 /* Make sure both inputs are not constants,
6270 there are no patterns for that. */
6271 operands[1] = force_reg (SImode, operands[1]);
6275 [(set (match_operand:SI 0 "register_operand" "=r")
6276 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6277 (match_operand:SI 2 "const_int_operand" "n")))]
6279 "{zdep|depw,z} %1,%P2,%L2,%0"
6280 [(set_attr "type" "shift")
6281 (set_attr "length" "4")])
6283 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
6284 ; Doing it like this makes slightly better code since reload can
6285 ; replace a register with a known value in range -16..15 with a
6286 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
6287 ; but since we have no more CONST_OK... characters, that is not
6289 (define_insn "zvdep32"
6290 [(set (match_operand:SI 0 "register_operand" "=r,r")
6291 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
6292 (minus:SI (const_int 31)
6293 (match_operand:SI 2 "register_operand" "q,q"))))]
6296 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
6297 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
6298 [(set_attr "type" "shift,shift")
6299 (set_attr "length" "4,4")])
6301 (define_insn "zvdep_imm32"
6302 [(set (match_operand:SI 0 "register_operand" "=r")
6303 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
6304 (minus:SI (const_int 31)
6305 (match_operand:SI 2 "register_operand" "q"))))]
6309 int x = INTVAL (operands[1]);
6310 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6311 operands[1] = GEN_INT ((x & 0xf) - 0x10);
6312 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
6314 [(set_attr "type" "shift")
6315 (set_attr "length" "4")])
6317 (define_insn "vdepi_ior"
6318 [(set (match_operand:SI 0 "register_operand" "=r")
6319 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
6320 (minus:SI (const_int 31)
6321 (match_operand:SI 2 "register_operand" "q")))
6322 (match_operand:SI 3 "register_operand" "0")))]
6323 ; accept ...0001...1, can this be generalized?
6324 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6327 int x = INTVAL (operands[1]);
6328 operands[2] = GEN_INT (exact_log2 (x + 1));
6329 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
6331 [(set_attr "type" "shift")
6332 (set_attr "length" "4")])
6334 (define_insn "vdepi_and"
6335 [(set (match_operand:SI 0 "register_operand" "=r")
6336 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
6337 (minus:SI (const_int 31)
6338 (match_operand:SI 2 "register_operand" "q")))
6339 (match_operand:SI 3 "register_operand" "0")))]
6340 ; this can be generalized...!
6341 "INTVAL (operands[1]) == -2"
6344 int x = INTVAL (operands[1]);
6345 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6346 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
6348 [(set_attr "type" "shift")
6349 (set_attr "length" "4")])
6351 (define_expand "ashldi3"
6352 [(set (match_operand:DI 0 "register_operand" "")
6353 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
6354 (match_operand:DI 2 "arith32_operand" "")))]
6358 if (GET_CODE (operands[2]) != CONST_INT)
6360 rtx temp = gen_reg_rtx (DImode);
6361 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6362 if (GET_CODE (operands[1]) == CONST_INT)
6363 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
6365 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
6368 /* Make sure both inputs are not constants,
6369 there are no patterns for that. */
6370 operands[1] = force_reg (DImode, operands[1]);
6374 [(set (match_operand:DI 0 "register_operand" "=r")
6375 (ashift:DI (match_operand:DI 1 "register_operand" "r")
6376 (match_operand:DI 2 "const_int_operand" "n")))]
6378 "depd,z %1,%p2,%Q2,%0"
6379 [(set_attr "type" "shift")
6380 (set_attr "length" "4")])
6382 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
6383 ; Doing it like this makes slightly better code since reload can
6384 ; replace a register with a known value in range -16..15 with a
6385 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
6386 ; but since we have no more CONST_OK... characters, that is not
6388 (define_insn "zvdep64"
6389 [(set (match_operand:DI 0 "register_operand" "=r,r")
6390 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
6391 (minus:DI (const_int 63)
6392 (match_operand:DI 2 "register_operand" "q,q"))))]
6395 depd,z %1,%%sar,64,%0
6396 depdi,z %1,%%sar,64,%0"
6397 [(set_attr "type" "shift,shift")
6398 (set_attr "length" "4,4")])
6400 (define_insn "zvdep_imm64"
6401 [(set (match_operand:DI 0 "register_operand" "=r")
6402 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
6403 (minus:DI (const_int 63)
6404 (match_operand:DI 2 "register_operand" "q"))))]
6408 int x = INTVAL (operands[1]);
6409 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
6410 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
6411 return \"depdi,z %1,%%sar,%2,%0\";
6413 [(set_attr "type" "shift")
6414 (set_attr "length" "4")])
6417 [(set (match_operand:DI 0 "register_operand" "=r")
6418 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
6419 (minus:DI (const_int 63)
6420 (match_operand:DI 2 "register_operand" "q")))
6421 (match_operand:DI 3 "register_operand" "0")))]
6422 ; accept ...0001...1, can this be generalized?
6423 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
6426 int x = INTVAL (operands[1]);
6427 operands[2] = GEN_INT (exact_log2 (x + 1));
6428 return \"depdi -1,%%sar,%2,%0\";
6430 [(set_attr "type" "shift")
6431 (set_attr "length" "4")])
6434 [(set (match_operand:DI 0 "register_operand" "=r")
6435 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
6436 (minus:DI (const_int 63)
6437 (match_operand:DI 2 "register_operand" "q")))
6438 (match_operand:DI 3 "register_operand" "0")))]
6439 ; this can be generalized...!
6440 "TARGET_64BIT && INTVAL (operands[1]) == -2"
6443 int x = INTVAL (operands[1]);
6444 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
6445 return \"depdi 0,%%sar,%2,%0\";
6447 [(set_attr "type" "shift")
6448 (set_attr "length" "4")])
6450 (define_expand "ashrsi3"
6451 [(set (match_operand:SI 0 "register_operand" "")
6452 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
6453 (match_operand:SI 2 "arith32_operand" "")))]
6457 if (GET_CODE (operands[2]) != CONST_INT)
6459 rtx temp = gen_reg_rtx (SImode);
6460 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
6461 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
6467 [(set (match_operand:SI 0 "register_operand" "=r")
6468 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6469 (match_operand:SI 2 "const_int_operand" "n")))]
6471 "{extrs|extrw,s} %1,%P2,%L2,%0"
6472 [(set_attr "type" "shift")
6473 (set_attr "length" "4")])
6475 (define_insn "vextrs32"
6476 [(set (match_operand:SI 0 "register_operand" "=r")
6477 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
6478 (minus:SI (const_int 31)
6479 (match_operand:SI 2 "register_operand" "q"))))]
6481 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
6482 [(set_attr "type" "shift")
6483 (set_attr "length" "4")])
6485 (define_expand "ashrdi3"
6486 [(set (match_operand:DI 0 "register_operand" "")
6487 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
6488 (match_operand:DI 2 "arith32_operand" "")))]
6492 if (GET_CODE (operands[2]) != CONST_INT)
6494 rtx temp = gen_reg_rtx (DImode);
6495 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
6496 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
6502 [(set (match_operand:DI 0 "register_operand" "=r")
6503 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6504 (match_operand:DI 2 "const_int_operand" "n")))]
6506 "extrd,s %1,%p2,%Q2,%0"
6507 [(set_attr "type" "shift")
6508 (set_attr "length" "4")])
6510 (define_insn "vextrs64"
6511 [(set (match_operand:DI 0 "register_operand" "=r")
6512 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
6513 (minus:DI (const_int 63)
6514 (match_operand:DI 2 "register_operand" "q"))))]
6516 "extrd,s %1,%%sar,64,%0"
6517 [(set_attr "type" "shift")
6518 (set_attr "length" "4")])
6520 (define_insn "lshrsi3"
6521 [(set (match_operand:SI 0 "register_operand" "=r,r")
6522 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
6523 (match_operand:SI 2 "arith32_operand" "q,n")))]
6526 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
6527 {extru|extrw,u} %1,%P2,%L2,%0"
6528 [(set_attr "type" "shift")
6529 (set_attr "length" "4")])
6531 (define_insn "lshrdi3"
6532 [(set (match_operand:DI 0 "register_operand" "=r,r")
6533 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
6534 (match_operand:DI 2 "arith32_operand" "q,n")))]
6537 shrpd %%r0,%1,%%sar,%0
6538 extrd,u %1,%p2,%Q2,%0"
6539 [(set_attr "type" "shift")
6540 (set_attr "length" "4")])
6542 (define_insn "rotrsi3"
6543 [(set (match_operand:SI 0 "register_operand" "=r,r")
6544 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
6545 (match_operand:SI 2 "arith32_operand" "q,n")))]
6549 if (GET_CODE (operands[2]) == CONST_INT)
6551 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
6552 return \"{shd|shrpw} %1,%1,%2,%0\";
6555 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
6557 [(set_attr "type" "shift")
6558 (set_attr "length" "4")])
6560 (define_expand "rotlsi3"
6561 [(set (match_operand:SI 0 "register_operand" "")
6562 (rotate:SI (match_operand:SI 1 "register_operand" "")
6563 (match_operand:SI 2 "arith32_operand" "")))]
6567 if (GET_CODE (operands[2]) != CONST_INT)
6569 rtx temp = gen_reg_rtx (SImode);
6570 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
6571 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
6574 /* Else expand normally. */
6578 [(set (match_operand:SI 0 "register_operand" "=r")
6579 (rotate:SI (match_operand:SI 1 "register_operand" "r")
6580 (match_operand:SI 2 "const_int_operand" "n")))]
6584 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
6585 return \"{shd|shrpw} %1,%1,%2,%0\";
6587 [(set_attr "type" "shift")
6588 (set_attr "length" "4")])
6591 [(set (match_operand:SI 0 "register_operand" "=r")
6592 (match_operator:SI 5 "plus_xor_ior_operator"
6593 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
6594 (match_operand:SI 3 "const_int_operand" "n"))
6595 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6596 (match_operand:SI 4 "const_int_operand" "n"))]))]
6597 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6598 "{shd|shrpw} %1,%2,%4,%0"
6599 [(set_attr "type" "shift")
6600 (set_attr "length" "4")])
6603 [(set (match_operand:SI 0 "register_operand" "=r")
6604 (match_operator:SI 5 "plus_xor_ior_operator"
6605 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
6606 (match_operand:SI 4 "const_int_operand" "n"))
6607 (ashift:SI (match_operand:SI 1 "register_operand" "r")
6608 (match_operand:SI 3 "const_int_operand" "n"))]))]
6609 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
6610 "{shd|shrpw} %1,%2,%4,%0"
6611 [(set_attr "type" "shift")
6612 (set_attr "length" "4")])
6615 [(set (match_operand:SI 0 "register_operand" "=r")
6616 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
6617 (match_operand:SI 2 "const_int_operand" ""))
6618 (match_operand:SI 3 "const_int_operand" "")))]
6619 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
6622 int cnt = INTVAL (operands[2]) & 31;
6623 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
6624 operands[2] = GEN_INT (31 - cnt);
6625 return \"{zdep|depw,z} %1,%2,%3,%0\";
6627 [(set_attr "type" "shift")
6628 (set_attr "length" "4")])
6630 ;; Unconditional and other jump instructions.
6632 ;; This can only be used in a leaf function, so we do
6633 ;; not need to use the PIC register when generating PIC code.
6634 (define_insn "return"
6638 "hppa_can_use_return_insn_p ()"
6642 return \"bve%* (%%r2)\";
6643 return \"bv%* %%r0(%%r2)\";
6645 [(set_attr "type" "branch")
6646 (set_attr "length" "4")])
6648 ;; Emit a different pattern for functions which have non-trivial
6649 ;; epilogues so as not to confuse jump and reorg.
6650 (define_insn "return_internal"
6658 return \"bve%* (%%r2)\";
6659 return \"bv%* %%r0(%%r2)\";
6661 [(set_attr "type" "branch")
6662 (set_attr "length" "4")])
6664 ;; This is used for eh returns which bypass the return stub.
6665 (define_insn "return_external_pic"
6667 (clobber (reg:SI 1))
6669 "!TARGET_NO_SPACE_REGS
6671 && flag_pic && current_function_calls_eh_return"
6672 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
6673 [(set_attr "type" "branch")
6674 (set_attr "length" "12")])
6676 (define_expand "prologue"
6679 "hppa_expand_prologue ();DONE;")
6681 (define_expand "sibcall_epilogue"
6686 hppa_expand_epilogue ();
6690 (define_expand "epilogue"
6695 /* Try to use the trivial return first. Else use the full
6697 if (hppa_can_use_return_insn_p ())
6698 emit_jump_insn (gen_return ());
6703 hppa_expand_epilogue ();
6705 /* EH returns bypass the normal return stub. Thus, we must do an
6706 interspace branch to return from functions that call eh_return.
6707 This is only a problem for returns from shared code on ports
6708 using space registers. */
6709 if (!TARGET_NO_SPACE_REGS
6711 && flag_pic && current_function_calls_eh_return)
6712 x = gen_return_external_pic ();
6714 x = gen_return_internal ();
6721 ; Used by hppa_profile_hook to load the starting address of the current
6722 ; function; operand 1 contains the address of the label in operand 3
6723 (define_insn "load_offset_label_address"
6724 [(set (match_operand:SI 0 "register_operand" "=r")
6725 (plus:SI (match_operand:SI 1 "register_operand" "r")
6726 (minus:SI (match_operand:SI 2 "" "")
6727 (label_ref:SI (match_operand 3 "" "")))))]
6730 [(set_attr "type" "multi")
6731 (set_attr "length" "4")])
6733 ; Output a code label and load its address.
6734 (define_insn "lcla1"
6735 [(set (match_operand:SI 0 "register_operand" "=r")
6736 (label_ref:SI (match_operand 1 "" "")))
6741 output_asm_insn (\"bl .+8,%0\;depi 0,31,2,%0\", operands);
6742 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6743 CODE_LABEL_NUMBER (operands[1]));
6746 [(set_attr "type" "multi")
6747 (set_attr "length" "8")])
6749 (define_insn "lcla2"
6750 [(set (match_operand:SI 0 "register_operand" "=r")
6751 (label_ref:SI (match_operand 1 "" "")))
6756 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
6757 CODE_LABEL_NUMBER (operands[1]));
6760 [(set_attr "type" "move")
6761 (set_attr "length" "4")])
6763 (define_insn "blockage"
6764 [(unspec_volatile [(const_int 2)] 0)]
6767 [(set_attr "length" "0")])
6770 [(set (pc) (label_ref (match_operand 0 "" "")))]
6774 /* An unconditional branch which can reach its target. */
6775 if (get_attr_length (insn) != 24
6776 && get_attr_length (insn) != 16)
6779 return output_lbranch (operands[0], insn);
6781 [(set_attr "type" "uncond_branch")
6782 (set_attr "pa_combine_type" "uncond_branch")
6783 (set (attr "length")
6784 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
6785 (if_then_else (lt (abs (minus (match_dup 0)
6786 (plus (pc) (const_int 8))))
6790 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
6792 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
6797 ;;; Hope this is only within a function...
6798 (define_insn "indirect_jump"
6799 [(set (pc) (match_operand 0 "register_operand" "r"))]
6800 "GET_MODE (operands[0]) == word_mode"
6802 [(set_attr "type" "branch")
6803 (set_attr "length" "4")])
6805 ;;; This jump is used in branch tables where the insn length is fixed.
6806 ;;; The length of this insn is adjusted if the delay slot is not filled.
6807 (define_insn "short_jump"
6808 [(set (pc) (label_ref (match_operand 0 "" "")))
6812 [(set_attr "type" "btable_branch")
6813 (set_attr "length" "4")])
6815 ;; Subroutines of "casesi".
6816 ;; operand 0 is index
6817 ;; operand 1 is the minimum bound
6818 ;; operand 2 is the maximum bound - minimum bound + 1
6819 ;; operand 3 is CODE_LABEL for the table;
6820 ;; operand 4 is the CODE_LABEL to go to if index out of range.
6822 (define_expand "casesi"
6823 [(match_operand:SI 0 "general_operand" "")
6824 (match_operand:SI 1 "const_int_operand" "")
6825 (match_operand:SI 2 "const_int_operand" "")
6826 (match_operand 3 "" "")
6827 (match_operand 4 "" "")]
6831 if (GET_CODE (operands[0]) != REG)
6832 operands[0] = force_reg (SImode, operands[0]);
6834 if (operands[1] != const0_rtx)
6836 rtx index = gen_reg_rtx (SImode);
6838 operands[1] = GEN_INT (-INTVAL (operands[1]));
6839 if (!INT_14_BITS (operands[1]))
6840 operands[1] = force_reg (SImode, operands[1]);
6841 emit_insn (gen_addsi3 (index, operands[0], operands[1]));
6842 operands[0] = index;
6845 /* In 64bit mode we must make sure to wipe the upper bits of the register
6846 just in case the addition overflowed or we had random bits in the
6847 high part of the register. */
6850 rtx index = gen_reg_rtx (DImode);
6852 emit_insn (gen_extendsidi2 (index, operands[0]));
6853 operands[0] = gen_rtx_SUBREG (SImode, index, 4);
6856 if (!INT_5_BITS (operands[2]))
6857 operands[2] = force_reg (SImode, operands[2]);
6859 /* This branch prevents us finding an insn for the delay slot of the
6860 following vectored branch. It might be possible to use the delay
6861 slot if an index value of -1 was used to transfer to the out-of-range
6862 label. In order to do this, we would have to output the -1 vector
6863 element after the delay insn. The casesi output code would have to
6864 check if the casesi insn is in a delay branch sequence and output
6865 the delay insn if one is found. If this was done, then it might
6866 then be worthwhile to split the casesi patterns to improve scheduling.
6867 However, it's not clear that all this extra complexity is worth
6869 emit_insn (gen_cmpsi (operands[0], operands[2]));
6870 emit_jump_insn (gen_bgtu (operands[4]));
6872 if (TARGET_BIG_SWITCH)
6876 rtx tmp1 = gen_reg_rtx (DImode);
6877 rtx tmp2 = gen_reg_rtx (DImode);
6879 emit_jump_insn (gen_casesi64p (operands[0], operands[3],
6884 rtx tmp1 = gen_reg_rtx (SImode);
6888 rtx tmp2 = gen_reg_rtx (SImode);
6890 emit_jump_insn (gen_casesi32p (operands[0], operands[3],
6894 emit_jump_insn (gen_casesi32 (operands[0], operands[3], tmp1));
6898 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
6902 ;;; The rtl for this pattern doesn't accurately describe what the insn
6903 ;;; actually does, particularly when case-vector elements are exploded
6904 ;;; in pa_reorg. However, the initial SET in these patterns must show
6905 ;;; the connection of the insn to the following jump table.
6906 (define_insn "casesi0"
6907 [(set (pc) (mem:SI (plus:SI
6908 (mult:SI (match_operand:SI 0 "register_operand" "r")
6910 (label_ref (match_operand 1 "" "")))))]
6912 "blr,n %0,%%r0\;nop"
6913 [(set_attr "type" "multi")
6914 (set_attr "length" "8")])
6916 ;;; 32-bit code, absolute branch table.
6917 (define_insn "casesi32"
6918 [(set (pc) (mem:SI (plus:SI
6919 (mult:SI (match_operand:SI 0 "register_operand" "r")
6921 (label_ref (match_operand 1 "" "")))))
6922 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
6923 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6924 "ldil L'%l1,%2\;ldo R'%l1(%2),%2\;{ldwx|ldw},s %0(%2),%2\;bv,n %%r0(%2)"
6925 [(set_attr "type" "multi")
6926 (set_attr "length" "16")])
6928 ;;; 32-bit code, relative branch table.
6929 (define_insn "casesi32p"
6930 [(set (pc) (mem:SI (plus:SI
6931 (mult:SI (match_operand:SI 0 "register_operand" "r")
6933 (label_ref (match_operand 1 "" "")))))
6934 (clobber (match_operand:SI 2 "register_operand" "=&a"))
6935 (clobber (match_operand:SI 3 "register_operand" "=&r"))]
6936 "!TARGET_64BIT && TARGET_BIG_SWITCH"
6937 "{bl .+8,%2\;depi 0,31,2,%2|mfia %2}\;ldo {16|20}(%2),%2\;\
6938 {ldwx|ldw},s %0(%2),%3\;{addl|add,l} %2,%3,%3\;bv,n %%r0(%3)"
6939 [(set_attr "type" "multi")
6940 (set (attr "length")
6941 (if_then_else (ne (symbol_ref "TARGET_PA_20") (const_int 0))
6945 ;;; 64-bit code, 32-bit relative branch table.
6946 (define_insn "casesi64p"
6947 [(set (pc) (mem:DI (plus:DI
6948 (mult:DI (sign_extend:DI
6949 (match_operand:SI 0 "register_operand" "r"))
6951 (label_ref (match_operand 1 "" "")))))
6952 (clobber (match_operand:DI 2 "register_operand" "=&r"))
6953 (clobber (match_operand:DI 3 "register_operand" "=&r"))]
6954 "TARGET_64BIT && TARGET_BIG_SWITCH"
6955 "mfia %2\;ldo 24(%2),%2\;ldw,s %0(%2),%3\;extrd,s %3,63,32,%3\;\
6956 add,l %2,%3,%3\;bv,n %%r0(%3)"
6957 [(set_attr "type" "multi")
6958 (set_attr "length" "24")])
6962 ;;- jump to subroutine
6964 (define_expand "call"
6965 [(parallel [(call (match_operand:SI 0 "" "")
6966 (match_operand 1 "" ""))
6967 (clobber (reg:SI 2))])]
6972 rtx nb = operands[1];
6974 if (TARGET_PORTABLE_RUNTIME)
6975 op = force_reg (SImode, XEXP (operands[0], 0));
6977 op = XEXP (operands[0], 0);
6981 if (!virtuals_instantiated)
6982 emit_move_insn (arg_pointer_rtx,
6983 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6987 /* The loop pass can generate new libcalls after the virtual
6988 registers are instantiated when fpregs are disabled because
6989 the only method that we have for doing DImode multiplication
6990 is with a libcall. This could be trouble if we haven't
6991 allocated enough space for the outgoing arguments. */
6992 if (INTVAL (nb) > current_function_outgoing_args_size)
6995 emit_move_insn (arg_pointer_rtx,
6996 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6997 GEN_INT (STACK_POINTER_OFFSET + 64)));
7001 /* Use two different patterns for calls to explicitly named functions
7002 and calls through function pointers. This is necessary as these two
7003 types of calls use different calling conventions, and CSE might try
7004 to change the named call into an indirect call in some cases (using
7005 two patterns keeps CSE from performing this optimization).
7007 We now use even more call patterns as there was a subtle bug in
7008 attempting to restore the pic register after a call using a simple
7009 move insn. During reload, a instruction involving a pseudo register
7010 with no explicit dependence on the PIC register can be converted
7011 to an equivalent load from memory using the PIC register. If we
7012 emit a simple move to restore the PIC register in the initial rtl
7013 generation, then it can potentially be repositioned during scheduling.
7014 and an instruction that eventually uses the PIC register may end up
7015 between the call and the PIC register restore.
7017 This only worked because there is a post call group of instructions
7018 that are scheduled with the call. These instructions are included
7019 in the same basic block as the call. However, calls can throw in
7020 C++ code and a basic block has to terminate at the call if the call
7021 can throw. This results in the PIC register restore being scheduled
7022 independently from the call. So, we now hide the save and restore
7023 of the PIC register in the call pattern until after reload. Then,
7024 we split the moves out. A small side benefit is that we now don't
7025 need to have a use of the PIC register in the return pattern and
7026 the final save/restore operation is not needed.
7028 I elected to just clobber %r4 in the PIC patterns and use it instead
7029 of trying to force hppa_pic_save_rtx () to a callee saved register.
7030 This might have required a new register class and constraint. It
7031 was also simpler to just handle the restore from a register than a
7035 if (GET_CODE (op) == SYMBOL_REF)
7036 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
7039 op = force_reg (word_mode, op);
7040 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
7045 if (GET_CODE (op) == SYMBOL_REF)
7048 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
7050 call_insn = emit_call_insn (gen_call_symref (op, nb));
7054 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7056 emit_move_insn (tmpreg, force_reg (word_mode, op));
7058 call_insn = emit_call_insn (gen_call_reg_pic (nb));
7060 call_insn = emit_call_insn (gen_call_reg (nb));
7067 ;; We use function calls to set the attribute length of calls and millicode
7068 ;; calls. This is necessary because of the large variety of call sequences.
7069 ;; Implementing the calculation in rtl is difficult as well as ugly. As
7070 ;; we need the same calculation in several places, maintenance becomes a
7073 ;; However, this has a subtle impact on branch shortening. When the
7074 ;; expression used to set the length attribute of an instruction depends
7075 ;; on a relative address (e.g., pc or a branch address), genattrtab
7076 ;; notes that the insn's length is variable, and attempts to determine a
7077 ;; worst-case default length and code to compute an insn's current length.
7079 ;; The use of a function call hides the variable dependence of our calls
7080 ;; and millicode calls. The result is genattrtab doesn't treat the operation
7081 ;; as variable and it only generates code for the default case using our
7082 ;; function call. Because of this, calls and millicode calls have a fixed
7083 ;; length in the branch shortening pass, and some branches will use a longer
7084 ;; code sequence than necessary. However, the length of any given call
7085 ;; will still reflect its final code location and it may be shorter than
7086 ;; the initial length estimate.
7088 ;; It's possible to trick genattrtab by adding an expression involving `pc'
7089 ;; in the set. However, when genattrtab hits a function call in its attempt
7090 ;; to compute the default length, it marks the result as unknown and sets
7091 ;; the default result to MAX_INT ;-( One possible fix that would allow
7092 ;; calls to participate in branch shortening would be to make the call to
7093 ;; insn_default_length a target option. Then, we could massage unknown
7094 ;; results. Another fix might be to change genattrtab so that it just does
7095 ;; the call in the variable case as it already does for the fixed case.
7097 (define_insn "call_symref"
7098 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7099 (match_operand 1 "" "i"))
7100 (clobber (reg:SI 1))
7101 (clobber (reg:SI 2))
7102 (use (const_int 0))]
7103 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7106 output_arg_descriptor (insn);
7107 return output_call (insn, operands[0], 0);
7109 [(set_attr "type" "call")
7110 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7112 (define_insn "call_symref_pic"
7113 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7114 (match_operand 1 "" "i"))
7115 (clobber (reg:SI 1))
7116 (clobber (reg:SI 2))
7117 (clobber (reg:SI 4))
7119 (use (const_int 0))]
7120 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7123 output_arg_descriptor (insn);
7124 return output_call (insn, operands[0], 0);
7126 [(set_attr "type" "call")
7127 (set (attr "length")
7128 (plus (symbol_ref "attr_length_call (insn, 0)")
7129 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7131 ;; Split out the PIC register save and restore after reload. This is
7132 ;; done only if the function returns. As the split is done after reload,
7133 ;; there are some situations in which we unnecessarily save and restore
7134 ;; %r4. This happens when there is a single call and the PIC register
7135 ;; is "dead" after the call. This isn't easy to fix as the usage of
7136 ;; the PIC register isn't completely determined until the reload pass.
7138 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7139 (match_operand 1 "" ""))
7140 (clobber (reg:SI 1))
7141 (clobber (reg:SI 2))
7142 (clobber (reg:SI 4))
7144 (use (const_int 0))])]
7145 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7147 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7148 [(set (reg:SI 4) (reg:SI 19))
7149 (parallel [(call (mem:SI (match_dup 0))
7151 (clobber (reg:SI 1))
7152 (clobber (reg:SI 2))
7154 (use (const_int 0))])
7155 (set (reg:SI 19) (reg:SI 4))]
7158 ;; Remove the clobber of register 4 when optimizing. This has to be
7159 ;; done with a peephole optimization rather than a split because the
7160 ;; split sequence for a call must be longer than one instruction.
7162 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7163 (match_operand 1 "" ""))
7164 (clobber (reg:SI 1))
7165 (clobber (reg:SI 2))
7166 (clobber (reg:SI 4))
7168 (use (const_int 0))])]
7169 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7170 [(parallel [(call (mem:SI (match_dup 0))
7172 (clobber (reg:SI 1))
7173 (clobber (reg:SI 2))
7175 (use (const_int 0))])]
7178 (define_insn "*call_symref_pic_post_reload"
7179 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7180 (match_operand 1 "" "i"))
7181 (clobber (reg:SI 1))
7182 (clobber (reg:SI 2))
7184 (use (const_int 0))]
7185 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7188 output_arg_descriptor (insn);
7189 return output_call (insn, operands[0], 0);
7191 [(set_attr "type" "call")
7192 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7194 ;; This pattern is split if it is necessary to save and restore the
7196 (define_insn "call_symref_64bit"
7197 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7198 (match_operand 1 "" "i"))
7199 (clobber (reg:DI 1))
7200 (clobber (reg:DI 2))
7201 (clobber (reg:DI 4))
7204 (use (const_int 0))]
7208 output_arg_descriptor (insn);
7209 return output_call (insn, operands[0], 0);
7211 [(set_attr "type" "call")
7212 (set (attr "length")
7213 (plus (symbol_ref "attr_length_call (insn, 0)")
7214 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7216 ;; Split out the PIC register save and restore after reload. This is
7217 ;; done only if the function returns. As the split is done after reload,
7218 ;; there are some situations in which we unnecessarily save and restore
7219 ;; %r4. This happens when there is a single call and the PIC register
7220 ;; is "dead" after the call. This isn't easy to fix as the usage of
7221 ;; the PIC register isn't completely determined until the reload pass.
7223 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7224 (match_operand 1 "" ""))
7225 (clobber (reg:DI 1))
7226 (clobber (reg:DI 2))
7227 (clobber (reg:DI 4))
7230 (use (const_int 0))])]
7233 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7234 [(set (reg:DI 4) (reg:DI 27))
7235 (parallel [(call (mem:SI (match_dup 0))
7237 (clobber (reg:DI 1))
7238 (clobber (reg:DI 2))
7241 (use (const_int 0))])
7242 (set (reg:DI 27) (reg:DI 4))]
7245 ;; Remove the clobber of register 4 when optimizing. This has to be
7246 ;; done with a peephole optimization rather than a split because the
7247 ;; split sequence for a call must be longer than one instruction.
7249 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7250 (match_operand 1 "" ""))
7251 (clobber (reg:DI 1))
7252 (clobber (reg:DI 2))
7253 (clobber (reg:DI 4))
7256 (use (const_int 0))])]
7257 "TARGET_64BIT && reload_completed"
7258 [(parallel [(call (mem:SI (match_dup 0))
7260 (clobber (reg:DI 1))
7261 (clobber (reg:DI 2))
7264 (use (const_int 0))])]
7267 (define_insn "*call_symref_64bit_post_reload"
7268 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
7269 (match_operand 1 "" "i"))
7270 (clobber (reg:DI 1))
7271 (clobber (reg:DI 2))
7274 (use (const_int 0))]
7278 output_arg_descriptor (insn);
7279 return output_call (insn, operands[0], 0);
7281 [(set_attr "type" "call")
7282 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7284 (define_insn "call_reg"
7285 [(call (mem:SI (reg:SI 22))
7286 (match_operand 0 "" "i"))
7287 (clobber (reg:SI 1))
7288 (clobber (reg:SI 2))
7289 (use (const_int 1))]
7293 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7295 [(set_attr "type" "dyncall")
7296 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7298 ;; This pattern is split if it is necessary to save and restore the
7300 (define_insn "call_reg_pic"
7301 [(call (mem:SI (reg:SI 22))
7302 (match_operand 0 "" "i"))
7303 (clobber (reg:SI 1))
7304 (clobber (reg:SI 2))
7305 (clobber (reg:SI 4))
7307 (use (const_int 1))]
7311 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7313 [(set_attr "type" "dyncall")
7314 (set (attr "length")
7315 (plus (symbol_ref "attr_length_indirect_call (insn)")
7316 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7318 ;; Split out the PIC register save and restore after reload. This is
7319 ;; done only if the function returns. As the split is done after reload,
7320 ;; there are some situations in which we unnecessarily save and restore
7321 ;; %r4. This happens when there is a single call and the PIC register
7322 ;; is "dead" after the call. This isn't easy to fix as the usage of
7323 ;; the PIC register isn't completely determined until the reload pass.
7325 [(parallel [(call (mem:SI (reg:SI 22))
7326 (match_operand 0 "" ""))
7327 (clobber (reg:SI 1))
7328 (clobber (reg:SI 2))
7329 (clobber (reg:SI 4))
7331 (use (const_int 1))])]
7334 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7335 [(set (reg:SI 4) (reg:SI 19))
7336 (parallel [(call (mem:SI (reg:SI 22))
7338 (clobber (reg:SI 1))
7339 (clobber (reg:SI 2))
7341 (use (const_int 1))])
7342 (set (reg:SI 19) (reg:SI 4))]
7345 ;; Remove the clobber of register 4 when optimizing. This has to be
7346 ;; done with a peephole optimization rather than a split because the
7347 ;; split sequence for a call must be longer than one instruction.
7349 [(parallel [(call (mem:SI (reg:SI 22))
7350 (match_operand 0 "" ""))
7351 (clobber (reg:SI 1))
7352 (clobber (reg:SI 2))
7353 (clobber (reg:SI 4))
7355 (use (const_int 1))])]
7356 "!TARGET_64BIT && reload_completed"
7357 [(parallel [(call (mem:SI (reg:SI 22))
7359 (clobber (reg:SI 1))
7360 (clobber (reg:SI 2))
7362 (use (const_int 1))])]
7365 (define_insn "*call_reg_pic_post_reload"
7366 [(call (mem:SI (reg:SI 22))
7367 (match_operand 0 "" "i"))
7368 (clobber (reg:SI 1))
7369 (clobber (reg:SI 2))
7371 (use (const_int 1))]
7375 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7377 [(set_attr "type" "dyncall")
7378 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7380 ;; This pattern is split if it is necessary to save and restore the
7382 (define_insn "call_reg_64bit"
7383 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7384 (match_operand 1 "" "i"))
7385 (clobber (reg:DI 2))
7386 (clobber (reg:DI 4))
7389 (use (const_int 1))]
7393 return output_indirect_call (insn, operands[0]);
7395 [(set_attr "type" "dyncall")
7396 (set (attr "length")
7397 (plus (symbol_ref "attr_length_indirect_call (insn)")
7398 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7400 ;; Split out the PIC register save and restore after reload. This is
7401 ;; done only if the function returns. As the split is done after reload,
7402 ;; there are some situations in which we unnecessarily save and restore
7403 ;; %r4. This happens when there is a single call and the PIC register
7404 ;; is "dead" after the call. This isn't easy to fix as the usage of
7405 ;; the PIC register isn't completely determined until the reload pass.
7407 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7408 (match_operand 1 "" ""))
7409 (clobber (reg:DI 2))
7410 (clobber (reg:DI 4))
7413 (use (const_int 1))])]
7416 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7417 [(set (reg:DI 4) (reg:DI 27))
7418 (parallel [(call (mem:SI (match_dup 0))
7420 (clobber (reg:DI 2))
7423 (use (const_int 1))])
7424 (set (reg:DI 27) (reg:DI 4))]
7427 ;; Remove the clobber of register 4 when optimizing. This has to be
7428 ;; done with a peephole optimization rather than a split because the
7429 ;; split sequence for a call must be longer than one instruction.
7431 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
7432 (match_operand 1 "" ""))
7433 (clobber (reg:DI 2))
7434 (clobber (reg:DI 4))
7437 (use (const_int 1))])]
7438 "TARGET_64BIT && reload_completed"
7439 [(parallel [(call (mem:SI (match_dup 0))
7441 (clobber (reg:DI 2))
7444 (use (const_int 1))])]
7447 (define_insn "*call_reg_64bit_post_reload"
7448 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
7449 (match_operand 1 "" "i"))
7450 (clobber (reg:DI 2))
7453 (use (const_int 1))]
7457 return output_indirect_call (insn, operands[0]);
7459 [(set_attr "type" "dyncall")
7460 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7462 (define_expand "call_value"
7463 [(parallel [(set (match_operand 0 "" "")
7464 (call (match_operand:SI 1 "" "")
7465 (match_operand 2 "" "")))
7466 (clobber (reg:SI 2))])]
7471 rtx dst = operands[0];
7472 rtx nb = operands[2];
7474 if (TARGET_PORTABLE_RUNTIME)
7475 op = force_reg (SImode, XEXP (operands[1], 0));
7477 op = XEXP (operands[1], 0);
7481 if (!virtuals_instantiated)
7482 emit_move_insn (arg_pointer_rtx,
7483 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
7487 /* The loop pass can generate new libcalls after the virtual
7488 registers are instantiated when fpregs are disabled because
7489 the only method that we have for doing DImode multiplication
7490 is with a libcall. This could be trouble if we haven't
7491 allocated enough space for the outgoing arguments. */
7492 if (INTVAL (nb) > current_function_outgoing_args_size)
7495 emit_move_insn (arg_pointer_rtx,
7496 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
7497 GEN_INT (STACK_POINTER_OFFSET + 64)));
7501 /* Use two different patterns for calls to explicitly named functions
7502 and calls through function pointers. This is necessary as these two
7503 types of calls use different calling conventions, and CSE might try
7504 to change the named call into an indirect call in some cases (using
7505 two patterns keeps CSE from performing this optimization).
7507 We now use even more call patterns as there was a subtle bug in
7508 attempting to restore the pic register after a call using a simple
7509 move insn. During reload, a instruction involving a pseudo register
7510 with no explicit dependence on the PIC register can be converted
7511 to an equivalent load from memory using the PIC register. If we
7512 emit a simple move to restore the PIC register in the initial rtl
7513 generation, then it can potentially be repositioned during scheduling.
7514 and an instruction that eventually uses the PIC register may end up
7515 between the call and the PIC register restore.
7517 This only worked because there is a post call group of instructions
7518 that are scheduled with the call. These instructions are included
7519 in the same basic block as the call. However, calls can throw in
7520 C++ code and a basic block has to terminate at the call if the call
7521 can throw. This results in the PIC register restore being scheduled
7522 independently from the call. So, we now hide the save and restore
7523 of the PIC register in the call pattern until after reload. Then,
7524 we split the moves out. A small side benefit is that we now don't
7525 need to have a use of the PIC register in the return pattern and
7526 the final save/restore operation is not needed.
7528 I elected to just clobber %r4 in the PIC patterns and use it instead
7529 of trying to force hppa_pic_save_rtx () to a callee saved register.
7530 This might have required a new register class and constraint. It
7531 was also simpler to just handle the restore from a register than a
7535 if (GET_CODE (op) == SYMBOL_REF)
7536 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
7539 op = force_reg (word_mode, op);
7540 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
7545 if (GET_CODE (op) == SYMBOL_REF)
7548 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
7550 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
7554 rtx tmpreg = gen_rtx_REG (word_mode, 22);
7556 emit_move_insn (tmpreg, force_reg (word_mode, op));
7558 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
7560 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
7567 (define_insn "call_val_symref"
7568 [(set (match_operand 0 "" "")
7569 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7570 (match_operand 2 "" "i")))
7571 (clobber (reg:SI 1))
7572 (clobber (reg:SI 2))
7573 (use (const_int 0))]
7574 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7577 output_arg_descriptor (insn);
7578 return output_call (insn, operands[1], 0);
7580 [(set_attr "type" "call")
7581 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7583 (define_insn "call_val_symref_pic"
7584 [(set (match_operand 0 "" "")
7585 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7586 (match_operand 2 "" "i")))
7587 (clobber (reg:SI 1))
7588 (clobber (reg:SI 2))
7589 (clobber (reg:SI 4))
7591 (use (const_int 0))]
7592 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7595 output_arg_descriptor (insn);
7596 return output_call (insn, operands[1], 0);
7598 [(set_attr "type" "call")
7599 (set (attr "length")
7600 (plus (symbol_ref "attr_length_call (insn, 0)")
7601 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7603 ;; Split out the PIC register save and restore after reload. This is
7604 ;; done only if the function returns. As the split is done after reload,
7605 ;; there are some situations in which we unnecessarily save and restore
7606 ;; %r4. This happens when there is a single call and the PIC register
7607 ;; is "dead" after the call. This isn't easy to fix as the usage of
7608 ;; the PIC register isn't completely determined until the reload pass.
7610 [(parallel [(set (match_operand 0 "" "")
7611 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7612 (match_operand 2 "" "")))
7613 (clobber (reg:SI 1))
7614 (clobber (reg:SI 2))
7615 (clobber (reg:SI 4))
7617 (use (const_int 0))])]
7618 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
7620 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7621 [(set (reg:SI 4) (reg:SI 19))
7622 (parallel [(set (match_dup 0)
7623 (call (mem:SI (match_dup 1))
7625 (clobber (reg:SI 1))
7626 (clobber (reg:SI 2))
7628 (use (const_int 0))])
7629 (set (reg:SI 19) (reg:SI 4))]
7632 ;; Remove the clobber of register 4 when optimizing. This has to be
7633 ;; done with a peephole optimization rather than a split because the
7634 ;; split sequence for a call must be longer than one instruction.
7636 [(parallel [(set (match_operand 0 "" "")
7637 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7638 (match_operand 2 "" "")))
7639 (clobber (reg:SI 1))
7640 (clobber (reg:SI 2))
7641 (clobber (reg:SI 4))
7643 (use (const_int 0))])]
7644 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
7645 [(parallel [(set (match_dup 0)
7646 (call (mem:SI (match_dup 1))
7648 (clobber (reg:SI 1))
7649 (clobber (reg:SI 2))
7651 (use (const_int 0))])]
7654 (define_insn "*call_val_symref_pic_post_reload"
7655 [(set (match_operand 0 "" "")
7656 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7657 (match_operand 2 "" "i")))
7658 (clobber (reg:SI 1))
7659 (clobber (reg:SI 2))
7661 (use (const_int 0))]
7662 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7665 output_arg_descriptor (insn);
7666 return output_call (insn, operands[1], 0);
7668 [(set_attr "type" "call")
7669 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7671 ;; This pattern is split if it is necessary to save and restore the
7673 (define_insn "call_val_symref_64bit"
7674 [(set (match_operand 0 "" "")
7675 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7676 (match_operand 2 "" "i")))
7677 (clobber (reg:DI 1))
7678 (clobber (reg:DI 2))
7679 (clobber (reg:DI 4))
7682 (use (const_int 0))]
7686 output_arg_descriptor (insn);
7687 return output_call (insn, operands[1], 0);
7689 [(set_attr "type" "call")
7690 (set (attr "length")
7691 (plus (symbol_ref "attr_length_call (insn, 0)")
7692 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7694 ;; Split out the PIC register save and restore after reload. This is
7695 ;; done only if the function returns. As the split is done after reload,
7696 ;; there are some situations in which we unnecessarily save and restore
7697 ;; %r4. This happens when there is a single call and the PIC register
7698 ;; is "dead" after the call. This isn't easy to fix as the usage of
7699 ;; the PIC register isn't completely determined until the reload pass.
7701 [(parallel [(set (match_operand 0 "" "")
7702 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7703 (match_operand 2 "" "")))
7704 (clobber (reg:DI 1))
7705 (clobber (reg:DI 2))
7706 (clobber (reg:DI 4))
7709 (use (const_int 0))])]
7712 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7713 [(set (reg:DI 4) (reg:DI 27))
7714 (parallel [(set (match_dup 0)
7715 (call (mem:SI (match_dup 1))
7717 (clobber (reg:DI 1))
7718 (clobber (reg:DI 2))
7721 (use (const_int 0))])
7722 (set (reg:DI 27) (reg:DI 4))]
7725 ;; Remove the clobber of register 4 when optimizing. This has to be
7726 ;; done with a peephole optimization rather than a split because the
7727 ;; split sequence for a call must be longer than one instruction.
7729 [(parallel [(set (match_operand 0 "" "")
7730 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7731 (match_operand 2 "" "")))
7732 (clobber (reg:DI 1))
7733 (clobber (reg:DI 2))
7734 (clobber (reg:DI 4))
7737 (use (const_int 0))])]
7738 "TARGET_64BIT && reload_completed"
7739 [(parallel [(set (match_dup 0)
7740 (call (mem:SI (match_dup 1))
7742 (clobber (reg:DI 1))
7743 (clobber (reg:DI 2))
7746 (use (const_int 0))])]
7749 (define_insn "*call_val_symref_64bit_post_reload"
7750 [(set (match_operand 0 "" "")
7751 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7752 (match_operand 2 "" "i")))
7753 (clobber (reg:DI 1))
7754 (clobber (reg:DI 2))
7757 (use (const_int 0))]
7761 output_arg_descriptor (insn);
7762 return output_call (insn, operands[1], 0);
7764 [(set_attr "type" "call")
7765 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
7767 (define_insn "call_val_reg"
7768 [(set (match_operand 0 "" "")
7769 (call (mem:SI (reg:SI 22))
7770 (match_operand 1 "" "i")))
7771 (clobber (reg:SI 1))
7772 (clobber (reg:SI 2))
7773 (use (const_int 1))]
7777 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7779 [(set_attr "type" "dyncall")
7780 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7782 ;; This pattern is split if it is necessary to save and restore the
7784 (define_insn "call_val_reg_pic"
7785 [(set (match_operand 0 "" "")
7786 (call (mem:SI (reg:SI 22))
7787 (match_operand 1 "" "i")))
7788 (clobber (reg:SI 1))
7789 (clobber (reg:SI 2))
7790 (clobber (reg:SI 4))
7792 (use (const_int 1))]
7796 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7798 [(set_attr "type" "dyncall")
7799 (set (attr "length")
7800 (plus (symbol_ref "attr_length_indirect_call (insn)")
7801 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7803 ;; Split out the PIC register save and restore after reload. This is
7804 ;; done only if the function returns. As the split is done after reload,
7805 ;; there are some situations in which we unnecessarily save and restore
7806 ;; %r4. This happens when there is a single call and the PIC register
7807 ;; is "dead" after the call. This isn't easy to fix as the usage of
7808 ;; the PIC register isn't completely determined until the reload pass.
7810 [(parallel [(set (match_operand 0 "" "")
7811 (call (mem:SI (reg:SI 22))
7812 (match_operand 1 "" "")))
7813 (clobber (reg:SI 1))
7814 (clobber (reg:SI 2))
7815 (clobber (reg:SI 4))
7817 (use (const_int 1))])]
7820 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7821 [(set (reg:SI 4) (reg:SI 19))
7822 (parallel [(set (match_dup 0)
7823 (call (mem:SI (reg:SI 22))
7825 (clobber (reg:SI 1))
7826 (clobber (reg:SI 2))
7828 (use (const_int 1))])
7829 (set (reg:SI 19) (reg:SI 4))]
7832 ;; Remove the clobber of register 4 when optimizing. This has to be
7833 ;; done with a peephole optimization rather than a split because the
7834 ;; split sequence for a call must be longer than one instruction.
7836 [(parallel [(set (match_operand 0 "" "")
7837 (call (mem:SI (reg:SI 22))
7838 (match_operand 1 "" "")))
7839 (clobber (reg:SI 1))
7840 (clobber (reg:SI 2))
7841 (clobber (reg:SI 4))
7843 (use (const_int 1))])]
7844 "!TARGET_64BIT && reload_completed"
7845 [(parallel [(set (match_dup 0)
7846 (call (mem:SI (reg:SI 22))
7848 (clobber (reg:SI 1))
7849 (clobber (reg:SI 2))
7851 (use (const_int 1))])]
7854 (define_insn "*call_val_reg_pic_post_reload"
7855 [(set (match_operand 0 "" "")
7856 (call (mem:SI (reg:SI 22))
7857 (match_operand 1 "" "i")))
7858 (clobber (reg:SI 1))
7859 (clobber (reg:SI 2))
7861 (use (const_int 1))]
7865 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
7867 [(set_attr "type" "dyncall")
7868 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7870 ;; This pattern is split if it is necessary to save and restore the
7872 (define_insn "call_val_reg_64bit"
7873 [(set (match_operand 0 "" "")
7874 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7875 (match_operand 2 "" "i")))
7876 (clobber (reg:DI 2))
7877 (clobber (reg:DI 4))
7880 (use (const_int 1))]
7884 return output_indirect_call (insn, operands[1]);
7886 [(set_attr "type" "dyncall")
7887 (set (attr "length")
7888 (plus (symbol_ref "attr_length_indirect_call (insn)")
7889 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
7891 ;; Split out the PIC register save and restore after reload. This is
7892 ;; done only if the function returns. As the split is done after reload,
7893 ;; there are some situations in which we unnecessarily save and restore
7894 ;; %r4. This happens when there is a single call and the PIC register
7895 ;; is "dead" after the call. This isn't easy to fix as the usage of
7896 ;; the PIC register isn't completely determined until the reload pass.
7898 [(parallel [(set (match_operand 0 "" "")
7899 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7900 (match_operand 2 "" "")))
7901 (clobber (reg:DI 2))
7902 (clobber (reg:DI 4))
7905 (use (const_int 1))])]
7908 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
7909 [(set (reg:DI 4) (reg:DI 27))
7910 (parallel [(set (match_dup 0)
7911 (call (mem:SI (match_dup 1))
7913 (clobber (reg:DI 2))
7916 (use (const_int 1))])
7917 (set (reg:DI 27) (reg:DI 4))]
7920 ;; Remove the clobber of register 4 when optimizing. This has to be
7921 ;; done with a peephole optimization rather than a split because the
7922 ;; split sequence for a call must be longer than one instruction.
7924 [(parallel [(set (match_operand 0 "" "")
7925 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
7926 (match_operand 2 "" "")))
7927 (clobber (reg:DI 2))
7928 (clobber (reg:DI 4))
7931 (use (const_int 1))])]
7932 "TARGET_64BIT && reload_completed"
7933 [(parallel [(set (match_dup 0)
7934 (call (mem:SI (match_dup 1))
7936 (clobber (reg:DI 2))
7939 (use (const_int 1))])]
7942 (define_insn "*call_val_reg_64bit_post_reload"
7943 [(set (match_operand 0 "" "")
7944 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
7945 (match_operand 2 "" "i")))
7946 (clobber (reg:DI 2))
7949 (use (const_int 1))]
7953 return output_indirect_call (insn, operands[1]);
7955 [(set_attr "type" "dyncall")
7956 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
7958 ;; Call subroutine returning any type.
7960 (define_expand "untyped_call"
7961 [(parallel [(call (match_operand 0 "" "")
7963 (match_operand 1 "" "")
7964 (match_operand 2 "" "")])]
7970 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
7972 for (i = 0; i < XVECLEN (operands[2], 0); i++)
7974 rtx set = XVECEXP (operands[2], 0, i);
7975 emit_move_insn (SET_DEST (set), SET_SRC (set));
7978 /* The optimizer does not know that the call sets the function value
7979 registers we stored in the result block. We avoid problems by
7980 claiming that all hard registers are used and clobbered at this
7982 emit_insn (gen_blockage ());
7987 (define_expand "sibcall"
7988 [(call (match_operand:SI 0 "" "")
7989 (match_operand 1 "" ""))]
7990 "!TARGET_PORTABLE_RUNTIME"
7994 rtx nb = operands[1];
7996 op = XEXP (operands[0], 0);
8000 if (!virtuals_instantiated)
8001 emit_move_insn (arg_pointer_rtx,
8002 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8006 /* The loop pass can generate new libcalls after the virtual
8007 registers are instantiated when fpregs are disabled because
8008 the only method that we have for doing DImode multiplication
8009 is with a libcall. This could be trouble if we haven't
8010 allocated enough space for the outgoing arguments. */
8011 if (INTVAL (nb) > current_function_outgoing_args_size)
8014 emit_move_insn (arg_pointer_rtx,
8015 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8016 GEN_INT (STACK_POINTER_OFFSET + 64)));
8020 /* Indirect sibling calls are not allowed. */
8022 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
8024 call_insn = gen_sibcall_internal_symref (op, operands[1]);
8026 call_insn = emit_call_insn (call_insn);
8029 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8031 /* We don't have to restore the PIC register. */
8033 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8038 (define_insn "sibcall_internal_symref"
8039 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8040 (match_operand 1 "" "i"))
8041 (clobber (reg:SI 1))
8043 (use (const_int 0))]
8044 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8047 output_arg_descriptor (insn);
8048 return output_call (insn, operands[0], 1);
8050 [(set_attr "type" "call")
8051 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8053 (define_insn "sibcall_internal_symref_64bit"
8054 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
8055 (match_operand 1 "" "i"))
8056 (clobber (reg:DI 1))
8058 (use (const_int 0))]
8062 output_arg_descriptor (insn);
8063 return output_call (insn, operands[0], 1);
8065 [(set_attr "type" "call")
8066 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8068 (define_expand "sibcall_value"
8069 [(set (match_operand 0 "" "")
8070 (call (match_operand:SI 1 "" "")
8071 (match_operand 2 "" "")))]
8072 "!TARGET_PORTABLE_RUNTIME"
8076 rtx nb = operands[1];
8078 op = XEXP (operands[1], 0);
8082 if (!virtuals_instantiated)
8083 emit_move_insn (arg_pointer_rtx,
8084 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
8088 /* The loop pass can generate new libcalls after the virtual
8089 registers are instantiated when fpregs are disabled because
8090 the only method that we have for doing DImode multiplication
8091 is with a libcall. This could be trouble if we haven't
8092 allocated enough space for the outgoing arguments. */
8093 if (INTVAL (nb) > current_function_outgoing_args_size)
8096 emit_move_insn (arg_pointer_rtx,
8097 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8098 GEN_INT (STACK_POINTER_OFFSET + 64)));
8102 /* Indirect sibling calls are not allowed. */
8105 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
8108 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
8110 call_insn = emit_call_insn (call_insn);
8113 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
8115 /* We don't have to restore the PIC register. */
8117 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
8122 (define_insn "sibcall_value_internal_symref"
8123 [(set (match_operand 0 "" "")
8124 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8125 (match_operand 2 "" "i")))
8126 (clobber (reg:SI 1))
8128 (use (const_int 0))]
8129 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
8132 output_arg_descriptor (insn);
8133 return output_call (insn, operands[1], 1);
8135 [(set_attr "type" "call")
8136 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8138 (define_insn "sibcall_value_internal_symref_64bit"
8139 [(set (match_operand 0 "" "")
8140 (call (mem:SI (match_operand 1 "call_operand_address" ""))
8141 (match_operand 2 "" "i")))
8142 (clobber (reg:DI 1))
8144 (use (const_int 0))]
8148 output_arg_descriptor (insn);
8149 return output_call (insn, operands[1], 1);
8151 [(set_attr "type" "call")
8152 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
8158 [(set_attr "type" "move")
8159 (set_attr "length" "4")])
8161 ;; These are just placeholders so we know where branch tables
8163 (define_insn "begin_brtab"
8168 /* Only GAS actually supports this pseudo-op. */
8170 return \".begin_brtab\";
8174 [(set_attr "type" "move")
8175 (set_attr "length" "0")])
8177 (define_insn "end_brtab"
8182 /* Only GAS actually supports this pseudo-op. */
8184 return \".end_brtab\";
8188 [(set_attr "type" "move")
8189 (set_attr "length" "0")])
8191 ;;; EH does longjmp's from and within the data section. Thus,
8192 ;;; an interspace branch is required for the longjmp implementation.
8193 ;;; Registers r1 and r2 are used as scratch registers for the jump
8195 (define_expand "interspace_jump"
8197 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8198 (clobber (match_dup 1))])]
8202 operands[1] = gen_rtx_REG (word_mode, 2);
8206 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8207 (clobber (reg:SI 2))]
8208 "TARGET_PA_20 && !TARGET_64BIT"
8210 [(set_attr "type" "branch")
8211 (set_attr "length" "4")])
8214 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8215 (clobber (reg:SI 2))]
8216 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
8218 [(set_attr "type" "branch")
8219 (set_attr "length" "4")])
8222 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8223 (clobber (reg:SI 2))]
8225 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
8226 [(set_attr "type" "branch")
8227 (set_attr "length" "12")])
8230 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
8231 (clobber (reg:DI 2))]
8234 [(set_attr "type" "branch")
8235 (set_attr "length" "4")])
8237 (define_expand "builtin_longjmp"
8238 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
8242 /* The elements of the buffer are, in order: */
8243 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
8244 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8245 POINTER_SIZE / BITS_PER_UNIT));
8246 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
8247 (POINTER_SIZE * 2) / BITS_PER_UNIT));
8248 rtx pv = gen_rtx_REG (Pmode, 1);
8250 /* This bit is the same as expand_builtin_longjmp. */
8251 emit_move_insn (hard_frame_pointer_rtx, fp);
8252 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
8253 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
8254 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
8256 /* Load the label we are jumping through into r1 so that we know
8257 where to look for it when we get back to setjmp's function for
8258 restoring the gp. */
8259 emit_move_insn (pv, lab);
8261 /* Prevent the insns above from being scheduled into the delay slot
8262 of the interspace jump because the space register could change. */
8263 emit_insn (gen_blockage ());
8265 emit_jump_insn (gen_interspace_jump (pv));
8270 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8271 (define_expand "extzv"
8272 [(set (match_operand 0 "register_operand" "")
8273 (zero_extract (match_operand 1 "register_operand" "")
8274 (match_operand 2 "uint32_operand" "")
8275 (match_operand 3 "uint32_operand" "")))]
8279 HOST_WIDE_INT len = INTVAL (operands[2]);
8280 HOST_WIDE_INT pos = INTVAL (operands[3]);
8282 /* PA extraction insns don't support zero length bitfields or fields
8283 extending beyond the left or right-most bits. Also, we reject lengths
8284 equal to a word as they are better handled by the move patterns. */
8285 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8288 /* From mips.md: extract_bit_field doesn't verify that our source
8289 matches the predicate, so check it again here. */
8290 if (!register_operand (operands[1], VOIDmode))
8294 emit_insn (gen_extzv_64 (operands[0], operands[1],
8295 operands[2], operands[3]));
8297 emit_insn (gen_extzv_32 (operands[0], operands[1],
8298 operands[2], operands[3]));
8302 (define_insn "extzv_32"
8303 [(set (match_operand:SI 0 "register_operand" "=r")
8304 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8305 (match_operand:SI 2 "uint5_operand" "")
8306 (match_operand:SI 3 "uint5_operand" "")))]
8308 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
8309 [(set_attr "type" "shift")
8310 (set_attr "length" "4")])
8313 [(set (match_operand:SI 0 "register_operand" "=r")
8314 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
8316 (match_operand:SI 2 "register_operand" "q")))]
8318 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
8319 [(set_attr "type" "shift")
8320 (set_attr "length" "4")])
8322 (define_insn "extzv_64"
8323 [(set (match_operand:DI 0 "register_operand" "=r")
8324 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8325 (match_operand:DI 2 "uint32_operand" "")
8326 (match_operand:DI 3 "uint32_operand" "")))]
8328 "extrd,u %1,%3+%2-1,%2,%0"
8329 [(set_attr "type" "shift")
8330 (set_attr "length" "4")])
8333 [(set (match_operand:DI 0 "register_operand" "=r")
8334 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
8336 (match_operand:DI 2 "register_operand" "q")))]
8338 "extrd,u %1,%%sar,1,%0"
8339 [(set_attr "type" "shift")
8340 (set_attr "length" "4")])
8342 ;;; Operands 2 and 3 are assumed to be CONST_INTs.
8343 (define_expand "extv"
8344 [(set (match_operand 0 "register_operand" "")
8345 (sign_extract (match_operand 1 "register_operand" "")
8346 (match_operand 2 "uint32_operand" "")
8347 (match_operand 3 "uint32_operand" "")))]
8351 HOST_WIDE_INT len = INTVAL (operands[2]);
8352 HOST_WIDE_INT pos = INTVAL (operands[3]);
8354 /* PA extraction insns don't support zero length bitfields or fields
8355 extending beyond the left or right-most bits. Also, we reject lengths
8356 equal to a word as they are better handled by the move patterns. */
8357 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8360 /* From mips.md: extract_bit_field doesn't verify that our source
8361 matches the predicate, so check it again here. */
8362 if (!register_operand (operands[1], VOIDmode))
8366 emit_insn (gen_extv_64 (operands[0], operands[1],
8367 operands[2], operands[3]));
8369 emit_insn (gen_extv_32 (operands[0], operands[1],
8370 operands[2], operands[3]));
8374 (define_insn "extv_32"
8375 [(set (match_operand:SI 0 "register_operand" "=r")
8376 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8377 (match_operand:SI 2 "uint5_operand" "")
8378 (match_operand:SI 3 "uint5_operand" "")))]
8380 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
8381 [(set_attr "type" "shift")
8382 (set_attr "length" "4")])
8385 [(set (match_operand:SI 0 "register_operand" "=r")
8386 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
8388 (match_operand:SI 2 "register_operand" "q")))]
8390 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
8391 [(set_attr "type" "shift")
8392 (set_attr "length" "4")])
8394 (define_insn "extv_64"
8395 [(set (match_operand:DI 0 "register_operand" "=r")
8396 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8397 (match_operand:DI 2 "uint32_operand" "")
8398 (match_operand:DI 3 "uint32_operand" "")))]
8400 "extrd,s %1,%3+%2-1,%2,%0"
8401 [(set_attr "type" "shift")
8402 (set_attr "length" "4")])
8405 [(set (match_operand:DI 0 "register_operand" "=r")
8406 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
8408 (match_operand:DI 2 "register_operand" "q")))]
8410 "extrd,s %1,%%sar,1,%0"
8411 [(set_attr "type" "shift")
8412 (set_attr "length" "4")])
8414 ;;; Operands 1 and 2 are assumed to be CONST_INTs.
8415 (define_expand "insv"
8416 [(set (zero_extract (match_operand 0 "register_operand" "")
8417 (match_operand 1 "uint32_operand" "")
8418 (match_operand 2 "uint32_operand" ""))
8419 (match_operand 3 "arith5_operand" ""))]
8423 HOST_WIDE_INT len = INTVAL (operands[1]);
8424 HOST_WIDE_INT pos = INTVAL (operands[2]);
8426 /* PA insertion insns don't support zero length bitfields or fields
8427 extending beyond the left or right-most bits. Also, we reject lengths
8428 equal to a word as they are better handled by the move patterns. */
8429 if (len <= 0 || len >= BITS_PER_WORD || pos < 0 || pos + len > BITS_PER_WORD)
8432 /* From mips.md: insert_bit_field doesn't verify that our destination
8433 matches the predicate, so check it again here. */
8434 if (!register_operand (operands[0], VOIDmode))
8438 emit_insn (gen_insv_64 (operands[0], operands[1],
8439 operands[2], operands[3]));
8441 emit_insn (gen_insv_32 (operands[0], operands[1],
8442 operands[2], operands[3]));
8446 (define_insn "insv_32"
8447 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
8448 (match_operand:SI 1 "uint5_operand" "")
8449 (match_operand:SI 2 "uint5_operand" ""))
8450 (match_operand:SI 3 "arith5_operand" "r,L"))]
8453 {dep|depw} %3,%2+%1-1,%1,%0
8454 {depi|depwi} %3,%2+%1-1,%1,%0"
8455 [(set_attr "type" "shift,shift")
8456 (set_attr "length" "4,4")])
8458 ;; Optimize insertion of const_int values of type 1...1xxxx.
8460 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
8461 (match_operand:SI 1 "uint5_operand" "")
8462 (match_operand:SI 2 "uint5_operand" ""))
8463 (match_operand:SI 3 "const_int_operand" ""))]
8464 "(INTVAL (operands[3]) & 0x10) != 0 &&
8465 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8468 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8469 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
8471 [(set_attr "type" "shift")
8472 (set_attr "length" "4")])
8474 (define_insn "insv_64"
8475 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
8476 (match_operand:DI 1 "uint32_operand" "")
8477 (match_operand:DI 2 "uint32_operand" ""))
8478 (match_operand:DI 3 "arith32_operand" "r,L"))]
8481 depd %3,%2+%1-1,%1,%0
8482 depdi %3,%2+%1-1,%1,%0"
8483 [(set_attr "type" "shift,shift")
8484 (set_attr "length" "4,4")])
8486 ;; Optimize insertion of const_int values of type 1...1xxxx.
8488 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
8489 (match_operand:DI 1 "uint32_operand" "")
8490 (match_operand:DI 2 "uint32_operand" ""))
8491 (match_operand:DI 3 "const_int_operand" ""))]
8492 "(INTVAL (operands[3]) & 0x10) != 0
8494 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
8497 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
8498 return \"depdi %3,%2+%1-1,%1,%0\";
8500 [(set_attr "type" "shift")
8501 (set_attr "length" "4")])
8504 [(set (match_operand:DI 0 "register_operand" "=r")
8505 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
8508 "depd,z %1,31,32,%0"
8509 [(set_attr "type" "shift")
8510 (set_attr "length" "4")])
8512 ;; This insn is used for some loop tests, typically loops reversed when
8513 ;; strength reduction is used. It is actually created when the instruction
8514 ;; combination phase combines the special loop test. Since this insn
8515 ;; is both a jump insn and has an output, it must deal with its own
8516 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
8517 ;; to not choose the register alternatives in the event a reload is needed.
8518 (define_insn "decrement_and_branch_until_zero"
8521 (match_operator 2 "comparison_operator"
8523 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
8524 (match_operand:SI 1 "int5_operand" "L,L,L"))
8526 (label_ref (match_operand 3 "" ""))
8529 (plus:SI (match_dup 0) (match_dup 1)))
8530 (clobber (match_scratch:SI 4 "=X,r,r"))]
8532 "* return output_dbra (operands, insn, which_alternative); "
8533 ;; Do not expect to understand this the first time through.
8534 [(set_attr "type" "cbranch,multi,multi")
8535 (set (attr "length")
8536 (if_then_else (eq_attr "alternative" "0")
8537 ;; Loop counter in register case
8538 ;; Short branch has length of 4
8539 ;; Long branch has length of 8
8540 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8545 ;; Loop counter in FP reg case.
8546 ;; Extra goo to deal with additional reload insns.
8547 (if_then_else (eq_attr "alternative" "1")
8548 (if_then_else (lt (match_dup 3) (pc))
8550 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
8555 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8559 ;; Loop counter in memory case.
8560 ;; Extra goo to deal with additional reload insns.
8561 (if_then_else (lt (match_dup 3) (pc))
8563 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8568 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8571 (const_int 16))))))])
8576 (match_operator 2 "movb_comparison_operator"
8577 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8578 (label_ref (match_operand 3 "" ""))
8580 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8583 "* return output_movb (operands, insn, which_alternative, 0); "
8584 ;; Do not expect to understand this the first time through.
8585 [(set_attr "type" "cbranch,multi,multi,multi")
8586 (set (attr "length")
8587 (if_then_else (eq_attr "alternative" "0")
8588 ;; Loop counter in register case
8589 ;; Short branch has length of 4
8590 ;; Long branch has length of 8
8591 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8596 ;; Loop counter in FP reg case.
8597 ;; Extra goo to deal with additional reload insns.
8598 (if_then_else (eq_attr "alternative" "1")
8599 (if_then_else (lt (match_dup 3) (pc))
8601 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8606 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8610 ;; Loop counter in memory or sar case.
8611 ;; Extra goo to deal with additional reload insns.
8613 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8616 (const_int 12)))))])
8618 ;; Handle negated branch.
8622 (match_operator 2 "movb_comparison_operator"
8623 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
8625 (label_ref (match_operand 3 "" ""))))
8626 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
8629 "* return output_movb (operands, insn, which_alternative, 1); "
8630 ;; Do not expect to understand this the first time through.
8631 [(set_attr "type" "cbranch,multi,multi,multi")
8632 (set (attr "length")
8633 (if_then_else (eq_attr "alternative" "0")
8634 ;; Loop counter in register case
8635 ;; Short branch has length of 4
8636 ;; Long branch has length of 8
8637 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8642 ;; Loop counter in FP reg case.
8643 ;; Extra goo to deal with additional reload insns.
8644 (if_then_else (eq_attr "alternative" "1")
8645 (if_then_else (lt (match_dup 3) (pc))
8647 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
8652 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8656 ;; Loop counter in memory or SAR case.
8657 ;; Extra goo to deal with additional reload insns.
8659 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8662 (const_int 12)))))])
8665 [(set (pc) (label_ref (match_operand 3 "" "" )))
8666 (set (match_operand:SI 0 "ireg_operand" "=r")
8667 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
8668 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
8669 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
8672 return output_parallel_addb (operands, get_attr_length (insn));
8674 [(set_attr "type" "parallel_branch")
8675 (set (attr "length")
8676 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
8682 [(set (pc) (label_ref (match_operand 2 "" "" )))
8683 (set (match_operand:SF 0 "ireg_operand" "=r")
8684 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
8688 return output_parallel_movb (operands, get_attr_length (insn));
8690 [(set_attr "type" "parallel_branch")
8691 (set (attr "length")
8692 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8698 [(set (pc) (label_ref (match_operand 2 "" "" )))
8699 (set (match_operand:SI 0 "ireg_operand" "=r")
8700 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
8704 return output_parallel_movb (operands, get_attr_length (insn));
8706 [(set_attr "type" "parallel_branch")
8707 (set (attr "length")
8708 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8714 [(set (pc) (label_ref (match_operand 2 "" "" )))
8715 (set (match_operand:HI 0 "ireg_operand" "=r")
8716 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
8720 return output_parallel_movb (operands, get_attr_length (insn));
8722 [(set_attr "type" "parallel_branch")
8723 (set (attr "length")
8724 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8730 [(set (pc) (label_ref (match_operand 2 "" "" )))
8731 (set (match_operand:QI 0 "ireg_operand" "=r")
8732 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
8736 return output_parallel_movb (operands, get_attr_length (insn));
8738 [(set_attr "type" "parallel_branch")
8739 (set (attr "length")
8740 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
8746 [(set (match_operand 0 "register_operand" "=f")
8747 (mult (match_operand 1 "register_operand" "f")
8748 (match_operand 2 "register_operand" "f")))
8749 (set (match_operand 3 "register_operand" "+f")
8750 (plus (match_operand 4 "register_operand" "f")
8751 (match_operand 5 "register_operand" "f")))]
8752 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8753 && reload_completed && fmpyaddoperands (operands)"
8756 if (GET_MODE (operands[0]) == DFmode)
8758 if (rtx_equal_p (operands[3], operands[5]))
8759 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8761 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8765 if (rtx_equal_p (operands[3], operands[5]))
8766 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8768 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8771 [(set_attr "type" "fpalu")
8772 (set_attr "length" "4")])
8775 [(set (match_operand 3 "register_operand" "+f")
8776 (plus (match_operand 4 "register_operand" "f")
8777 (match_operand 5 "register_operand" "f")))
8778 (set (match_operand 0 "register_operand" "=f")
8779 (mult (match_operand 1 "register_operand" "f")
8780 (match_operand 2 "register_operand" "f")))]
8781 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8782 && reload_completed && fmpyaddoperands (operands)"
8785 if (GET_MODE (operands[0]) == DFmode)
8787 if (rtx_equal_p (operands[3], operands[5]))
8788 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
8790 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
8794 if (rtx_equal_p (operands[3], operands[5]))
8795 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
8797 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
8800 [(set_attr "type" "fpalu")
8801 (set_attr "length" "4")])
8804 [(set (match_operand 0 "register_operand" "=f")
8805 (mult (match_operand 1 "register_operand" "f")
8806 (match_operand 2 "register_operand" "f")))
8807 (set (match_operand 3 "register_operand" "+f")
8808 (minus (match_operand 4 "register_operand" "f")
8809 (match_operand 5 "register_operand" "f")))]
8810 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8811 && reload_completed && fmpysuboperands (operands)"
8814 if (GET_MODE (operands[0]) == DFmode)
8815 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8817 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8819 [(set_attr "type" "fpalu")
8820 (set_attr "length" "4")])
8823 [(set (match_operand 3 "register_operand" "+f")
8824 (minus (match_operand 4 "register_operand" "f")
8825 (match_operand 5 "register_operand" "f")))
8826 (set (match_operand 0 "register_operand" "=f")
8827 (mult (match_operand 1 "register_operand" "f")
8828 (match_operand 2 "register_operand" "f")))]
8829 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
8830 && reload_completed && fmpysuboperands (operands)"
8833 if (GET_MODE (operands[0]) == DFmode)
8834 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
8836 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
8838 [(set_attr "type" "fpalu")
8839 (set_attr "length" "4")])
8841 ;; Clean up turds left by reload.
8843 [(set (match_operand 0 "move_dest_operand" "")
8844 (match_operand 1 "register_operand" "fr"))
8845 (set (match_operand 2 "register_operand" "fr")
8848 && GET_CODE (operands[0]) == MEM
8849 && ! MEM_VOLATILE_P (operands[0])
8850 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8851 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8852 && GET_MODE (operands[0]) == DFmode
8853 && GET_CODE (operands[1]) == REG
8854 && GET_CODE (operands[2]) == REG
8855 && ! side_effects_p (XEXP (operands[0], 0))
8856 && REGNO_REG_CLASS (REGNO (operands[1]))
8857 == REGNO_REG_CLASS (REGNO (operands[2]))"
8862 if (FP_REG_P (operands[1]))
8863 output_asm_insn (output_fp_move_double (operands), operands);
8865 output_asm_insn (output_move_double (operands), operands);
8867 if (rtx_equal_p (operands[1], operands[2]))
8870 xoperands[0] = operands[2];
8871 xoperands[1] = operands[1];
8873 if (FP_REG_P (xoperands[1]))
8874 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8876 output_asm_insn (output_move_double (xoperands), xoperands);
8882 [(set (match_operand 0 "register_operand" "fr")
8883 (match_operand 1 "move_src_operand" ""))
8884 (set (match_operand 2 "register_operand" "fr")
8887 && GET_CODE (operands[1]) == MEM
8888 && ! MEM_VOLATILE_P (operands[1])
8889 && GET_MODE (operands[0]) == GET_MODE (operands[1])
8890 && GET_MODE (operands[0]) == GET_MODE (operands[2])
8891 && GET_MODE (operands[0]) == DFmode
8892 && GET_CODE (operands[0]) == REG
8893 && GET_CODE (operands[2]) == REG
8894 && ! side_effects_p (XEXP (operands[1], 0))
8895 && REGNO_REG_CLASS (REGNO (operands[0]))
8896 == REGNO_REG_CLASS (REGNO (operands[2]))"
8901 if (FP_REG_P (operands[0]))
8902 output_asm_insn (output_fp_move_double (operands), operands);
8904 output_asm_insn (output_move_double (operands), operands);
8906 xoperands[0] = operands[2];
8907 xoperands[1] = operands[0];
8909 if (FP_REG_P (xoperands[1]))
8910 output_asm_insn (output_fp_move_double (xoperands), xoperands);
8912 output_asm_insn (output_move_double (xoperands), xoperands);
8917 ;; Flush the I and D cache lines from the start address (operand0)
8918 ;; to the end address (operand1). No lines are flushed if the end
8919 ;; address is less than the start address (unsigned).
8921 ;; Because the range of memory flushed is variable and the size of
8922 ;; a MEM can only be a CONST_INT, the patterns specify that they
8923 ;; perform an unspecified volatile operation on all memory.
8925 ;; The address range for an icache flush must lie within a single
8926 ;; space on targets with non-equivalent space registers.
8928 ;; This is used by the trampoline code for nested functions.
8930 ;; Operand 0 contains the start address.
8931 ;; Operand 1 contains the end address.
8932 ;; Operand 2 contains the line length to use.
8933 ;; Operands 3 and 4 (icacheflush) are clobbered scratch registers.
8934 (define_insn "dcacheflush"
8936 (unspec_volatile [(mem:BLK (scratch))] 0)
8937 (use (match_operand 0 "pmode_register_operand" "r"))
8938 (use (match_operand 1 "pmode_register_operand" "r"))
8939 (use (match_operand 2 "pmode_register_operand" "r"))
8940 (clobber (match_scratch 3 "=&0"))]
8945 return \"cmpb,*<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8947 return \"cmpb,<<=,n %3,%1,.\;fdc,m %2(%3)\;sync\";
8949 [(set_attr "type" "multi")
8950 (set_attr "length" "12")])
8952 (define_insn "icacheflush"
8954 (unspec_volatile [(mem:BLK (scratch))] 0)
8955 (use (match_operand 0 "pmode_register_operand" "r"))
8956 (use (match_operand 1 "pmode_register_operand" "r"))
8957 (use (match_operand 2 "pmode_register_operand" "r"))
8958 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
8959 (clobber (match_operand 4 "pmode_register_operand" "=&r"))
8960 (clobber (match_scratch 5 "=&0"))]
8965 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,*<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8967 return \"mfsp %%sr0,%4\;ldsid (%5),%3\;mtsp %3,%%sr0\;cmpb,<<=,n %5,%1,.\;fic,m %2(%%sr0,%5)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop\";
8969 [(set_attr "type" "multi")
8970 (set_attr "length" "52")])
8972 ;; An out-of-line prologue.
8973 (define_insn "outline_prologue_call"
8974 [(unspec_volatile [(const_int 0)] 0)
8975 (clobber (reg:SI 31))
8976 (clobber (reg:SI 22))
8977 (clobber (reg:SI 21))
8978 (clobber (reg:SI 20))
8979 (clobber (reg:SI 19))
8980 (clobber (reg:SI 1))]
8984 extern int frame_pointer_needed;
8986 /* We need two different versions depending on whether or not we
8987 need a frame pointer. Also note that we return to the instruction
8988 immediately after the branch rather than two instructions after the
8989 break as normally is the case. */
8990 if (frame_pointer_needed)
8992 /* Must import the magic millicode routine(s). */
8993 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
8995 if (TARGET_PORTABLE_RUNTIME)
8997 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
8998 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
9002 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
9006 /* Must import the magic millicode routine(s). */
9007 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
9009 if (TARGET_PORTABLE_RUNTIME)
9011 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
9012 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
9015 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
9019 [(set_attr "type" "multi")
9020 (set_attr "length" "8")])
9022 ;; An out-of-line epilogue.
9023 (define_insn "outline_epilogue_call"
9024 [(unspec_volatile [(const_int 1)] 0)
9027 (clobber (reg:SI 31))
9028 (clobber (reg:SI 22))
9029 (clobber (reg:SI 21))
9030 (clobber (reg:SI 20))
9031 (clobber (reg:SI 19))
9032 (clobber (reg:SI 2))
9033 (clobber (reg:SI 1))]
9037 extern int frame_pointer_needed;
9039 /* We need two different versions depending on whether or not we
9040 need a frame pointer. Also note that we return to the instruction
9041 immediately after the branch rather than two instructions after the
9042 break as normally is the case. */
9043 if (frame_pointer_needed)
9045 /* Must import the magic millicode routine. */
9046 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
9048 /* The out-of-line prologue will make sure we return to the right
9050 if (TARGET_PORTABLE_RUNTIME)
9052 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
9053 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
9057 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
9061 /* Must import the magic millicode routine. */
9062 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
9064 /* The out-of-line prologue will make sure we return to the right
9066 if (TARGET_PORTABLE_RUNTIME)
9068 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
9069 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
9072 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
9076 [(set_attr "type" "multi")
9077 (set_attr "length" "8")])
9079 ;; Given a function pointer, canonicalize it so it can be
9080 ;; reliably compared to another function pointer. */
9081 (define_expand "canonicalize_funcptr_for_compare"
9082 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
9083 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9084 (clobber (match_dup 2))
9085 (clobber (reg:SI 26))
9086 (clobber (reg:SI 22))
9087 (clobber (reg:SI 31))])
9088 (set (match_operand:SI 0 "register_operand" "")
9090 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
9095 rtx canonicalize_funcptr_for_compare_libfunc
9096 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
9098 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
9099 operands[0], LCT_NORMAL, Pmode,
9100 1, operands[1], Pmode);
9104 operands[2] = gen_reg_rtx (SImode);
9105 if (GET_CODE (operands[1]) != REG)
9107 rtx tmp = gen_reg_rtx (Pmode);
9108 emit_move_insn (tmp, operands[1]);
9114 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
9115 (clobber (match_operand:SI 0 "register_operand" "=a"))
9116 (clobber (reg:SI 26))
9117 (clobber (reg:SI 22))
9118 (clobber (reg:SI 31))]
9122 int length = get_attr_length (insn);
9125 xoperands[0] = GEN_INT (length - 8);
9126 xoperands[1] = GEN_INT (length - 16);
9128 /* Must import the magic millicode routine. */
9129 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
9131 /* This is absolutely amazing.
9133 First, copy our input parameter into %r29 just in case we don't
9134 need to call $$sh_func_adrs. */
9135 output_asm_insn (\"copy %%r26,%%r29\", NULL);
9136 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
9138 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
9139 we use %r26 unchanged. */
9140 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
9141 output_asm_insn (\"ldi 4096,%%r31\", NULL);
9143 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
9144 4096, then again we use %r26 unchanged. */
9145 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
9147 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
9148 return output_millicode_call (insn,
9149 gen_rtx_SYMBOL_REF (SImode,
9150 \"$$sh_func_adrs\"));
9152 [(set_attr "type" "multi")
9153 (set (attr "length")
9154 (plus (symbol_ref "attr_length_millicode_call (insn)")
9157 ;; On the PA, the PIC register is call clobbered, so it must
9158 ;; be saved & restored around calls by the caller. If the call
9159 ;; doesn't return normally (nonlocal goto, or an exception is
9160 ;; thrown), then the code at the exception handler label must
9161 ;; restore the PIC register.
9162 (define_expand "exception_receiver"
9167 /* On the 64-bit port, we need a blockage because there is
9168 confusion regarding the dependence of the restore on the
9169 frame pointer. As a result, the frame pointer and pic
9170 register restores sometimes are interchanged erroneously. */
9172 emit_insn (gen_blockage ());
9173 /* Restore the PIC register using hppa_pic_save_rtx (). The
9174 PIC register is not saved in the frame in 64-bit ABI. */
9175 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9176 emit_insn (gen_blockage ());
9180 (define_expand "builtin_setjmp_receiver"
9181 [(label_ref (match_operand 0 "" ""))]
9186 emit_insn (gen_blockage ());
9187 /* Restore the PIC register. Hopefully, this will always be from
9188 a stack slot. The only registers that are valid after a
9189 builtin_longjmp are the stack and frame pointers. */
9190 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
9191 emit_insn (gen_blockage ());
9195 ;; Allocate new stack space and update the saved stack pointer in the
9196 ;; frame marker. The HP C compilers also copy additional words in the
9197 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
9198 ;; The 32-bit compiler copies the word at -16 (Static Link). We
9199 ;; currently don't copy these values.
9201 ;; Since the copy of the frame marker can't be done atomically, I
9202 ;; suspect that using it for unwind purposes may be somewhat unreliable.
9203 ;; The HP compilers appear to raise the stack and copy the frame
9204 ;; marker in a strict instruction sequence. This suggests that the
9205 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
9206 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
9207 ;; as GAS doesn't support it, or try to keep the instructions emitted
9208 ;; here in strict sequence.
9209 (define_expand "allocate_stack"
9210 [(match_operand 0 "" "")
9211 (match_operand 1 "" "")]
9217 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
9218 in operand 0 before adjusting the stack. */
9219 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
9220 anti_adjust_stack (operands[1]);
9221 if (TARGET_HPUX_UNWIND_LIBRARY)
9223 addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
9224 GEN_INT (TARGET_64BIT ? -8 : -4));
9225 emit_move_insn (gen_rtx_MEM (word_mode, addr), frame_pointer_rtx);
9227 if (!TARGET_64BIT && flag_pic)
9229 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
9230 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);