1 ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2 ;; Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 ;; 2002, 2003 Free Software Foundation, Inc.
4 ;; Contributed by the Center for Software Science at the University
7 ;; This file is part of GNU CC.
9 ;; GNU CC is free software; you can redistribute it and/or modify
10 ;; it under the terms of the GNU General Public License as published by
11 ;; the Free Software Foundation; either version 2, or (at your option)
14 ;; GNU CC is distributed in the hope that it will be useful,
15 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 ;; GNU General Public License for more details.
19 ;; You should have received a copy of the GNU General Public License
20 ;; along with GNU CC; see the file COPYING. If not, write to
21 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
22 ;; Boston, MA 02111-1307, USA.
24 ;; This gcc Version 2 machine description is inspired by sparc.md and
27 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
29 ;; Insn type. Used to default other attribute values.
31 ;; type "unary" insns have one input operand (1) and one output operand (0)
32 ;; type "binary" insns have two input operands (1,2) and one output (0)
35 "move,unary,binary,shift,nullshift,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,milli,parallel_branch"
36 (const_string "binary"))
38 (define_attr "pa_combine_type"
39 "fmpy,faddsub,uncond_branch,addmove,none"
40 (const_string "none"))
42 ;; Processor type (for scheduling, not code generation) -- this attribute
43 ;; must exactly match the processor_type enumeration in pa.h.
45 ;; FIXME: Add 800 scheduling for completeness?
47 (define_attr "cpu" "700,7100,7100LC,7200,7300,8000" (const (symbol_ref "pa_cpu_attr")))
49 ;; Length (in # of bytes).
50 (define_attr "length" ""
51 (cond [(eq_attr "type" "load,fpload")
52 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
53 (const_int 8) (const_int 4))
55 (eq_attr "type" "store,fpstore")
56 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
57 (const_int 8) (const_int 4))
59 (eq_attr "type" "binary,shift,nullshift")
60 (if_then_else (match_operand 2 "arith_operand" "")
61 (const_int 4) (const_int 12))
63 (eq_attr "type" "move,unary,shift,nullshift")
64 (if_then_else (match_operand 1 "arith_operand" "")
65 (const_int 4) (const_int 8))]
69 (define_asm_attributes
70 [(set_attr "length" "4")
71 (set_attr "type" "multi")])
73 ;; Attributes for instruction and branch scheduling
75 ;; For conditional branches.
76 (define_attr "in_branch_delay" "false,true"
77 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
78 (eq_attr "length" "4"))
80 (const_string "false")))
82 ;; Disallow instructions which use the FPU since they will tie up the FPU
83 ;; even if the instruction is nullified.
84 (define_attr "in_nullified_branch_delay" "false,true"
85 (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,parallel_branch")
86 (eq_attr "length" "4"))
88 (const_string "false")))
90 ;; For calls and millicode calls. Allow unconditional branches in the
92 (define_attr "in_call_delay" "false,true"
93 (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
94 (eq_attr "length" "4"))
96 (eq_attr "type" "uncond_branch")
97 (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
100 (const_string "false"))]
101 (const_string "false")))
104 ;; Call delay slot description.
105 (define_delay (eq_attr "type" "call")
106 [(eq_attr "in_call_delay" "true") (nil) (nil)])
108 ;; Millicode call delay slot description.
109 (define_delay (eq_attr "type" "milli")
110 [(eq_attr "in_call_delay" "true") (nil) (nil)])
112 ;; Return and other similar instructions.
113 (define_delay (eq_attr "type" "branch,parallel_branch")
114 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
116 ;; Floating point conditional branch delay slot description and
117 (define_delay (eq_attr "type" "fbranch")
118 [(eq_attr "in_branch_delay" "true")
119 (eq_attr "in_nullified_branch_delay" "true")
122 ;; Integer conditional branch delay slot description.
123 ;; Nullification of conditional branches on the PA is dependent on the
124 ;; direction of the branch. Forward branches nullify true and
125 ;; backward branches nullify false. If the direction is unknown
126 ;; then nullification is not allowed.
127 (define_delay (eq_attr "type" "cbranch")
128 [(eq_attr "in_branch_delay" "true")
129 (and (eq_attr "in_nullified_branch_delay" "true")
130 (attr_flag "forward"))
131 (and (eq_attr "in_nullified_branch_delay" "true")
132 (attr_flag "backward"))])
134 (define_delay (and (eq_attr "type" "uncond_branch")
135 (eq (symbol_ref "following_call (insn)")
137 [(eq_attr "in_branch_delay" "true") (nil) (nil)])
139 ;; Memory. Disregarding Cache misses, the Mustang memory times are:
140 ;; load: 2, fpload: 3
141 ;; store, fpstore: 3, no D-cache operations should be scheduled.
143 ;; The Timex (aka 700) has two floating-point units: ALU, and MUL/DIV/SQRT.
145 ;; Instruction Time Unit Minimum Distance (unit contention)
152 ;; fmpyadd 3 ALU,MPY 2
153 ;; fmpysub 3 ALU,MPY 2
154 ;; fmpycfxt 3 ALU,MPY 2
157 ;; fdiv,sgl 10 MPY 10
158 ;; fdiv,dbl 12 MPY 12
159 ;; fsqrt,sgl 14 MPY 14
160 ;; fsqrt,dbl 18 MPY 18
162 ;; We don't model fmpyadd/fmpysub properly as those instructions
163 ;; keep both the FP ALU and MPY units busy. Given that these
164 ;; processors are obsolete, I'm not going to spend the time to
165 ;; model those instructions correctly.
167 (define_automaton "pa700")
168 (define_cpu_unit "dummy_700,mem_700,fpalu_700,fpmpy_700" "pa700")
170 (define_insn_reservation "W0" 4
171 (and (eq_attr "type" "fpcc")
172 (eq_attr "cpu" "700"))
175 (define_insn_reservation "W1" 3
176 (and (eq_attr "type" "fpalu")
177 (eq_attr "cpu" "700"))
180 (define_insn_reservation "W2" 3
181 (and (eq_attr "type" "fpmulsgl,fpmuldbl")
182 (eq_attr "cpu" "700"))
185 (define_insn_reservation "W3" 10
186 (and (eq_attr "type" "fpdivsgl")
187 (eq_attr "cpu" "700"))
190 (define_insn_reservation "W4" 12
191 (and (eq_attr "type" "fpdivdbl")
192 (eq_attr "cpu" "700"))
195 (define_insn_reservation "W5" 14
196 (and (eq_attr "type" "fpsqrtsgl")
197 (eq_attr "cpu" "700"))
200 (define_insn_reservation "W6" 18
201 (and (eq_attr "type" "fpsqrtdbl")
202 (eq_attr "cpu" "700"))
205 (define_insn_reservation "W7" 2
206 (and (eq_attr "type" "load")
207 (eq_attr "cpu" "700"))
210 (define_insn_reservation "W8" 2
211 (and (eq_attr "type" "fpload")
212 (eq_attr "cpu" "700"))
215 (define_insn_reservation "W9" 3
216 (and (eq_attr "type" "store")
217 (eq_attr "cpu" "700"))
220 (define_insn_reservation "W10" 3
221 (and (eq_attr "type" "fpstore")
222 (eq_attr "cpu" "700"))
225 (define_insn_reservation "W11" 1
226 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,load,fpload,store,fpstore")
227 (eq_attr "cpu" "700"))
230 ;; We have a bypass for all computations in the FP unit which feed an
231 ;; FP store as long as the sizes are the same.
232 (define_bypass 2 "W1,W2" "W10" "hppa_fpstore_bypass_p")
233 (define_bypass 9 "W3" "W10" "hppa_fpstore_bypass_p")
234 (define_bypass 11 "W4" "W10" "hppa_fpstore_bypass_p")
235 (define_bypass 13 "W5" "W10" "hppa_fpstore_bypass_p")
236 (define_bypass 17 "W6" "W10" "hppa_fpstore_bypass_p")
238 ;; We have an "anti-bypass" for FP loads which feed an FP store.
239 (define_bypass 4 "W8" "W10" "hppa_fpstore_bypass_p")
241 ;; Function units for the 7100 and 7150. The 7100/7150 can dual-issue
242 ;; floating point computations with non-floating point computations (fp loads
243 ;; and stores are not fp computations).
245 ;; Memory. Disregarding Cache misses, memory loads take two cycles; stores also
246 ;; take two cycles, during which no Dcache operations should be scheduled.
247 ;; Any special cases are handled in pa_adjust_cost. The 7100, 7150 and 7100LC
248 ;; all have the same memory characteristics if one disregards cache misses.
250 ;; The 7100/7150 has three floating-point units: ALU, MUL, and DIV.
251 ;; There's no value in modeling the ALU and MUL separately though
252 ;; since there can never be a functional unit conflict given the
253 ;; latency and issue rates for those units.
256 ;; Instruction Time Unit Minimum Distance (unit contention)
263 ;; fmpyadd 2 ALU,MPY 1
264 ;; fmpysub 2 ALU,MPY 1
265 ;; fmpycfxt 2 ALU,MPY 1
269 ;; fdiv,dbl 15 DIV 15
271 ;; fsqrt,dbl 15 DIV 15
273 (define_automaton "pa7100")
274 (define_cpu_unit "i_7100, f_7100,fpmac_7100,fpdivsqrt_7100,mem_7100" "pa7100")
276 (define_insn_reservation "X0" 2
277 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
278 (eq_attr "cpu" "7100"))
281 (define_insn_reservation "X1" 8
282 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl")
283 (eq_attr "cpu" "7100"))
284 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*7")
286 (define_insn_reservation "X2" 15
287 (and (eq_attr "type" "fpdivdbl,fpsqrtdbl")
288 (eq_attr "cpu" "7100"))
289 "f_7100+fpdivsqrt_7100,fpdivsqrt_7100*14")
291 (define_insn_reservation "X3" 2
292 (and (eq_attr "type" "load")
293 (eq_attr "cpu" "7100"))
296 (define_insn_reservation "X4" 2
297 (and (eq_attr "type" "fpload")
298 (eq_attr "cpu" "7100"))
301 (define_insn_reservation "X5" 2
302 (and (eq_attr "type" "store")
303 (eq_attr "cpu" "7100"))
304 "i_7100+mem_7100,mem_7100")
306 (define_insn_reservation "X6" 2
307 (and (eq_attr "type" "fpstore")
308 (eq_attr "cpu" "7100"))
309 "i_7100+mem_7100,mem_7100")
311 (define_insn_reservation "X7" 1
312 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore")
313 (eq_attr "cpu" "7100"))
316 ;; We have a bypass for all computations in the FP unit which feed an
317 ;; FP store as long as the sizes are the same.
318 (define_bypass 1 "X0" "X6" "hppa_fpstore_bypass_p")
319 (define_bypass 7 "X1" "X6" "hppa_fpstore_bypass_p")
320 (define_bypass 14 "X2" "X6" "hppa_fpstore_bypass_p")
322 ;; We have an "anti-bypass" for FP loads which feed an FP store.
323 (define_bypass 3 "X4" "X6" "hppa_fpstore_bypass_p")
325 ;; The 7100LC has three floating-point units: ALU, MUL, and DIV.
326 ;; There's no value in modeling the ALU and MUL separately though
327 ;; since there can never be a functional unit conflict that
328 ;; can be avoided given the latency, issue rates and mandatory
329 ;; one cycle cpu-wide lock for a double precision fp multiply.
332 ;; Instruction Time Unit Minimum Distance (unit contention)
339 ;; fmpyadd,sgl 2 ALU,MPY 1
340 ;; fmpyadd,dbl 3 ALU,MPY 2
341 ;; fmpysub,sgl 2 ALU,MPY 1
342 ;; fmpysub,dbl 3 ALU,MPY 2
343 ;; fmpycfxt,sgl 2 ALU,MPY 1
344 ;; fmpycfxt,dbl 3 ALU,MPY 2
349 ;; fdiv,dbl 15 DIV 15
351 ;; fsqrt,dbl 15 DIV 15
353 ;; The PA7200 is just like the PA7100LC except that there is
354 ;; no store-store penalty.
356 ;; The PA7300 is just like the PA7200 except that there is
357 ;; no store-load penalty.
359 ;; Note there are some aspects of the 7100LC we are not modeling
360 ;; at the moment. I'll be reviewing the 7100LC scheduling info
361 ;; shortly and updating this description.
365 ;; other issue modeling
367 (define_automaton "pa7100lc")
368 (define_cpu_unit "i0_7100lc, i1_7100lc, f_7100lc" "pa7100lc")
369 (define_cpu_unit "fpmac_7100lc" "pa7100lc")
370 (define_cpu_unit "mem_7100lc" "pa7100lc")
372 ;; Double precision multiplies lock the entire CPU for one
373 ;; cycle. There is no way to avoid this lock and trying to
374 ;; schedule around the lock is pointless and thus there is no
375 ;; value in trying to model this lock.
377 ;; Not modeling the lock allows us to treat fp multiplies just
378 ;; like any other FP alu instruction. It allows for a smaller
379 ;; DFA and may reduce register pressure.
380 (define_insn_reservation "Y0" 2
381 (and (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
382 (eq_attr "cpu" "7100LC,7200,7300"))
383 "f_7100lc,fpmac_7100lc")
385 ;; fp division and sqrt instructions lock the entire CPU for
386 ;; 7 cycles (single precision) or 14 cycles (double precision).
387 ;; There is no way to avoid this lock and trying to schedule
388 ;; around the lock is pointless and thus there is no value in
389 ;; trying to model this lock. Not modeling the lock allows
390 ;; for a smaller DFA and may reduce register pressure.
391 (define_insn_reservation "Y1" 1
392 (and (eq_attr "type" "fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl")
393 (eq_attr "cpu" "7100LC,7200,7300"))
396 (define_insn_reservation "Y2" 2
397 (and (eq_attr "type" "load")
398 (eq_attr "cpu" "7100LC,7200,7300"))
399 "i1_7100lc+mem_7100lc")
401 (define_insn_reservation "Y3" 2
402 (and (eq_attr "type" "fpload")
403 (eq_attr "cpu" "7100LC,7200,7300"))
404 "i1_7100lc+mem_7100lc")
406 (define_insn_reservation "Y4" 2
407 (and (eq_attr "type" "store")
408 (eq_attr "cpu" "7100LC"))
409 "i1_7100lc+mem_7100lc,mem_7100lc")
411 (define_insn_reservation "Y5" 2
412 (and (eq_attr "type" "fpstore")
413 (eq_attr "cpu" "7100LC"))
414 "i1_7100lc+mem_7100lc,mem_7100lc")
416 (define_insn_reservation "Y6" 1
417 (and (eq_attr "type" "shift,nullshift")
418 (eq_attr "cpu" "7100LC,7200,7300"))
421 (define_insn_reservation "Y7" 1
422 (and (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
423 (eq_attr "cpu" "7100LC,7200,7300"))
424 "(i0_7100lc|i1_7100lc)")
426 ;; The 7200 has a store-load penalty
427 (define_insn_reservation "Y8" 2
428 (and (eq_attr "type" "store")
429 (eq_attr "cpu" "7200"))
430 "i1_7100lc,mem_7100lc")
432 (define_insn_reservation "Y9" 2
433 (and (eq_attr "type" "fpstore")
434 (eq_attr "cpu" "7200"))
435 "i1_7100lc,mem_7100lc")
437 ;; The 7300 has no penalty for store-store or store-load
438 (define_insn_reservation "Y10" 2
439 (and (eq_attr "type" "store")
440 (eq_attr "cpu" "7300"))
443 (define_insn_reservation "Y11" 2
444 (and (eq_attr "type" "fpstore")
445 (eq_attr "cpu" "7300"))
448 ;; We have an "anti-bypass" for FP loads which feed an FP store.
449 (define_bypass 3 "Y3" "Y5,Y9,Y11" "hppa_fpstore_bypass_p")
451 ;; Scheduling for the PA8000 is somewhat different than scheduling for a
452 ;; traditional architecture.
454 ;; The PA8000 has a large (56) entry reorder buffer that is split between
455 ;; memory and non-memory operations.
457 ;; The PA8000 can issue two memory and two non-memory operations per cycle to
458 ;; the function units, with the exception of branches and multi-output
459 ;; instructions. The PA8000 can retire two non-memory operations per cycle
460 ;; and two memory operations per cycle, only one of which may be a store.
462 ;; Given the large reorder buffer, the processor can hide most latencies.
463 ;; According to HP, they've got the best results by scheduling for retirement
464 ;; bandwidth with limited latency scheduling for floating point operations.
465 ;; Latency for integer operations and memory references is ignored.
468 ;; We claim floating point operations have a 2 cycle latency and are
469 ;; fully pipelined, except for div and sqrt which are not pipelined and
470 ;; take from 17 to 31 cycles to complete.
472 ;; It's worth noting that there is no way to saturate all the functional
473 ;; units on the PA8000 as there is not enough issue bandwidth.
475 (define_automaton "pa8000")
476 (define_cpu_unit "inm0_8000, inm1_8000, im0_8000, im1_8000" "pa8000")
477 (define_cpu_unit "rnm0_8000, rnm1_8000, rm0_8000, rm1_8000" "pa8000")
478 (define_cpu_unit "store_8000" "pa8000")
479 (define_cpu_unit "f0_8000, f1_8000" "pa8000")
480 (define_cpu_unit "fdivsqrt0_8000, fdivsqrt1_8000" "pa8000")
481 (define_reservation "inm_8000" "inm0_8000 | inm1_8000")
482 (define_reservation "im_8000" "im0_8000 | im1_8000")
483 (define_reservation "rnm_8000" "rnm0_8000 | rnm1_8000")
484 (define_reservation "rm_8000" "rm0_8000 | rm1_8000")
485 (define_reservation "f_8000" "f0_8000 | f1_8000")
486 (define_reservation "fdivsqrt_8000" "fdivsqrt0_8000 | fdivsqrt1_8000")
488 ;; We can issue any two memops per cycle, but we can only retire
489 ;; one memory store per cycle. We assume that the reorder buffer
490 ;; will hide any memory latencies per HP's recommendation.
491 (define_insn_reservation "Z0" 0
493 (eq_attr "type" "load,fpload")
494 (eq_attr "cpu" "8000"))
497 (define_insn_reservation "Z1" 0
499 (eq_attr "type" "store,fpstore")
500 (eq_attr "cpu" "8000"))
501 "im_8000,rm_8000+store_8000")
503 ;; We can issue and retire two non-memory operations per cycle with
504 ;; a few exceptions (branches). This group catches those we want
505 ;; to assume have zero latency.
506 (define_insn_reservation "Z2" 0
508 (eq_attr "type" "!load,fpload,store,fpstore,uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch,fpcc,fpalu,fpmulsgl,fpmuldbl,fpsqrtsgl,fpsqrtdbl,fpdivsgl,fpdivdbl")
509 (eq_attr "cpu" "8000"))
512 ;; Branches use both slots in the non-memory issue and
514 (define_insn_reservation "Z3" 0
516 (eq_attr "type" "uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,parallel_branch")
517 (eq_attr "cpu" "8000"))
518 "inm0_8000+inm1_8000,rnm0_8000+rnm1_8000")
520 ;; We partial latency schedule the floating point units.
521 ;; They can issue/retire two at a time in the non-memory
522 ;; units. We fix their latency at 2 cycles and they
523 ;; are fully pipelined.
524 (define_insn_reservation "Z4" 1
526 (eq_attr "type" "fpcc,fpalu,fpmulsgl,fpmuldbl")
527 (eq_attr "cpu" "8000"))
528 "inm_8000,f_8000,rnm_8000")
530 ;; The fdivsqrt units are not pipelined and have a very long latency.
531 ;; To keep the DFA from exploding, we do not show all the
532 ;; reservations for the divsqrt unit.
533 (define_insn_reservation "Z5" 17
535 (eq_attr "type" "fpdivsgl,fpsqrtsgl")
536 (eq_attr "cpu" "8000"))
537 "inm_8000,fdivsqrt_8000*6,rnm_8000")
539 (define_insn_reservation "Z6" 31
541 (eq_attr "type" "fpdivdbl,fpsqrtdbl")
542 (eq_attr "cpu" "8000"))
543 "inm_8000,fdivsqrt_8000*6,rnm_8000")
547 ;; Compare instructions.
548 ;; This controls RTL generation and register allocation.
550 ;; We generate RTL for comparisons and branches by having the cmpxx
551 ;; patterns store away the operands. Then, the scc and bcc patterns
552 ;; emit RTL for both the compare and the branch.
555 (define_expand "cmpdi"
557 (compare:CC (match_operand:DI 0 "reg_or_0_operand" "")
558 (match_operand:DI 1 "register_operand" "")))]
563 hppa_compare_op0 = operands[0];
564 hppa_compare_op1 = operands[1];
565 hppa_branch_type = CMP_SI;
569 (define_expand "cmpsi"
571 (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
572 (match_operand:SI 1 "arith5_operand" "")))]
576 hppa_compare_op0 = operands[0];
577 hppa_compare_op1 = operands[1];
578 hppa_branch_type = CMP_SI;
582 (define_expand "cmpsf"
584 (compare:CCFP (match_operand:SF 0 "reg_or_0_operand" "")
585 (match_operand:SF 1 "reg_or_0_operand" "")))]
586 "! TARGET_SOFT_FLOAT"
589 hppa_compare_op0 = operands[0];
590 hppa_compare_op1 = operands[1];
591 hppa_branch_type = CMP_SF;
595 (define_expand "cmpdf"
597 (compare:CCFP (match_operand:DF 0 "reg_or_0_operand" "")
598 (match_operand:DF 1 "reg_or_0_operand" "")))]
599 "! TARGET_SOFT_FLOAT"
602 hppa_compare_op0 = operands[0];
603 hppa_compare_op1 = operands[1];
604 hppa_branch_type = CMP_DF;
610 (match_operator:CCFP 2 "comparison_operator"
611 [(match_operand:SF 0 "reg_or_0_operand" "fG")
612 (match_operand:SF 1 "reg_or_0_operand" "fG")]))]
613 "! TARGET_SOFT_FLOAT"
614 "fcmp,sgl,%Y2 %f0,%f1"
615 [(set_attr "length" "4")
616 (set_attr "type" "fpcc")])
620 (match_operator:CCFP 2 "comparison_operator"
621 [(match_operand:DF 0 "reg_or_0_operand" "fG")
622 (match_operand:DF 1 "reg_or_0_operand" "fG")]))]
623 "! TARGET_SOFT_FLOAT"
624 "fcmp,dbl,%Y2 %f0,%f1"
625 [(set_attr "length" "4")
626 (set_attr "type" "fpcc")])
628 ;; Provide a means to emit the movccfp0 and movccfp1 optimization
629 ;; placeholders. This is necessary in rare situations when a
630 ;; placeholder is re-emitted (see PR 8705).
632 (define_expand "movccfp"
634 (match_operand 0 "const_int_operand" ""))]
635 "! TARGET_SOFT_FLOAT"
638 if ((unsigned HOST_WIDE_INT) INTVAL (operands[0]) > 1)
642 ;; The following patterns are optimization placeholders. In almost
643 ;; all cases, the user of the condition code will be simplified and the
644 ;; original condition code setting insn should be eliminated.
646 (define_insn "*movccfp0"
649 "! TARGET_SOFT_FLOAT"
650 "fcmp,dbl,= %%fr0,%%fr0"
651 [(set_attr "length" "4")
652 (set_attr "type" "fpcc")])
654 (define_insn "*movccfp1"
657 "! TARGET_SOFT_FLOAT"
658 "fcmp,dbl,!= %%fr0,%%fr0"
659 [(set_attr "length" "4")
660 (set_attr "type" "fpcc")])
665 [(set (match_operand:SI 0 "register_operand" "")
671 /* fp scc patterns rarely match, and are not a win on the PA. */
672 if (hppa_branch_type != CMP_SI)
674 /* set up operands from compare. */
675 operands[1] = hppa_compare_op0;
676 operands[2] = hppa_compare_op1;
677 /* fall through and generate default code */
681 [(set (match_operand:SI 0 "register_operand" "")
687 /* fp scc patterns rarely match, and are not a win on the PA. */
688 if (hppa_branch_type != CMP_SI)
690 operands[1] = hppa_compare_op0;
691 operands[2] = hppa_compare_op1;
695 [(set (match_operand:SI 0 "register_operand" "")
701 /* fp scc patterns rarely match, and are not a win on the PA. */
702 if (hppa_branch_type != CMP_SI)
704 operands[1] = hppa_compare_op0;
705 operands[2] = hppa_compare_op1;
709 [(set (match_operand:SI 0 "register_operand" "")
715 /* fp scc patterns rarely match, and are not a win on the PA. */
716 if (hppa_branch_type != CMP_SI)
718 operands[1] = hppa_compare_op0;
719 operands[2] = hppa_compare_op1;
723 [(set (match_operand:SI 0 "register_operand" "")
729 /* fp scc patterns rarely match, and are not a win on the PA. */
730 if (hppa_branch_type != CMP_SI)
732 operands[1] = hppa_compare_op0;
733 operands[2] = hppa_compare_op1;
737 [(set (match_operand:SI 0 "register_operand" "")
743 /* fp scc patterns rarely match, and are not a win on the PA. */
744 if (hppa_branch_type != CMP_SI)
746 operands[1] = hppa_compare_op0;
747 operands[2] = hppa_compare_op1;
750 (define_expand "sltu"
751 [(set (match_operand:SI 0 "register_operand" "")
752 (ltu:SI (match_dup 1)
757 if (hppa_branch_type != CMP_SI)
759 operands[1] = hppa_compare_op0;
760 operands[2] = hppa_compare_op1;
763 (define_expand "sgtu"
764 [(set (match_operand:SI 0 "register_operand" "")
765 (gtu:SI (match_dup 1)
770 if (hppa_branch_type != CMP_SI)
772 operands[1] = hppa_compare_op0;
773 operands[2] = hppa_compare_op1;
776 (define_expand "sleu"
777 [(set (match_operand:SI 0 "register_operand" "")
778 (leu:SI (match_dup 1)
783 if (hppa_branch_type != CMP_SI)
785 operands[1] = hppa_compare_op0;
786 operands[2] = hppa_compare_op1;
789 (define_expand "sgeu"
790 [(set (match_operand:SI 0 "register_operand" "")
791 (geu:SI (match_dup 1)
796 if (hppa_branch_type != CMP_SI)
798 operands[1] = hppa_compare_op0;
799 operands[2] = hppa_compare_op1;
802 ;; Instruction canonicalization puts immediate operands second, which
803 ;; is the reverse of what we want.
806 [(set (match_operand:SI 0 "register_operand" "=r")
807 (match_operator:SI 3 "comparison_operator"
808 [(match_operand:SI 1 "register_operand" "r")
809 (match_operand:SI 2 "arith11_operand" "rI")]))]
811 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi 1,%0"
812 [(set_attr "type" "binary")
813 (set_attr "length" "8")])
816 [(set (match_operand:DI 0 "register_operand" "=r")
817 (match_operator:DI 3 "comparison_operator"
818 [(match_operand:DI 1 "register_operand" "r")
819 (match_operand:DI 2 "arith11_operand" "rI")]))]
821 "cmp%I2clr,*%B3 %2,%1,%0\;ldi 1,%0"
822 [(set_attr "type" "binary")
823 (set_attr "length" "8")])
825 (define_insn "iorscc"
826 [(set (match_operand:SI 0 "register_operand" "=r")
827 (ior:SI (match_operator:SI 3 "comparison_operator"
828 [(match_operand:SI 1 "register_operand" "r")
829 (match_operand:SI 2 "arith11_operand" "rI")])
830 (match_operator:SI 6 "comparison_operator"
831 [(match_operand:SI 4 "register_operand" "r")
832 (match_operand:SI 5 "arith11_operand" "rI")])))]
834 "{com%I2clr|cmp%I2clr},%S3 %2,%1,%%r0\;{com%I5clr|cmp%I5clr},%B6 %5,%4,%0\;ldi 1,%0"
835 [(set_attr "type" "binary")
836 (set_attr "length" "12")])
839 [(set (match_operand:DI 0 "register_operand" "=r")
840 (ior:DI (match_operator:DI 3 "comparison_operator"
841 [(match_operand:DI 1 "register_operand" "r")
842 (match_operand:DI 2 "arith11_operand" "rI")])
843 (match_operator:DI 6 "comparison_operator"
844 [(match_operand:DI 4 "register_operand" "r")
845 (match_operand:DI 5 "arith11_operand" "rI")])))]
847 "cmp%I2clr,*%S3 %2,%1,%%r0\;cmp%I5clr,*%B6 %5,%4,%0\;ldi 1,%0"
848 [(set_attr "type" "binary")
849 (set_attr "length" "12")])
851 ;; Combiner patterns for common operations performed with the output
852 ;; from an scc insn (negscc and incscc).
853 (define_insn "negscc"
854 [(set (match_operand:SI 0 "register_operand" "=r")
855 (neg:SI (match_operator:SI 3 "comparison_operator"
856 [(match_operand:SI 1 "register_operand" "r")
857 (match_operand:SI 2 "arith11_operand" "rI")])))]
859 "{com%I2clr|cmp%I2clr},%B3 %2,%1,%0\;ldi -1,%0"
860 [(set_attr "type" "binary")
861 (set_attr "length" "8")])
864 [(set (match_operand:DI 0 "register_operand" "=r")
865 (neg:DI (match_operator:DI 3 "comparison_operator"
866 [(match_operand:DI 1 "register_operand" "r")
867 (match_operand:DI 2 "arith11_operand" "rI")])))]
869 "cmp%I2clr,*%B3 %2,%1,%0\;ldi -1,%0"
870 [(set_attr "type" "binary")
871 (set_attr "length" "8")])
873 ;; Patterns for adding/subtracting the result of a boolean expression from
874 ;; a register. First we have special patterns that make use of the carry
875 ;; bit, and output only two instructions. For the cases we can't in
876 ;; general do in two instructions, the incscc pattern at the end outputs
877 ;; two or three instructions.
880 [(set (match_operand:SI 0 "register_operand" "=r")
881 (plus:SI (leu:SI (match_operand:SI 2 "register_operand" "r")
882 (match_operand:SI 3 "arith11_operand" "rI"))
883 (match_operand:SI 1 "register_operand" "r")))]
885 "sub%I3 %3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
886 [(set_attr "type" "binary")
887 (set_attr "length" "8")])
890 [(set (match_operand:DI 0 "register_operand" "=r")
891 (plus:DI (leu:DI (match_operand:DI 2 "register_operand" "r")
892 (match_operand:DI 3 "arith11_operand" "rI"))
893 (match_operand:DI 1 "register_operand" "r")))]
895 "sub%I3 %3,%2,%%r0\;add,dc %%r0,%1,%0"
896 [(set_attr "type" "binary")
897 (set_attr "length" "8")])
899 ; This need only accept registers for op3, since canonicalization
900 ; replaces geu with gtu when op3 is an integer.
902 [(set (match_operand:SI 0 "register_operand" "=r")
903 (plus:SI (geu:SI (match_operand:SI 2 "register_operand" "r")
904 (match_operand:SI 3 "register_operand" "r"))
905 (match_operand:SI 1 "register_operand" "r")))]
907 "sub %2,%3,%%r0\;{addc|add,c} %%r0,%1,%0"
908 [(set_attr "type" "binary")
909 (set_attr "length" "8")])
912 [(set (match_operand:DI 0 "register_operand" "=r")
913 (plus:DI (geu:DI (match_operand:DI 2 "register_operand" "r")
914 (match_operand:DI 3 "register_operand" "r"))
915 (match_operand:DI 1 "register_operand" "r")))]
917 "sub %2,%3,%%r0\;add,dc %%r0,%1,%0"
918 [(set_attr "type" "binary")
919 (set_attr "length" "8")])
921 ; Match only integers for op3 here. This is used as canonical form of the
922 ; geu pattern when op3 is an integer. Don't match registers since we can't
923 ; make better code than the general incscc pattern.
925 [(set (match_operand:SI 0 "register_operand" "=r")
926 (plus:SI (gtu:SI (match_operand:SI 2 "register_operand" "r")
927 (match_operand:SI 3 "int11_operand" "I"))
928 (match_operand:SI 1 "register_operand" "r")))]
930 "addi %k3,%2,%%r0\;{addc|add,c} %%r0,%1,%0"
931 [(set_attr "type" "binary")
932 (set_attr "length" "8")])
935 [(set (match_operand:DI 0 "register_operand" "=r")
936 (plus:DI (gtu:DI (match_operand:DI 2 "register_operand" "r")
937 (match_operand:DI 3 "int11_operand" "I"))
938 (match_operand:DI 1 "register_operand" "r")))]
940 "addi %k3,%2,%%r0\;add,dc %%r0,%1,%0"
941 [(set_attr "type" "binary")
942 (set_attr "length" "8")])
944 (define_insn "incscc"
945 [(set (match_operand:SI 0 "register_operand" "=r,r")
946 (plus:SI (match_operator:SI 4 "comparison_operator"
947 [(match_operand:SI 2 "register_operand" "r,r")
948 (match_operand:SI 3 "arith11_operand" "rI,rI")])
949 (match_operand:SI 1 "register_operand" "0,?r")))]
952 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi 1,%0,%0
953 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
954 [(set_attr "type" "binary,binary")
955 (set_attr "length" "8,12")])
958 [(set (match_operand:DI 0 "register_operand" "=r,r")
959 (plus:DI (match_operator:DI 4 "comparison_operator"
960 [(match_operand:DI 2 "register_operand" "r,r")
961 (match_operand:DI 3 "arith11_operand" "rI,rI")])
962 (match_operand:DI 1 "register_operand" "0,?r")))]
965 cmp%I3clr,*%B4 %3,%2,%%r0\;addi 1,%0,%0
966 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr 1,%1,%0\;copy %1,%0"
967 [(set_attr "type" "binary,binary")
968 (set_attr "length" "8,12")])
971 [(set (match_operand:SI 0 "register_operand" "=r")
972 (minus:SI (match_operand:SI 1 "register_operand" "r")
973 (gtu:SI (match_operand:SI 2 "register_operand" "r")
974 (match_operand:SI 3 "arith11_operand" "rI"))))]
976 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
977 [(set_attr "type" "binary")
978 (set_attr "length" "8")])
981 [(set (match_operand:DI 0 "register_operand" "=r")
982 (minus:DI (match_operand:DI 1 "register_operand" "r")
983 (gtu:DI (match_operand:DI 2 "register_operand" "r")
984 (match_operand:DI 3 "arith11_operand" "rI"))))]
986 "sub%I3 %3,%2,%%r0\;sub,db %1,%%r0,%0"
987 [(set_attr "type" "binary")
988 (set_attr "length" "8")])
991 [(set (match_operand:SI 0 "register_operand" "=r")
992 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
993 (gtu:SI (match_operand:SI 2 "register_operand" "r")
994 (match_operand:SI 3 "arith11_operand" "rI")))
995 (match_operand:SI 4 "register_operand" "r")))]
997 "sub%I3 %3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
998 [(set_attr "type" "binary")
999 (set_attr "length" "8")])
1002 [(set (match_operand:DI 0 "register_operand" "=r")
1003 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1004 (gtu:DI (match_operand:DI 2 "register_operand" "r")
1005 (match_operand:DI 3 "arith11_operand" "rI")))
1006 (match_operand:DI 4 "register_operand" "r")))]
1008 "sub%I3 %3,%2,%%r0\;sub,db %1,%4,%0"
1009 [(set_attr "type" "binary")
1010 (set_attr "length" "8")])
1012 ; This need only accept registers for op3, since canonicalization
1013 ; replaces ltu with leu when op3 is an integer.
1015 [(set (match_operand:SI 0 "register_operand" "=r")
1016 (minus:SI (match_operand:SI 1 "register_operand" "r")
1017 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1018 (match_operand:SI 3 "register_operand" "r"))))]
1020 "sub %2,%3,%%r0\;{subb|sub,b} %1,%%r0,%0"
1021 [(set_attr "type" "binary")
1022 (set_attr "length" "8")])
1025 [(set (match_operand:DI 0 "register_operand" "=r")
1026 (minus:DI (match_operand:DI 1 "register_operand" "r")
1027 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1028 (match_operand:DI 3 "register_operand" "r"))))]
1030 "sub %2,%3,%%r0\;sub,db %1,%%r0,%0"
1031 [(set_attr "type" "binary")
1032 (set_attr "length" "8")])
1035 [(set (match_operand:SI 0 "register_operand" "=r")
1036 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1037 (ltu:SI (match_operand:SI 2 "register_operand" "r")
1038 (match_operand:SI 3 "register_operand" "r")))
1039 (match_operand:SI 4 "register_operand" "r")))]
1041 "sub %2,%3,%%r0\;{subb|sub,b} %1,%4,%0"
1042 [(set_attr "type" "binary")
1043 (set_attr "length" "8")])
1046 [(set (match_operand:DI 0 "register_operand" "=r")
1047 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1048 (ltu:DI (match_operand:DI 2 "register_operand" "r")
1049 (match_operand:DI 3 "register_operand" "r")))
1050 (match_operand:DI 4 "register_operand" "r")))]
1052 "sub %2,%3,%%r0\;sub,db %1,%4,%0"
1053 [(set_attr "type" "binary")
1054 (set_attr "length" "8")])
1056 ; Match only integers for op3 here. This is used as canonical form of the
1057 ; ltu pattern when op3 is an integer. Don't match registers since we can't
1058 ; make better code than the general incscc pattern.
1060 [(set (match_operand:SI 0 "register_operand" "=r")
1061 (minus:SI (match_operand:SI 1 "register_operand" "r")
1062 (leu:SI (match_operand:SI 2 "register_operand" "r")
1063 (match_operand:SI 3 "int11_operand" "I"))))]
1065 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%%r0,%0"
1066 [(set_attr "type" "binary")
1067 (set_attr "length" "8")])
1070 [(set (match_operand:DI 0 "register_operand" "=r")
1071 (minus:DI (match_operand:DI 1 "register_operand" "r")
1072 (leu:DI (match_operand:DI 2 "register_operand" "r")
1073 (match_operand:DI 3 "int11_operand" "I"))))]
1075 "addi %k3,%2,%%r0\;sub,db %1,%%r0,%0"
1076 [(set_attr "type" "binary")
1077 (set_attr "length" "8")])
1080 [(set (match_operand:SI 0 "register_operand" "=r")
1081 (minus:SI (minus:SI (match_operand:SI 1 "register_operand" "r")
1082 (leu:SI (match_operand:SI 2 "register_operand" "r")
1083 (match_operand:SI 3 "int11_operand" "I")))
1084 (match_operand:SI 4 "register_operand" "r")))]
1086 "addi %k3,%2,%%r0\;{subb|sub,b} %1,%4,%0"
1087 [(set_attr "type" "binary")
1088 (set_attr "length" "8")])
1091 [(set (match_operand:DI 0 "register_operand" "=r")
1092 (minus:DI (minus:DI (match_operand:DI 1 "register_operand" "r")
1093 (leu:DI (match_operand:DI 2 "register_operand" "r")
1094 (match_operand:DI 3 "int11_operand" "I")))
1095 (match_operand:DI 4 "register_operand" "r")))]
1097 "addi %k3,%2,%%r0\;sub,db %1,%4,%0"
1098 [(set_attr "type" "binary")
1099 (set_attr "length" "8")])
1101 (define_insn "decscc"
1102 [(set (match_operand:SI 0 "register_operand" "=r,r")
1103 (minus:SI (match_operand:SI 1 "register_operand" "0,?r")
1104 (match_operator:SI 4 "comparison_operator"
1105 [(match_operand:SI 2 "register_operand" "r,r")
1106 (match_operand:SI 3 "arith11_operand" "rI,rI")])))]
1109 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi -1,%0,%0
1110 {com%I3clr|cmp%I3clr},%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1111 [(set_attr "type" "binary,binary")
1112 (set_attr "length" "8,12")])
1115 [(set (match_operand:DI 0 "register_operand" "=r,r")
1116 (minus:DI (match_operand:DI 1 "register_operand" "0,?r")
1117 (match_operator:DI 4 "comparison_operator"
1118 [(match_operand:DI 2 "register_operand" "r,r")
1119 (match_operand:DI 3 "arith11_operand" "rI,rI")])))]
1122 cmp%I3clr,*%B4 %3,%2,%%r0\;addi -1,%0,%0
1123 cmp%I3clr,*%B4 %3,%2,%%r0\;addi,tr -1,%1,%0\;copy %1,%0"
1124 [(set_attr "type" "binary,binary")
1125 (set_attr "length" "8,12")])
1127 ; Patterns for max and min. (There is no need for an earlyclobber in the
1128 ; last alternative since the middle alternative will match if op0 == op1.)
1130 (define_insn "sminsi3"
1131 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1132 (smin:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1133 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1136 {comclr|cmpclr},> %2,%0,%%r0\;copy %2,%0
1137 {comiclr|cmpiclr},> %2,%0,%%r0\;ldi %2,%0
1138 {comclr|cmpclr},> %1,%r2,%0\;copy %1,%0"
1139 [(set_attr "type" "multi,multi,multi")
1140 (set_attr "length" "8,8,8")])
1142 (define_insn "smindi3"
1143 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1144 (smin:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1145 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1148 cmpclr,*> %2,%0,%%r0\;copy %2,%0
1149 cmpiclr,*> %2,%0,%%r0\;ldi %2,%0
1150 cmpclr,*> %1,%r2,%0\;copy %1,%0"
1151 [(set_attr "type" "multi,multi,multi")
1152 (set_attr "length" "8,8,8")])
1154 (define_insn "uminsi3"
1155 [(set (match_operand:SI 0 "register_operand" "=r,r")
1156 (umin:SI (match_operand:SI 1 "register_operand" "%0,0")
1157 (match_operand:SI 2 "arith11_operand" "r,I")))]
1160 {comclr|cmpclr},>> %2,%0,%%r0\;copy %2,%0
1161 {comiclr|cmpiclr},>> %2,%0,%%r0\;ldi %2,%0"
1162 [(set_attr "type" "multi,multi")
1163 (set_attr "length" "8,8")])
1165 (define_insn "umindi3"
1166 [(set (match_operand:DI 0 "register_operand" "=r,r")
1167 (umin:DI (match_operand:DI 1 "register_operand" "%0,0")
1168 (match_operand:DI 2 "arith11_operand" "r,I")))]
1171 cmpclr,*>> %2,%0,%%r0\;copy %2,%0
1172 cmpiclr,*>> %2,%0,%%r0\;ldi %2,%0"
1173 [(set_attr "type" "multi,multi")
1174 (set_attr "length" "8,8")])
1176 (define_insn "smaxsi3"
1177 [(set (match_operand:SI 0 "register_operand" "=r,r,r")
1178 (smax:SI (match_operand:SI 1 "register_operand" "%0,0,r")
1179 (match_operand:SI 2 "arith11_operand" "r,I,M")))]
1182 {comclr|cmpclr},< %2,%0,%%r0\;copy %2,%0
1183 {comiclr|cmpiclr},< %2,%0,%%r0\;ldi %2,%0
1184 {comclr|cmpclr},< %1,%r2,%0\;copy %1,%0"
1185 [(set_attr "type" "multi,multi,multi")
1186 (set_attr "length" "8,8,8")])
1188 (define_insn "smaxdi3"
1189 [(set (match_operand:DI 0 "register_operand" "=r,r,r")
1190 (smax:DI (match_operand:DI 1 "register_operand" "%0,0,r")
1191 (match_operand:DI 2 "arith11_operand" "r,I,M")))]
1194 cmpclr,*< %2,%0,%%r0\;copy %2,%0
1195 cmpiclr,*< %2,%0,%%r0\;ldi %2,%0
1196 cmpclr,*< %1,%r2,%0\;copy %1,%0"
1197 [(set_attr "type" "multi,multi,multi")
1198 (set_attr "length" "8,8,8")])
1200 (define_insn "umaxsi3"
1201 [(set (match_operand:SI 0 "register_operand" "=r,r")
1202 (umax:SI (match_operand:SI 1 "register_operand" "%0,0")
1203 (match_operand:SI 2 "arith11_operand" "r,I")))]
1206 {comclr|cmpclr},<< %2,%0,%%r0\;copy %2,%0
1207 {comiclr|cmpiclr},<< %2,%0,%%r0\;ldi %2,%0"
1208 [(set_attr "type" "multi,multi")
1209 (set_attr "length" "8,8")])
1211 (define_insn "umaxdi3"
1212 [(set (match_operand:DI 0 "register_operand" "=r,r")
1213 (umax:DI (match_operand:DI 1 "register_operand" "%0,0")
1214 (match_operand:DI 2 "arith11_operand" "r,I")))]
1217 cmpclr,*<< %2,%0,%%r0\;copy %2,%0
1218 cmpiclr,*<< %2,%0,%%r0\;ldi %2,%0"
1219 [(set_attr "type" "multi,multi")
1220 (set_attr "length" "8,8")])
1222 (define_insn "abssi2"
1223 [(set (match_operand:SI 0 "register_operand" "=r")
1224 (abs:SI (match_operand:SI 1 "register_operand" "r")))]
1226 "or,>= %%r0,%1,%0\;subi 0,%0,%0"
1227 [(set_attr "type" "multi")
1228 (set_attr "length" "8")])
1230 (define_insn "absdi2"
1231 [(set (match_operand:DI 0 "register_operand" "=r")
1232 (abs:DI (match_operand:DI 1 "register_operand" "r")))]
1234 "or,*>= %%r0,%1,%0\;subi 0,%0,%0"
1235 [(set_attr "type" "multi")
1236 (set_attr "length" "8")])
1238 ;;; Experimental conditional move patterns
1240 (define_expand "movsicc"
1241 [(set (match_operand:SI 0 "register_operand" "")
1243 (match_operator 1 "comparison_operator"
1246 (match_operand:SI 2 "reg_or_cint_move_operand" "")
1247 (match_operand:SI 3 "reg_or_cint_move_operand" "")))]
1251 enum rtx_code code = GET_CODE (operands[1]);
1253 if (hppa_branch_type != CMP_SI)
1256 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1257 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1260 /* operands[1] is currently the result of compare_from_rtx. We want to
1261 emit a compare of the original operands. */
1262 operands[1] = gen_rtx_fmt_ee (code, SImode, hppa_compare_op0, hppa_compare_op1);
1263 operands[4] = hppa_compare_op0;
1264 operands[5] = hppa_compare_op1;
1267 ;; We used to accept any register for op1.
1269 ;; However, it loses sometimes because the compiler will end up using
1270 ;; different registers for op0 and op1 in some critical cases. local-alloc
1271 ;; will not tie op0 and op1 because op0 is used in multiple basic blocks.
1273 ;; If/when global register allocation supports tying we should allow any
1274 ;; register for op1 again.
1276 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
1278 (match_operator 2 "comparison_operator"
1279 [(match_operand:SI 3 "register_operand" "r,r,r,r")
1280 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI")])
1281 (match_operand:SI 1 "reg_or_cint_move_operand" "0,J,N,K")
1285 {com%I4clr|cmp%I4clr},%S2 %4,%3,%%r0\;ldi 0,%0
1286 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldi %1,%0
1287 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;ldil L'%1,%0
1288 {com%I4clr|cmp%I4clr},%B2 %4,%3,%0\;{zdepi|depwi,z} %Z1,%0"
1289 [(set_attr "type" "multi,multi,multi,nullshift")
1290 (set_attr "length" "8,8,8,8")])
1293 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1295 (match_operator 5 "comparison_operator"
1296 [(match_operand:SI 3 "register_operand" "r,r,r,r,r,r,r,r")
1297 (match_operand:SI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1298 (match_operand:SI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1299 (match_operand:SI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1302 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;copy %2,%0
1303 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldi %2,%0
1304 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;ldil L'%2,%0
1305 {com%I4clr|cmp%I4clr},%S5 %4,%3,%%r0\;{zdepi|depwi,z} %Z2,%0
1306 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;copy %1,%0
1307 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldi %1,%0
1308 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;ldil L'%1,%0
1309 {com%I4clr|cmp%I4clr},%B5 %4,%3,%%r0\;{zdepi|depwi,z} %Z1,%0"
1310 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1311 (set_attr "length" "8,8,8,8,8,8,8,8")])
1313 (define_expand "movdicc"
1314 [(set (match_operand:DI 0 "register_operand" "")
1316 (match_operator 1 "comparison_operator"
1319 (match_operand:DI 2 "reg_or_cint_move_operand" "")
1320 (match_operand:DI 3 "reg_or_cint_move_operand" "")))]
1324 enum rtx_code code = GET_CODE (operands[1]);
1326 if (hppa_branch_type != CMP_SI)
1329 if (GET_MODE (hppa_compare_op0) != GET_MODE (hppa_compare_op1)
1330 || GET_MODE (hppa_compare_op0) != GET_MODE (operands[0]))
1333 /* operands[1] is currently the result of compare_from_rtx. We want to
1334 emit a compare of the original operands. */
1335 operands[1] = gen_rtx_fmt_ee (code, DImode, hppa_compare_op0, hppa_compare_op1);
1336 operands[4] = hppa_compare_op0;
1337 operands[5] = hppa_compare_op1;
1340 ; We need the first constraint alternative in order to avoid
1341 ; earlyclobbers on all other alternatives.
1343 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r")
1345 (match_operator 2 "comparison_operator"
1346 [(match_operand:DI 3 "register_operand" "r,r,r,r,r")
1347 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI")])
1348 (match_operand:DI 1 "reg_or_cint_move_operand" "0,r,J,N,K")
1352 cmp%I4clr,*%S2 %4,%3,%%r0\;ldi 0,%0
1353 cmp%I4clr,*%B2 %4,%3,%0\;copy %1,%0
1354 cmp%I4clr,*%B2 %4,%3,%0\;ldi %1,%0
1355 cmp%I4clr,*%B2 %4,%3,%0\;ldil L'%1,%0
1356 cmp%I4clr,*%B2 %4,%3,%0\;depdi,z %z1,%0"
1357 [(set_attr "type" "multi,multi,multi,multi,nullshift")
1358 (set_attr "length" "8,8,8,8,8")])
1361 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r,r,r,r,r")
1363 (match_operator 5 "comparison_operator"
1364 [(match_operand:DI 3 "register_operand" "r,r,r,r,r,r,r,r")
1365 (match_operand:DI 4 "arith11_operand" "rI,rI,rI,rI,rI,rI,rI,rI")])
1366 (match_operand:DI 1 "reg_or_cint_move_operand" "0,0,0,0,r,J,N,K")
1367 (match_operand:DI 2 "reg_or_cint_move_operand" "r,J,N,K,0,0,0,0")))]
1370 cmp%I4clr,*%S5 %4,%3,%%r0\;copy %2,%0
1371 cmp%I4clr,*%S5 %4,%3,%%r0\;ldi %2,%0
1372 cmp%I4clr,*%S5 %4,%3,%%r0\;ldil L'%2,%0
1373 cmp%I4clr,*%S5 %4,%3,%%r0\;depdi,z %z2,%0
1374 cmp%I4clr,*%B5 %4,%3,%%r0\;copy %1,%0
1375 cmp%I4clr,*%B5 %4,%3,%%r0\;ldi %1,%0
1376 cmp%I4clr,*%B5 %4,%3,%%r0\;ldil L'%1,%0
1377 cmp%I4clr,*%B5 %4,%3,%%r0\;depdi,z %z1,%0"
1378 [(set_attr "type" "multi,multi,multi,nullshift,multi,multi,multi,nullshift")
1379 (set_attr "length" "8,8,8,8,8,8,8,8")])
1381 ;; Conditional Branches
1383 (define_expand "beq"
1385 (if_then_else (eq (match_dup 1) (match_dup 2))
1386 (label_ref (match_operand 0 "" ""))
1391 if (hppa_branch_type != CMP_SI)
1393 emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
1394 emit_bcond_fp (NE, operands[0]);
1397 /* set up operands from compare. */
1398 operands[1] = hppa_compare_op0;
1399 operands[2] = hppa_compare_op1;
1400 /* fall through and generate default code */
1403 (define_expand "bne"
1405 (if_then_else (ne (match_dup 1) (match_dup 2))
1406 (label_ref (match_operand 0 "" ""))
1411 if (hppa_branch_type != CMP_SI)
1413 emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
1414 emit_bcond_fp (NE, operands[0]);
1417 operands[1] = hppa_compare_op0;
1418 operands[2] = hppa_compare_op1;
1421 (define_expand "bgt"
1423 (if_then_else (gt (match_dup 1) (match_dup 2))
1424 (label_ref (match_operand 0 "" ""))
1429 if (hppa_branch_type != CMP_SI)
1431 emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
1432 emit_bcond_fp (NE, operands[0]);
1435 operands[1] = hppa_compare_op0;
1436 operands[2] = hppa_compare_op1;
1439 (define_expand "blt"
1441 (if_then_else (lt (match_dup 1) (match_dup 2))
1442 (label_ref (match_operand 0 "" ""))
1447 if (hppa_branch_type != CMP_SI)
1449 emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
1450 emit_bcond_fp (NE, operands[0]);
1453 operands[1] = hppa_compare_op0;
1454 operands[2] = hppa_compare_op1;
1457 (define_expand "bge"
1459 (if_then_else (ge (match_dup 1) (match_dup 2))
1460 (label_ref (match_operand 0 "" ""))
1465 if (hppa_branch_type != CMP_SI)
1467 emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
1468 emit_bcond_fp (NE, operands[0]);
1471 operands[1] = hppa_compare_op0;
1472 operands[2] = hppa_compare_op1;
1475 (define_expand "ble"
1477 (if_then_else (le (match_dup 1) (match_dup 2))
1478 (label_ref (match_operand 0 "" ""))
1483 if (hppa_branch_type != CMP_SI)
1485 emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
1486 emit_bcond_fp (NE, operands[0]);
1489 operands[1] = hppa_compare_op0;
1490 operands[2] = hppa_compare_op1;
1493 (define_expand "bgtu"
1495 (if_then_else (gtu (match_dup 1) (match_dup 2))
1496 (label_ref (match_operand 0 "" ""))
1501 if (hppa_branch_type != CMP_SI)
1503 operands[1] = hppa_compare_op0;
1504 operands[2] = hppa_compare_op1;
1507 (define_expand "bltu"
1509 (if_then_else (ltu (match_dup 1) (match_dup 2))
1510 (label_ref (match_operand 0 "" ""))
1515 if (hppa_branch_type != CMP_SI)
1517 operands[1] = hppa_compare_op0;
1518 operands[2] = hppa_compare_op1;
1521 (define_expand "bgeu"
1523 (if_then_else (geu (match_dup 1) (match_dup 2))
1524 (label_ref (match_operand 0 "" ""))
1529 if (hppa_branch_type != CMP_SI)
1531 operands[1] = hppa_compare_op0;
1532 operands[2] = hppa_compare_op1;
1535 (define_expand "bleu"
1537 (if_then_else (leu (match_dup 1) (match_dup 2))
1538 (label_ref (match_operand 0 "" ""))
1543 if (hppa_branch_type != CMP_SI)
1545 operands[1] = hppa_compare_op0;
1546 operands[2] = hppa_compare_op1;
1549 (define_expand "bltgt"
1551 (if_then_else (ltgt (match_dup 1) (match_dup 2))
1552 (label_ref (match_operand 0 "" ""))
1557 if (hppa_branch_type == CMP_SI)
1559 emit_insn (gen_cmp_fp (LTGT, hppa_compare_op0, hppa_compare_op1));
1560 emit_bcond_fp (NE, operands[0]);
1564 (define_expand "bunle"
1566 (if_then_else (unle (match_dup 1) (match_dup 2))
1567 (label_ref (match_operand 0 "" ""))
1572 if (hppa_branch_type == CMP_SI)
1574 emit_insn (gen_cmp_fp (UNLE, hppa_compare_op0, hppa_compare_op1));
1575 emit_bcond_fp (NE, operands[0]);
1579 (define_expand "bunlt"
1581 (if_then_else (unlt (match_dup 1) (match_dup 2))
1582 (label_ref (match_operand 0 "" ""))
1587 if (hppa_branch_type == CMP_SI)
1589 emit_insn (gen_cmp_fp (UNLT, hppa_compare_op0, hppa_compare_op1));
1590 emit_bcond_fp (NE, operands[0]);
1594 (define_expand "bunge"
1596 (if_then_else (unge (match_dup 1) (match_dup 2))
1597 (label_ref (match_operand 0 "" ""))
1602 if (hppa_branch_type == CMP_SI)
1604 emit_insn (gen_cmp_fp (UNGE, hppa_compare_op0, hppa_compare_op1));
1605 emit_bcond_fp (NE, operands[0]);
1609 (define_expand "bungt"
1611 (if_then_else (ungt (match_dup 1) (match_dup 2))
1612 (label_ref (match_operand 0 "" ""))
1617 if (hppa_branch_type == CMP_SI)
1619 emit_insn (gen_cmp_fp (UNGT, hppa_compare_op0, hppa_compare_op1));
1620 emit_bcond_fp (NE, operands[0]);
1624 (define_expand "buneq"
1626 (if_then_else (uneq (match_dup 1) (match_dup 2))
1627 (label_ref (match_operand 0 "" ""))
1632 if (hppa_branch_type == CMP_SI)
1634 emit_insn (gen_cmp_fp (UNEQ, hppa_compare_op0, hppa_compare_op1));
1635 emit_bcond_fp (NE, operands[0]);
1639 (define_expand "bunordered"
1641 (if_then_else (unordered (match_dup 1) (match_dup 2))
1642 (label_ref (match_operand 0 "" ""))
1647 if (hppa_branch_type == CMP_SI)
1649 emit_insn (gen_cmp_fp (UNORDERED, hppa_compare_op0, hppa_compare_op1));
1650 emit_bcond_fp (NE, operands[0]);
1654 (define_expand "bordered"
1656 (if_then_else (ordered (match_dup 1) (match_dup 2))
1657 (label_ref (match_operand 0 "" ""))
1662 if (hppa_branch_type == CMP_SI)
1664 emit_insn (gen_cmp_fp (ORDERED, hppa_compare_op0, hppa_compare_op1));
1665 emit_bcond_fp (NE, operands[0]);
1669 ;; Match the branch patterns.
1672 ;; Note a long backward conditional branch with an annulled delay slot
1673 ;; has a length of 12.
1677 (match_operator 3 "comparison_operator"
1678 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1679 (match_operand:SI 2 "arith5_operand" "rL")])
1680 (label_ref (match_operand 0 "" ""))
1685 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1686 get_attr_length (insn), 0, insn);
1688 [(set_attr "type" "cbranch")
1689 (set (attr "length")
1690 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1693 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1696 (eq (symbol_ref "flag_pic") (const_int 0))
1700 ;; Match the negated branch.
1705 (match_operator 3 "comparison_operator"
1706 [(match_operand:SI 1 "reg_or_0_operand" "rM")
1707 (match_operand:SI 2 "arith5_operand" "rL")])
1709 (label_ref (match_operand 0 "" ""))))]
1713 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1714 get_attr_length (insn), 1, insn);
1716 [(set_attr "type" "cbranch")
1717 (set (attr "length")
1718 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1721 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1724 (eq (symbol_ref "flag_pic") (const_int 0))
1731 (match_operator 3 "comparison_operator"
1732 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1733 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1734 (label_ref (match_operand 0 "" ""))
1739 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1740 get_attr_length (insn), 0, insn);
1742 [(set_attr "type" "cbranch")
1743 (set (attr "length")
1744 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1747 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1750 (eq (symbol_ref "flag_pic") (const_int 0))
1754 ;; Match the negated branch.
1759 (match_operator 3 "comparison_operator"
1760 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1761 (match_operand:DI 2 "reg_or_0_operand" "rM")])
1763 (label_ref (match_operand 0 "" ""))))]
1767 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1768 get_attr_length (insn), 1, insn);
1770 [(set_attr "type" "cbranch")
1771 (set (attr "length")
1772 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1775 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1778 (eq (symbol_ref "flag_pic") (const_int 0))
1784 (match_operator 3 "cmpib_comparison_operator"
1785 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1786 (match_operand:DI 2 "arith5_operand" "rL")])
1787 (label_ref (match_operand 0 "" ""))
1792 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1793 get_attr_length (insn), 0, insn);
1795 [(set_attr "type" "cbranch")
1796 (set (attr "length")
1797 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1800 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1803 (eq (symbol_ref "flag_pic") (const_int 0))
1807 ;; Match the negated branch.
1812 (match_operator 3 "cmpib_comparison_operator"
1813 [(match_operand:DI 1 "reg_or_0_operand" "rM")
1814 (match_operand:DI 2 "arith5_operand" "rL")])
1816 (label_ref (match_operand 0 "" ""))))]
1820 return output_cbranch (operands, INSN_ANNULLED_BRANCH_P (insn),
1821 get_attr_length (insn), 1, insn);
1823 [(set_attr "type" "cbranch")
1824 (set (attr "length")
1825 (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1828 (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
1831 (eq (symbol_ref "flag_pic") (const_int 0))
1835 ;; Branch on Bit patterns.
1839 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1841 (match_operand:SI 1 "uint5_operand" ""))
1843 (label_ref (match_operand 2 "" ""))
1848 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1849 get_attr_length (insn), 0, insn, 0);
1851 [(set_attr "type" "cbranch")
1852 (set (attr "length")
1853 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1861 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1863 (match_operand:DI 1 "uint32_operand" ""))
1865 (label_ref (match_operand 2 "" ""))
1870 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1871 get_attr_length (insn), 0, insn, 0);
1873 [(set_attr "type" "cbranch")
1874 (set (attr "length")
1875 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1883 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1885 (match_operand:SI 1 "uint5_operand" ""))
1888 (label_ref (match_operand 2 "" ""))))]
1892 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1893 get_attr_length (insn), 1, insn, 0);
1895 [(set_attr "type" "cbranch")
1896 (set (attr "length")
1897 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1905 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1907 (match_operand:DI 1 "uint32_operand" ""))
1910 (label_ref (match_operand 2 "" ""))))]
1914 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1915 get_attr_length (insn), 1, insn, 0);
1917 [(set_attr "type" "cbranch")
1918 (set (attr "length")
1919 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1927 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1929 (match_operand:SI 1 "uint5_operand" ""))
1931 (label_ref (match_operand 2 "" ""))
1936 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1937 get_attr_length (insn), 0, insn, 1);
1939 [(set_attr "type" "cbranch")
1940 (set (attr "length")
1941 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1949 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1951 (match_operand:DI 1 "uint32_operand" ""))
1953 (label_ref (match_operand 2 "" ""))
1958 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1959 get_attr_length (insn), 0, insn, 1);
1961 [(set_attr "type" "cbranch")
1962 (set (attr "length")
1963 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1971 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
1973 (match_operand:SI 1 "uint5_operand" ""))
1976 (label_ref (match_operand 2 "" ""))))]
1980 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
1981 get_attr_length (insn), 1, insn, 1);
1983 [(set_attr "type" "cbranch")
1984 (set (attr "length")
1985 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
1993 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
1995 (match_operand:DI 1 "uint32_operand" ""))
1998 (label_ref (match_operand 2 "" ""))))]
2002 return output_bb (operands, INSN_ANNULLED_BRANCH_P (insn),
2003 get_attr_length (insn), 1, insn, 1);
2005 [(set_attr "type" "cbranch")
2006 (set (attr "length")
2007 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2012 ;; Branch on Variable Bit patterns.
2016 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2018 (match_operand:SI 1 "register_operand" "q"))
2020 (label_ref (match_operand 2 "" ""))
2025 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2026 get_attr_length (insn), 0, insn, 0);
2028 [(set_attr "type" "cbranch")
2029 (set (attr "length")
2030 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2038 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2040 (match_operand:DI 1 "register_operand" "q"))
2042 (label_ref (match_operand 2 "" ""))
2047 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2048 get_attr_length (insn), 0, insn, 0);
2050 [(set_attr "type" "cbranch")
2051 (set (attr "length")
2052 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2060 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2062 (match_operand:SI 1 "register_operand" "q"))
2065 (label_ref (match_operand 2 "" ""))))]
2069 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2070 get_attr_length (insn), 1, insn, 0);
2072 [(set_attr "type" "cbranch")
2073 (set (attr "length")
2074 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2082 (ne (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2084 (match_operand:DI 1 "register_operand" "q"))
2087 (label_ref (match_operand 2 "" ""))))]
2091 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2092 get_attr_length (insn), 1, insn, 0);
2094 [(set_attr "type" "cbranch")
2095 (set (attr "length")
2096 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2104 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2106 (match_operand:SI 1 "register_operand" "q"))
2108 (label_ref (match_operand 2 "" ""))
2113 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2114 get_attr_length (insn), 0, insn, 1);
2116 [(set_attr "type" "cbranch")
2117 (set (attr "length")
2118 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2126 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2128 (match_operand:DI 1 "register_operand" "q"))
2130 (label_ref (match_operand 2 "" ""))
2135 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2136 get_attr_length (insn), 0, insn, 1);
2138 [(set_attr "type" "cbranch")
2139 (set (attr "length")
2140 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2148 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r")
2150 (match_operand:SI 1 "register_operand" "q"))
2153 (label_ref (match_operand 2 "" ""))))]
2157 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2158 get_attr_length (insn), 1, insn, 1);
2160 [(set_attr "type" "cbranch")
2161 (set (attr "length")
2162 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2170 (eq (zero_extract:DI (match_operand:DI 0 "register_operand" "r")
2172 (match_operand:DI 1 "register_operand" "q"))
2175 (label_ref (match_operand 2 "" ""))))]
2179 return output_bvb (operands, INSN_ANNULLED_BRANCH_P (insn),
2180 get_attr_length (insn), 1, insn, 1);
2182 [(set_attr "type" "cbranch")
2183 (set (attr "length")
2184 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
2189 ;; Floating point branches
2191 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2192 (label_ref (match_operand 0 "" ""))
2194 "! TARGET_SOFT_FLOAT"
2197 if (INSN_ANNULLED_BRANCH_P (insn))
2198 return \"ftest\;b,n %0\";
2200 return \"ftest\;b%* %0\";
2202 [(set_attr "type" "fbranch")
2203 (set_attr "length" "8")])
2206 [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
2208 (label_ref (match_operand 0 "" ""))))]
2209 "! TARGET_SOFT_FLOAT"
2212 if (INSN_ANNULLED_BRANCH_P (insn))
2213 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b,n %0\";
2215 return \"ftest\;add,tr %%r0,%%r0,%%r0\;b%* %0\";
2217 [(set_attr "type" "fbranch")
2218 (set_attr "length" "12")])
2220 ;; Move instructions
2222 (define_expand "movsi"
2223 [(set (match_operand:SI 0 "general_operand" "")
2224 (match_operand:SI 1 "general_operand" ""))]
2228 if (emit_move_sequence (operands, SImode, 0))
2232 ;; Reloading an SImode or DImode value requires a scratch register if
2233 ;; going in to or out of float point registers.
2235 (define_expand "reload_insi"
2236 [(set (match_operand:SI 0 "register_operand" "=Z")
2237 (match_operand:SI 1 "non_hard_reg_operand" ""))
2238 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2242 if (emit_move_sequence (operands, SImode, operands[2]))
2245 /* We don't want the clobber emitted, so handle this ourselves. */
2246 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2250 (define_expand "reload_outsi"
2251 [(set (match_operand:SI 0 "non_hard_reg_operand" "")
2252 (match_operand:SI 1 "register_operand" "Z"))
2253 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
2257 if (emit_move_sequence (operands, SImode, operands[2]))
2260 /* We don't want the clobber emitted, so handle this ourselves. */
2261 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
2266 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2267 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
2268 (match_operand:SI 1 "move_operand"
2269 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
2270 "(register_operand (operands[0], SImode)
2271 || reg_or_0_operand (operands[1], SImode))
2272 && ! TARGET_SOFT_FLOAT"
2278 {zdepi|depwi,z} %Z1,%0
2285 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
2286 (set_attr "pa_combine_type" "addmove")
2287 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
2290 [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
2291 "=r,r,r,r,r,r,Q,*q")
2292 (match_operand:SI 1 "move_operand"
2293 "A,r,J,N,K,RQ,rM,rM"))]
2294 "(register_operand (operands[0], SImode)
2295 || reg_or_0_operand (operands[1], SImode))
2296 && TARGET_SOFT_FLOAT"
2302 {zdepi|depwi,z} %Z1,%0
2306 [(set_attr "type" "load,move,move,move,move,load,store,move")
2307 (set_attr "pa_combine_type" "addmove")
2308 (set_attr "length" "4,4,4,4,4,4,4,4")])
2311 [(set (match_operand:SI 0 "register_operand" "=r")
2312 (mem:SI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2313 (match_operand:SI 2 "register_operand" "r"))))]
2314 "! TARGET_DISABLE_INDEXING"
2315 "{ldwx|ldw} %2(%1),%0"
2316 [(set_attr "type" "load")
2317 (set_attr "length" "4")])
2320 [(set (match_operand:SI 0 "register_operand" "=r")
2321 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2322 (match_operand:SI 2 "basereg_operand" "r"))))]
2323 "! TARGET_DISABLE_INDEXING"
2324 "{ldwx|ldw} %1(%2),%0"
2325 [(set_attr "type" "load")
2326 (set_attr "length" "4")])
2328 ;; Load or store with base-register modification.
2330 (define_expand "pre_load"
2331 [(parallel [(set (match_operand:SI 0 "register_operand" "")
2332 (mem (plus (match_operand 1 "register_operand" "")
2333 (match_operand 2 "pre_cint_operand" ""))))
2335 (plus (match_dup 1) (match_dup 2)))])]
2341 emit_insn (gen_pre_ldd (operands[0], operands[1], operands[2]));
2344 emit_insn (gen_pre_ldw (operands[0], operands[1], operands[2]));
2348 (define_insn "pre_ldw"
2349 [(set (match_operand:SI 0 "register_operand" "=r")
2350 (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2351 (match_operand:SI 2 "pre_cint_operand" ""))))
2353 (plus:SI (match_dup 1) (match_dup 2)))]
2357 if (INTVAL (operands[2]) < 0)
2358 return \"{ldwm|ldw,mb} %2(%1),%0\";
2359 return \"{ldws|ldw},mb %2(%1),%0\";
2361 [(set_attr "type" "load")
2362 (set_attr "length" "4")])
2364 (define_insn "pre_ldd"
2365 [(set (match_operand:DI 0 "register_operand" "=r")
2366 (mem:DI (plus:DI (match_operand:DI 1 "register_operand" "+r")
2367 (match_operand:DI 2 "pre_cint_operand" ""))))
2369 (plus:DI (match_dup 1) (match_dup 2)))]
2372 [(set_attr "type" "load")
2373 (set_attr "length" "4")])
2376 [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2377 (match_operand:SI 1 "pre_cint_operand" "")))
2378 (match_operand:SI 2 "reg_or_0_operand" "rM"))
2380 (plus:SI (match_dup 0) (match_dup 1)))]
2384 if (INTVAL (operands[1]) < 0)
2385 return \"{stwm|stw,mb} %r2,%1(%0)\";
2386 return \"{stws|stw},mb %r2,%1(%0)\";
2388 [(set_attr "type" "store")
2389 (set_attr "length" "4")])
2392 [(set (match_operand:SI 0 "register_operand" "=r")
2393 (mem:SI (match_operand:SI 1 "register_operand" "+r")))
2395 (plus:SI (match_dup 1)
2396 (match_operand:SI 2 "post_cint_operand" "")))]
2400 if (INTVAL (operands[2]) > 0)
2401 return \"{ldwm|ldw,ma} %2(%1),%0\";
2402 return \"{ldws|ldw},ma %2(%1),%0\";
2404 [(set_attr "type" "load")
2405 (set_attr "length" "4")])
2407 (define_expand "post_store"
2408 [(parallel [(set (mem (match_operand 0 "register_operand" ""))
2409 (match_operand 1 "reg_or_0_operand" ""))
2412 (match_operand 2 "post_cint_operand" "")))])]
2418 emit_insn (gen_post_std (operands[0], operands[1], operands[2]));
2421 emit_insn (gen_post_stw (operands[0], operands[1], operands[2]));
2425 (define_insn "post_stw"
2426 [(set (mem:SI (match_operand:SI 0 "register_operand" "+r"))
2427 (match_operand:SI 1 "reg_or_0_operand" "rM"))
2429 (plus:SI (match_dup 0)
2430 (match_operand:SI 2 "post_cint_operand" "")))]
2434 if (INTVAL (operands[2]) > 0)
2435 return \"{stwm|stw,ma} %r1,%2(%0)\";
2436 return \"{stws|stw},ma %r1,%2(%0)\";
2438 [(set_attr "type" "store")
2439 (set_attr "length" "4")])
2441 (define_insn "post_std"
2442 [(set (mem:DI (match_operand:DI 0 "register_operand" "+r"))
2443 (match_operand:DI 1 "reg_or_0_operand" "rM"))
2445 (plus:DI (match_dup 0)
2446 (match_operand:DI 2 "post_cint_operand" "")))]
2449 [(set_attr "type" "store")
2450 (set_attr "length" "4")])
2452 ;; For loading the address of a label while generating PIC code.
2453 ;; Note since this pattern can be created at reload time (via movsi), all
2454 ;; the same rules for movsi apply here. (no new pseudos, no temporaries).
2456 [(set (match_operand 0 "pmode_register_operand" "=a")
2457 (match_operand 1 "pic_label_operand" ""))]
2462 extern FILE *asm_out_file;
2464 xoperands[0] = operands[0];
2465 xoperands[1] = operands[1];
2466 if (TARGET_SOM || ! TARGET_GAS)
2467 xoperands[2] = gen_label_rtx ();
2469 output_asm_insn (\"{bl|b,l} .+8,%0\", xoperands);
2470 output_asm_insn (\"{depi|depwi} 0,31,2,%0\", xoperands);
2471 if (TARGET_SOM || ! TARGET_GAS)
2472 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
2473 CODE_LABEL_NUMBER (xoperands[2]));
2475 /* If we're trying to load the address of a label that happens to be
2476 close, then we can use a shorter sequence. */
2477 if (GET_CODE (operands[1]) == LABEL_REF
2478 && INSN_ADDRESSES_SET_P ()
2479 && abs (INSN_ADDRESSES (INSN_UID (XEXP (operands[1], 0)))
2480 - INSN_ADDRESSES (INSN_UID (insn))) < 8100)
2482 /* Prefixing with R% here is wrong, it extracts just 11 bits and is
2483 always non-negative. */
2484 if (TARGET_SOM || ! TARGET_GAS)
2485 output_asm_insn (\"ldo %1-%2(%0),%0\", xoperands);
2487 output_asm_insn (\"ldo %1-$PIC_pcrel$0+8(%0),%0\", xoperands);
2491 if (TARGET_SOM || ! TARGET_GAS)
2493 output_asm_insn (\"addil L%%%1-%2,%0\", xoperands);
2494 output_asm_insn (\"ldo R%%%1-%2(%0),%0\", xoperands);
2498 output_asm_insn (\"addil L%%%1-$PIC_pcrel$0+8,%0\", xoperands);
2499 output_asm_insn (\"ldo R%%%1-$PIC_pcrel$0+12(%0),%0\",
2505 [(set_attr "type" "multi")
2506 (set_attr "length" "16")]) ; 12 or 16
2509 [(set (match_operand:SI 0 "register_operand" "=a")
2510 (plus:SI (match_operand:SI 1 "register_operand" "r")
2511 (high:SI (match_operand 2 "" ""))))]
2512 "symbolic_operand (operands[2], Pmode)
2513 && ! function_label_operand (operands[2], Pmode)
2516 [(set_attr "type" "binary")
2517 (set_attr "length" "4")])
2520 [(set (match_operand:DI 0 "register_operand" "=a")
2521 (plus:DI (match_operand:DI 1 "register_operand" "r")
2522 (high:DI (match_operand 2 "" ""))))]
2523 "symbolic_operand (operands[2], Pmode)
2524 && ! function_label_operand (operands[2], Pmode)
2528 [(set_attr "type" "binary")
2529 (set_attr "length" "4")])
2531 ;; Always use addil rather than ldil;add sequences. This allows the
2532 ;; HP linker to eliminate the dp relocation if the symbolic operand
2533 ;; lives in the TEXT space.
2535 [(set (match_operand:SI 0 "register_operand" "=a")
2536 (high:SI (match_operand 1 "" "")))]
2537 "symbolic_operand (operands[1], Pmode)
2538 && ! function_label_operand (operands[1], Pmode)
2539 && ! read_only_operand (operands[1], Pmode)
2543 if (TARGET_LONG_LOAD_STORE)
2544 return \"addil NLR'%H1,%%r27\;ldo N'%H1(%%r1),%%r1\";
2546 return \"addil LR'%H1,%%r27\";
2548 [(set_attr "type" "binary")
2549 (set (attr "length")
2550 (if_then_else (eq (symbol_ref "TARGET_LONG_LOAD_STORE") (const_int 0))
2555 ;; This is for use in the prologue/epilogue code. We need it
2556 ;; to add large constants to a stack pointer or frame pointer.
2557 ;; Because of the additional %r1 pressure, we probably do not
2558 ;; want to use this in general code, so make it available
2559 ;; only after reload.
2561 [(set (match_operand:SI 0 "register_operand" "=!a,*r")
2562 (plus:SI (match_operand:SI 1 "register_operand" "r,r")
2563 (high:SI (match_operand 2 "const_int_operand" ""))))]
2567 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2568 [(set_attr "type" "binary,binary")
2569 (set_attr "length" "4,8")])
2572 [(set (match_operand:DI 0 "register_operand" "=!a,*r")
2573 (plus:DI (match_operand:DI 1 "register_operand" "r,r")
2574 (high:DI (match_operand 2 "const_int_operand" ""))))]
2575 "reload_completed && TARGET_64BIT"
2578 ldil L'%G2,%0\;{addl|add,l} %0,%1,%0"
2579 [(set_attr "type" "binary,binary")
2580 (set_attr "length" "4,8")])
2583 [(set (match_operand:SI 0 "register_operand" "=r")
2584 (high:SI (match_operand 1 "" "")))]
2585 "(!flag_pic || !symbolic_operand (operands[1], Pmode))
2586 && !is_function_label_plus_const (operands[1])"
2589 if (symbolic_operand (operands[1], Pmode))
2590 return \"ldil LR'%H1,%0\";
2592 return \"ldil L'%G1,%0\";
2594 [(set_attr "type" "move")
2595 (set_attr "length" "4")])
2598 [(set (match_operand:DI 0 "register_operand" "=r")
2599 (high:DI (match_operand 1 "const_int_operand" "")))]
2602 [(set_attr "type" "move")
2603 (set_attr "length" "4")])
2606 [(set (match_operand:DI 0 "register_operand" "=r")
2607 (lo_sum:DI (match_operand:DI 1 "register_operand" "r")
2608 (match_operand:DI 2 "const_int_operand" "i")))]
2611 [(set_attr "type" "move")
2612 (set_attr "length" "4")])
2615 [(set (match_operand:SI 0 "register_operand" "=r")
2616 (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
2617 (match_operand:SI 2 "immediate_operand" "i")))]
2618 "!is_function_label_plus_const (operands[2])"
2621 if (flag_pic && symbolic_operand (operands[2], Pmode))
2623 else if (symbolic_operand (operands[2], Pmode))
2624 return \"ldo RR'%G2(%1),%0\";
2626 return \"ldo R'%G2(%1),%0\";
2628 [(set_attr "type" "move")
2629 (set_attr "length" "4")])
2631 ;; Now that a symbolic_address plus a constant is broken up early
2632 ;; in the compilation phase (for better CSE) we need a special
2633 ;; combiner pattern to load the symbolic address plus the constant
2634 ;; in only 2 instructions. (For cases where the symbolic address
2635 ;; was not a common subexpression.)
2637 [(set (match_operand:SI 0 "register_operand" "")
2638 (match_operand:SI 1 "symbolic_operand" ""))
2639 (clobber (match_operand:SI 2 "register_operand" ""))]
2640 "! (flag_pic && pic_label_operand (operands[1], SImode))"
2641 [(set (match_dup 2) (high:SI (match_dup 1)))
2642 (set (match_dup 0) (lo_sum:SI (match_dup 2) (match_dup 1)))]
2645 ;; hppa_legitimize_address goes to a great deal of trouble to
2646 ;; create addresses which use indexing. In some cases, this
2647 ;; is a lose because there isn't any store instructions which
2648 ;; allow indexed addresses (with integer register source).
2650 ;; These define_splits try to turn a 3 insn store into
2651 ;; a 2 insn store with some creative RTL rewriting.
2653 [(set (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2654 (match_operand:SI 1 "shadd_operand" ""))
2655 (plus:SI (match_operand:SI 2 "register_operand" "")
2656 (match_operand:SI 3 "const_int_operand" ""))))
2657 (match_operand:SI 4 "register_operand" ""))
2658 (clobber (match_operand:SI 5 "register_operand" ""))]
2660 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2662 (set (mem:SI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2666 [(set (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2667 (match_operand:SI 1 "shadd_operand" ""))
2668 (plus:SI (match_operand:SI 2 "register_operand" "")
2669 (match_operand:SI 3 "const_int_operand" ""))))
2670 (match_operand:HI 4 "register_operand" ""))
2671 (clobber (match_operand:SI 5 "register_operand" ""))]
2673 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2675 (set (mem:HI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2679 [(set (mem:QI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "")
2680 (match_operand:SI 1 "shadd_operand" ""))
2681 (plus:SI (match_operand:SI 2 "register_operand" "")
2682 (match_operand:SI 3 "const_int_operand" ""))))
2683 (match_operand:QI 4 "register_operand" ""))
2684 (clobber (match_operand:SI 5 "register_operand" ""))]
2686 [(set (match_dup 5) (plus:SI (mult:SI (match_dup 0) (match_dup 1))
2688 (set (mem:QI (plus:SI (match_dup 5) (match_dup 3))) (match_dup 4))]
2691 (define_expand "movhi"
2692 [(set (match_operand:HI 0 "general_operand" "")
2693 (match_operand:HI 1 "general_operand" ""))]
2697 if (emit_move_sequence (operands, HImode, 0))
2702 [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2703 (match_operand:HI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2704 "register_operand (operands[0], HImode)
2705 || reg_or_0_operand (operands[1], HImode)"
2710 {zdepi|depwi,z} %Z1,%0
2715 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2716 (set_attr "pa_combine_type" "addmove")
2717 (set_attr "length" "4,4,4,4,4,4,4,4")])
2720 [(set (match_operand:HI 0 "register_operand" "=r")
2721 (mem:HI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2722 (match_operand:SI 2 "register_operand" "r"))))]
2723 "! TARGET_DISABLE_INDEXING"
2724 "{ldhx|ldh} %2(%1),%0"
2725 [(set_attr "type" "load")
2726 (set_attr "length" "4")])
2729 [(set (match_operand:HI 0 "register_operand" "=r")
2730 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
2731 (match_operand:SI 2 "basereg_operand" "r"))))]
2732 "! TARGET_DISABLE_INDEXING"
2733 "{ldhx|ldh} %1(%2),%0"
2734 [(set_attr "type" "load")
2735 (set_attr "length" "4")])
2737 ; Now zero extended variants.
2739 [(set (match_operand:SI 0 "register_operand" "=r")
2740 (zero_extend:SI (mem:HI
2742 (match_operand:SI 1 "basereg_operand" "r")
2743 (match_operand:SI 2 "register_operand" "r")))))]
2744 "! TARGET_DISABLE_INDEXING"
2745 "{ldhx|ldh} %2(%1),%0"
2746 [(set_attr "type" "load")
2747 (set_attr "length" "4")])
2750 [(set (match_operand:SI 0 "register_operand" "=r")
2751 (zero_extend:SI (mem:HI
2753 (match_operand:SI 1 "register_operand" "r")
2754 (match_operand:SI 2 "basereg_operand" "r")))))]
2755 "! TARGET_DISABLE_INDEXING"
2756 "{ldhx|ldh} %1(%2),%0"
2757 [(set_attr "type" "load")
2758 (set_attr "length" "4")])
2761 [(set (match_operand:HI 0 "register_operand" "=r")
2762 (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2763 (match_operand:SI 2 "int5_operand" "L"))))
2765 (plus:SI (match_dup 1) (match_dup 2)))]
2767 "{ldhs|ldh},mb %2(%1),%0"
2768 [(set_attr "type" "load")
2769 (set_attr "length" "4")])
2771 ; And a zero extended variant.
2773 [(set (match_operand:SI 0 "register_operand" "=r")
2774 (zero_extend:SI (mem:HI
2776 (match_operand:SI 1 "register_operand" "+r")
2777 (match_operand:SI 2 "int5_operand" "L")))))
2779 (plus:SI (match_dup 1) (match_dup 2)))]
2781 "{ldhs|ldh},mb %2(%1),%0"
2782 [(set_attr "type" "load")
2783 (set_attr "length" "4")])
2786 [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2787 (match_operand:SI 1 "int5_operand" "L")))
2788 (match_operand:HI 2 "reg_or_0_operand" "rM"))
2790 (plus:SI (match_dup 0) (match_dup 1)))]
2792 "{sths|sth},mb %r2,%1(%0)"
2793 [(set_attr "type" "store")
2794 (set_attr "length" "4")])
2797 [(set (match_operand:HI 0 "register_operand" "=r")
2798 (plus:HI (match_operand:HI 1 "register_operand" "r")
2799 (match_operand 2 "const_int_operand" "J")))]
2802 [(set_attr "type" "binary")
2803 (set_attr "pa_combine_type" "addmove")
2804 (set_attr "length" "4")])
2806 (define_expand "movqi"
2807 [(set (match_operand:QI 0 "general_operand" "")
2808 (match_operand:QI 1 "general_operand" ""))]
2812 if (emit_move_sequence (operands, QImode, 0))
2817 [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,r,r,r,Q,*q,!*f")
2818 (match_operand:QI 1 "move_operand" "r,J,N,K,RQ,rM,rM,!*fM"))]
2819 "register_operand (operands[0], QImode)
2820 || reg_or_0_operand (operands[1], QImode)"
2825 {zdepi|depwi,z} %Z1,%0
2830 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu")
2831 (set_attr "pa_combine_type" "addmove")
2832 (set_attr "length" "4,4,4,4,4,4,4,4")])
2835 [(set (match_operand:QI 0 "register_operand" "=r")
2836 (mem:QI (plus:SI (match_operand:SI 1 "basereg_operand" "r")
2837 (match_operand:SI 2 "register_operand" "r"))))]
2838 "! TARGET_DISABLE_INDEXING"
2839 "{ldbx|ldb} %2(%1),%0"
2840 [(set_attr "type" "load")
2841 (set_attr "length" "4")])
2844 [(set (match_operand:QI 0 "register_operand" "=r")
2845 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
2846 (match_operand:SI 2 "basereg_operand" "r"))))]
2847 "! TARGET_DISABLE_INDEXING"
2848 "{ldbx|ldb} %1(%2),%0"
2849 [(set_attr "type" "load")
2850 (set_attr "length" "4")])
2852 ; Indexed byte load with zero extension to SImode or HImode.
2854 [(set (match_operand:SI 0 "register_operand" "=r")
2855 (zero_extend:SI (mem:QI
2857 (match_operand:SI 1 "basereg_operand" "r")
2858 (match_operand:SI 2 "register_operand" "r")))))]
2859 "! TARGET_DISABLE_INDEXING"
2860 "{ldbx|ldb} %2(%1),%0"
2861 [(set_attr "type" "load")
2862 (set_attr "length" "4")])
2865 [(set (match_operand:SI 0 "register_operand" "=r")
2866 (zero_extend:SI (mem:QI
2868 (match_operand:SI 1 "register_operand" "r")
2869 (match_operand:SI 2 "basereg_operand" "r")))))]
2870 "! TARGET_DISABLE_INDEXING"
2871 "{ldbx|ldb} %1(%2),%0"
2872 [(set_attr "type" "load")
2873 (set_attr "length" "4")])
2876 [(set (match_operand:HI 0 "register_operand" "=r")
2877 (zero_extend:HI (mem:QI
2879 (match_operand:SI 1 "basereg_operand" "r")
2880 (match_operand:SI 2 "register_operand" "r")))))]
2881 "! TARGET_DISABLE_INDEXING"
2882 "{ldbx|ldb} %2(%1),%0"
2883 [(set_attr "type" "load")
2884 (set_attr "length" "4")])
2887 [(set (match_operand:HI 0 "register_operand" "=r")
2888 (zero_extend:HI (mem:QI
2890 (match_operand:SI 1 "register_operand" "r")
2891 (match_operand:SI 2 "basereg_operand" "r")))))]
2892 "! TARGET_DISABLE_INDEXING"
2893 "{ldbx|ldb} %1(%2),%0"
2894 [(set_attr "type" "load")
2895 (set_attr "length" "4")])
2898 [(set (match_operand:QI 0 "register_operand" "=r")
2899 (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "+r")
2900 (match_operand:SI 2 "int5_operand" "L"))))
2901 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2903 "{ldbs|ldb},mb %2(%1),%0"
2904 [(set_attr "type" "load")
2905 (set_attr "length" "4")])
2907 ; Now the same thing with zero extensions.
2909 [(set (match_operand:SI 0 "register_operand" "=r")
2910 (zero_extend:SI (mem:QI (plus:SI
2911 (match_operand:SI 1 "register_operand" "+r")
2912 (match_operand:SI 2 "int5_operand" "L")))))
2913 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2915 "{ldbs|ldb},mb %2(%1),%0"
2916 [(set_attr "type" "load")
2917 (set_attr "length" "4")])
2920 [(set (match_operand:HI 0 "register_operand" "=r")
2921 (zero_extend:HI (mem:QI (plus:SI
2922 (match_operand:SI 1 "register_operand" "+r")
2923 (match_operand:SI 2 "int5_operand" "L")))))
2924 (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))]
2926 "{ldbs|ldb},mb %2(%1),%0"
2927 [(set_attr "type" "load")
2928 (set_attr "length" "4")])
2931 [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "+r")
2932 (match_operand:SI 1 "int5_operand" "L")))
2933 (match_operand:QI 2 "reg_or_0_operand" "rM"))
2935 (plus:SI (match_dup 0) (match_dup 1)))]
2937 "{stbs|stb},mb %r2,%1(%0)"
2938 [(set_attr "type" "store")
2939 (set_attr "length" "4")])
2941 ;; The definition of this insn does not really explain what it does,
2942 ;; but it should suffice
2943 ;; that anything generated as this insn will be recognized as one
2944 ;; and that it will not successfully combine with anything.
2945 (define_expand "movstrsi"
2946 [(parallel [(set (match_operand:BLK 0 "" "")
2947 (match_operand:BLK 1 "" ""))
2948 (clobber (match_dup 7))
2949 (clobber (match_dup 8))
2950 (clobber (match_dup 4))
2951 (clobber (match_dup 5))
2952 (clobber (match_dup 6))
2953 (use (match_operand:SI 2 "arith_operand" ""))
2954 (use (match_operand:SI 3 "const_int_operand" ""))])]
2960 /* HP provides very fast block move library routine for the PA;
2961 this routine includes:
2963 4x4 byte at a time block moves,
2964 1x4 byte at a time with alignment checked at runtime with
2965 attempts to align the source and destination as needed
2968 With that in mind, here's the heuristics to try and guess when
2969 the inlined block move will be better than the library block
2972 If the size isn't constant, then always use the library routines.
2974 If the size is large in respect to the known alignment, then use
2975 the library routines.
2977 If the size is small in repsect to the known alignment, then open
2978 code the copy (since that will lead to better scheduling).
2980 Else use the block move pattern. */
2982 /* Undetermined size, use the library routine. */
2983 if (GET_CODE (operands[2]) != CONST_INT)
2986 size = INTVAL (operands[2]);
2987 align = INTVAL (operands[3]);
2988 align = align > 4 ? 4 : align;
2990 /* If size/alignment > 8 (eg size is large in respect to alignment),
2991 then use the library routines. */
2992 if (size / align > 16)
2995 /* This does happen, but not often enough to worry much about. */
2996 if (size / align < MOVE_RATIO)
2999 /* Fall through means we're going to use our block move pattern. */
3001 = replace_equiv_address (operands[0],
3002 copy_to_mode_reg (SImode, XEXP (operands[0], 0)));
3004 = replace_equiv_address (operands[1],
3005 copy_to_mode_reg (SImode, XEXP (operands[1], 0)));
3006 operands[4] = gen_reg_rtx (SImode);
3007 operands[5] = gen_reg_rtx (SImode);
3008 operands[6] = gen_reg_rtx (SImode);
3009 operands[7] = XEXP (operands[0], 0);
3010 operands[8] = XEXP (operands[1], 0);
3013 ;; The operand constraints are written like this to support both compile-time
3014 ;; and run-time determined byte count. If the count is run-time determined,
3015 ;; the register with the byte count is clobbered by the copying code, and
3016 ;; therefore it is forced to operand 2. If the count is compile-time
3017 ;; determined, we need two scratch registers for the unrolled code.
3018 (define_insn "movstrsi_internal"
3019 [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
3020 (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
3021 (clobber (match_dup 0))
3022 (clobber (match_dup 1))
3023 (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
3024 (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
3025 (clobber (match_operand:SI 6 "register_operand" "=&r,&r")) ;item tmp2
3026 (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
3027 (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
3029 "* return output_block_move (operands, !which_alternative);"
3030 [(set_attr "type" "multi,multi")])
3032 ;; Floating point move insns
3034 ;; This pattern forces (set (reg:DF ...) (const_double ...))
3035 ;; to be reloaded by putting the constant into memory when
3036 ;; reg is a floating point register.
3038 ;; For integer registers we use ldil;ldo to set the appropriate
3041 ;; This must come before the movdf pattern, and it must be present
3042 ;; to handle obscure reloading cases.
3044 [(set (match_operand:DF 0 "register_operand" "=?r,f")
3045 (match_operand:DF 1 "" "?F,m"))]
3046 "GET_CODE (operands[1]) == CONST_DOUBLE
3047 && operands[1] != CONST0_RTX (DFmode)
3049 && ! TARGET_SOFT_FLOAT"
3050 "* return (which_alternative == 0 ? output_move_double (operands)
3051 : \"fldd%F1 %1,%0\");"
3052 [(set_attr "type" "move,fpload")
3053 (set_attr "length" "16,4")])
3055 (define_expand "movdf"
3056 [(set (match_operand:DF 0 "general_operand" "")
3057 (match_operand:DF 1 "general_operand" ""))]
3061 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3062 operands[1] = force_const_mem (DFmode, operands[1]);
3064 if (emit_move_sequence (operands, DFmode, 0))
3068 ;; Reloading an SImode or DImode value requires a scratch register if
3069 ;; going in to or out of float point registers.
3071 (define_expand "reload_indf"
3072 [(set (match_operand:DF 0 "register_operand" "=Z")
3073 (match_operand:DF 1 "non_hard_reg_operand" ""))
3074 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3078 if (emit_move_sequence (operands, DFmode, operands[2]))
3081 /* We don't want the clobber emitted, so handle this ourselves. */
3082 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3086 (define_expand "reload_outdf"
3087 [(set (match_operand:DF 0 "non_hard_reg_operand" "")
3088 (match_operand:DF 1 "register_operand" "Z"))
3089 (clobber (match_operand:DF 2 "register_operand" "=&r"))]
3093 if (emit_move_sequence (operands, DFmode, operands[2]))
3096 /* We don't want the clobber emitted, so handle this ourselves. */
3097 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3102 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3103 "=f,*r,RQ,?o,?Q,f,*r,*r")
3104 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3105 "fG,*rG,f,*r,*r,RQ,o,RQ"))]
3106 "(register_operand (operands[0], DFmode)
3107 || reg_or_0_operand (operands[1], DFmode))
3108 && ! (GET_CODE (operands[1]) == CONST_DOUBLE
3109 && GET_CODE (operands[0]) == MEM)
3111 && ! TARGET_SOFT_FLOAT"
3114 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3115 || operands[1] == CONST0_RTX (DFmode))
3116 return output_fp_move_double (operands);
3117 return output_move_double (operands);
3119 [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
3120 (set_attr "length" "4,8,4,8,16,4,8,16")])
3123 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3125 (match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
3127 "(register_operand (operands[0], DFmode)
3128 || reg_or_0_operand (operands[1], DFmode))
3130 && TARGET_SOFT_FLOAT"
3133 return output_move_double (operands);
3135 [(set_attr "type" "move,store,store,load,load")
3136 (set_attr "length" "8,8,16,8,16")])
3139 [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
3140 "=r,r,r,r,r,Q,*q,!f,f,*TR")
3141 (match_operand:DF 1 "move_operand"
3142 "r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3143 "(register_operand (operands[0], DFmode)
3144 || reg_or_0_operand (operands[1], DFmode))
3145 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3157 [(set_attr "type" "move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3158 (set_attr "pa_combine_type" "addmove")
3159 (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
3162 [(set (match_operand:DF 0 "register_operand" "=fx")
3163 (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3164 (match_operand:SI 2 "register_operand" "r"))))]
3165 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3166 "{flddx|fldd} %2(%1),%0"
3167 [(set_attr "type" "fpload")
3168 (set_attr "length" "4")])
3171 [(set (match_operand:DF 0 "register_operand" "=fx")
3172 (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3173 (match_operand:SI 2 "basereg_operand" "r"))))]
3174 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3175 "{flddx|fldd} %1(%2),%0"
3176 [(set_attr "type" "fpload")
3177 (set_attr "length" "4")])
3180 [(set (mem:DF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3181 (match_operand:SI 2 "register_operand" "r")))
3182 (match_operand:DF 0 "register_operand" "fx"))]
3183 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3184 "{fstdx|fstd} %0,%2(%1)"
3185 [(set_attr "type" "fpstore")
3186 (set_attr "length" "4")])
3189 [(set (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "r")
3190 (match_operand:SI 2 "basereg_operand" "r")))
3191 (match_operand:DF 0 "register_operand" "fx"))]
3192 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3193 "{fstdx|fstd} %0,%1(%2)"
3194 [(set_attr "type" "fpstore")
3195 (set_attr "length" "4")])
3197 (define_expand "movdi"
3198 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
3199 (match_operand:DI 1 "general_operand" ""))]
3203 if (GET_CODE (operands[1]) == CONST_DOUBLE && TARGET_64BIT)
3204 operands[1] = force_const_mem (DImode, operands[1]);
3206 if (emit_move_sequence (operands, DImode, 0))
3210 (define_expand "reload_indi"
3211 [(set (match_operand:DI 0 "register_operand" "=Z")
3212 (match_operand:DI 1 "non_hard_reg_operand" ""))
3213 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3217 if (emit_move_sequence (operands, DImode, operands[2]))
3220 /* We don't want the clobber emitted, so handle this ourselves. */
3221 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3225 (define_expand "reload_outdi"
3226 [(set (match_operand:DI 0 "non_hard_reg_operand" "")
3227 (match_operand:DI 1 "register_operand" "Z"))
3228 (clobber (match_operand:SI 2 "register_operand" "=&r"))]
3232 if (emit_move_sequence (operands, DImode, operands[2]))
3235 /* We don't want the clobber emitted, so handle this ourselves. */
3236 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3241 [(set (match_operand:DI 0 "register_operand" "=r")
3242 (high:DI (match_operand 1 "" "")))]
3246 rtx op0 = operands[0];
3247 rtx op1 = operands[1];
3249 if (GET_CODE (op1) == CONST_INT)
3251 operands[0] = operand_subword (op0, 1, 0, DImode);
3252 output_asm_insn (\"ldil L'%1,%0\", operands);
3254 operands[0] = operand_subword (op0, 0, 0, DImode);
3255 if (INTVAL (op1) < 0)
3256 output_asm_insn (\"ldi -1,%0\", operands);
3258 output_asm_insn (\"ldi 0,%0\", operands);
3261 else if (GET_CODE (op1) == CONST_DOUBLE)
3263 operands[0] = operand_subword (op0, 1, 0, DImode);
3264 operands[1] = GEN_INT (CONST_DOUBLE_LOW (op1));
3265 output_asm_insn (\"ldil L'%1,%0\", operands);
3267 operands[0] = operand_subword (op0, 0, 0, DImode);
3268 operands[1] = GEN_INT (CONST_DOUBLE_HIGH (op1));
3269 output_asm_insn (singlemove_string (operands), operands);
3275 [(set_attr "type" "move")
3276 (set_attr "length" "8")])
3279 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3280 "=r,o,Q,r,r,r,f,f,*TR")
3281 (match_operand:DI 1 "general_operand"
3282 "rM,r,r,o*R,Q,i,fM,*TR,f"))]
3283 "(register_operand (operands[0], DImode)
3284 || reg_or_0_operand (operands[1], DImode))
3286 && ! TARGET_SOFT_FLOAT"
3289 if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
3290 || (operands[1] == CONST0_RTX (DImode)))
3291 return output_fp_move_double (operands);
3292 return output_move_double (operands);
3294 [(set_attr "type" "move,store,store,load,load,multi,fpalu,fpload,fpstore")
3295 (set_attr "length" "8,8,16,8,16,16,4,4,4")])
3298 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3299 "=r,r,r,r,r,r,Q,*q,!f,f,*TR")
3300 (match_operand:DI 1 "move_operand"
3301 "A,r,J,N,K,RQ,rM,rM,!fM,*RT,f"))]
3302 "(register_operand (operands[0], DImode)
3303 || reg_or_0_operand (operands[1], DImode))
3304 && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
3317 [(set_attr "type" "load,move,move,move,shift,load,store,move,fpalu,fpload,fpstore")
3318 (set_attr "pa_combine_type" "addmove")
3319 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4")])
3322 [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
3324 (match_operand:DI 1 "general_operand"
3326 "(register_operand (operands[0], DImode)
3327 || reg_or_0_operand (operands[1], DImode))
3329 && TARGET_SOFT_FLOAT"
3332 return output_move_double (operands);
3334 [(set_attr "type" "move,store,store,load,load,multi")
3335 (set_attr "length" "8,8,16,8,16,16")])
3338 [(set (match_operand:DI 0 "register_operand" "=r,&r")
3339 (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
3340 (match_operand:DI 2 "immediate_operand" "i,i")))]
3344 /* Don't output a 64 bit constant, since we can't trust the assembler to
3345 handle it correctly. */
3346 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3347 operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3348 if (which_alternative == 1)
3349 output_asm_insn (\"copy %1,%0\", operands);
3350 return \"ldo R'%G2(%R1),%R0\";
3352 [(set_attr "type" "move,move")
3353 (set_attr "length" "4,8")])
3355 ;; This pattern forces (set (reg:SF ...) (const_double ...))
3356 ;; to be reloaded by putting the constant into memory when
3357 ;; reg is a floating point register.
3359 ;; For integer registers we use ldil;ldo to set the appropriate
3362 ;; This must come before the movsf pattern, and it must be present
3363 ;; to handle obscure reloading cases.
3365 [(set (match_operand:SF 0 "register_operand" "=?r,f")
3366 (match_operand:SF 1 "" "?F,m"))]
3367 "GET_CODE (operands[1]) == CONST_DOUBLE
3368 && operands[1] != CONST0_RTX (SFmode)
3369 && ! TARGET_SOFT_FLOAT"
3370 "* return (which_alternative == 0 ? singlemove_string (operands)
3371 : \" fldw%F1 %1,%0\");"
3372 [(set_attr "type" "move,fpload")
3373 (set_attr "length" "8,4")])
3375 (define_expand "movsf"
3376 [(set (match_operand:SF 0 "general_operand" "")
3377 (match_operand:SF 1 "general_operand" ""))]
3381 if (emit_move_sequence (operands, SFmode, 0))
3385 ;; Reloading an SImode or DImode value requires a scratch register if
3386 ;; going in to or out of float point registers.
3388 (define_expand "reload_insf"
3389 [(set (match_operand:SF 0 "register_operand" "=Z")
3390 (match_operand:SF 1 "non_hard_reg_operand" ""))
3391 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3395 if (emit_move_sequence (operands, SFmode, operands[2]))
3398 /* We don't want the clobber emitted, so handle this ourselves. */
3399 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3403 (define_expand "reload_outsf"
3404 [(set (match_operand:SF 0 "non_hard_reg_operand" "")
3405 (match_operand:SF 1 "register_operand" "Z"))
3406 (clobber (match_operand:SF 2 "register_operand" "=&r"))]
3410 if (emit_move_sequence (operands, SFmode, operands[2]))
3413 /* We don't want the clobber emitted, so handle this ourselves. */
3414 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1]));
3419 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3421 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3422 "fG,rG,RQ,RQ,f,rG"))]
3423 "(register_operand (operands[0], SFmode)
3424 || reg_or_0_operand (operands[1], SFmode))
3425 && ! TARGET_SOFT_FLOAT"
3433 [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
3434 (set_attr "pa_combine_type" "addmove")
3435 (set_attr "length" "4,4,4,4,4,4")])
3438 [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
3440 (match_operand:SF 1 "reg_or_0_or_nonsymb_mem_operand"
3442 "(register_operand (operands[0], SFmode)
3443 || reg_or_0_operand (operands[1], SFmode))
3444 && TARGET_SOFT_FLOAT"
3449 [(set_attr "type" "move,load,store")
3450 (set_attr "pa_combine_type" "addmove")
3451 (set_attr "length" "4,4,4")])
3454 [(set (match_operand:SF 0 "register_operand" "=fx")
3455 (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3456 (match_operand:SI 2 "register_operand" "r"))))]
3457 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3458 "{fldwx|fldw} %2(%1),%0"
3459 [(set_attr "type" "fpload")
3460 (set_attr "length" "4")])
3463 [(set (match_operand:SF 0 "register_operand" "=fx")
3464 (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3465 (match_operand:SI 2 "basereg_operand" "r"))))]
3466 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3467 "{fldwx|fldw} %1(%2),%0"
3468 [(set_attr "type" "fpload")
3469 (set_attr "length" "4")])
3472 [(set (mem:SF (plus:SI (match_operand:SI 1 "basereg_operand" "r")
3473 (match_operand:SI 2 "register_operand" "r")))
3474 (match_operand:SF 0 "register_operand" "fx"))]
3475 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3476 "{fstwx|fstw} %0,%2(%1)"
3477 [(set_attr "type" "fpstore")
3478 (set_attr "length" "4")])
3481 [(set (mem:SF (plus:SI (match_operand:SI 1 "register_operand" "r")
3482 (match_operand:SI 2 "basereg_operand" "r")))
3483 (match_operand:SF 0 "register_operand" "fx"))]
3484 "! TARGET_DISABLE_INDEXING && ! TARGET_SOFT_FLOAT"
3485 "{fstwx|fstw} %0,%1(%2)"
3486 [(set_attr "type" "fpstore")
3487 (set_attr "length" "4")])
3490 ;;- zero extension instructions
3491 ;; We have define_expand for zero extension patterns to make sure the
3492 ;; operands get loaded into registers. The define_insns accept
3493 ;; memory operands. This gives us better overall code than just
3494 ;; having a pattern that does or does not accept memory operands.
3496 (define_expand "zero_extendhisi2"
3497 [(set (match_operand:SI 0 "register_operand" "")
3499 (match_operand:HI 1 "register_operand" "")))]
3504 [(set (match_operand:SI 0 "register_operand" "=r,r")
3506 (match_operand:HI 1 "move_operand" "r,RQ")))]
3507 "GET_CODE (operands[1]) != CONST_INT"
3509 {extru|extrw,u} %1,31,16,%0
3511 [(set_attr "type" "shift,load")
3512 (set_attr "length" "4,4")])
3514 (define_expand "zero_extendqihi2"
3515 [(set (match_operand:HI 0 "register_operand" "")
3517 (match_operand:QI 1 "register_operand" "")))]
3522 [(set (match_operand:HI 0 "register_operand" "=r,r")
3524 (match_operand:QI 1 "move_operand" "r,RQ")))]
3525 "GET_CODE (operands[1]) != CONST_INT"
3527 {extru|extrw,u} %1,31,8,%0
3529 [(set_attr "type" "shift,load")
3530 (set_attr "length" "4,4")])
3532 (define_expand "zero_extendqisi2"
3533 [(set (match_operand:SI 0 "register_operand" "")
3535 (match_operand:QI 1 "register_operand" "")))]
3540 [(set (match_operand:SI 0 "register_operand" "=r,r")
3542 (match_operand:QI 1 "move_operand" "r,RQ")))]
3543 "GET_CODE (operands[1]) != CONST_INT"
3545 {extru|extrw,u} %1,31,8,%0
3547 [(set_attr "type" "shift,load")
3548 (set_attr "length" "4,4")])
3550 (define_insn "zero_extendqidi2"
3551 [(set (match_operand:DI 0 "register_operand" "=r")
3552 (zero_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3554 "extrd,u %1,63,8,%0"
3555 [(set_attr "type" "shift")
3556 (set_attr "length" "4")])
3558 (define_insn "zero_extendhidi2"
3559 [(set (match_operand:DI 0 "register_operand" "=r")
3560 (zero_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3562 "extrd,u %1,63,16,%0"
3563 [(set_attr "type" "shift")
3564 (set_attr "length" "4")])
3566 (define_insn "zero_extendsidi2"
3567 [(set (match_operand:DI 0 "register_operand" "=r")
3568 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3570 "extrd,u %1,63,32,%0"
3571 [(set_attr "type" "shift")
3572 (set_attr "length" "4")])
3574 ;;- sign extension instructions
3576 (define_insn "extendhisi2"
3577 [(set (match_operand:SI 0 "register_operand" "=r")
3578 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
3580 "{extrs|extrw,s} %1,31,16,%0"
3581 [(set_attr "type" "shift")
3582 (set_attr "length" "4")])
3584 (define_insn "extendqihi2"
3585 [(set (match_operand:HI 0 "register_operand" "=r")
3586 (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
3588 "{extrs|extrw,s} %1,31,8,%0"
3589 [(set_attr "type" "shift")
3590 (set_attr "length" "4")])
3592 (define_insn "extendqisi2"
3593 [(set (match_operand:SI 0 "register_operand" "=r")
3594 (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
3596 "{extrs|extrw,s} %1,31,8,%0"
3597 [(set_attr "type" "shift")
3598 (set_attr "length" "4")])
3600 (define_insn "extendqidi2"
3601 [(set (match_operand:DI 0 "register_operand" "=r")
3602 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))]
3604 "extrd,s %1,63,8,%0"
3605 [(set_attr "type" "shift")
3606 (set_attr "length" "4")])
3608 (define_insn "extendhidi2"
3609 [(set (match_operand:DI 0 "register_operand" "=r")
3610 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))]
3612 "extrd,s %1,63,16,%0"
3613 [(set_attr "type" "shift")
3614 (set_attr "length" "4")])
3616 (define_insn "extendsidi2"
3617 [(set (match_operand:DI 0 "register_operand" "=r")
3618 (sign_extend:DI (match_operand:SI 1 "register_operand" "r")))]
3620 "extrd,s %1,63,32,%0"
3621 [(set_attr "type" "shift")
3622 (set_attr "length" "4")])
3625 ;; Conversions between float and double.
3627 (define_insn "extendsfdf2"
3628 [(set (match_operand:DF 0 "register_operand" "=f")
3630 (match_operand:SF 1 "register_operand" "f")))]
3631 "! TARGET_SOFT_FLOAT"
3632 "{fcnvff|fcnv},sgl,dbl %1,%0"
3633 [(set_attr "type" "fpalu")
3634 (set_attr "length" "4")])
3636 (define_insn "truncdfsf2"
3637 [(set (match_operand:SF 0 "register_operand" "=f")
3639 (match_operand:DF 1 "register_operand" "f")))]
3640 "! TARGET_SOFT_FLOAT"
3641 "{fcnvff|fcnv},dbl,sgl %1,%0"
3642 [(set_attr "type" "fpalu")
3643 (set_attr "length" "4")])
3645 ;; Conversion between fixed point and floating point.
3646 ;; Note that among the fix-to-float insns
3647 ;; the ones that start with SImode come first.
3648 ;; That is so that an operand that is a CONST_INT
3649 ;; (and therefore lacks a specific machine mode).
3650 ;; will be recognized as SImode (which is always valid)
3651 ;; rather than as QImode or HImode.
3653 ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
3654 ;; to be reloaded by putting the constant into memory.
3655 ;; It must come before the more general floatsisf2 pattern.
3657 [(set (match_operand:SF 0 "register_operand" "=f")
3658 (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
3659 "! TARGET_SOFT_FLOAT"
3660 "fldw%F1 %1,%0\;{fcnvxf,sgl,sgl|fcnv,w,sgl} %0,%0"
3661 [(set_attr "type" "fpalu")
3662 (set_attr "length" "8")])
3664 (define_insn "floatsisf2"
3665 [(set (match_operand:SF 0 "register_operand" "=f")
3666 (float:SF (match_operand:SI 1 "register_operand" "f")))]
3667 "! TARGET_SOFT_FLOAT"
3668 "{fcnvxf,sgl,sgl|fcnv,w,sgl} %1,%0"
3669 [(set_attr "type" "fpalu")
3670 (set_attr "length" "4")])
3672 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
3673 ;; to be reloaded by putting the constant into memory.
3674 ;; It must come before the more general floatsidf2 pattern.
3676 [(set (match_operand:DF 0 "register_operand" "=f")
3677 (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
3678 "! TARGET_SOFT_FLOAT"
3679 "fldw%F1 %1,%0\;{fcnvxf,sgl,dbl|fcnv,w,dbl} %0,%0"
3680 [(set_attr "type" "fpalu")
3681 (set_attr "length" "8")])
3683 (define_insn "floatsidf2"
3684 [(set (match_operand:DF 0 "register_operand" "=f")
3685 (float:DF (match_operand:SI 1 "register_operand" "f")))]
3686 "! TARGET_SOFT_FLOAT"
3687 "{fcnvxf,sgl,dbl|fcnv,w,dbl} %1,%0"
3688 [(set_attr "type" "fpalu")
3689 (set_attr "length" "4")])
3691 (define_expand "floatunssisf2"
3692 [(set (subreg:SI (match_dup 2) 4)
3693 (match_operand:SI 1 "register_operand" ""))
3694 (set (subreg:SI (match_dup 2) 0)
3696 (set (match_operand:SF 0 "register_operand" "")
3697 (float:SF (match_dup 2)))]
3698 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3703 emit_insn (gen_floatunssisf2_pa20 (operands[0], operands[1]));
3706 operands[2] = gen_reg_rtx (DImode);
3709 (define_expand "floatunssidf2"
3710 [(set (subreg:SI (match_dup 2) 4)
3711 (match_operand:SI 1 "register_operand" ""))
3712 (set (subreg:SI (match_dup 2) 0)
3714 (set (match_operand:DF 0 "register_operand" "")
3715 (float:DF (match_dup 2)))]
3716 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3721 emit_insn (gen_floatunssidf2_pa20 (operands[0], operands[1]));
3724 operands[2] = gen_reg_rtx (DImode);
3727 (define_insn "floatdisf2"
3728 [(set (match_operand:SF 0 "register_operand" "=f")
3729 (float:SF (match_operand:DI 1 "register_operand" "f")))]
3730 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3731 "{fcnvxf,dbl,sgl|fcnv,dw,sgl} %1,%0"
3732 [(set_attr "type" "fpalu")
3733 (set_attr "length" "4")])
3735 (define_insn "floatdidf2"
3736 [(set (match_operand:DF 0 "register_operand" "=f")
3737 (float:DF (match_operand:DI 1 "register_operand" "f")))]
3738 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3739 "{fcnvxf,dbl,dbl|fcnv,dw,dbl} %1,%0"
3740 [(set_attr "type" "fpalu")
3741 (set_attr "length" "4")])
3743 ;; Convert a float to an actual integer.
3744 ;; Truncation is performed as part of the conversion.
3746 (define_insn "fix_truncsfsi2"
3747 [(set (match_operand:SI 0 "register_operand" "=f")
3748 (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3749 "! TARGET_SOFT_FLOAT"
3750 "{fcnvfxt,sgl,sgl|fcnv,t,sgl,w} %1,%0"
3751 [(set_attr "type" "fpalu")
3752 (set_attr "length" "4")])
3754 (define_insn "fix_truncdfsi2"
3755 [(set (match_operand:SI 0 "register_operand" "=f")
3756 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3757 "! TARGET_SOFT_FLOAT"
3758 "{fcnvfxt,dbl,sgl|fcnv,t,dbl,w} %1,%0"
3759 [(set_attr "type" "fpalu")
3760 (set_attr "length" "4")])
3762 (define_insn "fix_truncsfdi2"
3763 [(set (match_operand:DI 0 "register_operand" "=f")
3764 (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3765 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3766 "{fcnvfxt,sgl,dbl|fcnv,t,sgl,dw} %1,%0"
3767 [(set_attr "type" "fpalu")
3768 (set_attr "length" "4")])
3770 (define_insn "fix_truncdfdi2"
3771 [(set (match_operand:DI 0 "register_operand" "=f")
3772 (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3773 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT"
3774 "{fcnvfxt,dbl,dbl|fcnv,t,dbl,dw} %1,%0"
3775 [(set_attr "type" "fpalu")
3776 (set_attr "length" "4")])
3778 (define_insn "floatunssidf2_pa20"
3779 [(set (match_operand:DF 0 "register_operand" "=f")
3780 (unsigned_float:DF (match_operand:SI 1 "register_operand" "f")))]
3781 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3783 [(set_attr "type" "fpalu")
3784 (set_attr "length" "4")])
3786 (define_insn "floatunssisf2_pa20"
3787 [(set (match_operand:SF 0 "register_operand" "=f")
3788 (unsigned_float:SF (match_operand:SI 1 "register_operand" "f")))]
3789 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3791 [(set_attr "type" "fpalu")
3792 (set_attr "length" "4")])
3794 (define_insn "floatunsdisf2"
3795 [(set (match_operand:SF 0 "register_operand" "=f")
3796 (unsigned_float:SF (match_operand:DI 1 "register_operand" "f")))]
3797 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3798 "fcnv,udw,sgl %1,%0"
3799 [(set_attr "type" "fpalu")
3800 (set_attr "length" "4")])
3802 (define_insn "floatunsdidf2"
3803 [(set (match_operand:DF 0 "register_operand" "=f")
3804 (unsigned_float:DF (match_operand:DI 1 "register_operand" "f")))]
3805 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3806 "fcnv,udw,dbl %1,%0"
3807 [(set_attr "type" "fpalu")
3808 (set_attr "length" "4")])
3810 (define_insn "fixuns_truncsfsi2"
3811 [(set (match_operand:SI 0 "register_operand" "=f")
3812 (unsigned_fix:SI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3813 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3814 "fcnv,t,sgl,uw %1,%0"
3815 [(set_attr "type" "fpalu")
3816 (set_attr "length" "4")])
3818 (define_insn "fixuns_truncdfsi2"
3819 [(set (match_operand:SI 0 "register_operand" "=f")
3820 (unsigned_fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3821 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3822 "fcnv,t,dbl,uw %1,%0"
3823 [(set_attr "type" "fpalu")
3824 (set_attr "length" "4")])
3826 (define_insn "fixuns_truncsfdi2"
3827 [(set (match_operand:DI 0 "register_operand" "=f")
3828 (unsigned_fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))]
3829 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3830 "fcnv,t,sgl,udw %1,%0"
3831 [(set_attr "type" "fpalu")
3832 (set_attr "length" "4")])
3834 (define_insn "fixuns_truncdfdi2"
3835 [(set (match_operand:DI 0 "register_operand" "=f")
3836 (unsigned_fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))]
3837 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
3838 "fcnv,t,dbl,udw %1,%0"
3839 [(set_attr "type" "fpalu")
3840 (set_attr "length" "4")])
3842 ;;- arithmetic instructions
3844 (define_expand "adddi3"
3845 [(set (match_operand:DI 0 "register_operand" "")
3846 (plus:DI (match_operand:DI 1 "register_operand" "")
3847 (match_operand:DI 2 "adddi3_operand" "")))]
3852 [(set (match_operand:DI 0 "register_operand" "=r")
3853 (plus:DI (match_operand:DI 1 "register_operand" "%r")
3854 (match_operand:DI 2 "arith11_operand" "rI")))]
3858 if (GET_CODE (operands[2]) == CONST_INT)
3860 if (INTVAL (operands[2]) >= 0)
3861 return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
3863 return \"addi %2,%R1,%R0\;{subb|sub,b} %1,%%r0,%0\";
3866 return \"add %R2,%R1,%R0\;{addc|add,c} %2,%1,%0\";
3868 [(set_attr "type" "binary")
3869 (set_attr "length" "8")])
3872 [(set (match_operand:DI 0 "register_operand" "=r,r")
3873 (plus:DI (match_operand:DI 1 "register_operand" "%r,r")
3874 (match_operand:DI 2 "arith_operand" "r,J")))]
3877 {addl|add,l} %1,%2,%0
3879 [(set_attr "type" "binary,binary")
3880 (set_attr "pa_combine_type" "addmove")
3881 (set_attr "length" "4,4")])
3884 [(set (match_operand:DI 0 "register_operand" "=r")
3885 (plus:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
3886 (match_operand:DI 2 "register_operand" "r")))]
3889 [(set_attr "type" "binary")
3890 (set_attr "length" "4")])
3893 [(set (match_operand:SI 0 "register_operand" "=r")
3894 (plus:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
3895 (match_operand:SI 2 "register_operand" "r")))]
3898 [(set_attr "type" "binary")
3899 (set_attr "length" "4")])
3901 ;; define_splits to optimize cases of adding a constant integer
3902 ;; to a register when the constant does not fit in 14 bits. */
3904 [(set (match_operand:SI 0 "register_operand" "")
3905 (plus:SI (match_operand:SI 1 "register_operand" "")
3906 (match_operand:SI 2 "const_int_operand" "")))
3907 (clobber (match_operand:SI 4 "register_operand" ""))]
3908 "! cint_ok_for_move (INTVAL (operands[2]))
3909 && VAL_14_BITS_P (INTVAL (operands[2]) >> 1)"
3910 [(set (match_dup 4) (plus:SI (match_dup 1) (match_dup 2)))
3911 (set (match_dup 0) (plus:SI (match_dup 4) (match_dup 3)))]
3914 int val = INTVAL (operands[2]);
3915 int low = (val < 0) ? -0x2000 : 0x1fff;
3916 int rest = val - low;
3918 operands[2] = GEN_INT (rest);
3919 operands[3] = GEN_INT (low);
3923 [(set (match_operand:SI 0 "register_operand" "")
3924 (plus:SI (match_operand:SI 1 "register_operand" "")
3925 (match_operand:SI 2 "const_int_operand" "")))
3926 (clobber (match_operand:SI 4 "register_operand" ""))]
3927 "! cint_ok_for_move (INTVAL (operands[2]))"
3928 [(set (match_dup 4) (match_dup 2))
3929 (set (match_dup 0) (plus:SI (mult:SI (match_dup 4) (match_dup 3))
3933 HOST_WIDE_INT intval = INTVAL (operands[2]);
3935 /* Try dividing the constant by 2, then 4, and finally 8 to see
3936 if we can get a constant which can be loaded into a register
3937 in a single instruction (cint_ok_for_move).
3939 If that fails, try to negate the constant and subtract it
3940 from our input operand. */
3941 if (intval % 2 == 0 && cint_ok_for_move (intval / 2))
3943 operands[2] = GEN_INT (intval / 2);
3944 operands[3] = GEN_INT (2);
3946 else if (intval % 4 == 0 && cint_ok_for_move (intval / 4))
3948 operands[2] = GEN_INT (intval / 4);
3949 operands[3] = GEN_INT (4);
3951 else if (intval % 8 == 0 && cint_ok_for_move (intval / 8))
3953 operands[2] = GEN_INT (intval / 8);
3954 operands[3] = GEN_INT (8);
3956 else if (cint_ok_for_move (-intval))
3958 emit_insn (gen_rtx_SET (VOIDmode, operands[4], GEN_INT (-intval)));
3959 emit_insn (gen_subsi3 (operands[0], operands[1], operands[4]));
3966 (define_insn "addsi3"
3967 [(set (match_operand:SI 0 "register_operand" "=r,r")
3968 (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
3969 (match_operand:SI 2 "arith_operand" "r,J")))]
3972 {addl|add,l} %1,%2,%0
3974 [(set_attr "type" "binary,binary")
3975 (set_attr "pa_combine_type" "addmove")
3976 (set_attr "length" "4,4")])
3978 (define_expand "subdi3"
3979 [(set (match_operand:DI 0 "register_operand" "")
3980 (minus:DI (match_operand:DI 1 "register_operand" "")
3981 (match_operand:DI 2 "register_operand" "")))]
3986 [(set (match_operand:DI 0 "register_operand" "=r")
3987 (minus:DI (match_operand:DI 1 "register_operand" "r")
3988 (match_operand:DI 2 "register_operand" "r")))]
3990 "sub %R1,%R2,%R0\;{subb|sub,b} %1,%2,%0"
3991 [(set_attr "type" "binary")
3992 (set_attr "length" "8")])
3995 [(set (match_operand:DI 0 "register_operand" "=r,r,q")
3996 (minus:DI (match_operand:DI 1 "arith11_operand" "r,I,U")
3997 (match_operand:DI 2 "register_operand" "r,r,r")))]
4003 [(set_attr "type" "binary,binary,move")
4004 (set_attr "length" "4,4,4")])
4006 (define_expand "subsi3"
4007 [(set (match_operand:SI 0 "register_operand" "")
4008 (minus:SI (match_operand:SI 1 "arith11_operand" "")
4009 (match_operand:SI 2 "register_operand" "")))]
4014 [(set (match_operand:SI 0 "register_operand" "=r,r")
4015 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
4016 (match_operand:SI 2 "register_operand" "r,r")))]
4021 [(set_attr "type" "binary,binary")
4022 (set_attr "length" "4,4")])
4025 [(set (match_operand:SI 0 "register_operand" "=r,r,q")
4026 (minus:SI (match_operand:SI 1 "arith11_operand" "r,I,S")
4027 (match_operand:SI 2 "register_operand" "r,r,r")))]
4033 [(set_attr "type" "binary,binary,move")
4034 (set_attr "length" "4,4,4")])
4036 ;; Clobbering a "register_operand" instead of a match_scratch
4037 ;; in operand3 of millicode calls avoids spilling %r1 and
4038 ;; produces better code.
4040 ;; The mulsi3 insns set up registers for the millicode call.
4041 (define_expand "mulsi3"
4042 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4043 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4044 (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4045 (clobber (match_dup 3))
4046 (clobber (reg:SI 26))
4047 (clobber (reg:SI 25))
4048 (clobber (match_dup 4))])
4049 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4053 operands[4] = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4054 if (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT)
4056 rtx scratch = gen_reg_rtx (DImode);
4057 operands[1] = force_reg (SImode, operands[1]);
4058 operands[2] = force_reg (SImode, operands[2]);
4059 emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
4060 emit_insn (gen_rtx_SET (VOIDmode, operands[0],
4061 gen_rtx_SUBREG (SImode, scratch, GET_MODE_SIZE (SImode))));
4064 operands[3] = gen_reg_rtx (SImode);
4067 (define_insn "umulsidi3"
4068 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4069 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4070 (zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "f"))))]
4071 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4073 [(set_attr "type" "fpmuldbl")
4074 (set_attr "length" "4")])
4077 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4078 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4079 (match_operand:DI 2 "uint32_operand" "f")))]
4080 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && !TARGET_64BIT"
4082 [(set_attr "type" "fpmuldbl")
4083 (set_attr "length" "4")])
4086 [(set (match_operand:DI 0 "nonimmediate_operand" "=f")
4087 (mult:DI (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "f"))
4088 (match_operand:DI 2 "uint32_operand" "f")))]
4089 "TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT && TARGET_64BIT"
4091 [(set_attr "type" "fpmuldbl")
4092 (set_attr "length" "4")])
4095 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4096 (clobber (match_operand:SI 0 "register_operand" "=a"))
4097 (clobber (reg:SI 26))
4098 (clobber (reg:SI 25))
4099 (clobber (reg:SI 31))]
4101 "* return output_mul_insn (0, insn);"
4102 [(set_attr "type" "milli")
4103 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4106 [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
4107 (clobber (match_operand:SI 0 "register_operand" "=a"))
4108 (clobber (reg:SI 26))
4109 (clobber (reg:SI 25))
4110 (clobber (reg:SI 2))]
4112 "* return output_mul_insn (0, insn);"
4113 [(set_attr "type" "milli")
4114 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4116 (define_expand "muldi3"
4117 [(set (match_operand:DI 0 "register_operand" "")
4118 (mult:DI (match_operand:DI 1 "register_operand" "")
4119 (match_operand:DI 2 "register_operand" "")))]
4120 "TARGET_64BIT && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT"
4123 rtx low_product = gen_reg_rtx (DImode);
4124 rtx cross_product1 = gen_reg_rtx (DImode);
4125 rtx cross_product2 = gen_reg_rtx (DImode);
4126 rtx cross_scratch = gen_reg_rtx (DImode);
4127 rtx cross_product = gen_reg_rtx (DImode);
4128 rtx op1l, op1r, op2l, op2r;
4129 rtx op1shifted, op2shifted;
4131 op1shifted = gen_reg_rtx (DImode);
4132 op2shifted = gen_reg_rtx (DImode);
4133 op1l = gen_reg_rtx (SImode);
4134 op1r = gen_reg_rtx (SImode);
4135 op2l = gen_reg_rtx (SImode);
4136 op2r = gen_reg_rtx (SImode);
4138 emit_move_insn (op1shifted, gen_rtx_LSHIFTRT (DImode, operands[1],
4140 emit_move_insn (op2shifted, gen_rtx_LSHIFTRT (DImode, operands[2],
4142 op1r = gen_rtx_SUBREG (SImode, operands[1], 4);
4143 op2r = gen_rtx_SUBREG (SImode, operands[2], 4);
4144 op1l = gen_rtx_SUBREG (SImode, op1shifted, 4);
4145 op2l = gen_rtx_SUBREG (SImode, op2shifted, 4);
4147 /* Emit multiplies for the cross products. */
4148 emit_insn (gen_umulsidi3 (cross_product1, op2r, op1l));
4149 emit_insn (gen_umulsidi3 (cross_product2, op2l, op1r));
4151 /* Emit a multiply for the low sub-word. */
4152 emit_insn (gen_umulsidi3 (low_product, copy_rtx (op2r), copy_rtx (op1r)));
4154 /* Sum the cross products and shift them into proper position. */
4155 emit_insn (gen_adddi3 (cross_scratch, cross_product1, cross_product2));
4156 emit_insn (gen_ashldi3 (cross_product, cross_scratch, GEN_INT (32)));
4158 /* Add the cross product to the low product and store the result
4159 into the output operand . */
4160 emit_insn (gen_adddi3 (operands[0], cross_product, low_product));
4164 ;;; Division and mod.
4165 (define_expand "divsi3"
4166 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4167 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4168 (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
4169 (clobber (match_dup 3))
4170 (clobber (match_dup 4))
4171 (clobber (reg:SI 26))
4172 (clobber (reg:SI 25))
4173 (clobber (match_dup 5))])
4174 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4178 operands[3] = gen_reg_rtx (SImode);
4181 operands[5] = gen_rtx_REG (SImode, 2);
4182 operands[4] = operands[5];
4186 operands[5] = gen_rtx_REG (SImode, 31);
4187 operands[4] = gen_reg_rtx (SImode);
4189 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 0))
4195 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4196 (clobber (match_operand:SI 1 "register_operand" "=a"))
4197 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4198 (clobber (reg:SI 26))
4199 (clobber (reg:SI 25))
4200 (clobber (reg:SI 31))]
4203 return output_div_insn (operands, 0, insn);"
4204 [(set_attr "type" "milli")
4205 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4209 (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4210 (clobber (match_operand:SI 1 "register_operand" "=a"))
4211 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4212 (clobber (reg:SI 26))
4213 (clobber (reg:SI 25))
4214 (clobber (reg:SI 2))]
4217 return output_div_insn (operands, 0, insn);"
4218 [(set_attr "type" "milli")
4219 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4221 (define_expand "udivsi3"
4222 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4223 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4224 (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
4225 (clobber (match_dup 3))
4226 (clobber (match_dup 4))
4227 (clobber (reg:SI 26))
4228 (clobber (reg:SI 25))
4229 (clobber (match_dup 5))])
4230 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4234 operands[3] = gen_reg_rtx (SImode);
4238 operands[5] = gen_rtx_REG (SImode, 2);
4239 operands[4] = operands[5];
4243 operands[5] = gen_rtx_REG (SImode, 31);
4244 operands[4] = gen_reg_rtx (SImode);
4246 if (GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const (operands, 1))
4252 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4253 (clobber (match_operand:SI 1 "register_operand" "=a"))
4254 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4255 (clobber (reg:SI 26))
4256 (clobber (reg:SI 25))
4257 (clobber (reg:SI 31))]
4260 return output_div_insn (operands, 1, insn);"
4261 [(set_attr "type" "milli")
4262 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4266 (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
4267 (clobber (match_operand:SI 1 "register_operand" "=a"))
4268 (clobber (match_operand:SI 2 "register_operand" "=&r"))
4269 (clobber (reg:SI 26))
4270 (clobber (reg:SI 25))
4271 (clobber (reg:SI 2))]
4274 return output_div_insn (operands, 1, insn);"
4275 [(set_attr "type" "milli")
4276 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4278 (define_expand "modsi3"
4279 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4280 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4281 (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4282 (clobber (match_dup 3))
4283 (clobber (match_dup 4))
4284 (clobber (reg:SI 26))
4285 (clobber (reg:SI 25))
4286 (clobber (match_dup 5))])
4287 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4293 operands[5] = gen_rtx_REG (SImode, 2);
4294 operands[4] = operands[5];
4298 operands[5] = gen_rtx_REG (SImode, 31);
4299 operands[4] = gen_reg_rtx (SImode);
4301 operands[3] = gen_reg_rtx (SImode);
4305 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4306 (clobber (match_operand:SI 0 "register_operand" "=a"))
4307 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4308 (clobber (reg:SI 26))
4309 (clobber (reg:SI 25))
4310 (clobber (reg:SI 31))]
4313 return output_mod_insn (0, insn);"
4314 [(set_attr "type" "milli")
4315 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4318 [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
4319 (clobber (match_operand:SI 0 "register_operand" "=a"))
4320 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4321 (clobber (reg:SI 26))
4322 (clobber (reg:SI 25))
4323 (clobber (reg:SI 2))]
4326 return output_mod_insn (0, insn);"
4327 [(set_attr "type" "milli")
4328 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4330 (define_expand "umodsi3"
4331 [(set (reg:SI 26) (match_operand:SI 1 "move_operand" ""))
4332 (set (reg:SI 25) (match_operand:SI 2 "move_operand" ""))
4333 (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4334 (clobber (match_dup 3))
4335 (clobber (match_dup 4))
4336 (clobber (reg:SI 26))
4337 (clobber (reg:SI 25))
4338 (clobber (match_dup 5))])
4339 (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
4345 operands[5] = gen_rtx_REG (SImode, 2);
4346 operands[4] = operands[5];
4350 operands[5] = gen_rtx_REG (SImode, 31);
4351 operands[4] = gen_reg_rtx (SImode);
4353 operands[3] = gen_reg_rtx (SImode);
4357 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4358 (clobber (match_operand:SI 0 "register_operand" "=a"))
4359 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4360 (clobber (reg:SI 26))
4361 (clobber (reg:SI 25))
4362 (clobber (reg:SI 31))]
4365 return output_mod_insn (1, insn);"
4366 [(set_attr "type" "milli")
4367 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4370 [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
4371 (clobber (match_operand:SI 0 "register_operand" "=a"))
4372 (clobber (match_operand:SI 1 "register_operand" "=&r"))
4373 (clobber (reg:SI 26))
4374 (clobber (reg:SI 25))
4375 (clobber (reg:SI 2))]
4378 return output_mod_insn (1, insn);"
4379 [(set_attr "type" "milli")
4380 (set (attr "length") (symbol_ref "attr_length_millicode_call (insn)"))])
4382 ;;- and instructions
4383 ;; We define DImode `and` so with DImode `not` we can get
4384 ;; DImode `andn`. Other combinations are possible.
4386 (define_expand "anddi3"
4387 [(set (match_operand:DI 0 "register_operand" "")
4388 (and:DI (match_operand:DI 1 "arith_double_operand" "")
4389 (match_operand:DI 2 "arith_double_operand" "")))]
4393 if (! register_operand (operands[1], DImode)
4394 || ! register_operand (operands[2], DImode))
4395 /* Let GCC break this into word-at-a-time operations. */
4400 [(set (match_operand:DI 0 "register_operand" "=r")
4401 (and:DI (match_operand:DI 1 "register_operand" "%r")
4402 (match_operand:DI 2 "register_operand" "r")))]
4404 "and %1,%2,%0\;and %R1,%R2,%R0"
4405 [(set_attr "type" "binary")
4406 (set_attr "length" "8")])
4409 [(set (match_operand:DI 0 "register_operand" "=r,r")
4410 (and:DI (match_operand:DI 1 "register_operand" "%?r,0")
4411 (match_operand:DI 2 "and_operand" "rO,P")))]
4413 "* return output_64bit_and (operands); "
4414 [(set_attr "type" "binary")
4415 (set_attr "length" "4")])
4417 ; The ? for op1 makes reload prefer zdepi instead of loading a huge
4418 ; constant with ldil;ldo.
4419 (define_insn "andsi3"
4420 [(set (match_operand:SI 0 "register_operand" "=r,r")
4421 (and:SI (match_operand:SI 1 "register_operand" "%?r,0")
4422 (match_operand:SI 2 "and_operand" "rO,P")))]
4424 "* return output_and (operands); "
4425 [(set_attr "type" "binary,shift")
4426 (set_attr "length" "4,4")])
4429 [(set (match_operand:DI 0 "register_operand" "=r")
4430 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4431 (match_operand:DI 2 "register_operand" "r")))]
4433 "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
4434 [(set_attr "type" "binary")
4435 (set_attr "length" "8")])
4438 [(set (match_operand:DI 0 "register_operand" "=r")
4439 (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
4440 (match_operand:DI 2 "register_operand" "r")))]
4443 [(set_attr "type" "binary")
4444 (set_attr "length" "4")])
4447 [(set (match_operand:SI 0 "register_operand" "=r")
4448 (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
4449 (match_operand:SI 2 "register_operand" "r")))]
4452 [(set_attr "type" "binary")
4453 (set_attr "length" "4")])
4455 (define_expand "iordi3"
4456 [(set (match_operand:DI 0 "register_operand" "")
4457 (ior:DI (match_operand:DI 1 "arith_double_operand" "")
4458 (match_operand:DI 2 "arith_double_operand" "")))]
4462 if (! register_operand (operands[1], DImode)
4463 || ! register_operand (operands[2], DImode))
4464 /* Let GCC break this into word-at-a-time operations. */
4469 [(set (match_operand:DI 0 "register_operand" "=r")
4470 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4471 (match_operand:DI 2 "register_operand" "r")))]
4473 "or %1,%2,%0\;or %R1,%R2,%R0"
4474 [(set_attr "type" "binary")
4475 (set_attr "length" "8")])
4478 [(set (match_operand:DI 0 "register_operand" "=r,r")
4479 (ior:DI (match_operand:DI 1 "register_operand" "0,0")
4480 (match_operand:DI 2 "ior_operand" "M,i")))]
4482 "* return output_64bit_ior (operands); "
4483 [(set_attr "type" "binary,shift")
4484 (set_attr "length" "4,4")])
4487 [(set (match_operand:DI 0 "register_operand" "=r")
4488 (ior:DI (match_operand:DI 1 "register_operand" "%r")
4489 (match_operand:DI 2 "register_operand" "r")))]
4492 [(set_attr "type" "binary")
4493 (set_attr "length" "4")])
4495 ;; Need a define_expand because we've run out of CONST_OK... characters.
4496 (define_expand "iorsi3"
4497 [(set (match_operand:SI 0 "register_operand" "")
4498 (ior:SI (match_operand:SI 1 "register_operand" "")
4499 (match_operand:SI 2 "arith32_operand" "")))]
4503 if (! (ior_operand (operands[2], SImode)
4504 || register_operand (operands[2], SImode)))
4505 operands[2] = force_reg (SImode, operands[2]);
4509 [(set (match_operand:SI 0 "register_operand" "=r,r")
4510 (ior:SI (match_operand:SI 1 "register_operand" "0,0")
4511 (match_operand:SI 2 "ior_operand" "M,i")))]
4513 "* return output_ior (operands); "
4514 [(set_attr "type" "binary,shift")
4515 (set_attr "length" "4,4")])
4518 [(set (match_operand:SI 0 "register_operand" "=r")
4519 (ior:SI (match_operand:SI 1 "register_operand" "%r")
4520 (match_operand:SI 2 "register_operand" "r")))]
4523 [(set_attr "type" "binary")
4524 (set_attr "length" "4")])
4526 (define_expand "xordi3"
4527 [(set (match_operand:DI 0 "register_operand" "")
4528 (xor:DI (match_operand:DI 1 "arith_double_operand" "")
4529 (match_operand:DI 2 "arith_double_operand" "")))]
4533 if (! register_operand (operands[1], DImode)
4534 || ! register_operand (operands[2], DImode))
4535 /* Let GCC break this into word-at-a-time operations. */
4540 [(set (match_operand:DI 0 "register_operand" "=r")
4541 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4542 (match_operand:DI 2 "register_operand" "r")))]
4544 "xor %1,%2,%0\;xor %R1,%R2,%R0"
4545 [(set_attr "type" "binary")
4546 (set_attr "length" "8")])
4549 [(set (match_operand:DI 0 "register_operand" "=r")
4550 (xor:DI (match_operand:DI 1 "register_operand" "%r")
4551 (match_operand:DI 2 "register_operand" "r")))]
4554 [(set_attr "type" "binary")
4555 (set_attr "length" "4")])
4557 (define_insn "xorsi3"
4558 [(set (match_operand:SI 0 "register_operand" "=r")
4559 (xor:SI (match_operand:SI 1 "register_operand" "%r")
4560 (match_operand:SI 2 "register_operand" "r")))]
4563 [(set_attr "type" "binary")
4564 (set_attr "length" "4")])
4566 (define_expand "negdi2"
4567 [(set (match_operand:DI 0 "register_operand" "")
4568 (neg:DI (match_operand:DI 1 "register_operand" "")))]
4573 [(set (match_operand:DI 0 "register_operand" "=r")
4574 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4576 "sub %%r0,%R1,%R0\;{subb|sub,b} %%r0,%1,%0"
4577 [(set_attr "type" "unary")
4578 (set_attr "length" "8")])
4581 [(set (match_operand:DI 0 "register_operand" "=r")
4582 (neg:DI (match_operand:DI 1 "register_operand" "r")))]
4585 [(set_attr "type" "unary")
4586 (set_attr "length" "4")])
4588 (define_insn "negsi2"
4589 [(set (match_operand:SI 0 "register_operand" "=r")
4590 (neg:SI (match_operand:SI 1 "register_operand" "r")))]
4593 [(set_attr "type" "unary")
4594 (set_attr "length" "4")])
4596 (define_expand "one_cmpldi2"
4597 [(set (match_operand:DI 0 "register_operand" "")
4598 (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
4602 if (! register_operand (operands[1], DImode))
4607 [(set (match_operand:DI 0 "register_operand" "=r")
4608 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4610 "uaddcm %%r0,%1,%0\;uaddcm %%r0,%R1,%R0"
4611 [(set_attr "type" "unary")
4612 (set_attr "length" "8")])
4615 [(set (match_operand:DI 0 "register_operand" "=r")
4616 (not:DI (match_operand:DI 1 "register_operand" "r")))]
4619 [(set_attr "type" "unary")
4620 (set_attr "length" "4")])
4622 (define_insn "one_cmplsi2"
4623 [(set (match_operand:SI 0 "register_operand" "=r")
4624 (not:SI (match_operand:SI 1 "register_operand" "r")))]
4627 [(set_attr "type" "unary")
4628 (set_attr "length" "4")])
4630 ;; Floating point arithmetic instructions.
4632 (define_insn "adddf3"
4633 [(set (match_operand:DF 0 "register_operand" "=f")
4634 (plus:DF (match_operand:DF 1 "register_operand" "f")
4635 (match_operand:DF 2 "register_operand" "f")))]
4636 "! TARGET_SOFT_FLOAT"
4638 [(set_attr "type" "fpalu")
4639 (set_attr "pa_combine_type" "faddsub")
4640 (set_attr "length" "4")])
4642 (define_insn "addsf3"
4643 [(set (match_operand:SF 0 "register_operand" "=f")
4644 (plus:SF (match_operand:SF 1 "register_operand" "f")
4645 (match_operand:SF 2 "register_operand" "f")))]
4646 "! TARGET_SOFT_FLOAT"
4648 [(set_attr "type" "fpalu")
4649 (set_attr "pa_combine_type" "faddsub")
4650 (set_attr "length" "4")])
4652 (define_insn "subdf3"
4653 [(set (match_operand:DF 0 "register_operand" "=f")
4654 (minus:DF (match_operand:DF 1 "register_operand" "f")
4655 (match_operand:DF 2 "register_operand" "f")))]
4656 "! TARGET_SOFT_FLOAT"
4658 [(set_attr "type" "fpalu")
4659 (set_attr "pa_combine_type" "faddsub")
4660 (set_attr "length" "4")])
4662 (define_insn "subsf3"
4663 [(set (match_operand:SF 0 "register_operand" "=f")
4664 (minus:SF (match_operand:SF 1 "register_operand" "f")
4665 (match_operand:SF 2 "register_operand" "f")))]
4666 "! TARGET_SOFT_FLOAT"
4668 [(set_attr "type" "fpalu")
4669 (set_attr "pa_combine_type" "faddsub")
4670 (set_attr "length" "4")])
4672 (define_insn "muldf3"
4673 [(set (match_operand:DF 0 "register_operand" "=f")
4674 (mult:DF (match_operand:DF 1 "register_operand" "f")
4675 (match_operand:DF 2 "register_operand" "f")))]
4676 "! TARGET_SOFT_FLOAT"
4678 [(set_attr "type" "fpmuldbl")
4679 (set_attr "pa_combine_type" "fmpy")
4680 (set_attr "length" "4")])
4682 (define_insn "mulsf3"
4683 [(set (match_operand:SF 0 "register_operand" "=f")
4684 (mult:SF (match_operand:SF 1 "register_operand" "f")
4685 (match_operand:SF 2 "register_operand" "f")))]
4686 "! TARGET_SOFT_FLOAT"
4688 [(set_attr "type" "fpmulsgl")
4689 (set_attr "pa_combine_type" "fmpy")
4690 (set_attr "length" "4")])
4692 (define_insn "divdf3"
4693 [(set (match_operand:DF 0 "register_operand" "=f")
4694 (div:DF (match_operand:DF 1 "register_operand" "f")
4695 (match_operand:DF 2 "register_operand" "f")))]
4696 "! TARGET_SOFT_FLOAT"
4698 [(set_attr "type" "fpdivdbl")
4699 (set_attr "length" "4")])
4701 (define_insn "divsf3"
4702 [(set (match_operand:SF 0 "register_operand" "=f")
4703 (div:SF (match_operand:SF 1 "register_operand" "f")
4704 (match_operand:SF 2 "register_operand" "f")))]
4705 "! TARGET_SOFT_FLOAT"
4707 [(set_attr "type" "fpdivsgl")
4708 (set_attr "length" "4")])
4710 ;; Processors prior to PA 2.0 don't have a fneg instruction. Fast
4711 ;; negation can be done by subtracting from plus zero. However, this
4712 ;; violates the IEEE standard when negating plus and minus zero.
4713 (define_expand "negdf2"
4714 [(parallel [(set (match_operand:DF 0 "register_operand" "")
4715 (neg:DF (match_operand:DF 1 "register_operand" "")))
4716 (use (match_dup 2))])]
4717 "! TARGET_SOFT_FLOAT"
4719 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4720 emit_insn (gen_negdf2_fast (operands[0], operands[1]));
4723 operands[2] = force_reg (DFmode,
4724 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, DFmode));
4725 emit_insn (gen_muldf3 (operands[0], operands[1], operands[2]));
4730 (define_insn "negdf2_fast"
4731 [(set (match_operand:DF 0 "register_operand" "=f")
4732 (neg:DF (match_operand:DF 1 "register_operand" "f")))]
4733 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4737 return \"fneg,dbl %1,%0\";
4739 return \"fsub,dbl %%fr0,%1,%0\";
4741 [(set_attr "type" "fpalu")
4742 (set_attr "length" "4")])
4744 (define_expand "negsf2"
4745 [(parallel [(set (match_operand:SF 0 "register_operand" "")
4746 (neg:SF (match_operand:SF 1 "register_operand" "")))
4747 (use (match_dup 2))])]
4748 "! TARGET_SOFT_FLOAT"
4750 if (TARGET_PA_20 || flag_unsafe_math_optimizations)
4751 emit_insn (gen_negsf2_fast (operands[0], operands[1]));
4754 operands[2] = force_reg (SFmode,
4755 CONST_DOUBLE_FROM_REAL_VALUE (dconstm1, SFmode));
4756 emit_insn (gen_mulsf3 (operands[0], operands[1], operands[2]));
4761 (define_insn "negsf2_fast"
4762 [(set (match_operand:SF 0 "register_operand" "=f")
4763 (neg:SF (match_operand:SF 1 "register_operand" "f")))]
4764 "! TARGET_SOFT_FLOAT && (TARGET_PA_20 || flag_unsafe_math_optimizations)"
4768 return \"fneg,sgl %1,%0\";
4770 return \"fsub,sgl %%fr0,%1,%0\";
4772 [(set_attr "type" "fpalu")
4773 (set_attr "length" "4")])
4775 (define_insn "absdf2"
4776 [(set (match_operand:DF 0 "register_operand" "=f")
4777 (abs:DF (match_operand:DF 1 "register_operand" "f")))]
4778 "! TARGET_SOFT_FLOAT"
4780 [(set_attr "type" "fpalu")
4781 (set_attr "length" "4")])
4783 (define_insn "abssf2"
4784 [(set (match_operand:SF 0 "register_operand" "=f")
4785 (abs:SF (match_operand:SF 1 "register_operand" "f")))]
4786 "! TARGET_SOFT_FLOAT"
4788 [(set_attr "type" "fpalu")
4789 (set_attr "length" "4")])
4791 (define_insn "sqrtdf2"
4792 [(set (match_operand:DF 0 "register_operand" "=f")
4793 (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
4794 "! TARGET_SOFT_FLOAT"
4796 [(set_attr "type" "fpsqrtdbl")
4797 (set_attr "length" "4")])
4799 (define_insn "sqrtsf2"
4800 [(set (match_operand:SF 0 "register_operand" "=f")
4801 (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
4802 "! TARGET_SOFT_FLOAT"
4804 [(set_attr "type" "fpsqrtsgl")
4805 (set_attr "length" "4")])
4807 ;; PA 2.0 floating point instructions
4811 [(set (match_operand:DF 0 "register_operand" "=f")
4812 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4813 (match_operand:DF 2 "register_operand" "f"))
4814 (match_operand:DF 3 "register_operand" "f")))]
4815 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4816 "fmpyfadd,dbl %1,%2,%3,%0"
4817 [(set_attr "type" "fpmuldbl")
4818 (set_attr "length" "4")])
4821 [(set (match_operand:DF 0 "register_operand" "=f")
4822 (plus:DF (match_operand:DF 1 "register_operand" "f")
4823 (mult:DF (match_operand:DF 2 "register_operand" "f")
4824 (match_operand:DF 3 "register_operand" "f"))))]
4825 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4826 "fmpyfadd,dbl %2,%3,%1,%0"
4827 [(set_attr "type" "fpmuldbl")
4828 (set_attr "length" "4")])
4831 [(set (match_operand:SF 0 "register_operand" "=f")
4832 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4833 (match_operand:SF 2 "register_operand" "f"))
4834 (match_operand:SF 3 "register_operand" "f")))]
4835 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4836 "fmpyfadd,sgl %1,%2,%3,%0"
4837 [(set_attr "type" "fpmulsgl")
4838 (set_attr "length" "4")])
4841 [(set (match_operand:SF 0 "register_operand" "=f")
4842 (plus:SF (match_operand:SF 1 "register_operand" "f")
4843 (mult:SF (match_operand:SF 2 "register_operand" "f")
4844 (match_operand:SF 3 "register_operand" "f"))))]
4845 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4846 "fmpyfadd,sgl %2,%3,%1,%0"
4847 [(set_attr "type" "fpmulsgl")
4848 (set_attr "length" "4")])
4850 ; fmpynfadd patterns
4852 [(set (match_operand:DF 0 "register_operand" "=f")
4853 (minus:DF (match_operand:DF 1 "register_operand" "f")
4854 (mult:DF (match_operand:DF 2 "register_operand" "f")
4855 (match_operand:DF 3 "register_operand" "f"))))]
4856 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4857 "fmpynfadd,dbl %2,%3,%1,%0"
4858 [(set_attr "type" "fpmuldbl")
4859 (set_attr "length" "4")])
4862 [(set (match_operand:SF 0 "register_operand" "=f")
4863 (minus:SF (match_operand:SF 1 "register_operand" "f")
4864 (mult:SF (match_operand:SF 2 "register_operand" "f")
4865 (match_operand:SF 3 "register_operand" "f"))))]
4866 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4867 "fmpynfadd,sgl %2,%3,%1,%0"
4868 [(set_attr "type" "fpmulsgl")
4869 (set_attr "length" "4")])
4873 [(set (match_operand:DF 0 "register_operand" "=f")
4874 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))]
4875 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4877 [(set_attr "type" "fpalu")
4878 (set_attr "length" "4")])
4881 [(set (match_operand:SF 0 "register_operand" "=f")
4882 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))]
4883 "TARGET_PA_20 && ! TARGET_SOFT_FLOAT"
4885 [(set_attr "type" "fpalu")
4886 (set_attr "length" "4")])
4888 ;; Generating a fused multiply sequence is a win for this case as it will
4889 ;; reduce the latency for the fused case without impacting the plain
4892 ;; Similar possibilities exist for fnegabs, shadd and other insns which
4893 ;; perform two operations with the result of the first feeding the second.
4895 [(set (match_operand:DF 0 "register_operand" "=f")
4896 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4897 (match_operand:DF 2 "register_operand" "f"))
4898 (match_operand:DF 3 "register_operand" "f")))
4899 (set (match_operand:DF 4 "register_operand" "=&f")
4900 (mult:DF (match_dup 1) (match_dup 2)))]
4901 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4902 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4903 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4905 [(set_attr "type" "fpmuldbl")
4906 (set_attr "length" "8")])
4908 ;; We want to split this up during scheduling since we want both insns
4909 ;; to schedule independently.
4911 [(set (match_operand:DF 0 "register_operand" "")
4912 (plus:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4913 (match_operand:DF 2 "register_operand" ""))
4914 (match_operand:DF 3 "register_operand" "")))
4915 (set (match_operand:DF 4 "register_operand" "")
4916 (mult:DF (match_dup 1) (match_dup 2)))]
4917 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4918 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
4919 (set (match_dup 0) (plus:DF (mult:DF (match_dup 1) (match_dup 2))
4924 [(set (match_operand:SF 0 "register_operand" "=f")
4925 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4926 (match_operand:SF 2 "register_operand" "f"))
4927 (match_operand:SF 3 "register_operand" "f")))
4928 (set (match_operand:SF 4 "register_operand" "=&f")
4929 (mult:SF (match_dup 1) (match_dup 2)))]
4930 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4931 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
4932 || reg_overlap_mentioned_p (operands[4], operands[2])))"
4934 [(set_attr "type" "fpmuldbl")
4935 (set_attr "length" "8")])
4937 ;; We want to split this up during scheduling since we want both insns
4938 ;; to schedule independently.
4940 [(set (match_operand:SF 0 "register_operand" "")
4941 (plus:SF (mult:SF (match_operand:SF 1 "register_operand" "")
4942 (match_operand:SF 2 "register_operand" ""))
4943 (match_operand:SF 3 "register_operand" "")))
4944 (set (match_operand:SF 4 "register_operand" "")
4945 (mult:SF (match_dup 1) (match_dup 2)))]
4946 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4947 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
4948 (set (match_dup 0) (plus:SF (mult:SF (match_dup 1) (match_dup 2))
4952 ;; Negating a multiply can be faked by adding zero in a fused multiply-add
4955 [(set (match_operand:DF 0 "register_operand" "=f")
4956 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4957 (match_operand:DF 2 "register_operand" "f"))))]
4958 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4959 "fmpynfadd,dbl %1,%2,%%fr0,%0"
4960 [(set_attr "type" "fpmuldbl")
4961 (set_attr "length" "4")])
4964 [(set (match_operand:SF 0 "register_operand" "=f")
4965 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4966 (match_operand:SF 2 "register_operand" "f"))))]
4967 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4968 "fmpynfadd,sgl %1,%2,%%fr0,%0"
4969 [(set_attr "type" "fpmuldbl")
4970 (set_attr "length" "4")])
4973 [(set (match_operand:DF 0 "register_operand" "=f")
4974 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
4975 (match_operand:DF 2 "register_operand" "f"))))
4976 (set (match_operand:DF 3 "register_operand" "=&f")
4977 (mult:DF (match_dup 1) (match_dup 2)))]
4978 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
4979 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
4980 || reg_overlap_mentioned_p (operands[3], operands[2])))"
4982 [(set_attr "type" "fpmuldbl")
4983 (set_attr "length" "8")])
4986 [(set (match_operand:DF 0 "register_operand" "")
4987 (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
4988 (match_operand:DF 2 "register_operand" ""))))
4989 (set (match_operand:DF 3 "register_operand" "")
4990 (mult:DF (match_dup 1) (match_dup 2)))]
4991 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
4992 [(set (match_dup 3) (mult:DF (match_dup 1) (match_dup 2)))
4993 (set (match_dup 0) (neg:DF (mult:DF (match_dup 1) (match_dup 2))))]
4997 [(set (match_operand:SF 0 "register_operand" "=f")
4998 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
4999 (match_operand:SF 2 "register_operand" "f"))))
5000 (set (match_operand:SF 3 "register_operand" "=&f")
5001 (mult:SF (match_dup 1) (match_dup 2)))]
5002 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5003 && ! (reg_overlap_mentioned_p (operands[3], operands[1])
5004 || reg_overlap_mentioned_p (operands[3], operands[2])))"
5006 [(set_attr "type" "fpmuldbl")
5007 (set_attr "length" "8")])
5010 [(set (match_operand:SF 0 "register_operand" "")
5011 (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5012 (match_operand:SF 2 "register_operand" ""))))
5013 (set (match_operand:SF 3 "register_operand" "")
5014 (mult:SF (match_dup 1) (match_dup 2)))]
5015 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5016 [(set (match_dup 3) (mult:SF (match_dup 1) (match_dup 2)))
5017 (set (match_dup 0) (neg:SF (mult:SF (match_dup 1) (match_dup 2))))]
5020 ;; Now fused multiplies with the result of the multiply negated.
5022 [(set (match_operand:DF 0 "register_operand" "=f")
5023 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5024 (match_operand:DF 2 "register_operand" "f")))
5025 (match_operand:DF 3 "register_operand" "f")))]
5026 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5027 "fmpynfadd,dbl %1,%2,%3,%0"
5028 [(set_attr "type" "fpmuldbl")
5029 (set_attr "length" "4")])
5032 [(set (match_operand:SF 0 "register_operand" "=f")
5033 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5034 (match_operand:SF 2 "register_operand" "f")))
5035 (match_operand:SF 3 "register_operand" "f")))]
5036 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5037 "fmpynfadd,sgl %1,%2,%3,%0"
5038 [(set_attr "type" "fpmuldbl")
5039 (set_attr "length" "4")])
5042 [(set (match_operand:DF 0 "register_operand" "=f")
5043 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "f")
5044 (match_operand:DF 2 "register_operand" "f")))
5045 (match_operand:DF 3 "register_operand" "f")))
5046 (set (match_operand:DF 4 "register_operand" "=&f")
5047 (mult:DF (match_dup 1) (match_dup 2)))]
5048 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5049 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5050 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5052 [(set_attr "type" "fpmuldbl")
5053 (set_attr "length" "8")])
5056 [(set (match_operand:DF 0 "register_operand" "")
5057 (plus:DF (neg:DF (mult:DF (match_operand:DF 1 "register_operand" "")
5058 (match_operand:DF 2 "register_operand" "")))
5059 (match_operand:DF 3 "register_operand" "")))
5060 (set (match_operand:DF 4 "register_operand" "")
5061 (mult:DF (match_dup 1) (match_dup 2)))]
5062 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5063 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5064 (set (match_dup 0) (plus:DF (neg:DF (mult:DF (match_dup 1) (match_dup 2)))
5069 [(set (match_operand:SF 0 "register_operand" "=f")
5070 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "f")
5071 (match_operand:SF 2 "register_operand" "f")))
5072 (match_operand:SF 3 "register_operand" "f")))
5073 (set (match_operand:SF 4 "register_operand" "=&f")
5074 (mult:SF (match_dup 1) (match_dup 2)))]
5075 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5076 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5077 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5079 [(set_attr "type" "fpmuldbl")
5080 (set_attr "length" "8")])
5083 [(set (match_operand:SF 0 "register_operand" "")
5084 (plus:SF (neg:SF (mult:SF (match_operand:SF 1 "register_operand" "")
5085 (match_operand:SF 2 "register_operand" "")))
5086 (match_operand:SF 3 "register_operand" "")))
5087 (set (match_operand:SF 4 "register_operand" "")
5088 (mult:SF (match_dup 1) (match_dup 2)))]
5089 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5090 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5091 (set (match_dup 0) (plus:SF (neg:SF (mult:SF (match_dup 1) (match_dup 2)))
5096 [(set (match_operand:DF 0 "register_operand" "=f")
5097 (minus:DF (match_operand:DF 3 "register_operand" "f")
5098 (mult:DF (match_operand:DF 1 "register_operand" "f")
5099 (match_operand:DF 2 "register_operand" "f"))))
5100 (set (match_operand:DF 4 "register_operand" "=&f")
5101 (mult:DF (match_dup 1) (match_dup 2)))]
5102 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5103 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5104 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5106 [(set_attr "type" "fpmuldbl")
5107 (set_attr "length" "8")])
5110 [(set (match_operand:DF 0 "register_operand" "")
5111 (minus:DF (match_operand:DF 3 "register_operand" "")
5112 (mult:DF (match_operand:DF 1 "register_operand" "")
5113 (match_operand:DF 2 "register_operand" ""))))
5114 (set (match_operand:DF 4 "register_operand" "")
5115 (mult:DF (match_dup 1) (match_dup 2)))]
5116 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5117 [(set (match_dup 4) (mult:DF (match_dup 1) (match_dup 2)))
5118 (set (match_dup 0) (minus:DF (match_dup 3)
5119 (mult:DF (match_dup 1) (match_dup 2))))]
5123 [(set (match_operand:SF 0 "register_operand" "=f")
5124 (minus:SF (match_operand:SF 3 "register_operand" "f")
5125 (mult:SF (match_operand:SF 1 "register_operand" "f")
5126 (match_operand:SF 2 "register_operand" "f"))))
5127 (set (match_operand:SF 4 "register_operand" "=&f")
5128 (mult:SF (match_dup 1) (match_dup 2)))]
5129 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5130 && ! (reg_overlap_mentioned_p (operands[4], operands[1])
5131 || reg_overlap_mentioned_p (operands[4], operands[2])))"
5133 [(set_attr "type" "fpmuldbl")
5134 (set_attr "length" "8")])
5137 [(set (match_operand:SF 0 "register_operand" "")
5138 (minus:SF (match_operand:SF 3 "register_operand" "")
5139 (mult:SF (match_operand:SF 1 "register_operand" "")
5140 (match_operand:SF 2 "register_operand" ""))))
5141 (set (match_operand:SF 4 "register_operand" "")
5142 (mult:SF (match_dup 1) (match_dup 2)))]
5143 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5144 [(set (match_dup 4) (mult:SF (match_dup 1) (match_dup 2)))
5145 (set (match_dup 0) (minus:SF (match_dup 3)
5146 (mult:SF (match_dup 1) (match_dup 2))))]
5150 [(set (match_operand:DF 0 "register_operand" "=f")
5151 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" "f"))))
5152 (set (match_operand:DF 2 "register_operand" "=&f") (abs:DF (match_dup 1)))]
5153 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5154 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5156 [(set_attr "type" "fpalu")
5157 (set_attr "length" "8")])
5160 [(set (match_operand:DF 0 "register_operand" "")
5161 (neg:DF (abs:DF (match_operand:DF 1 "register_operand" ""))))
5162 (set (match_operand:DF 2 "register_operand" "") (abs:DF (match_dup 1)))]
5163 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5164 [(set (match_dup 2) (abs:DF (match_dup 1)))
5165 (set (match_dup 0) (neg:DF (abs:DF (match_dup 1))))]
5169 [(set (match_operand:SF 0 "register_operand" "=f")
5170 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" "f"))))
5171 (set (match_operand:SF 2 "register_operand" "=&f") (abs:SF (match_dup 1)))]
5172 "(! TARGET_SOFT_FLOAT && TARGET_PA_20
5173 && ! reg_overlap_mentioned_p (operands[2], operands[1]))"
5175 [(set_attr "type" "fpalu")
5176 (set_attr "length" "8")])
5179 [(set (match_operand:SF 0 "register_operand" "")
5180 (neg:SF (abs:SF (match_operand:SF 1 "register_operand" ""))))
5181 (set (match_operand:SF 2 "register_operand" "") (abs:SF (match_dup 1)))]
5182 "! TARGET_SOFT_FLOAT && TARGET_PA_20"
5183 [(set (match_dup 2) (abs:SF (match_dup 1)))
5184 (set (match_dup 0) (neg:SF (abs:SF (match_dup 1))))]
5187 ;;- Shift instructions
5189 ;; Optimized special case of shifting.
5192 [(set (match_operand:SI 0 "register_operand" "=r")
5193 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5197 [(set_attr "type" "load")
5198 (set_attr "length" "4")])
5201 [(set (match_operand:SI 0 "register_operand" "=r")
5202 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
5206 [(set_attr "type" "load")
5207 (set_attr "length" "4")])
5210 [(set (match_operand:SI 0 "register_operand" "=r")
5211 (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
5212 (match_operand:SI 3 "shadd_operand" ""))
5213 (match_operand:SI 1 "register_operand" "r")))]
5215 "{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0} "
5216 [(set_attr "type" "binary")
5217 (set_attr "length" "4")])
5220 [(set (match_operand:DI 0 "register_operand" "=r")
5221 (plus:DI (mult:DI (match_operand:DI 2 "register_operand" "r")
5222 (match_operand:DI 3 "shadd_operand" ""))
5223 (match_operand:DI 1 "register_operand" "r")))]
5225 "shladd,l %2,%O3,%1,%0"
5226 [(set_attr "type" "binary")
5227 (set_attr "length" "4")])
5229 (define_expand "ashlsi3"
5230 [(set (match_operand:SI 0 "register_operand" "")
5231 (ashift:SI (match_operand:SI 1 "lhs_lshift_operand" "")
5232 (match_operand:SI 2 "arith32_operand" "")))]
5236 if (GET_CODE (operands[2]) != CONST_INT)
5238 rtx temp = gen_reg_rtx (SImode);
5239 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5240 if (GET_CODE (operands[1]) == CONST_INT)
5241 emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
5243 emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
5246 /* Make sure both inputs are not constants,
5247 there are no patterns for that. */
5248 operands[1] = force_reg (SImode, operands[1]);
5252 [(set (match_operand:SI 0 "register_operand" "=r")
5253 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5254 (match_operand:SI 2 "const_int_operand" "n")))]
5256 "{zdep|depw,z} %1,%P2,%L2,%0"
5257 [(set_attr "type" "shift")
5258 (set_attr "length" "4")])
5260 ; Match cases of op1 a CONST_INT here that zvdep_imm32 doesn't handle.
5261 ; Doing it like this makes slightly better code since reload can
5262 ; replace a register with a known value in range -16..15 with a
5263 ; constant. Ideally, we would like to merge zvdep32 and zvdep_imm32,
5264 ; but since we have no more CONST_OK... characters, that is not
5266 (define_insn "zvdep32"
5267 [(set (match_operand:SI 0 "register_operand" "=r,r")
5268 (ashift:SI (match_operand:SI 1 "arith5_operand" "r,L")
5269 (minus:SI (const_int 31)
5270 (match_operand:SI 2 "register_operand" "q,q"))))]
5273 {zvdep %1,32,%0|depw,z %1,%%sar,32,%0}
5274 {zvdepi %1,32,%0|depwi,z %1,%%sar,32,%0}"
5275 [(set_attr "type" "shift,shift")
5276 (set_attr "length" "4,4")])
5278 (define_insn "zvdep_imm32"
5279 [(set (match_operand:SI 0 "register_operand" "=r")
5280 (ashift:SI (match_operand:SI 1 "lhs_lshift_cint_operand" "")
5281 (minus:SI (const_int 31)
5282 (match_operand:SI 2 "register_operand" "q"))))]
5286 int x = INTVAL (operands[1]);
5287 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5288 operands[1] = GEN_INT ((x & 0xf) - 0x10);
5289 return \"{zvdepi %1,%2,%0|depwi,z %1,%%sar,%2,%0}\";
5291 [(set_attr "type" "shift")
5292 (set_attr "length" "4")])
5294 (define_insn "vdepi_ior"
5295 [(set (match_operand:SI 0 "register_operand" "=r")
5296 (ior:SI (ashift:SI (match_operand:SI 1 "const_int_operand" "")
5297 (minus:SI (const_int 31)
5298 (match_operand:SI 2 "register_operand" "q")))
5299 (match_operand:SI 3 "register_operand" "0")))]
5300 ; accept ...0001...1, can this be generalized?
5301 "exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5304 int x = INTVAL (operands[1]);
5305 operands[2] = GEN_INT (exact_log2 (x + 1));
5306 return \"{vdepi -1,%2,%0|depwi -1,%%sar,%2,%0}\";
5308 [(set_attr "type" "shift")
5309 (set_attr "length" "4")])
5311 (define_insn "vdepi_and"
5312 [(set (match_operand:SI 0 "register_operand" "=r")
5313 (and:SI (rotate:SI (match_operand:SI 1 "const_int_operand" "")
5314 (minus:SI (const_int 31)
5315 (match_operand:SI 2 "register_operand" "q")))
5316 (match_operand:SI 3 "register_operand" "0")))]
5317 ; this can be generalized...!
5318 "INTVAL (operands[1]) == -2"
5321 int x = INTVAL (operands[1]);
5322 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5323 return \"{vdepi 0,%2,%0|depwi 0,%%sar,%2,%0}\";
5325 [(set_attr "type" "shift")
5326 (set_attr "length" "4")])
5328 (define_expand "ashldi3"
5329 [(set (match_operand:DI 0 "register_operand" "")
5330 (ashift:DI (match_operand:DI 1 "lhs_lshift_operand" "")
5331 (match_operand:DI 2 "arith32_operand" "")))]
5335 if (GET_CODE (operands[2]) != CONST_INT)
5337 rtx temp = gen_reg_rtx (DImode);
5338 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5339 if (GET_CODE (operands[1]) == CONST_INT)
5340 emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
5342 emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
5345 /* Make sure both inputs are not constants,
5346 there are no patterns for that. */
5347 operands[1] = force_reg (DImode, operands[1]);
5351 [(set (match_operand:DI 0 "register_operand" "=r")
5352 (ashift:DI (match_operand:DI 1 "register_operand" "r")
5353 (match_operand:DI 2 "const_int_operand" "n")))]
5355 "depd,z %1,%p2,%Q2,%0"
5356 [(set_attr "type" "shift")
5357 (set_attr "length" "4")])
5359 ; Match cases of op1 a CONST_INT here that zvdep_imm64 doesn't handle.
5360 ; Doing it like this makes slightly better code since reload can
5361 ; replace a register with a known value in range -16..15 with a
5362 ; constant. Ideally, we would like to merge zvdep64 and zvdep_imm64,
5363 ; but since we have no more CONST_OK... characters, that is not
5365 (define_insn "zvdep64"
5366 [(set (match_operand:DI 0 "register_operand" "=r,r")
5367 (ashift:DI (match_operand:DI 1 "arith5_operand" "r,L")
5368 (minus:DI (const_int 63)
5369 (match_operand:DI 2 "register_operand" "q,q"))))]
5372 depd,z %1,%%sar,64,%0
5373 depdi,z %1,%%sar,64,%0"
5374 [(set_attr "type" "shift,shift")
5375 (set_attr "length" "4,4")])
5377 (define_insn "zvdep_imm64"
5378 [(set (match_operand:DI 0 "register_operand" "=r")
5379 (ashift:DI (match_operand:DI 1 "lhs_lshift_cint_operand" "")
5380 (minus:DI (const_int 63)
5381 (match_operand:DI 2 "register_operand" "q"))))]
5385 int x = INTVAL (operands[1]);
5386 operands[2] = GEN_INT (4 + exact_log2 ((x >> 4) + 1));
5387 operands[1] = GEN_INT ((x & 0x1f) - 0x20);
5388 return \"depdi,z %1,%%sar,%2,%0\";
5390 [(set_attr "type" "shift")
5391 (set_attr "length" "4")])
5394 [(set (match_operand:DI 0 "register_operand" "=r")
5395 (ior:DI (ashift:DI (match_operand:DI 1 "const_int_operand" "")
5396 (minus:DI (const_int 63)
5397 (match_operand:DI 2 "register_operand" "q")))
5398 (match_operand:DI 3 "register_operand" "0")))]
5399 ; accept ...0001...1, can this be generalized?
5400 "TARGET_64BIT && exact_log2 (INTVAL (operands[1]) + 1) >= 0"
5403 int x = INTVAL (operands[1]);
5404 operands[2] = GEN_INT (exact_log2 (x + 1));
5405 return \"depdi -1,%%sar,%2,%0\";
5407 [(set_attr "type" "shift")
5408 (set_attr "length" "4")])
5411 [(set (match_operand:DI 0 "register_operand" "=r")
5412 (and:DI (rotate:DI (match_operand:DI 1 "const_int_operand" "")
5413 (minus:DI (const_int 63)
5414 (match_operand:DI 2 "register_operand" "q")))
5415 (match_operand:DI 3 "register_operand" "0")))]
5416 ; this can be generalized...!
5417 "TARGET_64BIT && INTVAL (operands[1]) == -2"
5420 int x = INTVAL (operands[1]);
5421 operands[2] = GEN_INT (exact_log2 ((~x) + 1));
5422 return \"depdi 0,%%sar,%2,%0\";
5424 [(set_attr "type" "shift")
5425 (set_attr "length" "4")])
5427 (define_expand "ashrsi3"
5428 [(set (match_operand:SI 0 "register_operand" "")
5429 (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
5430 (match_operand:SI 2 "arith32_operand" "")))]
5434 if (GET_CODE (operands[2]) != CONST_INT)
5436 rtx temp = gen_reg_rtx (SImode);
5437 emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
5438 emit_insn (gen_vextrs32 (operands[0], operands[1], temp));
5444 [(set (match_operand:SI 0 "register_operand" "=r")
5445 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5446 (match_operand:SI 2 "const_int_operand" "n")))]
5448 "{extrs|extrw,s} %1,%P2,%L2,%0"
5449 [(set_attr "type" "shift")
5450 (set_attr "length" "4")])
5452 (define_insn "vextrs32"
5453 [(set (match_operand:SI 0 "register_operand" "=r")
5454 (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
5455 (minus:SI (const_int 31)
5456 (match_operand:SI 2 "register_operand" "q"))))]
5458 "{vextrs %1,32,%0|extrw,s %1,%%sar,32,%0}"
5459 [(set_attr "type" "shift")
5460 (set_attr "length" "4")])
5462 (define_expand "ashrdi3"
5463 [(set (match_operand:DI 0 "register_operand" "")
5464 (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
5465 (match_operand:DI 2 "arith32_operand" "")))]
5469 if (GET_CODE (operands[2]) != CONST_INT)
5471 rtx temp = gen_reg_rtx (DImode);
5472 emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
5473 emit_insn (gen_vextrs64 (operands[0], operands[1], temp));
5479 [(set (match_operand:DI 0 "register_operand" "=r")
5480 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5481 (match_operand:DI 2 "const_int_operand" "n")))]
5483 "extrd,s %1,%p2,%Q2,%0"
5484 [(set_attr "type" "shift")
5485 (set_attr "length" "4")])
5487 (define_insn "vextrs64"
5488 [(set (match_operand:DI 0 "register_operand" "=r")
5489 (ashiftrt:DI (match_operand:DI 1 "register_operand" "r")
5490 (minus:DI (const_int 63)
5491 (match_operand:DI 2 "register_operand" "q"))))]
5493 "extrd,s %1,%%sar,64,%0"
5494 [(set_attr "type" "shift")
5495 (set_attr "length" "4")])
5497 (define_insn "lshrsi3"
5498 [(set (match_operand:SI 0 "register_operand" "=r,r")
5499 (lshiftrt:SI (match_operand:SI 1 "register_operand" "r,r")
5500 (match_operand:SI 2 "arith32_operand" "q,n")))]
5503 {vshd %%r0,%1,%0|shrpw %%r0,%1,%%sar,%0}
5504 {extru|extrw,u} %1,%P2,%L2,%0"
5505 [(set_attr "type" "shift")
5506 (set_attr "length" "4")])
5508 (define_insn "lshrdi3"
5509 [(set (match_operand:DI 0 "register_operand" "=r,r")
5510 (lshiftrt:DI (match_operand:DI 1 "register_operand" "r,r")
5511 (match_operand:DI 2 "arith32_operand" "q,n")))]
5514 shrpd %%r0,%1,%%sar,%0
5515 extrd,u %1,%p2,%Q2,%0"
5516 [(set_attr "type" "shift")
5517 (set_attr "length" "4")])
5519 (define_insn "rotrsi3"
5520 [(set (match_operand:SI 0 "register_operand" "=r,r")
5521 (rotatert:SI (match_operand:SI 1 "register_operand" "r,r")
5522 (match_operand:SI 2 "arith32_operand" "q,n")))]
5526 if (GET_CODE (operands[2]) == CONST_INT)
5528 operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
5529 return \"{shd|shrpw} %1,%1,%2,%0\";
5532 return \"{vshd %1,%1,%0|shrpw %1,%1,%%sar,%0}\";
5534 [(set_attr "type" "shift")
5535 (set_attr "length" "4")])
5537 (define_expand "rotlsi3"
5538 [(set (match_operand:SI 0 "register_operand" "")
5539 (rotate:SI (match_operand:SI 1 "register_operand" "")
5540 (match_operand:SI 2 "arith32_operand" "")))]
5544 if (GET_CODE (operands[2]) != CONST_INT)
5546 rtx temp = gen_reg_rtx (SImode);
5547 emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
5548 emit_insn (gen_rotrsi3 (operands[0], operands[1], temp));
5551 /* Else expand normally. */
5555 [(set (match_operand:SI 0 "register_operand" "=r")
5556 (rotate:SI (match_operand:SI 1 "register_operand" "r")
5557 (match_operand:SI 2 "const_int_operand" "n")))]
5561 operands[2] = GEN_INT ((32 - INTVAL (operands[2])) & 31);
5562 return \"{shd|shrpw} %1,%1,%2,%0\";
5564 [(set_attr "type" "shift")
5565 (set_attr "length" "4")])
5568 [(set (match_operand:SI 0 "register_operand" "=r")
5569 (match_operator:SI 5 "plus_xor_ior_operator"
5570 [(ashift:SI (match_operand:SI 1 "register_operand" "r")
5571 (match_operand:SI 3 "const_int_operand" "n"))
5572 (lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5573 (match_operand:SI 4 "const_int_operand" "n"))]))]
5574 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5575 "{shd|shrpw} %1,%2,%4,%0"
5576 [(set_attr "type" "shift")
5577 (set_attr "length" "4")])
5580 [(set (match_operand:SI 0 "register_operand" "=r")
5581 (match_operator:SI 5 "plus_xor_ior_operator"
5582 [(lshiftrt:SI (match_operand:SI 2 "register_operand" "r")
5583 (match_operand:SI 4 "const_int_operand" "n"))
5584 (ashift:SI (match_operand:SI 1 "register_operand" "r")
5585 (match_operand:SI 3 "const_int_operand" "n"))]))]
5586 "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
5587 "{shd|shrpw} %1,%2,%4,%0"
5588 [(set_attr "type" "shift")
5589 (set_attr "length" "4")])
5592 [(set (match_operand:SI 0 "register_operand" "=r")
5593 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
5594 (match_operand:SI 2 "const_int_operand" ""))
5595 (match_operand:SI 3 "const_int_operand" "")))]
5596 "exact_log2 (1 + (INTVAL (operands[3]) >> (INTVAL (operands[2]) & 31))) >= 0"
5599 int cnt = INTVAL (operands[2]) & 31;
5600 operands[3] = GEN_INT (exact_log2 (1 + (INTVAL (operands[3]) >> cnt)));
5601 operands[2] = GEN_INT (31 - cnt);
5602 return \"{zdep|depw,z} %1,%2,%3,%0\";
5604 [(set_attr "type" "shift")
5605 (set_attr "length" "4")])
5607 ;; Unconditional and other jump instructions.
5609 ;; This can only be used in a leaf function, so we do
5610 ;; not need to use the PIC register when generating PIC code.
5611 (define_insn "return"
5615 "hppa_can_use_return_insn_p ()"
5619 return \"bve%* (%%r2)\";
5620 return \"bv%* %%r0(%%r2)\";
5622 [(set_attr "type" "branch")
5623 (set_attr "length" "4")])
5625 ;; Emit a different pattern for functions which have non-trivial
5626 ;; epilogues so as not to confuse jump and reorg.
5627 (define_insn "return_internal"
5635 return \"bve%* (%%r2)\";
5636 return \"bv%* %%r0(%%r2)\";
5638 [(set_attr "type" "branch")
5639 (set_attr "length" "4")])
5641 ;; This is used for eh returns which bypass the return stub.
5642 (define_insn "return_external_pic"
5644 (clobber (reg:SI 1))
5646 "!TARGET_NO_SPACE_REGS
5648 && flag_pic && current_function_calls_eh_return"
5649 "ldsid (%%sr0,%%r2),%%r1\;mtsp %%r1,%%sr0\;be%* 0(%%sr0,%%r2)"
5650 [(set_attr "type" "branch")
5651 (set_attr "length" "12")])
5653 (define_expand "prologue"
5656 "hppa_expand_prologue ();DONE;")
5658 (define_expand "sibcall_epilogue"
5663 hppa_expand_epilogue ();
5667 (define_expand "epilogue"
5672 /* Try to use the trivial return first. Else use the full
5674 if (hppa_can_use_return_insn_p ())
5675 emit_jump_insn (gen_return ());
5680 hppa_expand_epilogue ();
5682 /* EH returns bypass the normal return stub. Thus, we must do an
5683 interspace branch to return from functions that call eh_return.
5684 This is only a problem for returns from shared code on ports
5685 using space registers. */
5686 if (!TARGET_NO_SPACE_REGS
5688 && flag_pic && current_function_calls_eh_return)
5689 x = gen_return_external_pic ();
5691 x = gen_return_internal ();
5698 ;; Special because we use the value placed in %r2 by the bl instruction
5699 ;; from within its delay slot to set the value for the 2nd parameter to
5701 (define_insn "call_profiler"
5702 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5703 (match_operand 1 "" ""))
5704 (use (match_operand 2 "" ""))
5707 (clobber (reg:SI 2))]
5713 output_arg_descriptor (insn);
5715 xoperands[0] = operands[0];
5716 xoperands[1] = operands[2];
5717 xoperands[2] = gen_label_rtx ();
5718 output_asm_insn (\"{bl|b,l} %0,%%r2\;ldo %1-%2(%%r2),%%r25\", xoperands);
5720 (*targetm.asm_out.internal_label) (asm_out_file, \"L\",
5721 CODE_LABEL_NUMBER (xoperands[2]));
5724 [(set_attr "type" "multi")
5725 (set_attr "length" "8")])
5727 (define_insn "blockage"
5728 [(unspec_volatile [(const_int 2)] 0)]
5731 [(set_attr "length" "0")])
5734 [(set (pc) (label_ref (match_operand 0 "" "")))]
5738 if (GET_MODE (insn) == SImode)
5741 /* An unconditional branch which can reach its target. */
5742 if (get_attr_length (insn) != 24
5743 && get_attr_length (insn) != 16)
5746 return output_lbranch (operands[0], insn);
5748 [(set_attr "type" "uncond_branch")
5749 (set_attr "pa_combine_type" "uncond_branch")
5750 (set (attr "length")
5751 (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 1))
5752 (if_then_else (lt (abs (minus (match_dup 0)
5753 (plus (pc) (const_int 8))))
5757 (ge (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
5759 (if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
5764 ;; Subroutines of "casesi".
5765 ;; operand 0 is index
5766 ;; operand 1 is the minimum bound
5767 ;; operand 2 is the maximum bound - minimum bound + 1
5768 ;; operand 3 is CODE_LABEL for the table;
5769 ;; operand 4 is the CODE_LABEL to go to if index out of range.
5771 (define_expand "casesi"
5772 [(match_operand:SI 0 "general_operand" "")
5773 (match_operand:SI 1 "const_int_operand" "")
5774 (match_operand:SI 2 "const_int_operand" "")
5775 (match_operand 3 "" "")
5776 (match_operand 4 "" "")]
5780 if (GET_CODE (operands[0]) != REG)
5781 operands[0] = force_reg (SImode, operands[0]);
5783 if (operands[1] != const0_rtx)
5785 rtx reg = gen_reg_rtx (SImode);
5787 operands[1] = GEN_INT (-INTVAL (operands[1]));
5788 if (!INT_14_BITS (operands[1]))
5789 operands[1] = force_reg (SImode, operands[1]);
5790 emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
5795 /* In 64bit mode we must make sure to wipe the upper bits of the register
5796 just in case the addition overflowed or we had random bits in the
5797 high part of the register. */
5800 rtx reg = gen_reg_rtx (DImode);
5801 emit_insn (gen_extendsidi2 (reg, operands[0]));
5802 operands[0] = gen_rtx_SUBREG (SImode, reg, 4);
5805 if (!INT_5_BITS (operands[2]))
5806 operands[2] = force_reg (SImode, operands[2]);
5808 emit_insn (gen_cmpsi (operands[0], operands[2]));
5809 emit_jump_insn (gen_bgtu (operands[4]));
5810 if (TARGET_BIG_SWITCH)
5812 rtx temp = gen_reg_rtx (SImode);
5813 emit_move_insn (temp, gen_rtx_PLUS (SImode, operands[0], operands[0]));
5816 emit_jump_insn (gen_casesi0 (operands[0], operands[3]));
5820 (define_insn "casesi0"
5822 (mem:SI (plus:SI (pc)
5823 (match_operand:SI 0 "register_operand" "r")))
5824 (label_ref (match_operand 1 "" ""))))]
5827 [(set_attr "type" "multi")
5828 (set_attr "length" "8")])
5830 ;; Need nops for the calls because execution is supposed to continue
5831 ;; past; we don't want to nullify an instruction that we need.
5832 ;;- jump to subroutine
5834 (define_expand "call"
5835 [(parallel [(call (match_operand:SI 0 "" "")
5836 (match_operand 1 "" ""))
5837 (clobber (reg:SI 2))])]
5842 rtx nb = operands[1];
5844 if (TARGET_PORTABLE_RUNTIME)
5845 op = force_reg (SImode, XEXP (operands[0], 0));
5847 op = XEXP (operands[0], 0);
5851 if (!virtuals_instantiated)
5852 emit_move_insn (arg_pointer_rtx,
5853 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
5857 /* The loop pass can generate new libcalls after the virtual
5858 registers are instantiated when fpregs are disabled because
5859 the only method that we have for doing DImode multiplication
5860 is with a libcall. This could be trouble if we haven't
5861 allocated enough space for the outgoing arguments. */
5862 if (INTVAL (nb) > current_function_outgoing_args_size)
5865 emit_move_insn (arg_pointer_rtx,
5866 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
5867 GEN_INT (STACK_POINTER_OFFSET + 64)));
5871 /* Use two different patterns for calls to explicitly named functions
5872 and calls through function pointers. This is necessary as these two
5873 types of calls use different calling conventions, and CSE might try
5874 to change the named call into an indirect call in some cases (using
5875 two patterns keeps CSE from performing this optimization).
5877 We now use even more call patterns as there was a subtle bug in
5878 attempting to restore the pic register after a call using a simple
5879 move insn. During reload, a instruction involving a pseudo register
5880 with no explicit dependence on the PIC register can be converted
5881 to an equivalent load from memory using the PIC register. If we
5882 emit a simple move to restore the PIC register in the initial rtl
5883 generation, then it can potentially be repositioned during scheduling.
5884 and an instruction that eventually uses the PIC register may end up
5885 between the call and the PIC register restore.
5887 This only worked because there is a post call group of instructions
5888 that are scheduled with the call. These instructions are included
5889 in the same basic block as the call. However, calls can throw in
5890 C++ code and a basic block has to terminate at the call if the call
5891 can throw. This results in the PIC register restore being scheduled
5892 independently from the call. So, we now hide the save and restore
5893 of the PIC register in the call pattern until after reload. Then,
5894 we split the moves out. A small side benefit is that we now don't
5895 need to have a use of the PIC register in the return pattern and
5896 the final save/restore operation is not needed.
5898 I elected to just clobber %r4 in the PIC patterns and use it instead
5899 of trying to force hppa_pic_save_rtx () to a callee saved register.
5900 This might have required a new register class and constraint. It
5901 was also simpler to just handle the restore from a register than a
5905 if (GET_CODE (op) == SYMBOL_REF)
5906 call_insn = emit_call_insn (gen_call_symref_64bit (op, nb));
5909 op = force_reg (word_mode, op);
5910 call_insn = emit_call_insn (gen_call_reg_64bit (op, nb));
5915 if (GET_CODE (op) == SYMBOL_REF)
5918 call_insn = emit_call_insn (gen_call_symref_pic (op, nb));
5920 call_insn = emit_call_insn (gen_call_symref (op, nb));
5924 rtx tmpreg = gen_rtx_REG (word_mode, 22);
5926 emit_move_insn (tmpreg, force_reg (word_mode, op));
5928 call_insn = emit_call_insn (gen_call_reg_pic (nb));
5930 call_insn = emit_call_insn (gen_call_reg (nb));
5937 ;; We use function calls to set the attribute length of calls and millicode
5938 ;; calls. This is necessary because of the large variety of call sequences.
5939 ;; Implementing the calculation in rtl is difficult as well as ugly. As
5940 ;; we need the same calculation in several places, maintenance becomes a
5943 ;; However, this has a subtle impact on branch shortening. When the
5944 ;; expression used to set the length attribute of an instruction depends
5945 ;; on a relative address (e.g., pc or a branch address), genattrtab
5946 ;; notes that the insn's length is variable, and attempts to determine a
5947 ;; worst-case default length and code to compute an insn's current length.
5949 ;; The use of a function call hides the variable dependence of our calls
5950 ;; and millicode calls. The result is genattrtab doesn't treat the operation
5951 ;; as variable and it only generates code for the default case using our
5952 ;; function call. Because of this, calls and millicode calls have a fixed
5953 ;; length in the branch shortening pass, and some branches will use a longer
5954 ;; code sequence than necessary. However, the length of any given call
5955 ;; will still reflect its final code location and it may be shorter than
5956 ;; the initial length estimate.
5958 ;; It's possible to trick genattrtab by adding an expression involving `pc'
5959 ;; in the set. However, when genattrtab hits a function call in its attempt
5960 ;; to compute the default length, it marks the result as unknown and sets
5961 ;; the default result to MAX_INT ;-( One possible fix that would allow
5962 ;; calls to participate in branch shortening would be to make the call to
5963 ;; insn_default_length a target option. Then, we could massage unknown
5964 ;; results. Another fix might be to change genattrtab so that it just does
5965 ;; the call in the variable case as it already does for the fixed case.
5967 (define_insn "call_symref"
5968 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5969 (match_operand 1 "" "i"))
5970 (clobber (reg:SI 1))
5971 (clobber (reg:SI 2))
5972 (use (const_int 0))]
5973 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
5976 output_arg_descriptor (insn);
5977 return output_call (insn, operands[0], 0);
5979 [(set_attr "type" "call")
5980 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
5982 (define_insn "call_symref_pic"
5983 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
5984 (match_operand 1 "" "i"))
5985 (clobber (reg:SI 1))
5986 (clobber (reg:SI 2))
5987 (clobber (reg:SI 4))
5989 (use (const_int 0))]
5990 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
5993 output_arg_descriptor (insn);
5994 return output_call (insn, operands[0], 0);
5996 [(set_attr "type" "call")
5997 (set (attr "length")
5998 (plus (symbol_ref "attr_length_call (insn, 0)")
5999 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6001 ;; Split out the PIC register save and restore after reload. This is
6002 ;; done only if the function returns. As the split is done after reload,
6003 ;; there are some situations in which we unnecessarily save and restore
6004 ;; %r4. This happens when there is a single call and the PIC register
6005 ;; is "dead" after the call. This isn't easy to fix as the usage of
6006 ;; the PIC register isn't completely determined until the reload pass.
6008 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6009 (match_operand 1 "" ""))
6010 (clobber (reg:SI 1))
6011 (clobber (reg:SI 2))
6012 (clobber (reg:SI 4))
6014 (use (const_int 0))])]
6015 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
6017 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6018 [(set (reg:SI 4) (reg:SI 19))
6019 (parallel [(call (mem:SI (match_dup 0))
6021 (clobber (reg:SI 1))
6022 (clobber (reg:SI 2))
6024 (use (const_int 0))])
6025 (set (reg:SI 19) (reg:SI 4))]
6028 ;; Remove the clobber of register 4 when optimizing. This has to be
6029 ;; done with a peephole optimization rather than a split because the
6030 ;; split sequence for a call must be longer than one instruction.
6032 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6033 (match_operand 1 "" ""))
6034 (clobber (reg:SI 1))
6035 (clobber (reg:SI 2))
6036 (clobber (reg:SI 4))
6038 (use (const_int 0))])]
6039 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
6040 [(parallel [(call (mem:SI (match_dup 0))
6042 (clobber (reg:SI 1))
6043 (clobber (reg:SI 2))
6045 (use (const_int 0))])]
6048 (define_insn "*call_symref_pic_post_reload"
6049 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6050 (match_operand 1 "" "i"))
6051 (clobber (reg:SI 1))
6052 (clobber (reg:SI 2))
6054 (use (const_int 0))]
6055 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6058 output_arg_descriptor (insn);
6059 return output_call (insn, operands[0], 0);
6061 [(set_attr "type" "call")
6062 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6064 ;; This pattern is split if it is necessary to save and restore the
6066 (define_insn "call_symref_64bit"
6067 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6068 (match_operand 1 "" "i"))
6069 (clobber (reg:DI 1))
6070 (clobber (reg:DI 2))
6071 (clobber (reg:DI 4))
6074 (use (const_int 0))]
6078 output_arg_descriptor (insn);
6079 return output_call (insn, operands[0], 0);
6081 [(set_attr "type" "call")
6082 (set (attr "length")
6083 (plus (symbol_ref "attr_length_call (insn, 0)")
6084 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6086 ;; Split out the PIC register save and restore after reload. This is
6087 ;; done only if the function returns. As the split is done after reload,
6088 ;; there are some situations in which we unnecessarily save and restore
6089 ;; %r4. This happens when there is a single call and the PIC register
6090 ;; is "dead" after the call. This isn't easy to fix as the usage of
6091 ;; the PIC register isn't completely determined until the reload pass.
6093 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6094 (match_operand 1 "" ""))
6095 (clobber (reg:DI 1))
6096 (clobber (reg:DI 2))
6097 (clobber (reg:DI 4))
6100 (use (const_int 0))])]
6103 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6104 [(set (reg:DI 4) (reg:DI 27))
6105 (parallel [(call (mem:SI (match_dup 0))
6107 (clobber (reg:DI 1))
6108 (clobber (reg:DI 2))
6111 (use (const_int 0))])
6112 (set (reg:DI 27) (reg:DI 4))]
6115 ;; Remove the clobber of register 4 when optimizing. This has to be
6116 ;; done with a peephole optimization rather than a split because the
6117 ;; split sequence for a call must be longer than one instruction.
6119 [(parallel [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6120 (match_operand 1 "" ""))
6121 (clobber (reg:DI 1))
6122 (clobber (reg:DI 2))
6123 (clobber (reg:DI 4))
6126 (use (const_int 0))])]
6127 "TARGET_64BIT && reload_completed"
6128 [(parallel [(call (mem:SI (match_dup 0))
6130 (clobber (reg:DI 1))
6131 (clobber (reg:DI 2))
6134 (use (const_int 0))])]
6137 (define_insn "*call_symref_64bit_post_reload"
6138 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6139 (match_operand 1 "" "i"))
6140 (clobber (reg:DI 1))
6141 (clobber (reg:DI 2))
6144 (use (const_int 0))]
6148 output_arg_descriptor (insn);
6149 return output_call (insn, operands[0], 0);
6151 [(set_attr "type" "call")
6152 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6154 (define_insn "call_reg"
6155 [(call (mem:SI (reg:SI 22))
6156 (match_operand 0 "" "i"))
6157 (clobber (reg:SI 1))
6158 (clobber (reg:SI 2))
6159 (use (const_int 1))]
6163 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6165 [(set_attr "type" "dyncall")
6166 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6168 ;; This pattern is split if it is necessary to save and restore the
6170 (define_insn "call_reg_pic"
6171 [(call (mem:SI (reg:SI 22))
6172 (match_operand 0 "" "i"))
6173 (clobber (reg:SI 1))
6174 (clobber (reg:SI 2))
6175 (clobber (reg:SI 4))
6177 (use (const_int 1))]
6181 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6183 [(set_attr "type" "dyncall")
6184 (set (attr "length")
6185 (plus (symbol_ref "attr_length_indirect_call (insn)")
6186 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6188 ;; Split out the PIC register save and restore after reload. This is
6189 ;; done only if the function returns. As the split is done after reload,
6190 ;; there are some situations in which we unnecessarily save and restore
6191 ;; %r4. This happens when there is a single call and the PIC register
6192 ;; is "dead" after the call. This isn't easy to fix as the usage of
6193 ;; the PIC register isn't completely determined until the reload pass.
6195 [(parallel [(call (mem:SI (reg:SI 22))
6196 (match_operand 0 "" ""))
6197 (clobber (reg:SI 1))
6198 (clobber (reg:SI 2))
6199 (clobber (reg:SI 4))
6201 (use (const_int 1))])]
6204 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6205 [(set (reg:SI 4) (reg:SI 19))
6206 (parallel [(call (mem:SI (reg:SI 22))
6208 (clobber (reg:SI 1))
6209 (clobber (reg:SI 2))
6211 (use (const_int 1))])
6212 (set (reg:SI 19) (reg:SI 4))]
6215 ;; Remove the clobber of register 4 when optimizing. This has to be
6216 ;; done with a peephole optimization rather than a split because the
6217 ;; split sequence for a call must be longer than one instruction.
6219 [(parallel [(call (mem:SI (reg:SI 22))
6220 (match_operand 0 "" ""))
6221 (clobber (reg:SI 1))
6222 (clobber (reg:SI 2))
6223 (clobber (reg:SI 4))
6225 (use (const_int 1))])]
6226 "!TARGET_64BIT && reload_completed"
6227 [(parallel [(call (mem:SI (reg:SI 22))
6229 (clobber (reg:SI 1))
6230 (clobber (reg:SI 2))
6232 (use (const_int 1))])]
6235 (define_insn "*call_reg_pic_post_reload"
6236 [(call (mem:SI (reg:SI 22))
6237 (match_operand 0 "" "i"))
6238 (clobber (reg:SI 1))
6239 (clobber (reg:SI 2))
6241 (use (const_int 1))]
6245 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6247 [(set_attr "type" "dyncall")
6248 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6250 ;; This pattern is split if it is necessary to save and restore the
6252 (define_insn "call_reg_64bit"
6253 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6254 (match_operand 1 "" "i"))
6255 (clobber (reg:DI 2))
6256 (clobber (reg:DI 4))
6259 (use (const_int 1))]
6263 return output_indirect_call (insn, operands[0]);
6265 [(set_attr "type" "dyncall")
6266 (set (attr "length")
6267 (plus (symbol_ref "attr_length_indirect_call (insn)")
6268 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6270 ;; Split out the PIC register save and restore after reload. This is
6271 ;; done only if the function returns. As the split is done after reload,
6272 ;; there are some situations in which we unnecessarily save and restore
6273 ;; %r4. This happens when there is a single call and the PIC register
6274 ;; is "dead" after the call. This isn't easy to fix as the usage of
6275 ;; the PIC register isn't completely determined until the reload pass.
6277 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
6278 (match_operand 1 "" ""))
6279 (clobber (reg:DI 2))
6280 (clobber (reg:DI 4))
6283 (use (const_int 1))])]
6286 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6287 [(set (reg:DI 4) (reg:DI 27))
6288 (parallel [(call (mem:SI (match_dup 0))
6290 (clobber (reg:DI 2))
6293 (use (const_int 1))])
6294 (set (reg:DI 27) (reg:DI 4))]
6297 ;; Remove the clobber of register 4 when optimizing. This has to be
6298 ;; done with a peephole optimization rather than a split because the
6299 ;; split sequence for a call must be longer than one instruction.
6301 [(parallel [(call (mem:SI (match_operand 0 "register_operand" ""))
6302 (match_operand 1 "" ""))
6303 (clobber (reg:DI 2))
6304 (clobber (reg:DI 4))
6307 (use (const_int 1))])]
6308 "TARGET_64BIT && reload_completed"
6309 [(parallel [(call (mem:SI (match_dup 0))
6311 (clobber (reg:DI 2))
6314 (use (const_int 1))])]
6317 (define_insn "*call_reg_64bit_post_reload"
6318 [(call (mem:SI (match_operand:DI 0 "register_operand" "r"))
6319 (match_operand 1 "" "i"))
6320 (clobber (reg:DI 2))
6323 (use (const_int 1))]
6327 return output_indirect_call (insn, operands[0]);
6329 [(set_attr "type" "dyncall")
6330 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6332 (define_expand "call_value"
6333 [(parallel [(set (match_operand 0 "" "")
6334 (call (match_operand:SI 1 "" "")
6335 (match_operand 2 "" "")))
6336 (clobber (reg:SI 2))])]
6341 rtx dst = operands[0];
6342 rtx nb = operands[2];
6344 if (TARGET_PORTABLE_RUNTIME)
6345 op = force_reg (SImode, XEXP (operands[1], 0));
6347 op = XEXP (operands[1], 0);
6351 if (!virtuals_instantiated)
6352 emit_move_insn (arg_pointer_rtx,
6353 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6357 /* The loop pass can generate new libcalls after the virtual
6358 registers are instantiated when fpregs are disabled because
6359 the only method that we have for doing DImode multiplication
6360 is with a libcall. This could be trouble if we haven't
6361 allocated enough space for the outgoing arguments. */
6362 if (INTVAL (nb) > current_function_outgoing_args_size)
6365 emit_move_insn (arg_pointer_rtx,
6366 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6367 GEN_INT (STACK_POINTER_OFFSET + 64)));
6371 /* Use two different patterns for calls to explicitly named functions
6372 and calls through function pointers. This is necessary as these two
6373 types of calls use different calling conventions, and CSE might try
6374 to change the named call into an indirect call in some cases (using
6375 two patterns keeps CSE from performing this optimization).
6377 We now use even more call patterns as there was a subtle bug in
6378 attempting to restore the pic register after a call using a simple
6379 move insn. During reload, a instruction involving a pseudo register
6380 with no explicit dependence on the PIC register can be converted
6381 to an equivalent load from memory using the PIC register. If we
6382 emit a simple move to restore the PIC register in the initial rtl
6383 generation, then it can potentially be repositioned during scheduling.
6384 and an instruction that eventually uses the PIC register may end up
6385 between the call and the PIC register restore.
6387 This only worked because there is a post call group of instructions
6388 that are scheduled with the call. These instructions are included
6389 in the same basic block as the call. However, calls can throw in
6390 C++ code and a basic block has to terminate at the call if the call
6391 can throw. This results in the PIC register restore being scheduled
6392 independently from the call. So, we now hide the save and restore
6393 of the PIC register in the call pattern until after reload. Then,
6394 we split the moves out. A small side benefit is that we now don't
6395 need to have a use of the PIC register in the return pattern and
6396 the final save/restore operation is not needed.
6398 I elected to just clobber %r4 in the PIC patterns and use it instead
6399 of trying to force hppa_pic_save_rtx () to a callee saved register.
6400 This might have required a new register class and constraint. It
6401 was also simpler to just handle the restore from a register than a
6405 if (GET_CODE (op) == SYMBOL_REF)
6406 call_insn = emit_call_insn (gen_call_val_symref_64bit (dst, op, nb));
6409 op = force_reg (word_mode, op);
6410 call_insn = emit_call_insn (gen_call_val_reg_64bit (dst, op, nb));
6415 if (GET_CODE (op) == SYMBOL_REF)
6418 call_insn = emit_call_insn (gen_call_val_symref_pic (dst, op, nb));
6420 call_insn = emit_call_insn (gen_call_val_symref (dst, op, nb));
6424 rtx tmpreg = gen_rtx_REG (word_mode, 22);
6426 emit_move_insn (tmpreg, force_reg (word_mode, op));
6428 call_insn = emit_call_insn (gen_call_val_reg_pic (dst, nb));
6430 call_insn = emit_call_insn (gen_call_val_reg (dst, nb));
6437 (define_insn "call_val_symref"
6438 [(set (match_operand 0 "" "")
6439 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6440 (match_operand 2 "" "i")))
6441 (clobber (reg:SI 1))
6442 (clobber (reg:SI 2))
6443 (use (const_int 0))]
6444 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6447 output_arg_descriptor (insn);
6448 return output_call (insn, operands[1], 0);
6450 [(set_attr "type" "call")
6451 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6453 (define_insn "call_val_symref_pic"
6454 [(set (match_operand 0 "" "")
6455 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6456 (match_operand 2 "" "i")))
6457 (clobber (reg:SI 1))
6458 (clobber (reg:SI 2))
6459 (clobber (reg:SI 4))
6461 (use (const_int 0))]
6462 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6465 output_arg_descriptor (insn);
6466 return output_call (insn, operands[1], 0);
6468 [(set_attr "type" "call")
6469 (set (attr "length")
6470 (plus (symbol_ref "attr_length_call (insn, 0)")
6471 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6473 ;; Split out the PIC register save and restore after reload. This is
6474 ;; done only if the function returns. As the split is done after reload,
6475 ;; there are some situations in which we unnecessarily save and restore
6476 ;; %r4. This happens when there is a single call and the PIC register
6477 ;; is "dead" after the call. This isn't easy to fix as the usage of
6478 ;; the PIC register isn't completely determined until the reload pass.
6480 [(parallel [(set (match_operand 0 "" "")
6481 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6482 (match_operand 2 "" "")))
6483 (clobber (reg:SI 1))
6484 (clobber (reg:SI 2))
6485 (clobber (reg:SI 4))
6487 (use (const_int 0))])]
6488 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT
6490 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6491 [(set (reg:SI 4) (reg:SI 19))
6492 (parallel [(set (match_dup 0)
6493 (call (mem:SI (match_dup 1))
6495 (clobber (reg:SI 1))
6496 (clobber (reg:SI 2))
6498 (use (const_int 0))])
6499 (set (reg:SI 19) (reg:SI 4))]
6502 ;; Remove the clobber of register 4 when optimizing. This has to be
6503 ;; done with a peephole optimization rather than a split because the
6504 ;; split sequence for a call must be longer than one instruction.
6506 [(parallel [(set (match_operand 0 "" "")
6507 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6508 (match_operand 2 "" "")))
6509 (clobber (reg:SI 1))
6510 (clobber (reg:SI 2))
6511 (clobber (reg:SI 4))
6513 (use (const_int 0))])]
6514 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT && reload_completed"
6515 [(parallel [(set (match_dup 0)
6516 (call (mem:SI (match_dup 1))
6518 (clobber (reg:SI 1))
6519 (clobber (reg:SI 2))
6521 (use (const_int 0))])]
6524 (define_insn "*call_val_symref_pic_post_reload"
6525 [(set (match_operand 0 "" "")
6526 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6527 (match_operand 2 "" "i")))
6528 (clobber (reg:SI 1))
6529 (clobber (reg:SI 2))
6531 (use (const_int 0))]
6532 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6535 output_arg_descriptor (insn);
6536 return output_call (insn, operands[1], 0);
6538 [(set_attr "type" "call")
6539 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6541 ;; This pattern is split if it is necessary to save and restore the
6543 (define_insn "call_val_symref_64bit"
6544 [(set (match_operand 0 "" "")
6545 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6546 (match_operand 2 "" "i")))
6547 (clobber (reg:DI 1))
6548 (clobber (reg:DI 2))
6549 (clobber (reg:DI 4))
6552 (use (const_int 0))]
6556 output_arg_descriptor (insn);
6557 return output_call (insn, operands[1], 0);
6559 [(set_attr "type" "call")
6560 (set (attr "length")
6561 (plus (symbol_ref "attr_length_call (insn, 0)")
6562 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6564 ;; Split out the PIC register save and restore after reload. This is
6565 ;; done only if the function returns. As the split is done after reload,
6566 ;; there are some situations in which we unnecessarily save and restore
6567 ;; %r4. This happens when there is a single call and the PIC register
6568 ;; is "dead" after the call. This isn't easy to fix as the usage of
6569 ;; the PIC register isn't completely determined until the reload pass.
6571 [(parallel [(set (match_operand 0 "" "")
6572 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6573 (match_operand 2 "" "")))
6574 (clobber (reg:DI 1))
6575 (clobber (reg:DI 2))
6576 (clobber (reg:DI 4))
6579 (use (const_int 0))])]
6582 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6583 [(set (reg:DI 4) (reg:DI 27))
6584 (parallel [(set (match_dup 0)
6585 (call (mem:SI (match_dup 1))
6587 (clobber (reg:DI 1))
6588 (clobber (reg:DI 2))
6591 (use (const_int 0))])
6592 (set (reg:DI 27) (reg:DI 4))]
6595 ;; Remove the clobber of register 4 when optimizing. This has to be
6596 ;; done with a peephole optimization rather than a split because the
6597 ;; split sequence for a call must be longer than one instruction.
6599 [(parallel [(set (match_operand 0 "" "")
6600 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6601 (match_operand 2 "" "")))
6602 (clobber (reg:DI 1))
6603 (clobber (reg:DI 2))
6604 (clobber (reg:DI 4))
6607 (use (const_int 0))])]
6608 "TARGET_64BIT && reload_completed"
6609 [(parallel [(set (match_dup 0)
6610 (call (mem:SI (match_dup 1))
6612 (clobber (reg:DI 1))
6613 (clobber (reg:DI 2))
6616 (use (const_int 0))])]
6619 (define_insn "*call_val_symref_64bit_post_reload"
6620 [(set (match_operand 0 "" "")
6621 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6622 (match_operand 2 "" "i")))
6623 (clobber (reg:DI 1))
6624 (clobber (reg:DI 2))
6627 (use (const_int 0))]
6631 output_arg_descriptor (insn);
6632 return output_call (insn, operands[1], 0);
6634 [(set_attr "type" "call")
6635 (set (attr "length") (symbol_ref "attr_length_call (insn, 0)"))])
6637 (define_insn "call_val_reg"
6638 [(set (match_operand 0 "" "")
6639 (call (mem:SI (reg:SI 22))
6640 (match_operand 1 "" "i")))
6641 (clobber (reg:SI 1))
6642 (clobber (reg:SI 2))
6643 (use (const_int 1))]
6647 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6649 [(set_attr "type" "dyncall")
6650 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6652 ;; This pattern is split if it is necessary to save and restore the
6654 (define_insn "call_val_reg_pic"
6655 [(set (match_operand 0 "" "")
6656 (call (mem:SI (reg:SI 22))
6657 (match_operand 1 "" "i")))
6658 (clobber (reg:SI 1))
6659 (clobber (reg:SI 2))
6660 (clobber (reg:SI 4))
6662 (use (const_int 1))]
6666 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6668 [(set_attr "type" "dyncall")
6669 (set (attr "length")
6670 (plus (symbol_ref "attr_length_indirect_call (insn)")
6671 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6673 ;; Split out the PIC register save and restore after reload. This is
6674 ;; done only if the function returns. As the split is done after reload,
6675 ;; there are some situations in which we unnecessarily save and restore
6676 ;; %r4. This happens when there is a single call and the PIC register
6677 ;; is "dead" after the call. This isn't easy to fix as the usage of
6678 ;; the PIC register isn't completely determined until the reload pass.
6680 [(parallel [(set (match_operand 0 "" "")
6681 (call (mem:SI (reg:SI 22))
6682 (match_operand 1 "" "")))
6683 (clobber (reg:SI 1))
6684 (clobber (reg:SI 2))
6685 (clobber (reg:SI 4))
6687 (use (const_int 1))])]
6690 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6691 [(set (reg:SI 4) (reg:SI 19))
6692 (parallel [(set (match_dup 0)
6693 (call (mem:SI (reg:SI 22))
6695 (clobber (reg:SI 1))
6696 (clobber (reg:SI 2))
6698 (use (const_int 1))])
6699 (set (reg:SI 19) (reg:SI 4))]
6702 ;; Remove the clobber of register 4 when optimizing. This has to be
6703 ;; done with a peephole optimization rather than a split because the
6704 ;; split sequence for a call must be longer than one instruction.
6706 [(parallel [(set (match_operand 0 "" "")
6707 (call (mem:SI (reg:SI 22))
6708 (match_operand 1 "" "")))
6709 (clobber (reg:SI 1))
6710 (clobber (reg:SI 2))
6711 (clobber (reg:SI 4))
6713 (use (const_int 1))])]
6714 "!TARGET_64BIT && reload_completed"
6715 [(parallel [(set (match_dup 0)
6716 (call (mem:SI (reg:SI 22))
6718 (clobber (reg:SI 1))
6719 (clobber (reg:SI 2))
6721 (use (const_int 1))])]
6724 (define_insn "*call_val_reg_pic_post_reload"
6725 [(set (match_operand 0 "" "")
6726 (call (mem:SI (reg:SI 22))
6727 (match_operand 1 "" "i")))
6728 (clobber (reg:SI 1))
6729 (clobber (reg:SI 2))
6731 (use (const_int 1))]
6735 return output_indirect_call (insn, gen_rtx_REG (word_mode, 22));
6737 [(set_attr "type" "dyncall")
6738 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6740 ;; This pattern is split if it is necessary to save and restore the
6742 (define_insn "call_val_reg_64bit"
6743 [(set (match_operand 0 "" "")
6744 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6745 (match_operand 2 "" "i")))
6746 (clobber (reg:DI 2))
6747 (clobber (reg:DI 4))
6750 (use (const_int 1))]
6754 return output_indirect_call (insn, operands[1]);
6756 [(set_attr "type" "dyncall")
6757 (set (attr "length")
6758 (plus (symbol_ref "attr_length_indirect_call (insn)")
6759 (symbol_ref "attr_length_save_restore_dltp (insn)")))])
6761 ;; Split out the PIC register save and restore after reload. This is
6762 ;; done only if the function returns. As the split is done after reload,
6763 ;; there are some situations in which we unnecessarily save and restore
6764 ;; %r4. This happens when there is a single call and the PIC register
6765 ;; is "dead" after the call. This isn't easy to fix as the usage of
6766 ;; the PIC register isn't completely determined until the reload pass.
6768 [(parallel [(set (match_operand 0 "" "")
6769 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
6770 (match_operand 2 "" "")))
6771 (clobber (reg:DI 2))
6772 (clobber (reg:DI 4))
6775 (use (const_int 1))])]
6778 && !find_reg_note (insn, REG_NORETURN, NULL_RTX)"
6779 [(set (reg:DI 4) (reg:DI 27))
6780 (parallel [(set (match_dup 0)
6781 (call (mem:SI (match_dup 1))
6783 (clobber (reg:DI 2))
6786 (use (const_int 1))])
6787 (set (reg:DI 27) (reg:DI 4))]
6790 ;; Remove the clobber of register 4 when optimizing. This has to be
6791 ;; done with a peephole optimization rather than a split because the
6792 ;; split sequence for a call must be longer than one instruction.
6794 [(parallel [(set (match_operand 0 "" "")
6795 (call (mem:SI (match_operand:DI 1 "register_operand" ""))
6796 (match_operand 2 "" "")))
6797 (clobber (reg:DI 2))
6798 (clobber (reg:DI 4))
6801 (use (const_int 1))])]
6802 "TARGET_64BIT && reload_completed"
6803 [(parallel [(set (match_dup 0)
6804 (call (mem:SI (match_dup 1))
6806 (clobber (reg:DI 2))
6809 (use (const_int 1))])]
6812 (define_insn "*call_val_reg_64bit_post_reload"
6813 [(set (match_operand 0 "" "")
6814 (call (mem:SI (match_operand:DI 1 "register_operand" "r"))
6815 (match_operand 2 "" "i")))
6816 (clobber (reg:DI 2))
6819 (use (const_int 1))]
6823 return output_indirect_call (insn, operands[1]);
6825 [(set_attr "type" "dyncall")
6826 (set (attr "length") (symbol_ref "attr_length_indirect_call (insn)"))])
6828 ;; Call subroutine returning any type.
6830 (define_expand "untyped_call"
6831 [(parallel [(call (match_operand 0 "" "")
6833 (match_operand 1 "" "")
6834 (match_operand 2 "" "")])]
6840 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
6842 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6844 rtx set = XVECEXP (operands[2], 0, i);
6845 emit_move_insn (SET_DEST (set), SET_SRC (set));
6848 /* The optimizer does not know that the call sets the function value
6849 registers we stored in the result block. We avoid problems by
6850 claiming that all hard registers are used and clobbered at this
6852 emit_insn (gen_blockage ());
6857 (define_expand "sibcall"
6858 [(call (match_operand:SI 0 "" "")
6859 (match_operand 1 "" ""))]
6860 "!TARGET_PORTABLE_RUNTIME"
6864 rtx nb = operands[1];
6866 op = XEXP (operands[0], 0);
6870 if (!virtuals_instantiated)
6871 emit_move_insn (arg_pointer_rtx,
6872 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6876 /* The loop pass can generate new libcalls after the virtual
6877 registers are instantiated when fpregs are disabled because
6878 the only method that we have for doing DImode multiplication
6879 is with a libcall. This could be trouble if we haven't
6880 allocated enough space for the outgoing arguments. */
6881 if (INTVAL (nb) > current_function_outgoing_args_size)
6884 emit_move_insn (arg_pointer_rtx,
6885 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6886 GEN_INT (STACK_POINTER_OFFSET + 64)));
6890 /* Indirect sibling calls are not allowed. */
6892 call_insn = gen_sibcall_internal_symref_64bit (op, operands[1]);
6894 call_insn = gen_sibcall_internal_symref (op, operands[1]);
6896 call_insn = emit_call_insn (call_insn);
6899 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6901 /* We don't have to restore the PIC register. */
6903 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6908 (define_insn "sibcall_internal_symref"
6909 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6910 (match_operand 1 "" "i"))
6911 (clobber (reg:SI 1))
6913 (use (const_int 0))]
6914 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
6917 output_arg_descriptor (insn);
6918 return output_call (insn, operands[0], 1);
6920 [(set_attr "type" "call")
6921 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6923 (define_insn "sibcall_internal_symref_64bit"
6924 [(call (mem:SI (match_operand 0 "call_operand_address" ""))
6925 (match_operand 1 "" "i"))
6926 (clobber (reg:DI 1))
6928 (use (const_int 0))]
6932 output_arg_descriptor (insn);
6933 return output_call (insn, operands[0], 1);
6935 [(set_attr "type" "call")
6936 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
6938 (define_expand "sibcall_value"
6939 [(set (match_operand 0 "" "")
6940 (call (match_operand:SI 1 "" "")
6941 (match_operand 2 "" "")))]
6942 "!TARGET_PORTABLE_RUNTIME"
6946 rtx nb = operands[1];
6948 op = XEXP (operands[1], 0);
6952 if (!virtuals_instantiated)
6953 emit_move_insn (arg_pointer_rtx,
6954 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
6958 /* The loop pass can generate new libcalls after the virtual
6959 registers are instantiated when fpregs are disabled because
6960 the only method that we have for doing DImode multiplication
6961 is with a libcall. This could be trouble if we haven't
6962 allocated enough space for the outgoing arguments. */
6963 if (INTVAL (nb) > current_function_outgoing_args_size)
6966 emit_move_insn (arg_pointer_rtx,
6967 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
6968 GEN_INT (STACK_POINTER_OFFSET + 64)));
6972 /* Indirect sibling calls are not allowed. */
6975 = gen_sibcall_value_internal_symref_64bit (operands[0], op, operands[2]);
6978 = gen_sibcall_value_internal_symref (operands[0], op, operands[2]);
6980 call_insn = emit_call_insn (call_insn);
6983 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
6985 /* We don't have to restore the PIC register. */
6987 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
6992 (define_insn "sibcall_value_internal_symref"
6993 [(set (match_operand 0 "" "")
6994 (call (mem:SI (match_operand 1 "call_operand_address" ""))
6995 (match_operand 2 "" "i")))
6996 (clobber (reg:SI 1))
6998 (use (const_int 0))]
6999 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7002 output_arg_descriptor (insn);
7003 return output_call (insn, operands[1], 1);
7005 [(set_attr "type" "call")
7006 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7008 (define_insn "sibcall_value_internal_symref_64bit"
7009 [(set (match_operand 0 "" "")
7010 (call (mem:SI (match_operand 1 "call_operand_address" ""))
7011 (match_operand 2 "" "i")))
7012 (clobber (reg:DI 1))
7014 (use (const_int 0))]
7018 output_arg_descriptor (insn);
7019 return output_call (insn, operands[1], 1);
7021 [(set_attr "type" "call")
7022 (set (attr "length") (symbol_ref "attr_length_call (insn, 1)"))])
7028 [(set_attr "type" "move")
7029 (set_attr "length" "4")])
7031 ;; These are just placeholders so we know where branch tables
7033 (define_insn "begin_brtab"
7038 /* Only GAS actually supports this pseudo-op. */
7040 return \".begin_brtab\";
7044 [(set_attr "type" "move")
7045 (set_attr "length" "0")])
7047 (define_insn "end_brtab"
7052 /* Only GAS actually supports this pseudo-op. */
7054 return \".end_brtab\";
7058 [(set_attr "type" "move")
7059 (set_attr "length" "0")])
7061 ;;; EH does longjmp's from and within the data section. Thus,
7062 ;;; an interspace branch is required for the longjmp implementation.
7063 ;;; Registers r1 and r2 are used as scratch registers for the jump
7065 (define_expand "interspace_jump"
7067 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7068 (clobber (match_dup 1))])]
7072 operands[1] = gen_rtx_REG (word_mode, 2);
7076 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7077 (clobber (reg:SI 2))]
7078 "TARGET_PA_20 && !TARGET_64BIT"
7080 [(set_attr "type" "branch")
7081 (set_attr "length" "4")])
7084 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7085 (clobber (reg:SI 2))]
7086 "TARGET_NO_SPACE_REGS && !TARGET_64BIT"
7088 [(set_attr "type" "branch")
7089 (set_attr "length" "4")])
7092 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7093 (clobber (reg:SI 2))]
7095 "ldsid (%%sr0,%0),%%r2\; mtsp %%r2,%%sr0\; be%* 0(%%sr0,%0)"
7096 [(set_attr "type" "branch")
7097 (set_attr "length" "12")])
7100 [(set (pc) (match_operand 0 "pmode_register_operand" "a"))
7101 (clobber (reg:DI 2))]
7104 [(set_attr "type" "branch")
7105 (set_attr "length" "4")])
7107 (define_expand "builtin_longjmp"
7108 [(unspec_volatile [(match_operand 0 "register_operand" "r")] 3)]
7112 /* The elements of the buffer are, in order: */
7113 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
7114 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0],
7115 POINTER_SIZE / BITS_PER_UNIT));
7116 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0],
7117 (POINTER_SIZE * 2) / BITS_PER_UNIT));
7118 rtx pv = gen_rtx_REG (Pmode, 1);
7120 /* This bit is the same as expand_builtin_longjmp. */
7121 emit_move_insn (hard_frame_pointer_rtx, fp);
7122 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
7123 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
7124 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
7126 /* Load the label we are jumping through into r1 so that we know
7127 where to look for it when we get back to setjmp's function for
7128 restoring the gp. */
7129 emit_move_insn (pv, lab);
7131 /* Prevent the insns above from being scheduled into the delay slot
7132 of the interspace jump because the space register could change. */
7133 emit_insn (gen_blockage ());
7135 emit_jump_insn (gen_interspace_jump (pv));
7140 ;;; Hope this is only within a function...
7141 (define_insn "indirect_jump"
7142 [(set (pc) (match_operand 0 "register_operand" "r"))]
7143 "GET_MODE (operands[0]) == word_mode"
7145 [(set_attr "type" "branch")
7146 (set_attr "length" "4")])
7148 (define_expand "extzv"
7149 [(set (match_operand 0 "register_operand" "")
7150 (zero_extract (match_operand 1 "register_operand" "")
7151 (match_operand 2 "uint32_operand" "")
7152 (match_operand 3 "uint32_operand" "")))]
7156 /* PA extraction insns don't support zero length bitfields. */
7157 if (INTVAL (operands[2]) == 0)
7161 emit_insn (gen_extzv_64 (operands[0], operands[1],
7162 operands[2], operands[3]));
7165 if (! uint5_operand (operands[2], SImode)
7166 || ! uint5_operand (operands[3], SImode))
7168 emit_insn (gen_extzv_32 (operands[0], operands[1],
7169 operands[2], operands[3]));
7174 (define_insn "extzv_32"
7175 [(set (match_operand:SI 0 "register_operand" "=r")
7176 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
7177 (match_operand:SI 2 "uint5_operand" "")
7178 (match_operand:SI 3 "uint5_operand" "")))]
7180 "{extru|extrw,u} %1,%3+%2-1,%2,%0"
7181 [(set_attr "type" "shift")
7182 (set_attr "length" "4")])
7185 [(set (match_operand:SI 0 "register_operand" "=r")
7186 (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
7188 (match_operand:SI 2 "register_operand" "q")))]
7190 "{vextru %1,1,%0|extrw,u %1,%%sar,1,%0}"
7191 [(set_attr "type" "shift")
7192 (set_attr "length" "4")])
7194 (define_insn "extzv_64"
7195 [(set (match_operand:DI 0 "register_operand" "=r")
7196 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
7197 (match_operand:DI 2 "uint32_operand" "")
7198 (match_operand:DI 3 "uint32_operand" "")))]
7200 "extrd,u %1,%3+%2-1,%2,%0"
7201 [(set_attr "type" "shift")
7202 (set_attr "length" "4")])
7205 [(set (match_operand:DI 0 "register_operand" "=r")
7206 (zero_extract:DI (match_operand:DI 1 "register_operand" "r")
7208 (match_operand:DI 2 "register_operand" "q")))]
7210 "extrd,u %1,%%sar,1,%0"
7211 [(set_attr "type" "shift")
7212 (set_attr "length" "4")])
7214 (define_expand "extv"
7215 [(set (match_operand 0 "register_operand" "")
7216 (sign_extract (match_operand 1 "register_operand" "")
7217 (match_operand 2 "uint32_operand" "")
7218 (match_operand 3 "uint32_operand" "")))]
7222 /* PA extraction insns don't support zero length bitfields. */
7223 if (INTVAL (operands[2]) == 0)
7227 emit_insn (gen_extv_64 (operands[0], operands[1],
7228 operands[2], operands[3]));
7231 if (! uint5_operand (operands[2], SImode)
7232 || ! uint5_operand (operands[3], SImode))
7234 emit_insn (gen_extv_32 (operands[0], operands[1],
7235 operands[2], operands[3]));
7240 (define_insn "extv_32"
7241 [(set (match_operand:SI 0 "register_operand" "=r")
7242 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
7243 (match_operand:SI 2 "uint5_operand" "")
7244 (match_operand:SI 3 "uint5_operand" "")))]
7246 "{extrs|extrw,s} %1,%3+%2-1,%2,%0"
7247 [(set_attr "type" "shift")
7248 (set_attr "length" "4")])
7251 [(set (match_operand:SI 0 "register_operand" "=r")
7252 (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
7254 (match_operand:SI 2 "register_operand" "q")))]
7256 "{vextrs %1,1,%0|extrw,s %1,%%sar,1,%0}"
7257 [(set_attr "type" "shift")
7258 (set_attr "length" "4")])
7260 (define_insn "extv_64"
7261 [(set (match_operand:DI 0 "register_operand" "=r")
7262 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
7263 (match_operand:DI 2 "uint32_operand" "")
7264 (match_operand:DI 3 "uint32_operand" "")))]
7266 "extrd,s %1,%3+%2-1,%2,%0"
7267 [(set_attr "type" "shift")
7268 (set_attr "length" "4")])
7271 [(set (match_operand:DI 0 "register_operand" "=r")
7272 (sign_extract:DI (match_operand:DI 1 "register_operand" "r")
7274 (match_operand:DI 2 "register_operand" "q")))]
7276 "extrd,s %1,%%sar,1,%0"
7277 [(set_attr "type" "shift")
7278 (set_attr "length" "4")])
7280 ;; Only specify the mode operands 0, the rest are assumed to be word_mode.
7281 (define_expand "insv"
7282 [(set (zero_extract (match_operand 0 "register_operand" "")
7283 (match_operand 1 "uint32_operand" "")
7284 (match_operand 2 "uint32_operand" ""))
7285 (match_operand 3 "arith5_operand" ""))]
7290 emit_insn (gen_insv_64 (operands[0], operands[1],
7291 operands[2], operands[3]));
7294 if (! uint5_operand (operands[2], SImode)
7295 || ! uint5_operand (operands[3], SImode))
7297 emit_insn (gen_insv_32 (operands[0], operands[1],
7298 operands[2], operands[3]));
7303 (define_insn "insv_32"
7304 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
7305 (match_operand:SI 1 "uint5_operand" "")
7306 (match_operand:SI 2 "uint5_operand" ""))
7307 (match_operand:SI 3 "arith5_operand" "r,L"))]
7310 {dep|depw} %3,%2+%1-1,%1,%0
7311 {depi|depwi} %3,%2+%1-1,%1,%0"
7312 [(set_attr "type" "shift,shift")
7313 (set_attr "length" "4,4")])
7315 ;; Optimize insertion of const_int values of type 1...1xxxx.
7317 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
7318 (match_operand:SI 1 "uint5_operand" "")
7319 (match_operand:SI 2 "uint5_operand" ""))
7320 (match_operand:SI 3 "const_int_operand" ""))]
7321 "(INTVAL (operands[3]) & 0x10) != 0 &&
7322 (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
7325 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
7326 return \"{depi|depwi} %3,%2+%1-1,%1,%0\";
7328 [(set_attr "type" "shift")
7329 (set_attr "length" "4")])
7331 (define_insn "insv_64"
7332 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r,r")
7333 (match_operand:DI 1 "uint32_operand" "")
7334 (match_operand:DI 2 "uint32_operand" ""))
7335 (match_operand:DI 3 "arith32_operand" "r,L"))]
7338 depd %3,%2+%1-1,%1,%0
7339 depdi %3,%2+%1-1,%1,%0"
7340 [(set_attr "type" "shift,shift")
7341 (set_attr "length" "4,4")])
7343 ;; Optimize insertion of const_int values of type 1...1xxxx.
7345 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+r")
7346 (match_operand:DI 1 "uint32_operand" "")
7347 (match_operand:DI 2 "uint32_operand" ""))
7348 (match_operand:DI 3 "const_int_operand" ""))]
7349 "(INTVAL (operands[3]) & 0x10) != 0
7351 && (~INTVAL (operands[3]) & ((1L << INTVAL (operands[1])) - 1) & ~0xf) == 0"
7354 operands[3] = GEN_INT ((INTVAL (operands[3]) & 0xf) - 0x10);
7355 return \"depdi %3,%2+%1-1,%1,%0\";
7357 [(set_attr "type" "shift")
7358 (set_attr "length" "4")])
7361 [(set (match_operand:DI 0 "register_operand" "=r")
7362 (ashift:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "r"))
7365 "depd,z %1,31,32,%0"
7366 [(set_attr "type" "shift")
7367 (set_attr "length" "4")])
7369 ;; This insn is used for some loop tests, typically loops reversed when
7370 ;; strength reduction is used. It is actually created when the instruction
7371 ;; combination phase combines the special loop test. Since this insn
7372 ;; is both a jump insn and has an output, it must deal with its own
7373 ;; reloads, hence the `m' constraints. The `!' constraints direct reload
7374 ;; to not choose the register alternatives in the event a reload is needed.
7375 (define_insn "decrement_and_branch_until_zero"
7378 (match_operator 2 "comparison_operator"
7380 (match_operand:SI 0 "reg_before_reload_operand" "+!r,!*f,*m")
7381 (match_operand:SI 1 "int5_operand" "L,L,L"))
7383 (label_ref (match_operand 3 "" ""))
7386 (plus:SI (match_dup 0) (match_dup 1)))
7387 (clobber (match_scratch:SI 4 "=X,r,r"))]
7389 "* return output_dbra (operands, insn, which_alternative); "
7390 ;; Do not expect to understand this the first time through.
7391 [(set_attr "type" "cbranch,multi,multi")
7392 (set (attr "length")
7393 (if_then_else (eq_attr "alternative" "0")
7394 ;; Loop counter in register case
7395 ;; Short branch has length of 4
7396 ;; Long branch has length of 8
7397 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7402 ;; Loop counter in FP reg case.
7403 ;; Extra goo to deal with additional reload insns.
7404 (if_then_else (eq_attr "alternative" "1")
7405 (if_then_else (lt (match_dup 3) (pc))
7407 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
7412 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7416 ;; Loop counter in memory case.
7417 ;; Extra goo to deal with additional reload insns.
7418 (if_then_else (lt (match_dup 3) (pc))
7420 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7425 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7428 (const_int 16))))))])
7433 (match_operator 2 "movb_comparison_operator"
7434 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
7435 (label_ref (match_operand 3 "" ""))
7437 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
7440 "* return output_movb (operands, insn, which_alternative, 0); "
7441 ;; Do not expect to understand this the first time through.
7442 [(set_attr "type" "cbranch,multi,multi,multi")
7443 (set (attr "length")
7444 (if_then_else (eq_attr "alternative" "0")
7445 ;; Loop counter in register case
7446 ;; Short branch has length of 4
7447 ;; Long branch has length of 8
7448 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7453 ;; Loop counter in FP reg case.
7454 ;; Extra goo to deal with additional reload insns.
7455 (if_then_else (eq_attr "alternative" "1")
7456 (if_then_else (lt (match_dup 3) (pc))
7458 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7463 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7467 ;; Loop counter in memory or sar case.
7468 ;; Extra goo to deal with additional reload insns.
7470 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7473 (const_int 12)))))])
7475 ;; Handle negated branch.
7479 (match_operator 2 "movb_comparison_operator"
7480 [(match_operand:SI 1 "register_operand" "r,r,r,r") (const_int 0)])
7482 (label_ref (match_operand 3 "" ""))))
7483 (set (match_operand:SI 0 "reg_before_reload_operand" "=!r,!*f,*m,!*q")
7486 "* return output_movb (operands, insn, which_alternative, 1); "
7487 ;; Do not expect to understand this the first time through.
7488 [(set_attr "type" "cbranch,multi,multi,multi")
7489 (set (attr "length")
7490 (if_then_else (eq_attr "alternative" "0")
7491 ;; Loop counter in register case
7492 ;; Short branch has length of 4
7493 ;; Long branch has length of 8
7494 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7499 ;; Loop counter in FP reg case.
7500 ;; Extra goo to deal with additional reload insns.
7501 (if_then_else (eq_attr "alternative" "1")
7502 (if_then_else (lt (match_dup 3) (pc))
7504 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
7509 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7513 ;; Loop counter in memory or SAR case.
7514 ;; Extra goo to deal with additional reload insns.
7516 (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7519 (const_int 12)))))])
7522 [(set (pc) (label_ref (match_operand 3 "" "" )))
7523 (set (match_operand:SI 0 "ireg_operand" "=r")
7524 (plus:SI (match_operand:SI 1 "ireg_operand" "r")
7525 (match_operand:SI 2 "ireg_or_int5_operand" "rL")))]
7526 "(reload_completed && operands[0] == operands[1]) || operands[0] == operands[2]"
7529 return output_parallel_addb (operands, get_attr_length (insn));
7531 [(set_attr "type" "parallel_branch")
7532 (set (attr "length")
7533 (if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
7539 [(set (pc) (label_ref (match_operand 2 "" "" )))
7540 (set (match_operand:SF 0 "ireg_operand" "=r")
7541 (match_operand:SF 1 "ireg_or_int5_operand" "rL"))]
7545 return output_parallel_movb (operands, get_attr_length (insn));
7547 [(set_attr "type" "parallel_branch")
7548 (set (attr "length")
7549 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7555 [(set (pc) (label_ref (match_operand 2 "" "" )))
7556 (set (match_operand:SI 0 "ireg_operand" "=r")
7557 (match_operand:SI 1 "ireg_or_int5_operand" "rL"))]
7561 return output_parallel_movb (operands, get_attr_length (insn));
7563 [(set_attr "type" "parallel_branch")
7564 (set (attr "length")
7565 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7571 [(set (pc) (label_ref (match_operand 2 "" "" )))
7572 (set (match_operand:HI 0 "ireg_operand" "=r")
7573 (match_operand:HI 1 "ireg_or_int5_operand" "rL"))]
7577 return output_parallel_movb (operands, get_attr_length (insn));
7579 [(set_attr "type" "parallel_branch")
7580 (set (attr "length")
7581 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7587 [(set (pc) (label_ref (match_operand 2 "" "" )))
7588 (set (match_operand:QI 0 "ireg_operand" "=r")
7589 (match_operand:QI 1 "ireg_or_int5_operand" "rL"))]
7593 return output_parallel_movb (operands, get_attr_length (insn));
7595 [(set_attr "type" "parallel_branch")
7596 (set (attr "length")
7597 (if_then_else (lt (abs (minus (match_dup 2) (plus (pc) (const_int 8))))
7603 [(set (match_operand 0 "register_operand" "=f")
7604 (mult (match_operand 1 "register_operand" "f")
7605 (match_operand 2 "register_operand" "f")))
7606 (set (match_operand 3 "register_operand" "+f")
7607 (plus (match_operand 4 "register_operand" "f")
7608 (match_operand 5 "register_operand" "f")))]
7609 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7610 && reload_completed && fmpyaddoperands (operands)"
7613 if (GET_MODE (operands[0]) == DFmode)
7615 if (rtx_equal_p (operands[3], operands[5]))
7616 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7618 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7622 if (rtx_equal_p (operands[3], operands[5]))
7623 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7625 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7628 [(set_attr "type" "fpalu")
7629 (set_attr "length" "4")])
7632 [(set (match_operand 3 "register_operand" "+f")
7633 (plus (match_operand 4 "register_operand" "f")
7634 (match_operand 5 "register_operand" "f")))
7635 (set (match_operand 0 "register_operand" "=f")
7636 (mult (match_operand 1 "register_operand" "f")
7637 (match_operand 2 "register_operand" "f")))]
7638 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7639 && reload_completed && fmpyaddoperands (operands)"
7642 if (GET_MODE (operands[0]) == DFmode)
7644 if (rtx_equal_p (operands[3], operands[5]))
7645 return \"fmpyadd,dbl %1,%2,%0,%4,%3\";
7647 return \"fmpyadd,dbl %1,%2,%0,%5,%3\";
7651 if (rtx_equal_p (operands[3], operands[5]))
7652 return \"fmpyadd,sgl %1,%2,%0,%4,%3\";
7654 return \"fmpyadd,sgl %1,%2,%0,%5,%3\";
7657 [(set_attr "type" "fpalu")
7658 (set_attr "length" "4")])
7661 [(set (match_operand 0 "register_operand" "=f")
7662 (mult (match_operand 1 "register_operand" "f")
7663 (match_operand 2 "register_operand" "f")))
7664 (set (match_operand 3 "register_operand" "+f")
7665 (minus (match_operand 4 "register_operand" "f")
7666 (match_operand 5 "register_operand" "f")))]
7667 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7668 && reload_completed && fmpysuboperands (operands)"
7671 if (GET_MODE (operands[0]) == DFmode)
7672 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7674 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7676 [(set_attr "type" "fpalu")
7677 (set_attr "length" "4")])
7680 [(set (match_operand 3 "register_operand" "+f")
7681 (minus (match_operand 4 "register_operand" "f")
7682 (match_operand 5 "register_operand" "f")))
7683 (set (match_operand 0 "register_operand" "=f")
7684 (mult (match_operand 1 "register_operand" "f")
7685 (match_operand 2 "register_operand" "f")))]
7686 "TARGET_PA_11 && ! TARGET_SOFT_FLOAT
7687 && reload_completed && fmpysuboperands (operands)"
7690 if (GET_MODE (operands[0]) == DFmode)
7691 return \"fmpysub,dbl %1,%2,%0,%5,%3\";
7693 return \"fmpysub,sgl %1,%2,%0,%5,%3\";
7695 [(set_attr "type" "fpalu")
7696 (set_attr "length" "4")])
7698 ;; Clean up turds left by reload.
7700 [(set (match_operand 0 "reg_or_nonsymb_mem_operand" "")
7701 (match_operand 1 "register_operand" "fr"))
7702 (set (match_operand 2 "register_operand" "fr")
7704 "! TARGET_SOFT_FLOAT
7705 && GET_CODE (operands[0]) == MEM
7706 && ! MEM_VOLATILE_P (operands[0])
7707 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7708 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7709 && GET_MODE (operands[0]) == DFmode
7710 && GET_CODE (operands[1]) == REG
7711 && GET_CODE (operands[2]) == REG
7712 && ! side_effects_p (XEXP (operands[0], 0))
7713 && REGNO_REG_CLASS (REGNO (operands[1]))
7714 == REGNO_REG_CLASS (REGNO (operands[2]))"
7719 if (FP_REG_P (operands[1]))
7720 output_asm_insn (output_fp_move_double (operands), operands);
7722 output_asm_insn (output_move_double (operands), operands);
7724 if (rtx_equal_p (operands[1], operands[2]))
7727 xoperands[0] = operands[2];
7728 xoperands[1] = operands[1];
7730 if (FP_REG_P (xoperands[1]))
7731 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7733 output_asm_insn (output_move_double (xoperands), xoperands);
7739 [(set (match_operand 0 "register_operand" "fr")
7740 (match_operand 1 "reg_or_nonsymb_mem_operand" ""))
7741 (set (match_operand 2 "register_operand" "fr")
7743 "! TARGET_SOFT_FLOAT
7744 && GET_CODE (operands[1]) == MEM
7745 && ! MEM_VOLATILE_P (operands[1])
7746 && GET_MODE (operands[0]) == GET_MODE (operands[1])
7747 && GET_MODE (operands[0]) == GET_MODE (operands[2])
7748 && GET_MODE (operands[0]) == DFmode
7749 && GET_CODE (operands[0]) == REG
7750 && GET_CODE (operands[2]) == REG
7751 && ! side_effects_p (XEXP (operands[1], 0))
7752 && REGNO_REG_CLASS (REGNO (operands[0]))
7753 == REGNO_REG_CLASS (REGNO (operands[2]))"
7758 if (FP_REG_P (operands[0]))
7759 output_asm_insn (output_fp_move_double (operands), operands);
7761 output_asm_insn (output_move_double (operands), operands);
7763 xoperands[0] = operands[2];
7764 xoperands[1] = operands[0];
7766 if (FP_REG_P (xoperands[1]))
7767 output_asm_insn (output_fp_move_double (xoperands), xoperands);
7769 output_asm_insn (output_move_double (xoperands), xoperands);
7774 ;; Flush the I and D cache line found at the address in operand 0.
7775 ;; This is used by the trampoline code for nested functions.
7776 ;; So long as the trampoline itself is less than 32 bytes this
7779 (define_insn "dcacheflush"
7780 [(unspec_volatile [(const_int 1)] 0)
7781 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7782 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))]
7784 "fdc 0(%0)\;fdc 0(%1)\;sync"
7785 [(set_attr "type" "multi")
7786 (set_attr "length" "12")])
7788 (define_insn "icacheflush"
7789 [(unspec_volatile [(const_int 2)] 0)
7790 (use (mem:SI (match_operand 0 "pmode_register_operand" "r")))
7791 (use (mem:SI (match_operand 1 "pmode_register_operand" "r")))
7792 (use (match_operand 2 "pmode_register_operand" "r"))
7793 (clobber (match_operand 3 "pmode_register_operand" "=&r"))
7794 (clobber (match_operand 4 "pmode_register_operand" "=&r"))]
7796 "mfsp %%sr0,%4\;ldsid (%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
7797 [(set_attr "type" "multi")
7798 (set_attr "length" "52")])
7800 ;; An out-of-line prologue.
7801 (define_insn "outline_prologue_call"
7802 [(unspec_volatile [(const_int 0)] 0)
7803 (clobber (reg:SI 31))
7804 (clobber (reg:SI 22))
7805 (clobber (reg:SI 21))
7806 (clobber (reg:SI 20))
7807 (clobber (reg:SI 19))
7808 (clobber (reg:SI 1))]
7812 extern int frame_pointer_needed;
7814 /* We need two different versions depending on whether or not we
7815 need a frame pointer. Also note that we return to the instruction
7816 immediately after the branch rather than two instructions after the
7817 break as normally is the case. */
7818 if (frame_pointer_needed)
7820 /* Must import the magic millicode routine(s). */
7821 output_asm_insn (\".IMPORT __outline_prologue_fp,MILLICODE\", NULL);
7823 if (TARGET_PORTABLE_RUNTIME)
7825 output_asm_insn (\"ldil L'__outline_prologue_fp,%%r31\", NULL);
7826 output_asm_insn (\"ble,n R'__outline_prologue_fp(%%sr0,%%r31)\",
7830 output_asm_insn (\"{bl|b,l},n __outline_prologue_fp,%%r31\", NULL);
7834 /* Must import the magic millicode routine(s). */
7835 output_asm_insn (\".IMPORT __outline_prologue,MILLICODE\", NULL);
7837 if (TARGET_PORTABLE_RUNTIME)
7839 output_asm_insn (\"ldil L'__outline_prologue,%%r31\", NULL);
7840 output_asm_insn (\"ble,n R'__outline_prologue(%%sr0,%%r31)\", NULL);
7843 output_asm_insn (\"{bl|b,l},n __outline_prologue,%%r31\", NULL);
7847 [(set_attr "type" "multi")
7848 (set_attr "length" "8")])
7850 ;; An out-of-line epilogue.
7851 (define_insn "outline_epilogue_call"
7852 [(unspec_volatile [(const_int 1)] 0)
7855 (clobber (reg:SI 31))
7856 (clobber (reg:SI 22))
7857 (clobber (reg:SI 21))
7858 (clobber (reg:SI 20))
7859 (clobber (reg:SI 19))
7860 (clobber (reg:SI 2))
7861 (clobber (reg:SI 1))]
7865 extern int frame_pointer_needed;
7867 /* We need two different versions depending on whether or not we
7868 need a frame pointer. Also note that we return to the instruction
7869 immediately after the branch rather than two instructions after the
7870 break as normally is the case. */
7871 if (frame_pointer_needed)
7873 /* Must import the magic millicode routine. */
7874 output_asm_insn (\".IMPORT __outline_epilogue_fp,MILLICODE\", NULL);
7876 /* The out-of-line prologue will make sure we return to the right
7878 if (TARGET_PORTABLE_RUNTIME)
7880 output_asm_insn (\"ldil L'__outline_epilogue_fp,%%r31\", NULL);
7881 output_asm_insn (\"ble,n R'__outline_epilogue_fp(%%sr0,%%r31)\",
7885 output_asm_insn (\"{bl|b,l},n __outline_epilogue_fp,%%r31\", NULL);
7889 /* Must import the magic millicode routine. */
7890 output_asm_insn (\".IMPORT __outline_epilogue,MILLICODE\", NULL);
7892 /* The out-of-line prologue will make sure we return to the right
7894 if (TARGET_PORTABLE_RUNTIME)
7896 output_asm_insn (\"ldil L'__outline_epilogue,%%r31\", NULL);
7897 output_asm_insn (\"ble,n R'__outline_epilogue(%%sr0,%%r31)\", NULL);
7900 output_asm_insn (\"{bl|b,l},n __outline_epilogue,%%r31\", NULL);
7904 [(set_attr "type" "multi")
7905 (set_attr "length" "8")])
7907 ;; Given a function pointer, canonicalize it so it can be
7908 ;; reliably compared to another function pointer. */
7909 (define_expand "canonicalize_funcptr_for_compare"
7910 [(set (reg:SI 26) (match_operand:SI 1 "register_operand" ""))
7911 (parallel [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7912 (clobber (match_dup 2))
7913 (clobber (reg:SI 26))
7914 (clobber (reg:SI 22))
7915 (clobber (reg:SI 31))])
7916 (set (match_operand:SI 0 "register_operand" "")
7918 "!TARGET_PORTABLE_RUNTIME && !TARGET_64BIT"
7923 rtx canonicalize_funcptr_for_compare_libfunc
7924 = init_one_libfunc (CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL);
7926 emit_library_call_value (canonicalize_funcptr_for_compare_libfunc,
7927 operands[0], LCT_NORMAL, Pmode,
7928 1, operands[1], Pmode);
7932 operands[2] = gen_reg_rtx (SImode);
7933 if (GET_CODE (operands[1]) != REG)
7935 rtx tmp = gen_reg_rtx (Pmode);
7936 emit_move_insn (tmp, operands[1]);
7942 [(set (reg:SI 29) (unspec:SI [(reg:SI 26)] 0))
7943 (clobber (match_operand:SI 0 "register_operand" "=a"))
7944 (clobber (reg:SI 26))
7945 (clobber (reg:SI 22))
7946 (clobber (reg:SI 31))]
7950 int length = get_attr_length (insn);
7953 xoperands[0] = GEN_INT (length - 8);
7954 xoperands[1] = GEN_INT (length - 16);
7956 /* Must import the magic millicode routine. */
7957 output_asm_insn (\".IMPORT $$sh_func_adrs,MILLICODE\", NULL);
7959 /* This is absolutely amazing.
7961 First, copy our input parameter into %r29 just in case we don't
7962 need to call $$sh_func_adrs. */
7963 output_asm_insn (\"copy %%r26,%%r29\", NULL);
7964 output_asm_insn (\"{extru|extrw,u} %%r26,31,2,%%r31\", NULL);
7966 /* Next, examine the low two bits in %r26, if they aren't 0x2, then
7967 we use %r26 unchanged. */
7968 output_asm_insn (\"{comib|cmpib},<>,n 2,%%r31,.+%0\", xoperands);
7969 output_asm_insn (\"ldi 4096,%%r31\", NULL);
7971 /* Next, compare %r26 with 4096, if %r26 is less than or equal to
7972 4096, then again we use %r26 unchanged. */
7973 output_asm_insn (\"{comb|cmpb},<<,n %%r26,%%r31,.+%1\", xoperands);
7975 /* Finally, call $$sh_func_adrs to extract the function's real add24. */
7976 return output_millicode_call (insn,
7977 gen_rtx_SYMBOL_REF (SImode,
7978 \"$$sh_func_adrs\"));
7980 [(set_attr "type" "multi")
7981 (set (attr "length")
7982 (plus (symbol_ref "attr_length_millicode_call (insn)")
7985 ;; On the PA, the PIC register is call clobbered, so it must
7986 ;; be saved & restored around calls by the caller. If the call
7987 ;; doesn't return normally (nonlocal goto, or an exception is
7988 ;; thrown), then the code at the exception handler label must
7989 ;; restore the PIC register.
7990 (define_expand "exception_receiver"
7995 /* On the 64-bit port, we need a blockage because there is
7996 confusion regarding the dependence of the restore on the
7997 frame pointer. As a result, the frame pointer and pic
7998 register restores sometimes are interchanged erroneously. */
8000 emit_insn (gen_blockage ());
8001 /* Restore the PIC register using hppa_pic_save_rtx (). The
8002 PIC register is not saved in the frame in 64-bit ABI. */
8003 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
8004 emit_insn (gen_blockage ());
8008 (define_expand "builtin_setjmp_receiver"
8009 [(label_ref (match_operand 0 "" ""))]
8014 emit_insn (gen_blockage ());
8015 /* Restore the PIC register. Hopefully, this will always be from
8016 a stack slot. The only registers that are valid after a
8017 builtin_longjmp are the stack and frame pointers. */
8018 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
8019 emit_insn (gen_blockage ());
8023 ;; Allocate new stack space and update the saved stack pointer in the
8024 ;; frame marker. The HP C compilers also copy additional words in the
8025 ;; frame marker. The 64-bit compiler copies words at -48, -32 and -24.
8026 ;; The 32-bit compiler copies the word at -16 (Static Link). We
8027 ;; currently don't copy these values.
8029 ;; Since the copy of the frame marker can't be done atomically, I
8030 ;; suspect that using it for unwind purposes may be somewhat unreliable.
8031 ;; The HP compilers appear to raise the stack and copy the frame
8032 ;; marker in a strict instruction sequence. This suggests that the
8033 ;; unwind library may check for an alloca sequence when ALLOCA_FRAME
8034 ;; is set in the callinfo data. We currently don't set ALLOCA_FRAME
8035 ;; as GAS doesn't support it, or try to keep the instructions emitted
8036 ;; here in strict sequence.
8037 (define_expand "allocate_stack"
8038 [(match_operand 0 "" "")
8039 (match_operand 1 "" "")]
8043 /* Since the stack grows upward, we need to store virtual_stack_dynamic_rtx
8044 in operand 0 before adjusting the stack. */
8045 emit_move_insn (operands[0], virtual_stack_dynamic_rtx);
8046 anti_adjust_stack (operands[1]);
8047 if (TARGET_HPUX_UNWIND_LIBRARY)
8049 rtx dst = gen_rtx_MEM (word_mode,
8050 gen_rtx_PLUS (word_mode, stack_pointer_rtx,
8051 GEN_INT (TARGET_64BIT ? -8 : -4)));
8053 emit_move_insn (dst, frame_pointer_rtx);