1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* For -mschedule= option. */
49 extern enum processor_type pa_cpu;
51 /* For -munix= option. */
52 extern int flag_pa_unix;
54 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
56 /* Print subsidiary information on the compiler version in use. */
58 #define TARGET_VERSION fputs (" (hppa)", stderr);
60 #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
62 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
64 #define TARGET_64BIT 0
67 /* Generate code for ELF32 ABI. */
69 #define TARGET_ELF32 0
72 /* Generate code for SOM 32bit ABI. */
77 /* HP-UX UNIX features. */
82 /* HP-UX 10.10 UNIX 95 features. */
83 #ifndef TARGET_HPUX_10_10
84 #define TARGET_HPUX_10_10 0
87 /* HP-UX 11i multibyte and UNIX 98 extensions. */
88 #ifndef TARGET_HPUX_11_11
89 #define TARGET_HPUX_11_11 0
92 /* The following three defines are potential target switches. The current
93 defines are optimal given the current capabilities of GAS and GNU ld. */
95 /* Define to a C expression evaluating to true to use long absolute calls.
96 Currently, only the HP assembler and SOM linker support long absolute
97 calls. They are used only in non-pic code. */
98 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
100 /* Define to a C expression evaluating to true to use long pic symbol
101 difference calls. This is a call variant similar to the long pic
102 pc-relative call. Long pic symbol difference calls are only used with
103 the HP SOM linker. Currently, only the HP assembler supports these
104 calls. GAS doesn't allow an arbitrary difference of two symbols. */
105 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
107 /* Define to a C expression evaluating to true to use long pic
108 pc-relative calls. Long pic pc-relative calls are only used with
109 GAS. Currently, they are usable for calls within a module but
110 not for external calls. */
111 #define TARGET_LONG_PIC_PCREL_CALL 0
113 /* Define to a C expression evaluating to true to use SOM secondary
114 definition symbols for weak support. Linker support for secondary
115 definition symbols is buggy prior to HP-UX 11.X. */
116 #define TARGET_SOM_SDEF 0
118 /* Define to a C expression evaluating to true to save the entry value
119 of SP in the current frame marker. This is normally unnecessary.
120 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
121 HP compilers don't use this flag but it is supported by the assembler.
122 We set this flag to indicate that register %r3 has been saved at the
123 start of the frame. Thus, when the HP unwind library is used, we
124 need to generate additional code to save SP into the frame marker. */
125 #define TARGET_HPUX_UNWIND_LIBRARY 0
127 #ifndef TARGET_DEFAULT
128 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
131 #ifndef TARGET_CPU_DEFAULT
132 #define TARGET_CPU_DEFAULT 0
135 #ifndef TARGET_SCHED_DEFAULT
136 #define TARGET_SCHED_DEFAULT PROCESSOR_8000
139 /* Support for a compile-time default CPU, et cetera. The rules are:
140 --with-schedule is ignored if -mschedule is specified.
141 --with-arch is ignored if -march is specified. */
142 #define OPTION_DEFAULT_SPECS \
143 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
144 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
146 /* Specify the dialect of assembler to use. New mnemonics is dialect one
147 and the old mnemonics are dialect zero. */
148 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
150 #define OVERRIDE_OPTIONS override_options ()
152 /* Override some settings from dbxelf.h. */
154 /* We do not have to be compatible with dbx, so we enable gdb extensions
156 #define DEFAULT_GDB_EXTENSIONS 1
158 /* This used to be zero (no max length), but big enums and such can
159 cause huge strings which killed gas.
161 We also have to avoid lossage in dbxout.c -- it does not compute the
162 string size accurately, so we are real conservative here. */
163 #undef DBX_CONTIN_LENGTH
164 #define DBX_CONTIN_LENGTH 3000
166 /* GDB always assumes the current function's frame begins at the value
167 of the stack pointer upon entry to the current function. Accessing
168 local variables and parameters passed on the stack is done using the
169 base of the frame + an offset provided by GCC.
171 For functions which have frame pointers this method works fine;
172 the (frame pointer) == (stack pointer at function entry) and GCC provides
173 an offset relative to the frame pointer.
175 This loses for functions without a frame pointer; GCC provides an offset
176 which is relative to the stack pointer after adjusting for the function's
177 frame size. GDB would prefer the offset to be relative to the value of
178 the stack pointer at the function's entry. Yuk! */
179 #define DEBUGGER_AUTO_OFFSET(X) \
180 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
181 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
183 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
184 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
185 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
187 #define TARGET_CPU_CPP_BUILTINS() \
189 builtin_assert("cpu=hppa"); \
190 builtin_assert("machine=hppa"); \
191 builtin_define("__hppa"); \
192 builtin_define("__hppa__"); \
194 builtin_define("_PA_RISC2_0"); \
195 else if (TARGET_PA_11) \
196 builtin_define("_PA_RISC1_1"); \
198 builtin_define("_PA_RISC1_0"); \
201 /* An old set of OS defines for various BSD-like systems. */
202 #define TARGET_OS_CPP_BUILTINS() \
205 builtin_define_std ("REVARGV"); \
206 builtin_define_std ("hp800"); \
207 builtin_define_std ("hp9000"); \
208 builtin_define_std ("hp9k8"); \
209 if (!c_dialect_cxx () && !flag_iso) \
210 builtin_define ("hppa"); \
211 builtin_define_std ("spectrum"); \
212 builtin_define_std ("unix"); \
213 builtin_assert ("system=bsd"); \
214 builtin_assert ("system=unix"); \
218 #define CC1_SPEC "%{pg:} %{p:}"
220 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
222 /* We don't want -lg. */
224 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
227 /* This macro defines command-line switches that modify the default
230 The definition is be an initializer for an array of structures. Each
231 array element has have three elements: the switch name, one of the
232 enumeration codes ADD or DELETE to indicate whether the string should be
233 inserted or deleted, and the string to be inserted or deleted. */
234 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
236 /* Make gcc agree with <machine/ansi.h> */
238 #define SIZE_TYPE "unsigned int"
239 #define PTRDIFF_TYPE "int"
240 #define WCHAR_TYPE "unsigned int"
241 #define WCHAR_TYPE_SIZE 32
243 /* Show we can debug even without a frame pointer. */
244 #define CAN_DEBUG_WITHOUT_FP
246 /* target machine storage layout */
247 typedef struct machine_function GTY(())
249 /* Flag indicating that a .NSUBSPA directive has been output for
254 /* Define this macro if it is advisable to hold scalars in registers
255 in a wider mode than that declared by the program. In such cases,
256 the value is constrained to be within the bounds of the declared
257 type, but kept valid in the wider mode. The signedness of the
258 extension may differ from that of the type. */
260 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
261 if (GET_MODE_CLASS (MODE) == MODE_INT \
262 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
265 /* Define this if most significant bit is lowest numbered
266 in instructions that operate on numbered bit-fields. */
267 #define BITS_BIG_ENDIAN 1
269 /* Define this if most significant byte of a word is the lowest numbered. */
270 /* That is true on the HP-PA. */
271 #define BYTES_BIG_ENDIAN 1
273 /* Define this if most significant word of a multiword number is lowest
275 #define WORDS_BIG_ENDIAN 1
277 #define MAX_BITS_PER_WORD 64
279 /* Width of a word, in units (bytes). */
280 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
282 /* Minimum number of units in a word. If this is undefined, the default
283 is UNITS_PER_WORD. Otherwise, it is the constant value that is the
284 smallest value that UNITS_PER_WORD can have at run-time.
286 FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
287 building of various TImode routines in libgcc. The HP runtime
288 specification doesn't provide the alignment requirements and calling
289 conventions for TImode variables. */
290 #define MIN_UNITS_PER_WORD 4
292 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
293 #define PARM_BOUNDARY BITS_PER_WORD
295 /* Largest alignment required for any stack parameter, in bits.
296 Don't define this if it is equal to PARM_BOUNDARY */
297 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
299 /* Boundary (in *bits*) on which stack pointer is always aligned;
300 certain optimizations in combine depend on this.
302 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
303 the stack on the 32 and 64-bit ports, respectively. However, we
304 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
305 in main. Thus, we treat the former as the preferred alignment. */
306 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
307 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
309 /* Allocation boundary (in *bits*) for the code of a function. */
310 #define FUNCTION_BOUNDARY BITS_PER_WORD
312 /* Alignment of field after `int : 0' in a structure. */
313 #define EMPTY_FIELD_BOUNDARY 32
315 /* Every structure's size must be a multiple of this. */
316 #define STRUCTURE_SIZE_BOUNDARY 8
318 /* A bit-field declared as `int' forces `int' alignment for the struct. */
319 #define PCC_BITFIELD_TYPE_MATTERS 1
321 /* No data type wants to be aligned rounder than this. */
322 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
324 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
325 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
326 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
328 /* Make arrays of chars word-aligned for the same reasons. */
329 #define DATA_ALIGNMENT(TYPE, ALIGN) \
330 (TREE_CODE (TYPE) == ARRAY_TYPE \
331 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
332 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
334 /* Set this nonzero if move instructions will actually fail to work
335 when given unaligned data. */
336 #define STRICT_ALIGNMENT 1
338 /* Value is 1 if it is a good idea to tie two pseudo registers
339 when one has mode MODE1 and one has mode MODE2.
340 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
341 for any hard reg, then this must be 0 for correct output. */
342 #define MODES_TIEABLE_P(MODE1, MODE2) \
343 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
345 /* Specify the registers used for certain standard purposes.
346 The values of these macros are register numbers. */
348 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
349 /* #define PC_REGNUM */
351 /* Register to use for pushing function arguments. */
352 #define STACK_POINTER_REGNUM 30
354 /* Base register for access to local variables of the function. */
355 #define FRAME_POINTER_REGNUM 3
357 /* Value should be nonzero if functions must have frame pointers. */
358 #define FRAME_POINTER_REQUIRED \
359 (current_function_calls_alloca)
361 /* C statement to store the difference between the frame pointer
362 and the stack pointer values immediately after the function prologue.
364 Note, we always pretend that this is a leaf function because if
365 it's not, there's no point in trying to eliminate the
366 frame pointer. If it is a leaf function, we guessed right! */
367 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
368 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
370 /* Base register for access to arguments of the function. */
371 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
373 /* Register in which static-chain is passed to a function. */
374 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
376 /* Register used to address the offset table for position-independent
378 #define PIC_OFFSET_TABLE_REGNUM \
379 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
381 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
383 /* Function to return the rtx used to save the pic offset table register
384 across function calls. */
385 extern struct rtx_def *hppa_pic_save_rtx (void);
387 #define DEFAULT_PCC_STRUCT_RETURN 0
389 /* Register in which address to store a structure value
390 is passed to a function. */
391 #define PA_STRUCT_VALUE_REGNUM 28
393 /* Describe how we implement __builtin_eh_return. */
394 #define EH_RETURN_DATA_REGNO(N) \
395 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
396 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
397 #define EH_RETURN_HANDLER_RTX \
398 gen_rtx_MEM (word_mode, \
399 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
400 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
403 /* Offset from the argument pointer register value to the top of
404 stack. This is different from FIRST_PARM_OFFSET because of the
406 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
408 /* The letters I, J, K, L and M in a register constraint string
409 can be used to stand for particular ranges of immediate operands.
410 This macro defines what the ranges are.
411 C is the letter, and VALUE is a constant value.
412 Return 1 if VALUE is in the range specified by C.
414 `I' is used for the 11 bit constants.
415 `J' is used for the 14 bit constants.
416 `K' is used for values that can be moved with a zdepi insn.
417 `L' is used for the 5 bit constants.
419 `N' is used for values with the least significant 11 bits equal to zero
420 and when sign extended from 32 to 64 bits the
421 value does not change.
422 `O' is used for numbers n such that n+1 is a power of 2.
425 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
426 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
427 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
428 : (C) == 'K' ? zdepi_cint_p (VALUE) \
429 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
430 : (C) == 'M' ? (VALUE) == 0 \
431 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
432 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
433 == (HOST_WIDE_INT) -1 << 31)) \
434 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
435 : (C) == 'P' ? and_mask_p (VALUE) \
438 /* Similar, but for floating or large integer constants, and defining letters
439 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
441 For PA, `G' is the floating-point constant zero. `H' is undefined. */
443 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
444 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
445 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
448 /* The class value for index registers, and the one for base regs. */
449 #define INDEX_REG_CLASS GENERAL_REGS
450 #define BASE_REG_CLASS GENERAL_REGS
452 #define FP_REG_CLASS_P(CLASS) \
453 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
455 /* True if register is floating-point. */
456 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
458 /* Given an rtx X being reloaded into a reg required to be
459 in class CLASS, return the class of reg to actually use.
460 In general this is just CLASS; but on some machines
461 in some cases it is preferable to use a more restrictive class. */
462 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
464 /* Return the register class of a scratch register needed to copy
465 IN into a register in CLASS in MODE, or a register in CLASS in MODE
466 to IN. If it can be done directly NO_REGS is returned.
468 Avoid doing any work for the common case calls. */
469 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
470 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
471 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
472 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
474 #define MAYBE_FP_REG_CLASS_P(CLASS) \
475 reg_classes_intersect_p ((CLASS), FP_REGS)
477 /* On the PA it is not possible to directly move data between
478 GENERAL_REGS and FP_REGS. */
479 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
480 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
481 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
483 /* Return the stack location to use for secondary memory needed reloads. */
484 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
485 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
488 /* Stack layout; function entry, exit and calling. */
490 /* Define this if pushing a word on the stack
491 makes the stack pointer a smaller address. */
492 /* #define STACK_GROWS_DOWNWARD */
494 /* Believe it or not. */
495 #define ARGS_GROW_DOWNWARD
497 /* Define this to non-zero if the nominal address of the stack frame
498 is at the high-address end of the local variables;
499 that is, each additional local variable allocated
500 goes at a more negative offset in the frame. */
501 #define FRAME_GROWS_DOWNWARD 0
503 /* Offset within stack frame to start allocating local variables at.
504 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
505 first local allocated. Otherwise, it is the offset to the BEGINNING
506 of the first local allocated.
508 On the 32-bit ports, we reserve one slot for the previous frame
509 pointer and one fill slot. The fill slot is for compatibility
510 with HP compiled programs. On the 64-bit ports, we reserve one
511 slot for the previous frame pointer. */
512 #define STARTING_FRAME_OFFSET 8
514 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
515 of the stack. The default is to align it to STACK_BOUNDARY. */
516 #define STACK_ALIGNMENT_NEEDED 0
518 /* If we generate an insn to push BYTES bytes,
519 this says how many the stack pointer really advances by.
520 On the HP-PA, don't define this because there are no push insns. */
521 /* #define PUSH_ROUNDING(BYTES) */
523 /* Offset of first parameter from the argument pointer register value.
524 This value will be negated because the arguments grow down.
525 Also note that on STACK_GROWS_UPWARD machines (such as this one)
526 this is the distance from the frame pointer to the end of the first
527 argument, not it's beginning. To get the real offset of the first
528 argument, the size of the argument must be added. */
530 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
532 /* When a parameter is passed in a register, stack space is still
534 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
536 /* Define this if the above stack space is to be considered part of the
537 space allocated by the caller. */
538 #define OUTGOING_REG_PARM_STACK_SPACE
540 /* Keep the stack pointer constant throughout the function.
541 This is both an optimization and a necessity: longjmp
542 doesn't behave itself when the stack pointer moves within
544 #define ACCUMULATE_OUTGOING_ARGS 1
546 /* The weird HPPA calling conventions require a minimum of 48 bytes on
547 the stack: 16 bytes for register saves, and 32 bytes for magic.
548 This is the difference between the logical top of stack and the
551 On the 64-bit port, the HP C compiler allocates a 48-byte frame
552 marker, although the runtime documentation only describes a 16
553 byte marker. For compatibility, we allocate 48 bytes. */
554 #define STACK_POINTER_OFFSET \
555 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
557 #define STACK_DYNAMIC_OFFSET(FNDECL) \
559 ? (STACK_POINTER_OFFSET) \
560 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
562 /* Value is 1 if returning from a function call automatically
563 pops the arguments described by the number-of-args field in the call.
564 FUNDECL is the declaration node of the function (as a tree),
565 FUNTYPE is the data type of the function (as a tree),
566 or for a library call it is an identifier node for the subroutine name. */
568 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
570 /* Define how to find the value returned by a function.
571 VALTYPE is the data type of the value (as a tree).
572 If the precise function being called is known, FUNC is its FUNCTION_DECL;
573 otherwise, FUNC is 0. */
575 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
577 /* Define how to find the value returned by a library function
578 assuming the value has mode MODE. */
580 #define LIBCALL_VALUE(MODE) \
582 (! TARGET_SOFT_FLOAT \
583 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
585 /* 1 if N is a possible register number for a function value
586 as seen by the caller. */
588 #define FUNCTION_VALUE_REGNO_P(N) \
589 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
592 /* Define a data type for recording info about an argument list
593 during the scan of that argument list. This data type should
594 hold all necessary information about the function itself
595 and about the args processed so far, enough to enable macros
596 such as FUNCTION_ARG to determine where the next arg should go.
598 On the HP-PA, the WORDS field holds the number of words
599 of arguments scanned so far (including the invisible argument,
600 if any, which holds the structure-value-address). Thus, 4 or
601 more means all following args should go on the stack.
603 The INCOMING field tracks whether this is an "incoming" or
606 The INDIRECT field indicates whether this is is an indirect
609 The NARGS_PROTOTYPE field indicates that an argument does not
610 have a prototype when it less than or equal to 0. */
612 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
614 #define CUMULATIVE_ARGS struct hppa_args
616 /* Initialize a variable CUM of type CUMULATIVE_ARGS
617 for a call to a function whose data type is FNTYPE.
618 For a library call, FNTYPE is 0. */
620 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
622 (CUM).incoming = 0, \
623 (CUM).indirect = (FNTYPE) && !(FNDECL), \
624 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
625 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
626 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
627 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
632 /* Similar, but when scanning the definition of a procedure. We always
633 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
635 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
637 (CUM).incoming = 1, \
638 (CUM).indirect = 0, \
639 (CUM).nargs_prototype = 1000
641 /* Figure out the size in words of the function argument. The size
642 returned by this macro should always be greater than zero because
643 we pass variable and zero sized objects by reference. */
645 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
646 ((((MODE) != BLKmode \
647 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
648 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
650 /* Update the data in CUM to advance over an argument
651 of mode MODE and data type TYPE.
652 (TYPE is null for libcalls where that information may not be available.) */
654 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
655 { (CUM).nargs_prototype--; \
656 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
657 + (((CUM).words & 01) && (TYPE) != 0 \
658 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
661 /* Determine where to put an argument to a function.
662 Value is zero to push the argument on the stack,
663 or a hard register in which to store the argument.
665 MODE is the argument's machine mode.
666 TYPE is the data type of the argument (as a tree).
667 This is null for libcalls where that information may
669 CUM is a variable of type CUMULATIVE_ARGS which gives info about
670 the preceding args and about the function being called.
671 NAMED is nonzero if this argument is a named parameter
672 (otherwise it is an extra parameter matching an ellipsis).
674 On the HP-PA the first four words of args are normally in registers
675 and the rest are pushed. But any arg that won't entirely fit in regs
678 Arguments passed in registers are either 1 or 2 words long.
680 The caller must make a distinction between calls to explicitly named
681 functions and calls through pointers to functions -- the conventions
682 are different! Calls through pointers to functions only use general
683 registers for the first four argument words.
685 Of course all this is different for the portable runtime model
686 HP wants everyone to use for ELF. Ugh. Here's a quick description
687 of how it's supposed to work.
689 1) callee side remains unchanged. It expects integer args to be
690 in the integer registers, float args in the float registers and
691 unnamed args in integer registers.
693 2) caller side now depends on if the function being called has
694 a prototype in scope (rather than if it's being called indirectly).
696 2a) If there is a prototype in scope, then arguments are passed
697 according to their type (ints in integer registers, floats in float
698 registers, unnamed args in integer registers.
700 2b) If there is no prototype in scope, then floating point arguments
701 are passed in both integer and float registers. egad.
703 FYI: The portable parameter passing conventions are almost exactly like
704 the standard parameter passing conventions on the RS6000. That's why
705 you'll see lots of similar code in rs6000.h. */
707 /* If defined, a C expression which determines whether, and in which
708 direction, to pad out an argument with extra space. */
709 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
711 /* Specify padding for the last element of a block move between registers
714 The 64-bit runtime specifies that objects need to be left justified
715 (i.e., the normal justification for a big endian target). The 32-bit
716 runtime specifies right justification for objects smaller than 64 bits.
717 We use a DImode register in the parallel for 5 to 7 byte structures
718 so that there is only one element. This allows the object to be
720 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
721 function_arg_padding ((MODE), (TYPE))
723 /* Do not expect to understand this without reading it several times. I'm
724 tempted to try and simply it, but I worry about breaking something. */
726 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
727 function_arg (&CUM, MODE, TYPE, NAMED)
729 /* If defined, a C expression that gives the alignment boundary, in
730 bits, of an argument with the specified mode and type. If it is
731 not defined, `PARM_BOUNDARY' is used for all arguments. */
733 /* Arguments larger than one word are double word aligned. */
735 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
737 ? (integer_zerop (TYPE_SIZE (TYPE)) \
738 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
739 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
740 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
741 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
744 extern GTY(()) rtx hppa_compare_op0;
745 extern GTY(()) rtx hppa_compare_op1;
746 extern enum cmp_type hppa_branch_type;
748 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
749 as assembly via FUNCTION_PROFILER. Just output a local label.
750 We can't use the function label because the GAS SOM target can't
751 handle the difference of a global symbol and a local symbol. */
753 #ifndef FUNC_BEGIN_PROLOG_LABEL
754 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
757 #define FUNCTION_PROFILER(FILE, LABEL) \
758 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
760 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
761 void hppa_profile_hook (int label_no);
763 /* The profile counter if emitted must come before the prologue. */
764 #define PROFILE_BEFORE_PROLOGUE 1
766 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
767 the stack pointer does not matter. The value is tested only in
768 functions that have frame pointers.
769 No definition is equivalent to always zero. */
771 extern int may_call_alloca;
773 #define EXIT_IGNORE_STACK \
774 (get_frame_size () != 0 \
775 || current_function_calls_alloca || current_function_outgoing_args_size)
777 /* Output assembler code for a block containing the constant parts
778 of a trampoline, leaving space for the variable parts.\
780 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
781 and then branches to the specified routine.
783 This code template is copied from text segment to stack location
784 and then patched with INITIALIZE_TRAMPOLINE to contain
785 valid values, and then entered as a subroutine.
787 It is best to keep this as small as possible to avoid having to
788 flush multiple lines in the cache. */
790 #define TRAMPOLINE_TEMPLATE(FILE) \
794 fputs ("\tldw 36(%r22),%r21\n", FILE); \
795 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
796 if (ASSEMBLER_DIALECT == 0) \
797 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
799 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
800 fputs ("\tldw 4(%r21),%r19\n", FILE); \
801 fputs ("\tldw 0(%r21),%r21\n", FILE); \
804 fputs ("\tbve (%r21)\n", FILE); \
805 fputs ("\tldw 40(%r22),%r29\n", FILE); \
806 fputs ("\t.word 0\n", FILE); \
807 fputs ("\t.word 0\n", FILE); \
811 fputs ("\tldsid (%r21),%r1\n", FILE); \
812 fputs ("\tmtsp %r1,%sr0\n", FILE); \
813 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
814 fputs ("\tldw 40(%r22),%r29\n", FILE); \
816 fputs ("\t.word 0\n", FILE); \
817 fputs ("\t.word 0\n", FILE); \
818 fputs ("\t.word 0\n", FILE); \
819 fputs ("\t.word 0\n", FILE); \
823 fputs ("\t.dword 0\n", FILE); \
824 fputs ("\t.dword 0\n", FILE); \
825 fputs ("\t.dword 0\n", FILE); \
826 fputs ("\t.dword 0\n", FILE); \
827 fputs ("\tmfia %r31\n", FILE); \
828 fputs ("\tldd 24(%r31),%r1\n", FILE); \
829 fputs ("\tldd 24(%r1),%r27\n", FILE); \
830 fputs ("\tldd 16(%r1),%r1\n", FILE); \
831 fputs ("\tbve (%r1)\n", FILE); \
832 fputs ("\tldd 32(%r31),%r31\n", FILE); \
833 fputs ("\t.dword 0 ; fptr\n", FILE); \
834 fputs ("\t.dword 0 ; static link\n", FILE); \
838 /* Length in units of the trampoline for entering a nested function. */
840 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
842 /* Length in units of the trampoline instruction code. */
844 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
846 /* Minimum length of a cache line. A length of 16 will work on all
847 PA-RISC processors. All PA 1.1 processors have a cache line of
848 32 bytes. Most but not all PA 2.0 processors have a cache line
849 of 64 bytes. As cache flushes are expensive and we don't support
850 PA 1.0, we use a minimum length of 32. */
852 #define MIN_CACHELINE_SIZE 32
854 /* Emit RTL insns to initialize the variable parts of a trampoline.
855 FNADDR is an RTX for the address of the function's pure code.
856 CXT is an RTX for the static chain value for the function.
858 Move the function address to the trampoline template at offset 36.
859 Move the static chain value to trampoline template at offset 40.
860 Move the trampoline address to trampoline template at offset 44.
861 Move r19 to trampoline template at offset 48. The latter two
862 words create a plabel for the indirect call to the trampoline.
864 A similar sequence is used for the 64-bit port but the plabel is
865 at the beginning of the trampoline.
867 Finally, the cache entries for the trampoline code are flushed.
868 This is necessary to ensure that the trampoline instruction sequence
869 is written to memory prior to any attempts at prefetching the code
872 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
874 rtx start_addr = gen_reg_rtx (Pmode); \
875 rtx end_addr = gen_reg_rtx (Pmode); \
876 rtx line_length = gen_reg_rtx (Pmode); \
881 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
882 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
883 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
884 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
886 /* Create a fat pointer for the trampoline. */ \
887 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
888 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
889 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
890 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
891 gen_rtx_REG (Pmode, 19)); \
893 /* fdc and fic only use registers for the address to flush, \
894 they do not accept integer displacements. We align the \
895 start and end addresses to the beginning of their respective \
896 cache lines to minimize the number of lines flushed. */ \
897 tmp = force_reg (Pmode, (TRAMP)); \
898 emit_insn (gen_andsi3 (start_addr, tmp, \
899 GEN_INT (-MIN_CACHELINE_SIZE))); \
900 tmp = force_reg (Pmode, \
901 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
902 emit_insn (gen_andsi3 (end_addr, tmp, \
903 GEN_INT (-MIN_CACHELINE_SIZE))); \
904 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
905 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
906 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
907 gen_reg_rtx (Pmode), \
908 gen_reg_rtx (Pmode))); \
912 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
913 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
914 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
915 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
917 /* Create a fat pointer for the trampoline. */ \
918 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
919 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
920 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
921 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
922 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
923 gen_rtx_REG (Pmode, 27)); \
925 /* fdc and fic only use registers for the address to flush, \
926 they do not accept integer displacements. We align the \
927 start and end addresses to the beginning of their respective \
928 cache lines to minimize the number of lines flushed. */ \
929 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
930 emit_insn (gen_anddi3 (start_addr, tmp, \
931 GEN_INT (-MIN_CACHELINE_SIZE))); \
932 tmp = force_reg (Pmode, \
933 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
934 emit_insn (gen_anddi3 (end_addr, tmp, \
935 GEN_INT (-MIN_CACHELINE_SIZE))); \
936 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
937 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
938 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
939 gen_reg_rtx (Pmode), \
940 gen_reg_rtx (Pmode))); \
944 /* Perform any machine-specific adjustment in the address of the trampoline.
945 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
946 Adjust the trampoline address to point to the plabel at offset 44. */
948 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
949 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
951 /* Implement `va_start' for varargs and stdarg. */
953 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
954 hppa_va_start (valist, nextarg)
956 /* Addressing modes, and classification of registers for them.
958 Using autoincrement addressing modes on PA8000 class machines is
961 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
962 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
964 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
965 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
967 /* Macros to check register numbers against specific register classes. */
969 /* The following macros assume that X is a hard or pseudo reg number.
970 They give nonzero only if X is a hard reg of the suitable class
971 or a pseudo reg currently allocated to a suitable hard reg.
972 Since they use reg_renumber, they are safe only once reg_renumber
973 has been allocated, which happens in local-alloc.c. */
975 #define REGNO_OK_FOR_INDEX_P(X) \
977 || (X >= FIRST_PSEUDO_REGISTER \
979 && (unsigned) reg_renumber[X] < 32)))
980 #define REGNO_OK_FOR_BASE_P(X) \
982 || (X >= FIRST_PSEUDO_REGISTER \
984 && (unsigned) reg_renumber[X] < 32)))
985 #define REGNO_OK_FOR_FP_P(X) \
987 || (X >= FIRST_PSEUDO_REGISTER \
989 && FP_REGNO_P (reg_renumber[X])))
991 /* Now macros that check whether X is a register and also,
992 strictly, whether it is in a specified class.
994 These macros are specific to the HP-PA, and may be used only
995 in code for printing assembler insns and in conditions for
996 define_optimization. */
998 /* 1 if X is an fp register. */
1000 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1002 /* Maximum number of registers that can appear in a valid memory address. */
1004 #define MAX_REGS_PER_ADDRESS 2
1006 /* Non-TLS symbolic references. */
1007 #define PA_SYMBOL_REF_TLS_P(RTX) \
1008 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
1010 /* Recognize any constant value that is a valid address except
1011 for symbolic addresses. We get better CSE by rejecting them
1012 here and allowing hppa_legitimize_address to break them up. We
1013 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1015 #define CONSTANT_ADDRESS_P(X) \
1016 ((GET_CODE (X) == LABEL_REF \
1017 || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
1018 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1019 || GET_CODE (X) == HIGH) \
1020 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1022 /* A C expression that is nonzero if we are using the new HP assembler. */
1024 #ifndef NEW_HP_ASSEMBLER
1025 #define NEW_HP_ASSEMBLER 0
1028 /* The macros below define the immediate range for CONST_INTS on
1029 the 64-bit port. Constants in this range can be loaded in three
1030 instructions using a ldil/ldo/depdi sequence. Constants outside
1031 this range are forced to the constant pool prior to reload. */
1033 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1034 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1035 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1036 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1038 /* A C expression that is nonzero if X is a legitimate constant for an
1041 We include all constant integers and constant doubles, but not
1042 floating-point, except for floating-point zero. We reject LABEL_REFs
1043 if we're not using gas or the new HP assembler.
1045 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1046 that need more than three instructions to load prior to reload. This
1047 limit is somewhat arbitrary. It takes three instructions to load a
1048 CONST_INT from memory but two are memory accesses. It may be better
1049 to increase the allowed range for CONST_INTS. We may also be able
1050 to handle CONST_DOUBLES. */
1052 #define LEGITIMATE_CONSTANT_P(X) \
1053 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1054 || (X) == CONST0_RTX (GET_MODE (X))) \
1055 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1056 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1057 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1058 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1059 || (reload_in_progress || reload_completed) \
1060 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1061 || cint_ok_for_move (INTVAL (X)))) \
1062 && !function_label_operand (X, VOIDmode))
1064 /* Target flags set on a symbol_ref. */
1066 /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
1067 #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
1068 #define SYMBOL_REF_REFERENCED_P(RTX) \
1069 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
1071 /* Subroutines for EXTRA_CONSTRAINT.
1073 Return 1 iff OP is a pseudo which did not get a hard register and
1074 we are running the reload pass. */
1075 #define IS_RELOADING_PSEUDO_P(OP) \
1076 ((reload_in_progress \
1077 && GET_CODE (OP) == REG \
1078 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1079 && reg_renumber [REGNO (OP)] < 0))
1081 /* Return 1 iff OP is a scaled or unscaled index address. */
1082 #define IS_INDEX_ADDR_P(OP) \
1083 (GET_CODE (OP) == PLUS \
1084 && GET_MODE (OP) == Pmode \
1085 && (GET_CODE (XEXP (OP, 0)) == MULT \
1086 || GET_CODE (XEXP (OP, 1)) == MULT \
1087 || (REG_P (XEXP (OP, 0)) \
1088 && REG_P (XEXP (OP, 1)))))
1090 /* Return 1 iff OP is a LO_SUM DLT address. */
1091 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1092 (GET_CODE (OP) == LO_SUM \
1093 && GET_MODE (OP) == Pmode \
1094 && REG_P (XEXP (OP, 0)) \
1095 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1096 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1098 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1100 `A' is a LO_SUM DLT memory operand.
1102 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1103 memory operand. Note that an unassigned pseudo register is such a
1104 memory operand. Needed because reload will generate these things
1105 and then not re-recognize the insn, causing constrain_operands to
1108 `R' is a scaled/unscaled indexed memory operand.
1110 `S' is the constant 31.
1112 `T' is for floating-point loads and stores.
1114 `U' is the constant 63.
1116 `W' is a register indirect memory operand. We could allow short
1117 displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
1118 long displacement is valid. This is only used for prefetch
1119 instructions with the `sl' completer. */
1121 #define EXTRA_CONSTRAINT(OP, C) \
1123 (IS_RELOADING_PSEUDO_P (OP) \
1124 || (GET_CODE (OP) == MEM \
1125 && (reload_in_progress \
1126 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1127 && !symbolic_memory_operand (OP, VOIDmode) \
1128 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1129 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1131 (GET_CODE (OP) == MEM \
1132 && REG_P (XEXP (OP, 0)) \
1133 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1135 (GET_CODE (OP) == MEM \
1136 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1138 (GET_CODE (OP) == MEM \
1139 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1141 (GET_CODE (OP) == MEM \
1142 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1143 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1144 /* Floating-point loads and stores are used to load \
1145 integer values as well as floating-point values. \
1146 They don't have the same set of REG+D address modes \
1147 as integer loads and stores. PA 1.x supports only \
1148 short displacements. PA 2.0 supports long displacements \
1149 but the base register needs to be aligned. \
1151 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1152 DFmode test the validity of an address for use in a \
1153 floating point load or store. So, we use SFmode/DFmode \
1154 to see if the address is valid for a floating-point \
1155 load/store operation. */ \
1156 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1161 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1163 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
1166 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1167 and check its validity for a certain class.
1168 We have two alternate definitions for each of them.
1169 The usual definition accepts all pseudo regs; the other rejects
1170 them unless they have been allocated suitable hard regs.
1171 The symbol REG_OK_STRICT causes the latter definition to be used.
1173 Most source files want to accept pseudo regs in the hope that
1174 they will get allocated to the class that the insn wants them to be in.
1175 Source files for reload pass need to be strict.
1176 After reload, it makes no difference, since pseudo regs have
1177 been eliminated by then. */
1179 #ifndef REG_OK_STRICT
1181 /* Nonzero if X is a hard reg that can be used as an index
1182 or if it is a pseudo reg. */
1183 #define REG_OK_FOR_INDEX_P(X) \
1184 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1185 /* Nonzero if X is a hard reg that can be used as a base reg
1186 or if it is a pseudo reg. */
1187 #define REG_OK_FOR_BASE_P(X) \
1188 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1192 /* Nonzero if X is a hard reg that can be used as an index. */
1193 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1194 /* Nonzero if X is a hard reg that can be used as a base reg. */
1195 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1199 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1200 valid memory address for an instruction. The MODE argument is the
1201 machine mode for the MEM expression that wants to use this address.
1203 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1204 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1205 available with floating point loads and stores, and integer loads.
1206 We get better code by allowing indexed addresses in the initial
1209 The acceptance of indexed addresses as legitimate implies that we
1210 must provide patterns for doing indexed integer stores, or the move
1211 expanders must force the address of an indexed store to a register.
1212 We have adopted the latter approach.
1214 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1215 the base register is a valid pointer for indexed instructions.
1216 On targets that have non-equivalent space registers, we have to
1217 know at the time of assembler output which register in a REG+REG
1218 pair is the base register. The REG_POINTER flag is sometimes lost
1219 in reload and the following passes, so it can't be relied on during
1220 code generation. Thus, we either have to canonicalize the order
1221 of the registers in REG+REG indexed addresses, or treat REG+REG
1222 addresses separately and provide patterns for both permutations.
1224 The latter approach requires several hundred additional lines of
1225 code in pa.md. The downside to canonicalizing is that a PLUS
1226 in the wrong order can't combine to form to make a scaled indexed
1227 memory operand. As we won't need to canonicalize the operands if
1228 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1230 We initially break out scaled indexed addresses in canonical order
1231 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1232 scaled indexed addresses during RTL generation. However, fold_rtx
1233 has its own opinion on how the operands of a PLUS should be ordered.
1234 If one of the operands is equivalent to a constant, it will make
1235 that operand the second operand. As the base register is likely to
1236 be equivalent to a SYMBOL_REF, we have made it the second operand.
1238 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1239 operands are in the order INDEX+BASE on targets with non-equivalent
1240 space registers, and in any order on targets with equivalent space
1241 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1243 We treat a SYMBOL_REF as legitimate if it is part of the current
1244 function's constant-pool, because such addresses can actually be
1245 output as REG+SMALLINT.
1247 Note we only allow 5 bit immediates for access to a constant address;
1248 doing so avoids losing for loading/storing a FP register at an address
1249 which will not fit in 5 bits. */
1251 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1252 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1254 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1255 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1257 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1258 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1260 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1261 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1263 #if HOST_BITS_PER_WIDE_INT > 32
1264 #define VAL_32_BITS_P(X) \
1265 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1266 < (unsigned HOST_WIDE_INT) 2 << 31)
1268 #define VAL_32_BITS_P(X) 1
1270 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1272 /* These are the modes that we allow for scaled indexing. */
1273 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1274 ((TARGET_64BIT && (MODE) == DImode) \
1275 || (MODE) == SImode \
1276 || (MODE) == HImode \
1277 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1279 /* These are the modes that we allow for unscaled indexing. */
1280 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1281 ((TARGET_64BIT && (MODE) == DImode) \
1282 || (MODE) == SImode \
1283 || (MODE) == HImode \
1284 || (MODE) == QImode \
1285 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1287 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1289 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1290 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1291 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1292 && REG_P (XEXP (X, 0)) \
1293 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1295 else if (GET_CODE (X) == PLUS) \
1297 rtx base = 0, index = 0; \
1298 if (REG_P (XEXP (X, 1)) \
1299 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1300 base = XEXP (X, 1), index = XEXP (X, 0); \
1301 else if (REG_P (XEXP (X, 0)) \
1302 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1303 base = XEXP (X, 0), index = XEXP (X, 1); \
1305 && GET_CODE (index) == CONST_INT \
1306 && ((INT_14_BITS (index) \
1307 && (((MODE) != DImode \
1308 && (MODE) != SFmode \
1309 && (MODE) != DFmode) \
1310 /* The base register for DImode loads and stores \
1311 with long displacements must be aligned because \
1312 the lower three bits in the displacement are \
1313 assumed to be zero. */ \
1314 || ((MODE) == DImode \
1316 || (INTVAL (index) % 8) == 0)) \
1317 /* Similarly, the base register for SFmode/DFmode \
1318 loads and stores with long displacements must \
1321 FIXME: the ELF32 linker clobbers the LSB of \
1322 the FP register number in PA 2.0 floating-point \
1323 insns with long displacements. This is because \
1324 R_PARISC_DPREL14WR and other relocations like \
1325 it are not supported. For now, we reject long \
1326 displacements on this target. */ \
1327 || (((MODE) == SFmode || (MODE) == DFmode) \
1328 && (TARGET_SOFT_FLOAT \
1331 && (INTVAL (index) \
1332 % GET_MODE_SIZE (MODE)) == 0))))) \
1333 || INT_5_BITS (index))) \
1335 if (!TARGET_DISABLE_INDEXING \
1336 /* Only accept the "canonical" INDEX+BASE operand order \
1337 on targets with non-equivalent space registers. */ \
1338 && (TARGET_NO_SPACE_REGS \
1339 ? (base && REG_P (index)) \
1340 : (base == XEXP (X, 1) && REG_P (index) \
1341 && (reload_completed \
1342 || (reload_in_progress && HARD_REGISTER_P (base)) \
1343 || REG_POINTER (base)) \
1344 && (reload_completed \
1345 || (reload_in_progress && HARD_REGISTER_P (index)) \
1346 || !REG_POINTER (index)))) \
1347 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1348 && REG_OK_FOR_INDEX_P (index) \
1349 && borx_reg_operand (base, Pmode) \
1350 && borx_reg_operand (index, Pmode)) \
1352 if (!TARGET_DISABLE_INDEXING \
1354 && GET_CODE (index) == MULT \
1355 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1356 && REG_P (XEXP (index, 0)) \
1357 && GET_MODE (XEXP (index, 0)) == Pmode \
1358 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1359 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1360 && INTVAL (XEXP (index, 1)) \
1361 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1362 && borx_reg_operand (base, Pmode)) \
1365 else if (GET_CODE (X) == LO_SUM \
1366 && GET_CODE (XEXP (X, 0)) == REG \
1367 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1368 && CONSTANT_P (XEXP (X, 1)) \
1369 && (TARGET_SOFT_FLOAT \
1370 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1373 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1374 || ((MODE) != SFmode \
1375 && (MODE) != DFmode))) \
1377 else if (GET_CODE (X) == LO_SUM \
1378 && GET_CODE (XEXP (X, 0)) == SUBREG \
1379 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1380 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1381 && CONSTANT_P (XEXP (X, 1)) \
1382 && (TARGET_SOFT_FLOAT \
1383 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1386 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1387 || ((MODE) != SFmode \
1388 && (MODE) != DFmode))) \
1390 else if (GET_CODE (X) == LABEL_REF \
1391 || (GET_CODE (X) == CONST_INT \
1392 && INT_5_BITS (X))) \
1394 /* Needed for -fPIC */ \
1395 else if (GET_CODE (X) == LO_SUM \
1396 && GET_CODE (XEXP (X, 0)) == REG \
1397 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1398 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1399 && (TARGET_SOFT_FLOAT \
1400 || (TARGET_PA_20 && !TARGET_ELF32) \
1401 || ((MODE) != SFmode \
1402 && (MODE) != DFmode))) \
1406 /* Look for machine dependent ways to make the invalid address AD a
1409 For the PA, transform:
1411 memory(X + <large int>)
1415 if (<large int> & mask) >= 16
1416 Y = (<large int> & ~mask) + mask + 1 Round up.
1418 Y = (<large int> & ~mask) Round down.
1420 memory (Z + (<large int> - Y));
1422 This makes reload inheritance and reload_cse work better since Z
1425 There may be more opportunities to improve code with this hook. */
1426 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1428 long offset, newoffset, mask; \
1429 rtx new, temp = NULL_RTX; \
1431 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1432 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1434 if (optimize && GET_CODE (AD) == PLUS) \
1435 temp = simplify_binary_operation (PLUS, Pmode, \
1436 XEXP (AD, 0), XEXP (AD, 1)); \
1438 new = temp ? temp : AD; \
1441 && GET_CODE (new) == PLUS \
1442 && GET_CODE (XEXP (new, 0)) == REG \
1443 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1445 offset = INTVAL (XEXP ((new), 1)); \
1447 /* Choose rounding direction. Round up if we are >= halfway. */ \
1448 if ((offset & mask) >= ((mask + 1) / 2)) \
1449 newoffset = (offset & ~mask) + mask + 1; \
1451 newoffset = offset & ~mask; \
1453 /* Ensure that long displacements are aligned. */ \
1454 if (!VAL_5_BITS_P (newoffset) \
1455 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1456 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1458 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1460 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1461 GEN_INT (newoffset)); \
1462 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1463 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1464 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1474 /* Try machine-dependent ways of modifying an illegitimate address
1475 to be legitimate. If we find one, return the new, valid address.
1476 This macro is used in only one place: `memory_address' in explow.c.
1478 OLDX is the address as it was before break_out_memory_refs was called.
1479 In some cases it is useful to look at this to decide what needs to be done.
1481 MODE and WIN are passed so that this macro can use
1482 GO_IF_LEGITIMATE_ADDRESS.
1484 It is always safe for this macro to do nothing. It exists to recognize
1485 opportunities to optimize the output. */
1487 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1488 { rtx orig_x = (X); \
1489 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1490 if ((X) != orig_x && memory_address_p (MODE, X)) \
1493 /* Go to LABEL if ADDR (a legitimate address expression)
1494 has an effect that depends on the machine mode it is used for. */
1496 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1497 if (GET_CODE (ADDR) == PRE_DEC \
1498 || GET_CODE (ADDR) == POST_DEC \
1499 || GET_CODE (ADDR) == PRE_INC \
1500 || GET_CODE (ADDR) == POST_INC) \
1503 #define TARGET_ASM_SELECT_SECTION pa_select_section
1505 /* Return a nonzero value if DECL has a section attribute. */
1506 #define IN_NAMED_SECTION_P(DECL) \
1507 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1508 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1510 /* The following extra sections and extra section functions are only used
1511 for SOM, but they must be provided unconditionally because pa.c's calls
1512 to the functions might not get optimized out when other object formats
1515 #define EXTRA_SECTIONS \
1516 in_som_readonly_data, \
1517 in_som_one_only_readonly_data, \
1518 in_som_one_only_data
1520 #define EXTRA_SECTION_FUNCTIONS \
1521 SOM_READONLY_DATA_SECTION_FUNCTION \
1522 SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1523 SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1524 FORGET_SECTION_FUNCTION
1526 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
1527 is not being generated. */
1528 #define SOM_READONLY_DATA_SECTION_FUNCTION \
1530 som_readonly_data_section (void) \
1534 if (in_section != in_som_readonly_data) \
1536 in_section = in_som_readonly_data; \
1537 fputs ("\t.SPACE $TEXT$\n\t.SUBSPA $LIT$\n", asm_out_file); \
1541 /* When secondary definitions are not supported, SOM makes readonly data one
1542 only by creating a new $LIT$ subspace in $TEXT$ with the comdat flag. */
1543 #define SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1545 som_one_only_readonly_data_section (void) \
1549 in_section = in_som_one_only_readonly_data; \
1550 fputs ("\t.SPACE $TEXT$\n" \
1551 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16,COMDAT\n",\
1555 /* When secondary definitions are not supported, SOM makes data one only by
1556 creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
1557 #define SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1559 som_one_only_data_section (void) \
1563 in_section = in_som_one_only_data; \
1564 fputs ("\t.SPACE $PRIVATE$\n" \
1565 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31,SORT=24,COMDAT\n", \
1569 #define FORGET_SECTION_FUNCTION \
1571 forget_section (void) \
1573 in_section = no_section; \
1576 /* Define this macro if references to a symbol must be treated
1577 differently depending on something about the variable or
1578 function named by the symbol (such as what section it is in).
1580 The macro definition, if any, is executed immediately after the
1581 rtl for DECL or other node is created.
1582 The value of the rtl will be a `mem' whose address is a
1585 The usual thing for this macro to do is to a flag in the
1586 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1587 name string in the `symbol_ref' (if one bit is not enough
1590 On the HP-PA we use this to indicate if a symbol is in text or
1591 data space. Also, function labels need special treatment. */
1593 #define TEXT_SPACE_P(DECL)\
1594 (TREE_CODE (DECL) == FUNCTION_DECL \
1595 || (TREE_CODE (DECL) == VAR_DECL \
1596 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1597 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1599 || CONSTANT_CLASS_P (DECL))
1601 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1603 /* Specify the machine mode that this machine uses for the index in the
1604 tablejump instruction. For small tables, an element consists of a
1605 ia-relative branch and its delay slot. When -mbig-switch is specified,
1606 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1607 for both 32 and 64-bit pic code. */
1608 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1610 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1611 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1613 /* Define this as 1 if `char' should by default be signed; else as 0. */
1614 #define DEFAULT_SIGNED_CHAR 1
1616 /* Max number of bytes we can move from memory to memory
1617 in one reasonably fast instruction. */
1620 /* Higher than the default as we prefer to use simple move insns
1621 (better scheduling and delay slot filling) and because our
1622 built-in block move is really a 2X unrolled loop.
1624 Believe it or not, this has to be big enough to allow for copying all
1625 arguments passed in registers to avoid infinite recursion during argument
1626 setup for a function call. Why? Consider how we copy the stack slots
1627 reserved for parameters when they may be trashed by a call. */
1628 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1630 /* Define if operations between registers always perform the operation
1631 on the full register even if a narrower mode is specified. */
1632 #define WORD_REGISTER_OPERATIONS
1634 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1635 will either zero-extend or sign-extend. The value of this macro should
1636 be the code that says which one of the two operations is implicitly
1637 done, UNKNOWN if none. */
1638 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1640 /* Nonzero if access to memory by bytes is slow and undesirable. */
1641 #define SLOW_BYTE_ACCESS 1
1643 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1644 is done just by pretending it is already truncated. */
1645 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1647 /* Specify the machine mode that pointers have.
1648 After generation of rtl, the compiler makes no further distinction
1649 between pointers and any other objects of this machine mode. */
1650 #define Pmode word_mode
1652 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1653 return the mode to be used for the comparison. For floating-point, CCFPmode
1654 should be used. CC_NOOVmode should be used when the first operand is a
1655 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1657 #define SELECT_CC_MODE(OP,X,Y) \
1658 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1660 /* A function address in a call instruction
1661 is a byte address (for indexing purposes)
1662 so give the MEM rtx a byte's mode. */
1663 #define FUNCTION_MODE SImode
1665 /* Define this if addresses of constant functions
1666 shouldn't be put through pseudo regs where they can be cse'd.
1667 Desirable on machines where ordinary constants are expensive
1668 but a CALL with constant address is cheap. */
1669 #define NO_FUNCTION_CSE
1671 /* Define this to be nonzero if shift instructions ignore all but the low-order
1673 #define SHIFT_COUNT_TRUNCATED 1
1675 /* Compute extra cost of moving data between one register class
1678 Make moves from SAR so expensive they should never happen. We used to
1679 have 0xffff here, but that generates overflow in rare cases.
1681 Copies involving a FP register and a non-FP register are relatively
1682 expensive because they must go through memory.
1684 Other copies are reasonably cheap. */
1685 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1686 (CLASS1 == SHIFT_REGS ? 0x100 \
1687 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1688 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1691 /* Adjust the cost of branches. */
1692 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1694 /* Handling the special cases is going to get too complicated for a macro,
1695 just call `pa_adjust_insn_length' to do the real work. */
1696 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1697 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1699 /* Millicode insns are actually function calls with some special
1700 constraints on arguments and register usage.
1702 Millicode calls always expect their arguments in the integer argument
1703 registers, and always return their result in %r29 (ret1). They
1704 are expected to clobber their arguments, %r1, %r29, and the return
1705 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1707 This macro tells reorg that the references to arguments and
1708 millicode calls do not appear to happen until after the millicode call.
1709 This allows reorg to put insns which set the argument registers into the
1710 delay slot of the millicode call -- thus they act more like traditional
1713 Note we cannot consider side effects of the insn to be delayed because
1714 the branch and link insn will clobber the return pointer. If we happened
1715 to use the return pointer in the delay slot of the call, then we lose.
1717 get_attr_type will try to recognize the given insn, so make sure to
1718 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1720 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1723 /* Control the assembler format that we output. */
1725 /* A C string constant describing how to begin a comment in the target
1726 assembler language. The compiler assumes that the comment will end at
1727 the end of the line. */
1729 #define ASM_COMMENT_START ";"
1731 /* Output to assembler file text saying following lines
1732 may contain character constants, extra white space, comments, etc. */
1734 #define ASM_APP_ON ""
1736 /* Output to assembler file text saying following lines
1737 no longer contain unusual constructs. */
1739 #define ASM_APP_OFF ""
1741 /* This is how to output the definition of a user-level label named NAME,
1742 such as the label on a static function or variable NAME. */
1744 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1745 do { assemble_name (FILE, NAME); \
1746 fputc ('\n', FILE); } while (0)
1748 /* This is how to output a reference to a user-level label named NAME.
1749 `assemble_name' uses this. */
1751 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1753 const char *xname = (NAME); \
1754 if (FUNCTION_NAME_P (NAME)) \
1756 if (xname[0] == '*') \
1759 fputs (user_label_prefix, FILE); \
1760 fputs (xname, FILE); \
1763 /* This how we output the symbol_ref X. */
1765 #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1767 SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1768 assemble_name (FILE, XSTR (X, 0)); \
1771 /* This is how to store into the string LABEL
1772 the symbol_ref name of an internal numbered label where
1773 PREFIX is the class of label and NUM is the number within the class.
1774 This is suitable for output with `assemble_name'. */
1776 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1777 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1779 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1781 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1782 output_ascii ((FILE), (P), (SIZE))
1784 /* Jump tables are always placed in the text section. Technically, it
1785 is possible to put them in the readonly data section when -mbig-switch
1786 is specified. This has the benefit of getting the table out of .text
1787 and reducing branch lengths as a result. The downside is that an
1788 additional insn (addil) is needed to access the table when generating
1789 PIC code. The address difference table also has to use 32-bit
1790 pc-relative relocations. Currently, GAS does not support these
1791 relocations, although it is easily modified to do this operation.
1792 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1793 when using ELF GAS. A simple difference can be used when using
1794 SOM GAS or the HP assembler. The final downside is GDB complains
1795 about the nesting of the label for the table when debugging. */
1797 #define JUMP_TABLES_IN_TEXT_SECTION 1
1799 /* This is how to output an element of a case-vector that is absolute. */
1801 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1802 if (TARGET_BIG_SWITCH) \
1803 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1805 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1807 /* This is how to output an element of a case-vector that is relative.
1808 Since we always place jump tables in the text section, the difference
1809 is absolute and requires no relocation. */
1811 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1812 if (TARGET_BIG_SWITCH) \
1813 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1815 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1817 /* This is how to output an assembler line that says to advance the
1818 location counter to a multiple of 2**LOG bytes. */
1820 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1821 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1823 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1824 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1825 (unsigned HOST_WIDE_INT)(SIZE))
1827 /* This says how to output an assembler line to define an uninitialized
1828 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1829 This macro exists to properly support languages like C++ which do not
1830 have common data. */
1832 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1833 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1835 /* This says how to output an assembler line to define a global common symbol
1836 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1838 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1839 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1841 /* This says how to output an assembler line to define a local common symbol
1842 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1843 controls how the assembler definitions of uninitialized static variables
1846 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1847 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1850 #define ASM_PN_FORMAT "%s___%lu"
1852 /* All HP assemblers use "!" to separate logical lines. */
1853 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1855 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1856 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1858 /* Print operand X (an rtx) in assembler syntax to file FILE.
1859 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1860 For `%' followed by punctuation, CODE is the punctuation and X is null.
1862 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1863 and an immediate zero should be represented as `r0'.
1865 Several % codes are defined:
1867 C compare conditions
1868 N extract conditions
1869 M modifier to handle preincrement addressing for memory refs.
1870 F modifier to handle preincrement addressing for fp memory refs */
1872 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1875 /* Print a memory address as an operand to reference that memory location. */
1877 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1878 { rtx addr = ADDR; \
1879 switch (GET_CODE (addr)) \
1882 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1885 gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1886 fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
1887 reg_names [REGNO (XEXP (addr, 0))]); \
1890 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1891 fputs ("R'", FILE); \
1892 else if (flag_pic == 0) \
1893 fputs ("RR'", FILE); \
1895 fputs ("RT'", FILE); \
1896 output_global_address (FILE, XEXP (addr, 1), 0); \
1897 fputs ("(", FILE); \
1898 output_operand (XEXP (addr, 0), 0); \
1899 fputs (")", FILE); \
1902 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1905 output_addr_const (FILE, addr); \
1909 /* Find the return address associated with the frame given by
1911 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1912 (return_addr_rtx (COUNT, FRAMEADDR))
1914 /* Used to mask out junk bits from the return address, such as
1915 processor state, interrupt status, condition codes and the like. */
1916 #define MASK_RETURN_ADDR \
1917 /* The privilege level is in the two low order bits, mask em out \
1918 of the return address. */ \
1921 /* The number of Pmode words for the setjmp buffer. */
1922 #define JMP_BUF_SIZE 50
1924 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1925 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1926 "__canonicalize_funcptr_for_compare"
1929 #undef TARGET_HAVE_TLS
1930 #define TARGET_HAVE_TLS true
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