1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned int total_code_bytes;
36 /* Which processor to schedule for. */
47 /* For -mschedule= option. */
48 extern const char *pa_cpu_string;
49 extern enum processor_type pa_cpu;
51 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
53 /* Which architecture to generate code for. */
55 enum architecture_type
64 /* For -march= option. */
65 extern const char *pa_arch_string;
66 extern enum architecture_type pa_arch;
68 /* Print subsidiary information on the compiler version in use. */
70 #define TARGET_VERSION fputs (" (hppa)", stderr);
72 /* Run-time compilation parameters selecting different hardware subsets. */
74 extern int target_flags;
76 /* compile code for HP-PA 1.1 ("Snake") */
81 #define TARGET_PA_11 (target_flags & MASK_PA_11)
84 /* Disable all FP registers (they all become fixed). This may be necessary
85 for compiling kernels which perform lazy context switching of FP regs.
86 Note if you use this option and try to perform floating point operations
87 the compiler will abort! */
89 #define MASK_DISABLE_FPREGS 2
90 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
92 /* Generate code which assumes that all space register are equivalent.
93 Triggers aggressive unscaled index addressing and faster
94 builtin_return_address. */
95 #define MASK_NO_SPACE_REGS 4
96 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
98 /* Allow unconditional jumps in the delay slots of call instructions. */
99 #define MASK_JUMP_IN_DELAY 8
100 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
102 /* Disable indexed addressing modes. */
103 #define MASK_DISABLE_INDEXING 32
104 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
106 /* Emit code which follows the new portable runtime calling conventions
107 HP wants everyone to use for ELF objects. If at all possible you want
108 to avoid this since it's a performance loss for non-prototyped code.
110 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
111 long-call stubs which is quite expensive. */
112 #define MASK_PORTABLE_RUNTIME 64
113 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
115 /* Emit directives only understood by GAS. This allows parameter
116 relocations to work for static functions. There is no way
117 to make them work the HP assembler at this time. */
119 #define TARGET_GAS (target_flags & MASK_GAS)
121 /* Emit code for processors which do not have an FPU. */
122 #define MASK_SOFT_FLOAT 256
123 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
125 /* Use 3-insn load/store sequences for access to large data segments
126 in shared libraries on hpux10. */
127 #define MASK_LONG_LOAD_STORE 512
128 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
130 /* Use a faster sequence for indirect calls. This assumes that calls
131 through function pointers will never cross a space boundary, and
132 that the executable is not dynamically linked. Such assumptions
133 are generally safe for building kernels and statically linked
134 executables. Code compiled with this option will fail miserably if
135 the executable is dynamically linked or uses nested functions! */
136 #define MASK_FAST_INDIRECT_CALLS 1024
137 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
139 /* Generate code with big switch statements to avoid out of range branches
140 occurring within the switch table. */
141 #define MASK_BIG_SWITCH 2048
142 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
145 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
146 true when this is true. */
147 #define MASK_PA_20 4096
149 #define TARGET_PA_20 (target_flags & MASK_PA_20)
152 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
154 #define TARGET_64BIT 0
157 /* Generate code for ELF32 ABI. */
159 #define TARGET_ELF32 0
162 /* Macro to define tables used to set the flags.
163 This is a list in braces of pairs in braces,
164 each pair being { "NAME", VALUE }
165 where VALUE is the bits to set or minus the bits to clear.
166 An empty string NAME is used to identify the default VALUE. */
168 #define TARGET_SWITCHES \
169 {{"snake", MASK_PA_11, "Generate PA1.1 code"}, \
170 {"nosnake", -(MASK_PA_11 | MASK_PA_20), "Generate PA1.0 code"}, \
171 {"pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), "Generate PA1.0 code"}, \
172 {"pa-risc-1-1", MASK_PA_11, "Generate PA1.1 code"}, \
173 {"pa-risc-2-0", MASK_PA_20, "Generate PA2.0 code. This option requires binutils 2.10 or later"}, \
174 {"disable-fpregs", MASK_DISABLE_FPREGS, "Disable FP regs"}, \
175 {"no-disable-fpregs", -MASK_DISABLE_FPREGS, "Do not disable FP regs"},\
176 {"no-space-regs", MASK_NO_SPACE_REGS, "Disable space regs"}, \
177 {"space-regs", -MASK_NO_SPACE_REGS, "Do not disable space regs"}, \
178 {"jump-in-delay", MASK_JUMP_IN_DELAY, "Put jumps in call delay slots"},\
179 {"no-jump-in-delay", -MASK_JUMP_IN_DELAY, "Do not put jumps in call delay slots"}, \
180 {"disable-indexing", MASK_DISABLE_INDEXING, "Disable indexed addressing"},\
181 {"no-disable-indexing", -MASK_DISABLE_INDEXING, "Do not disable indexed addressing"},\
182 {"portable-runtime", MASK_PORTABLE_RUNTIME, "Use portable calling conventions"}, \
183 {"no-portable-runtime", -MASK_PORTABLE_RUNTIME, "Do not use portable calling conventions"},\
184 {"gas", MASK_GAS, "Assume code will be assembled by GAS"}, \
185 {"no-gas", -MASK_GAS, "Do not assume code will be assembled by GAS"}, \
186 {"soft-float", MASK_SOFT_FLOAT, "Use software floating point"}, \
187 {"no-soft-float", -MASK_SOFT_FLOAT, "Do not use software floating point"}, \
188 {"long-load-store", MASK_LONG_LOAD_STORE, "Emit long load/store sequences"}, \
189 {"no-long-load-store", -MASK_LONG_LOAD_STORE, "Do not emit long load/store sequences"},\
190 {"fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, "Generate fast indirect calls"},\
191 {"no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, "Do not generate fast indirect calls"},\
192 {"big-switch", MASK_BIG_SWITCH, "Generate code for huge switch statements"}, \
193 {"no-big-switch", -MASK_BIG_SWITCH, "Do not generate code for huge switch statements"}, \
194 {"linker-opt", 0, "Enable linker optimizations"}, \
195 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, NULL}}
197 #ifndef TARGET_DEFAULT
198 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
201 #ifndef TARGET_CPU_DEFAULT
202 #define TARGET_CPU_DEFAULT 0
205 #define TARGET_OPTIONS \
207 { "schedule=", &pa_cpu_string, "Specify CPU for scheduling purposes" },\
208 { "arch=", &pa_arch_string, "Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later." }\
211 /* Specify the dialect of assembler to use. New mnemonics is dialect one
212 and the old mnemonics are dialect zero. */
213 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
215 #define OVERRIDE_OPTIONS override_options ()
217 /* stabs-in-som is nearly identical to stabs-in-elf. To avoid useless
218 code duplication we simply include this file and override as needed. */
221 /* We do not have to be compatible with dbx, so we enable gdb extensions
223 #define DEFAULT_GDB_EXTENSIONS 1
225 /* This used to be zero (no max length), but big enums and such can
226 cause huge strings which killed gas.
228 We also have to avoid lossage in dbxout.c -- it does not compute the
229 string size accurately, so we are real conservative here. */
230 #undef DBX_CONTIN_LENGTH
231 #define DBX_CONTIN_LENGTH 3000
233 /* Only labels should ever begin in column zero. */
234 #define ASM_STABS_OP "\t.stabs\t"
235 #define ASM_STABN_OP "\t.stabn\t"
237 /* GDB always assumes the current function's frame begins at the value
238 of the stack pointer upon entry to the current function. Accessing
239 local variables and parameters passed on the stack is done using the
240 base of the frame + an offset provided by GCC.
242 For functions which have frame pointers this method works fine;
243 the (frame pointer) == (stack pointer at function entry) and GCC provides
244 an offset relative to the frame pointer.
246 This loses for functions without a frame pointer; GCC provides an offset
247 which is relative to the stack pointer after adjusting for the function's
248 frame size. GDB would prefer the offset to be relative to the value of
249 the stack pointer at the function's entry. Yuk! */
250 #define DEBUGGER_AUTO_OFFSET(X) \
251 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
252 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
254 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
255 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
256 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
258 #define CPP_PA10_SPEC ""
259 #define CPP_PA11_SPEC "-D_PA_RISC1_1 -D__hp9000s700"
260 #define CPP_PA20_SPEC "-D_PA_RISC2_0 -D__hp9000s800"
261 #define CPP_64BIT_SPEC "-D__LP64__ -D__LONG_MAX__=9223372036854775807L"
263 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_11) == 0
264 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa10)"
267 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_11) != 0
268 #if ((TARGET_DEFAULT | TARGET_CPU_DEFAULT) & MASK_PA_20) != 0
269 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa11) %(cpp_pa20)"
271 #define CPP_CPU_DEFAULT_SPEC "%(cpp_pa11)"
276 #define CPP_64BIT_DEFAULT_SPEC "%(cpp_64bit)"
278 #define CPP_64BIT_DEFAULT_SPEC ""
281 /* This macro defines names of additional specifications to put in the
282 specs that can be used in various specifications like CC1_SPEC. Its
283 definition is an initializer with a subgrouping for each command option.
285 Each subgrouping contains a string constant, that defines the
286 specification name, and a string constant that used by the GNU CC driver
289 Do not define this macro if it does not need to do anything. */
291 #ifndef SUBTARGET_EXTRA_SPECS
292 #define SUBTARGET_EXTRA_SPECS
295 #define EXTRA_SPECS \
296 { "cpp_pa10", CPP_PA10_SPEC}, \
297 { "cpp_pa11", CPP_PA11_SPEC}, \
298 { "cpp_pa20", CPP_PA20_SPEC}, \
299 { "cpp_64bit", CPP_64BIT_SPEC}, \
300 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \
301 { "cpp_64bit_default", CPP_64BIT_DEFAULT_SPEC }, \
302 SUBTARGET_EXTRA_SPECS
305 %{mpa-risc-1-0:%(cpp_pa10)} \
306 %{mpa-risc-1-1:%(cpp_pa11)} \
307 %{msnake:%(cpp_pa11)} \
308 %{mpa-risc-2-0:%(cpp_pa20)} \
309 %{!mpa-risc-1-0:%{!mpa-risc-1-1:%{!mpa-risc-2-0:%{!msnake:%(cpp_cpu_default)}}}} \
310 %{m64bit:%(cpp_64bit)} \
311 %{!m64bit:%(cpp_64bit_default)} \
312 %{!ansi: -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__} \
313 %{threads: -D_REENTRANT -D_DCE_THREADS}"
315 #define CPLUSPLUS_CPP_SPEC "\
316 -D_HPUX_SOURCE -D_HIUX_SOURCE -D__STDC_EXT__ \
317 %{mpa-risc-1-0:%(cpp_pa10)} \
318 %{mpa-risc-1-1:%(cpp_pa11)} \
319 %{msnake:%(cpp_pa11)} \
320 %{mpa-risc-2-0:%(cpp_pa20)} \
321 %{!mpa-risc-1-0:%{!mpa-risc-1-1:%{!mpa-risc-2-0:%{!msnake:%(cpp_cpu_default)}}}} \
322 %{m64bit:%(cpp_64bit)} \
323 %{!m64bit:%(cpp_64bit_default)} \
324 %{threads: -D_REENTRANT -D_DCE_THREADS}"
326 /* Defines for a K&R CC */
328 #define CC1_SPEC "%{pg:} %{p:}"
330 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
332 /* We don't want -lg. */
334 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
337 /* This macro defines command-line switches that modify the default
340 The definition is be an initializer for an array of structures. Each
341 array element has have three elements: the switch name, one of the
342 enumeration codes ADD or DELETE to indicate whether the string should be
343 inserted or deleted, and the string to be inserted or deleted. */
344 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
346 /* Make gcc agree with <machine/ansi.h> */
348 #define SIZE_TYPE "unsigned int"
349 #define PTRDIFF_TYPE "int"
350 #define WCHAR_TYPE "unsigned int"
351 #define WCHAR_TYPE_SIZE 32
353 /* Show we can debug even without a frame pointer. */
354 #define CAN_DEBUG_WITHOUT_FP
356 /* Machine dependent reorg pass. */
357 #define MACHINE_DEPENDENT_REORG(X) pa_reorg(X)
359 /* Names to predefine in the preprocessor for this target machine. */
361 #define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -Dhp9000 -Dhp800 -Dspectrum -DREVARGV -Asystem=unix -Asystem=bsd -Acpu=hppa -Amachine=hppa"
363 /* target machine storage layout */
365 /* Define for cross-compilation from a host with a different float format
366 or endianness (e.g. VAX, x86). */
367 #define REAL_ARITHMETIC
369 /* Define this macro if it is advisable to hold scalars in registers
370 in a wider mode than that declared by the program. In such cases,
371 the value is constrained to be within the bounds of the declared
372 type, but kept valid in the wider mode. The signedness of the
373 extension may differ from that of the type. */
375 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
376 if (GET_MODE_CLASS (MODE) == MODE_INT \
377 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
380 /* Define this if most significant bit is lowest numbered
381 in instructions that operate on numbered bit-fields. */
382 #define BITS_BIG_ENDIAN 1
384 /* Define this if most significant byte of a word is the lowest numbered. */
385 /* That is true on the HP-PA. */
386 #define BYTES_BIG_ENDIAN 1
388 /* Define this if most significant word of a multiword number is lowest
390 #define WORDS_BIG_ENDIAN 1
392 /* number of bits in an addressable storage unit */
393 #define BITS_PER_UNIT 8
395 /* Width in bits of a "word", which is the contents of a machine register.
396 Note that this is not necessarily the width of data type `int';
397 if using 16-bit ints on a 68000, this would still be 32.
398 But on a machine with 16-bit registers, this would be 16. */
399 #define BITS_PER_WORD (TARGET_64BIT ? 64 : 32)
400 #define MAX_BITS_PER_WORD 64
401 #define MAX_LONG_TYPE_SIZE 32
402 #define MAX_WCHAR_TYPE_SIZE 32
404 /* Width of a word, in units (bytes). */
405 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
406 #define MIN_UNITS_PER_WORD 4
408 /* Width in bits of a pointer.
409 See also the macro `Pmode' defined below. */
410 #define POINTER_SIZE BITS_PER_WORD
412 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
413 #define PARM_BOUNDARY BITS_PER_WORD
415 /* Largest alignment required for any stack parameter, in bits.
416 Don't define this if it is equal to PARM_BOUNDARY */
417 #define MAX_PARM_BOUNDARY 64
419 /* Boundary (in *bits*) on which stack pointer is always aligned;
420 certain optimizations in combine depend on this.
422 GCC for the PA always rounds its stacks to a 512bit boundary,
423 but that happens late in the compilation process. */
424 #define STACK_BOUNDARY (TARGET_64BIT ? 128 : 64)
426 /* Allocation boundary (in *bits*) for the code of a function. */
427 #define FUNCTION_BOUNDARY (TARGET_64BIT ? 64 : 32)
429 /* Alignment of field after `int : 0' in a structure. */
430 #define EMPTY_FIELD_BOUNDARY 32
432 /* Every structure's size must be a multiple of this. */
433 #define STRUCTURE_SIZE_BOUNDARY 8
435 /* A bitfield declared as `int' forces `int' alignment for the struct. */
436 #define PCC_BITFIELD_TYPE_MATTERS 1
438 /* No data type wants to be aligned rounder than this. */
439 #define BIGGEST_ALIGNMENT 64
441 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
442 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
443 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
445 /* Make arrays of chars word-aligned for the same reasons. */
446 #define DATA_ALIGNMENT(TYPE, ALIGN) \
447 (TREE_CODE (TYPE) == ARRAY_TYPE \
448 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
449 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
452 /* Set this nonzero if move instructions will actually fail to work
453 when given unaligned data. */
454 #define STRICT_ALIGNMENT 1
456 /* Generate calls to memcpy, memcmp and memset. */
457 #define TARGET_MEM_FUNCTIONS
459 /* Value is 1 if it is a good idea to tie two pseudo registers
460 when one has mode MODE1 and one has mode MODE2.
461 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
462 for any hard reg, then this must be 0 for correct output. */
463 #define MODES_TIEABLE_P(MODE1, MODE2) \
464 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
466 /* Specify the registers used for certain standard purposes.
467 The values of these macros are register numbers. */
469 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
470 /* #define PC_REGNUM */
472 /* Register to use for pushing function arguments. */
473 #define STACK_POINTER_REGNUM 30
475 /* Base register for access to local variables of the function. */
476 #define FRAME_POINTER_REGNUM 3
478 /* Value should be nonzero if functions must have frame pointers. */
479 #define FRAME_POINTER_REQUIRED \
480 (current_function_calls_alloca)
482 /* C statement to store the difference between the frame pointer
483 and the stack pointer values immediately after the function prologue.
485 Note, we always pretend that this is a leaf function because if
486 it's not, there's no point in trying to eliminate the
487 frame pointer. If it is a leaf function, we guessed right! */
488 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
489 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
491 /* Base register for access to arguments of the function. */
492 #define ARG_POINTER_REGNUM 3
494 /* Register in which static-chain is passed to a function. */
495 #define STATIC_CHAIN_REGNUM 29
497 /* Register which holds offset table for position-independent
500 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? 27 : 19)
501 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
503 /* Function to return the rtx used to save the pic offset table register
504 across function calls. */
505 extern struct rtx_def *hppa_pic_save_rtx PARAMS ((void));
507 #define DEFAULT_PCC_STRUCT_RETURN 0
509 /* SOM ABI says that objects larger than 64 bits are returned in memory.
510 PA64 ABI says that objects larger than 128 bits are returned in memory.
511 Note, int_size_in_bytes can return -1 if the size of the object is
512 variable or larger than the maximum value that can be expressed as
514 #define RETURN_IN_MEMORY(TYPE) \
515 ((unsigned HOST_WIDE_INT) int_size_in_bytes (TYPE) > (TARGET_64BIT ? 16 : 8))
517 /* Register in which address to store a structure value
518 is passed to a function. */
519 #define STRUCT_VALUE_REGNUM 28
521 /* Describe how we implement __builtin_eh_return. */
522 #define EH_RETURN_DATA_REGNO(N) \
523 ((N) < 3 ? (N) + 20 : (N) == 4 ? 31 : INVALID_REGNUM)
524 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
525 #define EH_RETURN_HANDLER_RTX gen_rtx_REG (Pmode, 2)
527 /* The letters I, J, K, L and M in a register constraint string
528 can be used to stand for particular ranges of immediate operands.
529 This macro defines what the ranges are.
530 C is the letter, and VALUE is a constant value.
531 Return 1 if VALUE is in the range specified by C.
533 `I' is used for the 11 bit constants.
534 `J' is used for the 14 bit constants.
535 `K' is used for values that can be moved with a zdepi insn.
536 `L' is used for the 5 bit constants.
538 `N' is used for values with the least significant 11 bits equal to zero
539 and when sign extended from 32 to 64 bits the
540 value does not change.
541 `O' is used for numbers n such that n+1 is a power of 2.
544 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
545 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
546 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
547 : (C) == 'K' ? zdepi_cint_p (VALUE) \
548 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
549 : (C) == 'M' ? (VALUE) == 0 \
550 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
551 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
552 == (HOST_WIDE_INT) -1 << 31)) \
553 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
554 : (C) == 'P' ? and_mask_p (VALUE) \
557 /* Similar, but for floating or large integer constants, and defining letters
558 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
560 For PA, `G' is the floating-point constant zero. `H' is undefined. */
562 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
563 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
564 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
567 /* The class value for index registers, and the one for base regs. */
568 #define INDEX_REG_CLASS GENERAL_REGS
569 #define BASE_REG_CLASS GENERAL_REGS
571 #define FP_REG_CLASS_P(CLASS) \
572 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
574 /* True if register is floating-point. */
575 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
577 /* Given an rtx X being reloaded into a reg required to be
578 in class CLASS, return the class of reg to actually use.
579 In general this is just CLASS; but on some machines
580 in some cases it is preferable to use a more restrictive class. */
581 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
583 /* Return the register class of a scratch register needed to copy IN into
584 or out of a register in CLASS in MODE. If it can be done directly
587 Avoid doing any work for the common case calls. */
589 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
590 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
591 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
592 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
594 /* On the PA it is not possible to directly move data between
595 GENERAL_REGS and FP_REGS. */
596 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
597 (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2))
599 /* Return the stack location to use for secondary memory needed reloads. */
600 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
601 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
604 /* Stack layout; function entry, exit and calling. */
606 /* Define this if pushing a word on the stack
607 makes the stack pointer a smaller address. */
608 /* #define STACK_GROWS_DOWNWARD */
610 /* Believe it or not. */
611 #define ARGS_GROW_DOWNWARD
613 /* Define this if the nominal address of the stack frame
614 is at the high-address end of the local variables;
615 that is, each additional local variable allocated
616 goes at a more negative offset in the frame. */
617 /* #define FRAME_GROWS_DOWNWARD */
619 /* Offset within stack frame to start allocating local variables at.
620 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
621 first local allocated. Otherwise, it is the offset to the BEGINNING
622 of the first local allocated. */
623 #define STARTING_FRAME_OFFSET 8
625 /* If we generate an insn to push BYTES bytes,
626 this says how many the stack pointer really advances by.
627 On the HP-PA, don't define this because there are no push insns. */
628 /* #define PUSH_ROUNDING(BYTES) */
630 /* Offset of first parameter from the argument pointer register value.
631 This value will be negated because the arguments grow down.
632 Also note that on STACK_GROWS_UPWARD machines (such as this one)
633 this is the distance from the frame pointer to the end of the first
634 argument, not it's beginning. To get the real offset of the first
635 argument, the size of the argument must be added. */
637 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
639 /* When a parameter is passed in a register, stack space is still
641 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
643 /* Define this if the above stack space is to be considered part of the
644 space allocated by the caller. */
645 #define OUTGOING_REG_PARM_STACK_SPACE
647 /* Keep the stack pointer constant throughout the function.
648 This is both an optimization and a necessity: longjmp
649 doesn't behave itself when the stack pointer moves within
651 #define ACCUMULATE_OUTGOING_ARGS 1
653 /* The weird HPPA calling conventions require a minimum of 48 bytes on
654 the stack: 16 bytes for register saves, and 32 bytes for magic.
655 This is the difference between the logical top of stack and the
657 #define STACK_POINTER_OFFSET \
658 (TARGET_64BIT ? -(current_function_outgoing_args_size + 16): -32)
660 #define STACK_DYNAMIC_OFFSET(FNDECL) \
662 ? (STACK_POINTER_OFFSET) \
663 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
665 /* Value is 1 if returning from a function call automatically
666 pops the arguments described by the number-of-args field in the call.
667 FUNDECL is the declaration node of the function (as a tree),
668 FUNTYPE is the data type of the function (as a tree),
669 or for a library call it is an identifier node for the subroutine name. */
671 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
673 /* Define how to find the value returned by a function.
674 VALTYPE is the data type of the value (as a tree).
675 If the precise function being called is known, FUNC is its FUNCTION_DECL;
676 otherwise, FUNC is 0. */
678 /* On the HP-PA the value is found in register(s) 28(-29), unless
679 the mode is SF or DF. Then the value is returned in fr4 (32, ) */
681 /* This must perform the same promotions as PROMOTE_MODE, else
682 PROMOTE_FUNCTION_RETURN will not work correctly. */
683 #define FUNCTION_VALUE(VALTYPE, FUNC) \
684 gen_rtx_REG (((INTEGRAL_TYPE_P (VALTYPE) \
685 && TYPE_PRECISION (VALTYPE) < BITS_PER_WORD) \
686 || POINTER_TYPE_P (VALTYPE)) \
687 ? word_mode : TYPE_MODE (VALTYPE), \
688 TREE_CODE (VALTYPE) == REAL_TYPE && !TARGET_SOFT_FLOAT ? 32 : 28)
690 /* Define how to find the value returned by a library function
691 assuming the value has mode MODE. */
693 #define LIBCALL_VALUE(MODE) \
695 (! TARGET_SOFT_FLOAT \
696 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
698 /* 1 if N is a possible register number for a function value
699 as seen by the caller. */
701 #define FUNCTION_VALUE_REGNO_P(N) \
702 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
705 /* Define a data type for recording info about an argument list
706 during the scan of that argument list. This data type should
707 hold all necessary information about the function itself
708 and about the args processed so far, enough to enable macros
709 such as FUNCTION_ARG to determine where the next arg should go.
711 On the HP-PA, this is a single integer, which is a number of words
712 of arguments scanned so far (including the invisible argument,
713 if any, which holds the structure-value-address).
714 Thus 4 or more means all following args should go on the stack. */
716 struct hppa_args {int words, nargs_prototype, indirect; };
718 #define CUMULATIVE_ARGS struct hppa_args
720 /* Initialize a variable CUM of type CUMULATIVE_ARGS
721 for a call to a function whose data type is FNTYPE.
722 For a library call, FNTYPE is 0. */
724 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
726 (CUM).indirect = INDIRECT, \
727 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
728 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
729 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
730 || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \
735 /* Similar, but when scanning the definition of a procedure. We always
736 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
738 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
740 (CUM).indirect = 0, \
741 (CUM).nargs_prototype = 1000
743 /* Figure out the size in words of the function argument. */
745 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
746 ((((MODE) != BLKmode \
747 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
748 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
750 /* Update the data in CUM to advance over an argument
751 of mode MODE and data type TYPE.
752 (TYPE is null for libcalls where that information may not be available.) */
754 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
755 { (CUM).nargs_prototype--; \
756 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
757 + (((CUM).words & 01) && (TYPE) != 0 \
758 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
761 /* Determine where to put an argument to a function.
762 Value is zero to push the argument on the stack,
763 or a hard register in which to store the argument.
765 MODE is the argument's machine mode.
766 TYPE is the data type of the argument (as a tree).
767 This is null for libcalls where that information may
769 CUM is a variable of type CUMULATIVE_ARGS which gives info about
770 the preceding args and about the function being called.
771 NAMED is nonzero if this argument is a named parameter
772 (otherwise it is an extra parameter matching an ellipsis).
774 On the HP-PA the first four words of args are normally in registers
775 and the rest are pushed. But any arg that won't entirely fit in regs
778 Arguments passed in registers are either 1 or 2 words long.
780 The caller must make a distinction between calls to explicitly named
781 functions and calls through pointers to functions -- the conventions
782 are different! Calls through pointers to functions only use general
783 registers for the first four argument words.
785 Of course all this is different for the portable runtime model
786 HP wants everyone to use for ELF. Ugh. Here's a quick description
787 of how it's supposed to work.
789 1) callee side remains unchanged. It expects integer args to be
790 in the integer registers, float args in the float registers and
791 unnamed args in integer registers.
793 2) caller side now depends on if the function being called has
794 a prototype in scope (rather than if it's being called indirectly).
796 2a) If there is a prototype in scope, then arguments are passed
797 according to their type (ints in integer registers, floats in float
798 registers, unnamed args in integer registers.
800 2b) If there is no prototype in scope, then floating point arguments
801 are passed in both integer and float registers. egad.
803 FYI: The portable parameter passing conventions are almost exactly like
804 the standard parameter passing conventions on the RS6000. That's why
805 you'll see lots of similar code in rs6000.h. */
807 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
809 /* Do not expect to understand this without reading it several times. I'm
810 tempted to try and simply it, but I worry about breaking something. */
812 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
813 function_arg (&CUM, MODE, TYPE, NAMED, 0)
815 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \
816 function_arg (&CUM, MODE, TYPE, NAMED, 1)
818 /* For an arg passed partly in registers and partly in memory,
819 this is the number of registers used.
820 For args passed entirely in registers or entirely in memory, zero. */
822 /* For PA32 there are never split arguments. PA64, on the other hand, can
823 pass arguments partially in registers and partially in memory. */
824 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
825 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
827 /* If defined, a C expression that gives the alignment boundary, in
828 bits, of an argument with the specified mode and type. If it is
829 not defined, `PARM_BOUNDARY' is used for all arguments. */
831 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
833 ? ((integer_zerop (TYPE_SIZE (TYPE)) \
834 || ! TREE_CONSTANT (TYPE_SIZE (TYPE))) \
836 : (((int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) \
837 / UNITS_PER_WORD) * BITS_PER_WORD) \
838 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
839 ? PARM_BOUNDARY : GET_MODE_ALIGNMENT(MODE)))
841 /* Arguments larger than eight bytes are passed by invisible reference */
843 /* PA64 does not pass anything by invisible reference. */
844 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
847 : (((TYPE) && int_size_in_bytes (TYPE) > 8) \
848 || ((MODE) && GET_MODE_SIZE (MODE) > 8)))
850 /* PA64 does not pass anything by invisible reference.
851 This should be undef'ed for 64bit, but we'll see if this works. The
852 problem is that we can't test TARGET_64BIT from the preprocessor. */
853 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
856 : (((TYPE) && int_size_in_bytes (TYPE) > 8) \
857 || ((MODE) && GET_MODE_SIZE (MODE) > 8)))
860 extern struct rtx_def *hppa_compare_op0, *hppa_compare_op1;
861 extern enum cmp_type hppa_branch_type;
863 #define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
864 { const char *target_name = XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0); \
865 STRIP_NAME_ENCODING (target_name, target_name); \
866 pa_output_function_prologue (FILE, 0); \
867 if (VAL_14_BITS_P (DELTA)) \
869 fprintf (FILE, "\tb %s\n\tldo ", target_name); \
870 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, DELTA); \
871 fprintf (FILE, "(%%r26),%%r26\n"); \
875 fprintf (FILE, "\taddil L%%"); \
876 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, DELTA); \
877 fprintf (FILE, ",%%r26\n\tb %s\n\tldo R%%", target_name); \
878 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, DELTA); \
879 fprintf (FILE, "(%%r1),%%r26\n"); \
881 fprintf (FILE, "\n\t.EXIT\n\t.PROCEND\n"); \
884 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
885 as assembly via FUNCTION_PROFILER. */
887 #define FUNCTION_PROFILER(FILE, LABEL) /* nothing */
889 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
890 void hppa_profile_hook PARAMS ((int label_no));
892 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
893 the stack pointer does not matter. The value is tested only in
894 functions that have frame pointers.
895 No definition is equivalent to always zero. */
897 extern int may_call_alloca;
899 #define EXIT_IGNORE_STACK \
900 (get_frame_size () != 0 \
901 || current_function_calls_alloca || current_function_outgoing_args_size)
903 /* Output assembler code for a block containing the constant parts
904 of a trampoline, leaving space for the variable parts.\
906 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
907 and then branches to the specified routine.
909 This code template is copied from text segment to stack location
910 and then patched with INITIALIZE_TRAMPOLINE to contain
911 valid values, and then entered as a subroutine.
913 It is best to keep this as small as possible to avoid having to
914 flush multiple lines in the cache. */
916 #define TRAMPOLINE_TEMPLATE(FILE) \
918 if (! TARGET_64BIT) \
920 fputs ("\tldw 36(%r22),%r21\n", FILE); \
921 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
922 if (ASSEMBLER_DIALECT == 0) \
923 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
925 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
926 fputs ("\tldw 4(%r21),%r19\n", FILE); \
927 fputs ("\tldw 0(%r21),%r21\n", FILE); \
928 fputs ("\tldsid (%r21),%r1\n", FILE); \
929 fputs ("\tmtsp %r1,%sr0\n", FILE); \
930 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
931 fputs ("\tldw 40(%r22),%r29\n", FILE); \
932 fputs ("\t.word 0\n", FILE); \
933 fputs ("\t.word 0\n", FILE); \
934 fputs ("\t.word 0\n", FILE); \
935 fputs ("\t.word 0\n", FILE); \
939 fputs ("\t.dword 0\n", FILE); \
940 fputs ("\t.dword 0\n", FILE); \
941 fputs ("\t.dword 0\n", FILE); \
942 fputs ("\t.dword 0\n", FILE); \
943 fputs ("\tmfia %r31\n", FILE); \
944 fputs ("\tldd 24(%r31),%r1\n", FILE); \
945 fputs ("\tldd 24(%r1),%r27\n", FILE); \
946 fputs ("\tldd 16(%r1),%r1\n", FILE); \
947 fputs ("\tbve (%r1)\n", FILE); \
948 fputs ("\tldd 32(%r31),%r31\n", FILE); \
949 fputs ("\t.dword 0 ; fptr\n", FILE); \
950 fputs ("\t.dword 0 ; static link\n", FILE); \
954 /* Length in units of the trampoline for entering a nested function.
956 Flush the cache entries corresponding to the first and last addresses
957 of the trampoline. This is necessary as the trampoline may cross two
960 If the code part of the trampoline ever grows to > 32 bytes, then it
961 will become necessary to hack on the cacheflush pattern in pa.md. */
963 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
965 /* Emit RTL insns to initialize the variable parts of a trampoline.
966 FNADDR is an RTX for the address of the function's pure code.
967 CXT is an RTX for the static chain value for the function.
969 Move the function address to the trampoline template at offset 36.
970 Move the static chain value to trampoline template at offset 40.
971 Move the trampoline address to trampoline template at offset 44.
972 Move r19 to trampoline template at offset 48. The latter two
973 words create a plabel for the indirect call to the trampoline. */
975 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
977 if (! TARGET_64BIT) \
979 rtx start_addr, end_addr; \
981 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
982 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR)); \
983 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
984 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT)); \
985 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
986 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (TRAMP)); \
987 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
988 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), \
989 gen_rtx_REG (Pmode, 19)); \
990 /* fdc and fic only use registers for the address to flush, \
991 they do not accept integer displacements. */ \
992 start_addr = force_reg (Pmode, (TRAMP)); \
993 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
994 emit_insn (gen_dcacheflush (start_addr, end_addr)); \
995 end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \
996 emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \
997 gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
1001 rtx start_addr, end_addr; \
1003 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1004 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (FNADDR)); \
1005 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1006 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), (CXT)); \
1007 /* Create a fat pointer for the trampoline. */ \
1008 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1009 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1010 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \
1011 end_addr = gen_rtx_REG (Pmode, 27); \
1012 start_addr = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1013 emit_move_insn (gen_rtx_MEM (Pmode, start_addr), end_addr); \
1014 /* fdc and fic only use registers for the address to flush, \
1015 they do not accept integer displacements. */ \
1016 start_addr = force_reg (Pmode, (TRAMP)); \
1017 end_addr = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1018 emit_insn (gen_dcacheflush (start_addr, end_addr)); \
1019 end_addr = force_reg (Pmode, plus_constant (start_addr, 32)); \
1020 emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \
1021 gen_reg_rtx (Pmode), gen_reg_rtx (Pmode)));\
1025 /* Perform any machine-specific adjustment in the address of the trampoline.
1026 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1027 Adjust the trampoline address to point to the plabel at offset 44. */
1029 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1030 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1032 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
1033 reference the 4 integer arg registers and 4 fp arg registers.
1034 Ordinarily they are not call used registers, but they are for
1035 _builtin_saveregs, so we must make this explicit. */
1037 #define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs ()
1039 /* Implement `va_start' for varargs and stdarg. */
1041 #define EXPAND_BUILTIN_VA_START(stdarg, valist, nextarg) \
1042 hppa_va_start (stdarg, valist, nextarg)
1044 /* Implement `va_arg'. */
1046 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1047 hppa_va_arg (valist, type)
1049 /* Addressing modes, and classification of registers for them.
1051 Using autoincrement addressing modes on PA8000 class machines is
1054 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1055 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1057 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1058 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1060 /* Macros to check register numbers against specific register classes. */
1062 /* These assume that REGNO is a hard or pseudo reg number.
1063 They give nonzero only if REGNO is a hard reg of the suitable class
1064 or a pseudo reg currently allocated to a suitable hard reg.
1065 Since they use reg_renumber, they are safe only once reg_renumber
1066 has been allocated, which happens in local-alloc.c. */
1068 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1069 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1070 #define REGNO_OK_FOR_BASE_P(REGNO) \
1071 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1072 #define REGNO_OK_FOR_FP_P(REGNO) \
1073 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1075 /* Now macros that check whether X is a register and also,
1076 strictly, whether it is in a specified class.
1078 These macros are specific to the HP-PA, and may be used only
1079 in code for printing assembler insns and in conditions for
1080 define_optimization. */
1082 /* 1 if X is an fp register. */
1084 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1086 /* Maximum number of registers that can appear in a valid memory address. */
1088 #define MAX_REGS_PER_ADDRESS 2
1090 /* Recognize any constant value that is a valid address except
1091 for symbolic addresses. We get better CSE by rejecting them
1092 here and allowing hppa_legitimize_address to break them up. We
1093 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1095 #define CONSTANT_ADDRESS_P(X) \
1096 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1097 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1098 || GET_CODE (X) == HIGH) \
1099 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1101 /* Include all constant integers and constant doubles, but not
1102 floating-point, except for floating-point zero.
1104 Reject LABEL_REFs if we're not using gas or the new HP assembler.
1106 ?!? For now also reject CONST_DOUBLES in 64bit mode. This will need
1108 #ifndef NEW_HP_ASSEMBLER
1109 #define NEW_HP_ASSEMBLER 0
1111 #define LEGITIMATE_CONSTANT_P(X) \
1112 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1113 || (X) == CONST0_RTX (GET_MODE (X))) \
1114 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1115 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1116 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1117 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1118 || (INTVAL (X) >= (HOST_WIDE_INT) -32 << 31 \
1119 && INTVAL (X) < (HOST_WIDE_INT) 32 << 31) \
1120 || cint_ok_for_move (INTVAL (X)))) \
1121 && !function_label_operand (X, VOIDmode))
1123 /* Subroutine for EXTRA_CONSTRAINT.
1125 Return 1 iff OP is a pseudo which did not get a hard register and
1126 we are running the reload pass. */
1128 #define IS_RELOADING_PSEUDO_P(OP) \
1129 ((reload_in_progress \
1130 && GET_CODE (OP) == REG \
1131 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1132 && reg_renumber [REGNO (OP)] < 0))
1134 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1136 For the HPPA, `Q' means that this is a memory operand but not a
1137 symbolic memory operand. Note that an unassigned pseudo register
1138 is such a memory operand. Needed because reload will generate
1139 these things in insns and then not re-recognize the insns, causing
1140 constrain_operands to fail.
1142 `R' is used for scaled indexed addresses.
1144 `S' is the constant 31.
1146 `T' is for fp loads and stores. */
1147 #define EXTRA_CONSTRAINT(OP, C) \
1149 (IS_RELOADING_PSEUDO_P (OP) \
1150 || (GET_CODE (OP) == MEM \
1151 && (memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
1152 || reload_in_progress) \
1153 && ! symbolic_memory_operand (OP, VOIDmode) \
1154 && !(GET_CODE (XEXP (OP, 0)) == PLUS \
1155 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
1156 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT))))\
1158 (GET_CODE (OP) == MEM \
1159 && GET_CODE (XEXP (OP, 0)) == PLUS \
1160 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT \
1161 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT) \
1162 && (move_operand (OP, GET_MODE (OP)) \
1163 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))\
1164 || reload_in_progress)) \
1166 (GET_CODE (OP) == MEM \
1167 /* Using DFmode forces only short displacements \
1168 to be recognized as valid in reg+d addresses. \
1169 However, this is not necessary for PA2.0 since\
1170 it has long FP loads/stores. */ \
1171 && memory_address_p ((TARGET_PA_20 \
1175 && !(GET_CODE (XEXP (OP, 0)) == PLUS \
1176 && (GET_CODE (XEXP (XEXP (OP, 0), 0)) == MULT\
1177 || GET_CODE (XEXP (XEXP (OP, 0), 1)) == MULT)))\
1179 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) \
1181 (GET_CODE (OP) == MEM \
1182 && GET_CODE (XEXP (OP, 0)) == LO_SUM \
1183 && GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
1184 && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0)) \
1185 && GET_CODE (XEXP (XEXP (OP, 0), 1)) == UNSPEC \
1186 && GET_MODE (XEXP (OP, 0)) == Pmode) \
1188 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) : 0))))))
1191 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1192 and check its validity for a certain class.
1193 We have two alternate definitions for each of them.
1194 The usual definition accepts all pseudo regs; the other rejects
1195 them unless they have been allocated suitable hard regs.
1196 The symbol REG_OK_STRICT causes the latter definition to be used.
1198 Most source files want to accept pseudo regs in the hope that
1199 they will get allocated to the class that the insn wants them to be in.
1200 Source files for reload pass need to be strict.
1201 After reload, it makes no difference, since pseudo regs have
1202 been eliminated by then. */
1204 #ifndef REG_OK_STRICT
1206 /* Nonzero if X is a hard reg that can be used as an index
1207 or if it is a pseudo reg. */
1208 #define REG_OK_FOR_INDEX_P(X) \
1209 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1210 /* Nonzero if X is a hard reg that can be used as a base reg
1211 or if it is a pseudo reg. */
1212 #define REG_OK_FOR_BASE_P(X) \
1213 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1217 /* Nonzero if X is a hard reg that can be used as an index. */
1218 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1219 /* Nonzero if X is a hard reg that can be used as a base reg. */
1220 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1224 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1225 that is a valid memory address for an instruction.
1226 The MODE argument is the machine mode for the MEM expression
1227 that wants to use this address.
1229 On the HP-PA, the actual legitimate addresses must be
1230 REG+REG, REG+(REG*SCALE) or REG+SMALLINT.
1231 But we can treat a SYMBOL_REF as legitimate if it is part of this
1232 function's constant-pool, because such addresses can actually
1233 be output as REG+SMALLINT.
1235 Note we only allow 5 bit immediates for access to a constant address;
1236 doing so avoids losing for loading/storing a FP register at an address
1237 which will not fit in 5 bits. */
1239 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1240 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1242 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1243 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1245 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1246 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1248 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1249 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1251 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1253 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1254 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1255 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1256 && REG_P (XEXP (X, 0)) \
1257 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1259 else if (GET_CODE (X) == PLUS) \
1261 rtx base = 0, index = 0; \
1262 if (REG_P (XEXP (X, 0)) \
1263 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1264 base = XEXP (X, 0), index = XEXP (X, 1); \
1265 else if (REG_P (XEXP (X, 1)) \
1266 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1267 base = XEXP (X, 1), index = XEXP (X, 0); \
1269 if (GET_CODE (index) == CONST_INT \
1270 && ((INT_14_BITS (index) \
1271 && (TARGET_SOFT_FLOAT \
1273 && ((MODE == SFmode \
1274 && (INTVAL (index) % 4) == 0)\
1275 || (MODE == DFmode \
1276 && (INTVAL (index) % 8) == 0)))\
1277 || ((MODE) != SFmode && (MODE) != DFmode))) \
1278 || INT_5_BITS (index))) \
1280 if (! TARGET_SOFT_FLOAT \
1281 && ! TARGET_DISABLE_INDEXING \
1283 && (mode == SFmode || mode == DFmode) \
1284 && GET_CODE (index) == MULT \
1285 && GET_CODE (XEXP (index, 0)) == REG \
1286 && REG_OK_FOR_BASE_P (XEXP (index, 0)) \
1287 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1288 && INTVAL (XEXP (index, 1)) == (mode == SFmode ? 4 : 8))\
1291 else if (GET_CODE (X) == LO_SUM \
1292 && GET_CODE (XEXP (X, 0)) == REG \
1293 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1294 && CONSTANT_P (XEXP (X, 1)) \
1295 && (TARGET_SOFT_FLOAT \
1296 /* We can allow symbolic LO_SUM addresses\
1299 && GET_CODE (XEXP (X, 1)) != CONST_INT)\
1300 || ((MODE) != SFmode \
1301 && (MODE) != DFmode))) \
1303 else if (GET_CODE (X) == LO_SUM \
1304 && GET_CODE (XEXP (X, 0)) == SUBREG \
1305 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\
1306 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\
1307 && CONSTANT_P (XEXP (X, 1)) \
1308 && (TARGET_SOFT_FLOAT \
1309 /* We can allow symbolic LO_SUM addresses\
1312 && GET_CODE (XEXP (X, 1)) != CONST_INT)\
1313 || ((MODE) != SFmode \
1314 && (MODE) != DFmode))) \
1316 else if (GET_CODE (X) == LABEL_REF \
1317 || (GET_CODE (X) == CONST_INT \
1318 && INT_5_BITS (X))) \
1320 /* Needed for -fPIC */ \
1321 else if (GET_CODE (X) == LO_SUM \
1322 && GET_CODE (XEXP (X, 0)) == REG \
1323 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1324 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1325 && (TARGET_SOFT_FLOAT \
1327 || ((MODE) != SFmode \
1328 && (MODE) != DFmode))) \
1332 /* Look for machine dependent ways to make the invalid address AD a
1335 For the PA, transform:
1337 memory(X + <large int>)
1341 if (<large int> & mask) >= 16
1342 Y = (<large int> & ~mask) + mask + 1 Round up.
1344 Y = (<large int> & ~mask) Round down.
1346 memory (Z + (<large int> - Y));
1348 This makes reload inheritance and reload_cse work better since Z
1351 There may be more opportunities to improve code with this hook. */
1352 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1354 int offset, newoffset, mask; \
1355 rtx new, temp = NULL_RTX; \
1357 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1358 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff); \
1361 && GET_CODE (AD) == PLUS) \
1362 temp = simplify_binary_operation (PLUS, Pmode, \
1363 XEXP (AD, 0), XEXP (AD, 1)); \
1365 new = temp ? temp : AD; \
1368 && GET_CODE (new) == PLUS \
1369 && GET_CODE (XEXP (new, 0)) == REG \
1370 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1372 offset = INTVAL (XEXP ((new), 1)); \
1374 /* Choose rounding direction. Round up if we are >= halfway. */ \
1375 if ((offset & mask) >= ((mask + 1) / 2)) \
1376 newoffset = (offset & ~mask) + mask + 1; \
1378 newoffset = offset & ~mask; \
1380 if (newoffset != 0 \
1381 && VAL_14_BITS_P (newoffset)) \
1384 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1385 GEN_INT (newoffset)); \
1386 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1387 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1388 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1398 /* Try machine-dependent ways of modifying an illegitimate address
1399 to be legitimate. If we find one, return the new, valid address.
1400 This macro is used in only one place: `memory_address' in explow.c.
1402 OLDX is the address as it was before break_out_memory_refs was called.
1403 In some cases it is useful to look at this to decide what needs to be done.
1405 MODE and WIN are passed so that this macro can use
1406 GO_IF_LEGITIMATE_ADDRESS.
1408 It is always safe for this macro to do nothing. It exists to recognize
1409 opportunities to optimize the output. */
1411 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1412 { rtx orig_x = (X); \
1413 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1414 if ((X) != orig_x && memory_address_p (MODE, X)) \
1417 /* Go to LABEL if ADDR (a legitimate address expression)
1418 has an effect that depends on the machine mode it is used for. */
1420 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1421 if (GET_CODE (ADDR) == PRE_DEC \
1422 || GET_CODE (ADDR) == POST_DEC \
1423 || GET_CODE (ADDR) == PRE_INC \
1424 || GET_CODE (ADDR) == POST_INC) \
1427 /* Arghh. The hpux10 linker chokes if we have a reference to symbols
1428 in a readonly data section when the symbol is defined in a shared
1429 library. Since we can't know at compile time if a symbol will be
1430 satisfied by a shared library or main program we put any symbolic
1431 constant into the normal data section. */
1432 #define SELECT_RTX_SECTION(MODE,RTX,ALIGN) \
1433 if (symbolic_operand (RTX, MODE)) \
1436 readonly_data_section ();
1438 /* On hpux10, the linker will give an error if we have a reference
1439 in the read-only data section to a symbol defined in a shared
1440 library. Therefore, expressions that might require a reloc can
1441 not be placed in the read-only data section. */
1442 #define SELECT_SECTION(EXP,RELOC,ALIGN) \
1443 if (TREE_CODE (EXP) == VAR_DECL \
1444 && TREE_READONLY (EXP) \
1445 && !TREE_THIS_VOLATILE (EXP) \
1446 && DECL_INITIAL (EXP) \
1447 && (DECL_INITIAL (EXP) == error_mark_node \
1448 || TREE_CONSTANT (DECL_INITIAL (EXP))) \
1450 readonly_data_section (); \
1451 else if (TREE_CODE_CLASS (TREE_CODE (EXP)) == 'c' \
1452 && !(TREE_CODE (EXP) == STRING_CST && flag_writable_strings) \
1454 readonly_data_section (); \
1458 /* Define this macro if references to a symbol must be treated
1459 differently depending on something about the variable or
1460 function named by the symbol (such as what section it is in).
1462 The macro definition, if any, is executed immediately after the
1463 rtl for DECL or other node is created.
1464 The value of the rtl will be a `mem' whose address is a
1467 The usual thing for this macro to do is to a flag in the
1468 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1469 name string in the `symbol_ref' (if one bit is not enough
1472 On the HP-PA we use this to indicate if a symbol is in text or
1473 data space. Also, function labels need special treatment. */
1475 #define TEXT_SPACE_P(DECL)\
1476 (TREE_CODE (DECL) == FUNCTION_DECL \
1477 || (TREE_CODE (DECL) == VAR_DECL \
1478 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1479 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1481 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c' \
1482 && !(TREE_CODE (DECL) == STRING_CST && flag_writable_strings)))
1484 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1486 #define ENCODE_SECTION_INFO(DECL)\
1488 { if (TEXT_SPACE_P (DECL)) \
1490 if (TREE_CODE (DECL) == FUNCTION_DECL \
1491 || TREE_CODE (DECL) == VAR_DECL) \
1492 _rtl = DECL_RTL (DECL); \
1494 _rtl = TREE_CST_RTL (DECL); \
1495 SYMBOL_REF_FLAG (XEXP (_rtl, 0)) = 1; \
1496 if (TREE_CODE (DECL) == FUNCTION_DECL) \
1497 hppa_encode_label (XEXP (DECL_RTL (DECL), 0));\
1502 /* Store the user-specified part of SYMBOL_NAME in VAR.
1503 This is sort of inverse to ENCODE_SECTION_INFO. */
1505 #define STRIP_NAME_ENCODING(VAR,SYMBOL_NAME) \
1506 (VAR) = ((SYMBOL_NAME) \
1507 + (*(SYMBOL_NAME) == '*' || *(SYMBOL_NAME) == '@'))
1509 /* Specify the machine mode that this machine uses
1510 for the index in the tablejump instruction. */
1511 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? TImode : DImode)
1513 /* Jump tables must be 32 bit aligned, no matter the size of the element. */
1514 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1516 /* Specify the tree operation to be used to convert reals to integers. */
1517 #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1519 /* This is the kind of divide that is easiest to do in the general case. */
1520 #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1522 /* Define this as 1 if `char' should by default be signed; else as 0. */
1523 #define DEFAULT_SIGNED_CHAR 1
1525 /* Max number of bytes we can move from memory to memory
1526 in one reasonably fast instruction. */
1529 /* Higher than the default as we prefer to use simple move insns
1530 (better scheduling and delay slot filling) and because our
1531 built-in block move is really a 2X unrolled loop.
1533 Believe it or not, this has to be big enough to allow for copying all
1534 arguments passed in registers to avoid infinite recursion during argument
1535 setup for a function call. Why? Consider how we copy the stack slots
1536 reserved for parameters when they may be trashed by a call. */
1537 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1539 /* Define if operations between registers always perform the operation
1540 on the full register even if a narrower mode is specified. */
1541 #define WORD_REGISTER_OPERATIONS
1543 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1544 will either zero-extend or sign-extend. The value of this macro should
1545 be the code that says which one of the two operations is implicitly
1546 done, NIL if none. */
1547 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1549 /* Nonzero if access to memory by bytes is slow and undesirable. */
1550 #define SLOW_BYTE_ACCESS 1
1552 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1553 is done just by pretending it is already truncated. */
1554 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1556 /* We assume that the store-condition-codes instructions store 0 for false
1557 and some other value for true. This is the value stored for true. */
1559 #define STORE_FLAG_VALUE 1
1561 /* When a prototype says `char' or `short', really pass an `int'. */
1562 #define PROMOTE_PROTOTYPES 1
1563 #define PROMOTE_FUNCTION_RETURN 1
1565 /* Specify the machine mode that pointers have.
1566 After generation of rtl, the compiler makes no further distinction
1567 between pointers and any other objects of this machine mode. */
1568 #define Pmode word_mode
1570 /* Add any extra modes needed to represent the condition code.
1572 HPPA floating comparisons produce condition codes. */
1573 #define EXTRA_CC_MODES CC(CCFPmode, "CCFP")
1575 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1576 return the mode to be used for the comparison. For floating-point, CCFPmode
1577 should be used. CC_NOOVmode should be used when the first operand is a
1578 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1580 #define SELECT_CC_MODE(OP,X,Y) \
1581 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1583 /* A function address in a call instruction
1584 is a byte address (for indexing purposes)
1585 so give the MEM rtx a byte's mode. */
1586 #define FUNCTION_MODE SImode
1588 /* Define this if addresses of constant functions
1589 shouldn't be put through pseudo regs where they can be cse'd.
1590 Desirable on machines where ordinary constants are expensive
1591 but a CALL with constant address is cheap. */
1592 #define NO_FUNCTION_CSE
1594 /* Define this to be nonzero if shift instructions ignore all but the low-order
1596 #define SHIFT_COUNT_TRUNCATED 1
1598 /* Compute the cost of computing a constant rtl expression RTX
1599 whose rtx-code is CODE. The body of this macro is a portion
1600 of a switch statement. If the code is computed here,
1601 return it with a return statement. Otherwise, break from the switch. */
1603 #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1605 if (INTVAL (RTX) == 0) return 0; \
1606 if (INT_14_BITS (RTX)) return 1; \
1613 case CONST_DOUBLE: \
1614 if ((RTX == CONST0_RTX (DFmode) || RTX == CONST0_RTX (SFmode)) \
1615 && OUTER_CODE != SET) \
1620 #define ADDRESS_COST(RTX) \
1621 (GET_CODE (RTX) == REG ? 1 : hppa_address_cost (RTX))
1623 /* Compute extra cost of moving data between one register class
1626 Make moves from SAR so expensive they should never happen. We used to
1627 have 0xffff here, but that generates overflow in rare cases.
1629 Copies involving a FP register and a non-FP register are relatively
1630 expensive because they must go through memory.
1632 Other copies are reasonably cheap. */
1633 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1634 (CLASS1 == SHIFT_REGS ? 0x100 \
1635 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1636 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1640 /* Provide the costs of a rtl expression. This is in the body of a
1641 switch on CODE. The purpose for the cost of MULT is to encourage
1642 `synth_mult' to find a synthetic multiply when reasonable. */
1644 #define RTX_COSTS(X,CODE,OUTER_CODE) \
1646 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1647 return COSTS_N_INSNS (3); \
1648 return (TARGET_PA_11 && ! TARGET_DISABLE_FPREGS && ! TARGET_SOFT_FLOAT) \
1649 ? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \
1651 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1652 return COSTS_N_INSNS (14); \
1656 return COSTS_N_INSNS (60); \
1657 case PLUS: /* this includes shNadd insns */ \
1659 if (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
1660 return COSTS_N_INSNS (3); \
1661 return COSTS_N_INSNS (1); \
1665 return COSTS_N_INSNS (1);
1667 /* Adjust the cost of branches. */
1668 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1670 /* Handling the special cases is going to get too complicated for a macro,
1671 just call `pa_adjust_insn_length' to do the real work. */
1672 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1673 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1675 /* Millicode insns are actually function calls with some special
1676 constraints on arguments and register usage.
1678 Millicode calls always expect their arguments in the integer argument
1679 registers, and always return their result in %r29 (ret1). They
1680 are expected to clobber their arguments, %r1, %r29, and the return
1681 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1683 This macro tells reorg that the references to arguments and
1684 millicode calls do not appear to happen until after the millicode call.
1685 This allows reorg to put insns which set the argument registers into the
1686 delay slot of the millicode call -- thus they act more like traditional
1689 Note we can not consider side effects of the insn to be delayed because
1690 the branch and link insn will clobber the return pointer. If we happened
1691 to use the return pointer in the delay slot of the call, then we lose.
1693 get_attr_type will try to recognize the given insn, so make sure to
1694 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1696 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1699 /* Control the assembler format that we output. */
1701 /* Output to assembler file text saying following lines
1702 may contain character constants, extra white space, comments, etc. */
1704 #define ASM_APP_ON ""
1706 /* Output to assembler file text saying following lines
1707 no longer contain unusual constructs. */
1709 #define ASM_APP_OFF ""
1711 /* This is how to output the definition of a user-level label named NAME,
1712 such as the label on a static function or variable NAME. */
1714 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1715 do { assemble_name (FILE, NAME); \
1716 fputc ('\n', FILE); } while (0)
1718 /* This is how to output a reference to a user-level label named NAME.
1719 `assemble_name' uses this. */
1721 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1722 fprintf ((FILE), "%s", (NAME) + (FUNCTION_NAME_P (NAME) ? 1 : 0))
1724 /* This is how to output an internal numbered label where
1725 PREFIX is the class of label and NUM is the number within the class. */
1727 #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1728 {fprintf (FILE, "%c$%s%04d\n", (PREFIX)[0], (PREFIX) + 1, NUM);}
1730 /* This is how to store into the string LABEL
1731 the symbol_ref name of an internal numbered label where
1732 PREFIX is the class of label and NUM is the number within the class.
1733 This is suitable for output with `assemble_name'. */
1735 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1736 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1738 /* This is how to output an assembler line defining a `double' constant. */
1740 #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1742 REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \
1743 fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", l[0], l[1]); \
1746 /* This is how to output an assembler line defining a `float' constant. */
1748 #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1750 REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \
1751 fprintf (FILE, "\t.word 0x%lx\n", l); \
1754 /* This is how to output an assembler line defining an `int' constant.
1756 This is made more complicated by the fact that functions must be
1757 prefixed by a P% as well as code label references for the exception
1758 table -- otherwise the linker chokes. */
1760 #define ASM_OUTPUT_INT(FILE,VALUE) \
1761 { fputs ("\t.word ", FILE); \
1762 if (function_label_operand (VALUE, VOIDmode)) \
1763 fputs ("P%", FILE); \
1764 output_addr_const (FILE, (VALUE)); \
1765 fputs ("\n", FILE);}
1767 /* Likewise for `short' and `char' constants. */
1769 #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1770 ( fputs ("\t.half ", FILE), \
1771 output_addr_const (FILE, (VALUE)), \
1774 #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1775 ( fputs ("\t.byte ", FILE), \
1776 output_addr_const (FILE, (VALUE)), \
1779 /* This is how to output an assembler line for a numeric constant byte. */
1781 #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1782 fprintf (FILE, "\t.byte 0x%x\n", (int)(VALUE))
1784 /* C string constants giving the pseudo-op to use for a sequence of
1785 2, 4, and 8 byte unaligned constants. dwarf2out.c needs these. */
1787 #define UNALIGNED_SHORT_ASM_OP (TARGET_GAS ? "\t.half " : NULL)
1788 #define UNALIGNED_INT_ASM_OP (TARGET_GAS ? "\t.word " : NULL)
1789 #define UNALIGNED_DOUBLE_INT_ASM_OP (TARGET_GAS ? "\t.dword " : NULL)
1791 #define ASM_GLOBALIZE_LABEL(FILE, NAME) \
1793 /* We only handle DATA objects here, functions are globalized in \
1794 ASM_DECLARE_FUNCTION_NAME. */ \
1795 if (! FUNCTION_NAME_P (NAME)) \
1797 fputs ("\t.EXPORT ", FILE); \
1798 assemble_name (FILE, NAME); \
1799 fputs (",DATA\n", FILE); \
1803 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1804 output_ascii ((FILE), (P), (SIZE))
1806 /* This is how to output an element of a case-vector that is absolute.
1807 Note that this method makes filling these branch delay slots
1810 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1811 if (TARGET_BIG_SWITCH) \
1812 fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldil LR'L$%04d,%%r1\n\tbe RR'L$%04d(%%sr4,%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE, VALUE); \
1814 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1816 /* Jump tables are executable code and live in the TEXT section on the PA. */
1817 #define JUMP_TABLES_IN_TEXT_SECTION 1
1819 /* This is how to output an element of a case-vector that is relative.
1820 This must be defined correctly as it is used when generating PIC code.
1822 I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT
1823 on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions
1824 rather than a table of absolute addresses. */
1826 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1827 if (TARGET_BIG_SWITCH) \
1828 fprintf (FILE, "\tstw %%r1,-16(%%r30)\n\tldw T'L$%04d(%%r19),%%r1\n\tbv %%r0(%%r1)\n\tldw -16(%%r30),%%r1\n", VALUE); \
1830 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1832 /* This is how to output an assembler line
1833 that says to advance the location counter
1834 to a multiple of 2**LOG bytes. */
1836 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1837 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1839 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1840 fprintf (FILE, "\t.blockz %d\n", (SIZE))
1842 /* This says how to output an assembler line to define a global common symbol
1843 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1845 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \
1847 assemble_name ((FILE), (NAME)); \
1848 fputs ("\t.comm ", (FILE)); \
1849 fprintf ((FILE), "%d\n", MAX ((SIZE), ((ALIGNED) / BITS_PER_UNIT)));}
1851 /* This says how to output an assembler line to define a local common symbol
1852 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1854 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1856 fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \
1857 assemble_name ((FILE), (NAME)); \
1858 fprintf ((FILE), "\n\t.block %d\n", (SIZE));}
1860 /* Store in OUTPUT a string (made with alloca) containing
1861 an assembler-name for a local static variable named NAME.
1862 LABELNO is an integer which is different for each call. */
1864 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1865 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 12), \
1866 sprintf ((OUTPUT), "%s___%d", (NAME), (LABELNO)))
1868 /* All HP assemblers use "!" to separate logical lines. */
1869 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1871 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1872 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1874 /* Print operand X (an rtx) in assembler syntax to file FILE.
1875 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1876 For `%' followed by punctuation, CODE is the punctuation and X is null.
1878 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1879 and an immediate zero should be represented as `r0'.
1881 Several % codes are defined:
1883 C compare conditions
1884 N extract conditions
1885 M modifier to handle preincrement addressing for memory refs.
1886 F modifier to handle preincrement addressing for fp memory refs */
1888 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1891 /* Print a memory address as an operand to reference that memory location. */
1893 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1894 { register rtx addr = ADDR; \
1895 register rtx base; \
1897 switch (GET_CODE (addr)) \
1900 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1903 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1904 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
1905 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1906 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
1909 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
1912 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1913 fputs ("R'", FILE); \
1914 else if (flag_pic == 0) \
1915 fputs ("RR'", FILE); \
1917 fputs ("RT'", FILE); \
1918 output_global_address (FILE, XEXP (addr, 1), 0); \
1919 fputs ("(", FILE); \
1920 output_operand (XEXP (addr, 0), 0); \
1921 fputs (")", FILE); \
1924 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); \
1925 fprintf (FILE, "(%%r0)"); \
1928 output_addr_const (FILE, addr); \
1932 /* Find the return address associated with the frame given by
1934 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1935 (return_addr_rtx (COUNT, FRAMEADDR))
1937 /* Used to mask out junk bits from the return address, such as
1938 processor state, interrupt status, condition codes and the like. */
1939 #define MASK_RETURN_ADDR \
1940 /* The privilege level is in the two low order bits, mask em out \
1941 of the return address. */ \
1944 /* The number of Pmode words for the setjmp buffer. */
1945 #define JMP_BUF_SIZE 50
1947 /* Only direct calls to static functions are allowed to be sibling (tail)
1950 This restriction is necessary because some linker generated stubs will
1951 store return pointers into rp' in some cases which might clobber a
1952 live value already in rp'.
1954 In a sibcall the current function and the target function share stack
1955 space. Thus if the path to the current function and the path to the
1956 target function save a value in rp', they save the value into the
1957 same stack slot, which has undesirable consequences.
1959 Because of the deferred binding nature of shared libraries any function
1960 with external scope could be in a different load module and thus require
1961 rp' to be saved when calling that function. So sibcall optimizations
1962 can only be safe for static function.
1964 Note that GCC never needs return value relocations, so we don't have to
1965 worry about static calls with return value relocations (which require
1968 It is safe to perform a sibcall optimization when the target function
1969 will never return. */
1970 #define FUNCTION_OK_FOR_SIBCALL(DECL) \
1973 && ! TREE_PUBLIC (DECL))
1975 #define PREDICATE_CODES \
1976 {"reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \
1977 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
1978 CONST_DOUBLE, CONST, HIGH, CONSTANT_P_RTX}}, \
1979 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
1980 {"symbolic_memory_operand", {SUBREG, MEM}}, \
1981 {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \
1982 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
1984 {"move_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
1985 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
1986 {"pic_label_operand", {LABEL_REF, CONST}}, \
1987 {"fp_reg_operand", {REG}}, \
1988 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1989 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
1990 {"pre_cint_operand", {CONST_INT}}, \
1991 {"post_cint_operand", {CONST_INT}}, \
1992 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1993 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
1994 {"int5_operand", {CONST_INT}}, \
1995 {"uint5_operand", {CONST_INT}}, \
1996 {"int11_operand", {CONST_INT}}, \
1997 {"uint32_operand", {CONST_INT, \
1998 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
1999 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
2000 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2001 {"ior_operand", {CONST_INT}}, \
2002 {"lhs_lshift_cint_operand", {CONST_INT}}, \
2003 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
2004 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
2005 {"pc_or_label_operand", {PC, LABEL_REF}}, \
2006 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
2007 {"shadd_operand", {CONST_INT}}, \
2008 {"basereg_operand", {REG}}, \
2009 {"div_operand", {REG, CONST_INT}}, \
2010 {"ireg_operand", {REG}}, \
2011 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
2013 {"movb_comparison_operator", {EQ, NE, LT, GE}},
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