1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
23 Boston, MA 02110-1301, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* For -mschedule= option. */
49 extern enum processor_type pa_cpu;
51 /* For -munix= option. */
52 extern int flag_pa_unix;
54 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
56 /* Print subsidiary information on the compiler version in use. */
58 #define TARGET_VERSION fputs (" (hppa)", stderr);
60 #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
62 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
64 #define TARGET_64BIT 0
67 /* Generate code for ELF32 ABI. */
69 #define TARGET_ELF32 0
72 /* Generate code for SOM 32bit ABI. */
77 /* HP-UX UNIX features. */
82 /* HP-UX 10.10 UNIX 95 features. */
83 #ifndef TARGET_HPUX_10_10
84 #define TARGET_HPUX_10_10 0
87 /* HP-UX 11i multibyte and UNIX 98 extensions. */
88 #ifndef TARGET_HPUX_11_11
89 #define TARGET_HPUX_11_11 0
92 /* The following three defines are potential target switches. The current
93 defines are optimal given the current capabilities of GAS and GNU ld. */
95 /* Define to a C expression evaluating to true to use long absolute calls.
96 Currently, only the HP assembler and SOM linker support long absolute
97 calls. They are used only in non-pic code. */
98 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
100 /* Define to a C expression evaluating to true to use long pic symbol
101 difference calls. This is a call variant similar to the long pic
102 pc-relative call. Long pic symbol difference calls are only used with
103 the HP SOM linker. Currently, only the HP assembler supports these
104 calls. GAS doesn't allow an arbitrary difference of two symbols. */
105 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
107 /* Define to a C expression evaluating to true to use long pic
108 pc-relative calls. Long pic pc-relative calls are only used with
109 GAS. Currently, they are usable for calls within a module but
110 not for external calls. */
111 #define TARGET_LONG_PIC_PCREL_CALL 0
113 /* Define to a C expression evaluating to true to use SOM secondary
114 definition symbols for weak support. Linker support for secondary
115 definition symbols is buggy prior to HP-UX 11.X. */
116 #define TARGET_SOM_SDEF 0
118 /* Define to a C expression evaluating to true to save the entry value
119 of SP in the current frame marker. This is normally unnecessary.
120 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
121 HP compilers don't use this flag but it is supported by the assembler.
122 We set this flag to indicate that register %r3 has been saved at the
123 start of the frame. Thus, when the HP unwind library is used, we
124 need to generate additional code to save SP into the frame marker. */
125 #define TARGET_HPUX_UNWIND_LIBRARY 0
127 #ifndef TARGET_DEFAULT
128 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
131 #ifndef TARGET_CPU_DEFAULT
132 #define TARGET_CPU_DEFAULT 0
135 #ifndef TARGET_SCHED_DEFAULT
136 #define TARGET_SCHED_DEFAULT PROCESSOR_8000
139 /* Support for a compile-time default CPU, et cetera. The rules are:
140 --with-schedule is ignored if -mschedule is specified.
141 --with-arch is ignored if -march is specified. */
142 #define OPTION_DEFAULT_SPECS \
143 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
144 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
146 /* Specify the dialect of assembler to use. New mnemonics is dialect one
147 and the old mnemonics are dialect zero. */
148 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
150 #define OVERRIDE_OPTIONS override_options ()
152 /* Override some settings from dbxelf.h. */
154 /* We do not have to be compatible with dbx, so we enable gdb extensions
156 #define DEFAULT_GDB_EXTENSIONS 1
158 /* This used to be zero (no max length), but big enums and such can
159 cause huge strings which killed gas.
161 We also have to avoid lossage in dbxout.c -- it does not compute the
162 string size accurately, so we are real conservative here. */
163 #undef DBX_CONTIN_LENGTH
164 #define DBX_CONTIN_LENGTH 3000
166 /* GDB always assumes the current function's frame begins at the value
167 of the stack pointer upon entry to the current function. Accessing
168 local variables and parameters passed on the stack is done using the
169 base of the frame + an offset provided by GCC.
171 For functions which have frame pointers this method works fine;
172 the (frame pointer) == (stack pointer at function entry) and GCC provides
173 an offset relative to the frame pointer.
175 This loses for functions without a frame pointer; GCC provides an offset
176 which is relative to the stack pointer after adjusting for the function's
177 frame size. GDB would prefer the offset to be relative to the value of
178 the stack pointer at the function's entry. Yuk! */
179 #define DEBUGGER_AUTO_OFFSET(X) \
180 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
181 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
183 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
184 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
185 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
187 #define TARGET_CPU_CPP_BUILTINS() \
189 builtin_assert("cpu=hppa"); \
190 builtin_assert("machine=hppa"); \
191 builtin_define("__hppa"); \
192 builtin_define("__hppa__"); \
194 builtin_define("_PA_RISC2_0"); \
195 else if (TARGET_PA_11) \
196 builtin_define("_PA_RISC1_1"); \
198 builtin_define("_PA_RISC1_0"); \
201 /* An old set of OS defines for various BSD-like systems. */
202 #define TARGET_OS_CPP_BUILTINS() \
205 builtin_define_std ("REVARGV"); \
206 builtin_define_std ("hp800"); \
207 builtin_define_std ("hp9000"); \
208 builtin_define_std ("hp9k8"); \
209 if (!c_dialect_cxx () && !flag_iso) \
210 builtin_define ("hppa"); \
211 builtin_define_std ("spectrum"); \
212 builtin_define_std ("unix"); \
213 builtin_assert ("system=bsd"); \
214 builtin_assert ("system=unix"); \
218 #define CC1_SPEC "%{pg:} %{p:}"
220 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
222 /* We don't want -lg. */
224 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
227 /* This macro defines command-line switches that modify the default
230 The definition is be an initializer for an array of structures. Each
231 array element has have three elements: the switch name, one of the
232 enumeration codes ADD or DELETE to indicate whether the string should be
233 inserted or deleted, and the string to be inserted or deleted. */
234 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
236 /* Make gcc agree with <machine/ansi.h> */
238 #define SIZE_TYPE "unsigned int"
239 #define PTRDIFF_TYPE "int"
240 #define WCHAR_TYPE "unsigned int"
241 #define WCHAR_TYPE_SIZE 32
243 /* Show we can debug even without a frame pointer. */
244 #define CAN_DEBUG_WITHOUT_FP
246 /* target machine storage layout */
247 typedef struct machine_function GTY(())
249 /* Flag indicating that a .NSUBSPA directive has been output for
254 /* Define this macro if it is advisable to hold scalars in registers
255 in a wider mode than that declared by the program. In such cases,
256 the value is constrained to be within the bounds of the declared
257 type, but kept valid in the wider mode. The signedness of the
258 extension may differ from that of the type. */
260 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
261 if (GET_MODE_CLASS (MODE) == MODE_INT \
262 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
265 /* Define this if most significant bit is lowest numbered
266 in instructions that operate on numbered bit-fields. */
267 #define BITS_BIG_ENDIAN 1
269 /* Define this if most significant byte of a word is the lowest numbered. */
270 /* That is true on the HP-PA. */
271 #define BYTES_BIG_ENDIAN 1
273 /* Define this if most significant word of a multiword number is lowest
275 #define WORDS_BIG_ENDIAN 1
277 #define MAX_BITS_PER_WORD 64
279 /* Width of a word, in units (bytes). */
280 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
282 /* Minimum number of units in a word. If this is undefined, the default
283 is UNITS_PER_WORD. Otherwise, it is the constant value that is the
284 smallest value that UNITS_PER_WORD can have at run-time.
286 FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
287 building of various TImode routines in libgcc. The HP runtime
288 specification doesn't provide the alignment requirements and calling
289 conventions for TImode variables. */
290 #define MIN_UNITS_PER_WORD 4
292 /* The widest floating point format supported by the hardware. Note that
293 setting this influences some Ada floating point type sizes, currently
294 required for GNAT to operate properly. */
295 #define WIDEST_HARDWARE_FP_SIZE 64
297 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
298 #define PARM_BOUNDARY BITS_PER_WORD
300 /* Largest alignment required for any stack parameter, in bits.
301 Don't define this if it is equal to PARM_BOUNDARY */
302 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
304 /* Boundary (in *bits*) on which stack pointer is always aligned;
305 certain optimizations in combine depend on this.
307 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
308 the stack on the 32 and 64-bit ports, respectively. However, we
309 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
310 in main. Thus, we treat the former as the preferred alignment. */
311 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
312 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
314 /* Allocation boundary (in *bits*) for the code of a function. */
315 #define FUNCTION_BOUNDARY BITS_PER_WORD
317 /* Alignment of field after `int : 0' in a structure. */
318 #define EMPTY_FIELD_BOUNDARY 32
320 /* Every structure's size must be a multiple of this. */
321 #define STRUCTURE_SIZE_BOUNDARY 8
323 /* A bit-field declared as `int' forces `int' alignment for the struct. */
324 #define PCC_BITFIELD_TYPE_MATTERS 1
326 /* No data type wants to be aligned rounder than this. */
327 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
329 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
330 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
331 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
333 /* Make arrays of chars word-aligned for the same reasons. */
334 #define DATA_ALIGNMENT(TYPE, ALIGN) \
335 (TREE_CODE (TYPE) == ARRAY_TYPE \
336 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
337 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
339 /* Set this nonzero if move instructions will actually fail to work
340 when given unaligned data. */
341 #define STRICT_ALIGNMENT 1
343 /* Value is 1 if it is a good idea to tie two pseudo registers
344 when one has mode MODE1 and one has mode MODE2.
345 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
346 for any hard reg, then this must be 0 for correct output. */
347 #define MODES_TIEABLE_P(MODE1, MODE2) \
348 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
350 /* Specify the registers used for certain standard purposes.
351 The values of these macros are register numbers. */
353 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
354 /* #define PC_REGNUM */
356 /* Register to use for pushing function arguments. */
357 #define STACK_POINTER_REGNUM 30
359 /* Base register for access to local variables of the function. */
360 #define FRAME_POINTER_REGNUM 3
362 /* Value should be nonzero if functions must have frame pointers. */
363 #define FRAME_POINTER_REQUIRED \
364 (current_function_calls_alloca)
366 /* Don't allow hard registers to be renamed into r2 unless r2
367 is already live or already being saved (due to eh). */
369 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
370 ((NEW_REG) != 2 || regs_ever_live[2] || current_function_calls_eh_return)
372 /* C statement to store the difference between the frame pointer
373 and the stack pointer values immediately after the function prologue.
375 Note, we always pretend that this is a leaf function because if
376 it's not, there's no point in trying to eliminate the
377 frame pointer. If it is a leaf function, we guessed right! */
378 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
379 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
381 /* Base register for access to arguments of the function. */
382 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
384 /* Register in which static-chain is passed to a function. */
385 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
387 /* Register used to address the offset table for position-independent
389 #define PIC_OFFSET_TABLE_REGNUM \
390 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
392 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
394 /* Function to return the rtx used to save the pic offset table register
395 across function calls. */
396 extern struct rtx_def *hppa_pic_save_rtx (void);
398 #define DEFAULT_PCC_STRUCT_RETURN 0
400 /* Register in which address to store a structure value
401 is passed to a function. */
402 #define PA_STRUCT_VALUE_REGNUM 28
404 /* Describe how we implement __builtin_eh_return. */
405 #define EH_RETURN_DATA_REGNO(N) \
406 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
407 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
408 #define EH_RETURN_HANDLER_RTX \
409 gen_rtx_MEM (word_mode, \
410 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
411 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
413 /* Offset from the frame pointer register value to the top of stack. */
414 #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
416 /* A C expression whose value is RTL representing the location of the
417 incoming return address at the beginning of any function, before the
418 prologue. You only need to define this macro if you want to support
419 call frame debugging information like that provided by DWARF 2. */
420 #define INCOMING_RETURN_ADDR_RTX (gen_rtx_REG (word_mode, 2))
421 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (2))
423 /* A C expression whose value is an integer giving a DWARF 2 column
424 number that may be used as an alternate return column. This should
425 be defined only if DWARF_FRAME_RETURN_COLUMN is set to a general
426 register, but an alternate column needs to be used for signal frames.
428 Column 0 is not used but unfortunately its register size is set to
429 4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
430 #define DWARF_ALT_FRAME_RETURN_COLUMN FIRST_PSEUDO_REGISTER
432 /* This macro chooses the encoding of pointers embedded in the exception
433 handling sections. If at all possible, this should be defined such
434 that the exception handling section will not require dynamic relocations,
435 and so may be read-only.
437 Because the HP assembler auto aligns, it is necessary to use
438 DW_EH_PE_aligned. It's not possible to make the data read-only
439 on the HP-UX SOM port since the linker requires fixups for label
440 differences in different sections to be word aligned. However,
441 the SOM linker can do unaligned fixups for absolute pointers.
442 We also need aligned pointers for global and function pointers.
444 Although the HP-UX 64-bit ELF linker can handle unaligned pc-relative
445 fixups, the runtime doesn't have a consistent relationship between
446 text and data for dynamically loaded objects. Thus, it's not possible
447 to use pc-relative encoding for pointers on this target. It may be
448 possible to use segment relative encodings but GAS doesn't currently
449 have a mechanism to generate these encodings. For other targets, we
450 use pc-relative encoding for pointers. If the pointer might require
451 dynamic relocation, we make it indirect. */
452 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
453 (TARGET_GAS && !TARGET_HPUX \
455 | ((GLOBAL) || (CODE) == 2 ? DW_EH_PE_indirect : 0) \
456 | (TARGET_64BIT ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)) \
457 : (!TARGET_GAS || (GLOBAL) || (CODE) == 2 \
458 ? DW_EH_PE_aligned : DW_EH_PE_absptr))
460 /* Handle special EH pointer encodings. Absolute, pc-relative, and
461 indirect are handled automatically. We output pc-relative, and
462 indirect pc-relative ourself since we need some special magic to
463 generate pc-relative relocations, and to handle indirect function
465 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
467 if (((ENCODING) & 0x70) == DW_EH_PE_pcrel) \
469 fputs (integer_asm_op (SIZE, FALSE), FILE); \
470 if ((ENCODING) & DW_EH_PE_indirect) \
471 output_addr_const (FILE, get_deferred_plabel (ADDR)); \
473 assemble_name (FILE, XSTR ((ADDR), 0)); \
474 fputs ("+8-$PIC_pcrel$0", FILE); \
479 /* The letters I, J, K, L and M in a register constraint string
480 can be used to stand for particular ranges of immediate operands.
481 This macro defines what the ranges are.
482 C is the letter, and VALUE is a constant value.
483 Return 1 if VALUE is in the range specified by C.
485 `I' is used for the 11 bit constants.
486 `J' is used for the 14 bit constants.
487 `K' is used for values that can be moved with a zdepi insn.
488 `L' is used for the 5 bit constants.
490 `N' is used for values with the least significant 11 bits equal to zero
491 and when sign extended from 32 to 64 bits the
492 value does not change.
493 `O' is used for numbers n such that n+1 is a power of 2.
496 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
497 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
498 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
499 : (C) == 'K' ? zdepi_cint_p (VALUE) \
500 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
501 : (C) == 'M' ? (VALUE) == 0 \
502 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
503 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
504 == (HOST_WIDE_INT) -1 << 31)) \
505 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
506 : (C) == 'P' ? and_mask_p (VALUE) \
509 /* Similar, but for floating or large integer constants, and defining letters
510 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
512 For PA, `G' is the floating-point constant zero. `H' is undefined. */
514 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
515 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
516 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
519 /* The class value for index registers, and the one for base regs. */
520 #define INDEX_REG_CLASS GENERAL_REGS
521 #define BASE_REG_CLASS GENERAL_REGS
523 #define FP_REG_CLASS_P(CLASS) \
524 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
526 /* True if register is floating-point. */
527 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
529 /* Given an rtx X being reloaded into a reg required to be
530 in class CLASS, return the class of reg to actually use.
531 In general this is just CLASS; but on some machines
532 in some cases it is preferable to use a more restrictive class. */
533 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
535 #define MAYBE_FP_REG_CLASS_P(CLASS) \
536 reg_classes_intersect_p ((CLASS), FP_REGS)
538 /* On the PA it is not possible to directly move data between
539 GENERAL_REGS and FP_REGS. On the 32-bit port, we use the
540 location at SP-16. We don't expose this location in the RTL to
541 avoid scheduling related problems. For example, the store and
542 load could be separated by a call to a pure or const function
543 which has no frame and uses SP-16. */
544 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
546 && (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
547 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1)))
550 /* Stack layout; function entry, exit and calling. */
552 /* Define this if pushing a word on the stack
553 makes the stack pointer a smaller address. */
554 /* #define STACK_GROWS_DOWNWARD */
556 /* Believe it or not. */
557 #define ARGS_GROW_DOWNWARD
559 /* Define this to nonzero if the nominal address of the stack frame
560 is at the high-address end of the local variables;
561 that is, each additional local variable allocated
562 goes at a more negative offset in the frame. */
563 #define FRAME_GROWS_DOWNWARD 0
565 /* Offset within stack frame to start allocating local variables at.
566 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
567 first local allocated. Otherwise, it is the offset to the BEGINNING
568 of the first local allocated.
570 On the 32-bit ports, we reserve one slot for the previous frame
571 pointer and one fill slot. The fill slot is for compatibility
572 with HP compiled programs. On the 64-bit ports, we reserve one
573 slot for the previous frame pointer. */
574 #define STARTING_FRAME_OFFSET 8
576 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
577 of the stack. The default is to align it to STACK_BOUNDARY. */
578 #define STACK_ALIGNMENT_NEEDED 0
580 /* If we generate an insn to push BYTES bytes,
581 this says how many the stack pointer really advances by.
582 On the HP-PA, don't define this because there are no push insns. */
583 /* #define PUSH_ROUNDING(BYTES) */
585 /* Offset of first parameter from the argument pointer register value.
586 This value will be negated because the arguments grow down.
587 Also note that on STACK_GROWS_UPWARD machines (such as this one)
588 this is the distance from the frame pointer to the end of the first
589 argument, not it's beginning. To get the real offset of the first
590 argument, the size of the argument must be added. */
592 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
594 /* When a parameter is passed in a register, stack space is still
596 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
598 /* Define this if the above stack space is to be considered part of the
599 space allocated by the caller. */
600 #define OUTGOING_REG_PARM_STACK_SPACE
602 /* Keep the stack pointer constant throughout the function.
603 This is both an optimization and a necessity: longjmp
604 doesn't behave itself when the stack pointer moves within
606 #define ACCUMULATE_OUTGOING_ARGS 1
608 /* The weird HPPA calling conventions require a minimum of 48 bytes on
609 the stack: 16 bytes for register saves, and 32 bytes for magic.
610 This is the difference between the logical top of stack and the
613 On the 64-bit port, the HP C compiler allocates a 48-byte frame
614 marker, although the runtime documentation only describes a 16
615 byte marker. For compatibility, we allocate 48 bytes. */
616 #define STACK_POINTER_OFFSET \
617 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
619 #define STACK_DYNAMIC_OFFSET(FNDECL) \
621 ? (STACK_POINTER_OFFSET) \
622 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
624 /* Value is 1 if returning from a function call automatically
625 pops the arguments described by the number-of-args field in the call.
626 FUNDECL is the declaration node of the function (as a tree),
627 FUNTYPE is the data type of the function (as a tree),
628 or for a library call it is an identifier node for the subroutine name. */
630 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
632 /* Define how to find the value returned by a function.
633 VALTYPE is the data type of the value (as a tree).
634 If the precise function being called is known, FUNC is its FUNCTION_DECL;
635 otherwise, FUNC is 0. */
637 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
639 /* Define how to find the value returned by a library function
640 assuming the value has mode MODE. */
642 #define LIBCALL_VALUE(MODE) \
644 (! TARGET_SOFT_FLOAT \
645 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
647 /* 1 if N is a possible register number for a function value
648 as seen by the caller. */
650 #define FUNCTION_VALUE_REGNO_P(N) \
651 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
654 /* Define a data type for recording info about an argument list
655 during the scan of that argument list. This data type should
656 hold all necessary information about the function itself
657 and about the args processed so far, enough to enable macros
658 such as FUNCTION_ARG to determine where the next arg should go.
660 On the HP-PA, the WORDS field holds the number of words
661 of arguments scanned so far (including the invisible argument,
662 if any, which holds the structure-value-address). Thus, 4 or
663 more means all following args should go on the stack.
665 The INCOMING field tracks whether this is an "incoming" or
668 The INDIRECT field indicates whether this is is an indirect
671 The NARGS_PROTOTYPE field indicates that an argument does not
672 have a prototype when it less than or equal to 0. */
674 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
676 #define CUMULATIVE_ARGS struct hppa_args
678 /* Initialize a variable CUM of type CUMULATIVE_ARGS
679 for a call to a function whose data type is FNTYPE.
680 For a library call, FNTYPE is 0. */
682 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
684 (CUM).incoming = 0, \
685 (CUM).indirect = (FNTYPE) && !(FNDECL), \
686 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
687 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
688 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
689 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
694 /* Similar, but when scanning the definition of a procedure. We always
695 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
697 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
699 (CUM).incoming = 1, \
700 (CUM).indirect = 0, \
701 (CUM).nargs_prototype = 1000
703 /* Figure out the size in words of the function argument. The size
704 returned by this macro should always be greater than zero because
705 we pass variable and zero sized objects by reference. */
707 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
708 ((((MODE) != BLKmode \
709 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
710 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
712 /* Update the data in CUM to advance over an argument
713 of mode MODE and data type TYPE.
714 (TYPE is null for libcalls where that information may not be available.) */
716 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
717 { (CUM).nargs_prototype--; \
718 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
719 + (((CUM).words & 01) && (TYPE) != 0 \
720 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
723 /* Determine where to put an argument to a function.
724 Value is zero to push the argument on the stack,
725 or a hard register in which to store the argument.
727 MODE is the argument's machine mode.
728 TYPE is the data type of the argument (as a tree).
729 This is null for libcalls where that information may
731 CUM is a variable of type CUMULATIVE_ARGS which gives info about
732 the preceding args and about the function being called.
733 NAMED is nonzero if this argument is a named parameter
734 (otherwise it is an extra parameter matching an ellipsis).
736 On the HP-PA the first four words of args are normally in registers
737 and the rest are pushed. But any arg that won't entirely fit in regs
740 Arguments passed in registers are either 1 or 2 words long.
742 The caller must make a distinction between calls to explicitly named
743 functions and calls through pointers to functions -- the conventions
744 are different! Calls through pointers to functions only use general
745 registers for the first four argument words.
747 Of course all this is different for the portable runtime model
748 HP wants everyone to use for ELF. Ugh. Here's a quick description
749 of how it's supposed to work.
751 1) callee side remains unchanged. It expects integer args to be
752 in the integer registers, float args in the float registers and
753 unnamed args in integer registers.
755 2) caller side now depends on if the function being called has
756 a prototype in scope (rather than if it's being called indirectly).
758 2a) If there is a prototype in scope, then arguments are passed
759 according to their type (ints in integer registers, floats in float
760 registers, unnamed args in integer registers.
762 2b) If there is no prototype in scope, then floating point arguments
763 are passed in both integer and float registers. egad.
765 FYI: The portable parameter passing conventions are almost exactly like
766 the standard parameter passing conventions on the RS6000. That's why
767 you'll see lots of similar code in rs6000.h. */
769 /* If defined, a C expression which determines whether, and in which
770 direction, to pad out an argument with extra space. */
771 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
773 /* Specify padding for the last element of a block move between registers
776 The 64-bit runtime specifies that objects need to be left justified
777 (i.e., the normal justification for a big endian target). The 32-bit
778 runtime specifies right justification for objects smaller than 64 bits.
779 We use a DImode register in the parallel for 5 to 7 byte structures
780 so that there is only one element. This allows the object to be
782 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
783 function_arg_padding ((MODE), (TYPE))
785 /* Do not expect to understand this without reading it several times. I'm
786 tempted to try and simply it, but I worry about breaking something. */
788 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
789 function_arg (&CUM, MODE, TYPE, NAMED)
791 /* If defined, a C expression that gives the alignment boundary, in
792 bits, of an argument with the specified mode and type. If it is
793 not defined, `PARM_BOUNDARY' is used for all arguments. */
795 /* Arguments larger than one word are double word aligned. */
797 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
799 ? (integer_zerop (TYPE_SIZE (TYPE)) \
800 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
801 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
802 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
803 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
806 extern GTY(()) rtx hppa_compare_op0;
807 extern GTY(()) rtx hppa_compare_op1;
808 extern enum cmp_type hppa_branch_type;
810 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
811 as assembly via FUNCTION_PROFILER. Just output a local label.
812 We can't use the function label because the GAS SOM target can't
813 handle the difference of a global symbol and a local symbol. */
815 #ifndef FUNC_BEGIN_PROLOG_LABEL
816 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
819 #define FUNCTION_PROFILER(FILE, LABEL) \
820 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
822 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
823 void hppa_profile_hook (int label_no);
825 /* The profile counter if emitted must come before the prologue. */
826 #define PROFILE_BEFORE_PROLOGUE 1
828 /* We never want final.c to emit profile counters. When profile
829 counters are required, we have to defer emitting them to the end
830 of the current file. */
831 #define NO_PROFILE_COUNTERS 1
833 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
834 the stack pointer does not matter. The value is tested only in
835 functions that have frame pointers.
836 No definition is equivalent to always zero. */
838 extern int may_call_alloca;
840 #define EXIT_IGNORE_STACK \
841 (get_frame_size () != 0 \
842 || current_function_calls_alloca || current_function_outgoing_args_size)
844 /* Output assembler code for a block containing the constant parts
845 of a trampoline, leaving space for the variable parts.\
847 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
848 and then branches to the specified routine.
850 This code template is copied from text segment to stack location
851 and then patched with INITIALIZE_TRAMPOLINE to contain
852 valid values, and then entered as a subroutine.
854 It is best to keep this as small as possible to avoid having to
855 flush multiple lines in the cache. */
857 #define TRAMPOLINE_TEMPLATE(FILE) \
861 fputs ("\tldw 36(%r22),%r21\n", FILE); \
862 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
863 if (ASSEMBLER_DIALECT == 0) \
864 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
866 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
867 fputs ("\tldw 4(%r21),%r19\n", FILE); \
868 fputs ("\tldw 0(%r21),%r21\n", FILE); \
871 fputs ("\tbve (%r21)\n", FILE); \
872 fputs ("\tldw 40(%r22),%r29\n", FILE); \
873 fputs ("\t.word 0\n", FILE); \
874 fputs ("\t.word 0\n", FILE); \
878 fputs ("\tldsid (%r21),%r1\n", FILE); \
879 fputs ("\tmtsp %r1,%sr0\n", FILE); \
880 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
881 fputs ("\tldw 40(%r22),%r29\n", FILE); \
883 fputs ("\t.word 0\n", FILE); \
884 fputs ("\t.word 0\n", FILE); \
885 fputs ("\t.word 0\n", FILE); \
886 fputs ("\t.word 0\n", FILE); \
890 fputs ("\t.dword 0\n", FILE); \
891 fputs ("\t.dword 0\n", FILE); \
892 fputs ("\t.dword 0\n", FILE); \
893 fputs ("\t.dword 0\n", FILE); \
894 fputs ("\tmfia %r31\n", FILE); \
895 fputs ("\tldd 24(%r31),%r1\n", FILE); \
896 fputs ("\tldd 24(%r1),%r27\n", FILE); \
897 fputs ("\tldd 16(%r1),%r1\n", FILE); \
898 fputs ("\tbve (%r1)\n", FILE); \
899 fputs ("\tldd 32(%r31),%r31\n", FILE); \
900 fputs ("\t.dword 0 ; fptr\n", FILE); \
901 fputs ("\t.dword 0 ; static link\n", FILE); \
905 /* Length in units of the trampoline for entering a nested function. */
907 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
909 /* Length in units of the trampoline instruction code. */
911 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
913 /* Minimum length of a cache line. A length of 16 will work on all
914 PA-RISC processors. All PA 1.1 processors have a cache line of
915 32 bytes. Most but not all PA 2.0 processors have a cache line
916 of 64 bytes. As cache flushes are expensive and we don't support
917 PA 1.0, we use a minimum length of 32. */
919 #define MIN_CACHELINE_SIZE 32
921 /* Emit RTL insns to initialize the variable parts of a trampoline.
922 FNADDR is an RTX for the address of the function's pure code.
923 CXT is an RTX for the static chain value for the function.
925 Move the function address to the trampoline template at offset 36.
926 Move the static chain value to trampoline template at offset 40.
927 Move the trampoline address to trampoline template at offset 44.
928 Move r19 to trampoline template at offset 48. The latter two
929 words create a plabel for the indirect call to the trampoline.
931 A similar sequence is used for the 64-bit port but the plabel is
932 at the beginning of the trampoline.
934 Finally, the cache entries for the trampoline code are flushed.
935 This is necessary to ensure that the trampoline instruction sequence
936 is written to memory prior to any attempts at prefetching the code
939 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
941 rtx start_addr = gen_reg_rtx (Pmode); \
942 rtx end_addr = gen_reg_rtx (Pmode); \
943 rtx line_length = gen_reg_rtx (Pmode); \
948 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
949 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
950 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
951 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
953 /* Create a fat pointer for the trampoline. */ \
954 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
955 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
956 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
957 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
958 gen_rtx_REG (Pmode, 19)); \
960 /* fdc and fic only use registers for the address to flush, \
961 they do not accept integer displacements. We align the \
962 start and end addresses to the beginning of their respective \
963 cache lines to minimize the number of lines flushed. */ \
964 tmp = force_reg (Pmode, (TRAMP)); \
965 emit_insn (gen_andsi3 (start_addr, tmp, \
966 GEN_INT (-MIN_CACHELINE_SIZE))); \
967 tmp = force_reg (Pmode, \
968 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
969 emit_insn (gen_andsi3 (end_addr, tmp, \
970 GEN_INT (-MIN_CACHELINE_SIZE))); \
971 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
972 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
973 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
974 gen_reg_rtx (Pmode), \
975 gen_reg_rtx (Pmode))); \
979 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
980 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
981 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
982 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
984 /* Create a fat pointer for the trampoline. */ \
985 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
986 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
987 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
988 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
989 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
990 gen_rtx_REG (Pmode, 27)); \
992 /* fdc and fic only use registers for the address to flush, \
993 they do not accept integer displacements. We align the \
994 start and end addresses to the beginning of their respective \
995 cache lines to minimize the number of lines flushed. */ \
996 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
997 emit_insn (gen_anddi3 (start_addr, tmp, \
998 GEN_INT (-MIN_CACHELINE_SIZE))); \
999 tmp = force_reg (Pmode, \
1000 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1001 emit_insn (gen_anddi3 (end_addr, tmp, \
1002 GEN_INT (-MIN_CACHELINE_SIZE))); \
1003 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1004 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1005 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1006 gen_reg_rtx (Pmode), \
1007 gen_reg_rtx (Pmode))); \
1011 /* Perform any machine-specific adjustment in the address of the trampoline.
1012 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1013 Adjust the trampoline address to point to the plabel at offset 44. */
1015 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1016 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1018 /* Implement `va_start' for varargs and stdarg. */
1020 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1021 hppa_va_start (valist, nextarg)
1023 /* Addressing modes, and classification of registers for them.
1025 Using autoincrement addressing modes on PA8000 class machines is
1028 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1029 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1031 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1032 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1034 /* Macros to check register numbers against specific register classes. */
1036 /* The following macros assume that X is a hard or pseudo reg number.
1037 They give nonzero only if X is a hard reg of the suitable class
1038 or a pseudo reg currently allocated to a suitable hard reg.
1039 Since they use reg_renumber, they are safe only once reg_renumber
1040 has been allocated, which happens in local-alloc.c. */
1042 #define REGNO_OK_FOR_INDEX_P(X) \
1044 || (X >= FIRST_PSEUDO_REGISTER \
1046 && (unsigned) reg_renumber[X] < 32)))
1047 #define REGNO_OK_FOR_BASE_P(X) \
1049 || (X >= FIRST_PSEUDO_REGISTER \
1051 && (unsigned) reg_renumber[X] < 32)))
1052 #define REGNO_OK_FOR_FP_P(X) \
1054 || (X >= FIRST_PSEUDO_REGISTER \
1056 && FP_REGNO_P (reg_renumber[X])))
1058 /* Now macros that check whether X is a register and also,
1059 strictly, whether it is in a specified class.
1061 These macros are specific to the HP-PA, and may be used only
1062 in code for printing assembler insns and in conditions for
1063 define_optimization. */
1065 /* 1 if X is an fp register. */
1067 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1069 /* Maximum number of registers that can appear in a valid memory address. */
1071 #define MAX_REGS_PER_ADDRESS 2
1073 /* Non-TLS symbolic references. */
1074 #define PA_SYMBOL_REF_TLS_P(RTX) \
1075 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
1077 /* Recognize any constant value that is a valid address except
1078 for symbolic addresses. We get better CSE by rejecting them
1079 here and allowing hppa_legitimize_address to break them up. We
1080 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1082 #define CONSTANT_ADDRESS_P(X) \
1083 ((GET_CODE (X) == LABEL_REF \
1084 || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
1085 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1086 || GET_CODE (X) == HIGH) \
1087 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1089 /* A C expression that is nonzero if we are using the new HP assembler. */
1091 #ifndef NEW_HP_ASSEMBLER
1092 #define NEW_HP_ASSEMBLER 0
1095 /* The macros below define the immediate range for CONST_INTS on
1096 the 64-bit port. Constants in this range can be loaded in three
1097 instructions using a ldil/ldo/depdi sequence. Constants outside
1098 this range are forced to the constant pool prior to reload. */
1100 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1101 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1102 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1103 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1105 /* A C expression that is nonzero if X is a legitimate constant for an
1108 We include all constant integers and constant doubles, but not
1109 floating-point, except for floating-point zero. We reject LABEL_REFs
1110 if we're not using gas or the new HP assembler.
1112 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1113 that need more than three instructions to load prior to reload. This
1114 limit is somewhat arbitrary. It takes three instructions to load a
1115 CONST_INT from memory but two are memory accesses. It may be better
1116 to increase the allowed range for CONST_INTS. We may also be able
1117 to handle CONST_DOUBLES. */
1119 #define LEGITIMATE_CONSTANT_P(X) \
1120 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1121 || (X) == CONST0_RTX (GET_MODE (X))) \
1122 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1123 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1124 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1125 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1126 || (reload_in_progress || reload_completed) \
1127 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1128 || cint_ok_for_move (INTVAL (X)))) \
1129 && !function_label_operand (X, VOIDmode))
1131 /* Target flags set on a symbol_ref. */
1133 /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
1134 #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
1135 #define SYMBOL_REF_REFERENCED_P(RTX) \
1136 ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
1138 /* Subroutines for EXTRA_CONSTRAINT.
1140 Return 1 iff OP is a pseudo which did not get a hard register and
1141 we are running the reload pass. */
1142 #define IS_RELOADING_PSEUDO_P(OP) \
1143 ((reload_in_progress \
1144 && GET_CODE (OP) == REG \
1145 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1146 && reg_renumber [REGNO (OP)] < 0))
1148 /* Return 1 iff OP is a scaled or unscaled index address. */
1149 #define IS_INDEX_ADDR_P(OP) \
1150 (GET_CODE (OP) == PLUS \
1151 && GET_MODE (OP) == Pmode \
1152 && (GET_CODE (XEXP (OP, 0)) == MULT \
1153 || GET_CODE (XEXP (OP, 1)) == MULT \
1154 || (REG_P (XEXP (OP, 0)) \
1155 && REG_P (XEXP (OP, 1)))))
1157 /* Return 1 iff OP is a LO_SUM DLT address. */
1158 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1159 (GET_CODE (OP) == LO_SUM \
1160 && GET_MODE (OP) == Pmode \
1161 && REG_P (XEXP (OP, 0)) \
1162 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1163 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1165 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1167 `A' is a LO_SUM DLT memory operand.
1169 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1170 memory operand. Note that an unassigned pseudo register is such a
1171 memory operand. Needed because reload will generate these things
1172 and then not re-recognize the insn, causing constrain_operands to
1175 `R' is a scaled/unscaled indexed memory operand.
1177 `S' is the constant 31.
1179 `T' is for floating-point loads and stores.
1181 `U' is the constant 63.
1183 `W' is a register indirect memory operand. We could allow short
1184 displacements but GO_IF_LEGITIMATE_ADDRESS can't tell when a
1185 long displacement is valid. This is only used for prefetch
1186 instructions with the `sl' completer. */
1188 #define EXTRA_CONSTRAINT(OP, C) \
1190 (IS_RELOADING_PSEUDO_P (OP) \
1191 || (GET_CODE (OP) == MEM \
1192 && (reload_in_progress \
1193 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1194 && !symbolic_memory_operand (OP, VOIDmode) \
1195 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1196 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1198 (GET_CODE (OP) == MEM \
1199 && REG_P (XEXP (OP, 0)) \
1200 && REG_OK_FOR_BASE_P (XEXP (OP, 0))) \
1202 (GET_CODE (OP) == MEM \
1203 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1205 (GET_CODE (OP) == MEM \
1206 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1208 (GET_CODE (OP) == MEM \
1209 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1210 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1211 /* Floating-point loads and stores are used to load \
1212 integer values as well as floating-point values. \
1213 They don't have the same set of REG+D address modes \
1214 as integer loads and stores. PA 1.x supports only \
1215 short displacements. PA 2.0 supports long displacements \
1216 but the base register needs to be aligned. \
1218 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1219 DFmode test the validity of an address for use in a \
1220 floating point load or store. So, we use SFmode/DFmode \
1221 to see if the address is valid for a floating-point \
1222 load/store operation. */ \
1223 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1228 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1230 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0)))))))
1233 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1234 and check its validity for a certain class.
1235 We have two alternate definitions for each of them.
1236 The usual definition accepts all pseudo regs; the other rejects
1237 them unless they have been allocated suitable hard regs.
1238 The symbol REG_OK_STRICT causes the latter definition to be used.
1240 Most source files want to accept pseudo regs in the hope that
1241 they will get allocated to the class that the insn wants them to be in.
1242 Source files for reload pass need to be strict.
1243 After reload, it makes no difference, since pseudo regs have
1244 been eliminated by then. */
1246 #ifndef REG_OK_STRICT
1248 /* Nonzero if X is a hard reg that can be used as an index
1249 or if it is a pseudo reg. */
1250 #define REG_OK_FOR_INDEX_P(X) \
1251 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1252 /* Nonzero if X is a hard reg that can be used as a base reg
1253 or if it is a pseudo reg. */
1254 #define REG_OK_FOR_BASE_P(X) \
1255 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1259 /* Nonzero if X is a hard reg that can be used as an index. */
1260 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1261 /* Nonzero if X is a hard reg that can be used as a base reg. */
1262 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1266 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1267 valid memory address for an instruction. The MODE argument is the
1268 machine mode for the MEM expression that wants to use this address.
1270 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1271 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1272 available with floating point loads and stores, and integer loads.
1273 We get better code by allowing indexed addresses in the initial
1276 The acceptance of indexed addresses as legitimate implies that we
1277 must provide patterns for doing indexed integer stores, or the move
1278 expanders must force the address of an indexed store to a register.
1279 We have adopted the latter approach.
1281 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1282 the base register is a valid pointer for indexed instructions.
1283 On targets that have non-equivalent space registers, we have to
1284 know at the time of assembler output which register in a REG+REG
1285 pair is the base register. The REG_POINTER flag is sometimes lost
1286 in reload and the following passes, so it can't be relied on during
1287 code generation. Thus, we either have to canonicalize the order
1288 of the registers in REG+REG indexed addresses, or treat REG+REG
1289 addresses separately and provide patterns for both permutations.
1291 The latter approach requires several hundred additional lines of
1292 code in pa.md. The downside to canonicalizing is that a PLUS
1293 in the wrong order can't combine to form to make a scaled indexed
1294 memory operand. As we won't need to canonicalize the operands if
1295 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1297 We initially break out scaled indexed addresses in canonical order
1298 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1299 scaled indexed addresses during RTL generation. However, fold_rtx
1300 has its own opinion on how the operands of a PLUS should be ordered.
1301 If one of the operands is equivalent to a constant, it will make
1302 that operand the second operand. As the base register is likely to
1303 be equivalent to a SYMBOL_REF, we have made it the second operand.
1305 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1306 operands are in the order INDEX+BASE on targets with non-equivalent
1307 space registers, and in any order on targets with equivalent space
1308 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1310 We treat a SYMBOL_REF as legitimate if it is part of the current
1311 function's constant-pool, because such addresses can actually be
1312 output as REG+SMALLINT.
1314 Note we only allow 5 bit immediates for access to a constant address;
1315 doing so avoids losing for loading/storing a FP register at an address
1316 which will not fit in 5 bits. */
1318 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1319 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1321 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1322 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1324 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1325 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1327 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1328 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1330 #if HOST_BITS_PER_WIDE_INT > 32
1331 #define VAL_32_BITS_P(X) \
1332 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1333 < (unsigned HOST_WIDE_INT) 2 << 31)
1335 #define VAL_32_BITS_P(X) 1
1337 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1339 /* These are the modes that we allow for scaled indexing. */
1340 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1341 ((TARGET_64BIT && (MODE) == DImode) \
1342 || (MODE) == SImode \
1343 || (MODE) == HImode \
1344 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1346 /* These are the modes that we allow for unscaled indexing. */
1347 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1348 ((TARGET_64BIT && (MODE) == DImode) \
1349 || (MODE) == SImode \
1350 || (MODE) == HImode \
1351 || (MODE) == QImode \
1352 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1354 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1356 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1357 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1358 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1359 && REG_P (XEXP (X, 0)) \
1360 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1362 else if (GET_CODE (X) == PLUS) \
1364 rtx base = 0, index = 0; \
1365 if (REG_P (XEXP (X, 1)) \
1366 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1367 base = XEXP (X, 1), index = XEXP (X, 0); \
1368 else if (REG_P (XEXP (X, 0)) \
1369 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1370 base = XEXP (X, 0), index = XEXP (X, 1); \
1372 && GET_CODE (index) == CONST_INT \
1373 && ((INT_14_BITS (index) \
1374 && (((MODE) != DImode \
1375 && (MODE) != SFmode \
1376 && (MODE) != DFmode) \
1377 /* The base register for DImode loads and stores \
1378 with long displacements must be aligned because \
1379 the lower three bits in the displacement are \
1380 assumed to be zero. */ \
1381 || ((MODE) == DImode \
1383 || (INTVAL (index) % 8) == 0)) \
1384 /* Similarly, the base register for SFmode/DFmode \
1385 loads and stores with long displacements must \
1388 FIXME: the ELF32 linker clobbers the LSB of \
1389 the FP register number in PA 2.0 floating-point \
1390 insns with long displacements. This is because \
1391 R_PARISC_DPREL14WR and other relocations like \
1392 it are not supported. For now, we reject long \
1393 displacements on this target. */ \
1394 || (((MODE) == SFmode || (MODE) == DFmode) \
1395 && (TARGET_SOFT_FLOAT \
1398 && (INTVAL (index) \
1399 % GET_MODE_SIZE (MODE)) == 0))))) \
1400 || INT_5_BITS (index))) \
1402 if (!TARGET_DISABLE_INDEXING \
1403 /* Only accept the "canonical" INDEX+BASE operand order \
1404 on targets with non-equivalent space registers. */ \
1405 && (TARGET_NO_SPACE_REGS \
1406 ? (base && REG_P (index)) \
1407 : (base == XEXP (X, 1) && REG_P (index) \
1408 && (reload_completed \
1409 || (reload_in_progress && HARD_REGISTER_P (base)) \
1410 || REG_POINTER (base)) \
1411 && (reload_completed \
1412 || (reload_in_progress && HARD_REGISTER_P (index)) \
1413 || !REG_POINTER (index)))) \
1414 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1415 && REG_OK_FOR_INDEX_P (index) \
1416 && borx_reg_operand (base, Pmode) \
1417 && borx_reg_operand (index, Pmode)) \
1419 if (!TARGET_DISABLE_INDEXING \
1421 && GET_CODE (index) == MULT \
1422 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1423 && REG_P (XEXP (index, 0)) \
1424 && GET_MODE (XEXP (index, 0)) == Pmode \
1425 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1426 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1427 && INTVAL (XEXP (index, 1)) \
1428 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1429 && borx_reg_operand (base, Pmode)) \
1432 else if (GET_CODE (X) == LO_SUM \
1433 && GET_CODE (XEXP (X, 0)) == REG \
1434 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1435 && CONSTANT_P (XEXP (X, 1)) \
1436 && (TARGET_SOFT_FLOAT \
1437 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1440 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1441 || ((MODE) != SFmode \
1442 && (MODE) != DFmode))) \
1444 else if (GET_CODE (X) == LO_SUM \
1445 && GET_CODE (XEXP (X, 0)) == SUBREG \
1446 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1447 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1448 && CONSTANT_P (XEXP (X, 1)) \
1449 && (TARGET_SOFT_FLOAT \
1450 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1453 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1454 || ((MODE) != SFmode \
1455 && (MODE) != DFmode))) \
1457 else if (GET_CODE (X) == LABEL_REF \
1458 || (GET_CODE (X) == CONST_INT \
1459 && INT_5_BITS (X))) \
1461 /* Needed for -fPIC */ \
1462 else if (GET_CODE (X) == LO_SUM \
1463 && GET_CODE (XEXP (X, 0)) == REG \
1464 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1465 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1466 && (TARGET_SOFT_FLOAT \
1467 || (TARGET_PA_20 && !TARGET_ELF32) \
1468 || ((MODE) != SFmode \
1469 && (MODE) != DFmode))) \
1473 /* Look for machine dependent ways to make the invalid address AD a
1476 For the PA, transform:
1478 memory(X + <large int>)
1482 if (<large int> & mask) >= 16
1483 Y = (<large int> & ~mask) + mask + 1 Round up.
1485 Y = (<large int> & ~mask) Round down.
1487 memory (Z + (<large int> - Y));
1489 This makes reload inheritance and reload_cse work better since Z
1492 There may be more opportunities to improve code with this hook. */
1493 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1495 long offset, newoffset, mask; \
1496 rtx new, temp = NULL_RTX; \
1498 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1499 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1501 if (optimize && GET_CODE (AD) == PLUS) \
1502 temp = simplify_binary_operation (PLUS, Pmode, \
1503 XEXP (AD, 0), XEXP (AD, 1)); \
1505 new = temp ? temp : AD; \
1508 && GET_CODE (new) == PLUS \
1509 && GET_CODE (XEXP (new, 0)) == REG \
1510 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1512 offset = INTVAL (XEXP ((new), 1)); \
1514 /* Choose rounding direction. Round up if we are >= halfway. */ \
1515 if ((offset & mask) >= ((mask + 1) / 2)) \
1516 newoffset = (offset & ~mask) + mask + 1; \
1518 newoffset = offset & ~mask; \
1520 /* Ensure that long displacements are aligned. */ \
1521 if (!VAL_5_BITS_P (newoffset) \
1522 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1523 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1525 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1527 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1528 GEN_INT (newoffset)); \
1529 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1530 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1531 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1541 /* Try machine-dependent ways of modifying an illegitimate address
1542 to be legitimate. If we find one, return the new, valid address.
1543 This macro is used in only one place: `memory_address' in explow.c.
1545 OLDX is the address as it was before break_out_memory_refs was called.
1546 In some cases it is useful to look at this to decide what needs to be done.
1548 MODE and WIN are passed so that this macro can use
1549 GO_IF_LEGITIMATE_ADDRESS.
1551 It is always safe for this macro to do nothing. It exists to recognize
1552 opportunities to optimize the output. */
1554 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1555 { rtx orig_x = (X); \
1556 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1557 if ((X) != orig_x && memory_address_p (MODE, X)) \
1560 /* Go to LABEL if ADDR (a legitimate address expression)
1561 has an effect that depends on the machine mode it is used for. */
1563 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1565 #define TARGET_ASM_SELECT_SECTION pa_select_section
1567 /* Return a nonzero value if DECL has a section attribute. */
1568 #define IN_NAMED_SECTION_P(DECL) \
1569 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1570 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1572 /* Define this macro if references to a symbol must be treated
1573 differently depending on something about the variable or
1574 function named by the symbol (such as what section it is in).
1576 The macro definition, if any, is executed immediately after the
1577 rtl for DECL or other node is created.
1578 The value of the rtl will be a `mem' whose address is a
1581 The usual thing for this macro to do is to a flag in the
1582 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1583 name string in the `symbol_ref' (if one bit is not enough
1586 On the HP-PA we use this to indicate if a symbol is in text or
1587 data space. Also, function labels need special treatment. */
1589 #define TEXT_SPACE_P(DECL)\
1590 (TREE_CODE (DECL) == FUNCTION_DECL \
1591 || (TREE_CODE (DECL) == VAR_DECL \
1592 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1593 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1595 || CONSTANT_CLASS_P (DECL))
1597 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1599 /* Specify the machine mode that this machine uses for the index in the
1600 tablejump instruction. For small tables, an element consists of a
1601 ia-relative branch and its delay slot. When -mbig-switch is specified,
1602 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1603 for both 32 and 64-bit pic code. */
1604 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1606 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1607 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1609 /* Define this as 1 if `char' should by default be signed; else as 0. */
1610 #define DEFAULT_SIGNED_CHAR 1
1612 /* Max number of bytes we can move from memory to memory
1613 in one reasonably fast instruction. */
1616 /* Higher than the default as we prefer to use simple move insns
1617 (better scheduling and delay slot filling) and because our
1618 built-in block move is really a 2X unrolled loop.
1620 Believe it or not, this has to be big enough to allow for copying all
1621 arguments passed in registers to avoid infinite recursion during argument
1622 setup for a function call. Why? Consider how we copy the stack slots
1623 reserved for parameters when they may be trashed by a call. */
1624 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1626 /* Define if operations between registers always perform the operation
1627 on the full register even if a narrower mode is specified. */
1628 #define WORD_REGISTER_OPERATIONS
1630 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1631 will either zero-extend or sign-extend. The value of this macro should
1632 be the code that says which one of the two operations is implicitly
1633 done, UNKNOWN if none. */
1634 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1636 /* Nonzero if access to memory by bytes is slow and undesirable. */
1637 #define SLOW_BYTE_ACCESS 1
1639 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1640 is done just by pretending it is already truncated. */
1641 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1643 /* Specify the machine mode that pointers have.
1644 After generation of rtl, the compiler makes no further distinction
1645 between pointers and any other objects of this machine mode. */
1646 #define Pmode word_mode
1648 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1649 return the mode to be used for the comparison. For floating-point, CCFPmode
1650 should be used. CC_NOOVmode should be used when the first operand is a
1651 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1653 #define SELECT_CC_MODE(OP,X,Y) \
1654 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1656 /* A function address in a call instruction
1657 is a byte address (for indexing purposes)
1658 so give the MEM rtx a byte's mode. */
1659 #define FUNCTION_MODE SImode
1661 /* Define this if addresses of constant functions
1662 shouldn't be put through pseudo regs where they can be cse'd.
1663 Desirable on machines where ordinary constants are expensive
1664 but a CALL with constant address is cheap. */
1665 #define NO_FUNCTION_CSE
1667 /* Define this to be nonzero if shift instructions ignore all but the low-order
1669 #define SHIFT_COUNT_TRUNCATED 1
1671 /* Compute extra cost of moving data between one register class
1674 Make moves from SAR so expensive they should never happen. We used to
1675 have 0xffff here, but that generates overflow in rare cases.
1677 Copies involving a FP register and a non-FP register are relatively
1678 expensive because they must go through memory.
1680 Other copies are reasonably cheap. */
1681 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1682 (CLASS1 == SHIFT_REGS ? 0x100 \
1683 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1684 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1687 /* Adjust the cost of branches. */
1688 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1690 /* Handling the special cases is going to get too complicated for a macro,
1691 just call `pa_adjust_insn_length' to do the real work. */
1692 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1693 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1695 /* Millicode insns are actually function calls with some special
1696 constraints on arguments and register usage.
1698 Millicode calls always expect their arguments in the integer argument
1699 registers, and always return their result in %r29 (ret1). They
1700 are expected to clobber their arguments, %r1, %r29, and the return
1701 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1703 This macro tells reorg that the references to arguments and
1704 millicode calls do not appear to happen until after the millicode call.
1705 This allows reorg to put insns which set the argument registers into the
1706 delay slot of the millicode call -- thus they act more like traditional
1709 Note we cannot consider side effects of the insn to be delayed because
1710 the branch and link insn will clobber the return pointer. If we happened
1711 to use the return pointer in the delay slot of the call, then we lose.
1713 get_attr_type will try to recognize the given insn, so make sure to
1714 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1716 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1719 /* Control the assembler format that we output. */
1721 /* A C string constant describing how to begin a comment in the target
1722 assembler language. The compiler assumes that the comment will end at
1723 the end of the line. */
1725 #define ASM_COMMENT_START ";"
1727 /* Output to assembler file text saying following lines
1728 may contain character constants, extra white space, comments, etc. */
1730 #define ASM_APP_ON ""
1732 /* Output to assembler file text saying following lines
1733 no longer contain unusual constructs. */
1735 #define ASM_APP_OFF ""
1737 /* This is how to output the definition of a user-level label named NAME,
1738 such as the label on a static function or variable NAME. */
1740 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1741 do { assemble_name (FILE, NAME); \
1742 fputc ('\n', FILE); } while (0)
1744 /* This is how to output a reference to a user-level label named NAME.
1745 `assemble_name' uses this. */
1747 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1749 const char *xname = (NAME); \
1750 if (FUNCTION_NAME_P (NAME)) \
1752 if (xname[0] == '*') \
1755 fputs (user_label_prefix, FILE); \
1756 fputs (xname, FILE); \
1759 /* This how we output the symbol_ref X. */
1761 #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1763 SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1764 assemble_name (FILE, XSTR (X, 0)); \
1767 /* This is how to store into the string LABEL
1768 the symbol_ref name of an internal numbered label where
1769 PREFIX is the class of label and NUM is the number within the class.
1770 This is suitable for output with `assemble_name'. */
1772 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1773 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1775 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1777 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1778 output_ascii ((FILE), (P), (SIZE))
1780 /* Jump tables are always placed in the text section. Technically, it
1781 is possible to put them in the readonly data section when -mbig-switch
1782 is specified. This has the benefit of getting the table out of .text
1783 and reducing branch lengths as a result. The downside is that an
1784 additional insn (addil) is needed to access the table when generating
1785 PIC code. The address difference table also has to use 32-bit
1786 pc-relative relocations. Currently, GAS does not support these
1787 relocations, although it is easily modified to do this operation.
1788 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1789 when using ELF GAS. A simple difference can be used when using
1790 SOM GAS or the HP assembler. The final downside is GDB complains
1791 about the nesting of the label for the table when debugging. */
1793 #define JUMP_TABLES_IN_TEXT_SECTION 1
1795 /* This is how to output an element of a case-vector that is absolute. */
1797 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1798 if (TARGET_BIG_SWITCH) \
1799 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1801 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1803 /* This is how to output an element of a case-vector that is relative.
1804 Since we always place jump tables in the text section, the difference
1805 is absolute and requires no relocation. */
1807 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1808 if (TARGET_BIG_SWITCH) \
1809 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1811 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1813 /* This is how to output an assembler line that says to advance the
1814 location counter to a multiple of 2**LOG bytes. */
1816 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1817 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1819 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1820 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1821 (unsigned HOST_WIDE_INT)(SIZE))
1823 /* This says how to output an assembler line to define an uninitialized
1824 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1825 This macro exists to properly support languages like C++ which do not
1826 have common data. */
1828 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1829 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1831 /* This says how to output an assembler line to define a global common symbol
1832 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1834 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1835 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1837 /* This says how to output an assembler line to define a local common symbol
1838 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1839 controls how the assembler definitions of uninitialized static variables
1842 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1843 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1846 #define ASM_PN_FORMAT "%s___%lu"
1848 /* All HP assemblers use "!" to separate logical lines. */
1849 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1851 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1852 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1854 /* Print operand X (an rtx) in assembler syntax to file FILE.
1855 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1856 For `%' followed by punctuation, CODE is the punctuation and X is null.
1858 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1859 and an immediate zero should be represented as `r0'.
1861 Several % codes are defined:
1863 C compare conditions
1864 N extract conditions
1865 M modifier to handle preincrement addressing for memory refs.
1866 F modifier to handle preincrement addressing for fp memory refs */
1868 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1871 /* Print a memory address as an operand to reference that memory location. */
1873 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1874 { rtx addr = ADDR; \
1875 switch (GET_CODE (addr)) \
1878 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1881 gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1882 fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
1883 reg_names [REGNO (XEXP (addr, 0))]); \
1886 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1887 fputs ("R'", FILE); \
1888 else if (flag_pic == 0) \
1889 fputs ("RR'", FILE); \
1891 fputs ("RT'", FILE); \
1892 output_global_address (FILE, XEXP (addr, 1), 0); \
1893 fputs ("(", FILE); \
1894 output_operand (XEXP (addr, 0), 0); \
1895 fputs (")", FILE); \
1898 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1901 output_addr_const (FILE, addr); \
1905 /* Find the return address associated with the frame given by
1907 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1908 (return_addr_rtx (COUNT, FRAMEADDR))
1910 /* Used to mask out junk bits from the return address, such as
1911 processor state, interrupt status, condition codes and the like. */
1912 #define MASK_RETURN_ADDR \
1913 /* The privilege level is in the two low order bits, mask em out \
1914 of the return address. */ \
1917 /* The number of Pmode words for the setjmp buffer. */
1918 #define JMP_BUF_SIZE 50
1920 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1921 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1922 "__canonicalize_funcptr_for_compare"
1925 #undef TARGET_HAVE_TLS
1926 #define TARGET_HAVE_TLS true
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