1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* Which architecture to generate code for. */
50 enum architecture_type
59 /* For -march= option. */
60 extern const char *pa_arch_string;
61 extern enum architecture_type pa_arch;
63 /* For -mfixed-range= option. */
64 extern const char *pa_fixed_range_string;
66 /* For -mschedule= option. */
67 extern const char *pa_cpu_string;
68 extern enum processor_type pa_cpu;
70 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
72 /* Print subsidiary information on the compiler version in use. */
74 #define TARGET_VERSION fputs (" (hppa)", stderr);
76 /* Run-time compilation parameters selecting different hardware subsets. */
78 extern int target_flags;
80 /* compile code for HP-PA 1.1 ("Snake"). */
84 /* Disable all FP registers (they all become fixed). This may be necessary
85 for compiling kernels which perform lazy context switching of FP regs.
86 Note if you use this option and try to perform floating point operations
87 the compiler will abort! */
89 #define MASK_DISABLE_FPREGS 2
90 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
92 /* Generate code which assumes that all space register are equivalent.
93 Triggers aggressive unscaled index addressing and faster
94 builtin_return_address. */
95 #define MASK_NO_SPACE_REGS 4
96 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
98 /* Allow unconditional jumps in the delay slots of call instructions. */
99 #define MASK_JUMP_IN_DELAY 8
100 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
102 /* Disable indexed addressing modes. */
103 #define MASK_DISABLE_INDEXING 32
104 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
106 /* Emit code which follows the new portable runtime calling conventions
107 HP wants everyone to use for ELF objects. If at all possible you want
108 to avoid this since it's a performance loss for non-prototyped code.
110 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
111 long-call stubs which is quite expensive. */
112 #define MASK_PORTABLE_RUNTIME 64
113 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
115 /* Emit directives only understood by GAS. This allows parameter
116 relocations to work for static functions. There is no way
117 to make them work the HP assembler at this time. */
119 #define TARGET_GAS (target_flags & MASK_GAS)
121 /* Emit code for processors which do not have an FPU. */
122 #define MASK_SOFT_FLOAT 256
123 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
125 /* Use 3-insn load/store sequences for access to large data segments
126 in shared libraries on hpux10. */
127 #define MASK_LONG_LOAD_STORE 512
128 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
130 /* Use a faster sequence for indirect calls. This assumes that calls
131 through function pointers will never cross a space boundary, and
132 that the executable is not dynamically linked. Such assumptions
133 are generally safe for building kernels and statically linked
134 executables. Code compiled with this option will fail miserably if
135 the executable is dynamically linked or uses nested functions! */
136 #define MASK_FAST_INDIRECT_CALLS 1024
137 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
139 /* Generate code with big switch statements to avoid out of range branches
140 occurring within the switch table. */
141 #define MASK_BIG_SWITCH 2048
142 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
144 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
145 true when this is true. */
146 #define MASK_PA_20 4096
148 /* Generate cpp defines for server I/O. */
149 #define MASK_SIO 8192
150 #define TARGET_SIO (target_flags & MASK_SIO)
152 /* Assume GNU linker by default. */
153 #define MASK_GNU_LD 16384
154 #ifndef TARGET_GNU_LD
155 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
158 /* Force generation of long calls. */
159 #define MASK_LONG_CALLS 32768
160 #ifndef TARGET_LONG_CALLS
161 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
165 #define TARGET_PA_10 (target_flags & (MASK_PA_11 | MASK_PA_20) == 0)
169 #define TARGET_PA_11 (target_flags & MASK_PA_11)
173 #define TARGET_PA_20 (target_flags & MASK_PA_20)
176 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
178 #define TARGET_64BIT 0
181 /* Generate code for ELF32 ABI. */
183 #define TARGET_ELF32 0
186 /* Generate code for SOM 32bit ABI. */
191 /* The following three defines are potential target switches. The current
192 defines are optimal given the current capabilities of GAS and GNU ld. */
194 /* Define to a C expression evaluating to true to use long absolute calls.
195 Currently, only the HP assembler and SOM linker support long absolute
196 calls. They are used only in non-pic code. */
197 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
199 /* Define to a C expression evaluating to true to use long pic symbol
200 difference calls. This is a call variant similar to the long pic
201 pc-relative call. Long pic symbol difference calls are only used with
202 the HP SOM linker. Currently, only the HP assembler supports these
203 calls. GAS doesn't allow an arbitrary difference of two symbols. */
204 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
206 /* Define to a C expression evaluating to true to use long pic
207 pc-relative calls. Long pic pc-relative calls are only used with
208 GAS. Currently, they are usable for calls within a module but
209 not for external calls. */
210 #define TARGET_LONG_PIC_PCREL_CALL 0
212 /* Define to a C expression evaluating to true to use SOM secondary
213 definition symbols for weak support. Linker support for secondary
214 definition symbols is buggy prior to HP-UX 11.X. */
215 #define TARGET_SOM_SDEF 0
217 /* Define to a C expression evaluating to true to save the entry value
218 of SP in the current frame marker. This is normally unnecessary.
219 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
220 HP compilers don't use this flag but it is supported by the assembler.
221 We set this flag to indicate that register %r3 has been saved at the
222 start of the frame. Thus, when the HP unwind library is used, we
223 need to generate additional code to save SP into the frame marker. */
224 #define TARGET_HPUX_UNWIND_LIBRARY 0
226 /* Macro to define tables used to set the flags. This is a
227 list in braces of target switches with each switch being
228 { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set,
229 or minus the bits to clear. An empty string NAME is used to
230 identify the default VALUE. Do not mark empty strings for
233 #define TARGET_SWITCHES \
234 {{ "snake", MASK_PA_11, \
235 N_("Generate PA1.1 code") }, \
236 { "nosnake", -(MASK_PA_11 | MASK_PA_20), \
237 N_("Generate PA1.0 code") }, \
238 { "pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), \
239 N_("Generate PA1.0 code") }, \
240 { "pa-risc-1-1", MASK_PA_11, \
241 N_("Generate PA1.1 code") }, \
242 { "pa-risc-2-0", MASK_PA_20, \
243 N_("Generate PA2.0 code (requires binutils 2.10 or later)") }, \
244 { "disable-fpregs", MASK_DISABLE_FPREGS, \
245 N_("Disable FP regs") }, \
246 { "no-disable-fpregs", -MASK_DISABLE_FPREGS, \
247 N_("Do not disable FP regs") }, \
248 { "no-space-regs", MASK_NO_SPACE_REGS, \
249 N_("Disable space regs") }, \
250 { "space-regs", -MASK_NO_SPACE_REGS, \
251 N_("Do not disable space regs") }, \
252 { "jump-in-delay", MASK_JUMP_IN_DELAY, \
253 N_("Put jumps in call delay slots") }, \
254 { "no-jump-in-delay", -MASK_JUMP_IN_DELAY, \
255 N_("Do not put jumps in call delay slots") }, \
256 { "disable-indexing", MASK_DISABLE_INDEXING, \
257 N_("Disable indexed addressing") }, \
258 { "no-disable-indexing", -MASK_DISABLE_INDEXING, \
259 N_("Do not disable indexed addressing") }, \
260 { "portable-runtime", MASK_PORTABLE_RUNTIME, \
261 N_("Use portable calling conventions") }, \
262 { "no-portable-runtime", -MASK_PORTABLE_RUNTIME, \
263 N_("Do not use portable calling conventions") }, \
265 N_("Assume code will be assembled by GAS") }, \
266 { "no-gas", -MASK_GAS, \
267 N_("Do not assume code will be assembled by GAS") }, \
268 { "soft-float", MASK_SOFT_FLOAT, \
269 N_("Use software floating point") }, \
270 { "no-soft-float", -MASK_SOFT_FLOAT, \
271 N_("Do not use software floating point") }, \
272 { "long-load-store", MASK_LONG_LOAD_STORE, \
273 N_("Emit long load/store sequences") }, \
274 { "no-long-load-store", -MASK_LONG_LOAD_STORE, \
275 N_("Do not emit long load/store sequences") }, \
276 { "fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, \
277 N_("Generate fast indirect calls") }, \
278 { "no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, \
279 N_("Do not generate fast indirect calls") }, \
280 { "big-switch", MASK_BIG_SWITCH, \
281 N_("Generate code for huge switch statements") }, \
282 { "no-big-switch", -MASK_BIG_SWITCH, \
283 N_("Do not generate code for huge switch statements") }, \
284 { "long-calls", MASK_LONG_CALLS, \
285 N_("Always generate long calls") }, \
286 { "no-long-calls", -MASK_LONG_CALLS, \
287 N_("Generate long calls only when needed") }, \
289 N_("Enable linker optimizations") }, \
291 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
294 #ifndef TARGET_DEFAULT
295 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY | MASK_BIG_SWITCH)
298 #ifndef TARGET_CPU_DEFAULT
299 #define TARGET_CPU_DEFAULT 0
302 #ifndef SUBTARGET_SWITCHES
303 #define SUBTARGET_SWITCHES
306 #ifndef TARGET_SCHED_DEFAULT
307 #define TARGET_SCHED_DEFAULT "8000"
310 #define TARGET_OPTIONS \
312 { "arch=", &pa_arch_string, \
313 N_("Specify PA-RISC architecture for code generation. " \
314 "Values are 1.0, 1.1 and 2.0."), 0}, \
315 { "fixed-range=", &pa_fixed_range_string, \
316 N_("Specify range of registers to make fixed"), 0}, \
317 { "schedule=", &pa_cpu_string, \
318 N_("Specify CPU for scheduling purposes"), 0} \
321 /* Support for a compile-time default CPU, et cetera. The rules are:
322 --with-schedule is ignored if -mschedule is specified.
323 --with-arch is ignored if -march is specified. */
324 #define OPTION_DEFAULT_SPECS \
325 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
326 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
328 /* Specify the dialect of assembler to use. New mnemonics is dialect one
329 and the old mnemonics are dialect zero. */
330 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
332 #define OVERRIDE_OPTIONS override_options ()
334 /* Override some settings from dbxelf.h. */
336 /* We do not have to be compatible with dbx, so we enable gdb extensions
338 #define DEFAULT_GDB_EXTENSIONS 1
340 /* This used to be zero (no max length), but big enums and such can
341 cause huge strings which killed gas.
343 We also have to avoid lossage in dbxout.c -- it does not compute the
344 string size accurately, so we are real conservative here. */
345 #undef DBX_CONTIN_LENGTH
346 #define DBX_CONTIN_LENGTH 3000
348 /* Only labels should ever begin in column zero. */
349 #define ASM_STABS_OP "\t.stabs\t"
350 #define ASM_STABN_OP "\t.stabn\t"
352 /* GDB always assumes the current function's frame begins at the value
353 of the stack pointer upon entry to the current function. Accessing
354 local variables and parameters passed on the stack is done using the
355 base of the frame + an offset provided by GCC.
357 For functions which have frame pointers this method works fine;
358 the (frame pointer) == (stack pointer at function entry) and GCC provides
359 an offset relative to the frame pointer.
361 This loses for functions without a frame pointer; GCC provides an offset
362 which is relative to the stack pointer after adjusting for the function's
363 frame size. GDB would prefer the offset to be relative to the value of
364 the stack pointer at the function's entry. Yuk! */
365 #define DEBUGGER_AUTO_OFFSET(X) \
366 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
367 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
369 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
370 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
371 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
373 #define TARGET_CPU_CPP_BUILTINS() \
375 builtin_assert("cpu=hppa"); \
376 builtin_assert("machine=hppa"); \
377 builtin_define("__hppa"); \
378 builtin_define("__hppa__"); \
380 builtin_define("_PA_RISC2_0"); \
381 else if (TARGET_PA_11) \
382 builtin_define("_PA_RISC1_1"); \
384 builtin_define("_PA_RISC1_0"); \
387 /* An old set of OS defines for various BSD-like systems. */
388 #define TARGET_OS_CPP_BUILTINS() \
391 builtin_define_std ("REVARGV"); \
392 builtin_define_std ("hp800"); \
393 builtin_define_std ("hp9000"); \
394 builtin_define_std ("hp9k8"); \
395 if (!c_dialect_cxx () && !flag_iso) \
396 builtin_define ("hppa"); \
397 builtin_define_std ("spectrum"); \
398 builtin_define_std ("unix"); \
399 builtin_assert ("system=bsd"); \
400 builtin_assert ("system=unix"); \
404 #define CC1_SPEC "%{pg:} %{p:}"
406 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
408 /* We don't want -lg. */
410 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
413 /* This macro defines command-line switches that modify the default
416 The definition is be an initializer for an array of structures. Each
417 array element has have three elements: the switch name, one of the
418 enumeration codes ADD or DELETE to indicate whether the string should be
419 inserted or deleted, and the string to be inserted or deleted. */
420 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
422 /* Make gcc agree with <machine/ansi.h> */
424 #define SIZE_TYPE "unsigned int"
425 #define PTRDIFF_TYPE "int"
426 #define WCHAR_TYPE "unsigned int"
427 #define WCHAR_TYPE_SIZE 32
429 /* Show we can debug even without a frame pointer. */
430 #define CAN_DEBUG_WITHOUT_FP
432 /* target machine storage layout */
433 typedef struct machine_function GTY(())
435 /* Flag indicating that a .NSUBSPA directive has been output for
440 /* Define this macro if it is advisable to hold scalars in registers
441 in a wider mode than that declared by the program. In such cases,
442 the value is constrained to be within the bounds of the declared
443 type, but kept valid in the wider mode. The signedness of the
444 extension may differ from that of the type. */
446 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
447 if (GET_MODE_CLASS (MODE) == MODE_INT \
448 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
451 /* Define this if most significant bit is lowest numbered
452 in instructions that operate on numbered bit-fields. */
453 #define BITS_BIG_ENDIAN 1
455 /* Define this if most significant byte of a word is the lowest numbered. */
456 /* That is true on the HP-PA. */
457 #define BYTES_BIG_ENDIAN 1
459 /* Define this if most significant word of a multiword number is lowest
461 #define WORDS_BIG_ENDIAN 1
463 #define MAX_BITS_PER_WORD 64
465 /* Width of a word, in units (bytes). */
466 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
467 #define MIN_UNITS_PER_WORD 4
469 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
470 #define PARM_BOUNDARY BITS_PER_WORD
472 /* Largest alignment required for any stack parameter, in bits.
473 Don't define this if it is equal to PARM_BOUNDARY */
474 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
476 /* Boundary (in *bits*) on which stack pointer is always aligned;
477 certain optimizations in combine depend on this.
479 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
480 the stack on the 32 and 64-bit ports, respectively. However, we
481 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
482 in main. Thus, we treat the former as the preferred alignment. */
483 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
484 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
486 /* Allocation boundary (in *bits*) for the code of a function. */
487 #define FUNCTION_BOUNDARY BITS_PER_WORD
489 /* Alignment of field after `int : 0' in a structure. */
490 #define EMPTY_FIELD_BOUNDARY 32
492 /* Every structure's size must be a multiple of this. */
493 #define STRUCTURE_SIZE_BOUNDARY 8
495 /* A bit-field declared as `int' forces `int' alignment for the struct. */
496 #define PCC_BITFIELD_TYPE_MATTERS 1
498 /* No data type wants to be aligned rounder than this. */
499 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
501 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
502 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
503 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
505 /* Make arrays of chars word-aligned for the same reasons. */
506 #define DATA_ALIGNMENT(TYPE, ALIGN) \
507 (TREE_CODE (TYPE) == ARRAY_TYPE \
508 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
509 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
511 /* Set this nonzero if move instructions will actually fail to work
512 when given unaligned data. */
513 #define STRICT_ALIGNMENT 1
515 /* Value is 1 if it is a good idea to tie two pseudo registers
516 when one has mode MODE1 and one has mode MODE2.
517 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
518 for any hard reg, then this must be 0 for correct output. */
519 #define MODES_TIEABLE_P(MODE1, MODE2) \
520 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
522 /* Specify the registers used for certain standard purposes.
523 The values of these macros are register numbers. */
525 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
526 /* #define PC_REGNUM */
528 /* Register to use for pushing function arguments. */
529 #define STACK_POINTER_REGNUM 30
531 /* Base register for access to local variables of the function. */
532 #define FRAME_POINTER_REGNUM 3
534 /* Value should be nonzero if functions must have frame pointers. */
535 #define FRAME_POINTER_REQUIRED \
536 (current_function_calls_alloca)
538 /* C statement to store the difference between the frame pointer
539 and the stack pointer values immediately after the function prologue.
541 Note, we always pretend that this is a leaf function because if
542 it's not, there's no point in trying to eliminate the
543 frame pointer. If it is a leaf function, we guessed right! */
544 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
545 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
547 /* Base register for access to arguments of the function. */
548 #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
550 /* Register in which static-chain is passed to a function. */
551 #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
553 /* Register used to address the offset table for position-independent
555 #define PIC_OFFSET_TABLE_REGNUM \
556 (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
558 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
560 /* Function to return the rtx used to save the pic offset table register
561 across function calls. */
562 extern struct rtx_def *hppa_pic_save_rtx (void);
564 #define DEFAULT_PCC_STRUCT_RETURN 0
566 /* Register in which address to store a structure value
567 is passed to a function. */
568 #define PA_STRUCT_VALUE_REGNUM 28
570 /* Describe how we implement __builtin_eh_return. */
571 #define EH_RETURN_DATA_REGNO(N) \
572 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
573 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
574 #define EH_RETURN_HANDLER_RTX \
575 gen_rtx_MEM (word_mode, \
576 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
577 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
580 /* Offset from the argument pointer register value to the top of
581 stack. This is different from FIRST_PARM_OFFSET because of the
583 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
585 /* The letters I, J, K, L and M in a register constraint string
586 can be used to stand for particular ranges of immediate operands.
587 This macro defines what the ranges are.
588 C is the letter, and VALUE is a constant value.
589 Return 1 if VALUE is in the range specified by C.
591 `I' is used for the 11 bit constants.
592 `J' is used for the 14 bit constants.
593 `K' is used for values that can be moved with a zdepi insn.
594 `L' is used for the 5 bit constants.
596 `N' is used for values with the least significant 11 bits equal to zero
597 and when sign extended from 32 to 64 bits the
598 value does not change.
599 `O' is used for numbers n such that n+1 is a power of 2.
602 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
603 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
604 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
605 : (C) == 'K' ? zdepi_cint_p (VALUE) \
606 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
607 : (C) == 'M' ? (VALUE) == 0 \
608 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
609 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
610 == (HOST_WIDE_INT) -1 << 31)) \
611 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
612 : (C) == 'P' ? and_mask_p (VALUE) \
615 /* Similar, but for floating or large integer constants, and defining letters
616 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
618 For PA, `G' is the floating-point constant zero. `H' is undefined. */
620 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
621 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
622 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
625 /* The class value for index registers, and the one for base regs. */
626 #define INDEX_REG_CLASS GENERAL_REGS
627 #define BASE_REG_CLASS GENERAL_REGS
629 #define FP_REG_CLASS_P(CLASS) \
630 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
632 /* True if register is floating-point. */
633 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
635 /* Given an rtx X being reloaded into a reg required to be
636 in class CLASS, return the class of reg to actually use.
637 In general this is just CLASS; but on some machines
638 in some cases it is preferable to use a more restrictive class. */
639 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
641 /* Return the register class of a scratch register needed to copy
642 IN into a register in CLASS in MODE, or a register in CLASS in MODE
643 to IN. If it can be done directly NO_REGS is returned.
645 Avoid doing any work for the common case calls. */
646 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
647 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
648 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
649 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
651 #define MAYBE_FP_REG_CLASS_P(CLASS) \
652 reg_classes_intersect_p ((CLASS), FP_REGS)
654 /* On the PA it is not possible to directly move data between
655 GENERAL_REGS and FP_REGS. */
656 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
657 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
658 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
660 /* Return the stack location to use for secondary memory needed reloads. */
661 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
662 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
665 /* Stack layout; function entry, exit and calling. */
667 /* Define this if pushing a word on the stack
668 makes the stack pointer a smaller address. */
669 /* #define STACK_GROWS_DOWNWARD */
671 /* Believe it or not. */
672 #define ARGS_GROW_DOWNWARD
674 /* Define this if the nominal address of the stack frame
675 is at the high-address end of the local variables;
676 that is, each additional local variable allocated
677 goes at a more negative offset in the frame. */
678 /* #define FRAME_GROWS_DOWNWARD */
680 /* Offset within stack frame to start allocating local variables at.
681 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
682 first local allocated. Otherwise, it is the offset to the BEGINNING
683 of the first local allocated.
685 On the 32-bit ports, we reserve one slot for the previous frame
686 pointer and one fill slot. The fill slot is for compatibility
687 with HP compiled programs. On the 64-bit ports, we reserve one
688 slot for the previous frame pointer. */
689 #define STARTING_FRAME_OFFSET 8
691 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
692 of the stack. The default is to align it to STACK_BOUNDARY. */
693 #define STACK_ALIGNMENT_NEEDED 0
695 /* If we generate an insn to push BYTES bytes,
696 this says how many the stack pointer really advances by.
697 On the HP-PA, don't define this because there are no push insns. */
698 /* #define PUSH_ROUNDING(BYTES) */
700 /* Offset of first parameter from the argument pointer register value.
701 This value will be negated because the arguments grow down.
702 Also note that on STACK_GROWS_UPWARD machines (such as this one)
703 this is the distance from the frame pointer to the end of the first
704 argument, not it's beginning. To get the real offset of the first
705 argument, the size of the argument must be added. */
707 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
709 /* When a parameter is passed in a register, stack space is still
711 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
713 /* Define this if the above stack space is to be considered part of the
714 space allocated by the caller. */
715 #define OUTGOING_REG_PARM_STACK_SPACE
717 /* Keep the stack pointer constant throughout the function.
718 This is both an optimization and a necessity: longjmp
719 doesn't behave itself when the stack pointer moves within
721 #define ACCUMULATE_OUTGOING_ARGS 1
723 /* The weird HPPA calling conventions require a minimum of 48 bytes on
724 the stack: 16 bytes for register saves, and 32 bytes for magic.
725 This is the difference between the logical top of stack and the
728 On the 64-bit port, the HP C compiler allocates a 48-byte frame
729 marker, although the runtime documentation only describes a 16
730 byte marker. For compatibility, we allocate 48 bytes. */
731 #define STACK_POINTER_OFFSET \
732 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
734 #define STACK_DYNAMIC_OFFSET(FNDECL) \
736 ? (STACK_POINTER_OFFSET) \
737 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
739 /* Value is 1 if returning from a function call automatically
740 pops the arguments described by the number-of-args field in the call.
741 FUNDECL is the declaration node of the function (as a tree),
742 FUNTYPE is the data type of the function (as a tree),
743 or for a library call it is an identifier node for the subroutine name. */
745 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
747 /* Define how to find the value returned by a function.
748 VALTYPE is the data type of the value (as a tree).
749 If the precise function being called is known, FUNC is its FUNCTION_DECL;
750 otherwise, FUNC is 0. */
752 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
754 /* Define how to find the value returned by a library function
755 assuming the value has mode MODE. */
757 #define LIBCALL_VALUE(MODE) \
759 (! TARGET_SOFT_FLOAT \
760 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
762 /* 1 if N is a possible register number for a function value
763 as seen by the caller. */
765 #define FUNCTION_VALUE_REGNO_P(N) \
766 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
769 /* Define a data type for recording info about an argument list
770 during the scan of that argument list. This data type should
771 hold all necessary information about the function itself
772 and about the args processed so far, enough to enable macros
773 such as FUNCTION_ARG to determine where the next arg should go.
775 On the HP-PA, the WORDS field holds the number of words
776 of arguments scanned so far (including the invisible argument,
777 if any, which holds the structure-value-address). Thus, 4 or
778 more means all following args should go on the stack.
780 The INCOMING field tracks whether this is an "incoming" or
783 The INDIRECT field indicates whether this is is an indirect
786 The NARGS_PROTOTYPE field indicates that an argument does not
787 have a prototype when it less than or equal to 0. */
789 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
791 #define CUMULATIVE_ARGS struct hppa_args
793 /* Initialize a variable CUM of type CUMULATIVE_ARGS
794 for a call to a function whose data type is FNTYPE.
795 For a library call, FNTYPE is 0. */
797 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
799 (CUM).incoming = 0, \
800 (CUM).indirect = (FNTYPE) && !(FNDECL), \
801 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
802 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
803 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
804 || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
809 /* Similar, but when scanning the definition of a procedure. We always
810 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
812 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
814 (CUM).incoming = 1, \
815 (CUM).indirect = 0, \
816 (CUM).nargs_prototype = 1000
818 /* Figure out the size in words of the function argument. The size
819 returned by this macro should always be greater than zero because
820 we pass variable and zero sized objects by reference. */
822 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
823 ((((MODE) != BLKmode \
824 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
825 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
827 /* Update the data in CUM to advance over an argument
828 of mode MODE and data type TYPE.
829 (TYPE is null for libcalls where that information may not be available.) */
831 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
832 { (CUM).nargs_prototype--; \
833 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
834 + (((CUM).words & 01) && (TYPE) != 0 \
835 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
838 /* Determine where to put an argument to a function.
839 Value is zero to push the argument on the stack,
840 or a hard register in which to store the argument.
842 MODE is the argument's machine mode.
843 TYPE is the data type of the argument (as a tree).
844 This is null for libcalls where that information may
846 CUM is a variable of type CUMULATIVE_ARGS which gives info about
847 the preceding args and about the function being called.
848 NAMED is nonzero if this argument is a named parameter
849 (otherwise it is an extra parameter matching an ellipsis).
851 On the HP-PA the first four words of args are normally in registers
852 and the rest are pushed. But any arg that won't entirely fit in regs
855 Arguments passed in registers are either 1 or 2 words long.
857 The caller must make a distinction between calls to explicitly named
858 functions and calls through pointers to functions -- the conventions
859 are different! Calls through pointers to functions only use general
860 registers for the first four argument words.
862 Of course all this is different for the portable runtime model
863 HP wants everyone to use for ELF. Ugh. Here's a quick description
864 of how it's supposed to work.
866 1) callee side remains unchanged. It expects integer args to be
867 in the integer registers, float args in the float registers and
868 unnamed args in integer registers.
870 2) caller side now depends on if the function being called has
871 a prototype in scope (rather than if it's being called indirectly).
873 2a) If there is a prototype in scope, then arguments are passed
874 according to their type (ints in integer registers, floats in float
875 registers, unnamed args in integer registers.
877 2b) If there is no prototype in scope, then floating point arguments
878 are passed in both integer and float registers. egad.
880 FYI: The portable parameter passing conventions are almost exactly like
881 the standard parameter passing conventions on the RS6000. That's why
882 you'll see lots of similar code in rs6000.h. */
884 /* If defined, a C expression which determines whether, and in which
885 direction, to pad out an argument with extra space. */
886 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
888 /* Specify padding for the last element of a block move between registers
891 The 64-bit runtime specifies that objects need to be left justified
892 (i.e., the normal justification for a big endian target). The 32-bit
893 runtime specifies right justification for objects smaller than 64 bits.
894 We use a DImode register in the parallel for 5 to 7 byte structures
895 so that there is only one element. This allows the object to be
897 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) (TARGET_64BIT ? upward : downward)
899 /* Do not expect to understand this without reading it several times. I'm
900 tempted to try and simply it, but I worry about breaking something. */
902 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
903 function_arg (&CUM, MODE, TYPE, NAMED)
905 /* For an arg passed partly in registers and partly in memory,
906 this is the number of registers used.
907 For args passed entirely in registers or entirely in memory, zero. */
909 /* For PA32 there are never split arguments. PA64, on the other hand, can
910 pass arguments partially in registers and partially in memory. */
911 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
912 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
914 /* If defined, a C expression that gives the alignment boundary, in
915 bits, of an argument with the specified mode and type. If it is
916 not defined, `PARM_BOUNDARY' is used for all arguments. */
918 /* Arguments larger than one word are double word aligned. */
920 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
922 ? (integer_zerop (TYPE_SIZE (TYPE)) \
923 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
924 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
925 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
926 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
928 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) 1
931 extern GTY(()) rtx hppa_compare_op0;
932 extern GTY(()) rtx hppa_compare_op1;
933 extern enum cmp_type hppa_branch_type;
935 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
936 as assembly via FUNCTION_PROFILER. Just output a local label.
937 We can't use the function label because the GAS SOM target can't
938 handle the difference of a global symbol and a local symbol. */
940 #ifndef FUNC_BEGIN_PROLOG_LABEL
941 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
944 #define FUNCTION_PROFILER(FILE, LABEL) \
945 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
947 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
948 void hppa_profile_hook (int label_no);
950 /* The profile counter if emitted must come before the prologue. */
951 #define PROFILE_BEFORE_PROLOGUE 1
953 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
954 the stack pointer does not matter. The value is tested only in
955 functions that have frame pointers.
956 No definition is equivalent to always zero. */
958 extern int may_call_alloca;
960 #define EXIT_IGNORE_STACK \
961 (get_frame_size () != 0 \
962 || current_function_calls_alloca || current_function_outgoing_args_size)
964 /* Output assembler code for a block containing the constant parts
965 of a trampoline, leaving space for the variable parts.\
967 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
968 and then branches to the specified routine.
970 This code template is copied from text segment to stack location
971 and then patched with INITIALIZE_TRAMPOLINE to contain
972 valid values, and then entered as a subroutine.
974 It is best to keep this as small as possible to avoid having to
975 flush multiple lines in the cache. */
977 #define TRAMPOLINE_TEMPLATE(FILE) \
981 fputs ("\tldw 36(%r22),%r21\n", FILE); \
982 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
983 if (ASSEMBLER_DIALECT == 0) \
984 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
986 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
987 fputs ("\tldw 4(%r21),%r19\n", FILE); \
988 fputs ("\tldw 0(%r21),%r21\n", FILE); \
991 fputs ("\tbve (%r21)\n", FILE); \
992 fputs ("\tldw 40(%r22),%r29\n", FILE); \
993 fputs ("\t.word 0\n", FILE); \
994 fputs ("\t.word 0\n", FILE); \
998 fputs ("\tldsid (%r21),%r1\n", FILE); \
999 fputs ("\tmtsp %r1,%sr0\n", FILE); \
1000 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
1001 fputs ("\tldw 40(%r22),%r29\n", FILE); \
1003 fputs ("\t.word 0\n", FILE); \
1004 fputs ("\t.word 0\n", FILE); \
1005 fputs ("\t.word 0\n", FILE); \
1006 fputs ("\t.word 0\n", FILE); \
1010 fputs ("\t.dword 0\n", FILE); \
1011 fputs ("\t.dword 0\n", FILE); \
1012 fputs ("\t.dword 0\n", FILE); \
1013 fputs ("\t.dword 0\n", FILE); \
1014 fputs ("\tmfia %r31\n", FILE); \
1015 fputs ("\tldd 24(%r31),%r1\n", FILE); \
1016 fputs ("\tldd 24(%r1),%r27\n", FILE); \
1017 fputs ("\tldd 16(%r1),%r1\n", FILE); \
1018 fputs ("\tbve (%r1)\n", FILE); \
1019 fputs ("\tldd 32(%r31),%r31\n", FILE); \
1020 fputs ("\t.dword 0 ; fptr\n", FILE); \
1021 fputs ("\t.dword 0 ; static link\n", FILE); \
1025 /* Length in units of the trampoline for entering a nested function. */
1027 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
1029 /* Length in units of the trampoline instruction code. */
1031 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
1033 /* Minimum length of a cache line. A length of 16 will work on all
1034 PA-RISC processors. All PA 1.1 processors have a cache line of
1035 32 bytes. Most but not all PA 2.0 processors have a cache line
1036 of 64 bytes. As cache flushes are expensive and we don't support
1037 PA 1.0, we use a minimum length of 32. */
1039 #define MIN_CACHELINE_SIZE 32
1041 /* Emit RTL insns to initialize the variable parts of a trampoline.
1042 FNADDR is an RTX for the address of the function's pure code.
1043 CXT is an RTX for the static chain value for the function.
1045 Move the function address to the trampoline template at offset 36.
1046 Move the static chain value to trampoline template at offset 40.
1047 Move the trampoline address to trampoline template at offset 44.
1048 Move r19 to trampoline template at offset 48. The latter two
1049 words create a plabel for the indirect call to the trampoline.
1051 A similar sequence is used for the 64-bit port but the plabel is
1052 at the beginning of the trampoline.
1054 Finally, the cache entries for the trampoline code are flushed.
1055 This is necessary to ensure that the trampoline instruction sequence
1056 is written to memory prior to any attempts at prefetching the code
1059 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1061 rtx start_addr = gen_reg_rtx (Pmode); \
1062 rtx end_addr = gen_reg_rtx (Pmode); \
1063 rtx line_length = gen_reg_rtx (Pmode); \
1066 if (!TARGET_64BIT) \
1068 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
1069 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1070 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
1071 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1073 /* Create a fat pointer for the trampoline. */ \
1074 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
1075 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
1076 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
1077 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1078 gen_rtx_REG (Pmode, 19)); \
1080 /* fdc and fic only use registers for the address to flush, \
1081 they do not accept integer displacements. We align the \
1082 start and end addresses to the beginning of their respective \
1083 cache lines to minimize the number of lines flushed. */ \
1084 tmp = force_reg (Pmode, (TRAMP)); \
1085 emit_insn (gen_andsi3 (start_addr, tmp, \
1086 GEN_INT (-MIN_CACHELINE_SIZE))); \
1087 tmp = force_reg (Pmode, \
1088 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1089 emit_insn (gen_andsi3 (end_addr, tmp, \
1090 GEN_INT (-MIN_CACHELINE_SIZE))); \
1091 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1092 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1093 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1094 gen_reg_rtx (Pmode), \
1095 gen_reg_rtx (Pmode))); \
1099 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1100 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1101 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1102 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1104 /* Create a fat pointer for the trampoline. */ \
1105 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1106 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1107 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
1108 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1109 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1110 gen_rtx_REG (Pmode, 27)); \
1112 /* fdc and fic only use registers for the address to flush, \
1113 they do not accept integer displacements. We align the \
1114 start and end addresses to the beginning of their respective \
1115 cache lines to minimize the number of lines flushed. */ \
1116 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1117 emit_insn (gen_anddi3 (start_addr, tmp, \
1118 GEN_INT (-MIN_CACHELINE_SIZE))); \
1119 tmp = force_reg (Pmode, \
1120 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1121 emit_insn (gen_anddi3 (end_addr, tmp, \
1122 GEN_INT (-MIN_CACHELINE_SIZE))); \
1123 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1124 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1125 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1126 gen_reg_rtx (Pmode), \
1127 gen_reg_rtx (Pmode))); \
1131 /* Perform any machine-specific adjustment in the address of the trampoline.
1132 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1133 Adjust the trampoline address to point to the plabel at offset 44. */
1135 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1136 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1138 /* Implement `va_start' for varargs and stdarg. */
1140 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1141 hppa_va_start (valist, nextarg)
1143 /* Addressing modes, and classification of registers for them.
1145 Using autoincrement addressing modes on PA8000 class machines is
1148 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1149 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1151 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1152 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1154 /* Macros to check register numbers against specific register classes. */
1156 /* These assume that REGNO is a hard or pseudo reg number.
1157 They give nonzero only if REGNO is a hard reg of the suitable class
1158 or a pseudo reg currently allocated to a suitable hard reg.
1159 Since they use reg_renumber, they are safe only once reg_renumber
1160 has been allocated, which happens in local-alloc.c. */
1162 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1163 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1164 #define REGNO_OK_FOR_BASE_P(REGNO) \
1165 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1166 #define REGNO_OK_FOR_FP_P(REGNO) \
1167 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1169 /* Now macros that check whether X is a register and also,
1170 strictly, whether it is in a specified class.
1172 These macros are specific to the HP-PA, and may be used only
1173 in code for printing assembler insns and in conditions for
1174 define_optimization. */
1176 /* 1 if X is an fp register. */
1178 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1180 /* Maximum number of registers that can appear in a valid memory address. */
1182 #define MAX_REGS_PER_ADDRESS 2
1184 /* Recognize any constant value that is a valid address except
1185 for symbolic addresses. We get better CSE by rejecting them
1186 here and allowing hppa_legitimize_address to break them up. We
1187 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1189 #define CONSTANT_ADDRESS_P(X) \
1190 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1191 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1192 || GET_CODE (X) == HIGH) \
1193 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1195 /* A C expression that is nonzero if we are using the new HP assembler. */
1197 #ifndef NEW_HP_ASSEMBLER
1198 #define NEW_HP_ASSEMBLER 0
1201 /* The macros below define the immediate range for CONST_INTS on
1202 the 64-bit port. Constants in this range can be loaded in three
1203 instructions using a ldil/ldo/depdi sequence. Constants outside
1204 this range are forced to the constant pool prior to reload. */
1206 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1207 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1208 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1209 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1211 /* A C expression that is nonzero if X is a legitimate constant for an
1214 We include all constant integers and constant doubles, but not
1215 floating-point, except for floating-point zero. We reject LABEL_REFs
1216 if we're not using gas or the new HP assembler.
1218 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1219 that need more than three instructions to load prior to reload. This
1220 limit is somewhat arbitrary. It takes three instructions to load a
1221 CONST_INT from memory but two are memory accesses. It may be better
1222 to increase the allowed range for CONST_INTS. We may also be able
1223 to handle CONST_DOUBLES. */
1225 #define LEGITIMATE_CONSTANT_P(X) \
1226 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1227 || (X) == CONST0_RTX (GET_MODE (X))) \
1228 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1229 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1230 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1231 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1232 || (reload_in_progress || reload_completed) \
1233 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1234 || cint_ok_for_move (INTVAL (X)))) \
1235 && !function_label_operand (X, VOIDmode))
1237 /* Subroutines for EXTRA_CONSTRAINT.
1239 Return 1 iff OP is a pseudo which did not get a hard register and
1240 we are running the reload pass. */
1241 #define IS_RELOADING_PSEUDO_P(OP) \
1242 ((reload_in_progress \
1243 && GET_CODE (OP) == REG \
1244 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1245 && reg_renumber [REGNO (OP)] < 0))
1247 /* Return 1 iff OP is a scaled or unscaled index address. */
1248 #define IS_INDEX_ADDR_P(OP) \
1249 (GET_CODE (OP) == PLUS \
1250 && GET_MODE (OP) == Pmode \
1251 && (GET_CODE (XEXP (OP, 0)) == MULT \
1252 || GET_CODE (XEXP (OP, 1)) == MULT \
1253 || (REG_P (XEXP (OP, 0)) \
1254 && REG_P (XEXP (OP, 1)))))
1256 /* Return 1 iff OP is a LO_SUM DLT address. */
1257 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1258 (GET_CODE (OP) == LO_SUM \
1259 && GET_MODE (OP) == Pmode \
1260 && REG_P (XEXP (OP, 0)) \
1261 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1262 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1264 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1266 `A' is a LO_SUM DLT memory operand.
1268 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1269 memory operand. Note that an unassigned pseudo register is such a
1270 memory operand. Needed because reload will generate these things
1271 and then not re-recognize the insn, causing constrain_operands to
1274 `R' is a scaled/unscaled indexed memory operand.
1276 `S' is the constant 31.
1278 `T' is for floating-point loads and stores.
1280 `U' is the constant 63. */
1282 #define EXTRA_CONSTRAINT(OP, C) \
1284 (IS_RELOADING_PSEUDO_P (OP) \
1285 || (GET_CODE (OP) == MEM \
1286 && (reload_in_progress \
1287 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1288 && !symbolic_memory_operand (OP, VOIDmode) \
1289 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1290 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1292 (GET_CODE (OP) == MEM \
1293 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1295 (GET_CODE (OP) == MEM \
1296 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1298 (GET_CODE (OP) == MEM \
1299 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1300 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1301 /* Floating-point loads and stores are used to load \
1302 integer values as well as floating-point values. \
1303 They don't have the same set of REG+D address modes \
1304 as integer loads and stores. PA 1.x supports only \
1305 short displacements. PA 2.0 supports long displacements \
1306 but the base register needs to be aligned. \
1308 The checks in GO_IF_LEGITIMATE_ADDRESS for SFmode and \
1309 DFmode test the validity of an address for use in a \
1310 floating point load or store. So, we use SFmode/DFmode \
1311 to see if the address is valid for a floating-point \
1312 load/store operation. */ \
1313 && memory_address_p ((GET_MODE_SIZE (GET_MODE (OP)) == 4 \
1318 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1320 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
1323 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1324 and check its validity for a certain class.
1325 We have two alternate definitions for each of them.
1326 The usual definition accepts all pseudo regs; the other rejects
1327 them unless they have been allocated suitable hard regs.
1328 The symbol REG_OK_STRICT causes the latter definition to be used.
1330 Most source files want to accept pseudo regs in the hope that
1331 they will get allocated to the class that the insn wants them to be in.
1332 Source files for reload pass need to be strict.
1333 After reload, it makes no difference, since pseudo regs have
1334 been eliminated by then. */
1336 #ifndef REG_OK_STRICT
1338 /* Nonzero if X is a hard reg that can be used as an index
1339 or if it is a pseudo reg. */
1340 #define REG_OK_FOR_INDEX_P(X) \
1341 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1342 /* Nonzero if X is a hard reg that can be used as a base reg
1343 or if it is a pseudo reg. */
1344 #define REG_OK_FOR_BASE_P(X) \
1345 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1349 /* Nonzero if X is a hard reg that can be used as an index. */
1350 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1351 /* Nonzero if X is a hard reg that can be used as a base reg. */
1352 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1356 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1357 valid memory address for an instruction. The MODE argument is the
1358 machine mode for the MEM expression that wants to use this address.
1360 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1361 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1362 available with floating point loads and stores, and integer loads.
1363 We get better code by allowing indexed addresses in the initial
1366 The acceptance of indexed addresses as legitimate implies that we
1367 must provide patterns for doing indexed integer stores, or the move
1368 expanders must force the address of an indexed store to a register.
1369 We have adopted the latter approach.
1371 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1372 the base register is a valid pointer for indexed instructions.
1373 On targets that have non-equivalent space registers, we have to
1374 know at the time of assembler output which register in a REG+REG
1375 pair is the base register. The REG_POINTER flag is sometimes lost
1376 in reload and the following passes, so it can't be relied on during
1377 code generation. Thus, we either have to canonicalize the order
1378 of the registers in REG+REG indexed addresses, or treat REG+REG
1379 addresses separately and provide patterns for both permutations.
1381 The latter approach requires several hundred additional lines of
1382 code in pa.md. The downside to canonicalizing is that a PLUS
1383 in the wrong order can't combine to form to make a scaled indexed
1384 memory operand. As we won't need to canonicalize the operands if
1385 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1387 We initially break out scaled indexed addresses in canonical order
1388 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1389 scaled indexed addresses during RTL generation. However, fold_rtx
1390 has its own opinion on how the operands of a PLUS should be ordered.
1391 If one of the operands is equivalent to a constant, it will make
1392 that operand the second operand. As the base register is likely to
1393 be equivalent to a SYMBOL_REF, we have made it the second operand.
1395 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1396 operands are in the order INDEX+BASE on targets with non-equivalent
1397 space registers, and in any order on targets with equivalent space
1398 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1400 We treat a SYMBOL_REF as legitimate if it is part of the current
1401 function's constant-pool, because such addresses can actually be
1402 output as REG+SMALLINT.
1404 Note we only allow 5 bit immediates for access to a constant address;
1405 doing so avoids losing for loading/storing a FP register at an address
1406 which will not fit in 5 bits. */
1408 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1409 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1411 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1412 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1414 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1415 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1417 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1418 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1420 #if HOST_BITS_PER_WIDE_INT > 32
1421 #define VAL_32_BITS_P(X) \
1422 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1423 < (unsigned HOST_WIDE_INT) 2 << 31)
1425 #define VAL_32_BITS_P(X) 1
1427 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1429 /* These are the modes that we allow for scaled indexing. */
1430 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1431 ((TARGET_64BIT && (MODE) == DImode) \
1432 || (MODE) == SImode \
1433 || (MODE) == HImode \
1434 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1436 /* These are the modes that we allow for unscaled indexing. */
1437 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1438 ((TARGET_64BIT && (MODE) == DImode) \
1439 || (MODE) == SImode \
1440 || (MODE) == HImode \
1441 || (MODE) == QImode \
1442 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1444 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1446 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1447 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1448 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1449 && REG_P (XEXP (X, 0)) \
1450 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1452 else if (GET_CODE (X) == PLUS) \
1454 rtx base = 0, index = 0; \
1455 if (REG_P (XEXP (X, 1)) \
1456 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1457 base = XEXP (X, 1), index = XEXP (X, 0); \
1458 else if (REG_P (XEXP (X, 0)) \
1459 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1460 base = XEXP (X, 0), index = XEXP (X, 1); \
1462 && GET_CODE (index) == CONST_INT \
1463 && ((INT_14_BITS (index) \
1464 && (((MODE) != DImode \
1465 && (MODE) != SFmode \
1466 && (MODE) != DFmode) \
1467 /* The base register for DImode loads and stores \
1468 with long displacements must be aligned because \
1469 the lower three bits in the displacement are \
1470 assumed to be zero. */ \
1471 || ((MODE) == DImode \
1473 || (INTVAL (index) % 8) == 0)) \
1474 /* Similarly, the base register for SFmode/DFmode \
1475 loads and stores with long displacements must \
1478 FIXME: the ELF32 linker clobbers the LSB of \
1479 the FP register number in PA 2.0 floating-point \
1480 insns with long displacements. This is because \
1481 R_PARISC_DPREL14WR and other relocations like \
1482 it are not supported. For now, we reject long \
1483 displacements on this target. */ \
1484 || (((MODE) == SFmode || (MODE) == DFmode) \
1485 && (TARGET_SOFT_FLOAT \
1488 && (INTVAL (index) \
1489 % GET_MODE_SIZE (MODE)) == 0))))) \
1490 || INT_5_BITS (index))) \
1492 if (!TARGET_DISABLE_INDEXING \
1493 /* Only accept the "canonical" INDEX+BASE operand order \
1494 on targets with non-equivalent space registers. */ \
1495 && (TARGET_NO_SPACE_REGS \
1496 ? (base && REG_P (index)) \
1497 : (base == XEXP (X, 1) && REG_P (index) \
1498 && REG_POINTER (base) && !REG_POINTER (index))) \
1499 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1500 && REG_OK_FOR_INDEX_P (index) \
1501 && borx_reg_operand (base, Pmode) \
1502 && borx_reg_operand (index, Pmode)) \
1504 if (!TARGET_DISABLE_INDEXING \
1506 && GET_CODE (index) == MULT \
1507 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1508 && REG_P (XEXP (index, 0)) \
1509 && GET_MODE (XEXP (index, 0)) == Pmode \
1510 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1511 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1512 && INTVAL (XEXP (index, 1)) \
1513 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1514 && borx_reg_operand (base, Pmode)) \
1517 else if (GET_CODE (X) == LO_SUM \
1518 && GET_CODE (XEXP (X, 0)) == REG \
1519 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1520 && CONSTANT_P (XEXP (X, 1)) \
1521 && (TARGET_SOFT_FLOAT \
1522 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1525 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1526 || ((MODE) != SFmode \
1527 && (MODE) != DFmode))) \
1529 else if (GET_CODE (X) == LO_SUM \
1530 && GET_CODE (XEXP (X, 0)) == SUBREG \
1531 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1532 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1533 && CONSTANT_P (XEXP (X, 1)) \
1534 && (TARGET_SOFT_FLOAT \
1535 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1538 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1539 || ((MODE) != SFmode \
1540 && (MODE) != DFmode))) \
1542 else if (GET_CODE (X) == LABEL_REF \
1543 || (GET_CODE (X) == CONST_INT \
1544 && INT_5_BITS (X))) \
1546 /* Needed for -fPIC */ \
1547 else if (GET_CODE (X) == LO_SUM \
1548 && GET_CODE (XEXP (X, 0)) == REG \
1549 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1550 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1551 && (TARGET_SOFT_FLOAT \
1552 || (TARGET_PA_20 && !TARGET_ELF32) \
1553 || ((MODE) != SFmode \
1554 && (MODE) != DFmode))) \
1558 /* Look for machine dependent ways to make the invalid address AD a
1561 For the PA, transform:
1563 memory(X + <large int>)
1567 if (<large int> & mask) >= 16
1568 Y = (<large int> & ~mask) + mask + 1 Round up.
1570 Y = (<large int> & ~mask) Round down.
1572 memory (Z + (<large int> - Y));
1574 This makes reload inheritance and reload_cse work better since Z
1577 There may be more opportunities to improve code with this hook. */
1578 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1580 long offset, newoffset, mask; \
1581 rtx new, temp = NULL_RTX; \
1583 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1584 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1586 if (optimize && GET_CODE (AD) == PLUS) \
1587 temp = simplify_binary_operation (PLUS, Pmode, \
1588 XEXP (AD, 0), XEXP (AD, 1)); \
1590 new = temp ? temp : AD; \
1593 && GET_CODE (new) == PLUS \
1594 && GET_CODE (XEXP (new, 0)) == REG \
1595 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1597 offset = INTVAL (XEXP ((new), 1)); \
1599 /* Choose rounding direction. Round up if we are >= halfway. */ \
1600 if ((offset & mask) >= ((mask + 1) / 2)) \
1601 newoffset = (offset & ~mask) + mask + 1; \
1603 newoffset = offset & ~mask; \
1605 /* Ensure that long displacements are aligned. */ \
1606 if (!VAL_5_BITS_P (newoffset) \
1607 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1608 newoffset &= ~(GET_MODE_SIZE (MODE) -1); \
1610 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1612 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1613 GEN_INT (newoffset)); \
1614 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1615 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1616 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1626 /* Try machine-dependent ways of modifying an illegitimate address
1627 to be legitimate. If we find one, return the new, valid address.
1628 This macro is used in only one place: `memory_address' in explow.c.
1630 OLDX is the address as it was before break_out_memory_refs was called.
1631 In some cases it is useful to look at this to decide what needs to be done.
1633 MODE and WIN are passed so that this macro can use
1634 GO_IF_LEGITIMATE_ADDRESS.
1636 It is always safe for this macro to do nothing. It exists to recognize
1637 opportunities to optimize the output. */
1639 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1640 { rtx orig_x = (X); \
1641 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1642 if ((X) != orig_x && memory_address_p (MODE, X)) \
1645 /* Go to LABEL if ADDR (a legitimate address expression)
1646 has an effect that depends on the machine mode it is used for. */
1648 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1649 if (GET_CODE (ADDR) == PRE_DEC \
1650 || GET_CODE (ADDR) == POST_DEC \
1651 || GET_CODE (ADDR) == PRE_INC \
1652 || GET_CODE (ADDR) == POST_INC) \
1655 #define TARGET_ASM_SELECT_SECTION pa_select_section
1657 /* Return a nonzero value if DECL has a section attribute. */
1658 #define IN_NAMED_SECTION_P(DECL) \
1659 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1660 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1662 /* The following extra sections and extra section functions are only used
1663 for SOM, but they must be provided unconditionally because pa.c's calls
1664 to the functions might not get optimized out when other object formats
1667 #define EXTRA_SECTIONS \
1668 in_som_readonly_data, \
1669 in_som_one_only_readonly_data, \
1670 in_som_one_only_data
1672 #define EXTRA_SECTION_FUNCTIONS \
1673 SOM_READONLY_DATA_SECTION_FUNCTION \
1674 SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1675 SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1676 FORGET_SECTION_FUNCTION
1678 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
1679 is not being generated. */
1680 #define SOM_READONLY_DATA_SECTION_FUNCTION \
1682 som_readonly_data_section (void) \
1686 if (in_section != in_som_readonly_data) \
1688 in_section = in_som_readonly_data; \
1689 fputs ("\t.SPACE $TEXT$\n\t.SUBSPA $LIT$\n", asm_out_file); \
1693 /* When secondary definitions are not supported, SOM makes readonly data one
1694 only by creating a new $LIT$ subspace in $TEXT$ with the comdat flag. */
1695 #define SOM_ONE_ONLY_READONLY_DATA_SECTION_FUNCTION \
1697 som_one_only_readonly_data_section (void) \
1701 in_section = in_som_one_only_readonly_data; \
1702 fputs ("\t.SPACE $TEXT$\n" \
1703 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=0x2c,SORT=16,COMDAT\n",\
1707 /* When secondary definitions are not supported, SOM makes data one only by
1708 creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
1709 #define SOM_ONE_ONLY_DATA_SECTION_FUNCTION \
1711 som_one_only_data_section (void) \
1715 in_section = in_som_one_only_data; \
1716 fputs ("\t.SPACE $PRIVATE$\n" \
1717 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31,SORT=24,COMDAT\n", \
1721 #define FORGET_SECTION_FUNCTION \
1723 forget_section (void) \
1725 in_section = no_section; \
1728 /* Define this macro if references to a symbol must be treated
1729 differently depending on something about the variable or
1730 function named by the symbol (such as what section it is in).
1732 The macro definition, if any, is executed immediately after the
1733 rtl for DECL or other node is created.
1734 The value of the rtl will be a `mem' whose address is a
1737 The usual thing for this macro to do is to a flag in the
1738 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1739 name string in the `symbol_ref' (if one bit is not enough
1742 On the HP-PA we use this to indicate if a symbol is in text or
1743 data space. Also, function labels need special treatment. */
1745 #define TEXT_SPACE_P(DECL)\
1746 (TREE_CODE (DECL) == FUNCTION_DECL \
1747 || (TREE_CODE (DECL) == VAR_DECL \
1748 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1749 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1751 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c'))
1753 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1755 /* Specify the machine mode that this machine uses for the index in the
1756 tablejump instruction. For small tables, an element consists of a
1757 ia-relative branch and its delay slot. When -mbig-switch is specified,
1758 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1759 for both 32 and 64-bit pic code. */
1760 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1762 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1763 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1765 /* Define this as 1 if `char' should by default be signed; else as 0. */
1766 #define DEFAULT_SIGNED_CHAR 1
1768 /* Max number of bytes we can move from memory to memory
1769 in one reasonably fast instruction. */
1772 /* Higher than the default as we prefer to use simple move insns
1773 (better scheduling and delay slot filling) and because our
1774 built-in block move is really a 2X unrolled loop.
1776 Believe it or not, this has to be big enough to allow for copying all
1777 arguments passed in registers to avoid infinite recursion during argument
1778 setup for a function call. Why? Consider how we copy the stack slots
1779 reserved for parameters when they may be trashed by a call. */
1780 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1782 /* Define if operations between registers always perform the operation
1783 on the full register even if a narrower mode is specified. */
1784 #define WORD_REGISTER_OPERATIONS
1786 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1787 will either zero-extend or sign-extend. The value of this macro should
1788 be the code that says which one of the two operations is implicitly
1789 done, UNKNOWN if none. */
1790 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1792 /* Nonzero if access to memory by bytes is slow and undesirable. */
1793 #define SLOW_BYTE_ACCESS 1
1795 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1796 is done just by pretending it is already truncated. */
1797 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1799 /* Specify the machine mode that pointers have.
1800 After generation of rtl, the compiler makes no further distinction
1801 between pointers and any other objects of this machine mode. */
1802 #define Pmode word_mode
1804 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1805 return the mode to be used for the comparison. For floating-point, CCFPmode
1806 should be used. CC_NOOVmode should be used when the first operand is a
1807 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1809 #define SELECT_CC_MODE(OP,X,Y) \
1810 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1812 /* A function address in a call instruction
1813 is a byte address (for indexing purposes)
1814 so give the MEM rtx a byte's mode. */
1815 #define FUNCTION_MODE SImode
1817 /* Define this if addresses of constant functions
1818 shouldn't be put through pseudo regs where they can be cse'd.
1819 Desirable on machines where ordinary constants are expensive
1820 but a CALL with constant address is cheap. */
1821 #define NO_FUNCTION_CSE
1823 /* Define this to be nonzero if shift instructions ignore all but the low-order
1825 #define SHIFT_COUNT_TRUNCATED 1
1827 /* Compute extra cost of moving data between one register class
1830 Make moves from SAR so expensive they should never happen. We used to
1831 have 0xffff here, but that generates overflow in rare cases.
1833 Copies involving a FP register and a non-FP register are relatively
1834 expensive because they must go through memory.
1836 Other copies are reasonably cheap. */
1837 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1838 (CLASS1 == SHIFT_REGS ? 0x100 \
1839 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1840 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1843 /* Adjust the cost of branches. */
1844 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1846 /* Handling the special cases is going to get too complicated for a macro,
1847 just call `pa_adjust_insn_length' to do the real work. */
1848 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1849 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1851 /* Millicode insns are actually function calls with some special
1852 constraints on arguments and register usage.
1854 Millicode calls always expect their arguments in the integer argument
1855 registers, and always return their result in %r29 (ret1). They
1856 are expected to clobber their arguments, %r1, %r29, and the return
1857 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1859 This macro tells reorg that the references to arguments and
1860 millicode calls do not appear to happen until after the millicode call.
1861 This allows reorg to put insns which set the argument registers into the
1862 delay slot of the millicode call -- thus they act more like traditional
1865 Note we cannot consider side effects of the insn to be delayed because
1866 the branch and link insn will clobber the return pointer. If we happened
1867 to use the return pointer in the delay slot of the call, then we lose.
1869 get_attr_type will try to recognize the given insn, so make sure to
1870 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1872 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1875 /* Control the assembler format that we output. */
1877 /* A C string constant describing how to begin a comment in the target
1878 assembler language. The compiler assumes that the comment will end at
1879 the end of the line. */
1881 #define ASM_COMMENT_START ";"
1883 /* Output to assembler file text saying following lines
1884 may contain character constants, extra white space, comments, etc. */
1886 #define ASM_APP_ON ""
1888 /* Output to assembler file text saying following lines
1889 no longer contain unusual constructs. */
1891 #define ASM_APP_OFF ""
1893 /* This is how to output the definition of a user-level label named NAME,
1894 such as the label on a static function or variable NAME. */
1896 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1897 do { assemble_name (FILE, NAME); \
1898 fputc ('\n', FILE); } while (0)
1900 /* This is how to output a reference to a user-level label named NAME.
1901 `assemble_name' uses this. */
1903 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1905 const char *xname = (NAME); \
1906 if (FUNCTION_NAME_P (NAME)) \
1908 if (xname[0] == '*') \
1911 fputs (user_label_prefix, FILE); \
1912 fputs (xname, FILE); \
1915 /* This is how to store into the string LABEL
1916 the symbol_ref name of an internal numbered label where
1917 PREFIX is the class of label and NUM is the number within the class.
1918 This is suitable for output with `assemble_name'. */
1920 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1921 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1923 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1925 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1926 output_ascii ((FILE), (P), (SIZE))
1928 /* Jump tables are always placed in the text section. Technically, it
1929 is possible to put them in the readonly data section when -mbig-switch
1930 is specified. This has the benefit of getting the table out of .text
1931 and reducing branch lengths as a result. The downside is that an
1932 additional insn (addil) is needed to access the table when generating
1933 PIC code. The address difference table also has to use 32-bit
1934 pc-relative relocations. Currently, GAS does not support these
1935 relocations, although it is easily modified to do this operation.
1936 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1937 when using ELF GAS. A simple difference can be used when using
1938 SOM GAS or the HP assembler. The final downside is GDB complains
1939 about the nesting of the label for the table when debugging. */
1941 #define JUMP_TABLES_IN_TEXT_SECTION 1
1943 /* This is how to output an element of a case-vector that is absolute. */
1945 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1946 if (TARGET_BIG_SWITCH) \
1947 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1949 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1951 /* This is how to output an element of a case-vector that is relative.
1952 Since we always place jump tables in the text section, the difference
1953 is absolute and requires no relocation. */
1955 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1956 if (TARGET_BIG_SWITCH) \
1957 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1959 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1961 /* This is how to output an assembler line that says to advance the
1962 location counter to a multiple of 2**LOG bytes. */
1964 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1965 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1967 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1968 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1969 (unsigned HOST_WIDE_INT)(SIZE))
1971 /* This says how to output an assembler line to define an uninitialized
1972 global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1973 This macro exists to properly support languages like C++ which do not
1974 have common data. */
1976 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1977 pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1979 /* This says how to output an assembler line to define a global common symbol
1980 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1982 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1983 pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1985 /* This says how to output an assembler line to define a local common symbol
1986 with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1987 controls how the assembler definitions of uninitialized static variables
1990 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1991 pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1994 #define ASM_PN_FORMAT "%s___%lu"
1996 /* All HP assemblers use "!" to separate logical lines. */
1997 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1999 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
2000 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
2002 /* Print operand X (an rtx) in assembler syntax to file FILE.
2003 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
2004 For `%' followed by punctuation, CODE is the punctuation and X is null.
2006 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
2007 and an immediate zero should be represented as `r0'.
2009 Several % codes are defined:
2011 C compare conditions
2012 N extract conditions
2013 M modifier to handle preincrement addressing for memory refs.
2014 F modifier to handle preincrement addressing for fp memory refs */
2016 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2019 /* Print a memory address as an operand to reference that memory location. */
2021 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
2022 { register rtx addr = ADDR; \
2023 register rtx base; \
2025 switch (GET_CODE (addr)) \
2028 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
2031 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
2032 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
2033 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
2034 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
2037 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
2040 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
2041 fputs ("R'", FILE); \
2042 else if (flag_pic == 0) \
2043 fputs ("RR'", FILE); \
2045 fputs ("RT'", FILE); \
2046 output_global_address (FILE, XEXP (addr, 1), 0); \
2047 fputs ("(", FILE); \
2048 output_operand (XEXP (addr, 0), 0); \
2049 fputs (")", FILE); \
2052 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
2055 output_addr_const (FILE, addr); \
2059 /* Find the return address associated with the frame given by
2061 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
2062 (return_addr_rtx (COUNT, FRAMEADDR))
2064 /* Used to mask out junk bits from the return address, such as
2065 processor state, interrupt status, condition codes and the like. */
2066 #define MASK_RETURN_ADDR \
2067 /* The privilege level is in the two low order bits, mask em out \
2068 of the return address. */ \
2071 /* The number of Pmode words for the setjmp buffer. */
2072 #define JMP_BUF_SIZE 50
2074 #define PREDICATE_CODES \
2075 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2076 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
2077 CONST_DOUBLE, CONST, HIGH}}, \
2078 {"indexed_memory_operand", {SUBREG, MEM}}, \
2079 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2080 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2081 {"reg_before_reload_operand", {REG, MEM}}, \
2082 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
2084 {"move_dest_operand", {SUBREG, REG, MEM}}, \
2085 {"move_src_operand", {SUBREG, REG, CONST_INT, MEM}}, \
2086 {"prefetch_operand", {MEM}}, \
2087 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
2088 {"pic_label_operand", {LABEL_REF, CONST}}, \
2089 {"fp_reg_operand", {REG}}, \
2090 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2091 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2092 {"pre_cint_operand", {CONST_INT}}, \
2093 {"post_cint_operand", {CONST_INT}}, \
2094 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2095 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
2096 {"int5_operand", {CONST_INT}}, \
2097 {"uint5_operand", {CONST_INT}}, \
2098 {"int11_operand", {CONST_INT}}, \
2099 {"uint32_operand", {CONST_INT, \
2100 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
2101 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
2102 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2103 {"ior_operand", {CONST_INT}}, \
2104 {"lhs_lshift_cint_operand", {CONST_INT}}, \
2105 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
2106 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
2107 {"pc_or_label_operand", {PC, LABEL_REF}}, \
2108 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
2109 {"shadd_operand", {CONST_INT}}, \
2110 {"div_operand", {REG, CONST_INT}}, \
2111 {"ireg_operand", {REG}}, \
2112 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
2114 {"movb_comparison_operator", {EQ, NE, LT, GE}},
2116 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
2117 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
2118 "__canonicalize_funcptr_for_compare"
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