1 /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000,
3 2001, 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support
5 and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for
6 Software Science at the University of Utah.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GCC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 enum cmp_type /* comparison type */
27 CMP_SI, /* compare integers */
28 CMP_SF, /* compare single precision floats */
29 CMP_DF, /* compare double precision floats */
30 CMP_MAX /* max comparison type */
33 /* For long call handling. */
34 extern unsigned long total_code_bytes;
36 /* Which processor to schedule for. */
48 /* For -mschedule= option. */
49 extern const char *pa_cpu_string;
50 extern enum processor_type pa_cpu;
52 #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
54 /* Which architecture to generate code for. */
56 enum architecture_type
65 /* For -march= option. */
66 extern const char *pa_arch_string;
67 extern enum architecture_type pa_arch;
69 /* Print subsidiary information on the compiler version in use. */
71 #define TARGET_VERSION fputs (" (hppa)", stderr);
73 /* Run-time compilation parameters selecting different hardware subsets. */
75 extern int target_flags;
77 /* compile code for HP-PA 1.1 ("Snake"). */
81 /* Disable all FP registers (they all become fixed). This may be necessary
82 for compiling kernels which perform lazy context switching of FP regs.
83 Note if you use this option and try to perform floating point operations
84 the compiler will abort! */
86 #define MASK_DISABLE_FPREGS 2
87 #define TARGET_DISABLE_FPREGS (target_flags & MASK_DISABLE_FPREGS)
89 /* Generate code which assumes that all space register are equivalent.
90 Triggers aggressive unscaled index addressing and faster
91 builtin_return_address. */
92 #define MASK_NO_SPACE_REGS 4
93 #define TARGET_NO_SPACE_REGS (target_flags & MASK_NO_SPACE_REGS)
95 /* Allow unconditional jumps in the delay slots of call instructions. */
96 #define MASK_JUMP_IN_DELAY 8
97 #define TARGET_JUMP_IN_DELAY (target_flags & MASK_JUMP_IN_DELAY)
99 /* Disable indexed addressing modes. */
100 #define MASK_DISABLE_INDEXING 32
101 #define TARGET_DISABLE_INDEXING (target_flags & MASK_DISABLE_INDEXING)
103 /* Emit code which follows the new portable runtime calling conventions
104 HP wants everyone to use for ELF objects. If at all possible you want
105 to avoid this since it's a performance loss for non-prototyped code.
107 Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline
108 long-call stubs which is quite expensive. */
109 #define MASK_PORTABLE_RUNTIME 64
110 #define TARGET_PORTABLE_RUNTIME (target_flags & MASK_PORTABLE_RUNTIME)
112 /* Emit directives only understood by GAS. This allows parameter
113 relocations to work for static functions. There is no way
114 to make them work the HP assembler at this time. */
116 #define TARGET_GAS (target_flags & MASK_GAS)
118 /* Emit code for processors which do not have an FPU. */
119 #define MASK_SOFT_FLOAT 256
120 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
122 /* Use 3-insn load/store sequences for access to large data segments
123 in shared libraries on hpux10. */
124 #define MASK_LONG_LOAD_STORE 512
125 #define TARGET_LONG_LOAD_STORE (target_flags & MASK_LONG_LOAD_STORE)
127 /* Use a faster sequence for indirect calls. This assumes that calls
128 through function pointers will never cross a space boundary, and
129 that the executable is not dynamically linked. Such assumptions
130 are generally safe for building kernels and statically linked
131 executables. Code compiled with this option will fail miserably if
132 the executable is dynamically linked or uses nested functions! */
133 #define MASK_FAST_INDIRECT_CALLS 1024
134 #define TARGET_FAST_INDIRECT_CALLS (target_flags & MASK_FAST_INDIRECT_CALLS)
136 /* Generate code with big switch statements to avoid out of range branches
137 occurring within the switch table. */
138 #define MASK_BIG_SWITCH 2048
139 #define TARGET_BIG_SWITCH (target_flags & MASK_BIG_SWITCH)
141 /* Generate code for the HPPA 2.0 architecture. TARGET_PA_11 should also be
142 true when this is true. */
143 #define MASK_PA_20 4096
145 /* Generate cpp defines for server I/O. */
146 #define MASK_SIO 8192
147 #define TARGET_SIO (target_flags & MASK_SIO)
149 /* Assume GNU linker by default. */
150 #define MASK_GNU_LD 16384
151 #ifndef TARGET_GNU_LD
152 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD)
155 /* Force generation of long calls. */
156 #define MASK_LONG_CALLS 32768
157 #ifndef TARGET_LONG_CALLS
158 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
162 #define TARGET_PA_10 (target_flags & (MASK_PA_11 | MASK_PA_20) == 0)
166 #define TARGET_PA_11 (target_flags & MASK_PA_11)
170 #define TARGET_PA_20 (target_flags & MASK_PA_20)
173 /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
175 #define TARGET_64BIT 0
178 /* Generate code for ELF32 ABI. */
180 #define TARGET_ELF32 0
183 /* Generate code for SOM 32bit ABI. */
188 /* The following three defines are potential target switches. The current
189 defines are optimal given the current capabilities of GAS and GNU ld. */
191 /* Define to a C expression evaluating to true to use long absolute calls.
192 Currently, only the HP assembler and SOM linker support long absolute
193 calls. They are used only in non-pic code. */
194 #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
196 /* Define to a C expression evaluating to true to use long pic symbol
197 difference calls. This is a call variant similar to the long pic
198 pc-relative call. Long pic symbol difference calls are only used with
199 the HP SOM linker. Currently, only the HP assembler supports these
200 calls. GAS doesn't allow an arbitrary difference of two symbols. */
201 #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS)
203 /* Define to a C expression evaluating to true to use long pic
204 pc-relative calls. Long pic pc-relative calls are only used with
205 GAS. Currently, they are usable for calls within a module but
206 not for external calls. */
207 #define TARGET_LONG_PIC_PCREL_CALL 0
209 /* Define to a C expression evaluating to true to use SOM secondary
210 definition symbols for weak support. Linker support for secondary
211 definition symbols is buggy prior to HP-UX 11.X. */
212 #define TARGET_SOM_SDEF 0
214 /* Define to a C expression evaluating to true to save the entry value
215 of SP in the current frame marker. This is normally unnecessary.
216 However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
217 HP compilers don't use this flag but it is supported by the assembler.
218 We set this flag to indicate that register %r3 has been saved at the
219 start of the frame. Thus, when the HP unwind library is used, we
220 need to generate additional code to save SP into the frame marker. */
221 #define TARGET_HPUX_UNWIND_LIBRARY 0
223 /* Macro to define tables used to set the flags. This is a
224 list in braces of target switches with each switch being
225 { "NAME", VALUE, "HELP_STRING" }. VALUE is the bits to set,
226 or minus the bits to clear. An empty string NAME is used to
227 identify the default VALUE. Do not mark empty strings for
230 #define TARGET_SWITCHES \
231 {{ "snake", MASK_PA_11, \
232 N_("Generate PA1.1 code") }, \
233 { "nosnake", -(MASK_PA_11 | MASK_PA_20), \
234 N_("Generate PA1.0 code") }, \
235 { "pa-risc-1-0", -(MASK_PA_11 | MASK_PA_20), \
236 N_("Generate PA1.0 code") }, \
237 { "pa-risc-1-1", MASK_PA_11, \
238 N_("Generate PA1.1 code") }, \
239 { "pa-risc-2-0", MASK_PA_20, \
240 N_("Generate PA2.0 code (requires binutils 2.10 or later)") }, \
241 { "disable-fpregs", MASK_DISABLE_FPREGS, \
242 N_("Disable FP regs") }, \
243 { "no-disable-fpregs", -MASK_DISABLE_FPREGS, \
244 N_("Do not disable FP regs") }, \
245 { "no-space-regs", MASK_NO_SPACE_REGS, \
246 N_("Disable space regs") }, \
247 { "space-regs", -MASK_NO_SPACE_REGS, \
248 N_("Do not disable space regs") }, \
249 { "jump-in-delay", MASK_JUMP_IN_DELAY, \
250 N_("Put jumps in call delay slots") }, \
251 { "no-jump-in-delay", -MASK_JUMP_IN_DELAY, \
252 N_("Do not put jumps in call delay slots") }, \
253 { "disable-indexing", MASK_DISABLE_INDEXING, \
254 N_("Disable indexed addressing") }, \
255 { "no-disable-indexing", -MASK_DISABLE_INDEXING, \
256 N_("Do not disable indexed addressing") }, \
257 { "portable-runtime", MASK_PORTABLE_RUNTIME, \
258 N_("Use portable calling conventions") }, \
259 { "no-portable-runtime", -MASK_PORTABLE_RUNTIME, \
260 N_("Do not use portable calling conventions") }, \
262 N_("Assume code will be assembled by GAS") }, \
263 { "no-gas", -MASK_GAS, \
264 N_("Do not assume code will be assembled by GAS") }, \
265 { "soft-float", MASK_SOFT_FLOAT, \
266 N_("Use software floating point") }, \
267 { "no-soft-float", -MASK_SOFT_FLOAT, \
268 N_("Do not use software floating point") }, \
269 { "long-load-store", MASK_LONG_LOAD_STORE, \
270 N_("Emit long load/store sequences") }, \
271 { "no-long-load-store", -MASK_LONG_LOAD_STORE, \
272 N_("Do not emit long load/store sequences") }, \
273 { "fast-indirect-calls", MASK_FAST_INDIRECT_CALLS, \
274 N_("Generate fast indirect calls") }, \
275 { "no-fast-indirect-calls", -MASK_FAST_INDIRECT_CALLS, \
276 N_("Do not generate fast indirect calls") }, \
277 { "big-switch", MASK_BIG_SWITCH, \
278 N_("Generate code for huge switch statements") }, \
279 { "no-big-switch", -MASK_BIG_SWITCH, \
280 N_("Do not generate code for huge switch statements") }, \
281 { "long-calls", MASK_LONG_CALLS, \
282 N_("Always generate long calls") }, \
283 { "no-long-calls", -MASK_LONG_CALLS, \
284 N_("Generate long calls only when needed") }, \
286 N_("Enable linker optimizations") }, \
288 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \
291 #ifndef TARGET_DEFAULT
292 #define TARGET_DEFAULT (MASK_GAS | MASK_JUMP_IN_DELAY)
295 #ifndef TARGET_CPU_DEFAULT
296 #define TARGET_CPU_DEFAULT 0
299 #ifndef SUBTARGET_SWITCHES
300 #define SUBTARGET_SWITCHES
303 #ifndef TARGET_SCHED_DEFAULT
304 #define TARGET_SCHED_DEFAULT "8000"
307 #define TARGET_OPTIONS \
309 { "schedule=", &pa_cpu_string, \
310 N_("Specify CPU for scheduling purposes"), 0}, \
311 { "arch=", &pa_arch_string, \
312 N_("Specify architecture for code generation. Values are 1.0, 1.1, and 2.0. 2.0 requires gas snapshot 19990413 or later."), 0}\
315 /* Support for a compile-time default CPU, et cetera. The rules are:
316 --with-schedule is ignored if -mschedule is specified.
317 --with-arch is ignored if -march is specified. */
318 #define OPTION_DEFAULT_SPECS \
319 {"arch", "%{!march=*:-march=%(VALUE)}" }, \
320 {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
322 /* Specify the dialect of assembler to use. New mnemonics is dialect one
323 and the old mnemonics are dialect zero. */
324 #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
326 #define OVERRIDE_OPTIONS override_options ()
328 /* Override some settings from dbxelf.h. */
330 /* We do not have to be compatible with dbx, so we enable gdb extensions
332 #define DEFAULT_GDB_EXTENSIONS 1
334 /* This used to be zero (no max length), but big enums and such can
335 cause huge strings which killed gas.
337 We also have to avoid lossage in dbxout.c -- it does not compute the
338 string size accurately, so we are real conservative here. */
339 #undef DBX_CONTIN_LENGTH
340 #define DBX_CONTIN_LENGTH 3000
342 /* Only labels should ever begin in column zero. */
343 #define ASM_STABS_OP "\t.stabs\t"
344 #define ASM_STABN_OP "\t.stabn\t"
346 /* GDB always assumes the current function's frame begins at the value
347 of the stack pointer upon entry to the current function. Accessing
348 local variables and parameters passed on the stack is done using the
349 base of the frame + an offset provided by GCC.
351 For functions which have frame pointers this method works fine;
352 the (frame pointer) == (stack pointer at function entry) and GCC provides
353 an offset relative to the frame pointer.
355 This loses for functions without a frame pointer; GCC provides an offset
356 which is relative to the stack pointer after adjusting for the function's
357 frame size. GDB would prefer the offset to be relative to the value of
358 the stack pointer at the function's entry. Yuk! */
359 #define DEBUGGER_AUTO_OFFSET(X) \
360 ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
361 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
363 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
364 ((GET_CODE (X) == PLUS ? OFFSET : 0) \
365 + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0)))
367 #define TARGET_CPU_CPP_BUILTINS() \
369 builtin_assert("cpu=hppa"); \
370 builtin_assert("machine=hppa"); \
371 builtin_define("__hppa"); \
372 builtin_define("__hppa__"); \
374 builtin_define("_PA_RISC2_0"); \
375 else if (TARGET_PA_11) \
376 builtin_define("_PA_RISC1_1"); \
378 builtin_define("_PA_RISC1_0"); \
381 /* An old set of OS defines for various BSD-like systems. */
382 #define TARGET_OS_CPP_BUILTINS() \
385 builtin_define_std ("REVARGV"); \
386 builtin_define_std ("hp800"); \
387 builtin_define_std ("hp9000"); \
388 builtin_define_std ("hp9k8"); \
389 if (!c_dialect_cxx () && !flag_iso) \
390 builtin_define ("hppa"); \
391 builtin_define_std ("spectrum"); \
392 builtin_define_std ("unix"); \
393 builtin_assert ("system=bsd"); \
394 builtin_assert ("system=unix"); \
398 #define CC1_SPEC "%{pg:} %{p:}"
400 #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
402 /* We don't want -lg. */
404 #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
407 /* This macro defines command-line switches that modify the default
410 The definition is be an initializer for an array of structures. Each
411 array element has have three elements: the switch name, one of the
412 enumeration codes ADD or DELETE to indicate whether the string should be
413 inserted or deleted, and the string to be inserted or deleted. */
414 #define MODIFY_TARGET_NAME {{"-32", DELETE, "64"}, {"-64", ADD, "64"}}
416 /* Make gcc agree with <machine/ansi.h> */
418 #define SIZE_TYPE "unsigned int"
419 #define PTRDIFF_TYPE "int"
420 #define WCHAR_TYPE "unsigned int"
421 #define WCHAR_TYPE_SIZE 32
423 /* Show we can debug even without a frame pointer. */
424 #define CAN_DEBUG_WITHOUT_FP
426 /* target machine storage layout */
428 /* Define this macro if it is advisable to hold scalars in registers
429 in a wider mode than that declared by the program. In such cases,
430 the value is constrained to be within the bounds of the declared
431 type, but kept valid in the wider mode. The signedness of the
432 extension may differ from that of the type. */
434 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
435 if (GET_MODE_CLASS (MODE) == MODE_INT \
436 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
439 /* Define this if most significant bit is lowest numbered
440 in instructions that operate on numbered bit-fields. */
441 #define BITS_BIG_ENDIAN 1
443 /* Define this if most significant byte of a word is the lowest numbered. */
444 /* That is true on the HP-PA. */
445 #define BYTES_BIG_ENDIAN 1
447 /* Define this if most significant word of a multiword number is lowest
449 #define WORDS_BIG_ENDIAN 1
451 #define MAX_BITS_PER_WORD 64
452 #define MAX_LONG_TYPE_SIZE 32
454 /* Width of a word, in units (bytes). */
455 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
456 #define MIN_UNITS_PER_WORD 4
458 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
459 #define PARM_BOUNDARY BITS_PER_WORD
461 /* Largest alignment required for any stack parameter, in bits.
462 Don't define this if it is equal to PARM_BOUNDARY */
463 #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
465 /* Boundary (in *bits*) on which stack pointer is always aligned;
466 certain optimizations in combine depend on this.
468 The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
469 the stack on the 32 and 64-bit ports, respectively. However, we
470 are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
471 in main. Thus, we treat the former as the preferred alignment. */
472 #define STACK_BOUNDARY BIGGEST_ALIGNMENT
473 #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
475 /* Allocation boundary (in *bits*) for the code of a function. */
476 #define FUNCTION_BOUNDARY BITS_PER_WORD
478 /* Alignment of field after `int : 0' in a structure. */
479 #define EMPTY_FIELD_BOUNDARY 32
481 /* Every structure's size must be a multiple of this. */
482 #define STRUCTURE_SIZE_BOUNDARY 8
484 /* A bit-field declared as `int' forces `int' alignment for the struct. */
485 #define PCC_BITFIELD_TYPE_MATTERS 1
487 /* No data type wants to be aligned rounder than this. */
488 #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
490 /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
491 #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \
492 ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN))
494 /* Make arrays of chars word-aligned for the same reasons. */
495 #define DATA_ALIGNMENT(TYPE, ALIGN) \
496 (TREE_CODE (TYPE) == ARRAY_TYPE \
497 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
498 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
500 /* Set this nonzero if move instructions will actually fail to work
501 when given unaligned data. */
502 #define STRICT_ALIGNMENT 1
504 /* Generate calls to memcpy, memcmp and memset. */
505 #define TARGET_MEM_FUNCTIONS
507 /* Value is 1 if it is a good idea to tie two pseudo registers
508 when one has mode MODE1 and one has mode MODE2.
509 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
510 for any hard reg, then this must be 0 for correct output. */
511 #define MODES_TIEABLE_P(MODE1, MODE2) \
512 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
514 /* Specify the registers used for certain standard purposes.
515 The values of these macros are register numbers. */
517 /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
518 /* #define PC_REGNUM */
520 /* Register to use for pushing function arguments. */
521 #define STACK_POINTER_REGNUM 30
523 /* Base register for access to local variables of the function. */
524 #define FRAME_POINTER_REGNUM 3
526 /* Value should be nonzero if functions must have frame pointers. */
527 #define FRAME_POINTER_REQUIRED \
528 (current_function_calls_alloca)
530 /* C statement to store the difference between the frame pointer
531 and the stack pointer values immediately after the function prologue.
533 Note, we always pretend that this is a leaf function because if
534 it's not, there's no point in trying to eliminate the
535 frame pointer. If it is a leaf function, we guessed right! */
536 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
537 do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0)
539 /* Base register for access to arguments of the function. */
540 #define ARG_POINTER_REGNUM 3
542 /* Register in which static-chain is passed to a function. */
543 #define STATIC_CHAIN_REGNUM 29
545 /* Register which holds offset table for position-independent
548 #define PIC_OFFSET_TABLE_REGNUM (TARGET_64BIT ? 27 : 19)
549 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
551 /* Function to return the rtx used to save the pic offset table register
552 across function calls. */
553 extern struct rtx_def *hppa_pic_save_rtx (void);
555 #define DEFAULT_PCC_STRUCT_RETURN 0
557 /* SOM ABI says that objects larger than 64 bits are returned in memory.
558 PA64 ABI says that objects larger than 128 bits are returned in memory.
559 Note, int_size_in_bytes can return -1 if the size of the object is
560 variable or larger than the maximum value that can be expressed as
561 a HOST_WIDE_INT. It can also return zero for an empty type. The
562 simplest way to handle variable and empty types is to pass them in
563 memory. This avoids problems in defining the boundaries of argument
564 slots, allocating registers, etc. */
565 #define RETURN_IN_MEMORY(TYPE) \
566 (int_size_in_bytes (TYPE) > (TARGET_64BIT ? 16 : 8) \
567 || int_size_in_bytes (TYPE) <= 0)
569 /* Register in which address to store a structure value
570 is passed to a function. */
571 #define STRUCT_VALUE_REGNUM 28
573 /* Describe how we implement __builtin_eh_return. */
574 #define EH_RETURN_DATA_REGNO(N) \
575 ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
576 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
577 #define EH_RETURN_HANDLER_RTX \
578 gen_rtx_MEM (word_mode, \
579 gen_rtx_PLUS (word_mode, frame_pointer_rtx, \
580 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20)))
583 /* Offset from the argument pointer register value to the top of
584 stack. This is different from FIRST_PARM_OFFSET because of the
586 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0
588 /* The letters I, J, K, L and M in a register constraint string
589 can be used to stand for particular ranges of immediate operands.
590 This macro defines what the ranges are.
591 C is the letter, and VALUE is a constant value.
592 Return 1 if VALUE is in the range specified by C.
594 `I' is used for the 11 bit constants.
595 `J' is used for the 14 bit constants.
596 `K' is used for values that can be moved with a zdepi insn.
597 `L' is used for the 5 bit constants.
599 `N' is used for values with the least significant 11 bits equal to zero
600 and when sign extended from 32 to 64 bits the
601 value does not change.
602 `O' is used for numbers n such that n+1 is a power of 2.
605 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
606 ((C) == 'I' ? VAL_11_BITS_P (VALUE) \
607 : (C) == 'J' ? VAL_14_BITS_P (VALUE) \
608 : (C) == 'K' ? zdepi_cint_p (VALUE) \
609 : (C) == 'L' ? VAL_5_BITS_P (VALUE) \
610 : (C) == 'M' ? (VALUE) == 0 \
611 : (C) == 'N' ? (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) == 0 \
612 || (((VALUE) & (((HOST_WIDE_INT) -1 << 31) | 0x7ff)) \
613 == (HOST_WIDE_INT) -1 << 31)) \
614 : (C) == 'O' ? (((VALUE) & ((VALUE) + 1)) == 0) \
615 : (C) == 'P' ? and_mask_p (VALUE) \
618 /* Similar, but for floating or large integer constants, and defining letters
619 G and H. Here VALUE is the CONST_DOUBLE rtx itself.
621 For PA, `G' is the floating-point constant zero. `H' is undefined. */
623 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
624 ((C) == 'G' ? (GET_MODE_CLASS (GET_MODE (VALUE)) == MODE_FLOAT \
625 && (VALUE) == CONST0_RTX (GET_MODE (VALUE))) \
628 /* The class value for index registers, and the one for base regs. */
629 #define INDEX_REG_CLASS GENERAL_REGS
630 #define BASE_REG_CLASS GENERAL_REGS
632 #define FP_REG_CLASS_P(CLASS) \
633 ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
635 /* True if register is floating-point. */
636 #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
638 /* Given an rtx X being reloaded into a reg required to be
639 in class CLASS, return the class of reg to actually use.
640 In general this is just CLASS; but on some machines
641 in some cases it is preferable to use a more restrictive class. */
642 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
644 /* Return the register class of a scratch register needed to copy
645 IN into a register in CLASS in MODE, or a register in CLASS in MODE
646 to IN. If it can be done directly NO_REGS is returned.
648 Avoid doing any work for the common case calls. */
649 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
650 ((CLASS == BASE_REG_CLASS && GET_CODE (IN) == REG \
651 && REGNO (IN) < FIRST_PSEUDO_REGISTER) \
652 ? NO_REGS : secondary_reload_class (CLASS, MODE, IN))
654 #define MAYBE_FP_REG_CLASS_P(CLASS) \
655 reg_classes_intersect_p ((CLASS), FP_REGS)
657 /* On the PA it is not possible to directly move data between
658 GENERAL_REGS and FP_REGS. */
659 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
660 (MAYBE_FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2) \
661 || MAYBE_FP_REG_CLASS_P (CLASS2) != FP_REG_CLASS_P (CLASS1))
663 /* Return the stack location to use for secondary memory needed reloads. */
664 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \
665 gen_rtx_MEM (MODE, gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (-16)))
668 /* Stack layout; function entry, exit and calling. */
670 /* Define this if pushing a word on the stack
671 makes the stack pointer a smaller address. */
672 /* #define STACK_GROWS_DOWNWARD */
674 /* Believe it or not. */
675 #define ARGS_GROW_DOWNWARD
677 /* Define this if the nominal address of the stack frame
678 is at the high-address end of the local variables;
679 that is, each additional local variable allocated
680 goes at a more negative offset in the frame. */
681 /* #define FRAME_GROWS_DOWNWARD */
683 /* Offset within stack frame to start allocating local variables at.
684 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
685 first local allocated. Otherwise, it is the offset to the BEGINNING
686 of the first local allocated.
688 On the 32-bit ports, we reserve one slot for the previous frame
689 pointer and one fill slot. The fill slot is for compatibility
690 with HP compiled programs. On the 64-bit ports, we reserve one
691 slot for the previous frame pointer. */
692 #define STARTING_FRAME_OFFSET 8
694 /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
695 of the stack. The default is to align it to STACK_BOUNDARY. */
696 #define STACK_ALIGNMENT_NEEDED 0
698 /* If we generate an insn to push BYTES bytes,
699 this says how many the stack pointer really advances by.
700 On the HP-PA, don't define this because there are no push insns. */
701 /* #define PUSH_ROUNDING(BYTES) */
703 /* Offset of first parameter from the argument pointer register value.
704 This value will be negated because the arguments grow down.
705 Also note that on STACK_GROWS_UPWARD machines (such as this one)
706 this is the distance from the frame pointer to the end of the first
707 argument, not it's beginning. To get the real offset of the first
708 argument, the size of the argument must be added. */
710 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
712 /* When a parameter is passed in a register, stack space is still
714 #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
716 /* Define this if the above stack space is to be considered part of the
717 space allocated by the caller. */
718 #define OUTGOING_REG_PARM_STACK_SPACE
720 /* Keep the stack pointer constant throughout the function.
721 This is both an optimization and a necessity: longjmp
722 doesn't behave itself when the stack pointer moves within
724 #define ACCUMULATE_OUTGOING_ARGS 1
726 /* The weird HPPA calling conventions require a minimum of 48 bytes on
727 the stack: 16 bytes for register saves, and 32 bytes for magic.
728 This is the difference between the logical top of stack and the
731 On the 64-bit port, the HP C compiler allocates a 48-byte frame
732 marker, although the runtime documentation only describes a 16
733 byte marker. For compatibility, we allocate 48 bytes. */
734 #define STACK_POINTER_OFFSET \
735 (TARGET_64BIT ? -(current_function_outgoing_args_size + 48): -32)
737 #define STACK_DYNAMIC_OFFSET(FNDECL) \
739 ? (STACK_POINTER_OFFSET) \
740 : ((STACK_POINTER_OFFSET) - current_function_outgoing_args_size))
742 /* Value is 1 if returning from a function call automatically
743 pops the arguments described by the number-of-args field in the call.
744 FUNDECL is the declaration node of the function (as a tree),
745 FUNTYPE is the data type of the function (as a tree),
746 or for a library call it is an identifier node for the subroutine name. */
748 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
750 /* Define how to find the value returned by a function.
751 VALTYPE is the data type of the value (as a tree).
752 If the precise function being called is known, FUNC is its FUNCTION_DECL;
753 otherwise, FUNC is 0. */
755 #define FUNCTION_VALUE(VALTYPE, FUNC) function_value (VALTYPE, FUNC)
757 /* Define how to find the value returned by a library function
758 assuming the value has mode MODE. */
760 #define LIBCALL_VALUE(MODE) \
762 (! TARGET_SOFT_FLOAT \
763 && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28))
765 /* 1 if N is a possible register number for a function value
766 as seen by the caller. */
768 #define FUNCTION_VALUE_REGNO_P(N) \
769 ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32))
772 /* Define a data type for recording info about an argument list
773 during the scan of that argument list. This data type should
774 hold all necessary information about the function itself
775 and about the args processed so far, enough to enable macros
776 such as FUNCTION_ARG to determine where the next arg should go.
778 On the HP-PA, the WORDS field holds the number of words
779 of arguments scanned so far (including the invisible argument,
780 if any, which holds the structure-value-address). Thus, 4 or
781 more means all following args should go on the stack.
783 The INCOMING field tracks whether this is an "incoming" or
786 The INDIRECT field indicates whether this is is an indirect
789 The NARGS_PROTOTYPE field indicates that an argument does not
790 have a prototype when it less than or equal to 0. */
792 struct hppa_args {int words, nargs_prototype, incoming, indirect; };
794 #define CUMULATIVE_ARGS struct hppa_args
796 /* Initialize a variable CUM of type CUMULATIVE_ARGS
797 for a call to a function whose data type is FNTYPE.
798 For a library call, FNTYPE is 0. */
800 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL) \
802 (CUM).incoming = 0, \
803 (CUM).indirect = (FNTYPE) && !(FNDECL), \
804 (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \
805 ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
806 + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
807 || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \
812 /* Similar, but when scanning the definition of a procedure. We always
813 set NARGS_PROTOTYPE large so we never return a PARALLEL. */
815 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
817 (CUM).incoming = 1, \
818 (CUM).indirect = 0, \
819 (CUM).nargs_prototype = 1000
821 /* Figure out the size in words of the function argument. The size
822 returned by this macro should always be greater than zero because
823 we pass variable and zero sized objects by reference. */
825 #define FUNCTION_ARG_SIZE(MODE, TYPE) \
826 ((((MODE) != BLKmode \
827 ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
828 : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
830 /* Update the data in CUM to advance over an argument
831 of mode MODE and data type TYPE.
832 (TYPE is null for libcalls where that information may not be available.) */
834 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
835 { (CUM).nargs_prototype--; \
836 (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE) \
837 + (((CUM).words & 01) && (TYPE) != 0 \
838 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1); \
841 /* Determine where to put an argument to a function.
842 Value is zero to push the argument on the stack,
843 or a hard register in which to store the argument.
845 MODE is the argument's machine mode.
846 TYPE is the data type of the argument (as a tree).
847 This is null for libcalls where that information may
849 CUM is a variable of type CUMULATIVE_ARGS which gives info about
850 the preceding args and about the function being called.
851 NAMED is nonzero if this argument is a named parameter
852 (otherwise it is an extra parameter matching an ellipsis).
854 On the HP-PA the first four words of args are normally in registers
855 and the rest are pushed. But any arg that won't entirely fit in regs
858 Arguments passed in registers are either 1 or 2 words long.
860 The caller must make a distinction between calls to explicitly named
861 functions and calls through pointers to functions -- the conventions
862 are different! Calls through pointers to functions only use general
863 registers for the first four argument words.
865 Of course all this is different for the portable runtime model
866 HP wants everyone to use for ELF. Ugh. Here's a quick description
867 of how it's supposed to work.
869 1) callee side remains unchanged. It expects integer args to be
870 in the integer registers, float args in the float registers and
871 unnamed args in integer registers.
873 2) caller side now depends on if the function being called has
874 a prototype in scope (rather than if it's being called indirectly).
876 2a) If there is a prototype in scope, then arguments are passed
877 according to their type (ints in integer registers, floats in float
878 registers, unnamed args in integer registers.
880 2b) If there is no prototype in scope, then floating point arguments
881 are passed in both integer and float registers. egad.
883 FYI: The portable parameter passing conventions are almost exactly like
884 the standard parameter passing conventions on the RS6000. That's why
885 you'll see lots of similar code in rs6000.h. */
887 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE))
889 /* Do not expect to understand this without reading it several times. I'm
890 tempted to try and simply it, but I worry about breaking something. */
892 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
893 function_arg (&CUM, MODE, TYPE, NAMED)
895 /* Nonzero if we do not know how to pass TYPE solely in registers. */
896 #define MUST_PASS_IN_STACK(MODE,TYPE) \
898 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
899 || TREE_ADDRESSABLE (TYPE)))
901 /* For an arg passed partly in registers and partly in memory,
902 this is the number of registers used.
903 For args passed entirely in registers or entirely in memory, zero. */
905 /* For PA32 there are never split arguments. PA64, on the other hand, can
906 pass arguments partially in registers and partially in memory. */
907 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
908 (TARGET_64BIT ? function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) : 0)
910 /* If defined, a C expression that gives the alignment boundary, in
911 bits, of an argument with the specified mode and type. If it is
912 not defined, `PARM_BOUNDARY' is used for all arguments. */
914 /* Arguments larger than one word are double word aligned. */
916 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
918 ? (integer_zerop (TYPE_SIZE (TYPE)) \
919 || !TREE_CONSTANT (TYPE_SIZE (TYPE)) \
920 || int_size_in_bytes (TYPE) <= UNITS_PER_WORD) \
921 : GET_MODE_SIZE(MODE) <= UNITS_PER_WORD) \
922 ? PARM_BOUNDARY : MAX_PARM_BOUNDARY)
924 /* In the 32-bit runtime, arguments larger than eight bytes are passed
925 by invisible reference. As a GCC extension, we also pass anything
926 with a zero or variable size by reference.
928 The 64-bit runtime does not describe passing any types by invisible
929 reference. The internals of GCC can't currently handle passing
930 empty structures, and zero or variable length arrays when they are
931 not passed entirely on the stack or by reference. Thus, as a GCC
932 extension, we pass these types by reference. The HP compiler doesn't
933 support these types, so hopefully there shouldn't be any compatibility
934 issues. This may have to be revisited when HP releases a C99 compiler
935 or updates the ABI. */
936 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
938 ? ((TYPE) && int_size_in_bytes (TYPE) <= 0) \
939 : (((TYPE) && (int_size_in_bytes (TYPE) > 8 \
940 || int_size_in_bytes (TYPE) <= 0)) \
941 || ((MODE) && GET_MODE_SIZE (MODE) > 8)))
943 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
944 FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED)
947 extern GTY(()) rtx hppa_compare_op0;
948 extern GTY(()) rtx hppa_compare_op1;
949 extern enum cmp_type hppa_branch_type;
951 /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
952 as assembly via FUNCTION_PROFILER. Just output a local label.
953 We can't use the function label because the GAS SOM target can't
954 handle the difference of a global symbol and a local symbol. */
956 #ifndef FUNC_BEGIN_PROLOG_LABEL
957 #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
960 #define FUNCTION_PROFILER(FILE, LABEL) \
961 (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
963 #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
964 void hppa_profile_hook (int label_no);
966 /* The profile counter if emitted must come before the prologue. */
967 #define PROFILE_BEFORE_PROLOGUE 1
969 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
970 the stack pointer does not matter. The value is tested only in
971 functions that have frame pointers.
972 No definition is equivalent to always zero. */
974 extern int may_call_alloca;
976 #define EXIT_IGNORE_STACK \
977 (get_frame_size () != 0 \
978 || current_function_calls_alloca || current_function_outgoing_args_size)
980 /* Output assembler code for a block containing the constant parts
981 of a trampoline, leaving space for the variable parts.\
983 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
984 and then branches to the specified routine.
986 This code template is copied from text segment to stack location
987 and then patched with INITIALIZE_TRAMPOLINE to contain
988 valid values, and then entered as a subroutine.
990 It is best to keep this as small as possible to avoid having to
991 flush multiple lines in the cache. */
993 #define TRAMPOLINE_TEMPLATE(FILE) \
997 fputs ("\tldw 36(%r22),%r21\n", FILE); \
998 fputs ("\tbb,>=,n %r21,30,.+16\n", FILE); \
999 if (ASSEMBLER_DIALECT == 0) \
1000 fputs ("\tdepi 0,31,2,%r21\n", FILE); \
1002 fputs ("\tdepwi 0,31,2,%r21\n", FILE); \
1003 fputs ("\tldw 4(%r21),%r19\n", FILE); \
1004 fputs ("\tldw 0(%r21),%r21\n", FILE); \
1007 fputs ("\tbve (%r21)\n", FILE); \
1008 fputs ("\tldw 40(%r22),%r29\n", FILE); \
1009 fputs ("\t.word 0\n", FILE); \
1010 fputs ("\t.word 0\n", FILE); \
1014 fputs ("\tldsid (%r21),%r1\n", FILE); \
1015 fputs ("\tmtsp %r1,%sr0\n", FILE); \
1016 fputs ("\tbe 0(%sr0,%r21)\n", FILE); \
1017 fputs ("\tldw 40(%r22),%r29\n", FILE); \
1019 fputs ("\t.word 0\n", FILE); \
1020 fputs ("\t.word 0\n", FILE); \
1021 fputs ("\t.word 0\n", FILE); \
1022 fputs ("\t.word 0\n", FILE); \
1026 fputs ("\t.dword 0\n", FILE); \
1027 fputs ("\t.dword 0\n", FILE); \
1028 fputs ("\t.dword 0\n", FILE); \
1029 fputs ("\t.dword 0\n", FILE); \
1030 fputs ("\tmfia %r31\n", FILE); \
1031 fputs ("\tldd 24(%r31),%r1\n", FILE); \
1032 fputs ("\tldd 24(%r1),%r27\n", FILE); \
1033 fputs ("\tldd 16(%r1),%r1\n", FILE); \
1034 fputs ("\tbve (%r1)\n", FILE); \
1035 fputs ("\tldd 32(%r31),%r31\n", FILE); \
1036 fputs ("\t.dword 0 ; fptr\n", FILE); \
1037 fputs ("\t.dword 0 ; static link\n", FILE); \
1041 /* Length in units of the trampoline for entering a nested function. */
1043 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
1045 /* Length in units of the trampoline instruction code. */
1047 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
1049 /* Minimum length of a cache line. A length of 16 will work on all
1050 PA-RISC processors. All PA 1.1 processors have a cache line of
1051 32 bytes. Most but not all PA 2.0 processors have a cache line
1052 of 64 bytes. As cache flushes are expensive and we don't support
1053 PA 1.0, we use a minimum length of 32. */
1055 #define MIN_CACHELINE_SIZE 32
1057 /* Emit RTL insns to initialize the variable parts of a trampoline.
1058 FNADDR is an RTX for the address of the function's pure code.
1059 CXT is an RTX for the static chain value for the function.
1061 Move the function address to the trampoline template at offset 36.
1062 Move the static chain value to trampoline template at offset 40.
1063 Move the trampoline address to trampoline template at offset 44.
1064 Move r19 to trampoline template at offset 48. The latter two
1065 words create a plabel for the indirect call to the trampoline.
1067 A similar sequence is used for the 64-bit port but the plabel is
1068 at the beginning of the trampoline.
1070 Finally, the cache entries for the trampoline code are flushed.
1071 This is necessary to ensure that the trampoline instruction sequence
1072 is written to memory prior to any attempts at prefetching the code
1075 #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1077 rtx start_addr = gen_reg_rtx (Pmode); \
1078 rtx end_addr = gen_reg_rtx (Pmode); \
1079 rtx line_length = gen_reg_rtx (Pmode); \
1082 if (!TARGET_64BIT) \
1084 tmp = memory_address (Pmode, plus_constant ((TRAMP), 36)); \
1085 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1086 tmp = memory_address (Pmode, plus_constant ((TRAMP), 40)); \
1087 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1089 /* Create a fat pointer for the trampoline. */ \
1090 tmp = memory_address (Pmode, plus_constant ((TRAMP), 44)); \
1091 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (TRAMP)); \
1092 tmp = memory_address (Pmode, plus_constant ((TRAMP), 48)); \
1093 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1094 gen_rtx_REG (Pmode, 19)); \
1096 /* fdc and fic only use registers for the address to flush, \
1097 they do not accept integer displacements. We align the \
1098 start and end addresses to the beginning of their respective \
1099 cache lines to minimize the number of lines flushed. */ \
1100 tmp = force_reg (Pmode, (TRAMP)); \
1101 emit_insn (gen_andsi3 (start_addr, tmp, \
1102 GEN_INT (-MIN_CACHELINE_SIZE))); \
1103 tmp = force_reg (Pmode, \
1104 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1105 emit_insn (gen_andsi3 (end_addr, tmp, \
1106 GEN_INT (-MIN_CACHELINE_SIZE))); \
1107 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1108 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1109 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1110 gen_reg_rtx (Pmode), \
1111 gen_reg_rtx (Pmode), \
1112 gen_reg_rtx (Pmode))); \
1116 tmp = memory_address (Pmode, plus_constant ((TRAMP), 56)); \
1117 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (FNADDR)); \
1118 tmp = memory_address (Pmode, plus_constant ((TRAMP), 64)); \
1119 emit_move_insn (gen_rtx_MEM (Pmode, tmp), (CXT)); \
1121 /* Create a fat pointer for the trampoline. */ \
1122 tmp = memory_address (Pmode, plus_constant ((TRAMP), 16)); \
1123 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1124 force_reg (Pmode, plus_constant ((TRAMP), 32))); \
1125 tmp = memory_address (Pmode, plus_constant ((TRAMP), 24)); \
1126 emit_move_insn (gen_rtx_MEM (Pmode, tmp), \
1127 gen_rtx_REG (Pmode, 27)); \
1129 /* fdc and fic only use registers for the address to flush, \
1130 they do not accept integer displacements. We align the \
1131 start and end addresses to the beginning of their respective \
1132 cache lines to minimize the number of lines flushed. */ \
1133 tmp = force_reg (Pmode, plus_constant ((TRAMP), 32)); \
1134 emit_insn (gen_anddi3 (start_addr, tmp, \
1135 GEN_INT (-MIN_CACHELINE_SIZE))); \
1136 tmp = force_reg (Pmode, \
1137 plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1)); \
1138 emit_insn (gen_anddi3 (end_addr, tmp, \
1139 GEN_INT (-MIN_CACHELINE_SIZE))); \
1140 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE)); \
1141 emit_insn (gen_dcacheflush (start_addr, end_addr, line_length)); \
1142 emit_insn (gen_icacheflush (start_addr, end_addr, line_length, \
1143 gen_reg_rtx (Pmode), \
1144 gen_reg_rtx (Pmode), \
1145 gen_reg_rtx (Pmode))); \
1149 /* Perform any machine-specific adjustment in the address of the trampoline.
1150 ADDR contains the address that was passed to INITIALIZE_TRAMPOLINE.
1151 Adjust the trampoline address to point to the plabel at offset 44. */
1153 #define TRAMPOLINE_ADJUST_ADDRESS(ADDR) \
1154 if (!TARGET_64BIT) (ADDR) = memory_address (Pmode, plus_constant ((ADDR), 46))
1156 /* Emit code for a call to builtin_saveregs. We must emit USE insns which
1157 reference the 4 integer arg registers and 4 fp arg registers.
1158 Ordinarily they are not call used registers, but they are for
1159 _builtin_saveregs, so we must make this explicit. */
1161 #define EXPAND_BUILTIN_SAVEREGS() hppa_builtin_saveregs ()
1163 /* Implement `va_start' for varargs and stdarg. */
1165 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
1166 hppa_va_start (valist, nextarg)
1168 /* Implement `va_arg'. */
1170 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
1171 hppa_va_arg (valist, type)
1173 /* Addressing modes, and classification of registers for them.
1175 Using autoincrement addressing modes on PA8000 class machines is
1178 #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
1179 #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
1181 #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
1182 #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
1184 /* Macros to check register numbers against specific register classes. */
1186 /* These assume that REGNO is a hard or pseudo reg number.
1187 They give nonzero only if REGNO is a hard reg of the suitable class
1188 or a pseudo reg currently allocated to a suitable hard reg.
1189 Since they use reg_renumber, they are safe only once reg_renumber
1190 has been allocated, which happens in local-alloc.c. */
1192 #define REGNO_OK_FOR_INDEX_P(REGNO) \
1193 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1194 #define REGNO_OK_FOR_BASE_P(REGNO) \
1195 ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32))
1196 #define REGNO_OK_FOR_FP_P(REGNO) \
1197 (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO]))
1199 /* Now macros that check whether X is a register and also,
1200 strictly, whether it is in a specified class.
1202 These macros are specific to the HP-PA, and may be used only
1203 in code for printing assembler insns and in conditions for
1204 define_optimization. */
1206 /* 1 if X is an fp register. */
1208 #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1210 /* Maximum number of registers that can appear in a valid memory address. */
1212 #define MAX_REGS_PER_ADDRESS 2
1214 /* Recognize any constant value that is a valid address except
1215 for symbolic addresses. We get better CSE by rejecting them
1216 here and allowing hppa_legitimize_address to break them up. We
1217 use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
1219 #define CONSTANT_ADDRESS_P(X) \
1220 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
1221 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
1222 || GET_CODE (X) == HIGH) \
1223 && (reload_in_progress || reload_completed || ! symbolic_expression_p (X)))
1225 /* A C expression that is nonzero if we are using the new HP assembler. */
1227 #ifndef NEW_HP_ASSEMBLER
1228 #define NEW_HP_ASSEMBLER 0
1231 /* The macros below define the immediate range for CONST_INTS on
1232 the 64-bit port. Constants in this range can be loaded in three
1233 instructions using a ldil/ldo/depdi sequence. Constants outside
1234 this range are forced to the constant pool prior to reload. */
1236 #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
1237 #define MIN_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) -32 << 31)
1238 #define LEGITIMATE_64BIT_CONST_INT_P(X) \
1239 ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
1241 /* A C expression that is nonzero if X is a legitimate constant for an
1244 We include all constant integers and constant doubles, but not
1245 floating-point, except for floating-point zero. We reject LABEL_REFs
1246 if we're not using gas or the new HP assembler.
1248 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
1249 that need more than three instructions to load prior to reload. This
1250 limit is somewhat arbitrary. It takes three instructions to load a
1251 CONST_INT from memory but two are memory accesses. It may be better
1252 to increase the allowed range for CONST_INTS. We may also be able
1253 to handle CONST_DOUBLES. */
1255 #define LEGITIMATE_CONSTANT_P(X) \
1256 ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \
1257 || (X) == CONST0_RTX (GET_MODE (X))) \
1258 && (NEW_HP_ASSEMBLER || TARGET_GAS || GET_CODE (X) != LABEL_REF) \
1259 && !(TARGET_64BIT && GET_CODE (X) == CONST_DOUBLE) \
1260 && !(TARGET_64BIT && GET_CODE (X) == CONST_INT \
1261 && !(HOST_BITS_PER_WIDE_INT <= 32 \
1262 || (reload_in_progress || reload_completed) \
1263 || LEGITIMATE_64BIT_CONST_INT_P (INTVAL (X)) \
1264 || cint_ok_for_move (INTVAL (X)))) \
1265 && !function_label_operand (X, VOIDmode))
1267 /* Subroutines for EXTRA_CONSTRAINT.
1269 Return 1 iff OP is a pseudo which did not get a hard register and
1270 we are running the reload pass. */
1271 #define IS_RELOADING_PSEUDO_P(OP) \
1272 ((reload_in_progress \
1273 && GET_CODE (OP) == REG \
1274 && REGNO (OP) >= FIRST_PSEUDO_REGISTER \
1275 && reg_renumber [REGNO (OP)] < 0))
1277 /* Return 1 iff OP is a scaled or unscaled index address. */
1278 #define IS_INDEX_ADDR_P(OP) \
1279 (GET_CODE (OP) == PLUS \
1280 && GET_MODE (OP) == Pmode \
1281 && (GET_CODE (XEXP (OP, 0)) == MULT \
1282 || GET_CODE (XEXP (OP, 1)) == MULT \
1283 || (REG_P (XEXP (OP, 0)) \
1284 && REG_P (XEXP (OP, 1)))))
1286 /* Return 1 iff OP is a LO_SUM DLT address. */
1287 #define IS_LO_SUM_DLT_ADDR_P(OP) \
1288 (GET_CODE (OP) == LO_SUM \
1289 && GET_MODE (OP) == Pmode \
1290 && REG_P (XEXP (OP, 0)) \
1291 && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
1292 && GET_CODE (XEXP (OP, 1)) == UNSPEC)
1294 /* Optional extra constraints for this machine. Borrowed from sparc.h.
1296 `A' is a LO_SUM DLT memory operand.
1298 `Q' is any memory operand that isn't a symbolic, indexed or lo_sum
1299 memory operand. Note that an unassigned pseudo register is such a
1300 memory operand. Needed because reload will generate these things
1301 and then not re-recognize the insn, causing constrain_operands to
1304 `R' is a scaled/unscaled indexed memory operand.
1306 `S' is the constant 31.
1308 `T' is for fp loads and stores.
1310 `U' is the constant 63. */
1312 #define EXTRA_CONSTRAINT(OP, C) \
1314 (IS_RELOADING_PSEUDO_P (OP) \
1315 || (GET_CODE (OP) == MEM \
1316 && (reload_in_progress \
1317 || memory_address_p (GET_MODE (OP), XEXP (OP, 0))) \
1318 && !symbolic_memory_operand (OP, VOIDmode) \
1319 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1320 && !IS_INDEX_ADDR_P (XEXP (OP, 0)))) \
1322 (GET_CODE (OP) == MEM \
1323 && IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0))) \
1325 (GET_CODE (OP) == MEM \
1326 && IS_INDEX_ADDR_P (XEXP (OP, 0))) \
1328 (GET_CODE (OP) == MEM \
1329 && !IS_LO_SUM_DLT_ADDR_P (XEXP (OP, 0)) \
1330 && !IS_INDEX_ADDR_P (XEXP (OP, 0)) \
1331 /* Using DFmode forces only short displacements \
1332 to be recognized as valid in reg+d addresses. \
1333 However, this is not necessary for PA2.0 since \
1334 it has long FP loads/stores. \
1336 FIXME: the ELF32 linker clobbers the LSB of \
1337 the FP register number in {fldw,fstw} insns. \
1338 Thus, we only allow long FP loads/stores on \
1340 && memory_address_p ((TARGET_PA_20 && !TARGET_ELF32 \
1345 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 31) \
1347 (GET_CODE (OP) == CONST_INT && INTVAL (OP) == 63) : 0))))))
1350 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1351 and check its validity for a certain class.
1352 We have two alternate definitions for each of them.
1353 The usual definition accepts all pseudo regs; the other rejects
1354 them unless they have been allocated suitable hard regs.
1355 The symbol REG_OK_STRICT causes the latter definition to be used.
1357 Most source files want to accept pseudo regs in the hope that
1358 they will get allocated to the class that the insn wants them to be in.
1359 Source files for reload pass need to be strict.
1360 After reload, it makes no difference, since pseudo regs have
1361 been eliminated by then. */
1363 #ifndef REG_OK_STRICT
1365 /* Nonzero if X is a hard reg that can be used as an index
1366 or if it is a pseudo reg. */
1367 #define REG_OK_FOR_INDEX_P(X) \
1368 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1369 /* Nonzero if X is a hard reg that can be used as a base reg
1370 or if it is a pseudo reg. */
1371 #define REG_OK_FOR_BASE_P(X) \
1372 (REGNO (X) && (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER))
1376 /* Nonzero if X is a hard reg that can be used as an index. */
1377 #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1378 /* Nonzero if X is a hard reg that can be used as a base reg. */
1379 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1383 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression that is a
1384 valid memory address for an instruction. The MODE argument is the
1385 machine mode for the MEM expression that wants to use this address.
1387 On HP PA-RISC, the legitimate address forms are REG+SMALLINT,
1388 REG+REG, and REG+(REG*SCALE). The indexed address forms are only
1389 available with floating point loads and stores, and integer loads.
1390 We get better code by allowing indexed addresses in the initial
1393 The acceptance of indexed addresses as legitimate implies that we
1394 must provide patterns for doing indexed integer stores, or the move
1395 expanders must force the address of an indexed store to a register.
1396 We have adopted the latter approach.
1398 Another function of GO_IF_LEGITIMATE_ADDRESS is to ensure that
1399 the base register is a valid pointer for indexed instructions.
1400 On targets that have non-equivalent space registers, we have to
1401 know at the time of assembler output which register in a REG+REG
1402 pair is the base register. The REG_POINTER flag is sometimes lost
1403 in reload and the following passes, so it can't be relied on during
1404 code generation. Thus, we either have to canonicalize the order
1405 of the registers in REG+REG indexed addresses, or treat REG+REG
1406 addresses separately and provide patterns for both permutations.
1408 The latter approach requires several hundred additional lines of
1409 code in pa.md. The downside to canonicalizing is that a PLUS
1410 in the wrong order can't combine to form to make a scaled indexed
1411 memory operand. As we won't need to canonicalize the operands if
1412 the REG_POINTER lossage can be fixed, it seems better canonicalize.
1414 We initially break out scaled indexed addresses in canonical order
1415 in emit_move_sequence. LEGITIMIZE_ADDRESS also canonicalizes
1416 scaled indexed addresses during RTL generation. However, fold_rtx
1417 has its own opinion on how the operands of a PLUS should be ordered.
1418 If one of the operands is equivalent to a constant, it will make
1419 that operand the second operand. As the base register is likely to
1420 be equivalent to a SYMBOL_REF, we have made it the second operand.
1422 GO_IF_LEGITIMATE_ADDRESS accepts REG+REG as legitimate when the
1423 operands are in the order INDEX+BASE on targets with non-equivalent
1424 space registers, and in any order on targets with equivalent space
1425 registers. It accepts both MULT+BASE and BASE+MULT for scaled indexing.
1427 We treat a SYMBOL_REF as legitimate if it is part of the current
1428 function's constant-pool, because such addresses can actually be
1429 output as REG+SMALLINT.
1431 Note we only allow 5 bit immediates for access to a constant address;
1432 doing so avoids losing for loading/storing a FP register at an address
1433 which will not fit in 5 bits. */
1435 #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
1436 #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
1438 #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
1439 #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
1441 #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
1442 #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
1444 #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
1445 #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
1447 #if HOST_BITS_PER_WIDE_INT > 32
1448 #define VAL_32_BITS_P(X) \
1449 ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
1450 < (unsigned HOST_WIDE_INT) 2 << 31)
1452 #define VAL_32_BITS_P(X) 1
1454 #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
1456 /* These are the modes that we allow for scaled indexing. */
1457 #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
1458 ((TARGET_64BIT && (MODE) == DImode) \
1459 || (MODE) == SImode \
1460 || (MODE) == HImode \
1461 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1463 /* These are the modes that we allow for unscaled indexing. */
1464 #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
1465 ((TARGET_64BIT && (MODE) == DImode) \
1466 || (MODE) == SImode \
1467 || (MODE) == HImode \
1468 || (MODE) == QImode \
1469 || (!TARGET_SOFT_FLOAT && ((MODE) == DFmode || (MODE) == SFmode)))
1471 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1473 if ((REG_P (X) && REG_OK_FOR_BASE_P (X)) \
1474 || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC \
1475 || GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC) \
1476 && REG_P (XEXP (X, 0)) \
1477 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) \
1479 else if (GET_CODE (X) == PLUS) \
1481 rtx base = 0, index = 0; \
1482 if (REG_P (XEXP (X, 1)) \
1483 && REG_OK_FOR_BASE_P (XEXP (X, 1))) \
1484 base = XEXP (X, 1), index = XEXP (X, 0); \
1485 else if (REG_P (XEXP (X, 0)) \
1486 && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1487 base = XEXP (X, 0), index = XEXP (X, 1); \
1489 && GET_CODE (index) == CONST_INT \
1490 && ((INT_14_BITS (index) \
1491 && (TARGET_SOFT_FLOAT \
1493 && ((MODE == SFmode \
1494 && (INTVAL (index) % 4) == 0) \
1495 || (MODE == DFmode \
1496 && (INTVAL (index) % 8) == 0))) \
1497 || ((MODE) != SFmode && (MODE) != DFmode))) \
1498 || INT_5_BITS (index))) \
1500 if (!TARGET_DISABLE_INDEXING \
1501 /* Only accept the "canonical" INDEX+BASE operand order \
1502 on targets with non-equivalent space registers. */ \
1503 && (TARGET_NO_SPACE_REGS \
1504 ? (base && REG_P (index)) \
1505 : (base == XEXP (X, 1) && REG_P (index) \
1506 && REG_POINTER (base) && !REG_POINTER (index))) \
1507 && MODE_OK_FOR_UNSCALED_INDEXING_P (MODE) \
1508 && REG_OK_FOR_INDEX_P (index) \
1509 && borx_reg_operand (base, Pmode) \
1510 && borx_reg_operand (index, Pmode)) \
1512 if (!TARGET_DISABLE_INDEXING \
1514 && GET_CODE (index) == MULT \
1515 && MODE_OK_FOR_SCALED_INDEXING_P (MODE) \
1516 && REG_P (XEXP (index, 0)) \
1517 && GET_MODE (XEXP (index, 0)) == Pmode \
1518 && REG_OK_FOR_INDEX_P (XEXP (index, 0)) \
1519 && GET_CODE (XEXP (index, 1)) == CONST_INT \
1520 && INTVAL (XEXP (index, 1)) \
1521 == (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
1522 && borx_reg_operand (base, Pmode)) \
1525 else if (GET_CODE (X) == LO_SUM \
1526 && GET_CODE (XEXP (X, 0)) == REG \
1527 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1528 && CONSTANT_P (XEXP (X, 1)) \
1529 && (TARGET_SOFT_FLOAT \
1530 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1533 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1534 || ((MODE) != SFmode \
1535 && (MODE) != DFmode))) \
1537 else if (GET_CODE (X) == LO_SUM \
1538 && GET_CODE (XEXP (X, 0)) == SUBREG \
1539 && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG \
1540 && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0))) \
1541 && CONSTANT_P (XEXP (X, 1)) \
1542 && (TARGET_SOFT_FLOAT \
1543 /* We can allow symbolic LO_SUM addresses for PA2.0. */ \
1546 && GET_CODE (XEXP (X, 1)) != CONST_INT) \
1547 || ((MODE) != SFmode \
1548 && (MODE) != DFmode))) \
1550 else if (GET_CODE (X) == LABEL_REF \
1551 || (GET_CODE (X) == CONST_INT \
1552 && INT_5_BITS (X))) \
1554 /* Needed for -fPIC */ \
1555 else if (GET_CODE (X) == LO_SUM \
1556 && GET_CODE (XEXP (X, 0)) == REG \
1557 && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1558 && GET_CODE (XEXP (X, 1)) == UNSPEC \
1559 && (TARGET_SOFT_FLOAT \
1560 || (TARGET_PA_20 && !TARGET_ELF32) \
1561 || ((MODE) != SFmode \
1562 && (MODE) != DFmode))) \
1566 /* Look for machine dependent ways to make the invalid address AD a
1569 For the PA, transform:
1571 memory(X + <large int>)
1575 if (<large int> & mask) >= 16
1576 Y = (<large int> & ~mask) + mask + 1 Round up.
1578 Y = (<large int> & ~mask) Round down.
1580 memory (Z + (<large int> - Y));
1582 This makes reload inheritance and reload_cse work better since Z
1585 There may be more opportunities to improve code with this hook. */
1586 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \
1588 long offset, newoffset, mask; \
1589 rtx new, temp = NULL_RTX; \
1591 mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT \
1592 ? (TARGET_PA_20 && !TARGET_ELF32 ? 0x3fff : 0x1f) : 0x3fff); \
1594 if (optimize && GET_CODE (AD) == PLUS) \
1595 temp = simplify_binary_operation (PLUS, Pmode, \
1596 XEXP (AD, 0), XEXP (AD, 1)); \
1598 new = temp ? temp : AD; \
1601 && GET_CODE (new) == PLUS \
1602 && GET_CODE (XEXP (new, 0)) == REG \
1603 && GET_CODE (XEXP (new, 1)) == CONST_INT) \
1605 offset = INTVAL (XEXP ((new), 1)); \
1607 /* Choose rounding direction. Round up if we are >= halfway. */ \
1608 if ((offset & mask) >= ((mask + 1) / 2)) \
1609 newoffset = (offset & ~mask) + mask + 1; \
1611 newoffset = offset & ~mask; \
1613 if (newoffset != 0 && VAL_14_BITS_P (newoffset)) \
1615 temp = gen_rtx_PLUS (Pmode, XEXP (new, 0), \
1616 GEN_INT (newoffset)); \
1617 AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
1618 push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0, \
1619 BASE_REG_CLASS, Pmode, VOIDmode, 0, 0, \
1629 /* Try machine-dependent ways of modifying an illegitimate address
1630 to be legitimate. If we find one, return the new, valid address.
1631 This macro is used in only one place: `memory_address' in explow.c.
1633 OLDX is the address as it was before break_out_memory_refs was called.
1634 In some cases it is useful to look at this to decide what needs to be done.
1636 MODE and WIN are passed so that this macro can use
1637 GO_IF_LEGITIMATE_ADDRESS.
1639 It is always safe for this macro to do nothing. It exists to recognize
1640 opportunities to optimize the output. */
1642 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1643 { rtx orig_x = (X); \
1644 (X) = hppa_legitimize_address (X, OLDX, MODE); \
1645 if ((X) != orig_x && memory_address_p (MODE, X)) \
1648 /* Go to LABEL if ADDR (a legitimate address expression)
1649 has an effect that depends on the machine mode it is used for. */
1651 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1652 if (GET_CODE (ADDR) == PRE_DEC \
1653 || GET_CODE (ADDR) == POST_DEC \
1654 || GET_CODE (ADDR) == PRE_INC \
1655 || GET_CODE (ADDR) == POST_INC) \
1658 #define TARGET_ASM_SELECT_SECTION pa_select_section
1660 /* Return a nonzero value if DECL has a section attribute. */
1661 #define IN_NAMED_SECTION_P(DECL) \
1662 ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
1663 && DECL_SECTION_NAME (DECL) != NULL_TREE)
1665 /* Define this macro if references to a symbol must be treated
1666 differently depending on something about the variable or
1667 function named by the symbol (such as what section it is in).
1669 The macro definition, if any, is executed immediately after the
1670 rtl for DECL or other node is created.
1671 The value of the rtl will be a `mem' whose address is a
1674 The usual thing for this macro to do is to a flag in the
1675 `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
1676 name string in the `symbol_ref' (if one bit is not enough
1679 On the HP-PA we use this to indicate if a symbol is in text or
1680 data space. Also, function labels need special treatment. */
1682 #define TEXT_SPACE_P(DECL)\
1683 (TREE_CODE (DECL) == FUNCTION_DECL \
1684 || (TREE_CODE (DECL) == VAR_DECL \
1685 && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1686 && (! DECL_INITIAL (DECL) || ! reloc_needed (DECL_INITIAL (DECL))) \
1688 || (TREE_CODE_CLASS (TREE_CODE (DECL)) == 'c' \
1689 && !(TREE_CODE (DECL) == STRING_CST && flag_writable_strings)))
1691 #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1693 /* Specify the machine mode that this machine uses for the index in the
1694 tablejump instruction. For small tables, an element consists of a
1695 ia-relative branch and its delay slot. When -mbig-switch is specified,
1696 we use a 32-bit absolute address for non-pic code, and a 32-bit offset
1697 for both 32 and 64-bit pic code. */
1698 #define CASE_VECTOR_MODE (TARGET_BIG_SWITCH ? SImode : DImode)
1700 /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1701 #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1703 /* Define this as 1 if `char' should by default be signed; else as 0. */
1704 #define DEFAULT_SIGNED_CHAR 1
1706 /* Max number of bytes we can move from memory to memory
1707 in one reasonably fast instruction. */
1710 /* Higher than the default as we prefer to use simple move insns
1711 (better scheduling and delay slot filling) and because our
1712 built-in block move is really a 2X unrolled loop.
1714 Believe it or not, this has to be big enough to allow for copying all
1715 arguments passed in registers to avoid infinite recursion during argument
1716 setup for a function call. Why? Consider how we copy the stack slots
1717 reserved for parameters when they may be trashed by a call. */
1718 #define MOVE_RATIO (TARGET_64BIT ? 8 : 4)
1720 /* Define if operations between registers always perform the operation
1721 on the full register even if a narrower mode is specified. */
1722 #define WORD_REGISTER_OPERATIONS
1724 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1725 will either zero-extend or sign-extend. The value of this macro should
1726 be the code that says which one of the two operations is implicitly
1727 done, NIL if none. */
1728 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1730 /* Nonzero if access to memory by bytes is slow and undesirable. */
1731 #define SLOW_BYTE_ACCESS 1
1733 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1734 is done just by pretending it is already truncated. */
1735 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1737 /* When a prototype says `char' or `short', really pass an `int'. */
1738 #define PROMOTE_PROTOTYPES 1
1739 #define PROMOTE_FUNCTION_RETURN 1
1741 /* Specify the machine mode that pointers have.
1742 After generation of rtl, the compiler makes no further distinction
1743 between pointers and any other objects of this machine mode. */
1744 #define Pmode word_mode
1746 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1747 return the mode to be used for the comparison. For floating-point, CCFPmode
1748 should be used. CC_NOOVmode should be used when the first operand is a
1749 PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1751 #define SELECT_CC_MODE(OP,X,Y) \
1752 (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1754 /* A function address in a call instruction
1755 is a byte address (for indexing purposes)
1756 so give the MEM rtx a byte's mode. */
1757 #define FUNCTION_MODE SImode
1759 /* Define this if addresses of constant functions
1760 shouldn't be put through pseudo regs where they can be cse'd.
1761 Desirable on machines where ordinary constants are expensive
1762 but a CALL with constant address is cheap. */
1763 #define NO_FUNCTION_CSE
1765 /* Define this to be nonzero if shift instructions ignore all but the low-order
1767 #define SHIFT_COUNT_TRUNCATED 1
1769 /* Compute extra cost of moving data between one register class
1772 Make moves from SAR so expensive they should never happen. We used to
1773 have 0xffff here, but that generates overflow in rare cases.
1775 Copies involving a FP register and a non-FP register are relatively
1776 expensive because they must go through memory.
1778 Other copies are reasonably cheap. */
1779 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \
1780 (CLASS1 == SHIFT_REGS ? 0x100 \
1781 : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \
1782 : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \
1785 /* Adjust the cost of branches. */
1786 #define BRANCH_COST (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1788 /* Handling the special cases is going to get too complicated for a macro,
1789 just call `pa_adjust_insn_length' to do the real work. */
1790 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1791 LENGTH += pa_adjust_insn_length (INSN, LENGTH);
1793 /* Millicode insns are actually function calls with some special
1794 constraints on arguments and register usage.
1796 Millicode calls always expect their arguments in the integer argument
1797 registers, and always return their result in %r29 (ret1). They
1798 are expected to clobber their arguments, %r1, %r29, and the return
1799 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1801 This macro tells reorg that the references to arguments and
1802 millicode calls do not appear to happen until after the millicode call.
1803 This allows reorg to put insns which set the argument registers into the
1804 delay slot of the millicode call -- thus they act more like traditional
1807 Note we can not consider side effects of the insn to be delayed because
1808 the branch and link insn will clobber the return pointer. If we happened
1809 to use the return pointer in the delay slot of the call, then we lose.
1811 get_attr_type will try to recognize the given insn, so make sure to
1812 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1814 #define INSN_REFERENCES_ARE_DELAYED(X) (insn_refs_are_delayed (X))
1817 /* Control the assembler format that we output. */
1819 /* A C string constant describing how to begin a comment in the target
1820 assembler language. The compiler assumes that the comment will end at
1821 the end of the line. */
1823 #define ASM_COMMENT_START ";"
1825 /* Output to assembler file text saying following lines
1826 may contain character constants, extra white space, comments, etc. */
1828 #define ASM_APP_ON ""
1830 /* Output to assembler file text saying following lines
1831 no longer contain unusual constructs. */
1833 #define ASM_APP_OFF ""
1835 /* This is how to output the definition of a user-level label named NAME,
1836 such as the label on a static function or variable NAME. */
1838 #define ASM_OUTPUT_LABEL(FILE, NAME) \
1839 do { assemble_name (FILE, NAME); \
1840 fputc ('\n', FILE); } while (0)
1842 /* This is how to output a reference to a user-level label named NAME.
1843 `assemble_name' uses this. */
1845 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1847 const char *xname = (NAME); \
1848 if (FUNCTION_NAME_P (NAME)) \
1850 if (xname[0] == '*') \
1853 fputs (user_label_prefix, FILE); \
1854 fputs (xname, FILE); \
1857 /* This is how to store into the string LABEL
1858 the symbol_ref name of an internal numbered label where
1859 PREFIX is the class of label and NUM is the number within the class.
1860 This is suitable for output with `assemble_name'. */
1862 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1863 sprintf (LABEL, "*%c$%s%04ld", (PREFIX)[0], (PREFIX) + 1, (long)(NUM))
1865 #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1867 #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1868 output_ascii ((FILE), (P), (SIZE))
1870 /* Jump tables are always placed in the text section. Technically, it
1871 is possible to put them in the readonly data section when -mbig-switch
1872 is specified. This has the benefit of getting the table out of .text
1873 and reducing branch lengths as a result. The downside is that an
1874 additional insn (addil) is needed to access the table when generating
1875 PIC code. The address difference table also has to use 32-bit
1876 pc-relative relocations. Currently, GAS does not support these
1877 relocations, although it is easily modified to do this operation.
1878 The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1879 when using ELF GAS. A simple difference can be used when using
1880 SOM GAS or the HP assembler. The final downside is GDB complains
1881 about the nesting of the label for the table when debugging. */
1883 #define JUMP_TABLES_IN_TEXT_SECTION 1
1885 /* This is how to output an element of a case-vector that is absolute. */
1887 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1888 if (TARGET_BIG_SWITCH) \
1889 fprintf (FILE, "\t.word L$%04d\n", VALUE); \
1891 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1893 /* This is how to output an element of a case-vector that is relative.
1894 Since we always place jump tables in the text section, the difference
1895 is absolute and requires no relocation. */
1897 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1898 if (TARGET_BIG_SWITCH) \
1899 fprintf (FILE, "\t.word L$%04d-L$%04d\n", VALUE, REL); \
1901 fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE)
1903 /* This is how to output an assembler line that says to advance the
1904 location counter to a multiple of 2**LOG bytes. */
1906 #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1907 fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1909 #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1910 fprintf (FILE, "\t.blockz "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1911 (unsigned HOST_WIDE_INT)(SIZE))
1913 /* This says how to output an assembler line to define a global common symbol
1914 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1916 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \
1918 assemble_name ((FILE), (NAME)); \
1919 fprintf ((FILE), "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1920 MAX ((unsigned HOST_WIDE_INT)(SIZE), \
1921 ((unsigned HOST_WIDE_INT)(ALIGNED) / BITS_PER_UNIT)));}
1923 /* This says how to output an assembler line to define a local common symbol
1924 with size SIZE (in bytes) and alignment ALIGN (in bits). */
1926 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \
1928 fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \
1929 assemble_name ((FILE), (NAME)); \
1930 fprintf ((FILE), "\n\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1931 (unsigned HOST_WIDE_INT)(SIZE));}
1933 #define ASM_PN_FORMAT "%s___%lu"
1935 /* All HP assemblers use "!" to separate logical lines. */
1936 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!')
1938 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
1939 ((CHAR) == '@' || (CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^')
1941 /* Print operand X (an rtx) in assembler syntax to file FILE.
1942 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1943 For `%' followed by punctuation, CODE is the punctuation and X is null.
1945 On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1946 and an immediate zero should be represented as `r0'.
1948 Several % codes are defined:
1950 C compare conditions
1951 N extract conditions
1952 M modifier to handle preincrement addressing for memory refs.
1953 F modifier to handle preincrement addressing for fp memory refs */
1955 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1958 /* Print a memory address as an operand to reference that memory location. */
1960 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1961 { register rtx addr = ADDR; \
1962 register rtx base; \
1964 switch (GET_CODE (addr)) \
1967 fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1970 if (GET_CODE (XEXP (addr, 0)) == CONST_INT) \
1971 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); \
1972 else if (GET_CODE (XEXP (addr, 1)) == CONST_INT) \
1973 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); \
1976 fprintf (FILE, "%d(%s)", offset, reg_names [REGNO (base)]); \
1979 if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1980 fputs ("R'", FILE); \
1981 else if (flag_pic == 0) \
1982 fputs ("RR'", FILE); \
1984 fputs ("RT'", FILE); \
1985 output_global_address (FILE, XEXP (addr, 1), 0); \
1986 fputs ("(", FILE); \
1987 output_operand (XEXP (addr, 0), 0); \
1988 fputs (")", FILE); \
1991 fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1994 output_addr_const (FILE, addr); \
1998 /* Find the return address associated with the frame given by
2000 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
2001 (return_addr_rtx (COUNT, FRAMEADDR))
2003 /* Used to mask out junk bits from the return address, such as
2004 processor state, interrupt status, condition codes and the like. */
2005 #define MASK_RETURN_ADDR \
2006 /* The privilege level is in the two low order bits, mask em out \
2007 of the return address. */ \
2010 /* The number of Pmode words for the setjmp buffer. */
2011 #define JMP_BUF_SIZE 50
2013 #define PREDICATE_CODES \
2014 {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \
2015 {"call_operand_address", {LABEL_REF, SYMBOL_REF, CONST_INT, \
2016 CONST_DOUBLE, CONST, HIGH, CONSTANT_P_RTX}}, \
2017 {"indexed_memory_operand", {SUBREG, MEM}}, \
2018 {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \
2019 {"symbolic_memory_operand", {SUBREG, MEM}}, \
2020 {"reg_before_reload_operand", {REG, MEM}}, \
2021 {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, MEM, CONST_INT, \
2023 {"move_dest_operand", {SUBREG, REG, MEM}}, \
2024 {"move_src_operand", {SUBREG, REG, CONSTANT_P_RTX, CONST_INT, MEM}}, \
2025 {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
2026 {"pic_label_operand", {LABEL_REF, CONST}}, \
2027 {"fp_reg_operand", {REG}}, \
2028 {"arith_operand", {SUBREG, REG, CONST_INT}}, \
2029 {"arith11_operand", {SUBREG, REG, CONST_INT}}, \
2030 {"pre_cint_operand", {CONST_INT}}, \
2031 {"post_cint_operand", {CONST_INT}}, \
2032 {"arith_double_operand", {SUBREG, REG, CONST_DOUBLE}}, \
2033 {"ireg_or_int5_operand", {CONST_INT, REG}}, \
2034 {"int5_operand", {CONST_INT}}, \
2035 {"uint5_operand", {CONST_INT}}, \
2036 {"int11_operand", {CONST_INT}}, \
2037 {"uint32_operand", {CONST_INT, \
2038 HOST_BITS_PER_WIDE_INT > 32 ? 0 : CONST_DOUBLE}}, \
2039 {"arith5_operand", {SUBREG, REG, CONST_INT}}, \
2040 {"and_operand", {SUBREG, REG, CONST_INT}}, \
2041 {"ior_operand", {CONST_INT}}, \
2042 {"lhs_lshift_cint_operand", {CONST_INT}}, \
2043 {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \
2044 {"arith32_operand", {SUBREG, REG, CONST_INT}}, \
2045 {"pc_or_label_operand", {PC, LABEL_REF}}, \
2046 {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \
2047 {"shadd_operand", {CONST_INT}}, \
2048 {"div_operand", {REG, CONST_INT}}, \
2049 {"ireg_operand", {REG}}, \
2050 {"cmpib_comparison_operator", {EQ, NE, LT, LE, LEU, \
2052 {"movb_comparison_operator", {EQ, NE, LT, GE}},
2054 /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
2055 #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
2056 "__canonicalize_funcptr_for_compare"
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