1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
48 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || (get_attr_type (in_insn) != TYPE_FPSTORE
62 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
63 || recog_memoized (out_insn) < 0)
66 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
68 set = single_set (out_insn);
72 other_mode = GET_MODE (SET_SRC (set));
74 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
78 #ifndef DO_FRAME_NOTES
79 #ifdef INCOMING_RETURN_ADDR_RTX
80 #define DO_FRAME_NOTES 1
82 #define DO_FRAME_NOTES 0
86 static void copy_reg_pointer (rtx, rtx);
87 static void fix_range (const char *);
88 static bool pa_handle_option (size_t, const char *, int);
89 static int hppa_address_cost (rtx);
90 static bool hppa_rtx_costs (rtx, int, int, int *);
91 static inline rtx force_mode (enum machine_mode, rtx);
92 static void pa_reorg (void);
93 static void pa_combine_instructions (void);
94 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
95 static int forward_branch_p (rtx);
96 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
97 static int compute_movmem_length (rtx);
98 static int compute_clrmem_length (rtx);
99 static bool pa_assemble_integer (rtx, unsigned int, int);
100 static void remove_useless_addtr_insns (int);
101 static void store_reg (int, HOST_WIDE_INT, int);
102 static void store_reg_modify (int, int, HOST_WIDE_INT);
103 static void load_reg (int, HOST_WIDE_INT, int);
104 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
105 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
106 static void update_total_code_bytes (int);
107 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
108 static int pa_adjust_cost (rtx, rtx, rtx, int);
109 static int pa_adjust_priority (rtx, int);
110 static int pa_issue_rate (void);
111 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
112 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
114 static void pa_encode_section_info (tree, rtx, int);
115 static const char *pa_strip_name_encoding (const char *);
116 static bool pa_function_ok_for_sibcall (tree, tree);
117 static void pa_globalize_label (FILE *, const char *)
119 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
120 HOST_WIDE_INT, tree);
121 #if !defined(USE_COLLECT2)
122 static void pa_asm_out_constructor (rtx, int);
123 static void pa_asm_out_destructor (rtx, int);
125 static void pa_init_builtins (void);
126 static rtx hppa_builtin_saveregs (void);
127 static void hppa_va_start (tree, rtx);
128 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
129 static bool pa_scalar_mode_supported_p (enum machine_mode);
130 static bool pa_commutative_p (const_rtx x, int outer_code);
131 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
132 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
135 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
136 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
137 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
140 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
141 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
142 static void output_deferred_plabels (void);
143 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
144 #ifdef ASM_OUTPUT_EXTERNAL_REAL
145 static void pa_hpux_file_end (void);
147 #ifdef HPUX_LONG_DOUBLE_LIBRARY
148 static void pa_hpux_init_libfuncs (void);
150 static rtx pa_struct_value_rtx (tree, int);
151 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
153 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
155 static struct machine_function * pa_init_machine_status (void);
156 static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
158 secondary_reload_info *);
159 static void pa_extra_live_on_entry (bitmap);
161 /* The following extra sections are only used for SOM. */
162 static GTY(()) section *som_readonly_data_section;
163 static GTY(()) section *som_one_only_readonly_data_section;
164 static GTY(()) section *som_one_only_data_section;
166 /* Save the operands last given to a compare for use when we
167 generate a scc or bcc insn. */
168 rtx hppa_compare_op0, hppa_compare_op1;
169 enum cmp_type hppa_branch_type;
171 /* Which cpu we are scheduling for. */
172 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
174 /* The UNIX standard to use for predefines and linking. */
175 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
177 /* Counts for the number of callee-saved general and floating point
178 registers which were saved by the current function's prologue. */
179 static int gr_saved, fr_saved;
181 /* Boolean indicating whether the return pointer was saved by the
182 current function's prologue. */
183 static bool rp_saved;
185 static rtx find_addr_reg (rtx);
187 /* Keep track of the number of bytes we have output in the CODE subspace
188 during this compilation so we'll know when to emit inline long-calls. */
189 unsigned long total_code_bytes;
191 /* The last address of the previous function plus the number of bytes in
192 associated thunks that have been output. This is used to determine if
193 a thunk can use an IA-relative branch to reach its target function. */
194 static int last_address;
196 /* Variables to handle plabels that we discover are necessary at assembly
197 output time. They are output after the current function. */
198 struct deferred_plabel GTY(())
203 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
205 static size_t n_deferred_plabels = 0;
208 /* Initialize the GCC target structure. */
210 #undef TARGET_ASM_ALIGNED_HI_OP
211 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
212 #undef TARGET_ASM_ALIGNED_SI_OP
213 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
214 #undef TARGET_ASM_ALIGNED_DI_OP
215 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
216 #undef TARGET_ASM_UNALIGNED_HI_OP
217 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
218 #undef TARGET_ASM_UNALIGNED_SI_OP
219 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
220 #undef TARGET_ASM_UNALIGNED_DI_OP
221 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
222 #undef TARGET_ASM_INTEGER
223 #define TARGET_ASM_INTEGER pa_assemble_integer
225 #undef TARGET_ASM_FUNCTION_PROLOGUE
226 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
227 #undef TARGET_ASM_FUNCTION_EPILOGUE
228 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
230 #undef TARGET_SCHED_ADJUST_COST
231 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
232 #undef TARGET_SCHED_ADJUST_PRIORITY
233 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
234 #undef TARGET_SCHED_ISSUE_RATE
235 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
237 #undef TARGET_ENCODE_SECTION_INFO
238 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
239 #undef TARGET_STRIP_NAME_ENCODING
240 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
242 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
243 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
245 #undef TARGET_COMMUTATIVE_P
246 #define TARGET_COMMUTATIVE_P pa_commutative_p
248 #undef TARGET_ASM_OUTPUT_MI_THUNK
249 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
250 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
251 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
253 #undef TARGET_ASM_FILE_END
254 #ifdef ASM_OUTPUT_EXTERNAL_REAL
255 #define TARGET_ASM_FILE_END pa_hpux_file_end
257 #define TARGET_ASM_FILE_END output_deferred_plabels
260 #if !defined(USE_COLLECT2)
261 #undef TARGET_ASM_CONSTRUCTOR
262 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
263 #undef TARGET_ASM_DESTRUCTOR
264 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
267 #undef TARGET_DEFAULT_TARGET_FLAGS
268 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
269 #undef TARGET_HANDLE_OPTION
270 #define TARGET_HANDLE_OPTION pa_handle_option
272 #undef TARGET_INIT_BUILTINS
273 #define TARGET_INIT_BUILTINS pa_init_builtins
275 #undef TARGET_RTX_COSTS
276 #define TARGET_RTX_COSTS hppa_rtx_costs
277 #undef TARGET_ADDRESS_COST
278 #define TARGET_ADDRESS_COST hppa_address_cost
280 #undef TARGET_MACHINE_DEPENDENT_REORG
281 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
283 #ifdef HPUX_LONG_DOUBLE_LIBRARY
284 #undef TARGET_INIT_LIBFUNCS
285 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
288 #undef TARGET_PROMOTE_FUNCTION_RETURN
289 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_const_tree_true
290 #undef TARGET_PROMOTE_PROTOTYPES
291 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
293 #undef TARGET_STRUCT_VALUE_RTX
294 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
295 #undef TARGET_RETURN_IN_MEMORY
296 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
297 #undef TARGET_MUST_PASS_IN_STACK
298 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
299 #undef TARGET_PASS_BY_REFERENCE
300 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
301 #undef TARGET_CALLEE_COPIES
302 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
303 #undef TARGET_ARG_PARTIAL_BYTES
304 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
306 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
307 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
308 #undef TARGET_EXPAND_BUILTIN_VA_START
309 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
310 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
311 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
313 #undef TARGET_SCALAR_MODE_SUPPORTED_P
314 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
316 #undef TARGET_CANNOT_FORCE_CONST_MEM
317 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
319 #undef TARGET_SECONDARY_RELOAD
320 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
322 #undef TARGET_EXTRA_LIVE_ON_ENTRY
323 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
325 struct gcc_target targetm = TARGET_INITIALIZER;
327 /* Parse the -mfixed-range= option string. */
330 fix_range (const char *const_str)
333 char *str, *dash, *comma;
335 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
336 REG2 are either register names or register numbers. The effect
337 of this option is to mark the registers in the range from REG1 to
338 REG2 as ``fixed'' so they won't be used by the compiler. This is
339 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
341 i = strlen (const_str);
342 str = (char *) alloca (i + 1);
343 memcpy (str, const_str, i + 1);
347 dash = strchr (str, '-');
350 warning (0, "value of -mfixed-range must have form REG1-REG2");
355 comma = strchr (dash + 1, ',');
359 first = decode_reg_name (str);
362 warning (0, "unknown register name: %s", str);
366 last = decode_reg_name (dash + 1);
369 warning (0, "unknown register name: %s", dash + 1);
377 warning (0, "%s-%s is an empty range", str, dash + 1);
381 for (i = first; i <= last; ++i)
382 fixed_regs[i] = call_used_regs[i] = 1;
391 /* Check if all floating point registers have been fixed. */
392 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
397 target_flags |= MASK_DISABLE_FPREGS;
400 /* Implement TARGET_HANDLE_OPTION. */
403 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
408 case OPT_mpa_risc_1_0:
410 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
414 case OPT_mpa_risc_1_1:
416 target_flags &= ~MASK_PA_20;
417 target_flags |= MASK_PA_11;
420 case OPT_mpa_risc_2_0:
422 target_flags |= MASK_PA_11 | MASK_PA_20;
426 if (strcmp (arg, "8000") == 0)
427 pa_cpu = PROCESSOR_8000;
428 else if (strcmp (arg, "7100") == 0)
429 pa_cpu = PROCESSOR_7100;
430 else if (strcmp (arg, "700") == 0)
431 pa_cpu = PROCESSOR_700;
432 else if (strcmp (arg, "7100LC") == 0)
433 pa_cpu = PROCESSOR_7100LC;
434 else if (strcmp (arg, "7200") == 0)
435 pa_cpu = PROCESSOR_7200;
436 else if (strcmp (arg, "7300") == 0)
437 pa_cpu = PROCESSOR_7300;
442 case OPT_mfixed_range_:
452 #if TARGET_HPUX_10_10
458 #if TARGET_HPUX_11_11
470 override_options (void)
472 /* Unconditional branches in the delay slot are not compatible with dwarf2
473 call frame information. There is no benefit in using this optimization
474 on PA8000 and later processors. */
475 if (pa_cpu >= PROCESSOR_8000
476 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
477 || flag_unwind_tables)
478 target_flags &= ~MASK_JUMP_IN_DELAY;
480 if (flag_pic && TARGET_PORTABLE_RUNTIME)
482 warning (0, "PIC code generation is not supported in the portable runtime model");
485 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
487 warning (0, "PIC code generation is not compatible with fast indirect calls");
490 if (! TARGET_GAS && write_symbols != NO_DEBUG)
492 warning (0, "-g is only supported when using GAS on this processor,");
493 warning (0, "-g option disabled");
494 write_symbols = NO_DEBUG;
497 /* We only support the "big PIC" model now. And we always generate PIC
498 code when in 64bit mode. */
499 if (flag_pic == 1 || TARGET_64BIT)
502 /* We can't guarantee that .dword is available for 32-bit targets. */
503 if (UNITS_PER_WORD == 4)
504 targetm.asm_out.aligned_op.di = NULL;
506 /* The unaligned ops are only available when using GAS. */
509 targetm.asm_out.unaligned_op.hi = NULL;
510 targetm.asm_out.unaligned_op.si = NULL;
511 targetm.asm_out.unaligned_op.di = NULL;
514 init_machine_status = pa_init_machine_status;
518 pa_init_builtins (void)
520 #ifdef DONT_HAVE_FPUTC_UNLOCKED
521 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
522 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
523 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
524 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
527 if (built_in_decls [BUILT_IN_FINITE])
528 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
529 if (built_in_decls [BUILT_IN_FINITEF])
530 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
534 /* Function to init struct machine_function.
535 This will be called, via a pointer variable,
536 from push_function_context. */
538 static struct machine_function *
539 pa_init_machine_status (void)
541 return ggc_alloc_cleared (sizeof (machine_function));
544 /* If FROM is a probable pointer register, mark TO as a probable
545 pointer register with the same pointer alignment as FROM. */
548 copy_reg_pointer (rtx to, rtx from)
550 if (REG_POINTER (from))
551 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
554 /* Return 1 if X contains a symbolic expression. We know these
555 expressions will have one of a few well defined forms, so
556 we need only check those forms. */
558 symbolic_expression_p (rtx x)
561 /* Strip off any HIGH. */
562 if (GET_CODE (x) == HIGH)
565 return (symbolic_operand (x, VOIDmode));
568 /* Accept any constant that can be moved in one instruction into a
571 cint_ok_for_move (HOST_WIDE_INT ival)
573 /* OK if ldo, ldil, or zdepi, can be used. */
574 return (VAL_14_BITS_P (ival)
575 || ldil_cint_p (ival)
576 || zdepi_cint_p (ival));
579 /* Return truth value of whether OP can be used as an operand in a
582 adddi3_operand (rtx op, enum machine_mode mode)
584 return (register_operand (op, mode)
585 || (GET_CODE (op) == CONST_INT
586 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
589 /* True iff the operand OP can be used as the destination operand of
590 an integer store. This also implies the operand could be used as
591 the source operand of an integer load. Symbolic, lo_sum and indexed
592 memory operands are not allowed. We accept reloading pseudos and
593 other memory operands. */
595 integer_store_memory_operand (rtx op, enum machine_mode mode)
597 return ((reload_in_progress
599 && REGNO (op) >= FIRST_PSEUDO_REGISTER
600 && reg_renumber [REGNO (op)] < 0)
601 || (GET_CODE (op) == MEM
602 && (reload_in_progress || memory_address_p (mode, XEXP (op, 0)))
603 && !symbolic_memory_operand (op, VOIDmode)
604 && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))
605 && !IS_INDEX_ADDR_P (XEXP (op, 0))));
608 /* True iff ldil can be used to load this CONST_INT. The least
609 significant 11 bits of the value must be zero and the value must
610 not change sign when extended from 32 to 64 bits. */
612 ldil_cint_p (HOST_WIDE_INT ival)
614 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
616 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
619 /* True iff zdepi can be used to generate this CONST_INT.
620 zdepi first sign extends a 5-bit signed number to a given field
621 length, then places this field anywhere in a zero. */
623 zdepi_cint_p (unsigned HOST_WIDE_INT x)
625 unsigned HOST_WIDE_INT lsb_mask, t;
627 /* This might not be obvious, but it's at least fast.
628 This function is critical; we don't have the time loops would take. */
630 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
631 /* Return true iff t is a power of two. */
632 return ((t & (t - 1)) == 0);
635 /* True iff depi or extru can be used to compute (reg & mask).
636 Accept bit pattern like these:
641 and_mask_p (unsigned HOST_WIDE_INT mask)
644 mask += mask & -mask;
645 return (mask & (mask - 1)) == 0;
648 /* True iff depi can be used to compute (reg | MASK). */
650 ior_mask_p (unsigned HOST_WIDE_INT mask)
652 mask += mask & -mask;
653 return (mask & (mask - 1)) == 0;
656 /* Legitimize PIC addresses. If the address is already
657 position-independent, we return ORIG. Newly generated
658 position-independent addresses go to REG. If we need more
659 than one register, we lose. */
662 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
666 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
668 /* Labels need special handling. */
669 if (pic_label_operand (orig, mode))
673 /* We do not want to go through the movXX expanders here since that
674 would create recursion.
676 Nor do we really want to call a generator for a named pattern
677 since that requires multiple patterns if we want to support
680 So instead we just emit the raw set, which avoids the movXX
681 expanders completely. */
682 mark_reg_pointer (reg, BITS_PER_UNIT);
683 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
685 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
686 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
688 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
689 and update LABEL_NUSES because this is not done automatically. */
690 if (reload_in_progress || reload_completed)
692 /* Extract LABEL_REF. */
693 if (GET_CODE (orig) == CONST)
694 orig = XEXP (XEXP (orig, 0), 0);
695 /* Extract CODE_LABEL. */
696 orig = XEXP (orig, 0);
697 REG_NOTES (insn) = gen_rtx_INSN_LIST (REG_LABEL_OPERAND, orig,
699 LABEL_NUSES (orig)++;
701 crtl->uses_pic_offset_table = 1;
704 if (GET_CODE (orig) == SYMBOL_REF)
710 /* Before reload, allocate a temporary register for the intermediate
711 result. This allows the sequence to be deleted when the final
712 result is unused and the insns are trivially dead. */
713 tmp_reg = ((reload_in_progress || reload_completed)
714 ? reg : gen_reg_rtx (Pmode));
716 if (function_label_operand (orig, mode))
718 /* Force function label into memory. */
719 orig = XEXP (force_const_mem (mode, orig), 0);
720 /* Load plabel address from DLT. */
721 emit_move_insn (tmp_reg,
722 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
723 gen_rtx_HIGH (word_mode, orig)));
725 = gen_const_mem (Pmode,
726 gen_rtx_LO_SUM (Pmode, tmp_reg,
727 gen_rtx_UNSPEC (Pmode,
730 emit_move_insn (reg, pic_ref);
731 /* Now load address of function descriptor. */
732 pic_ref = gen_rtx_MEM (Pmode, reg);
736 /* Load symbol reference from DLT. */
737 emit_move_insn (tmp_reg,
738 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
739 gen_rtx_HIGH (word_mode, orig)));
741 = gen_const_mem (Pmode,
742 gen_rtx_LO_SUM (Pmode, tmp_reg,
743 gen_rtx_UNSPEC (Pmode,
748 crtl->uses_pic_offset_table = 1;
749 mark_reg_pointer (reg, BITS_PER_UNIT);
750 insn = emit_move_insn (reg, pic_ref);
752 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
753 set_unique_reg_note (insn, REG_EQUAL, orig);
757 else if (GET_CODE (orig) == CONST)
761 if (GET_CODE (XEXP (orig, 0)) == PLUS
762 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
766 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
768 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
769 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
770 base == reg ? 0 : reg);
772 if (GET_CODE (orig) == CONST_INT)
774 if (INT_14_BITS (orig))
775 return plus_constant (base, INTVAL (orig));
776 orig = force_reg (Pmode, orig);
778 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
779 /* Likewise, should we set special REG_NOTEs here? */
785 static GTY(()) rtx gen_tls_tga;
788 gen_tls_get_addr (void)
791 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
796 hppa_tls_call (rtx arg)
800 ret = gen_reg_rtx (Pmode);
801 emit_library_call_value (gen_tls_get_addr (), ret,
802 LCT_CONST, Pmode, 1, arg, Pmode);
808 legitimize_tls_address (rtx addr)
810 rtx ret, insn, tmp, t1, t2, tp;
811 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
815 case TLS_MODEL_GLOBAL_DYNAMIC:
816 tmp = gen_reg_rtx (Pmode);
818 emit_insn (gen_tgd_load_pic (tmp, addr));
820 emit_insn (gen_tgd_load (tmp, addr));
821 ret = hppa_tls_call (tmp);
824 case TLS_MODEL_LOCAL_DYNAMIC:
825 ret = gen_reg_rtx (Pmode);
826 tmp = gen_reg_rtx (Pmode);
829 emit_insn (gen_tld_load_pic (tmp, addr));
831 emit_insn (gen_tld_load (tmp, addr));
832 t1 = hppa_tls_call (tmp);
835 t2 = gen_reg_rtx (Pmode);
836 emit_libcall_block (insn, t2, t1,
837 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
839 emit_insn (gen_tld_offset_load (ret, addr, t2));
842 case TLS_MODEL_INITIAL_EXEC:
843 tp = gen_reg_rtx (Pmode);
844 tmp = gen_reg_rtx (Pmode);
845 ret = gen_reg_rtx (Pmode);
846 emit_insn (gen_tp_load (tp));
848 emit_insn (gen_tie_load_pic (tmp, addr));
850 emit_insn (gen_tie_load (tmp, addr));
851 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
854 case TLS_MODEL_LOCAL_EXEC:
855 tp = gen_reg_rtx (Pmode);
856 ret = gen_reg_rtx (Pmode);
857 emit_insn (gen_tp_load (tp));
858 emit_insn (gen_tle_load (ret, addr, tp));
868 /* Try machine-dependent ways of modifying an illegitimate address
869 to be legitimate. If we find one, return the new, valid address.
870 This macro is used in only one place: `memory_address' in explow.c.
872 OLDX is the address as it was before break_out_memory_refs was called.
873 In some cases it is useful to look at this to decide what needs to be done.
875 MODE and WIN are passed so that this macro can use
876 GO_IF_LEGITIMATE_ADDRESS.
878 It is always safe for this macro to do nothing. It exists to recognize
879 opportunities to optimize the output.
881 For the PA, transform:
883 memory(X + <large int>)
887 if (<large int> & mask) >= 16
888 Y = (<large int> & ~mask) + mask + 1 Round up.
890 Y = (<large int> & ~mask) Round down.
892 memory (Z + (<large int> - Y));
894 This is for CSE to find several similar references, and only use one Z.
896 X can either be a SYMBOL_REF or REG, but because combine cannot
897 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
898 D will not fit in 14 bits.
900 MODE_FLOAT references allow displacements which fit in 5 bits, so use
903 MODE_INT references allow displacements which fit in 14 bits, so use
906 This relies on the fact that most mode MODE_FLOAT references will use FP
907 registers and most mode MODE_INT references will use integer registers.
908 (In the rare case of an FP register used in an integer MODE, we depend
909 on secondary reloads to clean things up.)
912 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
913 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
914 addressing modes to be used).
916 Put X and Z into registers. Then put the entire expression into
920 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
921 enum machine_mode mode)
925 /* We need to canonicalize the order of operands in unscaled indexed
926 addresses since the code that checks if an address is valid doesn't
927 always try both orders. */
928 if (!TARGET_NO_SPACE_REGS
929 && GET_CODE (x) == PLUS
930 && GET_MODE (x) == Pmode
931 && REG_P (XEXP (x, 0))
932 && REG_P (XEXP (x, 1))
933 && REG_POINTER (XEXP (x, 0))
934 && !REG_POINTER (XEXP (x, 1)))
935 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
937 if (PA_SYMBOL_REF_TLS_P (x))
938 return legitimize_tls_address (x);
940 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
942 /* Strip off CONST. */
943 if (GET_CODE (x) == CONST)
946 /* Special case. Get the SYMBOL_REF into a register and use indexing.
947 That should always be safe. */
948 if (GET_CODE (x) == PLUS
949 && GET_CODE (XEXP (x, 0)) == REG
950 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
952 rtx reg = force_reg (Pmode, XEXP (x, 1));
953 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
956 /* Note we must reject symbols which represent function addresses
957 since the assembler/linker can't handle arithmetic on plabels. */
958 if (GET_CODE (x) == PLUS
959 && GET_CODE (XEXP (x, 1)) == CONST_INT
960 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
961 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
962 || GET_CODE (XEXP (x, 0)) == REG))
964 rtx int_part, ptr_reg;
966 int offset = INTVAL (XEXP (x, 1));
969 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
970 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
972 /* Choose which way to round the offset. Round up if we
973 are >= halfway to the next boundary. */
974 if ((offset & mask) >= ((mask + 1) / 2))
975 newoffset = (offset & ~ mask) + mask + 1;
977 newoffset = (offset & ~ mask);
979 /* If the newoffset will not fit in 14 bits (ldo), then
980 handling this would take 4 or 5 instructions (2 to load
981 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
982 add the new offset and the SYMBOL_REF.) Combine can
983 not handle 4->2 or 5->2 combinations, so do not create
985 if (! VAL_14_BITS_P (newoffset)
986 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
988 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
991 gen_rtx_HIGH (Pmode, const_part));
994 gen_rtx_LO_SUM (Pmode,
995 tmp_reg, const_part));
999 if (! VAL_14_BITS_P (newoffset))
1000 int_part = force_reg (Pmode, GEN_INT (newoffset));
1002 int_part = GEN_INT (newoffset);
1004 ptr_reg = force_reg (Pmode,
1005 gen_rtx_PLUS (Pmode,
1006 force_reg (Pmode, XEXP (x, 0)),
1009 return plus_constant (ptr_reg, offset - newoffset);
1012 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1014 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1015 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1016 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1017 && (OBJECT_P (XEXP (x, 1))
1018 || GET_CODE (XEXP (x, 1)) == SUBREG)
1019 && GET_CODE (XEXP (x, 1)) != CONST)
1021 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1025 if (GET_CODE (reg1) != REG)
1026 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1028 reg2 = XEXP (XEXP (x, 0), 0);
1029 if (GET_CODE (reg2) != REG)
1030 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1032 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1033 gen_rtx_MULT (Pmode,
1039 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1041 Only do so for floating point modes since this is more speculative
1042 and we lose if it's an integer store. */
1043 if (GET_CODE (x) == PLUS
1044 && GET_CODE (XEXP (x, 0)) == PLUS
1045 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1046 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1047 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1048 && (mode == SFmode || mode == DFmode))
1051 /* First, try and figure out what to use as a base register. */
1052 rtx reg1, reg2, base, idx, orig_base;
1054 reg1 = XEXP (XEXP (x, 0), 1);
1059 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1060 then emit_move_sequence will turn on REG_POINTER so we'll know
1061 it's a base register below. */
1062 if (GET_CODE (reg1) != REG)
1063 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1065 if (GET_CODE (reg2) != REG)
1066 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1068 /* Figure out what the base and index are. */
1070 if (GET_CODE (reg1) == REG
1071 && REG_POINTER (reg1))
1074 orig_base = XEXP (XEXP (x, 0), 1);
1075 idx = gen_rtx_PLUS (Pmode,
1076 gen_rtx_MULT (Pmode,
1077 XEXP (XEXP (XEXP (x, 0), 0), 0),
1078 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1081 else if (GET_CODE (reg2) == REG
1082 && REG_POINTER (reg2))
1085 orig_base = XEXP (x, 1);
1092 /* If the index adds a large constant, try to scale the
1093 constant so that it can be loaded with only one insn. */
1094 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1095 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1096 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1097 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1099 /* Divide the CONST_INT by the scale factor, then add it to A. */
1100 int val = INTVAL (XEXP (idx, 1));
1102 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1103 reg1 = XEXP (XEXP (idx, 0), 0);
1104 if (GET_CODE (reg1) != REG)
1105 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1107 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1109 /* We can now generate a simple scaled indexed address. */
1112 (Pmode, gen_rtx_PLUS (Pmode,
1113 gen_rtx_MULT (Pmode, reg1,
1114 XEXP (XEXP (idx, 0), 1)),
1118 /* If B + C is still a valid base register, then add them. */
1119 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1120 && INTVAL (XEXP (idx, 1)) <= 4096
1121 && INTVAL (XEXP (idx, 1)) >= -4096)
1123 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1126 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1128 reg2 = XEXP (XEXP (idx, 0), 0);
1129 if (GET_CODE (reg2) != CONST_INT)
1130 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1132 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1133 gen_rtx_MULT (Pmode,
1139 /* Get the index into a register, then add the base + index and
1140 return a register holding the result. */
1142 /* First get A into a register. */
1143 reg1 = XEXP (XEXP (idx, 0), 0);
1144 if (GET_CODE (reg1) != REG)
1145 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1147 /* And get B into a register. */
1148 reg2 = XEXP (idx, 1);
1149 if (GET_CODE (reg2) != REG)
1150 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1152 reg1 = force_reg (Pmode,
1153 gen_rtx_PLUS (Pmode,
1154 gen_rtx_MULT (Pmode, reg1,
1155 XEXP (XEXP (idx, 0), 1)),
1158 /* Add the result to our base register and return. */
1159 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1163 /* Uh-oh. We might have an address for x[n-100000]. This needs
1164 special handling to avoid creating an indexed memory address
1165 with x-100000 as the base.
1167 If the constant part is small enough, then it's still safe because
1168 there is a guard page at the beginning and end of the data segment.
1170 Scaled references are common enough that we want to try and rearrange the
1171 terms so that we can use indexing for these addresses too. Only
1172 do the optimization for floatint point modes. */
1174 if (GET_CODE (x) == PLUS
1175 && symbolic_expression_p (XEXP (x, 1)))
1177 /* Ugly. We modify things here so that the address offset specified
1178 by the index expression is computed first, then added to x to form
1179 the entire address. */
1181 rtx regx1, regx2, regy1, regy2, y;
1183 /* Strip off any CONST. */
1185 if (GET_CODE (y) == CONST)
1188 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1190 /* See if this looks like
1191 (plus (mult (reg) (shadd_const))
1192 (const (plus (symbol_ref) (const_int))))
1194 Where const_int is small. In that case the const
1195 expression is a valid pointer for indexing.
1197 If const_int is big, but can be divided evenly by shadd_const
1198 and added to (reg). This allows more scaled indexed addresses. */
1199 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1200 && GET_CODE (XEXP (x, 0)) == MULT
1201 && GET_CODE (XEXP (y, 1)) == CONST_INT
1202 && INTVAL (XEXP (y, 1)) >= -4096
1203 && INTVAL (XEXP (y, 1)) <= 4095
1204 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1205 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1207 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1211 if (GET_CODE (reg1) != REG)
1212 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1214 reg2 = XEXP (XEXP (x, 0), 0);
1215 if (GET_CODE (reg2) != REG)
1216 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1218 return force_reg (Pmode,
1219 gen_rtx_PLUS (Pmode,
1220 gen_rtx_MULT (Pmode,
1225 else if ((mode == DFmode || mode == SFmode)
1226 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1227 && GET_CODE (XEXP (x, 0)) == MULT
1228 && GET_CODE (XEXP (y, 1)) == CONST_INT
1229 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1230 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1231 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1234 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1235 / INTVAL (XEXP (XEXP (x, 0), 1))));
1236 regx2 = XEXP (XEXP (x, 0), 0);
1237 if (GET_CODE (regx2) != REG)
1238 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1239 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1243 gen_rtx_PLUS (Pmode,
1244 gen_rtx_MULT (Pmode, regx2,
1245 XEXP (XEXP (x, 0), 1)),
1246 force_reg (Pmode, XEXP (y, 0))));
1248 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1249 && INTVAL (XEXP (y, 1)) >= -4096
1250 && INTVAL (XEXP (y, 1)) <= 4095)
1252 /* This is safe because of the guard page at the
1253 beginning and end of the data space. Just
1254 return the original address. */
1259 /* Doesn't look like one we can optimize. */
1260 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1261 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1262 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1263 regx1 = force_reg (Pmode,
1264 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1266 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1274 /* For the HPPA, REG and REG+CONST is cost 0
1275 and addresses involving symbolic constants are cost 2.
1277 PIC addresses are very expensive.
1279 It is no coincidence that this has the same structure
1280 as GO_IF_LEGITIMATE_ADDRESS. */
1283 hppa_address_cost (rtx X)
1285 switch (GET_CODE (X))
1298 /* Compute a (partial) cost for rtx X. Return true if the complete
1299 cost has been computed, and false if subexpressions should be
1300 scanned. In either case, *TOTAL contains the cost result. */
1303 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1308 if (INTVAL (x) == 0)
1310 else if (INT_14_BITS (x))
1327 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1328 && outer_code != SET)
1335 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1336 *total = COSTS_N_INSNS (3);
1337 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1338 *total = COSTS_N_INSNS (8);
1340 *total = COSTS_N_INSNS (20);
1344 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1346 *total = COSTS_N_INSNS (14);
1354 *total = COSTS_N_INSNS (60);
1357 case PLUS: /* this includes shNadd insns */
1359 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1360 *total = COSTS_N_INSNS (3);
1362 *total = COSTS_N_INSNS (1);
1368 *total = COSTS_N_INSNS (1);
1376 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1377 new rtx with the correct mode. */
1379 force_mode (enum machine_mode mode, rtx orig)
1381 if (mode == GET_MODE (orig))
1384 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1386 return gen_rtx_REG (mode, REGNO (orig));
1389 /* Return 1 if *X is a thread-local symbol. */
1392 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1394 return PA_SYMBOL_REF_TLS_P (*x);
1397 /* Return 1 if X contains a thread-local symbol. */
1400 pa_tls_referenced_p (rtx x)
1402 if (!TARGET_HAVE_TLS)
1405 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1408 /* Emit insns to move operands[1] into operands[0].
1410 Return 1 if we have written out everything that needs to be done to
1411 do the move. Otherwise, return 0 and the caller will emit the move
1414 Note SCRATCH_REG may not be in the proper mode depending on how it
1415 will be used. This routine is responsible for creating a new copy
1416 of SCRATCH_REG in the proper mode. */
1419 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1421 register rtx operand0 = operands[0];
1422 register rtx operand1 = operands[1];
1425 /* We can only handle indexed addresses in the destination operand
1426 of floating point stores. Thus, we need to break out indexed
1427 addresses from the destination operand. */
1428 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1430 gcc_assert (can_create_pseudo_p ());
1432 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1433 operand0 = replace_equiv_address (operand0, tem);
1436 /* On targets with non-equivalent space registers, break out unscaled
1437 indexed addresses from the source operand before the final CSE.
1438 We have to do this because the REG_POINTER flag is not correctly
1439 carried through various optimization passes and CSE may substitute
1440 a pseudo without the pointer set for one with the pointer set. As
1441 a result, we loose various opportunities to create insns with
1442 unscaled indexed addresses. */
1443 if (!TARGET_NO_SPACE_REGS
1444 && !cse_not_expected
1445 && GET_CODE (operand1) == MEM
1446 && GET_CODE (XEXP (operand1, 0)) == PLUS
1447 && REG_P (XEXP (XEXP (operand1, 0), 0))
1448 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1450 = replace_equiv_address (operand1,
1451 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1454 && reload_in_progress && GET_CODE (operand0) == REG
1455 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1456 operand0 = reg_equiv_mem[REGNO (operand0)];
1457 else if (scratch_reg
1458 && reload_in_progress && GET_CODE (operand0) == SUBREG
1459 && GET_CODE (SUBREG_REG (operand0)) == REG
1460 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1462 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1463 the code which tracks sets/uses for delete_output_reload. */
1464 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1465 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1466 SUBREG_BYTE (operand0));
1467 operand0 = alter_subreg (&temp);
1471 && reload_in_progress && GET_CODE (operand1) == REG
1472 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1473 operand1 = reg_equiv_mem[REGNO (operand1)];
1474 else if (scratch_reg
1475 && reload_in_progress && GET_CODE (operand1) == SUBREG
1476 && GET_CODE (SUBREG_REG (operand1)) == REG
1477 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1479 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1480 the code which tracks sets/uses for delete_output_reload. */
1481 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1482 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1483 SUBREG_BYTE (operand1));
1484 operand1 = alter_subreg (&temp);
1487 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1488 && ((tem = find_replacement (&XEXP (operand0, 0)))
1489 != XEXP (operand0, 0)))
1490 operand0 = replace_equiv_address (operand0, tem);
1492 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1493 && ((tem = find_replacement (&XEXP (operand1, 0)))
1494 != XEXP (operand1, 0)))
1495 operand1 = replace_equiv_address (operand1, tem);
1497 /* Handle secondary reloads for loads/stores of FP registers from
1498 REG+D addresses where D does not fit in 5 or 14 bits, including
1499 (subreg (mem (addr))) cases. */
1501 && fp_reg_operand (operand0, mode)
1502 && ((GET_CODE (operand1) == MEM
1503 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1504 XEXP (operand1, 0)))
1505 || ((GET_CODE (operand1) == SUBREG
1506 && GET_CODE (XEXP (operand1, 0)) == MEM
1507 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1509 XEXP (XEXP (operand1, 0), 0))))))
1511 if (GET_CODE (operand1) == SUBREG)
1512 operand1 = XEXP (operand1, 0);
1514 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1515 it in WORD_MODE regardless of what mode it was originally given
1517 scratch_reg = force_mode (word_mode, scratch_reg);
1519 /* D might not fit in 14 bits either; for such cases load D into
1521 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1523 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1524 emit_move_insn (scratch_reg,
1525 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1527 XEXP (XEXP (operand1, 0), 0),
1531 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1532 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1533 replace_equiv_address (operand1, scratch_reg)));
1536 else if (scratch_reg
1537 && fp_reg_operand (operand1, mode)
1538 && ((GET_CODE (operand0) == MEM
1539 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1541 XEXP (operand0, 0)))
1542 || ((GET_CODE (operand0) == SUBREG)
1543 && GET_CODE (XEXP (operand0, 0)) == MEM
1544 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1546 XEXP (XEXP (operand0, 0), 0)))))
1548 if (GET_CODE (operand0) == SUBREG)
1549 operand0 = XEXP (operand0, 0);
1551 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1552 it in WORD_MODE regardless of what mode it was originally given
1554 scratch_reg = force_mode (word_mode, scratch_reg);
1556 /* D might not fit in 14 bits either; for such cases load D into
1558 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1560 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1561 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1564 XEXP (XEXP (operand0, 0),
1569 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1570 emit_insn (gen_rtx_SET (VOIDmode,
1571 replace_equiv_address (operand0, scratch_reg),
1575 /* Handle secondary reloads for loads of FP registers from constant
1576 expressions by forcing the constant into memory.
1578 Use scratch_reg to hold the address of the memory location.
1580 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1581 NO_REGS when presented with a const_int and a register class
1582 containing only FP registers. Doing so unfortunately creates
1583 more problems than it solves. Fix this for 2.5. */
1584 else if (scratch_reg
1585 && CONSTANT_P (operand1)
1586 && fp_reg_operand (operand0, mode))
1588 rtx const_mem, xoperands[2];
1590 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1591 it in WORD_MODE regardless of what mode it was originally given
1593 scratch_reg = force_mode (word_mode, scratch_reg);
1595 /* Force the constant into memory and put the address of the
1596 memory location into scratch_reg. */
1597 const_mem = force_const_mem (mode, operand1);
1598 xoperands[0] = scratch_reg;
1599 xoperands[1] = XEXP (const_mem, 0);
1600 emit_move_sequence (xoperands, Pmode, 0);
1602 /* Now load the destination register. */
1603 emit_insn (gen_rtx_SET (mode, operand0,
1604 replace_equiv_address (const_mem, scratch_reg)));
1607 /* Handle secondary reloads for SAR. These occur when trying to load
1608 the SAR from memory, FP register, or with a constant. */
1609 else if (scratch_reg
1610 && GET_CODE (operand0) == REG
1611 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1612 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1613 && (GET_CODE (operand1) == MEM
1614 || GET_CODE (operand1) == CONST_INT
1615 || (GET_CODE (operand1) == REG
1616 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1618 /* D might not fit in 14 bits either; for such cases load D into
1620 if (GET_CODE (operand1) == MEM
1621 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1623 /* We are reloading the address into the scratch register, so we
1624 want to make sure the scratch register is a full register. */
1625 scratch_reg = force_mode (word_mode, scratch_reg);
1627 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1628 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1631 XEXP (XEXP (operand1, 0),
1635 /* Now we are going to load the scratch register from memory,
1636 we want to load it in the same width as the original MEM,
1637 which must be the same as the width of the ultimate destination,
1639 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1641 emit_move_insn (scratch_reg,
1642 replace_equiv_address (operand1, scratch_reg));
1646 /* We want to load the scratch register using the same mode as
1647 the ultimate destination. */
1648 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1650 emit_move_insn (scratch_reg, operand1);
1653 /* And emit the insn to set the ultimate destination. We know that
1654 the scratch register has the same mode as the destination at this
1656 emit_move_insn (operand0, scratch_reg);
1659 /* Handle the most common case: storing into a register. */
1660 else if (register_operand (operand0, mode))
1662 if (register_operand (operand1, mode)
1663 || (GET_CODE (operand1) == CONST_INT
1664 && cint_ok_for_move (INTVAL (operand1)))
1665 || (operand1 == CONST0_RTX (mode))
1666 || (GET_CODE (operand1) == HIGH
1667 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1668 /* Only `general_operands' can come here, so MEM is ok. */
1669 || GET_CODE (operand1) == MEM)
1671 /* Various sets are created during RTL generation which don't
1672 have the REG_POINTER flag correctly set. After the CSE pass,
1673 instruction recognition can fail if we don't consistently
1674 set this flag when performing register copies. This should
1675 also improve the opportunities for creating insns that use
1676 unscaled indexing. */
1677 if (REG_P (operand0) && REG_P (operand1))
1679 if (REG_POINTER (operand1)
1680 && !REG_POINTER (operand0)
1681 && !HARD_REGISTER_P (operand0))
1682 copy_reg_pointer (operand0, operand1);
1683 else if (REG_POINTER (operand0)
1684 && !REG_POINTER (operand1)
1685 && !HARD_REGISTER_P (operand1))
1686 copy_reg_pointer (operand1, operand0);
1689 /* When MEMs are broken out, the REG_POINTER flag doesn't
1690 get set. In some cases, we can set the REG_POINTER flag
1691 from the declaration for the MEM. */
1692 if (REG_P (operand0)
1693 && GET_CODE (operand1) == MEM
1694 && !REG_POINTER (operand0))
1696 tree decl = MEM_EXPR (operand1);
1698 /* Set the register pointer flag and register alignment
1699 if the declaration for this memory reference is a
1700 pointer type. Fortran indirect argument references
1703 && !(flag_argument_noalias > 1
1704 && TREE_CODE (decl) == INDIRECT_REF
1705 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1709 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1711 if (TREE_CODE (decl) == COMPONENT_REF)
1712 decl = TREE_OPERAND (decl, 1);
1714 type = TREE_TYPE (decl);
1715 if (TREE_CODE (type) == ARRAY_TYPE)
1716 type = get_inner_array_type (type);
1718 if (POINTER_TYPE_P (type))
1722 type = TREE_TYPE (type);
1723 /* Using TYPE_ALIGN_OK is rather conservative as
1724 only the ada frontend actually sets it. */
1725 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1727 mark_reg_pointer (operand0, align);
1732 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1736 else if (GET_CODE (operand0) == MEM)
1738 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1739 && !(reload_in_progress || reload_completed))
1741 rtx temp = gen_reg_rtx (DFmode);
1743 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1744 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1747 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1749 /* Run this case quickly. */
1750 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1753 if (! (reload_in_progress || reload_completed))
1755 operands[0] = validize_mem (operand0);
1756 operands[1] = operand1 = force_reg (mode, operand1);
1760 /* Simplify the source if we need to.
1761 Note we do have to handle function labels here, even though we do
1762 not consider them legitimate constants. Loop optimizations can
1763 call the emit_move_xxx with one as a source. */
1764 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1765 || function_label_operand (operand1, mode)
1766 || (GET_CODE (operand1) == HIGH
1767 && symbolic_operand (XEXP (operand1, 0), mode)))
1771 if (GET_CODE (operand1) == HIGH)
1774 operand1 = XEXP (operand1, 0);
1776 if (symbolic_operand (operand1, mode))
1778 /* Argh. The assembler and linker can't handle arithmetic
1781 So we force the plabel into memory, load operand0 from
1782 the memory location, then add in the constant part. */
1783 if ((GET_CODE (operand1) == CONST
1784 && GET_CODE (XEXP (operand1, 0)) == PLUS
1785 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1786 || function_label_operand (operand1, mode))
1788 rtx temp, const_part;
1790 /* Figure out what (if any) scratch register to use. */
1791 if (reload_in_progress || reload_completed)
1793 scratch_reg = scratch_reg ? scratch_reg : operand0;
1794 /* SCRATCH_REG will hold an address and maybe the actual
1795 data. We want it in WORD_MODE regardless of what mode it
1796 was originally given to us. */
1797 scratch_reg = force_mode (word_mode, scratch_reg);
1800 scratch_reg = gen_reg_rtx (Pmode);
1802 if (GET_CODE (operand1) == CONST)
1804 /* Save away the constant part of the expression. */
1805 const_part = XEXP (XEXP (operand1, 0), 1);
1806 gcc_assert (GET_CODE (const_part) == CONST_INT);
1808 /* Force the function label into memory. */
1809 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1813 /* No constant part. */
1814 const_part = NULL_RTX;
1816 /* Force the function label into memory. */
1817 temp = force_const_mem (mode, operand1);
1821 /* Get the address of the memory location. PIC-ify it if
1823 temp = XEXP (temp, 0);
1825 temp = legitimize_pic_address (temp, mode, scratch_reg);
1827 /* Put the address of the memory location into our destination
1830 emit_move_sequence (operands, mode, scratch_reg);
1832 /* Now load from the memory location into our destination
1834 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1835 emit_move_sequence (operands, mode, scratch_reg);
1837 /* And add back in the constant part. */
1838 if (const_part != NULL_RTX)
1839 expand_inc (operand0, const_part);
1848 if (reload_in_progress || reload_completed)
1850 temp = scratch_reg ? scratch_reg : operand0;
1851 /* TEMP will hold an address and maybe the actual
1852 data. We want it in WORD_MODE regardless of what mode it
1853 was originally given to us. */
1854 temp = force_mode (word_mode, temp);
1857 temp = gen_reg_rtx (Pmode);
1859 /* (const (plus (symbol) (const_int))) must be forced to
1860 memory during/after reload if the const_int will not fit
1862 if (GET_CODE (operand1) == CONST
1863 && GET_CODE (XEXP (operand1, 0)) == PLUS
1864 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1865 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1866 && (reload_completed || reload_in_progress)
1869 rtx const_mem = force_const_mem (mode, operand1);
1870 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1872 operands[1] = replace_equiv_address (const_mem, operands[1]);
1873 emit_move_sequence (operands, mode, temp);
1877 operands[1] = legitimize_pic_address (operand1, mode, temp);
1878 if (REG_P (operand0) && REG_P (operands[1]))
1879 copy_reg_pointer (operand0, operands[1]);
1880 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1883 /* On the HPPA, references to data space are supposed to use dp,
1884 register 27, but showing it in the RTL inhibits various cse
1885 and loop optimizations. */
1890 if (reload_in_progress || reload_completed)
1892 temp = scratch_reg ? scratch_reg : operand0;
1893 /* TEMP will hold an address and maybe the actual
1894 data. We want it in WORD_MODE regardless of what mode it
1895 was originally given to us. */
1896 temp = force_mode (word_mode, temp);
1899 temp = gen_reg_rtx (mode);
1901 /* Loading a SYMBOL_REF into a register makes that register
1902 safe to be used as the base in an indexed address.
1904 Don't mark hard registers though. That loses. */
1905 if (GET_CODE (operand0) == REG
1906 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1907 mark_reg_pointer (operand0, BITS_PER_UNIT);
1908 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1909 mark_reg_pointer (temp, BITS_PER_UNIT);
1912 set = gen_rtx_SET (mode, operand0, temp);
1914 set = gen_rtx_SET (VOIDmode,
1916 gen_rtx_LO_SUM (mode, temp, operand1));
1918 emit_insn (gen_rtx_SET (VOIDmode,
1920 gen_rtx_HIGH (mode, operand1)));
1926 else if (pa_tls_referenced_p (operand1))
1931 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1933 addend = XEXP (XEXP (tmp, 0), 1);
1934 tmp = XEXP (XEXP (tmp, 0), 0);
1937 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1938 tmp = legitimize_tls_address (tmp);
1941 tmp = gen_rtx_PLUS (mode, tmp, addend);
1942 tmp = force_operand (tmp, operands[0]);
1946 else if (GET_CODE (operand1) != CONST_INT
1947 || !cint_ok_for_move (INTVAL (operand1)))
1951 HOST_WIDE_INT value = 0;
1952 HOST_WIDE_INT insv = 0;
1955 if (GET_CODE (operand1) == CONST_INT)
1956 value = INTVAL (operand1);
1959 && GET_CODE (operand1) == CONST_INT
1960 && HOST_BITS_PER_WIDE_INT > 32
1961 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1965 /* Extract the low order 32 bits of the value and sign extend.
1966 If the new value is the same as the original value, we can
1967 can use the original value as-is. If the new value is
1968 different, we use it and insert the most-significant 32-bits
1969 of the original value into the final result. */
1970 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1971 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1974 #if HOST_BITS_PER_WIDE_INT > 32
1975 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1979 operand1 = GEN_INT (nval);
1983 if (reload_in_progress || reload_completed)
1984 temp = scratch_reg ? scratch_reg : operand0;
1986 temp = gen_reg_rtx (mode);
1988 /* We don't directly split DImode constants on 32-bit targets
1989 because PLUS uses an 11-bit immediate and the insn sequence
1990 generated is not as efficient as the one using HIGH/LO_SUM. */
1991 if (GET_CODE (operand1) == CONST_INT
1992 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
1993 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1996 /* Directly break constant into high and low parts. This
1997 provides better optimization opportunities because various
1998 passes recognize constants split with PLUS but not LO_SUM.
1999 We use a 14-bit signed low part except when the addition
2000 of 0x4000 to the high part might change the sign of the
2002 HOST_WIDE_INT low = value & 0x3fff;
2003 HOST_WIDE_INT high = value & ~ 0x3fff;
2007 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2015 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2016 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2020 emit_insn (gen_rtx_SET (VOIDmode, temp,
2021 gen_rtx_HIGH (mode, operand1)));
2022 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2025 insn = emit_move_insn (operands[0], operands[1]);
2027 /* Now insert the most significant 32 bits of the value
2028 into the register. When we don't have a second register
2029 available, it could take up to nine instructions to load
2030 a 64-bit integer constant. Prior to reload, we force
2031 constants that would take more than three instructions
2032 to load to the constant pool. During and after reload,
2033 we have to handle all possible values. */
2036 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2037 register and the value to be inserted is outside the
2038 range that can be loaded with three depdi instructions. */
2039 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2041 operand1 = GEN_INT (insv);
2043 emit_insn (gen_rtx_SET (VOIDmode, temp,
2044 gen_rtx_HIGH (mode, operand1)));
2045 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2046 emit_insn (gen_insv (operand0, GEN_INT (32),
2051 int len = 5, pos = 27;
2053 /* Insert the bits using the depdi instruction. */
2056 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2057 HOST_WIDE_INT sign = v5 < 0;
2059 /* Left extend the insertion. */
2060 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2061 while (pos > 0 && (insv & 1) == sign)
2063 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2068 emit_insn (gen_insv (operand0, GEN_INT (len),
2069 GEN_INT (pos), GEN_INT (v5)));
2071 len = pos > 0 && pos < 5 ? pos : 5;
2077 set_unique_reg_note (insn, REG_EQUAL, op1);
2082 /* Now have insn-emit do whatever it normally does. */
2086 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2087 it will need a link/runtime reloc). */
2090 reloc_needed (tree exp)
2094 switch (TREE_CODE (exp))
2099 case POINTER_PLUS_EXPR:
2102 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2103 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2108 case NON_LVALUE_EXPR:
2109 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2115 unsigned HOST_WIDE_INT ix;
2117 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2119 reloc |= reloc_needed (value);
2132 /* Does operand (which is a symbolic_operand) live in text space?
2133 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2137 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2139 if (GET_CODE (operand) == CONST)
2140 operand = XEXP (XEXP (operand, 0), 0);
2143 if (GET_CODE (operand) == SYMBOL_REF)
2144 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2148 if (GET_CODE (operand) == SYMBOL_REF)
2149 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2155 /* Return the best assembler insn template
2156 for moving operands[1] into operands[0] as a fullword. */
2158 singlemove_string (rtx *operands)
2160 HOST_WIDE_INT intval;
2162 if (GET_CODE (operands[0]) == MEM)
2163 return "stw %r1,%0";
2164 if (GET_CODE (operands[1]) == MEM)
2166 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2171 gcc_assert (GET_MODE (operands[1]) == SFmode);
2173 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2175 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2176 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2178 operands[1] = GEN_INT (i);
2179 /* Fall through to CONST_INT case. */
2181 if (GET_CODE (operands[1]) == CONST_INT)
2183 intval = INTVAL (operands[1]);
2185 if (VAL_14_BITS_P (intval))
2187 else if ((intval & 0x7ff) == 0)
2188 return "ldil L'%1,%0";
2189 else if (zdepi_cint_p (intval))
2190 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2192 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2194 return "copy %1,%0";
2198 /* Compute position (in OP[1]) and width (in OP[2])
2199 useful for copying IMM to a register using the zdepi
2200 instructions. Store the immediate value to insert in OP[0]. */
2202 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2206 /* Find the least significant set bit in IMM. */
2207 for (lsb = 0; lsb < 32; lsb++)
2214 /* Choose variants based on *sign* of the 5-bit field. */
2215 if ((imm & 0x10) == 0)
2216 len = (lsb <= 28) ? 4 : 32 - lsb;
2219 /* Find the width of the bitstring in IMM. */
2220 for (len = 5; len < 32; len++)
2222 if ((imm & (1 << len)) == 0)
2226 /* Sign extend IMM as a 5-bit value. */
2227 imm = (imm & 0xf) - 0x10;
2235 /* Compute position (in OP[1]) and width (in OP[2])
2236 useful for copying IMM to a register using the depdi,z
2237 instructions. Store the immediate value to insert in OP[0]. */
2239 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2241 HOST_WIDE_INT lsb, len;
2243 /* Find the least significant set bit in IMM. */
2244 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2251 /* Choose variants based on *sign* of the 5-bit field. */
2252 if ((imm & 0x10) == 0)
2253 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2254 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2257 /* Find the width of the bitstring in IMM. */
2258 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2260 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2264 /* Sign extend IMM as a 5-bit value. */
2265 imm = (imm & 0xf) - 0x10;
2273 /* Output assembler code to perform a doubleword move insn
2274 with operands OPERANDS. */
2277 output_move_double (rtx *operands)
2279 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2281 rtx addreg0 = 0, addreg1 = 0;
2283 /* First classify both operands. */
2285 if (REG_P (operands[0]))
2287 else if (offsettable_memref_p (operands[0]))
2289 else if (GET_CODE (operands[0]) == MEM)
2294 if (REG_P (operands[1]))
2296 else if (CONSTANT_P (operands[1]))
2298 else if (offsettable_memref_p (operands[1]))
2300 else if (GET_CODE (operands[1]) == MEM)
2305 /* Check for the cases that the operand constraints are not
2306 supposed to allow to happen. */
2307 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2309 /* Handle copies between general and floating registers. */
2311 if (optype0 == REGOP && optype1 == REGOP
2312 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2314 if (FP_REG_P (operands[0]))
2316 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2317 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2318 return "{fldds|fldd} -16(%%sp),%0";
2322 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2323 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2324 return "{ldws|ldw} -12(%%sp),%R0";
2328 /* Handle auto decrementing and incrementing loads and stores
2329 specifically, since the structure of the function doesn't work
2330 for them without major modification. Do it better when we learn
2331 this port about the general inc/dec addressing of PA.
2332 (This was written by tege. Chide him if it doesn't work.) */
2334 if (optype0 == MEMOP)
2336 /* We have to output the address syntax ourselves, since print_operand
2337 doesn't deal with the addresses we want to use. Fix this later. */
2339 rtx addr = XEXP (operands[0], 0);
2340 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2342 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2344 operands[0] = XEXP (addr, 0);
2345 gcc_assert (GET_CODE (operands[1]) == REG
2346 && GET_CODE (operands[0]) == REG);
2348 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2350 /* No overlap between high target register and address
2351 register. (We do this in a non-obvious way to
2352 save a register file writeback) */
2353 if (GET_CODE (addr) == POST_INC)
2354 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2355 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2357 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2359 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2361 operands[0] = XEXP (addr, 0);
2362 gcc_assert (GET_CODE (operands[1]) == REG
2363 && GET_CODE (operands[0]) == REG);
2365 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2366 /* No overlap between high target register and address
2367 register. (We do this in a non-obvious way to save a
2368 register file writeback) */
2369 if (GET_CODE (addr) == PRE_INC)
2370 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2371 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2374 if (optype1 == MEMOP)
2376 /* We have to output the address syntax ourselves, since print_operand
2377 doesn't deal with the addresses we want to use. Fix this later. */
2379 rtx addr = XEXP (operands[1], 0);
2380 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2382 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2384 operands[1] = XEXP (addr, 0);
2385 gcc_assert (GET_CODE (operands[0]) == REG
2386 && GET_CODE (operands[1]) == REG);
2388 if (!reg_overlap_mentioned_p (high_reg, addr))
2390 /* No overlap between high target register and address
2391 register. (We do this in a non-obvious way to
2392 save a register file writeback) */
2393 if (GET_CODE (addr) == POST_INC)
2394 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2395 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2399 /* This is an undefined situation. We should load into the
2400 address register *and* update that register. Probably
2401 we don't need to handle this at all. */
2402 if (GET_CODE (addr) == POST_INC)
2403 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2404 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2407 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2409 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2411 operands[1] = XEXP (addr, 0);
2412 gcc_assert (GET_CODE (operands[0]) == REG
2413 && GET_CODE (operands[1]) == REG);
2415 if (!reg_overlap_mentioned_p (high_reg, addr))
2417 /* No overlap between high target register and address
2418 register. (We do this in a non-obvious way to
2419 save a register file writeback) */
2420 if (GET_CODE (addr) == PRE_INC)
2421 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2422 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2426 /* This is an undefined situation. We should load into the
2427 address register *and* update that register. Probably
2428 we don't need to handle this at all. */
2429 if (GET_CODE (addr) == PRE_INC)
2430 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2431 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2434 else if (GET_CODE (addr) == PLUS
2435 && GET_CODE (XEXP (addr, 0)) == MULT)
2438 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2440 if (!reg_overlap_mentioned_p (high_reg, addr))
2442 xoperands[0] = high_reg;
2443 xoperands[1] = XEXP (addr, 1);
2444 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2445 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2446 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2448 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2452 xoperands[0] = high_reg;
2453 xoperands[1] = XEXP (addr, 1);
2454 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2455 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2456 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2458 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2463 /* If an operand is an unoffsettable memory ref, find a register
2464 we can increment temporarily to make it refer to the second word. */
2466 if (optype0 == MEMOP)
2467 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2469 if (optype1 == MEMOP)
2470 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2472 /* Ok, we can do one word at a time.
2473 Normally we do the low-numbered word first.
2475 In either case, set up in LATEHALF the operands to use
2476 for the high-numbered word and in some cases alter the
2477 operands in OPERANDS to be suitable for the low-numbered word. */
2479 if (optype0 == REGOP)
2480 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2481 else if (optype0 == OFFSOP)
2482 latehalf[0] = adjust_address (operands[0], SImode, 4);
2484 latehalf[0] = operands[0];
2486 if (optype1 == REGOP)
2487 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2488 else if (optype1 == OFFSOP)
2489 latehalf[1] = adjust_address (operands[1], SImode, 4);
2490 else if (optype1 == CNSTOP)
2491 split_double (operands[1], &operands[1], &latehalf[1]);
2493 latehalf[1] = operands[1];
2495 /* If the first move would clobber the source of the second one,
2496 do them in the other order.
2498 This can happen in two cases:
2500 mem -> register where the first half of the destination register
2501 is the same register used in the memory's address. Reload
2502 can create such insns.
2504 mem in this case will be either register indirect or register
2505 indirect plus a valid offset.
2507 register -> register move where REGNO(dst) == REGNO(src + 1)
2508 someone (Tim/Tege?) claimed this can happen for parameter loads.
2510 Handle mem -> register case first. */
2511 if (optype0 == REGOP
2512 && (optype1 == MEMOP || optype1 == OFFSOP)
2513 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2516 /* Do the late half first. */
2518 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2519 output_asm_insn (singlemove_string (latehalf), latehalf);
2523 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2524 return singlemove_string (operands);
2527 /* Now handle register -> register case. */
2528 if (optype0 == REGOP && optype1 == REGOP
2529 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2531 output_asm_insn (singlemove_string (latehalf), latehalf);
2532 return singlemove_string (operands);
2535 /* Normal case: do the two words, low-numbered first. */
2537 output_asm_insn (singlemove_string (operands), operands);
2539 /* Make any unoffsettable addresses point at high-numbered word. */
2541 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2543 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2546 output_asm_insn (singlemove_string (latehalf), latehalf);
2548 /* Undo the adds we just did. */
2550 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2552 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2558 output_fp_move_double (rtx *operands)
2560 if (FP_REG_P (operands[0]))
2562 if (FP_REG_P (operands[1])
2563 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2564 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2566 output_asm_insn ("fldd%F1 %1,%0", operands);
2568 else if (FP_REG_P (operands[1]))
2570 output_asm_insn ("fstd%F0 %1,%0", operands);
2576 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2578 /* This is a pain. You have to be prepared to deal with an
2579 arbitrary address here including pre/post increment/decrement.
2581 so avoid this in the MD. */
2582 gcc_assert (GET_CODE (operands[0]) == REG);
2584 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2585 xoperands[0] = operands[0];
2586 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2591 /* Return a REG that occurs in ADDR with coefficient 1.
2592 ADDR can be effectively incremented by incrementing REG. */
2595 find_addr_reg (rtx addr)
2597 while (GET_CODE (addr) == PLUS)
2599 if (GET_CODE (XEXP (addr, 0)) == REG)
2600 addr = XEXP (addr, 0);
2601 else if (GET_CODE (XEXP (addr, 1)) == REG)
2602 addr = XEXP (addr, 1);
2603 else if (CONSTANT_P (XEXP (addr, 0)))
2604 addr = XEXP (addr, 1);
2605 else if (CONSTANT_P (XEXP (addr, 1)))
2606 addr = XEXP (addr, 0);
2610 gcc_assert (GET_CODE (addr) == REG);
2614 /* Emit code to perform a block move.
2616 OPERANDS[0] is the destination pointer as a REG, clobbered.
2617 OPERANDS[1] is the source pointer as a REG, clobbered.
2618 OPERANDS[2] is a register for temporary storage.
2619 OPERANDS[3] is a register for temporary storage.
2620 OPERANDS[4] is the size as a CONST_INT
2621 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2622 OPERANDS[6] is another temporary register. */
2625 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2627 int align = INTVAL (operands[5]);
2628 unsigned long n_bytes = INTVAL (operands[4]);
2630 /* We can't move more than a word at a time because the PA
2631 has no longer integer move insns. (Could use fp mem ops?) */
2632 if (align > (TARGET_64BIT ? 8 : 4))
2633 align = (TARGET_64BIT ? 8 : 4);
2635 /* Note that we know each loop below will execute at least twice
2636 (else we would have open-coded the copy). */
2640 /* Pre-adjust the loop counter. */
2641 operands[4] = GEN_INT (n_bytes - 16);
2642 output_asm_insn ("ldi %4,%2", operands);
2645 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2646 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2647 output_asm_insn ("std,ma %3,8(%0)", operands);
2648 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2649 output_asm_insn ("std,ma %6,8(%0)", operands);
2651 /* Handle the residual. There could be up to 7 bytes of
2652 residual to copy! */
2653 if (n_bytes % 16 != 0)
2655 operands[4] = GEN_INT (n_bytes % 8);
2656 if (n_bytes % 16 >= 8)
2657 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2658 if (n_bytes % 8 != 0)
2659 output_asm_insn ("ldd 0(%1),%6", operands);
2660 if (n_bytes % 16 >= 8)
2661 output_asm_insn ("std,ma %3,8(%0)", operands);
2662 if (n_bytes % 8 != 0)
2663 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2668 /* Pre-adjust the loop counter. */
2669 operands[4] = GEN_INT (n_bytes - 8);
2670 output_asm_insn ("ldi %4,%2", operands);
2673 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2674 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2675 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2676 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2677 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2679 /* Handle the residual. There could be up to 7 bytes of
2680 residual to copy! */
2681 if (n_bytes % 8 != 0)
2683 operands[4] = GEN_INT (n_bytes % 4);
2684 if (n_bytes % 8 >= 4)
2685 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2686 if (n_bytes % 4 != 0)
2687 output_asm_insn ("ldw 0(%1),%6", operands);
2688 if (n_bytes % 8 >= 4)
2689 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2690 if (n_bytes % 4 != 0)
2691 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2696 /* Pre-adjust the loop counter. */
2697 operands[4] = GEN_INT (n_bytes - 4);
2698 output_asm_insn ("ldi %4,%2", operands);
2701 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2702 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2703 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2704 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2705 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2707 /* Handle the residual. */
2708 if (n_bytes % 4 != 0)
2710 if (n_bytes % 4 >= 2)
2711 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2712 if (n_bytes % 2 != 0)
2713 output_asm_insn ("ldb 0(%1),%6", operands);
2714 if (n_bytes % 4 >= 2)
2715 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2716 if (n_bytes % 2 != 0)
2717 output_asm_insn ("stb %6,0(%0)", operands);
2722 /* Pre-adjust the loop counter. */
2723 operands[4] = GEN_INT (n_bytes - 2);
2724 output_asm_insn ("ldi %4,%2", operands);
2727 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2728 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2729 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2730 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2731 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2733 /* Handle the residual. */
2734 if (n_bytes % 2 != 0)
2736 output_asm_insn ("ldb 0(%1),%3", operands);
2737 output_asm_insn ("stb %3,0(%0)", operands);
2746 /* Count the number of insns necessary to handle this block move.
2748 Basic structure is the same as emit_block_move, except that we
2749 count insns rather than emit them. */
2752 compute_movmem_length (rtx insn)
2754 rtx pat = PATTERN (insn);
2755 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2756 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2757 unsigned int n_insns = 0;
2759 /* We can't move more than four bytes at a time because the PA
2760 has no longer integer move insns. (Could use fp mem ops?) */
2761 if (align > (TARGET_64BIT ? 8 : 4))
2762 align = (TARGET_64BIT ? 8 : 4);
2764 /* The basic copying loop. */
2768 if (n_bytes % (2 * align) != 0)
2770 if ((n_bytes % (2 * align)) >= align)
2773 if ((n_bytes % align) != 0)
2777 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2781 /* Emit code to perform a block clear.
2783 OPERANDS[0] is the destination pointer as a REG, clobbered.
2784 OPERANDS[1] is a register for temporary storage.
2785 OPERANDS[2] is the size as a CONST_INT
2786 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2789 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2791 int align = INTVAL (operands[3]);
2792 unsigned long n_bytes = INTVAL (operands[2]);
2794 /* We can't clear more than a word at a time because the PA
2795 has no longer integer move insns. */
2796 if (align > (TARGET_64BIT ? 8 : 4))
2797 align = (TARGET_64BIT ? 8 : 4);
2799 /* Note that we know each loop below will execute at least twice
2800 (else we would have open-coded the copy). */
2804 /* Pre-adjust the loop counter. */
2805 operands[2] = GEN_INT (n_bytes - 16);
2806 output_asm_insn ("ldi %2,%1", operands);
2809 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2810 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2811 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2813 /* Handle the residual. There could be up to 7 bytes of
2814 residual to copy! */
2815 if (n_bytes % 16 != 0)
2817 operands[2] = GEN_INT (n_bytes % 8);
2818 if (n_bytes % 16 >= 8)
2819 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2820 if (n_bytes % 8 != 0)
2821 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2826 /* Pre-adjust the loop counter. */
2827 operands[2] = GEN_INT (n_bytes - 8);
2828 output_asm_insn ("ldi %2,%1", operands);
2831 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2832 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2833 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2835 /* Handle the residual. There could be up to 7 bytes of
2836 residual to copy! */
2837 if (n_bytes % 8 != 0)
2839 operands[2] = GEN_INT (n_bytes % 4);
2840 if (n_bytes % 8 >= 4)
2841 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2842 if (n_bytes % 4 != 0)
2843 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2848 /* Pre-adjust the loop counter. */
2849 operands[2] = GEN_INT (n_bytes - 4);
2850 output_asm_insn ("ldi %2,%1", operands);
2853 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2854 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2855 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2857 /* Handle the residual. */
2858 if (n_bytes % 4 != 0)
2860 if (n_bytes % 4 >= 2)
2861 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2862 if (n_bytes % 2 != 0)
2863 output_asm_insn ("stb %%r0,0(%0)", operands);
2868 /* Pre-adjust the loop counter. */
2869 operands[2] = GEN_INT (n_bytes - 2);
2870 output_asm_insn ("ldi %2,%1", operands);
2873 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2874 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2875 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2877 /* Handle the residual. */
2878 if (n_bytes % 2 != 0)
2879 output_asm_insn ("stb %%r0,0(%0)", operands);
2888 /* Count the number of insns necessary to handle this block move.
2890 Basic structure is the same as emit_block_move, except that we
2891 count insns rather than emit them. */
2894 compute_clrmem_length (rtx insn)
2896 rtx pat = PATTERN (insn);
2897 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2898 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2899 unsigned int n_insns = 0;
2901 /* We can't clear more than a word at a time because the PA
2902 has no longer integer move insns. */
2903 if (align > (TARGET_64BIT ? 8 : 4))
2904 align = (TARGET_64BIT ? 8 : 4);
2906 /* The basic loop. */
2910 if (n_bytes % (2 * align) != 0)
2912 if ((n_bytes % (2 * align)) >= align)
2915 if ((n_bytes % align) != 0)
2919 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2925 output_and (rtx *operands)
2927 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2929 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2930 int ls0, ls1, ms0, p, len;
2932 for (ls0 = 0; ls0 < 32; ls0++)
2933 if ((mask & (1 << ls0)) == 0)
2936 for (ls1 = ls0; ls1 < 32; ls1++)
2937 if ((mask & (1 << ls1)) != 0)
2940 for (ms0 = ls1; ms0 < 32; ms0++)
2941 if ((mask & (1 << ms0)) == 0)
2944 gcc_assert (ms0 == 32);
2952 operands[2] = GEN_INT (len);
2953 return "{extru|extrw,u} %1,31,%2,%0";
2957 /* We could use this `depi' for the case above as well, but `depi'
2958 requires one more register file access than an `extru'. */
2963 operands[2] = GEN_INT (p);
2964 operands[3] = GEN_INT (len);
2965 return "{depi|depwi} 0,%2,%3,%0";
2969 return "and %1,%2,%0";
2972 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2973 storing the result in operands[0]. */
2975 output_64bit_and (rtx *operands)
2977 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2979 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2980 int ls0, ls1, ms0, p, len;
2982 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2983 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2986 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2987 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2990 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2991 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2994 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2996 if (ls1 == HOST_BITS_PER_WIDE_INT)
3002 operands[2] = GEN_INT (len);
3003 return "extrd,u %1,63,%2,%0";
3007 /* We could use this `depi' for the case above as well, but `depi'
3008 requires one more register file access than an `extru'. */
3013 operands[2] = GEN_INT (p);
3014 operands[3] = GEN_INT (len);
3015 return "depdi 0,%2,%3,%0";
3019 return "and %1,%2,%0";
3023 output_ior (rtx *operands)
3025 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3026 int bs0, bs1, p, len;
3028 if (INTVAL (operands[2]) == 0)
3029 return "copy %1,%0";
3031 for (bs0 = 0; bs0 < 32; bs0++)
3032 if ((mask & (1 << bs0)) != 0)
3035 for (bs1 = bs0; bs1 < 32; bs1++)
3036 if ((mask & (1 << bs1)) == 0)
3039 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3044 operands[2] = GEN_INT (p);
3045 operands[3] = GEN_INT (len);
3046 return "{depi|depwi} -1,%2,%3,%0";
3049 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3050 storing the result in operands[0]. */
3052 output_64bit_ior (rtx *operands)
3054 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3055 int bs0, bs1, p, len;
3057 if (INTVAL (operands[2]) == 0)
3058 return "copy %1,%0";
3060 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3061 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3064 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3065 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3068 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3069 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3074 operands[2] = GEN_INT (p);
3075 operands[3] = GEN_INT (len);
3076 return "depdi -1,%2,%3,%0";
3079 /* Target hook for assembling integer objects. This code handles
3080 aligned SI and DI integers specially since function references
3081 must be preceded by P%. */
3084 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3086 if (size == UNITS_PER_WORD
3088 && function_label_operand (x, VOIDmode))
3090 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3091 output_addr_const (asm_out_file, x);
3092 fputc ('\n', asm_out_file);
3095 return default_assemble_integer (x, size, aligned_p);
3098 /* Output an ascii string. */
3100 output_ascii (FILE *file, const char *p, int size)
3104 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3106 /* The HP assembler can only take strings of 256 characters at one
3107 time. This is a limitation on input line length, *not* the
3108 length of the string. Sigh. Even worse, it seems that the
3109 restriction is in number of input characters (see \xnn &
3110 \whatever). So we have to do this very carefully. */
3112 fputs ("\t.STRING \"", file);
3115 for (i = 0; i < size; i += 4)
3119 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3121 register unsigned int c = (unsigned char) p[i + io];
3123 if (c == '\"' || c == '\\')
3124 partial_output[co++] = '\\';
3125 if (c >= ' ' && c < 0177)
3126 partial_output[co++] = c;
3130 partial_output[co++] = '\\';
3131 partial_output[co++] = 'x';
3132 hexd = c / 16 - 0 + '0';
3134 hexd -= '9' - 'a' + 1;
3135 partial_output[co++] = hexd;
3136 hexd = c % 16 - 0 + '0';
3138 hexd -= '9' - 'a' + 1;
3139 partial_output[co++] = hexd;
3142 if (chars_output + co > 243)
3144 fputs ("\"\n\t.STRING \"", file);
3147 fwrite (partial_output, 1, (size_t) co, file);
3151 fputs ("\"\n", file);
3154 /* Try to rewrite floating point comparisons & branches to avoid
3155 useless add,tr insns.
3157 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3158 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3159 first attempt to remove useless add,tr insns. It is zero
3160 for the second pass as reorg sometimes leaves bogus REG_DEAD
3163 When CHECK_NOTES is zero we can only eliminate add,tr insns
3164 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3167 remove_useless_addtr_insns (int check_notes)
3170 static int pass = 0;
3172 /* This is fairly cheap, so always run it when optimizing. */
3176 int fbranch_count = 0;
3178 /* Walk all the insns in this function looking for fcmp & fbranch
3179 instructions. Keep track of how many of each we find. */
3180 for (insn = get_insns (); insn; insn = next_insn (insn))
3184 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3185 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3188 tmp = PATTERN (insn);
3190 /* It must be a set. */
3191 if (GET_CODE (tmp) != SET)
3194 /* If the destination is CCFP, then we've found an fcmp insn. */
3195 tmp = SET_DEST (tmp);
3196 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3202 tmp = PATTERN (insn);
3203 /* If this is an fbranch instruction, bump the fbranch counter. */
3204 if (GET_CODE (tmp) == SET
3205 && SET_DEST (tmp) == pc_rtx
3206 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3207 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3208 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3209 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3217 /* Find all floating point compare + branch insns. If possible,
3218 reverse the comparison & the branch to avoid add,tr insns. */
3219 for (insn = get_insns (); insn; insn = next_insn (insn))
3223 /* Ignore anything that isn't an INSN. */
3224 if (GET_CODE (insn) != INSN)
3227 tmp = PATTERN (insn);
3229 /* It must be a set. */
3230 if (GET_CODE (tmp) != SET)
3233 /* The destination must be CCFP, which is register zero. */
3234 tmp = SET_DEST (tmp);
3235 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3238 /* INSN should be a set of CCFP.
3240 See if the result of this insn is used in a reversed FP
3241 conditional branch. If so, reverse our condition and
3242 the branch. Doing so avoids useless add,tr insns. */
3243 next = next_insn (insn);
3246 /* Jumps, calls and labels stop our search. */
3247 if (GET_CODE (next) == JUMP_INSN
3248 || GET_CODE (next) == CALL_INSN
3249 || GET_CODE (next) == CODE_LABEL)
3252 /* As does another fcmp insn. */
3253 if (GET_CODE (next) == INSN
3254 && GET_CODE (PATTERN (next)) == SET
3255 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3256 && REGNO (SET_DEST (PATTERN (next))) == 0)
3259 next = next_insn (next);
3262 /* Is NEXT_INSN a branch? */
3264 && GET_CODE (next) == JUMP_INSN)
3266 rtx pattern = PATTERN (next);
3268 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3269 and CCFP dies, then reverse our conditional and the branch
3270 to avoid the add,tr. */
3271 if (GET_CODE (pattern) == SET
3272 && SET_DEST (pattern) == pc_rtx
3273 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3274 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3275 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3276 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3277 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3278 && (fcmp_count == fbranch_count
3280 && find_regno_note (next, REG_DEAD, 0))))
3282 /* Reverse the branch. */
3283 tmp = XEXP (SET_SRC (pattern), 1);
3284 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3285 XEXP (SET_SRC (pattern), 2) = tmp;
3286 INSN_CODE (next) = -1;
3288 /* Reverse our condition. */
3289 tmp = PATTERN (insn);
3290 PUT_CODE (XEXP (tmp, 1),
3291 (reverse_condition_maybe_unordered
3292 (GET_CODE (XEXP (tmp, 1)))));
3302 /* You may have trouble believing this, but this is the 32 bit HP-PA
3307 Variable arguments (optional; any number may be allocated)
3309 SP-(4*(N+9)) arg word N
3314 Fixed arguments (must be allocated; may remain unused)
3323 SP-32 External Data Pointer (DP)
3325 SP-24 External/stub RP (RP')
3329 SP-8 Calling Stub RP (RP'')
3334 SP-0 Stack Pointer (points to next available address)
3338 /* This function saves registers as follows. Registers marked with ' are
3339 this function's registers (as opposed to the previous function's).
3340 If a frame_pointer isn't needed, r4 is saved as a general register;
3341 the space for the frame pointer is still allocated, though, to keep
3347 SP (FP') Previous FP
3348 SP + 4 Alignment filler (sigh)
3349 SP + 8 Space for locals reserved here.
3353 SP + n All call saved register used.
3357 SP + o All call saved fp registers used.
3361 SP + p (SP') points to next available address.
3365 /* Global variables set by output_function_prologue(). */
3366 /* Size of frame. Need to know this to emit return insns from
3368 static HOST_WIDE_INT actual_fsize, local_fsize;
3369 static int save_fregs;
3371 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3372 Handle case where DISP > 8k by using the add_high_const patterns.
3374 Note in DISP > 8k case, we will leave the high part of the address
3375 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3378 store_reg (int reg, HOST_WIDE_INT disp, int base)
3380 rtx insn, dest, src, basereg;
3382 src = gen_rtx_REG (word_mode, reg);
3383 basereg = gen_rtx_REG (Pmode, base);
3384 if (VAL_14_BITS_P (disp))
3386 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3387 insn = emit_move_insn (dest, src);
3389 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3391 rtx delta = GEN_INT (disp);
3392 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3394 emit_move_insn (tmpreg, delta);
3395 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3399 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3400 gen_rtx_SET (VOIDmode, tmpreg,
3401 gen_rtx_PLUS (Pmode, basereg, delta)),
3403 RTX_FRAME_RELATED_P (insn) = 1;
3405 dest = gen_rtx_MEM (word_mode, tmpreg);
3406 insn = emit_move_insn (dest, src);
3410 rtx delta = GEN_INT (disp);
3411 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3412 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3414 emit_move_insn (tmpreg, high);
3415 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3416 insn = emit_move_insn (dest, src);
3420 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3421 gen_rtx_SET (VOIDmode,
3422 gen_rtx_MEM (word_mode,
3423 gen_rtx_PLUS (word_mode, basereg,
3431 RTX_FRAME_RELATED_P (insn) = 1;
3434 /* Emit RTL to store REG at the memory location specified by BASE and then
3435 add MOD to BASE. MOD must be <= 8k. */
3438 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3440 rtx insn, basereg, srcreg, delta;
3442 gcc_assert (VAL_14_BITS_P (mod));
3444 basereg = gen_rtx_REG (Pmode, base);
3445 srcreg = gen_rtx_REG (word_mode, reg);
3446 delta = GEN_INT (mod);
3448 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3451 RTX_FRAME_RELATED_P (insn) = 1;
3453 /* RTX_FRAME_RELATED_P must be set on each frame related set
3454 in a parallel with more than one element. */
3455 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3456 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3460 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3461 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3462 whether to add a frame note or not.
3464 In the DISP > 8k case, we leave the high part of the address in %r1.
3465 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3468 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3472 if (VAL_14_BITS_P (disp))
3474 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3475 plus_constant (gen_rtx_REG (Pmode, base), disp));
3477 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3479 rtx basereg = gen_rtx_REG (Pmode, base);
3480 rtx delta = GEN_INT (disp);
3481 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3483 emit_move_insn (tmpreg, delta);
3484 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3485 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3488 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3489 gen_rtx_SET (VOIDmode, tmpreg,
3490 gen_rtx_PLUS (Pmode, basereg, delta)),
3495 rtx basereg = gen_rtx_REG (Pmode, base);
3496 rtx delta = GEN_INT (disp);
3497 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3499 emit_move_insn (tmpreg,
3500 gen_rtx_PLUS (Pmode, basereg,
3501 gen_rtx_HIGH (Pmode, delta)));
3502 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3503 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3506 if (DO_FRAME_NOTES && note)
3507 RTX_FRAME_RELATED_P (insn) = 1;
3511 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3516 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3517 be consistent with the rounding and size calculation done here.
3518 Change them at the same time. */
3520 /* We do our own stack alignment. First, round the size of the
3521 stack locals up to a word boundary. */
3522 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3524 /* Space for previous frame pointer + filler. If any frame is
3525 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3526 waste some space here for the sake of HP compatibility. The
3527 first slot is only used when the frame pointer is needed. */
3528 if (size || frame_pointer_needed)
3529 size += STARTING_FRAME_OFFSET;
3531 /* If the current function calls __builtin_eh_return, then we need
3532 to allocate stack space for registers that will hold data for
3533 the exception handler. */
3534 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3538 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3540 size += i * UNITS_PER_WORD;
3543 /* Account for space used by the callee general register saves. */
3544 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3545 if (df_regs_ever_live_p (i))
3546 size += UNITS_PER_WORD;
3548 /* Account for space used by the callee floating point register saves. */
3549 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3550 if (df_regs_ever_live_p (i)
3551 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3555 /* We always save both halves of the FP register, so always
3556 increment the frame size by 8 bytes. */
3560 /* If any of the floating registers are saved, account for the
3561 alignment needed for the floating point register save block. */
3564 size = (size + 7) & ~7;
3569 /* The various ABIs include space for the outgoing parameters in the
3570 size of the current function's stack frame. We don't need to align
3571 for the outgoing arguments as their alignment is set by the final
3572 rounding for the frame as a whole. */
3573 size += crtl->outgoing_args_size;
3575 /* Allocate space for the fixed frame marker. This space must be
3576 allocated for any function that makes calls or allocates
3578 if (!current_function_is_leaf || size)
3579 size += TARGET_64BIT ? 48 : 32;
3581 /* Finally, round to the preferred stack boundary. */
3582 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3583 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3586 /* Generate the assembly code for function entry. FILE is a stdio
3587 stream to output the code to. SIZE is an int: how many units of
3588 temporary storage to allocate.
3590 Refer to the array `regs_ever_live' to determine which registers to
3591 save; `regs_ever_live[I]' is nonzero if register number I is ever
3592 used in the function. This function is responsible for knowing
3593 which registers should not be saved even if used. */
3595 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3596 of memory. If any fpu reg is used in the function, we allocate
3597 such a block here, at the bottom of the frame, just in case it's needed.
3599 If this function is a leaf procedure, then we may choose not
3600 to do a "save" insn. The decision about whether or not
3601 to do this is made in regclass.c. */
3604 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3606 /* The function's label and associated .PROC must never be
3607 separated and must be output *after* any profiling declarations
3608 to avoid changing spaces/subspaces within a procedure. */
3609 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3610 fputs ("\t.PROC\n", file);
3612 /* hppa_expand_prologue does the dirty work now. We just need
3613 to output the assembler directives which denote the start
3615 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3616 if (current_function_is_leaf)
3617 fputs (",NO_CALLS", file);
3619 fputs (",CALLS", file);
3621 fputs (",SAVE_RP", file);
3623 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3624 at the beginning of the frame and that it is used as the frame
3625 pointer for the frame. We do this because our current frame
3626 layout doesn't conform to that specified in the HP runtime
3627 documentation and we need a way to indicate to programs such as
3628 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3629 isn't used by HP compilers but is supported by the assembler.
3630 However, SAVE_SP is supposed to indicate that the previous stack
3631 pointer has been saved in the frame marker. */
3632 if (frame_pointer_needed)
3633 fputs (",SAVE_SP", file);
3635 /* Pass on information about the number of callee register saves
3636 performed in the prologue.
3638 The compiler is supposed to pass the highest register number
3639 saved, the assembler then has to adjust that number before
3640 entering it into the unwind descriptor (to account for any
3641 caller saved registers with lower register numbers than the
3642 first callee saved register). */
3644 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3647 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3649 fputs ("\n\t.ENTRY\n", file);
3651 remove_useless_addtr_insns (0);
3655 hppa_expand_prologue (void)
3657 int merge_sp_adjust_with_store = 0;
3658 HOST_WIDE_INT size = get_frame_size ();
3659 HOST_WIDE_INT offset;
3667 /* Compute total size for frame pointer, filler, locals and rounding to
3668 the next word boundary. Similar code appears in compute_frame_size
3669 and must be changed in tandem with this code. */
3670 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3671 if (local_fsize || frame_pointer_needed)
3672 local_fsize += STARTING_FRAME_OFFSET;
3674 actual_fsize = compute_frame_size (size, &save_fregs);
3676 /* Compute a few things we will use often. */
3677 tmpreg = gen_rtx_REG (word_mode, 1);
3679 /* Save RP first. The calling conventions manual states RP will
3680 always be stored into the caller's frame at sp - 20 or sp - 16
3681 depending on which ABI is in use. */
3682 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3684 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3690 /* Allocate the local frame and set up the frame pointer if needed. */
3691 if (actual_fsize != 0)
3693 if (frame_pointer_needed)
3695 /* Copy the old frame pointer temporarily into %r1. Set up the
3696 new stack pointer, then store away the saved old frame pointer
3697 into the stack at sp and at the same time update the stack
3698 pointer by actual_fsize bytes. Two versions, first
3699 handles small (<8k) frames. The second handles large (>=8k)
3701 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3703 RTX_FRAME_RELATED_P (insn) = 1;
3705 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3707 RTX_FRAME_RELATED_P (insn) = 1;
3709 if (VAL_14_BITS_P (actual_fsize))
3710 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3713 /* It is incorrect to store the saved frame pointer at *sp,
3714 then increment sp (writes beyond the current stack boundary).
3716 So instead use stwm to store at *sp and post-increment the
3717 stack pointer as an atomic operation. Then increment sp to
3718 finish allocating the new frame. */
3719 HOST_WIDE_INT adjust1 = 8192 - 64;
3720 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3722 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3723 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3727 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3728 we need to store the previous stack pointer (frame pointer)
3729 into the frame marker on targets that use the HP unwind
3730 library. This allows the HP unwind library to be used to
3731 unwind GCC frames. However, we are not fully compatible
3732 with the HP library because our frame layout differs from
3733 that specified in the HP runtime specification.
3735 We don't want a frame note on this instruction as the frame
3736 marker moves during dynamic stack allocation.
3738 This instruction also serves as a blockage to prevent
3739 register spills from being scheduled before the stack
3740 pointer is raised. This is necessary as we store
3741 registers using the frame pointer as a base register,
3742 and the frame pointer is set before sp is raised. */
3743 if (TARGET_HPUX_UNWIND_LIBRARY)
3745 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3746 GEN_INT (TARGET_64BIT ? -8 : -4));
3748 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3752 emit_insn (gen_blockage ());
3754 /* no frame pointer needed. */
3757 /* In some cases we can perform the first callee register save
3758 and allocating the stack frame at the same time. If so, just
3759 make a note of it and defer allocating the frame until saving
3760 the callee registers. */
3761 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3762 merge_sp_adjust_with_store = 1;
3763 /* Can not optimize. Adjust the stack frame by actual_fsize
3766 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3771 /* Normal register save.
3773 Do not save the frame pointer in the frame_pointer_needed case. It
3774 was done earlier. */
3775 if (frame_pointer_needed)
3777 offset = local_fsize;
3779 /* Saving the EH return data registers in the frame is the simplest
3780 way to get the frame unwind information emitted. We put them
3781 just before the general registers. */
3782 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3784 unsigned int i, regno;
3788 regno = EH_RETURN_DATA_REGNO (i);
3789 if (regno == INVALID_REGNUM)
3792 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3793 offset += UNITS_PER_WORD;
3797 for (i = 18; i >= 4; i--)
3798 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3800 store_reg (i, offset, FRAME_POINTER_REGNUM);
3801 offset += UNITS_PER_WORD;
3804 /* Account for %r3 which is saved in a special place. */
3807 /* No frame pointer needed. */
3810 offset = local_fsize - actual_fsize;
3812 /* Saving the EH return data registers in the frame is the simplest
3813 way to get the frame unwind information emitted. */
3814 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3816 unsigned int i, regno;
3820 regno = EH_RETURN_DATA_REGNO (i);
3821 if (regno == INVALID_REGNUM)
3824 /* If merge_sp_adjust_with_store is nonzero, then we can
3825 optimize the first save. */
3826 if (merge_sp_adjust_with_store)
3828 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3829 merge_sp_adjust_with_store = 0;
3832 store_reg (regno, offset, STACK_POINTER_REGNUM);
3833 offset += UNITS_PER_WORD;
3837 for (i = 18; i >= 3; i--)
3838 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3840 /* If merge_sp_adjust_with_store is nonzero, then we can
3841 optimize the first GR save. */
3842 if (merge_sp_adjust_with_store)
3844 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3845 merge_sp_adjust_with_store = 0;
3848 store_reg (i, offset, STACK_POINTER_REGNUM);
3849 offset += UNITS_PER_WORD;
3853 /* If we wanted to merge the SP adjustment with a GR save, but we never
3854 did any GR saves, then just emit the adjustment here. */
3855 if (merge_sp_adjust_with_store)
3856 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3860 /* The hppa calling conventions say that %r19, the pic offset
3861 register, is saved at sp - 32 (in this function's frame)
3862 when generating PIC code. FIXME: What is the correct thing
3863 to do for functions which make no calls and allocate no
3864 frame? Do we need to allocate a frame, or can we just omit
3865 the save? For now we'll just omit the save.
3867 We don't want a note on this insn as the frame marker can
3868 move if there is a dynamic stack allocation. */
3869 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3871 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3873 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3877 /* Align pointer properly (doubleword boundary). */
3878 offset = (offset + 7) & ~7;
3880 /* Floating point register store. */
3885 /* First get the frame or stack pointer to the start of the FP register
3887 if (frame_pointer_needed)
3889 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3890 base = frame_pointer_rtx;
3894 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3895 base = stack_pointer_rtx;
3898 /* Now actually save the FP registers. */
3899 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3901 if (df_regs_ever_live_p (i)
3902 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3904 rtx addr, insn, reg;
3905 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3906 reg = gen_rtx_REG (DFmode, i);
3907 insn = emit_move_insn (addr, reg);
3910 RTX_FRAME_RELATED_P (insn) = 1;
3913 rtx mem = gen_rtx_MEM (DFmode,
3914 plus_constant (base, offset));
3916 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3917 gen_rtx_SET (VOIDmode, mem, reg),
3922 rtx meml = gen_rtx_MEM (SFmode,
3923 plus_constant (base, offset));
3924 rtx memr = gen_rtx_MEM (SFmode,
3925 plus_constant (base, offset + 4));
3926 rtx regl = gen_rtx_REG (SFmode, i);
3927 rtx regr = gen_rtx_REG (SFmode, i + 1);
3928 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3929 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3932 RTX_FRAME_RELATED_P (setl) = 1;
3933 RTX_FRAME_RELATED_P (setr) = 1;
3934 vec = gen_rtvec (2, setl, setr);
3936 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3937 gen_rtx_SEQUENCE (VOIDmode, vec),
3941 offset += GET_MODE_SIZE (DFmode);
3948 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3949 Handle case where DISP > 8k by using the add_high_const patterns. */
3952 load_reg (int reg, HOST_WIDE_INT disp, int base)
3954 rtx dest = gen_rtx_REG (word_mode, reg);
3955 rtx basereg = gen_rtx_REG (Pmode, base);
3958 if (VAL_14_BITS_P (disp))
3959 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3960 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3962 rtx delta = GEN_INT (disp);
3963 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3965 emit_move_insn (tmpreg, delta);
3966 if (TARGET_DISABLE_INDEXING)
3968 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3969 src = gen_rtx_MEM (word_mode, tmpreg);
3972 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3976 rtx delta = GEN_INT (disp);
3977 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3978 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3980 emit_move_insn (tmpreg, high);
3981 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3984 emit_move_insn (dest, src);
3987 /* Update the total code bytes output to the text section. */
3990 update_total_code_bytes (int nbytes)
3992 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3993 && !IN_NAMED_SECTION_P (cfun->decl))
3995 if (INSN_ADDRESSES_SET_P ())
3997 unsigned long old_total = total_code_bytes;
3999 total_code_bytes += nbytes;
4001 /* Be prepared to handle overflows. */
4002 if (old_total > total_code_bytes)
4003 total_code_bytes = -1;
4006 total_code_bytes = -1;
4010 /* This function generates the assembly code for function exit.
4011 Args are as for output_function_prologue ().
4013 The function epilogue should not depend on the current stack
4014 pointer! It should use the frame pointer only. This is mandatory
4015 because of alloca; we also take advantage of it to omit stack
4016 adjustments before returning. */
4019 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4021 rtx insn = get_last_insn ();
4025 /* hppa_expand_epilogue does the dirty work now. We just need
4026 to output the assembler directives which denote the end
4029 To make debuggers happy, emit a nop if the epilogue was completely
4030 eliminated due to a volatile call as the last insn in the
4031 current function. That way the return address (in %r2) will
4032 always point to a valid instruction in the current function. */
4034 /* Get the last real insn. */
4035 if (GET_CODE (insn) == NOTE)
4036 insn = prev_real_insn (insn);
4038 /* If it is a sequence, then look inside. */
4039 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4040 insn = XVECEXP (PATTERN (insn), 0, 0);
4042 /* If insn is a CALL_INSN, then it must be a call to a volatile
4043 function (otherwise there would be epilogue insns). */
4044 if (insn && GET_CODE (insn) == CALL_INSN)
4046 fputs ("\tnop\n", file);
4050 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4052 if (TARGET_SOM && TARGET_GAS)
4054 /* We done with this subspace except possibly for some additional
4055 debug information. Forget that we are in this subspace to ensure
4056 that the next function is output in its own subspace. */
4058 cfun->machine->in_nsubspa = 2;
4061 if (INSN_ADDRESSES_SET_P ())
4063 insn = get_last_nonnote_insn ();
4064 last_address += INSN_ADDRESSES (INSN_UID (insn));
4066 last_address += insn_default_length (insn);
4067 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4068 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4071 /* Finally, update the total number of code bytes output so far. */
4072 update_total_code_bytes (last_address);
4076 hppa_expand_epilogue (void)
4079 HOST_WIDE_INT offset;
4080 HOST_WIDE_INT ret_off = 0;
4082 int merge_sp_adjust_with_load = 0;
4084 /* We will use this often. */
4085 tmpreg = gen_rtx_REG (word_mode, 1);
4087 /* Try to restore RP early to avoid load/use interlocks when
4088 RP gets used in the return (bv) instruction. This appears to still
4089 be necessary even when we schedule the prologue and epilogue. */
4092 ret_off = TARGET_64BIT ? -16 : -20;
4093 if (frame_pointer_needed)
4095 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4100 /* No frame pointer, and stack is smaller than 8k. */
4101 if (VAL_14_BITS_P (ret_off - actual_fsize))
4103 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4109 /* General register restores. */
4110 if (frame_pointer_needed)
4112 offset = local_fsize;
4114 /* If the current function calls __builtin_eh_return, then we need
4115 to restore the saved EH data registers. */
4116 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4118 unsigned int i, regno;
4122 regno = EH_RETURN_DATA_REGNO (i);
4123 if (regno == INVALID_REGNUM)
4126 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4127 offset += UNITS_PER_WORD;
4131 for (i = 18; i >= 4; i--)
4132 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4134 load_reg (i, offset, FRAME_POINTER_REGNUM);
4135 offset += UNITS_PER_WORD;
4140 offset = local_fsize - actual_fsize;
4142 /* If the current function calls __builtin_eh_return, then we need
4143 to restore the saved EH data registers. */
4144 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4146 unsigned int i, regno;
4150 regno = EH_RETURN_DATA_REGNO (i);
4151 if (regno == INVALID_REGNUM)
4154 /* Only for the first load.
4155 merge_sp_adjust_with_load holds the register load
4156 with which we will merge the sp adjustment. */
4157 if (merge_sp_adjust_with_load == 0
4159 && VAL_14_BITS_P (-actual_fsize))
4160 merge_sp_adjust_with_load = regno;
4162 load_reg (regno, offset, STACK_POINTER_REGNUM);
4163 offset += UNITS_PER_WORD;
4167 for (i = 18; i >= 3; i--)
4169 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4171 /* Only for the first load.
4172 merge_sp_adjust_with_load holds the register load
4173 with which we will merge the sp adjustment. */
4174 if (merge_sp_adjust_with_load == 0
4176 && VAL_14_BITS_P (-actual_fsize))
4177 merge_sp_adjust_with_load = i;
4179 load_reg (i, offset, STACK_POINTER_REGNUM);
4180 offset += UNITS_PER_WORD;
4185 /* Align pointer properly (doubleword boundary). */
4186 offset = (offset + 7) & ~7;
4188 /* FP register restores. */
4191 /* Adjust the register to index off of. */
4192 if (frame_pointer_needed)
4193 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4195 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4197 /* Actually do the restores now. */
4198 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4199 if (df_regs_ever_live_p (i)
4200 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4202 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4203 rtx dest = gen_rtx_REG (DFmode, i);
4204 emit_move_insn (dest, src);
4208 /* Emit a blockage insn here to keep these insns from being moved to
4209 an earlier spot in the epilogue, or into the main instruction stream.
4211 This is necessary as we must not cut the stack back before all the
4212 restores are finished. */
4213 emit_insn (gen_blockage ());
4215 /* Reset stack pointer (and possibly frame pointer). The stack
4216 pointer is initially set to fp + 64 to avoid a race condition. */
4217 if (frame_pointer_needed)
4219 rtx delta = GEN_INT (-64);
4221 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4222 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4224 /* If we were deferring a callee register restore, do it now. */
4225 else if (merge_sp_adjust_with_load)
4227 rtx delta = GEN_INT (-actual_fsize);
4228 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4230 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4232 else if (actual_fsize != 0)
4233 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4236 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4237 frame greater than 8k), do so now. */
4239 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4241 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4243 rtx sa = EH_RETURN_STACKADJ_RTX;
4245 emit_insn (gen_blockage ());
4246 emit_insn (TARGET_64BIT
4247 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4248 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4253 hppa_pic_save_rtx (void)
4255 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4258 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4259 #define NO_DEFERRED_PROFILE_COUNTERS 0
4263 /* Vector of funcdef numbers. */
4264 static VEC(int,heap) *funcdef_nos;
4266 /* Output deferred profile counters. */
4268 output_deferred_profile_counters (void)
4273 if (VEC_empty (int, funcdef_nos))
4276 switch_to_section (data_section);
4277 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4278 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4280 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4282 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4283 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4286 VEC_free (int, heap, funcdef_nos);
4290 hppa_profile_hook (int label_no)
4292 /* We use SImode for the address of the function in both 32 and
4293 64-bit code to avoid having to provide DImode versions of the
4294 lcla2 and load_offset_label_address insn patterns. */
4295 rtx reg = gen_reg_rtx (SImode);
4296 rtx label_rtx = gen_label_rtx ();
4297 rtx begin_label_rtx, call_insn;
4298 char begin_label_name[16];
4300 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4302 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4305 emit_move_insn (arg_pointer_rtx,
4306 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4309 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4311 /* The address of the function is loaded into %r25 with an instruction-
4312 relative sequence that avoids the use of relocations. The sequence
4313 is split so that the load_offset_label_address instruction can
4314 occupy the delay slot of the call to _mcount. */
4316 emit_insn (gen_lcla2 (reg, label_rtx));
4318 emit_insn (gen_lcla1 (reg, label_rtx));
4320 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4321 reg, begin_label_rtx, label_rtx));
4323 #if !NO_DEFERRED_PROFILE_COUNTERS
4325 rtx count_label_rtx, addr, r24;
4326 char count_label_name[16];
4328 VEC_safe_push (int, heap, funcdef_nos, label_no);
4329 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4330 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4332 addr = force_reg (Pmode, count_label_rtx);
4333 r24 = gen_rtx_REG (Pmode, 24);
4334 emit_move_insn (r24, addr);
4337 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4338 gen_rtx_SYMBOL_REF (Pmode,
4340 GEN_INT (TARGET_64BIT ? 24 : 12)));
4342 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4347 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4348 gen_rtx_SYMBOL_REF (Pmode,
4350 GEN_INT (TARGET_64BIT ? 16 : 8)));
4354 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4355 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4357 /* Indicate the _mcount call cannot throw, nor will it execute a
4359 REG_NOTES (call_insn)
4360 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4363 /* Fetch the return address for the frame COUNT steps up from
4364 the current frame, after the prologue. FRAMEADDR is the
4365 frame pointer of the COUNT frame.
4367 We want to ignore any export stub remnants here. To handle this,
4368 we examine the code at the return address, and if it is an export
4369 stub, we return a memory rtx for the stub return address stored
4372 The value returned is used in two different ways:
4374 1. To find a function's caller.
4376 2. To change the return address for a function.
4378 This function handles most instances of case 1; however, it will
4379 fail if there are two levels of stubs to execute on the return
4380 path. The only way I believe that can happen is if the return value
4381 needs a parameter relocation, which never happens for C code.
4383 This function handles most instances of case 2; however, it will
4384 fail if we did not originally have stub code on the return path
4385 but will need stub code on the new return path. This can happen if
4386 the caller & callee are both in the main program, but the new
4387 return location is in a shared library. */
4390 return_addr_rtx (int count, rtx frameaddr)
4400 rp = get_hard_reg_initial_val (Pmode, 2);
4402 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4405 saved_rp = gen_reg_rtx (Pmode);
4406 emit_move_insn (saved_rp, rp);
4408 /* Get pointer to the instruction stream. We have to mask out the
4409 privilege level from the two low order bits of the return address
4410 pointer here so that ins will point to the start of the first
4411 instruction that would have been executed if we returned. */
4412 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4413 label = gen_label_rtx ();
4415 /* Check the instruction stream at the normal return address for the
4418 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4419 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4420 0x00011820 | stub+16: mtsp r1,sr0
4421 0xe0400002 | stub+20: be,n 0(sr0,rp)
4423 If it is an export stub, than our return address is really in
4426 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4427 NULL_RTX, SImode, 1);
4428 emit_jump_insn (gen_bne (label));
4430 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4431 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4432 emit_jump_insn (gen_bne (label));
4434 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4435 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4436 emit_jump_insn (gen_bne (label));
4438 /* 0xe0400002 must be specified as -532676606 so that it won't be
4439 rejected as an invalid immediate operand on 64-bit hosts. */
4440 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4441 GEN_INT (-532676606), NE, NULL_RTX, SImode, 1);
4443 /* If there is no export stub then just use the value saved from
4444 the return pointer register. */
4446 emit_jump_insn (gen_bne (label));
4448 /* Here we know that our return address points to an export
4449 stub. We don't want to return the address of the export stub,
4450 but rather the return address of the export stub. That return
4451 address is stored at -24[frameaddr]. */
4453 emit_move_insn (saved_rp,
4455 memory_address (Pmode,
4456 plus_constant (frameaddr,
4464 emit_bcond_fp (enum rtx_code code, rtx operand0)
4466 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4467 gen_rtx_IF_THEN_ELSE (VOIDmode,
4468 gen_rtx_fmt_ee (code,
4470 gen_rtx_REG (CCFPmode, 0),
4472 gen_rtx_LABEL_REF (VOIDmode, operand0),
4478 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4480 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4481 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4484 /* Adjust the cost of a scheduling dependency. Return the new cost of
4485 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4488 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4490 enum attr_type attr_type;
4492 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4493 true dependencies as they are described with bypasses now. */
4494 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4497 if (! recog_memoized (insn))
4500 attr_type = get_attr_type (insn);
4502 switch (REG_NOTE_KIND (link))
4505 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4508 if (attr_type == TYPE_FPLOAD)
4510 rtx pat = PATTERN (insn);
4511 rtx dep_pat = PATTERN (dep_insn);
4512 if (GET_CODE (pat) == PARALLEL)
4514 /* This happens for the fldXs,mb patterns. */
4515 pat = XVECEXP (pat, 0, 0);
4517 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4518 /* If this happens, we have to extend this to schedule
4519 optimally. Return 0 for now. */
4522 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4524 if (! recog_memoized (dep_insn))
4526 switch (get_attr_type (dep_insn))
4533 case TYPE_FPSQRTSGL:
4534 case TYPE_FPSQRTDBL:
4535 /* A fpload can't be issued until one cycle before a
4536 preceding arithmetic operation has finished if
4537 the target of the fpload is any of the sources
4538 (or destination) of the arithmetic operation. */
4539 return insn_default_latency (dep_insn) - 1;
4546 else if (attr_type == TYPE_FPALU)
4548 rtx pat = PATTERN (insn);
4549 rtx dep_pat = PATTERN (dep_insn);
4550 if (GET_CODE (pat) == PARALLEL)
4552 /* This happens for the fldXs,mb patterns. */
4553 pat = XVECEXP (pat, 0, 0);
4555 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4556 /* If this happens, we have to extend this to schedule
4557 optimally. Return 0 for now. */
4560 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4562 if (! recog_memoized (dep_insn))
4564 switch (get_attr_type (dep_insn))
4568 case TYPE_FPSQRTSGL:
4569 case TYPE_FPSQRTDBL:
4570 /* An ALU flop can't be issued until two cycles before a
4571 preceding divide or sqrt operation has finished if
4572 the target of the ALU flop is any of the sources
4573 (or destination) of the divide or sqrt operation. */
4574 return insn_default_latency (dep_insn) - 2;
4582 /* For other anti dependencies, the cost is 0. */
4585 case REG_DEP_OUTPUT:
4586 /* Output dependency; DEP_INSN writes a register that INSN writes some
4588 if (attr_type == TYPE_FPLOAD)
4590 rtx pat = PATTERN (insn);
4591 rtx dep_pat = PATTERN (dep_insn);
4592 if (GET_CODE (pat) == PARALLEL)
4594 /* This happens for the fldXs,mb patterns. */
4595 pat = XVECEXP (pat, 0, 0);
4597 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4598 /* If this happens, we have to extend this to schedule
4599 optimally. Return 0 for now. */
4602 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4604 if (! recog_memoized (dep_insn))
4606 switch (get_attr_type (dep_insn))
4613 case TYPE_FPSQRTSGL:
4614 case TYPE_FPSQRTDBL:
4615 /* A fpload can't be issued until one cycle before a
4616 preceding arithmetic operation has finished if
4617 the target of the fpload is the destination of the
4618 arithmetic operation.
4620 Exception: For PA7100LC, PA7200 and PA7300, the cost
4621 is 3 cycles, unless they bundle together. We also
4622 pay the penalty if the second insn is a fpload. */
4623 return insn_default_latency (dep_insn) - 1;
4630 else if (attr_type == TYPE_FPALU)
4632 rtx pat = PATTERN (insn);
4633 rtx dep_pat = PATTERN (dep_insn);
4634 if (GET_CODE (pat) == PARALLEL)
4636 /* This happens for the fldXs,mb patterns. */
4637 pat = XVECEXP (pat, 0, 0);
4639 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4640 /* If this happens, we have to extend this to schedule
4641 optimally. Return 0 for now. */
4644 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4646 if (! recog_memoized (dep_insn))
4648 switch (get_attr_type (dep_insn))
4652 case TYPE_FPSQRTSGL:
4653 case TYPE_FPSQRTDBL:
4654 /* An ALU flop can't be issued until two cycles before a
4655 preceding divide or sqrt operation has finished if
4656 the target of the ALU flop is also the target of
4657 the divide or sqrt operation. */
4658 return insn_default_latency (dep_insn) - 2;
4666 /* For other output dependencies, the cost is 0. */
4674 /* Adjust scheduling priorities. We use this to try and keep addil
4675 and the next use of %r1 close together. */
4677 pa_adjust_priority (rtx insn, int priority)
4679 rtx set = single_set (insn);
4683 src = SET_SRC (set);
4684 dest = SET_DEST (set);
4685 if (GET_CODE (src) == LO_SUM
4686 && symbolic_operand (XEXP (src, 1), VOIDmode)
4687 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4690 else if (GET_CODE (src) == MEM
4691 && GET_CODE (XEXP (src, 0)) == LO_SUM
4692 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4693 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4696 else if (GET_CODE (dest) == MEM
4697 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4698 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4699 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4705 /* The 700 can only issue a single insn at a time.
4706 The 7XXX processors can issue two insns at a time.
4707 The 8000 can issue 4 insns at a time. */
4709 pa_issue_rate (void)
4713 case PROCESSOR_700: return 1;
4714 case PROCESSOR_7100: return 2;
4715 case PROCESSOR_7100LC: return 2;
4716 case PROCESSOR_7200: return 2;
4717 case PROCESSOR_7300: return 2;
4718 case PROCESSOR_8000: return 4;
4727 /* Return any length adjustment needed by INSN which already has its length
4728 computed as LENGTH. Return zero if no adjustment is necessary.
4730 For the PA: function calls, millicode calls, and backwards short
4731 conditional branches with unfilled delay slots need an adjustment by +1
4732 (to account for the NOP which will be inserted into the instruction stream).
4734 Also compute the length of an inline block move here as it is too
4735 complicated to express as a length attribute in pa.md. */
4737 pa_adjust_insn_length (rtx insn, int length)
4739 rtx pat = PATTERN (insn);
4741 /* Jumps inside switch tables which have unfilled delay slots need
4743 if (GET_CODE (insn) == JUMP_INSN
4744 && GET_CODE (pat) == PARALLEL
4745 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4747 /* Millicode insn with an unfilled delay slot. */
4748 else if (GET_CODE (insn) == INSN
4749 && GET_CODE (pat) != SEQUENCE
4750 && GET_CODE (pat) != USE
4751 && GET_CODE (pat) != CLOBBER
4752 && get_attr_type (insn) == TYPE_MILLI)
4754 /* Block move pattern. */
4755 else if (GET_CODE (insn) == INSN
4756 && GET_CODE (pat) == PARALLEL
4757 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4758 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4759 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4760 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4761 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4762 return compute_movmem_length (insn) - 4;
4763 /* Block clear pattern. */
4764 else if (GET_CODE (insn) == INSN
4765 && GET_CODE (pat) == PARALLEL
4766 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4767 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4768 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4769 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4770 return compute_clrmem_length (insn) - 4;
4771 /* Conditional branch with an unfilled delay slot. */
4772 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4774 /* Adjust a short backwards conditional with an unfilled delay slot. */
4775 if (GET_CODE (pat) == SET
4777 && ! forward_branch_p (insn))
4779 else if (GET_CODE (pat) == PARALLEL
4780 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4783 /* Adjust dbra insn with short backwards conditional branch with
4784 unfilled delay slot -- only for case where counter is in a
4785 general register register. */
4786 else if (GET_CODE (pat) == PARALLEL
4787 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4788 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4789 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4791 && ! forward_branch_p (insn))
4799 /* Print operand X (an rtx) in assembler syntax to file FILE.
4800 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4801 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4804 print_operand (FILE *file, rtx x, int code)
4809 /* Output a 'nop' if there's nothing for the delay slot. */
4810 if (dbr_sequence_length () == 0)
4811 fputs ("\n\tnop", file);
4814 /* Output a nullification completer if there's nothing for the */
4815 /* delay slot or nullification is requested. */
4816 if (dbr_sequence_length () == 0 ||
4818 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4822 /* Print out the second register name of a register pair.
4823 I.e., R (6) => 7. */
4824 fputs (reg_names[REGNO (x) + 1], file);
4827 /* A register or zero. */
4829 || (x == CONST0_RTX (DFmode))
4830 || (x == CONST0_RTX (SFmode)))
4832 fputs ("%r0", file);
4838 /* A register or zero (floating point). */
4840 || (x == CONST0_RTX (DFmode))
4841 || (x == CONST0_RTX (SFmode)))
4843 fputs ("%fr0", file);
4852 xoperands[0] = XEXP (XEXP (x, 0), 0);
4853 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4854 output_global_address (file, xoperands[1], 0);
4855 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4859 case 'C': /* Plain (C)ondition */
4861 switch (GET_CODE (x))
4864 fputs ("=", file); break;
4866 fputs ("<>", file); break;
4868 fputs (">", file); break;
4870 fputs (">=", file); break;
4872 fputs (">>=", file); break;
4874 fputs (">>", file); break;
4876 fputs ("<", file); break;
4878 fputs ("<=", file); break;
4880 fputs ("<<=", file); break;
4882 fputs ("<<", file); break;
4887 case 'N': /* Condition, (N)egated */
4888 switch (GET_CODE (x))
4891 fputs ("<>", file); break;
4893 fputs ("=", file); break;
4895 fputs ("<=", file); break;
4897 fputs ("<", file); break;
4899 fputs ("<<", file); break;
4901 fputs ("<<=", file); break;
4903 fputs (">=", file); break;
4905 fputs (">", file); break;
4907 fputs (">>", file); break;
4909 fputs (">>=", file); break;
4914 /* For floating point comparisons. Note that the output
4915 predicates are the complement of the desired mode. The
4916 conditions for GT, GE, LT, LE and LTGT cause an invalid
4917 operation exception if the result is unordered and this
4918 exception is enabled in the floating-point status register. */
4920 switch (GET_CODE (x))
4923 fputs ("!=", file); break;
4925 fputs ("=", file); break;
4927 fputs ("!>", file); break;
4929 fputs ("!>=", file); break;
4931 fputs ("!<", file); break;
4933 fputs ("!<=", file); break;
4935 fputs ("!<>", file); break;
4937 fputs ("!?<=", file); break;
4939 fputs ("!?<", file); break;
4941 fputs ("!?>=", file); break;
4943 fputs ("!?>", file); break;
4945 fputs ("!?=", file); break;
4947 fputs ("!?", file); break;
4949 fputs ("?", file); break;
4954 case 'S': /* Condition, operands are (S)wapped. */
4955 switch (GET_CODE (x))
4958 fputs ("=", file); break;
4960 fputs ("<>", file); break;
4962 fputs ("<", file); break;
4964 fputs ("<=", file); break;
4966 fputs ("<<=", file); break;
4968 fputs ("<<", file); break;
4970 fputs (">", file); break;
4972 fputs (">=", file); break;
4974 fputs (">>=", file); break;
4976 fputs (">>", file); break;
4981 case 'B': /* Condition, (B)oth swapped and negate. */
4982 switch (GET_CODE (x))
4985 fputs ("<>", file); break;
4987 fputs ("=", file); break;
4989 fputs (">=", file); break;
4991 fputs (">", file); break;
4993 fputs (">>", file); break;
4995 fputs (">>=", file); break;
4997 fputs ("<=", file); break;
4999 fputs ("<", file); break;
5001 fputs ("<<", file); break;
5003 fputs ("<<=", file); break;
5009 gcc_assert (GET_CODE (x) == CONST_INT);
5010 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5013 gcc_assert (GET_CODE (x) == CONST_INT);
5014 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5017 gcc_assert (GET_CODE (x) == CONST_INT);
5018 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5021 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5022 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5025 gcc_assert (GET_CODE (x) == CONST_INT);
5026 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5029 gcc_assert (GET_CODE (x) == CONST_INT);
5030 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5033 if (GET_CODE (x) == CONST_INT)
5038 switch (GET_CODE (XEXP (x, 0)))
5042 if (ASSEMBLER_DIALECT == 0)
5043 fputs ("s,mb", file);
5045 fputs (",mb", file);
5049 if (ASSEMBLER_DIALECT == 0)
5050 fputs ("s,ma", file);
5052 fputs (",ma", file);
5055 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5056 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5058 if (ASSEMBLER_DIALECT == 0)
5061 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5062 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5064 if (ASSEMBLER_DIALECT == 0)
5065 fputs ("x,s", file);
5069 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5073 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5079 output_global_address (file, x, 0);
5082 output_global_address (file, x, 1);
5084 case 0: /* Don't do anything special */
5089 compute_zdepwi_operands (INTVAL (x), op);
5090 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5096 compute_zdepdi_operands (INTVAL (x), op);
5097 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5101 /* We can get here from a .vtable_inherit due to our
5102 CONSTANT_ADDRESS_P rejecting perfectly good constant
5108 if (GET_CODE (x) == REG)
5110 fputs (reg_names [REGNO (x)], file);
5111 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5117 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5118 && (REGNO (x) & 1) == 0)
5121 else if (GET_CODE (x) == MEM)
5123 int size = GET_MODE_SIZE (GET_MODE (x));
5124 rtx base = NULL_RTX;
5125 switch (GET_CODE (XEXP (x, 0)))
5129 base = XEXP (XEXP (x, 0), 0);
5130 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5134 base = XEXP (XEXP (x, 0), 0);
5135 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5138 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5139 fprintf (file, "%s(%s)",
5140 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5141 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5142 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5143 fprintf (file, "%s(%s)",
5144 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5145 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5146 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5147 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5149 /* Because the REG_POINTER flag can get lost during reload,
5150 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5151 index and base registers in the combined move patterns. */
5152 rtx base = XEXP (XEXP (x, 0), 1);
5153 rtx index = XEXP (XEXP (x, 0), 0);
5155 fprintf (file, "%s(%s)",
5156 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5159 output_address (XEXP (x, 0));
5162 output_address (XEXP (x, 0));
5167 output_addr_const (file, x);
5170 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5173 output_global_address (FILE *file, rtx x, int round_constant)
5176 /* Imagine (high (const (plus ...))). */
5177 if (GET_CODE (x) == HIGH)
5180 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5181 output_addr_const (file, x);
5182 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5184 output_addr_const (file, x);
5185 fputs ("-$global$", file);
5187 else if (GET_CODE (x) == CONST)
5189 const char *sep = "";
5190 int offset = 0; /* assembler wants -$global$ at end */
5191 rtx base = NULL_RTX;
5193 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5196 base = XEXP (XEXP (x, 0), 0);
5197 output_addr_const (file, base);
5200 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5206 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5209 base = XEXP (XEXP (x, 0), 1);
5210 output_addr_const (file, base);
5213 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5219 /* How bogus. The compiler is apparently responsible for
5220 rounding the constant if it uses an LR field selector.
5222 The linker and/or assembler seem a better place since
5223 they have to do this kind of thing already.
5225 If we fail to do this, HP's optimizing linker may eliminate
5226 an addil, but not update the ldw/stw/ldo instruction that
5227 uses the result of the addil. */
5229 offset = ((offset + 0x1000) & ~0x1fff);
5231 switch (GET_CODE (XEXP (x, 0)))
5244 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5252 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5253 fputs ("-$global$", file);
5255 fprintf (file, "%s%d", sep, offset);
5258 output_addr_const (file, x);
5261 /* Output boilerplate text to appear at the beginning of the file.
5262 There are several possible versions. */
5263 #define aputs(x) fputs(x, asm_out_file)
5265 pa_file_start_level (void)
5268 aputs ("\t.LEVEL 2.0w\n");
5269 else if (TARGET_PA_20)
5270 aputs ("\t.LEVEL 2.0\n");
5271 else if (TARGET_PA_11)
5272 aputs ("\t.LEVEL 1.1\n");
5274 aputs ("\t.LEVEL 1.0\n");
5278 pa_file_start_space (int sortspace)
5280 aputs ("\t.SPACE $PRIVATE$");
5283 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5284 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5285 "\n\t.SPACE $TEXT$");
5288 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5289 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5293 pa_file_start_file (int want_version)
5295 if (write_symbols != NO_DEBUG)
5297 output_file_directive (asm_out_file, main_input_filename);
5299 aputs ("\t.version\t\"01.01\"\n");
5304 pa_file_start_mcount (const char *aswhat)
5307 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5311 pa_elf_file_start (void)
5313 pa_file_start_level ();
5314 pa_file_start_mcount ("ENTRY");
5315 pa_file_start_file (0);
5319 pa_som_file_start (void)
5321 pa_file_start_level ();
5322 pa_file_start_space (0);
5323 aputs ("\t.IMPORT $global$,DATA\n"
5324 "\t.IMPORT $$dyncall,MILLICODE\n");
5325 pa_file_start_mcount ("CODE");
5326 pa_file_start_file (0);
5330 pa_linux_file_start (void)
5332 pa_file_start_file (1);
5333 pa_file_start_level ();
5334 pa_file_start_mcount ("CODE");
5338 pa_hpux64_gas_file_start (void)
5340 pa_file_start_level ();
5341 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5343 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5345 pa_file_start_file (1);
5349 pa_hpux64_hpas_file_start (void)
5351 pa_file_start_level ();
5352 pa_file_start_space (1);
5353 pa_file_start_mcount ("CODE");
5354 pa_file_start_file (0);
5358 /* Search the deferred plabel list for SYMBOL and return its internal
5359 label. If an entry for SYMBOL is not found, a new entry is created. */
5362 get_deferred_plabel (rtx symbol)
5364 const char *fname = XSTR (symbol, 0);
5367 /* See if we have already put this function on the list of deferred
5368 plabels. This list is generally small, so a liner search is not
5369 too ugly. If it proves too slow replace it with something faster. */
5370 for (i = 0; i < n_deferred_plabels; i++)
5371 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5374 /* If the deferred plabel list is empty, or this entry was not found
5375 on the list, create a new entry on the list. */
5376 if (deferred_plabels == NULL || i == n_deferred_plabels)
5380 if (deferred_plabels == 0)
5381 deferred_plabels = (struct deferred_plabel *)
5382 ggc_alloc (sizeof (struct deferred_plabel));
5384 deferred_plabels = (struct deferred_plabel *)
5385 ggc_realloc (deferred_plabels,
5386 ((n_deferred_plabels + 1)
5387 * sizeof (struct deferred_plabel)));
5389 i = n_deferred_plabels++;
5390 deferred_plabels[i].internal_label = gen_label_rtx ();
5391 deferred_plabels[i].symbol = symbol;
5393 /* Gross. We have just implicitly taken the address of this
5394 function. Mark it in the same manner as assemble_name. */
5395 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5397 mark_referenced (id);
5400 return deferred_plabels[i].internal_label;
5404 output_deferred_plabels (void)
5408 /* If we have some deferred plabels, then we need to switch into the
5409 data or readonly data section, and align it to a 4 byte boundary
5410 before outputting the deferred plabels. */
5411 if (n_deferred_plabels)
5413 switch_to_section (flag_pic ? data_section : readonly_data_section);
5414 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5417 /* Now output the deferred plabels. */
5418 for (i = 0; i < n_deferred_plabels; i++)
5420 targetm.asm_out.internal_label (asm_out_file, "L",
5421 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5422 assemble_integer (deferred_plabels[i].symbol,
5423 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5427 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5428 /* Initialize optabs to point to HPUX long double emulation routines. */
5430 pa_hpux_init_libfuncs (void)
5432 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5433 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5434 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5435 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5436 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5437 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5438 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5439 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5440 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5442 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5443 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5444 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5445 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5446 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5447 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5448 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5450 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5451 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5452 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5453 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5455 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5456 ? "__U_Qfcnvfxt_quad_to_sgl"
5457 : "_U_Qfcnvfxt_quad_to_sgl");
5458 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5459 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5460 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5462 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5463 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5464 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5465 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5469 /* HP's millicode routines mean something special to the assembler.
5470 Keep track of which ones we have used. */
5472 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5473 static void import_milli (enum millicodes);
5474 static char imported[(int) end1000];
5475 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5476 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5477 #define MILLI_START 10
5480 import_milli (enum millicodes code)
5482 char str[sizeof (import_string)];
5484 if (!imported[(int) code])
5486 imported[(int) code] = 1;
5487 strcpy (str, import_string);
5488 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5489 output_asm_insn (str, 0);
5493 /* The register constraints have put the operands and return value in
5494 the proper registers. */
5497 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5499 import_milli (mulI);
5500 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5503 /* Emit the rtl for doing a division by a constant. */
5505 /* Do magic division millicodes exist for this value? */
5506 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5508 /* We'll use an array to keep track of the magic millicodes and
5509 whether or not we've used them already. [n][0] is signed, [n][1] is
5512 static int div_milli[16][2];
5515 emit_hpdiv_const (rtx *operands, int unsignedp)
5517 if (GET_CODE (operands[2]) == CONST_INT
5518 && INTVAL (operands[2]) > 0
5519 && INTVAL (operands[2]) < 16
5520 && magic_milli[INTVAL (operands[2])])
5522 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5524 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5528 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5529 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5531 gen_rtx_REG (SImode, 26),
5533 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5534 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5535 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5536 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5537 gen_rtx_CLOBBER (VOIDmode, ret))));
5538 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5545 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5549 /* If the divisor is a constant, try to use one of the special
5551 if (GET_CODE (operands[0]) == CONST_INT)
5553 static char buf[100];
5554 divisor = INTVAL (operands[0]);
5555 if (!div_milli[divisor][unsignedp])
5557 div_milli[divisor][unsignedp] = 1;
5559 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5561 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5565 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5566 INTVAL (operands[0]));
5567 return output_millicode_call (insn,
5568 gen_rtx_SYMBOL_REF (SImode, buf));
5572 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5573 INTVAL (operands[0]));
5574 return output_millicode_call (insn,
5575 gen_rtx_SYMBOL_REF (SImode, buf));
5578 /* Divisor isn't a special constant. */
5583 import_milli (divU);
5584 return output_millicode_call (insn,
5585 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5589 import_milli (divI);
5590 return output_millicode_call (insn,
5591 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5596 /* Output a $$rem millicode to do mod. */
5599 output_mod_insn (int unsignedp, rtx insn)
5603 import_milli (remU);
5604 return output_millicode_call (insn,
5605 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5609 import_milli (remI);
5610 return output_millicode_call (insn,
5611 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5616 output_arg_descriptor (rtx call_insn)
5618 const char *arg_regs[4];
5619 enum machine_mode arg_mode;
5621 int i, output_flag = 0;
5624 /* We neither need nor want argument location descriptors for the
5625 64bit runtime environment or the ELF32 environment. */
5626 if (TARGET_64BIT || TARGET_ELF32)
5629 for (i = 0; i < 4; i++)
5632 /* Specify explicitly that no argument relocations should take place
5633 if using the portable runtime calling conventions. */
5634 if (TARGET_PORTABLE_RUNTIME)
5636 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5641 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5642 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5643 link; link = XEXP (link, 1))
5645 rtx use = XEXP (link, 0);
5647 if (! (GET_CODE (use) == USE
5648 && GET_CODE (XEXP (use, 0)) == REG
5649 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5652 arg_mode = GET_MODE (XEXP (use, 0));
5653 regno = REGNO (XEXP (use, 0));
5654 if (regno >= 23 && regno <= 26)
5656 arg_regs[26 - regno] = "GR";
5657 if (arg_mode == DImode)
5658 arg_regs[25 - regno] = "GR";
5660 else if (regno >= 32 && regno <= 39)
5662 if (arg_mode == SFmode)
5663 arg_regs[(regno - 32) / 2] = "FR";
5666 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5667 arg_regs[(regno - 34) / 2] = "FR";
5668 arg_regs[(regno - 34) / 2 + 1] = "FU";
5670 arg_regs[(regno - 34) / 2] = "FU";
5671 arg_regs[(regno - 34) / 2 + 1] = "FR";
5676 fputs ("\t.CALL ", asm_out_file);
5677 for (i = 0; i < 4; i++)
5682 fputc (',', asm_out_file);
5683 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5686 fputc ('\n', asm_out_file);
5689 static enum reg_class
5690 pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
5691 enum machine_mode mode, secondary_reload_info *sri)
5693 int is_symbolic, regno;
5695 /* Handle the easy stuff first. */
5696 if (class == R1_REGS)
5702 if (class == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5708 /* If we have something like (mem (mem (...)), we can safely assume the
5709 inner MEM will end up in a general register after reloading, so there's
5710 no need for a secondary reload. */
5711 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5714 /* Trying to load a constant into a FP register during PIC code
5715 generation requires %r1 as a scratch register. */
5717 && (mode == SImode || mode == DImode)
5718 && FP_REG_CLASS_P (class)
5719 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5721 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5722 : CODE_FOR_reload_indi_r1);
5726 /* Profiling showed the PA port spends about 1.3% of its compilation
5727 time in true_regnum from calls inside pa_secondary_reload_class. */
5728 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5729 regno = true_regnum (x);
5731 /* In order to allow 14-bit displacements in integer loads and stores,
5732 we need to prevent reload from generating out of range integer mode
5733 loads and stores to the floating point registers. Previously, we
5734 used to call for a secondary reload and have emit_move_sequence()
5735 fix the instruction sequence. However, reload occasionally wouldn't
5736 generate the reload and we would end up with an invalid REG+D memory
5737 address. So, now we use an intermediate general register for most
5738 memory loads and stores. */
5739 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5740 && GET_MODE_CLASS (mode) == MODE_INT
5741 && FP_REG_CLASS_P (class))
5743 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5744 the secondary reload needed for a pseudo. It never passes a
5746 if (GET_CODE (x) == MEM)
5750 /* We don't need an intermediate for indexed and LO_SUM DLT
5751 memory addresses. When INT14_OK_STRICT is true, it might
5752 appear that we could directly allow register indirect
5753 memory addresses. However, this doesn't work because we
5754 don't support SUBREGs in floating-point register copies
5755 and reload doesn't tell us when it's going to use a SUBREG. */
5756 if (IS_INDEX_ADDR_P (x)
5757 || IS_LO_SUM_DLT_ADDR_P (x))
5760 /* Otherwise, we need an intermediate general register. */
5761 return GENERAL_REGS;
5764 /* Request a secondary reload with a general scratch register
5765 for everthing else. ??? Could symbolic operands be handled
5766 directly when generating non-pic PA 2.0 code? */
5767 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5771 /* We need a secondary register (GPR) for copies between the SAR
5772 and anything other than a general register. */
5773 if (class == SHIFT_REGS && (regno <= 0 || regno >= 32))
5775 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5779 /* A SAR<->FP register copy requires a secondary register (GPR) as
5780 well as secondary memory. */
5781 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5782 && (REGNO_REG_CLASS (regno) == SHIFT_REGS
5783 && FP_REG_CLASS_P (class)))
5785 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5789 /* Secondary reloads of symbolic operands require %r1 as a scratch
5790 register when we're generating PIC code and when the operand isn't
5792 if (GET_CODE (x) == HIGH)
5795 /* Profiling has showed GCC spends about 2.6% of its compilation
5796 time in symbolic_operand from calls inside pa_secondary_reload_class.
5797 So, we use an inline copy to avoid useless work. */
5798 switch (GET_CODE (x))
5803 is_symbolic = !SYMBOL_REF_TLS_MODEL (x);
5810 is_symbolic = (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5811 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
5812 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
5813 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5820 if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode)))
5822 gcc_assert (mode == SImode || mode == DImode);
5823 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5824 : CODE_FOR_reload_indi_r1);
5830 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5831 is only marked as live on entry by df-scan when it is a fixed
5832 register. It isn't a fixed register in the 64-bit runtime,
5833 so we need to mark it here. */
5836 pa_extra_live_on_entry (bitmap regs)
5839 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5842 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5843 to prevent it from being deleted. */
5846 pa_eh_return_handler_rtx (void)
5850 tmp = gen_rtx_PLUS (word_mode, frame_pointer_rtx,
5851 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5852 tmp = gen_rtx_MEM (word_mode, tmp);
5857 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5858 by invisible reference. As a GCC extension, we also pass anything
5859 with a zero or variable size by reference.
5861 The 64-bit runtime does not describe passing any types by invisible
5862 reference. The internals of GCC can't currently handle passing
5863 empty structures, and zero or variable length arrays when they are
5864 not passed entirely on the stack or by reference. Thus, as a GCC
5865 extension, we pass these types by reference. The HP compiler doesn't
5866 support these types, so hopefully there shouldn't be any compatibility
5867 issues. This may have to be revisited when HP releases a C99 compiler
5868 or updates the ABI. */
5871 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5872 enum machine_mode mode, const_tree type,
5873 bool named ATTRIBUTE_UNUSED)
5878 size = int_size_in_bytes (type);
5880 size = GET_MODE_SIZE (mode);
5885 return size <= 0 || size > 8;
5889 function_arg_padding (enum machine_mode mode, const_tree type)
5892 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5894 /* Return none if justification is not required. */
5896 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5897 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5900 /* The directions set here are ignored when a BLKmode argument larger
5901 than a word is placed in a register. Different code is used for
5902 the stack and registers. This makes it difficult to have a
5903 consistent data representation for both the stack and registers.
5904 For both runtimes, the justification and padding for arguments on
5905 the stack and in registers should be identical. */
5907 /* The 64-bit runtime specifies left justification for aggregates. */
5910 /* The 32-bit runtime architecture specifies right justification.
5911 When the argument is passed on the stack, the argument is padded
5912 with garbage on the left. The HP compiler pads with zeros. */
5916 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5923 /* Do what is necessary for `va_start'. We look at the current function
5924 to determine if stdargs or varargs is used and fill in an initial
5925 va_list. A pointer to this constructor is returned. */
5928 hppa_builtin_saveregs (void)
5931 tree fntype = TREE_TYPE (current_function_decl);
5932 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5933 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5934 != void_type_node)))
5935 ? UNITS_PER_WORD : 0);
5938 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
5940 offset = crtl->args.arg_offset_rtx;
5946 /* Adjust for varargs/stdarg differences. */
5948 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
5950 offset = crtl->args.arg_offset_rtx;
5952 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5953 from the incoming arg pointer and growing to larger addresses. */
5954 for (i = 26, off = -64; i >= 19; i--, off += 8)
5955 emit_move_insn (gen_rtx_MEM (word_mode,
5956 plus_constant (arg_pointer_rtx, off)),
5957 gen_rtx_REG (word_mode, i));
5959 /* The incoming args pointer points just beyond the flushback area;
5960 normally this is not a serious concern. However, when we are doing
5961 varargs/stdargs we want to make the arg pointer point to the start
5962 of the incoming argument area. */
5963 emit_move_insn (virtual_incoming_args_rtx,
5964 plus_constant (arg_pointer_rtx, -64));
5966 /* Now return a pointer to the first anonymous argument. */
5967 return copy_to_reg (expand_binop (Pmode, add_optab,
5968 virtual_incoming_args_rtx,
5969 offset, 0, 0, OPTAB_LIB_WIDEN));
5972 /* Store general registers on the stack. */
5973 dest = gen_rtx_MEM (BLKmode,
5974 plus_constant (crtl->args.internal_arg_pointer,
5976 set_mem_alias_set (dest, get_varargs_alias_set ());
5977 set_mem_align (dest, BITS_PER_WORD);
5978 move_block_from_reg (23, dest, 4);
5980 /* move_block_from_reg will emit code to store the argument registers
5981 individually as scalar stores.
5983 However, other insns may later load from the same addresses for
5984 a structure load (passing a struct to a varargs routine).
5986 The alias code assumes that such aliasing can never happen, so we
5987 have to keep memory referencing insns from moving up beyond the
5988 last argument register store. So we emit a blockage insn here. */
5989 emit_insn (gen_blockage ());
5991 return copy_to_reg (expand_binop (Pmode, add_optab,
5992 crtl->args.internal_arg_pointer,
5993 offset, 0, 0, OPTAB_LIB_WIDEN));
5997 hppa_va_start (tree valist, rtx nextarg)
5999 nextarg = expand_builtin_saveregs ();
6000 std_expand_builtin_va_start (valist, nextarg);
6004 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6008 /* Args grow upward. We can use the generic routines. */
6009 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6011 else /* !TARGET_64BIT */
6013 tree ptr = build_pointer_type (type);
6016 unsigned int size, ofs;
6019 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6023 ptr = build_pointer_type (type);
6025 size = int_size_in_bytes (type);
6026 valist_type = TREE_TYPE (valist);
6028 /* Args grow down. Not handled by generic routines. */
6030 u = fold_convert (sizetype, size_in_bytes (type));
6031 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6032 t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u);
6034 /* Copied from va-pa.h, but we probably don't need to align to
6035 word size, since we generate and preserve that invariant. */
6036 u = size_int (size > 4 ? -8 : -4);
6037 t = fold_convert (sizetype, t);
6038 t = build2 (BIT_AND_EXPR, sizetype, t, u);
6039 t = fold_convert (valist_type, t);
6041 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6043 ofs = (8 - size) % 4;
6047 t = build2 (POINTER_PLUS_EXPR, valist_type, t, u);
6050 t = fold_convert (ptr, t);
6051 t = build_va_arg_indirect_ref (t);
6054 t = build_va_arg_indirect_ref (t);
6060 /* True if MODE is valid for the target. By "valid", we mean able to
6061 be manipulated in non-trivial ways. In particular, this means all
6062 the arithmetic is supported.
6064 Currently, TImode is not valid as the HP 64-bit runtime documentation
6065 doesn't document the alignment and calling conventions for this type.
6066 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6067 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6070 pa_scalar_mode_supported_p (enum machine_mode mode)
6072 int precision = GET_MODE_PRECISION (mode);
6074 switch (GET_MODE_CLASS (mode))
6076 case MODE_PARTIAL_INT:
6078 if (precision == CHAR_TYPE_SIZE)
6080 if (precision == SHORT_TYPE_SIZE)
6082 if (precision == INT_TYPE_SIZE)
6084 if (precision == LONG_TYPE_SIZE)
6086 if (precision == LONG_LONG_TYPE_SIZE)
6091 if (precision == FLOAT_TYPE_SIZE)
6093 if (precision == DOUBLE_TYPE_SIZE)
6095 if (precision == LONG_DOUBLE_TYPE_SIZE)
6099 case MODE_DECIMAL_FLOAT:
6107 /* This routine handles all the normal conditional branch sequences we
6108 might need to generate. It handles compare immediate vs compare
6109 register, nullification of delay slots, varying length branches,
6110 negated branches, and all combinations of the above. It returns the
6111 output appropriate to emit the branch corresponding to all given
6115 output_cbranch (rtx *operands, int negated, rtx insn)
6117 static char buf[100];
6119 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6120 int length = get_attr_length (insn);
6123 /* A conditional branch to the following instruction (e.g. the delay slot)
6124 is asking for a disaster. This can happen when not optimizing and
6125 when jump optimization fails.
6127 While it is usually safe to emit nothing, this can fail if the
6128 preceding instruction is a nullified branch with an empty delay
6129 slot and the same branch target as this branch. We could check
6130 for this but jump optimization should eliminate nop jumps. It
6131 is always safe to emit a nop. */
6132 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6135 /* The doubleword form of the cmpib instruction doesn't have the LEU
6136 and GTU conditions while the cmpb instruction does. Since we accept
6137 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6138 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6139 operands[2] = gen_rtx_REG (DImode, 0);
6140 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6141 operands[1] = gen_rtx_REG (DImode, 0);
6143 /* If this is a long branch with its delay slot unfilled, set `nullify'
6144 as it can nullify the delay slot and save a nop. */
6145 if (length == 8 && dbr_sequence_length () == 0)
6148 /* If this is a short forward conditional branch which did not get
6149 its delay slot filled, the delay slot can still be nullified. */
6150 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6151 nullify = forward_branch_p (insn);
6153 /* A forward branch over a single nullified insn can be done with a
6154 comclr instruction. This avoids a single cycle penalty due to
6155 mis-predicted branch if we fall through (branch not taken). */
6157 && next_real_insn (insn) != 0
6158 && get_attr_length (next_real_insn (insn)) == 4
6159 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6165 /* All short conditional branches except backwards with an unfilled
6169 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6171 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6172 if (GET_MODE (operands[1]) == DImode)
6175 strcat (buf, "%B3");
6177 strcat (buf, "%S3");
6179 strcat (buf, " %2,%r1,%%r0");
6181 strcat (buf, ",n %2,%r1,%0");
6183 strcat (buf, " %2,%r1,%0");
6186 /* All long conditionals. Note a short backward branch with an
6187 unfilled delay slot is treated just like a long backward branch
6188 with an unfilled delay slot. */
6190 /* Handle weird backwards branch with a filled delay slot
6191 which is nullified. */
6192 if (dbr_sequence_length () != 0
6193 && ! forward_branch_p (insn)
6196 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6197 if (GET_MODE (operands[1]) == DImode)
6200 strcat (buf, "%S3");
6202 strcat (buf, "%B3");
6203 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6205 /* Handle short backwards branch with an unfilled delay slot.
6206 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6207 taken and untaken branches. */
6208 else if (dbr_sequence_length () == 0
6209 && ! forward_branch_p (insn)
6210 && INSN_ADDRESSES_SET_P ()
6211 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6212 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6214 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6215 if (GET_MODE (operands[1]) == DImode)
6218 strcat (buf, "%B3 %2,%r1,%0%#");
6220 strcat (buf, "%S3 %2,%r1,%0%#");
6224 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6225 if (GET_MODE (operands[1]) == DImode)
6228 strcat (buf, "%S3");
6230 strcat (buf, "%B3");
6232 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6234 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6239 /* The reversed conditional branch must branch over one additional
6240 instruction if the delay slot is filled and needs to be extracted
6241 by output_lbranch. If the delay slot is empty or this is a
6242 nullified forward branch, the instruction after the reversed
6243 condition branch must be nullified. */
6244 if (dbr_sequence_length () == 0
6245 || (nullify && forward_branch_p (insn)))
6249 operands[4] = GEN_INT (length);
6254 operands[4] = GEN_INT (length + 4);
6257 /* Create a reversed conditional branch which branches around
6258 the following insns. */
6259 if (GET_MODE (operands[1]) != DImode)
6265 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6268 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6274 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6277 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6286 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6289 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6295 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6298 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6302 output_asm_insn (buf, operands);
6303 return output_lbranch (operands[0], insn, xdelay);
6308 /* This routine handles output of long unconditional branches that
6309 exceed the maximum range of a simple branch instruction. Since
6310 we don't have a register available for the branch, we save register
6311 %r1 in the frame marker, load the branch destination DEST into %r1,
6312 execute the branch, and restore %r1 in the delay slot of the branch.
6314 Since long branches may have an insn in the delay slot and the
6315 delay slot is used to restore %r1, we in general need to extract
6316 this insn and execute it before the branch. However, to facilitate
6317 use of this function by conditional branches, we also provide an
6318 option to not extract the delay insn so that it will be emitted
6319 after the long branch. So, if there is an insn in the delay slot,
6320 it is extracted if XDELAY is nonzero.
6322 The lengths of the various long-branch sequences are 20, 16 and 24
6323 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6326 output_lbranch (rtx dest, rtx insn, int xdelay)
6330 xoperands[0] = dest;
6332 /* First, free up the delay slot. */
6333 if (xdelay && dbr_sequence_length () != 0)
6335 /* We can't handle a jump in the delay slot. */
6336 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6338 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6341 /* Now delete the delay insn. */
6342 SET_INSN_DELETED (NEXT_INSN (insn));
6345 /* Output an insn to save %r1. The runtime documentation doesn't
6346 specify whether the "Clean Up" slot in the callers frame can
6347 be clobbered by the callee. It isn't copied by HP's builtin
6348 alloca, so this suggests that it can be clobbered if necessary.
6349 The "Static Link" location is copied by HP builtin alloca, so
6350 we avoid using it. Using the cleanup slot might be a problem
6351 if we have to interoperate with languages that pass cleanup
6352 information. However, it should be possible to handle these
6353 situations with GCC's asm feature.
6355 The "Current RP" slot is reserved for the called procedure, so
6356 we try to use it when we don't have a frame of our own. It's
6357 rather unlikely that we won't have a frame when we need to emit
6360 Really the way to go long term is a register scavenger; goto
6361 the target of the jump and find a register which we can use
6362 as a scratch to hold the value in %r1. Then, we wouldn't have
6363 to free up the delay slot or clobber a slot that may be needed
6364 for other purposes. */
6367 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6368 /* Use the return pointer slot in the frame marker. */
6369 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6371 /* Use the slot at -40 in the frame marker since HP builtin
6372 alloca doesn't copy it. */
6373 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6377 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6378 /* Use the return pointer slot in the frame marker. */
6379 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6381 /* Use the "Clean Up" slot in the frame marker. In GCC,
6382 the only other use of this location is for copying a
6383 floating point double argument from a floating-point
6384 register to two general registers. The copy is done
6385 as an "atomic" operation when outputting a call, so it
6386 won't interfere with our using the location here. */
6387 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6390 if (TARGET_PORTABLE_RUNTIME)
6392 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6393 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6394 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6398 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6399 if (TARGET_SOM || !TARGET_GAS)
6401 xoperands[1] = gen_label_rtx ();
6402 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6403 targetm.asm_out.internal_label (asm_out_file, "L",
6404 CODE_LABEL_NUMBER (xoperands[1]));
6405 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6409 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6410 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6412 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6415 /* Now output a very long branch to the original target. */
6416 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6418 /* Now restore the value of %r1 in the delay slot. */
6421 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6422 return "ldd -16(%%r30),%%r1";
6424 return "ldd -40(%%r30),%%r1";
6428 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6429 return "ldw -20(%%r30),%%r1";
6431 return "ldw -12(%%r30),%%r1";
6435 /* This routine handles all the branch-on-bit conditional branch sequences we
6436 might need to generate. It handles nullification of delay slots,
6437 varying length branches, negated branches and all combinations of the
6438 above. it returns the appropriate output template to emit the branch. */
6441 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6443 static char buf[100];
6445 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6446 int length = get_attr_length (insn);
6449 /* A conditional branch to the following instruction (e.g. the delay slot) is
6450 asking for a disaster. I do not think this can happen as this pattern
6451 is only used when optimizing; jump optimization should eliminate the
6452 jump. But be prepared just in case. */
6454 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6457 /* If this is a long branch with its delay slot unfilled, set `nullify'
6458 as it can nullify the delay slot and save a nop. */
6459 if (length == 8 && dbr_sequence_length () == 0)
6462 /* If this is a short forward conditional branch which did not get
6463 its delay slot filled, the delay slot can still be nullified. */
6464 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6465 nullify = forward_branch_p (insn);
6467 /* A forward branch over a single nullified insn can be done with a
6468 extrs instruction. This avoids a single cycle penalty due to
6469 mis-predicted branch if we fall through (branch not taken). */
6472 && next_real_insn (insn) != 0
6473 && get_attr_length (next_real_insn (insn)) == 4
6474 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6481 /* All short conditional branches except backwards with an unfilled
6485 strcpy (buf, "{extrs,|extrw,s,}");
6487 strcpy (buf, "bb,");
6488 if (useskip && GET_MODE (operands[0]) == DImode)
6489 strcpy (buf, "extrd,s,*");
6490 else if (GET_MODE (operands[0]) == DImode)
6491 strcpy (buf, "bb,*");
6492 if ((which == 0 && negated)
6493 || (which == 1 && ! negated))
6498 strcat (buf, " %0,%1,1,%%r0");
6499 else if (nullify && negated)
6500 strcat (buf, ",n %0,%1,%3");
6501 else if (nullify && ! negated)
6502 strcat (buf, ",n %0,%1,%2");
6503 else if (! nullify && negated)
6504 strcat (buf, "%0,%1,%3");
6505 else if (! nullify && ! negated)
6506 strcat (buf, " %0,%1,%2");
6509 /* All long conditionals. Note a short backward branch with an
6510 unfilled delay slot is treated just like a long backward branch
6511 with an unfilled delay slot. */
6513 /* Handle weird backwards branch with a filled delay slot
6514 which is nullified. */
6515 if (dbr_sequence_length () != 0
6516 && ! forward_branch_p (insn)
6519 strcpy (buf, "bb,");
6520 if (GET_MODE (operands[0]) == DImode)
6522 if ((which == 0 && negated)
6523 || (which == 1 && ! negated))
6528 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6530 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6532 /* Handle short backwards branch with an unfilled delay slot.
6533 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6534 taken and untaken branches. */
6535 else if (dbr_sequence_length () == 0
6536 && ! forward_branch_p (insn)
6537 && INSN_ADDRESSES_SET_P ()
6538 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6539 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6541 strcpy (buf, "bb,");
6542 if (GET_MODE (operands[0]) == DImode)
6544 if ((which == 0 && negated)
6545 || (which == 1 && ! negated))
6550 strcat (buf, " %0,%1,%3%#");
6552 strcat (buf, " %0,%1,%2%#");
6556 if (GET_MODE (operands[0]) == DImode)
6557 strcpy (buf, "extrd,s,*");
6559 strcpy (buf, "{extrs,|extrw,s,}");
6560 if ((which == 0 && negated)
6561 || (which == 1 && ! negated))
6565 if (nullify && negated)
6566 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6567 else if (nullify && ! negated)
6568 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6570 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6572 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6577 /* The reversed conditional branch must branch over one additional
6578 instruction if the delay slot is filled and needs to be extracted
6579 by output_lbranch. If the delay slot is empty or this is a
6580 nullified forward branch, the instruction after the reversed
6581 condition branch must be nullified. */
6582 if (dbr_sequence_length () == 0
6583 || (nullify && forward_branch_p (insn)))
6587 operands[4] = GEN_INT (length);
6592 operands[4] = GEN_INT (length + 4);
6595 if (GET_MODE (operands[0]) == DImode)
6596 strcpy (buf, "bb,*");
6598 strcpy (buf, "bb,");
6599 if ((which == 0 && negated)
6600 || (which == 1 && !negated))
6605 strcat (buf, ",n %0,%1,.+%4");
6607 strcat (buf, " %0,%1,.+%4");
6608 output_asm_insn (buf, operands);
6609 return output_lbranch (negated ? operands[3] : operands[2],
6615 /* This routine handles all the branch-on-variable-bit conditional branch
6616 sequences we might need to generate. It handles nullification of delay
6617 slots, varying length branches, negated branches and all combinations
6618 of the above. it returns the appropriate output template to emit the
6622 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6624 static char buf[100];
6626 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6627 int length = get_attr_length (insn);
6630 /* A conditional branch to the following instruction (e.g. the delay slot) is
6631 asking for a disaster. I do not think this can happen as this pattern
6632 is only used when optimizing; jump optimization should eliminate the
6633 jump. But be prepared just in case. */
6635 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6638 /* If this is a long branch with its delay slot unfilled, set `nullify'
6639 as it can nullify the delay slot and save a nop. */
6640 if (length == 8 && dbr_sequence_length () == 0)
6643 /* If this is a short forward conditional branch which did not get
6644 its delay slot filled, the delay slot can still be nullified. */
6645 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6646 nullify = forward_branch_p (insn);
6648 /* A forward branch over a single nullified insn can be done with a
6649 extrs instruction. This avoids a single cycle penalty due to
6650 mis-predicted branch if we fall through (branch not taken). */
6653 && next_real_insn (insn) != 0
6654 && get_attr_length (next_real_insn (insn)) == 4
6655 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6662 /* All short conditional branches except backwards with an unfilled
6666 strcpy (buf, "{vextrs,|extrw,s,}");
6668 strcpy (buf, "{bvb,|bb,}");
6669 if (useskip && GET_MODE (operands[0]) == DImode)
6670 strcpy (buf, "extrd,s,*");
6671 else if (GET_MODE (operands[0]) == DImode)
6672 strcpy (buf, "bb,*");
6673 if ((which == 0 && negated)
6674 || (which == 1 && ! negated))
6679 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6680 else if (nullify && negated)
6681 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6682 else if (nullify && ! negated)
6683 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6684 else if (! nullify && negated)
6685 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6686 else if (! nullify && ! negated)
6687 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6690 /* All long conditionals. Note a short backward branch with an
6691 unfilled delay slot is treated just like a long backward branch
6692 with an unfilled delay slot. */
6694 /* Handle weird backwards branch with a filled delay slot
6695 which is nullified. */
6696 if (dbr_sequence_length () != 0
6697 && ! forward_branch_p (insn)
6700 strcpy (buf, "{bvb,|bb,}");
6701 if (GET_MODE (operands[0]) == DImode)
6703 if ((which == 0 && negated)
6704 || (which == 1 && ! negated))
6709 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6711 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6713 /* Handle short backwards branch with an unfilled delay slot.
6714 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6715 taken and untaken branches. */
6716 else if (dbr_sequence_length () == 0
6717 && ! forward_branch_p (insn)
6718 && INSN_ADDRESSES_SET_P ()
6719 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6720 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6722 strcpy (buf, "{bvb,|bb,}");
6723 if (GET_MODE (operands[0]) == DImode)
6725 if ((which == 0 && negated)
6726 || (which == 1 && ! negated))
6731 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6733 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6737 strcpy (buf, "{vextrs,|extrw,s,}");
6738 if (GET_MODE (operands[0]) == DImode)
6739 strcpy (buf, "extrd,s,*");
6740 if ((which == 0 && negated)
6741 || (which == 1 && ! negated))
6745 if (nullify && negated)
6746 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6747 else if (nullify && ! negated)
6748 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6750 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6752 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6757 /* The reversed conditional branch must branch over one additional
6758 instruction if the delay slot is filled and needs to be extracted
6759 by output_lbranch. If the delay slot is empty or this is a
6760 nullified forward branch, the instruction after the reversed
6761 condition branch must be nullified. */
6762 if (dbr_sequence_length () == 0
6763 || (nullify && forward_branch_p (insn)))
6767 operands[4] = GEN_INT (length);
6772 operands[4] = GEN_INT (length + 4);
6775 if (GET_MODE (operands[0]) == DImode)
6776 strcpy (buf, "bb,*");
6778 strcpy (buf, "{bvb,|bb,}");
6779 if ((which == 0 && negated)
6780 || (which == 1 && !negated))
6785 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6787 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6788 output_asm_insn (buf, operands);
6789 return output_lbranch (negated ? operands[3] : operands[2],
6795 /* Return the output template for emitting a dbra type insn.
6797 Note it may perform some output operations on its own before
6798 returning the final output string. */
6800 output_dbra (rtx *operands, rtx insn, int which_alternative)
6802 int length = get_attr_length (insn);
6804 /* A conditional branch to the following instruction (e.g. the delay slot) is
6805 asking for a disaster. Be prepared! */
6807 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6809 if (which_alternative == 0)
6810 return "ldo %1(%0),%0";
6811 else if (which_alternative == 1)
6813 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6814 output_asm_insn ("ldw -16(%%r30),%4", operands);
6815 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6816 return "{fldws|fldw} -16(%%r30),%0";
6820 output_asm_insn ("ldw %0,%4", operands);
6821 return "ldo %1(%4),%4\n\tstw %4,%0";
6825 if (which_alternative == 0)
6827 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6830 /* If this is a long branch with its delay slot unfilled, set `nullify'
6831 as it can nullify the delay slot and save a nop. */
6832 if (length == 8 && dbr_sequence_length () == 0)
6835 /* If this is a short forward conditional branch which did not get
6836 its delay slot filled, the delay slot can still be nullified. */
6837 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6838 nullify = forward_branch_p (insn);
6844 return "addib,%C2,n %1,%0,%3";
6846 return "addib,%C2 %1,%0,%3";
6849 /* Handle weird backwards branch with a fulled delay slot
6850 which is nullified. */
6851 if (dbr_sequence_length () != 0
6852 && ! forward_branch_p (insn)
6854 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6855 /* Handle short backwards branch with an unfilled delay slot.
6856 Using a addb;nop rather than addi;bl saves 1 cycle for both
6857 taken and untaken branches. */
6858 else if (dbr_sequence_length () == 0
6859 && ! forward_branch_p (insn)
6860 && INSN_ADDRESSES_SET_P ()
6861 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6862 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6863 return "addib,%C2 %1,%0,%3%#";
6865 /* Handle normal cases. */
6867 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6869 return "addi,%N2 %1,%0,%0\n\tb %3";
6872 /* The reversed conditional branch must branch over one additional
6873 instruction if the delay slot is filled and needs to be extracted
6874 by output_lbranch. If the delay slot is empty or this is a
6875 nullified forward branch, the instruction after the reversed
6876 condition branch must be nullified. */
6877 if (dbr_sequence_length () == 0
6878 || (nullify && forward_branch_p (insn)))
6882 operands[4] = GEN_INT (length);
6887 operands[4] = GEN_INT (length + 4);
6891 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
6893 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
6895 return output_lbranch (operands[3], insn, xdelay);
6899 /* Deal with gross reload from FP register case. */
6900 else if (which_alternative == 1)
6902 /* Move loop counter from FP register to MEM then into a GR,
6903 increment the GR, store the GR into MEM, and finally reload
6904 the FP register from MEM from within the branch's delay slot. */
6905 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6907 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6909 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6910 else if (length == 28)
6911 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6914 operands[5] = GEN_INT (length - 16);
6915 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
6916 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6917 return output_lbranch (operands[3], insn, 0);
6920 /* Deal with gross reload from memory case. */
6923 /* Reload loop counter from memory, the store back to memory
6924 happens in the branch's delay slot. */
6925 output_asm_insn ("ldw %0,%4", operands);
6927 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6928 else if (length == 16)
6929 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6932 operands[5] = GEN_INT (length - 4);
6933 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
6934 return output_lbranch (operands[3], insn, 0);
6939 /* Return the output template for emitting a movb type insn.
6941 Note it may perform some output operations on its own before
6942 returning the final output string. */
6944 output_movb (rtx *operands, rtx insn, int which_alternative,
6945 int reverse_comparison)
6947 int length = get_attr_length (insn);
6949 /* A conditional branch to the following instruction (e.g. the delay slot) is
6950 asking for a disaster. Be prepared! */
6952 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6954 if (which_alternative == 0)
6955 return "copy %1,%0";
6956 else if (which_alternative == 1)
6958 output_asm_insn ("stw %1,-16(%%r30)", operands);
6959 return "{fldws|fldw} -16(%%r30),%0";
6961 else if (which_alternative == 2)
6967 /* Support the second variant. */
6968 if (reverse_comparison)
6969 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6971 if (which_alternative == 0)
6973 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6976 /* If this is a long branch with its delay slot unfilled, set `nullify'
6977 as it can nullify the delay slot and save a nop. */
6978 if (length == 8 && dbr_sequence_length () == 0)
6981 /* If this is a short forward conditional branch which did not get
6982 its delay slot filled, the delay slot can still be nullified. */
6983 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6984 nullify = forward_branch_p (insn);
6990 return "movb,%C2,n %1,%0,%3";
6992 return "movb,%C2 %1,%0,%3";
6995 /* Handle weird backwards branch with a filled delay slot
6996 which is nullified. */
6997 if (dbr_sequence_length () != 0
6998 && ! forward_branch_p (insn)
7000 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7002 /* Handle short backwards branch with an unfilled delay slot.
7003 Using a movb;nop rather than or;bl saves 1 cycle for both
7004 taken and untaken branches. */
7005 else if (dbr_sequence_length () == 0
7006 && ! forward_branch_p (insn)
7007 && INSN_ADDRESSES_SET_P ()
7008 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7009 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7010 return "movb,%C2 %1,%0,%3%#";
7011 /* Handle normal cases. */
7013 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7015 return "or,%N2 %1,%%r0,%0\n\tb %3";
7018 /* The reversed conditional branch must branch over one additional
7019 instruction if the delay slot is filled and needs to be extracted
7020 by output_lbranch. If the delay slot is empty or this is a
7021 nullified forward branch, the instruction after the reversed
7022 condition branch must be nullified. */
7023 if (dbr_sequence_length () == 0
7024 || (nullify && forward_branch_p (insn)))
7028 operands[4] = GEN_INT (length);
7033 operands[4] = GEN_INT (length + 4);
7037 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7039 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7041 return output_lbranch (operands[3], insn, xdelay);
7044 /* Deal with gross reload for FP destination register case. */
7045 else if (which_alternative == 1)
7047 /* Move source register to MEM, perform the branch test, then
7048 finally load the FP register from MEM from within the branch's
7050 output_asm_insn ("stw %1,-16(%%r30)", operands);
7052 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7053 else if (length == 16)
7054 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7057 operands[4] = GEN_INT (length - 4);
7058 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7059 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7060 return output_lbranch (operands[3], insn, 0);
7063 /* Deal with gross reload from memory case. */
7064 else if (which_alternative == 2)
7066 /* Reload loop counter from memory, the store back to memory
7067 happens in the branch's delay slot. */
7069 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7070 else if (length == 12)
7071 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7074 operands[4] = GEN_INT (length);
7075 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7077 return output_lbranch (operands[3], insn, 0);
7080 /* Handle SAR as a destination. */
7084 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7085 else if (length == 12)
7086 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7089 operands[4] = GEN_INT (length);
7090 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7092 return output_lbranch (operands[3], insn, 0);
7097 /* Copy any FP arguments in INSN into integer registers. */
7099 copy_fp_args (rtx insn)
7104 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7106 int arg_mode, regno;
7107 rtx use = XEXP (link, 0);
7109 if (! (GET_CODE (use) == USE
7110 && GET_CODE (XEXP (use, 0)) == REG
7111 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7114 arg_mode = GET_MODE (XEXP (use, 0));
7115 regno = REGNO (XEXP (use, 0));
7117 /* Is it a floating point register? */
7118 if (regno >= 32 && regno <= 39)
7120 /* Copy the FP register into an integer register via memory. */
7121 if (arg_mode == SFmode)
7123 xoperands[0] = XEXP (use, 0);
7124 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7125 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7126 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7130 xoperands[0] = XEXP (use, 0);
7131 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7132 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7133 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7134 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7140 /* Compute length of the FP argument copy sequence for INSN. */
7142 length_fp_args (rtx insn)
7147 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7149 int arg_mode, regno;
7150 rtx use = XEXP (link, 0);
7152 if (! (GET_CODE (use) == USE
7153 && GET_CODE (XEXP (use, 0)) == REG
7154 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7157 arg_mode = GET_MODE (XEXP (use, 0));
7158 regno = REGNO (XEXP (use, 0));
7160 /* Is it a floating point register? */
7161 if (regno >= 32 && regno <= 39)
7163 if (arg_mode == SFmode)
7173 /* Return the attribute length for the millicode call instruction INSN.
7174 The length must match the code generated by output_millicode_call.
7175 We include the delay slot in the returned length as it is better to
7176 over estimate the length than to under estimate it. */
7179 attr_length_millicode_call (rtx insn)
7181 unsigned long distance = -1;
7182 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7184 if (INSN_ADDRESSES_SET_P ())
7186 distance = (total + insn_current_reference_address (insn));
7187 if (distance < total)
7193 if (!TARGET_LONG_CALLS && distance < 7600000)
7198 else if (TARGET_PORTABLE_RUNTIME)
7202 if (!TARGET_LONG_CALLS && distance < 240000)
7205 if (TARGET_LONG_ABS_CALL && !flag_pic)
7212 /* INSN is a function call. It may have an unconditional jump
7215 CALL_DEST is the routine we are calling. */
7218 output_millicode_call (rtx insn, rtx call_dest)
7220 int attr_length = get_attr_length (insn);
7221 int seq_length = dbr_sequence_length ();
7226 xoperands[0] = call_dest;
7227 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7229 /* Handle the common case where we are sure that the branch will
7230 reach the beginning of the $CODE$ subspace. The within reach
7231 form of the $$sh_func_adrs call has a length of 28. Because
7232 it has an attribute type of multi, it never has a nonzero
7233 sequence length. The length of the $$sh_func_adrs is the same
7234 as certain out of reach PIC calls to other routines. */
7235 if (!TARGET_LONG_CALLS
7236 && ((seq_length == 0
7237 && (attr_length == 12
7238 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7239 || (seq_length != 0 && attr_length == 8)))
7241 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7247 /* It might seem that one insn could be saved by accessing
7248 the millicode function using the linkage table. However,
7249 this doesn't work in shared libraries and other dynamically
7250 loaded objects. Using a pc-relative sequence also avoids
7251 problems related to the implicit use of the gp register. */
7252 output_asm_insn ("b,l .+8,%%r1", xoperands);
7256 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7257 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7261 xoperands[1] = gen_label_rtx ();
7262 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7263 targetm.asm_out.internal_label (asm_out_file, "L",
7264 CODE_LABEL_NUMBER (xoperands[1]));
7265 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7268 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7270 else if (TARGET_PORTABLE_RUNTIME)
7272 /* Pure portable runtime doesn't allow be/ble; we also don't
7273 have PIC support in the assembler/linker, so this sequence
7276 /* Get the address of our target into %r1. */
7277 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7278 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7280 /* Get our return address into %r31. */
7281 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7282 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7284 /* Jump to our target address in %r1. */
7285 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7289 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7291 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7293 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7297 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7298 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7300 if (TARGET_SOM || !TARGET_GAS)
7302 /* The HP assembler can generate relocations for the
7303 difference of two symbols. GAS can do this for a
7304 millicode symbol but not an arbitrary external
7305 symbol when generating SOM output. */
7306 xoperands[1] = gen_label_rtx ();
7307 targetm.asm_out.internal_label (asm_out_file, "L",
7308 CODE_LABEL_NUMBER (xoperands[1]));
7309 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7310 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7314 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7315 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7319 /* Jump to our target address in %r1. */
7320 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7324 if (seq_length == 0)
7325 output_asm_insn ("nop", xoperands);
7327 /* We are done if there isn't a jump in the delay slot. */
7328 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7331 /* This call has an unconditional jump in its delay slot. */
7332 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7334 /* See if the return address can be adjusted. Use the containing
7335 sequence insn's address. */
7336 if (INSN_ADDRESSES_SET_P ())
7338 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7339 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7340 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7342 if (VAL_14_BITS_P (distance))
7344 xoperands[1] = gen_label_rtx ();
7345 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7346 targetm.asm_out.internal_label (asm_out_file, "L",
7347 CODE_LABEL_NUMBER (xoperands[1]));
7350 /* ??? This branch may not reach its target. */
7351 output_asm_insn ("nop\n\tb,n %0", xoperands);
7354 /* ??? This branch may not reach its target. */
7355 output_asm_insn ("nop\n\tb,n %0", xoperands);
7357 /* Delete the jump. */
7358 SET_INSN_DELETED (NEXT_INSN (insn));
7363 /* Return the attribute length of the call instruction INSN. The SIBCALL
7364 flag indicates whether INSN is a regular call or a sibling call. The
7365 length returned must be longer than the code actually generated by
7366 output_call. Since branch shortening is done before delay branch
7367 sequencing, there is no way to determine whether or not the delay
7368 slot will be filled during branch shortening. Even when the delay
7369 slot is filled, we may have to add a nop if the delay slot contains
7370 a branch that can't reach its target. Thus, we always have to include
7371 the delay slot in the length estimate. This used to be done in
7372 pa_adjust_insn_length but we do it here now as some sequences always
7373 fill the delay slot and we can save four bytes in the estimate for
7377 attr_length_call (rtx insn, int sibcall)
7383 rtx pat = PATTERN (insn);
7384 unsigned long distance = -1;
7386 if (INSN_ADDRESSES_SET_P ())
7388 unsigned long total;
7390 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7391 distance = (total + insn_current_reference_address (insn));
7392 if (distance < total)
7396 /* Determine if this is a local call. */
7397 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7398 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7400 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7402 call_decl = SYMBOL_REF_DECL (call_dest);
7403 local_call = call_decl && targetm.binds_local_p (call_decl);
7405 /* pc-relative branch. */
7406 if (!TARGET_LONG_CALLS
7407 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7408 || distance < 240000))
7411 /* 64-bit plabel sequence. */
7412 else if (TARGET_64BIT && !local_call)
7413 length += sibcall ? 28 : 24;
7415 /* non-pic long absolute branch sequence. */
7416 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7419 /* long pc-relative branch sequence. */
7420 else if (TARGET_LONG_PIC_SDIFF_CALL
7421 || (TARGET_GAS && !TARGET_SOM
7422 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7426 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && flag_pic)
7430 /* 32-bit plabel sequence. */
7436 length += length_fp_args (insn);
7446 if (!TARGET_NO_SPACE_REGS && flag_pic)
7454 /* INSN is a function call. It may have an unconditional jump
7457 CALL_DEST is the routine we are calling. */
7460 output_call (rtx insn, rtx call_dest, int sibcall)
7462 int delay_insn_deleted = 0;
7463 int delay_slot_filled = 0;
7464 int seq_length = dbr_sequence_length ();
7465 tree call_decl = SYMBOL_REF_DECL (call_dest);
7466 int local_call = call_decl && targetm.binds_local_p (call_decl);
7469 xoperands[0] = call_dest;
7471 /* Handle the common case where we're sure that the branch will reach
7472 the beginning of the "$CODE$" subspace. This is the beginning of
7473 the current function if we are in a named section. */
7474 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7476 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7477 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7481 if (TARGET_64BIT && !local_call)
7483 /* ??? As far as I can tell, the HP linker doesn't support the
7484 long pc-relative sequence described in the 64-bit runtime
7485 architecture. So, we use a slightly longer indirect call. */
7486 xoperands[0] = get_deferred_plabel (call_dest);
7487 xoperands[1] = gen_label_rtx ();
7489 /* If this isn't a sibcall, we put the load of %r27 into the
7490 delay slot. We can't do this in a sibcall as we don't
7491 have a second call-clobbered scratch register available. */
7493 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7496 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7499 /* Now delete the delay insn. */
7500 SET_INSN_DELETED (NEXT_INSN (insn));
7501 delay_insn_deleted = 1;
7504 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7505 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7506 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7510 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7511 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7512 output_asm_insn ("bve (%%r1)", xoperands);
7516 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7517 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7518 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7519 delay_slot_filled = 1;
7524 int indirect_call = 0;
7526 /* Emit a long call. There are several different sequences
7527 of increasing length and complexity. In most cases,
7528 they don't allow an instruction in the delay slot. */
7529 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7530 && !TARGET_LONG_PIC_SDIFF_CALL
7531 && !(TARGET_GAS && !TARGET_SOM
7532 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7537 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7539 && (!TARGET_PA_20 || indirect_call))
7541 /* A non-jump insn in the delay slot. By definition we can
7542 emit this insn before the call (and in fact before argument
7544 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7547 /* Now delete the delay insn. */
7548 SET_INSN_DELETED (NEXT_INSN (insn));
7549 delay_insn_deleted = 1;
7552 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7554 /* This is the best sequence for making long calls in
7555 non-pic code. Unfortunately, GNU ld doesn't provide
7556 the stub needed for external calls, and GAS's support
7557 for this with the SOM linker is buggy. It is safe
7558 to use this for local calls. */
7559 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7561 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7565 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7568 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7570 output_asm_insn ("copy %%r31,%%r2", xoperands);
7571 delay_slot_filled = 1;
7576 if (TARGET_LONG_PIC_SDIFF_CALL)
7578 /* The HP assembler and linker can handle relocations
7579 for the difference of two symbols. The HP assembler
7580 recognizes the sequence as a pc-relative call and
7581 the linker provides stubs when needed. */
7582 xoperands[1] = gen_label_rtx ();
7583 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7584 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7585 targetm.asm_out.internal_label (asm_out_file, "L",
7586 CODE_LABEL_NUMBER (xoperands[1]));
7587 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7589 else if (TARGET_GAS && !TARGET_SOM
7590 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7592 /* GAS currently can't generate the relocations that
7593 are needed for the SOM linker under HP-UX using this
7594 sequence. The GNU linker doesn't generate the stubs
7595 that are needed for external calls on TARGET_ELF32
7596 with this sequence. For now, we have to use a
7597 longer plabel sequence when using GAS. */
7598 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7599 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7601 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7606 /* Emit a long plabel-based call sequence. This is
7607 essentially an inline implementation of $$dyncall.
7608 We don't actually try to call $$dyncall as this is
7609 as difficult as calling the function itself. */
7610 xoperands[0] = get_deferred_plabel (call_dest);
7611 xoperands[1] = gen_label_rtx ();
7613 /* Since the call is indirect, FP arguments in registers
7614 need to be copied to the general registers. Then, the
7615 argument relocation stub will copy them back. */
7617 copy_fp_args (insn);
7621 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7622 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7623 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7627 output_asm_insn ("addil LR'%0-$global$,%%r27",
7629 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7633 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7634 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7635 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7636 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7638 if (!sibcall && !TARGET_PA_20)
7640 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7641 if (TARGET_NO_SPACE_REGS)
7642 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7644 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7651 output_asm_insn ("bve (%%r1)", xoperands);
7656 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7657 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7658 delay_slot_filled = 1;
7661 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7666 if (!TARGET_NO_SPACE_REGS && flag_pic)
7667 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7672 if (TARGET_NO_SPACE_REGS || !flag_pic)
7673 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7675 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7679 if (TARGET_NO_SPACE_REGS || !flag_pic)
7680 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7682 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7685 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7687 output_asm_insn ("copy %%r31,%%r2", xoperands);
7688 delay_slot_filled = 1;
7695 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7696 output_asm_insn ("nop", xoperands);
7698 /* We are done if there isn't a jump in the delay slot. */
7700 || delay_insn_deleted
7701 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7704 /* A sibcall should never have a branch in the delay slot. */
7705 gcc_assert (!sibcall);
7707 /* This call has an unconditional jump in its delay slot. */
7708 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7710 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7712 /* See if the return address can be adjusted. Use the containing
7713 sequence insn's address. */
7714 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7715 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7716 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7718 if (VAL_14_BITS_P (distance))
7720 xoperands[1] = gen_label_rtx ();
7721 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7722 targetm.asm_out.internal_label (asm_out_file, "L",
7723 CODE_LABEL_NUMBER (xoperands[1]));
7726 output_asm_insn ("nop\n\tb,n %0", xoperands);
7729 output_asm_insn ("b,n %0", xoperands);
7731 /* Delete the jump. */
7732 SET_INSN_DELETED (NEXT_INSN (insn));
7737 /* Return the attribute length of the indirect call instruction INSN.
7738 The length must match the code generated by output_indirect call.
7739 The returned length includes the delay slot. Currently, the delay
7740 slot of an indirect call sequence is not exposed and it is used by
7741 the sequence itself. */
7744 attr_length_indirect_call (rtx insn)
7746 unsigned long distance = -1;
7747 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7749 if (INSN_ADDRESSES_SET_P ())
7751 distance = (total + insn_current_reference_address (insn));
7752 if (distance < total)
7759 if (TARGET_FAST_INDIRECT_CALLS
7760 || (!TARGET_PORTABLE_RUNTIME
7761 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7762 || distance < 240000)))
7768 if (TARGET_PORTABLE_RUNTIME)
7771 /* Out of reach, can use ble. */
7776 output_indirect_call (rtx insn, rtx call_dest)
7782 xoperands[0] = call_dest;
7783 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7784 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7788 /* First the special case for kernels, level 0 systems, etc. */
7789 if (TARGET_FAST_INDIRECT_CALLS)
7790 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7792 /* Now the normal case -- we can reach $$dyncall directly or
7793 we're sure that we can get there via a long-branch stub.
7795 No need to check target flags as the length uniquely identifies
7796 the remaining cases. */
7797 if (attr_length_indirect_call (insn) == 8)
7799 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7800 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7801 variant of the B,L instruction can't be used on the SOM target. */
7802 if (TARGET_PA_20 && !TARGET_SOM)
7803 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7805 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7808 /* Long millicode call, but we are not generating PIC or portable runtime
7810 if (attr_length_indirect_call (insn) == 12)
7811 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7813 /* Long millicode call for portable runtime. */
7814 if (attr_length_indirect_call (insn) == 20)
7815 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7817 /* We need a long PIC call to $$dyncall. */
7818 xoperands[0] = NULL_RTX;
7819 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7820 if (TARGET_SOM || !TARGET_GAS)
7822 xoperands[0] = gen_label_rtx ();
7823 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7824 targetm.asm_out.internal_label (asm_out_file, "L",
7825 CODE_LABEL_NUMBER (xoperands[0]));
7826 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7830 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7831 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7834 output_asm_insn ("blr %%r0,%%r2", xoperands);
7835 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7839 /* Return the total length of the save and restore instructions needed for
7840 the data linkage table pointer (i.e., the PIC register) across the call
7841 instruction INSN. No-return calls do not require a save and restore.
7842 In addition, we may be able to avoid the save and restore for calls
7843 within the same translation unit. */
7846 attr_length_save_restore_dltp (rtx insn)
7848 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7854 /* In HPUX 8.0's shared library scheme, special relocations are needed
7855 for function labels if they might be passed to a function
7856 in a shared library (because shared libraries don't live in code
7857 space), and special magic is needed to construct their address. */
7860 hppa_encode_label (rtx sym)
7862 const char *str = XSTR (sym, 0);
7863 int len = strlen (str) + 1;
7866 p = newstr = alloca (len + 1);
7870 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7874 pa_encode_section_info (tree decl, rtx rtl, int first)
7876 int old_referenced = 0;
7878 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
7880 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
7882 default_encode_section_info (decl, rtl, first);
7884 if (first && TEXT_SPACE_P (decl))
7886 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7887 if (TREE_CODE (decl) == FUNCTION_DECL)
7888 hppa_encode_label (XEXP (rtl, 0));
7890 else if (old_referenced)
7891 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
7894 /* This is sort of inverse to pa_encode_section_info. */
7897 pa_strip_name_encoding (const char *str)
7899 str += (*str == '@');
7900 str += (*str == '*');
7905 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7907 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7910 /* Returns 1 if OP is a function label involved in a simple addition
7911 with a constant. Used to keep certain patterns from matching
7912 during instruction combination. */
7914 is_function_label_plus_const (rtx op)
7916 /* Strip off any CONST. */
7917 if (GET_CODE (op) == CONST)
7920 return (GET_CODE (op) == PLUS
7921 && function_label_operand (XEXP (op, 0), Pmode)
7922 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7925 /* Output assembly code for a thunk to FUNCTION. */
7928 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7929 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7932 static unsigned int current_thunk_number;
7933 int val_14 = VAL_14_BITS_P (delta);
7938 xoperands[0] = XEXP (DECL_RTL (function), 0);
7939 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7940 xoperands[2] = GEN_INT (delta);
7942 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7943 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7945 /* Output the thunk. We know that the function is in the same
7946 translation unit (i.e., the same space) as the thunk, and that
7947 thunks are output after their method. Thus, we don't need an
7948 external branch to reach the function. With SOM and GAS,
7949 functions and thunks are effectively in different sections.
7950 Thus, we can always use a IA-relative branch and the linker
7951 will add a long branch stub if necessary.
7953 However, we have to be careful when generating PIC code on the
7954 SOM port to ensure that the sequence does not transfer to an
7955 import stub for the target function as this could clobber the
7956 return value saved at SP-24. This would also apply to the
7957 32-bit linux port if the multi-space model is implemented. */
7958 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7959 && !(flag_pic && TREE_PUBLIC (function))
7960 && (TARGET_GAS || last_address < 262132))
7961 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7962 && ((targetm.have_named_sections
7963 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7964 /* The GNU 64-bit linker has rather poor stub management.
7965 So, we use a long branch from thunks that aren't in
7966 the same section as the target function. */
7968 && (DECL_SECTION_NAME (thunk_fndecl)
7969 != DECL_SECTION_NAME (function)))
7970 || ((DECL_SECTION_NAME (thunk_fndecl)
7971 == DECL_SECTION_NAME (function))
7972 && last_address < 262132)))
7973 || (!targetm.have_named_sections && last_address < 262132))))
7976 output_asm_insn ("addil L'%2,%%r26", xoperands);
7978 output_asm_insn ("b %0", xoperands);
7982 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7987 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7991 else if (TARGET_64BIT)
7993 /* We only have one call-clobbered scratch register, so we can't
7994 make use of the delay slot if delta doesn't fit in 14 bits. */
7997 output_asm_insn ("addil L'%2,%%r26", xoperands);
7998 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8001 output_asm_insn ("b,l .+8,%%r1", xoperands);
8005 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8006 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8010 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8011 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8016 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8017 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8022 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8026 else if (TARGET_PORTABLE_RUNTIME)
8028 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8029 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8032 output_asm_insn ("addil L'%2,%%r26", xoperands);
8034 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8038 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8043 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8047 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8049 /* The function is accessible from outside this module. The only
8050 way to avoid an import stub between the thunk and function is to
8051 call the function directly with an indirect sequence similar to
8052 that used by $$dyncall. This is possible because $$dyncall acts
8053 as the import stub in an indirect call. */
8054 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8055 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8056 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8057 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8058 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8059 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8060 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8061 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8062 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8066 output_asm_insn ("addil L'%2,%%r26", xoperands);
8072 output_asm_insn ("bve (%%r22)", xoperands);
8075 else if (TARGET_NO_SPACE_REGS)
8077 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8082 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8083 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8084 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8089 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8091 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8095 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8097 if (TARGET_SOM || !TARGET_GAS)
8099 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8100 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8104 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8105 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8109 output_asm_insn ("addil L'%2,%%r26", xoperands);
8111 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8115 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8120 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8127 output_asm_insn ("addil L'%2,%%r26", xoperands);
8129 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8130 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8134 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8139 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8144 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8146 if (TARGET_SOM && TARGET_GAS)
8148 /* We done with this subspace except possibly for some additional
8149 debug information. Forget that we are in this subspace to ensure
8150 that the next function is output in its own subspace. */
8152 cfun->machine->in_nsubspa = 2;
8155 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8157 switch_to_section (data_section);
8158 output_asm_insn (".align 4", xoperands);
8159 ASM_OUTPUT_LABEL (file, label);
8160 output_asm_insn (".word P'%0", xoperands);
8163 current_thunk_number++;
8164 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8165 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8166 last_address += nbytes;
8167 update_total_code_bytes (nbytes);
8170 /* Only direct calls to static functions are allowed to be sibling (tail)
8173 This restriction is necessary because some linker generated stubs will
8174 store return pointers into rp' in some cases which might clobber a
8175 live value already in rp'.
8177 In a sibcall the current function and the target function share stack
8178 space. Thus if the path to the current function and the path to the
8179 target function save a value in rp', they save the value into the
8180 same stack slot, which has undesirable consequences.
8182 Because of the deferred binding nature of shared libraries any function
8183 with external scope could be in a different load module and thus require
8184 rp' to be saved when calling that function. So sibcall optimizations
8185 can only be safe for static function.
8187 Note that GCC never needs return value relocations, so we don't have to
8188 worry about static calls with return value relocations (which require
8191 It is safe to perform a sibcall optimization when the target function
8192 will never return. */
8194 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8196 if (TARGET_PORTABLE_RUNTIME)
8199 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8200 single subspace mode and the call is not indirect. As far as I know,
8201 there is no operating system support for the multiple subspace mode.
8202 It might be possible to support indirect calls if we didn't use
8203 $$dyncall (see the indirect sequence generated in output_call). */
8205 return (decl != NULL_TREE);
8207 /* Sibcalls are not ok because the arg pointer register is not a fixed
8208 register. This prevents the sibcall optimization from occurring. In
8209 addition, there are problems with stub placement using GNU ld. This
8210 is because a normal sibcall branch uses a 17-bit relocation while
8211 a regular call branch uses a 22-bit relocation. As a result, more
8212 care needs to be taken in the placement of long-branch stubs. */
8216 /* Sibcalls are only ok within a translation unit. */
8217 return (decl && !TREE_PUBLIC (decl));
8220 /* ??? Addition is not commutative on the PA due to the weird implicit
8221 space register selection rules for memory addresses. Therefore, we
8222 don't consider a + b == b + a, as this might be inside a MEM. */
8224 pa_commutative_p (const_rtx x, int outer_code)
8226 return (COMMUTATIVE_P (x)
8227 && (TARGET_NO_SPACE_REGS
8228 || (outer_code != UNKNOWN && outer_code != MEM)
8229 || GET_CODE (x) != PLUS));
8232 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8233 use in fmpyadd instructions. */
8235 fmpyaddoperands (rtx *operands)
8237 enum machine_mode mode = GET_MODE (operands[0]);
8239 /* Must be a floating point mode. */
8240 if (mode != SFmode && mode != DFmode)
8243 /* All modes must be the same. */
8244 if (! (mode == GET_MODE (operands[1])
8245 && mode == GET_MODE (operands[2])
8246 && mode == GET_MODE (operands[3])
8247 && mode == GET_MODE (operands[4])
8248 && mode == GET_MODE (operands[5])))
8251 /* All operands must be registers. */
8252 if (! (GET_CODE (operands[1]) == REG
8253 && GET_CODE (operands[2]) == REG
8254 && GET_CODE (operands[3]) == REG
8255 && GET_CODE (operands[4]) == REG
8256 && GET_CODE (operands[5]) == REG))
8259 /* Only 2 real operands to the addition. One of the input operands must
8260 be the same as the output operand. */
8261 if (! rtx_equal_p (operands[3], operands[4])
8262 && ! rtx_equal_p (operands[3], operands[5]))
8265 /* Inout operand of add cannot conflict with any operands from multiply. */
8266 if (rtx_equal_p (operands[3], operands[0])
8267 || rtx_equal_p (operands[3], operands[1])
8268 || rtx_equal_p (operands[3], operands[2]))
8271 /* multiply cannot feed into addition operands. */
8272 if (rtx_equal_p (operands[4], operands[0])
8273 || rtx_equal_p (operands[5], operands[0]))
8276 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8278 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8279 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8280 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8281 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8282 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8283 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8286 /* Passed. Operands are suitable for fmpyadd. */
8290 #if !defined(USE_COLLECT2)
8292 pa_asm_out_constructor (rtx symbol, int priority)
8294 if (!function_label_operand (symbol, VOIDmode))
8295 hppa_encode_label (symbol);
8297 #ifdef CTORS_SECTION_ASM_OP
8298 default_ctor_section_asm_out_constructor (symbol, priority);
8300 # ifdef TARGET_ASM_NAMED_SECTION
8301 default_named_section_asm_out_constructor (symbol, priority);
8303 default_stabs_asm_out_constructor (symbol, priority);
8309 pa_asm_out_destructor (rtx symbol, int priority)
8311 if (!function_label_operand (symbol, VOIDmode))
8312 hppa_encode_label (symbol);
8314 #ifdef DTORS_SECTION_ASM_OP
8315 default_dtor_section_asm_out_destructor (symbol, priority);
8317 # ifdef TARGET_ASM_NAMED_SECTION
8318 default_named_section_asm_out_destructor (symbol, priority);
8320 default_stabs_asm_out_destructor (symbol, priority);
8326 /* This function places uninitialized global data in the bss section.
8327 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8328 function on the SOM port to prevent uninitialized global data from
8329 being placed in the data section. */
8332 pa_asm_output_aligned_bss (FILE *stream,
8334 unsigned HOST_WIDE_INT size,
8337 switch_to_section (bss_section);
8338 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8340 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8341 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8344 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8345 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8348 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8349 ASM_OUTPUT_LABEL (stream, name);
8350 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8353 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8354 that doesn't allow the alignment of global common storage to be directly
8355 specified. The SOM linker aligns common storage based on the rounded
8356 value of the NUM_BYTES parameter in the .comm directive. It's not
8357 possible to use the .align directive as it doesn't affect the alignment
8358 of the label associated with a .comm directive. */
8361 pa_asm_output_aligned_common (FILE *stream,
8363 unsigned HOST_WIDE_INT size,
8366 unsigned int max_common_align;
8368 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8369 if (align > max_common_align)
8371 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8372 "for global common data. Using %u",
8373 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8374 align = max_common_align;
8377 switch_to_section (bss_section);
8379 assemble_name (stream, name);
8380 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8381 MAX (size, align / BITS_PER_UNIT));
8384 /* We can't use .comm for local common storage as the SOM linker effectively
8385 treats the symbol as universal and uses the same storage for local symbols
8386 with the same name in different object files. The .block directive
8387 reserves an uninitialized block of storage. However, it's not common
8388 storage. Fortunately, GCC never requests common storage with the same
8389 name in any given translation unit. */
8392 pa_asm_output_aligned_local (FILE *stream,
8394 unsigned HOST_WIDE_INT size,
8397 switch_to_section (bss_section);
8398 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8401 fprintf (stream, "%s", LOCAL_ASM_OP);
8402 assemble_name (stream, name);
8403 fprintf (stream, "\n");
8406 ASM_OUTPUT_LABEL (stream, name);
8407 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8410 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8411 use in fmpysub instructions. */
8413 fmpysuboperands (rtx *operands)
8415 enum machine_mode mode = GET_MODE (operands[0]);
8417 /* Must be a floating point mode. */
8418 if (mode != SFmode && mode != DFmode)
8421 /* All modes must be the same. */
8422 if (! (mode == GET_MODE (operands[1])
8423 && mode == GET_MODE (operands[2])
8424 && mode == GET_MODE (operands[3])
8425 && mode == GET_MODE (operands[4])
8426 && mode == GET_MODE (operands[5])))
8429 /* All operands must be registers. */
8430 if (! (GET_CODE (operands[1]) == REG
8431 && GET_CODE (operands[2]) == REG
8432 && GET_CODE (operands[3]) == REG
8433 && GET_CODE (operands[4]) == REG
8434 && GET_CODE (operands[5]) == REG))
8437 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8438 operation, so operands[4] must be the same as operand[3]. */
8439 if (! rtx_equal_p (operands[3], operands[4]))
8442 /* multiply cannot feed into subtraction. */
8443 if (rtx_equal_p (operands[5], operands[0]))
8446 /* Inout operand of sub cannot conflict with any operands from multiply. */
8447 if (rtx_equal_p (operands[3], operands[0])
8448 || rtx_equal_p (operands[3], operands[1])
8449 || rtx_equal_p (operands[3], operands[2]))
8452 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8454 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8455 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8456 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8457 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8458 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8459 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8462 /* Passed. Operands are suitable for fmpysub. */
8466 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8467 constants for shadd instructions. */
8469 shadd_constant_p (int val)
8471 if (val == 2 || val == 4 || val == 8)
8477 /* Return 1 if OP is valid as a base or index register in a
8481 borx_reg_operand (rtx op, enum machine_mode mode)
8483 if (GET_CODE (op) != REG)
8486 /* We must reject virtual registers as the only expressions that
8487 can be instantiated are REG and REG+CONST. */
8488 if (op == virtual_incoming_args_rtx
8489 || op == virtual_stack_vars_rtx
8490 || op == virtual_stack_dynamic_rtx
8491 || op == virtual_outgoing_args_rtx
8492 || op == virtual_cfa_rtx)
8495 /* While it's always safe to index off the frame pointer, it's not
8496 profitable to do so when the frame pointer is being eliminated. */
8497 if (!reload_completed
8498 && flag_omit_frame_pointer
8499 && !cfun->calls_alloca
8500 && op == frame_pointer_rtx)
8503 return register_operand (op, mode);
8506 /* Return 1 if this operand is anything other than a hard register. */
8509 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8511 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8514 /* Return 1 if INSN branches forward. Should be using insn_addresses
8515 to avoid walking through all the insns... */
8517 forward_branch_p (rtx insn)
8519 rtx label = JUMP_LABEL (insn);
8526 insn = NEXT_INSN (insn);
8529 return (insn == label);
8532 /* Return 1 if OP is an equality comparison, else return 0. */
8534 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8536 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8539 /* Return 1 if INSN is in the delay slot of a call instruction. */
8541 jump_in_call_delay (rtx insn)
8544 if (GET_CODE (insn) != JUMP_INSN)
8547 if (PREV_INSN (insn)
8548 && PREV_INSN (PREV_INSN (insn))
8549 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8551 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8553 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8554 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8561 /* Output an unconditional move and branch insn. */
8564 output_parallel_movb (rtx *operands, rtx insn)
8566 int length = get_attr_length (insn);
8568 /* These are the cases in which we win. */
8570 return "mov%I1b,tr %1,%0,%2";
8572 /* None of the following cases win, but they don't lose either. */
8575 if (dbr_sequence_length () == 0)
8577 /* Nothing in the delay slot, fake it by putting the combined
8578 insn (the copy or add) in the delay slot of a bl. */
8579 if (GET_CODE (operands[1]) == CONST_INT)
8580 return "b %2\n\tldi %1,%0";
8582 return "b %2\n\tcopy %1,%0";
8586 /* Something in the delay slot, but we've got a long branch. */
8587 if (GET_CODE (operands[1]) == CONST_INT)
8588 return "ldi %1,%0\n\tb %2";
8590 return "copy %1,%0\n\tb %2";
8594 if (GET_CODE (operands[1]) == CONST_INT)
8595 output_asm_insn ("ldi %1,%0", operands);
8597 output_asm_insn ("copy %1,%0", operands);
8598 return output_lbranch (operands[2], insn, 1);
8601 /* Output an unconditional add and branch insn. */
8604 output_parallel_addb (rtx *operands, rtx insn)
8606 int length = get_attr_length (insn);
8608 /* To make life easy we want operand0 to be the shared input/output
8609 operand and operand1 to be the readonly operand. */
8610 if (operands[0] == operands[1])
8611 operands[1] = operands[2];
8613 /* These are the cases in which we win. */
8615 return "add%I1b,tr %1,%0,%3";
8617 /* None of the following cases win, but they don't lose either. */
8620 if (dbr_sequence_length () == 0)
8621 /* Nothing in the delay slot, fake it by putting the combined
8622 insn (the copy or add) in the delay slot of a bl. */
8623 return "b %3\n\tadd%I1 %1,%0,%0";
8625 /* Something in the delay slot, but we've got a long branch. */
8626 return "add%I1 %1,%0,%0\n\tb %3";
8629 output_asm_insn ("add%I1 %1,%0,%0", operands);
8630 return output_lbranch (operands[3], insn, 1);
8633 /* Return nonzero if INSN (a jump insn) immediately follows a call
8634 to a named function. This is used to avoid filling the delay slot
8635 of the jump since it can usually be eliminated by modifying RP in
8636 the delay slot of the call. */
8639 following_call (rtx insn)
8641 if (! TARGET_JUMP_IN_DELAY)
8644 /* Find the previous real insn, skipping NOTEs. */
8645 insn = PREV_INSN (insn);
8646 while (insn && GET_CODE (insn) == NOTE)
8647 insn = PREV_INSN (insn);
8649 /* Check for CALL_INSNs and millicode calls. */
8651 && ((GET_CODE (insn) == CALL_INSN
8652 && get_attr_type (insn) != TYPE_DYNCALL)
8653 || (GET_CODE (insn) == INSN
8654 && GET_CODE (PATTERN (insn)) != SEQUENCE
8655 && GET_CODE (PATTERN (insn)) != USE
8656 && GET_CODE (PATTERN (insn)) != CLOBBER
8657 && get_attr_type (insn) == TYPE_MILLI)))
8663 /* We use this hook to perform a PA specific optimization which is difficult
8664 to do in earlier passes.
8666 We want the delay slots of branches within jump tables to be filled.
8667 None of the compiler passes at the moment even has the notion that a
8668 PA jump table doesn't contain addresses, but instead contains actual
8671 Because we actually jump into the table, the addresses of each entry
8672 must stay constant in relation to the beginning of the table (which
8673 itself must stay constant relative to the instruction to jump into
8674 it). I don't believe we can guarantee earlier passes of the compiler
8675 will adhere to those rules.
8677 So, late in the compilation process we find all the jump tables, and
8678 expand them into real code -- e.g. each entry in the jump table vector
8679 will get an appropriate label followed by a jump to the final target.
8681 Reorg and the final jump pass can then optimize these branches and
8682 fill their delay slots. We end up with smaller, more efficient code.
8684 The jump instructions within the table are special; we must be able
8685 to identify them during assembly output (if the jumps don't get filled
8686 we need to emit a nop rather than nullifying the delay slot)). We
8687 identify jumps in switch tables by using insns with the attribute
8688 type TYPE_BTABLE_BRANCH.
8690 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8691 insns. This serves two purposes, first it prevents jump.c from
8692 noticing that the last N entries in the table jump to the instruction
8693 immediately after the table and deleting the jumps. Second, those
8694 insns mark where we should emit .begin_brtab and .end_brtab directives
8695 when using GAS (allows for better link time optimizations). */
8702 remove_useless_addtr_insns (1);
8704 if (pa_cpu < PROCESSOR_8000)
8705 pa_combine_instructions ();
8708 /* This is fairly cheap, so always run it if optimizing. */
8709 if (optimize > 0 && !TARGET_BIG_SWITCH)
8711 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8712 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8714 rtx pattern, tmp, location, label;
8715 unsigned int length, i;
8717 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8718 if (GET_CODE (insn) != JUMP_INSN
8719 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8720 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8723 /* Emit marker for the beginning of the branch table. */
8724 emit_insn_before (gen_begin_brtab (), insn);
8726 pattern = PATTERN (insn);
8727 location = PREV_INSN (insn);
8728 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8730 for (i = 0; i < length; i++)
8732 /* Emit a label before each jump to keep jump.c from
8733 removing this code. */
8734 tmp = gen_label_rtx ();
8735 LABEL_NUSES (tmp) = 1;
8736 emit_label_after (tmp, location);
8737 location = NEXT_INSN (location);
8739 if (GET_CODE (pattern) == ADDR_VEC)
8740 label = XEXP (XVECEXP (pattern, 0, i), 0);
8742 label = XEXP (XVECEXP (pattern, 1, i), 0);
8744 tmp = gen_short_jump (label);
8746 /* Emit the jump itself. */
8747 tmp = emit_jump_insn_after (tmp, location);
8748 JUMP_LABEL (tmp) = label;
8749 LABEL_NUSES (label)++;
8750 location = NEXT_INSN (location);
8752 /* Emit a BARRIER after the jump. */
8753 emit_barrier_after (location);
8754 location = NEXT_INSN (location);
8757 /* Emit marker for the end of the branch table. */
8758 emit_insn_before (gen_end_brtab (), location);
8759 location = NEXT_INSN (location);
8760 emit_barrier_after (location);
8762 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8768 /* Still need brtab marker insns. FIXME: the presence of these
8769 markers disables output of the branch table to readonly memory,
8770 and any alignment directives that might be needed. Possibly,
8771 the begin_brtab insn should be output before the label for the
8772 table. This doesn't matter at the moment since the tables are
8773 always output in the text section. */
8774 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8776 /* Find an ADDR_VEC insn. */
8777 if (GET_CODE (insn) != JUMP_INSN
8778 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8779 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8782 /* Now generate markers for the beginning and end of the
8784 emit_insn_before (gen_begin_brtab (), insn);
8785 emit_insn_after (gen_end_brtab (), insn);
8790 /* The PA has a number of odd instructions which can perform multiple
8791 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8792 it may be profitable to combine two instructions into one instruction
8793 with two outputs. It's not profitable PA2.0 machines because the
8794 two outputs would take two slots in the reorder buffers.
8796 This routine finds instructions which can be combined and combines
8797 them. We only support some of the potential combinations, and we
8798 only try common ways to find suitable instructions.
8800 * addb can add two registers or a register and a small integer
8801 and jump to a nearby (+-8k) location. Normally the jump to the
8802 nearby location is conditional on the result of the add, but by
8803 using the "true" condition we can make the jump unconditional.
8804 Thus addb can perform two independent operations in one insn.
8806 * movb is similar to addb in that it can perform a reg->reg
8807 or small immediate->reg copy and jump to a nearby (+-8k location).
8809 * fmpyadd and fmpysub can perform a FP multiply and either an
8810 FP add or FP sub if the operands of the multiply and add/sub are
8811 independent (there are other minor restrictions). Note both
8812 the fmpy and fadd/fsub can in theory move to better spots according
8813 to data dependencies, but for now we require the fmpy stay at a
8816 * Many of the memory operations can perform pre & post updates
8817 of index registers. GCC's pre/post increment/decrement addressing
8818 is far too simple to take advantage of all the possibilities. This
8819 pass may not be suitable since those insns may not be independent.
8821 * comclr can compare two ints or an int and a register, nullify
8822 the following instruction and zero some other register. This
8823 is more difficult to use as it's harder to find an insn which
8824 will generate a comclr than finding something like an unconditional
8825 branch. (conditional moves & long branches create comclr insns).
8827 * Most arithmetic operations can conditionally skip the next
8828 instruction. They can be viewed as "perform this operation
8829 and conditionally jump to this nearby location" (where nearby
8830 is an insns away). These are difficult to use due to the
8831 branch length restrictions. */
8834 pa_combine_instructions (void)
8838 /* This can get expensive since the basic algorithm is on the
8839 order of O(n^2) (or worse). Only do it for -O2 or higher
8840 levels of optimization. */
8844 /* Walk down the list of insns looking for "anchor" insns which
8845 may be combined with "floating" insns. As the name implies,
8846 "anchor" instructions don't move, while "floating" insns may
8848 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8849 new = make_insn_raw (new);
8851 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8853 enum attr_pa_combine_type anchor_attr;
8854 enum attr_pa_combine_type floater_attr;
8856 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8857 Also ignore any special USE insns. */
8858 if ((GET_CODE (anchor) != INSN
8859 && GET_CODE (anchor) != JUMP_INSN
8860 && GET_CODE (anchor) != CALL_INSN)
8861 || GET_CODE (PATTERN (anchor)) == USE
8862 || GET_CODE (PATTERN (anchor)) == CLOBBER
8863 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8864 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8867 anchor_attr = get_attr_pa_combine_type (anchor);
8868 /* See if anchor is an insn suitable for combination. */
8869 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8870 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8871 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8872 && ! forward_branch_p (anchor)))
8876 for (floater = PREV_INSN (anchor);
8878 floater = PREV_INSN (floater))
8880 if (GET_CODE (floater) == NOTE
8881 || (GET_CODE (floater) == INSN
8882 && (GET_CODE (PATTERN (floater)) == USE
8883 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8886 /* Anything except a regular INSN will stop our search. */
8887 if (GET_CODE (floater) != INSN
8888 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8889 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8895 /* See if FLOATER is suitable for combination with the
8897 floater_attr = get_attr_pa_combine_type (floater);
8898 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8899 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8900 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8901 && floater_attr == PA_COMBINE_TYPE_FMPY))
8903 /* If ANCHOR and FLOATER can be combined, then we're
8904 done with this pass. */
8905 if (pa_can_combine_p (new, anchor, floater, 0,
8906 SET_DEST (PATTERN (floater)),
8907 XEXP (SET_SRC (PATTERN (floater)), 0),
8908 XEXP (SET_SRC (PATTERN (floater)), 1)))
8912 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8913 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8915 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8917 if (pa_can_combine_p (new, anchor, floater, 0,
8918 SET_DEST (PATTERN (floater)),
8919 XEXP (SET_SRC (PATTERN (floater)), 0),
8920 XEXP (SET_SRC (PATTERN (floater)), 1)))
8925 if (pa_can_combine_p (new, anchor, floater, 0,
8926 SET_DEST (PATTERN (floater)),
8927 SET_SRC (PATTERN (floater)),
8928 SET_SRC (PATTERN (floater))))
8934 /* If we didn't find anything on the backwards scan try forwards. */
8936 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8937 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8939 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8941 if (GET_CODE (floater) == NOTE
8942 || (GET_CODE (floater) == INSN
8943 && (GET_CODE (PATTERN (floater)) == USE
8944 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8948 /* Anything except a regular INSN will stop our search. */
8949 if (GET_CODE (floater) != INSN
8950 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8951 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8957 /* See if FLOATER is suitable for combination with the
8959 floater_attr = get_attr_pa_combine_type (floater);
8960 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8961 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8962 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8963 && floater_attr == PA_COMBINE_TYPE_FMPY))
8965 /* If ANCHOR and FLOATER can be combined, then we're
8966 done with this pass. */
8967 if (pa_can_combine_p (new, anchor, floater, 1,
8968 SET_DEST (PATTERN (floater)),
8969 XEXP (SET_SRC (PATTERN (floater)),
8971 XEXP (SET_SRC (PATTERN (floater)),
8978 /* FLOATER will be nonzero if we found a suitable floating
8979 insn for combination with ANCHOR. */
8981 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8982 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8984 /* Emit the new instruction and delete the old anchor. */
8985 emit_insn_before (gen_rtx_PARALLEL
8987 gen_rtvec (2, PATTERN (anchor),
8988 PATTERN (floater))),
8991 SET_INSN_DELETED (anchor);
8993 /* Emit a special USE insn for FLOATER, then delete
8994 the floating insn. */
8995 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8996 delete_insn (floater);
9001 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9004 /* Emit the new_jump instruction and delete the old anchor. */
9006 = emit_jump_insn_before (gen_rtx_PARALLEL
9008 gen_rtvec (2, PATTERN (anchor),
9009 PATTERN (floater))),
9012 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9013 SET_INSN_DELETED (anchor);
9015 /* Emit a special USE insn for FLOATER, then delete
9016 the floating insn. */
9017 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9018 delete_insn (floater);
9026 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
9029 int insn_code_number;
9032 /* Create a PARALLEL with the patterns of ANCHOR and
9033 FLOATER, try to recognize it, then test constraints
9034 for the resulting pattern.
9036 If the pattern doesn't match or the constraints
9037 aren't met keep searching for a suitable floater
9039 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
9040 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
9041 INSN_CODE (new) = -1;
9042 insn_code_number = recog_memoized (new);
9043 if (insn_code_number < 0
9044 || (extract_insn (new), ! constrain_operands (1)))
9058 /* There's up to three operands to consider. One
9059 output and two inputs.
9061 The output must not be used between FLOATER & ANCHOR
9062 exclusive. The inputs must not be set between
9063 FLOATER and ANCHOR exclusive. */
9065 if (reg_used_between_p (dest, start, end))
9068 if (reg_set_between_p (src1, start, end))
9071 if (reg_set_between_p (src2, start, end))
9074 /* If we get here, then everything is good. */
9078 /* Return nonzero if references for INSN are delayed.
9080 Millicode insns are actually function calls with some special
9081 constraints on arguments and register usage.
9083 Millicode calls always expect their arguments in the integer argument
9084 registers, and always return their result in %r29 (ret1). They
9085 are expected to clobber their arguments, %r1, %r29, and the return
9086 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9088 This function tells reorg that the references to arguments and
9089 millicode calls do not appear to happen until after the millicode call.
9090 This allows reorg to put insns which set the argument registers into the
9091 delay slot of the millicode call -- thus they act more like traditional
9094 Note we cannot consider side effects of the insn to be delayed because
9095 the branch and link insn will clobber the return pointer. If we happened
9096 to use the return pointer in the delay slot of the call, then we lose.
9098 get_attr_type will try to recognize the given insn, so make sure to
9099 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9102 insn_refs_are_delayed (rtx insn)
9104 return ((GET_CODE (insn) == INSN
9105 && GET_CODE (PATTERN (insn)) != SEQUENCE
9106 && GET_CODE (PATTERN (insn)) != USE
9107 && GET_CODE (PATTERN (insn)) != CLOBBER
9108 && get_attr_type (insn) == TYPE_MILLI));
9111 /* On the HP-PA the value is found in register(s) 28(-29), unless
9112 the mode is SF or DF. Then the value is returned in fr4 (32).
9114 This must perform the same promotions as PROMOTE_MODE, else
9115 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9117 Small structures must be returned in a PARALLEL on PA64 in order
9118 to match the HP Compiler ABI. */
9121 function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED)
9123 enum machine_mode valmode;
9125 if (AGGREGATE_TYPE_P (valtype)
9126 || TREE_CODE (valtype) == COMPLEX_TYPE
9127 || TREE_CODE (valtype) == VECTOR_TYPE)
9131 /* Aggregates with a size less than or equal to 128 bits are
9132 returned in GR 28(-29). They are left justified. The pad
9133 bits are undefined. Larger aggregates are returned in
9137 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9139 for (i = 0; i < ub; i++)
9141 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9142 gen_rtx_REG (DImode, 28 + i),
9147 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9149 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9151 /* Aggregates 5 to 8 bytes in size are returned in general
9152 registers r28-r29 in the same manner as other non
9153 floating-point objects. The data is right-justified and
9154 zero-extended to 64 bits. This is opposite to the normal
9155 justification used on big endian targets and requires
9156 special treatment. */
9157 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9158 gen_rtx_REG (DImode, 28), const0_rtx);
9159 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9163 if ((INTEGRAL_TYPE_P (valtype)
9164 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9165 || POINTER_TYPE_P (valtype))
9166 valmode = word_mode;
9168 valmode = TYPE_MODE (valtype);
9170 if (TREE_CODE (valtype) == REAL_TYPE
9171 && !AGGREGATE_TYPE_P (valtype)
9172 && TYPE_MODE (valtype) != TFmode
9173 && !TARGET_SOFT_FLOAT)
9174 return gen_rtx_REG (valmode, 32);
9176 return gen_rtx_REG (valmode, 28);
9179 /* Return the location of a parameter that is passed in a register or NULL
9180 if the parameter has any component that is passed in memory.
9182 This is new code and will be pushed to into the net sources after
9185 ??? We might want to restructure this so that it looks more like other
9188 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9189 int named ATTRIBUTE_UNUSED)
9191 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9198 if (mode == VOIDmode)
9201 arg_size = FUNCTION_ARG_SIZE (mode, type);
9203 /* If this arg would be passed partially or totally on the stack, then
9204 this routine should return zero. pa_arg_partial_bytes will
9205 handle arguments which are split between regs and stack slots if
9206 the ABI mandates split arguments. */
9209 /* The 32-bit ABI does not split arguments. */
9210 if (cum->words + arg_size > max_arg_words)
9216 alignment = cum->words & 1;
9217 if (cum->words + alignment >= max_arg_words)
9221 /* The 32bit ABIs and the 64bit ABIs are rather different,
9222 particularly in their handling of FP registers. We might
9223 be able to cleverly share code between them, but I'm not
9224 going to bother in the hope that splitting them up results
9225 in code that is more easily understood. */
9229 /* Advance the base registers to their current locations.
9231 Remember, gprs grow towards smaller register numbers while
9232 fprs grow to higher register numbers. Also remember that
9233 although FP regs are 32-bit addressable, we pretend that
9234 the registers are 64-bits wide. */
9235 gpr_reg_base = 26 - cum->words;
9236 fpr_reg_base = 32 + cum->words;
9238 /* Arguments wider than one word and small aggregates need special
9242 || (type && (AGGREGATE_TYPE_P (type)
9243 || TREE_CODE (type) == COMPLEX_TYPE
9244 || TREE_CODE (type) == VECTOR_TYPE)))
9246 /* Double-extended precision (80-bit), quad-precision (128-bit)
9247 and aggregates including complex numbers are aligned on
9248 128-bit boundaries. The first eight 64-bit argument slots
9249 are associated one-to-one, with general registers r26
9250 through r19, and also with floating-point registers fr4
9251 through fr11. Arguments larger than one word are always
9252 passed in general registers.
9254 Using a PARALLEL with a word mode register results in left
9255 justified data on a big-endian target. */
9258 int i, offset = 0, ub = arg_size;
9260 /* Align the base register. */
9261 gpr_reg_base -= alignment;
9263 ub = MIN (ub, max_arg_words - cum->words - alignment);
9264 for (i = 0; i < ub; i++)
9266 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9267 gen_rtx_REG (DImode, gpr_reg_base),
9273 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9278 /* If the argument is larger than a word, then we know precisely
9279 which registers we must use. */
9293 /* Structures 5 to 8 bytes in size are passed in the general
9294 registers in the same manner as other non floating-point
9295 objects. The data is right-justified and zero-extended
9296 to 64 bits. This is opposite to the normal justification
9297 used on big endian targets and requires special treatment.
9298 We now define BLOCK_REG_PADDING to pad these objects.
9299 Aggregates, complex and vector types are passed in the same
9300 manner as structures. */
9302 || (type && (AGGREGATE_TYPE_P (type)
9303 || TREE_CODE (type) == COMPLEX_TYPE
9304 || TREE_CODE (type) == VECTOR_TYPE)))
9306 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9307 gen_rtx_REG (DImode, gpr_reg_base),
9309 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9314 /* We have a single word (32 bits). A simple computation
9315 will get us the register #s we need. */
9316 gpr_reg_base = 26 - cum->words;
9317 fpr_reg_base = 32 + 2 * cum->words;
9321 /* Determine if the argument needs to be passed in both general and
9322 floating point registers. */
9323 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9324 /* If we are doing soft-float with portable runtime, then there
9325 is no need to worry about FP regs. */
9326 && !TARGET_SOFT_FLOAT
9327 /* The parameter must be some kind of scalar float, else we just
9328 pass it in integer registers. */
9329 && GET_MODE_CLASS (mode) == MODE_FLOAT
9330 /* The target function must not have a prototype. */
9331 && cum->nargs_prototype <= 0
9332 /* libcalls do not need to pass items in both FP and general
9334 && type != NULL_TREE
9335 /* All this hair applies to "outgoing" args only. This includes
9336 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9338 /* Also pass outgoing floating arguments in both registers in indirect
9339 calls with the 32 bit ABI and the HP assembler since there is no
9340 way to the specify argument locations in static functions. */
9345 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9351 gen_rtx_EXPR_LIST (VOIDmode,
9352 gen_rtx_REG (mode, fpr_reg_base),
9354 gen_rtx_EXPR_LIST (VOIDmode,
9355 gen_rtx_REG (mode, gpr_reg_base),
9360 /* See if we should pass this parameter in a general register. */
9361 if (TARGET_SOFT_FLOAT
9362 /* Indirect calls in the normal 32bit ABI require all arguments
9363 to be passed in general registers. */
9364 || (!TARGET_PORTABLE_RUNTIME
9368 /* If the parameter is not a scalar floating-point parameter,
9369 then it belongs in GPRs. */
9370 || GET_MODE_CLASS (mode) != MODE_FLOAT
9371 /* Structure with single SFmode field belongs in GPR. */
9372 || (type && AGGREGATE_TYPE_P (type)))
9373 retval = gen_rtx_REG (mode, gpr_reg_base);
9375 retval = gen_rtx_REG (mode, fpr_reg_base);
9381 /* If this arg would be passed totally in registers or totally on the stack,
9382 then this routine should return zero. */
9385 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9386 tree type, bool named ATTRIBUTE_UNUSED)
9388 unsigned int max_arg_words = 8;
9389 unsigned int offset = 0;
9394 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9397 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9398 /* Arg fits fully into registers. */
9400 else if (cum->words + offset >= max_arg_words)
9401 /* Arg fully on the stack. */
9405 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9409 /* A get_unnamed_section callback for switching to the text section.
9411 This function is only used with SOM. Because we don't support
9412 named subspaces, we can only create a new subspace or switch back
9413 to the default text subspace. */
9416 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9418 gcc_assert (TARGET_SOM);
9421 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9423 /* We only want to emit a .nsubspa directive once at the
9424 start of the function. */
9425 cfun->machine->in_nsubspa = 1;
9427 /* Create a new subspace for the text. This provides
9428 better stub placement and one-only functions. */
9430 && DECL_ONE_ONLY (cfun->decl)
9431 && !DECL_WEAK (cfun->decl))
9433 output_section_asm_op ("\t.SPACE $TEXT$\n"
9434 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9435 "ACCESS=44,SORT=24,COMDAT");
9441 /* There isn't a current function or the body of the current
9442 function has been completed. So, we are changing to the
9443 text section to output debugging information. Thus, we
9444 need to forget that we are in the text section so that
9445 varasm.c will call us when text_section is selected again. */
9446 gcc_assert (!cfun || !cfun->machine
9447 || cfun->machine->in_nsubspa == 2);
9450 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9453 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9456 /* A get_unnamed_section callback for switching to comdat data
9457 sections. This function is only used with SOM. */
9460 som_output_comdat_data_section_asm_op (const void *data)
9463 output_section_asm_op (data);
9466 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9469 pa_som_asm_init_sections (void)
9472 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9474 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9475 is not being generated. */
9476 som_readonly_data_section
9477 = get_unnamed_section (0, output_section_asm_op,
9478 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9480 /* When secondary definitions are not supported, SOM makes readonly
9481 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9483 som_one_only_readonly_data_section
9484 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9486 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9487 "ACCESS=0x2c,SORT=16,COMDAT");
9490 /* When secondary definitions are not supported, SOM makes data one-only
9491 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9492 som_one_only_data_section
9493 = get_unnamed_section (SECTION_WRITE,
9494 som_output_comdat_data_section_asm_op,
9495 "\t.SPACE $PRIVATE$\n"
9496 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9497 "ACCESS=31,SORT=24,COMDAT");
9499 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9500 which reference data within the $TEXT$ space (for example constant
9501 strings in the $LIT$ subspace).
9503 The assemblers (GAS and HP as) both have problems with handling
9504 the difference of two symbols which is the other correct way to
9505 reference constant data during PIC code generation.
9507 So, there's no way to reference constant data which is in the
9508 $TEXT$ space during PIC generation. Instead place all constant
9509 data into the $PRIVATE$ subspace (this reduces sharing, but it
9510 works correctly). */
9511 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9513 /* We must not have a reference to an external symbol defined in a
9514 shared library in a readonly section, else the SOM linker will
9517 So, we force exception information into the data section. */
9518 exception_section = data_section;
9521 /* On hpux10, the linker will give an error if we have a reference
9522 in the read-only data section to a symbol defined in a shared
9523 library. Therefore, expressions that might require a reloc can
9524 not be placed in the read-only data section. */
9527 pa_select_section (tree exp, int reloc,
9528 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9530 if (TREE_CODE (exp) == VAR_DECL
9531 && TREE_READONLY (exp)
9532 && !TREE_THIS_VOLATILE (exp)
9533 && DECL_INITIAL (exp)
9534 && (DECL_INITIAL (exp) == error_mark_node
9535 || TREE_CONSTANT (DECL_INITIAL (exp)))
9539 && DECL_ONE_ONLY (exp)
9540 && !DECL_WEAK (exp))
9541 return som_one_only_readonly_data_section;
9543 return readonly_data_section;
9545 else if (CONSTANT_CLASS_P (exp) && !reloc)
9546 return readonly_data_section;
9548 && TREE_CODE (exp) == VAR_DECL
9549 && DECL_ONE_ONLY (exp)
9550 && !DECL_WEAK (exp))
9551 return som_one_only_data_section;
9553 return data_section;
9557 pa_globalize_label (FILE *stream, const char *name)
9559 /* We only handle DATA objects here, functions are globalized in
9560 ASM_DECLARE_FUNCTION_NAME. */
9561 if (! FUNCTION_NAME_P (name))
9563 fputs ("\t.EXPORT ", stream);
9564 assemble_name (stream, name);
9565 fputs (",DATA\n", stream);
9569 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9572 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9573 int incoming ATTRIBUTE_UNUSED)
9575 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9578 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9581 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9583 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9584 PA64 ABI says that objects larger than 128 bits are returned in memory.
9585 Note, int_size_in_bytes can return -1 if the size of the object is
9586 variable or larger than the maximum value that can be expressed as
9587 a HOST_WIDE_INT. It can also return zero for an empty type. The
9588 simplest way to handle variable and empty types is to pass them in
9589 memory. This avoids problems in defining the boundaries of argument
9590 slots, allocating registers, etc. */
9591 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9592 || int_size_in_bytes (type) <= 0);
9595 /* Structure to hold declaration and name of external symbols that are
9596 emitted by GCC. We generate a vector of these symbols and output them
9597 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9598 This avoids putting out names that are never really used. */
9600 typedef struct extern_symbol GTY(())
9606 /* Define gc'd vector type for extern_symbol. */
9607 DEF_VEC_O(extern_symbol);
9608 DEF_VEC_ALLOC_O(extern_symbol,gc);
9610 /* Vector of extern_symbol pointers. */
9611 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9613 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9614 /* Mark DECL (name NAME) as an external reference (assembler output
9615 file FILE). This saves the names to output at the end of the file
9616 if actually referenced. */
9619 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9621 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9623 gcc_assert (file == asm_out_file);
9628 /* Output text required at the end of an assembler file.
9629 This includes deferred plabels and .import directives for
9630 all external symbols that were actually referenced. */
9633 pa_hpux_file_end (void)
9638 if (!NO_DEFERRED_PROFILE_COUNTERS)
9639 output_deferred_profile_counters ();
9641 output_deferred_plabels ();
9643 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9645 tree decl = p->decl;
9647 if (!TREE_ASM_WRITTEN (decl)
9648 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9649 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9652 VEC_free (extern_symbol, gc, extern_symbols);
9656 /* Return true if a change from mode FROM to mode TO for a register
9657 in register class CLASS is invalid. */
9660 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9661 enum reg_class class)
9666 /* Reject changes to/from complex and vector modes. */
9667 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9668 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9671 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9674 /* There is no way to load QImode or HImode values directly from
9675 memory. SImode loads to the FP registers are not zero extended.
9676 On the 64-bit target, this conflicts with the definition of
9677 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9678 with different sizes in the floating-point registers. */
9679 if (MAYBE_FP_REG_CLASS_P (class))
9682 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9683 in specific sets of registers. Thus, we cannot allow changing
9684 to a larger mode when it's larger than a word. */
9685 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9686 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9692 /* Returns TRUE if it is a good idea to tie two pseudo registers
9693 when one has mode MODE1 and one has mode MODE2.
9694 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9695 for any hard reg, then this must be FALSE for correct output.
9697 We should return FALSE for QImode and HImode because these modes
9698 are not ok in the floating-point registers. However, this prevents
9699 tieing these modes to SImode and DImode in the general registers.
9700 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9701 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9702 in the floating-point registers. */
9705 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9707 /* Don't tie modes in different classes. */
9708 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))