1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
42 #include "diagnostic-core.h"
48 #include "common/common-target.h"
49 #include "target-def.h"
50 #include "langhooks.h"
54 /* Return nonzero if there is a bypass for the output of
55 OUT_INSN and the fp store IN_INSN. */
57 pa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
59 enum machine_mode store_mode;
60 enum machine_mode other_mode;
63 if (recog_memoized (in_insn) < 0
64 || (get_attr_type (in_insn) != TYPE_FPSTORE
65 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
66 || recog_memoized (out_insn) < 0)
69 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
71 set = single_set (out_insn);
75 other_mode = GET_MODE (SET_SRC (set));
77 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
81 #ifndef DO_FRAME_NOTES
82 #ifdef INCOMING_RETURN_ADDR_RTX
83 #define DO_FRAME_NOTES 1
85 #define DO_FRAME_NOTES 0
89 static void pa_option_override (void);
90 static void copy_reg_pointer (rtx, rtx);
91 static void fix_range (const char *);
92 static int hppa_register_move_cost (enum machine_mode mode, reg_class_t,
94 static int hppa_address_cost (rtx, bool);
95 static bool hppa_rtx_costs (rtx, int, int, int, int *, bool);
96 static inline rtx force_mode (enum machine_mode, rtx);
97 static void pa_reorg (void);
98 static void pa_combine_instructions (void);
99 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
100 static bool forward_branch_p (rtx);
101 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
102 static void compute_zdepdi_operands (unsigned HOST_WIDE_INT, unsigned *);
103 static int compute_movmem_length (rtx);
104 static int compute_clrmem_length (rtx);
105 static bool pa_assemble_integer (rtx, unsigned int, int);
106 static void remove_useless_addtr_insns (int);
107 static void store_reg (int, HOST_WIDE_INT, int);
108 static void store_reg_modify (int, int, HOST_WIDE_INT);
109 static void load_reg (int, HOST_WIDE_INT, int);
110 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
111 static rtx pa_function_value (const_tree, const_tree, bool);
112 static rtx pa_libcall_value (enum machine_mode, const_rtx);
113 static bool pa_function_value_regno_p (const unsigned int);
114 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void update_total_code_bytes (unsigned int);
116 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static int pa_adjust_cost (rtx, rtx, rtx, int);
118 static int pa_adjust_priority (rtx, int);
119 static int pa_issue_rate (void);
120 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
121 static section *pa_som_tm_clone_table_section (void) ATTRIBUTE_UNUSED;
122 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
124 static void pa_encode_section_info (tree, rtx, int);
125 static const char *pa_strip_name_encoding (const char *);
126 static bool pa_function_ok_for_sibcall (tree, tree);
127 static void pa_globalize_label (FILE *, const char *)
129 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
130 HOST_WIDE_INT, tree);
131 #if !defined(USE_COLLECT2)
132 static void pa_asm_out_constructor (rtx, int);
133 static void pa_asm_out_destructor (rtx, int);
135 static void pa_init_builtins (void);
136 static rtx pa_expand_builtin (tree, rtx, rtx, enum machine_mode mode, int);
137 static rtx hppa_builtin_saveregs (void);
138 static void hppa_va_start (tree, rtx);
139 static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
140 static bool pa_scalar_mode_supported_p (enum machine_mode);
141 static bool pa_commutative_p (const_rtx x, int outer_code);
142 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
143 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
144 static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
145 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
146 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
147 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
148 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
149 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
150 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
151 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
152 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
153 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
154 static void output_deferred_plabels (void);
155 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
156 #ifdef ASM_OUTPUT_EXTERNAL_REAL
157 static void pa_hpux_file_end (void);
159 static void pa_init_libfuncs (void);
160 static rtx pa_struct_value_rtx (tree, int);
161 static bool pa_pass_by_reference (cumulative_args_t, enum machine_mode,
163 static int pa_arg_partial_bytes (cumulative_args_t, enum machine_mode,
165 static void pa_function_arg_advance (cumulative_args_t, enum machine_mode,
167 static rtx pa_function_arg (cumulative_args_t, enum machine_mode,
169 static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree);
170 static struct machine_function * pa_init_machine_status (void);
171 static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
173 secondary_reload_info *);
174 static void pa_extra_live_on_entry (bitmap);
175 static enum machine_mode pa_promote_function_mode (const_tree,
176 enum machine_mode, int *,
179 static void pa_asm_trampoline_template (FILE *);
180 static void pa_trampoline_init (rtx, tree, rtx);
181 static rtx pa_trampoline_adjust_address (rtx);
182 static rtx pa_delegitimize_address (rtx);
183 static bool pa_print_operand_punct_valid_p (unsigned char);
184 static rtx pa_internal_arg_pointer (void);
185 static bool pa_can_eliminate (const int, const int);
186 static void pa_conditional_register_usage (void);
187 static enum machine_mode pa_c_mode_for_suffix (char);
188 static section *pa_function_section (tree, enum node_frequency, bool, bool);
189 static bool pa_cannot_force_const_mem (enum machine_mode, rtx);
190 static bool pa_legitimate_constant_p (enum machine_mode, rtx);
191 static unsigned int pa_section_type_flags (tree, const char *, int);
193 /* The following extra sections are only used for SOM. */
194 static GTY(()) section *som_readonly_data_section;
195 static GTY(()) section *som_one_only_readonly_data_section;
196 static GTY(()) section *som_one_only_data_section;
197 static GTY(()) section *som_tm_clone_table_section;
199 /* Counts for the number of callee-saved general and floating point
200 registers which were saved by the current function's prologue. */
201 static int gr_saved, fr_saved;
203 /* Boolean indicating whether the return pointer was saved by the
204 current function's prologue. */
205 static bool rp_saved;
207 static rtx find_addr_reg (rtx);
209 /* Keep track of the number of bytes we have output in the CODE subspace
210 during this compilation so we'll know when to emit inline long-calls. */
211 unsigned long total_code_bytes;
213 /* The last address of the previous function plus the number of bytes in
214 associated thunks that have been output. This is used to determine if
215 a thunk can use an IA-relative branch to reach its target function. */
216 static unsigned int last_address;
218 /* Variables to handle plabels that we discover are necessary at assembly
219 output time. They are output after the current function. */
220 struct GTY(()) deferred_plabel
225 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
227 static size_t n_deferred_plabels = 0;
229 /* Initialize the GCC target structure. */
231 #undef TARGET_OPTION_OVERRIDE
232 #define TARGET_OPTION_OVERRIDE pa_option_override
234 #undef TARGET_ASM_ALIGNED_HI_OP
235 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
236 #undef TARGET_ASM_ALIGNED_SI_OP
237 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
238 #undef TARGET_ASM_ALIGNED_DI_OP
239 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
240 #undef TARGET_ASM_UNALIGNED_HI_OP
241 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
242 #undef TARGET_ASM_UNALIGNED_SI_OP
243 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
244 #undef TARGET_ASM_UNALIGNED_DI_OP
245 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
246 #undef TARGET_ASM_INTEGER
247 #define TARGET_ASM_INTEGER pa_assemble_integer
249 #undef TARGET_ASM_FUNCTION_PROLOGUE
250 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
251 #undef TARGET_ASM_FUNCTION_EPILOGUE
252 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
254 #undef TARGET_FUNCTION_VALUE
255 #define TARGET_FUNCTION_VALUE pa_function_value
256 #undef TARGET_LIBCALL_VALUE
257 #define TARGET_LIBCALL_VALUE pa_libcall_value
258 #undef TARGET_FUNCTION_VALUE_REGNO_P
259 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
261 #undef TARGET_LEGITIMIZE_ADDRESS
262 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
264 #undef TARGET_SCHED_ADJUST_COST
265 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
266 #undef TARGET_SCHED_ADJUST_PRIORITY
267 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
268 #undef TARGET_SCHED_ISSUE_RATE
269 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
271 #undef TARGET_ENCODE_SECTION_INFO
272 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
273 #undef TARGET_STRIP_NAME_ENCODING
274 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
276 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
277 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
279 #undef TARGET_COMMUTATIVE_P
280 #define TARGET_COMMUTATIVE_P pa_commutative_p
282 #undef TARGET_ASM_OUTPUT_MI_THUNK
283 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
284 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
285 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
287 #undef TARGET_ASM_FILE_END
288 #ifdef ASM_OUTPUT_EXTERNAL_REAL
289 #define TARGET_ASM_FILE_END pa_hpux_file_end
291 #define TARGET_ASM_FILE_END output_deferred_plabels
294 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
295 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
297 #if !defined(USE_COLLECT2)
298 #undef TARGET_ASM_CONSTRUCTOR
299 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
300 #undef TARGET_ASM_DESTRUCTOR
301 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
304 #undef TARGET_INIT_BUILTINS
305 #define TARGET_INIT_BUILTINS pa_init_builtins
307 #undef TARGET_EXPAND_BUILTIN
308 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
310 #undef TARGET_REGISTER_MOVE_COST
311 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
312 #undef TARGET_RTX_COSTS
313 #define TARGET_RTX_COSTS hppa_rtx_costs
314 #undef TARGET_ADDRESS_COST
315 #define TARGET_ADDRESS_COST hppa_address_cost
317 #undef TARGET_MACHINE_DEPENDENT_REORG
318 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
320 #undef TARGET_INIT_LIBFUNCS
321 #define TARGET_INIT_LIBFUNCS pa_init_libfuncs
323 #undef TARGET_PROMOTE_FUNCTION_MODE
324 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
325 #undef TARGET_PROMOTE_PROTOTYPES
326 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
328 #undef TARGET_STRUCT_VALUE_RTX
329 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
330 #undef TARGET_RETURN_IN_MEMORY
331 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
332 #undef TARGET_MUST_PASS_IN_STACK
333 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
334 #undef TARGET_PASS_BY_REFERENCE
335 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
336 #undef TARGET_CALLEE_COPIES
337 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
338 #undef TARGET_ARG_PARTIAL_BYTES
339 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
340 #undef TARGET_FUNCTION_ARG
341 #define TARGET_FUNCTION_ARG pa_function_arg
342 #undef TARGET_FUNCTION_ARG_ADVANCE
343 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
344 #undef TARGET_FUNCTION_ARG_BOUNDARY
345 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
347 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
348 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
349 #undef TARGET_EXPAND_BUILTIN_VA_START
350 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
351 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
352 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
354 #undef TARGET_SCALAR_MODE_SUPPORTED_P
355 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
357 #undef TARGET_CANNOT_FORCE_CONST_MEM
358 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
360 #undef TARGET_SECONDARY_RELOAD
361 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
363 #undef TARGET_EXTRA_LIVE_ON_ENTRY
364 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
366 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
367 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
368 #undef TARGET_TRAMPOLINE_INIT
369 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
370 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
371 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
372 #undef TARGET_DELEGITIMIZE_ADDRESS
373 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
374 #undef TARGET_INTERNAL_ARG_POINTER
375 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
376 #undef TARGET_CAN_ELIMINATE
377 #define TARGET_CAN_ELIMINATE pa_can_eliminate
378 #undef TARGET_CONDITIONAL_REGISTER_USAGE
379 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
380 #undef TARGET_C_MODE_FOR_SUFFIX
381 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
382 #undef TARGET_ASM_FUNCTION_SECTION
383 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
385 #undef TARGET_LEGITIMATE_CONSTANT_P
386 #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p
387 #undef TARGET_SECTION_TYPE_FLAGS
388 #define TARGET_SECTION_TYPE_FLAGS pa_section_type_flags
390 struct gcc_target targetm = TARGET_INITIALIZER;
392 /* Parse the -mfixed-range= option string. */
395 fix_range (const char *const_str)
398 char *str, *dash, *comma;
400 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
401 REG2 are either register names or register numbers. The effect
402 of this option is to mark the registers in the range from REG1 to
403 REG2 as ``fixed'' so they won't be used by the compiler. This is
404 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
406 i = strlen (const_str);
407 str = (char *) alloca (i + 1);
408 memcpy (str, const_str, i + 1);
412 dash = strchr (str, '-');
415 warning (0, "value of -mfixed-range must have form REG1-REG2");
420 comma = strchr (dash + 1, ',');
424 first = decode_reg_name (str);
427 warning (0, "unknown register name: %s", str);
431 last = decode_reg_name (dash + 1);
434 warning (0, "unknown register name: %s", dash + 1);
442 warning (0, "%s-%s is an empty range", str, dash + 1);
446 for (i = first; i <= last; ++i)
447 fixed_regs[i] = call_used_regs[i] = 1;
456 /* Check if all floating point registers have been fixed. */
457 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
462 target_flags |= MASK_DISABLE_FPREGS;
465 /* Implement the TARGET_OPTION_OVERRIDE hook. */
468 pa_option_override (void)
471 cl_deferred_option *opt;
472 VEC(cl_deferred_option,heap) *vec
473 = (VEC(cl_deferred_option,heap) *) pa_deferred_options;
475 FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt)
477 switch (opt->opt_index)
479 case OPT_mfixed_range_:
480 fix_range (opt->arg);
488 /* Unconditional branches in the delay slot are not compatible with dwarf2
489 call frame information. There is no benefit in using this optimization
490 on PA8000 and later processors. */
491 if (pa_cpu >= PROCESSOR_8000
492 || (targetm_common.except_unwind_info (&global_options) == UI_DWARF2
494 || flag_unwind_tables)
495 target_flags &= ~MASK_JUMP_IN_DELAY;
497 if (flag_pic && TARGET_PORTABLE_RUNTIME)
499 warning (0, "PIC code generation is not supported in the portable runtime model");
502 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
504 warning (0, "PIC code generation is not compatible with fast indirect calls");
507 if (! TARGET_GAS && write_symbols != NO_DEBUG)
509 warning (0, "-g is only supported when using GAS on this processor,");
510 warning (0, "-g option disabled");
511 write_symbols = NO_DEBUG;
514 /* We only support the "big PIC" model now. And we always generate PIC
515 code when in 64bit mode. */
516 if (flag_pic == 1 || TARGET_64BIT)
519 /* Disable -freorder-blocks-and-partition as we don't support hot and
520 cold partitioning. */
521 if (flag_reorder_blocks_and_partition)
523 inform (input_location,
524 "-freorder-blocks-and-partition does not work "
525 "on this architecture");
526 flag_reorder_blocks_and_partition = 0;
527 flag_reorder_blocks = 1;
530 /* We can't guarantee that .dword is available for 32-bit targets. */
531 if (UNITS_PER_WORD == 4)
532 targetm.asm_out.aligned_op.di = NULL;
534 /* The unaligned ops are only available when using GAS. */
537 targetm.asm_out.unaligned_op.hi = NULL;
538 targetm.asm_out.unaligned_op.si = NULL;
539 targetm.asm_out.unaligned_op.di = NULL;
542 init_machine_status = pa_init_machine_status;
547 PA_BUILTIN_COPYSIGNQ,
550 PA_BUILTIN_HUGE_VALQ,
554 static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max];
557 pa_init_builtins (void)
559 #ifdef DONT_HAVE_FPUTC_UNLOCKED
561 tree decl = builtin_decl_explicit (BUILT_IN_PUTC_UNLOCKED);
562 set_builtin_decl (BUILT_IN_FPUTC_UNLOCKED, decl,
563 builtin_decl_implicit_p (BUILT_IN_PUTC_UNLOCKED));
570 if ((decl = builtin_decl_explicit (BUILT_IN_FINITE)) != NULL_TREE)
571 set_user_assembler_name (decl, "_Isfinite");
572 if ((decl = builtin_decl_explicit (BUILT_IN_FINITEF)) != NULL_TREE)
573 set_user_assembler_name (decl, "_Isfinitef");
577 if (HPUX_LONG_DOUBLE_LIBRARY)
581 /* Under HPUX, the __float128 type is a synonym for "long double". */
582 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
585 /* TFmode support builtins. */
586 ftype = build_function_type_list (long_double_type_node,
587 long_double_type_node,
589 decl = add_builtin_function ("__builtin_fabsq", ftype,
590 PA_BUILTIN_FABSQ, BUILT_IN_MD,
591 "_U_Qfabs", NULL_TREE);
592 TREE_READONLY (decl) = 1;
593 pa_builtins[PA_BUILTIN_FABSQ] = decl;
595 ftype = build_function_type_list (long_double_type_node,
596 long_double_type_node,
597 long_double_type_node,
599 decl = add_builtin_function ("__builtin_copysignq", ftype,
600 PA_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
601 "_U_Qfcopysign", NULL_TREE);
602 TREE_READONLY (decl) = 1;
603 pa_builtins[PA_BUILTIN_COPYSIGNQ] = decl;
605 ftype = build_function_type_list (long_double_type_node, NULL_TREE);
606 decl = add_builtin_function ("__builtin_infq", ftype,
607 PA_BUILTIN_INFQ, BUILT_IN_MD,
609 pa_builtins[PA_BUILTIN_INFQ] = decl;
611 decl = add_builtin_function ("__builtin_huge_valq", ftype,
612 PA_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
614 pa_builtins[PA_BUILTIN_HUGE_VALQ] = decl;
619 pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
620 enum machine_mode mode ATTRIBUTE_UNUSED,
621 int ignore ATTRIBUTE_UNUSED)
623 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
624 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
628 case PA_BUILTIN_FABSQ:
629 case PA_BUILTIN_COPYSIGNQ:
630 return expand_call (exp, target, ignore);
632 case PA_BUILTIN_INFQ:
633 case PA_BUILTIN_HUGE_VALQ:
635 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
640 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
642 tmp = validize_mem (force_const_mem (target_mode, tmp));
645 target = gen_reg_rtx (target_mode);
647 emit_move_insn (target, tmp);
658 /* Function to init struct machine_function.
659 This will be called, via a pointer variable,
660 from push_function_context. */
662 static struct machine_function *
663 pa_init_machine_status (void)
665 return ggc_alloc_cleared_machine_function ();
668 /* If FROM is a probable pointer register, mark TO as a probable
669 pointer register with the same pointer alignment as FROM. */
672 copy_reg_pointer (rtx to, rtx from)
674 if (REG_POINTER (from))
675 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
678 /* Return 1 if X contains a symbolic expression. We know these
679 expressions will have one of a few well defined forms, so
680 we need only check those forms. */
682 pa_symbolic_expression_p (rtx x)
685 /* Strip off any HIGH. */
686 if (GET_CODE (x) == HIGH)
689 return (symbolic_operand (x, VOIDmode));
692 /* Accept any constant that can be moved in one instruction into a
695 pa_cint_ok_for_move (HOST_WIDE_INT ival)
697 /* OK if ldo, ldil, or zdepi, can be used. */
698 return (VAL_14_BITS_P (ival)
699 || pa_ldil_cint_p (ival)
700 || pa_zdepi_cint_p (ival));
703 /* True iff ldil can be used to load this CONST_INT. The least
704 significant 11 bits of the value must be zero and the value must
705 not change sign when extended from 32 to 64 bits. */
707 pa_ldil_cint_p (HOST_WIDE_INT ival)
709 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
711 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
714 /* True iff zdepi can be used to generate this CONST_INT.
715 zdepi first sign extends a 5-bit signed number to a given field
716 length, then places this field anywhere in a zero. */
718 pa_zdepi_cint_p (unsigned HOST_WIDE_INT x)
720 unsigned HOST_WIDE_INT lsb_mask, t;
722 /* This might not be obvious, but it's at least fast.
723 This function is critical; we don't have the time loops would take. */
725 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
726 /* Return true iff t is a power of two. */
727 return ((t & (t - 1)) == 0);
730 /* True iff depi or extru can be used to compute (reg & mask).
731 Accept bit pattern like these:
736 pa_and_mask_p (unsigned HOST_WIDE_INT mask)
739 mask += mask & -mask;
740 return (mask & (mask - 1)) == 0;
743 /* True iff depi can be used to compute (reg | MASK). */
745 pa_ior_mask_p (unsigned HOST_WIDE_INT mask)
747 mask += mask & -mask;
748 return (mask & (mask - 1)) == 0;
751 /* Legitimize PIC addresses. If the address is already
752 position-independent, we return ORIG. Newly generated
753 position-independent addresses go to REG. If we need more
754 than one register, we lose. */
757 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
761 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
763 /* Labels need special handling. */
764 if (pic_label_operand (orig, mode))
768 /* We do not want to go through the movXX expanders here since that
769 would create recursion.
771 Nor do we really want to call a generator for a named pattern
772 since that requires multiple patterns if we want to support
775 So instead we just emit the raw set, which avoids the movXX
776 expanders completely. */
777 mark_reg_pointer (reg, BITS_PER_UNIT);
778 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
780 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
781 add_reg_note (insn, REG_EQUAL, orig);
783 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
784 and update LABEL_NUSES because this is not done automatically. */
785 if (reload_in_progress || reload_completed)
787 /* Extract LABEL_REF. */
788 if (GET_CODE (orig) == CONST)
789 orig = XEXP (XEXP (orig, 0), 0);
790 /* Extract CODE_LABEL. */
791 orig = XEXP (orig, 0);
792 add_reg_note (insn, REG_LABEL_OPERAND, orig);
793 LABEL_NUSES (orig)++;
795 crtl->uses_pic_offset_table = 1;
798 if (GET_CODE (orig) == SYMBOL_REF)
804 /* Before reload, allocate a temporary register for the intermediate
805 result. This allows the sequence to be deleted when the final
806 result is unused and the insns are trivially dead. */
807 tmp_reg = ((reload_in_progress || reload_completed)
808 ? reg : gen_reg_rtx (Pmode));
810 if (function_label_operand (orig, VOIDmode))
812 /* Force function label into memory in word mode. */
813 orig = XEXP (force_const_mem (word_mode, orig), 0);
814 /* Load plabel address from DLT. */
815 emit_move_insn (tmp_reg,
816 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
817 gen_rtx_HIGH (word_mode, orig)));
819 = gen_const_mem (Pmode,
820 gen_rtx_LO_SUM (Pmode, tmp_reg,
821 gen_rtx_UNSPEC (Pmode,
824 emit_move_insn (reg, pic_ref);
825 /* Now load address of function descriptor. */
826 pic_ref = gen_rtx_MEM (Pmode, reg);
830 /* Load symbol reference from DLT. */
831 emit_move_insn (tmp_reg,
832 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
833 gen_rtx_HIGH (word_mode, orig)));
835 = gen_const_mem (Pmode,
836 gen_rtx_LO_SUM (Pmode, tmp_reg,
837 gen_rtx_UNSPEC (Pmode,
842 crtl->uses_pic_offset_table = 1;
843 mark_reg_pointer (reg, BITS_PER_UNIT);
844 insn = emit_move_insn (reg, pic_ref);
846 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
847 set_unique_reg_note (insn, REG_EQUAL, orig);
851 else if (GET_CODE (orig) == CONST)
855 if (GET_CODE (XEXP (orig, 0)) == PLUS
856 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
860 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
862 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
863 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
864 base == reg ? 0 : reg);
866 if (GET_CODE (orig) == CONST_INT)
868 if (INT_14_BITS (orig))
869 return plus_constant (base, INTVAL (orig));
870 orig = force_reg (Pmode, orig);
872 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
873 /* Likewise, should we set special REG_NOTEs here? */
879 static GTY(()) rtx gen_tls_tga;
882 gen_tls_get_addr (void)
885 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
890 hppa_tls_call (rtx arg)
894 ret = gen_reg_rtx (Pmode);
895 emit_library_call_value (gen_tls_get_addr (), ret,
896 LCT_CONST, Pmode, 1, arg, Pmode);
902 legitimize_tls_address (rtx addr)
904 rtx ret, insn, tmp, t1, t2, tp;
905 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
909 case TLS_MODEL_GLOBAL_DYNAMIC:
910 tmp = gen_reg_rtx (Pmode);
912 emit_insn (gen_tgd_load_pic (tmp, addr));
914 emit_insn (gen_tgd_load (tmp, addr));
915 ret = hppa_tls_call (tmp);
918 case TLS_MODEL_LOCAL_DYNAMIC:
919 ret = gen_reg_rtx (Pmode);
920 tmp = gen_reg_rtx (Pmode);
923 emit_insn (gen_tld_load_pic (tmp, addr));
925 emit_insn (gen_tld_load (tmp, addr));
926 t1 = hppa_tls_call (tmp);
929 t2 = gen_reg_rtx (Pmode);
930 emit_libcall_block (insn, t2, t1,
931 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
933 emit_insn (gen_tld_offset_load (ret, addr, t2));
936 case TLS_MODEL_INITIAL_EXEC:
937 tp = gen_reg_rtx (Pmode);
938 tmp = gen_reg_rtx (Pmode);
939 ret = gen_reg_rtx (Pmode);
940 emit_insn (gen_tp_load (tp));
942 emit_insn (gen_tie_load_pic (tmp, addr));
944 emit_insn (gen_tie_load (tmp, addr));
945 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
948 case TLS_MODEL_LOCAL_EXEC:
949 tp = gen_reg_rtx (Pmode);
950 ret = gen_reg_rtx (Pmode);
951 emit_insn (gen_tp_load (tp));
952 emit_insn (gen_tle_load (ret, addr, tp));
962 /* Try machine-dependent ways of modifying an illegitimate address
963 to be legitimate. If we find one, return the new, valid address.
964 This macro is used in only one place: `memory_address' in explow.c.
966 OLDX is the address as it was before break_out_memory_refs was called.
967 In some cases it is useful to look at this to decide what needs to be done.
969 It is always safe for this macro to do nothing. It exists to recognize
970 opportunities to optimize the output.
972 For the PA, transform:
974 memory(X + <large int>)
978 if (<large int> & mask) >= 16
979 Y = (<large int> & ~mask) + mask + 1 Round up.
981 Y = (<large int> & ~mask) Round down.
983 memory (Z + (<large int> - Y));
985 This is for CSE to find several similar references, and only use one Z.
987 X can either be a SYMBOL_REF or REG, but because combine cannot
988 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
989 D will not fit in 14 bits.
991 MODE_FLOAT references allow displacements which fit in 5 bits, so use
994 MODE_INT references allow displacements which fit in 14 bits, so use
997 This relies on the fact that most mode MODE_FLOAT references will use FP
998 registers and most mode MODE_INT references will use integer registers.
999 (In the rare case of an FP register used in an integer MODE, we depend
1000 on secondary reloads to clean things up.)
1003 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1004 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1005 addressing modes to be used).
1007 Put X and Z into registers. Then put the entire expression into
1011 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1012 enum machine_mode mode)
1016 /* We need to canonicalize the order of operands in unscaled indexed
1017 addresses since the code that checks if an address is valid doesn't
1018 always try both orders. */
1019 if (!TARGET_NO_SPACE_REGS
1020 && GET_CODE (x) == PLUS
1021 && GET_MODE (x) == Pmode
1022 && REG_P (XEXP (x, 0))
1023 && REG_P (XEXP (x, 1))
1024 && REG_POINTER (XEXP (x, 0))
1025 && !REG_POINTER (XEXP (x, 1)))
1026 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1028 if (PA_SYMBOL_REF_TLS_P (x))
1029 return legitimize_tls_address (x);
1031 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1033 /* Strip off CONST. */
1034 if (GET_CODE (x) == CONST)
1037 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1038 That should always be safe. */
1039 if (GET_CODE (x) == PLUS
1040 && GET_CODE (XEXP (x, 0)) == REG
1041 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1043 rtx reg = force_reg (Pmode, XEXP (x, 1));
1044 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1047 /* Note we must reject symbols which represent function addresses
1048 since the assembler/linker can't handle arithmetic on plabels. */
1049 if (GET_CODE (x) == PLUS
1050 && GET_CODE (XEXP (x, 1)) == CONST_INT
1051 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1052 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1053 || GET_CODE (XEXP (x, 0)) == REG))
1055 rtx int_part, ptr_reg;
1057 int offset = INTVAL (XEXP (x, 1));
1060 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1061 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
1063 /* Choose which way to round the offset. Round up if we
1064 are >= halfway to the next boundary. */
1065 if ((offset & mask) >= ((mask + 1) / 2))
1066 newoffset = (offset & ~ mask) + mask + 1;
1068 newoffset = (offset & ~ mask);
1070 /* If the newoffset will not fit in 14 bits (ldo), then
1071 handling this would take 4 or 5 instructions (2 to load
1072 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1073 add the new offset and the SYMBOL_REF.) Combine can
1074 not handle 4->2 or 5->2 combinations, so do not create
1076 if (! VAL_14_BITS_P (newoffset)
1077 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1079 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1082 gen_rtx_HIGH (Pmode, const_part));
1085 gen_rtx_LO_SUM (Pmode,
1086 tmp_reg, const_part));
1090 if (! VAL_14_BITS_P (newoffset))
1091 int_part = force_reg (Pmode, GEN_INT (newoffset));
1093 int_part = GEN_INT (newoffset);
1095 ptr_reg = force_reg (Pmode,
1096 gen_rtx_PLUS (Pmode,
1097 force_reg (Pmode, XEXP (x, 0)),
1100 return plus_constant (ptr_reg, offset - newoffset);
1103 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1105 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1106 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1107 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1108 && (OBJECT_P (XEXP (x, 1))
1109 || GET_CODE (XEXP (x, 1)) == SUBREG)
1110 && GET_CODE (XEXP (x, 1)) != CONST)
1112 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1116 if (GET_CODE (reg1) != REG)
1117 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1119 reg2 = XEXP (XEXP (x, 0), 0);
1120 if (GET_CODE (reg2) != REG)
1121 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1123 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1124 gen_rtx_MULT (Pmode,
1130 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1132 Only do so for floating point modes since this is more speculative
1133 and we lose if it's an integer store. */
1134 if (GET_CODE (x) == PLUS
1135 && GET_CODE (XEXP (x, 0)) == PLUS
1136 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1137 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1138 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1139 && (mode == SFmode || mode == DFmode))
1142 /* First, try and figure out what to use as a base register. */
1143 rtx reg1, reg2, base, idx;
1145 reg1 = XEXP (XEXP (x, 0), 1);
1150 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1151 then pa_emit_move_sequence will turn on REG_POINTER so we'll know
1152 it's a base register below. */
1153 if (GET_CODE (reg1) != REG)
1154 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1156 if (GET_CODE (reg2) != REG)
1157 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1159 /* Figure out what the base and index are. */
1161 if (GET_CODE (reg1) == REG
1162 && REG_POINTER (reg1))
1165 idx = gen_rtx_PLUS (Pmode,
1166 gen_rtx_MULT (Pmode,
1167 XEXP (XEXP (XEXP (x, 0), 0), 0),
1168 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1171 else if (GET_CODE (reg2) == REG
1172 && REG_POINTER (reg2))
1181 /* If the index adds a large constant, try to scale the
1182 constant so that it can be loaded with only one insn. */
1183 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1184 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1185 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1186 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1188 /* Divide the CONST_INT by the scale factor, then add it to A. */
1189 int val = INTVAL (XEXP (idx, 1));
1191 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1192 reg1 = XEXP (XEXP (idx, 0), 0);
1193 if (GET_CODE (reg1) != REG)
1194 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1196 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1198 /* We can now generate a simple scaled indexed address. */
1201 (Pmode, gen_rtx_PLUS (Pmode,
1202 gen_rtx_MULT (Pmode, reg1,
1203 XEXP (XEXP (idx, 0), 1)),
1207 /* If B + C is still a valid base register, then add them. */
1208 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1209 && INTVAL (XEXP (idx, 1)) <= 4096
1210 && INTVAL (XEXP (idx, 1)) >= -4096)
1212 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1215 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1217 reg2 = XEXP (XEXP (idx, 0), 0);
1218 if (GET_CODE (reg2) != CONST_INT)
1219 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1221 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1222 gen_rtx_MULT (Pmode,
1228 /* Get the index into a register, then add the base + index and
1229 return a register holding the result. */
1231 /* First get A into a register. */
1232 reg1 = XEXP (XEXP (idx, 0), 0);
1233 if (GET_CODE (reg1) != REG)
1234 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1236 /* And get B into a register. */
1237 reg2 = XEXP (idx, 1);
1238 if (GET_CODE (reg2) != REG)
1239 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1241 reg1 = force_reg (Pmode,
1242 gen_rtx_PLUS (Pmode,
1243 gen_rtx_MULT (Pmode, reg1,
1244 XEXP (XEXP (idx, 0), 1)),
1247 /* Add the result to our base register and return. */
1248 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1252 /* Uh-oh. We might have an address for x[n-100000]. This needs
1253 special handling to avoid creating an indexed memory address
1254 with x-100000 as the base.
1256 If the constant part is small enough, then it's still safe because
1257 there is a guard page at the beginning and end of the data segment.
1259 Scaled references are common enough that we want to try and rearrange the
1260 terms so that we can use indexing for these addresses too. Only
1261 do the optimization for floatint point modes. */
1263 if (GET_CODE (x) == PLUS
1264 && pa_symbolic_expression_p (XEXP (x, 1)))
1266 /* Ugly. We modify things here so that the address offset specified
1267 by the index expression is computed first, then added to x to form
1268 the entire address. */
1270 rtx regx1, regx2, regy1, regy2, y;
1272 /* Strip off any CONST. */
1274 if (GET_CODE (y) == CONST)
1277 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1279 /* See if this looks like
1280 (plus (mult (reg) (shadd_const))
1281 (const (plus (symbol_ref) (const_int))))
1283 Where const_int is small. In that case the const
1284 expression is a valid pointer for indexing.
1286 If const_int is big, but can be divided evenly by shadd_const
1287 and added to (reg). This allows more scaled indexed addresses. */
1288 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1289 && GET_CODE (XEXP (x, 0)) == MULT
1290 && GET_CODE (XEXP (y, 1)) == CONST_INT
1291 && INTVAL (XEXP (y, 1)) >= -4096
1292 && INTVAL (XEXP (y, 1)) <= 4095
1293 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1294 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1296 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1300 if (GET_CODE (reg1) != REG)
1301 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1303 reg2 = XEXP (XEXP (x, 0), 0);
1304 if (GET_CODE (reg2) != REG)
1305 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1307 return force_reg (Pmode,
1308 gen_rtx_PLUS (Pmode,
1309 gen_rtx_MULT (Pmode,
1314 else if ((mode == DFmode || mode == SFmode)
1315 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1316 && GET_CODE (XEXP (x, 0)) == MULT
1317 && GET_CODE (XEXP (y, 1)) == CONST_INT
1318 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1319 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1320 && pa_shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1323 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1324 / INTVAL (XEXP (XEXP (x, 0), 1))));
1325 regx2 = XEXP (XEXP (x, 0), 0);
1326 if (GET_CODE (regx2) != REG)
1327 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1328 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1332 gen_rtx_PLUS (Pmode,
1333 gen_rtx_MULT (Pmode, regx2,
1334 XEXP (XEXP (x, 0), 1)),
1335 force_reg (Pmode, XEXP (y, 0))));
1337 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1338 && INTVAL (XEXP (y, 1)) >= -4096
1339 && INTVAL (XEXP (y, 1)) <= 4095)
1341 /* This is safe because of the guard page at the
1342 beginning and end of the data space. Just
1343 return the original address. */
1348 /* Doesn't look like one we can optimize. */
1349 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1350 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1351 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1352 regx1 = force_reg (Pmode,
1353 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1355 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1363 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1365 Compute extra cost of moving data between one register class
1368 Make moves from SAR so expensive they should never happen. We used to
1369 have 0xffff here, but that generates overflow in rare cases.
1371 Copies involving a FP register and a non-FP register are relatively
1372 expensive because they must go through memory.
1374 Other copies are reasonably cheap. */
1377 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1378 reg_class_t from, reg_class_t to)
1380 if (from == SHIFT_REGS)
1382 else if (to == SHIFT_REGS && FP_REG_CLASS_P (from))
1384 else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
1385 || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
1391 /* For the HPPA, REG and REG+CONST is cost 0
1392 and addresses involving symbolic constants are cost 2.
1394 PIC addresses are very expensive.
1396 It is no coincidence that this has the same structure
1397 as GO_IF_LEGITIMATE_ADDRESS. */
1400 hppa_address_cost (rtx X,
1401 bool speed ATTRIBUTE_UNUSED)
1403 switch (GET_CODE (X))
1416 /* Compute a (partial) cost for rtx X. Return true if the complete
1417 cost has been computed, and false if subexpressions should be
1418 scanned. In either case, *TOTAL contains the cost result. */
1421 hppa_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
1422 int *total, bool speed ATTRIBUTE_UNUSED)
1427 if (INTVAL (x) == 0)
1429 else if (INT_14_BITS (x))
1446 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1447 && outer_code != SET)
1454 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1455 *total = COSTS_N_INSNS (3);
1456 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1457 *total = COSTS_N_INSNS (8);
1459 *total = COSTS_N_INSNS (20);
1463 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1465 *total = COSTS_N_INSNS (14);
1473 *total = COSTS_N_INSNS (60);
1476 case PLUS: /* this includes shNadd insns */
1478 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1479 *total = COSTS_N_INSNS (3);
1481 *total = COSTS_N_INSNS (1);
1487 *total = COSTS_N_INSNS (1);
1495 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1496 new rtx with the correct mode. */
1498 force_mode (enum machine_mode mode, rtx orig)
1500 if (mode == GET_MODE (orig))
1503 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1505 return gen_rtx_REG (mode, REGNO (orig));
1508 /* Return 1 if *X is a thread-local symbol. */
1511 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1513 return PA_SYMBOL_REF_TLS_P (*x);
1516 /* Return 1 if X contains a thread-local symbol. */
1519 pa_tls_referenced_p (rtx x)
1521 if (!TARGET_HAVE_TLS)
1524 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1527 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1530 pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1532 return pa_tls_referenced_p (x);
1535 /* Emit insns to move operands[1] into operands[0].
1537 Return 1 if we have written out everything that needs to be done to
1538 do the move. Otherwise, return 0 and the caller will emit the move
1541 Note SCRATCH_REG may not be in the proper mode depending on how it
1542 will be used. This routine is responsible for creating a new copy
1543 of SCRATCH_REG in the proper mode. */
1546 pa_emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1548 register rtx operand0 = operands[0];
1549 register rtx operand1 = operands[1];
1552 /* We can only handle indexed addresses in the destination operand
1553 of floating point stores. Thus, we need to break out indexed
1554 addresses from the destination operand. */
1555 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1557 gcc_assert (can_create_pseudo_p ());
1559 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1560 operand0 = replace_equiv_address (operand0, tem);
1563 /* On targets with non-equivalent space registers, break out unscaled
1564 indexed addresses from the source operand before the final CSE.
1565 We have to do this because the REG_POINTER flag is not correctly
1566 carried through various optimization passes and CSE may substitute
1567 a pseudo without the pointer set for one with the pointer set. As
1568 a result, we loose various opportunities to create insns with
1569 unscaled indexed addresses. */
1570 if (!TARGET_NO_SPACE_REGS
1571 && !cse_not_expected
1572 && GET_CODE (operand1) == MEM
1573 && GET_CODE (XEXP (operand1, 0)) == PLUS
1574 && REG_P (XEXP (XEXP (operand1, 0), 0))
1575 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1577 = replace_equiv_address (operand1,
1578 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1581 && reload_in_progress && GET_CODE (operand0) == REG
1582 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1583 operand0 = reg_equiv_mem (REGNO (operand0));
1584 else if (scratch_reg
1585 && reload_in_progress && GET_CODE (operand0) == SUBREG
1586 && GET_CODE (SUBREG_REG (operand0)) == REG
1587 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1589 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1590 the code which tracks sets/uses for delete_output_reload. */
1591 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1592 reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
1593 SUBREG_BYTE (operand0));
1594 operand0 = alter_subreg (&temp);
1598 && reload_in_progress && GET_CODE (operand1) == REG
1599 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1600 operand1 = reg_equiv_mem (REGNO (operand1));
1601 else if (scratch_reg
1602 && reload_in_progress && GET_CODE (operand1) == SUBREG
1603 && GET_CODE (SUBREG_REG (operand1)) == REG
1604 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1606 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1607 the code which tracks sets/uses for delete_output_reload. */
1608 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1609 reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
1610 SUBREG_BYTE (operand1));
1611 operand1 = alter_subreg (&temp);
1614 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1615 && ((tem = find_replacement (&XEXP (operand0, 0)))
1616 != XEXP (operand0, 0)))
1617 operand0 = replace_equiv_address (operand0, tem);
1619 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1620 && ((tem = find_replacement (&XEXP (operand1, 0)))
1621 != XEXP (operand1, 0)))
1622 operand1 = replace_equiv_address (operand1, tem);
1624 /* Handle secondary reloads for loads/stores of FP registers from
1625 REG+D addresses where D does not fit in 5 or 14 bits, including
1626 (subreg (mem (addr))) cases. */
1628 && fp_reg_operand (operand0, mode)
1629 && ((GET_CODE (operand1) == MEM
1630 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1631 XEXP (operand1, 0)))
1632 || ((GET_CODE (operand1) == SUBREG
1633 && GET_CODE (XEXP (operand1, 0)) == MEM
1634 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1636 XEXP (XEXP (operand1, 0), 0))))))
1638 if (GET_CODE (operand1) == SUBREG)
1639 operand1 = XEXP (operand1, 0);
1641 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1642 it in WORD_MODE regardless of what mode it was originally given
1644 scratch_reg = force_mode (word_mode, scratch_reg);
1646 /* D might not fit in 14 bits either; for such cases load D into
1648 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1650 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1651 emit_move_insn (scratch_reg,
1652 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1654 XEXP (XEXP (operand1, 0), 0),
1658 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1659 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1660 replace_equiv_address (operand1, scratch_reg)));
1663 else if (scratch_reg
1664 && fp_reg_operand (operand1, mode)
1665 && ((GET_CODE (operand0) == MEM
1666 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1668 XEXP (operand0, 0)))
1669 || ((GET_CODE (operand0) == SUBREG)
1670 && GET_CODE (XEXP (operand0, 0)) == MEM
1671 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1673 XEXP (XEXP (operand0, 0), 0)))))
1675 if (GET_CODE (operand0) == SUBREG)
1676 operand0 = XEXP (operand0, 0);
1678 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1679 it in WORD_MODE regardless of what mode it was originally given
1681 scratch_reg = force_mode (word_mode, scratch_reg);
1683 /* D might not fit in 14 bits either; for such cases load D into
1685 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1687 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1688 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1691 XEXP (XEXP (operand0, 0),
1696 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1697 emit_insn (gen_rtx_SET (VOIDmode,
1698 replace_equiv_address (operand0, scratch_reg),
1702 /* Handle secondary reloads for loads of FP registers from constant
1703 expressions by forcing the constant into memory.
1705 Use scratch_reg to hold the address of the memory location.
1707 The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return
1708 NO_REGS when presented with a const_int and a register class
1709 containing only FP registers. Doing so unfortunately creates
1710 more problems than it solves. Fix this for 2.5. */
1711 else if (scratch_reg
1712 && CONSTANT_P (operand1)
1713 && fp_reg_operand (operand0, mode))
1715 rtx const_mem, xoperands[2];
1717 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1718 it in WORD_MODE regardless of what mode it was originally given
1720 scratch_reg = force_mode (word_mode, scratch_reg);
1722 /* Force the constant into memory and put the address of the
1723 memory location into scratch_reg. */
1724 const_mem = force_const_mem (mode, operand1);
1725 xoperands[0] = scratch_reg;
1726 xoperands[1] = XEXP (const_mem, 0);
1727 pa_emit_move_sequence (xoperands, Pmode, 0);
1729 /* Now load the destination register. */
1730 emit_insn (gen_rtx_SET (mode, operand0,
1731 replace_equiv_address (const_mem, scratch_reg)));
1734 /* Handle secondary reloads for SAR. These occur when trying to load
1735 the SAR from memory or a constant. */
1736 else if (scratch_reg
1737 && GET_CODE (operand0) == REG
1738 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1739 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1740 && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
1742 /* D might not fit in 14 bits either; for such cases load D into
1744 if (GET_CODE (operand1) == MEM
1745 && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
1747 /* We are reloading the address into the scratch register, so we
1748 want to make sure the scratch register is a full register. */
1749 scratch_reg = force_mode (word_mode, scratch_reg);
1751 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1752 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1755 XEXP (XEXP (operand1, 0),
1759 /* Now we are going to load the scratch register from memory,
1760 we want to load it in the same width as the original MEM,
1761 which must be the same as the width of the ultimate destination,
1763 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1765 emit_move_insn (scratch_reg,
1766 replace_equiv_address (operand1, scratch_reg));
1770 /* We want to load the scratch register using the same mode as
1771 the ultimate destination. */
1772 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1774 emit_move_insn (scratch_reg, operand1);
1777 /* And emit the insn to set the ultimate destination. We know that
1778 the scratch register has the same mode as the destination at this
1780 emit_move_insn (operand0, scratch_reg);
1783 /* Handle the most common case: storing into a register. */
1784 else if (register_operand (operand0, mode))
1786 /* Legitimize TLS symbol references. This happens for references
1787 that aren't a legitimate constant. */
1788 if (PA_SYMBOL_REF_TLS_P (operand1))
1789 operand1 = legitimize_tls_address (operand1);
1791 if (register_operand (operand1, mode)
1792 || (GET_CODE (operand1) == CONST_INT
1793 && pa_cint_ok_for_move (INTVAL (operand1)))
1794 || (operand1 == CONST0_RTX (mode))
1795 || (GET_CODE (operand1) == HIGH
1796 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1797 /* Only `general_operands' can come here, so MEM is ok. */
1798 || GET_CODE (operand1) == MEM)
1800 /* Various sets are created during RTL generation which don't
1801 have the REG_POINTER flag correctly set. After the CSE pass,
1802 instruction recognition can fail if we don't consistently
1803 set this flag when performing register copies. This should
1804 also improve the opportunities for creating insns that use
1805 unscaled indexing. */
1806 if (REG_P (operand0) && REG_P (operand1))
1808 if (REG_POINTER (operand1)
1809 && !REG_POINTER (operand0)
1810 && !HARD_REGISTER_P (operand0))
1811 copy_reg_pointer (operand0, operand1);
1814 /* When MEMs are broken out, the REG_POINTER flag doesn't
1815 get set. In some cases, we can set the REG_POINTER flag
1816 from the declaration for the MEM. */
1817 if (REG_P (operand0)
1818 && GET_CODE (operand1) == MEM
1819 && !REG_POINTER (operand0))
1821 tree decl = MEM_EXPR (operand1);
1823 /* Set the register pointer flag and register alignment
1824 if the declaration for this memory reference is a
1830 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1832 if (TREE_CODE (decl) == COMPONENT_REF)
1833 decl = TREE_OPERAND (decl, 1);
1835 type = TREE_TYPE (decl);
1836 type = strip_array_types (type);
1838 if (POINTER_TYPE_P (type))
1842 type = TREE_TYPE (type);
1843 /* Using TYPE_ALIGN_OK is rather conservative as
1844 only the ada frontend actually sets it. */
1845 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1847 mark_reg_pointer (operand0, align);
1852 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1856 else if (GET_CODE (operand0) == MEM)
1858 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1859 && !(reload_in_progress || reload_completed))
1861 rtx temp = gen_reg_rtx (DFmode);
1863 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1864 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1867 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1869 /* Run this case quickly. */
1870 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1873 if (! (reload_in_progress || reload_completed))
1875 operands[0] = validize_mem (operand0);
1876 operands[1] = operand1 = force_reg (mode, operand1);
1880 /* Simplify the source if we need to.
1881 Note we do have to handle function labels here, even though we do
1882 not consider them legitimate constants. Loop optimizations can
1883 call the emit_move_xxx with one as a source. */
1884 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1885 || function_label_operand (operand1, VOIDmode)
1886 || (GET_CODE (operand1) == HIGH
1887 && symbolic_operand (XEXP (operand1, 0), mode)))
1891 if (GET_CODE (operand1) == HIGH)
1894 operand1 = XEXP (operand1, 0);
1896 if (symbolic_operand (operand1, mode))
1898 /* Argh. The assembler and linker can't handle arithmetic
1901 So we force the plabel into memory, load operand0 from
1902 the memory location, then add in the constant part. */
1903 if ((GET_CODE (operand1) == CONST
1904 && GET_CODE (XEXP (operand1, 0)) == PLUS
1905 && function_label_operand (XEXP (XEXP (operand1, 0), 0),
1907 || function_label_operand (operand1, VOIDmode))
1909 rtx temp, const_part;
1911 /* Figure out what (if any) scratch register to use. */
1912 if (reload_in_progress || reload_completed)
1914 scratch_reg = scratch_reg ? scratch_reg : operand0;
1915 /* SCRATCH_REG will hold an address and maybe the actual
1916 data. We want it in WORD_MODE regardless of what mode it
1917 was originally given to us. */
1918 scratch_reg = force_mode (word_mode, scratch_reg);
1921 scratch_reg = gen_reg_rtx (Pmode);
1923 if (GET_CODE (operand1) == CONST)
1925 /* Save away the constant part of the expression. */
1926 const_part = XEXP (XEXP (operand1, 0), 1);
1927 gcc_assert (GET_CODE (const_part) == CONST_INT);
1929 /* Force the function label into memory. */
1930 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1934 /* No constant part. */
1935 const_part = NULL_RTX;
1937 /* Force the function label into memory. */
1938 temp = force_const_mem (mode, operand1);
1942 /* Get the address of the memory location. PIC-ify it if
1944 temp = XEXP (temp, 0);
1946 temp = legitimize_pic_address (temp, mode, scratch_reg);
1948 /* Put the address of the memory location into our destination
1951 pa_emit_move_sequence (operands, mode, scratch_reg);
1953 /* Now load from the memory location into our destination
1955 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1956 pa_emit_move_sequence (operands, mode, scratch_reg);
1958 /* And add back in the constant part. */
1959 if (const_part != NULL_RTX)
1960 expand_inc (operand0, const_part);
1969 if (reload_in_progress || reload_completed)
1971 temp = scratch_reg ? scratch_reg : operand0;
1972 /* TEMP will hold an address and maybe the actual
1973 data. We want it in WORD_MODE regardless of what mode it
1974 was originally given to us. */
1975 temp = force_mode (word_mode, temp);
1978 temp = gen_reg_rtx (Pmode);
1980 /* (const (plus (symbol) (const_int))) must be forced to
1981 memory during/after reload if the const_int will not fit
1983 if (GET_CODE (operand1) == CONST
1984 && GET_CODE (XEXP (operand1, 0)) == PLUS
1985 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1986 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1987 && (reload_completed || reload_in_progress)
1990 rtx const_mem = force_const_mem (mode, operand1);
1991 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1993 operands[1] = replace_equiv_address (const_mem, operands[1]);
1994 pa_emit_move_sequence (operands, mode, temp);
1998 operands[1] = legitimize_pic_address (operand1, mode, temp);
1999 if (REG_P (operand0) && REG_P (operands[1]))
2000 copy_reg_pointer (operand0, operands[1]);
2001 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2004 /* On the HPPA, references to data space are supposed to use dp,
2005 register 27, but showing it in the RTL inhibits various cse
2006 and loop optimizations. */
2011 if (reload_in_progress || reload_completed)
2013 temp = scratch_reg ? scratch_reg : operand0;
2014 /* TEMP will hold an address and maybe the actual
2015 data. We want it in WORD_MODE regardless of what mode it
2016 was originally given to us. */
2017 temp = force_mode (word_mode, temp);
2020 temp = gen_reg_rtx (mode);
2022 /* Loading a SYMBOL_REF into a register makes that register
2023 safe to be used as the base in an indexed address.
2025 Don't mark hard registers though. That loses. */
2026 if (GET_CODE (operand0) == REG
2027 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2028 mark_reg_pointer (operand0, BITS_PER_UNIT);
2029 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2030 mark_reg_pointer (temp, BITS_PER_UNIT);
2033 set = gen_rtx_SET (mode, operand0, temp);
2035 set = gen_rtx_SET (VOIDmode,
2037 gen_rtx_LO_SUM (mode, temp, operand1));
2039 emit_insn (gen_rtx_SET (VOIDmode,
2041 gen_rtx_HIGH (mode, operand1)));
2047 else if (pa_tls_referenced_p (operand1))
2052 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
2054 addend = XEXP (XEXP (tmp, 0), 1);
2055 tmp = XEXP (XEXP (tmp, 0), 0);
2058 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
2059 tmp = legitimize_tls_address (tmp);
2062 tmp = gen_rtx_PLUS (mode, tmp, addend);
2063 tmp = force_operand (tmp, operands[0]);
2067 else if (GET_CODE (operand1) != CONST_INT
2068 || !pa_cint_ok_for_move (INTVAL (operand1)))
2072 HOST_WIDE_INT value = 0;
2073 HOST_WIDE_INT insv = 0;
2076 if (GET_CODE (operand1) == CONST_INT)
2077 value = INTVAL (operand1);
2080 && GET_CODE (operand1) == CONST_INT
2081 && HOST_BITS_PER_WIDE_INT > 32
2082 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2086 /* Extract the low order 32 bits of the value and sign extend.
2087 If the new value is the same as the original value, we can
2088 can use the original value as-is. If the new value is
2089 different, we use it and insert the most-significant 32-bits
2090 of the original value into the final result. */
2091 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2092 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2095 #if HOST_BITS_PER_WIDE_INT > 32
2096 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2100 operand1 = GEN_INT (nval);
2104 if (reload_in_progress || reload_completed)
2105 temp = scratch_reg ? scratch_reg : operand0;
2107 temp = gen_reg_rtx (mode);
2109 /* We don't directly split DImode constants on 32-bit targets
2110 because PLUS uses an 11-bit immediate and the insn sequence
2111 generated is not as efficient as the one using HIGH/LO_SUM. */
2112 if (GET_CODE (operand1) == CONST_INT
2113 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
2114 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2117 /* Directly break constant into high and low parts. This
2118 provides better optimization opportunities because various
2119 passes recognize constants split with PLUS but not LO_SUM.
2120 We use a 14-bit signed low part except when the addition
2121 of 0x4000 to the high part might change the sign of the
2123 HOST_WIDE_INT low = value & 0x3fff;
2124 HOST_WIDE_INT high = value & ~ 0x3fff;
2128 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2136 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2137 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2141 emit_insn (gen_rtx_SET (VOIDmode, temp,
2142 gen_rtx_HIGH (mode, operand1)));
2143 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2146 insn = emit_move_insn (operands[0], operands[1]);
2148 /* Now insert the most significant 32 bits of the value
2149 into the register. When we don't have a second register
2150 available, it could take up to nine instructions to load
2151 a 64-bit integer constant. Prior to reload, we force
2152 constants that would take more than three instructions
2153 to load to the constant pool. During and after reload,
2154 we have to handle all possible values. */
2157 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2158 register and the value to be inserted is outside the
2159 range that can be loaded with three depdi instructions. */
2160 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2162 operand1 = GEN_INT (insv);
2164 emit_insn (gen_rtx_SET (VOIDmode, temp,
2165 gen_rtx_HIGH (mode, operand1)));
2166 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2167 emit_insn (gen_insv (operand0, GEN_INT (32),
2172 int len = 5, pos = 27;
2174 /* Insert the bits using the depdi instruction. */
2177 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2178 HOST_WIDE_INT sign = v5 < 0;
2180 /* Left extend the insertion. */
2181 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2182 while (pos > 0 && (insv & 1) == sign)
2184 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2189 emit_insn (gen_insv (operand0, GEN_INT (len),
2190 GEN_INT (pos), GEN_INT (v5)));
2192 len = pos > 0 && pos < 5 ? pos : 5;
2198 set_unique_reg_note (insn, REG_EQUAL, op1);
2203 /* Now have insn-emit do whatever it normally does. */
2207 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2208 it will need a link/runtime reloc). */
2211 pa_reloc_needed (tree exp)
2215 switch (TREE_CODE (exp))
2220 case POINTER_PLUS_EXPR:
2223 reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
2224 reloc |= pa_reloc_needed (TREE_OPERAND (exp, 1));
2228 case NON_LVALUE_EXPR:
2229 reloc = pa_reloc_needed (TREE_OPERAND (exp, 0));
2235 unsigned HOST_WIDE_INT ix;
2237 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2239 reloc |= pa_reloc_needed (value);
2253 /* Return the best assembler insn template
2254 for moving operands[1] into operands[0] as a fullword. */
2256 pa_singlemove_string (rtx *operands)
2258 HOST_WIDE_INT intval;
2260 if (GET_CODE (operands[0]) == MEM)
2261 return "stw %r1,%0";
2262 if (GET_CODE (operands[1]) == MEM)
2264 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2269 gcc_assert (GET_MODE (operands[1]) == SFmode);
2271 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2273 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2274 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2276 operands[1] = GEN_INT (i);
2277 /* Fall through to CONST_INT case. */
2279 if (GET_CODE (operands[1]) == CONST_INT)
2281 intval = INTVAL (operands[1]);
2283 if (VAL_14_BITS_P (intval))
2285 else if ((intval & 0x7ff) == 0)
2286 return "ldil L'%1,%0";
2287 else if (pa_zdepi_cint_p (intval))
2288 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2290 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2292 return "copy %1,%0";
2296 /* Compute position (in OP[1]) and width (in OP[2])
2297 useful for copying IMM to a register using the zdepi
2298 instructions. Store the immediate value to insert in OP[0]. */
2300 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2304 /* Find the least significant set bit in IMM. */
2305 for (lsb = 0; lsb < 32; lsb++)
2312 /* Choose variants based on *sign* of the 5-bit field. */
2313 if ((imm & 0x10) == 0)
2314 len = (lsb <= 28) ? 4 : 32 - lsb;
2317 /* Find the width of the bitstring in IMM. */
2318 for (len = 5; len < 32 - lsb; len++)
2320 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2324 /* Sign extend IMM as a 5-bit value. */
2325 imm = (imm & 0xf) - 0x10;
2333 /* Compute position (in OP[1]) and width (in OP[2])
2334 useful for copying IMM to a register using the depdi,z
2335 instructions. Store the immediate value to insert in OP[0]. */
2338 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2340 int lsb, len, maxlen;
2342 maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64);
2344 /* Find the least significant set bit in IMM. */
2345 for (lsb = 0; lsb < maxlen; lsb++)
2352 /* Choose variants based on *sign* of the 5-bit field. */
2353 if ((imm & 0x10) == 0)
2354 len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb;
2357 /* Find the width of the bitstring in IMM. */
2358 for (len = 5; len < maxlen - lsb; len++)
2360 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2364 /* Extend length if host is narrow and IMM is negative. */
2365 if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb)
2368 /* Sign extend IMM as a 5-bit value. */
2369 imm = (imm & 0xf) - 0x10;
2377 /* Output assembler code to perform a doubleword move insn
2378 with operands OPERANDS. */
2381 pa_output_move_double (rtx *operands)
2383 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2385 rtx addreg0 = 0, addreg1 = 0;
2387 /* First classify both operands. */
2389 if (REG_P (operands[0]))
2391 else if (offsettable_memref_p (operands[0]))
2393 else if (GET_CODE (operands[0]) == MEM)
2398 if (REG_P (operands[1]))
2400 else if (CONSTANT_P (operands[1]))
2402 else if (offsettable_memref_p (operands[1]))
2404 else if (GET_CODE (operands[1]) == MEM)
2409 /* Check for the cases that the operand constraints are not
2410 supposed to allow to happen. */
2411 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2413 /* Handle copies between general and floating registers. */
2415 if (optype0 == REGOP && optype1 == REGOP
2416 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2418 if (FP_REG_P (operands[0]))
2420 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2421 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2422 return "{fldds|fldd} -16(%%sp),%0";
2426 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2427 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2428 return "{ldws|ldw} -12(%%sp),%R0";
2432 /* Handle auto decrementing and incrementing loads and stores
2433 specifically, since the structure of the function doesn't work
2434 for them without major modification. Do it better when we learn
2435 this port about the general inc/dec addressing of PA.
2436 (This was written by tege. Chide him if it doesn't work.) */
2438 if (optype0 == MEMOP)
2440 /* We have to output the address syntax ourselves, since print_operand
2441 doesn't deal with the addresses we want to use. Fix this later. */
2443 rtx addr = XEXP (operands[0], 0);
2444 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2446 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2448 operands[0] = XEXP (addr, 0);
2449 gcc_assert (GET_CODE (operands[1]) == REG
2450 && GET_CODE (operands[0]) == REG);
2452 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2454 /* No overlap between high target register and address
2455 register. (We do this in a non-obvious way to
2456 save a register file writeback) */
2457 if (GET_CODE (addr) == POST_INC)
2458 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2459 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2461 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2463 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2465 operands[0] = XEXP (addr, 0);
2466 gcc_assert (GET_CODE (operands[1]) == REG
2467 && GET_CODE (operands[0]) == REG);
2469 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2470 /* No overlap between high target register and address
2471 register. (We do this in a non-obvious way to save a
2472 register file writeback) */
2473 if (GET_CODE (addr) == PRE_INC)
2474 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2475 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2478 if (optype1 == MEMOP)
2480 /* We have to output the address syntax ourselves, since print_operand
2481 doesn't deal with the addresses we want to use. Fix this later. */
2483 rtx addr = XEXP (operands[1], 0);
2484 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2486 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2488 operands[1] = XEXP (addr, 0);
2489 gcc_assert (GET_CODE (operands[0]) == REG
2490 && GET_CODE (operands[1]) == REG);
2492 if (!reg_overlap_mentioned_p (high_reg, addr))
2494 /* No overlap between high target register and address
2495 register. (We do this in a non-obvious way to
2496 save a register file writeback) */
2497 if (GET_CODE (addr) == POST_INC)
2498 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2499 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2503 /* This is an undefined situation. We should load into the
2504 address register *and* update that register. Probably
2505 we don't need to handle this at all. */
2506 if (GET_CODE (addr) == POST_INC)
2507 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2508 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2511 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2513 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2515 operands[1] = XEXP (addr, 0);
2516 gcc_assert (GET_CODE (operands[0]) == REG
2517 && GET_CODE (operands[1]) == REG);
2519 if (!reg_overlap_mentioned_p (high_reg, addr))
2521 /* No overlap between high target register and address
2522 register. (We do this in a non-obvious way to
2523 save a register file writeback) */
2524 if (GET_CODE (addr) == PRE_INC)
2525 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2526 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2530 /* This is an undefined situation. We should load into the
2531 address register *and* update that register. Probably
2532 we don't need to handle this at all. */
2533 if (GET_CODE (addr) == PRE_INC)
2534 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2535 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2538 else if (GET_CODE (addr) == PLUS
2539 && GET_CODE (XEXP (addr, 0)) == MULT)
2542 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2544 if (!reg_overlap_mentioned_p (high_reg, addr))
2546 xoperands[0] = high_reg;
2547 xoperands[1] = XEXP (addr, 1);
2548 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2549 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2550 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2552 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2556 xoperands[0] = high_reg;
2557 xoperands[1] = XEXP (addr, 1);
2558 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2559 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2560 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2562 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2567 /* If an operand is an unoffsettable memory ref, find a register
2568 we can increment temporarily to make it refer to the second word. */
2570 if (optype0 == MEMOP)
2571 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2573 if (optype1 == MEMOP)
2574 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2576 /* Ok, we can do one word at a time.
2577 Normally we do the low-numbered word first.
2579 In either case, set up in LATEHALF the operands to use
2580 for the high-numbered word and in some cases alter the
2581 operands in OPERANDS to be suitable for the low-numbered word. */
2583 if (optype0 == REGOP)
2584 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2585 else if (optype0 == OFFSOP)
2586 latehalf[0] = adjust_address (operands[0], SImode, 4);
2588 latehalf[0] = operands[0];
2590 if (optype1 == REGOP)
2591 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2592 else if (optype1 == OFFSOP)
2593 latehalf[1] = adjust_address (operands[1], SImode, 4);
2594 else if (optype1 == CNSTOP)
2595 split_double (operands[1], &operands[1], &latehalf[1]);
2597 latehalf[1] = operands[1];
2599 /* If the first move would clobber the source of the second one,
2600 do them in the other order.
2602 This can happen in two cases:
2604 mem -> register where the first half of the destination register
2605 is the same register used in the memory's address. Reload
2606 can create such insns.
2608 mem in this case will be either register indirect or register
2609 indirect plus a valid offset.
2611 register -> register move where REGNO(dst) == REGNO(src + 1)
2612 someone (Tim/Tege?) claimed this can happen for parameter loads.
2614 Handle mem -> register case first. */
2615 if (optype0 == REGOP
2616 && (optype1 == MEMOP || optype1 == OFFSOP)
2617 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2620 /* Do the late half first. */
2622 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2623 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2627 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2628 return pa_singlemove_string (operands);
2631 /* Now handle register -> register case. */
2632 if (optype0 == REGOP && optype1 == REGOP
2633 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2635 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2636 return pa_singlemove_string (operands);
2639 /* Normal case: do the two words, low-numbered first. */
2641 output_asm_insn (pa_singlemove_string (operands), operands);
2643 /* Make any unoffsettable addresses point at high-numbered word. */
2645 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2647 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2650 output_asm_insn (pa_singlemove_string (latehalf), latehalf);
2652 /* Undo the adds we just did. */
2654 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2656 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2662 pa_output_fp_move_double (rtx *operands)
2664 if (FP_REG_P (operands[0]))
2666 if (FP_REG_P (operands[1])
2667 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2668 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2670 output_asm_insn ("fldd%F1 %1,%0", operands);
2672 else if (FP_REG_P (operands[1]))
2674 output_asm_insn ("fstd%F0 %1,%0", operands);
2680 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2682 /* This is a pain. You have to be prepared to deal with an
2683 arbitrary address here including pre/post increment/decrement.
2685 so avoid this in the MD. */
2686 gcc_assert (GET_CODE (operands[0]) == REG);
2688 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2689 xoperands[0] = operands[0];
2690 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2695 /* Return a REG that occurs in ADDR with coefficient 1.
2696 ADDR can be effectively incremented by incrementing REG. */
2699 find_addr_reg (rtx addr)
2701 while (GET_CODE (addr) == PLUS)
2703 if (GET_CODE (XEXP (addr, 0)) == REG)
2704 addr = XEXP (addr, 0);
2705 else if (GET_CODE (XEXP (addr, 1)) == REG)
2706 addr = XEXP (addr, 1);
2707 else if (CONSTANT_P (XEXP (addr, 0)))
2708 addr = XEXP (addr, 1);
2709 else if (CONSTANT_P (XEXP (addr, 1)))
2710 addr = XEXP (addr, 0);
2714 gcc_assert (GET_CODE (addr) == REG);
2718 /* Emit code to perform a block move.
2720 OPERANDS[0] is the destination pointer as a REG, clobbered.
2721 OPERANDS[1] is the source pointer as a REG, clobbered.
2722 OPERANDS[2] is a register for temporary storage.
2723 OPERANDS[3] is a register for temporary storage.
2724 OPERANDS[4] is the size as a CONST_INT
2725 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2726 OPERANDS[6] is another temporary register. */
2729 pa_output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2731 int align = INTVAL (operands[5]);
2732 unsigned long n_bytes = INTVAL (operands[4]);
2734 /* We can't move more than a word at a time because the PA
2735 has no longer integer move insns. (Could use fp mem ops?) */
2736 if (align > (TARGET_64BIT ? 8 : 4))
2737 align = (TARGET_64BIT ? 8 : 4);
2739 /* Note that we know each loop below will execute at least twice
2740 (else we would have open-coded the copy). */
2744 /* Pre-adjust the loop counter. */
2745 operands[4] = GEN_INT (n_bytes - 16);
2746 output_asm_insn ("ldi %4,%2", operands);
2749 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2750 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2751 output_asm_insn ("std,ma %3,8(%0)", operands);
2752 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2753 output_asm_insn ("std,ma %6,8(%0)", operands);
2755 /* Handle the residual. There could be up to 7 bytes of
2756 residual to copy! */
2757 if (n_bytes % 16 != 0)
2759 operands[4] = GEN_INT (n_bytes % 8);
2760 if (n_bytes % 16 >= 8)
2761 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2762 if (n_bytes % 8 != 0)
2763 output_asm_insn ("ldd 0(%1),%6", operands);
2764 if (n_bytes % 16 >= 8)
2765 output_asm_insn ("std,ma %3,8(%0)", operands);
2766 if (n_bytes % 8 != 0)
2767 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2772 /* Pre-adjust the loop counter. */
2773 operands[4] = GEN_INT (n_bytes - 8);
2774 output_asm_insn ("ldi %4,%2", operands);
2777 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2778 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2779 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2780 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2781 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2783 /* Handle the residual. There could be up to 7 bytes of
2784 residual to copy! */
2785 if (n_bytes % 8 != 0)
2787 operands[4] = GEN_INT (n_bytes % 4);
2788 if (n_bytes % 8 >= 4)
2789 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2790 if (n_bytes % 4 != 0)
2791 output_asm_insn ("ldw 0(%1),%6", operands);
2792 if (n_bytes % 8 >= 4)
2793 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2794 if (n_bytes % 4 != 0)
2795 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2800 /* Pre-adjust the loop counter. */
2801 operands[4] = GEN_INT (n_bytes - 4);
2802 output_asm_insn ("ldi %4,%2", operands);
2805 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2806 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2807 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2808 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2809 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2811 /* Handle the residual. */
2812 if (n_bytes % 4 != 0)
2814 if (n_bytes % 4 >= 2)
2815 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2816 if (n_bytes % 2 != 0)
2817 output_asm_insn ("ldb 0(%1),%6", operands);
2818 if (n_bytes % 4 >= 2)
2819 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2820 if (n_bytes % 2 != 0)
2821 output_asm_insn ("stb %6,0(%0)", operands);
2826 /* Pre-adjust the loop counter. */
2827 operands[4] = GEN_INT (n_bytes - 2);
2828 output_asm_insn ("ldi %4,%2", operands);
2831 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2832 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2833 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2834 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2835 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2837 /* Handle the residual. */
2838 if (n_bytes % 2 != 0)
2840 output_asm_insn ("ldb 0(%1),%3", operands);
2841 output_asm_insn ("stb %3,0(%0)", operands);
2850 /* Count the number of insns necessary to handle this block move.
2852 Basic structure is the same as emit_block_move, except that we
2853 count insns rather than emit them. */
2856 compute_movmem_length (rtx insn)
2858 rtx pat = PATTERN (insn);
2859 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2860 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2861 unsigned int n_insns = 0;
2863 /* We can't move more than four bytes at a time because the PA
2864 has no longer integer move insns. (Could use fp mem ops?) */
2865 if (align > (TARGET_64BIT ? 8 : 4))
2866 align = (TARGET_64BIT ? 8 : 4);
2868 /* The basic copying loop. */
2872 if (n_bytes % (2 * align) != 0)
2874 if ((n_bytes % (2 * align)) >= align)
2877 if ((n_bytes % align) != 0)
2881 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2885 /* Emit code to perform a block clear.
2887 OPERANDS[0] is the destination pointer as a REG, clobbered.
2888 OPERANDS[1] is a register for temporary storage.
2889 OPERANDS[2] is the size as a CONST_INT
2890 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2893 pa_output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2895 int align = INTVAL (operands[3]);
2896 unsigned long n_bytes = INTVAL (operands[2]);
2898 /* We can't clear more than a word at a time because the PA
2899 has no longer integer move insns. */
2900 if (align > (TARGET_64BIT ? 8 : 4))
2901 align = (TARGET_64BIT ? 8 : 4);
2903 /* Note that we know each loop below will execute at least twice
2904 (else we would have open-coded the copy). */
2908 /* Pre-adjust the loop counter. */
2909 operands[2] = GEN_INT (n_bytes - 16);
2910 output_asm_insn ("ldi %2,%1", operands);
2913 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2914 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2915 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2917 /* Handle the residual. There could be up to 7 bytes of
2918 residual to copy! */
2919 if (n_bytes % 16 != 0)
2921 operands[2] = GEN_INT (n_bytes % 8);
2922 if (n_bytes % 16 >= 8)
2923 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2924 if (n_bytes % 8 != 0)
2925 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2930 /* Pre-adjust the loop counter. */
2931 operands[2] = GEN_INT (n_bytes - 8);
2932 output_asm_insn ("ldi %2,%1", operands);
2935 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2936 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2937 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2939 /* Handle the residual. There could be up to 7 bytes of
2940 residual to copy! */
2941 if (n_bytes % 8 != 0)
2943 operands[2] = GEN_INT (n_bytes % 4);
2944 if (n_bytes % 8 >= 4)
2945 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2946 if (n_bytes % 4 != 0)
2947 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2952 /* Pre-adjust the loop counter. */
2953 operands[2] = GEN_INT (n_bytes - 4);
2954 output_asm_insn ("ldi %2,%1", operands);
2957 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2958 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2959 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2961 /* Handle the residual. */
2962 if (n_bytes % 4 != 0)
2964 if (n_bytes % 4 >= 2)
2965 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2966 if (n_bytes % 2 != 0)
2967 output_asm_insn ("stb %%r0,0(%0)", operands);
2972 /* Pre-adjust the loop counter. */
2973 operands[2] = GEN_INT (n_bytes - 2);
2974 output_asm_insn ("ldi %2,%1", operands);
2977 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2978 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2979 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2981 /* Handle the residual. */
2982 if (n_bytes % 2 != 0)
2983 output_asm_insn ("stb %%r0,0(%0)", operands);
2992 /* Count the number of insns necessary to handle this block move.
2994 Basic structure is the same as emit_block_move, except that we
2995 count insns rather than emit them. */
2998 compute_clrmem_length (rtx insn)
3000 rtx pat = PATTERN (insn);
3001 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3002 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3003 unsigned int n_insns = 0;
3005 /* We can't clear more than a word at a time because the PA
3006 has no longer integer move insns. */
3007 if (align > (TARGET_64BIT ? 8 : 4))
3008 align = (TARGET_64BIT ? 8 : 4);
3010 /* The basic loop. */
3014 if (n_bytes % (2 * align) != 0)
3016 if ((n_bytes % (2 * align)) >= align)
3019 if ((n_bytes % align) != 0)
3023 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3029 pa_output_and (rtx *operands)
3031 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3033 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3034 int ls0, ls1, ms0, p, len;
3036 for (ls0 = 0; ls0 < 32; ls0++)
3037 if ((mask & (1 << ls0)) == 0)
3040 for (ls1 = ls0; ls1 < 32; ls1++)
3041 if ((mask & (1 << ls1)) != 0)
3044 for (ms0 = ls1; ms0 < 32; ms0++)
3045 if ((mask & (1 << ms0)) == 0)
3048 gcc_assert (ms0 == 32);
3056 operands[2] = GEN_INT (len);
3057 return "{extru|extrw,u} %1,31,%2,%0";
3061 /* We could use this `depi' for the case above as well, but `depi'
3062 requires one more register file access than an `extru'. */
3067 operands[2] = GEN_INT (p);
3068 operands[3] = GEN_INT (len);
3069 return "{depi|depwi} 0,%2,%3,%0";
3073 return "and %1,%2,%0";
3076 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3077 storing the result in operands[0]. */
3079 pa_output_64bit_and (rtx *operands)
3081 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3083 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3084 int ls0, ls1, ms0, p, len;
3086 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3087 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3090 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3091 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3094 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3095 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3098 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
3100 if (ls1 == HOST_BITS_PER_WIDE_INT)
3106 operands[2] = GEN_INT (len);
3107 return "extrd,u %1,63,%2,%0";
3111 /* We could use this `depi' for the case above as well, but `depi'
3112 requires one more register file access than an `extru'. */
3117 operands[2] = GEN_INT (p);
3118 operands[3] = GEN_INT (len);
3119 return "depdi 0,%2,%3,%0";
3123 return "and %1,%2,%0";
3127 pa_output_ior (rtx *operands)
3129 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3130 int bs0, bs1, p, len;
3132 if (INTVAL (operands[2]) == 0)
3133 return "copy %1,%0";
3135 for (bs0 = 0; bs0 < 32; bs0++)
3136 if ((mask & (1 << bs0)) != 0)
3139 for (bs1 = bs0; bs1 < 32; bs1++)
3140 if ((mask & (1 << bs1)) == 0)
3143 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3148 operands[2] = GEN_INT (p);
3149 operands[3] = GEN_INT (len);
3150 return "{depi|depwi} -1,%2,%3,%0";
3153 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3154 storing the result in operands[0]. */
3156 pa_output_64bit_ior (rtx *operands)
3158 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3159 int bs0, bs1, p, len;
3161 if (INTVAL (operands[2]) == 0)
3162 return "copy %1,%0";
3164 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3165 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3168 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3169 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3172 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3173 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3178 operands[2] = GEN_INT (p);
3179 operands[3] = GEN_INT (len);
3180 return "depdi -1,%2,%3,%0";
3183 /* Target hook for assembling integer objects. This code handles
3184 aligned SI and DI integers specially since function references
3185 must be preceded by P%. */
3188 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3190 if (size == UNITS_PER_WORD
3192 && function_label_operand (x, VOIDmode))
3194 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3195 output_addr_const (asm_out_file, x);
3196 fputc ('\n', asm_out_file);
3199 return default_assemble_integer (x, size, aligned_p);
3202 /* Output an ascii string. */
3204 pa_output_ascii (FILE *file, const char *p, int size)
3208 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3210 /* The HP assembler can only take strings of 256 characters at one
3211 time. This is a limitation on input line length, *not* the
3212 length of the string. Sigh. Even worse, it seems that the
3213 restriction is in number of input characters (see \xnn &
3214 \whatever). So we have to do this very carefully. */
3216 fputs ("\t.STRING \"", file);
3219 for (i = 0; i < size; i += 4)
3223 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3225 register unsigned int c = (unsigned char) p[i + io];
3227 if (c == '\"' || c == '\\')
3228 partial_output[co++] = '\\';
3229 if (c >= ' ' && c < 0177)
3230 partial_output[co++] = c;
3234 partial_output[co++] = '\\';
3235 partial_output[co++] = 'x';
3236 hexd = c / 16 - 0 + '0';
3238 hexd -= '9' - 'a' + 1;
3239 partial_output[co++] = hexd;
3240 hexd = c % 16 - 0 + '0';
3242 hexd -= '9' - 'a' + 1;
3243 partial_output[co++] = hexd;
3246 if (chars_output + co > 243)
3248 fputs ("\"\n\t.STRING \"", file);
3251 fwrite (partial_output, 1, (size_t) co, file);
3255 fputs ("\"\n", file);
3258 /* Try to rewrite floating point comparisons & branches to avoid
3259 useless add,tr insns.
3261 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3262 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3263 first attempt to remove useless add,tr insns. It is zero
3264 for the second pass as reorg sometimes leaves bogus REG_DEAD
3267 When CHECK_NOTES is zero we can only eliminate add,tr insns
3268 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3271 remove_useless_addtr_insns (int check_notes)
3274 static int pass = 0;
3276 /* This is fairly cheap, so always run it when optimizing. */
3280 int fbranch_count = 0;
3282 /* Walk all the insns in this function looking for fcmp & fbranch
3283 instructions. Keep track of how many of each we find. */
3284 for (insn = get_insns (); insn; insn = next_insn (insn))
3288 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3289 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3292 tmp = PATTERN (insn);
3294 /* It must be a set. */
3295 if (GET_CODE (tmp) != SET)
3298 /* If the destination is CCFP, then we've found an fcmp insn. */
3299 tmp = SET_DEST (tmp);
3300 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3306 tmp = PATTERN (insn);
3307 /* If this is an fbranch instruction, bump the fbranch counter. */
3308 if (GET_CODE (tmp) == SET
3309 && SET_DEST (tmp) == pc_rtx
3310 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3311 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3312 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3313 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3321 /* Find all floating point compare + branch insns. If possible,
3322 reverse the comparison & the branch to avoid add,tr insns. */
3323 for (insn = get_insns (); insn; insn = next_insn (insn))
3327 /* Ignore anything that isn't an INSN. */
3328 if (GET_CODE (insn) != INSN)
3331 tmp = PATTERN (insn);
3333 /* It must be a set. */
3334 if (GET_CODE (tmp) != SET)
3337 /* The destination must be CCFP, which is register zero. */
3338 tmp = SET_DEST (tmp);
3339 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3342 /* INSN should be a set of CCFP.
3344 See if the result of this insn is used in a reversed FP
3345 conditional branch. If so, reverse our condition and
3346 the branch. Doing so avoids useless add,tr insns. */
3347 next = next_insn (insn);
3350 /* Jumps, calls and labels stop our search. */
3351 if (GET_CODE (next) == JUMP_INSN
3352 || GET_CODE (next) == CALL_INSN
3353 || GET_CODE (next) == CODE_LABEL)
3356 /* As does another fcmp insn. */
3357 if (GET_CODE (next) == INSN
3358 && GET_CODE (PATTERN (next)) == SET
3359 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3360 && REGNO (SET_DEST (PATTERN (next))) == 0)
3363 next = next_insn (next);
3366 /* Is NEXT_INSN a branch? */
3368 && GET_CODE (next) == JUMP_INSN)
3370 rtx pattern = PATTERN (next);
3372 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3373 and CCFP dies, then reverse our conditional and the branch
3374 to avoid the add,tr. */
3375 if (GET_CODE (pattern) == SET
3376 && SET_DEST (pattern) == pc_rtx
3377 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3378 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3379 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3380 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3381 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3382 && (fcmp_count == fbranch_count
3384 && find_regno_note (next, REG_DEAD, 0))))
3386 /* Reverse the branch. */
3387 tmp = XEXP (SET_SRC (pattern), 1);
3388 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3389 XEXP (SET_SRC (pattern), 2) = tmp;
3390 INSN_CODE (next) = -1;
3392 /* Reverse our condition. */
3393 tmp = PATTERN (insn);
3394 PUT_CODE (XEXP (tmp, 1),
3395 (reverse_condition_maybe_unordered
3396 (GET_CODE (XEXP (tmp, 1)))));
3406 /* You may have trouble believing this, but this is the 32 bit HP-PA
3411 Variable arguments (optional; any number may be allocated)
3413 SP-(4*(N+9)) arg word N
3418 Fixed arguments (must be allocated; may remain unused)
3427 SP-32 External Data Pointer (DP)
3429 SP-24 External/stub RP (RP')
3433 SP-8 Calling Stub RP (RP'')
3438 SP-0 Stack Pointer (points to next available address)
3442 /* This function saves registers as follows. Registers marked with ' are
3443 this function's registers (as opposed to the previous function's).
3444 If a frame_pointer isn't needed, r4 is saved as a general register;
3445 the space for the frame pointer is still allocated, though, to keep
3451 SP (FP') Previous FP
3452 SP + 4 Alignment filler (sigh)
3453 SP + 8 Space for locals reserved here.
3457 SP + n All call saved register used.
3461 SP + o All call saved fp registers used.
3465 SP + p (SP') points to next available address.
3469 /* Global variables set by output_function_prologue(). */
3470 /* Size of frame. Need to know this to emit return insns from
3472 static HOST_WIDE_INT actual_fsize, local_fsize;
3473 static int save_fregs;
3475 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3476 Handle case where DISP > 8k by using the add_high_const patterns.
3478 Note in DISP > 8k case, we will leave the high part of the address
3479 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3482 store_reg (int reg, HOST_WIDE_INT disp, int base)
3484 rtx insn, dest, src, basereg;
3486 src = gen_rtx_REG (word_mode, reg);
3487 basereg = gen_rtx_REG (Pmode, base);
3488 if (VAL_14_BITS_P (disp))
3490 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3491 insn = emit_move_insn (dest, src);
3493 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3495 rtx delta = GEN_INT (disp);
3496 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3498 emit_move_insn (tmpreg, delta);
3499 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3502 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3503 gen_rtx_SET (VOIDmode, tmpreg,
3504 gen_rtx_PLUS (Pmode, basereg, delta)));
3505 RTX_FRAME_RELATED_P (insn) = 1;
3507 dest = gen_rtx_MEM (word_mode, tmpreg);
3508 insn = emit_move_insn (dest, src);
3512 rtx delta = GEN_INT (disp);
3513 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3514 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3516 emit_move_insn (tmpreg, high);
3517 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3518 insn = emit_move_insn (dest, src);
3520 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3521 gen_rtx_SET (VOIDmode,
3522 gen_rtx_MEM (word_mode,
3523 gen_rtx_PLUS (word_mode,
3530 RTX_FRAME_RELATED_P (insn) = 1;
3533 /* Emit RTL to store REG at the memory location specified by BASE and then
3534 add MOD to BASE. MOD must be <= 8k. */
3537 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3539 rtx insn, basereg, srcreg, delta;
3541 gcc_assert (VAL_14_BITS_P (mod));
3543 basereg = gen_rtx_REG (Pmode, base);
3544 srcreg = gen_rtx_REG (word_mode, reg);
3545 delta = GEN_INT (mod);
3547 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3550 RTX_FRAME_RELATED_P (insn) = 1;
3552 /* RTX_FRAME_RELATED_P must be set on each frame related set
3553 in a parallel with more than one element. */
3554 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3555 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3559 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3560 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3561 whether to add a frame note or not.
3563 In the DISP > 8k case, we leave the high part of the address in %r1.
3564 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3567 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3571 if (VAL_14_BITS_P (disp))
3573 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3574 plus_constant (gen_rtx_REG (Pmode, base), disp));
3576 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3578 rtx basereg = gen_rtx_REG (Pmode, base);
3579 rtx delta = GEN_INT (disp);
3580 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3582 emit_move_insn (tmpreg, delta);
3583 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3584 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3586 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3587 gen_rtx_SET (VOIDmode, tmpreg,
3588 gen_rtx_PLUS (Pmode, basereg, delta)));
3592 rtx basereg = gen_rtx_REG (Pmode, base);
3593 rtx delta = GEN_INT (disp);
3594 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3596 emit_move_insn (tmpreg,
3597 gen_rtx_PLUS (Pmode, basereg,
3598 gen_rtx_HIGH (Pmode, delta)));
3599 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3600 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3603 if (DO_FRAME_NOTES && note)
3604 RTX_FRAME_RELATED_P (insn) = 1;
3608 pa_compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3613 /* The code in pa_expand_prologue and pa_expand_epilogue must
3614 be consistent with the rounding and size calculation done here.
3615 Change them at the same time. */
3617 /* We do our own stack alignment. First, round the size of the
3618 stack locals up to a word boundary. */
3619 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3621 /* Space for previous frame pointer + filler. If any frame is
3622 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3623 waste some space here for the sake of HP compatibility. The
3624 first slot is only used when the frame pointer is needed. */
3625 if (size || frame_pointer_needed)
3626 size += STARTING_FRAME_OFFSET;
3628 /* If the current function calls __builtin_eh_return, then we need
3629 to allocate stack space for registers that will hold data for
3630 the exception handler. */
3631 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3635 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3637 size += i * UNITS_PER_WORD;
3640 /* Account for space used by the callee general register saves. */
3641 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3642 if (df_regs_ever_live_p (i))
3643 size += UNITS_PER_WORD;
3645 /* Account for space used by the callee floating point register saves. */
3646 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3647 if (df_regs_ever_live_p (i)
3648 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3652 /* We always save both halves of the FP register, so always
3653 increment the frame size by 8 bytes. */
3657 /* If any of the floating registers are saved, account for the
3658 alignment needed for the floating point register save block. */
3661 size = (size + 7) & ~7;
3666 /* The various ABIs include space for the outgoing parameters in the
3667 size of the current function's stack frame. We don't need to align
3668 for the outgoing arguments as their alignment is set by the final
3669 rounding for the frame as a whole. */
3670 size += crtl->outgoing_args_size;
3672 /* Allocate space for the fixed frame marker. This space must be
3673 allocated for any function that makes calls or allocates
3675 if (!current_function_is_leaf || size)
3676 size += TARGET_64BIT ? 48 : 32;
3678 /* Finally, round to the preferred stack boundary. */
3679 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3680 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3683 /* Generate the assembly code for function entry. FILE is a stdio
3684 stream to output the code to. SIZE is an int: how many units of
3685 temporary storage to allocate.
3687 Refer to the array `regs_ever_live' to determine which registers to
3688 save; `regs_ever_live[I]' is nonzero if register number I is ever
3689 used in the function. This function is responsible for knowing
3690 which registers should not be saved even if used. */
3692 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3693 of memory. If any fpu reg is used in the function, we allocate
3694 such a block here, at the bottom of the frame, just in case it's needed.
3696 If this function is a leaf procedure, then we may choose not
3697 to do a "save" insn. The decision about whether or not
3698 to do this is made in regclass.c. */
3701 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3703 /* The function's label and associated .PROC must never be
3704 separated and must be output *after* any profiling declarations
3705 to avoid changing spaces/subspaces within a procedure. */
3706 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3707 fputs ("\t.PROC\n", file);
3709 /* pa_expand_prologue does the dirty work now. We just need
3710 to output the assembler directives which denote the start
3712 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3713 if (current_function_is_leaf)
3714 fputs (",NO_CALLS", file);
3716 fputs (",CALLS", file);
3718 fputs (",SAVE_RP", file);
3720 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3721 at the beginning of the frame and that it is used as the frame
3722 pointer for the frame. We do this because our current frame
3723 layout doesn't conform to that specified in the HP runtime
3724 documentation and we need a way to indicate to programs such as
3725 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3726 isn't used by HP compilers but is supported by the assembler.
3727 However, SAVE_SP is supposed to indicate that the previous stack
3728 pointer has been saved in the frame marker. */
3729 if (frame_pointer_needed)
3730 fputs (",SAVE_SP", file);
3732 /* Pass on information about the number of callee register saves
3733 performed in the prologue.
3735 The compiler is supposed to pass the highest register number
3736 saved, the assembler then has to adjust that number before
3737 entering it into the unwind descriptor (to account for any
3738 caller saved registers with lower register numbers than the
3739 first callee saved register). */
3741 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3744 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3746 fputs ("\n\t.ENTRY\n", file);
3748 remove_useless_addtr_insns (0);
3752 pa_expand_prologue (void)
3754 int merge_sp_adjust_with_store = 0;
3755 HOST_WIDE_INT size = get_frame_size ();
3756 HOST_WIDE_INT offset;
3764 /* Compute total size for frame pointer, filler, locals and rounding to
3765 the next word boundary. Similar code appears in pa_compute_frame_size
3766 and must be changed in tandem with this code. */
3767 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3768 if (local_fsize || frame_pointer_needed)
3769 local_fsize += STARTING_FRAME_OFFSET;
3771 actual_fsize = pa_compute_frame_size (size, &save_fregs);
3772 if (flag_stack_usage_info)
3773 current_function_static_stack_size = actual_fsize;
3775 /* Compute a few things we will use often. */
3776 tmpreg = gen_rtx_REG (word_mode, 1);
3778 /* Save RP first. The calling conventions manual states RP will
3779 always be stored into the caller's frame at sp - 20 or sp - 16
3780 depending on which ABI is in use. */
3781 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3783 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3789 /* Allocate the local frame and set up the frame pointer if needed. */
3790 if (actual_fsize != 0)
3792 if (frame_pointer_needed)
3794 /* Copy the old frame pointer temporarily into %r1. Set up the
3795 new stack pointer, then store away the saved old frame pointer
3796 into the stack at sp and at the same time update the stack
3797 pointer by actual_fsize bytes. Two versions, first
3798 handles small (<8k) frames. The second handles large (>=8k)
3800 insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx);
3802 RTX_FRAME_RELATED_P (insn) = 1;
3804 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3806 RTX_FRAME_RELATED_P (insn) = 1;
3808 if (VAL_14_BITS_P (actual_fsize))
3809 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3812 /* It is incorrect to store the saved frame pointer at *sp,
3813 then increment sp (writes beyond the current stack boundary).
3815 So instead use stwm to store at *sp and post-increment the
3816 stack pointer as an atomic operation. Then increment sp to
3817 finish allocating the new frame. */
3818 HOST_WIDE_INT adjust1 = 8192 - 64;
3819 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3821 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3822 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3826 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3827 we need to store the previous stack pointer (frame pointer)
3828 into the frame marker on targets that use the HP unwind
3829 library. This allows the HP unwind library to be used to
3830 unwind GCC frames. However, we are not fully compatible
3831 with the HP library because our frame layout differs from
3832 that specified in the HP runtime specification.
3834 We don't want a frame note on this instruction as the frame
3835 marker moves during dynamic stack allocation.
3837 This instruction also serves as a blockage to prevent
3838 register spills from being scheduled before the stack
3839 pointer is raised. This is necessary as we store
3840 registers using the frame pointer as a base register,
3841 and the frame pointer is set before sp is raised. */
3842 if (TARGET_HPUX_UNWIND_LIBRARY)
3844 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3845 GEN_INT (TARGET_64BIT ? -8 : -4));
3847 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3848 hard_frame_pointer_rtx);
3851 emit_insn (gen_blockage ());
3853 /* no frame pointer needed. */
3856 /* In some cases we can perform the first callee register save
3857 and allocating the stack frame at the same time. If so, just
3858 make a note of it and defer allocating the frame until saving
3859 the callee registers. */
3860 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3861 merge_sp_adjust_with_store = 1;
3862 /* Can not optimize. Adjust the stack frame by actual_fsize
3865 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3870 /* Normal register save.
3872 Do not save the frame pointer in the frame_pointer_needed case. It
3873 was done earlier. */
3874 if (frame_pointer_needed)
3876 offset = local_fsize;
3878 /* Saving the EH return data registers in the frame is the simplest
3879 way to get the frame unwind information emitted. We put them
3880 just before the general registers. */
3881 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3883 unsigned int i, regno;
3887 regno = EH_RETURN_DATA_REGNO (i);
3888 if (regno == INVALID_REGNUM)
3891 store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
3892 offset += UNITS_PER_WORD;
3896 for (i = 18; i >= 4; i--)
3897 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3899 store_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
3900 offset += UNITS_PER_WORD;
3903 /* Account for %r3 which is saved in a special place. */
3906 /* No frame pointer needed. */
3909 offset = local_fsize - actual_fsize;
3911 /* Saving the EH return data registers in the frame is the simplest
3912 way to get the frame unwind information emitted. */
3913 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3915 unsigned int i, regno;
3919 regno = EH_RETURN_DATA_REGNO (i);
3920 if (regno == INVALID_REGNUM)
3923 /* If merge_sp_adjust_with_store is nonzero, then we can
3924 optimize the first save. */
3925 if (merge_sp_adjust_with_store)
3927 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3928 merge_sp_adjust_with_store = 0;
3931 store_reg (regno, offset, STACK_POINTER_REGNUM);
3932 offset += UNITS_PER_WORD;
3936 for (i = 18; i >= 3; i--)
3937 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3939 /* If merge_sp_adjust_with_store is nonzero, then we can
3940 optimize the first GR save. */
3941 if (merge_sp_adjust_with_store)
3943 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3944 merge_sp_adjust_with_store = 0;
3947 store_reg (i, offset, STACK_POINTER_REGNUM);
3948 offset += UNITS_PER_WORD;
3952 /* If we wanted to merge the SP adjustment with a GR save, but we never
3953 did any GR saves, then just emit the adjustment here. */
3954 if (merge_sp_adjust_with_store)
3955 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3959 /* The hppa calling conventions say that %r19, the pic offset
3960 register, is saved at sp - 32 (in this function's frame)
3961 when generating PIC code. FIXME: What is the correct thing
3962 to do for functions which make no calls and allocate no
3963 frame? Do we need to allocate a frame, or can we just omit
3964 the save? For now we'll just omit the save.
3966 We don't want a note on this insn as the frame marker can
3967 move if there is a dynamic stack allocation. */
3968 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3970 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3972 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3976 /* Align pointer properly (doubleword boundary). */
3977 offset = (offset + 7) & ~7;
3979 /* Floating point register store. */
3984 /* First get the frame or stack pointer to the start of the FP register
3986 if (frame_pointer_needed)
3988 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
3989 base = hard_frame_pointer_rtx;
3993 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3994 base = stack_pointer_rtx;
3997 /* Now actually save the FP registers. */
3998 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4000 if (df_regs_ever_live_p (i)
4001 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4003 rtx addr, insn, reg;
4004 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4005 reg = gen_rtx_REG (DFmode, i);
4006 insn = emit_move_insn (addr, reg);
4009 RTX_FRAME_RELATED_P (insn) = 1;
4012 rtx mem = gen_rtx_MEM (DFmode,
4013 plus_constant (base, offset));
4014 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4015 gen_rtx_SET (VOIDmode, mem, reg));
4019 rtx meml = gen_rtx_MEM (SFmode,
4020 plus_constant (base, offset));
4021 rtx memr = gen_rtx_MEM (SFmode,
4022 plus_constant (base, offset + 4));
4023 rtx regl = gen_rtx_REG (SFmode, i);
4024 rtx regr = gen_rtx_REG (SFmode, i + 1);
4025 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4026 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4029 RTX_FRAME_RELATED_P (setl) = 1;
4030 RTX_FRAME_RELATED_P (setr) = 1;
4031 vec = gen_rtvec (2, setl, setr);
4032 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4033 gen_rtx_SEQUENCE (VOIDmode, vec));
4036 offset += GET_MODE_SIZE (DFmode);
4043 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4044 Handle case where DISP > 8k by using the add_high_const patterns. */
4047 load_reg (int reg, HOST_WIDE_INT disp, int base)
4049 rtx dest = gen_rtx_REG (word_mode, reg);
4050 rtx basereg = gen_rtx_REG (Pmode, base);
4053 if (VAL_14_BITS_P (disp))
4054 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4055 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4057 rtx delta = GEN_INT (disp);
4058 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4060 emit_move_insn (tmpreg, delta);
4061 if (TARGET_DISABLE_INDEXING)
4063 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4064 src = gen_rtx_MEM (word_mode, tmpreg);
4067 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4071 rtx delta = GEN_INT (disp);
4072 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4073 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4075 emit_move_insn (tmpreg, high);
4076 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4079 emit_move_insn (dest, src);
4082 /* Update the total code bytes output to the text section. */
4085 update_total_code_bytes (unsigned int nbytes)
4087 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4088 && !IN_NAMED_SECTION_P (cfun->decl))
4090 unsigned int old_total = total_code_bytes;
4092 total_code_bytes += nbytes;
4094 /* Be prepared to handle overflows. */
4095 if (old_total > total_code_bytes)
4096 total_code_bytes = UINT_MAX;
4100 /* This function generates the assembly code for function exit.
4101 Args are as for output_function_prologue ().
4103 The function epilogue should not depend on the current stack
4104 pointer! It should use the frame pointer only. This is mandatory
4105 because of alloca; we also take advantage of it to omit stack
4106 adjustments before returning. */
4109 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4111 rtx insn = get_last_insn ();
4115 /* pa_expand_epilogue does the dirty work now. We just need
4116 to output the assembler directives which denote the end
4119 To make debuggers happy, emit a nop if the epilogue was completely
4120 eliminated due to a volatile call as the last insn in the
4121 current function. That way the return address (in %r2) will
4122 always point to a valid instruction in the current function. */
4124 /* Get the last real insn. */
4125 if (GET_CODE (insn) == NOTE)
4126 insn = prev_real_insn (insn);
4128 /* If it is a sequence, then look inside. */
4129 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4130 insn = XVECEXP (PATTERN (insn), 0, 0);
4132 /* If insn is a CALL_INSN, then it must be a call to a volatile
4133 function (otherwise there would be epilogue insns). */
4134 if (insn && GET_CODE (insn) == CALL_INSN)
4136 fputs ("\tnop\n", file);
4140 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4142 if (TARGET_SOM && TARGET_GAS)
4144 /* We done with this subspace except possibly for some additional
4145 debug information. Forget that we are in this subspace to ensure
4146 that the next function is output in its own subspace. */
4148 cfun->machine->in_nsubspa = 2;
4151 if (INSN_ADDRESSES_SET_P ())
4153 insn = get_last_nonnote_insn ();
4154 last_address += INSN_ADDRESSES (INSN_UID (insn));
4156 last_address += insn_default_length (insn);
4157 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4158 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4161 last_address = UINT_MAX;
4163 /* Finally, update the total number of code bytes output so far. */
4164 update_total_code_bytes (last_address);
4168 pa_expand_epilogue (void)
4171 HOST_WIDE_INT offset;
4172 HOST_WIDE_INT ret_off = 0;
4174 int merge_sp_adjust_with_load = 0;
4176 /* We will use this often. */
4177 tmpreg = gen_rtx_REG (word_mode, 1);
4179 /* Try to restore RP early to avoid load/use interlocks when
4180 RP gets used in the return (bv) instruction. This appears to still
4181 be necessary even when we schedule the prologue and epilogue. */
4184 ret_off = TARGET_64BIT ? -16 : -20;
4185 if (frame_pointer_needed)
4187 load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM);
4192 /* No frame pointer, and stack is smaller than 8k. */
4193 if (VAL_14_BITS_P (ret_off - actual_fsize))
4195 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4201 /* General register restores. */
4202 if (frame_pointer_needed)
4204 offset = local_fsize;
4206 /* If the current function calls __builtin_eh_return, then we need
4207 to restore the saved EH data registers. */
4208 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4210 unsigned int i, regno;
4214 regno = EH_RETURN_DATA_REGNO (i);
4215 if (regno == INVALID_REGNUM)
4218 load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
4219 offset += UNITS_PER_WORD;
4223 for (i = 18; i >= 4; i--)
4224 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4226 load_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
4227 offset += UNITS_PER_WORD;
4232 offset = local_fsize - actual_fsize;
4234 /* If the current function calls __builtin_eh_return, then we need
4235 to restore the saved EH data registers. */
4236 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4238 unsigned int i, regno;
4242 regno = EH_RETURN_DATA_REGNO (i);
4243 if (regno == INVALID_REGNUM)
4246 /* Only for the first load.
4247 merge_sp_adjust_with_load holds the register load
4248 with which we will merge the sp adjustment. */
4249 if (merge_sp_adjust_with_load == 0
4251 && VAL_14_BITS_P (-actual_fsize))
4252 merge_sp_adjust_with_load = regno;
4254 load_reg (regno, offset, STACK_POINTER_REGNUM);
4255 offset += UNITS_PER_WORD;
4259 for (i = 18; i >= 3; i--)
4261 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4263 /* Only for the first load.
4264 merge_sp_adjust_with_load holds the register load
4265 with which we will merge the sp adjustment. */
4266 if (merge_sp_adjust_with_load == 0
4268 && VAL_14_BITS_P (-actual_fsize))
4269 merge_sp_adjust_with_load = i;
4271 load_reg (i, offset, STACK_POINTER_REGNUM);
4272 offset += UNITS_PER_WORD;
4277 /* Align pointer properly (doubleword boundary). */
4278 offset = (offset + 7) & ~7;
4280 /* FP register restores. */
4283 /* Adjust the register to index off of. */
4284 if (frame_pointer_needed)
4285 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4287 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4289 /* Actually do the restores now. */
4290 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4291 if (df_regs_ever_live_p (i)
4292 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4294 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4295 rtx dest = gen_rtx_REG (DFmode, i);
4296 emit_move_insn (dest, src);
4300 /* Emit a blockage insn here to keep these insns from being moved to
4301 an earlier spot in the epilogue, or into the main instruction stream.
4303 This is necessary as we must not cut the stack back before all the
4304 restores are finished. */
4305 emit_insn (gen_blockage ());
4307 /* Reset stack pointer (and possibly frame pointer). The stack
4308 pointer is initially set to fp + 64 to avoid a race condition. */
4309 if (frame_pointer_needed)
4311 rtx delta = GEN_INT (-64);
4313 set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0);
4314 emit_insn (gen_pre_load (hard_frame_pointer_rtx,
4315 stack_pointer_rtx, delta));
4317 /* If we were deferring a callee register restore, do it now. */
4318 else if (merge_sp_adjust_with_load)
4320 rtx delta = GEN_INT (-actual_fsize);
4321 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4323 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4325 else if (actual_fsize != 0)
4326 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4329 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4330 frame greater than 8k), do so now. */
4332 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4334 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4336 rtx sa = EH_RETURN_STACKADJ_RTX;
4338 emit_insn (gen_blockage ());
4339 emit_insn (TARGET_64BIT
4340 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4341 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4346 pa_can_use_return_insn (void)
4348 if (!reload_completed)
4351 if (frame_pointer_needed)
4354 if (df_regs_ever_live_p (2))
4360 return pa_compute_frame_size (get_frame_size (), 0) == 0;
4364 hppa_pic_save_rtx (void)
4366 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4369 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4370 #define NO_DEFERRED_PROFILE_COUNTERS 0
4374 /* Vector of funcdef numbers. */
4375 static VEC(int,heap) *funcdef_nos;
4377 /* Output deferred profile counters. */
4379 output_deferred_profile_counters (void)
4384 if (VEC_empty (int, funcdef_nos))
4387 switch_to_section (data_section);
4388 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4389 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4391 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4393 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4394 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4397 VEC_free (int, heap, funcdef_nos);
4401 hppa_profile_hook (int label_no)
4403 /* We use SImode for the address of the function in both 32 and
4404 64-bit code to avoid having to provide DImode versions of the
4405 lcla2 and load_offset_label_address insn patterns. */
4406 rtx reg = gen_reg_rtx (SImode);
4407 rtx label_rtx = gen_label_rtx ();
4408 rtx begin_label_rtx, call_insn;
4409 char begin_label_name[16];
4411 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4413 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4416 emit_move_insn (arg_pointer_rtx,
4417 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4420 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4422 /* The address of the function is loaded into %r25 with an instruction-
4423 relative sequence that avoids the use of relocations. The sequence
4424 is split so that the load_offset_label_address instruction can
4425 occupy the delay slot of the call to _mcount. */
4427 emit_insn (gen_lcla2 (reg, label_rtx));
4429 emit_insn (gen_lcla1 (reg, label_rtx));
4431 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4432 reg, begin_label_rtx, label_rtx));
4434 #if !NO_DEFERRED_PROFILE_COUNTERS
4436 rtx count_label_rtx, addr, r24;
4437 char count_label_name[16];
4439 VEC_safe_push (int, heap, funcdef_nos, label_no);
4440 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4441 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4443 addr = force_reg (Pmode, count_label_rtx);
4444 r24 = gen_rtx_REG (Pmode, 24);
4445 emit_move_insn (r24, addr);
4448 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4449 gen_rtx_SYMBOL_REF (Pmode,
4451 GEN_INT (TARGET_64BIT ? 24 : 12)));
4453 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4458 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4459 gen_rtx_SYMBOL_REF (Pmode,
4461 GEN_INT (TARGET_64BIT ? 16 : 8)));
4465 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4466 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4468 /* Indicate the _mcount call cannot throw, nor will it execute a
4470 make_reg_eh_region_note_nothrow_nononlocal (call_insn);
4473 /* Fetch the return address for the frame COUNT steps up from
4474 the current frame, after the prologue. FRAMEADDR is the
4475 frame pointer of the COUNT frame.
4477 We want to ignore any export stub remnants here. To handle this,
4478 we examine the code at the return address, and if it is an export
4479 stub, we return a memory rtx for the stub return address stored
4482 The value returned is used in two different ways:
4484 1. To find a function's caller.
4486 2. To change the return address for a function.
4488 This function handles most instances of case 1; however, it will
4489 fail if there are two levels of stubs to execute on the return
4490 path. The only way I believe that can happen is if the return value
4491 needs a parameter relocation, which never happens for C code.
4493 This function handles most instances of case 2; however, it will
4494 fail if we did not originally have stub code on the return path
4495 but will need stub code on the new return path. This can happen if
4496 the caller & callee are both in the main program, but the new
4497 return location is in a shared library. */
4500 pa_return_addr_rtx (int count, rtx frameaddr)
4507 /* The instruction stream at the return address of a PA1.X export stub is:
4509 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4510 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4511 0x00011820 | stub+16: mtsp r1,sr0
4512 0xe0400002 | stub+20: be,n 0(sr0,rp)
4514 0xe0400002 must be specified as -532676606 so that it won't be
4515 rejected as an invalid immediate operand on 64-bit hosts.
4517 The instruction stream at the return address of a PA2.0 export stub is:
4519 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4520 0xe840d002 | stub+12: bve,n (rp)
4523 HOST_WIDE_INT insns[4];
4529 rp = get_hard_reg_initial_val (Pmode, 2);
4531 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4534 /* If there is no export stub then just use the value saved from
4535 the return pointer register. */
4537 saved_rp = gen_reg_rtx (Pmode);
4538 emit_move_insn (saved_rp, rp);
4540 /* Get pointer to the instruction stream. We have to mask out the
4541 privilege level from the two low order bits of the return address
4542 pointer here so that ins will point to the start of the first
4543 instruction that would have been executed if we returned. */
4544 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4545 label = gen_label_rtx ();
4549 insns[0] = 0x4bc23fd1;
4550 insns[1] = -398405630;
4555 insns[0] = 0x4bc23fd1;
4556 insns[1] = 0x004010a1;
4557 insns[2] = 0x00011820;
4558 insns[3] = -532676606;
4562 /* Check the instruction stream at the normal return address for the
4563 export stub. If it is an export stub, than our return address is
4564 really in -24[frameaddr]. */
4566 for (i = 0; i < len; i++)
4568 rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4));
4569 rtx op1 = GEN_INT (insns[i]);
4570 emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label);
4573 /* Here we know that our return address points to an export
4574 stub. We don't want to return the address of the export stub,
4575 but rather the return address of the export stub. That return
4576 address is stored at -24[frameaddr]. */
4578 emit_move_insn (saved_rp,
4580 memory_address (Pmode,
4581 plus_constant (frameaddr,
4590 pa_emit_bcond_fp (rtx operands[])
4592 enum rtx_code code = GET_CODE (operands[0]);
4593 rtx operand0 = operands[1];
4594 rtx operand1 = operands[2];
4595 rtx label = operands[3];
4597 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4598 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)));
4600 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4601 gen_rtx_IF_THEN_ELSE (VOIDmode,
4604 gen_rtx_REG (CCFPmode, 0),
4606 gen_rtx_LABEL_REF (VOIDmode, label),
4611 /* Adjust the cost of a scheduling dependency. Return the new cost of
4612 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4615 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4617 enum attr_type attr_type;
4619 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4620 true dependencies as they are described with bypasses now. */
4621 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4624 if (! recog_memoized (insn))
4627 attr_type = get_attr_type (insn);
4629 switch (REG_NOTE_KIND (link))
4632 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4635 if (attr_type == TYPE_FPLOAD)
4637 rtx pat = PATTERN (insn);
4638 rtx dep_pat = PATTERN (dep_insn);
4639 if (GET_CODE (pat) == PARALLEL)
4641 /* This happens for the fldXs,mb patterns. */
4642 pat = XVECEXP (pat, 0, 0);
4644 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4645 /* If this happens, we have to extend this to schedule
4646 optimally. Return 0 for now. */
4649 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4651 if (! recog_memoized (dep_insn))
4653 switch (get_attr_type (dep_insn))
4660 case TYPE_FPSQRTSGL:
4661 case TYPE_FPSQRTDBL:
4662 /* A fpload can't be issued until one cycle before a
4663 preceding arithmetic operation has finished if
4664 the target of the fpload is any of the sources
4665 (or destination) of the arithmetic operation. */
4666 return insn_default_latency (dep_insn) - 1;
4673 else if (attr_type == TYPE_FPALU)
4675 rtx pat = PATTERN (insn);
4676 rtx dep_pat = PATTERN (dep_insn);
4677 if (GET_CODE (pat) == PARALLEL)
4679 /* This happens for the fldXs,mb patterns. */
4680 pat = XVECEXP (pat, 0, 0);
4682 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4683 /* If this happens, we have to extend this to schedule
4684 optimally. Return 0 for now. */
4687 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4689 if (! recog_memoized (dep_insn))
4691 switch (get_attr_type (dep_insn))
4695 case TYPE_FPSQRTSGL:
4696 case TYPE_FPSQRTDBL:
4697 /* An ALU flop can't be issued until two cycles before a
4698 preceding divide or sqrt operation has finished if
4699 the target of the ALU flop is any of the sources
4700 (or destination) of the divide or sqrt operation. */
4701 return insn_default_latency (dep_insn) - 2;
4709 /* For other anti dependencies, the cost is 0. */
4712 case REG_DEP_OUTPUT:
4713 /* Output dependency; DEP_INSN writes a register that INSN writes some
4715 if (attr_type == TYPE_FPLOAD)
4717 rtx pat = PATTERN (insn);
4718 rtx dep_pat = PATTERN (dep_insn);
4719 if (GET_CODE (pat) == PARALLEL)
4721 /* This happens for the fldXs,mb patterns. */
4722 pat = XVECEXP (pat, 0, 0);
4724 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4725 /* If this happens, we have to extend this to schedule
4726 optimally. Return 0 for now. */
4729 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4731 if (! recog_memoized (dep_insn))
4733 switch (get_attr_type (dep_insn))
4740 case TYPE_FPSQRTSGL:
4741 case TYPE_FPSQRTDBL:
4742 /* A fpload can't be issued until one cycle before a
4743 preceding arithmetic operation has finished if
4744 the target of the fpload is the destination of the
4745 arithmetic operation.
4747 Exception: For PA7100LC, PA7200 and PA7300, the cost
4748 is 3 cycles, unless they bundle together. We also
4749 pay the penalty if the second insn is a fpload. */
4750 return insn_default_latency (dep_insn) - 1;
4757 else if (attr_type == TYPE_FPALU)
4759 rtx pat = PATTERN (insn);
4760 rtx dep_pat = PATTERN (dep_insn);
4761 if (GET_CODE (pat) == PARALLEL)
4763 /* This happens for the fldXs,mb patterns. */
4764 pat = XVECEXP (pat, 0, 0);
4766 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4767 /* If this happens, we have to extend this to schedule
4768 optimally. Return 0 for now. */
4771 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4773 if (! recog_memoized (dep_insn))
4775 switch (get_attr_type (dep_insn))
4779 case TYPE_FPSQRTSGL:
4780 case TYPE_FPSQRTDBL:
4781 /* An ALU flop can't be issued until two cycles before a
4782 preceding divide or sqrt operation has finished if
4783 the target of the ALU flop is also the target of
4784 the divide or sqrt operation. */
4785 return insn_default_latency (dep_insn) - 2;
4793 /* For other output dependencies, the cost is 0. */
4801 /* Adjust scheduling priorities. We use this to try and keep addil
4802 and the next use of %r1 close together. */
4804 pa_adjust_priority (rtx insn, int priority)
4806 rtx set = single_set (insn);
4810 src = SET_SRC (set);
4811 dest = SET_DEST (set);
4812 if (GET_CODE (src) == LO_SUM
4813 && symbolic_operand (XEXP (src, 1), VOIDmode)
4814 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4817 else if (GET_CODE (src) == MEM
4818 && GET_CODE (XEXP (src, 0)) == LO_SUM
4819 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4820 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4823 else if (GET_CODE (dest) == MEM
4824 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4825 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4826 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4832 /* The 700 can only issue a single insn at a time.
4833 The 7XXX processors can issue two insns at a time.
4834 The 8000 can issue 4 insns at a time. */
4836 pa_issue_rate (void)
4840 case PROCESSOR_700: return 1;
4841 case PROCESSOR_7100: return 2;
4842 case PROCESSOR_7100LC: return 2;
4843 case PROCESSOR_7200: return 2;
4844 case PROCESSOR_7300: return 2;
4845 case PROCESSOR_8000: return 4;
4854 /* Return any length adjustment needed by INSN which already has its length
4855 computed as LENGTH. Return zero if no adjustment is necessary.
4857 For the PA: function calls, millicode calls, and backwards short
4858 conditional branches with unfilled delay slots need an adjustment by +1
4859 (to account for the NOP which will be inserted into the instruction stream).
4861 Also compute the length of an inline block move here as it is too
4862 complicated to express as a length attribute in pa.md. */
4864 pa_adjust_insn_length (rtx insn, int length)
4866 rtx pat = PATTERN (insn);
4868 /* Jumps inside switch tables which have unfilled delay slots need
4870 if (GET_CODE (insn) == JUMP_INSN
4871 && GET_CODE (pat) == PARALLEL
4872 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4874 /* Millicode insn with an unfilled delay slot. */
4875 else if (GET_CODE (insn) == INSN
4876 && GET_CODE (pat) != SEQUENCE
4877 && GET_CODE (pat) != USE
4878 && GET_CODE (pat) != CLOBBER
4879 && get_attr_type (insn) == TYPE_MILLI)
4881 /* Block move pattern. */
4882 else if (GET_CODE (insn) == INSN
4883 && GET_CODE (pat) == PARALLEL
4884 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4885 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4886 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4887 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4888 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4889 return compute_movmem_length (insn) - 4;
4890 /* Block clear pattern. */
4891 else if (GET_CODE (insn) == INSN
4892 && GET_CODE (pat) == PARALLEL
4893 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4894 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4895 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4896 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4897 return compute_clrmem_length (insn) - 4;
4898 /* Conditional branch with an unfilled delay slot. */
4899 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4901 /* Adjust a short backwards conditional with an unfilled delay slot. */
4902 if (GET_CODE (pat) == SET
4904 && JUMP_LABEL (insn) != NULL_RTX
4905 && ! forward_branch_p (insn))
4907 else if (GET_CODE (pat) == PARALLEL
4908 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4911 /* Adjust dbra insn with short backwards conditional branch with
4912 unfilled delay slot -- only for case where counter is in a
4913 general register register. */
4914 else if (GET_CODE (pat) == PARALLEL
4915 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4916 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4917 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4919 && ! forward_branch_p (insn))
4927 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
4930 pa_print_operand_punct_valid_p (unsigned char code)
4941 /* Print operand X (an rtx) in assembler syntax to file FILE.
4942 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4943 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4946 pa_print_operand (FILE *file, rtx x, int code)
4951 /* Output a 'nop' if there's nothing for the delay slot. */
4952 if (dbr_sequence_length () == 0)
4953 fputs ("\n\tnop", file);
4956 /* Output a nullification completer if there's nothing for the */
4957 /* delay slot or nullification is requested. */
4958 if (dbr_sequence_length () == 0 ||
4960 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4964 /* Print out the second register name of a register pair.
4965 I.e., R (6) => 7. */
4966 fputs (reg_names[REGNO (x) + 1], file);
4969 /* A register or zero. */
4971 || (x == CONST0_RTX (DFmode))
4972 || (x == CONST0_RTX (SFmode)))
4974 fputs ("%r0", file);
4980 /* A register or zero (floating point). */
4982 || (x == CONST0_RTX (DFmode))
4983 || (x == CONST0_RTX (SFmode)))
4985 fputs ("%fr0", file);
4994 xoperands[0] = XEXP (XEXP (x, 0), 0);
4995 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4996 pa_output_global_address (file, xoperands[1], 0);
4997 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5001 case 'C': /* Plain (C)ondition */
5003 switch (GET_CODE (x))
5006 fputs ("=", file); break;
5008 fputs ("<>", file); break;
5010 fputs (">", file); break;
5012 fputs (">=", file); break;
5014 fputs (">>=", file); break;
5016 fputs (">>", file); break;
5018 fputs ("<", file); break;
5020 fputs ("<=", file); break;
5022 fputs ("<<=", file); break;
5024 fputs ("<<", file); break;
5029 case 'N': /* Condition, (N)egated */
5030 switch (GET_CODE (x))
5033 fputs ("<>", file); break;
5035 fputs ("=", file); break;
5037 fputs ("<=", file); break;
5039 fputs ("<", file); break;
5041 fputs ("<<", file); break;
5043 fputs ("<<=", file); break;
5045 fputs (">=", file); break;
5047 fputs (">", file); break;
5049 fputs (">>", file); break;
5051 fputs (">>=", file); break;
5056 /* For floating point comparisons. Note that the output
5057 predicates are the complement of the desired mode. The
5058 conditions for GT, GE, LT, LE and LTGT cause an invalid
5059 operation exception if the result is unordered and this
5060 exception is enabled in the floating-point status register. */
5062 switch (GET_CODE (x))
5065 fputs ("!=", file); break;
5067 fputs ("=", file); break;
5069 fputs ("!>", file); break;
5071 fputs ("!>=", file); break;
5073 fputs ("!<", file); break;
5075 fputs ("!<=", file); break;
5077 fputs ("!<>", file); break;
5079 fputs ("!?<=", file); break;
5081 fputs ("!?<", file); break;
5083 fputs ("!?>=", file); break;
5085 fputs ("!?>", file); break;
5087 fputs ("!?=", file); break;
5089 fputs ("!?", file); break;
5091 fputs ("?", file); break;
5096 case 'S': /* Condition, operands are (S)wapped. */
5097 switch (GET_CODE (x))
5100 fputs ("=", file); break;
5102 fputs ("<>", file); break;
5104 fputs ("<", file); break;
5106 fputs ("<=", file); break;
5108 fputs ("<<=", file); break;
5110 fputs ("<<", file); break;
5112 fputs (">", file); break;
5114 fputs (">=", file); break;
5116 fputs (">>=", file); break;
5118 fputs (">>", file); break;
5123 case 'B': /* Condition, (B)oth swapped and negate. */
5124 switch (GET_CODE (x))
5127 fputs ("<>", file); break;
5129 fputs ("=", file); break;
5131 fputs (">=", file); break;
5133 fputs (">", file); break;
5135 fputs (">>", file); break;
5137 fputs (">>=", file); break;
5139 fputs ("<=", file); break;
5141 fputs ("<", file); break;
5143 fputs ("<<", file); break;
5145 fputs ("<<=", file); break;
5151 gcc_assert (GET_CODE (x) == CONST_INT);
5152 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5155 gcc_assert (GET_CODE (x) == CONST_INT);
5156 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5159 gcc_assert (GET_CODE (x) == CONST_INT);
5160 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5163 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5164 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5167 gcc_assert (GET_CODE (x) == CONST_INT);
5168 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5171 gcc_assert (GET_CODE (x) == CONST_INT);
5172 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5175 if (GET_CODE (x) == CONST_INT)
5180 switch (GET_CODE (XEXP (x, 0)))
5184 if (ASSEMBLER_DIALECT == 0)
5185 fputs ("s,mb", file);
5187 fputs (",mb", file);
5191 if (ASSEMBLER_DIALECT == 0)
5192 fputs ("s,ma", file);
5194 fputs (",ma", file);
5197 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5198 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5200 if (ASSEMBLER_DIALECT == 0)
5203 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5204 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5206 if (ASSEMBLER_DIALECT == 0)
5207 fputs ("x,s", file);
5211 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5215 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5221 pa_output_global_address (file, x, 0);
5224 pa_output_global_address (file, x, 1);
5226 case 0: /* Don't do anything special */
5231 compute_zdepwi_operands (INTVAL (x), op);
5232 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5238 compute_zdepdi_operands (INTVAL (x), op);
5239 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5243 /* We can get here from a .vtable_inherit due to our
5244 CONSTANT_ADDRESS_P rejecting perfectly good constant
5250 if (GET_CODE (x) == REG)
5252 fputs (reg_names [REGNO (x)], file);
5253 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5259 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5260 && (REGNO (x) & 1) == 0)
5263 else if (GET_CODE (x) == MEM)
5265 int size = GET_MODE_SIZE (GET_MODE (x));
5266 rtx base = NULL_RTX;
5267 switch (GET_CODE (XEXP (x, 0)))
5271 base = XEXP (XEXP (x, 0), 0);
5272 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5276 base = XEXP (XEXP (x, 0), 0);
5277 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5280 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5281 fprintf (file, "%s(%s)",
5282 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5283 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5284 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5285 fprintf (file, "%s(%s)",
5286 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5287 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5288 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5289 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5291 /* Because the REG_POINTER flag can get lost during reload,
5292 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5293 index and base registers in the combined move patterns. */
5294 rtx base = XEXP (XEXP (x, 0), 1);
5295 rtx index = XEXP (XEXP (x, 0), 0);
5297 fprintf (file, "%s(%s)",
5298 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5301 output_address (XEXP (x, 0));
5304 output_address (XEXP (x, 0));
5309 output_addr_const (file, x);
5312 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5315 pa_output_global_address (FILE *file, rtx x, int round_constant)
5318 /* Imagine (high (const (plus ...))). */
5319 if (GET_CODE (x) == HIGH)
5322 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5323 output_addr_const (file, x);
5324 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5326 output_addr_const (file, x);
5327 fputs ("-$global$", file);
5329 else if (GET_CODE (x) == CONST)
5331 const char *sep = "";
5332 int offset = 0; /* assembler wants -$global$ at end */
5333 rtx base = NULL_RTX;
5335 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5338 base = XEXP (XEXP (x, 0), 0);
5339 output_addr_const (file, base);
5342 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5348 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5351 base = XEXP (XEXP (x, 0), 1);
5352 output_addr_const (file, base);
5355 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5361 /* How bogus. The compiler is apparently responsible for
5362 rounding the constant if it uses an LR field selector.
5364 The linker and/or assembler seem a better place since
5365 they have to do this kind of thing already.
5367 If we fail to do this, HP's optimizing linker may eliminate
5368 an addil, but not update the ldw/stw/ldo instruction that
5369 uses the result of the addil. */
5371 offset = ((offset + 0x1000) & ~0x1fff);
5373 switch (GET_CODE (XEXP (x, 0)))
5386 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5394 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5395 fputs ("-$global$", file);
5397 fprintf (file, "%s%d", sep, offset);
5400 output_addr_const (file, x);
5403 /* Output boilerplate text to appear at the beginning of the file.
5404 There are several possible versions. */
5405 #define aputs(x) fputs(x, asm_out_file)
5407 pa_file_start_level (void)
5410 aputs ("\t.LEVEL 2.0w\n");
5411 else if (TARGET_PA_20)
5412 aputs ("\t.LEVEL 2.0\n");
5413 else if (TARGET_PA_11)
5414 aputs ("\t.LEVEL 1.1\n");
5416 aputs ("\t.LEVEL 1.0\n");
5420 pa_file_start_space (int sortspace)
5422 aputs ("\t.SPACE $PRIVATE$");
5425 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31");
5427 aputs ("\n\t.SUBSPA $TM_CLONE_TABLE$,QUAD=1,ALIGN=8,ACCESS=31");
5428 aputs ("\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5429 "\n\t.SPACE $TEXT$");
5432 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5433 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5437 pa_file_start_file (int want_version)
5439 if (write_symbols != NO_DEBUG)
5441 output_file_directive (asm_out_file, main_input_filename);
5443 aputs ("\t.version\t\"01.01\"\n");
5448 pa_file_start_mcount (const char *aswhat)
5451 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5455 pa_elf_file_start (void)
5457 pa_file_start_level ();
5458 pa_file_start_mcount ("ENTRY");
5459 pa_file_start_file (0);
5463 pa_som_file_start (void)
5465 pa_file_start_level ();
5466 pa_file_start_space (0);
5467 aputs ("\t.IMPORT $global$,DATA\n"
5468 "\t.IMPORT $$dyncall,MILLICODE\n");
5469 pa_file_start_mcount ("CODE");
5470 pa_file_start_file (0);
5474 pa_linux_file_start (void)
5476 pa_file_start_file (1);
5477 pa_file_start_level ();
5478 pa_file_start_mcount ("CODE");
5482 pa_hpux64_gas_file_start (void)
5484 pa_file_start_level ();
5485 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5487 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5489 pa_file_start_file (1);
5493 pa_hpux64_hpas_file_start (void)
5495 pa_file_start_level ();
5496 pa_file_start_space (1);
5497 pa_file_start_mcount ("CODE");
5498 pa_file_start_file (0);
5502 /* Search the deferred plabel list for SYMBOL and return its internal
5503 label. If an entry for SYMBOL is not found, a new entry is created. */
5506 pa_get_deferred_plabel (rtx symbol)
5508 const char *fname = XSTR (symbol, 0);
5511 /* See if we have already put this function on the list of deferred
5512 plabels. This list is generally small, so a liner search is not
5513 too ugly. If it proves too slow replace it with something faster. */
5514 for (i = 0; i < n_deferred_plabels; i++)
5515 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5518 /* If the deferred plabel list is empty, or this entry was not found
5519 on the list, create a new entry on the list. */
5520 if (deferred_plabels == NULL || i == n_deferred_plabels)
5524 if (deferred_plabels == 0)
5525 deferred_plabels = ggc_alloc_deferred_plabel ();
5527 deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel,
5529 n_deferred_plabels + 1);
5531 i = n_deferred_plabels++;
5532 deferred_plabels[i].internal_label = gen_label_rtx ();
5533 deferred_plabels[i].symbol = symbol;
5535 /* Gross. We have just implicitly taken the address of this
5536 function. Mark it in the same manner as assemble_name. */
5537 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5539 mark_referenced (id);
5542 return deferred_plabels[i].internal_label;
5546 output_deferred_plabels (void)
5550 /* If we have some deferred plabels, then we need to switch into the
5551 data or readonly data section, and align it to a 4 byte boundary
5552 before outputting the deferred plabels. */
5553 if (n_deferred_plabels)
5555 switch_to_section (flag_pic ? data_section : readonly_data_section);
5556 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5559 /* Now output the deferred plabels. */
5560 for (i = 0; i < n_deferred_plabels; i++)
5562 targetm.asm_out.internal_label (asm_out_file, "L",
5563 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5564 assemble_integer (deferred_plabels[i].symbol,
5565 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5569 /* Initialize optabs to point to emulation routines. */
5572 pa_init_libfuncs (void)
5574 if (HPUX_LONG_DOUBLE_LIBRARY)
5576 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5577 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5578 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5579 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5580 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5581 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5582 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5583 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5584 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5586 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5587 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5588 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5589 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5590 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5591 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5592 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5594 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5595 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5596 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5597 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5599 set_conv_libfunc (sfix_optab, SImode, TFmode,
5600 TARGET_64BIT ? "__U_Qfcnvfxt_quad_to_sgl"
5601 : "_U_Qfcnvfxt_quad_to_sgl");
5602 set_conv_libfunc (sfix_optab, DImode, TFmode,
5603 "_U_Qfcnvfxt_quad_to_dbl");
5604 set_conv_libfunc (ufix_optab, SImode, TFmode,
5605 "_U_Qfcnvfxt_quad_to_usgl");
5606 set_conv_libfunc (ufix_optab, DImode, TFmode,
5607 "_U_Qfcnvfxt_quad_to_udbl");
5609 set_conv_libfunc (sfloat_optab, TFmode, SImode,
5610 "_U_Qfcnvxf_sgl_to_quad");
5611 set_conv_libfunc (sfloat_optab, TFmode, DImode,
5612 "_U_Qfcnvxf_dbl_to_quad");
5613 set_conv_libfunc (ufloat_optab, TFmode, SImode,
5614 "_U_Qfcnvxf_usgl_to_quad");
5615 set_conv_libfunc (ufloat_optab, TFmode, DImode,
5616 "_U_Qfcnvxf_udbl_to_quad");
5619 if (TARGET_SYNC_LIBCALL)
5620 init_sync_libfuncs (UNITS_PER_WORD);
5623 /* HP's millicode routines mean something special to the assembler.
5624 Keep track of which ones we have used. */
5626 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5627 static void import_milli (enum millicodes);
5628 static char imported[(int) end1000];
5629 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5630 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5631 #define MILLI_START 10
5634 import_milli (enum millicodes code)
5636 char str[sizeof (import_string)];
5638 if (!imported[(int) code])
5640 imported[(int) code] = 1;
5641 strcpy (str, import_string);
5642 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5643 output_asm_insn (str, 0);
5647 /* The register constraints have put the operands and return value in
5648 the proper registers. */
5651 pa_output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5653 import_milli (mulI);
5654 return pa_output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5657 /* Emit the rtl for doing a division by a constant. */
5659 /* Do magic division millicodes exist for this value? */
5660 const int pa_magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5662 /* We'll use an array to keep track of the magic millicodes and
5663 whether or not we've used them already. [n][0] is signed, [n][1] is
5666 static int div_milli[16][2];
5669 pa_emit_hpdiv_const (rtx *operands, int unsignedp)
5671 if (GET_CODE (operands[2]) == CONST_INT
5672 && INTVAL (operands[2]) > 0
5673 && INTVAL (operands[2]) < 16
5674 && pa_magic_milli[INTVAL (operands[2])])
5676 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5678 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5682 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5683 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5685 gen_rtx_REG (SImode, 26),
5687 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5688 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5689 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5690 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5691 gen_rtx_CLOBBER (VOIDmode, ret))));
5692 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5699 pa_output_div_insn (rtx *operands, int unsignedp, rtx insn)
5703 /* If the divisor is a constant, try to use one of the special
5705 if (GET_CODE (operands[0]) == CONST_INT)
5707 static char buf[100];
5708 divisor = INTVAL (operands[0]);
5709 if (!div_milli[divisor][unsignedp])
5711 div_milli[divisor][unsignedp] = 1;
5713 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5715 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5719 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5720 INTVAL (operands[0]));
5721 return pa_output_millicode_call (insn,
5722 gen_rtx_SYMBOL_REF (SImode, buf));
5726 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5727 INTVAL (operands[0]));
5728 return pa_output_millicode_call (insn,
5729 gen_rtx_SYMBOL_REF (SImode, buf));
5732 /* Divisor isn't a special constant. */
5737 import_milli (divU);
5738 return pa_output_millicode_call (insn,
5739 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5743 import_milli (divI);
5744 return pa_output_millicode_call (insn,
5745 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5750 /* Output a $$rem millicode to do mod. */
5753 pa_output_mod_insn (int unsignedp, rtx insn)
5757 import_milli (remU);
5758 return pa_output_millicode_call (insn,
5759 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5763 import_milli (remI);
5764 return pa_output_millicode_call (insn,
5765 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5770 pa_output_arg_descriptor (rtx call_insn)
5772 const char *arg_regs[4];
5773 enum machine_mode arg_mode;
5775 int i, output_flag = 0;
5778 /* We neither need nor want argument location descriptors for the
5779 64bit runtime environment or the ELF32 environment. */
5780 if (TARGET_64BIT || TARGET_ELF32)
5783 for (i = 0; i < 4; i++)
5786 /* Specify explicitly that no argument relocations should take place
5787 if using the portable runtime calling conventions. */
5788 if (TARGET_PORTABLE_RUNTIME)
5790 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5795 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5796 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5797 link; link = XEXP (link, 1))
5799 rtx use = XEXP (link, 0);
5801 if (! (GET_CODE (use) == USE
5802 && GET_CODE (XEXP (use, 0)) == REG
5803 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5806 arg_mode = GET_MODE (XEXP (use, 0));
5807 regno = REGNO (XEXP (use, 0));
5808 if (regno >= 23 && regno <= 26)
5810 arg_regs[26 - regno] = "GR";
5811 if (arg_mode == DImode)
5812 arg_regs[25 - regno] = "GR";
5814 else if (regno >= 32 && regno <= 39)
5816 if (arg_mode == SFmode)
5817 arg_regs[(regno - 32) / 2] = "FR";
5820 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5821 arg_regs[(regno - 34) / 2] = "FR";
5822 arg_regs[(regno - 34) / 2 + 1] = "FU";
5824 arg_regs[(regno - 34) / 2] = "FU";
5825 arg_regs[(regno - 34) / 2 + 1] = "FR";
5830 fputs ("\t.CALL ", asm_out_file);
5831 for (i = 0; i < 4; i++)
5836 fputc (',', asm_out_file);
5837 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5840 fputc ('\n', asm_out_file);
5843 /* Inform reload about cases where moving X with a mode MODE to a register in
5844 RCLASS requires an extra scratch or immediate register. Return the class
5845 needed for the immediate register. */
5848 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
5849 enum machine_mode mode, secondary_reload_info *sri)
5852 enum reg_class rclass = (enum reg_class) rclass_i;
5854 /* Handle the easy stuff first. */
5855 if (rclass == R1_REGS)
5861 if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5867 /* If we have something like (mem (mem (...)), we can safely assume the
5868 inner MEM will end up in a general register after reloading, so there's
5869 no need for a secondary reload. */
5870 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5873 /* Trying to load a constant into a FP register during PIC code
5874 generation requires %r1 as a scratch register. */
5876 && (mode == SImode || mode == DImode)
5877 && FP_REG_CLASS_P (rclass)
5878 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5880 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5881 : CODE_FOR_reload_indi_r1);
5885 /* Secondary reloads of symbolic operands require %r1 as a scratch
5886 register when we're generating PIC code and when the operand isn't
5888 if (pa_symbolic_expression_p (x))
5890 if (GET_CODE (x) == HIGH)
5893 if (flag_pic || !read_only_operand (x, VOIDmode))
5895 gcc_assert (mode == SImode || mode == DImode);
5896 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5897 : CODE_FOR_reload_indi_r1);
5902 /* Profiling showed the PA port spends about 1.3% of its compilation
5903 time in true_regnum from calls inside pa_secondary_reload_class. */
5904 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5905 regno = true_regnum (x);
5907 /* In order to allow 14-bit displacements in integer loads and stores,
5908 we need to prevent reload from generating out of range integer mode
5909 loads and stores to the floating point registers. Previously, we
5910 used to call for a secondary reload and have pa_emit_move_sequence()
5911 fix the instruction sequence. However, reload occasionally wouldn't
5912 generate the reload and we would end up with an invalid REG+D memory
5913 address. So, now we use an intermediate general register for most
5914 memory loads and stores. */
5915 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5916 && GET_MODE_CLASS (mode) == MODE_INT
5917 && FP_REG_CLASS_P (rclass))
5919 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5920 the secondary reload needed for a pseudo. It never passes a
5922 if (GET_CODE (x) == MEM)
5926 /* We don't need an intermediate for indexed and LO_SUM DLT
5927 memory addresses. When INT14_OK_STRICT is true, it might
5928 appear that we could directly allow register indirect
5929 memory addresses. However, this doesn't work because we
5930 don't support SUBREGs in floating-point register copies
5931 and reload doesn't tell us when it's going to use a SUBREG. */
5932 if (IS_INDEX_ADDR_P (x)
5933 || IS_LO_SUM_DLT_ADDR_P (x))
5936 /* Otherwise, we need an intermediate general register. */
5937 return GENERAL_REGS;
5940 /* Request a secondary reload with a general scratch register
5941 for everthing else. ??? Could symbolic operands be handled
5942 directly when generating non-pic PA 2.0 code? */
5944 ? direct_optab_handler (reload_in_optab, mode)
5945 : direct_optab_handler (reload_out_optab, mode));
5949 /* A SAR<->FP register copy requires an intermediate general register
5950 and secondary memory. We need a secondary reload with a general
5951 scratch register for spills. */
5952 if (rclass == SHIFT_REGS)
5955 if (regno >= FIRST_PSEUDO_REGISTER || regno < 0)
5958 ? direct_optab_handler (reload_in_optab, mode)
5959 : direct_optab_handler (reload_out_optab, mode));
5963 /* Handle FP copy. */
5964 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))
5965 return GENERAL_REGS;
5968 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5969 && REGNO_REG_CLASS (regno) == SHIFT_REGS
5970 && FP_REG_CLASS_P (rclass))
5971 return GENERAL_REGS;
5976 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5977 is only marked as live on entry by df-scan when it is a fixed
5978 register. It isn't a fixed register in the 64-bit runtime,
5979 so we need to mark it here. */
5982 pa_extra_live_on_entry (bitmap regs)
5985 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5988 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5989 to prevent it from being deleted. */
5992 pa_eh_return_handler_rtx (void)
5996 tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx,
5997 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5998 tmp = gen_rtx_MEM (word_mode, tmp);
6003 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6004 by invisible reference. As a GCC extension, we also pass anything
6005 with a zero or variable size by reference.
6007 The 64-bit runtime does not describe passing any types by invisible
6008 reference. The internals of GCC can't currently handle passing
6009 empty structures, and zero or variable length arrays when they are
6010 not passed entirely on the stack or by reference. Thus, as a GCC
6011 extension, we pass these types by reference. The HP compiler doesn't
6012 support these types, so hopefully there shouldn't be any compatibility
6013 issues. This may have to be revisited when HP releases a C99 compiler
6014 or updates the ABI. */
6017 pa_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED,
6018 enum machine_mode mode, const_tree type,
6019 bool named ATTRIBUTE_UNUSED)
6024 size = int_size_in_bytes (type);
6026 size = GET_MODE_SIZE (mode);
6031 return size <= 0 || size > 8;
6035 pa_function_arg_padding (enum machine_mode mode, const_tree type)
6040 && (AGGREGATE_TYPE_P (type)
6041 || TREE_CODE (type) == COMPLEX_TYPE
6042 || TREE_CODE (type) == VECTOR_TYPE)))
6044 /* Return none if justification is not required. */
6046 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6047 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6050 /* The directions set here are ignored when a BLKmode argument larger
6051 than a word is placed in a register. Different code is used for
6052 the stack and registers. This makes it difficult to have a
6053 consistent data representation for both the stack and registers.
6054 For both runtimes, the justification and padding for arguments on
6055 the stack and in registers should be identical. */
6057 /* The 64-bit runtime specifies left justification for aggregates. */
6060 /* The 32-bit runtime architecture specifies right justification.
6061 When the argument is passed on the stack, the argument is padded
6062 with garbage on the left. The HP compiler pads with zeros. */
6066 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6073 /* Do what is necessary for `va_start'. We look at the current function
6074 to determine if stdargs or varargs is used and fill in an initial
6075 va_list. A pointer to this constructor is returned. */
6078 hppa_builtin_saveregs (void)
6081 tree fntype = TREE_TYPE (current_function_decl);
6082 int argadj = ((!stdarg_p (fntype))
6083 ? UNITS_PER_WORD : 0);
6086 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
6088 offset = crtl->args.arg_offset_rtx;
6094 /* Adjust for varargs/stdarg differences. */
6096 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
6098 offset = crtl->args.arg_offset_rtx;
6100 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6101 from the incoming arg pointer and growing to larger addresses. */
6102 for (i = 26, off = -64; i >= 19; i--, off += 8)
6103 emit_move_insn (gen_rtx_MEM (word_mode,
6104 plus_constant (arg_pointer_rtx, off)),
6105 gen_rtx_REG (word_mode, i));
6107 /* The incoming args pointer points just beyond the flushback area;
6108 normally this is not a serious concern. However, when we are doing
6109 varargs/stdargs we want to make the arg pointer point to the start
6110 of the incoming argument area. */
6111 emit_move_insn (virtual_incoming_args_rtx,
6112 plus_constant (arg_pointer_rtx, -64));
6114 /* Now return a pointer to the first anonymous argument. */
6115 return copy_to_reg (expand_binop (Pmode, add_optab,
6116 virtual_incoming_args_rtx,
6117 offset, 0, 0, OPTAB_LIB_WIDEN));
6120 /* Store general registers on the stack. */
6121 dest = gen_rtx_MEM (BLKmode,
6122 plus_constant (crtl->args.internal_arg_pointer,
6124 set_mem_alias_set (dest, get_varargs_alias_set ());
6125 set_mem_align (dest, BITS_PER_WORD);
6126 move_block_from_reg (23, dest, 4);
6128 /* move_block_from_reg will emit code to store the argument registers
6129 individually as scalar stores.
6131 However, other insns may later load from the same addresses for
6132 a structure load (passing a struct to a varargs routine).
6134 The alias code assumes that such aliasing can never happen, so we
6135 have to keep memory referencing insns from moving up beyond the
6136 last argument register store. So we emit a blockage insn here. */
6137 emit_insn (gen_blockage ());
6139 return copy_to_reg (expand_binop (Pmode, add_optab,
6140 crtl->args.internal_arg_pointer,
6141 offset, 0, 0, OPTAB_LIB_WIDEN));
6145 hppa_va_start (tree valist, rtx nextarg)
6147 nextarg = expand_builtin_saveregs ();
6148 std_expand_builtin_va_start (valist, nextarg);
6152 hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6157 /* Args grow upward. We can use the generic routines. */
6158 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6160 else /* !TARGET_64BIT */
6162 tree ptr = build_pointer_type (type);
6165 unsigned int size, ofs;
6168 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6172 ptr = build_pointer_type (type);
6174 size = int_size_in_bytes (type);
6175 valist_type = TREE_TYPE (valist);
6177 /* Args grow down. Not handled by generic routines. */
6179 u = fold_convert (sizetype, size_in_bytes (type));
6180 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6181 t = fold_build_pointer_plus (valist, u);
6183 /* Align to 4 or 8 byte boundary depending on argument size. */
6185 u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4));
6186 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6187 t = fold_convert (valist_type, t);
6189 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6191 ofs = (8 - size) % 4;
6193 t = fold_build_pointer_plus_hwi (t, ofs);
6195 t = fold_convert (ptr, t);
6196 t = build_va_arg_indirect_ref (t);
6199 t = build_va_arg_indirect_ref (t);
6205 /* True if MODE is valid for the target. By "valid", we mean able to
6206 be manipulated in non-trivial ways. In particular, this means all
6207 the arithmetic is supported.
6209 Currently, TImode is not valid as the HP 64-bit runtime documentation
6210 doesn't document the alignment and calling conventions for this type.
6211 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6212 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6215 pa_scalar_mode_supported_p (enum machine_mode mode)
6217 int precision = GET_MODE_PRECISION (mode);
6219 switch (GET_MODE_CLASS (mode))
6221 case MODE_PARTIAL_INT:
6223 if (precision == CHAR_TYPE_SIZE)
6225 if (precision == SHORT_TYPE_SIZE)
6227 if (precision == INT_TYPE_SIZE)
6229 if (precision == LONG_TYPE_SIZE)
6231 if (precision == LONG_LONG_TYPE_SIZE)
6236 if (precision == FLOAT_TYPE_SIZE)
6238 if (precision == DOUBLE_TYPE_SIZE)
6240 if (precision == LONG_DOUBLE_TYPE_SIZE)
6244 case MODE_DECIMAL_FLOAT:
6252 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6253 it branches into the delay slot. Otherwise, return FALSE. */
6256 branch_to_delay_slot_p (rtx insn)
6260 if (dbr_sequence_length ())
6263 jump_insn = next_active_insn (JUMP_LABEL (insn));
6266 insn = next_active_insn (insn);
6267 if (jump_insn == insn)
6270 /* We can't rely on the length of asms. So, we return FALSE when
6271 the branch is followed by an asm. */
6273 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6274 || extract_asm_operands (PATTERN (insn)) != NULL_RTX
6275 || get_attr_length (insn) > 0)
6282 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6284 This occurs when INSN has an unfilled delay slot and is followed
6285 by an asm. Disaster can occur if the asm is empty and the jump
6286 branches into the delay slot. So, we add a nop in the delay slot
6287 when this occurs. */
6290 branch_needs_nop_p (rtx insn)
6294 if (dbr_sequence_length ())
6297 jump_insn = next_active_insn (JUMP_LABEL (insn));
6300 insn = next_active_insn (insn);
6301 if (!insn || jump_insn == insn)
6304 if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT
6305 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6306 && get_attr_length (insn) > 0)
6313 /* Return TRUE if INSN, a forward jump insn, can use nullification
6314 to skip the following instruction. This avoids an extra cycle due
6315 to a mis-predicted branch when we fall through. */
6318 use_skip_p (rtx insn)
6320 rtx jump_insn = next_active_insn (JUMP_LABEL (insn));
6324 insn = next_active_insn (insn);
6326 /* We can't rely on the length of asms, so we can't skip asms. */
6328 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6329 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6331 if (get_attr_length (insn) == 4
6332 && jump_insn == next_active_insn (insn))
6334 if (get_attr_length (insn) > 0)
6341 /* This routine handles all the normal conditional branch sequences we
6342 might need to generate. It handles compare immediate vs compare
6343 register, nullification of delay slots, varying length branches,
6344 negated branches, and all combinations of the above. It returns the
6345 output appropriate to emit the branch corresponding to all given
6349 pa_output_cbranch (rtx *operands, int negated, rtx insn)
6351 static char buf[100];
6353 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6354 int length = get_attr_length (insn);
6357 /* A conditional branch to the following instruction (e.g. the delay slot)
6358 is asking for a disaster. This can happen when not optimizing and
6359 when jump optimization fails.
6361 While it is usually safe to emit nothing, this can fail if the
6362 preceding instruction is a nullified branch with an empty delay
6363 slot and the same branch target as this branch. We could check
6364 for this but jump optimization should eliminate nop jumps. It
6365 is always safe to emit a nop. */
6366 if (branch_to_delay_slot_p (insn))
6369 /* The doubleword form of the cmpib instruction doesn't have the LEU
6370 and GTU conditions while the cmpb instruction does. Since we accept
6371 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6372 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6373 operands[2] = gen_rtx_REG (DImode, 0);
6374 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6375 operands[1] = gen_rtx_REG (DImode, 0);
6377 /* If this is a long branch with its delay slot unfilled, set `nullify'
6378 as it can nullify the delay slot and save a nop. */
6379 if (length == 8 && dbr_sequence_length () == 0)
6382 /* If this is a short forward conditional branch which did not get
6383 its delay slot filled, the delay slot can still be nullified. */
6384 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6385 nullify = forward_branch_p (insn);
6387 /* A forward branch over a single nullified insn can be done with a
6388 comclr instruction. This avoids a single cycle penalty due to
6389 mis-predicted branch if we fall through (branch not taken). */
6390 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6394 /* All short conditional branches except backwards with an unfilled
6398 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6400 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6401 if (GET_MODE (operands[1]) == DImode)
6404 strcat (buf, "%B3");
6406 strcat (buf, "%S3");
6408 strcat (buf, " %2,%r1,%%r0");
6411 if (branch_needs_nop_p (insn))
6412 strcat (buf, ",n %2,%r1,%0%#");
6414 strcat (buf, ",n %2,%r1,%0");
6417 strcat (buf, " %2,%r1,%0");
6420 /* All long conditionals. Note a short backward branch with an
6421 unfilled delay slot is treated just like a long backward branch
6422 with an unfilled delay slot. */
6424 /* Handle weird backwards branch with a filled delay slot
6425 which is nullified. */
6426 if (dbr_sequence_length () != 0
6427 && ! forward_branch_p (insn)
6430 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6431 if (GET_MODE (operands[1]) == DImode)
6434 strcat (buf, "%S3");
6436 strcat (buf, "%B3");
6437 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6439 /* Handle short backwards branch with an unfilled delay slot.
6440 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6441 taken and untaken branches. */
6442 else if (dbr_sequence_length () == 0
6443 && ! forward_branch_p (insn)
6444 && INSN_ADDRESSES_SET_P ()
6445 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6446 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6448 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6449 if (GET_MODE (operands[1]) == DImode)
6452 strcat (buf, "%B3 %2,%r1,%0%#");
6454 strcat (buf, "%S3 %2,%r1,%0%#");
6458 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6459 if (GET_MODE (operands[1]) == DImode)
6462 strcat (buf, "%S3");
6464 strcat (buf, "%B3");
6466 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6468 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6473 /* The reversed conditional branch must branch over one additional
6474 instruction if the delay slot is filled and needs to be extracted
6475 by pa_output_lbranch. If the delay slot is empty or this is a
6476 nullified forward branch, the instruction after the reversed
6477 condition branch must be nullified. */
6478 if (dbr_sequence_length () == 0
6479 || (nullify && forward_branch_p (insn)))
6483 operands[4] = GEN_INT (length);
6488 operands[4] = GEN_INT (length + 4);
6491 /* Create a reversed conditional branch which branches around
6492 the following insns. */
6493 if (GET_MODE (operands[1]) != DImode)
6499 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6502 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6508 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6511 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6520 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6523 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6529 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6532 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6536 output_asm_insn (buf, operands);
6537 return pa_output_lbranch (operands[0], insn, xdelay);
6542 /* This routine handles output of long unconditional branches that
6543 exceed the maximum range of a simple branch instruction. Since
6544 we don't have a register available for the branch, we save register
6545 %r1 in the frame marker, load the branch destination DEST into %r1,
6546 execute the branch, and restore %r1 in the delay slot of the branch.
6548 Since long branches may have an insn in the delay slot and the
6549 delay slot is used to restore %r1, we in general need to extract
6550 this insn and execute it before the branch. However, to facilitate
6551 use of this function by conditional branches, we also provide an
6552 option to not extract the delay insn so that it will be emitted
6553 after the long branch. So, if there is an insn in the delay slot,
6554 it is extracted if XDELAY is nonzero.
6556 The lengths of the various long-branch sequences are 20, 16 and 24
6557 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6560 pa_output_lbranch (rtx dest, rtx insn, int xdelay)
6564 xoperands[0] = dest;
6566 /* First, free up the delay slot. */
6567 if (xdelay && dbr_sequence_length () != 0)
6569 /* We can't handle a jump in the delay slot. */
6570 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6572 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6575 /* Now delete the delay insn. */
6576 SET_INSN_DELETED (NEXT_INSN (insn));
6579 /* Output an insn to save %r1. The runtime documentation doesn't
6580 specify whether the "Clean Up" slot in the callers frame can
6581 be clobbered by the callee. It isn't copied by HP's builtin
6582 alloca, so this suggests that it can be clobbered if necessary.
6583 The "Static Link" location is copied by HP builtin alloca, so
6584 we avoid using it. Using the cleanup slot might be a problem
6585 if we have to interoperate with languages that pass cleanup
6586 information. However, it should be possible to handle these
6587 situations with GCC's asm feature.
6589 The "Current RP" slot is reserved for the called procedure, so
6590 we try to use it when we don't have a frame of our own. It's
6591 rather unlikely that we won't have a frame when we need to emit
6594 Really the way to go long term is a register scavenger; goto
6595 the target of the jump and find a register which we can use
6596 as a scratch to hold the value in %r1. Then, we wouldn't have
6597 to free up the delay slot or clobber a slot that may be needed
6598 for other purposes. */
6601 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6602 /* Use the return pointer slot in the frame marker. */
6603 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6605 /* Use the slot at -40 in the frame marker since HP builtin
6606 alloca doesn't copy it. */
6607 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6611 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6612 /* Use the return pointer slot in the frame marker. */
6613 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6615 /* Use the "Clean Up" slot in the frame marker. In GCC,
6616 the only other use of this location is for copying a
6617 floating point double argument from a floating-point
6618 register to two general registers. The copy is done
6619 as an "atomic" operation when outputting a call, so it
6620 won't interfere with our using the location here. */
6621 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6624 if (TARGET_PORTABLE_RUNTIME)
6626 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6627 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6628 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6632 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6633 if (TARGET_SOM || !TARGET_GAS)
6635 xoperands[1] = gen_label_rtx ();
6636 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6637 targetm.asm_out.internal_label (asm_out_file, "L",
6638 CODE_LABEL_NUMBER (xoperands[1]));
6639 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6643 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6644 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6646 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6649 /* Now output a very long branch to the original target. */
6650 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6652 /* Now restore the value of %r1 in the delay slot. */
6655 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6656 return "ldd -16(%%r30),%%r1";
6658 return "ldd -40(%%r30),%%r1";
6662 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6663 return "ldw -20(%%r30),%%r1";
6665 return "ldw -12(%%r30),%%r1";
6669 /* This routine handles all the branch-on-bit conditional branch sequences we
6670 might need to generate. It handles nullification of delay slots,
6671 varying length branches, negated branches and all combinations of the
6672 above. it returns the appropriate output template to emit the branch. */
6675 pa_output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6677 static char buf[100];
6679 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6680 int length = get_attr_length (insn);
6683 /* A conditional branch to the following instruction (e.g. the delay slot) is
6684 asking for a disaster. I do not think this can happen as this pattern
6685 is only used when optimizing; jump optimization should eliminate the
6686 jump. But be prepared just in case. */
6688 if (branch_to_delay_slot_p (insn))
6691 /* If this is a long branch with its delay slot unfilled, set `nullify'
6692 as it can nullify the delay slot and save a nop. */
6693 if (length == 8 && dbr_sequence_length () == 0)
6696 /* If this is a short forward conditional branch which did not get
6697 its delay slot filled, the delay slot can still be nullified. */
6698 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6699 nullify = forward_branch_p (insn);
6701 /* A forward branch over a single nullified insn can be done with a
6702 extrs instruction. This avoids a single cycle penalty due to
6703 mis-predicted branch if we fall through (branch not taken). */
6704 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6709 /* All short conditional branches except backwards with an unfilled
6713 strcpy (buf, "{extrs,|extrw,s,}");
6715 strcpy (buf, "bb,");
6716 if (useskip && GET_MODE (operands[0]) == DImode)
6717 strcpy (buf, "extrd,s,*");
6718 else if (GET_MODE (operands[0]) == DImode)
6719 strcpy (buf, "bb,*");
6720 if ((which == 0 && negated)
6721 || (which == 1 && ! negated))
6726 strcat (buf, " %0,%1,1,%%r0");
6727 else if (nullify && negated)
6729 if (branch_needs_nop_p (insn))
6730 strcat (buf, ",n %0,%1,%3%#");
6732 strcat (buf, ",n %0,%1,%3");
6734 else if (nullify && ! negated)
6736 if (branch_needs_nop_p (insn))
6737 strcat (buf, ",n %0,%1,%2%#");
6739 strcat (buf, ",n %0,%1,%2");
6741 else if (! nullify && negated)
6742 strcat (buf, " %0,%1,%3");
6743 else if (! nullify && ! negated)
6744 strcat (buf, " %0,%1,%2");
6747 /* All long conditionals. Note a short backward branch with an
6748 unfilled delay slot is treated just like a long backward branch
6749 with an unfilled delay slot. */
6751 /* Handle weird backwards branch with a filled delay slot
6752 which is nullified. */
6753 if (dbr_sequence_length () != 0
6754 && ! forward_branch_p (insn)
6757 strcpy (buf, "bb,");
6758 if (GET_MODE (operands[0]) == DImode)
6760 if ((which == 0 && negated)
6761 || (which == 1 && ! negated))
6766 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6768 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6770 /* Handle short backwards branch with an unfilled delay slot.
6771 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6772 taken and untaken branches. */
6773 else if (dbr_sequence_length () == 0
6774 && ! forward_branch_p (insn)
6775 && INSN_ADDRESSES_SET_P ()
6776 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6777 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6779 strcpy (buf, "bb,");
6780 if (GET_MODE (operands[0]) == DImode)
6782 if ((which == 0 && negated)
6783 || (which == 1 && ! negated))
6788 strcat (buf, " %0,%1,%3%#");
6790 strcat (buf, " %0,%1,%2%#");
6794 if (GET_MODE (operands[0]) == DImode)
6795 strcpy (buf, "extrd,s,*");
6797 strcpy (buf, "{extrs,|extrw,s,}");
6798 if ((which == 0 && negated)
6799 || (which == 1 && ! negated))
6803 if (nullify && negated)
6804 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6805 else if (nullify && ! negated)
6806 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6808 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6810 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6815 /* The reversed conditional branch must branch over one additional
6816 instruction if the delay slot is filled and needs to be extracted
6817 by pa_output_lbranch. If the delay slot is empty or this is a
6818 nullified forward branch, the instruction after the reversed
6819 condition branch must be nullified. */
6820 if (dbr_sequence_length () == 0
6821 || (nullify && forward_branch_p (insn)))
6825 operands[4] = GEN_INT (length);
6830 operands[4] = GEN_INT (length + 4);
6833 if (GET_MODE (operands[0]) == DImode)
6834 strcpy (buf, "bb,*");
6836 strcpy (buf, "bb,");
6837 if ((which == 0 && negated)
6838 || (which == 1 && !negated))
6843 strcat (buf, ",n %0,%1,.+%4");
6845 strcat (buf, " %0,%1,.+%4");
6846 output_asm_insn (buf, operands);
6847 return pa_output_lbranch (negated ? operands[3] : operands[2],
6853 /* This routine handles all the branch-on-variable-bit conditional branch
6854 sequences we might need to generate. It handles nullification of delay
6855 slots, varying length branches, negated branches and all combinations
6856 of the above. it returns the appropriate output template to emit the
6860 pa_output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn,
6863 static char buf[100];
6865 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6866 int length = get_attr_length (insn);
6869 /* A conditional branch to the following instruction (e.g. the delay slot) is
6870 asking for a disaster. I do not think this can happen as this pattern
6871 is only used when optimizing; jump optimization should eliminate the
6872 jump. But be prepared just in case. */
6874 if (branch_to_delay_slot_p (insn))
6877 /* If this is a long branch with its delay slot unfilled, set `nullify'
6878 as it can nullify the delay slot and save a nop. */
6879 if (length == 8 && dbr_sequence_length () == 0)
6882 /* If this is a short forward conditional branch which did not get
6883 its delay slot filled, the delay slot can still be nullified. */
6884 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6885 nullify = forward_branch_p (insn);
6887 /* A forward branch over a single nullified insn can be done with a
6888 extrs instruction. This avoids a single cycle penalty due to
6889 mis-predicted branch if we fall through (branch not taken). */
6890 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6895 /* All short conditional branches except backwards with an unfilled
6899 strcpy (buf, "{vextrs,|extrw,s,}");
6901 strcpy (buf, "{bvb,|bb,}");
6902 if (useskip && GET_MODE (operands[0]) == DImode)
6903 strcpy (buf, "extrd,s,*");
6904 else if (GET_MODE (operands[0]) == DImode)
6905 strcpy (buf, "bb,*");
6906 if ((which == 0 && negated)
6907 || (which == 1 && ! negated))
6912 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6913 else if (nullify && negated)
6915 if (branch_needs_nop_p (insn))
6916 strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
6918 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6920 else if (nullify && ! negated)
6922 if (branch_needs_nop_p (insn))
6923 strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
6925 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6927 else if (! nullify && negated)
6928 strcat (buf, "{ %0,%3| %0,%%sar,%3}");
6929 else if (! nullify && ! negated)
6930 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6933 /* All long conditionals. Note a short backward branch with an
6934 unfilled delay slot is treated just like a long backward branch
6935 with an unfilled delay slot. */
6937 /* Handle weird backwards branch with a filled delay slot
6938 which is nullified. */
6939 if (dbr_sequence_length () != 0
6940 && ! forward_branch_p (insn)
6943 strcpy (buf, "{bvb,|bb,}");
6944 if (GET_MODE (operands[0]) == DImode)
6946 if ((which == 0 && negated)
6947 || (which == 1 && ! negated))
6952 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6954 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6956 /* Handle short backwards branch with an unfilled delay slot.
6957 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6958 taken and untaken branches. */
6959 else if (dbr_sequence_length () == 0
6960 && ! forward_branch_p (insn)
6961 && INSN_ADDRESSES_SET_P ()
6962 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6963 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6965 strcpy (buf, "{bvb,|bb,}");
6966 if (GET_MODE (operands[0]) == DImode)
6968 if ((which == 0 && negated)
6969 || (which == 1 && ! negated))
6974 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6976 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6980 strcpy (buf, "{vextrs,|extrw,s,}");
6981 if (GET_MODE (operands[0]) == DImode)
6982 strcpy (buf, "extrd,s,*");
6983 if ((which == 0 && negated)
6984 || (which == 1 && ! negated))
6988 if (nullify && negated)
6989 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6990 else if (nullify && ! negated)
6991 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6993 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6995 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
7000 /* The reversed conditional branch must branch over one additional
7001 instruction if the delay slot is filled and needs to be extracted
7002 by pa_output_lbranch. If the delay slot is empty or this is a
7003 nullified forward branch, the instruction after the reversed
7004 condition branch must be nullified. */
7005 if (dbr_sequence_length () == 0
7006 || (nullify && forward_branch_p (insn)))
7010 operands[4] = GEN_INT (length);
7015 operands[4] = GEN_INT (length + 4);
7018 if (GET_MODE (operands[0]) == DImode)
7019 strcpy (buf, "bb,*");
7021 strcpy (buf, "{bvb,|bb,}");
7022 if ((which == 0 && negated)
7023 || (which == 1 && !negated))
7028 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
7030 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
7031 output_asm_insn (buf, operands);
7032 return pa_output_lbranch (negated ? operands[3] : operands[2],
7038 /* Return the output template for emitting a dbra type insn.
7040 Note it may perform some output operations on its own before
7041 returning the final output string. */
7043 pa_output_dbra (rtx *operands, rtx insn, int which_alternative)
7045 int length = get_attr_length (insn);
7047 /* A conditional branch to the following instruction (e.g. the delay slot) is
7048 asking for a disaster. Be prepared! */
7050 if (branch_to_delay_slot_p (insn))
7052 if (which_alternative == 0)
7053 return "ldo %1(%0),%0";
7054 else if (which_alternative == 1)
7056 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
7057 output_asm_insn ("ldw -16(%%r30),%4", operands);
7058 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7059 return "{fldws|fldw} -16(%%r30),%0";
7063 output_asm_insn ("ldw %0,%4", operands);
7064 return "ldo %1(%4),%4\n\tstw %4,%0";
7068 if (which_alternative == 0)
7070 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7073 /* If this is a long branch with its delay slot unfilled, set `nullify'
7074 as it can nullify the delay slot and save a nop. */
7075 if (length == 8 && dbr_sequence_length () == 0)
7078 /* If this is a short forward conditional branch which did not get
7079 its delay slot filled, the delay slot can still be nullified. */
7080 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7081 nullify = forward_branch_p (insn);
7088 if (branch_needs_nop_p (insn))
7089 return "addib,%C2,n %1,%0,%3%#";
7091 return "addib,%C2,n %1,%0,%3";
7094 return "addib,%C2 %1,%0,%3";
7097 /* Handle weird backwards branch with a fulled delay slot
7098 which is nullified. */
7099 if (dbr_sequence_length () != 0
7100 && ! forward_branch_p (insn)
7102 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7103 /* Handle short backwards branch with an unfilled delay slot.
7104 Using a addb;nop rather than addi;bl saves 1 cycle for both
7105 taken and untaken branches. */
7106 else if (dbr_sequence_length () == 0
7107 && ! forward_branch_p (insn)
7108 && INSN_ADDRESSES_SET_P ()
7109 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7110 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7111 return "addib,%C2 %1,%0,%3%#";
7113 /* Handle normal cases. */
7115 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7117 return "addi,%N2 %1,%0,%0\n\tb %3";
7120 /* The reversed conditional branch must branch over one additional
7121 instruction if the delay slot is filled and needs to be extracted
7122 by pa_output_lbranch. If the delay slot is empty or this is a
7123 nullified forward branch, the instruction after the reversed
7124 condition branch must be nullified. */
7125 if (dbr_sequence_length () == 0
7126 || (nullify && forward_branch_p (insn)))
7130 operands[4] = GEN_INT (length);
7135 operands[4] = GEN_INT (length + 4);
7139 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
7141 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
7143 return pa_output_lbranch (operands[3], insn, xdelay);
7147 /* Deal with gross reload from FP register case. */
7148 else if (which_alternative == 1)
7150 /* Move loop counter from FP register to MEM then into a GR,
7151 increment the GR, store the GR into MEM, and finally reload
7152 the FP register from MEM from within the branch's delay slot. */
7153 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7155 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7157 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7158 else if (length == 28)
7159 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7162 operands[5] = GEN_INT (length - 16);
7163 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
7164 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7165 return pa_output_lbranch (operands[3], insn, 0);
7168 /* Deal with gross reload from memory case. */
7171 /* Reload loop counter from memory, the store back to memory
7172 happens in the branch's delay slot. */
7173 output_asm_insn ("ldw %0,%4", operands);
7175 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7176 else if (length == 16)
7177 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7180 operands[5] = GEN_INT (length - 4);
7181 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
7182 return pa_output_lbranch (operands[3], insn, 0);
7187 /* Return the output template for emitting a movb type insn.
7189 Note it may perform some output operations on its own before
7190 returning the final output string. */
7192 pa_output_movb (rtx *operands, rtx insn, int which_alternative,
7193 int reverse_comparison)
7195 int length = get_attr_length (insn);
7197 /* A conditional branch to the following instruction (e.g. the delay slot) is
7198 asking for a disaster. Be prepared! */
7200 if (branch_to_delay_slot_p (insn))
7202 if (which_alternative == 0)
7203 return "copy %1,%0";
7204 else if (which_alternative == 1)
7206 output_asm_insn ("stw %1,-16(%%r30)", operands);
7207 return "{fldws|fldw} -16(%%r30),%0";
7209 else if (which_alternative == 2)
7215 /* Support the second variant. */
7216 if (reverse_comparison)
7217 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7219 if (which_alternative == 0)
7221 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7224 /* If this is a long branch with its delay slot unfilled, set `nullify'
7225 as it can nullify the delay slot and save a nop. */
7226 if (length == 8 && dbr_sequence_length () == 0)
7229 /* If this is a short forward conditional branch which did not get
7230 its delay slot filled, the delay slot can still be nullified. */
7231 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7232 nullify = forward_branch_p (insn);
7239 if (branch_needs_nop_p (insn))
7240 return "movb,%C2,n %1,%0,%3%#";
7242 return "movb,%C2,n %1,%0,%3";
7245 return "movb,%C2 %1,%0,%3";
7248 /* Handle weird backwards branch with a filled delay slot
7249 which is nullified. */
7250 if (dbr_sequence_length () != 0
7251 && ! forward_branch_p (insn)
7253 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7255 /* Handle short backwards branch with an unfilled delay slot.
7256 Using a movb;nop rather than or;bl saves 1 cycle for both
7257 taken and untaken branches. */
7258 else if (dbr_sequence_length () == 0
7259 && ! forward_branch_p (insn)
7260 && INSN_ADDRESSES_SET_P ()
7261 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7262 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7263 return "movb,%C2 %1,%0,%3%#";
7264 /* Handle normal cases. */
7266 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7268 return "or,%N2 %1,%%r0,%0\n\tb %3";
7271 /* The reversed conditional branch must branch over one additional
7272 instruction if the delay slot is filled and needs to be extracted
7273 by pa_output_lbranch. If the delay slot is empty or this is a
7274 nullified forward branch, the instruction after the reversed
7275 condition branch must be nullified. */
7276 if (dbr_sequence_length () == 0
7277 || (nullify && forward_branch_p (insn)))
7281 operands[4] = GEN_INT (length);
7286 operands[4] = GEN_INT (length + 4);
7290 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7292 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7294 return pa_output_lbranch (operands[3], insn, xdelay);
7297 /* Deal with gross reload for FP destination register case. */
7298 else if (which_alternative == 1)
7300 /* Move source register to MEM, perform the branch test, then
7301 finally load the FP register from MEM from within the branch's
7303 output_asm_insn ("stw %1,-16(%%r30)", operands);
7305 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7306 else if (length == 16)
7307 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7310 operands[4] = GEN_INT (length - 4);
7311 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7312 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7313 return pa_output_lbranch (operands[3], insn, 0);
7316 /* Deal with gross reload from memory case. */
7317 else if (which_alternative == 2)
7319 /* Reload loop counter from memory, the store back to memory
7320 happens in the branch's delay slot. */
7322 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7323 else if (length == 12)
7324 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7327 operands[4] = GEN_INT (length);
7328 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7330 return pa_output_lbranch (operands[3], insn, 0);
7333 /* Handle SAR as a destination. */
7337 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7338 else if (length == 12)
7339 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7342 operands[4] = GEN_INT (length);
7343 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7345 return pa_output_lbranch (operands[3], insn, 0);
7350 /* Copy any FP arguments in INSN into integer registers. */
7352 copy_fp_args (rtx insn)
7357 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7359 int arg_mode, regno;
7360 rtx use = XEXP (link, 0);
7362 if (! (GET_CODE (use) == USE
7363 && GET_CODE (XEXP (use, 0)) == REG
7364 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7367 arg_mode = GET_MODE (XEXP (use, 0));
7368 regno = REGNO (XEXP (use, 0));
7370 /* Is it a floating point register? */
7371 if (regno >= 32 && regno <= 39)
7373 /* Copy the FP register into an integer register via memory. */
7374 if (arg_mode == SFmode)
7376 xoperands[0] = XEXP (use, 0);
7377 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7378 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7379 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7383 xoperands[0] = XEXP (use, 0);
7384 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7385 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7386 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7387 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7393 /* Compute length of the FP argument copy sequence for INSN. */
7395 length_fp_args (rtx insn)
7400 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7402 int arg_mode, regno;
7403 rtx use = XEXP (link, 0);
7405 if (! (GET_CODE (use) == USE
7406 && GET_CODE (XEXP (use, 0)) == REG
7407 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7410 arg_mode = GET_MODE (XEXP (use, 0));
7411 regno = REGNO (XEXP (use, 0));
7413 /* Is it a floating point register? */
7414 if (regno >= 32 && regno <= 39)
7416 if (arg_mode == SFmode)
7426 /* Return the attribute length for the millicode call instruction INSN.
7427 The length must match the code generated by pa_output_millicode_call.
7428 We include the delay slot in the returned length as it is better to
7429 over estimate the length than to under estimate it. */
7432 pa_attr_length_millicode_call (rtx insn)
7434 unsigned long distance = -1;
7435 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7437 if (INSN_ADDRESSES_SET_P ())
7439 distance = (total + insn_current_reference_address (insn));
7440 if (distance < total)
7446 if (!TARGET_LONG_CALLS && distance < 7600000)
7451 else if (TARGET_PORTABLE_RUNTIME)
7455 if (!TARGET_LONG_CALLS && distance < 240000)
7458 if (TARGET_LONG_ABS_CALL && !flag_pic)
7465 /* INSN is a function call. It may have an unconditional jump
7468 CALL_DEST is the routine we are calling. */
7471 pa_output_millicode_call (rtx insn, rtx call_dest)
7473 int attr_length = get_attr_length (insn);
7474 int seq_length = dbr_sequence_length ();
7479 xoperands[0] = call_dest;
7480 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7482 /* Handle the common case where we are sure that the branch will
7483 reach the beginning of the $CODE$ subspace. The within reach
7484 form of the $$sh_func_adrs call has a length of 28. Because
7485 it has an attribute type of multi, it never has a nonzero
7486 sequence length. The length of the $$sh_func_adrs is the same
7487 as certain out of reach PIC calls to other routines. */
7488 if (!TARGET_LONG_CALLS
7489 && ((seq_length == 0
7490 && (attr_length == 12
7491 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7492 || (seq_length != 0 && attr_length == 8)))
7494 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7500 /* It might seem that one insn could be saved by accessing
7501 the millicode function using the linkage table. However,
7502 this doesn't work in shared libraries and other dynamically
7503 loaded objects. Using a pc-relative sequence also avoids
7504 problems related to the implicit use of the gp register. */
7505 output_asm_insn ("b,l .+8,%%r1", xoperands);
7509 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7510 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7514 xoperands[1] = gen_label_rtx ();
7515 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7516 targetm.asm_out.internal_label (asm_out_file, "L",
7517 CODE_LABEL_NUMBER (xoperands[1]));
7518 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7521 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7523 else if (TARGET_PORTABLE_RUNTIME)
7525 /* Pure portable runtime doesn't allow be/ble; we also don't
7526 have PIC support in the assembler/linker, so this sequence
7529 /* Get the address of our target into %r1. */
7530 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7531 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7533 /* Get our return address into %r31. */
7534 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7535 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7537 /* Jump to our target address in %r1. */
7538 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7542 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7544 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7546 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7550 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7551 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7553 if (TARGET_SOM || !TARGET_GAS)
7555 /* The HP assembler can generate relocations for the
7556 difference of two symbols. GAS can do this for a
7557 millicode symbol but not an arbitrary external
7558 symbol when generating SOM output. */
7559 xoperands[1] = gen_label_rtx ();
7560 targetm.asm_out.internal_label (asm_out_file, "L",
7561 CODE_LABEL_NUMBER (xoperands[1]));
7562 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7563 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7567 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7568 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7572 /* Jump to our target address in %r1. */
7573 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7577 if (seq_length == 0)
7578 output_asm_insn ("nop", xoperands);
7580 /* We are done if there isn't a jump in the delay slot. */
7581 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7584 /* This call has an unconditional jump in its delay slot. */
7585 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7587 /* See if the return address can be adjusted. Use the containing
7588 sequence insn's address. */
7589 if (INSN_ADDRESSES_SET_P ())
7591 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7592 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7593 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7595 if (VAL_14_BITS_P (distance))
7597 xoperands[1] = gen_label_rtx ();
7598 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7599 targetm.asm_out.internal_label (asm_out_file, "L",
7600 CODE_LABEL_NUMBER (xoperands[1]));
7603 /* ??? This branch may not reach its target. */
7604 output_asm_insn ("nop\n\tb,n %0", xoperands);
7607 /* ??? This branch may not reach its target. */
7608 output_asm_insn ("nop\n\tb,n %0", xoperands);
7610 /* Delete the jump. */
7611 SET_INSN_DELETED (NEXT_INSN (insn));
7616 /* Return the attribute length of the call instruction INSN. The SIBCALL
7617 flag indicates whether INSN is a regular call or a sibling call. The
7618 length returned must be longer than the code actually generated by
7619 pa_output_call. Since branch shortening is done before delay branch
7620 sequencing, there is no way to determine whether or not the delay
7621 slot will be filled during branch shortening. Even when the delay
7622 slot is filled, we may have to add a nop if the delay slot contains
7623 a branch that can't reach its target. Thus, we always have to include
7624 the delay slot in the length estimate. This used to be done in
7625 pa_adjust_insn_length but we do it here now as some sequences always
7626 fill the delay slot and we can save four bytes in the estimate for
7630 pa_attr_length_call (rtx insn, int sibcall)
7633 rtx call, call_dest;
7636 rtx pat = PATTERN (insn);
7637 unsigned long distance = -1;
7639 gcc_assert (GET_CODE (insn) == CALL_INSN);
7641 if (INSN_ADDRESSES_SET_P ())
7643 unsigned long total;
7645 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7646 distance = (total + insn_current_reference_address (insn));
7647 if (distance < total)
7651 gcc_assert (GET_CODE (pat) == PARALLEL);
7653 /* Get the call rtx. */
7654 call = XVECEXP (pat, 0, 0);
7655 if (GET_CODE (call) == SET)
7656 call = SET_SRC (call);
7658 gcc_assert (GET_CODE (call) == CALL);
7660 /* Determine if this is a local call. */
7661 call_dest = XEXP (XEXP (call, 0), 0);
7662 call_decl = SYMBOL_REF_DECL (call_dest);
7663 local_call = call_decl && targetm.binds_local_p (call_decl);
7665 /* pc-relative branch. */
7666 if (!TARGET_LONG_CALLS
7667 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7668 || distance < 240000))
7671 /* 64-bit plabel sequence. */
7672 else if (TARGET_64BIT && !local_call)
7673 length += sibcall ? 28 : 24;
7675 /* non-pic long absolute branch sequence. */
7676 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7679 /* long pc-relative branch sequence. */
7680 else if (TARGET_LONG_PIC_SDIFF_CALL
7681 || (TARGET_GAS && !TARGET_SOM
7682 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7686 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7690 /* 32-bit plabel sequence. */
7696 length += length_fp_args (insn);
7706 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7714 /* INSN is a function call. It may have an unconditional jump
7717 CALL_DEST is the routine we are calling. */
7720 pa_output_call (rtx insn, rtx call_dest, int sibcall)
7722 int delay_insn_deleted = 0;
7723 int delay_slot_filled = 0;
7724 int seq_length = dbr_sequence_length ();
7725 tree call_decl = SYMBOL_REF_DECL (call_dest);
7726 int local_call = call_decl && targetm.binds_local_p (call_decl);
7729 xoperands[0] = call_dest;
7731 /* Handle the common case where we're sure that the branch will reach
7732 the beginning of the "$CODE$" subspace. This is the beginning of
7733 the current function if we are in a named section. */
7734 if (!TARGET_LONG_CALLS && pa_attr_length_call (insn, sibcall) == 8)
7736 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7737 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7741 if (TARGET_64BIT && !local_call)
7743 /* ??? As far as I can tell, the HP linker doesn't support the
7744 long pc-relative sequence described in the 64-bit runtime
7745 architecture. So, we use a slightly longer indirect call. */
7746 xoperands[0] = pa_get_deferred_plabel (call_dest);
7747 xoperands[1] = gen_label_rtx ();
7749 /* If this isn't a sibcall, we put the load of %r27 into the
7750 delay slot. We can't do this in a sibcall as we don't
7751 have a second call-clobbered scratch register available. */
7753 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7756 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7759 /* Now delete the delay insn. */
7760 SET_INSN_DELETED (NEXT_INSN (insn));
7761 delay_insn_deleted = 1;
7764 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7765 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7766 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7770 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7771 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7772 output_asm_insn ("bve (%%r1)", xoperands);
7776 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7777 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7778 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7779 delay_slot_filled = 1;
7784 int indirect_call = 0;
7786 /* Emit a long call. There are several different sequences
7787 of increasing length and complexity. In most cases,
7788 they don't allow an instruction in the delay slot. */
7789 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7790 && !TARGET_LONG_PIC_SDIFF_CALL
7791 && !(TARGET_GAS && !TARGET_SOM
7792 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7797 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7801 || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)))
7803 /* A non-jump insn in the delay slot. By definition we can
7804 emit this insn before the call (and in fact before argument
7806 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7809 /* Now delete the delay insn. */
7810 SET_INSN_DELETED (NEXT_INSN (insn));
7811 delay_insn_deleted = 1;
7814 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7816 /* This is the best sequence for making long calls in
7817 non-pic code. Unfortunately, GNU ld doesn't provide
7818 the stub needed for external calls, and GAS's support
7819 for this with the SOM linker is buggy. It is safe
7820 to use this for local calls. */
7821 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7823 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7827 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7830 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7832 output_asm_insn ("copy %%r31,%%r2", xoperands);
7833 delay_slot_filled = 1;
7838 if (TARGET_LONG_PIC_SDIFF_CALL)
7840 /* The HP assembler and linker can handle relocations
7841 for the difference of two symbols. The HP assembler
7842 recognizes the sequence as a pc-relative call and
7843 the linker provides stubs when needed. */
7844 xoperands[1] = gen_label_rtx ();
7845 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7846 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7847 targetm.asm_out.internal_label (asm_out_file, "L",
7848 CODE_LABEL_NUMBER (xoperands[1]));
7849 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7851 else if (TARGET_GAS && !TARGET_SOM
7852 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7854 /* GAS currently can't generate the relocations that
7855 are needed for the SOM linker under HP-UX using this
7856 sequence. The GNU linker doesn't generate the stubs
7857 that are needed for external calls on TARGET_ELF32
7858 with this sequence. For now, we have to use a
7859 longer plabel sequence when using GAS. */
7860 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7861 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7863 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7868 /* Emit a long plabel-based call sequence. This is
7869 essentially an inline implementation of $$dyncall.
7870 We don't actually try to call $$dyncall as this is
7871 as difficult as calling the function itself. */
7872 xoperands[0] = pa_get_deferred_plabel (call_dest);
7873 xoperands[1] = gen_label_rtx ();
7875 /* Since the call is indirect, FP arguments in registers
7876 need to be copied to the general registers. Then, the
7877 argument relocation stub will copy them back. */
7879 copy_fp_args (insn);
7883 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7884 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7885 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7889 output_asm_insn ("addil LR'%0-$global$,%%r27",
7891 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7895 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7896 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7897 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7898 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7900 if (!sibcall && !TARGET_PA_20)
7902 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7903 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7904 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7906 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7913 output_asm_insn ("bve (%%r1)", xoperands);
7918 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7919 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7920 delay_slot_filled = 1;
7923 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7928 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7929 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7934 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7935 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7937 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7941 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7942 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7944 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7947 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7949 output_asm_insn ("copy %%r31,%%r2", xoperands);
7950 delay_slot_filled = 1;
7957 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7958 output_asm_insn ("nop", xoperands);
7960 /* We are done if there isn't a jump in the delay slot. */
7962 || delay_insn_deleted
7963 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7966 /* A sibcall should never have a branch in the delay slot. */
7967 gcc_assert (!sibcall);
7969 /* This call has an unconditional jump in its delay slot. */
7970 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7972 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7974 /* See if the return address can be adjusted. Use the containing
7975 sequence insn's address. This would break the regular call/return@
7976 relationship assumed by the table based eh unwinder, so only do that
7977 if the call is not possibly throwing. */
7978 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7979 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7980 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7982 if (VAL_14_BITS_P (distance)
7983 && !(can_throw_internal (insn) || can_throw_external (insn)))
7985 xoperands[1] = gen_label_rtx ();
7986 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7987 targetm.asm_out.internal_label (asm_out_file, "L",
7988 CODE_LABEL_NUMBER (xoperands[1]));
7991 output_asm_insn ("nop\n\tb,n %0", xoperands);
7994 output_asm_insn ("b,n %0", xoperands);
7996 /* Delete the jump. */
7997 SET_INSN_DELETED (NEXT_INSN (insn));
8002 /* Return the attribute length of the indirect call instruction INSN.
8003 The length must match the code generated by output_indirect call.
8004 The returned length includes the delay slot. Currently, the delay
8005 slot of an indirect call sequence is not exposed and it is used by
8006 the sequence itself. */
8009 pa_attr_length_indirect_call (rtx insn)
8011 unsigned long distance = -1;
8012 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
8014 if (INSN_ADDRESSES_SET_P ())
8016 distance = (total + insn_current_reference_address (insn));
8017 if (distance < total)
8024 if (TARGET_FAST_INDIRECT_CALLS
8025 || (!TARGET_PORTABLE_RUNTIME
8026 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
8027 || distance < 240000)))
8033 if (TARGET_PORTABLE_RUNTIME)
8036 /* Out of reach, can use ble. */
8041 pa_output_indirect_call (rtx insn, rtx call_dest)
8047 xoperands[0] = call_dest;
8048 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
8049 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
8053 /* First the special case for kernels, level 0 systems, etc. */
8054 if (TARGET_FAST_INDIRECT_CALLS)
8055 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8057 /* Now the normal case -- we can reach $$dyncall directly or
8058 we're sure that we can get there via a long-branch stub.
8060 No need to check target flags as the length uniquely identifies
8061 the remaining cases. */
8062 if (pa_attr_length_indirect_call (insn) == 8)
8064 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8065 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8066 variant of the B,L instruction can't be used on the SOM target. */
8067 if (TARGET_PA_20 && !TARGET_SOM)
8068 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
8070 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8073 /* Long millicode call, but we are not generating PIC or portable runtime
8075 if (pa_attr_length_indirect_call (insn) == 12)
8076 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8078 /* Long millicode call for portable runtime. */
8079 if (pa_attr_length_indirect_call (insn) == 20)
8080 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
8082 /* We need a long PIC call to $$dyncall. */
8083 xoperands[0] = NULL_RTX;
8084 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8085 if (TARGET_SOM || !TARGET_GAS)
8087 xoperands[0] = gen_label_rtx ();
8088 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
8089 targetm.asm_out.internal_label (asm_out_file, "L",
8090 CODE_LABEL_NUMBER (xoperands[0]));
8091 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
8095 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
8096 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
8099 output_asm_insn ("blr %%r0,%%r2", xoperands);
8100 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
8104 /* In HPUX 8.0's shared library scheme, special relocations are needed
8105 for function labels if they might be passed to a function
8106 in a shared library (because shared libraries don't live in code
8107 space), and special magic is needed to construct their address. */
8110 pa_encode_label (rtx sym)
8112 const char *str = XSTR (sym, 0);
8113 int len = strlen (str) + 1;
8116 p = newstr = XALLOCAVEC (char, len + 1);
8120 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
8124 pa_encode_section_info (tree decl, rtx rtl, int first)
8126 int old_referenced = 0;
8128 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
8130 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
8132 default_encode_section_info (decl, rtl, first);
8134 if (first && TEXT_SPACE_P (decl))
8136 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
8137 if (TREE_CODE (decl) == FUNCTION_DECL)
8138 pa_encode_label (XEXP (rtl, 0));
8140 else if (old_referenced)
8141 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
8144 /* This is sort of inverse to pa_encode_section_info. */
8147 pa_strip_name_encoding (const char *str)
8149 str += (*str == '@');
8150 str += (*str == '*');
8154 /* Returns 1 if OP is a function label involved in a simple addition
8155 with a constant. Used to keep certain patterns from matching
8156 during instruction combination. */
8158 pa_is_function_label_plus_const (rtx op)
8160 /* Strip off any CONST. */
8161 if (GET_CODE (op) == CONST)
8164 return (GET_CODE (op) == PLUS
8165 && function_label_operand (XEXP (op, 0), VOIDmode)
8166 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8169 /* Output assembly code for a thunk to FUNCTION. */
8172 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
8173 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8176 static unsigned int current_thunk_number;
8177 int val_14 = VAL_14_BITS_P (delta);
8178 unsigned int old_last_address = last_address, nbytes = 0;
8182 xoperands[0] = XEXP (DECL_RTL (function), 0);
8183 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
8184 xoperands[2] = GEN_INT (delta);
8186 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
8187 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
8189 /* Output the thunk. We know that the function is in the same
8190 translation unit (i.e., the same space) as the thunk, and that
8191 thunks are output after their method. Thus, we don't need an
8192 external branch to reach the function. With SOM and GAS,
8193 functions and thunks are effectively in different sections.
8194 Thus, we can always use a IA-relative branch and the linker
8195 will add a long branch stub if necessary.
8197 However, we have to be careful when generating PIC code on the
8198 SOM port to ensure that the sequence does not transfer to an
8199 import stub for the target function as this could clobber the
8200 return value saved at SP-24. This would also apply to the
8201 32-bit linux port if the multi-space model is implemented. */
8202 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8203 && !(flag_pic && TREE_PUBLIC (function))
8204 && (TARGET_GAS || last_address < 262132))
8205 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8206 && ((targetm_common.have_named_sections
8207 && DECL_SECTION_NAME (thunk_fndecl) != NULL
8208 /* The GNU 64-bit linker has rather poor stub management.
8209 So, we use a long branch from thunks that aren't in
8210 the same section as the target function. */
8212 && (DECL_SECTION_NAME (thunk_fndecl)
8213 != DECL_SECTION_NAME (function)))
8214 || ((DECL_SECTION_NAME (thunk_fndecl)
8215 == DECL_SECTION_NAME (function))
8216 && last_address < 262132)))
8217 || (targetm_common.have_named_sections
8218 && DECL_SECTION_NAME (thunk_fndecl) == NULL
8219 && DECL_SECTION_NAME (function) == NULL
8220 && last_address < 262132)
8221 || (!targetm_common.have_named_sections
8222 && last_address < 262132))))
8225 output_asm_insn ("addil L'%2,%%r26", xoperands);
8227 output_asm_insn ("b %0", xoperands);
8231 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8236 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8240 else if (TARGET_64BIT)
8242 /* We only have one call-clobbered scratch register, so we can't
8243 make use of the delay slot if delta doesn't fit in 14 bits. */
8246 output_asm_insn ("addil L'%2,%%r26", xoperands);
8247 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8250 output_asm_insn ("b,l .+8,%%r1", xoperands);
8254 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8255 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8259 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8260 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8265 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8266 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8271 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8275 else if (TARGET_PORTABLE_RUNTIME)
8277 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8278 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8281 output_asm_insn ("addil L'%2,%%r26", xoperands);
8283 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8287 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8292 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8296 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8298 /* The function is accessible from outside this module. The only
8299 way to avoid an import stub between the thunk and function is to
8300 call the function directly with an indirect sequence similar to
8301 that used by $$dyncall. This is possible because $$dyncall acts
8302 as the import stub in an indirect call. */
8303 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8304 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8305 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8306 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8307 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8308 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8309 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8310 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8311 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8315 output_asm_insn ("addil L'%2,%%r26", xoperands);
8321 output_asm_insn ("bve (%%r22)", xoperands);
8324 else if (TARGET_NO_SPACE_REGS)
8326 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8331 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8332 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8333 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8338 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8340 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8344 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8346 if (TARGET_SOM || !TARGET_GAS)
8348 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8349 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8353 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8354 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8358 output_asm_insn ("addil L'%2,%%r26", xoperands);
8360 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8364 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8369 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8376 output_asm_insn ("addil L'%2,%%r26", xoperands);
8378 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8379 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8383 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8388 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8393 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8395 if (TARGET_SOM && TARGET_GAS)
8397 /* We done with this subspace except possibly for some additional
8398 debug information. Forget that we are in this subspace to ensure
8399 that the next function is output in its own subspace. */
8401 cfun->machine->in_nsubspa = 2;
8404 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8406 switch_to_section (data_section);
8407 output_asm_insn (".align 4", xoperands);
8408 ASM_OUTPUT_LABEL (file, label);
8409 output_asm_insn (".word P'%0", xoperands);
8412 current_thunk_number++;
8413 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8414 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8415 last_address += nbytes;
8416 if (old_last_address > last_address)
8417 last_address = UINT_MAX;
8418 update_total_code_bytes (nbytes);
8421 /* Only direct calls to static functions are allowed to be sibling (tail)
8424 This restriction is necessary because some linker generated stubs will
8425 store return pointers into rp' in some cases which might clobber a
8426 live value already in rp'.
8428 In a sibcall the current function and the target function share stack
8429 space. Thus if the path to the current function and the path to the
8430 target function save a value in rp', they save the value into the
8431 same stack slot, which has undesirable consequences.
8433 Because of the deferred binding nature of shared libraries any function
8434 with external scope could be in a different load module and thus require
8435 rp' to be saved when calling that function. So sibcall optimizations
8436 can only be safe for static function.
8438 Note that GCC never needs return value relocations, so we don't have to
8439 worry about static calls with return value relocations (which require
8442 It is safe to perform a sibcall optimization when the target function
8443 will never return. */
8445 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8447 if (TARGET_PORTABLE_RUNTIME)
8450 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8451 single subspace mode and the call is not indirect. As far as I know,
8452 there is no operating system support for the multiple subspace mode.
8453 It might be possible to support indirect calls if we didn't use
8454 $$dyncall (see the indirect sequence generated in pa_output_call). */
8456 return (decl != NULL_TREE);
8458 /* Sibcalls are not ok because the arg pointer register is not a fixed
8459 register. This prevents the sibcall optimization from occurring. In
8460 addition, there are problems with stub placement using GNU ld. This
8461 is because a normal sibcall branch uses a 17-bit relocation while
8462 a regular call branch uses a 22-bit relocation. As a result, more
8463 care needs to be taken in the placement of long-branch stubs. */
8467 /* Sibcalls are only ok within a translation unit. */
8468 return (decl && !TREE_PUBLIC (decl));
8471 /* ??? Addition is not commutative on the PA due to the weird implicit
8472 space register selection rules for memory addresses. Therefore, we
8473 don't consider a + b == b + a, as this might be inside a MEM. */
8475 pa_commutative_p (const_rtx x, int outer_code)
8477 return (COMMUTATIVE_P (x)
8478 && (TARGET_NO_SPACE_REGS
8479 || (outer_code != UNKNOWN && outer_code != MEM)
8480 || GET_CODE (x) != PLUS));
8483 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8484 use in fmpyadd instructions. */
8486 pa_fmpyaddoperands (rtx *operands)
8488 enum machine_mode mode = GET_MODE (operands[0]);
8490 /* Must be a floating point mode. */
8491 if (mode != SFmode && mode != DFmode)
8494 /* All modes must be the same. */
8495 if (! (mode == GET_MODE (operands[1])
8496 && mode == GET_MODE (operands[2])
8497 && mode == GET_MODE (operands[3])
8498 && mode == GET_MODE (operands[4])
8499 && mode == GET_MODE (operands[5])))
8502 /* All operands must be registers. */
8503 if (! (GET_CODE (operands[1]) == REG
8504 && GET_CODE (operands[2]) == REG
8505 && GET_CODE (operands[3]) == REG
8506 && GET_CODE (operands[4]) == REG
8507 && GET_CODE (operands[5]) == REG))
8510 /* Only 2 real operands to the addition. One of the input operands must
8511 be the same as the output operand. */
8512 if (! rtx_equal_p (operands[3], operands[4])
8513 && ! rtx_equal_p (operands[3], operands[5]))
8516 /* Inout operand of add cannot conflict with any operands from multiply. */
8517 if (rtx_equal_p (operands[3], operands[0])
8518 || rtx_equal_p (operands[3], operands[1])
8519 || rtx_equal_p (operands[3], operands[2]))
8522 /* multiply cannot feed into addition operands. */
8523 if (rtx_equal_p (operands[4], operands[0])
8524 || rtx_equal_p (operands[5], operands[0]))
8527 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8529 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8530 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8531 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8532 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8533 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8534 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8537 /* Passed. Operands are suitable for fmpyadd. */
8541 #if !defined(USE_COLLECT2)
8543 pa_asm_out_constructor (rtx symbol, int priority)
8545 if (!function_label_operand (symbol, VOIDmode))
8546 pa_encode_label (symbol);
8548 #ifdef CTORS_SECTION_ASM_OP
8549 default_ctor_section_asm_out_constructor (symbol, priority);
8551 # ifdef TARGET_ASM_NAMED_SECTION
8552 default_named_section_asm_out_constructor (symbol, priority);
8554 default_stabs_asm_out_constructor (symbol, priority);
8560 pa_asm_out_destructor (rtx symbol, int priority)
8562 if (!function_label_operand (symbol, VOIDmode))
8563 pa_encode_label (symbol);
8565 #ifdef DTORS_SECTION_ASM_OP
8566 default_dtor_section_asm_out_destructor (symbol, priority);
8568 # ifdef TARGET_ASM_NAMED_SECTION
8569 default_named_section_asm_out_destructor (symbol, priority);
8571 default_stabs_asm_out_destructor (symbol, priority);
8577 /* This function places uninitialized global data in the bss section.
8578 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8579 function on the SOM port to prevent uninitialized global data from
8580 being placed in the data section. */
8583 pa_asm_output_aligned_bss (FILE *stream,
8585 unsigned HOST_WIDE_INT size,
8588 switch_to_section (bss_section);
8589 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8591 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8592 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8595 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8596 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8599 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8600 ASM_OUTPUT_LABEL (stream, name);
8601 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8604 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8605 that doesn't allow the alignment of global common storage to be directly
8606 specified. The SOM linker aligns common storage based on the rounded
8607 value of the NUM_BYTES parameter in the .comm directive. It's not
8608 possible to use the .align directive as it doesn't affect the alignment
8609 of the label associated with a .comm directive. */
8612 pa_asm_output_aligned_common (FILE *stream,
8614 unsigned HOST_WIDE_INT size,
8617 unsigned int max_common_align;
8619 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8620 if (align > max_common_align)
8622 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8623 "for global common data. Using %u",
8624 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8625 align = max_common_align;
8628 switch_to_section (bss_section);
8630 assemble_name (stream, name);
8631 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8632 MAX (size, align / BITS_PER_UNIT));
8635 /* We can't use .comm for local common storage as the SOM linker effectively
8636 treats the symbol as universal and uses the same storage for local symbols
8637 with the same name in different object files. The .block directive
8638 reserves an uninitialized block of storage. However, it's not common
8639 storage. Fortunately, GCC never requests common storage with the same
8640 name in any given translation unit. */
8643 pa_asm_output_aligned_local (FILE *stream,
8645 unsigned HOST_WIDE_INT size,
8648 switch_to_section (bss_section);
8649 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8652 fprintf (stream, "%s", LOCAL_ASM_OP);
8653 assemble_name (stream, name);
8654 fprintf (stream, "\n");
8657 ASM_OUTPUT_LABEL (stream, name);
8658 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8661 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8662 use in fmpysub instructions. */
8664 pa_fmpysuboperands (rtx *operands)
8666 enum machine_mode mode = GET_MODE (operands[0]);
8668 /* Must be a floating point mode. */
8669 if (mode != SFmode && mode != DFmode)
8672 /* All modes must be the same. */
8673 if (! (mode == GET_MODE (operands[1])
8674 && mode == GET_MODE (operands[2])
8675 && mode == GET_MODE (operands[3])
8676 && mode == GET_MODE (operands[4])
8677 && mode == GET_MODE (operands[5])))
8680 /* All operands must be registers. */
8681 if (! (GET_CODE (operands[1]) == REG
8682 && GET_CODE (operands[2]) == REG
8683 && GET_CODE (operands[3]) == REG
8684 && GET_CODE (operands[4]) == REG
8685 && GET_CODE (operands[5]) == REG))
8688 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8689 operation, so operands[4] must be the same as operand[3]. */
8690 if (! rtx_equal_p (operands[3], operands[4]))
8693 /* multiply cannot feed into subtraction. */
8694 if (rtx_equal_p (operands[5], operands[0]))
8697 /* Inout operand of sub cannot conflict with any operands from multiply. */
8698 if (rtx_equal_p (operands[3], operands[0])
8699 || rtx_equal_p (operands[3], operands[1])
8700 || rtx_equal_p (operands[3], operands[2]))
8703 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8705 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8706 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8707 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8708 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8709 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8710 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8713 /* Passed. Operands are suitable for fmpysub. */
8717 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8718 constants for shadd instructions. */
8720 pa_shadd_constant_p (int val)
8722 if (val == 2 || val == 4 || val == 8)
8728 /* Return TRUE if INSN branches forward. */
8731 forward_branch_p (rtx insn)
8733 rtx lab = JUMP_LABEL (insn);
8735 /* The INSN must have a jump label. */
8736 gcc_assert (lab != NULL_RTX);
8738 if (INSN_ADDRESSES_SET_P ())
8739 return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn));
8746 insn = NEXT_INSN (insn);
8752 /* Return 1 if INSN is in the delay slot of a call instruction. */
8754 pa_jump_in_call_delay (rtx insn)
8757 if (GET_CODE (insn) != JUMP_INSN)
8760 if (PREV_INSN (insn)
8761 && PREV_INSN (PREV_INSN (insn))
8762 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8764 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8766 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8767 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8774 /* Output an unconditional move and branch insn. */
8777 pa_output_parallel_movb (rtx *operands, rtx insn)
8779 int length = get_attr_length (insn);
8781 /* These are the cases in which we win. */
8783 return "mov%I1b,tr %1,%0,%2";
8785 /* None of the following cases win, but they don't lose either. */
8788 if (dbr_sequence_length () == 0)
8790 /* Nothing in the delay slot, fake it by putting the combined
8791 insn (the copy or add) in the delay slot of a bl. */
8792 if (GET_CODE (operands[1]) == CONST_INT)
8793 return "b %2\n\tldi %1,%0";
8795 return "b %2\n\tcopy %1,%0";
8799 /* Something in the delay slot, but we've got a long branch. */
8800 if (GET_CODE (operands[1]) == CONST_INT)
8801 return "ldi %1,%0\n\tb %2";
8803 return "copy %1,%0\n\tb %2";
8807 if (GET_CODE (operands[1]) == CONST_INT)
8808 output_asm_insn ("ldi %1,%0", operands);
8810 output_asm_insn ("copy %1,%0", operands);
8811 return pa_output_lbranch (operands[2], insn, 1);
8814 /* Output an unconditional add and branch insn. */
8817 pa_output_parallel_addb (rtx *operands, rtx insn)
8819 int length = get_attr_length (insn);
8821 /* To make life easy we want operand0 to be the shared input/output
8822 operand and operand1 to be the readonly operand. */
8823 if (operands[0] == operands[1])
8824 operands[1] = operands[2];
8826 /* These are the cases in which we win. */
8828 return "add%I1b,tr %1,%0,%3";
8830 /* None of the following cases win, but they don't lose either. */
8833 if (dbr_sequence_length () == 0)
8834 /* Nothing in the delay slot, fake it by putting the combined
8835 insn (the copy or add) in the delay slot of a bl. */
8836 return "b %3\n\tadd%I1 %1,%0,%0";
8838 /* Something in the delay slot, but we've got a long branch. */
8839 return "add%I1 %1,%0,%0\n\tb %3";
8842 output_asm_insn ("add%I1 %1,%0,%0", operands);
8843 return pa_output_lbranch (operands[3], insn, 1);
8846 /* Return nonzero if INSN (a jump insn) immediately follows a call
8847 to a named function. This is used to avoid filling the delay slot
8848 of the jump since it can usually be eliminated by modifying RP in
8849 the delay slot of the call. */
8852 pa_following_call (rtx insn)
8854 if (! TARGET_JUMP_IN_DELAY)
8857 /* Find the previous real insn, skipping NOTEs. */
8858 insn = PREV_INSN (insn);
8859 while (insn && GET_CODE (insn) == NOTE)
8860 insn = PREV_INSN (insn);
8862 /* Check for CALL_INSNs and millicode calls. */
8864 && ((GET_CODE (insn) == CALL_INSN
8865 && get_attr_type (insn) != TYPE_DYNCALL)
8866 || (GET_CODE (insn) == INSN
8867 && GET_CODE (PATTERN (insn)) != SEQUENCE
8868 && GET_CODE (PATTERN (insn)) != USE
8869 && GET_CODE (PATTERN (insn)) != CLOBBER
8870 && get_attr_type (insn) == TYPE_MILLI)))
8876 /* We use this hook to perform a PA specific optimization which is difficult
8877 to do in earlier passes.
8879 We want the delay slots of branches within jump tables to be filled.
8880 None of the compiler passes at the moment even has the notion that a
8881 PA jump table doesn't contain addresses, but instead contains actual
8884 Because we actually jump into the table, the addresses of each entry
8885 must stay constant in relation to the beginning of the table (which
8886 itself must stay constant relative to the instruction to jump into
8887 it). I don't believe we can guarantee earlier passes of the compiler
8888 will adhere to those rules.
8890 So, late in the compilation process we find all the jump tables, and
8891 expand them into real code -- e.g. each entry in the jump table vector
8892 will get an appropriate label followed by a jump to the final target.
8894 Reorg and the final jump pass can then optimize these branches and
8895 fill their delay slots. We end up with smaller, more efficient code.
8897 The jump instructions within the table are special; we must be able
8898 to identify them during assembly output (if the jumps don't get filled
8899 we need to emit a nop rather than nullifying the delay slot)). We
8900 identify jumps in switch tables by using insns with the attribute
8901 type TYPE_BTABLE_BRANCH.
8903 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8904 insns. This serves two purposes, first it prevents jump.c from
8905 noticing that the last N entries in the table jump to the instruction
8906 immediately after the table and deleting the jumps. Second, those
8907 insns mark where we should emit .begin_brtab and .end_brtab directives
8908 when using GAS (allows for better link time optimizations). */
8915 remove_useless_addtr_insns (1);
8917 if (pa_cpu < PROCESSOR_8000)
8918 pa_combine_instructions ();
8921 /* This is fairly cheap, so always run it if optimizing. */
8922 if (optimize > 0 && !TARGET_BIG_SWITCH)
8924 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8925 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8927 rtx pattern, tmp, location, label;
8928 unsigned int length, i;
8930 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8931 if (GET_CODE (insn) != JUMP_INSN
8932 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8933 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8936 /* Emit marker for the beginning of the branch table. */
8937 emit_insn_before (gen_begin_brtab (), insn);
8939 pattern = PATTERN (insn);
8940 location = PREV_INSN (insn);
8941 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8943 for (i = 0; i < length; i++)
8945 /* Emit a label before each jump to keep jump.c from
8946 removing this code. */
8947 tmp = gen_label_rtx ();
8948 LABEL_NUSES (tmp) = 1;
8949 emit_label_after (tmp, location);
8950 location = NEXT_INSN (location);
8952 if (GET_CODE (pattern) == ADDR_VEC)
8953 label = XEXP (XVECEXP (pattern, 0, i), 0);
8955 label = XEXP (XVECEXP (pattern, 1, i), 0);
8957 tmp = gen_short_jump (label);
8959 /* Emit the jump itself. */
8960 tmp = emit_jump_insn_after (tmp, location);
8961 JUMP_LABEL (tmp) = label;
8962 LABEL_NUSES (label)++;
8963 location = NEXT_INSN (location);
8965 /* Emit a BARRIER after the jump. */
8966 emit_barrier_after (location);
8967 location = NEXT_INSN (location);
8970 /* Emit marker for the end of the branch table. */
8971 emit_insn_before (gen_end_brtab (), location);
8972 location = NEXT_INSN (location);
8973 emit_barrier_after (location);
8975 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8981 /* Still need brtab marker insns. FIXME: the presence of these
8982 markers disables output of the branch table to readonly memory,
8983 and any alignment directives that might be needed. Possibly,
8984 the begin_brtab insn should be output before the label for the
8985 table. This doesn't matter at the moment since the tables are
8986 always output in the text section. */
8987 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8989 /* Find an ADDR_VEC insn. */
8990 if (GET_CODE (insn) != JUMP_INSN
8991 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8992 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8995 /* Now generate markers for the beginning and end of the
8997 emit_insn_before (gen_begin_brtab (), insn);
8998 emit_insn_after (gen_end_brtab (), insn);
9003 /* The PA has a number of odd instructions which can perform multiple
9004 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
9005 it may be profitable to combine two instructions into one instruction
9006 with two outputs. It's not profitable PA2.0 machines because the
9007 two outputs would take two slots in the reorder buffers.
9009 This routine finds instructions which can be combined and combines
9010 them. We only support some of the potential combinations, and we
9011 only try common ways to find suitable instructions.
9013 * addb can add two registers or a register and a small integer
9014 and jump to a nearby (+-8k) location. Normally the jump to the
9015 nearby location is conditional on the result of the add, but by
9016 using the "true" condition we can make the jump unconditional.
9017 Thus addb can perform two independent operations in one insn.
9019 * movb is similar to addb in that it can perform a reg->reg
9020 or small immediate->reg copy and jump to a nearby (+-8k location).
9022 * fmpyadd and fmpysub can perform a FP multiply and either an
9023 FP add or FP sub if the operands of the multiply and add/sub are
9024 independent (there are other minor restrictions). Note both
9025 the fmpy and fadd/fsub can in theory move to better spots according
9026 to data dependencies, but for now we require the fmpy stay at a
9029 * Many of the memory operations can perform pre & post updates
9030 of index registers. GCC's pre/post increment/decrement addressing
9031 is far too simple to take advantage of all the possibilities. This
9032 pass may not be suitable since those insns may not be independent.
9034 * comclr can compare two ints or an int and a register, nullify
9035 the following instruction and zero some other register. This
9036 is more difficult to use as it's harder to find an insn which
9037 will generate a comclr than finding something like an unconditional
9038 branch. (conditional moves & long branches create comclr insns).
9040 * Most arithmetic operations can conditionally skip the next
9041 instruction. They can be viewed as "perform this operation
9042 and conditionally jump to this nearby location" (where nearby
9043 is an insns away). These are difficult to use due to the
9044 branch length restrictions. */
9047 pa_combine_instructions (void)
9049 rtx anchor, new_rtx;
9051 /* This can get expensive since the basic algorithm is on the
9052 order of O(n^2) (or worse). Only do it for -O2 or higher
9053 levels of optimization. */
9057 /* Walk down the list of insns looking for "anchor" insns which
9058 may be combined with "floating" insns. As the name implies,
9059 "anchor" instructions don't move, while "floating" insns may
9061 new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
9062 new_rtx = make_insn_raw (new_rtx);
9064 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
9066 enum attr_pa_combine_type anchor_attr;
9067 enum attr_pa_combine_type floater_attr;
9069 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9070 Also ignore any special USE insns. */
9071 if ((GET_CODE (anchor) != INSN
9072 && GET_CODE (anchor) != JUMP_INSN
9073 && GET_CODE (anchor) != CALL_INSN)
9074 || GET_CODE (PATTERN (anchor)) == USE
9075 || GET_CODE (PATTERN (anchor)) == CLOBBER
9076 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
9077 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
9080 anchor_attr = get_attr_pa_combine_type (anchor);
9081 /* See if anchor is an insn suitable for combination. */
9082 if (anchor_attr == PA_COMBINE_TYPE_FMPY
9083 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
9084 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9085 && ! forward_branch_p (anchor)))
9089 for (floater = PREV_INSN (anchor);
9091 floater = PREV_INSN (floater))
9093 if (GET_CODE (floater) == NOTE
9094 || (GET_CODE (floater) == INSN
9095 && (GET_CODE (PATTERN (floater)) == USE
9096 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9099 /* Anything except a regular INSN will stop our search. */
9100 if (GET_CODE (floater) != INSN
9101 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9102 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9108 /* See if FLOATER is suitable for combination with the
9110 floater_attr = get_attr_pa_combine_type (floater);
9111 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9112 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9113 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9114 && floater_attr == PA_COMBINE_TYPE_FMPY))
9116 /* If ANCHOR and FLOATER can be combined, then we're
9117 done with this pass. */
9118 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9119 SET_DEST (PATTERN (floater)),
9120 XEXP (SET_SRC (PATTERN (floater)), 0),
9121 XEXP (SET_SRC (PATTERN (floater)), 1)))
9125 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9126 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
9128 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
9130 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9131 SET_DEST (PATTERN (floater)),
9132 XEXP (SET_SRC (PATTERN (floater)), 0),
9133 XEXP (SET_SRC (PATTERN (floater)), 1)))
9138 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9139 SET_DEST (PATTERN (floater)),
9140 SET_SRC (PATTERN (floater)),
9141 SET_SRC (PATTERN (floater))))
9147 /* If we didn't find anything on the backwards scan try forwards. */
9149 && (anchor_attr == PA_COMBINE_TYPE_FMPY
9150 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
9152 for (floater = anchor; floater; floater = NEXT_INSN (floater))
9154 if (GET_CODE (floater) == NOTE
9155 || (GET_CODE (floater) == INSN
9156 && (GET_CODE (PATTERN (floater)) == USE
9157 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9161 /* Anything except a regular INSN will stop our search. */
9162 if (GET_CODE (floater) != INSN
9163 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9164 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9170 /* See if FLOATER is suitable for combination with the
9172 floater_attr = get_attr_pa_combine_type (floater);
9173 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9174 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9175 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9176 && floater_attr == PA_COMBINE_TYPE_FMPY))
9178 /* If ANCHOR and FLOATER can be combined, then we're
9179 done with this pass. */
9180 if (pa_can_combine_p (new_rtx, anchor, floater, 1,
9181 SET_DEST (PATTERN (floater)),
9182 XEXP (SET_SRC (PATTERN (floater)),
9184 XEXP (SET_SRC (PATTERN (floater)),
9191 /* FLOATER will be nonzero if we found a suitable floating
9192 insn for combination with ANCHOR. */
9194 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9195 || anchor_attr == PA_COMBINE_TYPE_FMPY))
9197 /* Emit the new instruction and delete the old anchor. */
9198 emit_insn_before (gen_rtx_PARALLEL
9200 gen_rtvec (2, PATTERN (anchor),
9201 PATTERN (floater))),
9204 SET_INSN_DELETED (anchor);
9206 /* Emit a special USE insn for FLOATER, then delete
9207 the floating insn. */
9208 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9209 delete_insn (floater);
9214 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9217 /* Emit the new_jump instruction and delete the old anchor. */
9219 = emit_jump_insn_before (gen_rtx_PARALLEL
9221 gen_rtvec (2, PATTERN (anchor),
9222 PATTERN (floater))),
9225 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9226 SET_INSN_DELETED (anchor);
9228 /* Emit a special USE insn for FLOATER, then delete
9229 the floating insn. */
9230 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9231 delete_insn (floater);
9239 pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
9242 int insn_code_number;
9245 /* Create a PARALLEL with the patterns of ANCHOR and
9246 FLOATER, try to recognize it, then test constraints
9247 for the resulting pattern.
9249 If the pattern doesn't match or the constraints
9250 aren't met keep searching for a suitable floater
9252 XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
9253 XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
9254 INSN_CODE (new_rtx) = -1;
9255 insn_code_number = recog_memoized (new_rtx);
9256 if (insn_code_number < 0
9257 || (extract_insn (new_rtx), ! constrain_operands (1)))
9271 /* There's up to three operands to consider. One
9272 output and two inputs.
9274 The output must not be used between FLOATER & ANCHOR
9275 exclusive. The inputs must not be set between
9276 FLOATER and ANCHOR exclusive. */
9278 if (reg_used_between_p (dest, start, end))
9281 if (reg_set_between_p (src1, start, end))
9284 if (reg_set_between_p (src2, start, end))
9287 /* If we get here, then everything is good. */
9291 /* Return nonzero if references for INSN are delayed.
9293 Millicode insns are actually function calls with some special
9294 constraints on arguments and register usage.
9296 Millicode calls always expect their arguments in the integer argument
9297 registers, and always return their result in %r29 (ret1). They
9298 are expected to clobber their arguments, %r1, %r29, and the return
9299 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9301 This function tells reorg that the references to arguments and
9302 millicode calls do not appear to happen until after the millicode call.
9303 This allows reorg to put insns which set the argument registers into the
9304 delay slot of the millicode call -- thus they act more like traditional
9307 Note we cannot consider side effects of the insn to be delayed because
9308 the branch and link insn will clobber the return pointer. If we happened
9309 to use the return pointer in the delay slot of the call, then we lose.
9311 get_attr_type will try to recognize the given insn, so make sure to
9312 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9315 pa_insn_refs_are_delayed (rtx insn)
9317 return ((GET_CODE (insn) == INSN
9318 && GET_CODE (PATTERN (insn)) != SEQUENCE
9319 && GET_CODE (PATTERN (insn)) != USE
9320 && GET_CODE (PATTERN (insn)) != CLOBBER
9321 && get_attr_type (insn) == TYPE_MILLI));
9324 /* Promote the return value, but not the arguments. */
9326 static enum machine_mode
9327 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
9328 enum machine_mode mode,
9329 int *punsignedp ATTRIBUTE_UNUSED,
9330 const_tree fntype ATTRIBUTE_UNUSED,
9333 if (for_return == 0)
9335 return promote_mode (type, mode, punsignedp);
9338 /* On the HP-PA the value is found in register(s) 28(-29), unless
9339 the mode is SF or DF. Then the value is returned in fr4 (32).
9341 This must perform the same promotions as PROMOTE_MODE, else promoting
9342 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9344 Small structures must be returned in a PARALLEL on PA64 in order
9345 to match the HP Compiler ABI. */
9348 pa_function_value (const_tree valtype,
9349 const_tree func ATTRIBUTE_UNUSED,
9350 bool outgoing ATTRIBUTE_UNUSED)
9352 enum machine_mode valmode;
9354 if (AGGREGATE_TYPE_P (valtype)
9355 || TREE_CODE (valtype) == COMPLEX_TYPE
9356 || TREE_CODE (valtype) == VECTOR_TYPE)
9360 /* Aggregates with a size less than or equal to 128 bits are
9361 returned in GR 28(-29). They are left justified. The pad
9362 bits are undefined. Larger aggregates are returned in
9366 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9368 for (i = 0; i < ub; i++)
9370 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9371 gen_rtx_REG (DImode, 28 + i),
9376 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9378 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9380 /* Aggregates 5 to 8 bytes in size are returned in general
9381 registers r28-r29 in the same manner as other non
9382 floating-point objects. The data is right-justified and
9383 zero-extended to 64 bits. This is opposite to the normal
9384 justification used on big endian targets and requires
9385 special treatment. */
9386 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9387 gen_rtx_REG (DImode, 28), const0_rtx);
9388 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9392 if ((INTEGRAL_TYPE_P (valtype)
9393 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9394 || POINTER_TYPE_P (valtype))
9395 valmode = word_mode;
9397 valmode = TYPE_MODE (valtype);
9399 if (TREE_CODE (valtype) == REAL_TYPE
9400 && !AGGREGATE_TYPE_P (valtype)
9401 && TYPE_MODE (valtype) != TFmode
9402 && !TARGET_SOFT_FLOAT)
9403 return gen_rtx_REG (valmode, 32);
9405 return gen_rtx_REG (valmode, 28);
9408 /* Implement the TARGET_LIBCALL_VALUE hook. */
9411 pa_libcall_value (enum machine_mode mode,
9412 const_rtx fun ATTRIBUTE_UNUSED)
9414 if (! TARGET_SOFT_FLOAT
9415 && (mode == SFmode || mode == DFmode))
9416 return gen_rtx_REG (mode, 32);
9418 return gen_rtx_REG (mode, 28);
9421 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9424 pa_function_value_regno_p (const unsigned int regno)
9427 || (! TARGET_SOFT_FLOAT && regno == 32))
9433 /* Update the data in CUM to advance over an argument
9434 of mode MODE and data type TYPE.
9435 (TYPE is null for libcalls where that information may not be available.) */
9438 pa_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode,
9439 const_tree type, bool named ATTRIBUTE_UNUSED)
9441 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9442 int arg_size = FUNCTION_ARG_SIZE (mode, type);
9444 cum->nargs_prototype--;
9445 cum->words += (arg_size
9446 + ((cum->words & 01)
9447 && type != NULL_TREE
9451 /* Return the location of a parameter that is passed in a register or NULL
9452 if the parameter has any component that is passed in memory.
9454 This is new code and will be pushed to into the net sources after
9457 ??? We might want to restructure this so that it looks more like other
9460 pa_function_arg (cumulative_args_t cum_v, enum machine_mode mode,
9461 const_tree type, bool named ATTRIBUTE_UNUSED)
9463 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9464 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9471 if (mode == VOIDmode)
9474 arg_size = FUNCTION_ARG_SIZE (mode, type);
9476 /* If this arg would be passed partially or totally on the stack, then
9477 this routine should return zero. pa_arg_partial_bytes will
9478 handle arguments which are split between regs and stack slots if
9479 the ABI mandates split arguments. */
9482 /* The 32-bit ABI does not split arguments. */
9483 if (cum->words + arg_size > max_arg_words)
9489 alignment = cum->words & 1;
9490 if (cum->words + alignment >= max_arg_words)
9494 /* The 32bit ABIs and the 64bit ABIs are rather different,
9495 particularly in their handling of FP registers. We might
9496 be able to cleverly share code between them, but I'm not
9497 going to bother in the hope that splitting them up results
9498 in code that is more easily understood. */
9502 /* Advance the base registers to their current locations.
9504 Remember, gprs grow towards smaller register numbers while
9505 fprs grow to higher register numbers. Also remember that
9506 although FP regs are 32-bit addressable, we pretend that
9507 the registers are 64-bits wide. */
9508 gpr_reg_base = 26 - cum->words;
9509 fpr_reg_base = 32 + cum->words;
9511 /* Arguments wider than one word and small aggregates need special
9515 || (type && (AGGREGATE_TYPE_P (type)
9516 || TREE_CODE (type) == COMPLEX_TYPE
9517 || TREE_CODE (type) == VECTOR_TYPE)))
9519 /* Double-extended precision (80-bit), quad-precision (128-bit)
9520 and aggregates including complex numbers are aligned on
9521 128-bit boundaries. The first eight 64-bit argument slots
9522 are associated one-to-one, with general registers r26
9523 through r19, and also with floating-point registers fr4
9524 through fr11. Arguments larger than one word are always
9525 passed in general registers.
9527 Using a PARALLEL with a word mode register results in left
9528 justified data on a big-endian target. */
9531 int i, offset = 0, ub = arg_size;
9533 /* Align the base register. */
9534 gpr_reg_base -= alignment;
9536 ub = MIN (ub, max_arg_words - cum->words - alignment);
9537 for (i = 0; i < ub; i++)
9539 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9540 gen_rtx_REG (DImode, gpr_reg_base),
9546 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9551 /* If the argument is larger than a word, then we know precisely
9552 which registers we must use. */
9566 /* Structures 5 to 8 bytes in size are passed in the general
9567 registers in the same manner as other non floating-point
9568 objects. The data is right-justified and zero-extended
9569 to 64 bits. This is opposite to the normal justification
9570 used on big endian targets and requires special treatment.
9571 We now define BLOCK_REG_PADDING to pad these objects.
9572 Aggregates, complex and vector types are passed in the same
9573 manner as structures. */
9575 || (type && (AGGREGATE_TYPE_P (type)
9576 || TREE_CODE (type) == COMPLEX_TYPE
9577 || TREE_CODE (type) == VECTOR_TYPE)))
9579 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9580 gen_rtx_REG (DImode, gpr_reg_base),
9582 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9587 /* We have a single word (32 bits). A simple computation
9588 will get us the register #s we need. */
9589 gpr_reg_base = 26 - cum->words;
9590 fpr_reg_base = 32 + 2 * cum->words;
9594 /* Determine if the argument needs to be passed in both general and
9595 floating point registers. */
9596 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9597 /* If we are doing soft-float with portable runtime, then there
9598 is no need to worry about FP regs. */
9599 && !TARGET_SOFT_FLOAT
9600 /* The parameter must be some kind of scalar float, else we just
9601 pass it in integer registers. */
9602 && GET_MODE_CLASS (mode) == MODE_FLOAT
9603 /* The target function must not have a prototype. */
9604 && cum->nargs_prototype <= 0
9605 /* libcalls do not need to pass items in both FP and general
9607 && type != NULL_TREE
9608 /* All this hair applies to "outgoing" args only. This includes
9609 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9611 /* Also pass outgoing floating arguments in both registers in indirect
9612 calls with the 32 bit ABI and the HP assembler since there is no
9613 way to the specify argument locations in static functions. */
9618 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9624 gen_rtx_EXPR_LIST (VOIDmode,
9625 gen_rtx_REG (mode, fpr_reg_base),
9627 gen_rtx_EXPR_LIST (VOIDmode,
9628 gen_rtx_REG (mode, gpr_reg_base),
9633 /* See if we should pass this parameter in a general register. */
9634 if (TARGET_SOFT_FLOAT
9635 /* Indirect calls in the normal 32bit ABI require all arguments
9636 to be passed in general registers. */
9637 || (!TARGET_PORTABLE_RUNTIME
9641 /* If the parameter is not a scalar floating-point parameter,
9642 then it belongs in GPRs. */
9643 || GET_MODE_CLASS (mode) != MODE_FLOAT
9644 /* Structure with single SFmode field belongs in GPR. */
9645 || (type && AGGREGATE_TYPE_P (type)))
9646 retval = gen_rtx_REG (mode, gpr_reg_base);
9648 retval = gen_rtx_REG (mode, fpr_reg_base);
9653 /* Arguments larger than one word are double word aligned. */
9656 pa_function_arg_boundary (enum machine_mode mode, const_tree type)
9658 bool singleword = (type
9659 ? (integer_zerop (TYPE_SIZE (type))
9660 || !TREE_CONSTANT (TYPE_SIZE (type))
9661 || int_size_in_bytes (type) <= UNITS_PER_WORD)
9662 : GET_MODE_SIZE (mode) <= UNITS_PER_WORD);
9664 return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY;
9667 /* If this arg would be passed totally in registers or totally on the stack,
9668 then this routine should return zero. */
9671 pa_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode,
9672 tree type, bool named ATTRIBUTE_UNUSED)
9674 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v);
9675 unsigned int max_arg_words = 8;
9676 unsigned int offset = 0;
9681 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9684 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9685 /* Arg fits fully into registers. */
9687 else if (cum->words + offset >= max_arg_words)
9688 /* Arg fully on the stack. */
9692 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9696 /* A get_unnamed_section callback for switching to the text section.
9698 This function is only used with SOM. Because we don't support
9699 named subspaces, we can only create a new subspace or switch back
9700 to the default text subspace. */
9703 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9705 gcc_assert (TARGET_SOM);
9708 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9710 /* We only want to emit a .nsubspa directive once at the
9711 start of the function. */
9712 cfun->machine->in_nsubspa = 1;
9714 /* Create a new subspace for the text. This provides
9715 better stub placement and one-only functions. */
9717 && DECL_ONE_ONLY (cfun->decl)
9718 && !DECL_WEAK (cfun->decl))
9720 output_section_asm_op ("\t.SPACE $TEXT$\n"
9721 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9722 "ACCESS=44,SORT=24,COMDAT");
9728 /* There isn't a current function or the body of the current
9729 function has been completed. So, we are changing to the
9730 text section to output debugging information. Thus, we
9731 need to forget that we are in the text section so that
9732 varasm.c will call us when text_section is selected again. */
9733 gcc_assert (!cfun || !cfun->machine
9734 || cfun->machine->in_nsubspa == 2);
9737 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9740 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9743 /* A get_unnamed_section callback for switching to comdat data
9744 sections. This function is only used with SOM. */
9747 som_output_comdat_data_section_asm_op (const void *data)
9750 output_section_asm_op (data);
9753 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9756 pa_som_asm_init_sections (void)
9759 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9761 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9762 is not being generated. */
9763 som_readonly_data_section
9764 = get_unnamed_section (0, output_section_asm_op,
9765 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9767 /* When secondary definitions are not supported, SOM makes readonly
9768 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9770 som_one_only_readonly_data_section
9771 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9773 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9774 "ACCESS=0x2c,SORT=16,COMDAT");
9777 /* When secondary definitions are not supported, SOM makes data one-only
9778 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9779 som_one_only_data_section
9780 = get_unnamed_section (SECTION_WRITE,
9781 som_output_comdat_data_section_asm_op,
9782 "\t.SPACE $PRIVATE$\n"
9783 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9784 "ACCESS=31,SORT=24,COMDAT");
9787 som_tm_clone_table_section
9788 = get_unnamed_section (0, output_section_asm_op,
9789 "\t.SPACE $PRIVATE$\n\t.SUBSPA $TM_CLONE_TABLE$");
9791 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9792 which reference data within the $TEXT$ space (for example constant
9793 strings in the $LIT$ subspace).
9795 The assemblers (GAS and HP as) both have problems with handling
9796 the difference of two symbols which is the other correct way to
9797 reference constant data during PIC code generation.
9799 So, there's no way to reference constant data which is in the
9800 $TEXT$ space during PIC generation. Instead place all constant
9801 data into the $PRIVATE$ subspace (this reduces sharing, but it
9802 works correctly). */
9803 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9805 /* We must not have a reference to an external symbol defined in a
9806 shared library in a readonly section, else the SOM linker will
9809 So, we force exception information into the data section. */
9810 exception_section = data_section;
9813 /* Implement TARGET_ASM_TM_CLONE_TABLE_SECTION. */
9816 pa_som_tm_clone_table_section (void)
9818 return som_tm_clone_table_section;
9821 /* On hpux10, the linker will give an error if we have a reference
9822 in the read-only data section to a symbol defined in a shared
9823 library. Therefore, expressions that might require a reloc can
9824 not be placed in the read-only data section. */
9827 pa_select_section (tree exp, int reloc,
9828 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9830 if (TREE_CODE (exp) == VAR_DECL
9831 && TREE_READONLY (exp)
9832 && !TREE_THIS_VOLATILE (exp)
9833 && DECL_INITIAL (exp)
9834 && (DECL_INITIAL (exp) == error_mark_node
9835 || TREE_CONSTANT (DECL_INITIAL (exp)))
9839 && DECL_ONE_ONLY (exp)
9840 && !DECL_WEAK (exp))
9841 return som_one_only_readonly_data_section;
9843 return readonly_data_section;
9845 else if (CONSTANT_CLASS_P (exp) && !reloc)
9846 return readonly_data_section;
9848 && TREE_CODE (exp) == VAR_DECL
9849 && DECL_ONE_ONLY (exp)
9850 && !DECL_WEAK (exp))
9851 return som_one_only_data_section;
9853 return data_section;
9857 pa_globalize_label (FILE *stream, const char *name)
9859 /* We only handle DATA objects here, functions are globalized in
9860 ASM_DECLARE_FUNCTION_NAME. */
9861 if (! FUNCTION_NAME_P (name))
9863 fputs ("\t.EXPORT ", stream);
9864 assemble_name (stream, name);
9865 fputs (",DATA\n", stream);
9869 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9872 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9873 int incoming ATTRIBUTE_UNUSED)
9875 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9878 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9881 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9883 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9884 PA64 ABI says that objects larger than 128 bits are returned in memory.
9885 Note, int_size_in_bytes can return -1 if the size of the object is
9886 variable or larger than the maximum value that can be expressed as
9887 a HOST_WIDE_INT. It can also return zero for an empty type. The
9888 simplest way to handle variable and empty types is to pass them in
9889 memory. This avoids problems in defining the boundaries of argument
9890 slots, allocating registers, etc. */
9891 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9892 || int_size_in_bytes (type) <= 0);
9895 /* Structure to hold declaration and name of external symbols that are
9896 emitted by GCC. We generate a vector of these symbols and output them
9897 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9898 This avoids putting out names that are never really used. */
9900 typedef struct GTY(()) extern_symbol
9906 /* Define gc'd vector type for extern_symbol. */
9907 DEF_VEC_O(extern_symbol);
9908 DEF_VEC_ALLOC_O(extern_symbol,gc);
9910 /* Vector of extern_symbol pointers. */
9911 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9913 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9914 /* Mark DECL (name NAME) as an external reference (assembler output
9915 file FILE). This saves the names to output at the end of the file
9916 if actually referenced. */
9919 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9921 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9923 gcc_assert (file == asm_out_file);
9928 /* Output text required at the end of an assembler file.
9929 This includes deferred plabels and .import directives for
9930 all external symbols that were actually referenced. */
9933 pa_hpux_file_end (void)
9938 if (!NO_DEFERRED_PROFILE_COUNTERS)
9939 output_deferred_profile_counters ();
9941 output_deferred_plabels ();
9943 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9945 tree decl = p->decl;
9947 if (!TREE_ASM_WRITTEN (decl)
9948 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9949 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9952 VEC_free (extern_symbol, gc, extern_symbols);
9956 /* Return true if a change from mode FROM to mode TO for a register
9957 in register class RCLASS is invalid. */
9960 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9961 enum reg_class rclass)
9966 /* Reject changes to/from complex and vector modes. */
9967 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9968 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9971 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9974 /* There is no way to load QImode or HImode values directly from
9975 memory. SImode loads to the FP registers are not zero extended.
9976 On the 64-bit target, this conflicts with the definition of
9977 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9978 with different sizes in the floating-point registers. */
9979 if (MAYBE_FP_REG_CLASS_P (rclass))
9982 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9983 in specific sets of registers. Thus, we cannot allow changing
9984 to a larger mode when it's larger than a word. */
9985 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9986 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9992 /* Returns TRUE if it is a good idea to tie two pseudo registers
9993 when one has mode MODE1 and one has mode MODE2.
9994 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9995 for any hard reg, then this must be FALSE for correct output.
9997 We should return FALSE for QImode and HImode because these modes
9998 are not ok in the floating-point registers. However, this prevents
9999 tieing these modes to SImode and DImode in the general registers.
10000 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
10001 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
10002 in the floating-point registers. */
10005 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
10007 /* Don't tie modes in different classes. */
10008 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))
10015 /* Length in units of the trampoline instruction code. */
10017 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
10020 /* Output assembler code for a block containing the constant parts
10021 of a trampoline, leaving space for the variable parts.\
10023 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10024 and then branches to the specified routine.
10026 This code template is copied from text segment to stack location
10027 and then patched with pa_trampoline_init to contain valid values,
10028 and then entered as a subroutine.
10030 It is best to keep this as small as possible to avoid having to
10031 flush multiple lines in the cache. */
10034 pa_asm_trampoline_template (FILE *f)
10038 fputs ("\tldw 36(%r22),%r21\n", f);
10039 fputs ("\tbb,>=,n %r21,30,.+16\n", f);
10040 if (ASSEMBLER_DIALECT == 0)
10041 fputs ("\tdepi 0,31,2,%r21\n", f);
10043 fputs ("\tdepwi 0,31,2,%r21\n", f);
10044 fputs ("\tldw 4(%r21),%r19\n", f);
10045 fputs ("\tldw 0(%r21),%r21\n", f);
10048 fputs ("\tbve (%r21)\n", f);
10049 fputs ("\tldw 40(%r22),%r29\n", f);
10050 fputs ("\t.word 0\n", f);
10051 fputs ("\t.word 0\n", f);
10055 fputs ("\tldsid (%r21),%r1\n", f);
10056 fputs ("\tmtsp %r1,%sr0\n", f);
10057 fputs ("\tbe 0(%sr0,%r21)\n", f);
10058 fputs ("\tldw 40(%r22),%r29\n", f);
10060 fputs ("\t.word 0\n", f);
10061 fputs ("\t.word 0\n", f);
10062 fputs ("\t.word 0\n", f);
10063 fputs ("\t.word 0\n", f);
10067 fputs ("\t.dword 0\n", f);
10068 fputs ("\t.dword 0\n", f);
10069 fputs ("\t.dword 0\n", f);
10070 fputs ("\t.dword 0\n", f);
10071 fputs ("\tmfia %r31\n", f);
10072 fputs ("\tldd 24(%r31),%r1\n", f);
10073 fputs ("\tldd 24(%r1),%r27\n", f);
10074 fputs ("\tldd 16(%r1),%r1\n", f);
10075 fputs ("\tbve (%r1)\n", f);
10076 fputs ("\tldd 32(%r31),%r31\n", f);
10077 fputs ("\t.dword 0 ; fptr\n", f);
10078 fputs ("\t.dword 0 ; static link\n", f);
10082 /* Emit RTL insns to initialize the variable parts of a trampoline.
10083 FNADDR is an RTX for the address of the function's pure code.
10084 CXT is an RTX for the static chain value for the function.
10086 Move the function address to the trampoline template at offset 36.
10087 Move the static chain value to trampoline template at offset 40.
10088 Move the trampoline address to trampoline template at offset 44.
10089 Move r19 to trampoline template at offset 48. The latter two
10090 words create a plabel for the indirect call to the trampoline.
10092 A similar sequence is used for the 64-bit port but the plabel is
10093 at the beginning of the trampoline.
10095 Finally, the cache entries for the trampoline code are flushed.
10096 This is necessary to ensure that the trampoline instruction sequence
10097 is written to memory prior to any attempts at prefetching the code
10101 pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
10103 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10104 rtx start_addr = gen_reg_rtx (Pmode);
10105 rtx end_addr = gen_reg_rtx (Pmode);
10106 rtx line_length = gen_reg_rtx (Pmode);
10109 emit_block_move (m_tramp, assemble_trampoline_template (),
10110 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
10111 r_tramp = force_reg (Pmode, XEXP (m_tramp, 0));
10115 tmp = adjust_address (m_tramp, Pmode, 36);
10116 emit_move_insn (tmp, fnaddr);
10117 tmp = adjust_address (m_tramp, Pmode, 40);
10118 emit_move_insn (tmp, chain_value);
10120 /* Create a fat pointer for the trampoline. */
10121 tmp = adjust_address (m_tramp, Pmode, 44);
10122 emit_move_insn (tmp, r_tramp);
10123 tmp = adjust_address (m_tramp, Pmode, 48);
10124 emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
10126 /* fdc and fic only use registers for the address to flush,
10127 they do not accept integer displacements. We align the
10128 start and end addresses to the beginning of their respective
10129 cache lines to minimize the number of lines flushed. */
10130 emit_insn (gen_andsi3 (start_addr, r_tramp,
10131 GEN_INT (-MIN_CACHELINE_SIZE)));
10132 tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1));
10133 emit_insn (gen_andsi3 (end_addr, tmp,
10134 GEN_INT (-MIN_CACHELINE_SIZE)));
10135 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10136 emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
10137 emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
10138 gen_reg_rtx (Pmode),
10139 gen_reg_rtx (Pmode)));
10143 tmp = adjust_address (m_tramp, Pmode, 56);
10144 emit_move_insn (tmp, fnaddr);
10145 tmp = adjust_address (m_tramp, Pmode, 64);
10146 emit_move_insn (tmp, chain_value);
10148 /* Create a fat pointer for the trampoline. */
10149 tmp = adjust_address (m_tramp, Pmode, 16);
10150 emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32)));
10151 tmp = adjust_address (m_tramp, Pmode, 24);
10152 emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
10154 /* fdc and fic only use registers for the address to flush,
10155 they do not accept integer displacements. We align the
10156 start and end addresses to the beginning of their respective
10157 cache lines to minimize the number of lines flushed. */
10158 tmp = force_reg (Pmode, plus_constant (r_tramp, 32));
10159 emit_insn (gen_anddi3 (start_addr, tmp,
10160 GEN_INT (-MIN_CACHELINE_SIZE)));
10161 tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));
10162 emit_insn (gen_anddi3 (end_addr, tmp,
10163 GEN_INT (-MIN_CACHELINE_SIZE)));
10164 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10165 emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
10166 emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
10167 gen_reg_rtx (Pmode),
10168 gen_reg_rtx (Pmode)));
10172 /* Perform any machine-specific adjustment in the address of the trampoline.
10173 ADDR contains the address that was passed to pa_trampoline_init.
10174 Adjust the trampoline address to point to the plabel at offset 44. */
10177 pa_trampoline_adjust_address (rtx addr)
10180 addr = memory_address (Pmode, plus_constant (addr, 46));
10185 pa_delegitimize_address (rtx orig_x)
10187 rtx x = delegitimize_mem_from_attrs (orig_x);
10189 if (GET_CODE (x) == LO_SUM
10190 && GET_CODE (XEXP (x, 1)) == UNSPEC
10191 && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R)
10192 return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0));
10197 pa_internal_arg_pointer (void)
10199 /* The argument pointer and the hard frame pointer are the same in
10200 the 32-bit runtime, so we don't need a copy. */
10202 return copy_to_reg (virtual_incoming_args_rtx);
10204 return virtual_incoming_args_rtx;
10207 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10208 Frame pointer elimination is automatically handled. */
10211 pa_can_eliminate (const int from, const int to)
10213 /* The argument cannot be eliminated in the 64-bit runtime. */
10214 if (TARGET_64BIT && from == ARG_POINTER_REGNUM)
10217 return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM
10218 ? ! frame_pointer_needed
10222 /* Define the offset between two registers, FROM to be eliminated and its
10223 replacement TO, at the start of a routine. */
10225 pa_initial_elimination_offset (int from, int to)
10227 HOST_WIDE_INT offset;
10229 if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
10230 && to == STACK_POINTER_REGNUM)
10231 offset = -pa_compute_frame_size (get_frame_size (), 0);
10232 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10235 gcc_unreachable ();
10241 pa_conditional_register_usage (void)
10245 if (!TARGET_64BIT && !TARGET_PA_11)
10247 for (i = 56; i <= FP_REG_LAST; i++)
10248 fixed_regs[i] = call_used_regs[i] = 1;
10249 for (i = 33; i < 56; i += 2)
10250 fixed_regs[i] = call_used_regs[i] = 1;
10252 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10254 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
10255 fixed_regs[i] = call_used_regs[i] = 1;
10258 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10261 /* Target hook for c_mode_for_suffix. */
10263 static enum machine_mode
10264 pa_c_mode_for_suffix (char suffix)
10266 if (HPUX_LONG_DOUBLE_LIBRARY)
10275 /* Target hook for function_section. */
10278 pa_function_section (tree decl, enum node_frequency freq,
10279 bool startup, bool exit)
10281 /* Put functions in text section if target doesn't have named sections. */
10282 if (!targetm_common.have_named_sections)
10283 return text_section;
10285 /* Force nested functions into the same section as the containing
10288 && DECL_SECTION_NAME (decl) == NULL_TREE
10289 && DECL_CONTEXT (decl) != NULL_TREE
10290 && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL
10291 && DECL_SECTION_NAME (DECL_CONTEXT (decl)) == NULL_TREE)
10292 return function_section (DECL_CONTEXT (decl));
10294 /* Otherwise, use the default function section. */
10295 return default_function_section (decl, freq, startup, exit);
10298 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
10300 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
10301 that need more than three instructions to load prior to reload. This
10302 limit is somewhat arbitrary. It takes three instructions to load a
10303 CONST_INT from memory but two are memory accesses. It may be better
10304 to increase the allowed range for CONST_INTS. We may also be able
10305 to handle CONST_DOUBLES. */
10308 pa_legitimate_constant_p (enum machine_mode mode, rtx x)
10310 if (GET_MODE_CLASS (mode) == MODE_FLOAT && x != CONST0_RTX (mode))
10313 if (!NEW_HP_ASSEMBLER && !TARGET_GAS && GET_CODE (x) == LABEL_REF)
10316 /* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
10317 legitimate constants. */
10318 if (PA_SYMBOL_REF_TLS_P (x))
10320 enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
10322 if (model == TLS_MODEL_GLOBAL_DYNAMIC || model == TLS_MODEL_LOCAL_DYNAMIC)
10326 if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)
10330 && HOST_BITS_PER_WIDE_INT > 32
10331 && GET_CODE (x) == CONST_INT
10332 && !reload_in_progress
10333 && !reload_completed
10334 && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x))
10335 && !pa_cint_ok_for_move (INTVAL (x)))
10338 if (function_label_operand (x, mode))
10344 /* Implement TARGET_SECTION_TYPE_FLAGS. */
10346 static unsigned int
10347 pa_section_type_flags (tree decl, const char *name, int reloc)
10349 unsigned int flags;
10351 flags = default_section_type_flags (decl, name, reloc);
10353 /* Function labels are placed in the constant pool. This can
10354 cause a section conflict if decls are put in ".data.rel.ro"
10355 or ".data.rel.ro.local" using the __attribute__ construct. */
10356 if (strcmp (name, ".data.rel.ro") == 0
10357 || strcmp (name, ".data.rel.ro.local") == 0)
10358 flags |= SECTION_WRITE | SECTION_RELRO;