1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
5 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
42 #include "diagnostic-core.h"
48 #include "target-def.h"
49 #include "langhooks.h"
53 /* Return nonzero if there is a bypass for the output of
54 OUT_INSN and the fp store IN_INSN. */
56 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
58 enum machine_mode store_mode;
59 enum machine_mode other_mode;
62 if (recog_memoized (in_insn) < 0
63 || (get_attr_type (in_insn) != TYPE_FPSTORE
64 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
65 || recog_memoized (out_insn) < 0)
68 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
70 set = single_set (out_insn);
74 other_mode = GET_MODE (SET_SRC (set));
76 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
80 #ifndef DO_FRAME_NOTES
81 #ifdef INCOMING_RETURN_ADDR_RTX
82 #define DO_FRAME_NOTES 1
84 #define DO_FRAME_NOTES 0
88 static void pa_option_override (void);
89 static void copy_reg_pointer (rtx, rtx);
90 static void fix_range (const char *);
91 static bool pa_handle_option (struct gcc_options *, struct gcc_options *,
92 const struct cl_decoded_option *, location_t);
93 static int hppa_register_move_cost (enum machine_mode mode, reg_class_t,
95 static int hppa_address_cost (rtx, bool);
96 static bool hppa_rtx_costs (rtx, int, int, int *, bool);
97 static inline rtx force_mode (enum machine_mode, rtx);
98 static void pa_reorg (void);
99 static void pa_combine_instructions (void);
100 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
101 static bool forward_branch_p (rtx);
102 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
103 static int compute_movmem_length (rtx);
104 static int compute_clrmem_length (rtx);
105 static bool pa_assemble_integer (rtx, unsigned int, int);
106 static void remove_useless_addtr_insns (int);
107 static void store_reg (int, HOST_WIDE_INT, int);
108 static void store_reg_modify (int, int, HOST_WIDE_INT);
109 static void load_reg (int, HOST_WIDE_INT, int);
110 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
111 static rtx pa_function_value (const_tree, const_tree, bool);
112 static rtx pa_libcall_value (enum machine_mode, const_rtx);
113 static bool pa_function_value_regno_p (const unsigned int);
114 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
115 static void update_total_code_bytes (unsigned int);
116 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
117 static int pa_adjust_cost (rtx, rtx, rtx, int);
118 static int pa_adjust_priority (rtx, int);
119 static int pa_issue_rate (void);
120 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
121 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
123 static void pa_encode_section_info (tree, rtx, int);
124 static const char *pa_strip_name_encoding (const char *);
125 static bool pa_function_ok_for_sibcall (tree, tree);
126 static void pa_globalize_label (FILE *, const char *)
128 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
129 HOST_WIDE_INT, tree);
130 #if !defined(USE_COLLECT2)
131 static void pa_asm_out_constructor (rtx, int);
132 static void pa_asm_out_destructor (rtx, int);
134 static void pa_init_builtins (void);
135 static rtx pa_expand_builtin (tree, rtx, rtx, enum machine_mode mode, int);
136 static rtx hppa_builtin_saveregs (void);
137 static void hppa_va_start (tree, rtx);
138 static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
139 static bool pa_scalar_mode_supported_p (enum machine_mode);
140 static bool pa_commutative_p (const_rtx x, int outer_code);
141 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
142 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
143 static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
144 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
145 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
146 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
147 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
148 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
149 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
150 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
151 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
152 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
153 static void output_deferred_plabels (void);
154 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
155 #ifdef ASM_OUTPUT_EXTERNAL_REAL
156 static void pa_hpux_file_end (void);
158 #if HPUX_LONG_DOUBLE_LIBRARY
159 static void pa_hpux_init_libfuncs (void);
161 static rtx pa_struct_value_rtx (tree, int);
162 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
164 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
166 static void pa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
168 static rtx pa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
170 static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree);
171 static struct machine_function * pa_init_machine_status (void);
172 static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
174 secondary_reload_info *);
175 static void pa_extra_live_on_entry (bitmap);
176 static enum machine_mode pa_promote_function_mode (const_tree,
177 enum machine_mode, int *,
180 static void pa_asm_trampoline_template (FILE *);
181 static void pa_trampoline_init (rtx, tree, rtx);
182 static rtx pa_trampoline_adjust_address (rtx);
183 static rtx pa_delegitimize_address (rtx);
184 static bool pa_print_operand_punct_valid_p (unsigned char);
185 static rtx pa_internal_arg_pointer (void);
186 static bool pa_can_eliminate (const int, const int);
187 static void pa_conditional_register_usage (void);
188 static enum machine_mode pa_c_mode_for_suffix (char);
189 static section *pa_function_section (tree, enum node_frequency, bool, bool);
190 static bool pa_cannot_force_const_mem (enum machine_mode, rtx);
191 static bool pa_legitimate_constant_p (enum machine_mode, rtx);
193 /* The following extra sections are only used for SOM. */
194 static GTY(()) section *som_readonly_data_section;
195 static GTY(()) section *som_one_only_readonly_data_section;
196 static GTY(()) section *som_one_only_data_section;
198 /* Counts for the number of callee-saved general and floating point
199 registers which were saved by the current function's prologue. */
200 static int gr_saved, fr_saved;
202 /* Boolean indicating whether the return pointer was saved by the
203 current function's prologue. */
204 static bool rp_saved;
206 static rtx find_addr_reg (rtx);
208 /* Keep track of the number of bytes we have output in the CODE subspace
209 during this compilation so we'll know when to emit inline long-calls. */
210 unsigned long total_code_bytes;
212 /* The last address of the previous function plus the number of bytes in
213 associated thunks that have been output. This is used to determine if
214 a thunk can use an IA-relative branch to reach its target function. */
215 static unsigned int last_address;
217 /* Variables to handle plabels that we discover are necessary at assembly
218 output time. They are output after the current function. */
219 struct GTY(()) deferred_plabel
224 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
226 static size_t n_deferred_plabels = 0;
228 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
229 static const struct default_options pa_option_optimization_table[] =
231 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
232 { OPT_LEVELS_NONE, 0, NULL, 0 }
236 /* Initialize the GCC target structure. */
238 #undef TARGET_OPTION_OVERRIDE
239 #define TARGET_OPTION_OVERRIDE pa_option_override
240 #undef TARGET_OPTION_OPTIMIZATION_TABLE
241 #define TARGET_OPTION_OPTIMIZATION_TABLE pa_option_optimization_table
243 #undef TARGET_ASM_ALIGNED_HI_OP
244 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
245 #undef TARGET_ASM_ALIGNED_SI_OP
246 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
247 #undef TARGET_ASM_ALIGNED_DI_OP
248 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
249 #undef TARGET_ASM_UNALIGNED_HI_OP
250 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
251 #undef TARGET_ASM_UNALIGNED_SI_OP
252 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
253 #undef TARGET_ASM_UNALIGNED_DI_OP
254 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
255 #undef TARGET_ASM_INTEGER
256 #define TARGET_ASM_INTEGER pa_assemble_integer
258 #undef TARGET_ASM_FUNCTION_PROLOGUE
259 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
260 #undef TARGET_ASM_FUNCTION_EPILOGUE
261 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
263 #undef TARGET_FUNCTION_VALUE
264 #define TARGET_FUNCTION_VALUE pa_function_value
265 #undef TARGET_LIBCALL_VALUE
266 #define TARGET_LIBCALL_VALUE pa_libcall_value
267 #undef TARGET_FUNCTION_VALUE_REGNO_P
268 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
270 #undef TARGET_LEGITIMIZE_ADDRESS
271 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
273 #undef TARGET_SCHED_ADJUST_COST
274 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
275 #undef TARGET_SCHED_ADJUST_PRIORITY
276 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
277 #undef TARGET_SCHED_ISSUE_RATE
278 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
280 #undef TARGET_ENCODE_SECTION_INFO
281 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
282 #undef TARGET_STRIP_NAME_ENCODING
283 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
285 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
286 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
288 #undef TARGET_COMMUTATIVE_P
289 #define TARGET_COMMUTATIVE_P pa_commutative_p
291 #undef TARGET_ASM_OUTPUT_MI_THUNK
292 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
293 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
294 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
296 #undef TARGET_ASM_FILE_END
297 #ifdef ASM_OUTPUT_EXTERNAL_REAL
298 #define TARGET_ASM_FILE_END pa_hpux_file_end
300 #define TARGET_ASM_FILE_END output_deferred_plabels
303 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
304 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
306 #if !defined(USE_COLLECT2)
307 #undef TARGET_ASM_CONSTRUCTOR
308 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
309 #undef TARGET_ASM_DESTRUCTOR
310 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
313 #undef TARGET_DEFAULT_TARGET_FLAGS
314 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
315 #undef TARGET_HANDLE_OPTION
316 #define TARGET_HANDLE_OPTION pa_handle_option
318 #undef TARGET_INIT_BUILTINS
319 #define TARGET_INIT_BUILTINS pa_init_builtins
321 #undef TARGET_EXPAND_BUILTIN
322 #define TARGET_EXPAND_BUILTIN pa_expand_builtin
324 #undef TARGET_REGISTER_MOVE_COST
325 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
326 #undef TARGET_RTX_COSTS
327 #define TARGET_RTX_COSTS hppa_rtx_costs
328 #undef TARGET_ADDRESS_COST
329 #define TARGET_ADDRESS_COST hppa_address_cost
331 #undef TARGET_MACHINE_DEPENDENT_REORG
332 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
334 #if HPUX_LONG_DOUBLE_LIBRARY
335 #undef TARGET_INIT_LIBFUNCS
336 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
339 #undef TARGET_PROMOTE_FUNCTION_MODE
340 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
341 #undef TARGET_PROMOTE_PROTOTYPES
342 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
344 #undef TARGET_STRUCT_VALUE_RTX
345 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
346 #undef TARGET_RETURN_IN_MEMORY
347 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
348 #undef TARGET_MUST_PASS_IN_STACK
349 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
350 #undef TARGET_PASS_BY_REFERENCE
351 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
352 #undef TARGET_CALLEE_COPIES
353 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
354 #undef TARGET_ARG_PARTIAL_BYTES
355 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
356 #undef TARGET_FUNCTION_ARG
357 #define TARGET_FUNCTION_ARG pa_function_arg
358 #undef TARGET_FUNCTION_ARG_ADVANCE
359 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
360 #undef TARGET_FUNCTION_ARG_BOUNDARY
361 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
363 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
364 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
365 #undef TARGET_EXPAND_BUILTIN_VA_START
366 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
367 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
368 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
370 #undef TARGET_SCALAR_MODE_SUPPORTED_P
371 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
373 #undef TARGET_CANNOT_FORCE_CONST_MEM
374 #define TARGET_CANNOT_FORCE_CONST_MEM pa_cannot_force_const_mem
376 #undef TARGET_SECONDARY_RELOAD
377 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
379 #undef TARGET_EXTRA_LIVE_ON_ENTRY
380 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
382 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
383 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
384 #undef TARGET_TRAMPOLINE_INIT
385 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
386 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
387 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
388 #undef TARGET_DELEGITIMIZE_ADDRESS
389 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
390 #undef TARGET_INTERNAL_ARG_POINTER
391 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
392 #undef TARGET_CAN_ELIMINATE
393 #define TARGET_CAN_ELIMINATE pa_can_eliminate
394 #undef TARGET_CONDITIONAL_REGISTER_USAGE
395 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
396 #undef TARGET_C_MODE_FOR_SUFFIX
397 #define TARGET_C_MODE_FOR_SUFFIX pa_c_mode_for_suffix
398 #undef TARGET_ASM_FUNCTION_SECTION
399 #define TARGET_ASM_FUNCTION_SECTION pa_function_section
401 #undef TARGET_LEGITIMATE_CONSTANT_P
402 #define TARGET_LEGITIMATE_CONSTANT_P pa_legitimate_constant_p
404 struct gcc_target targetm = TARGET_INITIALIZER;
406 /* Parse the -mfixed-range= option string. */
409 fix_range (const char *const_str)
412 char *str, *dash, *comma;
414 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
415 REG2 are either register names or register numbers. The effect
416 of this option is to mark the registers in the range from REG1 to
417 REG2 as ``fixed'' so they won't be used by the compiler. This is
418 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
420 i = strlen (const_str);
421 str = (char *) alloca (i + 1);
422 memcpy (str, const_str, i + 1);
426 dash = strchr (str, '-');
429 warning (0, "value of -mfixed-range must have form REG1-REG2");
434 comma = strchr (dash + 1, ',');
438 first = decode_reg_name (str);
441 warning (0, "unknown register name: %s", str);
445 last = decode_reg_name (dash + 1);
448 warning (0, "unknown register name: %s", dash + 1);
456 warning (0, "%s-%s is an empty range", str, dash + 1);
460 for (i = first; i <= last; ++i)
461 fixed_regs[i] = call_used_regs[i] = 1;
470 /* Check if all floating point registers have been fixed. */
471 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
476 target_flags |= MASK_DISABLE_FPREGS;
479 /* Implement TARGET_HANDLE_OPTION. */
482 pa_handle_option (struct gcc_options *opts,
483 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
484 const struct cl_decoded_option *decoded,
485 location_t loc ATTRIBUTE_UNUSED)
487 size_t code = decoded->opt_index;
492 case OPT_mpa_risc_1_0:
494 opts->x_target_flags &= ~(MASK_PA_11 | MASK_PA_20);
498 case OPT_mpa_risc_1_1:
500 opts->x_target_flags &= ~MASK_PA_20;
501 opts->x_target_flags |= MASK_PA_11;
504 case OPT_mpa_risc_2_0:
506 opts->x_target_flags |= MASK_PA_11 | MASK_PA_20;
514 /* Implement the TARGET_OPTION_OVERRIDE hook. */
517 pa_option_override (void)
520 cl_deferred_option *opt;
521 VEC(cl_deferred_option,heap) *vec
522 = (VEC(cl_deferred_option,heap) *) pa_deferred_options;
524 FOR_EACH_VEC_ELT (cl_deferred_option, vec, i, opt)
526 switch (opt->opt_index)
528 case OPT_mfixed_range_:
529 fix_range (opt->arg);
537 /* Unconditional branches in the delay slot are not compatible with dwarf2
538 call frame information. There is no benefit in using this optimization
539 on PA8000 and later processors. */
540 if (pa_cpu >= PROCESSOR_8000
541 || (targetm.except_unwind_info (&global_options) == UI_DWARF2
543 || flag_unwind_tables)
544 target_flags &= ~MASK_JUMP_IN_DELAY;
546 if (flag_pic && TARGET_PORTABLE_RUNTIME)
548 warning (0, "PIC code generation is not supported in the portable runtime model");
551 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
553 warning (0, "PIC code generation is not compatible with fast indirect calls");
556 if (! TARGET_GAS && write_symbols != NO_DEBUG)
558 warning (0, "-g is only supported when using GAS on this processor,");
559 warning (0, "-g option disabled");
560 write_symbols = NO_DEBUG;
563 /* We only support the "big PIC" model now. And we always generate PIC
564 code when in 64bit mode. */
565 if (flag_pic == 1 || TARGET_64BIT)
568 /* Disable -freorder-blocks-and-partition as we don't support hot and
569 cold partitioning. */
570 if (flag_reorder_blocks_and_partition)
572 inform (input_location,
573 "-freorder-blocks-and-partition does not work "
574 "on this architecture");
575 flag_reorder_blocks_and_partition = 0;
576 flag_reorder_blocks = 1;
579 /* We can't guarantee that .dword is available for 32-bit targets. */
580 if (UNITS_PER_WORD == 4)
581 targetm.asm_out.aligned_op.di = NULL;
583 /* The unaligned ops are only available when using GAS. */
586 targetm.asm_out.unaligned_op.hi = NULL;
587 targetm.asm_out.unaligned_op.si = NULL;
588 targetm.asm_out.unaligned_op.di = NULL;
591 init_machine_status = pa_init_machine_status;
596 PA_BUILTIN_COPYSIGNQ,
599 PA_BUILTIN_HUGE_VALQ,
603 static GTY(()) tree pa_builtins[(int) PA_BUILTIN_max];
606 pa_init_builtins (void)
608 #ifdef DONT_HAVE_FPUTC_UNLOCKED
609 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
610 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
611 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
612 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
615 if (built_in_decls [BUILT_IN_FINITE])
616 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
617 if (built_in_decls [BUILT_IN_FINITEF])
618 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
621 if (HPUX_LONG_DOUBLE_LIBRARY)
625 /* Under HPUX, the __float128 type is a synonym for "long double". */
626 (*lang_hooks.types.register_builtin_type) (long_double_type_node,
629 /* TFmode support builtins. */
630 ftype = build_function_type_list (long_double_type_node,
631 long_double_type_node,
633 decl = add_builtin_function ("__builtin_fabsq", ftype,
634 PA_BUILTIN_FABSQ, BUILT_IN_MD,
635 "_U_Qfabs", NULL_TREE);
636 TREE_READONLY (decl) = 1;
637 pa_builtins[PA_BUILTIN_FABSQ] = decl;
639 ftype = build_function_type_list (long_double_type_node,
640 long_double_type_node,
641 long_double_type_node,
643 decl = add_builtin_function ("__builtin_copysignq", ftype,
644 PA_BUILTIN_COPYSIGNQ, BUILT_IN_MD,
645 "_U_Qfcopysign", NULL_TREE);
646 TREE_READONLY (decl) = 1;
647 pa_builtins[PA_BUILTIN_COPYSIGNQ] = decl;
649 ftype = build_function_type_list (long_double_type_node, NULL_TREE);
650 decl = add_builtin_function ("__builtin_infq", ftype,
651 PA_BUILTIN_INFQ, BUILT_IN_MD,
653 pa_builtins[PA_BUILTIN_INFQ] = decl;
655 decl = add_builtin_function ("__builtin_huge_valq", ftype,
656 PA_BUILTIN_HUGE_VALQ, BUILT_IN_MD,
658 pa_builtins[PA_BUILTIN_HUGE_VALQ] = decl;
663 pa_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
664 enum machine_mode mode ATTRIBUTE_UNUSED,
665 int ignore ATTRIBUTE_UNUSED)
667 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0);
668 unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
672 case PA_BUILTIN_FABSQ:
673 case PA_BUILTIN_COPYSIGNQ:
674 return expand_call (exp, target, ignore);
676 case PA_BUILTIN_INFQ:
677 case PA_BUILTIN_HUGE_VALQ:
679 enum machine_mode target_mode = TYPE_MODE (TREE_TYPE (exp));
684 tmp = CONST_DOUBLE_FROM_REAL_VALUE (inf, target_mode);
686 tmp = validize_mem (force_const_mem (target_mode, tmp));
689 target = gen_reg_rtx (target_mode);
691 emit_move_insn (target, tmp);
702 /* Function to init struct machine_function.
703 This will be called, via a pointer variable,
704 from push_function_context. */
706 static struct machine_function *
707 pa_init_machine_status (void)
709 return ggc_alloc_cleared_machine_function ();
712 /* If FROM is a probable pointer register, mark TO as a probable
713 pointer register with the same pointer alignment as FROM. */
716 copy_reg_pointer (rtx to, rtx from)
718 if (REG_POINTER (from))
719 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
722 /* Return 1 if X contains a symbolic expression. We know these
723 expressions will have one of a few well defined forms, so
724 we need only check those forms. */
726 symbolic_expression_p (rtx x)
729 /* Strip off any HIGH. */
730 if (GET_CODE (x) == HIGH)
733 return (symbolic_operand (x, VOIDmode));
736 /* Accept any constant that can be moved in one instruction into a
739 cint_ok_for_move (HOST_WIDE_INT ival)
741 /* OK if ldo, ldil, or zdepi, can be used. */
742 return (VAL_14_BITS_P (ival)
743 || ldil_cint_p (ival)
744 || zdepi_cint_p (ival));
747 /* True iff ldil can be used to load this CONST_INT. The least
748 significant 11 bits of the value must be zero and the value must
749 not change sign when extended from 32 to 64 bits. */
751 ldil_cint_p (HOST_WIDE_INT ival)
753 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
755 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
758 /* True iff zdepi can be used to generate this CONST_INT.
759 zdepi first sign extends a 5-bit signed number to a given field
760 length, then places this field anywhere in a zero. */
762 zdepi_cint_p (unsigned HOST_WIDE_INT x)
764 unsigned HOST_WIDE_INT lsb_mask, t;
766 /* This might not be obvious, but it's at least fast.
767 This function is critical; we don't have the time loops would take. */
769 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
770 /* Return true iff t is a power of two. */
771 return ((t & (t - 1)) == 0);
774 /* True iff depi or extru can be used to compute (reg & mask).
775 Accept bit pattern like these:
780 and_mask_p (unsigned HOST_WIDE_INT mask)
783 mask += mask & -mask;
784 return (mask & (mask - 1)) == 0;
787 /* True iff depi can be used to compute (reg | MASK). */
789 ior_mask_p (unsigned HOST_WIDE_INT mask)
791 mask += mask & -mask;
792 return (mask & (mask - 1)) == 0;
795 /* Legitimize PIC addresses. If the address is already
796 position-independent, we return ORIG. Newly generated
797 position-independent addresses go to REG. If we need more
798 than one register, we lose. */
801 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
805 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
807 /* Labels need special handling. */
808 if (pic_label_operand (orig, mode))
812 /* We do not want to go through the movXX expanders here since that
813 would create recursion.
815 Nor do we really want to call a generator for a named pattern
816 since that requires multiple patterns if we want to support
819 So instead we just emit the raw set, which avoids the movXX
820 expanders completely. */
821 mark_reg_pointer (reg, BITS_PER_UNIT);
822 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
824 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
825 add_reg_note (insn, REG_EQUAL, orig);
827 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
828 and update LABEL_NUSES because this is not done automatically. */
829 if (reload_in_progress || reload_completed)
831 /* Extract LABEL_REF. */
832 if (GET_CODE (orig) == CONST)
833 orig = XEXP (XEXP (orig, 0), 0);
834 /* Extract CODE_LABEL. */
835 orig = XEXP (orig, 0);
836 add_reg_note (insn, REG_LABEL_OPERAND, orig);
837 LABEL_NUSES (orig)++;
839 crtl->uses_pic_offset_table = 1;
842 if (GET_CODE (orig) == SYMBOL_REF)
848 /* Before reload, allocate a temporary register for the intermediate
849 result. This allows the sequence to be deleted when the final
850 result is unused and the insns are trivially dead. */
851 tmp_reg = ((reload_in_progress || reload_completed)
852 ? reg : gen_reg_rtx (Pmode));
854 if (function_label_operand (orig, VOIDmode))
856 /* Force function label into memory in word mode. */
857 orig = XEXP (force_const_mem (word_mode, orig), 0);
858 /* Load plabel address from DLT. */
859 emit_move_insn (tmp_reg,
860 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
861 gen_rtx_HIGH (word_mode, orig)));
863 = gen_const_mem (Pmode,
864 gen_rtx_LO_SUM (Pmode, tmp_reg,
865 gen_rtx_UNSPEC (Pmode,
868 emit_move_insn (reg, pic_ref);
869 /* Now load address of function descriptor. */
870 pic_ref = gen_rtx_MEM (Pmode, reg);
874 /* Load symbol reference from DLT. */
875 emit_move_insn (tmp_reg,
876 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
877 gen_rtx_HIGH (word_mode, orig)));
879 = gen_const_mem (Pmode,
880 gen_rtx_LO_SUM (Pmode, tmp_reg,
881 gen_rtx_UNSPEC (Pmode,
886 crtl->uses_pic_offset_table = 1;
887 mark_reg_pointer (reg, BITS_PER_UNIT);
888 insn = emit_move_insn (reg, pic_ref);
890 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
891 set_unique_reg_note (insn, REG_EQUAL, orig);
895 else if (GET_CODE (orig) == CONST)
899 if (GET_CODE (XEXP (orig, 0)) == PLUS
900 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
904 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
906 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
907 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
908 base == reg ? 0 : reg);
910 if (GET_CODE (orig) == CONST_INT)
912 if (INT_14_BITS (orig))
913 return plus_constant (base, INTVAL (orig));
914 orig = force_reg (Pmode, orig);
916 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
917 /* Likewise, should we set special REG_NOTEs here? */
923 static GTY(()) rtx gen_tls_tga;
926 gen_tls_get_addr (void)
929 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
934 hppa_tls_call (rtx arg)
938 ret = gen_reg_rtx (Pmode);
939 emit_library_call_value (gen_tls_get_addr (), ret,
940 LCT_CONST, Pmode, 1, arg, Pmode);
946 legitimize_tls_address (rtx addr)
948 rtx ret, insn, tmp, t1, t2, tp;
949 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
953 case TLS_MODEL_GLOBAL_DYNAMIC:
954 tmp = gen_reg_rtx (Pmode);
956 emit_insn (gen_tgd_load_pic (tmp, addr));
958 emit_insn (gen_tgd_load (tmp, addr));
959 ret = hppa_tls_call (tmp);
962 case TLS_MODEL_LOCAL_DYNAMIC:
963 ret = gen_reg_rtx (Pmode);
964 tmp = gen_reg_rtx (Pmode);
967 emit_insn (gen_tld_load_pic (tmp, addr));
969 emit_insn (gen_tld_load (tmp, addr));
970 t1 = hppa_tls_call (tmp);
973 t2 = gen_reg_rtx (Pmode);
974 emit_libcall_block (insn, t2, t1,
975 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
977 emit_insn (gen_tld_offset_load (ret, addr, t2));
980 case TLS_MODEL_INITIAL_EXEC:
981 tp = gen_reg_rtx (Pmode);
982 tmp = gen_reg_rtx (Pmode);
983 ret = gen_reg_rtx (Pmode);
984 emit_insn (gen_tp_load (tp));
986 emit_insn (gen_tie_load_pic (tmp, addr));
988 emit_insn (gen_tie_load (tmp, addr));
989 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
992 case TLS_MODEL_LOCAL_EXEC:
993 tp = gen_reg_rtx (Pmode);
994 ret = gen_reg_rtx (Pmode);
995 emit_insn (gen_tp_load (tp));
996 emit_insn (gen_tle_load (ret, addr, tp));
1006 /* Try machine-dependent ways of modifying an illegitimate address
1007 to be legitimate. If we find one, return the new, valid address.
1008 This macro is used in only one place: `memory_address' in explow.c.
1010 OLDX is the address as it was before break_out_memory_refs was called.
1011 In some cases it is useful to look at this to decide what needs to be done.
1013 It is always safe for this macro to do nothing. It exists to recognize
1014 opportunities to optimize the output.
1016 For the PA, transform:
1018 memory(X + <large int>)
1022 if (<large int> & mask) >= 16
1023 Y = (<large int> & ~mask) + mask + 1 Round up.
1025 Y = (<large int> & ~mask) Round down.
1027 memory (Z + (<large int> - Y));
1029 This is for CSE to find several similar references, and only use one Z.
1031 X can either be a SYMBOL_REF or REG, but because combine cannot
1032 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1033 D will not fit in 14 bits.
1035 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1038 MODE_INT references allow displacements which fit in 14 bits, so use
1041 This relies on the fact that most mode MODE_FLOAT references will use FP
1042 registers and most mode MODE_INT references will use integer registers.
1043 (In the rare case of an FP register used in an integer MODE, we depend
1044 on secondary reloads to clean things up.)
1047 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1048 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1049 addressing modes to be used).
1051 Put X and Z into registers. Then put the entire expression into
1055 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1056 enum machine_mode mode)
1060 /* We need to canonicalize the order of operands in unscaled indexed
1061 addresses since the code that checks if an address is valid doesn't
1062 always try both orders. */
1063 if (!TARGET_NO_SPACE_REGS
1064 && GET_CODE (x) == PLUS
1065 && GET_MODE (x) == Pmode
1066 && REG_P (XEXP (x, 0))
1067 && REG_P (XEXP (x, 1))
1068 && REG_POINTER (XEXP (x, 0))
1069 && !REG_POINTER (XEXP (x, 1)))
1070 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1072 if (PA_SYMBOL_REF_TLS_P (x))
1073 return legitimize_tls_address (x);
1075 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1077 /* Strip off CONST. */
1078 if (GET_CODE (x) == CONST)
1081 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1082 That should always be safe. */
1083 if (GET_CODE (x) == PLUS
1084 && GET_CODE (XEXP (x, 0)) == REG
1085 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1087 rtx reg = force_reg (Pmode, XEXP (x, 1));
1088 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1091 /* Note we must reject symbols which represent function addresses
1092 since the assembler/linker can't handle arithmetic on plabels. */
1093 if (GET_CODE (x) == PLUS
1094 && GET_CODE (XEXP (x, 1)) == CONST_INT
1095 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1096 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1097 || GET_CODE (XEXP (x, 0)) == REG))
1099 rtx int_part, ptr_reg;
1101 int offset = INTVAL (XEXP (x, 1));
1104 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1105 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
1107 /* Choose which way to round the offset. Round up if we
1108 are >= halfway to the next boundary. */
1109 if ((offset & mask) >= ((mask + 1) / 2))
1110 newoffset = (offset & ~ mask) + mask + 1;
1112 newoffset = (offset & ~ mask);
1114 /* If the newoffset will not fit in 14 bits (ldo), then
1115 handling this would take 4 or 5 instructions (2 to load
1116 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1117 add the new offset and the SYMBOL_REF.) Combine can
1118 not handle 4->2 or 5->2 combinations, so do not create
1120 if (! VAL_14_BITS_P (newoffset)
1121 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1123 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1126 gen_rtx_HIGH (Pmode, const_part));
1129 gen_rtx_LO_SUM (Pmode,
1130 tmp_reg, const_part));
1134 if (! VAL_14_BITS_P (newoffset))
1135 int_part = force_reg (Pmode, GEN_INT (newoffset));
1137 int_part = GEN_INT (newoffset);
1139 ptr_reg = force_reg (Pmode,
1140 gen_rtx_PLUS (Pmode,
1141 force_reg (Pmode, XEXP (x, 0)),
1144 return plus_constant (ptr_reg, offset - newoffset);
1147 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1149 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1150 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1151 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1152 && (OBJECT_P (XEXP (x, 1))
1153 || GET_CODE (XEXP (x, 1)) == SUBREG)
1154 && GET_CODE (XEXP (x, 1)) != CONST)
1156 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1160 if (GET_CODE (reg1) != REG)
1161 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1163 reg2 = XEXP (XEXP (x, 0), 0);
1164 if (GET_CODE (reg2) != REG)
1165 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1167 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1168 gen_rtx_MULT (Pmode,
1174 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1176 Only do so for floating point modes since this is more speculative
1177 and we lose if it's an integer store. */
1178 if (GET_CODE (x) == PLUS
1179 && GET_CODE (XEXP (x, 0)) == PLUS
1180 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1181 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1182 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1183 && (mode == SFmode || mode == DFmode))
1186 /* First, try and figure out what to use as a base register. */
1187 rtx reg1, reg2, base, idx;
1189 reg1 = XEXP (XEXP (x, 0), 1);
1194 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1195 then emit_move_sequence will turn on REG_POINTER so we'll know
1196 it's a base register below. */
1197 if (GET_CODE (reg1) != REG)
1198 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1200 if (GET_CODE (reg2) != REG)
1201 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1203 /* Figure out what the base and index are. */
1205 if (GET_CODE (reg1) == REG
1206 && REG_POINTER (reg1))
1209 idx = gen_rtx_PLUS (Pmode,
1210 gen_rtx_MULT (Pmode,
1211 XEXP (XEXP (XEXP (x, 0), 0), 0),
1212 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1215 else if (GET_CODE (reg2) == REG
1216 && REG_POINTER (reg2))
1225 /* If the index adds a large constant, try to scale the
1226 constant so that it can be loaded with only one insn. */
1227 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1228 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1229 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1230 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1232 /* Divide the CONST_INT by the scale factor, then add it to A. */
1233 int val = INTVAL (XEXP (idx, 1));
1235 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1236 reg1 = XEXP (XEXP (idx, 0), 0);
1237 if (GET_CODE (reg1) != REG)
1238 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1240 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1242 /* We can now generate a simple scaled indexed address. */
1245 (Pmode, gen_rtx_PLUS (Pmode,
1246 gen_rtx_MULT (Pmode, reg1,
1247 XEXP (XEXP (idx, 0), 1)),
1251 /* If B + C is still a valid base register, then add them. */
1252 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1253 && INTVAL (XEXP (idx, 1)) <= 4096
1254 && INTVAL (XEXP (idx, 1)) >= -4096)
1256 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1259 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1261 reg2 = XEXP (XEXP (idx, 0), 0);
1262 if (GET_CODE (reg2) != CONST_INT)
1263 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1265 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1266 gen_rtx_MULT (Pmode,
1272 /* Get the index into a register, then add the base + index and
1273 return a register holding the result. */
1275 /* First get A into a register. */
1276 reg1 = XEXP (XEXP (idx, 0), 0);
1277 if (GET_CODE (reg1) != REG)
1278 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1280 /* And get B into a register. */
1281 reg2 = XEXP (idx, 1);
1282 if (GET_CODE (reg2) != REG)
1283 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1285 reg1 = force_reg (Pmode,
1286 gen_rtx_PLUS (Pmode,
1287 gen_rtx_MULT (Pmode, reg1,
1288 XEXP (XEXP (idx, 0), 1)),
1291 /* Add the result to our base register and return. */
1292 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1296 /* Uh-oh. We might have an address for x[n-100000]. This needs
1297 special handling to avoid creating an indexed memory address
1298 with x-100000 as the base.
1300 If the constant part is small enough, then it's still safe because
1301 there is a guard page at the beginning and end of the data segment.
1303 Scaled references are common enough that we want to try and rearrange the
1304 terms so that we can use indexing for these addresses too. Only
1305 do the optimization for floatint point modes. */
1307 if (GET_CODE (x) == PLUS
1308 && symbolic_expression_p (XEXP (x, 1)))
1310 /* Ugly. We modify things here so that the address offset specified
1311 by the index expression is computed first, then added to x to form
1312 the entire address. */
1314 rtx regx1, regx2, regy1, regy2, y;
1316 /* Strip off any CONST. */
1318 if (GET_CODE (y) == CONST)
1321 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1323 /* See if this looks like
1324 (plus (mult (reg) (shadd_const))
1325 (const (plus (symbol_ref) (const_int))))
1327 Where const_int is small. In that case the const
1328 expression is a valid pointer for indexing.
1330 If const_int is big, but can be divided evenly by shadd_const
1331 and added to (reg). This allows more scaled indexed addresses. */
1332 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1333 && GET_CODE (XEXP (x, 0)) == MULT
1334 && GET_CODE (XEXP (y, 1)) == CONST_INT
1335 && INTVAL (XEXP (y, 1)) >= -4096
1336 && INTVAL (XEXP (y, 1)) <= 4095
1337 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1338 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1340 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1344 if (GET_CODE (reg1) != REG)
1345 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1347 reg2 = XEXP (XEXP (x, 0), 0);
1348 if (GET_CODE (reg2) != REG)
1349 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1351 return force_reg (Pmode,
1352 gen_rtx_PLUS (Pmode,
1353 gen_rtx_MULT (Pmode,
1358 else if ((mode == DFmode || mode == SFmode)
1359 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1360 && GET_CODE (XEXP (x, 0)) == MULT
1361 && GET_CODE (XEXP (y, 1)) == CONST_INT
1362 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1363 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1364 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1367 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1368 / INTVAL (XEXP (XEXP (x, 0), 1))));
1369 regx2 = XEXP (XEXP (x, 0), 0);
1370 if (GET_CODE (regx2) != REG)
1371 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1372 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1376 gen_rtx_PLUS (Pmode,
1377 gen_rtx_MULT (Pmode, regx2,
1378 XEXP (XEXP (x, 0), 1)),
1379 force_reg (Pmode, XEXP (y, 0))));
1381 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1382 && INTVAL (XEXP (y, 1)) >= -4096
1383 && INTVAL (XEXP (y, 1)) <= 4095)
1385 /* This is safe because of the guard page at the
1386 beginning and end of the data space. Just
1387 return the original address. */
1392 /* Doesn't look like one we can optimize. */
1393 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1394 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1395 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1396 regx1 = force_reg (Pmode,
1397 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1399 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1407 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1409 Compute extra cost of moving data between one register class
1412 Make moves from SAR so expensive they should never happen. We used to
1413 have 0xffff here, but that generates overflow in rare cases.
1415 Copies involving a FP register and a non-FP register are relatively
1416 expensive because they must go through memory.
1418 Other copies are reasonably cheap. */
1421 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1422 reg_class_t from, reg_class_t to)
1424 if (from == SHIFT_REGS)
1426 else if (to == SHIFT_REGS && FP_REG_CLASS_P (from))
1428 else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
1429 || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
1435 /* For the HPPA, REG and REG+CONST is cost 0
1436 and addresses involving symbolic constants are cost 2.
1438 PIC addresses are very expensive.
1440 It is no coincidence that this has the same structure
1441 as GO_IF_LEGITIMATE_ADDRESS. */
1444 hppa_address_cost (rtx X,
1445 bool speed ATTRIBUTE_UNUSED)
1447 switch (GET_CODE (X))
1460 /* Compute a (partial) cost for rtx X. Return true if the complete
1461 cost has been computed, and false if subexpressions should be
1462 scanned. In either case, *TOTAL contains the cost result. */
1465 hppa_rtx_costs (rtx x, int code, int outer_code, int *total,
1466 bool speed ATTRIBUTE_UNUSED)
1471 if (INTVAL (x) == 0)
1473 else if (INT_14_BITS (x))
1490 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1491 && outer_code != SET)
1498 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1499 *total = COSTS_N_INSNS (3);
1500 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1501 *total = COSTS_N_INSNS (8);
1503 *total = COSTS_N_INSNS (20);
1507 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1509 *total = COSTS_N_INSNS (14);
1517 *total = COSTS_N_INSNS (60);
1520 case PLUS: /* this includes shNadd insns */
1522 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1523 *total = COSTS_N_INSNS (3);
1525 *total = COSTS_N_INSNS (1);
1531 *total = COSTS_N_INSNS (1);
1539 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1540 new rtx with the correct mode. */
1542 force_mode (enum machine_mode mode, rtx orig)
1544 if (mode == GET_MODE (orig))
1547 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1549 return gen_rtx_REG (mode, REGNO (orig));
1552 /* Return 1 if *X is a thread-local symbol. */
1555 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1557 return PA_SYMBOL_REF_TLS_P (*x);
1560 /* Return 1 if X contains a thread-local symbol. */
1563 pa_tls_referenced_p (rtx x)
1565 if (!TARGET_HAVE_TLS)
1568 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1571 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
1574 pa_cannot_force_const_mem (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x)
1576 return pa_tls_referenced_p (x);
1579 /* Emit insns to move operands[1] into operands[0].
1581 Return 1 if we have written out everything that needs to be done to
1582 do the move. Otherwise, return 0 and the caller will emit the move
1585 Note SCRATCH_REG may not be in the proper mode depending on how it
1586 will be used. This routine is responsible for creating a new copy
1587 of SCRATCH_REG in the proper mode. */
1590 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1592 register rtx operand0 = operands[0];
1593 register rtx operand1 = operands[1];
1596 /* We can only handle indexed addresses in the destination operand
1597 of floating point stores. Thus, we need to break out indexed
1598 addresses from the destination operand. */
1599 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1601 gcc_assert (can_create_pseudo_p ());
1603 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1604 operand0 = replace_equiv_address (operand0, tem);
1607 /* On targets with non-equivalent space registers, break out unscaled
1608 indexed addresses from the source operand before the final CSE.
1609 We have to do this because the REG_POINTER flag is not correctly
1610 carried through various optimization passes and CSE may substitute
1611 a pseudo without the pointer set for one with the pointer set. As
1612 a result, we loose various opportunities to create insns with
1613 unscaled indexed addresses. */
1614 if (!TARGET_NO_SPACE_REGS
1615 && !cse_not_expected
1616 && GET_CODE (operand1) == MEM
1617 && GET_CODE (XEXP (operand1, 0)) == PLUS
1618 && REG_P (XEXP (XEXP (operand1, 0), 0))
1619 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1621 = replace_equiv_address (operand1,
1622 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1625 && reload_in_progress && GET_CODE (operand0) == REG
1626 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1627 operand0 = reg_equiv_mem (REGNO (operand0));
1628 else if (scratch_reg
1629 && reload_in_progress && GET_CODE (operand0) == SUBREG
1630 && GET_CODE (SUBREG_REG (operand0)) == REG
1631 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1633 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1634 the code which tracks sets/uses for delete_output_reload. */
1635 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1636 reg_equiv_mem (REGNO (SUBREG_REG (operand0))),
1637 SUBREG_BYTE (operand0));
1638 operand0 = alter_subreg (&temp);
1642 && reload_in_progress && GET_CODE (operand1) == REG
1643 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1644 operand1 = reg_equiv_mem (REGNO (operand1));
1645 else if (scratch_reg
1646 && reload_in_progress && GET_CODE (operand1) == SUBREG
1647 && GET_CODE (SUBREG_REG (operand1)) == REG
1648 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1650 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1651 the code which tracks sets/uses for delete_output_reload. */
1652 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1653 reg_equiv_mem (REGNO (SUBREG_REG (operand1))),
1654 SUBREG_BYTE (operand1));
1655 operand1 = alter_subreg (&temp);
1658 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1659 && ((tem = find_replacement (&XEXP (operand0, 0)))
1660 != XEXP (operand0, 0)))
1661 operand0 = replace_equiv_address (operand0, tem);
1663 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1664 && ((tem = find_replacement (&XEXP (operand1, 0)))
1665 != XEXP (operand1, 0)))
1666 operand1 = replace_equiv_address (operand1, tem);
1668 /* Handle secondary reloads for loads/stores of FP registers from
1669 REG+D addresses where D does not fit in 5 or 14 bits, including
1670 (subreg (mem (addr))) cases. */
1672 && fp_reg_operand (operand0, mode)
1673 && ((GET_CODE (operand1) == MEM
1674 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1675 XEXP (operand1, 0)))
1676 || ((GET_CODE (operand1) == SUBREG
1677 && GET_CODE (XEXP (operand1, 0)) == MEM
1678 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1680 XEXP (XEXP (operand1, 0), 0))))))
1682 if (GET_CODE (operand1) == SUBREG)
1683 operand1 = XEXP (operand1, 0);
1685 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1686 it in WORD_MODE regardless of what mode it was originally given
1688 scratch_reg = force_mode (word_mode, scratch_reg);
1690 /* D might not fit in 14 bits either; for such cases load D into
1692 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1694 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1695 emit_move_insn (scratch_reg,
1696 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1698 XEXP (XEXP (operand1, 0), 0),
1702 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1703 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1704 replace_equiv_address (operand1, scratch_reg)));
1707 else if (scratch_reg
1708 && fp_reg_operand (operand1, mode)
1709 && ((GET_CODE (operand0) == MEM
1710 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1712 XEXP (operand0, 0)))
1713 || ((GET_CODE (operand0) == SUBREG)
1714 && GET_CODE (XEXP (operand0, 0)) == MEM
1715 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1717 XEXP (XEXP (operand0, 0), 0)))))
1719 if (GET_CODE (operand0) == SUBREG)
1720 operand0 = XEXP (operand0, 0);
1722 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1723 it in WORD_MODE regardless of what mode it was originally given
1725 scratch_reg = force_mode (word_mode, scratch_reg);
1727 /* D might not fit in 14 bits either; for such cases load D into
1729 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1731 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1732 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1735 XEXP (XEXP (operand0, 0),
1740 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1741 emit_insn (gen_rtx_SET (VOIDmode,
1742 replace_equiv_address (operand0, scratch_reg),
1746 /* Handle secondary reloads for loads of FP registers from constant
1747 expressions by forcing the constant into memory.
1749 Use scratch_reg to hold the address of the memory location.
1751 The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return
1752 NO_REGS when presented with a const_int and a register class
1753 containing only FP registers. Doing so unfortunately creates
1754 more problems than it solves. Fix this for 2.5. */
1755 else if (scratch_reg
1756 && CONSTANT_P (operand1)
1757 && fp_reg_operand (operand0, mode))
1759 rtx const_mem, xoperands[2];
1761 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1762 it in WORD_MODE regardless of what mode it was originally given
1764 scratch_reg = force_mode (word_mode, scratch_reg);
1766 /* Force the constant into memory and put the address of the
1767 memory location into scratch_reg. */
1768 const_mem = force_const_mem (mode, operand1);
1769 xoperands[0] = scratch_reg;
1770 xoperands[1] = XEXP (const_mem, 0);
1771 emit_move_sequence (xoperands, Pmode, 0);
1773 /* Now load the destination register. */
1774 emit_insn (gen_rtx_SET (mode, operand0,
1775 replace_equiv_address (const_mem, scratch_reg)));
1778 /* Handle secondary reloads for SAR. These occur when trying to load
1779 the SAR from memory or a constant. */
1780 else if (scratch_reg
1781 && GET_CODE (operand0) == REG
1782 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1783 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1784 && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
1786 /* D might not fit in 14 bits either; for such cases load D into
1788 if (GET_CODE (operand1) == MEM
1789 && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
1791 /* We are reloading the address into the scratch register, so we
1792 want to make sure the scratch register is a full register. */
1793 scratch_reg = force_mode (word_mode, scratch_reg);
1795 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1796 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1799 XEXP (XEXP (operand1, 0),
1803 /* Now we are going to load the scratch register from memory,
1804 we want to load it in the same width as the original MEM,
1805 which must be the same as the width of the ultimate destination,
1807 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1809 emit_move_insn (scratch_reg,
1810 replace_equiv_address (operand1, scratch_reg));
1814 /* We want to load the scratch register using the same mode as
1815 the ultimate destination. */
1816 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1818 emit_move_insn (scratch_reg, operand1);
1821 /* And emit the insn to set the ultimate destination. We know that
1822 the scratch register has the same mode as the destination at this
1824 emit_move_insn (operand0, scratch_reg);
1827 /* Handle the most common case: storing into a register. */
1828 else if (register_operand (operand0, mode))
1830 if (register_operand (operand1, mode)
1831 || (GET_CODE (operand1) == CONST_INT
1832 && cint_ok_for_move (INTVAL (operand1)))
1833 || (operand1 == CONST0_RTX (mode))
1834 || (GET_CODE (operand1) == HIGH
1835 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1836 /* Only `general_operands' can come here, so MEM is ok. */
1837 || GET_CODE (operand1) == MEM)
1839 /* Various sets are created during RTL generation which don't
1840 have the REG_POINTER flag correctly set. After the CSE pass,
1841 instruction recognition can fail if we don't consistently
1842 set this flag when performing register copies. This should
1843 also improve the opportunities for creating insns that use
1844 unscaled indexing. */
1845 if (REG_P (operand0) && REG_P (operand1))
1847 if (REG_POINTER (operand1)
1848 && !REG_POINTER (operand0)
1849 && !HARD_REGISTER_P (operand0))
1850 copy_reg_pointer (operand0, operand1);
1853 /* When MEMs are broken out, the REG_POINTER flag doesn't
1854 get set. In some cases, we can set the REG_POINTER flag
1855 from the declaration for the MEM. */
1856 if (REG_P (operand0)
1857 && GET_CODE (operand1) == MEM
1858 && !REG_POINTER (operand0))
1860 tree decl = MEM_EXPR (operand1);
1862 /* Set the register pointer flag and register alignment
1863 if the declaration for this memory reference is a
1869 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1871 if (TREE_CODE (decl) == COMPONENT_REF)
1872 decl = TREE_OPERAND (decl, 1);
1874 type = TREE_TYPE (decl);
1875 type = strip_array_types (type);
1877 if (POINTER_TYPE_P (type))
1881 type = TREE_TYPE (type);
1882 /* Using TYPE_ALIGN_OK is rather conservative as
1883 only the ada frontend actually sets it. */
1884 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1886 mark_reg_pointer (operand0, align);
1891 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1895 else if (GET_CODE (operand0) == MEM)
1897 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1898 && !(reload_in_progress || reload_completed))
1900 rtx temp = gen_reg_rtx (DFmode);
1902 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1903 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1906 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1908 /* Run this case quickly. */
1909 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1912 if (! (reload_in_progress || reload_completed))
1914 operands[0] = validize_mem (operand0);
1915 operands[1] = operand1 = force_reg (mode, operand1);
1919 /* Simplify the source if we need to.
1920 Note we do have to handle function labels here, even though we do
1921 not consider them legitimate constants. Loop optimizations can
1922 call the emit_move_xxx with one as a source. */
1923 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1924 || function_label_operand (operand1, VOIDmode)
1925 || (GET_CODE (operand1) == HIGH
1926 && symbolic_operand (XEXP (operand1, 0), mode)))
1930 if (GET_CODE (operand1) == HIGH)
1933 operand1 = XEXP (operand1, 0);
1935 if (symbolic_operand (operand1, mode))
1937 /* Argh. The assembler and linker can't handle arithmetic
1940 So we force the plabel into memory, load operand0 from
1941 the memory location, then add in the constant part. */
1942 if ((GET_CODE (operand1) == CONST
1943 && GET_CODE (XEXP (operand1, 0)) == PLUS
1944 && function_label_operand (XEXP (XEXP (operand1, 0), 0),
1946 || function_label_operand (operand1, VOIDmode))
1948 rtx temp, const_part;
1950 /* Figure out what (if any) scratch register to use. */
1951 if (reload_in_progress || reload_completed)
1953 scratch_reg = scratch_reg ? scratch_reg : operand0;
1954 /* SCRATCH_REG will hold an address and maybe the actual
1955 data. We want it in WORD_MODE regardless of what mode it
1956 was originally given to us. */
1957 scratch_reg = force_mode (word_mode, scratch_reg);
1960 scratch_reg = gen_reg_rtx (Pmode);
1962 if (GET_CODE (operand1) == CONST)
1964 /* Save away the constant part of the expression. */
1965 const_part = XEXP (XEXP (operand1, 0), 1);
1966 gcc_assert (GET_CODE (const_part) == CONST_INT);
1968 /* Force the function label into memory. */
1969 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1973 /* No constant part. */
1974 const_part = NULL_RTX;
1976 /* Force the function label into memory. */
1977 temp = force_const_mem (mode, operand1);
1981 /* Get the address of the memory location. PIC-ify it if
1983 temp = XEXP (temp, 0);
1985 temp = legitimize_pic_address (temp, mode, scratch_reg);
1987 /* Put the address of the memory location into our destination
1990 emit_move_sequence (operands, mode, scratch_reg);
1992 /* Now load from the memory location into our destination
1994 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1995 emit_move_sequence (operands, mode, scratch_reg);
1997 /* And add back in the constant part. */
1998 if (const_part != NULL_RTX)
1999 expand_inc (operand0, const_part);
2008 if (reload_in_progress || reload_completed)
2010 temp = scratch_reg ? scratch_reg : operand0;
2011 /* TEMP will hold an address and maybe the actual
2012 data. We want it in WORD_MODE regardless of what mode it
2013 was originally given to us. */
2014 temp = force_mode (word_mode, temp);
2017 temp = gen_reg_rtx (Pmode);
2019 /* (const (plus (symbol) (const_int))) must be forced to
2020 memory during/after reload if the const_int will not fit
2022 if (GET_CODE (operand1) == CONST
2023 && GET_CODE (XEXP (operand1, 0)) == PLUS
2024 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2025 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2026 && (reload_completed || reload_in_progress)
2029 rtx const_mem = force_const_mem (mode, operand1);
2030 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
2032 operands[1] = replace_equiv_address (const_mem, operands[1]);
2033 emit_move_sequence (operands, mode, temp);
2037 operands[1] = legitimize_pic_address (operand1, mode, temp);
2038 if (REG_P (operand0) && REG_P (operands[1]))
2039 copy_reg_pointer (operand0, operands[1]);
2040 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2043 /* On the HPPA, references to data space are supposed to use dp,
2044 register 27, but showing it in the RTL inhibits various cse
2045 and loop optimizations. */
2050 if (reload_in_progress || reload_completed)
2052 temp = scratch_reg ? scratch_reg : operand0;
2053 /* TEMP will hold an address and maybe the actual
2054 data. We want it in WORD_MODE regardless of what mode it
2055 was originally given to us. */
2056 temp = force_mode (word_mode, temp);
2059 temp = gen_reg_rtx (mode);
2061 /* Loading a SYMBOL_REF into a register makes that register
2062 safe to be used as the base in an indexed address.
2064 Don't mark hard registers though. That loses. */
2065 if (GET_CODE (operand0) == REG
2066 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2067 mark_reg_pointer (operand0, BITS_PER_UNIT);
2068 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2069 mark_reg_pointer (temp, BITS_PER_UNIT);
2072 set = gen_rtx_SET (mode, operand0, temp);
2074 set = gen_rtx_SET (VOIDmode,
2076 gen_rtx_LO_SUM (mode, temp, operand1));
2078 emit_insn (gen_rtx_SET (VOIDmode,
2080 gen_rtx_HIGH (mode, operand1)));
2086 else if (pa_tls_referenced_p (operand1))
2091 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
2093 addend = XEXP (XEXP (tmp, 0), 1);
2094 tmp = XEXP (XEXP (tmp, 0), 0);
2097 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
2098 tmp = legitimize_tls_address (tmp);
2101 tmp = gen_rtx_PLUS (mode, tmp, addend);
2102 tmp = force_operand (tmp, operands[0]);
2106 else if (GET_CODE (operand1) != CONST_INT
2107 || !cint_ok_for_move (INTVAL (operand1)))
2111 HOST_WIDE_INT value = 0;
2112 HOST_WIDE_INT insv = 0;
2115 if (GET_CODE (operand1) == CONST_INT)
2116 value = INTVAL (operand1);
2119 && GET_CODE (operand1) == CONST_INT
2120 && HOST_BITS_PER_WIDE_INT > 32
2121 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2125 /* Extract the low order 32 bits of the value and sign extend.
2126 If the new value is the same as the original value, we can
2127 can use the original value as-is. If the new value is
2128 different, we use it and insert the most-significant 32-bits
2129 of the original value into the final result. */
2130 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2131 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2134 #if HOST_BITS_PER_WIDE_INT > 32
2135 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2139 operand1 = GEN_INT (nval);
2143 if (reload_in_progress || reload_completed)
2144 temp = scratch_reg ? scratch_reg : operand0;
2146 temp = gen_reg_rtx (mode);
2148 /* We don't directly split DImode constants on 32-bit targets
2149 because PLUS uses an 11-bit immediate and the insn sequence
2150 generated is not as efficient as the one using HIGH/LO_SUM. */
2151 if (GET_CODE (operand1) == CONST_INT
2152 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
2153 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2156 /* Directly break constant into high and low parts. This
2157 provides better optimization opportunities because various
2158 passes recognize constants split with PLUS but not LO_SUM.
2159 We use a 14-bit signed low part except when the addition
2160 of 0x4000 to the high part might change the sign of the
2162 HOST_WIDE_INT low = value & 0x3fff;
2163 HOST_WIDE_INT high = value & ~ 0x3fff;
2167 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2175 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2176 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2180 emit_insn (gen_rtx_SET (VOIDmode, temp,
2181 gen_rtx_HIGH (mode, operand1)));
2182 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2185 insn = emit_move_insn (operands[0], operands[1]);
2187 /* Now insert the most significant 32 bits of the value
2188 into the register. When we don't have a second register
2189 available, it could take up to nine instructions to load
2190 a 64-bit integer constant. Prior to reload, we force
2191 constants that would take more than three instructions
2192 to load to the constant pool. During and after reload,
2193 we have to handle all possible values. */
2196 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2197 register and the value to be inserted is outside the
2198 range that can be loaded with three depdi instructions. */
2199 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2201 operand1 = GEN_INT (insv);
2203 emit_insn (gen_rtx_SET (VOIDmode, temp,
2204 gen_rtx_HIGH (mode, operand1)));
2205 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2206 emit_insn (gen_insv (operand0, GEN_INT (32),
2211 int len = 5, pos = 27;
2213 /* Insert the bits using the depdi instruction. */
2216 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2217 HOST_WIDE_INT sign = v5 < 0;
2219 /* Left extend the insertion. */
2220 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2221 while (pos > 0 && (insv & 1) == sign)
2223 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2228 emit_insn (gen_insv (operand0, GEN_INT (len),
2229 GEN_INT (pos), GEN_INT (v5)));
2231 len = pos > 0 && pos < 5 ? pos : 5;
2237 set_unique_reg_note (insn, REG_EQUAL, op1);
2242 /* Now have insn-emit do whatever it normally does. */
2246 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2247 it will need a link/runtime reloc). */
2250 reloc_needed (tree exp)
2254 switch (TREE_CODE (exp))
2259 case POINTER_PLUS_EXPR:
2262 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2263 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2267 case NON_LVALUE_EXPR:
2268 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2274 unsigned HOST_WIDE_INT ix;
2276 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2278 reloc |= reloc_needed (value);
2292 /* Return the best assembler insn template
2293 for moving operands[1] into operands[0] as a fullword. */
2295 singlemove_string (rtx *operands)
2297 HOST_WIDE_INT intval;
2299 if (GET_CODE (operands[0]) == MEM)
2300 return "stw %r1,%0";
2301 if (GET_CODE (operands[1]) == MEM)
2303 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2308 gcc_assert (GET_MODE (operands[1]) == SFmode);
2310 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2312 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2313 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2315 operands[1] = GEN_INT (i);
2316 /* Fall through to CONST_INT case. */
2318 if (GET_CODE (operands[1]) == CONST_INT)
2320 intval = INTVAL (operands[1]);
2322 if (VAL_14_BITS_P (intval))
2324 else if ((intval & 0x7ff) == 0)
2325 return "ldil L'%1,%0";
2326 else if (zdepi_cint_p (intval))
2327 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2329 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2331 return "copy %1,%0";
2335 /* Compute position (in OP[1]) and width (in OP[2])
2336 useful for copying IMM to a register using the zdepi
2337 instructions. Store the immediate value to insert in OP[0]. */
2339 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2343 /* Find the least significant set bit in IMM. */
2344 for (lsb = 0; lsb < 32; lsb++)
2351 /* Choose variants based on *sign* of the 5-bit field. */
2352 if ((imm & 0x10) == 0)
2353 len = (lsb <= 28) ? 4 : 32 - lsb;
2356 /* Find the width of the bitstring in IMM. */
2357 for (len = 5; len < 32 - lsb; len++)
2359 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2363 /* Sign extend IMM as a 5-bit value. */
2364 imm = (imm & 0xf) - 0x10;
2372 /* Compute position (in OP[1]) and width (in OP[2])
2373 useful for copying IMM to a register using the depdi,z
2374 instructions. Store the immediate value to insert in OP[0]. */
2376 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2378 int lsb, len, maxlen;
2380 maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64);
2382 /* Find the least significant set bit in IMM. */
2383 for (lsb = 0; lsb < maxlen; lsb++)
2390 /* Choose variants based on *sign* of the 5-bit field. */
2391 if ((imm & 0x10) == 0)
2392 len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb;
2395 /* Find the width of the bitstring in IMM. */
2396 for (len = 5; len < maxlen - lsb; len++)
2398 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2402 /* Extend length if host is narrow and IMM is negative. */
2403 if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb)
2406 /* Sign extend IMM as a 5-bit value. */
2407 imm = (imm & 0xf) - 0x10;
2415 /* Output assembler code to perform a doubleword move insn
2416 with operands OPERANDS. */
2419 output_move_double (rtx *operands)
2421 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2423 rtx addreg0 = 0, addreg1 = 0;
2425 /* First classify both operands. */
2427 if (REG_P (operands[0]))
2429 else if (offsettable_memref_p (operands[0]))
2431 else if (GET_CODE (operands[0]) == MEM)
2436 if (REG_P (operands[1]))
2438 else if (CONSTANT_P (operands[1]))
2440 else if (offsettable_memref_p (operands[1]))
2442 else if (GET_CODE (operands[1]) == MEM)
2447 /* Check for the cases that the operand constraints are not
2448 supposed to allow to happen. */
2449 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2451 /* Handle copies between general and floating registers. */
2453 if (optype0 == REGOP && optype1 == REGOP
2454 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2456 if (FP_REG_P (operands[0]))
2458 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2459 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2460 return "{fldds|fldd} -16(%%sp),%0";
2464 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2465 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2466 return "{ldws|ldw} -12(%%sp),%R0";
2470 /* Handle auto decrementing and incrementing loads and stores
2471 specifically, since the structure of the function doesn't work
2472 for them without major modification. Do it better when we learn
2473 this port about the general inc/dec addressing of PA.
2474 (This was written by tege. Chide him if it doesn't work.) */
2476 if (optype0 == MEMOP)
2478 /* We have to output the address syntax ourselves, since print_operand
2479 doesn't deal with the addresses we want to use. Fix this later. */
2481 rtx addr = XEXP (operands[0], 0);
2482 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2484 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2486 operands[0] = XEXP (addr, 0);
2487 gcc_assert (GET_CODE (operands[1]) == REG
2488 && GET_CODE (operands[0]) == REG);
2490 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2492 /* No overlap between high target register and address
2493 register. (We do this in a non-obvious way to
2494 save a register file writeback) */
2495 if (GET_CODE (addr) == POST_INC)
2496 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2497 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2499 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2501 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2503 operands[0] = XEXP (addr, 0);
2504 gcc_assert (GET_CODE (operands[1]) == REG
2505 && GET_CODE (operands[0]) == REG);
2507 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2508 /* No overlap between high target register and address
2509 register. (We do this in a non-obvious way to save a
2510 register file writeback) */
2511 if (GET_CODE (addr) == PRE_INC)
2512 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2513 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2516 if (optype1 == MEMOP)
2518 /* We have to output the address syntax ourselves, since print_operand
2519 doesn't deal with the addresses we want to use. Fix this later. */
2521 rtx addr = XEXP (operands[1], 0);
2522 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2524 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2526 operands[1] = XEXP (addr, 0);
2527 gcc_assert (GET_CODE (operands[0]) == REG
2528 && GET_CODE (operands[1]) == REG);
2530 if (!reg_overlap_mentioned_p (high_reg, addr))
2532 /* No overlap between high target register and address
2533 register. (We do this in a non-obvious way to
2534 save a register file writeback) */
2535 if (GET_CODE (addr) == POST_INC)
2536 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2537 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2541 /* This is an undefined situation. We should load into the
2542 address register *and* update that register. Probably
2543 we don't need to handle this at all. */
2544 if (GET_CODE (addr) == POST_INC)
2545 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2546 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2549 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2551 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2553 operands[1] = XEXP (addr, 0);
2554 gcc_assert (GET_CODE (operands[0]) == REG
2555 && GET_CODE (operands[1]) == REG);
2557 if (!reg_overlap_mentioned_p (high_reg, addr))
2559 /* No overlap between high target register and address
2560 register. (We do this in a non-obvious way to
2561 save a register file writeback) */
2562 if (GET_CODE (addr) == PRE_INC)
2563 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2564 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2568 /* This is an undefined situation. We should load into the
2569 address register *and* update that register. Probably
2570 we don't need to handle this at all. */
2571 if (GET_CODE (addr) == PRE_INC)
2572 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2573 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2576 else if (GET_CODE (addr) == PLUS
2577 && GET_CODE (XEXP (addr, 0)) == MULT)
2580 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2582 if (!reg_overlap_mentioned_p (high_reg, addr))
2584 xoperands[0] = high_reg;
2585 xoperands[1] = XEXP (addr, 1);
2586 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2587 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2588 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2590 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2594 xoperands[0] = high_reg;
2595 xoperands[1] = XEXP (addr, 1);
2596 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2597 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2598 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2600 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2605 /* If an operand is an unoffsettable memory ref, find a register
2606 we can increment temporarily to make it refer to the second word. */
2608 if (optype0 == MEMOP)
2609 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2611 if (optype1 == MEMOP)
2612 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2614 /* Ok, we can do one word at a time.
2615 Normally we do the low-numbered word first.
2617 In either case, set up in LATEHALF the operands to use
2618 for the high-numbered word and in some cases alter the
2619 operands in OPERANDS to be suitable for the low-numbered word. */
2621 if (optype0 == REGOP)
2622 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2623 else if (optype0 == OFFSOP)
2624 latehalf[0] = adjust_address (operands[0], SImode, 4);
2626 latehalf[0] = operands[0];
2628 if (optype1 == REGOP)
2629 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2630 else if (optype1 == OFFSOP)
2631 latehalf[1] = adjust_address (operands[1], SImode, 4);
2632 else if (optype1 == CNSTOP)
2633 split_double (operands[1], &operands[1], &latehalf[1]);
2635 latehalf[1] = operands[1];
2637 /* If the first move would clobber the source of the second one,
2638 do them in the other order.
2640 This can happen in two cases:
2642 mem -> register where the first half of the destination register
2643 is the same register used in the memory's address. Reload
2644 can create such insns.
2646 mem in this case will be either register indirect or register
2647 indirect plus a valid offset.
2649 register -> register move where REGNO(dst) == REGNO(src + 1)
2650 someone (Tim/Tege?) claimed this can happen for parameter loads.
2652 Handle mem -> register case first. */
2653 if (optype0 == REGOP
2654 && (optype1 == MEMOP || optype1 == OFFSOP)
2655 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2658 /* Do the late half first. */
2660 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2661 output_asm_insn (singlemove_string (latehalf), latehalf);
2665 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2666 return singlemove_string (operands);
2669 /* Now handle register -> register case. */
2670 if (optype0 == REGOP && optype1 == REGOP
2671 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2673 output_asm_insn (singlemove_string (latehalf), latehalf);
2674 return singlemove_string (operands);
2677 /* Normal case: do the two words, low-numbered first. */
2679 output_asm_insn (singlemove_string (operands), operands);
2681 /* Make any unoffsettable addresses point at high-numbered word. */
2683 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2685 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2688 output_asm_insn (singlemove_string (latehalf), latehalf);
2690 /* Undo the adds we just did. */
2692 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2694 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2700 output_fp_move_double (rtx *operands)
2702 if (FP_REG_P (operands[0]))
2704 if (FP_REG_P (operands[1])
2705 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2706 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2708 output_asm_insn ("fldd%F1 %1,%0", operands);
2710 else if (FP_REG_P (operands[1]))
2712 output_asm_insn ("fstd%F0 %1,%0", operands);
2718 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2720 /* This is a pain. You have to be prepared to deal with an
2721 arbitrary address here including pre/post increment/decrement.
2723 so avoid this in the MD. */
2724 gcc_assert (GET_CODE (operands[0]) == REG);
2726 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2727 xoperands[0] = operands[0];
2728 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2733 /* Return a REG that occurs in ADDR with coefficient 1.
2734 ADDR can be effectively incremented by incrementing REG. */
2737 find_addr_reg (rtx addr)
2739 while (GET_CODE (addr) == PLUS)
2741 if (GET_CODE (XEXP (addr, 0)) == REG)
2742 addr = XEXP (addr, 0);
2743 else if (GET_CODE (XEXP (addr, 1)) == REG)
2744 addr = XEXP (addr, 1);
2745 else if (CONSTANT_P (XEXP (addr, 0)))
2746 addr = XEXP (addr, 1);
2747 else if (CONSTANT_P (XEXP (addr, 1)))
2748 addr = XEXP (addr, 0);
2752 gcc_assert (GET_CODE (addr) == REG);
2756 /* Emit code to perform a block move.
2758 OPERANDS[0] is the destination pointer as a REG, clobbered.
2759 OPERANDS[1] is the source pointer as a REG, clobbered.
2760 OPERANDS[2] is a register for temporary storage.
2761 OPERANDS[3] is a register for temporary storage.
2762 OPERANDS[4] is the size as a CONST_INT
2763 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2764 OPERANDS[6] is another temporary register. */
2767 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2769 int align = INTVAL (operands[5]);
2770 unsigned long n_bytes = INTVAL (operands[4]);
2772 /* We can't move more than a word at a time because the PA
2773 has no longer integer move insns. (Could use fp mem ops?) */
2774 if (align > (TARGET_64BIT ? 8 : 4))
2775 align = (TARGET_64BIT ? 8 : 4);
2777 /* Note that we know each loop below will execute at least twice
2778 (else we would have open-coded the copy). */
2782 /* Pre-adjust the loop counter. */
2783 operands[4] = GEN_INT (n_bytes - 16);
2784 output_asm_insn ("ldi %4,%2", operands);
2787 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2788 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2789 output_asm_insn ("std,ma %3,8(%0)", operands);
2790 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2791 output_asm_insn ("std,ma %6,8(%0)", operands);
2793 /* Handle the residual. There could be up to 7 bytes of
2794 residual to copy! */
2795 if (n_bytes % 16 != 0)
2797 operands[4] = GEN_INT (n_bytes % 8);
2798 if (n_bytes % 16 >= 8)
2799 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2800 if (n_bytes % 8 != 0)
2801 output_asm_insn ("ldd 0(%1),%6", operands);
2802 if (n_bytes % 16 >= 8)
2803 output_asm_insn ("std,ma %3,8(%0)", operands);
2804 if (n_bytes % 8 != 0)
2805 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2810 /* Pre-adjust the loop counter. */
2811 operands[4] = GEN_INT (n_bytes - 8);
2812 output_asm_insn ("ldi %4,%2", operands);
2815 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2816 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2817 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2818 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2819 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2821 /* Handle the residual. There could be up to 7 bytes of
2822 residual to copy! */
2823 if (n_bytes % 8 != 0)
2825 operands[4] = GEN_INT (n_bytes % 4);
2826 if (n_bytes % 8 >= 4)
2827 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2828 if (n_bytes % 4 != 0)
2829 output_asm_insn ("ldw 0(%1),%6", operands);
2830 if (n_bytes % 8 >= 4)
2831 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2832 if (n_bytes % 4 != 0)
2833 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2838 /* Pre-adjust the loop counter. */
2839 operands[4] = GEN_INT (n_bytes - 4);
2840 output_asm_insn ("ldi %4,%2", operands);
2843 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2844 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2845 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2846 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2847 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2849 /* Handle the residual. */
2850 if (n_bytes % 4 != 0)
2852 if (n_bytes % 4 >= 2)
2853 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2854 if (n_bytes % 2 != 0)
2855 output_asm_insn ("ldb 0(%1),%6", operands);
2856 if (n_bytes % 4 >= 2)
2857 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2858 if (n_bytes % 2 != 0)
2859 output_asm_insn ("stb %6,0(%0)", operands);
2864 /* Pre-adjust the loop counter. */
2865 operands[4] = GEN_INT (n_bytes - 2);
2866 output_asm_insn ("ldi %4,%2", operands);
2869 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2870 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2871 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2872 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2873 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2875 /* Handle the residual. */
2876 if (n_bytes % 2 != 0)
2878 output_asm_insn ("ldb 0(%1),%3", operands);
2879 output_asm_insn ("stb %3,0(%0)", operands);
2888 /* Count the number of insns necessary to handle this block move.
2890 Basic structure is the same as emit_block_move, except that we
2891 count insns rather than emit them. */
2894 compute_movmem_length (rtx insn)
2896 rtx pat = PATTERN (insn);
2897 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2898 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2899 unsigned int n_insns = 0;
2901 /* We can't move more than four bytes at a time because the PA
2902 has no longer integer move insns. (Could use fp mem ops?) */
2903 if (align > (TARGET_64BIT ? 8 : 4))
2904 align = (TARGET_64BIT ? 8 : 4);
2906 /* The basic copying loop. */
2910 if (n_bytes % (2 * align) != 0)
2912 if ((n_bytes % (2 * align)) >= align)
2915 if ((n_bytes % align) != 0)
2919 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2923 /* Emit code to perform a block clear.
2925 OPERANDS[0] is the destination pointer as a REG, clobbered.
2926 OPERANDS[1] is a register for temporary storage.
2927 OPERANDS[2] is the size as a CONST_INT
2928 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2931 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2933 int align = INTVAL (operands[3]);
2934 unsigned long n_bytes = INTVAL (operands[2]);
2936 /* We can't clear more than a word at a time because the PA
2937 has no longer integer move insns. */
2938 if (align > (TARGET_64BIT ? 8 : 4))
2939 align = (TARGET_64BIT ? 8 : 4);
2941 /* Note that we know each loop below will execute at least twice
2942 (else we would have open-coded the copy). */
2946 /* Pre-adjust the loop counter. */
2947 operands[2] = GEN_INT (n_bytes - 16);
2948 output_asm_insn ("ldi %2,%1", operands);
2951 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2952 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2953 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2955 /* Handle the residual. There could be up to 7 bytes of
2956 residual to copy! */
2957 if (n_bytes % 16 != 0)
2959 operands[2] = GEN_INT (n_bytes % 8);
2960 if (n_bytes % 16 >= 8)
2961 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2962 if (n_bytes % 8 != 0)
2963 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2968 /* Pre-adjust the loop counter. */
2969 operands[2] = GEN_INT (n_bytes - 8);
2970 output_asm_insn ("ldi %2,%1", operands);
2973 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2974 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2975 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2977 /* Handle the residual. There could be up to 7 bytes of
2978 residual to copy! */
2979 if (n_bytes % 8 != 0)
2981 operands[2] = GEN_INT (n_bytes % 4);
2982 if (n_bytes % 8 >= 4)
2983 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2984 if (n_bytes % 4 != 0)
2985 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2990 /* Pre-adjust the loop counter. */
2991 operands[2] = GEN_INT (n_bytes - 4);
2992 output_asm_insn ("ldi %2,%1", operands);
2995 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2996 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2997 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2999 /* Handle the residual. */
3000 if (n_bytes % 4 != 0)
3002 if (n_bytes % 4 >= 2)
3003 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3004 if (n_bytes % 2 != 0)
3005 output_asm_insn ("stb %%r0,0(%0)", operands);
3010 /* Pre-adjust the loop counter. */
3011 operands[2] = GEN_INT (n_bytes - 2);
3012 output_asm_insn ("ldi %2,%1", operands);
3015 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3016 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3017 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3019 /* Handle the residual. */
3020 if (n_bytes % 2 != 0)
3021 output_asm_insn ("stb %%r0,0(%0)", operands);
3030 /* Count the number of insns necessary to handle this block move.
3032 Basic structure is the same as emit_block_move, except that we
3033 count insns rather than emit them. */
3036 compute_clrmem_length (rtx insn)
3038 rtx pat = PATTERN (insn);
3039 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3040 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3041 unsigned int n_insns = 0;
3043 /* We can't clear more than a word at a time because the PA
3044 has no longer integer move insns. */
3045 if (align > (TARGET_64BIT ? 8 : 4))
3046 align = (TARGET_64BIT ? 8 : 4);
3048 /* The basic loop. */
3052 if (n_bytes % (2 * align) != 0)
3054 if ((n_bytes % (2 * align)) >= align)
3057 if ((n_bytes % align) != 0)
3061 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3067 output_and (rtx *operands)
3069 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3071 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3072 int ls0, ls1, ms0, p, len;
3074 for (ls0 = 0; ls0 < 32; ls0++)
3075 if ((mask & (1 << ls0)) == 0)
3078 for (ls1 = ls0; ls1 < 32; ls1++)
3079 if ((mask & (1 << ls1)) != 0)
3082 for (ms0 = ls1; ms0 < 32; ms0++)
3083 if ((mask & (1 << ms0)) == 0)
3086 gcc_assert (ms0 == 32);
3094 operands[2] = GEN_INT (len);
3095 return "{extru|extrw,u} %1,31,%2,%0";
3099 /* We could use this `depi' for the case above as well, but `depi'
3100 requires one more register file access than an `extru'. */
3105 operands[2] = GEN_INT (p);
3106 operands[3] = GEN_INT (len);
3107 return "{depi|depwi} 0,%2,%3,%0";
3111 return "and %1,%2,%0";
3114 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3115 storing the result in operands[0]. */
3117 output_64bit_and (rtx *operands)
3119 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3121 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3122 int ls0, ls1, ms0, p, len;
3124 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3125 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3128 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3129 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3132 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3133 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3136 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
3138 if (ls1 == HOST_BITS_PER_WIDE_INT)
3144 operands[2] = GEN_INT (len);
3145 return "extrd,u %1,63,%2,%0";
3149 /* We could use this `depi' for the case above as well, but `depi'
3150 requires one more register file access than an `extru'. */
3155 operands[2] = GEN_INT (p);
3156 operands[3] = GEN_INT (len);
3157 return "depdi 0,%2,%3,%0";
3161 return "and %1,%2,%0";
3165 output_ior (rtx *operands)
3167 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3168 int bs0, bs1, p, len;
3170 if (INTVAL (operands[2]) == 0)
3171 return "copy %1,%0";
3173 for (bs0 = 0; bs0 < 32; bs0++)
3174 if ((mask & (1 << bs0)) != 0)
3177 for (bs1 = bs0; bs1 < 32; bs1++)
3178 if ((mask & (1 << bs1)) == 0)
3181 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3186 operands[2] = GEN_INT (p);
3187 operands[3] = GEN_INT (len);
3188 return "{depi|depwi} -1,%2,%3,%0";
3191 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3192 storing the result in operands[0]. */
3194 output_64bit_ior (rtx *operands)
3196 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3197 int bs0, bs1, p, len;
3199 if (INTVAL (operands[2]) == 0)
3200 return "copy %1,%0";
3202 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3203 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3206 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3207 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3210 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3211 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3216 operands[2] = GEN_INT (p);
3217 operands[3] = GEN_INT (len);
3218 return "depdi -1,%2,%3,%0";
3221 /* Target hook for assembling integer objects. This code handles
3222 aligned SI and DI integers specially since function references
3223 must be preceded by P%. */
3226 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3228 if (size == UNITS_PER_WORD
3230 && function_label_operand (x, VOIDmode))
3232 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3233 output_addr_const (asm_out_file, x);
3234 fputc ('\n', asm_out_file);
3237 return default_assemble_integer (x, size, aligned_p);
3240 /* Output an ascii string. */
3242 output_ascii (FILE *file, const char *p, int size)
3246 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3248 /* The HP assembler can only take strings of 256 characters at one
3249 time. This is a limitation on input line length, *not* the
3250 length of the string. Sigh. Even worse, it seems that the
3251 restriction is in number of input characters (see \xnn &
3252 \whatever). So we have to do this very carefully. */
3254 fputs ("\t.STRING \"", file);
3257 for (i = 0; i < size; i += 4)
3261 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3263 register unsigned int c = (unsigned char) p[i + io];
3265 if (c == '\"' || c == '\\')
3266 partial_output[co++] = '\\';
3267 if (c >= ' ' && c < 0177)
3268 partial_output[co++] = c;
3272 partial_output[co++] = '\\';
3273 partial_output[co++] = 'x';
3274 hexd = c / 16 - 0 + '0';
3276 hexd -= '9' - 'a' + 1;
3277 partial_output[co++] = hexd;
3278 hexd = c % 16 - 0 + '0';
3280 hexd -= '9' - 'a' + 1;
3281 partial_output[co++] = hexd;
3284 if (chars_output + co > 243)
3286 fputs ("\"\n\t.STRING \"", file);
3289 fwrite (partial_output, 1, (size_t) co, file);
3293 fputs ("\"\n", file);
3296 /* Try to rewrite floating point comparisons & branches to avoid
3297 useless add,tr insns.
3299 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3300 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3301 first attempt to remove useless add,tr insns. It is zero
3302 for the second pass as reorg sometimes leaves bogus REG_DEAD
3305 When CHECK_NOTES is zero we can only eliminate add,tr insns
3306 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3309 remove_useless_addtr_insns (int check_notes)
3312 static int pass = 0;
3314 /* This is fairly cheap, so always run it when optimizing. */
3318 int fbranch_count = 0;
3320 /* Walk all the insns in this function looking for fcmp & fbranch
3321 instructions. Keep track of how many of each we find. */
3322 for (insn = get_insns (); insn; insn = next_insn (insn))
3326 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3327 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3330 tmp = PATTERN (insn);
3332 /* It must be a set. */
3333 if (GET_CODE (tmp) != SET)
3336 /* If the destination is CCFP, then we've found an fcmp insn. */
3337 tmp = SET_DEST (tmp);
3338 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3344 tmp = PATTERN (insn);
3345 /* If this is an fbranch instruction, bump the fbranch counter. */
3346 if (GET_CODE (tmp) == SET
3347 && SET_DEST (tmp) == pc_rtx
3348 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3349 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3350 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3351 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3359 /* Find all floating point compare + branch insns. If possible,
3360 reverse the comparison & the branch to avoid add,tr insns. */
3361 for (insn = get_insns (); insn; insn = next_insn (insn))
3365 /* Ignore anything that isn't an INSN. */
3366 if (GET_CODE (insn) != INSN)
3369 tmp = PATTERN (insn);
3371 /* It must be a set. */
3372 if (GET_CODE (tmp) != SET)
3375 /* The destination must be CCFP, which is register zero. */
3376 tmp = SET_DEST (tmp);
3377 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3380 /* INSN should be a set of CCFP.
3382 See if the result of this insn is used in a reversed FP
3383 conditional branch. If so, reverse our condition and
3384 the branch. Doing so avoids useless add,tr insns. */
3385 next = next_insn (insn);
3388 /* Jumps, calls and labels stop our search. */
3389 if (GET_CODE (next) == JUMP_INSN
3390 || GET_CODE (next) == CALL_INSN
3391 || GET_CODE (next) == CODE_LABEL)
3394 /* As does another fcmp insn. */
3395 if (GET_CODE (next) == INSN
3396 && GET_CODE (PATTERN (next)) == SET
3397 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3398 && REGNO (SET_DEST (PATTERN (next))) == 0)
3401 next = next_insn (next);
3404 /* Is NEXT_INSN a branch? */
3406 && GET_CODE (next) == JUMP_INSN)
3408 rtx pattern = PATTERN (next);
3410 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3411 and CCFP dies, then reverse our conditional and the branch
3412 to avoid the add,tr. */
3413 if (GET_CODE (pattern) == SET
3414 && SET_DEST (pattern) == pc_rtx
3415 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3416 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3417 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3418 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3419 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3420 && (fcmp_count == fbranch_count
3422 && find_regno_note (next, REG_DEAD, 0))))
3424 /* Reverse the branch. */
3425 tmp = XEXP (SET_SRC (pattern), 1);
3426 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3427 XEXP (SET_SRC (pattern), 2) = tmp;
3428 INSN_CODE (next) = -1;
3430 /* Reverse our condition. */
3431 tmp = PATTERN (insn);
3432 PUT_CODE (XEXP (tmp, 1),
3433 (reverse_condition_maybe_unordered
3434 (GET_CODE (XEXP (tmp, 1)))));
3444 /* You may have trouble believing this, but this is the 32 bit HP-PA
3449 Variable arguments (optional; any number may be allocated)
3451 SP-(4*(N+9)) arg word N
3456 Fixed arguments (must be allocated; may remain unused)
3465 SP-32 External Data Pointer (DP)
3467 SP-24 External/stub RP (RP')
3471 SP-8 Calling Stub RP (RP'')
3476 SP-0 Stack Pointer (points to next available address)
3480 /* This function saves registers as follows. Registers marked with ' are
3481 this function's registers (as opposed to the previous function's).
3482 If a frame_pointer isn't needed, r4 is saved as a general register;
3483 the space for the frame pointer is still allocated, though, to keep
3489 SP (FP') Previous FP
3490 SP + 4 Alignment filler (sigh)
3491 SP + 8 Space for locals reserved here.
3495 SP + n All call saved register used.
3499 SP + o All call saved fp registers used.
3503 SP + p (SP') points to next available address.
3507 /* Global variables set by output_function_prologue(). */
3508 /* Size of frame. Need to know this to emit return insns from
3510 static HOST_WIDE_INT actual_fsize, local_fsize;
3511 static int save_fregs;
3513 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3514 Handle case where DISP > 8k by using the add_high_const patterns.
3516 Note in DISP > 8k case, we will leave the high part of the address
3517 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3520 store_reg (int reg, HOST_WIDE_INT disp, int base)
3522 rtx insn, dest, src, basereg;
3524 src = gen_rtx_REG (word_mode, reg);
3525 basereg = gen_rtx_REG (Pmode, base);
3526 if (VAL_14_BITS_P (disp))
3528 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3529 insn = emit_move_insn (dest, src);
3531 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3533 rtx delta = GEN_INT (disp);
3534 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3536 emit_move_insn (tmpreg, delta);
3537 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3540 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3541 gen_rtx_SET (VOIDmode, tmpreg,
3542 gen_rtx_PLUS (Pmode, basereg, delta)));
3543 RTX_FRAME_RELATED_P (insn) = 1;
3545 dest = gen_rtx_MEM (word_mode, tmpreg);
3546 insn = emit_move_insn (dest, src);
3550 rtx delta = GEN_INT (disp);
3551 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3552 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3554 emit_move_insn (tmpreg, high);
3555 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3556 insn = emit_move_insn (dest, src);
3558 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3559 gen_rtx_SET (VOIDmode,
3560 gen_rtx_MEM (word_mode,
3561 gen_rtx_PLUS (word_mode,
3568 RTX_FRAME_RELATED_P (insn) = 1;
3571 /* Emit RTL to store REG at the memory location specified by BASE and then
3572 add MOD to BASE. MOD must be <= 8k. */
3575 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3577 rtx insn, basereg, srcreg, delta;
3579 gcc_assert (VAL_14_BITS_P (mod));
3581 basereg = gen_rtx_REG (Pmode, base);
3582 srcreg = gen_rtx_REG (word_mode, reg);
3583 delta = GEN_INT (mod);
3585 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3588 RTX_FRAME_RELATED_P (insn) = 1;
3590 /* RTX_FRAME_RELATED_P must be set on each frame related set
3591 in a parallel with more than one element. */
3592 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3593 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3597 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3598 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3599 whether to add a frame note or not.
3601 In the DISP > 8k case, we leave the high part of the address in %r1.
3602 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3605 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3609 if (VAL_14_BITS_P (disp))
3611 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3612 plus_constant (gen_rtx_REG (Pmode, base), disp));
3614 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3616 rtx basereg = gen_rtx_REG (Pmode, base);
3617 rtx delta = GEN_INT (disp);
3618 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3620 emit_move_insn (tmpreg, delta);
3621 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3622 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3624 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3625 gen_rtx_SET (VOIDmode, tmpreg,
3626 gen_rtx_PLUS (Pmode, basereg, delta)));
3630 rtx basereg = gen_rtx_REG (Pmode, base);
3631 rtx delta = GEN_INT (disp);
3632 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3634 emit_move_insn (tmpreg,
3635 gen_rtx_PLUS (Pmode, basereg,
3636 gen_rtx_HIGH (Pmode, delta)));
3637 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3638 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3641 if (DO_FRAME_NOTES && note)
3642 RTX_FRAME_RELATED_P (insn) = 1;
3646 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3651 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3652 be consistent with the rounding and size calculation done here.
3653 Change them at the same time. */
3655 /* We do our own stack alignment. First, round the size of the
3656 stack locals up to a word boundary. */
3657 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3659 /* Space for previous frame pointer + filler. If any frame is
3660 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3661 waste some space here for the sake of HP compatibility. The
3662 first slot is only used when the frame pointer is needed. */
3663 if (size || frame_pointer_needed)
3664 size += STARTING_FRAME_OFFSET;
3666 /* If the current function calls __builtin_eh_return, then we need
3667 to allocate stack space for registers that will hold data for
3668 the exception handler. */
3669 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3673 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3675 size += i * UNITS_PER_WORD;
3678 /* Account for space used by the callee general register saves. */
3679 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3680 if (df_regs_ever_live_p (i))
3681 size += UNITS_PER_WORD;
3683 /* Account for space used by the callee floating point register saves. */
3684 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3685 if (df_regs_ever_live_p (i)
3686 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3690 /* We always save both halves of the FP register, so always
3691 increment the frame size by 8 bytes. */
3695 /* If any of the floating registers are saved, account for the
3696 alignment needed for the floating point register save block. */
3699 size = (size + 7) & ~7;
3704 /* The various ABIs include space for the outgoing parameters in the
3705 size of the current function's stack frame. We don't need to align
3706 for the outgoing arguments as their alignment is set by the final
3707 rounding for the frame as a whole. */
3708 size += crtl->outgoing_args_size;
3710 /* Allocate space for the fixed frame marker. This space must be
3711 allocated for any function that makes calls or allocates
3713 if (!current_function_is_leaf || size)
3714 size += TARGET_64BIT ? 48 : 32;
3716 /* Finally, round to the preferred stack boundary. */
3717 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3718 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3721 /* Generate the assembly code for function entry. FILE is a stdio
3722 stream to output the code to. SIZE is an int: how many units of
3723 temporary storage to allocate.
3725 Refer to the array `regs_ever_live' to determine which registers to
3726 save; `regs_ever_live[I]' is nonzero if register number I is ever
3727 used in the function. This function is responsible for knowing
3728 which registers should not be saved even if used. */
3730 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3731 of memory. If any fpu reg is used in the function, we allocate
3732 such a block here, at the bottom of the frame, just in case it's needed.
3734 If this function is a leaf procedure, then we may choose not
3735 to do a "save" insn. The decision about whether or not
3736 to do this is made in regclass.c. */
3739 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3741 /* The function's label and associated .PROC must never be
3742 separated and must be output *after* any profiling declarations
3743 to avoid changing spaces/subspaces within a procedure. */
3744 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3745 fputs ("\t.PROC\n", file);
3747 /* hppa_expand_prologue does the dirty work now. We just need
3748 to output the assembler directives which denote the start
3750 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3751 if (current_function_is_leaf)
3752 fputs (",NO_CALLS", file);
3754 fputs (",CALLS", file);
3756 fputs (",SAVE_RP", file);
3758 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3759 at the beginning of the frame and that it is used as the frame
3760 pointer for the frame. We do this because our current frame
3761 layout doesn't conform to that specified in the HP runtime
3762 documentation and we need a way to indicate to programs such as
3763 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3764 isn't used by HP compilers but is supported by the assembler.
3765 However, SAVE_SP is supposed to indicate that the previous stack
3766 pointer has been saved in the frame marker. */
3767 if (frame_pointer_needed)
3768 fputs (",SAVE_SP", file);
3770 /* Pass on information about the number of callee register saves
3771 performed in the prologue.
3773 The compiler is supposed to pass the highest register number
3774 saved, the assembler then has to adjust that number before
3775 entering it into the unwind descriptor (to account for any
3776 caller saved registers with lower register numbers than the
3777 first callee saved register). */
3779 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3782 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3784 fputs ("\n\t.ENTRY\n", file);
3786 remove_useless_addtr_insns (0);
3790 hppa_expand_prologue (void)
3792 int merge_sp_adjust_with_store = 0;
3793 HOST_WIDE_INT size = get_frame_size ();
3794 HOST_WIDE_INT offset;
3802 /* Compute total size for frame pointer, filler, locals and rounding to
3803 the next word boundary. Similar code appears in compute_frame_size
3804 and must be changed in tandem with this code. */
3805 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3806 if (local_fsize || frame_pointer_needed)
3807 local_fsize += STARTING_FRAME_OFFSET;
3809 actual_fsize = compute_frame_size (size, &save_fregs);
3810 if (flag_stack_usage)
3811 current_function_static_stack_size = actual_fsize;
3813 /* Compute a few things we will use often. */
3814 tmpreg = gen_rtx_REG (word_mode, 1);
3816 /* Save RP first. The calling conventions manual states RP will
3817 always be stored into the caller's frame at sp - 20 or sp - 16
3818 depending on which ABI is in use. */
3819 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3821 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3827 /* Allocate the local frame and set up the frame pointer if needed. */
3828 if (actual_fsize != 0)
3830 if (frame_pointer_needed)
3832 /* Copy the old frame pointer temporarily into %r1. Set up the
3833 new stack pointer, then store away the saved old frame pointer
3834 into the stack at sp and at the same time update the stack
3835 pointer by actual_fsize bytes. Two versions, first
3836 handles small (<8k) frames. The second handles large (>=8k)
3838 insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx);
3840 RTX_FRAME_RELATED_P (insn) = 1;
3842 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3844 RTX_FRAME_RELATED_P (insn) = 1;
3846 if (VAL_14_BITS_P (actual_fsize))
3847 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3850 /* It is incorrect to store the saved frame pointer at *sp,
3851 then increment sp (writes beyond the current stack boundary).
3853 So instead use stwm to store at *sp and post-increment the
3854 stack pointer as an atomic operation. Then increment sp to
3855 finish allocating the new frame. */
3856 HOST_WIDE_INT adjust1 = 8192 - 64;
3857 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3859 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3860 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3864 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3865 we need to store the previous stack pointer (frame pointer)
3866 into the frame marker on targets that use the HP unwind
3867 library. This allows the HP unwind library to be used to
3868 unwind GCC frames. However, we are not fully compatible
3869 with the HP library because our frame layout differs from
3870 that specified in the HP runtime specification.
3872 We don't want a frame note on this instruction as the frame
3873 marker moves during dynamic stack allocation.
3875 This instruction also serves as a blockage to prevent
3876 register spills from being scheduled before the stack
3877 pointer is raised. This is necessary as we store
3878 registers using the frame pointer as a base register,
3879 and the frame pointer is set before sp is raised. */
3880 if (TARGET_HPUX_UNWIND_LIBRARY)
3882 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3883 GEN_INT (TARGET_64BIT ? -8 : -4));
3885 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3886 hard_frame_pointer_rtx);
3889 emit_insn (gen_blockage ());
3891 /* no frame pointer needed. */
3894 /* In some cases we can perform the first callee register save
3895 and allocating the stack frame at the same time. If so, just
3896 make a note of it and defer allocating the frame until saving
3897 the callee registers. */
3898 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3899 merge_sp_adjust_with_store = 1;
3900 /* Can not optimize. Adjust the stack frame by actual_fsize
3903 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3908 /* Normal register save.
3910 Do not save the frame pointer in the frame_pointer_needed case. It
3911 was done earlier. */
3912 if (frame_pointer_needed)
3914 offset = local_fsize;
3916 /* Saving the EH return data registers in the frame is the simplest
3917 way to get the frame unwind information emitted. We put them
3918 just before the general registers. */
3919 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3921 unsigned int i, regno;
3925 regno = EH_RETURN_DATA_REGNO (i);
3926 if (regno == INVALID_REGNUM)
3929 store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
3930 offset += UNITS_PER_WORD;
3934 for (i = 18; i >= 4; i--)
3935 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3937 store_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
3938 offset += UNITS_PER_WORD;
3941 /* Account for %r3 which is saved in a special place. */
3944 /* No frame pointer needed. */
3947 offset = local_fsize - actual_fsize;
3949 /* Saving the EH return data registers in the frame is the simplest
3950 way to get the frame unwind information emitted. */
3951 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3953 unsigned int i, regno;
3957 regno = EH_RETURN_DATA_REGNO (i);
3958 if (regno == INVALID_REGNUM)
3961 /* If merge_sp_adjust_with_store is nonzero, then we can
3962 optimize the first save. */
3963 if (merge_sp_adjust_with_store)
3965 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3966 merge_sp_adjust_with_store = 0;
3969 store_reg (regno, offset, STACK_POINTER_REGNUM);
3970 offset += UNITS_PER_WORD;
3974 for (i = 18; i >= 3; i--)
3975 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3977 /* If merge_sp_adjust_with_store is nonzero, then we can
3978 optimize the first GR save. */
3979 if (merge_sp_adjust_with_store)
3981 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3982 merge_sp_adjust_with_store = 0;
3985 store_reg (i, offset, STACK_POINTER_REGNUM);
3986 offset += UNITS_PER_WORD;
3990 /* If we wanted to merge the SP adjustment with a GR save, but we never
3991 did any GR saves, then just emit the adjustment here. */
3992 if (merge_sp_adjust_with_store)
3993 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3997 /* The hppa calling conventions say that %r19, the pic offset
3998 register, is saved at sp - 32 (in this function's frame)
3999 when generating PIC code. FIXME: What is the correct thing
4000 to do for functions which make no calls and allocate no
4001 frame? Do we need to allocate a frame, or can we just omit
4002 the save? For now we'll just omit the save.
4004 We don't want a note on this insn as the frame marker can
4005 move if there is a dynamic stack allocation. */
4006 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4008 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4010 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4014 /* Align pointer properly (doubleword boundary). */
4015 offset = (offset + 7) & ~7;
4017 /* Floating point register store. */
4022 /* First get the frame or stack pointer to the start of the FP register
4024 if (frame_pointer_needed)
4026 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4027 base = hard_frame_pointer_rtx;
4031 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4032 base = stack_pointer_rtx;
4035 /* Now actually save the FP registers. */
4036 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4038 if (df_regs_ever_live_p (i)
4039 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4041 rtx addr, insn, reg;
4042 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4043 reg = gen_rtx_REG (DFmode, i);
4044 insn = emit_move_insn (addr, reg);
4047 RTX_FRAME_RELATED_P (insn) = 1;
4050 rtx mem = gen_rtx_MEM (DFmode,
4051 plus_constant (base, offset));
4052 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4053 gen_rtx_SET (VOIDmode, mem, reg));
4057 rtx meml = gen_rtx_MEM (SFmode,
4058 plus_constant (base, offset));
4059 rtx memr = gen_rtx_MEM (SFmode,
4060 plus_constant (base, offset + 4));
4061 rtx regl = gen_rtx_REG (SFmode, i);
4062 rtx regr = gen_rtx_REG (SFmode, i + 1);
4063 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4064 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4067 RTX_FRAME_RELATED_P (setl) = 1;
4068 RTX_FRAME_RELATED_P (setr) = 1;
4069 vec = gen_rtvec (2, setl, setr);
4070 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4071 gen_rtx_SEQUENCE (VOIDmode, vec));
4074 offset += GET_MODE_SIZE (DFmode);
4081 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4082 Handle case where DISP > 8k by using the add_high_const patterns. */
4085 load_reg (int reg, HOST_WIDE_INT disp, int base)
4087 rtx dest = gen_rtx_REG (word_mode, reg);
4088 rtx basereg = gen_rtx_REG (Pmode, base);
4091 if (VAL_14_BITS_P (disp))
4092 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4093 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4095 rtx delta = GEN_INT (disp);
4096 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4098 emit_move_insn (tmpreg, delta);
4099 if (TARGET_DISABLE_INDEXING)
4101 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4102 src = gen_rtx_MEM (word_mode, tmpreg);
4105 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4109 rtx delta = GEN_INT (disp);
4110 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4111 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4113 emit_move_insn (tmpreg, high);
4114 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4117 emit_move_insn (dest, src);
4120 /* Update the total code bytes output to the text section. */
4123 update_total_code_bytes (unsigned int nbytes)
4125 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4126 && !IN_NAMED_SECTION_P (cfun->decl))
4128 unsigned int old_total = total_code_bytes;
4130 total_code_bytes += nbytes;
4132 /* Be prepared to handle overflows. */
4133 if (old_total > total_code_bytes)
4134 total_code_bytes = UINT_MAX;
4138 /* This function generates the assembly code for function exit.
4139 Args are as for output_function_prologue ().
4141 The function epilogue should not depend on the current stack
4142 pointer! It should use the frame pointer only. This is mandatory
4143 because of alloca; we also take advantage of it to omit stack
4144 adjustments before returning. */
4147 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4149 rtx insn = get_last_insn ();
4153 /* hppa_expand_epilogue does the dirty work now. We just need
4154 to output the assembler directives which denote the end
4157 To make debuggers happy, emit a nop if the epilogue was completely
4158 eliminated due to a volatile call as the last insn in the
4159 current function. That way the return address (in %r2) will
4160 always point to a valid instruction in the current function. */
4162 /* Get the last real insn. */
4163 if (GET_CODE (insn) == NOTE)
4164 insn = prev_real_insn (insn);
4166 /* If it is a sequence, then look inside. */
4167 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4168 insn = XVECEXP (PATTERN (insn), 0, 0);
4170 /* If insn is a CALL_INSN, then it must be a call to a volatile
4171 function (otherwise there would be epilogue insns). */
4172 if (insn && GET_CODE (insn) == CALL_INSN)
4174 fputs ("\tnop\n", file);
4178 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4180 if (TARGET_SOM && TARGET_GAS)
4182 /* We done with this subspace except possibly for some additional
4183 debug information. Forget that we are in this subspace to ensure
4184 that the next function is output in its own subspace. */
4186 cfun->machine->in_nsubspa = 2;
4189 if (INSN_ADDRESSES_SET_P ())
4191 insn = get_last_nonnote_insn ();
4192 last_address += INSN_ADDRESSES (INSN_UID (insn));
4194 last_address += insn_default_length (insn);
4195 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4196 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4199 last_address = UINT_MAX;
4201 /* Finally, update the total number of code bytes output so far. */
4202 update_total_code_bytes (last_address);
4206 hppa_expand_epilogue (void)
4209 HOST_WIDE_INT offset;
4210 HOST_WIDE_INT ret_off = 0;
4212 int merge_sp_adjust_with_load = 0;
4214 /* We will use this often. */
4215 tmpreg = gen_rtx_REG (word_mode, 1);
4217 /* Try to restore RP early to avoid load/use interlocks when
4218 RP gets used in the return (bv) instruction. This appears to still
4219 be necessary even when we schedule the prologue and epilogue. */
4222 ret_off = TARGET_64BIT ? -16 : -20;
4223 if (frame_pointer_needed)
4225 load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM);
4230 /* No frame pointer, and stack is smaller than 8k. */
4231 if (VAL_14_BITS_P (ret_off - actual_fsize))
4233 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4239 /* General register restores. */
4240 if (frame_pointer_needed)
4242 offset = local_fsize;
4244 /* If the current function calls __builtin_eh_return, then we need
4245 to restore the saved EH data registers. */
4246 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4248 unsigned int i, regno;
4252 regno = EH_RETURN_DATA_REGNO (i);
4253 if (regno == INVALID_REGNUM)
4256 load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
4257 offset += UNITS_PER_WORD;
4261 for (i = 18; i >= 4; i--)
4262 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4264 load_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
4265 offset += UNITS_PER_WORD;
4270 offset = local_fsize - actual_fsize;
4272 /* If the current function calls __builtin_eh_return, then we need
4273 to restore the saved EH data registers. */
4274 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4276 unsigned int i, regno;
4280 regno = EH_RETURN_DATA_REGNO (i);
4281 if (regno == INVALID_REGNUM)
4284 /* Only for the first load.
4285 merge_sp_adjust_with_load holds the register load
4286 with which we will merge the sp adjustment. */
4287 if (merge_sp_adjust_with_load == 0
4289 && VAL_14_BITS_P (-actual_fsize))
4290 merge_sp_adjust_with_load = regno;
4292 load_reg (regno, offset, STACK_POINTER_REGNUM);
4293 offset += UNITS_PER_WORD;
4297 for (i = 18; i >= 3; i--)
4299 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4301 /* Only for the first load.
4302 merge_sp_adjust_with_load holds the register load
4303 with which we will merge the sp adjustment. */
4304 if (merge_sp_adjust_with_load == 0
4306 && VAL_14_BITS_P (-actual_fsize))
4307 merge_sp_adjust_with_load = i;
4309 load_reg (i, offset, STACK_POINTER_REGNUM);
4310 offset += UNITS_PER_WORD;
4315 /* Align pointer properly (doubleword boundary). */
4316 offset = (offset + 7) & ~7;
4318 /* FP register restores. */
4321 /* Adjust the register to index off of. */
4322 if (frame_pointer_needed)
4323 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4325 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4327 /* Actually do the restores now. */
4328 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4329 if (df_regs_ever_live_p (i)
4330 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4332 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4333 rtx dest = gen_rtx_REG (DFmode, i);
4334 emit_move_insn (dest, src);
4338 /* Emit a blockage insn here to keep these insns from being moved to
4339 an earlier spot in the epilogue, or into the main instruction stream.
4341 This is necessary as we must not cut the stack back before all the
4342 restores are finished. */
4343 emit_insn (gen_blockage ());
4345 /* Reset stack pointer (and possibly frame pointer). The stack
4346 pointer is initially set to fp + 64 to avoid a race condition. */
4347 if (frame_pointer_needed)
4349 rtx delta = GEN_INT (-64);
4351 set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0);
4352 emit_insn (gen_pre_load (hard_frame_pointer_rtx,
4353 stack_pointer_rtx, delta));
4355 /* If we were deferring a callee register restore, do it now. */
4356 else if (merge_sp_adjust_with_load)
4358 rtx delta = GEN_INT (-actual_fsize);
4359 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4361 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4363 else if (actual_fsize != 0)
4364 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4367 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4368 frame greater than 8k), do so now. */
4370 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4372 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4374 rtx sa = EH_RETURN_STACKADJ_RTX;
4376 emit_insn (gen_blockage ());
4377 emit_insn (TARGET_64BIT
4378 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4379 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4384 hppa_pic_save_rtx (void)
4386 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4389 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4390 #define NO_DEFERRED_PROFILE_COUNTERS 0
4394 /* Vector of funcdef numbers. */
4395 static VEC(int,heap) *funcdef_nos;
4397 /* Output deferred profile counters. */
4399 output_deferred_profile_counters (void)
4404 if (VEC_empty (int, funcdef_nos))
4407 switch_to_section (data_section);
4408 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4409 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4411 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4413 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4414 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4417 VEC_free (int, heap, funcdef_nos);
4421 hppa_profile_hook (int label_no)
4423 /* We use SImode for the address of the function in both 32 and
4424 64-bit code to avoid having to provide DImode versions of the
4425 lcla2 and load_offset_label_address insn patterns. */
4426 rtx reg = gen_reg_rtx (SImode);
4427 rtx label_rtx = gen_label_rtx ();
4428 rtx begin_label_rtx, call_insn;
4429 char begin_label_name[16];
4431 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4433 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4436 emit_move_insn (arg_pointer_rtx,
4437 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4440 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4442 /* The address of the function is loaded into %r25 with an instruction-
4443 relative sequence that avoids the use of relocations. The sequence
4444 is split so that the load_offset_label_address instruction can
4445 occupy the delay slot of the call to _mcount. */
4447 emit_insn (gen_lcla2 (reg, label_rtx));
4449 emit_insn (gen_lcla1 (reg, label_rtx));
4451 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4452 reg, begin_label_rtx, label_rtx));
4454 #if !NO_DEFERRED_PROFILE_COUNTERS
4456 rtx count_label_rtx, addr, r24;
4457 char count_label_name[16];
4459 VEC_safe_push (int, heap, funcdef_nos, label_no);
4460 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4461 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4463 addr = force_reg (Pmode, count_label_rtx);
4464 r24 = gen_rtx_REG (Pmode, 24);
4465 emit_move_insn (r24, addr);
4468 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4469 gen_rtx_SYMBOL_REF (Pmode,
4471 GEN_INT (TARGET_64BIT ? 24 : 12)));
4473 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4478 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4479 gen_rtx_SYMBOL_REF (Pmode,
4481 GEN_INT (TARGET_64BIT ? 16 : 8)));
4485 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4486 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4488 /* Indicate the _mcount call cannot throw, nor will it execute a
4490 make_reg_eh_region_note_nothrow_nononlocal (call_insn);
4493 /* Fetch the return address for the frame COUNT steps up from
4494 the current frame, after the prologue. FRAMEADDR is the
4495 frame pointer of the COUNT frame.
4497 We want to ignore any export stub remnants here. To handle this,
4498 we examine the code at the return address, and if it is an export
4499 stub, we return a memory rtx for the stub return address stored
4502 The value returned is used in two different ways:
4504 1. To find a function's caller.
4506 2. To change the return address for a function.
4508 This function handles most instances of case 1; however, it will
4509 fail if there are two levels of stubs to execute on the return
4510 path. The only way I believe that can happen is if the return value
4511 needs a parameter relocation, which never happens for C code.
4513 This function handles most instances of case 2; however, it will
4514 fail if we did not originally have stub code on the return path
4515 but will need stub code on the new return path. This can happen if
4516 the caller & callee are both in the main program, but the new
4517 return location is in a shared library. */
4520 return_addr_rtx (int count, rtx frameaddr)
4527 /* Instruction stream at the normal return address for the export stub:
4529 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4530 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4531 0x00011820 | stub+16: mtsp r1,sr0
4532 0xe0400002 | stub+20: be,n 0(sr0,rp)
4534 0xe0400002 must be specified as -532676606 so that it won't be
4535 rejected as an invalid immediate operand on 64-bit hosts. */
4537 HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606};
4543 rp = get_hard_reg_initial_val (Pmode, 2);
4545 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4548 /* If there is no export stub then just use the value saved from
4549 the return pointer register. */
4551 saved_rp = gen_reg_rtx (Pmode);
4552 emit_move_insn (saved_rp, rp);
4554 /* Get pointer to the instruction stream. We have to mask out the
4555 privilege level from the two low order bits of the return address
4556 pointer here so that ins will point to the start of the first
4557 instruction that would have been executed if we returned. */
4558 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4559 label = gen_label_rtx ();
4561 /* Check the instruction stream at the normal return address for the
4562 export stub. If it is an export stub, than our return address is
4563 really in -24[frameaddr]. */
4565 for (i = 0; i < 3; i++)
4567 rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4));
4568 rtx op1 = GEN_INT (insns[i]);
4569 emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label);
4572 /* Here we know that our return address points to an export
4573 stub. We don't want to return the address of the export stub,
4574 but rather the return address of the export stub. That return
4575 address is stored at -24[frameaddr]. */
4577 emit_move_insn (saved_rp,
4579 memory_address (Pmode,
4580 plus_constant (frameaddr,
4589 emit_bcond_fp (rtx operands[])
4591 enum rtx_code code = GET_CODE (operands[0]);
4592 rtx operand0 = operands[1];
4593 rtx operand1 = operands[2];
4594 rtx label = operands[3];
4596 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4597 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)));
4599 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4600 gen_rtx_IF_THEN_ELSE (VOIDmode,
4603 gen_rtx_REG (CCFPmode, 0),
4605 gen_rtx_LABEL_REF (VOIDmode, label),
4610 /* Adjust the cost of a scheduling dependency. Return the new cost of
4611 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4614 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4616 enum attr_type attr_type;
4618 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4619 true dependencies as they are described with bypasses now. */
4620 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4623 if (! recog_memoized (insn))
4626 attr_type = get_attr_type (insn);
4628 switch (REG_NOTE_KIND (link))
4631 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4634 if (attr_type == TYPE_FPLOAD)
4636 rtx pat = PATTERN (insn);
4637 rtx dep_pat = PATTERN (dep_insn);
4638 if (GET_CODE (pat) == PARALLEL)
4640 /* This happens for the fldXs,mb patterns. */
4641 pat = XVECEXP (pat, 0, 0);
4643 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4644 /* If this happens, we have to extend this to schedule
4645 optimally. Return 0 for now. */
4648 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4650 if (! recog_memoized (dep_insn))
4652 switch (get_attr_type (dep_insn))
4659 case TYPE_FPSQRTSGL:
4660 case TYPE_FPSQRTDBL:
4661 /* A fpload can't be issued until one cycle before a
4662 preceding arithmetic operation has finished if
4663 the target of the fpload is any of the sources
4664 (or destination) of the arithmetic operation. */
4665 return insn_default_latency (dep_insn) - 1;
4672 else if (attr_type == TYPE_FPALU)
4674 rtx pat = PATTERN (insn);
4675 rtx dep_pat = PATTERN (dep_insn);
4676 if (GET_CODE (pat) == PARALLEL)
4678 /* This happens for the fldXs,mb patterns. */
4679 pat = XVECEXP (pat, 0, 0);
4681 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4682 /* If this happens, we have to extend this to schedule
4683 optimally. Return 0 for now. */
4686 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4688 if (! recog_memoized (dep_insn))
4690 switch (get_attr_type (dep_insn))
4694 case TYPE_FPSQRTSGL:
4695 case TYPE_FPSQRTDBL:
4696 /* An ALU flop can't be issued until two cycles before a
4697 preceding divide or sqrt operation has finished if
4698 the target of the ALU flop is any of the sources
4699 (or destination) of the divide or sqrt operation. */
4700 return insn_default_latency (dep_insn) - 2;
4708 /* For other anti dependencies, the cost is 0. */
4711 case REG_DEP_OUTPUT:
4712 /* Output dependency; DEP_INSN writes a register that INSN writes some
4714 if (attr_type == TYPE_FPLOAD)
4716 rtx pat = PATTERN (insn);
4717 rtx dep_pat = PATTERN (dep_insn);
4718 if (GET_CODE (pat) == PARALLEL)
4720 /* This happens for the fldXs,mb patterns. */
4721 pat = XVECEXP (pat, 0, 0);
4723 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4724 /* If this happens, we have to extend this to schedule
4725 optimally. Return 0 for now. */
4728 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4730 if (! recog_memoized (dep_insn))
4732 switch (get_attr_type (dep_insn))
4739 case TYPE_FPSQRTSGL:
4740 case TYPE_FPSQRTDBL:
4741 /* A fpload can't be issued until one cycle before a
4742 preceding arithmetic operation has finished if
4743 the target of the fpload is the destination of the
4744 arithmetic operation.
4746 Exception: For PA7100LC, PA7200 and PA7300, the cost
4747 is 3 cycles, unless they bundle together. We also
4748 pay the penalty if the second insn is a fpload. */
4749 return insn_default_latency (dep_insn) - 1;
4756 else if (attr_type == TYPE_FPALU)
4758 rtx pat = PATTERN (insn);
4759 rtx dep_pat = PATTERN (dep_insn);
4760 if (GET_CODE (pat) == PARALLEL)
4762 /* This happens for the fldXs,mb patterns. */
4763 pat = XVECEXP (pat, 0, 0);
4765 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4766 /* If this happens, we have to extend this to schedule
4767 optimally. Return 0 for now. */
4770 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4772 if (! recog_memoized (dep_insn))
4774 switch (get_attr_type (dep_insn))
4778 case TYPE_FPSQRTSGL:
4779 case TYPE_FPSQRTDBL:
4780 /* An ALU flop can't be issued until two cycles before a
4781 preceding divide or sqrt operation has finished if
4782 the target of the ALU flop is also the target of
4783 the divide or sqrt operation. */
4784 return insn_default_latency (dep_insn) - 2;
4792 /* For other output dependencies, the cost is 0. */
4800 /* Adjust scheduling priorities. We use this to try and keep addil
4801 and the next use of %r1 close together. */
4803 pa_adjust_priority (rtx insn, int priority)
4805 rtx set = single_set (insn);
4809 src = SET_SRC (set);
4810 dest = SET_DEST (set);
4811 if (GET_CODE (src) == LO_SUM
4812 && symbolic_operand (XEXP (src, 1), VOIDmode)
4813 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4816 else if (GET_CODE (src) == MEM
4817 && GET_CODE (XEXP (src, 0)) == LO_SUM
4818 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4819 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4822 else if (GET_CODE (dest) == MEM
4823 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4824 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4825 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4831 /* The 700 can only issue a single insn at a time.
4832 The 7XXX processors can issue two insns at a time.
4833 The 8000 can issue 4 insns at a time. */
4835 pa_issue_rate (void)
4839 case PROCESSOR_700: return 1;
4840 case PROCESSOR_7100: return 2;
4841 case PROCESSOR_7100LC: return 2;
4842 case PROCESSOR_7200: return 2;
4843 case PROCESSOR_7300: return 2;
4844 case PROCESSOR_8000: return 4;
4853 /* Return any length adjustment needed by INSN which already has its length
4854 computed as LENGTH. Return zero if no adjustment is necessary.
4856 For the PA: function calls, millicode calls, and backwards short
4857 conditional branches with unfilled delay slots need an adjustment by +1
4858 (to account for the NOP which will be inserted into the instruction stream).
4860 Also compute the length of an inline block move here as it is too
4861 complicated to express as a length attribute in pa.md. */
4863 pa_adjust_insn_length (rtx insn, int length)
4865 rtx pat = PATTERN (insn);
4867 /* Jumps inside switch tables which have unfilled delay slots need
4869 if (GET_CODE (insn) == JUMP_INSN
4870 && GET_CODE (pat) == PARALLEL
4871 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4873 /* Millicode insn with an unfilled delay slot. */
4874 else if (GET_CODE (insn) == INSN
4875 && GET_CODE (pat) != SEQUENCE
4876 && GET_CODE (pat) != USE
4877 && GET_CODE (pat) != CLOBBER
4878 && get_attr_type (insn) == TYPE_MILLI)
4880 /* Block move pattern. */
4881 else if (GET_CODE (insn) == INSN
4882 && GET_CODE (pat) == PARALLEL
4883 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4884 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4885 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4886 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4887 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4888 return compute_movmem_length (insn) - 4;
4889 /* Block clear pattern. */
4890 else if (GET_CODE (insn) == INSN
4891 && GET_CODE (pat) == PARALLEL
4892 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4893 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4894 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4895 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4896 return compute_clrmem_length (insn) - 4;
4897 /* Conditional branch with an unfilled delay slot. */
4898 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4900 /* Adjust a short backwards conditional with an unfilled delay slot. */
4901 if (GET_CODE (pat) == SET
4903 && JUMP_LABEL (insn) != NULL_RTX
4904 && ! forward_branch_p (insn))
4906 else if (GET_CODE (pat) == PARALLEL
4907 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4910 /* Adjust dbra insn with short backwards conditional branch with
4911 unfilled delay slot -- only for case where counter is in a
4912 general register register. */
4913 else if (GET_CODE (pat) == PARALLEL
4914 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4915 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4916 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4918 && ! forward_branch_p (insn))
4926 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
4929 pa_print_operand_punct_valid_p (unsigned char code)
4940 /* Print operand X (an rtx) in assembler syntax to file FILE.
4941 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4942 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4945 print_operand (FILE *file, rtx x, int code)
4950 /* Output a 'nop' if there's nothing for the delay slot. */
4951 if (dbr_sequence_length () == 0)
4952 fputs ("\n\tnop", file);
4955 /* Output a nullification completer if there's nothing for the */
4956 /* delay slot or nullification is requested. */
4957 if (dbr_sequence_length () == 0 ||
4959 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4963 /* Print out the second register name of a register pair.
4964 I.e., R (6) => 7. */
4965 fputs (reg_names[REGNO (x) + 1], file);
4968 /* A register or zero. */
4970 || (x == CONST0_RTX (DFmode))
4971 || (x == CONST0_RTX (SFmode)))
4973 fputs ("%r0", file);
4979 /* A register or zero (floating point). */
4981 || (x == CONST0_RTX (DFmode))
4982 || (x == CONST0_RTX (SFmode)))
4984 fputs ("%fr0", file);
4993 xoperands[0] = XEXP (XEXP (x, 0), 0);
4994 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4995 output_global_address (file, xoperands[1], 0);
4996 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5000 case 'C': /* Plain (C)ondition */
5002 switch (GET_CODE (x))
5005 fputs ("=", file); break;
5007 fputs ("<>", file); break;
5009 fputs (">", file); break;
5011 fputs (">=", file); break;
5013 fputs (">>=", file); break;
5015 fputs (">>", file); break;
5017 fputs ("<", file); break;
5019 fputs ("<=", file); break;
5021 fputs ("<<=", file); break;
5023 fputs ("<<", file); break;
5028 case 'N': /* Condition, (N)egated */
5029 switch (GET_CODE (x))
5032 fputs ("<>", file); break;
5034 fputs ("=", file); break;
5036 fputs ("<=", file); break;
5038 fputs ("<", file); break;
5040 fputs ("<<", file); break;
5042 fputs ("<<=", file); break;
5044 fputs (">=", file); break;
5046 fputs (">", file); break;
5048 fputs (">>", file); break;
5050 fputs (">>=", file); break;
5055 /* For floating point comparisons. Note that the output
5056 predicates are the complement of the desired mode. The
5057 conditions for GT, GE, LT, LE and LTGT cause an invalid
5058 operation exception if the result is unordered and this
5059 exception is enabled in the floating-point status register. */
5061 switch (GET_CODE (x))
5064 fputs ("!=", file); break;
5066 fputs ("=", file); break;
5068 fputs ("!>", file); break;
5070 fputs ("!>=", file); break;
5072 fputs ("!<", file); break;
5074 fputs ("!<=", file); break;
5076 fputs ("!<>", file); break;
5078 fputs ("!?<=", file); break;
5080 fputs ("!?<", file); break;
5082 fputs ("!?>=", file); break;
5084 fputs ("!?>", file); break;
5086 fputs ("!?=", file); break;
5088 fputs ("!?", file); break;
5090 fputs ("?", file); break;
5095 case 'S': /* Condition, operands are (S)wapped. */
5096 switch (GET_CODE (x))
5099 fputs ("=", file); break;
5101 fputs ("<>", file); break;
5103 fputs ("<", file); break;
5105 fputs ("<=", file); break;
5107 fputs ("<<=", file); break;
5109 fputs ("<<", file); break;
5111 fputs (">", file); break;
5113 fputs (">=", file); break;
5115 fputs (">>=", file); break;
5117 fputs (">>", file); break;
5122 case 'B': /* Condition, (B)oth swapped and negate. */
5123 switch (GET_CODE (x))
5126 fputs ("<>", file); break;
5128 fputs ("=", file); break;
5130 fputs (">=", file); break;
5132 fputs (">", file); break;
5134 fputs (">>", file); break;
5136 fputs (">>=", file); break;
5138 fputs ("<=", file); break;
5140 fputs ("<", file); break;
5142 fputs ("<<", file); break;
5144 fputs ("<<=", file); break;
5150 gcc_assert (GET_CODE (x) == CONST_INT);
5151 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5154 gcc_assert (GET_CODE (x) == CONST_INT);
5155 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5158 gcc_assert (GET_CODE (x) == CONST_INT);
5159 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5162 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5163 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5166 gcc_assert (GET_CODE (x) == CONST_INT);
5167 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5170 gcc_assert (GET_CODE (x) == CONST_INT);
5171 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5174 if (GET_CODE (x) == CONST_INT)
5179 switch (GET_CODE (XEXP (x, 0)))
5183 if (ASSEMBLER_DIALECT == 0)
5184 fputs ("s,mb", file);
5186 fputs (",mb", file);
5190 if (ASSEMBLER_DIALECT == 0)
5191 fputs ("s,ma", file);
5193 fputs (",ma", file);
5196 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5197 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5199 if (ASSEMBLER_DIALECT == 0)
5202 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5203 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5205 if (ASSEMBLER_DIALECT == 0)
5206 fputs ("x,s", file);
5210 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5214 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5220 output_global_address (file, x, 0);
5223 output_global_address (file, x, 1);
5225 case 0: /* Don't do anything special */
5230 compute_zdepwi_operands (INTVAL (x), op);
5231 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5237 compute_zdepdi_operands (INTVAL (x), op);
5238 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5242 /* We can get here from a .vtable_inherit due to our
5243 CONSTANT_ADDRESS_P rejecting perfectly good constant
5249 if (GET_CODE (x) == REG)
5251 fputs (reg_names [REGNO (x)], file);
5252 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5258 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5259 && (REGNO (x) & 1) == 0)
5262 else if (GET_CODE (x) == MEM)
5264 int size = GET_MODE_SIZE (GET_MODE (x));
5265 rtx base = NULL_RTX;
5266 switch (GET_CODE (XEXP (x, 0)))
5270 base = XEXP (XEXP (x, 0), 0);
5271 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5275 base = XEXP (XEXP (x, 0), 0);
5276 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5279 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5280 fprintf (file, "%s(%s)",
5281 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5282 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5283 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5284 fprintf (file, "%s(%s)",
5285 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5286 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5287 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5288 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5290 /* Because the REG_POINTER flag can get lost during reload,
5291 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5292 index and base registers in the combined move patterns. */
5293 rtx base = XEXP (XEXP (x, 0), 1);
5294 rtx index = XEXP (XEXP (x, 0), 0);
5296 fprintf (file, "%s(%s)",
5297 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5300 output_address (XEXP (x, 0));
5303 output_address (XEXP (x, 0));
5308 output_addr_const (file, x);
5311 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5314 output_global_address (FILE *file, rtx x, int round_constant)
5317 /* Imagine (high (const (plus ...))). */
5318 if (GET_CODE (x) == HIGH)
5321 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5322 output_addr_const (file, x);
5323 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5325 output_addr_const (file, x);
5326 fputs ("-$global$", file);
5328 else if (GET_CODE (x) == CONST)
5330 const char *sep = "";
5331 int offset = 0; /* assembler wants -$global$ at end */
5332 rtx base = NULL_RTX;
5334 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5337 base = XEXP (XEXP (x, 0), 0);
5338 output_addr_const (file, base);
5341 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5347 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5350 base = XEXP (XEXP (x, 0), 1);
5351 output_addr_const (file, base);
5354 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5360 /* How bogus. The compiler is apparently responsible for
5361 rounding the constant if it uses an LR field selector.
5363 The linker and/or assembler seem a better place since
5364 they have to do this kind of thing already.
5366 If we fail to do this, HP's optimizing linker may eliminate
5367 an addil, but not update the ldw/stw/ldo instruction that
5368 uses the result of the addil. */
5370 offset = ((offset + 0x1000) & ~0x1fff);
5372 switch (GET_CODE (XEXP (x, 0)))
5385 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5393 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5394 fputs ("-$global$", file);
5396 fprintf (file, "%s%d", sep, offset);
5399 output_addr_const (file, x);
5402 /* Output boilerplate text to appear at the beginning of the file.
5403 There are several possible versions. */
5404 #define aputs(x) fputs(x, asm_out_file)
5406 pa_file_start_level (void)
5409 aputs ("\t.LEVEL 2.0w\n");
5410 else if (TARGET_PA_20)
5411 aputs ("\t.LEVEL 2.0\n");
5412 else if (TARGET_PA_11)
5413 aputs ("\t.LEVEL 1.1\n");
5415 aputs ("\t.LEVEL 1.0\n");
5419 pa_file_start_space (int sortspace)
5421 aputs ("\t.SPACE $PRIVATE$");
5424 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5425 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5426 "\n\t.SPACE $TEXT$");
5429 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5430 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5434 pa_file_start_file (int want_version)
5436 if (write_symbols != NO_DEBUG)
5438 output_file_directive (asm_out_file, main_input_filename);
5440 aputs ("\t.version\t\"01.01\"\n");
5445 pa_file_start_mcount (const char *aswhat)
5448 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5452 pa_elf_file_start (void)
5454 pa_file_start_level ();
5455 pa_file_start_mcount ("ENTRY");
5456 pa_file_start_file (0);
5460 pa_som_file_start (void)
5462 pa_file_start_level ();
5463 pa_file_start_space (0);
5464 aputs ("\t.IMPORT $global$,DATA\n"
5465 "\t.IMPORT $$dyncall,MILLICODE\n");
5466 pa_file_start_mcount ("CODE");
5467 pa_file_start_file (0);
5471 pa_linux_file_start (void)
5473 pa_file_start_file (1);
5474 pa_file_start_level ();
5475 pa_file_start_mcount ("CODE");
5479 pa_hpux64_gas_file_start (void)
5481 pa_file_start_level ();
5482 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5484 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5486 pa_file_start_file (1);
5490 pa_hpux64_hpas_file_start (void)
5492 pa_file_start_level ();
5493 pa_file_start_space (1);
5494 pa_file_start_mcount ("CODE");
5495 pa_file_start_file (0);
5499 /* Search the deferred plabel list for SYMBOL and return its internal
5500 label. If an entry for SYMBOL is not found, a new entry is created. */
5503 get_deferred_plabel (rtx symbol)
5505 const char *fname = XSTR (symbol, 0);
5508 /* See if we have already put this function on the list of deferred
5509 plabels. This list is generally small, so a liner search is not
5510 too ugly. If it proves too slow replace it with something faster. */
5511 for (i = 0; i < n_deferred_plabels; i++)
5512 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5515 /* If the deferred plabel list is empty, or this entry was not found
5516 on the list, create a new entry on the list. */
5517 if (deferred_plabels == NULL || i == n_deferred_plabels)
5521 if (deferred_plabels == 0)
5522 deferred_plabels = ggc_alloc_deferred_plabel ();
5524 deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel,
5526 n_deferred_plabels + 1);
5528 i = n_deferred_plabels++;
5529 deferred_plabels[i].internal_label = gen_label_rtx ();
5530 deferred_plabels[i].symbol = symbol;
5532 /* Gross. We have just implicitly taken the address of this
5533 function. Mark it in the same manner as assemble_name. */
5534 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5536 mark_referenced (id);
5539 return deferred_plabels[i].internal_label;
5543 output_deferred_plabels (void)
5547 /* If we have some deferred plabels, then we need to switch into the
5548 data or readonly data section, and align it to a 4 byte boundary
5549 before outputting the deferred plabels. */
5550 if (n_deferred_plabels)
5552 switch_to_section (flag_pic ? data_section : readonly_data_section);
5553 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5556 /* Now output the deferred plabels. */
5557 for (i = 0; i < n_deferred_plabels; i++)
5559 targetm.asm_out.internal_label (asm_out_file, "L",
5560 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5561 assemble_integer (deferred_plabels[i].symbol,
5562 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5566 #if HPUX_LONG_DOUBLE_LIBRARY
5567 /* Initialize optabs to point to HPUX long double emulation routines. */
5569 pa_hpux_init_libfuncs (void)
5571 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5572 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5573 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5574 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5575 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5576 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5577 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5578 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5579 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5581 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5582 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5583 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5584 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5585 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5586 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5587 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5589 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5590 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5591 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5592 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5594 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5595 ? "__U_Qfcnvfxt_quad_to_sgl"
5596 : "_U_Qfcnvfxt_quad_to_sgl");
5597 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5598 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5599 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5601 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5602 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5603 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5604 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5608 /* HP's millicode routines mean something special to the assembler.
5609 Keep track of which ones we have used. */
5611 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5612 static void import_milli (enum millicodes);
5613 static char imported[(int) end1000];
5614 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5615 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5616 #define MILLI_START 10
5619 import_milli (enum millicodes code)
5621 char str[sizeof (import_string)];
5623 if (!imported[(int) code])
5625 imported[(int) code] = 1;
5626 strcpy (str, import_string);
5627 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5628 output_asm_insn (str, 0);
5632 /* The register constraints have put the operands and return value in
5633 the proper registers. */
5636 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5638 import_milli (mulI);
5639 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5642 /* Emit the rtl for doing a division by a constant. */
5644 /* Do magic division millicodes exist for this value? */
5645 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5647 /* We'll use an array to keep track of the magic millicodes and
5648 whether or not we've used them already. [n][0] is signed, [n][1] is
5651 static int div_milli[16][2];
5654 emit_hpdiv_const (rtx *operands, int unsignedp)
5656 if (GET_CODE (operands[2]) == CONST_INT
5657 && INTVAL (operands[2]) > 0
5658 && INTVAL (operands[2]) < 16
5659 && magic_milli[INTVAL (operands[2])])
5661 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5663 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5667 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5668 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5670 gen_rtx_REG (SImode, 26),
5672 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5673 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5674 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5675 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5676 gen_rtx_CLOBBER (VOIDmode, ret))));
5677 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5684 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5688 /* If the divisor is a constant, try to use one of the special
5690 if (GET_CODE (operands[0]) == CONST_INT)
5692 static char buf[100];
5693 divisor = INTVAL (operands[0]);
5694 if (!div_milli[divisor][unsignedp])
5696 div_milli[divisor][unsignedp] = 1;
5698 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5700 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5704 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5705 INTVAL (operands[0]));
5706 return output_millicode_call (insn,
5707 gen_rtx_SYMBOL_REF (SImode, buf));
5711 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5712 INTVAL (operands[0]));
5713 return output_millicode_call (insn,
5714 gen_rtx_SYMBOL_REF (SImode, buf));
5717 /* Divisor isn't a special constant. */
5722 import_milli (divU);
5723 return output_millicode_call (insn,
5724 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5728 import_milli (divI);
5729 return output_millicode_call (insn,
5730 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5735 /* Output a $$rem millicode to do mod. */
5738 output_mod_insn (int unsignedp, rtx insn)
5742 import_milli (remU);
5743 return output_millicode_call (insn,
5744 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5748 import_milli (remI);
5749 return output_millicode_call (insn,
5750 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5755 output_arg_descriptor (rtx call_insn)
5757 const char *arg_regs[4];
5758 enum machine_mode arg_mode;
5760 int i, output_flag = 0;
5763 /* We neither need nor want argument location descriptors for the
5764 64bit runtime environment or the ELF32 environment. */
5765 if (TARGET_64BIT || TARGET_ELF32)
5768 for (i = 0; i < 4; i++)
5771 /* Specify explicitly that no argument relocations should take place
5772 if using the portable runtime calling conventions. */
5773 if (TARGET_PORTABLE_RUNTIME)
5775 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5780 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5781 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5782 link; link = XEXP (link, 1))
5784 rtx use = XEXP (link, 0);
5786 if (! (GET_CODE (use) == USE
5787 && GET_CODE (XEXP (use, 0)) == REG
5788 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5791 arg_mode = GET_MODE (XEXP (use, 0));
5792 regno = REGNO (XEXP (use, 0));
5793 if (regno >= 23 && regno <= 26)
5795 arg_regs[26 - regno] = "GR";
5796 if (arg_mode == DImode)
5797 arg_regs[25 - regno] = "GR";
5799 else if (regno >= 32 && regno <= 39)
5801 if (arg_mode == SFmode)
5802 arg_regs[(regno - 32) / 2] = "FR";
5805 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5806 arg_regs[(regno - 34) / 2] = "FR";
5807 arg_regs[(regno - 34) / 2 + 1] = "FU";
5809 arg_regs[(regno - 34) / 2] = "FU";
5810 arg_regs[(regno - 34) / 2 + 1] = "FR";
5815 fputs ("\t.CALL ", asm_out_file);
5816 for (i = 0; i < 4; i++)
5821 fputc (',', asm_out_file);
5822 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5825 fputc ('\n', asm_out_file);
5828 /* Inform reload about cases where moving X with a mode MODE to a register in
5829 RCLASS requires an extra scratch or immediate register. Return the class
5830 needed for the immediate register. */
5833 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
5834 enum machine_mode mode, secondary_reload_info *sri)
5837 enum reg_class rclass = (enum reg_class) rclass_i;
5839 /* Handle the easy stuff first. */
5840 if (rclass == R1_REGS)
5846 if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5852 /* If we have something like (mem (mem (...)), we can safely assume the
5853 inner MEM will end up in a general register after reloading, so there's
5854 no need for a secondary reload. */
5855 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5858 /* Trying to load a constant into a FP register during PIC code
5859 generation requires %r1 as a scratch register. */
5861 && (mode == SImode || mode == DImode)
5862 && FP_REG_CLASS_P (rclass)
5863 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5865 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5866 : CODE_FOR_reload_indi_r1);
5870 /* Secondary reloads of symbolic operands require %r1 as a scratch
5871 register when we're generating PIC code and when the operand isn't
5873 if (symbolic_expression_p (x))
5875 if (GET_CODE (x) == HIGH)
5878 if (flag_pic || !read_only_operand (x, VOIDmode))
5880 gcc_assert (mode == SImode || mode == DImode);
5881 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5882 : CODE_FOR_reload_indi_r1);
5887 /* Profiling showed the PA port spends about 1.3% of its compilation
5888 time in true_regnum from calls inside pa_secondary_reload_class. */
5889 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5890 regno = true_regnum (x);
5892 /* In order to allow 14-bit displacements in integer loads and stores,
5893 we need to prevent reload from generating out of range integer mode
5894 loads and stores to the floating point registers. Previously, we
5895 used to call for a secondary reload and have emit_move_sequence()
5896 fix the instruction sequence. However, reload occasionally wouldn't
5897 generate the reload and we would end up with an invalid REG+D memory
5898 address. So, now we use an intermediate general register for most
5899 memory loads and stores. */
5900 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5901 && GET_MODE_CLASS (mode) == MODE_INT
5902 && FP_REG_CLASS_P (rclass))
5904 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5905 the secondary reload needed for a pseudo. It never passes a
5907 if (GET_CODE (x) == MEM)
5911 /* We don't need an intermediate for indexed and LO_SUM DLT
5912 memory addresses. When INT14_OK_STRICT is true, it might
5913 appear that we could directly allow register indirect
5914 memory addresses. However, this doesn't work because we
5915 don't support SUBREGs in floating-point register copies
5916 and reload doesn't tell us when it's going to use a SUBREG. */
5917 if (IS_INDEX_ADDR_P (x)
5918 || IS_LO_SUM_DLT_ADDR_P (x))
5921 /* Otherwise, we need an intermediate general register. */
5922 return GENERAL_REGS;
5925 /* Request a secondary reload with a general scratch register
5926 for everthing else. ??? Could symbolic operands be handled
5927 directly when generating non-pic PA 2.0 code? */
5929 ? direct_optab_handler (reload_in_optab, mode)
5930 : direct_optab_handler (reload_out_optab, mode));
5934 /* A SAR<->FP register copy requires an intermediate general register
5935 and secondary memory. We need a secondary reload with a general
5936 scratch register for spills. */
5937 if (rclass == SHIFT_REGS)
5940 if (regno >= FIRST_PSEUDO_REGISTER || regno < 0)
5943 ? direct_optab_handler (reload_in_optab, mode)
5944 : direct_optab_handler (reload_out_optab, mode));
5948 /* Handle FP copy. */
5949 if (FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))
5950 return GENERAL_REGS;
5953 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5954 && REGNO_REG_CLASS (regno) == SHIFT_REGS
5955 && FP_REG_CLASS_P (rclass))
5956 return GENERAL_REGS;
5961 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5962 is only marked as live on entry by df-scan when it is a fixed
5963 register. It isn't a fixed register in the 64-bit runtime,
5964 so we need to mark it here. */
5967 pa_extra_live_on_entry (bitmap regs)
5970 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5973 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5974 to prevent it from being deleted. */
5977 pa_eh_return_handler_rtx (void)
5981 tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx,
5982 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5983 tmp = gen_rtx_MEM (word_mode, tmp);
5988 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5989 by invisible reference. As a GCC extension, we also pass anything
5990 with a zero or variable size by reference.
5992 The 64-bit runtime does not describe passing any types by invisible
5993 reference. The internals of GCC can't currently handle passing
5994 empty structures, and zero or variable length arrays when they are
5995 not passed entirely on the stack or by reference. Thus, as a GCC
5996 extension, we pass these types by reference. The HP compiler doesn't
5997 support these types, so hopefully there shouldn't be any compatibility
5998 issues. This may have to be revisited when HP releases a C99 compiler
5999 or updates the ABI. */
6002 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6003 enum machine_mode mode, const_tree type,
6004 bool named ATTRIBUTE_UNUSED)
6009 size = int_size_in_bytes (type);
6011 size = GET_MODE_SIZE (mode);
6016 return size <= 0 || size > 8;
6020 function_arg_padding (enum machine_mode mode, const_tree type)
6025 && (AGGREGATE_TYPE_P (type)
6026 || TREE_CODE (type) == COMPLEX_TYPE
6027 || TREE_CODE (type) == VECTOR_TYPE)))
6029 /* Return none if justification is not required. */
6031 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6032 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6035 /* The directions set here are ignored when a BLKmode argument larger
6036 than a word is placed in a register. Different code is used for
6037 the stack and registers. This makes it difficult to have a
6038 consistent data representation for both the stack and registers.
6039 For both runtimes, the justification and padding for arguments on
6040 the stack and in registers should be identical. */
6042 /* The 64-bit runtime specifies left justification for aggregates. */
6045 /* The 32-bit runtime architecture specifies right justification.
6046 When the argument is passed on the stack, the argument is padded
6047 with garbage on the left. The HP compiler pads with zeros. */
6051 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6058 /* Do what is necessary for `va_start'. We look at the current function
6059 to determine if stdargs or varargs is used and fill in an initial
6060 va_list. A pointer to this constructor is returned. */
6063 hppa_builtin_saveregs (void)
6066 tree fntype = TREE_TYPE (current_function_decl);
6067 int argadj = ((!stdarg_p (fntype))
6068 ? UNITS_PER_WORD : 0);
6071 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
6073 offset = crtl->args.arg_offset_rtx;
6079 /* Adjust for varargs/stdarg differences. */
6081 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
6083 offset = crtl->args.arg_offset_rtx;
6085 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6086 from the incoming arg pointer and growing to larger addresses. */
6087 for (i = 26, off = -64; i >= 19; i--, off += 8)
6088 emit_move_insn (gen_rtx_MEM (word_mode,
6089 plus_constant (arg_pointer_rtx, off)),
6090 gen_rtx_REG (word_mode, i));
6092 /* The incoming args pointer points just beyond the flushback area;
6093 normally this is not a serious concern. However, when we are doing
6094 varargs/stdargs we want to make the arg pointer point to the start
6095 of the incoming argument area. */
6096 emit_move_insn (virtual_incoming_args_rtx,
6097 plus_constant (arg_pointer_rtx, -64));
6099 /* Now return a pointer to the first anonymous argument. */
6100 return copy_to_reg (expand_binop (Pmode, add_optab,
6101 virtual_incoming_args_rtx,
6102 offset, 0, 0, OPTAB_LIB_WIDEN));
6105 /* Store general registers on the stack. */
6106 dest = gen_rtx_MEM (BLKmode,
6107 plus_constant (crtl->args.internal_arg_pointer,
6109 set_mem_alias_set (dest, get_varargs_alias_set ());
6110 set_mem_align (dest, BITS_PER_WORD);
6111 move_block_from_reg (23, dest, 4);
6113 /* move_block_from_reg will emit code to store the argument registers
6114 individually as scalar stores.
6116 However, other insns may later load from the same addresses for
6117 a structure load (passing a struct to a varargs routine).
6119 The alias code assumes that such aliasing can never happen, so we
6120 have to keep memory referencing insns from moving up beyond the
6121 last argument register store. So we emit a blockage insn here. */
6122 emit_insn (gen_blockage ());
6124 return copy_to_reg (expand_binop (Pmode, add_optab,
6125 crtl->args.internal_arg_pointer,
6126 offset, 0, 0, OPTAB_LIB_WIDEN));
6130 hppa_va_start (tree valist, rtx nextarg)
6132 nextarg = expand_builtin_saveregs ();
6133 std_expand_builtin_va_start (valist, nextarg);
6137 hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6142 /* Args grow upward. We can use the generic routines. */
6143 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6145 else /* !TARGET_64BIT */
6147 tree ptr = build_pointer_type (type);
6150 unsigned int size, ofs;
6153 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6157 ptr = build_pointer_type (type);
6159 size = int_size_in_bytes (type);
6160 valist_type = TREE_TYPE (valist);
6162 /* Args grow down. Not handled by generic routines. */
6164 u = fold_convert (sizetype, size_in_bytes (type));
6165 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6166 t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u);
6168 /* Align to 4 or 8 byte boundary depending on argument size. */
6170 u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4));
6171 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6172 t = fold_convert (valist_type, t);
6174 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6176 ofs = (8 - size) % 4;
6180 t = build2 (POINTER_PLUS_EXPR, valist_type, t, u);
6183 t = fold_convert (ptr, t);
6184 t = build_va_arg_indirect_ref (t);
6187 t = build_va_arg_indirect_ref (t);
6193 /* True if MODE is valid for the target. By "valid", we mean able to
6194 be manipulated in non-trivial ways. In particular, this means all
6195 the arithmetic is supported.
6197 Currently, TImode is not valid as the HP 64-bit runtime documentation
6198 doesn't document the alignment and calling conventions for this type.
6199 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6200 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6203 pa_scalar_mode_supported_p (enum machine_mode mode)
6205 int precision = GET_MODE_PRECISION (mode);
6207 switch (GET_MODE_CLASS (mode))
6209 case MODE_PARTIAL_INT:
6211 if (precision == CHAR_TYPE_SIZE)
6213 if (precision == SHORT_TYPE_SIZE)
6215 if (precision == INT_TYPE_SIZE)
6217 if (precision == LONG_TYPE_SIZE)
6219 if (precision == LONG_LONG_TYPE_SIZE)
6224 if (precision == FLOAT_TYPE_SIZE)
6226 if (precision == DOUBLE_TYPE_SIZE)
6228 if (precision == LONG_DOUBLE_TYPE_SIZE)
6232 case MODE_DECIMAL_FLOAT:
6240 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6241 it branches into the delay slot. Otherwise, return FALSE. */
6244 branch_to_delay_slot_p (rtx insn)
6248 if (dbr_sequence_length ())
6251 jump_insn = next_active_insn (JUMP_LABEL (insn));
6254 insn = next_active_insn (insn);
6255 if (jump_insn == insn)
6258 /* We can't rely on the length of asms. So, we return FALSE when
6259 the branch is followed by an asm. */
6261 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6262 || extract_asm_operands (PATTERN (insn)) != NULL_RTX
6263 || get_attr_length (insn) > 0)
6270 /* Return TRUE if INSN, a forward jump insn, needs a nop in its delay slot.
6272 This occurs when INSN has an unfilled delay slot and is followed
6273 by an asm. Disaster can occur if the asm is empty and the jump
6274 branches into the delay slot. So, we add a nop in the delay slot
6275 when this occurs. */
6278 branch_needs_nop_p (rtx insn)
6282 if (dbr_sequence_length ())
6285 jump_insn = next_active_insn (JUMP_LABEL (insn));
6288 insn = next_active_insn (insn);
6289 if (!insn || jump_insn == insn)
6292 if (!(GET_CODE (PATTERN (insn)) == ASM_INPUT
6293 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6294 && get_attr_length (insn) > 0)
6301 /* Return TRUE if INSN, a forward jump insn, can use nullification
6302 to skip the following instruction. This avoids an extra cycle due
6303 to a mis-predicted branch when we fall through. */
6306 use_skip_p (rtx insn)
6308 rtx jump_insn = next_active_insn (JUMP_LABEL (insn));
6312 insn = next_active_insn (insn);
6314 /* We can't rely on the length of asms, so we can't skip asms. */
6316 || GET_CODE (PATTERN (insn)) == ASM_INPUT
6317 || extract_asm_operands (PATTERN (insn)) != NULL_RTX)
6319 if (get_attr_length (insn) == 4
6320 && jump_insn == next_active_insn (insn))
6322 if (get_attr_length (insn) > 0)
6329 /* This routine handles all the normal conditional branch sequences we
6330 might need to generate. It handles compare immediate vs compare
6331 register, nullification of delay slots, varying length branches,
6332 negated branches, and all combinations of the above. It returns the
6333 output appropriate to emit the branch corresponding to all given
6337 output_cbranch (rtx *operands, int negated, rtx insn)
6339 static char buf[100];
6341 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6342 int length = get_attr_length (insn);
6345 /* A conditional branch to the following instruction (e.g. the delay slot)
6346 is asking for a disaster. This can happen when not optimizing and
6347 when jump optimization fails.
6349 While it is usually safe to emit nothing, this can fail if the
6350 preceding instruction is a nullified branch with an empty delay
6351 slot and the same branch target as this branch. We could check
6352 for this but jump optimization should eliminate nop jumps. It
6353 is always safe to emit a nop. */
6354 if (branch_to_delay_slot_p (insn))
6357 /* The doubleword form of the cmpib instruction doesn't have the LEU
6358 and GTU conditions while the cmpb instruction does. Since we accept
6359 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6360 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6361 operands[2] = gen_rtx_REG (DImode, 0);
6362 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6363 operands[1] = gen_rtx_REG (DImode, 0);
6365 /* If this is a long branch with its delay slot unfilled, set `nullify'
6366 as it can nullify the delay slot and save a nop. */
6367 if (length == 8 && dbr_sequence_length () == 0)
6370 /* If this is a short forward conditional branch which did not get
6371 its delay slot filled, the delay slot can still be nullified. */
6372 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6373 nullify = forward_branch_p (insn);
6375 /* A forward branch over a single nullified insn can be done with a
6376 comclr instruction. This avoids a single cycle penalty due to
6377 mis-predicted branch if we fall through (branch not taken). */
6378 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6382 /* All short conditional branches except backwards with an unfilled
6386 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6388 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6389 if (GET_MODE (operands[1]) == DImode)
6392 strcat (buf, "%B3");
6394 strcat (buf, "%S3");
6396 strcat (buf, " %2,%r1,%%r0");
6399 if (branch_needs_nop_p (insn))
6400 strcat (buf, ",n %2,%r1,%0%#");
6402 strcat (buf, ",n %2,%r1,%0");
6405 strcat (buf, " %2,%r1,%0");
6408 /* All long conditionals. Note a short backward branch with an
6409 unfilled delay slot is treated just like a long backward branch
6410 with an unfilled delay slot. */
6412 /* Handle weird backwards branch with a filled delay slot
6413 which is nullified. */
6414 if (dbr_sequence_length () != 0
6415 && ! forward_branch_p (insn)
6418 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6419 if (GET_MODE (operands[1]) == DImode)
6422 strcat (buf, "%S3");
6424 strcat (buf, "%B3");
6425 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6427 /* Handle short backwards branch with an unfilled delay slot.
6428 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6429 taken and untaken branches. */
6430 else if (dbr_sequence_length () == 0
6431 && ! forward_branch_p (insn)
6432 && INSN_ADDRESSES_SET_P ()
6433 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6434 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6436 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6437 if (GET_MODE (operands[1]) == DImode)
6440 strcat (buf, "%B3 %2,%r1,%0%#");
6442 strcat (buf, "%S3 %2,%r1,%0%#");
6446 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6447 if (GET_MODE (operands[1]) == DImode)
6450 strcat (buf, "%S3");
6452 strcat (buf, "%B3");
6454 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6456 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6461 /* The reversed conditional branch must branch over one additional
6462 instruction if the delay slot is filled and needs to be extracted
6463 by output_lbranch. If the delay slot is empty or this is a
6464 nullified forward branch, the instruction after the reversed
6465 condition branch must be nullified. */
6466 if (dbr_sequence_length () == 0
6467 || (nullify && forward_branch_p (insn)))
6471 operands[4] = GEN_INT (length);
6476 operands[4] = GEN_INT (length + 4);
6479 /* Create a reversed conditional branch which branches around
6480 the following insns. */
6481 if (GET_MODE (operands[1]) != DImode)
6487 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6490 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6496 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6499 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6508 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6511 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6517 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6520 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6524 output_asm_insn (buf, operands);
6525 return output_lbranch (operands[0], insn, xdelay);
6530 /* This routine handles output of long unconditional branches that
6531 exceed the maximum range of a simple branch instruction. Since
6532 we don't have a register available for the branch, we save register
6533 %r1 in the frame marker, load the branch destination DEST into %r1,
6534 execute the branch, and restore %r1 in the delay slot of the branch.
6536 Since long branches may have an insn in the delay slot and the
6537 delay slot is used to restore %r1, we in general need to extract
6538 this insn and execute it before the branch. However, to facilitate
6539 use of this function by conditional branches, we also provide an
6540 option to not extract the delay insn so that it will be emitted
6541 after the long branch. So, if there is an insn in the delay slot,
6542 it is extracted if XDELAY is nonzero.
6544 The lengths of the various long-branch sequences are 20, 16 and 24
6545 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6548 output_lbranch (rtx dest, rtx insn, int xdelay)
6552 xoperands[0] = dest;
6554 /* First, free up the delay slot. */
6555 if (xdelay && dbr_sequence_length () != 0)
6557 /* We can't handle a jump in the delay slot. */
6558 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6560 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6563 /* Now delete the delay insn. */
6564 SET_INSN_DELETED (NEXT_INSN (insn));
6567 /* Output an insn to save %r1. The runtime documentation doesn't
6568 specify whether the "Clean Up" slot in the callers frame can
6569 be clobbered by the callee. It isn't copied by HP's builtin
6570 alloca, so this suggests that it can be clobbered if necessary.
6571 The "Static Link" location is copied by HP builtin alloca, so
6572 we avoid using it. Using the cleanup slot might be a problem
6573 if we have to interoperate with languages that pass cleanup
6574 information. However, it should be possible to handle these
6575 situations with GCC's asm feature.
6577 The "Current RP" slot is reserved for the called procedure, so
6578 we try to use it when we don't have a frame of our own. It's
6579 rather unlikely that we won't have a frame when we need to emit
6582 Really the way to go long term is a register scavenger; goto
6583 the target of the jump and find a register which we can use
6584 as a scratch to hold the value in %r1. Then, we wouldn't have
6585 to free up the delay slot or clobber a slot that may be needed
6586 for other purposes. */
6589 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6590 /* Use the return pointer slot in the frame marker. */
6591 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6593 /* Use the slot at -40 in the frame marker since HP builtin
6594 alloca doesn't copy it. */
6595 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6599 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6600 /* Use the return pointer slot in the frame marker. */
6601 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6603 /* Use the "Clean Up" slot in the frame marker. In GCC,
6604 the only other use of this location is for copying a
6605 floating point double argument from a floating-point
6606 register to two general registers. The copy is done
6607 as an "atomic" operation when outputting a call, so it
6608 won't interfere with our using the location here. */
6609 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6612 if (TARGET_PORTABLE_RUNTIME)
6614 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6615 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6616 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6620 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6621 if (TARGET_SOM || !TARGET_GAS)
6623 xoperands[1] = gen_label_rtx ();
6624 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6625 targetm.asm_out.internal_label (asm_out_file, "L",
6626 CODE_LABEL_NUMBER (xoperands[1]));
6627 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6631 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6632 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6634 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6637 /* Now output a very long branch to the original target. */
6638 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6640 /* Now restore the value of %r1 in the delay slot. */
6643 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6644 return "ldd -16(%%r30),%%r1";
6646 return "ldd -40(%%r30),%%r1";
6650 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6651 return "ldw -20(%%r30),%%r1";
6653 return "ldw -12(%%r30),%%r1";
6657 /* This routine handles all the branch-on-bit conditional branch sequences we
6658 might need to generate. It handles nullification of delay slots,
6659 varying length branches, negated branches and all combinations of the
6660 above. it returns the appropriate output template to emit the branch. */
6663 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6665 static char buf[100];
6667 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6668 int length = get_attr_length (insn);
6671 /* A conditional branch to the following instruction (e.g. the delay slot) is
6672 asking for a disaster. I do not think this can happen as this pattern
6673 is only used when optimizing; jump optimization should eliminate the
6674 jump. But be prepared just in case. */
6676 if (branch_to_delay_slot_p (insn))
6679 /* If this is a long branch with its delay slot unfilled, set `nullify'
6680 as it can nullify the delay slot and save a nop. */
6681 if (length == 8 && dbr_sequence_length () == 0)
6684 /* If this is a short forward conditional branch which did not get
6685 its delay slot filled, the delay slot can still be nullified. */
6686 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6687 nullify = forward_branch_p (insn);
6689 /* A forward branch over a single nullified insn can be done with a
6690 extrs instruction. This avoids a single cycle penalty due to
6691 mis-predicted branch if we fall through (branch not taken). */
6692 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6697 /* All short conditional branches except backwards with an unfilled
6701 strcpy (buf, "{extrs,|extrw,s,}");
6703 strcpy (buf, "bb,");
6704 if (useskip && GET_MODE (operands[0]) == DImode)
6705 strcpy (buf, "extrd,s,*");
6706 else if (GET_MODE (operands[0]) == DImode)
6707 strcpy (buf, "bb,*");
6708 if ((which == 0 && negated)
6709 || (which == 1 && ! negated))
6714 strcat (buf, " %0,%1,1,%%r0");
6715 else if (nullify && negated)
6717 if (branch_needs_nop_p (insn))
6718 strcat (buf, ",n %0,%1,%3%#");
6720 strcat (buf, ",n %0,%1,%3");
6722 else if (nullify && ! negated)
6724 if (branch_needs_nop_p (insn))
6725 strcat (buf, ",n %0,%1,%2%#");
6727 strcat (buf, ",n %0,%1,%2");
6729 else if (! nullify && negated)
6730 strcat (buf, " %0,%1,%3");
6731 else if (! nullify && ! negated)
6732 strcat (buf, " %0,%1,%2");
6735 /* All long conditionals. Note a short backward branch with an
6736 unfilled delay slot is treated just like a long backward branch
6737 with an unfilled delay slot. */
6739 /* Handle weird backwards branch with a filled delay slot
6740 which is nullified. */
6741 if (dbr_sequence_length () != 0
6742 && ! forward_branch_p (insn)
6745 strcpy (buf, "bb,");
6746 if (GET_MODE (operands[0]) == DImode)
6748 if ((which == 0 && negated)
6749 || (which == 1 && ! negated))
6754 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6756 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6758 /* Handle short backwards branch with an unfilled delay slot.
6759 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6760 taken and untaken branches. */
6761 else if (dbr_sequence_length () == 0
6762 && ! forward_branch_p (insn)
6763 && INSN_ADDRESSES_SET_P ()
6764 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6765 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6767 strcpy (buf, "bb,");
6768 if (GET_MODE (operands[0]) == DImode)
6770 if ((which == 0 && negated)
6771 || (which == 1 && ! negated))
6776 strcat (buf, " %0,%1,%3%#");
6778 strcat (buf, " %0,%1,%2%#");
6782 if (GET_MODE (operands[0]) == DImode)
6783 strcpy (buf, "extrd,s,*");
6785 strcpy (buf, "{extrs,|extrw,s,}");
6786 if ((which == 0 && negated)
6787 || (which == 1 && ! negated))
6791 if (nullify && negated)
6792 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6793 else if (nullify && ! negated)
6794 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6796 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6798 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6803 /* The reversed conditional branch must branch over one additional
6804 instruction if the delay slot is filled and needs to be extracted
6805 by output_lbranch. If the delay slot is empty or this is a
6806 nullified forward branch, the instruction after the reversed
6807 condition branch must be nullified. */
6808 if (dbr_sequence_length () == 0
6809 || (nullify && forward_branch_p (insn)))
6813 operands[4] = GEN_INT (length);
6818 operands[4] = GEN_INT (length + 4);
6821 if (GET_MODE (operands[0]) == DImode)
6822 strcpy (buf, "bb,*");
6824 strcpy (buf, "bb,");
6825 if ((which == 0 && negated)
6826 || (which == 1 && !negated))
6831 strcat (buf, ",n %0,%1,.+%4");
6833 strcat (buf, " %0,%1,.+%4");
6834 output_asm_insn (buf, operands);
6835 return output_lbranch (negated ? operands[3] : operands[2],
6841 /* This routine handles all the branch-on-variable-bit conditional branch
6842 sequences we might need to generate. It handles nullification of delay
6843 slots, varying length branches, negated branches and all combinations
6844 of the above. it returns the appropriate output template to emit the
6848 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6850 static char buf[100];
6852 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6853 int length = get_attr_length (insn);
6856 /* A conditional branch to the following instruction (e.g. the delay slot) is
6857 asking for a disaster. I do not think this can happen as this pattern
6858 is only used when optimizing; jump optimization should eliminate the
6859 jump. But be prepared just in case. */
6861 if (branch_to_delay_slot_p (insn))
6864 /* If this is a long branch with its delay slot unfilled, set `nullify'
6865 as it can nullify the delay slot and save a nop. */
6866 if (length == 8 && dbr_sequence_length () == 0)
6869 /* If this is a short forward conditional branch which did not get
6870 its delay slot filled, the delay slot can still be nullified. */
6871 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6872 nullify = forward_branch_p (insn);
6874 /* A forward branch over a single nullified insn can be done with a
6875 extrs instruction. This avoids a single cycle penalty due to
6876 mis-predicted branch if we fall through (branch not taken). */
6877 useskip = (length == 4 && nullify) ? use_skip_p (insn) : FALSE;
6882 /* All short conditional branches except backwards with an unfilled
6886 strcpy (buf, "{vextrs,|extrw,s,}");
6888 strcpy (buf, "{bvb,|bb,}");
6889 if (useskip && GET_MODE (operands[0]) == DImode)
6890 strcpy (buf, "extrd,s,*");
6891 else if (GET_MODE (operands[0]) == DImode)
6892 strcpy (buf, "bb,*");
6893 if ((which == 0 && negated)
6894 || (which == 1 && ! negated))
6899 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6900 else if (nullify && negated)
6902 if (branch_needs_nop_p (insn))
6903 strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
6905 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6907 else if (nullify && ! negated)
6909 if (branch_needs_nop_p (insn))
6910 strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
6912 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6914 else if (! nullify && negated)
6915 strcat (buf, "{ %0,%3| %0,%%sar,%3}");
6916 else if (! nullify && ! negated)
6917 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6920 /* All long conditionals. Note a short backward branch with an
6921 unfilled delay slot is treated just like a long backward branch
6922 with an unfilled delay slot. */
6924 /* Handle weird backwards branch with a filled delay slot
6925 which is nullified. */
6926 if (dbr_sequence_length () != 0
6927 && ! forward_branch_p (insn)
6930 strcpy (buf, "{bvb,|bb,}");
6931 if (GET_MODE (operands[0]) == DImode)
6933 if ((which == 0 && negated)
6934 || (which == 1 && ! negated))
6939 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6941 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6943 /* Handle short backwards branch with an unfilled delay slot.
6944 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6945 taken and untaken branches. */
6946 else if (dbr_sequence_length () == 0
6947 && ! forward_branch_p (insn)
6948 && INSN_ADDRESSES_SET_P ()
6949 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6950 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6952 strcpy (buf, "{bvb,|bb,}");
6953 if (GET_MODE (operands[0]) == DImode)
6955 if ((which == 0 && negated)
6956 || (which == 1 && ! negated))
6961 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6963 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6967 strcpy (buf, "{vextrs,|extrw,s,}");
6968 if (GET_MODE (operands[0]) == DImode)
6969 strcpy (buf, "extrd,s,*");
6970 if ((which == 0 && negated)
6971 || (which == 1 && ! negated))
6975 if (nullify && negated)
6976 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6977 else if (nullify && ! negated)
6978 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6980 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6982 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6987 /* The reversed conditional branch must branch over one additional
6988 instruction if the delay slot is filled and needs to be extracted
6989 by output_lbranch. If the delay slot is empty or this is a
6990 nullified forward branch, the instruction after the reversed
6991 condition branch must be nullified. */
6992 if (dbr_sequence_length () == 0
6993 || (nullify && forward_branch_p (insn)))
6997 operands[4] = GEN_INT (length);
7002 operands[4] = GEN_INT (length + 4);
7005 if (GET_MODE (operands[0]) == DImode)
7006 strcpy (buf, "bb,*");
7008 strcpy (buf, "{bvb,|bb,}");
7009 if ((which == 0 && negated)
7010 || (which == 1 && !negated))
7015 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
7017 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
7018 output_asm_insn (buf, operands);
7019 return output_lbranch (negated ? operands[3] : operands[2],
7025 /* Return the output template for emitting a dbra type insn.
7027 Note it may perform some output operations on its own before
7028 returning the final output string. */
7030 output_dbra (rtx *operands, rtx insn, int which_alternative)
7032 int length = get_attr_length (insn);
7034 /* A conditional branch to the following instruction (e.g. the delay slot) is
7035 asking for a disaster. Be prepared! */
7037 if (branch_to_delay_slot_p (insn))
7039 if (which_alternative == 0)
7040 return "ldo %1(%0),%0";
7041 else if (which_alternative == 1)
7043 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
7044 output_asm_insn ("ldw -16(%%r30),%4", operands);
7045 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7046 return "{fldws|fldw} -16(%%r30),%0";
7050 output_asm_insn ("ldw %0,%4", operands);
7051 return "ldo %1(%4),%4\n\tstw %4,%0";
7055 if (which_alternative == 0)
7057 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7060 /* If this is a long branch with its delay slot unfilled, set `nullify'
7061 as it can nullify the delay slot and save a nop. */
7062 if (length == 8 && dbr_sequence_length () == 0)
7065 /* If this is a short forward conditional branch which did not get
7066 its delay slot filled, the delay slot can still be nullified. */
7067 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7068 nullify = forward_branch_p (insn);
7075 if (branch_needs_nop_p (insn))
7076 return "addib,%C2,n %1,%0,%3%#";
7078 return "addib,%C2,n %1,%0,%3";
7081 return "addib,%C2 %1,%0,%3";
7084 /* Handle weird backwards branch with a fulled delay slot
7085 which is nullified. */
7086 if (dbr_sequence_length () != 0
7087 && ! forward_branch_p (insn)
7089 return "addib,%N2,n %1,%0,.+12\n\tb %3";
7090 /* Handle short backwards branch with an unfilled delay slot.
7091 Using a addb;nop rather than addi;bl saves 1 cycle for both
7092 taken and untaken branches. */
7093 else if (dbr_sequence_length () == 0
7094 && ! forward_branch_p (insn)
7095 && INSN_ADDRESSES_SET_P ()
7096 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7097 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7098 return "addib,%C2 %1,%0,%3%#";
7100 /* Handle normal cases. */
7102 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7104 return "addi,%N2 %1,%0,%0\n\tb %3";
7107 /* The reversed conditional branch must branch over one additional
7108 instruction if the delay slot is filled and needs to be extracted
7109 by output_lbranch. If the delay slot is empty or this is a
7110 nullified forward branch, the instruction after the reversed
7111 condition branch must be nullified. */
7112 if (dbr_sequence_length () == 0
7113 || (nullify && forward_branch_p (insn)))
7117 operands[4] = GEN_INT (length);
7122 operands[4] = GEN_INT (length + 4);
7126 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
7128 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
7130 return output_lbranch (operands[3], insn, xdelay);
7134 /* Deal with gross reload from FP register case. */
7135 else if (which_alternative == 1)
7137 /* Move loop counter from FP register to MEM then into a GR,
7138 increment the GR, store the GR into MEM, and finally reload
7139 the FP register from MEM from within the branch's delay slot. */
7140 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7142 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7144 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7145 else if (length == 28)
7146 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7149 operands[5] = GEN_INT (length - 16);
7150 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
7151 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7152 return output_lbranch (operands[3], insn, 0);
7155 /* Deal with gross reload from memory case. */
7158 /* Reload loop counter from memory, the store back to memory
7159 happens in the branch's delay slot. */
7160 output_asm_insn ("ldw %0,%4", operands);
7162 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7163 else if (length == 16)
7164 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7167 operands[5] = GEN_INT (length - 4);
7168 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
7169 return output_lbranch (operands[3], insn, 0);
7174 /* Return the output template for emitting a movb type insn.
7176 Note it may perform some output operations on its own before
7177 returning the final output string. */
7179 output_movb (rtx *operands, rtx insn, int which_alternative,
7180 int reverse_comparison)
7182 int length = get_attr_length (insn);
7184 /* A conditional branch to the following instruction (e.g. the delay slot) is
7185 asking for a disaster. Be prepared! */
7187 if (branch_to_delay_slot_p (insn))
7189 if (which_alternative == 0)
7190 return "copy %1,%0";
7191 else if (which_alternative == 1)
7193 output_asm_insn ("stw %1,-16(%%r30)", operands);
7194 return "{fldws|fldw} -16(%%r30),%0";
7196 else if (which_alternative == 2)
7202 /* Support the second variant. */
7203 if (reverse_comparison)
7204 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7206 if (which_alternative == 0)
7208 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7211 /* If this is a long branch with its delay slot unfilled, set `nullify'
7212 as it can nullify the delay slot and save a nop. */
7213 if (length == 8 && dbr_sequence_length () == 0)
7216 /* If this is a short forward conditional branch which did not get
7217 its delay slot filled, the delay slot can still be nullified. */
7218 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7219 nullify = forward_branch_p (insn);
7226 if (branch_needs_nop_p (insn))
7227 return "movb,%C2,n %1,%0,%3%#";
7229 return "movb,%C2,n %1,%0,%3";
7232 return "movb,%C2 %1,%0,%3";
7235 /* Handle weird backwards branch with a filled delay slot
7236 which is nullified. */
7237 if (dbr_sequence_length () != 0
7238 && ! forward_branch_p (insn)
7240 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7242 /* Handle short backwards branch with an unfilled delay slot.
7243 Using a movb;nop rather than or;bl saves 1 cycle for both
7244 taken and untaken branches. */
7245 else if (dbr_sequence_length () == 0
7246 && ! forward_branch_p (insn)
7247 && INSN_ADDRESSES_SET_P ()
7248 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7249 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7250 return "movb,%C2 %1,%0,%3%#";
7251 /* Handle normal cases. */
7253 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7255 return "or,%N2 %1,%%r0,%0\n\tb %3";
7258 /* The reversed conditional branch must branch over one additional
7259 instruction if the delay slot is filled and needs to be extracted
7260 by output_lbranch. If the delay slot is empty or this is a
7261 nullified forward branch, the instruction after the reversed
7262 condition branch must be nullified. */
7263 if (dbr_sequence_length () == 0
7264 || (nullify && forward_branch_p (insn)))
7268 operands[4] = GEN_INT (length);
7273 operands[4] = GEN_INT (length + 4);
7277 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7279 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7281 return output_lbranch (operands[3], insn, xdelay);
7284 /* Deal with gross reload for FP destination register case. */
7285 else if (which_alternative == 1)
7287 /* Move source register to MEM, perform the branch test, then
7288 finally load the FP register from MEM from within the branch's
7290 output_asm_insn ("stw %1,-16(%%r30)", operands);
7292 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7293 else if (length == 16)
7294 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7297 operands[4] = GEN_INT (length - 4);
7298 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7299 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7300 return output_lbranch (operands[3], insn, 0);
7303 /* Deal with gross reload from memory case. */
7304 else if (which_alternative == 2)
7306 /* Reload loop counter from memory, the store back to memory
7307 happens in the branch's delay slot. */
7309 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7310 else if (length == 12)
7311 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7314 operands[4] = GEN_INT (length);
7315 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7317 return output_lbranch (operands[3], insn, 0);
7320 /* Handle SAR as a destination. */
7324 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7325 else if (length == 12)
7326 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7329 operands[4] = GEN_INT (length);
7330 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7332 return output_lbranch (operands[3], insn, 0);
7337 /* Copy any FP arguments in INSN into integer registers. */
7339 copy_fp_args (rtx insn)
7344 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7346 int arg_mode, regno;
7347 rtx use = XEXP (link, 0);
7349 if (! (GET_CODE (use) == USE
7350 && GET_CODE (XEXP (use, 0)) == REG
7351 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7354 arg_mode = GET_MODE (XEXP (use, 0));
7355 regno = REGNO (XEXP (use, 0));
7357 /* Is it a floating point register? */
7358 if (regno >= 32 && regno <= 39)
7360 /* Copy the FP register into an integer register via memory. */
7361 if (arg_mode == SFmode)
7363 xoperands[0] = XEXP (use, 0);
7364 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7365 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7366 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7370 xoperands[0] = XEXP (use, 0);
7371 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7372 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7373 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7374 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7380 /* Compute length of the FP argument copy sequence for INSN. */
7382 length_fp_args (rtx insn)
7387 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7389 int arg_mode, regno;
7390 rtx use = XEXP (link, 0);
7392 if (! (GET_CODE (use) == USE
7393 && GET_CODE (XEXP (use, 0)) == REG
7394 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7397 arg_mode = GET_MODE (XEXP (use, 0));
7398 regno = REGNO (XEXP (use, 0));
7400 /* Is it a floating point register? */
7401 if (regno >= 32 && regno <= 39)
7403 if (arg_mode == SFmode)
7413 /* Return the attribute length for the millicode call instruction INSN.
7414 The length must match the code generated by output_millicode_call.
7415 We include the delay slot in the returned length as it is better to
7416 over estimate the length than to under estimate it. */
7419 attr_length_millicode_call (rtx insn)
7421 unsigned long distance = -1;
7422 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7424 if (INSN_ADDRESSES_SET_P ())
7426 distance = (total + insn_current_reference_address (insn));
7427 if (distance < total)
7433 if (!TARGET_LONG_CALLS && distance < 7600000)
7438 else if (TARGET_PORTABLE_RUNTIME)
7442 if (!TARGET_LONG_CALLS && distance < 240000)
7445 if (TARGET_LONG_ABS_CALL && !flag_pic)
7452 /* INSN is a function call. It may have an unconditional jump
7455 CALL_DEST is the routine we are calling. */
7458 output_millicode_call (rtx insn, rtx call_dest)
7460 int attr_length = get_attr_length (insn);
7461 int seq_length = dbr_sequence_length ();
7466 xoperands[0] = call_dest;
7467 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7469 /* Handle the common case where we are sure that the branch will
7470 reach the beginning of the $CODE$ subspace. The within reach
7471 form of the $$sh_func_adrs call has a length of 28. Because
7472 it has an attribute type of multi, it never has a nonzero
7473 sequence length. The length of the $$sh_func_adrs is the same
7474 as certain out of reach PIC calls to other routines. */
7475 if (!TARGET_LONG_CALLS
7476 && ((seq_length == 0
7477 && (attr_length == 12
7478 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7479 || (seq_length != 0 && attr_length == 8)))
7481 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7487 /* It might seem that one insn could be saved by accessing
7488 the millicode function using the linkage table. However,
7489 this doesn't work in shared libraries and other dynamically
7490 loaded objects. Using a pc-relative sequence also avoids
7491 problems related to the implicit use of the gp register. */
7492 output_asm_insn ("b,l .+8,%%r1", xoperands);
7496 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7497 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7501 xoperands[1] = gen_label_rtx ();
7502 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7503 targetm.asm_out.internal_label (asm_out_file, "L",
7504 CODE_LABEL_NUMBER (xoperands[1]));
7505 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7508 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7510 else if (TARGET_PORTABLE_RUNTIME)
7512 /* Pure portable runtime doesn't allow be/ble; we also don't
7513 have PIC support in the assembler/linker, so this sequence
7516 /* Get the address of our target into %r1. */
7517 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7518 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7520 /* Get our return address into %r31. */
7521 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7522 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7524 /* Jump to our target address in %r1. */
7525 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7529 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7531 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7533 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7537 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7538 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7540 if (TARGET_SOM || !TARGET_GAS)
7542 /* The HP assembler can generate relocations for the
7543 difference of two symbols. GAS can do this for a
7544 millicode symbol but not an arbitrary external
7545 symbol when generating SOM output. */
7546 xoperands[1] = gen_label_rtx ();
7547 targetm.asm_out.internal_label (asm_out_file, "L",
7548 CODE_LABEL_NUMBER (xoperands[1]));
7549 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7550 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7554 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7555 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7559 /* Jump to our target address in %r1. */
7560 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7564 if (seq_length == 0)
7565 output_asm_insn ("nop", xoperands);
7567 /* We are done if there isn't a jump in the delay slot. */
7568 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7571 /* This call has an unconditional jump in its delay slot. */
7572 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7574 /* See if the return address can be adjusted. Use the containing
7575 sequence insn's address. */
7576 if (INSN_ADDRESSES_SET_P ())
7578 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7579 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7580 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7582 if (VAL_14_BITS_P (distance))
7584 xoperands[1] = gen_label_rtx ();
7585 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7586 targetm.asm_out.internal_label (asm_out_file, "L",
7587 CODE_LABEL_NUMBER (xoperands[1]));
7590 /* ??? This branch may not reach its target. */
7591 output_asm_insn ("nop\n\tb,n %0", xoperands);
7594 /* ??? This branch may not reach its target. */
7595 output_asm_insn ("nop\n\tb,n %0", xoperands);
7597 /* Delete the jump. */
7598 SET_INSN_DELETED (NEXT_INSN (insn));
7603 /* Return the attribute length of the call instruction INSN. The SIBCALL
7604 flag indicates whether INSN is a regular call or a sibling call. The
7605 length returned must be longer than the code actually generated by
7606 output_call. Since branch shortening is done before delay branch
7607 sequencing, there is no way to determine whether or not the delay
7608 slot will be filled during branch shortening. Even when the delay
7609 slot is filled, we may have to add a nop if the delay slot contains
7610 a branch that can't reach its target. Thus, we always have to include
7611 the delay slot in the length estimate. This used to be done in
7612 pa_adjust_insn_length but we do it here now as some sequences always
7613 fill the delay slot and we can save four bytes in the estimate for
7617 attr_length_call (rtx insn, int sibcall)
7620 rtx call, call_dest;
7623 rtx pat = PATTERN (insn);
7624 unsigned long distance = -1;
7626 gcc_assert (GET_CODE (insn) == CALL_INSN);
7628 if (INSN_ADDRESSES_SET_P ())
7630 unsigned long total;
7632 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7633 distance = (total + insn_current_reference_address (insn));
7634 if (distance < total)
7638 gcc_assert (GET_CODE (pat) == PARALLEL);
7640 /* Get the call rtx. */
7641 call = XVECEXP (pat, 0, 0);
7642 if (GET_CODE (call) == SET)
7643 call = SET_SRC (call);
7645 gcc_assert (GET_CODE (call) == CALL);
7647 /* Determine if this is a local call. */
7648 call_dest = XEXP (XEXP (call, 0), 0);
7649 call_decl = SYMBOL_REF_DECL (call_dest);
7650 local_call = call_decl && targetm.binds_local_p (call_decl);
7652 /* pc-relative branch. */
7653 if (!TARGET_LONG_CALLS
7654 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7655 || distance < 240000))
7658 /* 64-bit plabel sequence. */
7659 else if (TARGET_64BIT && !local_call)
7660 length += sibcall ? 28 : 24;
7662 /* non-pic long absolute branch sequence. */
7663 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7666 /* long pc-relative branch sequence. */
7667 else if (TARGET_LONG_PIC_SDIFF_CALL
7668 || (TARGET_GAS && !TARGET_SOM
7669 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7673 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7677 /* 32-bit plabel sequence. */
7683 length += length_fp_args (insn);
7693 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7701 /* INSN is a function call. It may have an unconditional jump
7704 CALL_DEST is the routine we are calling. */
7707 output_call (rtx insn, rtx call_dest, int sibcall)
7709 int delay_insn_deleted = 0;
7710 int delay_slot_filled = 0;
7711 int seq_length = dbr_sequence_length ();
7712 tree call_decl = SYMBOL_REF_DECL (call_dest);
7713 int local_call = call_decl && targetm.binds_local_p (call_decl);
7716 xoperands[0] = call_dest;
7718 /* Handle the common case where we're sure that the branch will reach
7719 the beginning of the "$CODE$" subspace. This is the beginning of
7720 the current function if we are in a named section. */
7721 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7723 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7724 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7728 if (TARGET_64BIT && !local_call)
7730 /* ??? As far as I can tell, the HP linker doesn't support the
7731 long pc-relative sequence described in the 64-bit runtime
7732 architecture. So, we use a slightly longer indirect call. */
7733 xoperands[0] = get_deferred_plabel (call_dest);
7734 xoperands[1] = gen_label_rtx ();
7736 /* If this isn't a sibcall, we put the load of %r27 into the
7737 delay slot. We can't do this in a sibcall as we don't
7738 have a second call-clobbered scratch register available. */
7740 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7743 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7746 /* Now delete the delay insn. */
7747 SET_INSN_DELETED (NEXT_INSN (insn));
7748 delay_insn_deleted = 1;
7751 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7752 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7753 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7757 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7758 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7759 output_asm_insn ("bve (%%r1)", xoperands);
7763 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7764 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7765 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7766 delay_slot_filled = 1;
7771 int indirect_call = 0;
7773 /* Emit a long call. There are several different sequences
7774 of increasing length and complexity. In most cases,
7775 they don't allow an instruction in the delay slot. */
7776 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7777 && !TARGET_LONG_PIC_SDIFF_CALL
7778 && !(TARGET_GAS && !TARGET_SOM
7779 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7784 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7788 || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)))
7790 /* A non-jump insn in the delay slot. By definition we can
7791 emit this insn before the call (and in fact before argument
7793 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7796 /* Now delete the delay insn. */
7797 SET_INSN_DELETED (NEXT_INSN (insn));
7798 delay_insn_deleted = 1;
7801 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7803 /* This is the best sequence for making long calls in
7804 non-pic code. Unfortunately, GNU ld doesn't provide
7805 the stub needed for external calls, and GAS's support
7806 for this with the SOM linker is buggy. It is safe
7807 to use this for local calls. */
7808 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7810 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7814 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7817 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7819 output_asm_insn ("copy %%r31,%%r2", xoperands);
7820 delay_slot_filled = 1;
7825 if (TARGET_LONG_PIC_SDIFF_CALL)
7827 /* The HP assembler and linker can handle relocations
7828 for the difference of two symbols. The HP assembler
7829 recognizes the sequence as a pc-relative call and
7830 the linker provides stubs when needed. */
7831 xoperands[1] = gen_label_rtx ();
7832 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7833 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7834 targetm.asm_out.internal_label (asm_out_file, "L",
7835 CODE_LABEL_NUMBER (xoperands[1]));
7836 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7838 else if (TARGET_GAS && !TARGET_SOM
7839 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7841 /* GAS currently can't generate the relocations that
7842 are needed for the SOM linker under HP-UX using this
7843 sequence. The GNU linker doesn't generate the stubs
7844 that are needed for external calls on TARGET_ELF32
7845 with this sequence. For now, we have to use a
7846 longer plabel sequence when using GAS. */
7847 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7848 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7850 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7855 /* Emit a long plabel-based call sequence. This is
7856 essentially an inline implementation of $$dyncall.
7857 We don't actually try to call $$dyncall as this is
7858 as difficult as calling the function itself. */
7859 xoperands[0] = get_deferred_plabel (call_dest);
7860 xoperands[1] = gen_label_rtx ();
7862 /* Since the call is indirect, FP arguments in registers
7863 need to be copied to the general registers. Then, the
7864 argument relocation stub will copy them back. */
7866 copy_fp_args (insn);
7870 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7871 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7872 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7876 output_asm_insn ("addil LR'%0-$global$,%%r27",
7878 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7882 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7883 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7884 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7885 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7887 if (!sibcall && !TARGET_PA_20)
7889 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7890 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7891 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7893 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7900 output_asm_insn ("bve (%%r1)", xoperands);
7905 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7906 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7907 delay_slot_filled = 1;
7910 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7915 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7916 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7921 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7922 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7924 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7928 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7929 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7931 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7934 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7936 output_asm_insn ("copy %%r31,%%r2", xoperands);
7937 delay_slot_filled = 1;
7944 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7945 output_asm_insn ("nop", xoperands);
7947 /* We are done if there isn't a jump in the delay slot. */
7949 || delay_insn_deleted
7950 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7953 /* A sibcall should never have a branch in the delay slot. */
7954 gcc_assert (!sibcall);
7956 /* This call has an unconditional jump in its delay slot. */
7957 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7959 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7961 /* See if the return address can be adjusted. Use the containing
7962 sequence insn's address. This would break the regular call/return@
7963 relationship assumed by the table based eh unwinder, so only do that
7964 if the call is not possibly throwing. */
7965 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7966 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7967 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7969 if (VAL_14_BITS_P (distance)
7970 && !(can_throw_internal (insn) || can_throw_external (insn)))
7972 xoperands[1] = gen_label_rtx ();
7973 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7974 targetm.asm_out.internal_label (asm_out_file, "L",
7975 CODE_LABEL_NUMBER (xoperands[1]));
7978 output_asm_insn ("nop\n\tb,n %0", xoperands);
7981 output_asm_insn ("b,n %0", xoperands);
7983 /* Delete the jump. */
7984 SET_INSN_DELETED (NEXT_INSN (insn));
7989 /* Return the attribute length of the indirect call instruction INSN.
7990 The length must match the code generated by output_indirect call.
7991 The returned length includes the delay slot. Currently, the delay
7992 slot of an indirect call sequence is not exposed and it is used by
7993 the sequence itself. */
7996 attr_length_indirect_call (rtx insn)
7998 unsigned long distance = -1;
7999 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
8001 if (INSN_ADDRESSES_SET_P ())
8003 distance = (total + insn_current_reference_address (insn));
8004 if (distance < total)
8011 if (TARGET_FAST_INDIRECT_CALLS
8012 || (!TARGET_PORTABLE_RUNTIME
8013 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
8014 || distance < 240000)))
8020 if (TARGET_PORTABLE_RUNTIME)
8023 /* Out of reach, can use ble. */
8028 output_indirect_call (rtx insn, rtx call_dest)
8034 xoperands[0] = call_dest;
8035 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
8036 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
8040 /* First the special case for kernels, level 0 systems, etc. */
8041 if (TARGET_FAST_INDIRECT_CALLS)
8042 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
8044 /* Now the normal case -- we can reach $$dyncall directly or
8045 we're sure that we can get there via a long-branch stub.
8047 No need to check target flags as the length uniquely identifies
8048 the remaining cases. */
8049 if (attr_length_indirect_call (insn) == 8)
8051 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
8052 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
8053 variant of the B,L instruction can't be used on the SOM target. */
8054 if (TARGET_PA_20 && !TARGET_SOM)
8055 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
8057 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
8060 /* Long millicode call, but we are not generating PIC or portable runtime
8062 if (attr_length_indirect_call (insn) == 12)
8063 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
8065 /* Long millicode call for portable runtime. */
8066 if (attr_length_indirect_call (insn) == 20)
8067 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
8069 /* We need a long PIC call to $$dyncall. */
8070 xoperands[0] = NULL_RTX;
8071 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8072 if (TARGET_SOM || !TARGET_GAS)
8074 xoperands[0] = gen_label_rtx ();
8075 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
8076 targetm.asm_out.internal_label (asm_out_file, "L",
8077 CODE_LABEL_NUMBER (xoperands[0]));
8078 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
8082 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
8083 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
8086 output_asm_insn ("blr %%r0,%%r2", xoperands);
8087 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
8091 /* Return the total length of the save and restore instructions needed for
8092 the data linkage table pointer (i.e., the PIC register) across the call
8093 instruction INSN. No-return calls do not require a save and restore.
8094 In addition, we may be able to avoid the save and restore for calls
8095 within the same translation unit. */
8098 attr_length_save_restore_dltp (rtx insn)
8100 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
8106 /* In HPUX 8.0's shared library scheme, special relocations are needed
8107 for function labels if they might be passed to a function
8108 in a shared library (because shared libraries don't live in code
8109 space), and special magic is needed to construct their address. */
8112 hppa_encode_label (rtx sym)
8114 const char *str = XSTR (sym, 0);
8115 int len = strlen (str) + 1;
8118 p = newstr = XALLOCAVEC (char, len + 1);
8122 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
8126 pa_encode_section_info (tree decl, rtx rtl, int first)
8128 int old_referenced = 0;
8130 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
8132 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
8134 default_encode_section_info (decl, rtl, first);
8136 if (first && TEXT_SPACE_P (decl))
8138 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
8139 if (TREE_CODE (decl) == FUNCTION_DECL)
8140 hppa_encode_label (XEXP (rtl, 0));
8142 else if (old_referenced)
8143 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
8146 /* This is sort of inverse to pa_encode_section_info. */
8149 pa_strip_name_encoding (const char *str)
8151 str += (*str == '@');
8152 str += (*str == '*');
8156 /* Returns 1 if OP is a function label involved in a simple addition
8157 with a constant. Used to keep certain patterns from matching
8158 during instruction combination. */
8160 is_function_label_plus_const (rtx op)
8162 /* Strip off any CONST. */
8163 if (GET_CODE (op) == CONST)
8166 return (GET_CODE (op) == PLUS
8167 && function_label_operand (XEXP (op, 0), VOIDmode)
8168 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8171 /* Output assembly code for a thunk to FUNCTION. */
8174 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
8175 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8178 static unsigned int current_thunk_number;
8179 int val_14 = VAL_14_BITS_P (delta);
8180 unsigned int old_last_address = last_address, nbytes = 0;
8184 xoperands[0] = XEXP (DECL_RTL (function), 0);
8185 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
8186 xoperands[2] = GEN_INT (delta);
8188 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
8189 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
8191 /* Output the thunk. We know that the function is in the same
8192 translation unit (i.e., the same space) as the thunk, and that
8193 thunks are output after their method. Thus, we don't need an
8194 external branch to reach the function. With SOM and GAS,
8195 functions and thunks are effectively in different sections.
8196 Thus, we can always use a IA-relative branch and the linker
8197 will add a long branch stub if necessary.
8199 However, we have to be careful when generating PIC code on the
8200 SOM port to ensure that the sequence does not transfer to an
8201 import stub for the target function as this could clobber the
8202 return value saved at SP-24. This would also apply to the
8203 32-bit linux port if the multi-space model is implemented. */
8204 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8205 && !(flag_pic && TREE_PUBLIC (function))
8206 && (TARGET_GAS || last_address < 262132))
8207 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8208 && ((targetm.have_named_sections
8209 && DECL_SECTION_NAME (thunk_fndecl) != NULL
8210 /* The GNU 64-bit linker has rather poor stub management.
8211 So, we use a long branch from thunks that aren't in
8212 the same section as the target function. */
8214 && (DECL_SECTION_NAME (thunk_fndecl)
8215 != DECL_SECTION_NAME (function)))
8216 || ((DECL_SECTION_NAME (thunk_fndecl)
8217 == DECL_SECTION_NAME (function))
8218 && last_address < 262132)))
8219 || (targetm.have_named_sections
8220 && DECL_SECTION_NAME (thunk_fndecl) == NULL
8221 && DECL_SECTION_NAME (function) == NULL
8222 && last_address < 262132)
8223 || (!targetm.have_named_sections && last_address < 262132))))
8226 output_asm_insn ("addil L'%2,%%r26", xoperands);
8228 output_asm_insn ("b %0", xoperands);
8232 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8237 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8241 else if (TARGET_64BIT)
8243 /* We only have one call-clobbered scratch register, so we can't
8244 make use of the delay slot if delta doesn't fit in 14 bits. */
8247 output_asm_insn ("addil L'%2,%%r26", xoperands);
8248 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8251 output_asm_insn ("b,l .+8,%%r1", xoperands);
8255 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8256 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8260 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8261 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8266 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8267 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8272 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8276 else if (TARGET_PORTABLE_RUNTIME)
8278 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8279 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8282 output_asm_insn ("addil L'%2,%%r26", xoperands);
8284 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8288 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8293 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8297 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8299 /* The function is accessible from outside this module. The only
8300 way to avoid an import stub between the thunk and function is to
8301 call the function directly with an indirect sequence similar to
8302 that used by $$dyncall. This is possible because $$dyncall acts
8303 as the import stub in an indirect call. */
8304 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8305 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8306 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8307 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8308 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8309 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8310 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8311 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8312 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8316 output_asm_insn ("addil L'%2,%%r26", xoperands);
8322 output_asm_insn ("bve (%%r22)", xoperands);
8325 else if (TARGET_NO_SPACE_REGS)
8327 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8332 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8333 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8334 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8339 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8341 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8345 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8347 if (TARGET_SOM || !TARGET_GAS)
8349 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8350 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8354 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8355 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8359 output_asm_insn ("addil L'%2,%%r26", xoperands);
8361 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8365 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8370 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8377 output_asm_insn ("addil L'%2,%%r26", xoperands);
8379 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8380 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8384 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8389 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8394 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8396 if (TARGET_SOM && TARGET_GAS)
8398 /* We done with this subspace except possibly for some additional
8399 debug information. Forget that we are in this subspace to ensure
8400 that the next function is output in its own subspace. */
8402 cfun->machine->in_nsubspa = 2;
8405 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8407 switch_to_section (data_section);
8408 output_asm_insn (".align 4", xoperands);
8409 ASM_OUTPUT_LABEL (file, label);
8410 output_asm_insn (".word P'%0", xoperands);
8413 current_thunk_number++;
8414 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8415 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8416 last_address += nbytes;
8417 if (old_last_address > last_address)
8418 last_address = UINT_MAX;
8419 update_total_code_bytes (nbytes);
8422 /* Only direct calls to static functions are allowed to be sibling (tail)
8425 This restriction is necessary because some linker generated stubs will
8426 store return pointers into rp' in some cases which might clobber a
8427 live value already in rp'.
8429 In a sibcall the current function and the target function share stack
8430 space. Thus if the path to the current function and the path to the
8431 target function save a value in rp', they save the value into the
8432 same stack slot, which has undesirable consequences.
8434 Because of the deferred binding nature of shared libraries any function
8435 with external scope could be in a different load module and thus require
8436 rp' to be saved when calling that function. So sibcall optimizations
8437 can only be safe for static function.
8439 Note that GCC never needs return value relocations, so we don't have to
8440 worry about static calls with return value relocations (which require
8443 It is safe to perform a sibcall optimization when the target function
8444 will never return. */
8446 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8448 if (TARGET_PORTABLE_RUNTIME)
8451 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8452 single subspace mode and the call is not indirect. As far as I know,
8453 there is no operating system support for the multiple subspace mode.
8454 It might be possible to support indirect calls if we didn't use
8455 $$dyncall (see the indirect sequence generated in output_call). */
8457 return (decl != NULL_TREE);
8459 /* Sibcalls are not ok because the arg pointer register is not a fixed
8460 register. This prevents the sibcall optimization from occurring. In
8461 addition, there are problems with stub placement using GNU ld. This
8462 is because a normal sibcall branch uses a 17-bit relocation while
8463 a regular call branch uses a 22-bit relocation. As a result, more
8464 care needs to be taken in the placement of long-branch stubs. */
8468 /* Sibcalls are only ok within a translation unit. */
8469 return (decl && !TREE_PUBLIC (decl));
8472 /* ??? Addition is not commutative on the PA due to the weird implicit
8473 space register selection rules for memory addresses. Therefore, we
8474 don't consider a + b == b + a, as this might be inside a MEM. */
8476 pa_commutative_p (const_rtx x, int outer_code)
8478 return (COMMUTATIVE_P (x)
8479 && (TARGET_NO_SPACE_REGS
8480 || (outer_code != UNKNOWN && outer_code != MEM)
8481 || GET_CODE (x) != PLUS));
8484 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8485 use in fmpyadd instructions. */
8487 fmpyaddoperands (rtx *operands)
8489 enum machine_mode mode = GET_MODE (operands[0]);
8491 /* Must be a floating point mode. */
8492 if (mode != SFmode && mode != DFmode)
8495 /* All modes must be the same. */
8496 if (! (mode == GET_MODE (operands[1])
8497 && mode == GET_MODE (operands[2])
8498 && mode == GET_MODE (operands[3])
8499 && mode == GET_MODE (operands[4])
8500 && mode == GET_MODE (operands[5])))
8503 /* All operands must be registers. */
8504 if (! (GET_CODE (operands[1]) == REG
8505 && GET_CODE (operands[2]) == REG
8506 && GET_CODE (operands[3]) == REG
8507 && GET_CODE (operands[4]) == REG
8508 && GET_CODE (operands[5]) == REG))
8511 /* Only 2 real operands to the addition. One of the input operands must
8512 be the same as the output operand. */
8513 if (! rtx_equal_p (operands[3], operands[4])
8514 && ! rtx_equal_p (operands[3], operands[5]))
8517 /* Inout operand of add cannot conflict with any operands from multiply. */
8518 if (rtx_equal_p (operands[3], operands[0])
8519 || rtx_equal_p (operands[3], operands[1])
8520 || rtx_equal_p (operands[3], operands[2]))
8523 /* multiply cannot feed into addition operands. */
8524 if (rtx_equal_p (operands[4], operands[0])
8525 || rtx_equal_p (operands[5], operands[0]))
8528 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8530 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8531 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8532 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8533 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8534 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8535 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8538 /* Passed. Operands are suitable for fmpyadd. */
8542 #if !defined(USE_COLLECT2)
8544 pa_asm_out_constructor (rtx symbol, int priority)
8546 if (!function_label_operand (symbol, VOIDmode))
8547 hppa_encode_label (symbol);
8549 #ifdef CTORS_SECTION_ASM_OP
8550 default_ctor_section_asm_out_constructor (symbol, priority);
8552 # ifdef TARGET_ASM_NAMED_SECTION
8553 default_named_section_asm_out_constructor (symbol, priority);
8555 default_stabs_asm_out_constructor (symbol, priority);
8561 pa_asm_out_destructor (rtx symbol, int priority)
8563 if (!function_label_operand (symbol, VOIDmode))
8564 hppa_encode_label (symbol);
8566 #ifdef DTORS_SECTION_ASM_OP
8567 default_dtor_section_asm_out_destructor (symbol, priority);
8569 # ifdef TARGET_ASM_NAMED_SECTION
8570 default_named_section_asm_out_destructor (symbol, priority);
8572 default_stabs_asm_out_destructor (symbol, priority);
8578 /* This function places uninitialized global data in the bss section.
8579 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8580 function on the SOM port to prevent uninitialized global data from
8581 being placed in the data section. */
8584 pa_asm_output_aligned_bss (FILE *stream,
8586 unsigned HOST_WIDE_INT size,
8589 switch_to_section (bss_section);
8590 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8592 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8593 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8596 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8597 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8600 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8601 ASM_OUTPUT_LABEL (stream, name);
8602 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8605 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8606 that doesn't allow the alignment of global common storage to be directly
8607 specified. The SOM linker aligns common storage based on the rounded
8608 value of the NUM_BYTES parameter in the .comm directive. It's not
8609 possible to use the .align directive as it doesn't affect the alignment
8610 of the label associated with a .comm directive. */
8613 pa_asm_output_aligned_common (FILE *stream,
8615 unsigned HOST_WIDE_INT size,
8618 unsigned int max_common_align;
8620 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8621 if (align > max_common_align)
8623 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8624 "for global common data. Using %u",
8625 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8626 align = max_common_align;
8629 switch_to_section (bss_section);
8631 assemble_name (stream, name);
8632 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8633 MAX (size, align / BITS_PER_UNIT));
8636 /* We can't use .comm for local common storage as the SOM linker effectively
8637 treats the symbol as universal and uses the same storage for local symbols
8638 with the same name in different object files. The .block directive
8639 reserves an uninitialized block of storage. However, it's not common
8640 storage. Fortunately, GCC never requests common storage with the same
8641 name in any given translation unit. */
8644 pa_asm_output_aligned_local (FILE *stream,
8646 unsigned HOST_WIDE_INT size,
8649 switch_to_section (bss_section);
8650 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8653 fprintf (stream, "%s", LOCAL_ASM_OP);
8654 assemble_name (stream, name);
8655 fprintf (stream, "\n");
8658 ASM_OUTPUT_LABEL (stream, name);
8659 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8662 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8663 use in fmpysub instructions. */
8665 fmpysuboperands (rtx *operands)
8667 enum machine_mode mode = GET_MODE (operands[0]);
8669 /* Must be a floating point mode. */
8670 if (mode != SFmode && mode != DFmode)
8673 /* All modes must be the same. */
8674 if (! (mode == GET_MODE (operands[1])
8675 && mode == GET_MODE (operands[2])
8676 && mode == GET_MODE (operands[3])
8677 && mode == GET_MODE (operands[4])
8678 && mode == GET_MODE (operands[5])))
8681 /* All operands must be registers. */
8682 if (! (GET_CODE (operands[1]) == REG
8683 && GET_CODE (operands[2]) == REG
8684 && GET_CODE (operands[3]) == REG
8685 && GET_CODE (operands[4]) == REG
8686 && GET_CODE (operands[5]) == REG))
8689 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8690 operation, so operands[4] must be the same as operand[3]. */
8691 if (! rtx_equal_p (operands[3], operands[4]))
8694 /* multiply cannot feed into subtraction. */
8695 if (rtx_equal_p (operands[5], operands[0]))
8698 /* Inout operand of sub cannot conflict with any operands from multiply. */
8699 if (rtx_equal_p (operands[3], operands[0])
8700 || rtx_equal_p (operands[3], operands[1])
8701 || rtx_equal_p (operands[3], operands[2]))
8704 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8706 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8707 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8708 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8709 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8710 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8711 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8714 /* Passed. Operands are suitable for fmpysub. */
8718 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8719 constants for shadd instructions. */
8721 shadd_constant_p (int val)
8723 if (val == 2 || val == 4 || val == 8)
8729 /* Return TRUE if INSN branches forward. */
8732 forward_branch_p (rtx insn)
8734 rtx lab = JUMP_LABEL (insn);
8736 /* The INSN must have a jump label. */
8737 gcc_assert (lab != NULL_RTX);
8739 if (INSN_ADDRESSES_SET_P ())
8740 return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn));
8747 insn = NEXT_INSN (insn);
8753 /* Return 1 if INSN is in the delay slot of a call instruction. */
8755 jump_in_call_delay (rtx insn)
8758 if (GET_CODE (insn) != JUMP_INSN)
8761 if (PREV_INSN (insn)
8762 && PREV_INSN (PREV_INSN (insn))
8763 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8765 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8767 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8768 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8775 /* Output an unconditional move and branch insn. */
8778 output_parallel_movb (rtx *operands, rtx insn)
8780 int length = get_attr_length (insn);
8782 /* These are the cases in which we win. */
8784 return "mov%I1b,tr %1,%0,%2";
8786 /* None of the following cases win, but they don't lose either. */
8789 if (dbr_sequence_length () == 0)
8791 /* Nothing in the delay slot, fake it by putting the combined
8792 insn (the copy or add) in the delay slot of a bl. */
8793 if (GET_CODE (operands[1]) == CONST_INT)
8794 return "b %2\n\tldi %1,%0";
8796 return "b %2\n\tcopy %1,%0";
8800 /* Something in the delay slot, but we've got a long branch. */
8801 if (GET_CODE (operands[1]) == CONST_INT)
8802 return "ldi %1,%0\n\tb %2";
8804 return "copy %1,%0\n\tb %2";
8808 if (GET_CODE (operands[1]) == CONST_INT)
8809 output_asm_insn ("ldi %1,%0", operands);
8811 output_asm_insn ("copy %1,%0", operands);
8812 return output_lbranch (operands[2], insn, 1);
8815 /* Output an unconditional add and branch insn. */
8818 output_parallel_addb (rtx *operands, rtx insn)
8820 int length = get_attr_length (insn);
8822 /* To make life easy we want operand0 to be the shared input/output
8823 operand and operand1 to be the readonly operand. */
8824 if (operands[0] == operands[1])
8825 operands[1] = operands[2];
8827 /* These are the cases in which we win. */
8829 return "add%I1b,tr %1,%0,%3";
8831 /* None of the following cases win, but they don't lose either. */
8834 if (dbr_sequence_length () == 0)
8835 /* Nothing in the delay slot, fake it by putting the combined
8836 insn (the copy or add) in the delay slot of a bl. */
8837 return "b %3\n\tadd%I1 %1,%0,%0";
8839 /* Something in the delay slot, but we've got a long branch. */
8840 return "add%I1 %1,%0,%0\n\tb %3";
8843 output_asm_insn ("add%I1 %1,%0,%0", operands);
8844 return output_lbranch (operands[3], insn, 1);
8847 /* Return nonzero if INSN (a jump insn) immediately follows a call
8848 to a named function. This is used to avoid filling the delay slot
8849 of the jump since it can usually be eliminated by modifying RP in
8850 the delay slot of the call. */
8853 following_call (rtx insn)
8855 if (! TARGET_JUMP_IN_DELAY)
8858 /* Find the previous real insn, skipping NOTEs. */
8859 insn = PREV_INSN (insn);
8860 while (insn && GET_CODE (insn) == NOTE)
8861 insn = PREV_INSN (insn);
8863 /* Check for CALL_INSNs and millicode calls. */
8865 && ((GET_CODE (insn) == CALL_INSN
8866 && get_attr_type (insn) != TYPE_DYNCALL)
8867 || (GET_CODE (insn) == INSN
8868 && GET_CODE (PATTERN (insn)) != SEQUENCE
8869 && GET_CODE (PATTERN (insn)) != USE
8870 && GET_CODE (PATTERN (insn)) != CLOBBER
8871 && get_attr_type (insn) == TYPE_MILLI)))
8877 /* We use this hook to perform a PA specific optimization which is difficult
8878 to do in earlier passes.
8880 We want the delay slots of branches within jump tables to be filled.
8881 None of the compiler passes at the moment even has the notion that a
8882 PA jump table doesn't contain addresses, but instead contains actual
8885 Because we actually jump into the table, the addresses of each entry
8886 must stay constant in relation to the beginning of the table (which
8887 itself must stay constant relative to the instruction to jump into
8888 it). I don't believe we can guarantee earlier passes of the compiler
8889 will adhere to those rules.
8891 So, late in the compilation process we find all the jump tables, and
8892 expand them into real code -- e.g. each entry in the jump table vector
8893 will get an appropriate label followed by a jump to the final target.
8895 Reorg and the final jump pass can then optimize these branches and
8896 fill their delay slots. We end up with smaller, more efficient code.
8898 The jump instructions within the table are special; we must be able
8899 to identify them during assembly output (if the jumps don't get filled
8900 we need to emit a nop rather than nullifying the delay slot)). We
8901 identify jumps in switch tables by using insns with the attribute
8902 type TYPE_BTABLE_BRANCH.
8904 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8905 insns. This serves two purposes, first it prevents jump.c from
8906 noticing that the last N entries in the table jump to the instruction
8907 immediately after the table and deleting the jumps. Second, those
8908 insns mark where we should emit .begin_brtab and .end_brtab directives
8909 when using GAS (allows for better link time optimizations). */
8916 remove_useless_addtr_insns (1);
8918 if (pa_cpu < PROCESSOR_8000)
8919 pa_combine_instructions ();
8922 /* This is fairly cheap, so always run it if optimizing. */
8923 if (optimize > 0 && !TARGET_BIG_SWITCH)
8925 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8926 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8928 rtx pattern, tmp, location, label;
8929 unsigned int length, i;
8931 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8932 if (GET_CODE (insn) != JUMP_INSN
8933 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8934 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8937 /* Emit marker for the beginning of the branch table. */
8938 emit_insn_before (gen_begin_brtab (), insn);
8940 pattern = PATTERN (insn);
8941 location = PREV_INSN (insn);
8942 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8944 for (i = 0; i < length; i++)
8946 /* Emit a label before each jump to keep jump.c from
8947 removing this code. */
8948 tmp = gen_label_rtx ();
8949 LABEL_NUSES (tmp) = 1;
8950 emit_label_after (tmp, location);
8951 location = NEXT_INSN (location);
8953 if (GET_CODE (pattern) == ADDR_VEC)
8954 label = XEXP (XVECEXP (pattern, 0, i), 0);
8956 label = XEXP (XVECEXP (pattern, 1, i), 0);
8958 tmp = gen_short_jump (label);
8960 /* Emit the jump itself. */
8961 tmp = emit_jump_insn_after (tmp, location);
8962 JUMP_LABEL (tmp) = label;
8963 LABEL_NUSES (label)++;
8964 location = NEXT_INSN (location);
8966 /* Emit a BARRIER after the jump. */
8967 emit_barrier_after (location);
8968 location = NEXT_INSN (location);
8971 /* Emit marker for the end of the branch table. */
8972 emit_insn_before (gen_end_brtab (), location);
8973 location = NEXT_INSN (location);
8974 emit_barrier_after (location);
8976 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8982 /* Still need brtab marker insns. FIXME: the presence of these
8983 markers disables output of the branch table to readonly memory,
8984 and any alignment directives that might be needed. Possibly,
8985 the begin_brtab insn should be output before the label for the
8986 table. This doesn't matter at the moment since the tables are
8987 always output in the text section. */
8988 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8990 /* Find an ADDR_VEC insn. */
8991 if (GET_CODE (insn) != JUMP_INSN
8992 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8993 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8996 /* Now generate markers for the beginning and end of the
8998 emit_insn_before (gen_begin_brtab (), insn);
8999 emit_insn_after (gen_end_brtab (), insn);
9004 /* The PA has a number of odd instructions which can perform multiple
9005 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
9006 it may be profitable to combine two instructions into one instruction
9007 with two outputs. It's not profitable PA2.0 machines because the
9008 two outputs would take two slots in the reorder buffers.
9010 This routine finds instructions which can be combined and combines
9011 them. We only support some of the potential combinations, and we
9012 only try common ways to find suitable instructions.
9014 * addb can add two registers or a register and a small integer
9015 and jump to a nearby (+-8k) location. Normally the jump to the
9016 nearby location is conditional on the result of the add, but by
9017 using the "true" condition we can make the jump unconditional.
9018 Thus addb can perform two independent operations in one insn.
9020 * movb is similar to addb in that it can perform a reg->reg
9021 or small immediate->reg copy and jump to a nearby (+-8k location).
9023 * fmpyadd and fmpysub can perform a FP multiply and either an
9024 FP add or FP sub if the operands of the multiply and add/sub are
9025 independent (there are other minor restrictions). Note both
9026 the fmpy and fadd/fsub can in theory move to better spots according
9027 to data dependencies, but for now we require the fmpy stay at a
9030 * Many of the memory operations can perform pre & post updates
9031 of index registers. GCC's pre/post increment/decrement addressing
9032 is far too simple to take advantage of all the possibilities. This
9033 pass may not be suitable since those insns may not be independent.
9035 * comclr can compare two ints or an int and a register, nullify
9036 the following instruction and zero some other register. This
9037 is more difficult to use as it's harder to find an insn which
9038 will generate a comclr than finding something like an unconditional
9039 branch. (conditional moves & long branches create comclr insns).
9041 * Most arithmetic operations can conditionally skip the next
9042 instruction. They can be viewed as "perform this operation
9043 and conditionally jump to this nearby location" (where nearby
9044 is an insns away). These are difficult to use due to the
9045 branch length restrictions. */
9048 pa_combine_instructions (void)
9050 rtx anchor, new_rtx;
9052 /* This can get expensive since the basic algorithm is on the
9053 order of O(n^2) (or worse). Only do it for -O2 or higher
9054 levels of optimization. */
9058 /* Walk down the list of insns looking for "anchor" insns which
9059 may be combined with "floating" insns. As the name implies,
9060 "anchor" instructions don't move, while "floating" insns may
9062 new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
9063 new_rtx = make_insn_raw (new_rtx);
9065 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
9067 enum attr_pa_combine_type anchor_attr;
9068 enum attr_pa_combine_type floater_attr;
9070 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9071 Also ignore any special USE insns. */
9072 if ((GET_CODE (anchor) != INSN
9073 && GET_CODE (anchor) != JUMP_INSN
9074 && GET_CODE (anchor) != CALL_INSN)
9075 || GET_CODE (PATTERN (anchor)) == USE
9076 || GET_CODE (PATTERN (anchor)) == CLOBBER
9077 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
9078 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
9081 anchor_attr = get_attr_pa_combine_type (anchor);
9082 /* See if anchor is an insn suitable for combination. */
9083 if (anchor_attr == PA_COMBINE_TYPE_FMPY
9084 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
9085 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9086 && ! forward_branch_p (anchor)))
9090 for (floater = PREV_INSN (anchor);
9092 floater = PREV_INSN (floater))
9094 if (GET_CODE (floater) == NOTE
9095 || (GET_CODE (floater) == INSN
9096 && (GET_CODE (PATTERN (floater)) == USE
9097 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9100 /* Anything except a regular INSN will stop our search. */
9101 if (GET_CODE (floater) != INSN
9102 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9103 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9109 /* See if FLOATER is suitable for combination with the
9111 floater_attr = get_attr_pa_combine_type (floater);
9112 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9113 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9114 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9115 && floater_attr == PA_COMBINE_TYPE_FMPY))
9117 /* If ANCHOR and FLOATER can be combined, then we're
9118 done with this pass. */
9119 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9120 SET_DEST (PATTERN (floater)),
9121 XEXP (SET_SRC (PATTERN (floater)), 0),
9122 XEXP (SET_SRC (PATTERN (floater)), 1)))
9126 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9127 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
9129 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
9131 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9132 SET_DEST (PATTERN (floater)),
9133 XEXP (SET_SRC (PATTERN (floater)), 0),
9134 XEXP (SET_SRC (PATTERN (floater)), 1)))
9139 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9140 SET_DEST (PATTERN (floater)),
9141 SET_SRC (PATTERN (floater)),
9142 SET_SRC (PATTERN (floater))))
9148 /* If we didn't find anything on the backwards scan try forwards. */
9150 && (anchor_attr == PA_COMBINE_TYPE_FMPY
9151 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
9153 for (floater = anchor; floater; floater = NEXT_INSN (floater))
9155 if (GET_CODE (floater) == NOTE
9156 || (GET_CODE (floater) == INSN
9157 && (GET_CODE (PATTERN (floater)) == USE
9158 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9162 /* Anything except a regular INSN will stop our search. */
9163 if (GET_CODE (floater) != INSN
9164 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9165 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9171 /* See if FLOATER is suitable for combination with the
9173 floater_attr = get_attr_pa_combine_type (floater);
9174 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9175 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9176 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9177 && floater_attr == PA_COMBINE_TYPE_FMPY))
9179 /* If ANCHOR and FLOATER can be combined, then we're
9180 done with this pass. */
9181 if (pa_can_combine_p (new_rtx, anchor, floater, 1,
9182 SET_DEST (PATTERN (floater)),
9183 XEXP (SET_SRC (PATTERN (floater)),
9185 XEXP (SET_SRC (PATTERN (floater)),
9192 /* FLOATER will be nonzero if we found a suitable floating
9193 insn for combination with ANCHOR. */
9195 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9196 || anchor_attr == PA_COMBINE_TYPE_FMPY))
9198 /* Emit the new instruction and delete the old anchor. */
9199 emit_insn_before (gen_rtx_PARALLEL
9201 gen_rtvec (2, PATTERN (anchor),
9202 PATTERN (floater))),
9205 SET_INSN_DELETED (anchor);
9207 /* Emit a special USE insn for FLOATER, then delete
9208 the floating insn. */
9209 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9210 delete_insn (floater);
9215 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9218 /* Emit the new_jump instruction and delete the old anchor. */
9220 = emit_jump_insn_before (gen_rtx_PARALLEL
9222 gen_rtvec (2, PATTERN (anchor),
9223 PATTERN (floater))),
9226 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9227 SET_INSN_DELETED (anchor);
9229 /* Emit a special USE insn for FLOATER, then delete
9230 the floating insn. */
9231 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9232 delete_insn (floater);
9240 pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
9243 int insn_code_number;
9246 /* Create a PARALLEL with the patterns of ANCHOR and
9247 FLOATER, try to recognize it, then test constraints
9248 for the resulting pattern.
9250 If the pattern doesn't match or the constraints
9251 aren't met keep searching for a suitable floater
9253 XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
9254 XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
9255 INSN_CODE (new_rtx) = -1;
9256 insn_code_number = recog_memoized (new_rtx);
9257 if (insn_code_number < 0
9258 || (extract_insn (new_rtx), ! constrain_operands (1)))
9272 /* There's up to three operands to consider. One
9273 output and two inputs.
9275 The output must not be used between FLOATER & ANCHOR
9276 exclusive. The inputs must not be set between
9277 FLOATER and ANCHOR exclusive. */
9279 if (reg_used_between_p (dest, start, end))
9282 if (reg_set_between_p (src1, start, end))
9285 if (reg_set_between_p (src2, start, end))
9288 /* If we get here, then everything is good. */
9292 /* Return nonzero if references for INSN are delayed.
9294 Millicode insns are actually function calls with some special
9295 constraints on arguments and register usage.
9297 Millicode calls always expect their arguments in the integer argument
9298 registers, and always return their result in %r29 (ret1). They
9299 are expected to clobber their arguments, %r1, %r29, and the return
9300 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9302 This function tells reorg that the references to arguments and
9303 millicode calls do not appear to happen until after the millicode call.
9304 This allows reorg to put insns which set the argument registers into the
9305 delay slot of the millicode call -- thus they act more like traditional
9308 Note we cannot consider side effects of the insn to be delayed because
9309 the branch and link insn will clobber the return pointer. If we happened
9310 to use the return pointer in the delay slot of the call, then we lose.
9312 get_attr_type will try to recognize the given insn, so make sure to
9313 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9316 insn_refs_are_delayed (rtx insn)
9318 return ((GET_CODE (insn) == INSN
9319 && GET_CODE (PATTERN (insn)) != SEQUENCE
9320 && GET_CODE (PATTERN (insn)) != USE
9321 && GET_CODE (PATTERN (insn)) != CLOBBER
9322 && get_attr_type (insn) == TYPE_MILLI));
9325 /* Promote the return value, but not the arguments. */
9327 static enum machine_mode
9328 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
9329 enum machine_mode mode,
9330 int *punsignedp ATTRIBUTE_UNUSED,
9331 const_tree fntype ATTRIBUTE_UNUSED,
9334 if (for_return == 0)
9336 return promote_mode (type, mode, punsignedp);
9339 /* On the HP-PA the value is found in register(s) 28(-29), unless
9340 the mode is SF or DF. Then the value is returned in fr4 (32).
9342 This must perform the same promotions as PROMOTE_MODE, else promoting
9343 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9345 Small structures must be returned in a PARALLEL on PA64 in order
9346 to match the HP Compiler ABI. */
9349 pa_function_value (const_tree valtype,
9350 const_tree func ATTRIBUTE_UNUSED,
9351 bool outgoing ATTRIBUTE_UNUSED)
9353 enum machine_mode valmode;
9355 if (AGGREGATE_TYPE_P (valtype)
9356 || TREE_CODE (valtype) == COMPLEX_TYPE
9357 || TREE_CODE (valtype) == VECTOR_TYPE)
9361 /* Aggregates with a size less than or equal to 128 bits are
9362 returned in GR 28(-29). They are left justified. The pad
9363 bits are undefined. Larger aggregates are returned in
9367 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9369 for (i = 0; i < ub; i++)
9371 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9372 gen_rtx_REG (DImode, 28 + i),
9377 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9379 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9381 /* Aggregates 5 to 8 bytes in size are returned in general
9382 registers r28-r29 in the same manner as other non
9383 floating-point objects. The data is right-justified and
9384 zero-extended to 64 bits. This is opposite to the normal
9385 justification used on big endian targets and requires
9386 special treatment. */
9387 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9388 gen_rtx_REG (DImode, 28), const0_rtx);
9389 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9393 if ((INTEGRAL_TYPE_P (valtype)
9394 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9395 || POINTER_TYPE_P (valtype))
9396 valmode = word_mode;
9398 valmode = TYPE_MODE (valtype);
9400 if (TREE_CODE (valtype) == REAL_TYPE
9401 && !AGGREGATE_TYPE_P (valtype)
9402 && TYPE_MODE (valtype) != TFmode
9403 && !TARGET_SOFT_FLOAT)
9404 return gen_rtx_REG (valmode, 32);
9406 return gen_rtx_REG (valmode, 28);
9409 /* Implement the TARGET_LIBCALL_VALUE hook. */
9412 pa_libcall_value (enum machine_mode mode,
9413 const_rtx fun ATTRIBUTE_UNUSED)
9415 if (! TARGET_SOFT_FLOAT
9416 && (mode == SFmode || mode == DFmode))
9417 return gen_rtx_REG (mode, 32);
9419 return gen_rtx_REG (mode, 28);
9422 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9425 pa_function_value_regno_p (const unsigned int regno)
9428 || (! TARGET_SOFT_FLOAT && regno == 32))
9434 /* Update the data in CUM to advance over an argument
9435 of mode MODE and data type TYPE.
9436 (TYPE is null for libcalls where that information may not be available.) */
9439 pa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9440 const_tree type, bool named ATTRIBUTE_UNUSED)
9442 int arg_size = FUNCTION_ARG_SIZE (mode, type);
9444 cum->nargs_prototype--;
9445 cum->words += (arg_size
9446 + ((cum->words & 01)
9447 && type != NULL_TREE
9451 /* Return the location of a parameter that is passed in a register or NULL
9452 if the parameter has any component that is passed in memory.
9454 This is new code and will be pushed to into the net sources after
9457 ??? We might want to restructure this so that it looks more like other
9460 pa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9461 const_tree type, bool named ATTRIBUTE_UNUSED)
9463 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9470 if (mode == VOIDmode)
9473 arg_size = FUNCTION_ARG_SIZE (mode, type);
9475 /* If this arg would be passed partially or totally on the stack, then
9476 this routine should return zero. pa_arg_partial_bytes will
9477 handle arguments which are split between regs and stack slots if
9478 the ABI mandates split arguments. */
9481 /* The 32-bit ABI does not split arguments. */
9482 if (cum->words + arg_size > max_arg_words)
9488 alignment = cum->words & 1;
9489 if (cum->words + alignment >= max_arg_words)
9493 /* The 32bit ABIs and the 64bit ABIs are rather different,
9494 particularly in their handling of FP registers. We might
9495 be able to cleverly share code between them, but I'm not
9496 going to bother in the hope that splitting them up results
9497 in code that is more easily understood. */
9501 /* Advance the base registers to their current locations.
9503 Remember, gprs grow towards smaller register numbers while
9504 fprs grow to higher register numbers. Also remember that
9505 although FP regs are 32-bit addressable, we pretend that
9506 the registers are 64-bits wide. */
9507 gpr_reg_base = 26 - cum->words;
9508 fpr_reg_base = 32 + cum->words;
9510 /* Arguments wider than one word and small aggregates need special
9514 || (type && (AGGREGATE_TYPE_P (type)
9515 || TREE_CODE (type) == COMPLEX_TYPE
9516 || TREE_CODE (type) == VECTOR_TYPE)))
9518 /* Double-extended precision (80-bit), quad-precision (128-bit)
9519 and aggregates including complex numbers are aligned on
9520 128-bit boundaries. The first eight 64-bit argument slots
9521 are associated one-to-one, with general registers r26
9522 through r19, and also with floating-point registers fr4
9523 through fr11. Arguments larger than one word are always
9524 passed in general registers.
9526 Using a PARALLEL with a word mode register results in left
9527 justified data on a big-endian target. */
9530 int i, offset = 0, ub = arg_size;
9532 /* Align the base register. */
9533 gpr_reg_base -= alignment;
9535 ub = MIN (ub, max_arg_words - cum->words - alignment);
9536 for (i = 0; i < ub; i++)
9538 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9539 gen_rtx_REG (DImode, gpr_reg_base),
9545 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9550 /* If the argument is larger than a word, then we know precisely
9551 which registers we must use. */
9565 /* Structures 5 to 8 bytes in size are passed in the general
9566 registers in the same manner as other non floating-point
9567 objects. The data is right-justified and zero-extended
9568 to 64 bits. This is opposite to the normal justification
9569 used on big endian targets and requires special treatment.
9570 We now define BLOCK_REG_PADDING to pad these objects.
9571 Aggregates, complex and vector types are passed in the same
9572 manner as structures. */
9574 || (type && (AGGREGATE_TYPE_P (type)
9575 || TREE_CODE (type) == COMPLEX_TYPE
9576 || TREE_CODE (type) == VECTOR_TYPE)))
9578 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9579 gen_rtx_REG (DImode, gpr_reg_base),
9581 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9586 /* We have a single word (32 bits). A simple computation
9587 will get us the register #s we need. */
9588 gpr_reg_base = 26 - cum->words;
9589 fpr_reg_base = 32 + 2 * cum->words;
9593 /* Determine if the argument needs to be passed in both general and
9594 floating point registers. */
9595 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9596 /* If we are doing soft-float with portable runtime, then there
9597 is no need to worry about FP regs. */
9598 && !TARGET_SOFT_FLOAT
9599 /* The parameter must be some kind of scalar float, else we just
9600 pass it in integer registers. */
9601 && GET_MODE_CLASS (mode) == MODE_FLOAT
9602 /* The target function must not have a prototype. */
9603 && cum->nargs_prototype <= 0
9604 /* libcalls do not need to pass items in both FP and general
9606 && type != NULL_TREE
9607 /* All this hair applies to "outgoing" args only. This includes
9608 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9610 /* Also pass outgoing floating arguments in both registers in indirect
9611 calls with the 32 bit ABI and the HP assembler since there is no
9612 way to the specify argument locations in static functions. */
9617 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9623 gen_rtx_EXPR_LIST (VOIDmode,
9624 gen_rtx_REG (mode, fpr_reg_base),
9626 gen_rtx_EXPR_LIST (VOIDmode,
9627 gen_rtx_REG (mode, gpr_reg_base),
9632 /* See if we should pass this parameter in a general register. */
9633 if (TARGET_SOFT_FLOAT
9634 /* Indirect calls in the normal 32bit ABI require all arguments
9635 to be passed in general registers. */
9636 || (!TARGET_PORTABLE_RUNTIME
9640 /* If the parameter is not a scalar floating-point parameter,
9641 then it belongs in GPRs. */
9642 || GET_MODE_CLASS (mode) != MODE_FLOAT
9643 /* Structure with single SFmode field belongs in GPR. */
9644 || (type && AGGREGATE_TYPE_P (type)))
9645 retval = gen_rtx_REG (mode, gpr_reg_base);
9647 retval = gen_rtx_REG (mode, fpr_reg_base);
9652 /* Arguments larger than one word are double word aligned. */
9655 pa_function_arg_boundary (enum machine_mode mode, const_tree type)
9657 bool singleword = (type
9658 ? (integer_zerop (TYPE_SIZE (type))
9659 || !TREE_CONSTANT (TYPE_SIZE (type))
9660 || int_size_in_bytes (type) <= UNITS_PER_WORD)
9661 : GET_MODE_SIZE (mode) <= UNITS_PER_WORD);
9663 return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY;
9666 /* If this arg would be passed totally in registers or totally on the stack,
9667 then this routine should return zero. */
9670 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9671 tree type, bool named ATTRIBUTE_UNUSED)
9673 unsigned int max_arg_words = 8;
9674 unsigned int offset = 0;
9679 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9682 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9683 /* Arg fits fully into registers. */
9685 else if (cum->words + offset >= max_arg_words)
9686 /* Arg fully on the stack. */
9690 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9694 /* A get_unnamed_section callback for switching to the text section.
9696 This function is only used with SOM. Because we don't support
9697 named subspaces, we can only create a new subspace or switch back
9698 to the default text subspace. */
9701 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9703 gcc_assert (TARGET_SOM);
9706 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9708 /* We only want to emit a .nsubspa directive once at the
9709 start of the function. */
9710 cfun->machine->in_nsubspa = 1;
9712 /* Create a new subspace for the text. This provides
9713 better stub placement and one-only functions. */
9715 && DECL_ONE_ONLY (cfun->decl)
9716 && !DECL_WEAK (cfun->decl))
9718 output_section_asm_op ("\t.SPACE $TEXT$\n"
9719 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9720 "ACCESS=44,SORT=24,COMDAT");
9726 /* There isn't a current function or the body of the current
9727 function has been completed. So, we are changing to the
9728 text section to output debugging information. Thus, we
9729 need to forget that we are in the text section so that
9730 varasm.c will call us when text_section is selected again. */
9731 gcc_assert (!cfun || !cfun->machine
9732 || cfun->machine->in_nsubspa == 2);
9735 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9738 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9741 /* A get_unnamed_section callback for switching to comdat data
9742 sections. This function is only used with SOM. */
9745 som_output_comdat_data_section_asm_op (const void *data)
9748 output_section_asm_op (data);
9751 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9754 pa_som_asm_init_sections (void)
9757 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9759 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9760 is not being generated. */
9761 som_readonly_data_section
9762 = get_unnamed_section (0, output_section_asm_op,
9763 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9765 /* When secondary definitions are not supported, SOM makes readonly
9766 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9768 som_one_only_readonly_data_section
9769 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9771 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9772 "ACCESS=0x2c,SORT=16,COMDAT");
9775 /* When secondary definitions are not supported, SOM makes data one-only
9776 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9777 som_one_only_data_section
9778 = get_unnamed_section (SECTION_WRITE,
9779 som_output_comdat_data_section_asm_op,
9780 "\t.SPACE $PRIVATE$\n"
9781 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9782 "ACCESS=31,SORT=24,COMDAT");
9784 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9785 which reference data within the $TEXT$ space (for example constant
9786 strings in the $LIT$ subspace).
9788 The assemblers (GAS and HP as) both have problems with handling
9789 the difference of two symbols which is the other correct way to
9790 reference constant data during PIC code generation.
9792 So, there's no way to reference constant data which is in the
9793 $TEXT$ space during PIC generation. Instead place all constant
9794 data into the $PRIVATE$ subspace (this reduces sharing, but it
9795 works correctly). */
9796 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9798 /* We must not have a reference to an external symbol defined in a
9799 shared library in a readonly section, else the SOM linker will
9802 So, we force exception information into the data section. */
9803 exception_section = data_section;
9806 /* On hpux10, the linker will give an error if we have a reference
9807 in the read-only data section to a symbol defined in a shared
9808 library. Therefore, expressions that might require a reloc can
9809 not be placed in the read-only data section. */
9812 pa_select_section (tree exp, int reloc,
9813 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9815 if (TREE_CODE (exp) == VAR_DECL
9816 && TREE_READONLY (exp)
9817 && !TREE_THIS_VOLATILE (exp)
9818 && DECL_INITIAL (exp)
9819 && (DECL_INITIAL (exp) == error_mark_node
9820 || TREE_CONSTANT (DECL_INITIAL (exp)))
9824 && DECL_ONE_ONLY (exp)
9825 && !DECL_WEAK (exp))
9826 return som_one_only_readonly_data_section;
9828 return readonly_data_section;
9830 else if (CONSTANT_CLASS_P (exp) && !reloc)
9831 return readonly_data_section;
9833 && TREE_CODE (exp) == VAR_DECL
9834 && DECL_ONE_ONLY (exp)
9835 && !DECL_WEAK (exp))
9836 return som_one_only_data_section;
9838 return data_section;
9842 pa_globalize_label (FILE *stream, const char *name)
9844 /* We only handle DATA objects here, functions are globalized in
9845 ASM_DECLARE_FUNCTION_NAME. */
9846 if (! FUNCTION_NAME_P (name))
9848 fputs ("\t.EXPORT ", stream);
9849 assemble_name (stream, name);
9850 fputs (",DATA\n", stream);
9854 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9857 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9858 int incoming ATTRIBUTE_UNUSED)
9860 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9863 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9866 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9868 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9869 PA64 ABI says that objects larger than 128 bits are returned in memory.
9870 Note, int_size_in_bytes can return -1 if the size of the object is
9871 variable or larger than the maximum value that can be expressed as
9872 a HOST_WIDE_INT. It can also return zero for an empty type. The
9873 simplest way to handle variable and empty types is to pass them in
9874 memory. This avoids problems in defining the boundaries of argument
9875 slots, allocating registers, etc. */
9876 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9877 || int_size_in_bytes (type) <= 0);
9880 /* Structure to hold declaration and name of external symbols that are
9881 emitted by GCC. We generate a vector of these symbols and output them
9882 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9883 This avoids putting out names that are never really used. */
9885 typedef struct GTY(()) extern_symbol
9891 /* Define gc'd vector type for extern_symbol. */
9892 DEF_VEC_O(extern_symbol);
9893 DEF_VEC_ALLOC_O(extern_symbol,gc);
9895 /* Vector of extern_symbol pointers. */
9896 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9898 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9899 /* Mark DECL (name NAME) as an external reference (assembler output
9900 file FILE). This saves the names to output at the end of the file
9901 if actually referenced. */
9904 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9906 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9908 gcc_assert (file == asm_out_file);
9913 /* Output text required at the end of an assembler file.
9914 This includes deferred plabels and .import directives for
9915 all external symbols that were actually referenced. */
9918 pa_hpux_file_end (void)
9923 if (!NO_DEFERRED_PROFILE_COUNTERS)
9924 output_deferred_profile_counters ();
9926 output_deferred_plabels ();
9928 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9930 tree decl = p->decl;
9932 if (!TREE_ASM_WRITTEN (decl)
9933 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9934 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9937 VEC_free (extern_symbol, gc, extern_symbols);
9941 /* Return true if a change from mode FROM to mode TO for a register
9942 in register class RCLASS is invalid. */
9945 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9946 enum reg_class rclass)
9951 /* Reject changes to/from complex and vector modes. */
9952 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9953 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9956 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9959 /* There is no way to load QImode or HImode values directly from
9960 memory. SImode loads to the FP registers are not zero extended.
9961 On the 64-bit target, this conflicts with the definition of
9962 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9963 with different sizes in the floating-point registers. */
9964 if (MAYBE_FP_REG_CLASS_P (rclass))
9967 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9968 in specific sets of registers. Thus, we cannot allow changing
9969 to a larger mode when it's larger than a word. */
9970 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9971 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9977 /* Returns TRUE if it is a good idea to tie two pseudo registers
9978 when one has mode MODE1 and one has mode MODE2.
9979 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9980 for any hard reg, then this must be FALSE for correct output.
9982 We should return FALSE for QImode and HImode because these modes
9983 are not ok in the floating-point registers. However, this prevents
9984 tieing these modes to SImode and DImode in the general registers.
9985 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9986 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9987 in the floating-point registers. */
9990 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9992 /* Don't tie modes in different classes. */
9993 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))
10000 /* Length in units of the trampoline instruction code. */
10002 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
10005 /* Output assembler code for a block containing the constant parts
10006 of a trampoline, leaving space for the variable parts.\
10008 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
10009 and then branches to the specified routine.
10011 This code template is copied from text segment to stack location
10012 and then patched with pa_trampoline_init to contain valid values,
10013 and then entered as a subroutine.
10015 It is best to keep this as small as possible to avoid having to
10016 flush multiple lines in the cache. */
10019 pa_asm_trampoline_template (FILE *f)
10023 fputs ("\tldw 36(%r22),%r21\n", f);
10024 fputs ("\tbb,>=,n %r21,30,.+16\n", f);
10025 if (ASSEMBLER_DIALECT == 0)
10026 fputs ("\tdepi 0,31,2,%r21\n", f);
10028 fputs ("\tdepwi 0,31,2,%r21\n", f);
10029 fputs ("\tldw 4(%r21),%r19\n", f);
10030 fputs ("\tldw 0(%r21),%r21\n", f);
10033 fputs ("\tbve (%r21)\n", f);
10034 fputs ("\tldw 40(%r22),%r29\n", f);
10035 fputs ("\t.word 0\n", f);
10036 fputs ("\t.word 0\n", f);
10040 fputs ("\tldsid (%r21),%r1\n", f);
10041 fputs ("\tmtsp %r1,%sr0\n", f);
10042 fputs ("\tbe 0(%sr0,%r21)\n", f);
10043 fputs ("\tldw 40(%r22),%r29\n", f);
10045 fputs ("\t.word 0\n", f);
10046 fputs ("\t.word 0\n", f);
10047 fputs ("\t.word 0\n", f);
10048 fputs ("\t.word 0\n", f);
10052 fputs ("\t.dword 0\n", f);
10053 fputs ("\t.dword 0\n", f);
10054 fputs ("\t.dword 0\n", f);
10055 fputs ("\t.dword 0\n", f);
10056 fputs ("\tmfia %r31\n", f);
10057 fputs ("\tldd 24(%r31),%r1\n", f);
10058 fputs ("\tldd 24(%r1),%r27\n", f);
10059 fputs ("\tldd 16(%r1),%r1\n", f);
10060 fputs ("\tbve (%r1)\n", f);
10061 fputs ("\tldd 32(%r31),%r31\n", f);
10062 fputs ("\t.dword 0 ; fptr\n", f);
10063 fputs ("\t.dword 0 ; static link\n", f);
10067 /* Emit RTL insns to initialize the variable parts of a trampoline.
10068 FNADDR is an RTX for the address of the function's pure code.
10069 CXT is an RTX for the static chain value for the function.
10071 Move the function address to the trampoline template at offset 36.
10072 Move the static chain value to trampoline template at offset 40.
10073 Move the trampoline address to trampoline template at offset 44.
10074 Move r19 to trampoline template at offset 48. The latter two
10075 words create a plabel for the indirect call to the trampoline.
10077 A similar sequence is used for the 64-bit port but the plabel is
10078 at the beginning of the trampoline.
10080 Finally, the cache entries for the trampoline code are flushed.
10081 This is necessary to ensure that the trampoline instruction sequence
10082 is written to memory prior to any attempts at prefetching the code
10086 pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
10088 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10089 rtx start_addr = gen_reg_rtx (Pmode);
10090 rtx end_addr = gen_reg_rtx (Pmode);
10091 rtx line_length = gen_reg_rtx (Pmode);
10094 emit_block_move (m_tramp, assemble_trampoline_template (),
10095 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
10096 r_tramp = force_reg (Pmode, XEXP (m_tramp, 0));
10100 tmp = adjust_address (m_tramp, Pmode, 36);
10101 emit_move_insn (tmp, fnaddr);
10102 tmp = adjust_address (m_tramp, Pmode, 40);
10103 emit_move_insn (tmp, chain_value);
10105 /* Create a fat pointer for the trampoline. */
10106 tmp = adjust_address (m_tramp, Pmode, 44);
10107 emit_move_insn (tmp, r_tramp);
10108 tmp = adjust_address (m_tramp, Pmode, 48);
10109 emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
10111 /* fdc and fic only use registers for the address to flush,
10112 they do not accept integer displacements. We align the
10113 start and end addresses to the beginning of their respective
10114 cache lines to minimize the number of lines flushed. */
10115 emit_insn (gen_andsi3 (start_addr, r_tramp,
10116 GEN_INT (-MIN_CACHELINE_SIZE)));
10117 tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1));
10118 emit_insn (gen_andsi3 (end_addr, tmp,
10119 GEN_INT (-MIN_CACHELINE_SIZE)));
10120 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10121 emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
10122 emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
10123 gen_reg_rtx (Pmode),
10124 gen_reg_rtx (Pmode)));
10128 tmp = adjust_address (m_tramp, Pmode, 56);
10129 emit_move_insn (tmp, fnaddr);
10130 tmp = adjust_address (m_tramp, Pmode, 64);
10131 emit_move_insn (tmp, chain_value);
10133 /* Create a fat pointer for the trampoline. */
10134 tmp = adjust_address (m_tramp, Pmode, 16);
10135 emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32)));
10136 tmp = adjust_address (m_tramp, Pmode, 24);
10137 emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
10139 /* fdc and fic only use registers for the address to flush,
10140 they do not accept integer displacements. We align the
10141 start and end addresses to the beginning of their respective
10142 cache lines to minimize the number of lines flushed. */
10143 tmp = force_reg (Pmode, plus_constant (r_tramp, 32));
10144 emit_insn (gen_anddi3 (start_addr, tmp,
10145 GEN_INT (-MIN_CACHELINE_SIZE)));
10146 tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));
10147 emit_insn (gen_anddi3 (end_addr, tmp,
10148 GEN_INT (-MIN_CACHELINE_SIZE)));
10149 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10150 emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
10151 emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
10152 gen_reg_rtx (Pmode),
10153 gen_reg_rtx (Pmode)));
10157 /* Perform any machine-specific adjustment in the address of the trampoline.
10158 ADDR contains the address that was passed to pa_trampoline_init.
10159 Adjust the trampoline address to point to the plabel at offset 44. */
10162 pa_trampoline_adjust_address (rtx addr)
10165 addr = memory_address (Pmode, plus_constant (addr, 46));
10170 pa_delegitimize_address (rtx orig_x)
10172 rtx x = delegitimize_mem_from_attrs (orig_x);
10174 if (GET_CODE (x) == LO_SUM
10175 && GET_CODE (XEXP (x, 1)) == UNSPEC
10176 && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R)
10177 return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0));
10182 pa_internal_arg_pointer (void)
10184 /* The argument pointer and the hard frame pointer are the same in
10185 the 32-bit runtime, so we don't need a copy. */
10187 return copy_to_reg (virtual_incoming_args_rtx);
10189 return virtual_incoming_args_rtx;
10192 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10193 Frame pointer elimination is automatically handled. */
10196 pa_can_eliminate (const int from, const int to)
10198 /* The argument cannot be eliminated in the 64-bit runtime. */
10199 if (TARGET_64BIT && from == ARG_POINTER_REGNUM)
10202 return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM
10203 ? ! frame_pointer_needed
10207 /* Define the offset between two registers, FROM to be eliminated and its
10208 replacement TO, at the start of a routine. */
10210 pa_initial_elimination_offset (int from, int to)
10212 HOST_WIDE_INT offset;
10214 if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
10215 && to == STACK_POINTER_REGNUM)
10216 offset = -compute_frame_size (get_frame_size (), 0);
10217 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10220 gcc_unreachable ();
10226 pa_conditional_register_usage (void)
10230 if (!TARGET_64BIT && !TARGET_PA_11)
10232 for (i = 56; i <= FP_REG_LAST; i++)
10233 fixed_regs[i] = call_used_regs[i] = 1;
10234 for (i = 33; i < 56; i += 2)
10235 fixed_regs[i] = call_used_regs[i] = 1;
10237 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10239 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
10240 fixed_regs[i] = call_used_regs[i] = 1;
10243 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;
10246 /* Target hook for c_mode_for_suffix. */
10248 static enum machine_mode
10249 pa_c_mode_for_suffix (char suffix)
10251 if (HPUX_LONG_DOUBLE_LIBRARY)
10260 /* Target hook for function_section. */
10263 pa_function_section (tree decl, enum node_frequency freq,
10264 bool startup, bool exit)
10266 /* Put functions in text section if target doesn't have named sections. */
10267 if (!targetm.have_named_sections)
10268 return text_section;
10270 /* Force nested functions into the same section as the containing
10273 && DECL_SECTION_NAME (decl) == NULL_TREE
10274 && DECL_CONTEXT (decl) != NULL_TREE
10275 && TREE_CODE (DECL_CONTEXT (decl)) == FUNCTION_DECL
10276 && DECL_SECTION_NAME (DECL_CONTEXT (decl)) == NULL_TREE)
10277 return function_section (DECL_CONTEXT (decl));
10279 /* Otherwise, use the default function section. */
10280 return default_function_section (decl, freq, startup, exit);
10283 /* Implement TARGET_LEGITIMATE_CONSTANT_P.
10285 In 64-bit mode, we reject CONST_DOUBLES. We also reject CONST_INTS
10286 that need more than three instructions to load prior to reload. This
10287 limit is somewhat arbitrary. It takes three instructions to load a
10288 CONST_INT from memory but two are memory accesses. It may be better
10289 to increase the allowed range for CONST_INTS. We may also be able
10290 to handle CONST_DOUBLES. */
10293 pa_legitimate_constant_p (enum machine_mode mode, rtx x)
10295 if (GET_MODE_CLASS (mode) == MODE_FLOAT && x != CONST0_RTX (mode))
10298 if (!NEW_HP_ASSEMBLER && !TARGET_GAS && GET_CODE (x) == LABEL_REF)
10301 if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)
10305 && HOST_BITS_PER_WIDE_INT > 32
10306 && GET_CODE (x) == CONST_INT
10307 && !reload_in_progress
10308 && !reload_completed
10309 && !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x))
10310 && !cint_ok_for_move (INTVAL (x)))
10313 if (function_label_operand (x, mode))