1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
42 #include "integrate.h"
51 #include "target-def.h"
53 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
55 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
56 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
59 hppa_use_dfa_pipeline_interface ()
64 /* Return nonzero if there is a bypass for the output of
65 OUT_INSN and the fp store IN_INSN. */
67 hppa_fpstore_bypass_p (out_insn, in_insn)
68 rtx out_insn, in_insn;
70 enum machine_mode store_mode;
71 enum machine_mode other_mode;
74 if (recog_memoized (in_insn) < 0
75 || get_attr_type (in_insn) != TYPE_FPSTORE
76 || recog_memoized (out_insn) < 0)
79 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
81 set = single_set (out_insn);
85 other_mode = GET_MODE (SET_SRC (set));
87 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
91 #ifndef DO_FRAME_NOTES
92 #ifdef INCOMING_RETURN_ADDR_RTX
93 #define DO_FRAME_NOTES 1
95 #define DO_FRAME_NOTES 0
99 static int hppa_address_cost PARAMS ((rtx));
100 static bool hppa_rtx_costs PARAMS ((rtx, int, int, int *));
101 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
102 static void pa_reorg PARAMS ((void));
103 static void pa_combine_instructions PARAMS ((void));
104 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
105 static int forward_branch_p PARAMS ((rtx));
106 static int shadd_constant_p PARAMS ((int));
107 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
108 static int compute_movstrsi_length PARAMS ((rtx));
109 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
110 static void remove_useless_addtr_insns PARAMS ((int));
111 static void store_reg PARAMS ((int, int, int));
112 static void store_reg_modify PARAMS ((int, int, int));
113 static void load_reg PARAMS ((int, int, int));
114 static void set_reg_plus_d PARAMS ((int, int, int, int));
115 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
116 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
117 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
118 static int pa_adjust_priority PARAMS ((rtx, int));
119 static int pa_issue_rate PARAMS ((void));
120 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
122 static void pa_encode_section_info PARAMS ((tree, rtx, int));
123 static const char *pa_strip_name_encoding PARAMS ((const char *));
124 static bool pa_function_ok_for_sibcall PARAMS ((tree, tree));
125 static void pa_globalize_label PARAMS ((FILE *, const char *))
127 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree));
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor PARAMS ((rtx, int));
131 static void pa_asm_out_destructor PARAMS ((rtx, int));
133 static void pa_init_builtins PARAMS ((void));
134 static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
135 static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
136 static struct deferred_plabel *get_plabel PARAMS ((const char *))
138 static inline void pa_file_start_level PARAMS ((void)) ATTRIBUTE_UNUSED;
139 static inline void pa_file_start_space PARAMS ((int)) ATTRIBUTE_UNUSED;
140 static inline void pa_file_start_file PARAMS ((int)) ATTRIBUTE_UNUSED;
141 static inline void pa_file_start_mcount PARAMS ((const char*)) ATTRIBUTE_UNUSED;
142 static void pa_elf_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
143 static void pa_som_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
144 static void pa_linux_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
145 static void pa_hpux64_gas_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
146 static void pa_hpux64_hpas_file_start PARAMS ((void)) ATTRIBUTE_UNUSED;
147 static void output_deferred_plabels PARAMS ((void));
149 /* Save the operands last given to a compare for use when we
150 generate a scc or bcc insn. */
151 rtx hppa_compare_op0, hppa_compare_op1;
152 enum cmp_type hppa_branch_type;
154 /* Which cpu we are scheduling for. */
155 enum processor_type pa_cpu;
157 /* String to hold which cpu we are scheduling for. */
158 const char *pa_cpu_string;
160 /* Which architecture we are generating code for. */
161 enum architecture_type pa_arch;
163 /* String to hold which architecture we are generating code for. */
164 const char *pa_arch_string;
166 /* Counts for the number of callee-saved general and floating point
167 registers which were saved by the current function's prologue. */
168 static int gr_saved, fr_saved;
170 static rtx find_addr_reg PARAMS ((rtx));
172 /* Keep track of the number of bytes we have output in the CODE subspaces
173 during this compilation so we'll know when to emit inline long-calls. */
174 unsigned long total_code_bytes;
176 /* Variables to handle plabels that we discover are necessary at assembly
177 output time. They are output after the current function. */
178 struct deferred_plabel GTY(())
183 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
185 static size_t n_deferred_plabels = 0;
188 /* Initialize the GCC target structure. */
190 #undef TARGET_ASM_ALIGNED_HI_OP
191 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
192 #undef TARGET_ASM_ALIGNED_SI_OP
193 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
194 #undef TARGET_ASM_ALIGNED_DI_OP
195 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
196 #undef TARGET_ASM_UNALIGNED_HI_OP
197 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
198 #undef TARGET_ASM_UNALIGNED_SI_OP
199 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
200 #undef TARGET_ASM_UNALIGNED_DI_OP
201 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
202 #undef TARGET_ASM_INTEGER
203 #define TARGET_ASM_INTEGER pa_assemble_integer
205 #undef TARGET_ASM_FUNCTION_PROLOGUE
206 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
207 #undef TARGET_ASM_FUNCTION_EPILOGUE
208 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
210 #undef TARGET_SCHED_ADJUST_COST
211 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
212 #undef TARGET_SCHED_ADJUST_PRIORITY
213 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
214 #undef TARGET_SCHED_ISSUE_RATE
215 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
217 #undef TARGET_ENCODE_SECTION_INFO
218 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
219 #undef TARGET_STRIP_NAME_ENCODING
220 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
222 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
223 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
225 #undef TARGET_ASM_OUTPUT_MI_THUNK
226 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
227 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
228 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
230 #undef TARGET_ASM_FILE_END
231 #define TARGET_ASM_FILE_END output_deferred_plabels
233 #if !defined(USE_COLLECT2)
234 #undef TARGET_ASM_CONSTRUCTOR
235 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
236 #undef TARGET_ASM_DESTRUCTOR
237 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
240 #undef TARGET_INIT_BUILTINS
241 #define TARGET_INIT_BUILTINS pa_init_builtins
243 #undef TARGET_RTX_COSTS
244 #define TARGET_RTX_COSTS hppa_rtx_costs
245 #undef TARGET_ADDRESS_COST
246 #define TARGET_ADDRESS_COST hppa_address_cost
248 #undef TARGET_MACHINE_DEPENDENT_REORG
249 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
251 struct gcc_target targetm = TARGET_INITIALIZER;
256 if (pa_cpu_string == NULL)
257 pa_cpu_string = TARGET_SCHED_DEFAULT;
259 if (! strcmp (pa_cpu_string, "8000"))
261 pa_cpu_string = "8000";
262 pa_cpu = PROCESSOR_8000;
264 else if (! strcmp (pa_cpu_string, "7100"))
266 pa_cpu_string = "7100";
267 pa_cpu = PROCESSOR_7100;
269 else if (! strcmp (pa_cpu_string, "700"))
271 pa_cpu_string = "700";
272 pa_cpu = PROCESSOR_700;
274 else if (! strcmp (pa_cpu_string, "7100LC"))
276 pa_cpu_string = "7100LC";
277 pa_cpu = PROCESSOR_7100LC;
279 else if (! strcmp (pa_cpu_string, "7200"))
281 pa_cpu_string = "7200";
282 pa_cpu = PROCESSOR_7200;
284 else if (! strcmp (pa_cpu_string, "7300"))
286 pa_cpu_string = "7300";
287 pa_cpu = PROCESSOR_7300;
291 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
294 /* Set the instruction set architecture. */
295 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
297 pa_arch_string = "1.0";
298 pa_arch = ARCHITECTURE_10;
299 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
301 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
303 pa_arch_string = "1.1";
304 pa_arch = ARCHITECTURE_11;
305 target_flags &= ~MASK_PA_20;
306 target_flags |= MASK_PA_11;
308 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
310 pa_arch_string = "2.0";
311 pa_arch = ARCHITECTURE_20;
312 target_flags |= MASK_PA_11 | MASK_PA_20;
314 else if (pa_arch_string)
316 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
319 /* Unconditional branches in the delay slot are not compatible with dwarf2
320 call frame information. There is no benefit in using this optimization
321 on PA8000 and later processors. */
322 if (pa_cpu >= PROCESSOR_8000
323 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
324 || flag_unwind_tables)
325 target_flags &= ~MASK_JUMP_IN_DELAY;
327 if (flag_pic && TARGET_PORTABLE_RUNTIME)
329 warning ("PIC code generation is not supported in the portable runtime model\n");
332 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
334 warning ("PIC code generation is not compatible with fast indirect calls\n");
337 if (! TARGET_GAS && write_symbols != NO_DEBUG)
339 warning ("-g is only supported when using GAS on this processor,");
340 warning ("-g option disabled");
341 write_symbols = NO_DEBUG;
344 /* We only support the "big PIC" model now. And we always generate PIC
345 code when in 64bit mode. */
346 if (flag_pic == 1 || TARGET_64BIT)
349 /* We can't guarantee that .dword is available for 32-bit targets. */
350 if (UNITS_PER_WORD == 4)
351 targetm.asm_out.aligned_op.di = NULL;
353 /* The unaligned ops are only available when using GAS. */
356 targetm.asm_out.unaligned_op.hi = NULL;
357 targetm.asm_out.unaligned_op.si = NULL;
358 targetm.asm_out.unaligned_op.di = NULL;
365 #ifdef DONT_HAVE_FPUTC_UNLOCKED
366 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
367 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
371 /* Return nonzero only if OP is a register of mode MODE,
374 reg_or_0_operand (op, mode)
376 enum machine_mode mode;
378 return (op == CONST0_RTX (mode) || register_operand (op, mode));
381 /* Return nonzero if OP is suitable for use in a call to a named
384 For 2.5 try to eliminate either call_operand_address or
385 function_label_operand, they perform very similar functions. */
387 call_operand_address (op, mode)
389 enum machine_mode mode ATTRIBUTE_UNUSED;
391 return (GET_MODE (op) == word_mode
392 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
395 /* Return 1 if X contains a symbolic expression. We know these
396 expressions will have one of a few well defined forms, so
397 we need only check those forms. */
399 symbolic_expression_p (x)
403 /* Strip off any HIGH. */
404 if (GET_CODE (x) == HIGH)
407 return (symbolic_operand (x, VOIDmode));
411 symbolic_operand (op, mode)
413 enum machine_mode mode ATTRIBUTE_UNUSED;
415 switch (GET_CODE (op))
422 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
423 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
424 && GET_CODE (XEXP (op, 1)) == CONST_INT);
430 /* Return truth value of statement that OP is a symbolic memory
431 operand of mode MODE. */
434 symbolic_memory_operand (op, mode)
436 enum machine_mode mode ATTRIBUTE_UNUSED;
438 if (GET_CODE (op) == SUBREG)
439 op = SUBREG_REG (op);
440 if (GET_CODE (op) != MEM)
443 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
444 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
447 /* Return 1 if the operand is either a register or a memory operand that is
451 reg_or_nonsymb_mem_operand (op, mode)
453 enum machine_mode mode;
455 if (register_operand (op, mode))
458 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
464 /* Return 1 if the operand is either a register, zero, or a memory operand
465 that is not symbolic. */
468 reg_or_0_or_nonsymb_mem_operand (op, mode)
470 enum machine_mode mode;
472 if (register_operand (op, mode))
475 if (op == CONST0_RTX (mode))
478 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
484 /* Return 1 if the operand is a register operand or a non-symbolic memory
485 operand after reload. This predicate is used for branch patterns that
486 internally handle register reloading. We need to accept non-symbolic
487 memory operands after reload to ensure that the pattern is still valid
488 if reload didn't find a hard register for the operand. */
491 reg_before_reload_operand (op, mode)
493 enum machine_mode mode;
495 /* Don't accept a SUBREG since it will need a reload. */
496 if (GET_CODE (op) == SUBREG)
499 if (register_operand (op, mode))
503 && memory_operand (op, mode)
504 && ! symbolic_memory_operand (op, mode))
510 /* Accept any constant that can be moved in one instruction into a
513 cint_ok_for_move (intval)
514 HOST_WIDE_INT intval;
516 /* OK if ldo, ldil, or zdepi, can be used. */
517 return (CONST_OK_FOR_LETTER_P (intval, 'J')
518 || CONST_OK_FOR_LETTER_P (intval, 'N')
519 || CONST_OK_FOR_LETTER_P (intval, 'K'));
522 /* Accept anything that can be moved in one instruction into a general
525 move_operand (op, mode)
527 enum machine_mode mode;
529 if (register_operand (op, mode))
532 if (GET_CODE (op) == CONSTANT_P_RTX)
535 if (GET_CODE (op) == CONST_INT)
536 return cint_ok_for_move (INTVAL (op));
538 if (GET_CODE (op) == SUBREG)
539 op = SUBREG_REG (op);
540 if (GET_CODE (op) != MEM)
545 /* We consider a LO_SUM DLT reference a move_operand now since it has
546 been merged into the normal movsi/movdi patterns. */
547 if (GET_CODE (op) == LO_SUM
548 && GET_CODE (XEXP (op, 0)) == REG
549 && REG_OK_FOR_BASE_P (XEXP (op, 0))
550 && GET_CODE (XEXP (op, 1)) == UNSPEC
551 && GET_MODE (op) == Pmode)
554 /* Since move_operand is only used for source operands, we can always
555 allow scaled indexing! */
556 if (! TARGET_DISABLE_INDEXING
557 && GET_CODE (op) == PLUS
558 && ((GET_CODE (XEXP (op, 0)) == MULT
559 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
560 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
561 && INTVAL (XEXP (XEXP (op, 0), 1))
562 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
563 && GET_CODE (XEXP (op, 1)) == REG)
564 || (GET_CODE (XEXP (op, 1)) == MULT
565 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
566 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
567 && INTVAL (XEXP (XEXP (op, 1), 1))
568 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
569 && GET_CODE (XEXP (op, 0)) == REG)))
572 return memory_address_p (mode, op);
575 /* Accept REG and any CONST_INT that can be moved in one instruction into a
578 reg_or_cint_move_operand (op, mode)
580 enum machine_mode mode;
582 if (register_operand (op, mode))
585 if (GET_CODE (op) == CONST_INT)
586 return cint_ok_for_move (INTVAL (op));
592 pic_label_operand (op, mode)
594 enum machine_mode mode ATTRIBUTE_UNUSED;
599 switch (GET_CODE (op))
605 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
606 && GET_CODE (XEXP (op, 1)) == CONST_INT);
613 fp_reg_operand (op, mode)
615 enum machine_mode mode ATTRIBUTE_UNUSED;
617 return reg_renumber && FP_REG_P (op);
622 /* Return truth value of whether OP can be used as an operand in a
623 three operand arithmetic insn that accepts registers of mode MODE
624 or 14-bit signed integers. */
626 arith_operand (op, mode)
628 enum machine_mode mode;
630 return (register_operand (op, mode)
631 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
634 /* Return truth value of whether OP can be used as an operand in a
635 three operand arithmetic insn that accepts registers of mode MODE
636 or 11-bit signed integers. */
638 arith11_operand (op, mode)
640 enum machine_mode mode;
642 return (register_operand (op, mode)
643 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
646 /* Return truth value of whether OP can be used as an operand in a
649 adddi3_operand (op, mode)
651 enum machine_mode mode;
653 return (register_operand (op, mode)
654 || (GET_CODE (op) == CONST_INT
655 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
658 /* A constant integer suitable for use in a PRE_MODIFY memory
661 pre_cint_operand (op, mode)
663 enum machine_mode mode ATTRIBUTE_UNUSED;
665 return (GET_CODE (op) == CONST_INT
666 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
669 /* A constant integer suitable for use in a POST_MODIFY memory
672 post_cint_operand (op, mode)
674 enum machine_mode mode ATTRIBUTE_UNUSED;
676 return (GET_CODE (op) == CONST_INT
677 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
681 arith_double_operand (op, mode)
683 enum machine_mode mode;
685 return (register_operand (op, mode)
686 || (GET_CODE (op) == CONST_DOUBLE
687 && GET_MODE (op) == mode
688 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
689 && ((CONST_DOUBLE_HIGH (op) >= 0)
690 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
693 /* Return truth value of whether OP is an integer which fits the
694 range constraining immediate operands in three-address insns, or
695 is an integer register. */
698 ireg_or_int5_operand (op, mode)
700 enum machine_mode mode ATTRIBUTE_UNUSED;
702 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
703 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
706 /* Return nonzero if OP is an integer register, else return zero. */
708 ireg_operand (op, mode)
710 enum machine_mode mode ATTRIBUTE_UNUSED;
712 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
715 /* Return truth value of whether OP is an integer which fits the
716 range constraining immediate operands in three-address insns. */
719 int5_operand (op, mode)
721 enum machine_mode mode ATTRIBUTE_UNUSED;
723 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
727 uint5_operand (op, mode)
729 enum machine_mode mode ATTRIBUTE_UNUSED;
731 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
735 int11_operand (op, mode)
737 enum machine_mode mode ATTRIBUTE_UNUSED;
739 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
743 uint32_operand (op, mode)
745 enum machine_mode mode ATTRIBUTE_UNUSED;
747 #if HOST_BITS_PER_WIDE_INT > 32
748 /* All allowed constants will fit a CONST_INT. */
749 return (GET_CODE (op) == CONST_INT
750 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
752 return (GET_CODE (op) == CONST_INT
753 || (GET_CODE (op) == CONST_DOUBLE
754 && CONST_DOUBLE_HIGH (op) == 0));
759 arith5_operand (op, mode)
761 enum machine_mode mode;
763 return register_operand (op, mode) || int5_operand (op, mode);
766 /* True iff zdepi can be used to generate this CONST_INT.
767 zdepi first sign extends a 5 bit signed number to a given field
768 length, then places this field anywhere in a zero. */
771 unsigned HOST_WIDE_INT x;
773 unsigned HOST_WIDE_INT lsb_mask, t;
775 /* This might not be obvious, but it's at least fast.
776 This function is critical; we don't have the time loops would take. */
778 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
779 /* Return true iff t is a power of two. */
780 return ((t & (t - 1)) == 0);
783 /* True iff depi or extru can be used to compute (reg & mask).
784 Accept bit pattern like these:
790 unsigned HOST_WIDE_INT mask;
793 mask += mask & -mask;
794 return (mask & (mask - 1)) == 0;
797 /* True iff depi or extru can be used to compute (reg & OP). */
799 and_operand (op, mode)
801 enum machine_mode mode;
803 return (register_operand (op, mode)
804 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
807 /* True iff depi can be used to compute (reg | MASK). */
810 unsigned HOST_WIDE_INT mask;
812 mask += mask & -mask;
813 return (mask & (mask - 1)) == 0;
816 /* True iff depi can be used to compute (reg | OP). */
818 ior_operand (op, mode)
820 enum machine_mode mode ATTRIBUTE_UNUSED;
822 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
826 lhs_lshift_operand (op, mode)
828 enum machine_mode mode;
830 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
833 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
834 Such values can be the left hand side x in (x << r), using the zvdepi
837 lhs_lshift_cint_operand (op, mode)
839 enum machine_mode mode ATTRIBUTE_UNUSED;
841 unsigned HOST_WIDE_INT x;
842 if (GET_CODE (op) != CONST_INT)
844 x = INTVAL (op) >> 4;
845 return (x & (x + 1)) == 0;
849 arith32_operand (op, mode)
851 enum machine_mode mode;
853 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
857 pc_or_label_operand (op, mode)
859 enum machine_mode mode ATTRIBUTE_UNUSED;
861 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
864 /* Legitimize PIC addresses. If the address is already
865 position-independent, we return ORIG. Newly generated
866 position-independent addresses go to REG. If we need more
867 than one register, we lose. */
870 legitimize_pic_address (orig, mode, reg)
872 enum machine_mode mode;
876 /* Labels need special handling. */
877 if (pic_label_operand (orig, mode))
879 /* We do not want to go through the movXX expanders here since that
880 would create recursion.
882 Nor do we really want to call a generator for a named pattern
883 since that requires multiple patterns if we want to support
886 So instead we just emit the raw set, which avoids the movXX
887 expanders completely. */
888 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
889 current_function_uses_pic_offset_table = 1;
892 if (GET_CODE (orig) == SYMBOL_REF)
898 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
899 gen_rtx_HIGH (word_mode, orig)));
901 = gen_rtx_MEM (Pmode,
902 gen_rtx_LO_SUM (Pmode, reg,
903 gen_rtx_UNSPEC (Pmode,
907 current_function_uses_pic_offset_table = 1;
908 RTX_UNCHANGING_P (pic_ref) = 1;
909 emit_move_insn (reg, pic_ref);
912 else if (GET_CODE (orig) == CONST)
916 if (GET_CODE (XEXP (orig, 0)) == PLUS
917 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
923 if (GET_CODE (XEXP (orig, 0)) == PLUS)
925 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
926 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
927 base == reg ? 0 : reg);
930 if (GET_CODE (orig) == CONST_INT)
932 if (INT_14_BITS (orig))
933 return plus_constant (base, INTVAL (orig));
934 orig = force_reg (Pmode, orig);
936 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
937 /* Likewise, should we set special REG_NOTEs here? */
942 /* Try machine-dependent ways of modifying an illegitimate address
943 to be legitimate. If we find one, return the new, valid address.
944 This macro is used in only one place: `memory_address' in explow.c.
946 OLDX is the address as it was before break_out_memory_refs was called.
947 In some cases it is useful to look at this to decide what needs to be done.
949 MODE and WIN are passed so that this macro can use
950 GO_IF_LEGITIMATE_ADDRESS.
952 It is always safe for this macro to do nothing. It exists to recognize
953 opportunities to optimize the output.
955 For the PA, transform:
957 memory(X + <large int>)
961 if (<large int> & mask) >= 16
962 Y = (<large int> & ~mask) + mask + 1 Round up.
964 Y = (<large int> & ~mask) Round down.
966 memory (Z + (<large int> - Y));
968 This is for CSE to find several similar references, and only use one Z.
970 X can either be a SYMBOL_REF or REG, but because combine can not
971 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
972 D will not fit in 14 bits.
974 MODE_FLOAT references allow displacements which fit in 5 bits, so use
977 MODE_INT references allow displacements which fit in 14 bits, so use
980 This relies on the fact that most mode MODE_FLOAT references will use FP
981 registers and most mode MODE_INT references will use integer registers.
982 (In the rare case of an FP register used in an integer MODE, we depend
983 on secondary reloads to clean things up.)
986 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
987 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
988 addressing modes to be used).
990 Put X and Z into registers. Then put the entire expression into
994 hppa_legitimize_address (x, oldx, mode)
995 rtx x, oldx ATTRIBUTE_UNUSED;
996 enum machine_mode mode;
1001 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1003 /* Strip off CONST. */
1004 if (GET_CODE (x) == CONST)
1007 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1008 That should always be safe. */
1009 if (GET_CODE (x) == PLUS
1010 && GET_CODE (XEXP (x, 0)) == REG
1011 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1013 rtx reg = force_reg (Pmode, XEXP (x, 1));
1014 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1017 /* Note we must reject symbols which represent function addresses
1018 since the assembler/linker can't handle arithmetic on plabels. */
1019 if (GET_CODE (x) == PLUS
1020 && GET_CODE (XEXP (x, 1)) == CONST_INT
1021 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1022 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1023 || GET_CODE (XEXP (x, 0)) == REG))
1025 rtx int_part, ptr_reg;
1027 int offset = INTVAL (XEXP (x, 1));
1030 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1031 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1033 /* Choose which way to round the offset. Round up if we
1034 are >= halfway to the next boundary. */
1035 if ((offset & mask) >= ((mask + 1) / 2))
1036 newoffset = (offset & ~ mask) + mask + 1;
1038 newoffset = (offset & ~ mask);
1040 /* If the newoffset will not fit in 14 bits (ldo), then
1041 handling this would take 4 or 5 instructions (2 to load
1042 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1043 add the new offset and the SYMBOL_REF.) Combine can
1044 not handle 4->2 or 5->2 combinations, so do not create
1046 if (! VAL_14_BITS_P (newoffset)
1047 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1049 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1052 gen_rtx_HIGH (Pmode, const_part));
1055 gen_rtx_LO_SUM (Pmode,
1056 tmp_reg, const_part));
1060 if (! VAL_14_BITS_P (newoffset))
1061 int_part = force_reg (Pmode, GEN_INT (newoffset));
1063 int_part = GEN_INT (newoffset);
1065 ptr_reg = force_reg (Pmode,
1066 gen_rtx_PLUS (Pmode,
1067 force_reg (Pmode, XEXP (x, 0)),
1070 return plus_constant (ptr_reg, offset - newoffset);
1073 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1075 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1076 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1077 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1078 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1079 || GET_CODE (XEXP (x, 1)) == SUBREG)
1080 && GET_CODE (XEXP (x, 1)) != CONST)
1082 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1086 if (GET_CODE (reg1) != REG)
1087 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1089 reg2 = XEXP (XEXP (x, 0), 0);
1090 if (GET_CODE (reg2) != REG)
1091 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1093 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1094 gen_rtx_MULT (Pmode,
1100 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1102 Only do so for floating point modes since this is more speculative
1103 and we lose if it's an integer store. */
1104 if (GET_CODE (x) == PLUS
1105 && GET_CODE (XEXP (x, 0)) == PLUS
1106 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1107 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1108 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1109 && (mode == SFmode || mode == DFmode))
1112 /* First, try and figure out what to use as a base register. */
1113 rtx reg1, reg2, base, idx, orig_base;
1115 reg1 = XEXP (XEXP (x, 0), 1);
1120 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1121 then emit_move_sequence will turn on REG_POINTER so we'll know
1122 it's a base register below. */
1123 if (GET_CODE (reg1) != REG)
1124 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1126 if (GET_CODE (reg2) != REG)
1127 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1129 /* Figure out what the base and index are. */
1131 if (GET_CODE (reg1) == REG
1132 && REG_POINTER (reg1))
1135 orig_base = XEXP (XEXP (x, 0), 1);
1136 idx = gen_rtx_PLUS (Pmode,
1137 gen_rtx_MULT (Pmode,
1138 XEXP (XEXP (XEXP (x, 0), 0), 0),
1139 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1142 else if (GET_CODE (reg2) == REG
1143 && REG_POINTER (reg2))
1146 orig_base = XEXP (x, 1);
1153 /* If the index adds a large constant, try to scale the
1154 constant so that it can be loaded with only one insn. */
1155 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1156 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1157 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1158 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1160 /* Divide the CONST_INT by the scale factor, then add it to A. */
1161 int val = INTVAL (XEXP (idx, 1));
1163 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1164 reg1 = XEXP (XEXP (idx, 0), 0);
1165 if (GET_CODE (reg1) != REG)
1166 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1168 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1170 /* We can now generate a simple scaled indexed address. */
1173 (Pmode, gen_rtx_PLUS (Pmode,
1174 gen_rtx_MULT (Pmode, reg1,
1175 XEXP (XEXP (idx, 0), 1)),
1179 /* If B + C is still a valid base register, then add them. */
1180 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1181 && INTVAL (XEXP (idx, 1)) <= 4096
1182 && INTVAL (XEXP (idx, 1)) >= -4096)
1184 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1187 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1189 reg2 = XEXP (XEXP (idx, 0), 0);
1190 if (GET_CODE (reg2) != CONST_INT)
1191 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1193 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1194 gen_rtx_MULT (Pmode,
1200 /* Get the index into a register, then add the base + index and
1201 return a register holding the result. */
1203 /* First get A into a register. */
1204 reg1 = XEXP (XEXP (idx, 0), 0);
1205 if (GET_CODE (reg1) != REG)
1206 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1208 /* And get B into a register. */
1209 reg2 = XEXP (idx, 1);
1210 if (GET_CODE (reg2) != REG)
1211 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1213 reg1 = force_reg (Pmode,
1214 gen_rtx_PLUS (Pmode,
1215 gen_rtx_MULT (Pmode, reg1,
1216 XEXP (XEXP (idx, 0), 1)),
1219 /* Add the result to our base register and return. */
1220 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1224 /* Uh-oh. We might have an address for x[n-100000]. This needs
1225 special handling to avoid creating an indexed memory address
1226 with x-100000 as the base.
1228 If the constant part is small enough, then it's still safe because
1229 there is a guard page at the beginning and end of the data segment.
1231 Scaled references are common enough that we want to try and rearrange the
1232 terms so that we can use indexing for these addresses too. Only
1233 do the optimization for floatint point modes. */
1235 if (GET_CODE (x) == PLUS
1236 && symbolic_expression_p (XEXP (x, 1)))
1238 /* Ugly. We modify things here so that the address offset specified
1239 by the index expression is computed first, then added to x to form
1240 the entire address. */
1242 rtx regx1, regx2, regy1, regy2, y;
1244 /* Strip off any CONST. */
1246 if (GET_CODE (y) == CONST)
1249 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1251 /* See if this looks like
1252 (plus (mult (reg) (shadd_const))
1253 (const (plus (symbol_ref) (const_int))))
1255 Where const_int is small. In that case the const
1256 expression is a valid pointer for indexing.
1258 If const_int is big, but can be divided evenly by shadd_const
1259 and added to (reg). This allows more scaled indexed addresses. */
1260 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1261 && GET_CODE (XEXP (x, 0)) == MULT
1262 && GET_CODE (XEXP (y, 1)) == CONST_INT
1263 && INTVAL (XEXP (y, 1)) >= -4096
1264 && INTVAL (XEXP (y, 1)) <= 4095
1265 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1266 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1268 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1272 if (GET_CODE (reg1) != REG)
1273 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1275 reg2 = XEXP (XEXP (x, 0), 0);
1276 if (GET_CODE (reg2) != REG)
1277 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1279 return force_reg (Pmode,
1280 gen_rtx_PLUS (Pmode,
1281 gen_rtx_MULT (Pmode,
1286 else if ((mode == DFmode || mode == SFmode)
1287 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1288 && GET_CODE (XEXP (x, 0)) == MULT
1289 && GET_CODE (XEXP (y, 1)) == CONST_INT
1290 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1291 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1292 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1295 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1296 / INTVAL (XEXP (XEXP (x, 0), 1))));
1297 regx2 = XEXP (XEXP (x, 0), 0);
1298 if (GET_CODE (regx2) != REG)
1299 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1300 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1304 gen_rtx_PLUS (Pmode,
1305 gen_rtx_MULT (Pmode, regx2,
1306 XEXP (XEXP (x, 0), 1)),
1307 force_reg (Pmode, XEXP (y, 0))));
1309 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1310 && INTVAL (XEXP (y, 1)) >= -4096
1311 && INTVAL (XEXP (y, 1)) <= 4095)
1313 /* This is safe because of the guard page at the
1314 beginning and end of the data space. Just
1315 return the original address. */
1320 /* Doesn't look like one we can optimize. */
1321 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1322 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1323 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1324 regx1 = force_reg (Pmode,
1325 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1327 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1335 /* For the HPPA, REG and REG+CONST is cost 0
1336 and addresses involving symbolic constants are cost 2.
1338 PIC addresses are very expensive.
1340 It is no coincidence that this has the same structure
1341 as GO_IF_LEGITIMATE_ADDRESS. */
1344 hppa_address_cost (X)
1347 switch (GET_CODE (X))
1360 /* Compute a (partial) cost for rtx X. Return true if the complete
1361 cost has been computed, and false if subexpressions should be
1362 scanned. In either case, *TOTAL contains the cost result. */
1365 hppa_rtx_costs (x, code, outer_code, total)
1367 int code, outer_code;
1373 if (INTVAL (x) == 0)
1375 else if (INT_14_BITS (x))
1392 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1393 && outer_code != SET)
1400 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1401 *total = COSTS_N_INSNS (3);
1402 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1403 *total = COSTS_N_INSNS (8);
1405 *total = COSTS_N_INSNS (20);
1409 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1411 *total = COSTS_N_INSNS (14);
1419 *total = COSTS_N_INSNS (60);
1422 case PLUS: /* this includes shNadd insns */
1424 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1425 *total = COSTS_N_INSNS (3);
1427 *total = COSTS_N_INSNS (1);
1433 *total = COSTS_N_INSNS (1);
1441 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1442 new rtx with the correct mode. */
1444 force_mode (mode, orig)
1445 enum machine_mode mode;
1448 if (mode == GET_MODE (orig))
1451 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1454 return gen_rtx_REG (mode, REGNO (orig));
1457 /* Emit insns to move operands[1] into operands[0].
1459 Return 1 if we have written out everything that needs to be done to
1460 do the move. Otherwise, return 0 and the caller will emit the move
1463 Note SCRATCH_REG may not be in the proper mode depending on how it
1464 will be used. This routine is resposible for creating a new copy
1465 of SCRATCH_REG in the proper mode. */
1468 emit_move_sequence (operands, mode, scratch_reg)
1470 enum machine_mode mode;
1473 register rtx operand0 = operands[0];
1474 register rtx operand1 = operands[1];
1478 && reload_in_progress && GET_CODE (operand0) == REG
1479 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1480 operand0 = reg_equiv_mem[REGNO (operand0)];
1481 else if (scratch_reg
1482 && reload_in_progress && GET_CODE (operand0) == SUBREG
1483 && GET_CODE (SUBREG_REG (operand0)) == REG
1484 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1486 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1487 the code which tracks sets/uses for delete_output_reload. */
1488 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1489 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1490 SUBREG_BYTE (operand0));
1491 operand0 = alter_subreg (&temp);
1495 && reload_in_progress && GET_CODE (operand1) == REG
1496 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1497 operand1 = reg_equiv_mem[REGNO (operand1)];
1498 else if (scratch_reg
1499 && reload_in_progress && GET_CODE (operand1) == SUBREG
1500 && GET_CODE (SUBREG_REG (operand1)) == REG
1501 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1503 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1504 the code which tracks sets/uses for delete_output_reload. */
1505 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1506 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1507 SUBREG_BYTE (operand1));
1508 operand1 = alter_subreg (&temp);
1511 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1512 && ((tem = find_replacement (&XEXP (operand0, 0)))
1513 != XEXP (operand0, 0)))
1514 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1515 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1516 && ((tem = find_replacement (&XEXP (operand1, 0)))
1517 != XEXP (operand1, 0)))
1518 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1520 /* Handle secondary reloads for loads/stores of FP registers from
1521 REG+D addresses where D does not fit in 5 bits, including
1522 (subreg (mem (addr))) cases. */
1523 if (fp_reg_operand (operand0, mode)
1524 && ((GET_CODE (operand1) == MEM
1525 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1526 || ((GET_CODE (operand1) == SUBREG
1527 && GET_CODE (XEXP (operand1, 0)) == MEM
1528 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1531 if (GET_CODE (operand1) == SUBREG)
1532 operand1 = XEXP (operand1, 0);
1534 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1535 it in WORD_MODE regardless of what mode it was originally given
1537 scratch_reg = force_mode (word_mode, scratch_reg);
1539 /* D might not fit in 14 bits either; for such cases load D into
1541 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1543 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1544 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1546 XEXP (XEXP (operand1, 0), 0),
1550 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1551 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1552 gen_rtx_MEM (mode, scratch_reg)));
1555 else if (fp_reg_operand (operand1, mode)
1556 && ((GET_CODE (operand0) == MEM
1557 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1558 || ((GET_CODE (operand0) == SUBREG)
1559 && GET_CODE (XEXP (operand0, 0)) == MEM
1560 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1563 if (GET_CODE (operand0) == SUBREG)
1564 operand0 = XEXP (operand0, 0);
1566 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1567 it in WORD_MODE regardless of what mode it was originally given
1569 scratch_reg = force_mode (word_mode, scratch_reg);
1571 /* D might not fit in 14 bits either; for such cases load D into
1573 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1575 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1576 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1579 XEXP (XEXP (operand0, 0),
1584 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1585 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1589 /* Handle secondary reloads for loads of FP registers from constant
1590 expressions by forcing the constant into memory.
1592 use scratch_reg to hold the address of the memory location.
1594 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1595 NO_REGS when presented with a const_int and a register class
1596 containing only FP registers. Doing so unfortunately creates
1597 more problems than it solves. Fix this for 2.5. */
1598 else if (fp_reg_operand (operand0, mode)
1599 && CONSTANT_P (operand1)
1604 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1605 it in WORD_MODE regardless of what mode it was originally given
1607 scratch_reg = force_mode (word_mode, scratch_reg);
1609 /* Force the constant into memory and put the address of the
1610 memory location into scratch_reg. */
1611 xoperands[0] = scratch_reg;
1612 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1613 emit_move_sequence (xoperands, Pmode, 0);
1615 /* Now load the destination register. */
1616 emit_insn (gen_rtx_SET (mode, operand0,
1617 gen_rtx_MEM (mode, scratch_reg)));
1620 /* Handle secondary reloads for SAR. These occur when trying to load
1621 the SAR from memory, FP register, or with a constant. */
1622 else if (GET_CODE (operand0) == REG
1623 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1624 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1625 && (GET_CODE (operand1) == MEM
1626 || GET_CODE (operand1) == CONST_INT
1627 || (GET_CODE (operand1) == REG
1628 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1631 /* D might not fit in 14 bits either; for such cases load D into
1633 if (GET_CODE (operand1) == MEM
1634 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1636 /* We are reloading the address into the scratch register, so we
1637 want to make sure the scratch register is a full register. */
1638 scratch_reg = force_mode (word_mode, scratch_reg);
1640 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1641 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1644 XEXP (XEXP (operand1, 0),
1648 /* Now we are going to load the scratch register from memory,
1649 we want to load it in the same width as the original MEM,
1650 which must be the same as the width of the ultimate destination,
1652 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1654 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1659 /* We want to load the scratch register using the same mode as
1660 the ultimate destination. */
1661 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1663 emit_move_insn (scratch_reg, operand1);
1666 /* And emit the insn to set the ultimate destination. We know that
1667 the scratch register has the same mode as the destination at this
1669 emit_move_insn (operand0, scratch_reg);
1672 /* Handle most common case: storing into a register. */
1673 else if (register_operand (operand0, mode))
1675 if (register_operand (operand1, mode)
1676 || (GET_CODE (operand1) == CONST_INT
1677 && cint_ok_for_move (INTVAL (operand1)))
1678 || (operand1 == CONST0_RTX (mode))
1679 || (GET_CODE (operand1) == HIGH
1680 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1681 /* Only `general_operands' can come here, so MEM is ok. */
1682 || GET_CODE (operand1) == MEM)
1684 /* Run this case quickly. */
1685 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1689 else if (GET_CODE (operand0) == MEM)
1691 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1692 && !(reload_in_progress || reload_completed))
1694 rtx temp = gen_reg_rtx (DFmode);
1696 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1697 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1700 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1702 /* Run this case quickly. */
1703 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1706 if (! (reload_in_progress || reload_completed))
1708 operands[0] = validize_mem (operand0);
1709 operands[1] = operand1 = force_reg (mode, operand1);
1713 /* Simplify the source if we need to.
1714 Note we do have to handle function labels here, even though we do
1715 not consider them legitimate constants. Loop optimizations can
1716 call the emit_move_xxx with one as a source. */
1717 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1718 || function_label_operand (operand1, mode)
1719 || (GET_CODE (operand1) == HIGH
1720 && symbolic_operand (XEXP (operand1, 0), mode)))
1724 if (GET_CODE (operand1) == HIGH)
1727 operand1 = XEXP (operand1, 0);
1729 if (symbolic_operand (operand1, mode))
1731 /* Argh. The assembler and linker can't handle arithmetic
1734 So we force the plabel into memory, load operand0 from
1735 the memory location, then add in the constant part. */
1736 if ((GET_CODE (operand1) == CONST
1737 && GET_CODE (XEXP (operand1, 0)) == PLUS
1738 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1739 || function_label_operand (operand1, mode))
1741 rtx temp, const_part;
1743 /* Figure out what (if any) scratch register to use. */
1744 if (reload_in_progress || reload_completed)
1746 scratch_reg = scratch_reg ? scratch_reg : operand0;
1747 /* SCRATCH_REG will hold an address and maybe the actual
1748 data. We want it in WORD_MODE regardless of what mode it
1749 was originally given to us. */
1750 scratch_reg = force_mode (word_mode, scratch_reg);
1753 scratch_reg = gen_reg_rtx (Pmode);
1755 if (GET_CODE (operand1) == CONST)
1757 /* Save away the constant part of the expression. */
1758 const_part = XEXP (XEXP (operand1, 0), 1);
1759 if (GET_CODE (const_part) != CONST_INT)
1762 /* Force the function label into memory. */
1763 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1767 /* No constant part. */
1768 const_part = NULL_RTX;
1770 /* Force the function label into memory. */
1771 temp = force_const_mem (mode, operand1);
1775 /* Get the address of the memory location. PIC-ify it if
1777 temp = XEXP (temp, 0);
1779 temp = legitimize_pic_address (temp, mode, scratch_reg);
1781 /* Put the address of the memory location into our destination
1784 emit_move_sequence (operands, mode, scratch_reg);
1786 /* Now load from the memory location into our destination
1788 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1789 emit_move_sequence (operands, mode, scratch_reg);
1791 /* And add back in the constant part. */
1792 if (const_part != NULL_RTX)
1793 expand_inc (operand0, const_part);
1802 if (reload_in_progress || reload_completed)
1804 temp = scratch_reg ? scratch_reg : operand0;
1805 /* TEMP will hold an address and maybe the actual
1806 data. We want it in WORD_MODE regardless of what mode it
1807 was originally given to us. */
1808 temp = force_mode (word_mode, temp);
1811 temp = gen_reg_rtx (Pmode);
1813 /* (const (plus (symbol) (const_int))) must be forced to
1814 memory during/after reload if the const_int will not fit
1816 if (GET_CODE (operand1) == CONST
1817 && GET_CODE (XEXP (operand1, 0)) == PLUS
1818 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1819 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1820 && (reload_completed || reload_in_progress)
1823 operands[1] = force_const_mem (mode, operand1);
1824 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1826 emit_move_sequence (operands, mode, temp);
1830 operands[1] = legitimize_pic_address (operand1, mode, temp);
1831 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1834 /* On the HPPA, references to data space are supposed to use dp,
1835 register 27, but showing it in the RTL inhibits various cse
1836 and loop optimizations. */
1841 if (reload_in_progress || reload_completed)
1843 temp = scratch_reg ? scratch_reg : operand0;
1844 /* TEMP will hold an address and maybe the actual
1845 data. We want it in WORD_MODE regardless of what mode it
1846 was originally given to us. */
1847 temp = force_mode (word_mode, temp);
1850 temp = gen_reg_rtx (mode);
1852 /* Loading a SYMBOL_REF into a register makes that register
1853 safe to be used as the base in an indexed address.
1855 Don't mark hard registers though. That loses. */
1856 if (GET_CODE (operand0) == REG
1857 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1858 REG_POINTER (operand0) = 1;
1859 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1860 REG_POINTER (temp) = 1;
1862 set = gen_rtx_SET (mode, operand0, temp);
1864 set = gen_rtx_SET (VOIDmode,
1866 gen_rtx_LO_SUM (mode, temp, operand1));
1868 emit_insn (gen_rtx_SET (VOIDmode,
1870 gen_rtx_HIGH (mode, operand1)));
1876 else if (GET_CODE (operand1) != CONST_INT
1877 || ! cint_ok_for_move (INTVAL (operand1)))
1879 rtx extend = NULL_RTX;
1882 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1883 && HOST_BITS_PER_WIDE_INT > 32
1884 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1886 HOST_WIDE_INT val = INTVAL (operand1);
1889 /* Extract the low order 32 bits of the value and sign extend.
1890 If the new value is the same as the original value, we can
1891 can use the original value as-is. If the new value is
1892 different, we use it and insert the most-significant 32-bits
1893 of the original value into the final result. */
1894 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1895 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1898 #if HOST_BITS_PER_WIDE_INT > 32
1899 extend = GEN_INT (val >> 32);
1901 operand1 = GEN_INT (nval);
1905 if (reload_in_progress || reload_completed)
1908 temp = gen_reg_rtx (mode);
1910 /* We don't directly split DImode constants on 32-bit targets
1911 because PLUS uses an 11-bit immediate and the insn sequence
1912 generated is not as efficient as the one using HIGH/LO_SUM. */
1913 if (GET_CODE (operand1) == CONST_INT
1914 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1916 /* Directly break constant into high and low parts. This
1917 provides better optimization opportunities because various
1918 passes recognize constants split with PLUS but not LO_SUM.
1919 We use a 14-bit signed low part except when the addition
1920 of 0x4000 to the high part might change the sign of the
1922 HOST_WIDE_INT value = INTVAL (operand1);
1923 HOST_WIDE_INT low = value & 0x3fff;
1924 HOST_WIDE_INT high = value & ~ 0x3fff;
1928 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1936 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1937 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1941 emit_insn (gen_rtx_SET (VOIDmode, temp,
1942 gen_rtx_HIGH (mode, operand1)));
1943 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1946 emit_move_insn (operands[0], operands[1]);
1948 if (extend != NULL_RTX)
1949 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1955 /* Now have insn-emit do whatever it normally does. */
1959 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1960 it will need a link/runtime reloc). */
1968 switch (TREE_CODE (exp))
1975 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1976 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1981 case NON_LVALUE_EXPR:
1982 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1988 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1989 if (TREE_VALUE (link) != 0)
1990 reloc |= reloc_needed (TREE_VALUE (link));
2003 /* Does operand (which is a symbolic_operand) live in text space?
2004 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2008 read_only_operand (operand, mode)
2010 enum machine_mode mode ATTRIBUTE_UNUSED;
2012 if (GET_CODE (operand) == CONST)
2013 operand = XEXP (XEXP (operand, 0), 0);
2016 if (GET_CODE (operand) == SYMBOL_REF)
2017 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2021 if (GET_CODE (operand) == SYMBOL_REF)
2022 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2028 /* Return the best assembler insn template
2029 for moving operands[1] into operands[0] as a fullword. */
2031 singlemove_string (operands)
2034 HOST_WIDE_INT intval;
2036 if (GET_CODE (operands[0]) == MEM)
2037 return "stw %r1,%0";
2038 if (GET_CODE (operands[1]) == MEM)
2040 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2045 if (GET_MODE (operands[1]) != SFmode)
2048 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2050 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2051 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2053 operands[1] = GEN_INT (i);
2054 /* Fall through to CONST_INT case. */
2056 if (GET_CODE (operands[1]) == CONST_INT)
2058 intval = INTVAL (operands[1]);
2060 if (VAL_14_BITS_P (intval))
2062 else if ((intval & 0x7ff) == 0)
2063 return "ldil L'%1,%0";
2064 else if (zdepi_cint_p (intval))
2065 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2067 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2069 return "copy %1,%0";
2073 /* Compute position (in OP[1]) and width (in OP[2])
2074 useful for copying IMM to a register using the zdepi
2075 instructions. Store the immediate value to insert in OP[0]. */
2077 compute_zdepwi_operands (imm, op)
2078 unsigned HOST_WIDE_INT imm;
2083 /* Find the least significant set bit in IMM. */
2084 for (lsb = 0; lsb < 32; lsb++)
2091 /* Choose variants based on *sign* of the 5-bit field. */
2092 if ((imm & 0x10) == 0)
2093 len = (lsb <= 28) ? 4 : 32 - lsb;
2096 /* Find the width of the bitstring in IMM. */
2097 for (len = 5; len < 32; len++)
2099 if ((imm & (1 << len)) == 0)
2103 /* Sign extend IMM as a 5-bit value. */
2104 imm = (imm & 0xf) - 0x10;
2112 /* Compute position (in OP[1]) and width (in OP[2])
2113 useful for copying IMM to a register using the depdi,z
2114 instructions. Store the immediate value to insert in OP[0]. */
2116 compute_zdepdi_operands (imm, op)
2117 unsigned HOST_WIDE_INT imm;
2120 HOST_WIDE_INT lsb, len;
2122 /* Find the least significant set bit in IMM. */
2123 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2130 /* Choose variants based on *sign* of the 5-bit field. */
2131 if ((imm & 0x10) == 0)
2132 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2133 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2136 /* Find the width of the bitstring in IMM. */
2137 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2139 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2143 /* Sign extend IMM as a 5-bit value. */
2144 imm = (imm & 0xf) - 0x10;
2152 /* Output assembler code to perform a doubleword move insn
2153 with operands OPERANDS. */
2156 output_move_double (operands)
2159 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2161 rtx addreg0 = 0, addreg1 = 0;
2163 /* First classify both operands. */
2165 if (REG_P (operands[0]))
2167 else if (offsettable_memref_p (operands[0]))
2169 else if (GET_CODE (operands[0]) == MEM)
2174 if (REG_P (operands[1]))
2176 else if (CONSTANT_P (operands[1]))
2178 else if (offsettable_memref_p (operands[1]))
2180 else if (GET_CODE (operands[1]) == MEM)
2185 /* Check for the cases that the operand constraints are not
2186 supposed to allow to happen. Abort if we get one,
2187 because generating code for these cases is painful. */
2189 if (optype0 != REGOP && optype1 != REGOP)
2192 /* Handle auto decrementing and incrementing loads and stores
2193 specifically, since the structure of the function doesn't work
2194 for them without major modification. Do it better when we learn
2195 this port about the general inc/dec addressing of PA.
2196 (This was written by tege. Chide him if it doesn't work.) */
2198 if (optype0 == MEMOP)
2200 /* We have to output the address syntax ourselves, since print_operand
2201 doesn't deal with the addresses we want to use. Fix this later. */
2203 rtx addr = XEXP (operands[0], 0);
2204 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2206 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2208 operands[0] = XEXP (addr, 0);
2209 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2212 if (!reg_overlap_mentioned_p (high_reg, addr))
2214 /* No overlap between high target register and address
2215 register. (We do this in a non-obvious way to
2216 save a register file writeback) */
2217 if (GET_CODE (addr) == POST_INC)
2218 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2219 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2224 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2226 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2228 operands[0] = XEXP (addr, 0);
2229 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2232 if (!reg_overlap_mentioned_p (high_reg, addr))
2234 /* No overlap between high target register and address
2235 register. (We do this in a non-obvious way to
2236 save a register file writeback) */
2237 if (GET_CODE (addr) == PRE_INC)
2238 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2239 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2245 if (optype1 == MEMOP)
2247 /* We have to output the address syntax ourselves, since print_operand
2248 doesn't deal with the addresses we want to use. Fix this later. */
2250 rtx addr = XEXP (operands[1], 0);
2251 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2253 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2255 operands[1] = XEXP (addr, 0);
2256 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2259 if (!reg_overlap_mentioned_p (high_reg, addr))
2261 /* No overlap between high target register and address
2262 register. (We do this in a non-obvious way to
2263 save a register file writeback) */
2264 if (GET_CODE (addr) == POST_INC)
2265 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2266 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2270 /* This is an undefined situation. We should load into the
2271 address register *and* update that register. Probably
2272 we don't need to handle this at all. */
2273 if (GET_CODE (addr) == POST_INC)
2274 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2275 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2278 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2280 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2282 operands[1] = XEXP (addr, 0);
2283 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2286 if (!reg_overlap_mentioned_p (high_reg, addr))
2288 /* No overlap between high target register and address
2289 register. (We do this in a non-obvious way to
2290 save a register file writeback) */
2291 if (GET_CODE (addr) == PRE_INC)
2292 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2293 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2297 /* This is an undefined situation. We should load into the
2298 address register *and* update that register. Probably
2299 we don't need to handle this at all. */
2300 if (GET_CODE (addr) == PRE_INC)
2301 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2302 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2305 else if (GET_CODE (addr) == PLUS
2306 && GET_CODE (XEXP (addr, 0)) == MULT)
2308 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2310 if (!reg_overlap_mentioned_p (high_reg, addr))
2314 xoperands[0] = high_reg;
2315 xoperands[1] = XEXP (addr, 1);
2316 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2317 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2318 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2320 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2326 xoperands[0] = high_reg;
2327 xoperands[1] = XEXP (addr, 1);
2328 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2329 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2330 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2332 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2337 /* If an operand is an unoffsettable memory ref, find a register
2338 we can increment temporarily to make it refer to the second word. */
2340 if (optype0 == MEMOP)
2341 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2343 if (optype1 == MEMOP)
2344 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2346 /* Ok, we can do one word at a time.
2347 Normally we do the low-numbered word first.
2349 In either case, set up in LATEHALF the operands to use
2350 for the high-numbered word and in some cases alter the
2351 operands in OPERANDS to be suitable for the low-numbered word. */
2353 if (optype0 == REGOP)
2354 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2355 else if (optype0 == OFFSOP)
2356 latehalf[0] = adjust_address (operands[0], SImode, 4);
2358 latehalf[0] = operands[0];
2360 if (optype1 == REGOP)
2361 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2362 else if (optype1 == OFFSOP)
2363 latehalf[1] = adjust_address (operands[1], SImode, 4);
2364 else if (optype1 == CNSTOP)
2365 split_double (operands[1], &operands[1], &latehalf[1]);
2367 latehalf[1] = operands[1];
2369 /* If the first move would clobber the source of the second one,
2370 do them in the other order.
2372 This can happen in two cases:
2374 mem -> register where the first half of the destination register
2375 is the same register used in the memory's address. Reload
2376 can create such insns.
2378 mem in this case will be either register indirect or register
2379 indirect plus a valid offset.
2381 register -> register move where REGNO(dst) == REGNO(src + 1)
2382 someone (Tim/Tege?) claimed this can happen for parameter loads.
2384 Handle mem -> register case first. */
2385 if (optype0 == REGOP
2386 && (optype1 == MEMOP || optype1 == OFFSOP)
2387 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2390 /* Do the late half first. */
2392 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2393 output_asm_insn (singlemove_string (latehalf), latehalf);
2397 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2398 return singlemove_string (operands);
2401 /* Now handle register -> register case. */
2402 if (optype0 == REGOP && optype1 == REGOP
2403 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2405 output_asm_insn (singlemove_string (latehalf), latehalf);
2406 return singlemove_string (operands);
2409 /* Normal case: do the two words, low-numbered first. */
2411 output_asm_insn (singlemove_string (operands), operands);
2413 /* Make any unoffsettable addresses point at high-numbered word. */
2415 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2417 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2420 output_asm_insn (singlemove_string (latehalf), latehalf);
2422 /* Undo the adds we just did. */
2424 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2426 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2432 output_fp_move_double (operands)
2435 if (FP_REG_P (operands[0]))
2437 if (FP_REG_P (operands[1])
2438 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2439 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2441 output_asm_insn ("fldd%F1 %1,%0", operands);
2443 else if (FP_REG_P (operands[1]))
2445 output_asm_insn ("fstd%F0 %1,%0", operands);
2447 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2449 if (GET_CODE (operands[0]) == REG)
2452 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2453 xoperands[0] = operands[0];
2454 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2456 /* This is a pain. You have to be prepared to deal with an
2457 arbitrary address here including pre/post increment/decrement.
2459 so avoid this in the MD. */
2467 /* Return a REG that occurs in ADDR with coefficient 1.
2468 ADDR can be effectively incremented by incrementing REG. */
2471 find_addr_reg (addr)
2474 while (GET_CODE (addr) == PLUS)
2476 if (GET_CODE (XEXP (addr, 0)) == REG)
2477 addr = XEXP (addr, 0);
2478 else if (GET_CODE (XEXP (addr, 1)) == REG)
2479 addr = XEXP (addr, 1);
2480 else if (CONSTANT_P (XEXP (addr, 0)))
2481 addr = XEXP (addr, 1);
2482 else if (CONSTANT_P (XEXP (addr, 1)))
2483 addr = XEXP (addr, 0);
2487 if (GET_CODE (addr) == REG)
2492 /* Emit code to perform a block move.
2494 OPERANDS[0] is the destination pointer as a REG, clobbered.
2495 OPERANDS[1] is the source pointer as a REG, clobbered.
2496 OPERANDS[2] is a register for temporary storage.
2497 OPERANDS[4] is the size as a CONST_INT
2498 OPERANDS[3] is a register for temporary storage.
2499 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2500 OPERANDS[6] is another temporary register. */
2503 output_block_move (operands, size_is_constant)
2505 int size_is_constant ATTRIBUTE_UNUSED;
2507 int align = INTVAL (operands[5]);
2508 unsigned long n_bytes = INTVAL (operands[4]);
2510 /* We can't move more than four bytes at a time because the PA
2511 has no longer integer move insns. (Could use fp mem ops?) */
2515 /* Note that we know each loop below will execute at least twice
2516 (else we would have open-coded the copy). */
2520 /* Pre-adjust the loop counter. */
2521 operands[4] = GEN_INT (n_bytes - 8);
2522 output_asm_insn ("ldi %4,%2", operands);
2525 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2526 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2527 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2528 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2529 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2531 /* Handle the residual. There could be up to 7 bytes of
2532 residual to copy! */
2533 if (n_bytes % 8 != 0)
2535 operands[4] = GEN_INT (n_bytes % 4);
2536 if (n_bytes % 8 >= 4)
2537 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2538 if (n_bytes % 4 != 0)
2539 output_asm_insn ("ldw 0(%1),%6", operands);
2540 if (n_bytes % 8 >= 4)
2541 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2542 if (n_bytes % 4 != 0)
2543 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2548 /* Pre-adjust the loop counter. */
2549 operands[4] = GEN_INT (n_bytes - 4);
2550 output_asm_insn ("ldi %4,%2", operands);
2553 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2554 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2555 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2556 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2557 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2559 /* Handle the residual. */
2560 if (n_bytes % 4 != 0)
2562 if (n_bytes % 4 >= 2)
2563 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2564 if (n_bytes % 2 != 0)
2565 output_asm_insn ("ldb 0(%1),%6", operands);
2566 if (n_bytes % 4 >= 2)
2567 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2568 if (n_bytes % 2 != 0)
2569 output_asm_insn ("stb %6,0(%0)", operands);
2574 /* Pre-adjust the loop counter. */
2575 operands[4] = GEN_INT (n_bytes - 2);
2576 output_asm_insn ("ldi %4,%2", operands);
2579 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2580 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2581 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2582 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2583 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2585 /* Handle the residual. */
2586 if (n_bytes % 2 != 0)
2588 output_asm_insn ("ldb 0(%1),%3", operands);
2589 output_asm_insn ("stb %3,0(%0)", operands);
2598 /* Count the number of insns necessary to handle this block move.
2600 Basic structure is the same as emit_block_move, except that we
2601 count insns rather than emit them. */
2604 compute_movstrsi_length (insn)
2607 rtx pat = PATTERN (insn);
2608 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2609 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2610 unsigned int n_insns = 0;
2612 /* We can't move more than four bytes at a time because the PA
2613 has no longer integer move insns. (Could use fp mem ops?) */
2617 /* The basic copying loop. */
2621 if (n_bytes % (2 * align) != 0)
2623 if ((n_bytes % (2 * align)) >= align)
2626 if ((n_bytes % align) != 0)
2630 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2636 output_and (operands)
2639 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2641 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2642 int ls0, ls1, ms0, p, len;
2644 for (ls0 = 0; ls0 < 32; ls0++)
2645 if ((mask & (1 << ls0)) == 0)
2648 for (ls1 = ls0; ls1 < 32; ls1++)
2649 if ((mask & (1 << ls1)) != 0)
2652 for (ms0 = ls1; ms0 < 32; ms0++)
2653 if ((mask & (1 << ms0)) == 0)
2666 operands[2] = GEN_INT (len);
2667 return "{extru|extrw,u} %1,31,%2,%0";
2671 /* We could use this `depi' for the case above as well, but `depi'
2672 requires one more register file access than an `extru'. */
2677 operands[2] = GEN_INT (p);
2678 operands[3] = GEN_INT (len);
2679 return "{depi|depwi} 0,%2,%3,%0";
2683 return "and %1,%2,%0";
2686 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2687 storing the result in operands[0]. */
2689 output_64bit_and (operands)
2692 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2694 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2695 int ls0, ls1, ms0, p, len;
2697 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2698 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2701 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2702 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2705 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2706 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2709 if (ms0 != HOST_BITS_PER_WIDE_INT)
2712 if (ls1 == HOST_BITS_PER_WIDE_INT)
2719 operands[2] = GEN_INT (len);
2720 return "extrd,u %1,63,%2,%0";
2724 /* We could use this `depi' for the case above as well, but `depi'
2725 requires one more register file access than an `extru'. */
2730 operands[2] = GEN_INT (p);
2731 operands[3] = GEN_INT (len);
2732 return "depdi 0,%2,%3,%0";
2736 return "and %1,%2,%0";
2740 output_ior (operands)
2743 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2744 int bs0, bs1, p, len;
2746 if (INTVAL (operands[2]) == 0)
2747 return "copy %1,%0";
2749 for (bs0 = 0; bs0 < 32; bs0++)
2750 if ((mask & (1 << bs0)) != 0)
2753 for (bs1 = bs0; bs1 < 32; bs1++)
2754 if ((mask & (1 << bs1)) == 0)
2757 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2763 operands[2] = GEN_INT (p);
2764 operands[3] = GEN_INT (len);
2765 return "{depi|depwi} -1,%2,%3,%0";
2768 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2769 storing the result in operands[0]. */
2771 output_64bit_ior (operands)
2774 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2775 int bs0, bs1, p, len;
2777 if (INTVAL (operands[2]) == 0)
2778 return "copy %1,%0";
2780 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2781 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2784 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2785 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2788 if (bs1 != HOST_BITS_PER_WIDE_INT
2789 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2795 operands[2] = GEN_INT (p);
2796 operands[3] = GEN_INT (len);
2797 return "depdi -1,%2,%3,%0";
2800 /* Target hook for assembling integer objects. This code handles
2801 aligned SI and DI integers specially, since function references must
2802 be preceded by P%. */
2805 pa_assemble_integer (x, size, aligned_p)
2810 if (size == UNITS_PER_WORD && aligned_p
2811 && function_label_operand (x, VOIDmode))
2813 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2814 output_addr_const (asm_out_file, x);
2815 fputc ('\n', asm_out_file);
2818 return default_assemble_integer (x, size, aligned_p);
2821 /* Output an ascii string. */
2823 output_ascii (file, p, size)
2830 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2832 /* The HP assembler can only take strings of 256 characters at one
2833 time. This is a limitation on input line length, *not* the
2834 length of the string. Sigh. Even worse, it seems that the
2835 restriction is in number of input characters (see \xnn &
2836 \whatever). So we have to do this very carefully. */
2838 fputs ("\t.STRING \"", file);
2841 for (i = 0; i < size; i += 4)
2845 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2847 register unsigned int c = (unsigned char) p[i + io];
2849 if (c == '\"' || c == '\\')
2850 partial_output[co++] = '\\';
2851 if (c >= ' ' && c < 0177)
2852 partial_output[co++] = c;
2856 partial_output[co++] = '\\';
2857 partial_output[co++] = 'x';
2858 hexd = c / 16 - 0 + '0';
2860 hexd -= '9' - 'a' + 1;
2861 partial_output[co++] = hexd;
2862 hexd = c % 16 - 0 + '0';
2864 hexd -= '9' - 'a' + 1;
2865 partial_output[co++] = hexd;
2868 if (chars_output + co > 243)
2870 fputs ("\"\n\t.STRING \"", file);
2873 fwrite (partial_output, 1, (size_t) co, file);
2877 fputs ("\"\n", file);
2880 /* Try to rewrite floating point comparisons & branches to avoid
2881 useless add,tr insns.
2883 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2884 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2885 first attempt to remove useless add,tr insns. It is zero
2886 for the second pass as reorg sometimes leaves bogus REG_DEAD
2889 When CHECK_NOTES is zero we can only eliminate add,tr insns
2890 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2893 remove_useless_addtr_insns (check_notes)
2897 static int pass = 0;
2899 /* This is fairly cheap, so always run it when optimizing. */
2903 int fbranch_count = 0;
2905 /* Walk all the insns in this function looking for fcmp & fbranch
2906 instructions. Keep track of how many of each we find. */
2907 for (insn = get_insns (); insn; insn = next_insn (insn))
2911 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2912 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2915 tmp = PATTERN (insn);
2917 /* It must be a set. */
2918 if (GET_CODE (tmp) != SET)
2921 /* If the destination is CCFP, then we've found an fcmp insn. */
2922 tmp = SET_DEST (tmp);
2923 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2929 tmp = PATTERN (insn);
2930 /* If this is an fbranch instruction, bump the fbranch counter. */
2931 if (GET_CODE (tmp) == SET
2932 && SET_DEST (tmp) == pc_rtx
2933 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2934 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2935 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2936 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2944 /* Find all floating point compare + branch insns. If possible,
2945 reverse the comparison & the branch to avoid add,tr insns. */
2946 for (insn = get_insns (); insn; insn = next_insn (insn))
2950 /* Ignore anything that isn't an INSN. */
2951 if (GET_CODE (insn) != INSN)
2954 tmp = PATTERN (insn);
2956 /* It must be a set. */
2957 if (GET_CODE (tmp) != SET)
2960 /* The destination must be CCFP, which is register zero. */
2961 tmp = SET_DEST (tmp);
2962 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2965 /* INSN should be a set of CCFP.
2967 See if the result of this insn is used in a reversed FP
2968 conditional branch. If so, reverse our condition and
2969 the branch. Doing so avoids useless add,tr insns. */
2970 next = next_insn (insn);
2973 /* Jumps, calls and labels stop our search. */
2974 if (GET_CODE (next) == JUMP_INSN
2975 || GET_CODE (next) == CALL_INSN
2976 || GET_CODE (next) == CODE_LABEL)
2979 /* As does another fcmp insn. */
2980 if (GET_CODE (next) == INSN
2981 && GET_CODE (PATTERN (next)) == SET
2982 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2983 && REGNO (SET_DEST (PATTERN (next))) == 0)
2986 next = next_insn (next);
2989 /* Is NEXT_INSN a branch? */
2991 && GET_CODE (next) == JUMP_INSN)
2993 rtx pattern = PATTERN (next);
2995 /* If it a reversed fp conditional branch (eg uses add,tr)
2996 and CCFP dies, then reverse our conditional and the branch
2997 to avoid the add,tr. */
2998 if (GET_CODE (pattern) == SET
2999 && SET_DEST (pattern) == pc_rtx
3000 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3001 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3002 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3003 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3004 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3005 && (fcmp_count == fbranch_count
3007 && find_regno_note (next, REG_DEAD, 0))))
3009 /* Reverse the branch. */
3010 tmp = XEXP (SET_SRC (pattern), 1);
3011 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3012 XEXP (SET_SRC (pattern), 2) = tmp;
3013 INSN_CODE (next) = -1;
3015 /* Reverse our condition. */
3016 tmp = PATTERN (insn);
3017 PUT_CODE (XEXP (tmp, 1),
3018 (reverse_condition_maybe_unordered
3019 (GET_CODE (XEXP (tmp, 1)))));
3029 /* You may have trouble believing this, but this is the 32 bit HP-PA
3034 Variable arguments (optional; any number may be allocated)
3036 SP-(4*(N+9)) arg word N
3041 Fixed arguments (must be allocated; may remain unused)
3050 SP-32 External Data Pointer (DP)
3052 SP-24 External/stub RP (RP')
3056 SP-8 Calling Stub RP (RP'')
3061 SP-0 Stack Pointer (points to next available address)
3065 /* This function saves registers as follows. Registers marked with ' are
3066 this function's registers (as opposed to the previous function's).
3067 If a frame_pointer isn't needed, r4 is saved as a general register;
3068 the space for the frame pointer is still allocated, though, to keep
3074 SP (FP') Previous FP
3075 SP + 4 Alignment filler (sigh)
3076 SP + 8 Space for locals reserved here.
3080 SP + n All call saved register used.
3084 SP + o All call saved fp registers used.
3088 SP + p (SP') points to next available address.
3092 /* Global variables set by output_function_prologue(). */
3093 /* Size of frame. Need to know this to emit return insns from
3095 static int actual_fsize;
3096 static int local_fsize, save_fregs;
3098 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3099 Handle case where DISP > 8k by using the add_high_const patterns.
3101 Note in DISP > 8k case, we will leave the high part of the address
3102 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3105 store_reg (reg, disp, base)
3106 int reg, disp, base;
3108 rtx insn, dest, src, basereg;
3110 src = gen_rtx_REG (word_mode, reg);
3111 basereg = gen_rtx_REG (Pmode, base);
3112 if (VAL_14_BITS_P (disp))
3114 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3115 insn = emit_move_insn (dest, src);
3119 rtx delta = GEN_INT (disp);
3120 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3121 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3122 emit_move_insn (tmpreg, high);
3123 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3124 insn = emit_move_insn (dest, src);
3128 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3129 gen_rtx_SET (VOIDmode,
3130 gen_rtx_MEM (word_mode,
3131 gen_rtx_PLUS (word_mode, basereg,
3139 RTX_FRAME_RELATED_P (insn) = 1;
3142 /* Emit RTL to store REG at the memory location specified by BASE and then
3143 add MOD to BASE. MOD must be <= 8k. */
3146 store_reg_modify (base, reg, mod)
3149 rtx insn, basereg, srcreg, delta;
3151 if (! VAL_14_BITS_P (mod))
3154 basereg = gen_rtx_REG (Pmode, base);
3155 srcreg = gen_rtx_REG (word_mode, reg);
3156 delta = GEN_INT (mod);
3158 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3161 RTX_FRAME_RELATED_P (insn) = 1;
3163 /* RTX_FRAME_RELATED_P must be set on each frame related set
3164 in a parallel with more than one element. Don't set
3165 RTX_FRAME_RELATED_P in the first set if reg is temporary
3166 register 1. The effect of this operation is recorded in
3167 the initial copy. */
3170 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3171 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3175 /* The first element of a PARALLEL is always processed if it is
3176 a SET. Thus, we need an expression list for this case. */
3178 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3179 gen_rtx_SET (VOIDmode, basereg,
3180 gen_rtx_PLUS (word_mode, basereg, delta)),
3186 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3187 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3188 whether to add a frame note or not.
3190 In the DISP > 8k case, we leave the high part of the address in %r1.
3191 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3194 set_reg_plus_d (reg, base, disp, note)
3195 int reg, base, disp, note;
3199 if (VAL_14_BITS_P (disp))
3201 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3202 plus_constant (gen_rtx_REG (Pmode, base), disp));
3206 rtx basereg = gen_rtx_REG (Pmode, base);
3207 rtx delta = GEN_INT (disp);
3209 emit_move_insn (gen_rtx_REG (Pmode, 1),
3210 gen_rtx_PLUS (Pmode, basereg,
3211 gen_rtx_HIGH (Pmode, delta)));
3212 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3213 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3217 if (DO_FRAME_NOTES && note)
3218 RTX_FRAME_RELATED_P (insn) = 1;
3222 compute_frame_size (size, fregs_live)
3229 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3230 be consistent with the rounding and size calculation done here.
3231 Change them at the same time. */
3233 /* We do our own stack alignment. First, round the size of the
3234 stack locals up to a word boundary. */
3235 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3237 /* Space for previous frame pointer + filler. If any frame is
3238 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3239 waste some space here for the sake of HP compatibility. The
3240 first slot is only used when the frame pointer is needed. */
3241 if (size || frame_pointer_needed)
3242 size += STARTING_FRAME_OFFSET;
3244 /* If the current function calls __builtin_eh_return, then we need
3245 to allocate stack space for registers that will hold data for
3246 the exception handler. */
3247 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3251 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3253 size += i * UNITS_PER_WORD;
3256 /* Account for space used by the callee general register saves. */
3257 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3258 if (regs_ever_live[i])
3259 size += UNITS_PER_WORD;
3261 /* Account for space used by the callee floating point register saves. */
3262 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3263 if (regs_ever_live[i]
3264 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3268 /* We always save both halves of the FP register, so always
3269 increment the frame size by 8 bytes. */
3273 /* If any of the floating registers are saved, account for the
3274 alignment needed for the floating point register save block. */
3277 size = (size + 7) & ~7;
3282 /* The various ABIs include space for the outgoing parameters in the
3283 size of the current function's stack frame. We don't need to align
3284 for the outgoing arguments as their alignment is set by the final
3285 rounding for the frame as a whole. */
3286 size += current_function_outgoing_args_size;
3288 /* Allocate space for the fixed frame marker. This space must be
3289 allocated for any function that makes calls or allocates
3291 if (!current_function_is_leaf || size)
3292 size += TARGET_64BIT ? 48 : 32;
3294 /* Finally, round to the preferred stack boundary. */
3295 return ((size + PREFERRED_STACK_BOUNDARY / 8 - 1)
3296 & ~(PREFERRED_STACK_BOUNDARY / 8 - 1));
3299 /* Generate the assembly code for function entry. FILE is a stdio
3300 stream to output the code to. SIZE is an int: how many units of
3301 temporary storage to allocate.
3303 Refer to the array `regs_ever_live' to determine which registers to
3304 save; `regs_ever_live[I]' is nonzero if register number I is ever
3305 used in the function. This function is responsible for knowing
3306 which registers should not be saved even if used. */
3308 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3309 of memory. If any fpu reg is used in the function, we allocate
3310 such a block here, at the bottom of the frame, just in case it's needed.
3312 If this function is a leaf procedure, then we may choose not
3313 to do a "save" insn. The decision about whether or not
3314 to do this is made in regclass.c. */
3317 pa_output_function_prologue (file, size)
3319 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3321 /* The function's label and associated .PROC must never be
3322 separated and must be output *after* any profiling declarations
3323 to avoid changing spaces/subspaces within a procedure. */
3324 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3325 fputs ("\t.PROC\n", file);
3327 /* hppa_expand_prologue does the dirty work now. We just need
3328 to output the assembler directives which denote the start
3330 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3331 if (regs_ever_live[2])
3332 fputs (",CALLS,SAVE_RP", file);
3334 fputs (",NO_CALLS", file);
3336 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3337 at the beginning of the frame and that it is used as the frame
3338 pointer for the frame. We do this because our current frame
3339 layout doesn't conform to that specified in the the HP runtime
3340 documentation and we need a way to indicate to programs such as
3341 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3342 isn't used by HP compilers but is supported by the assembler.
3343 However, SAVE_SP is supposed to indicate that the previous stack
3344 pointer has been saved in the frame marker. */
3345 if (frame_pointer_needed)
3346 fputs (",SAVE_SP", file);
3348 /* Pass on information about the number of callee register saves
3349 performed in the prologue.
3351 The compiler is supposed to pass the highest register number
3352 saved, the assembler then has to adjust that number before
3353 entering it into the unwind descriptor (to account for any
3354 caller saved registers with lower register numbers than the
3355 first callee saved register). */
3357 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3360 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3362 fputs ("\n\t.ENTRY\n", file);
3364 remove_useless_addtr_insns (0);
3368 hppa_expand_prologue ()
3370 int merge_sp_adjust_with_store = 0;
3371 int size = get_frame_size ();
3379 /* Compute total size for frame pointer, filler, locals and rounding to
3380 the next word boundary. Similar code appears in compute_frame_size
3381 and must be changed in tandem with this code. */
3382 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3383 if (local_fsize || frame_pointer_needed)
3384 local_fsize += STARTING_FRAME_OFFSET;
3386 actual_fsize = compute_frame_size (size, &save_fregs);
3388 /* Compute a few things we will use often. */
3389 tmpreg = gen_rtx_REG (word_mode, 1);
3391 /* Save RP first. The calling conventions manual states RP will
3392 always be stored into the caller's frame at sp - 20 or sp - 16
3393 depending on which ABI is in use. */
3394 if (regs_ever_live[2] || current_function_calls_eh_return)
3395 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3397 /* Allocate the local frame and set up the frame pointer if needed. */
3398 if (actual_fsize != 0)
3400 if (frame_pointer_needed)
3402 /* Copy the old frame pointer temporarily into %r1. Set up the
3403 new stack pointer, then store away the saved old frame pointer
3404 into the stack at sp and at the same time update the stack
3405 pointer by actual_fsize bytes. Two versions, first
3406 handles small (<8k) frames. The second handles large (>=8k)
3408 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3411 /* We need to record the frame pointer save here since the
3412 new frame pointer is set in the following insn. */
3413 RTX_FRAME_RELATED_P (insn) = 1;
3415 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3416 gen_rtx_SET (VOIDmode,
3417 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3422 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3424 RTX_FRAME_RELATED_P (insn) = 1;
3426 if (VAL_14_BITS_P (actual_fsize))
3427 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3430 /* It is incorrect to store the saved frame pointer at *sp,
3431 then increment sp (writes beyond the current stack boundary).
3433 So instead use stwm to store at *sp and post-increment the
3434 stack pointer as an atomic operation. Then increment sp to
3435 finish allocating the new frame. */
3436 int adjust1 = 8192 - 64;
3437 int adjust2 = actual_fsize - adjust1;
3439 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3440 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3444 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3445 we need to store the previous stack pointer (frame pointer)
3446 into the frame marker on targets that use the HP unwind
3447 library. This allows the HP unwind library to be used to
3448 unwind GCC frames. However, we are not fully compatible
3449 with the HP library because our frame layout differs from
3450 that specified in the HP runtime specification.
3452 We don't want a frame note on this instruction as the frame
3453 marker moves during dynamic stack allocation.
3455 This instruction also serves as a blockage to prevent
3456 register spills from being scheduled before the stack
3457 pointer is raised. This is necessary as we store
3458 registers using the frame pointer as a base register,
3459 and the frame pointer is set before sp is raised. */
3460 if (TARGET_HPUX_UNWIND_LIBRARY)
3462 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3463 GEN_INT (TARGET_64BIT ? -8 : -4));
3465 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3469 emit_insn (gen_blockage ());
3471 /* no frame pointer needed. */
3474 /* In some cases we can perform the first callee register save
3475 and allocating the stack frame at the same time. If so, just
3476 make a note of it and defer allocating the frame until saving
3477 the callee registers. */
3478 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3479 merge_sp_adjust_with_store = 1;
3480 /* Can not optimize. Adjust the stack frame by actual_fsize
3483 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3488 /* Normal register save.
3490 Do not save the frame pointer in the frame_pointer_needed case. It
3491 was done earlier. */
3492 if (frame_pointer_needed)
3494 offset = local_fsize;
3496 /* Saving the EH return data registers in the frame is the simplest
3497 way to get the frame unwind information emitted. We put them
3498 just before the general registers. */
3499 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3501 unsigned int i, regno;
3505 regno = EH_RETURN_DATA_REGNO (i);
3506 if (regno == INVALID_REGNUM)
3509 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3510 offset += UNITS_PER_WORD;
3514 for (i = 18; i >= 4; i--)
3515 if (regs_ever_live[i] && ! call_used_regs[i])
3517 store_reg (i, offset, FRAME_POINTER_REGNUM);
3518 offset += UNITS_PER_WORD;
3521 /* Account for %r3 which is saved in a special place. */
3524 /* No frame pointer needed. */
3527 offset = local_fsize - actual_fsize;
3529 /* Saving the EH return data registers in the frame is the simplest
3530 way to get the frame unwind information emitted. */
3531 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3533 unsigned int i, regno;
3537 regno = EH_RETURN_DATA_REGNO (i);
3538 if (regno == INVALID_REGNUM)
3541 /* If merge_sp_adjust_with_store is nonzero, then we can
3542 optimize the first save. */
3543 if (merge_sp_adjust_with_store)
3545 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3546 merge_sp_adjust_with_store = 0;
3549 store_reg (regno, offset, STACK_POINTER_REGNUM);
3550 offset += UNITS_PER_WORD;
3554 for (i = 18; i >= 3; i--)
3555 if (regs_ever_live[i] && ! call_used_regs[i])
3557 /* If merge_sp_adjust_with_store is nonzero, then we can
3558 optimize the first GR save. */
3559 if (merge_sp_adjust_with_store)
3561 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3562 merge_sp_adjust_with_store = 0;
3565 store_reg (i, offset, STACK_POINTER_REGNUM);
3566 offset += UNITS_PER_WORD;
3570 /* If we wanted to merge the SP adjustment with a GR save, but we never
3571 did any GR saves, then just emit the adjustment here. */
3572 if (merge_sp_adjust_with_store)
3573 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3577 /* The hppa calling conventions say that %r19, the pic offset
3578 register, is saved at sp - 32 (in this function's frame)
3579 when generating PIC code. FIXME: What is the correct thing
3580 to do for functions which make no calls and allocate no
3581 frame? Do we need to allocate a frame, or can we just omit
3582 the save? For now we'll just omit the save. */
3583 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3584 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3586 /* Align pointer properly (doubleword boundary). */
3587 offset = (offset + 7) & ~7;
3589 /* Floating point register store. */
3594 /* First get the frame or stack pointer to the start of the FP register
3596 if (frame_pointer_needed)
3598 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3599 base = frame_pointer_rtx;
3603 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3604 base = stack_pointer_rtx;
3607 /* Now actually save the FP registers. */
3608 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3610 if (regs_ever_live[i]
3611 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3613 rtx addr, insn, reg;
3614 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3615 reg = gen_rtx_REG (DFmode, i);
3616 insn = emit_move_insn (addr, reg);
3619 RTX_FRAME_RELATED_P (insn) = 1;
3622 rtx mem = gen_rtx_MEM (DFmode,
3623 plus_constant (base, offset));
3625 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3626 gen_rtx_SET (VOIDmode, mem, reg),
3631 rtx meml = gen_rtx_MEM (SFmode,
3632 plus_constant (base, offset));
3633 rtx memr = gen_rtx_MEM (SFmode,
3634 plus_constant (base, offset + 4));
3635 rtx regl = gen_rtx_REG (SFmode, i);
3636 rtx regr = gen_rtx_REG (SFmode, i + 1);
3637 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3638 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3641 RTX_FRAME_RELATED_P (setl) = 1;
3642 RTX_FRAME_RELATED_P (setr) = 1;
3643 vec = gen_rtvec (2, setl, setr);
3645 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3646 gen_rtx_SEQUENCE (VOIDmode, vec),
3650 offset += GET_MODE_SIZE (DFmode);
3657 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3658 Handle case where DISP > 8k by using the add_high_const patterns. */
3661 load_reg (reg, disp, base)
3662 int reg, disp, base;
3664 rtx src, dest, basereg;
3666 dest = gen_rtx_REG (word_mode, reg);
3667 basereg = gen_rtx_REG (Pmode, base);
3668 if (VAL_14_BITS_P (disp))
3670 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3671 emit_move_insn (dest, src);
3675 rtx delta = GEN_INT (disp);
3676 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3677 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3678 emit_move_insn (tmpreg, high);
3679 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3680 emit_move_insn (dest, src);
3684 /* This function generates the assembly code for function exit.
3685 Args are as for output_function_prologue ().
3687 The function epilogue should not depend on the current stack
3688 pointer! It should use the frame pointer only. This is mandatory
3689 because of alloca; we also take advantage of it to omit stack
3690 adjustments before returning. */
3693 pa_output_function_epilogue (file, size)
3695 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3697 int last_address = 0;
3698 rtx insn = get_last_insn ();
3700 /* hppa_expand_epilogue does the dirty work now. We just need
3701 to output the assembler directives which denote the end
3704 To make debuggers happy, emit a nop if the epilogue was completely
3705 eliminated due to a volatile call as the last insn in the
3706 current function. That way the return address (in %r2) will
3707 always point to a valid instruction in the current function. */
3709 /* Get the last real insn. */
3710 if (GET_CODE (insn) == NOTE)
3711 insn = prev_real_insn (insn);
3713 /* If it is a sequence, then look inside. */
3714 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3715 insn = XVECEXP (PATTERN (insn), 0, 0);
3717 /* If insn is a CALL_INSN, then it must be a call to a volatile
3718 function (otherwise there would be epilogue insns). */
3719 if (insn && GET_CODE (insn) == CALL_INSN)
3721 fputs ("\tnop\n", file);
3725 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3727 /* Finally, update the total number of code bytes output so far. */
3728 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3729 && !flag_function_sections)
3731 if (INSN_ADDRESSES_SET_P ())
3733 unsigned long old_total = total_code_bytes;
3735 insn = get_last_nonnote_insn ();
3736 last_address += INSN_ADDRESSES (INSN_UID (insn));
3738 last_address += insn_default_length (insn);
3740 total_code_bytes += last_address;
3741 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3743 /* Be prepared to handle overflows. */
3744 if (old_total > total_code_bytes)
3745 total_code_bytes = -1;
3748 total_code_bytes = -1;
3753 hppa_expand_epilogue ()
3757 int merge_sp_adjust_with_load = 0;
3760 /* We will use this often. */
3761 tmpreg = gen_rtx_REG (word_mode, 1);
3763 /* Try to restore RP early to avoid load/use interlocks when
3764 RP gets used in the return (bv) instruction. This appears to still
3765 be necessary even when we schedule the prologue and epilogue. */
3766 if (regs_ever_live [2] || current_function_calls_eh_return)
3768 ret_off = TARGET_64BIT ? -16 : -20;
3769 if (frame_pointer_needed)
3771 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3776 /* No frame pointer, and stack is smaller than 8k. */
3777 if (VAL_14_BITS_P (ret_off - actual_fsize))
3779 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3785 /* General register restores. */
3786 if (frame_pointer_needed)
3788 offset = local_fsize;
3790 /* If the current function calls __builtin_eh_return, then we need
3791 to restore the saved EH data registers. */
3792 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3794 unsigned int i, regno;
3798 regno = EH_RETURN_DATA_REGNO (i);
3799 if (regno == INVALID_REGNUM)
3802 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3803 offset += UNITS_PER_WORD;
3807 for (i = 18; i >= 4; i--)
3808 if (regs_ever_live[i] && ! call_used_regs[i])
3810 load_reg (i, offset, FRAME_POINTER_REGNUM);
3811 offset += UNITS_PER_WORD;
3816 offset = local_fsize - actual_fsize;
3818 /* If the current function calls __builtin_eh_return, then we need
3819 to restore the saved EH data registers. */
3820 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3822 unsigned int i, regno;
3826 regno = EH_RETURN_DATA_REGNO (i);
3827 if (regno == INVALID_REGNUM)
3830 /* Only for the first load.
3831 merge_sp_adjust_with_load holds the register load
3832 with which we will merge the sp adjustment. */
3833 if (merge_sp_adjust_with_load == 0
3835 && VAL_14_BITS_P (-actual_fsize))
3836 merge_sp_adjust_with_load = regno;
3838 load_reg (regno, offset, STACK_POINTER_REGNUM);
3839 offset += UNITS_PER_WORD;
3843 for (i = 18; i >= 3; i--)
3845 if (regs_ever_live[i] && ! call_used_regs[i])
3847 /* Only for the first load.
3848 merge_sp_adjust_with_load holds the register load
3849 with which we will merge the sp adjustment. */
3850 if (merge_sp_adjust_with_load == 0
3852 && VAL_14_BITS_P (-actual_fsize))
3853 merge_sp_adjust_with_load = i;
3855 load_reg (i, offset, STACK_POINTER_REGNUM);
3856 offset += UNITS_PER_WORD;
3861 /* Align pointer properly (doubleword boundary). */
3862 offset = (offset + 7) & ~7;
3864 /* FP register restores. */
3867 /* Adjust the register to index off of. */
3868 if (frame_pointer_needed)
3869 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3871 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3873 /* Actually do the restores now. */
3874 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3875 if (regs_ever_live[i]
3876 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3878 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3879 rtx dest = gen_rtx_REG (DFmode, i);
3880 emit_move_insn (dest, src);
3884 /* Emit a blockage insn here to keep these insns from being moved to
3885 an earlier spot in the epilogue, or into the main instruction stream.
3887 This is necessary as we must not cut the stack back before all the
3888 restores are finished. */
3889 emit_insn (gen_blockage ());
3891 /* Reset stack pointer (and possibly frame pointer). The stack
3892 pointer is initially set to fp + 64 to avoid a race condition. */
3893 if (frame_pointer_needed)
3895 rtx delta = GEN_INT (-64);
3897 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3898 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3900 /* If we were deferring a callee register restore, do it now. */
3901 else if (merge_sp_adjust_with_load)
3903 rtx delta = GEN_INT (-actual_fsize);
3904 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3906 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3908 else if (actual_fsize != 0)
3909 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3912 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3913 frame greater than 8k), do so now. */
3915 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3917 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3919 rtx sa = EH_RETURN_STACKADJ_RTX;
3921 emit_insn (gen_blockage ());
3922 emit_insn (TARGET_64BIT
3923 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3924 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3929 hppa_pic_save_rtx ()
3931 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3935 hppa_profile_hook (label_no)
3938 rtx begin_label_rtx, call_insn;
3939 char begin_label_name[16];
3941 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3943 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3946 emit_move_insn (arg_pointer_rtx,
3947 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3950 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3952 #ifndef NO_PROFILE_COUNTERS
3954 rtx count_label_rtx, addr, r24;
3955 char count_label_name[16];
3957 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3958 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3960 addr = force_reg (Pmode, count_label_rtx);
3961 r24 = gen_rtx_REG (Pmode, 24);
3962 emit_move_insn (r24, addr);
3964 /* %r25 is set from within the output pattern. */
3966 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3967 GEN_INT (TARGET_64BIT ? 24 : 12),
3970 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3973 /* %r25 is set from within the output pattern. */
3975 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3976 GEN_INT (TARGET_64BIT ? 16 : 8),
3980 /* Indicate the _mcount call cannot throw, nor will it execute a
3982 REG_NOTES (call_insn)
3983 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3987 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3989 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3991 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3995 /* Fetch the return address for the frame COUNT steps up from
3996 the current frame, after the prologue. FRAMEADDR is the
3997 frame pointer of the COUNT frame.
3999 We want to ignore any export stub remnants here. To handle this,
4000 we examine the code at the return address, and if it is an export
4001 stub, we return a memory rtx for the stub return address stored
4004 The value returned is used in two different ways:
4006 1. To find a function's caller.
4008 2. To change the return address for a function.
4010 This function handles most instances of case 1; however, it will
4011 fail if there are two levels of stubs to execute on the return
4012 path. The only way I believe that can happen is if the return value
4013 needs a parameter relocation, which never happens for C code.
4015 This function handles most instances of case 2; however, it will
4016 fail if we did not originally have stub code on the return path
4017 but will need stub code on the new return path. This can happen if
4018 the caller & callee are both in the main program, but the new
4019 return location is in a shared library. */
4022 return_addr_rtx (count, frameaddr)
4034 rp = get_hard_reg_initial_val (Pmode, 2);
4036 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4039 saved_rp = gen_reg_rtx (Pmode);
4040 emit_move_insn (saved_rp, rp);
4042 /* Get pointer to the instruction stream. We have to mask out the
4043 privilege level from the two low order bits of the return address
4044 pointer here so that ins will point to the start of the first
4045 instruction that would have been executed if we returned. */
4046 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4047 label = gen_label_rtx ();
4049 /* Check the instruction stream at the normal return address for the
4052 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4053 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4054 0x00011820 | stub+16: mtsp r1,sr0
4055 0xe0400002 | stub+20: be,n 0(sr0,rp)
4057 If it is an export stub, than our return address is really in
4060 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4061 NULL_RTX, SImode, 1);
4062 emit_jump_insn (gen_bne (label));
4064 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4065 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4066 emit_jump_insn (gen_bne (label));
4068 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4069 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4070 emit_jump_insn (gen_bne (label));
4072 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4073 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4075 /* If there is no export stub then just use the value saved from
4076 the return pointer register. */
4078 emit_jump_insn (gen_bne (label));
4080 /* Here we know that our return address points to an export
4081 stub. We don't want to return the address of the export stub,
4082 but rather the return address of the export stub. That return
4083 address is stored at -24[frameaddr]. */
4085 emit_move_insn (saved_rp,
4087 memory_address (Pmode,
4088 plus_constant (frameaddr,
4095 /* This is only valid once reload has completed because it depends on
4096 knowing exactly how much (if any) frame there is and...
4098 It's only valid if there is no frame marker to de-allocate and...
4100 It's only valid if %r2 hasn't been saved into the caller's frame
4101 (we're not profiling and %r2 isn't live anywhere). */
4103 hppa_can_use_return_insn_p ()
4105 return (reload_completed
4106 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4107 && ! regs_ever_live[2]
4108 && ! frame_pointer_needed);
4112 emit_bcond_fp (code, operand0)
4116 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4117 gen_rtx_IF_THEN_ELSE (VOIDmode,
4118 gen_rtx_fmt_ee (code,
4120 gen_rtx_REG (CCFPmode, 0),
4122 gen_rtx_LABEL_REF (VOIDmode, operand0),
4128 gen_cmp_fp (code, operand0, operand1)
4130 rtx operand0, operand1;
4132 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4133 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4136 /* Adjust the cost of a scheduling dependency. Return the new cost of
4137 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4140 pa_adjust_cost (insn, link, dep_insn, cost)
4146 enum attr_type attr_type;
4148 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4149 true dependencies as they are described with bypasses now. */
4150 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4153 if (! recog_memoized (insn))
4156 attr_type = get_attr_type (insn);
4158 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4160 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4163 if (attr_type == TYPE_FPLOAD)
4165 rtx pat = PATTERN (insn);
4166 rtx dep_pat = PATTERN (dep_insn);
4167 if (GET_CODE (pat) == PARALLEL)
4169 /* This happens for the fldXs,mb patterns. */
4170 pat = XVECEXP (pat, 0, 0);
4172 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4173 /* If this happens, we have to extend this to schedule
4174 optimally. Return 0 for now. */
4177 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4179 if (! recog_memoized (dep_insn))
4181 switch (get_attr_type (dep_insn))
4188 case TYPE_FPSQRTSGL:
4189 case TYPE_FPSQRTDBL:
4190 /* A fpload can't be issued until one cycle before a
4191 preceding arithmetic operation has finished if
4192 the target of the fpload is any of the sources
4193 (or destination) of the arithmetic operation. */
4194 return insn_default_latency (dep_insn) - 1;
4201 else if (attr_type == TYPE_FPALU)
4203 rtx pat = PATTERN (insn);
4204 rtx dep_pat = PATTERN (dep_insn);
4205 if (GET_CODE (pat) == PARALLEL)
4207 /* This happens for the fldXs,mb patterns. */
4208 pat = XVECEXP (pat, 0, 0);
4210 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4211 /* If this happens, we have to extend this to schedule
4212 optimally. Return 0 for now. */
4215 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4217 if (! recog_memoized (dep_insn))
4219 switch (get_attr_type (dep_insn))
4223 case TYPE_FPSQRTSGL:
4224 case TYPE_FPSQRTDBL:
4225 /* An ALU flop can't be issued until two cycles before a
4226 preceding divide or sqrt operation has finished if
4227 the target of the ALU flop is any of the sources
4228 (or destination) of the divide or sqrt operation. */
4229 return insn_default_latency (dep_insn) - 2;
4237 /* For other anti dependencies, the cost is 0. */
4240 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4242 /* Output dependency; DEP_INSN writes a register that INSN writes some
4244 if (attr_type == TYPE_FPLOAD)
4246 rtx pat = PATTERN (insn);
4247 rtx dep_pat = PATTERN (dep_insn);
4248 if (GET_CODE (pat) == PARALLEL)
4250 /* This happens for the fldXs,mb patterns. */
4251 pat = XVECEXP (pat, 0, 0);
4253 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4254 /* If this happens, we have to extend this to schedule
4255 optimally. Return 0 for now. */
4258 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4260 if (! recog_memoized (dep_insn))
4262 switch (get_attr_type (dep_insn))
4269 case TYPE_FPSQRTSGL:
4270 case TYPE_FPSQRTDBL:
4271 /* A fpload can't be issued until one cycle before a
4272 preceding arithmetic operation has finished if
4273 the target of the fpload is the destination of the
4274 arithmetic operation.
4276 Exception: For PA7100LC, PA7200 and PA7300, the cost
4277 is 3 cycles, unless they bundle together. We also
4278 pay the penalty if the second insn is a fpload. */
4279 return insn_default_latency (dep_insn) - 1;
4286 else if (attr_type == TYPE_FPALU)
4288 rtx pat = PATTERN (insn);
4289 rtx dep_pat = PATTERN (dep_insn);
4290 if (GET_CODE (pat) == PARALLEL)
4292 /* This happens for the fldXs,mb patterns. */
4293 pat = XVECEXP (pat, 0, 0);
4295 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4296 /* If this happens, we have to extend this to schedule
4297 optimally. Return 0 for now. */
4300 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4302 if (! recog_memoized (dep_insn))
4304 switch (get_attr_type (dep_insn))
4308 case TYPE_FPSQRTSGL:
4309 case TYPE_FPSQRTDBL:
4310 /* An ALU flop can't be issued until two cycles before a
4311 preceding divide or sqrt operation has finished if
4312 the target of the ALU flop is also the target of
4313 the divide or sqrt operation. */
4314 return insn_default_latency (dep_insn) - 2;
4322 /* For other output dependencies, the cost is 0. */
4329 /* Adjust scheduling priorities. We use this to try and keep addil
4330 and the next use of %r1 close together. */
4332 pa_adjust_priority (insn, priority)
4336 rtx set = single_set (insn);
4340 src = SET_SRC (set);
4341 dest = SET_DEST (set);
4342 if (GET_CODE (src) == LO_SUM
4343 && symbolic_operand (XEXP (src, 1), VOIDmode)
4344 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4347 else if (GET_CODE (src) == MEM
4348 && GET_CODE (XEXP (src, 0)) == LO_SUM
4349 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4350 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4353 else if (GET_CODE (dest) == MEM
4354 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4355 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4356 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4362 /* The 700 can only issue a single insn at a time.
4363 The 7XXX processors can issue two insns at a time.
4364 The 8000 can issue 4 insns at a time. */
4370 case PROCESSOR_700: return 1;
4371 case PROCESSOR_7100: return 2;
4372 case PROCESSOR_7100LC: return 2;
4373 case PROCESSOR_7200: return 2;
4374 case PROCESSOR_7300: return 2;
4375 case PROCESSOR_8000: return 4;
4384 /* Return any length adjustment needed by INSN which already has its length
4385 computed as LENGTH. Return zero if no adjustment is necessary.
4387 For the PA: function calls, millicode calls, and backwards short
4388 conditional branches with unfilled delay slots need an adjustment by +1
4389 (to account for the NOP which will be inserted into the instruction stream).
4391 Also compute the length of an inline block move here as it is too
4392 complicated to express as a length attribute in pa.md. */
4394 pa_adjust_insn_length (insn, length)
4398 rtx pat = PATTERN (insn);
4400 /* Call insns which are *not* indirect and have unfilled delay slots. */
4401 if (GET_CODE (insn) == CALL_INSN)
4404 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4405 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4407 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4408 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4414 /* Jumps inside switch tables which have unfilled delay slots
4415 also need adjustment. */
4416 else if (GET_CODE (insn) == JUMP_INSN
4417 && simplejump_p (insn)
4418 && GET_MODE (insn) == SImode)
4420 /* Millicode insn with an unfilled delay slot. */
4421 else if (GET_CODE (insn) == INSN
4422 && GET_CODE (pat) != SEQUENCE
4423 && GET_CODE (pat) != USE
4424 && GET_CODE (pat) != CLOBBER
4425 && get_attr_type (insn) == TYPE_MILLI)
4427 /* Block move pattern. */
4428 else if (GET_CODE (insn) == INSN
4429 && GET_CODE (pat) == PARALLEL
4430 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4431 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4432 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4433 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4434 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4435 return compute_movstrsi_length (insn) - 4;
4436 /* Conditional branch with an unfilled delay slot. */
4437 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4439 /* Adjust a short backwards conditional with an unfilled delay slot. */
4440 if (GET_CODE (pat) == SET
4442 && ! forward_branch_p (insn))
4444 else if (GET_CODE (pat) == PARALLEL
4445 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4448 /* Adjust dbra insn with short backwards conditional branch with
4449 unfilled delay slot -- only for case where counter is in a
4450 general register register. */
4451 else if (GET_CODE (pat) == PARALLEL
4452 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4453 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4454 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4456 && ! forward_branch_p (insn))
4464 /* Print operand X (an rtx) in assembler syntax to file FILE.
4465 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4466 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4469 print_operand (file, x, code)
4477 /* Output a 'nop' if there's nothing for the delay slot. */
4478 if (dbr_sequence_length () == 0)
4479 fputs ("\n\tnop", file);
4482 /* Output a nullification completer if there's nothing for the */
4483 /* delay slot or nullification is requested. */
4484 if (dbr_sequence_length () == 0 ||
4486 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4490 /* Print out the second register name of a register pair.
4491 I.e., R (6) => 7. */
4492 fputs (reg_names[REGNO (x) + 1], file);
4495 /* A register or zero. */
4497 || (x == CONST0_RTX (DFmode))
4498 || (x == CONST0_RTX (SFmode)))
4500 fputs ("%r0", file);
4506 /* A register or zero (floating point). */
4508 || (x == CONST0_RTX (DFmode))
4509 || (x == CONST0_RTX (SFmode)))
4511 fputs ("%fr0", file);
4520 xoperands[0] = XEXP (XEXP (x, 0), 0);
4521 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4522 output_global_address (file, xoperands[1], 0);
4523 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4527 case 'C': /* Plain (C)ondition */
4529 switch (GET_CODE (x))
4532 fputs ("=", file); break;
4534 fputs ("<>", file); break;
4536 fputs (">", file); break;
4538 fputs (">=", file); break;
4540 fputs (">>=", file); break;
4542 fputs (">>", file); break;
4544 fputs ("<", file); break;
4546 fputs ("<=", file); break;
4548 fputs ("<<=", file); break;
4550 fputs ("<<", file); break;
4555 case 'N': /* Condition, (N)egated */
4556 switch (GET_CODE (x))
4559 fputs ("<>", file); break;
4561 fputs ("=", file); break;
4563 fputs ("<=", file); break;
4565 fputs ("<", file); break;
4567 fputs ("<<", file); break;
4569 fputs ("<<=", file); break;
4571 fputs (">=", file); break;
4573 fputs (">", file); break;
4575 fputs (">>", file); break;
4577 fputs (">>=", file); break;
4582 /* For floating point comparisons. Note that the output
4583 predicates are the complement of the desired mode. */
4585 switch (GET_CODE (x))
4588 fputs ("!=", file); break;
4590 fputs ("=", file); break;
4592 fputs ("!>", file); break;
4594 fputs ("!>=", file); break;
4596 fputs ("!<", file); break;
4598 fputs ("!<=", file); break;
4600 fputs ("!<>", file); break;
4602 fputs (">", file); break;
4604 fputs (">=", file); break;
4606 fputs ("<", file); break;
4608 fputs ("<=", file); break;
4610 fputs ("<>", file); break;
4612 fputs ("<=>", file); break;
4614 fputs ("!<=>", file); break;
4619 case 'S': /* Condition, operands are (S)wapped. */
4620 switch (GET_CODE (x))
4623 fputs ("=", file); break;
4625 fputs ("<>", file); break;
4627 fputs ("<", file); break;
4629 fputs ("<=", file); break;
4631 fputs ("<<=", file); break;
4633 fputs ("<<", file); break;
4635 fputs (">", file); break;
4637 fputs (">=", file); break;
4639 fputs (">>=", file); break;
4641 fputs (">>", file); break;
4646 case 'B': /* Condition, (B)oth swapped and negate. */
4647 switch (GET_CODE (x))
4650 fputs ("<>", file); break;
4652 fputs ("=", file); break;
4654 fputs (">=", file); break;
4656 fputs (">", file); break;
4658 fputs (">>", file); break;
4660 fputs (">>=", file); break;
4662 fputs ("<=", file); break;
4664 fputs ("<", file); break;
4666 fputs ("<<", file); break;
4668 fputs ("<<=", file); break;
4674 if (GET_CODE (x) == CONST_INT)
4676 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4681 if (GET_CODE (x) == CONST_INT)
4683 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4688 if (GET_CODE (x) == CONST_INT)
4690 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4695 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4697 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4702 if (GET_CODE (x) == CONST_INT)
4704 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4709 if (GET_CODE (x) == CONST_INT)
4711 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4716 if (GET_CODE (x) == CONST_INT)
4721 switch (GET_CODE (XEXP (x, 0)))
4725 if (ASSEMBLER_DIALECT == 0)
4726 fputs ("s,mb", file);
4728 fputs (",mb", file);
4732 if (ASSEMBLER_DIALECT == 0)
4733 fputs ("s,ma", file);
4735 fputs (",ma", file);
4738 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4739 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4741 if (ASSEMBLER_DIALECT == 0)
4742 fputs ("x,s", file);
4746 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4750 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4756 output_global_address (file, x, 0);
4759 output_global_address (file, x, 1);
4761 case 0: /* Don't do anything special */
4766 compute_zdepwi_operands (INTVAL (x), op);
4767 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4773 compute_zdepdi_operands (INTVAL (x), op);
4774 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4778 /* We can get here from a .vtable_inherit due to our
4779 CONSTANT_ADDRESS_P rejecting perfectly good constant
4785 if (GET_CODE (x) == REG)
4787 fputs (reg_names [REGNO (x)], file);
4788 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4794 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4795 && (REGNO (x) & 1) == 0)
4798 else if (GET_CODE (x) == MEM)
4800 int size = GET_MODE_SIZE (GET_MODE (x));
4801 rtx base = NULL_RTX;
4802 switch (GET_CODE (XEXP (x, 0)))
4806 base = XEXP (XEXP (x, 0), 0);
4807 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4811 base = XEXP (XEXP (x, 0), 0);
4812 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4815 if (GET_CODE (XEXP (x, 0)) == PLUS
4816 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4817 fprintf (file, "%s(%s)",
4818 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4819 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4820 else if (GET_CODE (XEXP (x, 0)) == PLUS
4821 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4822 fprintf (file, "%s(%s)",
4823 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4824 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4826 output_address (XEXP (x, 0));
4831 output_addr_const (file, x);
4834 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4837 output_global_address (file, x, round_constant)
4843 /* Imagine (high (const (plus ...))). */
4844 if (GET_CODE (x) == HIGH)
4847 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4848 assemble_name (file, XSTR (x, 0));
4849 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4851 assemble_name (file, XSTR (x, 0));
4852 fputs ("-$global$", file);
4854 else if (GET_CODE (x) == CONST)
4856 const char *sep = "";
4857 int offset = 0; /* assembler wants -$global$ at end */
4858 rtx base = NULL_RTX;
4860 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4862 base = XEXP (XEXP (x, 0), 0);
4863 output_addr_const (file, base);
4865 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4866 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4869 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4871 base = XEXP (XEXP (x, 0), 1);
4872 output_addr_const (file, base);
4874 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4875 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4878 /* How bogus. The compiler is apparently responsible for
4879 rounding the constant if it uses an LR field selector.
4881 The linker and/or assembler seem a better place since
4882 they have to do this kind of thing already.
4884 If we fail to do this, HP's optimizing linker may eliminate
4885 an addil, but not update the ldw/stw/ldo instruction that
4886 uses the result of the addil. */
4888 offset = ((offset + 0x1000) & ~0x1fff);
4890 if (GET_CODE (XEXP (x, 0)) == PLUS)
4900 else if (GET_CODE (XEXP (x, 0)) == MINUS
4901 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4905 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4906 fputs ("-$global$", file);
4908 fprintf (file, "%s%d", sep, offset);
4911 output_addr_const (file, x);
4914 /* Output boilerplate text to appear at the beginning of the file.
4915 There are several possible versions. */
4916 #define aputs(x) fputs(x, asm_out_file)
4918 pa_file_start_level ()
4921 aputs ("\t.LEVEL 2.0w\n");
4922 else if (TARGET_PA_20)
4923 aputs ("\t.LEVEL 2.0\n");
4924 else if (TARGET_PA_11)
4925 aputs ("\t.LEVEL 1.1\n");
4927 aputs ("\t.LEVEL 1.0\n");
4931 pa_file_start_space (sortspace)
4934 aputs ("\t.SPACE $PRIVATE$");
4937 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
4938 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
4939 "\n\t.SPACE $TEXT$");
4942 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
4943 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
4947 pa_file_start_file (want_version)
4950 if (write_symbols != NO_DEBUG)
4952 output_file_directive (asm_out_file, main_input_filename);
4954 aputs ("\t.version\t\"01.01\"\n");
4959 pa_file_start_mcount (aswhat)
4963 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
4967 pa_elf_file_start ()
4969 pa_file_start_level ();
4970 pa_file_start_mcount ("ENTRY");
4971 pa_file_start_file (0);
4975 pa_som_file_start ()
4977 pa_file_start_level ();
4978 pa_file_start_space (0);
4979 aputs ("\t.IMPORT $global$,DATA\n"
4980 "\t.IMPORT $$dyncall,MILLICODE\n");
4981 pa_file_start_mcount ("CODE");
4982 pa_file_start_file (0);
4986 pa_linux_file_start ()
4988 pa_file_start_file (1);
4989 pa_file_start_level ();
4990 pa_file_start_mcount ("CODE");
4994 pa_hpux64_gas_file_start ()
4996 pa_file_start_level ();
4997 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
4999 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5001 pa_file_start_file (1);
5005 pa_hpux64_hpas_file_start ()
5007 pa_file_start_level ();
5008 pa_file_start_space (1);
5009 pa_file_start_mcount ("CODE");
5010 pa_file_start_file (0);
5014 static struct deferred_plabel *
5020 /* See if we have already put this function on the list of deferred
5021 plabels. This list is generally small, so a liner search is not
5022 too ugly. If it proves too slow replace it with something faster. */
5023 for (i = 0; i < n_deferred_plabels; i++)
5024 if (strcmp (fname, deferred_plabels[i].name) == 0)
5027 /* If the deferred plabel list is empty, or this entry was not found
5028 on the list, create a new entry on the list. */
5029 if (deferred_plabels == NULL || i == n_deferred_plabels)
5031 const char *real_name;
5033 if (deferred_plabels == 0)
5034 deferred_plabels = (struct deferred_plabel *)
5035 ggc_alloc (sizeof (struct deferred_plabel));
5037 deferred_plabels = (struct deferred_plabel *)
5038 ggc_realloc (deferred_plabels,
5039 ((n_deferred_plabels + 1)
5040 * sizeof (struct deferred_plabel)));
5042 i = n_deferred_plabels++;
5043 deferred_plabels[i].internal_label = gen_label_rtx ();
5044 deferred_plabels[i].name = ggc_strdup (fname);
5046 /* Gross. We have just implicitly taken the address of this function,
5048 real_name = (*targetm.strip_name_encoding) (fname);
5049 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5052 return &deferred_plabels[i];
5056 output_deferred_plabels ()
5059 /* If we have deferred plabels, then we need to switch into the data
5060 section and align it to a 4 byte boundary before we output the
5061 deferred plabels. */
5062 if (n_deferred_plabels)
5065 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5068 /* Now output the deferred plabels. */
5069 for (i = 0; i < n_deferred_plabels; i++)
5071 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5072 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5073 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5074 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5078 /* HP's millicode routines mean something special to the assembler.
5079 Keep track of which ones we have used. */
5081 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5082 static void import_milli PARAMS ((enum millicodes));
5083 static char imported[(int) end1000];
5084 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5085 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5086 #define MILLI_START 10
5090 enum millicodes code;
5092 char str[sizeof (import_string)];
5094 if (!imported[(int) code])
5096 imported[(int) code] = 1;
5097 strcpy (str, import_string);
5098 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5099 output_asm_insn (str, 0);
5103 /* The register constraints have put the operands and return value in
5104 the proper registers. */
5107 output_mul_insn (unsignedp, insn)
5108 int unsignedp ATTRIBUTE_UNUSED;
5111 import_milli (mulI);
5112 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5115 /* Emit the rtl for doing a division by a constant. */
5117 /* Do magic division millicodes exist for this value? */
5118 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5121 /* We'll use an array to keep track of the magic millicodes and
5122 whether or not we've used them already. [n][0] is signed, [n][1] is
5125 static int div_milli[16][2];
5128 div_operand (op, mode)
5130 enum machine_mode mode;
5132 return (mode == SImode
5133 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5134 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5135 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5139 emit_hpdiv_const (operands, unsignedp)
5143 if (GET_CODE (operands[2]) == CONST_INT
5144 && INTVAL (operands[2]) > 0
5145 && INTVAL (operands[2]) < 16
5146 && magic_milli[INTVAL (operands[2])])
5148 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5150 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5153 (PARALLEL, VOIDmode,
5154 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5155 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5157 gen_rtx_REG (SImode, 26),
5159 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5160 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5161 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5162 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5163 gen_rtx_CLOBBER (VOIDmode, ret))));
5164 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5171 output_div_insn (operands, unsignedp, insn)
5178 /* If the divisor is a constant, try to use one of the special
5180 if (GET_CODE (operands[0]) == CONST_INT)
5182 static char buf[100];
5183 divisor = INTVAL (operands[0]);
5184 if (!div_milli[divisor][unsignedp])
5186 div_milli[divisor][unsignedp] = 1;
5188 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5190 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5194 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5195 INTVAL (operands[0]));
5196 return output_millicode_call (insn,
5197 gen_rtx_SYMBOL_REF (SImode, buf));
5201 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5202 INTVAL (operands[0]));
5203 return output_millicode_call (insn,
5204 gen_rtx_SYMBOL_REF (SImode, buf));
5207 /* Divisor isn't a special constant. */
5212 import_milli (divU);
5213 return output_millicode_call (insn,
5214 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5218 import_milli (divI);
5219 return output_millicode_call (insn,
5220 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5225 /* Output a $$rem millicode to do mod. */
5228 output_mod_insn (unsignedp, insn)
5234 import_milli (remU);
5235 return output_millicode_call (insn,
5236 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5240 import_milli (remI);
5241 return output_millicode_call (insn,
5242 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5247 output_arg_descriptor (call_insn)
5250 const char *arg_regs[4];
5251 enum machine_mode arg_mode;
5253 int i, output_flag = 0;
5256 /* We neither need nor want argument location descriptors for the
5257 64bit runtime environment or the ELF32 environment. */
5258 if (TARGET_64BIT || TARGET_ELF32)
5261 for (i = 0; i < 4; i++)
5264 /* Specify explicitly that no argument relocations should take place
5265 if using the portable runtime calling conventions. */
5266 if (TARGET_PORTABLE_RUNTIME)
5268 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5273 if (GET_CODE (call_insn) != CALL_INSN)
5275 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5277 rtx use = XEXP (link, 0);
5279 if (! (GET_CODE (use) == USE
5280 && GET_CODE (XEXP (use, 0)) == REG
5281 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5284 arg_mode = GET_MODE (XEXP (use, 0));
5285 regno = REGNO (XEXP (use, 0));
5286 if (regno >= 23 && regno <= 26)
5288 arg_regs[26 - regno] = "GR";
5289 if (arg_mode == DImode)
5290 arg_regs[25 - regno] = "GR";
5292 else if (regno >= 32 && regno <= 39)
5294 if (arg_mode == SFmode)
5295 arg_regs[(regno - 32) / 2] = "FR";
5298 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5299 arg_regs[(regno - 34) / 2] = "FR";
5300 arg_regs[(regno - 34) / 2 + 1] = "FU";
5302 arg_regs[(regno - 34) / 2] = "FU";
5303 arg_regs[(regno - 34) / 2 + 1] = "FR";
5308 fputs ("\t.CALL ", asm_out_file);
5309 for (i = 0; i < 4; i++)
5314 fputc (',', asm_out_file);
5315 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5318 fputc ('\n', asm_out_file);
5321 /* Return the class of any secondary reload register that is needed to
5322 move IN into a register in class CLASS using mode MODE.
5324 Profiling has showed this routine and its descendants account for
5325 a significant amount of compile time (~7%). So it has been
5326 optimized to reduce redundant computations and eliminate useless
5329 It might be worthwhile to try and make this a leaf function too. */
5332 secondary_reload_class (class, mode, in)
5333 enum reg_class class;
5334 enum machine_mode mode;
5337 int regno, is_symbolic;
5339 /* Trying to load a constant into a FP register during PIC code
5340 generation will require %r1 as a scratch register. */
5342 && GET_MODE_CLASS (mode) == MODE_INT
5343 && FP_REG_CLASS_P (class)
5344 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5347 /* Profiling showed the PA port spends about 1.3% of its compilation
5348 time in true_regnum from calls inside secondary_reload_class. */
5350 if (GET_CODE (in) == REG)
5353 if (regno >= FIRST_PSEUDO_REGISTER)
5354 regno = true_regnum (in);
5356 else if (GET_CODE (in) == SUBREG)
5357 regno = true_regnum (in);
5361 /* If we have something like (mem (mem (...)), we can safely assume the
5362 inner MEM will end up in a general register after reloading, so there's
5363 no need for a secondary reload. */
5364 if (GET_CODE (in) == MEM
5365 && GET_CODE (XEXP (in, 0)) == MEM)
5368 /* Handle out of range displacement for integer mode loads/stores of
5370 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5371 && GET_MODE_CLASS (mode) == MODE_INT
5372 && FP_REG_CLASS_P (class))
5373 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5374 return GENERAL_REGS;
5376 /* A SAR<->FP register copy requires a secondary register (GPR) as
5377 well as secondary memory. */
5378 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5379 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5380 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5381 return GENERAL_REGS;
5383 if (GET_CODE (in) == HIGH)
5386 /* Profiling has showed GCC spends about 2.6% of its compilation
5387 time in symbolic_operand from calls inside secondary_reload_class.
5389 We use an inline copy and only compute its return value once to avoid
5391 switch (GET_CODE (in))
5401 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5402 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5403 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5413 && read_only_operand (in, VOIDmode))
5416 if (class != R1_REGS && is_symbolic)
5423 function_arg_padding (mode, type)
5424 enum machine_mode mode;
5428 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5430 /* Return none if justification is not required. */
5432 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5433 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5436 /* The directions set here are ignored when a BLKmode argument larger
5437 than a word is placed in a register. Different code is used for
5438 the stack and registers. This makes it difficult to have a
5439 consistent data representation for both the stack and registers.
5440 For both runtimes, the justification and padding for arguments on
5441 the stack and in registers should be identical. */
5443 /* The 64-bit runtime specifies left justification for aggregates. */
5446 /* The 32-bit runtime architecture specifies right justification.
5447 When the argument is passed on the stack, the argument is padded
5448 with garbage on the left. The HP compiler pads with zeros. */
5452 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5459 /* Do what is necessary for `va_start'. We look at the current function
5460 to determine if stdargs or varargs is used and fill in an initial
5461 va_list. A pointer to this constructor is returned. */
5464 hppa_builtin_saveregs ()
5467 tree fntype = TREE_TYPE (current_function_decl);
5468 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5469 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5470 != void_type_node)))
5471 ? UNITS_PER_WORD : 0);
5474 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5476 offset = current_function_arg_offset_rtx;
5482 /* Adjust for varargs/stdarg differences. */
5484 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5486 offset = current_function_arg_offset_rtx;
5488 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5489 from the incoming arg pointer and growing to larger addresses. */
5490 for (i = 26, off = -64; i >= 19; i--, off += 8)
5491 emit_move_insn (gen_rtx_MEM (word_mode,
5492 plus_constant (arg_pointer_rtx, off)),
5493 gen_rtx_REG (word_mode, i));
5495 /* The incoming args pointer points just beyond the flushback area;
5496 normally this is not a serious concern. However, when we are doing
5497 varargs/stdargs we want to make the arg pointer point to the start
5498 of the incoming argument area. */
5499 emit_move_insn (virtual_incoming_args_rtx,
5500 plus_constant (arg_pointer_rtx, -64));
5502 /* Now return a pointer to the first anonymous argument. */
5503 return copy_to_reg (expand_binop (Pmode, add_optab,
5504 virtual_incoming_args_rtx,
5505 offset, 0, 0, OPTAB_LIB_WIDEN));
5508 /* Store general registers on the stack. */
5509 dest = gen_rtx_MEM (BLKmode,
5510 plus_constant (current_function_internal_arg_pointer,
5512 set_mem_alias_set (dest, get_varargs_alias_set ());
5513 set_mem_align (dest, BITS_PER_WORD);
5514 move_block_from_reg (23, dest, 4);
5516 /* move_block_from_reg will emit code to store the argument registers
5517 individually as scalar stores.
5519 However, other insns may later load from the same addresses for
5520 a structure load (passing a struct to a varargs routine).
5522 The alias code assumes that such aliasing can never happen, so we
5523 have to keep memory referencing insns from moving up beyond the
5524 last argument register store. So we emit a blockage insn here. */
5525 emit_insn (gen_blockage ());
5527 return copy_to_reg (expand_binop (Pmode, add_optab,
5528 current_function_internal_arg_pointer,
5529 offset, 0, 0, OPTAB_LIB_WIDEN));
5533 hppa_va_start (valist, nextarg)
5537 nextarg = expand_builtin_saveregs ();
5538 std_expand_builtin_va_start (valist, nextarg);
5542 hppa_va_arg (valist, type)
5545 HOST_WIDE_INT size = int_size_in_bytes (type);
5551 /* Every argument in PA64 is supposed to be passed by value
5552 (including large structs). However, as a GCC extension, we
5553 pass zero and variable sized arguments by reference. Empty
5554 structures are a GCC extension not supported by the HP
5555 compilers. Thus, passing them by reference isn't likely
5556 to conflict with the ABI. For variable sized arguments,
5557 GCC doesn't have the infrastructure to allocate these to
5560 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5562 if (size > UNITS_PER_WORD)
5564 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5565 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5566 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5567 build_int_2 (-2 * UNITS_PER_WORD, -1));
5568 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5569 TREE_SIDE_EFFECTS (t) = 1;
5570 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5574 return std_expand_builtin_va_arg (valist, type);
5577 ptr = build_pointer_type (type);
5579 /* Args grow upward. */
5580 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5581 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5582 TREE_SIDE_EFFECTS (t) = 1;
5584 pptr = build_pointer_type (ptr);
5585 t = build1 (NOP_EXPR, pptr, t);
5586 TREE_SIDE_EFFECTS (t) = 1;
5588 t = build1 (INDIRECT_REF, ptr, t);
5589 TREE_SIDE_EFFECTS (t) = 1;
5592 else /* !TARGET_64BIT */
5594 ptr = build_pointer_type (type);
5596 /* "Large" and variable sized types are passed by reference. */
5597 if (size > 8 || size <= 0)
5599 /* Args grow downward. */
5600 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5601 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5602 TREE_SIDE_EFFECTS (t) = 1;
5604 pptr = build_pointer_type (ptr);
5605 t = build1 (NOP_EXPR, pptr, t);
5606 TREE_SIDE_EFFECTS (t) = 1;
5608 t = build1 (INDIRECT_REF, ptr, t);
5609 TREE_SIDE_EFFECTS (t) = 1;
5613 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5614 build_int_2 (-size, -1));
5616 /* Copied from va-pa.h, but we probably don't need to align to
5617 word size, since we generate and preserve that invariant. */
5618 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5619 build_int_2 ((size > 4 ? -8 : -4), -1));
5621 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5622 TREE_SIDE_EFFECTS (t) = 1;
5624 ofs = (8 - size) % 4;
5627 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5628 build_int_2 (ofs, 0));
5629 TREE_SIDE_EFFECTS (t) = 1;
5632 t = build1 (NOP_EXPR, ptr, t);
5633 TREE_SIDE_EFFECTS (t) = 1;
5638 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5643 /* This routine handles all the normal conditional branch sequences we
5644 might need to generate. It handles compare immediate vs compare
5645 register, nullification of delay slots, varying length branches,
5646 negated branches, and all combinations of the above. It returns the
5647 output appropriate to emit the branch corresponding to all given
5651 output_cbranch (operands, nullify, length, negated, insn)
5653 int nullify, length, negated;
5656 static char buf[100];
5660 /* A conditional branch to the following instruction (eg the delay slot)
5661 is asking for a disaster. This can happen when not optimizing and
5662 when jump optimization fails.
5664 While it is usually safe to emit nothing, this can fail if the
5665 preceding instruction is a nullified branch with an empty delay
5666 slot and the same branch target as this branch. We could check
5667 for this but jump optimization should eliminate nop jumps. It
5668 is always safe to emit a nop. */
5669 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5672 /* If this is a long branch with its delay slot unfilled, set `nullify'
5673 as it can nullify the delay slot and save a nop. */
5674 if (length == 8 && dbr_sequence_length () == 0)
5677 /* If this is a short forward conditional branch which did not get
5678 its delay slot filled, the delay slot can still be nullified. */
5679 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5680 nullify = forward_branch_p (insn);
5682 /* A forward branch over a single nullified insn can be done with a
5683 comclr instruction. This avoids a single cycle penalty due to
5684 mis-predicted branch if we fall through (branch not taken). */
5686 && next_real_insn (insn) != 0
5687 && get_attr_length (next_real_insn (insn)) == 4
5688 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5694 /* All short conditional branches except backwards with an unfilled
5698 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5700 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5701 if (GET_MODE (operands[1]) == DImode)
5704 strcat (buf, "%B3");
5706 strcat (buf, "%S3");
5708 strcat (buf, " %2,%r1,%%r0");
5710 strcat (buf, ",n %2,%r1,%0");
5712 strcat (buf, " %2,%r1,%0");
5715 /* All long conditionals. Note a short backward branch with an
5716 unfilled delay slot is treated just like a long backward branch
5717 with an unfilled delay slot. */
5719 /* Handle weird backwards branch with a filled delay slot
5720 with is nullified. */
5721 if (dbr_sequence_length () != 0
5722 && ! forward_branch_p (insn)
5725 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5726 if (GET_MODE (operands[1]) == DImode)
5729 strcat (buf, "%S3");
5731 strcat (buf, "%B3");
5732 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5734 /* Handle short backwards branch with an unfilled delay slot.
5735 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5736 taken and untaken branches. */
5737 else if (dbr_sequence_length () == 0
5738 && ! forward_branch_p (insn)
5739 && INSN_ADDRESSES_SET_P ()
5740 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5741 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5743 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5744 if (GET_MODE (operands[1]) == DImode)
5747 strcat (buf, "%B3 %2,%r1,%0%#");
5749 strcat (buf, "%S3 %2,%r1,%0%#");
5753 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5754 if (GET_MODE (operands[1]) == DImode)
5757 strcat (buf, "%S3");
5759 strcat (buf, "%B3");
5761 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5763 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5769 xoperands[0] = operands[0];
5770 xoperands[1] = operands[1];
5771 xoperands[2] = operands[2];
5772 xoperands[3] = operands[3];
5774 /* The reversed conditional branch must branch over one additional
5775 instruction if the delay slot is filled. If the delay slot
5776 is empty, the instruction after the reversed condition branch
5777 must be nullified. */
5778 nullify = dbr_sequence_length () == 0;
5779 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5781 /* Create a reversed conditional branch which branches around
5782 the following insns. */
5783 if (GET_MODE (operands[1]) != DImode)
5789 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5792 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5798 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5801 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
5810 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
5813 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
5819 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
5822 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
5826 output_asm_insn (buf, xoperands);
5827 return output_lbranch (operands[0], insn);
5835 /* This routine handles long unconditional branches that exceed the
5836 maximum range of a simple branch instruction. */
5839 output_lbranch (dest, insn)
5844 xoperands[0] = dest;
5846 /* First, free up the delay slot. */
5847 if (dbr_sequence_length () != 0)
5849 /* We can't handle a jump in the delay slot. */
5850 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
5853 final_scan_insn (NEXT_INSN (insn), asm_out_file,
5856 /* Now delete the delay insn. */
5857 PUT_CODE (NEXT_INSN (insn), NOTE);
5858 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5859 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5862 /* Output an insn to save %r1. The runtime documentation doesn't
5863 specify whether the "Clean Up" slot in the callers frame can
5864 be clobbered by the callee. It isn't copied by HP's builtin
5865 alloca, so this suggests that it can be clobbered if necessary.
5866 The "Static Link" location is copied by HP builtin alloca, so
5867 we avoid using it. Using the cleanup slot might be a problem
5868 if we have to interoperate with languages that pass cleanup
5869 information. However, it should be possible to handle these
5870 situations with GCC's asm feature.
5872 The "Current RP" slot is reserved for the called procedure, so
5873 we try to use it when we don't have a frame of our own. It's
5874 rather unlikely that we won't have a frame when we need to emit
5877 Really the way to go long term is a register scavenger; goto
5878 the target of the jump and find a register which we can use
5879 as a scratch to hold the value in %r1. Then, we wouldn't have
5880 to free up the delay slot or clobber a slot that may be needed
5881 for other purposes. */
5884 if (actual_fsize == 0 && !regs_ever_live[2])
5885 /* Use the return pointer slot in the frame marker. */
5886 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
5888 /* Use the slot at -40 in the frame marker since HP builtin
5889 alloca doesn't copy it. */
5890 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
5894 if (actual_fsize == 0 && !regs_ever_live[2])
5895 /* Use the return pointer slot in the frame marker. */
5896 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
5898 /* Use the "Clean Up" slot in the frame marker. In GCC,
5899 the only other use of this location is for copying a
5900 floating point double argument from a floating-point
5901 register to two general registers. The copy is done
5902 as an "atomic" operation when outputting a call, so it
5903 won't interfere with our using the location here. */
5904 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
5909 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5910 if (TARGET_SOM || !TARGET_GAS)
5912 xoperands[1] = gen_label_rtx ();
5913 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
5914 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5915 CODE_LABEL_NUMBER (xoperands[1]));
5916 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
5920 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5921 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
5923 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5926 /* Now output a very long branch to the original target. */
5927 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
5929 /* Now restore the value of %r1 in the delay slot. */
5932 if (actual_fsize == 0 && !regs_ever_live[2])
5933 return "ldd -16(%%r30),%%r1";
5935 return "ldd -40(%%r30),%%r1";
5939 if (actual_fsize == 0 && !regs_ever_live[2])
5940 return "ldw -20(%%r30),%%r1";
5942 return "ldw -12(%%r30),%%r1";
5946 /* This routine handles all the branch-on-bit conditional branch sequences we
5947 might need to generate. It handles nullification of delay slots,
5948 varying length branches, negated branches and all combinations of the
5949 above. it returns the appropriate output template to emit the branch. */
5952 output_bb (operands, nullify, length, negated, insn, which)
5953 rtx *operands ATTRIBUTE_UNUSED;
5954 int nullify, length, negated;
5958 static char buf[100];
5961 /* A conditional branch to the following instruction (eg the delay slot) is
5962 asking for a disaster. I do not think this can happen as this pattern
5963 is only used when optimizing; jump optimization should eliminate the
5964 jump. But be prepared just in case. */
5966 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5969 /* If this is a long branch with its delay slot unfilled, set `nullify'
5970 as it can nullify the delay slot and save a nop. */
5971 if (length == 8 && dbr_sequence_length () == 0)
5974 /* If this is a short forward conditional branch which did not get
5975 its delay slot filled, the delay slot can still be nullified. */
5976 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5977 nullify = forward_branch_p (insn);
5979 /* A forward branch over a single nullified insn can be done with a
5980 extrs instruction. This avoids a single cycle penalty due to
5981 mis-predicted branch if we fall through (branch not taken). */
5984 && next_real_insn (insn) != 0
5985 && get_attr_length (next_real_insn (insn)) == 4
5986 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5993 /* All short conditional branches except backwards with an unfilled
5997 strcpy (buf, "{extrs,|extrw,s,}");
5999 strcpy (buf, "bb,");
6000 if (useskip && GET_MODE (operands[0]) == DImode)
6001 strcpy (buf, "extrd,s,*");
6002 else if (GET_MODE (operands[0]) == DImode)
6003 strcpy (buf, "bb,*");
6004 if ((which == 0 && negated)
6005 || (which == 1 && ! negated))
6010 strcat (buf, " %0,%1,1,%%r0");
6011 else if (nullify && negated)
6012 strcat (buf, ",n %0,%1,%3");
6013 else if (nullify && ! negated)
6014 strcat (buf, ",n %0,%1,%2");
6015 else if (! nullify && negated)
6016 strcat (buf, "%0,%1,%3");
6017 else if (! nullify && ! negated)
6018 strcat (buf, " %0,%1,%2");
6021 /* All long conditionals. Note a short backward branch with an
6022 unfilled delay slot is treated just like a long backward branch
6023 with an unfilled delay slot. */
6025 /* Handle weird backwards branch with a filled delay slot
6026 with is nullified. */
6027 if (dbr_sequence_length () != 0
6028 && ! forward_branch_p (insn)
6031 strcpy (buf, "bb,");
6032 if (GET_MODE (operands[0]) == DImode)
6034 if ((which == 0 && negated)
6035 || (which == 1 && ! negated))
6040 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6042 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6044 /* Handle short backwards branch with an unfilled delay slot.
6045 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6046 taken and untaken branches. */
6047 else if (dbr_sequence_length () == 0
6048 && ! forward_branch_p (insn)
6049 && INSN_ADDRESSES_SET_P ()
6050 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6051 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6053 strcpy (buf, "bb,");
6054 if (GET_MODE (operands[0]) == DImode)
6056 if ((which == 0 && negated)
6057 || (which == 1 && ! negated))
6062 strcat (buf, " %0,%1,%3%#");
6064 strcat (buf, " %0,%1,%2%#");
6068 strcpy (buf, "{extrs,|extrw,s,}");
6069 if (GET_MODE (operands[0]) == DImode)
6070 strcpy (buf, "extrd,s,*");
6071 if ((which == 0 && negated)
6072 || (which == 1 && ! negated))
6076 if (nullify && negated)
6077 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6078 else if (nullify && ! negated)
6079 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6081 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6083 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6093 /* This routine handles all the branch-on-variable-bit conditional branch
6094 sequences we might need to generate. It handles nullification of delay
6095 slots, varying length branches, negated branches and all combinations
6096 of the above. it returns the appropriate output template to emit the
6100 output_bvb (operands, nullify, length, negated, insn, which)
6101 rtx *operands ATTRIBUTE_UNUSED;
6102 int nullify, length, negated;
6106 static char buf[100];
6109 /* A conditional branch to the following instruction (eg the delay slot) is
6110 asking for a disaster. I do not think this can happen as this pattern
6111 is only used when optimizing; jump optimization should eliminate the
6112 jump. But be prepared just in case. */
6114 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6117 /* If this is a long branch with its delay slot unfilled, set `nullify'
6118 as it can nullify the delay slot and save a nop. */
6119 if (length == 8 && dbr_sequence_length () == 0)
6122 /* If this is a short forward conditional branch which did not get
6123 its delay slot filled, the delay slot can still be nullified. */
6124 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6125 nullify = forward_branch_p (insn);
6127 /* A forward branch over a single nullified insn can be done with a
6128 extrs instruction. This avoids a single cycle penalty due to
6129 mis-predicted branch if we fall through (branch not taken). */
6132 && next_real_insn (insn) != 0
6133 && get_attr_length (next_real_insn (insn)) == 4
6134 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6141 /* All short conditional branches except backwards with an unfilled
6145 strcpy (buf, "{vextrs,|extrw,s,}");
6147 strcpy (buf, "{bvb,|bb,}");
6148 if (useskip && GET_MODE (operands[0]) == DImode)
6149 strcpy (buf, "extrd,s,*}");
6150 else if (GET_MODE (operands[0]) == DImode)
6151 strcpy (buf, "bb,*");
6152 if ((which == 0 && negated)
6153 || (which == 1 && ! negated))
6158 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6159 else if (nullify && negated)
6160 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6161 else if (nullify && ! negated)
6162 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6163 else if (! nullify && negated)
6164 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6165 else if (! nullify && ! negated)
6166 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6169 /* All long conditionals. Note a short backward branch with an
6170 unfilled delay slot is treated just like a long backward branch
6171 with an unfilled delay slot. */
6173 /* Handle weird backwards branch with a filled delay slot
6174 with is nullified. */
6175 if (dbr_sequence_length () != 0
6176 && ! forward_branch_p (insn)
6179 strcpy (buf, "{bvb,|bb,}");
6180 if (GET_MODE (operands[0]) == DImode)
6182 if ((which == 0 && negated)
6183 || (which == 1 && ! negated))
6188 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6190 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6192 /* Handle short backwards branch with an unfilled delay slot.
6193 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6194 taken and untaken branches. */
6195 else if (dbr_sequence_length () == 0
6196 && ! forward_branch_p (insn)
6197 && INSN_ADDRESSES_SET_P ()
6198 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6199 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6201 strcpy (buf, "{bvb,|bb,}");
6202 if (GET_MODE (operands[0]) == DImode)
6204 if ((which == 0 && negated)
6205 || (which == 1 && ! negated))
6210 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6212 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6216 strcpy (buf, "{vextrs,|extrw,s,}");
6217 if (GET_MODE (operands[0]) == DImode)
6218 strcpy (buf, "extrd,s,*");
6219 if ((which == 0 && negated)
6220 || (which == 1 && ! negated))
6224 if (nullify && negated)
6225 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6226 else if (nullify && ! negated)
6227 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6229 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6231 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6241 /* Return the output template for emitting a dbra type insn.
6243 Note it may perform some output operations on its own before
6244 returning the final output string. */
6246 output_dbra (operands, insn, which_alternative)
6249 int which_alternative;
6252 /* A conditional branch to the following instruction (eg the delay slot) is
6253 asking for a disaster. Be prepared! */
6255 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6257 if (which_alternative == 0)
6258 return "ldo %1(%0),%0";
6259 else if (which_alternative == 1)
6261 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6262 output_asm_insn ("ldw -16(%%r30),%4", operands);
6263 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6264 return "{fldws|fldw} -16(%%r30),%0";
6268 output_asm_insn ("ldw %0,%4", operands);
6269 return "ldo %1(%4),%4\n\tstw %4,%0";
6273 if (which_alternative == 0)
6275 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6276 int length = get_attr_length (insn);
6278 /* If this is a long branch with its delay slot unfilled, set `nullify'
6279 as it can nullify the delay slot and save a nop. */
6280 if (length == 8 && dbr_sequence_length () == 0)
6283 /* If this is a short forward conditional branch which did not get
6284 its delay slot filled, the delay slot can still be nullified. */
6285 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6286 nullify = forward_branch_p (insn);
6288 /* Handle short versions first. */
6289 if (length == 4 && nullify)
6290 return "addib,%C2,n %1,%0,%3";
6291 else if (length == 4 && ! nullify)
6292 return "addib,%C2 %1,%0,%3";
6293 else if (length == 8)
6295 /* Handle weird backwards branch with a fulled delay slot
6296 which is nullified. */
6297 if (dbr_sequence_length () != 0
6298 && ! forward_branch_p (insn)
6300 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6301 /* Handle short backwards branch with an unfilled delay slot.
6302 Using a addb;nop rather than addi;bl saves 1 cycle for both
6303 taken and untaken branches. */
6304 else if (dbr_sequence_length () == 0
6305 && ! forward_branch_p (insn)
6306 && INSN_ADDRESSES_SET_P ()
6307 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6308 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6309 return "addib,%C2 %1,%0,%3%#";
6311 /* Handle normal cases. */
6313 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6315 return "addi,%N2 %1,%0,%0\n\tb %3";
6320 /* Deal with gross reload from FP register case. */
6321 else if (which_alternative == 1)
6323 /* Move loop counter from FP register to MEM then into a GR,
6324 increment the GR, store the GR into MEM, and finally reload
6325 the FP register from MEM from within the branch's delay slot. */
6326 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6328 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6329 if (get_attr_length (insn) == 24)
6330 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6332 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6334 /* Deal with gross reload from memory case. */
6337 /* Reload loop counter from memory, the store back to memory
6338 happens in the branch's delay slot. */
6339 output_asm_insn ("ldw %0,%4", operands);
6340 if (get_attr_length (insn) == 12)
6341 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6343 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6347 /* Return the output template for emitting a dbra type insn.
6349 Note it may perform some output operations on its own before
6350 returning the final output string. */
6352 output_movb (operands, insn, which_alternative, reverse_comparison)
6355 int which_alternative;
6356 int reverse_comparison;
6359 /* A conditional branch to the following instruction (eg the delay slot) is
6360 asking for a disaster. Be prepared! */
6362 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6364 if (which_alternative == 0)
6365 return "copy %1,%0";
6366 else if (which_alternative == 1)
6368 output_asm_insn ("stw %1,-16(%%r30)", operands);
6369 return "{fldws|fldw} -16(%%r30),%0";
6371 else if (which_alternative == 2)
6377 /* Support the second variant. */
6378 if (reverse_comparison)
6379 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6381 if (which_alternative == 0)
6383 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6384 int length = get_attr_length (insn);
6386 /* If this is a long branch with its delay slot unfilled, set `nullify'
6387 as it can nullify the delay slot and save a nop. */
6388 if (length == 8 && dbr_sequence_length () == 0)
6391 /* If this is a short forward conditional branch which did not get
6392 its delay slot filled, the delay slot can still be nullified. */
6393 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6394 nullify = forward_branch_p (insn);
6396 /* Handle short versions first. */
6397 if (length == 4 && nullify)
6398 return "movb,%C2,n %1,%0,%3";
6399 else if (length == 4 && ! nullify)
6400 return "movb,%C2 %1,%0,%3";
6401 else if (length == 8)
6403 /* Handle weird backwards branch with a filled delay slot
6404 which is nullified. */
6405 if (dbr_sequence_length () != 0
6406 && ! forward_branch_p (insn)
6408 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6410 /* Handle short backwards branch with an unfilled delay slot.
6411 Using a movb;nop rather than or;bl saves 1 cycle for both
6412 taken and untaken branches. */
6413 else if (dbr_sequence_length () == 0
6414 && ! forward_branch_p (insn)
6415 && INSN_ADDRESSES_SET_P ()
6416 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6417 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6418 return "movb,%C2 %1,%0,%3%#";
6419 /* Handle normal cases. */
6421 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6423 return "or,%N2 %1,%%r0,%0\n\tb %3";
6428 /* Deal with gross reload from FP register case. */
6429 else if (which_alternative == 1)
6431 /* Move loop counter from FP register to MEM then into a GR,
6432 increment the GR, store the GR into MEM, and finally reload
6433 the FP register from MEM from within the branch's delay slot. */
6434 output_asm_insn ("stw %1,-16(%%r30)", operands);
6435 if (get_attr_length (insn) == 12)
6436 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6438 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6440 /* Deal with gross reload from memory case. */
6441 else if (which_alternative == 2)
6443 /* Reload loop counter from memory, the store back to memory
6444 happens in the branch's delay slot. */
6445 if (get_attr_length (insn) == 8)
6446 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6448 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6450 /* Handle SAR as a destination. */
6453 if (get_attr_length (insn) == 8)
6454 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6456 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6460 /* Copy any FP arguments in INSN into integer registers. */
6468 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6470 int arg_mode, regno;
6471 rtx use = XEXP (link, 0);
6473 if (! (GET_CODE (use) == USE
6474 && GET_CODE (XEXP (use, 0)) == REG
6475 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6478 arg_mode = GET_MODE (XEXP (use, 0));
6479 regno = REGNO (XEXP (use, 0));
6481 /* Is it a floating point register? */
6482 if (regno >= 32 && regno <= 39)
6484 /* Copy the FP register into an integer register via memory. */
6485 if (arg_mode == SFmode)
6487 xoperands[0] = XEXP (use, 0);
6488 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6489 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6490 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6494 xoperands[0] = XEXP (use, 0);
6495 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6496 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6497 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6498 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6504 /* Compute length of the FP argument copy sequence for INSN. */
6506 length_fp_args (insn)
6512 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6514 int arg_mode, regno;
6515 rtx use = XEXP (link, 0);
6517 if (! (GET_CODE (use) == USE
6518 && GET_CODE (XEXP (use, 0)) == REG
6519 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6522 arg_mode = GET_MODE (XEXP (use, 0));
6523 regno = REGNO (XEXP (use, 0));
6525 /* Is it a floating point register? */
6526 if (regno >= 32 && regno <= 39)
6528 if (arg_mode == SFmode)
6538 /* Return the attribute length for the millicode call instruction INSN.
6539 The length must match the code generated by output_millicode_call.
6540 We include the delay slot in the returned length as it is better to
6541 over estimate the length than to under estimate it. */
6544 attr_length_millicode_call (insn)
6547 unsigned long distance = -1;
6549 if (INSN_ADDRESSES_SET_P ())
6551 distance = (total_code_bytes + insn_current_reference_address (insn));
6552 if (distance < total_code_bytes)
6558 if (!TARGET_LONG_CALLS && distance < 7600000)
6563 else if (TARGET_PORTABLE_RUNTIME)
6567 if (!TARGET_LONG_CALLS && distance < 240000)
6570 if (TARGET_LONG_ABS_CALL && !flag_pic)
6577 /* INSN is a function call. It may have an unconditional jump
6580 CALL_DEST is the routine we are calling. */
6583 output_millicode_call (insn, call_dest)
6587 int attr_length = get_attr_length (insn);
6588 int seq_length = dbr_sequence_length ();
6593 xoperands[0] = call_dest;
6594 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6596 /* Handle the common case where we are sure that the branch will
6597 reach the beginning of the $CODE$ subspace. The within reach
6598 form of the $$sh_func_adrs call has a length of 28. Because
6599 it has an attribute type of multi, it never has a nonzero
6600 sequence length. The length of the $$sh_func_adrs is the same
6601 as certain out of reach PIC calls to other routines. */
6602 if (!TARGET_LONG_CALLS
6603 && ((seq_length == 0
6604 && (attr_length == 12
6605 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6606 || (seq_length != 0 && attr_length == 8)))
6608 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6614 /* It might seem that one insn could be saved by accessing
6615 the millicode function using the linkage table. However,
6616 this doesn't work in shared libraries and other dynamically
6617 loaded objects. Using a pc-relative sequence also avoids
6618 problems related to the implicit use of the gp register. */
6619 output_asm_insn ("b,l .+8,%%r1", xoperands);
6623 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6624 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6628 xoperands[1] = gen_label_rtx ();
6629 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6630 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6631 CODE_LABEL_NUMBER (xoperands[1]));
6632 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6635 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6637 else if (TARGET_PORTABLE_RUNTIME)
6639 /* Pure portable runtime doesn't allow be/ble; we also don't
6640 have PIC support in the assembler/linker, so this sequence
6643 /* Get the address of our target into %r1. */
6644 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6645 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6647 /* Get our return address into %r31. */
6648 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6649 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6651 /* Jump to our target address in %r1. */
6652 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6656 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6658 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6660 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6664 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6665 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6667 if (TARGET_SOM || !TARGET_GAS)
6669 /* The HP assembler can generate relocations for the
6670 difference of two symbols. GAS can do this for a
6671 millicode symbol but not an arbitrary external
6672 symbol when generating SOM output. */
6673 xoperands[1] = gen_label_rtx ();
6674 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6675 CODE_LABEL_NUMBER (xoperands[1]));
6676 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6677 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6681 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6682 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6686 /* Jump to our target address in %r1. */
6687 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6691 if (seq_length == 0)
6692 output_asm_insn ("nop", xoperands);
6694 /* We are done if there isn't a jump in the delay slot. */
6695 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6698 /* This call has an unconditional jump in its delay slot. */
6699 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6701 /* See if the return address can be adjusted. Use the containing
6702 sequence insn's address. */
6703 if (INSN_ADDRESSES_SET_P ())
6705 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6706 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6707 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6709 if (VAL_14_BITS_P (distance))
6711 xoperands[1] = gen_label_rtx ();
6712 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6713 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6714 CODE_LABEL_NUMBER (xoperands[1]));
6717 /* ??? This branch may not reach its target. */
6718 output_asm_insn ("nop\n\tb,n %0", xoperands);
6721 /* ??? This branch may not reach its target. */
6722 output_asm_insn ("nop\n\tb,n %0", xoperands);
6724 /* Delete the jump. */
6725 PUT_CODE (NEXT_INSN (insn), NOTE);
6726 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6727 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6732 /* Return the attribute length of the call instruction INSN. The SIBCALL
6733 flag indicates whether INSN is a regular call or a sibling call. The
6734 length must match the code generated by output_call. We include the delay
6735 slot in the returned length as it is better to over estimate the length
6736 than to under estimate it. */
6739 attr_length_call (insn, sibcall)
6743 unsigned long distance = -1;
6745 if (INSN_ADDRESSES_SET_P ())
6747 distance = (total_code_bytes + insn_current_reference_address (insn));
6748 if (distance < total_code_bytes)
6754 if (!TARGET_LONG_CALLS
6755 && ((!sibcall && distance < 7600000) || distance < 240000))
6758 return (sibcall ? 28 : 24);
6762 if (!TARGET_LONG_CALLS
6763 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6764 || distance < 240000))
6767 if (TARGET_LONG_ABS_CALL && !flag_pic)
6770 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6771 || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6783 length += length_fp_args (insn);
6789 return (length + 32);
6791 if (!TARGET_NO_SPACE_REGS)
6797 return (length + 32);
6802 /* INSN is a function call. It may have an unconditional jump
6805 CALL_DEST is the routine we are calling. */
6808 output_call (insn, call_dest, sibcall)
6813 int delay_insn_deleted = 0;
6814 int delay_slot_filled = 0;
6815 int seq_length = dbr_sequence_length ();
6818 xoperands[0] = call_dest;
6820 /* Handle the common case where we're sure that the branch will reach
6821 the beginning of the $CODE$ subspace. */
6822 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
6824 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6825 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
6831 /* ??? As far as I can tell, the HP linker doesn't support the
6832 long pc-relative sequence described in the 64-bit runtime
6833 architecture. So, we use a slightly longer indirect call. */
6834 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6836 xoperands[0] = p->internal_label;
6837 xoperands[1] = gen_label_rtx ();
6839 /* If this isn't a sibcall, we put the load of %r27 into the
6840 delay slot. We can't do this in a sibcall as we don't
6841 have a second call-clobbered scratch register available. */
6843 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6846 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6849 /* Now delete the delay insn. */
6850 PUT_CODE (NEXT_INSN (insn), NOTE);
6851 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6852 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6853 delay_insn_deleted = 1;
6856 output_asm_insn ("addil LT'%0,%%r27", xoperands);
6857 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
6858 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
6862 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6863 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
6864 output_asm_insn ("bve (%%r1)", xoperands);
6868 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
6869 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
6870 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6871 delay_slot_filled = 1;
6876 int indirect_call = 0;
6878 /* Emit a long call. There are several different sequences
6879 of increasing length and complexity. In most cases,
6880 they don't allow an instruction in the delay slot. */
6881 if (!(TARGET_LONG_ABS_CALL && !flag_pic)
6882 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6883 && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6887 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6889 && (!TARGET_PA_20 || indirect_call))
6891 /* A non-jump insn in the delay slot. By definition we can
6892 emit this insn before the call (and in fact before argument
6894 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6896 /* Now delete the delay insn. */
6897 PUT_CODE (NEXT_INSN (insn), NOTE);
6898 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6899 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6900 delay_insn_deleted = 1;
6903 if (TARGET_LONG_ABS_CALL && !flag_pic)
6905 /* This is the best sequence for making long calls in
6906 non-pic code. Unfortunately, GNU ld doesn't provide
6907 the stub needed for external calls, and GAS's support
6908 for this with the SOM linker is buggy. */
6909 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6911 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
6915 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
6918 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6920 output_asm_insn ("copy %%r31,%%r2", xoperands);
6921 delay_slot_filled = 1;
6926 if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6928 /* The HP assembler and linker can handle relocations
6929 for the difference of two symbols. GAS and the HP
6930 linker can't do this when one of the symbols is
6932 xoperands[1] = gen_label_rtx ();
6933 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6934 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6935 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6936 CODE_LABEL_NUMBER (xoperands[1]));
6937 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6939 else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)
6941 /* GAS currently can't generate the relocations that
6942 are needed for the SOM linker under HP-UX using this
6943 sequence. The GNU linker doesn't generate the stubs
6944 that are needed for external calls on TARGET_ELF32
6945 with this sequence. For now, we have to use a
6946 longer plabel sequence when using GAS. */
6947 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6948 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
6950 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
6955 /* Emit a long plabel-based call sequence. This is
6956 essentially an inline implementation of $$dyncall.
6957 We don't actually try to call $$dyncall as this is
6958 as difficult as calling the function itself. */
6959 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6961 xoperands[0] = p->internal_label;
6962 xoperands[1] = gen_label_rtx ();
6964 /* Since the call is indirect, FP arguments in registers
6965 need to be copied to the general registers. Then, the
6966 argument relocation stub will copy them back. */
6968 copy_fp_args (insn);
6972 output_asm_insn ("addil LT'%0,%%r19", xoperands);
6973 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
6974 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
6978 output_asm_insn ("addil LR'%0-$global$,%%r27",
6980 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
6984 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
6985 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
6986 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
6987 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
6989 if (!sibcall && !TARGET_PA_20)
6991 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
6992 if (TARGET_NO_SPACE_REGS)
6993 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
6995 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7002 output_asm_insn ("bve (%%r1)", xoperands);
7007 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7008 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7009 delay_slot_filled = 1;
7012 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7017 if (!TARGET_NO_SPACE_REGS)
7018 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7023 if (TARGET_NO_SPACE_REGS)
7024 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7026 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7030 if (TARGET_NO_SPACE_REGS)
7031 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7033 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7036 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7038 output_asm_insn ("copy %%r31,%%r2", xoperands);
7039 delay_slot_filled = 1;
7046 if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
7047 output_asm_insn ("nop", xoperands);
7049 /* We are done if there isn't a jump in the delay slot. */
7051 || delay_insn_deleted
7052 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7055 /* A sibcall should never have a branch in the delay slot. */
7059 /* This call has an unconditional jump in its delay slot. */
7060 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7062 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7064 /* See if the return address can be adjusted. Use the containing
7065 sequence insn's address. */
7066 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7067 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7068 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7070 if (VAL_14_BITS_P (distance))
7072 xoperands[1] = gen_label_rtx ();
7073 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7074 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7075 CODE_LABEL_NUMBER (xoperands[1]));
7078 /* ??? This branch may not reach its target. */
7079 output_asm_insn ("nop\n\tb,n %0", xoperands);
7082 /* ??? This branch may not reach its target. */
7083 output_asm_insn ("b,n %0", xoperands);
7085 /* Delete the jump. */
7086 PUT_CODE (NEXT_INSN (insn), NOTE);
7087 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7088 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7093 /* Return the attribute length of the indirect call instruction INSN.
7094 The length must match the code generated by output_indirect call.
7095 The returned length includes the delay slot. Currently, the delay
7096 slot of an indirect call sequence is not exposed and it is used by
7097 the sequence itself. */
7100 attr_length_indirect_call (insn)
7103 unsigned long distance = -1;
7105 if (INSN_ADDRESSES_SET_P ())
7107 distance = (total_code_bytes + insn_current_reference_address (insn));
7108 if (distance < total_code_bytes)
7115 if (TARGET_FAST_INDIRECT_CALLS
7116 || (!TARGET_PORTABLE_RUNTIME
7117 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7123 if (TARGET_PORTABLE_RUNTIME)
7126 /* Out of reach, can use ble. */
7131 output_indirect_call (insn, call_dest)
7139 xoperands[0] = call_dest;
7140 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7141 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7145 /* First the special case for kernels, level 0 systems, etc. */
7146 if (TARGET_FAST_INDIRECT_CALLS)
7147 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7149 /* Now the normal case -- we can reach $$dyncall directly or
7150 we're sure that we can get there via a long-branch stub.
7152 No need to check target flags as the length uniquely identifies
7153 the remaining cases. */
7154 if (attr_length_indirect_call (insn) == 8)
7155 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7157 /* Long millicode call, but we are not generating PIC or portable runtime
7159 if (attr_length_indirect_call (insn) == 12)
7160 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7162 /* Long millicode call for portable runtime. */
7163 if (attr_length_indirect_call (insn) == 20)
7164 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7166 /* We need a long PIC call to $$dyncall. */
7167 xoperands[0] = NULL_RTX;
7168 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7169 if (TARGET_SOM || !TARGET_GAS)
7171 xoperands[0] = gen_label_rtx ();
7172 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7173 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7174 CODE_LABEL_NUMBER (xoperands[0]));
7175 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7179 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7180 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7183 output_asm_insn ("blr %%r0,%%r2", xoperands);
7184 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7188 /* Return the total length of the save and restore instructions needed for
7189 the data linkage table pointer (i.e., the PIC register) across the call
7190 instruction INSN. No-return calls do not require a save and restore.
7191 In addition, we may be able to avoid the save and restore for calls
7192 within the same translation unit. */
7195 attr_length_save_restore_dltp (insn)
7198 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7204 /* In HPUX 8.0's shared library scheme, special relocations are needed
7205 for function labels if they might be passed to a function
7206 in a shared library (because shared libraries don't live in code
7207 space), and special magic is needed to construct their address. */
7210 hppa_encode_label (sym)
7213 const char *str = XSTR (sym, 0);
7214 int len = strlen (str) + 1;
7217 p = newstr = alloca (len + 1);
7221 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7225 pa_encode_section_info (decl, rtl, first)
7230 if (first && TEXT_SPACE_P (decl))
7232 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7233 if (TREE_CODE (decl) == FUNCTION_DECL)
7234 hppa_encode_label (XEXP (rtl, 0));
7238 /* This is sort of inverse to pa_encode_section_info. */
7241 pa_strip_name_encoding (str)
7244 str += (*str == '@');
7245 str += (*str == '*');
7250 function_label_operand (op, mode)
7252 enum machine_mode mode ATTRIBUTE_UNUSED;
7254 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7257 /* Returns 1 if OP is a function label involved in a simple addition
7258 with a constant. Used to keep certain patterns from matching
7259 during instruction combination. */
7261 is_function_label_plus_const (op)
7264 /* Strip off any CONST. */
7265 if (GET_CODE (op) == CONST)
7268 return (GET_CODE (op) == PLUS
7269 && function_label_operand (XEXP (op, 0), Pmode)
7270 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7273 /* Output assembly code for a thunk to FUNCTION. */
7276 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
7279 HOST_WIDE_INT delta;
7280 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
7283 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
7284 static unsigned int current_thunk_number;
7287 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7288 lab = (*targetm.strip_name_encoding) (label);
7289 target_name = (*targetm.strip_name_encoding) (target_name);
7290 /* FIXME: total_code_bytes is not handled correctly in files with
7292 pa_output_function_prologue (file, 0);
7293 if (VAL_14_BITS_P (delta))
7295 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7297 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7298 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7299 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7300 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7301 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7302 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7303 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7304 if (TARGET_NO_SPACE_REGS)
7305 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7308 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7309 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7310 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7312 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7315 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7317 target_name, delta);
7321 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7323 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7324 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n",
7326 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7327 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7328 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7329 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7330 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7331 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7332 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7333 if (TARGET_NO_SPACE_REGS)
7334 fprintf (file, "\tbe 0(%%sr4,%%r22)");
7337 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7338 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7339 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
7343 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7344 ",%%r26\n\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7345 "(%%r1),%%r26\n", delta, target_name, delta);
7348 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7349 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
7352 fprintf (file, "\t.align 4\n");
7353 (*targetm.asm_out.internal_label) (file, "LTHN", current_thunk_number);
7354 fprintf (file, "\t.word P'%s\n", target_name);
7355 function_section (thunk_fndecl);
7357 current_thunk_number++;
7360 /* Only direct calls to static functions are allowed to be sibling (tail)
7363 This restriction is necessary because some linker generated stubs will
7364 store return pointers into rp' in some cases which might clobber a
7365 live value already in rp'.
7367 In a sibcall the current function and the target function share stack
7368 space. Thus if the path to the current function and the path to the
7369 target function save a value in rp', they save the value into the
7370 same stack slot, which has undesirable consequences.
7372 Because of the deferred binding nature of shared libraries any function
7373 with external scope could be in a different load module and thus require
7374 rp' to be saved when calling that function. So sibcall optimizations
7375 can only be safe for static function.
7377 Note that GCC never needs return value relocations, so we don't have to
7378 worry about static calls with return value relocations (which require
7381 It is safe to perform a sibcall optimization when the target function
7382 will never return. */
7384 pa_function_ok_for_sibcall (decl, exp)
7386 tree exp ATTRIBUTE_UNUSED;
7388 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7389 single subspace mode and the call is not indirect. As far as I know,
7390 there is no operating system support for the multiple subspace mode.
7391 It might be possible to support indirect calls if we didn't use
7392 $$dyncall (see the indirect sequence generated in output_call). */
7394 return (decl != NULL_TREE);
7396 /* Sibcalls are not ok because the arg pointer register is not a fixed
7397 register. This prevents the sibcall optimization from occuring. In
7398 addition, there are problems with stub placement using GNU ld. This
7399 is because a normal sibcall branch uses a 17-bit relocation while
7400 a regular call branch uses a 22-bit relocation. As a result, more
7401 care needs to be taken in the placement of long-branch stubs. */
7406 && !TARGET_PORTABLE_RUNTIME
7407 && !TREE_PUBLIC (decl));
7410 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7411 use in fmpyadd instructions. */
7413 fmpyaddoperands (operands)
7416 enum machine_mode mode = GET_MODE (operands[0]);
7418 /* Must be a floating point mode. */
7419 if (mode != SFmode && mode != DFmode)
7422 /* All modes must be the same. */
7423 if (! (mode == GET_MODE (operands[1])
7424 && mode == GET_MODE (operands[2])
7425 && mode == GET_MODE (operands[3])
7426 && mode == GET_MODE (operands[4])
7427 && mode == GET_MODE (operands[5])))
7430 /* All operands must be registers. */
7431 if (! (GET_CODE (operands[1]) == REG
7432 && GET_CODE (operands[2]) == REG
7433 && GET_CODE (operands[3]) == REG
7434 && GET_CODE (operands[4]) == REG
7435 && GET_CODE (operands[5]) == REG))
7438 /* Only 2 real operands to the addition. One of the input operands must
7439 be the same as the output operand. */
7440 if (! rtx_equal_p (operands[3], operands[4])
7441 && ! rtx_equal_p (operands[3], operands[5]))
7444 /* Inout operand of add can not conflict with any operands from multiply. */
7445 if (rtx_equal_p (operands[3], operands[0])
7446 || rtx_equal_p (operands[3], operands[1])
7447 || rtx_equal_p (operands[3], operands[2]))
7450 /* multiply can not feed into addition operands. */
7451 if (rtx_equal_p (operands[4], operands[0])
7452 || rtx_equal_p (operands[5], operands[0]))
7455 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7457 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7458 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7459 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7460 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7461 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7462 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7465 /* Passed. Operands are suitable for fmpyadd. */
7469 #if !defined(USE_COLLECT2)
7471 pa_asm_out_constructor (symbol, priority)
7475 if (!function_label_operand (symbol, VOIDmode))
7476 hppa_encode_label (symbol);
7478 #ifdef CTORS_SECTION_ASM_OP
7479 default_ctor_section_asm_out_constructor (symbol, priority);
7481 # ifdef TARGET_ASM_NAMED_SECTION
7482 default_named_section_asm_out_constructor (symbol, priority);
7484 default_stabs_asm_out_constructor (symbol, priority);
7490 pa_asm_out_destructor (symbol, priority)
7494 if (!function_label_operand (symbol, VOIDmode))
7495 hppa_encode_label (symbol);
7497 #ifdef DTORS_SECTION_ASM_OP
7498 default_dtor_section_asm_out_destructor (symbol, priority);
7500 # ifdef TARGET_ASM_NAMED_SECTION
7501 default_named_section_asm_out_destructor (symbol, priority);
7503 default_stabs_asm_out_destructor (symbol, priority);
7509 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7510 use in fmpysub instructions. */
7512 fmpysuboperands (operands)
7515 enum machine_mode mode = GET_MODE (operands[0]);
7517 /* Must be a floating point mode. */
7518 if (mode != SFmode && mode != DFmode)
7521 /* All modes must be the same. */
7522 if (! (mode == GET_MODE (operands[1])
7523 && mode == GET_MODE (operands[2])
7524 && mode == GET_MODE (operands[3])
7525 && mode == GET_MODE (operands[4])
7526 && mode == GET_MODE (operands[5])))
7529 /* All operands must be registers. */
7530 if (! (GET_CODE (operands[1]) == REG
7531 && GET_CODE (operands[2]) == REG
7532 && GET_CODE (operands[3]) == REG
7533 && GET_CODE (operands[4]) == REG
7534 && GET_CODE (operands[5]) == REG))
7537 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7538 operation, so operands[4] must be the same as operand[3]. */
7539 if (! rtx_equal_p (operands[3], operands[4]))
7542 /* multiply can not feed into subtraction. */
7543 if (rtx_equal_p (operands[5], operands[0]))
7546 /* Inout operand of sub can not conflict with any operands from multiply. */
7547 if (rtx_equal_p (operands[3], operands[0])
7548 || rtx_equal_p (operands[3], operands[1])
7549 || rtx_equal_p (operands[3], operands[2]))
7552 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7554 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7555 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7556 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7557 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7558 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7559 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7562 /* Passed. Operands are suitable for fmpysub. */
7567 plus_xor_ior_operator (op, mode)
7569 enum machine_mode mode ATTRIBUTE_UNUSED;
7571 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
7572 || GET_CODE (op) == IOR);
7575 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7576 constants for shadd instructions. */
7578 shadd_constant_p (val)
7581 if (val == 2 || val == 4 || val == 8)
7587 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
7588 the valid constant for shadd instructions. */
7590 shadd_operand (op, mode)
7592 enum machine_mode mode ATTRIBUTE_UNUSED;
7594 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
7597 /* Return 1 if OP is valid as a base register in a reg + reg address. */
7600 basereg_operand (op, mode)
7602 enum machine_mode mode;
7604 /* cse will create some unscaled indexed addresses, however; it
7605 generally isn't a win on the PA, so avoid creating unscaled
7606 indexed addresses until after cse is finished. */
7607 if (!cse_not_expected)
7610 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
7611 we don't have to worry about the braindamaged implicit space
7612 register selection from the basereg. */
7613 if (TARGET_NO_SPACE_REGS)
7614 return (GET_CODE (op) == REG);
7616 /* While it's always safe to index off the frame pointer, it's not
7617 always profitable, particularly when the frame pointer is being
7619 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
7622 return (GET_CODE (op) == REG
7624 && register_operand (op, mode));
7627 /* Return 1 if this operand is anything other than a hard register. */
7630 non_hard_reg_operand (op, mode)
7632 enum machine_mode mode ATTRIBUTE_UNUSED;
7634 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
7637 /* Return 1 if INSN branches forward. Should be using insn_addresses
7638 to avoid walking through all the insns... */
7640 forward_branch_p (insn)
7643 rtx label = JUMP_LABEL (insn);
7650 insn = NEXT_INSN (insn);
7653 return (insn == label);
7656 /* Return 1 if OP is an equality comparison, else return 0. */
7658 eq_neq_comparison_operator (op, mode)
7660 enum machine_mode mode ATTRIBUTE_UNUSED;
7662 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
7665 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
7667 movb_comparison_operator (op, mode)
7669 enum machine_mode mode ATTRIBUTE_UNUSED;
7671 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
7672 || GET_CODE (op) == LT || GET_CODE (op) == GE);
7675 /* Return 1 if INSN is in the delay slot of a call instruction. */
7677 jump_in_call_delay (insn)
7681 if (GET_CODE (insn) != JUMP_INSN)
7684 if (PREV_INSN (insn)
7685 && PREV_INSN (PREV_INSN (insn))
7686 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
7688 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
7690 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
7691 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
7698 /* Output an unconditional move and branch insn. */
7701 output_parallel_movb (operands, length)
7705 /* These are the cases in which we win. */
7707 return "mov%I1b,tr %1,%0,%2";
7709 /* None of these cases wins, but they don't lose either. */
7710 if (dbr_sequence_length () == 0)
7712 /* Nothing in the delay slot, fake it by putting the combined
7713 insn (the copy or add) in the delay slot of a bl. */
7714 if (GET_CODE (operands[1]) == CONST_INT)
7715 return "b %2\n\tldi %1,%0";
7717 return "b %2\n\tcopy %1,%0";
7721 /* Something in the delay slot, but we've got a long branch. */
7722 if (GET_CODE (operands[1]) == CONST_INT)
7723 return "ldi %1,%0\n\tb %2";
7725 return "copy %1,%0\n\tb %2";
7729 /* Output an unconditional add and branch insn. */
7732 output_parallel_addb (operands, length)
7736 /* To make life easy we want operand0 to be the shared input/output
7737 operand and operand1 to be the readonly operand. */
7738 if (operands[0] == operands[1])
7739 operands[1] = operands[2];
7741 /* These are the cases in which we win. */
7743 return "add%I1b,tr %1,%0,%3";
7745 /* None of these cases win, but they don't lose either. */
7746 if (dbr_sequence_length () == 0)
7748 /* Nothing in the delay slot, fake it by putting the combined
7749 insn (the copy or add) in the delay slot of a bl. */
7750 return "b %3\n\tadd%I1 %1,%0,%0";
7754 /* Something in the delay slot, but we've got a long branch. */
7755 return "add%I1 %1,%0,%0\n\tb %3";
7759 /* Return nonzero if INSN (a jump insn) immediately follows a call
7760 to a named function. This is used to avoid filling the delay slot
7761 of the jump since it can usually be eliminated by modifying RP in
7762 the delay slot of the call. */
7765 following_call (insn)
7768 if (! TARGET_JUMP_IN_DELAY)
7771 /* Find the previous real insn, skipping NOTEs. */
7772 insn = PREV_INSN (insn);
7773 while (insn && GET_CODE (insn) == NOTE)
7774 insn = PREV_INSN (insn);
7776 /* Check for CALL_INSNs and millicode calls. */
7778 && ((GET_CODE (insn) == CALL_INSN
7779 && get_attr_type (insn) != TYPE_DYNCALL)
7780 || (GET_CODE (insn) == INSN
7781 && GET_CODE (PATTERN (insn)) != SEQUENCE
7782 && GET_CODE (PATTERN (insn)) != USE
7783 && GET_CODE (PATTERN (insn)) != CLOBBER
7784 && get_attr_type (insn) == TYPE_MILLI)))
7790 /* We use this hook to perform a PA specific optimization which is difficult
7791 to do in earlier passes.
7793 We want the delay slots of branches within jump tables to be filled.
7794 None of the compiler passes at the moment even has the notion that a
7795 PA jump table doesn't contain addresses, but instead contains actual
7798 Because we actually jump into the table, the addresses of each entry
7799 must stay constant in relation to the beginning of the table (which
7800 itself must stay constant relative to the instruction to jump into
7801 it). I don't believe we can guarantee earlier passes of the compiler
7802 will adhere to those rules.
7804 So, late in the compilation process we find all the jump tables, and
7805 expand them into real code -- eg each entry in the jump table vector
7806 will get an appropriate label followed by a jump to the final target.
7808 Reorg and the final jump pass can then optimize these branches and
7809 fill their delay slots. We end up with smaller, more efficient code.
7811 The jump instructions within the table are special; we must be able
7812 to identify them during assembly output (if the jumps don't get filled
7813 we need to emit a nop rather than nullifying the delay slot)). We
7814 identify jumps in switch tables by marking the SET with DImode.
7816 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7817 insns. This serves two purposes, first it prevents jump.c from
7818 noticing that the last N entries in the table jump to the instruction
7819 immediately after the table and deleting the jumps. Second, those
7820 insns mark where we should emit .begin_brtab and .end_brtab directives
7821 when using GAS (allows for better link time optimizations). */
7828 remove_useless_addtr_insns (1);
7830 if (pa_cpu < PROCESSOR_8000)
7831 pa_combine_instructions ();
7834 /* This is fairly cheap, so always run it if optimizing. */
7835 if (optimize > 0 && !TARGET_BIG_SWITCH)
7837 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7838 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7840 rtx pattern, tmp, location;
7841 unsigned int length, i;
7843 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7844 if (GET_CODE (insn) != JUMP_INSN
7845 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7846 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7849 /* Emit marker for the beginning of the branch table. */
7850 emit_insn_before (gen_begin_brtab (), insn);
7852 pattern = PATTERN (insn);
7853 location = PREV_INSN (insn);
7854 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7856 for (i = 0; i < length; i++)
7858 /* Emit a label before each jump to keep jump.c from
7859 removing this code. */
7860 tmp = gen_label_rtx ();
7861 LABEL_NUSES (tmp) = 1;
7862 emit_label_after (tmp, location);
7863 location = NEXT_INSN (location);
7865 if (GET_CODE (pattern) == ADDR_VEC)
7867 /* Emit the jump itself. */
7868 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7869 tmp = emit_jump_insn_after (tmp, location);
7870 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7871 /* It is easy to rely on the branch table markers
7872 during assembly output to trigger the correct code
7873 for a switch table jump with an unfilled delay slot,
7875 However, that requires state and assumes that we look
7878 We can't make such assumptions when computing the length
7879 of instructions. Ugh. We could walk the insn chain to
7880 determine if this instruction is in a branch table, but
7881 that can get rather expensive, particularly during the
7882 branch shortening phase of the compiler.
7884 So instead we mark this jump as being special. This is
7885 far from ideal and knows that no code after this will
7886 muck around with the mode of the JUMP_INSN itself. */
7887 PUT_MODE (tmp, SImode);
7888 LABEL_NUSES (JUMP_LABEL (tmp))++;
7889 location = NEXT_INSN (location);
7893 /* Emit the jump itself. */
7894 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7895 tmp = emit_jump_insn_after (tmp, location);
7896 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7897 /* It is easy to rely on the branch table markers
7898 during assembly output to trigger the correct code
7899 for a switch table jump with an unfilled delay slot,
7901 However, that requires state and assumes that we look
7904 We can't make such assumptions when computing the length
7905 of instructions. Ugh. We could walk the insn chain to
7906 determine if this instruction is in a branch table, but
7907 that can get rather expensive, particularly during the
7908 branch shortening phase of the compiler.
7910 So instead we mark this jump as being special. This is
7911 far from ideal and knows that no code after this will
7912 muck around with the mode of the JUMP_INSN itself. */
7913 PUT_MODE (tmp, SImode);
7914 LABEL_NUSES (JUMP_LABEL (tmp))++;
7915 location = NEXT_INSN (location);
7918 /* Emit a BARRIER after the jump. */
7919 emit_barrier_after (location);
7920 location = NEXT_INSN (location);
7923 /* Emit marker for the end of the branch table. */
7924 emit_insn_before (gen_end_brtab (), location);
7925 location = NEXT_INSN (location);
7926 emit_barrier_after (location);
7928 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7934 /* Sill need an end_brtab insn. */
7935 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7937 /* Find an ADDR_VEC insn. */
7938 if (GET_CODE (insn) != JUMP_INSN
7939 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7940 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7943 /* Now generate markers for the beginning and end of the
7945 emit_insn_before (gen_begin_brtab (), insn);
7946 emit_insn_after (gen_end_brtab (), insn);
7951 /* The PA has a number of odd instructions which can perform multiple
7952 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7953 it may be profitable to combine two instructions into one instruction
7954 with two outputs. It's not profitable PA2.0 machines because the
7955 two outputs would take two slots in the reorder buffers.
7957 This routine finds instructions which can be combined and combines
7958 them. We only support some of the potential combinations, and we
7959 only try common ways to find suitable instructions.
7961 * addb can add two registers or a register and a small integer
7962 and jump to a nearby (+-8k) location. Normally the jump to the
7963 nearby location is conditional on the result of the add, but by
7964 using the "true" condition we can make the jump unconditional.
7965 Thus addb can perform two independent operations in one insn.
7967 * movb is similar to addb in that it can perform a reg->reg
7968 or small immediate->reg copy and jump to a nearby (+-8k location).
7970 * fmpyadd and fmpysub can perform a FP multiply and either an
7971 FP add or FP sub if the operands of the multiply and add/sub are
7972 independent (there are other minor restrictions). Note both
7973 the fmpy and fadd/fsub can in theory move to better spots according
7974 to data dependencies, but for now we require the fmpy stay at a
7977 * Many of the memory operations can perform pre & post updates
7978 of index registers. GCC's pre/post increment/decrement addressing
7979 is far too simple to take advantage of all the possibilities. This
7980 pass may not be suitable since those insns may not be independent.
7982 * comclr can compare two ints or an int and a register, nullify
7983 the following instruction and zero some other register. This
7984 is more difficult to use as it's harder to find an insn which
7985 will generate a comclr than finding something like an unconditional
7986 branch. (conditional moves & long branches create comclr insns).
7988 * Most arithmetic operations can conditionally skip the next
7989 instruction. They can be viewed as "perform this operation
7990 and conditionally jump to this nearby location" (where nearby
7991 is an insns away). These are difficult to use due to the
7992 branch length restrictions. */
7995 pa_combine_instructions ()
7999 /* This can get expensive since the basic algorithm is on the
8000 order of O(n^2) (or worse). Only do it for -O2 or higher
8001 levels of optimization. */
8005 /* Walk down the list of insns looking for "anchor" insns which
8006 may be combined with "floating" insns. As the name implies,
8007 "anchor" instructions don't move, while "floating" insns may
8009 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8010 new = make_insn_raw (new);
8012 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8014 enum attr_pa_combine_type anchor_attr;
8015 enum attr_pa_combine_type floater_attr;
8017 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8018 Also ignore any special USE insns. */
8019 if ((GET_CODE (anchor) != INSN
8020 && GET_CODE (anchor) != JUMP_INSN
8021 && GET_CODE (anchor) != CALL_INSN)
8022 || GET_CODE (PATTERN (anchor)) == USE
8023 || GET_CODE (PATTERN (anchor)) == CLOBBER
8024 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8025 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8028 anchor_attr = get_attr_pa_combine_type (anchor);
8029 /* See if anchor is an insn suitable for combination. */
8030 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8031 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8032 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8033 && ! forward_branch_p (anchor)))
8037 for (floater = PREV_INSN (anchor);
8039 floater = PREV_INSN (floater))
8041 if (GET_CODE (floater) == NOTE
8042 || (GET_CODE (floater) == INSN
8043 && (GET_CODE (PATTERN (floater)) == USE
8044 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8047 /* Anything except a regular INSN will stop our search. */
8048 if (GET_CODE (floater) != INSN
8049 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8050 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8056 /* See if FLOATER is suitable for combination with the
8058 floater_attr = get_attr_pa_combine_type (floater);
8059 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8060 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8061 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8062 && floater_attr == PA_COMBINE_TYPE_FMPY))
8064 /* If ANCHOR and FLOATER can be combined, then we're
8065 done with this pass. */
8066 if (pa_can_combine_p (new, anchor, floater, 0,
8067 SET_DEST (PATTERN (floater)),
8068 XEXP (SET_SRC (PATTERN (floater)), 0),
8069 XEXP (SET_SRC (PATTERN (floater)), 1)))
8073 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8074 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8076 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8078 if (pa_can_combine_p (new, anchor, floater, 0,
8079 SET_DEST (PATTERN (floater)),
8080 XEXP (SET_SRC (PATTERN (floater)), 0),
8081 XEXP (SET_SRC (PATTERN (floater)), 1)))
8086 if (pa_can_combine_p (new, anchor, floater, 0,
8087 SET_DEST (PATTERN (floater)),
8088 SET_SRC (PATTERN (floater)),
8089 SET_SRC (PATTERN (floater))))
8095 /* If we didn't find anything on the backwards scan try forwards. */
8097 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8098 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8100 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8102 if (GET_CODE (floater) == NOTE
8103 || (GET_CODE (floater) == INSN
8104 && (GET_CODE (PATTERN (floater)) == USE
8105 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8109 /* Anything except a regular INSN will stop our search. */
8110 if (GET_CODE (floater) != INSN
8111 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8112 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8118 /* See if FLOATER is suitable for combination with the
8120 floater_attr = get_attr_pa_combine_type (floater);
8121 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8122 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8123 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8124 && floater_attr == PA_COMBINE_TYPE_FMPY))
8126 /* If ANCHOR and FLOATER can be combined, then we're
8127 done with this pass. */
8128 if (pa_can_combine_p (new, anchor, floater, 1,
8129 SET_DEST (PATTERN (floater)),
8130 XEXP (SET_SRC (PATTERN (floater)),
8132 XEXP (SET_SRC (PATTERN (floater)),
8139 /* FLOATER will be nonzero if we found a suitable floating
8140 insn for combination with ANCHOR. */
8142 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8143 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8145 /* Emit the new instruction and delete the old anchor. */
8146 emit_insn_before (gen_rtx_PARALLEL
8148 gen_rtvec (2, PATTERN (anchor),
8149 PATTERN (floater))),
8152 PUT_CODE (anchor, NOTE);
8153 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8154 NOTE_SOURCE_FILE (anchor) = 0;
8156 /* Emit a special USE insn for FLOATER, then delete
8157 the floating insn. */
8158 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8159 delete_insn (floater);
8164 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8167 /* Emit the new_jump instruction and delete the old anchor. */
8169 = emit_jump_insn_before (gen_rtx_PARALLEL
8171 gen_rtvec (2, PATTERN (anchor),
8172 PATTERN (floater))),
8175 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8176 PUT_CODE (anchor, NOTE);
8177 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8178 NOTE_SOURCE_FILE (anchor) = 0;
8180 /* Emit a special USE insn for FLOATER, then delete
8181 the floating insn. */
8182 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8183 delete_insn (floater);
8191 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
8192 rtx new, anchor, floater;
8194 rtx dest, src1, src2;
8196 int insn_code_number;
8199 /* Create a PARALLEL with the patterns of ANCHOR and
8200 FLOATER, try to recognize it, then test constraints
8201 for the resulting pattern.
8203 If the pattern doesn't match or the constraints
8204 aren't met keep searching for a suitable floater
8206 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8207 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8208 INSN_CODE (new) = -1;
8209 insn_code_number = recog_memoized (new);
8210 if (insn_code_number < 0
8211 || (extract_insn (new), ! constrain_operands (1)))
8225 /* There's up to three operands to consider. One
8226 output and two inputs.
8228 The output must not be used between FLOATER & ANCHOR
8229 exclusive. The inputs must not be set between
8230 FLOATER and ANCHOR exclusive. */
8232 if (reg_used_between_p (dest, start, end))
8235 if (reg_set_between_p (src1, start, end))
8238 if (reg_set_between_p (src2, start, end))
8241 /* If we get here, then everything is good. */
8245 /* Return nonzero if references for INSN are delayed.
8247 Millicode insns are actually function calls with some special
8248 constraints on arguments and register usage.
8250 Millicode calls always expect their arguments in the integer argument
8251 registers, and always return their result in %r29 (ret1). They
8252 are expected to clobber their arguments, %r1, %r29, and the return
8253 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8255 This function tells reorg that the references to arguments and
8256 millicode calls do not appear to happen until after the millicode call.
8257 This allows reorg to put insns which set the argument registers into the
8258 delay slot of the millicode call -- thus they act more like traditional
8261 Note we can not consider side effects of the insn to be delayed because
8262 the branch and link insn will clobber the return pointer. If we happened
8263 to use the return pointer in the delay slot of the call, then we lose.
8265 get_attr_type will try to recognize the given insn, so make sure to
8266 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8269 insn_refs_are_delayed (insn)
8272 return ((GET_CODE (insn) == INSN
8273 && GET_CODE (PATTERN (insn)) != SEQUENCE
8274 && GET_CODE (PATTERN (insn)) != USE
8275 && GET_CODE (PATTERN (insn)) != CLOBBER
8276 && get_attr_type (insn) == TYPE_MILLI));
8279 /* On the HP-PA the value is found in register(s) 28(-29), unless
8280 the mode is SF or DF. Then the value is returned in fr4 (32).
8282 This must perform the same promotions as PROMOTE_MODE, else
8283 PROMOTE_FUNCTION_RETURN will not work correctly.
8285 Small structures must be returned in a PARALLEL on PA64 in order
8286 to match the HP Compiler ABI. */
8289 function_value (valtype, func)
8291 tree func ATTRIBUTE_UNUSED;
8293 enum machine_mode valmode;
8295 /* Aggregates with a size less than or equal to 128 bits are returned
8296 in GR 28(-29). They are left justified. The pad bits are undefined.
8297 Larger aggregates are returned in memory. */
8298 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8302 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8304 for (i = 0; i < ub; i++)
8306 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8307 gen_rtx_REG (DImode, 28 + i),
8312 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8315 if ((INTEGRAL_TYPE_P (valtype)
8316 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8317 || POINTER_TYPE_P (valtype))
8318 valmode = word_mode;
8320 valmode = TYPE_MODE (valtype);
8322 if (TREE_CODE (valtype) == REAL_TYPE
8323 && TYPE_MODE (valtype) != TFmode
8324 && !TARGET_SOFT_FLOAT)
8325 return gen_rtx_REG (valmode, 32);
8327 return gen_rtx_REG (valmode, 28);
8330 /* Return the location of a parameter that is passed in a register or NULL
8331 if the parameter has any component that is passed in memory.
8333 This is new code and will be pushed to into the net sources after
8336 ??? We might want to restructure this so that it looks more like other
8339 function_arg (cum, mode, type, named)
8340 CUMULATIVE_ARGS *cum;
8341 enum machine_mode mode;
8343 int named ATTRIBUTE_UNUSED;
8345 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8352 if (mode == VOIDmode)
8355 arg_size = FUNCTION_ARG_SIZE (mode, type);
8357 /* If this arg would be passed partially or totally on the stack, then
8358 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8359 handle arguments which are split between regs and stack slots if
8360 the ABI mandates split arguments. */
8363 /* The 32-bit ABI does not split arguments. */
8364 if (cum->words + arg_size > max_arg_words)
8370 alignment = cum->words & 1;
8371 if (cum->words + alignment >= max_arg_words)
8375 /* The 32bit ABIs and the 64bit ABIs are rather different,
8376 particularly in their handling of FP registers. We might
8377 be able to cleverly share code between them, but I'm not
8378 going to bother in the hope that splitting them up results
8379 in code that is more easily understood. */
8383 /* Advance the base registers to their current locations.
8385 Remember, gprs grow towards smaller register numbers while
8386 fprs grow to higher register numbers. Also remember that
8387 although FP regs are 32-bit addressable, we pretend that
8388 the registers are 64-bits wide. */
8389 gpr_reg_base = 26 - cum->words;
8390 fpr_reg_base = 32 + cum->words;
8392 /* Arguments wider than one word and small aggregates need special
8396 || (type && AGGREGATE_TYPE_P (type)))
8398 /* Double-extended precision (80-bit), quad-precision (128-bit)
8399 and aggregates including complex numbers are aligned on
8400 128-bit boundaries. The first eight 64-bit argument slots
8401 are associated one-to-one, with general registers r26
8402 through r19, and also with floating-point registers fr4
8403 through fr11. Arguments larger than one word are always
8404 passed in general registers.
8406 Using a PARALLEL with a word mode register results in left
8407 justified data on a big-endian target. */
8410 int i, offset = 0, ub = arg_size;
8412 /* Align the base register. */
8413 gpr_reg_base -= alignment;
8415 ub = MIN (ub, max_arg_words - cum->words - alignment);
8416 for (i = 0; i < ub; i++)
8418 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8419 gen_rtx_REG (DImode, gpr_reg_base),
8425 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8430 /* If the argument is larger than a word, then we know precisely
8431 which registers we must use. */
8445 /* Structures 5 to 8 bytes in size are passed in the general
8446 registers in the same manner as other non floating-point
8447 objects. The data is right-justified and zero-extended
8450 This is magic. Normally, using a PARALLEL results in left
8451 justified data on a big-endian target. However, using a
8452 single double-word register provides the required right
8453 justication for 5 to 8 byte structures. This has nothing
8454 to do with the direction of padding specified for the argument.
8455 It has to do with how the data is widened and shifted into
8456 and from the register.
8458 Aside from adding load_multiple and store_multiple patterns,
8459 this is the only way that I have found to obtain right
8460 justification of BLKmode data when it has a size greater
8461 than one word. Splitting the operation into two SImode loads
8462 or returning a DImode REG results in left justified data. */
8463 if (mode == BLKmode)
8465 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8466 gen_rtx_REG (DImode, gpr_reg_base),
8468 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8473 /* We have a single word (32 bits). A simple computation
8474 will get us the register #s we need. */
8475 gpr_reg_base = 26 - cum->words;
8476 fpr_reg_base = 32 + 2 * cum->words;
8480 /* Determine if the argument needs to be passed in both general and
8481 floating point registers. */
8482 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8483 /* If we are doing soft-float with portable runtime, then there
8484 is no need to worry about FP regs. */
8485 && !TARGET_SOFT_FLOAT
8486 /* The parameter must be some kind of float, else we can just
8487 pass it in integer registers. */
8488 && FLOAT_MODE_P (mode)
8489 /* The target function must not have a prototype. */
8490 && cum->nargs_prototype <= 0
8491 /* libcalls do not need to pass items in both FP and general
8493 && type != NULL_TREE
8494 /* All this hair applies to "outgoing" args only. This includes
8495 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8497 /* Also pass outgoing floating arguments in both registers in indirect
8498 calls with the 32 bit ABI and the HP assembler since there is no
8499 way to the specify argument locations in static functions. */
8504 && FLOAT_MODE_P (mode)))
8510 gen_rtx_EXPR_LIST (VOIDmode,
8511 gen_rtx_REG (mode, fpr_reg_base),
8513 gen_rtx_EXPR_LIST (VOIDmode,
8514 gen_rtx_REG (mode, gpr_reg_base),
8519 /* See if we should pass this parameter in a general register. */
8520 if (TARGET_SOFT_FLOAT
8521 /* Indirect calls in the normal 32bit ABI require all arguments
8522 to be passed in general registers. */
8523 || (!TARGET_PORTABLE_RUNTIME
8527 /* If the parameter is not a floating point parameter, then
8528 it belongs in GPRs. */
8529 || !FLOAT_MODE_P (mode))
8530 retval = gen_rtx_REG (mode, gpr_reg_base);
8532 retval = gen_rtx_REG (mode, fpr_reg_base);
8538 /* If this arg would be passed totally in registers or totally on the stack,
8539 then this routine should return zero. It is currently called only for
8540 the 64-bit target. */
8542 function_arg_partial_nregs (cum, mode, type, named)
8543 CUMULATIVE_ARGS *cum;
8544 enum machine_mode mode;
8546 int named ATTRIBUTE_UNUSED;
8548 unsigned int max_arg_words = 8;
8549 unsigned int offset = 0;
8551 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8554 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8555 /* Arg fits fully into registers. */
8557 else if (cum->words + offset >= max_arg_words)
8558 /* Arg fully on the stack. */
8562 return max_arg_words - cum->words - offset;
8566 /* Return 1 if this is a comparison operator. This allows the use of
8567 MATCH_OPERATOR to recognize all the branch insns. */
8570 cmpib_comparison_operator (op, mode)
8572 enum machine_mode mode;
8574 return ((mode == VOIDmode || GET_MODE (op) == mode)
8575 && (GET_CODE (op) == EQ
8576 || GET_CODE (op) == NE
8577 || GET_CODE (op) == GT
8578 || GET_CODE (op) == GTU
8579 || GET_CODE (op) == GE
8580 || GET_CODE (op) == LT
8581 || GET_CODE (op) == LE
8582 || GET_CODE (op) == LEU));
8585 /* On hpux10, the linker will give an error if we have a reference
8586 in the read-only data section to a symbol defined in a shared
8587 library. Therefore, expressions that might require a reloc can
8588 not be placed in the read-only data section. */
8591 pa_select_section (exp, reloc, align)
8594 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8596 if (TREE_CODE (exp) == VAR_DECL
8597 && TREE_READONLY (exp)
8598 && !TREE_THIS_VOLATILE (exp)
8599 && DECL_INITIAL (exp)
8600 && (DECL_INITIAL (exp) == error_mark_node
8601 || TREE_CONSTANT (DECL_INITIAL (exp)))
8603 readonly_data_section ();
8604 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
8605 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
8607 readonly_data_section ();
8613 pa_globalize_label (stream, name)
8617 /* We only handle DATA objects here, functions are globalized in
8618 ASM_DECLARE_FUNCTION_NAME. */
8619 if (! FUNCTION_NAME_P (name))
8621 fputs ("\t.EXPORT ", stream);
8622 assemble_name (stream, name);
8623 fputs (",DATA\n", stream);