1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || (get_attr_type (in_insn) != TYPE_FPSTORE
62 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
63 || recog_memoized (out_insn) < 0)
66 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
68 set = single_set (out_insn);
72 other_mode = GET_MODE (SET_SRC (set));
74 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
78 #ifndef DO_FRAME_NOTES
79 #ifdef INCOMING_RETURN_ADDR_RTX
80 #define DO_FRAME_NOTES 1
82 #define DO_FRAME_NOTES 0
86 static void copy_reg_pointer (rtx, rtx);
87 static void fix_range (const char *);
88 static bool pa_handle_option (size_t, const char *, int);
89 static int hppa_address_cost (rtx);
90 static bool hppa_rtx_costs (rtx, int, int, int *);
91 static inline rtx force_mode (enum machine_mode, rtx);
92 static void pa_reorg (void);
93 static void pa_combine_instructions (void);
94 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
95 static int forward_branch_p (rtx);
96 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
97 static int compute_movmem_length (rtx);
98 static int compute_clrmem_length (rtx);
99 static bool pa_assemble_integer (rtx, unsigned int, int);
100 static void remove_useless_addtr_insns (int);
101 static void store_reg (int, HOST_WIDE_INT, int);
102 static void store_reg_modify (int, int, HOST_WIDE_INT);
103 static void load_reg (int, HOST_WIDE_INT, int);
104 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
105 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
106 static void update_total_code_bytes (int);
107 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
108 static int pa_adjust_cost (rtx, rtx, rtx, int);
109 static int pa_adjust_priority (rtx, int);
110 static int pa_issue_rate (void);
111 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
112 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
114 static void pa_encode_section_info (tree, rtx, int);
115 static const char *pa_strip_name_encoding (const char *);
116 static bool pa_function_ok_for_sibcall (tree, tree);
117 static void pa_globalize_label (FILE *, const char *)
119 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
120 HOST_WIDE_INT, tree);
121 #if !defined(USE_COLLECT2)
122 static void pa_asm_out_constructor (rtx, int);
123 static void pa_asm_out_destructor (rtx, int);
125 static void pa_init_builtins (void);
126 static rtx hppa_builtin_saveregs (void);
127 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
128 static bool pa_scalar_mode_supported_p (enum machine_mode);
129 static bool pa_commutative_p (rtx x, int outer_code);
130 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
131 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
134 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
135 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
136 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
139 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
140 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
141 static void output_deferred_plabels (void);
142 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
143 #ifdef ASM_OUTPUT_EXTERNAL_REAL
144 static void pa_hpux_file_end (void);
146 #ifdef HPUX_LONG_DOUBLE_LIBRARY
147 static void pa_hpux_init_libfuncs (void);
149 static rtx pa_struct_value_rtx (tree, int);
150 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
152 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
154 static struct machine_function * pa_init_machine_status (void);
155 static enum reg_class pa_secondary_reload (bool, rtx, enum reg_class,
157 secondary_reload_info *);
160 /* The following extra sections are only used for SOM. */
161 static GTY(()) section *som_readonly_data_section;
162 static GTY(()) section *som_one_only_readonly_data_section;
163 static GTY(()) section *som_one_only_data_section;
165 /* Save the operands last given to a compare for use when we
166 generate a scc or bcc insn. */
167 rtx hppa_compare_op0, hppa_compare_op1;
168 enum cmp_type hppa_branch_type;
170 /* Which cpu we are scheduling for. */
171 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
173 /* The UNIX standard to use for predefines and linking. */
174 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
176 /* Counts for the number of callee-saved general and floating point
177 registers which were saved by the current function's prologue. */
178 static int gr_saved, fr_saved;
180 static rtx find_addr_reg (rtx);
182 /* Keep track of the number of bytes we have output in the CODE subspace
183 during this compilation so we'll know when to emit inline long-calls. */
184 unsigned long total_code_bytes;
186 /* The last address of the previous function plus the number of bytes in
187 associated thunks that have been output. This is used to determine if
188 a thunk can use an IA-relative branch to reach its target function. */
189 static int last_address;
191 /* Variables to handle plabels that we discover are necessary at assembly
192 output time. They are output after the current function. */
193 struct deferred_plabel GTY(())
198 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
200 static size_t n_deferred_plabels = 0;
203 /* Initialize the GCC target structure. */
205 #undef TARGET_ASM_ALIGNED_HI_OP
206 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
207 #undef TARGET_ASM_ALIGNED_SI_OP
208 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
209 #undef TARGET_ASM_ALIGNED_DI_OP
210 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
211 #undef TARGET_ASM_UNALIGNED_HI_OP
212 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
213 #undef TARGET_ASM_UNALIGNED_SI_OP
214 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
215 #undef TARGET_ASM_UNALIGNED_DI_OP
216 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
217 #undef TARGET_ASM_INTEGER
218 #define TARGET_ASM_INTEGER pa_assemble_integer
220 #undef TARGET_ASM_FUNCTION_PROLOGUE
221 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
222 #undef TARGET_ASM_FUNCTION_EPILOGUE
223 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
225 #undef TARGET_SCHED_ADJUST_COST
226 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
227 #undef TARGET_SCHED_ADJUST_PRIORITY
228 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
229 #undef TARGET_SCHED_ISSUE_RATE
230 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
232 #undef TARGET_ENCODE_SECTION_INFO
233 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
234 #undef TARGET_STRIP_NAME_ENCODING
235 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
237 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
238 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
240 #undef TARGET_COMMUTATIVE_P
241 #define TARGET_COMMUTATIVE_P pa_commutative_p
243 #undef TARGET_ASM_OUTPUT_MI_THUNK
244 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
245 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
246 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
248 #undef TARGET_ASM_FILE_END
249 #ifdef ASM_OUTPUT_EXTERNAL_REAL
250 #define TARGET_ASM_FILE_END pa_hpux_file_end
252 #define TARGET_ASM_FILE_END output_deferred_plabels
255 #if !defined(USE_COLLECT2)
256 #undef TARGET_ASM_CONSTRUCTOR
257 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
258 #undef TARGET_ASM_DESTRUCTOR
259 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
262 #undef TARGET_DEFAULT_TARGET_FLAGS
263 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
264 #undef TARGET_HANDLE_OPTION
265 #define TARGET_HANDLE_OPTION pa_handle_option
267 #undef TARGET_INIT_BUILTINS
268 #define TARGET_INIT_BUILTINS pa_init_builtins
270 #undef TARGET_RTX_COSTS
271 #define TARGET_RTX_COSTS hppa_rtx_costs
272 #undef TARGET_ADDRESS_COST
273 #define TARGET_ADDRESS_COST hppa_address_cost
275 #undef TARGET_MACHINE_DEPENDENT_REORG
276 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
278 #ifdef HPUX_LONG_DOUBLE_LIBRARY
279 #undef TARGET_INIT_LIBFUNCS
280 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
283 #undef TARGET_PROMOTE_FUNCTION_RETURN
284 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
285 #undef TARGET_PROMOTE_PROTOTYPES
286 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
288 #undef TARGET_STRUCT_VALUE_RTX
289 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
290 #undef TARGET_RETURN_IN_MEMORY
291 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
292 #undef TARGET_MUST_PASS_IN_STACK
293 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
294 #undef TARGET_PASS_BY_REFERENCE
295 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
296 #undef TARGET_CALLEE_COPIES
297 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
298 #undef TARGET_ARG_PARTIAL_BYTES
299 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
301 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
302 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
303 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
304 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
306 #undef TARGET_SCALAR_MODE_SUPPORTED_P
307 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
309 #undef TARGET_CANNOT_FORCE_CONST_MEM
310 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
312 #undef TARGET_SECONDARY_RELOAD
313 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
315 struct gcc_target targetm = TARGET_INITIALIZER;
317 /* Parse the -mfixed-range= option string. */
320 fix_range (const char *const_str)
323 char *str, *dash, *comma;
325 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
326 REG2 are either register names or register numbers. The effect
327 of this option is to mark the registers in the range from REG1 to
328 REG2 as ``fixed'' so they won't be used by the compiler. This is
329 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
331 i = strlen (const_str);
332 str = (char *) alloca (i + 1);
333 memcpy (str, const_str, i + 1);
337 dash = strchr (str, '-');
340 warning (0, "value of -mfixed-range must have form REG1-REG2");
345 comma = strchr (dash + 1, ',');
349 first = decode_reg_name (str);
352 warning (0, "unknown register name: %s", str);
356 last = decode_reg_name (dash + 1);
359 warning (0, "unknown register name: %s", dash + 1);
367 warning (0, "%s-%s is an empty range", str, dash + 1);
371 for (i = first; i <= last; ++i)
372 fixed_regs[i] = call_used_regs[i] = 1;
381 /* Check if all floating point registers have been fixed. */
382 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
387 target_flags |= MASK_DISABLE_FPREGS;
390 /* Implement TARGET_HANDLE_OPTION. */
393 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
398 case OPT_mpa_risc_1_0:
400 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
404 case OPT_mpa_risc_1_1:
406 target_flags &= ~MASK_PA_20;
407 target_flags |= MASK_PA_11;
410 case OPT_mpa_risc_2_0:
412 target_flags |= MASK_PA_11 | MASK_PA_20;
416 if (strcmp (arg, "8000") == 0)
417 pa_cpu = PROCESSOR_8000;
418 else if (strcmp (arg, "7100") == 0)
419 pa_cpu = PROCESSOR_7100;
420 else if (strcmp (arg, "700") == 0)
421 pa_cpu = PROCESSOR_700;
422 else if (strcmp (arg, "7100LC") == 0)
423 pa_cpu = PROCESSOR_7100LC;
424 else if (strcmp (arg, "7200") == 0)
425 pa_cpu = PROCESSOR_7200;
426 else if (strcmp (arg, "7300") == 0)
427 pa_cpu = PROCESSOR_7300;
432 case OPT_mfixed_range_:
442 #if TARGET_HPUX_10_10
448 #if TARGET_HPUX_11_11
460 override_options (void)
462 /* Unconditional branches in the delay slot are not compatible with dwarf2
463 call frame information. There is no benefit in using this optimization
464 on PA8000 and later processors. */
465 if (pa_cpu >= PROCESSOR_8000
466 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
467 || flag_unwind_tables)
468 target_flags &= ~MASK_JUMP_IN_DELAY;
470 if (flag_pic && TARGET_PORTABLE_RUNTIME)
472 warning (0, "PIC code generation is not supported in the portable runtime model");
475 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
477 warning (0, "PIC code generation is not compatible with fast indirect calls");
480 if (! TARGET_GAS && write_symbols != NO_DEBUG)
482 warning (0, "-g is only supported when using GAS on this processor,");
483 warning (0, "-g option disabled");
484 write_symbols = NO_DEBUG;
487 /* We only support the "big PIC" model now. And we always generate PIC
488 code when in 64bit mode. */
489 if (flag_pic == 1 || TARGET_64BIT)
492 /* We can't guarantee that .dword is available for 32-bit targets. */
493 if (UNITS_PER_WORD == 4)
494 targetm.asm_out.aligned_op.di = NULL;
496 /* The unaligned ops are only available when using GAS. */
499 targetm.asm_out.unaligned_op.hi = NULL;
500 targetm.asm_out.unaligned_op.si = NULL;
501 targetm.asm_out.unaligned_op.di = NULL;
504 init_machine_status = pa_init_machine_status;
508 pa_init_builtins (void)
510 #ifdef DONT_HAVE_FPUTC_UNLOCKED
511 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
512 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
513 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
514 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
517 if (built_in_decls [BUILT_IN_FINITE])
518 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
519 if (built_in_decls [BUILT_IN_FINITEF])
520 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
524 /* Function to init struct machine_function.
525 This will be called, via a pointer variable,
526 from push_function_context. */
528 static struct machine_function *
529 pa_init_machine_status (void)
531 return ggc_alloc_cleared (sizeof (machine_function));
534 /* If FROM is a probable pointer register, mark TO as a probable
535 pointer register with the same pointer alignment as FROM. */
538 copy_reg_pointer (rtx to, rtx from)
540 if (REG_POINTER (from))
541 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
544 /* Return 1 if X contains a symbolic expression. We know these
545 expressions will have one of a few well defined forms, so
546 we need only check those forms. */
548 symbolic_expression_p (rtx x)
551 /* Strip off any HIGH. */
552 if (GET_CODE (x) == HIGH)
555 return (symbolic_operand (x, VOIDmode));
558 /* Accept any constant that can be moved in one instruction into a
561 cint_ok_for_move (HOST_WIDE_INT intval)
563 /* OK if ldo, ldil, or zdepi, can be used. */
564 return (CONST_OK_FOR_LETTER_P (intval, 'J')
565 || CONST_OK_FOR_LETTER_P (intval, 'N')
566 || CONST_OK_FOR_LETTER_P (intval, 'K'));
569 /* Return truth value of whether OP can be used as an operand in a
572 adddi3_operand (rtx op, enum machine_mode mode)
574 return (register_operand (op, mode)
575 || (GET_CODE (op) == CONST_INT
576 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
579 /* True iff zdepi can be used to generate this CONST_INT.
580 zdepi first sign extends a 5-bit signed number to a given field
581 length, then places this field anywhere in a zero. */
583 zdepi_cint_p (unsigned HOST_WIDE_INT x)
585 unsigned HOST_WIDE_INT lsb_mask, t;
587 /* This might not be obvious, but it's at least fast.
588 This function is critical; we don't have the time loops would take. */
590 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
591 /* Return true iff t is a power of two. */
592 return ((t & (t - 1)) == 0);
595 /* True iff depi or extru can be used to compute (reg & mask).
596 Accept bit pattern like these:
601 and_mask_p (unsigned HOST_WIDE_INT mask)
604 mask += mask & -mask;
605 return (mask & (mask - 1)) == 0;
608 /* True iff depi can be used to compute (reg | MASK). */
610 ior_mask_p (unsigned HOST_WIDE_INT mask)
612 mask += mask & -mask;
613 return (mask & (mask - 1)) == 0;
616 /* Legitimize PIC addresses. If the address is already
617 position-independent, we return ORIG. Newly generated
618 position-independent addresses go to REG. If we need more
619 than one register, we lose. */
622 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
626 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
628 /* Labels need special handling. */
629 if (pic_label_operand (orig, mode))
631 /* We do not want to go through the movXX expanders here since that
632 would create recursion.
634 Nor do we really want to call a generator for a named pattern
635 since that requires multiple patterns if we want to support
638 So instead we just emit the raw set, which avoids the movXX
639 expanders completely. */
640 mark_reg_pointer (reg, BITS_PER_UNIT);
641 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
642 current_function_uses_pic_offset_table = 1;
645 if (GET_CODE (orig) == SYMBOL_REF)
651 /* Before reload, allocate a temporary register for the intermediate
652 result. This allows the sequence to be deleted when the final
653 result is unused and the insns are trivially dead. */
654 tmp_reg = ((reload_in_progress || reload_completed)
655 ? reg : gen_reg_rtx (Pmode));
657 emit_move_insn (tmp_reg,
658 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
659 gen_rtx_HIGH (word_mode, orig)));
661 = gen_const_mem (Pmode,
662 gen_rtx_LO_SUM (Pmode, tmp_reg,
663 gen_rtx_UNSPEC (Pmode,
667 current_function_uses_pic_offset_table = 1;
668 mark_reg_pointer (reg, BITS_PER_UNIT);
669 insn = emit_move_insn (reg, pic_ref);
671 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
672 set_unique_reg_note (insn, REG_EQUAL, orig);
676 else if (GET_CODE (orig) == CONST)
680 if (GET_CODE (XEXP (orig, 0)) == PLUS
681 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
685 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
687 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
688 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
689 base == reg ? 0 : reg);
691 if (GET_CODE (orig) == CONST_INT)
693 if (INT_14_BITS (orig))
694 return plus_constant (base, INTVAL (orig));
695 orig = force_reg (Pmode, orig);
697 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
698 /* Likewise, should we set special REG_NOTEs here? */
704 static GTY(()) rtx gen_tls_tga;
707 gen_tls_get_addr (void)
710 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
715 hppa_tls_call (rtx arg)
719 ret = gen_reg_rtx (Pmode);
720 emit_library_call_value (gen_tls_get_addr (), ret,
721 LCT_CONST, Pmode, 1, arg, Pmode);
727 legitimize_tls_address (rtx addr)
729 rtx ret, insn, tmp, t1, t2, tp;
730 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
734 case TLS_MODEL_GLOBAL_DYNAMIC:
735 tmp = gen_reg_rtx (Pmode);
736 emit_insn (gen_tgd_load (tmp, addr));
737 ret = hppa_tls_call (tmp);
740 case TLS_MODEL_LOCAL_DYNAMIC:
741 ret = gen_reg_rtx (Pmode);
742 tmp = gen_reg_rtx (Pmode);
744 emit_insn (gen_tld_load (tmp, addr));
745 t1 = hppa_tls_call (tmp);
748 t2 = gen_reg_rtx (Pmode);
749 emit_libcall_block (insn, t2, t1,
750 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
752 emit_insn (gen_tld_offset_load (ret, addr, t2));
755 case TLS_MODEL_INITIAL_EXEC:
756 tp = gen_reg_rtx (Pmode);
757 tmp = gen_reg_rtx (Pmode);
758 ret = gen_reg_rtx (Pmode);
759 emit_insn (gen_tp_load (tp));
760 emit_insn (gen_tie_load (tmp, addr));
761 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
764 case TLS_MODEL_LOCAL_EXEC:
765 tp = gen_reg_rtx (Pmode);
766 ret = gen_reg_rtx (Pmode);
767 emit_insn (gen_tp_load (tp));
768 emit_insn (gen_tle_load (ret, addr, tp));
778 /* Try machine-dependent ways of modifying an illegitimate address
779 to be legitimate. If we find one, return the new, valid address.
780 This macro is used in only one place: `memory_address' in explow.c.
782 OLDX is the address as it was before break_out_memory_refs was called.
783 In some cases it is useful to look at this to decide what needs to be done.
785 MODE and WIN are passed so that this macro can use
786 GO_IF_LEGITIMATE_ADDRESS.
788 It is always safe for this macro to do nothing. It exists to recognize
789 opportunities to optimize the output.
791 For the PA, transform:
793 memory(X + <large int>)
797 if (<large int> & mask) >= 16
798 Y = (<large int> & ~mask) + mask + 1 Round up.
800 Y = (<large int> & ~mask) Round down.
802 memory (Z + (<large int> - Y));
804 This is for CSE to find several similar references, and only use one Z.
806 X can either be a SYMBOL_REF or REG, but because combine cannot
807 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
808 D will not fit in 14 bits.
810 MODE_FLOAT references allow displacements which fit in 5 bits, so use
813 MODE_INT references allow displacements which fit in 14 bits, so use
816 This relies on the fact that most mode MODE_FLOAT references will use FP
817 registers and most mode MODE_INT references will use integer registers.
818 (In the rare case of an FP register used in an integer MODE, we depend
819 on secondary reloads to clean things up.)
822 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
823 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
824 addressing modes to be used).
826 Put X and Z into registers. Then put the entire expression into
830 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
831 enum machine_mode mode)
835 /* We need to canonicalize the order of operands in unscaled indexed
836 addresses since the code that checks if an address is valid doesn't
837 always try both orders. */
838 if (!TARGET_NO_SPACE_REGS
839 && GET_CODE (x) == PLUS
840 && GET_MODE (x) == Pmode
841 && REG_P (XEXP (x, 0))
842 && REG_P (XEXP (x, 1))
843 && REG_POINTER (XEXP (x, 0))
844 && !REG_POINTER (XEXP (x, 1)))
845 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
847 if (PA_SYMBOL_REF_TLS_P (x))
848 return legitimize_tls_address (x);
850 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
852 /* Strip off CONST. */
853 if (GET_CODE (x) == CONST)
856 /* Special case. Get the SYMBOL_REF into a register and use indexing.
857 That should always be safe. */
858 if (GET_CODE (x) == PLUS
859 && GET_CODE (XEXP (x, 0)) == REG
860 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
862 rtx reg = force_reg (Pmode, XEXP (x, 1));
863 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
866 /* Note we must reject symbols which represent function addresses
867 since the assembler/linker can't handle arithmetic on plabels. */
868 if (GET_CODE (x) == PLUS
869 && GET_CODE (XEXP (x, 1)) == CONST_INT
870 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
871 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
872 || GET_CODE (XEXP (x, 0)) == REG))
874 rtx int_part, ptr_reg;
876 int offset = INTVAL (XEXP (x, 1));
879 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
880 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
882 /* Choose which way to round the offset. Round up if we
883 are >= halfway to the next boundary. */
884 if ((offset & mask) >= ((mask + 1) / 2))
885 newoffset = (offset & ~ mask) + mask + 1;
887 newoffset = (offset & ~ mask);
889 /* If the newoffset will not fit in 14 bits (ldo), then
890 handling this would take 4 or 5 instructions (2 to load
891 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
892 add the new offset and the SYMBOL_REF.) Combine can
893 not handle 4->2 or 5->2 combinations, so do not create
895 if (! VAL_14_BITS_P (newoffset)
896 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
898 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
901 gen_rtx_HIGH (Pmode, const_part));
904 gen_rtx_LO_SUM (Pmode,
905 tmp_reg, const_part));
909 if (! VAL_14_BITS_P (newoffset))
910 int_part = force_reg (Pmode, GEN_INT (newoffset));
912 int_part = GEN_INT (newoffset);
914 ptr_reg = force_reg (Pmode,
916 force_reg (Pmode, XEXP (x, 0)),
919 return plus_constant (ptr_reg, offset - newoffset);
922 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
924 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
925 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
926 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
927 && (OBJECT_P (XEXP (x, 1))
928 || GET_CODE (XEXP (x, 1)) == SUBREG)
929 && GET_CODE (XEXP (x, 1)) != CONST)
931 int val = INTVAL (XEXP (XEXP (x, 0), 1));
935 if (GET_CODE (reg1) != REG)
936 reg1 = force_reg (Pmode, force_operand (reg1, 0));
938 reg2 = XEXP (XEXP (x, 0), 0);
939 if (GET_CODE (reg2) != REG)
940 reg2 = force_reg (Pmode, force_operand (reg2, 0));
942 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
949 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
951 Only do so for floating point modes since this is more speculative
952 and we lose if it's an integer store. */
953 if (GET_CODE (x) == PLUS
954 && GET_CODE (XEXP (x, 0)) == PLUS
955 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
956 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
957 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
958 && (mode == SFmode || mode == DFmode))
961 /* First, try and figure out what to use as a base register. */
962 rtx reg1, reg2, base, idx, orig_base;
964 reg1 = XEXP (XEXP (x, 0), 1);
969 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
970 then emit_move_sequence will turn on REG_POINTER so we'll know
971 it's a base register below. */
972 if (GET_CODE (reg1) != REG)
973 reg1 = force_reg (Pmode, force_operand (reg1, 0));
975 if (GET_CODE (reg2) != REG)
976 reg2 = force_reg (Pmode, force_operand (reg2, 0));
978 /* Figure out what the base and index are. */
980 if (GET_CODE (reg1) == REG
981 && REG_POINTER (reg1))
984 orig_base = XEXP (XEXP (x, 0), 1);
985 idx = gen_rtx_PLUS (Pmode,
987 XEXP (XEXP (XEXP (x, 0), 0), 0),
988 XEXP (XEXP (XEXP (x, 0), 0), 1)),
991 else if (GET_CODE (reg2) == REG
992 && REG_POINTER (reg2))
995 orig_base = XEXP (x, 1);
1002 /* If the index adds a large constant, try to scale the
1003 constant so that it can be loaded with only one insn. */
1004 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1005 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1006 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1007 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1009 /* Divide the CONST_INT by the scale factor, then add it to A. */
1010 int val = INTVAL (XEXP (idx, 1));
1012 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1013 reg1 = XEXP (XEXP (idx, 0), 0);
1014 if (GET_CODE (reg1) != REG)
1015 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1017 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1019 /* We can now generate a simple scaled indexed address. */
1022 (Pmode, gen_rtx_PLUS (Pmode,
1023 gen_rtx_MULT (Pmode, reg1,
1024 XEXP (XEXP (idx, 0), 1)),
1028 /* If B + C is still a valid base register, then add them. */
1029 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1030 && INTVAL (XEXP (idx, 1)) <= 4096
1031 && INTVAL (XEXP (idx, 1)) >= -4096)
1033 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1036 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1038 reg2 = XEXP (XEXP (idx, 0), 0);
1039 if (GET_CODE (reg2) != CONST_INT)
1040 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1042 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1043 gen_rtx_MULT (Pmode,
1049 /* Get the index into a register, then add the base + index and
1050 return a register holding the result. */
1052 /* First get A into a register. */
1053 reg1 = XEXP (XEXP (idx, 0), 0);
1054 if (GET_CODE (reg1) != REG)
1055 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1057 /* And get B into a register. */
1058 reg2 = XEXP (idx, 1);
1059 if (GET_CODE (reg2) != REG)
1060 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1062 reg1 = force_reg (Pmode,
1063 gen_rtx_PLUS (Pmode,
1064 gen_rtx_MULT (Pmode, reg1,
1065 XEXP (XEXP (idx, 0), 1)),
1068 /* Add the result to our base register and return. */
1069 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1073 /* Uh-oh. We might have an address for x[n-100000]. This needs
1074 special handling to avoid creating an indexed memory address
1075 with x-100000 as the base.
1077 If the constant part is small enough, then it's still safe because
1078 there is a guard page at the beginning and end of the data segment.
1080 Scaled references are common enough that we want to try and rearrange the
1081 terms so that we can use indexing for these addresses too. Only
1082 do the optimization for floatint point modes. */
1084 if (GET_CODE (x) == PLUS
1085 && symbolic_expression_p (XEXP (x, 1)))
1087 /* Ugly. We modify things here so that the address offset specified
1088 by the index expression is computed first, then added to x to form
1089 the entire address. */
1091 rtx regx1, regx2, regy1, regy2, y;
1093 /* Strip off any CONST. */
1095 if (GET_CODE (y) == CONST)
1098 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1100 /* See if this looks like
1101 (plus (mult (reg) (shadd_const))
1102 (const (plus (symbol_ref) (const_int))))
1104 Where const_int is small. In that case the const
1105 expression is a valid pointer for indexing.
1107 If const_int is big, but can be divided evenly by shadd_const
1108 and added to (reg). This allows more scaled indexed addresses. */
1109 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1110 && GET_CODE (XEXP (x, 0)) == MULT
1111 && GET_CODE (XEXP (y, 1)) == CONST_INT
1112 && INTVAL (XEXP (y, 1)) >= -4096
1113 && INTVAL (XEXP (y, 1)) <= 4095
1114 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1115 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1117 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1121 if (GET_CODE (reg1) != REG)
1122 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1124 reg2 = XEXP (XEXP (x, 0), 0);
1125 if (GET_CODE (reg2) != REG)
1126 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1128 return force_reg (Pmode,
1129 gen_rtx_PLUS (Pmode,
1130 gen_rtx_MULT (Pmode,
1135 else if ((mode == DFmode || mode == SFmode)
1136 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1137 && GET_CODE (XEXP (x, 0)) == MULT
1138 && GET_CODE (XEXP (y, 1)) == CONST_INT
1139 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1140 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1141 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1144 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1145 / INTVAL (XEXP (XEXP (x, 0), 1))));
1146 regx2 = XEXP (XEXP (x, 0), 0);
1147 if (GET_CODE (regx2) != REG)
1148 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1149 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1153 gen_rtx_PLUS (Pmode,
1154 gen_rtx_MULT (Pmode, regx2,
1155 XEXP (XEXP (x, 0), 1)),
1156 force_reg (Pmode, XEXP (y, 0))));
1158 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1159 && INTVAL (XEXP (y, 1)) >= -4096
1160 && INTVAL (XEXP (y, 1)) <= 4095)
1162 /* This is safe because of the guard page at the
1163 beginning and end of the data space. Just
1164 return the original address. */
1169 /* Doesn't look like one we can optimize. */
1170 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1171 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1172 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1173 regx1 = force_reg (Pmode,
1174 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1176 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1184 /* For the HPPA, REG and REG+CONST is cost 0
1185 and addresses involving symbolic constants are cost 2.
1187 PIC addresses are very expensive.
1189 It is no coincidence that this has the same structure
1190 as GO_IF_LEGITIMATE_ADDRESS. */
1193 hppa_address_cost (rtx X)
1195 switch (GET_CODE (X))
1208 /* Compute a (partial) cost for rtx X. Return true if the complete
1209 cost has been computed, and false if subexpressions should be
1210 scanned. In either case, *TOTAL contains the cost result. */
1213 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1218 if (INTVAL (x) == 0)
1220 else if (INT_14_BITS (x))
1237 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1238 && outer_code != SET)
1245 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1246 *total = COSTS_N_INSNS (3);
1247 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1248 *total = COSTS_N_INSNS (8);
1250 *total = COSTS_N_INSNS (20);
1254 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1256 *total = COSTS_N_INSNS (14);
1264 *total = COSTS_N_INSNS (60);
1267 case PLUS: /* this includes shNadd insns */
1269 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1270 *total = COSTS_N_INSNS (3);
1272 *total = COSTS_N_INSNS (1);
1278 *total = COSTS_N_INSNS (1);
1286 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1287 new rtx with the correct mode. */
1289 force_mode (enum machine_mode mode, rtx orig)
1291 if (mode == GET_MODE (orig))
1294 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1296 return gen_rtx_REG (mode, REGNO (orig));
1299 /* Return 1 if *X is a thread-local symbol. */
1302 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1304 return PA_SYMBOL_REF_TLS_P (*x);
1307 /* Return 1 if X contains a thread-local symbol. */
1310 pa_tls_referenced_p (rtx x)
1312 if (!TARGET_HAVE_TLS)
1315 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1318 /* Emit insns to move operands[1] into operands[0].
1320 Return 1 if we have written out everything that needs to be done to
1321 do the move. Otherwise, return 0 and the caller will emit the move
1324 Note SCRATCH_REG may not be in the proper mode depending on how it
1325 will be used. This routine is responsible for creating a new copy
1326 of SCRATCH_REG in the proper mode. */
1329 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1331 register rtx operand0 = operands[0];
1332 register rtx operand1 = operands[1];
1335 /* We can only handle indexed addresses in the destination operand
1336 of floating point stores. Thus, we need to break out indexed
1337 addresses from the destination operand. */
1338 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1340 /* This is only safe up to the beginning of life analysis. */
1341 gcc_assert (!no_new_pseudos);
1343 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1344 operand0 = replace_equiv_address (operand0, tem);
1347 /* On targets with non-equivalent space registers, break out unscaled
1348 indexed addresses from the source operand before the final CSE.
1349 We have to do this because the REG_POINTER flag is not correctly
1350 carried through various optimization passes and CSE may substitute
1351 a pseudo without the pointer set for one with the pointer set. As
1352 a result, we loose various opportunities to create insns with
1353 unscaled indexed addresses. */
1354 if (!TARGET_NO_SPACE_REGS
1355 && !cse_not_expected
1356 && GET_CODE (operand1) == MEM
1357 && GET_CODE (XEXP (operand1, 0)) == PLUS
1358 && REG_P (XEXP (XEXP (operand1, 0), 0))
1359 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1361 = replace_equiv_address (operand1,
1362 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1365 && reload_in_progress && GET_CODE (operand0) == REG
1366 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1367 operand0 = reg_equiv_mem[REGNO (operand0)];
1368 else if (scratch_reg
1369 && reload_in_progress && GET_CODE (operand0) == SUBREG
1370 && GET_CODE (SUBREG_REG (operand0)) == REG
1371 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1373 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1374 the code which tracks sets/uses for delete_output_reload. */
1375 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1376 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1377 SUBREG_BYTE (operand0));
1378 operand0 = alter_subreg (&temp);
1382 && reload_in_progress && GET_CODE (operand1) == REG
1383 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1384 operand1 = reg_equiv_mem[REGNO (operand1)];
1385 else if (scratch_reg
1386 && reload_in_progress && GET_CODE (operand1) == SUBREG
1387 && GET_CODE (SUBREG_REG (operand1)) == REG
1388 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1390 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1391 the code which tracks sets/uses for delete_output_reload. */
1392 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1393 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1394 SUBREG_BYTE (operand1));
1395 operand1 = alter_subreg (&temp);
1398 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1399 && ((tem = find_replacement (&XEXP (operand0, 0)))
1400 != XEXP (operand0, 0)))
1401 operand0 = replace_equiv_address (operand0, tem);
1403 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1404 && ((tem = find_replacement (&XEXP (operand1, 0)))
1405 != XEXP (operand1, 0)))
1406 operand1 = replace_equiv_address (operand1, tem);
1408 /* Handle secondary reloads for loads/stores of FP registers from
1409 REG+D addresses where D does not fit in 5 or 14 bits, including
1410 (subreg (mem (addr))) cases. */
1412 && fp_reg_operand (operand0, mode)
1413 && ((GET_CODE (operand1) == MEM
1414 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1415 XEXP (operand1, 0)))
1416 || ((GET_CODE (operand1) == SUBREG
1417 && GET_CODE (XEXP (operand1, 0)) == MEM
1418 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1420 XEXP (XEXP (operand1, 0), 0))))))
1422 if (GET_CODE (operand1) == SUBREG)
1423 operand1 = XEXP (operand1, 0);
1425 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1426 it in WORD_MODE regardless of what mode it was originally given
1428 scratch_reg = force_mode (word_mode, scratch_reg);
1430 /* D might not fit in 14 bits either; for such cases load D into
1432 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1434 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1435 emit_move_insn (scratch_reg,
1436 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1438 XEXP (XEXP (operand1, 0), 0),
1442 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1443 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1444 replace_equiv_address (operand1, scratch_reg)));
1447 else if (scratch_reg
1448 && fp_reg_operand (operand1, mode)
1449 && ((GET_CODE (operand0) == MEM
1450 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1452 XEXP (operand0, 0)))
1453 || ((GET_CODE (operand0) == SUBREG)
1454 && GET_CODE (XEXP (operand0, 0)) == MEM
1455 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1457 XEXP (XEXP (operand0, 0), 0)))))
1459 if (GET_CODE (operand0) == SUBREG)
1460 operand0 = XEXP (operand0, 0);
1462 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1463 it in WORD_MODE regardless of what mode it was originally given
1465 scratch_reg = force_mode (word_mode, scratch_reg);
1467 /* D might not fit in 14 bits either; for such cases load D into
1469 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1471 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1472 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1475 XEXP (XEXP (operand0, 0),
1480 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1481 emit_insn (gen_rtx_SET (VOIDmode,
1482 replace_equiv_address (operand0, scratch_reg),
1486 /* Handle secondary reloads for loads of FP registers from constant
1487 expressions by forcing the constant into memory.
1489 Use scratch_reg to hold the address of the memory location.
1491 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1492 NO_REGS when presented with a const_int and a register class
1493 containing only FP registers. Doing so unfortunately creates
1494 more problems than it solves. Fix this for 2.5. */
1495 else if (scratch_reg
1496 && CONSTANT_P (operand1)
1497 && fp_reg_operand (operand0, mode))
1499 rtx const_mem, xoperands[2];
1501 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1502 it in WORD_MODE regardless of what mode it was originally given
1504 scratch_reg = force_mode (word_mode, scratch_reg);
1506 /* Force the constant into memory and put the address of the
1507 memory location into scratch_reg. */
1508 const_mem = force_const_mem (mode, operand1);
1509 xoperands[0] = scratch_reg;
1510 xoperands[1] = XEXP (const_mem, 0);
1511 emit_move_sequence (xoperands, Pmode, 0);
1513 /* Now load the destination register. */
1514 emit_insn (gen_rtx_SET (mode, operand0,
1515 replace_equiv_address (const_mem, scratch_reg)));
1518 /* Handle secondary reloads for SAR. These occur when trying to load
1519 the SAR from memory, FP register, or with a constant. */
1520 else if (scratch_reg
1521 && GET_CODE (operand0) == REG
1522 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1523 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1524 && (GET_CODE (operand1) == MEM
1525 || GET_CODE (operand1) == CONST_INT
1526 || (GET_CODE (operand1) == REG
1527 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1529 /* D might not fit in 14 bits either; for such cases load D into
1531 if (GET_CODE (operand1) == MEM
1532 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1534 /* We are reloading the address into the scratch register, so we
1535 want to make sure the scratch register is a full register. */
1536 scratch_reg = force_mode (word_mode, scratch_reg);
1538 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1539 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1542 XEXP (XEXP (operand1, 0),
1546 /* Now we are going to load the scratch register from memory,
1547 we want to load it in the same width as the original MEM,
1548 which must be the same as the width of the ultimate destination,
1550 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1552 emit_move_insn (scratch_reg,
1553 replace_equiv_address (operand1, scratch_reg));
1557 /* We want to load the scratch register using the same mode as
1558 the ultimate destination. */
1559 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1561 emit_move_insn (scratch_reg, operand1);
1564 /* And emit the insn to set the ultimate destination. We know that
1565 the scratch register has the same mode as the destination at this
1567 emit_move_insn (operand0, scratch_reg);
1570 /* Handle the most common case: storing into a register. */
1571 else if (register_operand (operand0, mode))
1573 if (register_operand (operand1, mode)
1574 || (GET_CODE (operand1) == CONST_INT
1575 && cint_ok_for_move (INTVAL (operand1)))
1576 || (operand1 == CONST0_RTX (mode))
1577 || (GET_CODE (operand1) == HIGH
1578 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1579 /* Only `general_operands' can come here, so MEM is ok. */
1580 || GET_CODE (operand1) == MEM)
1582 /* Various sets are created during RTL generation which don't
1583 have the REG_POINTER flag correctly set. After the CSE pass,
1584 instruction recognition can fail if we don't consistently
1585 set this flag when performing register copies. This should
1586 also improve the opportunities for creating insns that use
1587 unscaled indexing. */
1588 if (REG_P (operand0) && REG_P (operand1))
1590 if (REG_POINTER (operand1)
1591 && !REG_POINTER (operand0)
1592 && !HARD_REGISTER_P (operand0))
1593 copy_reg_pointer (operand0, operand1);
1594 else if (REG_POINTER (operand0)
1595 && !REG_POINTER (operand1)
1596 && !HARD_REGISTER_P (operand1))
1597 copy_reg_pointer (operand1, operand0);
1600 /* When MEMs are broken out, the REG_POINTER flag doesn't
1601 get set. In some cases, we can set the REG_POINTER flag
1602 from the declaration for the MEM. */
1603 if (REG_P (operand0)
1604 && GET_CODE (operand1) == MEM
1605 && !REG_POINTER (operand0))
1607 tree decl = MEM_EXPR (operand1);
1609 /* Set the register pointer flag and register alignment
1610 if the declaration for this memory reference is a
1611 pointer type. Fortran indirect argument references
1614 && !(flag_argument_noalias > 1
1615 && TREE_CODE (decl) == INDIRECT_REF
1616 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1620 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1622 if (TREE_CODE (decl) == COMPONENT_REF)
1623 decl = TREE_OPERAND (decl, 1);
1625 type = TREE_TYPE (decl);
1626 if (TREE_CODE (type) == ARRAY_TYPE)
1627 type = get_inner_array_type (type);
1629 if (POINTER_TYPE_P (type))
1633 type = TREE_TYPE (type);
1634 /* Using TYPE_ALIGN_OK is rather conservative as
1635 only the ada frontend actually sets it. */
1636 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1638 mark_reg_pointer (operand0, align);
1643 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1647 else if (GET_CODE (operand0) == MEM)
1649 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1650 && !(reload_in_progress || reload_completed))
1652 rtx temp = gen_reg_rtx (DFmode);
1654 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1655 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1658 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1660 /* Run this case quickly. */
1661 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1664 if (! (reload_in_progress || reload_completed))
1666 operands[0] = validize_mem (operand0);
1667 operands[1] = operand1 = force_reg (mode, operand1);
1671 /* Simplify the source if we need to.
1672 Note we do have to handle function labels here, even though we do
1673 not consider them legitimate constants. Loop optimizations can
1674 call the emit_move_xxx with one as a source. */
1675 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1676 || function_label_operand (operand1, mode)
1677 || (GET_CODE (operand1) == HIGH
1678 && symbolic_operand (XEXP (operand1, 0), mode)))
1682 if (GET_CODE (operand1) == HIGH)
1685 operand1 = XEXP (operand1, 0);
1687 if (symbolic_operand (operand1, mode))
1689 /* Argh. The assembler and linker can't handle arithmetic
1692 So we force the plabel into memory, load operand0 from
1693 the memory location, then add in the constant part. */
1694 if ((GET_CODE (operand1) == CONST
1695 && GET_CODE (XEXP (operand1, 0)) == PLUS
1696 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1697 || function_label_operand (operand1, mode))
1699 rtx temp, const_part;
1701 /* Figure out what (if any) scratch register to use. */
1702 if (reload_in_progress || reload_completed)
1704 scratch_reg = scratch_reg ? scratch_reg : operand0;
1705 /* SCRATCH_REG will hold an address and maybe the actual
1706 data. We want it in WORD_MODE regardless of what mode it
1707 was originally given to us. */
1708 scratch_reg = force_mode (word_mode, scratch_reg);
1711 scratch_reg = gen_reg_rtx (Pmode);
1713 if (GET_CODE (operand1) == CONST)
1715 /* Save away the constant part of the expression. */
1716 const_part = XEXP (XEXP (operand1, 0), 1);
1717 gcc_assert (GET_CODE (const_part) == CONST_INT);
1719 /* Force the function label into memory. */
1720 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1724 /* No constant part. */
1725 const_part = NULL_RTX;
1727 /* Force the function label into memory. */
1728 temp = force_const_mem (mode, operand1);
1732 /* Get the address of the memory location. PIC-ify it if
1734 temp = XEXP (temp, 0);
1736 temp = legitimize_pic_address (temp, mode, scratch_reg);
1738 /* Put the address of the memory location into our destination
1741 emit_move_sequence (operands, mode, scratch_reg);
1743 /* Now load from the memory location into our destination
1745 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1746 emit_move_sequence (operands, mode, scratch_reg);
1748 /* And add back in the constant part. */
1749 if (const_part != NULL_RTX)
1750 expand_inc (operand0, const_part);
1759 if (reload_in_progress || reload_completed)
1761 temp = scratch_reg ? scratch_reg : operand0;
1762 /* TEMP will hold an address and maybe the actual
1763 data. We want it in WORD_MODE regardless of what mode it
1764 was originally given to us. */
1765 temp = force_mode (word_mode, temp);
1768 temp = gen_reg_rtx (Pmode);
1770 /* (const (plus (symbol) (const_int))) must be forced to
1771 memory during/after reload if the const_int will not fit
1773 if (GET_CODE (operand1) == CONST
1774 && GET_CODE (XEXP (operand1, 0)) == PLUS
1775 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1776 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1777 && (reload_completed || reload_in_progress)
1780 rtx const_mem = force_const_mem (mode, operand1);
1781 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1783 operands[1] = replace_equiv_address (const_mem, operands[1]);
1784 emit_move_sequence (operands, mode, temp);
1788 operands[1] = legitimize_pic_address (operand1, mode, temp);
1789 if (REG_P (operand0) && REG_P (operands[1]))
1790 copy_reg_pointer (operand0, operands[1]);
1791 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1794 /* On the HPPA, references to data space are supposed to use dp,
1795 register 27, but showing it in the RTL inhibits various cse
1796 and loop optimizations. */
1801 if (reload_in_progress || reload_completed)
1803 temp = scratch_reg ? scratch_reg : operand0;
1804 /* TEMP will hold an address and maybe the actual
1805 data. We want it in WORD_MODE regardless of what mode it
1806 was originally given to us. */
1807 temp = force_mode (word_mode, temp);
1810 temp = gen_reg_rtx (mode);
1812 /* Loading a SYMBOL_REF into a register makes that register
1813 safe to be used as the base in an indexed address.
1815 Don't mark hard registers though. That loses. */
1816 if (GET_CODE (operand0) == REG
1817 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1818 mark_reg_pointer (operand0, BITS_PER_UNIT);
1819 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1820 mark_reg_pointer (temp, BITS_PER_UNIT);
1823 set = gen_rtx_SET (mode, operand0, temp);
1825 set = gen_rtx_SET (VOIDmode,
1827 gen_rtx_LO_SUM (mode, temp, operand1));
1829 emit_insn (gen_rtx_SET (VOIDmode,
1831 gen_rtx_HIGH (mode, operand1)));
1837 else if (pa_tls_referenced_p (operand1))
1842 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1844 addend = XEXP (XEXP (tmp, 0), 1);
1845 tmp = XEXP (XEXP (tmp, 0), 0);
1848 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1849 tmp = legitimize_tls_address (tmp);
1852 tmp = gen_rtx_PLUS (mode, tmp, addend);
1853 tmp = force_operand (tmp, operands[0]);
1857 else if (GET_CODE (operand1) != CONST_INT
1858 || !cint_ok_for_move (INTVAL (operand1)))
1862 HOST_WIDE_INT value = 0;
1863 HOST_WIDE_INT insv = 0;
1866 if (GET_CODE (operand1) == CONST_INT)
1867 value = INTVAL (operand1);
1870 && GET_CODE (operand1) == CONST_INT
1871 && HOST_BITS_PER_WIDE_INT > 32
1872 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1876 /* Extract the low order 32 bits of the value and sign extend.
1877 If the new value is the same as the original value, we can
1878 can use the original value as-is. If the new value is
1879 different, we use it and insert the most-significant 32-bits
1880 of the original value into the final result. */
1881 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1882 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1885 #if HOST_BITS_PER_WIDE_INT > 32
1886 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1890 operand1 = GEN_INT (nval);
1894 if (reload_in_progress || reload_completed)
1895 temp = scratch_reg ? scratch_reg : operand0;
1897 temp = gen_reg_rtx (mode);
1899 /* We don't directly split DImode constants on 32-bit targets
1900 because PLUS uses an 11-bit immediate and the insn sequence
1901 generated is not as efficient as the one using HIGH/LO_SUM. */
1902 if (GET_CODE (operand1) == CONST_INT
1903 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
1904 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1907 /* Directly break constant into high and low parts. This
1908 provides better optimization opportunities because various
1909 passes recognize constants split with PLUS but not LO_SUM.
1910 We use a 14-bit signed low part except when the addition
1911 of 0x4000 to the high part might change the sign of the
1913 HOST_WIDE_INT low = value & 0x3fff;
1914 HOST_WIDE_INT high = value & ~ 0x3fff;
1918 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1926 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1927 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1931 emit_insn (gen_rtx_SET (VOIDmode, temp,
1932 gen_rtx_HIGH (mode, operand1)));
1933 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1936 insn = emit_move_insn (operands[0], operands[1]);
1938 /* Now insert the most significant 32 bits of the value
1939 into the register. When we don't have a second register
1940 available, it could take up to nine instructions to load
1941 a 64-bit integer constant. Prior to reload, we force
1942 constants that would take more than three instructions
1943 to load to the constant pool. During and after reload,
1944 we have to handle all possible values. */
1947 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1948 register and the value to be inserted is outside the
1949 range that can be loaded with three depdi instructions. */
1950 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1952 operand1 = GEN_INT (insv);
1954 emit_insn (gen_rtx_SET (VOIDmode, temp,
1955 gen_rtx_HIGH (mode, operand1)));
1956 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1957 emit_insn (gen_insv (operand0, GEN_INT (32),
1962 int len = 5, pos = 27;
1964 /* Insert the bits using the depdi instruction. */
1967 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1968 HOST_WIDE_INT sign = v5 < 0;
1970 /* Left extend the insertion. */
1971 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1972 while (pos > 0 && (insv & 1) == sign)
1974 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1979 emit_insn (gen_insv (operand0, GEN_INT (len),
1980 GEN_INT (pos), GEN_INT (v5)));
1982 len = pos > 0 && pos < 5 ? pos : 5;
1988 set_unique_reg_note (insn, REG_EQUAL, op1);
1993 /* Now have insn-emit do whatever it normally does. */
1997 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1998 it will need a link/runtime reloc). */
2001 reloc_needed (tree exp)
2005 switch (TREE_CODE (exp))
2012 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2013 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2018 case NON_LVALUE_EXPR:
2019 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2025 unsigned HOST_WIDE_INT ix;
2027 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2029 reloc |= reloc_needed (value);
2042 /* Does operand (which is a symbolic_operand) live in text space?
2043 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2047 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2049 if (GET_CODE (operand) == CONST)
2050 operand = XEXP (XEXP (operand, 0), 0);
2053 if (GET_CODE (operand) == SYMBOL_REF)
2054 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2058 if (GET_CODE (operand) == SYMBOL_REF)
2059 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2065 /* Return the best assembler insn template
2066 for moving operands[1] into operands[0] as a fullword. */
2068 singlemove_string (rtx *operands)
2070 HOST_WIDE_INT intval;
2072 if (GET_CODE (operands[0]) == MEM)
2073 return "stw %r1,%0";
2074 if (GET_CODE (operands[1]) == MEM)
2076 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2081 gcc_assert (GET_MODE (operands[1]) == SFmode);
2083 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2085 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2086 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2088 operands[1] = GEN_INT (i);
2089 /* Fall through to CONST_INT case. */
2091 if (GET_CODE (operands[1]) == CONST_INT)
2093 intval = INTVAL (operands[1]);
2095 if (VAL_14_BITS_P (intval))
2097 else if ((intval & 0x7ff) == 0)
2098 return "ldil L'%1,%0";
2099 else if (zdepi_cint_p (intval))
2100 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2102 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2104 return "copy %1,%0";
2108 /* Compute position (in OP[1]) and width (in OP[2])
2109 useful for copying IMM to a register using the zdepi
2110 instructions. Store the immediate value to insert in OP[0]. */
2112 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2116 /* Find the least significant set bit in IMM. */
2117 for (lsb = 0; lsb < 32; lsb++)
2124 /* Choose variants based on *sign* of the 5-bit field. */
2125 if ((imm & 0x10) == 0)
2126 len = (lsb <= 28) ? 4 : 32 - lsb;
2129 /* Find the width of the bitstring in IMM. */
2130 for (len = 5; len < 32; len++)
2132 if ((imm & (1 << len)) == 0)
2136 /* Sign extend IMM as a 5-bit value. */
2137 imm = (imm & 0xf) - 0x10;
2145 /* Compute position (in OP[1]) and width (in OP[2])
2146 useful for copying IMM to a register using the depdi,z
2147 instructions. Store the immediate value to insert in OP[0]. */
2149 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2151 HOST_WIDE_INT lsb, len;
2153 /* Find the least significant set bit in IMM. */
2154 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2161 /* Choose variants based on *sign* of the 5-bit field. */
2162 if ((imm & 0x10) == 0)
2163 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2164 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2167 /* Find the width of the bitstring in IMM. */
2168 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2170 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2174 /* Sign extend IMM as a 5-bit value. */
2175 imm = (imm & 0xf) - 0x10;
2183 /* Output assembler code to perform a doubleword move insn
2184 with operands OPERANDS. */
2187 output_move_double (rtx *operands)
2189 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2191 rtx addreg0 = 0, addreg1 = 0;
2193 /* First classify both operands. */
2195 if (REG_P (operands[0]))
2197 else if (offsettable_memref_p (operands[0]))
2199 else if (GET_CODE (operands[0]) == MEM)
2204 if (REG_P (operands[1]))
2206 else if (CONSTANT_P (operands[1]))
2208 else if (offsettable_memref_p (operands[1]))
2210 else if (GET_CODE (operands[1]) == MEM)
2215 /* Check for the cases that the operand constraints are not
2216 supposed to allow to happen. */
2217 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2219 /* Handle copies between general and floating registers. */
2221 if (optype0 == REGOP && optype1 == REGOP
2222 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2224 if (FP_REG_P (operands[0]))
2226 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2227 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2228 return "{fldds|fldd} -16(%%sp),%0";
2232 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2233 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2234 return "{ldws|ldw} -12(%%sp),%R0";
2238 /* Handle auto decrementing and incrementing loads and stores
2239 specifically, since the structure of the function doesn't work
2240 for them without major modification. Do it better when we learn
2241 this port about the general inc/dec addressing of PA.
2242 (This was written by tege. Chide him if it doesn't work.) */
2244 if (optype0 == MEMOP)
2246 /* We have to output the address syntax ourselves, since print_operand
2247 doesn't deal with the addresses we want to use. Fix this later. */
2249 rtx addr = XEXP (operands[0], 0);
2250 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2252 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2254 operands[0] = XEXP (addr, 0);
2255 gcc_assert (GET_CODE (operands[1]) == REG
2256 && GET_CODE (operands[0]) == REG);
2258 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2260 /* No overlap between high target register and address
2261 register. (We do this in a non-obvious way to
2262 save a register file writeback) */
2263 if (GET_CODE (addr) == POST_INC)
2264 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2265 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2267 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2269 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2271 operands[0] = XEXP (addr, 0);
2272 gcc_assert (GET_CODE (operands[1]) == REG
2273 && GET_CODE (operands[0]) == REG);
2275 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2276 /* No overlap between high target register and address
2277 register. (We do this in a non-obvious way to save a
2278 register file writeback) */
2279 if (GET_CODE (addr) == PRE_INC)
2280 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2281 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2284 if (optype1 == MEMOP)
2286 /* We have to output the address syntax ourselves, since print_operand
2287 doesn't deal with the addresses we want to use. Fix this later. */
2289 rtx addr = XEXP (operands[1], 0);
2290 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2292 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2294 operands[1] = XEXP (addr, 0);
2295 gcc_assert (GET_CODE (operands[0]) == REG
2296 && GET_CODE (operands[1]) == REG);
2298 if (!reg_overlap_mentioned_p (high_reg, addr))
2300 /* No overlap between high target register and address
2301 register. (We do this in a non-obvious way to
2302 save a register file writeback) */
2303 if (GET_CODE (addr) == POST_INC)
2304 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2305 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2309 /* This is an undefined situation. We should load into the
2310 address register *and* update that register. Probably
2311 we don't need to handle this at all. */
2312 if (GET_CODE (addr) == POST_INC)
2313 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2314 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2317 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2319 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2321 operands[1] = XEXP (addr, 0);
2322 gcc_assert (GET_CODE (operands[0]) == REG
2323 && GET_CODE (operands[1]) == REG);
2325 if (!reg_overlap_mentioned_p (high_reg, addr))
2327 /* No overlap between high target register and address
2328 register. (We do this in a non-obvious way to
2329 save a register file writeback) */
2330 if (GET_CODE (addr) == PRE_INC)
2331 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2332 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2336 /* This is an undefined situation. We should load into the
2337 address register *and* update that register. Probably
2338 we don't need to handle this at all. */
2339 if (GET_CODE (addr) == PRE_INC)
2340 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2341 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2344 else if (GET_CODE (addr) == PLUS
2345 && GET_CODE (XEXP (addr, 0)) == MULT)
2348 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2350 if (!reg_overlap_mentioned_p (high_reg, addr))
2352 xoperands[0] = high_reg;
2353 xoperands[1] = XEXP (addr, 1);
2354 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2355 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2356 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2358 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2362 xoperands[0] = high_reg;
2363 xoperands[1] = XEXP (addr, 1);
2364 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2365 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2366 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2368 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2373 /* If an operand is an unoffsettable memory ref, find a register
2374 we can increment temporarily to make it refer to the second word. */
2376 if (optype0 == MEMOP)
2377 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2379 if (optype1 == MEMOP)
2380 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2382 /* Ok, we can do one word at a time.
2383 Normally we do the low-numbered word first.
2385 In either case, set up in LATEHALF the operands to use
2386 for the high-numbered word and in some cases alter the
2387 operands in OPERANDS to be suitable for the low-numbered word. */
2389 if (optype0 == REGOP)
2390 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2391 else if (optype0 == OFFSOP)
2392 latehalf[0] = adjust_address (operands[0], SImode, 4);
2394 latehalf[0] = operands[0];
2396 if (optype1 == REGOP)
2397 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2398 else if (optype1 == OFFSOP)
2399 latehalf[1] = adjust_address (operands[1], SImode, 4);
2400 else if (optype1 == CNSTOP)
2401 split_double (operands[1], &operands[1], &latehalf[1]);
2403 latehalf[1] = operands[1];
2405 /* If the first move would clobber the source of the second one,
2406 do them in the other order.
2408 This can happen in two cases:
2410 mem -> register where the first half of the destination register
2411 is the same register used in the memory's address. Reload
2412 can create such insns.
2414 mem in this case will be either register indirect or register
2415 indirect plus a valid offset.
2417 register -> register move where REGNO(dst) == REGNO(src + 1)
2418 someone (Tim/Tege?) claimed this can happen for parameter loads.
2420 Handle mem -> register case first. */
2421 if (optype0 == REGOP
2422 && (optype1 == MEMOP || optype1 == OFFSOP)
2423 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2426 /* Do the late half first. */
2428 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2429 output_asm_insn (singlemove_string (latehalf), latehalf);
2433 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2434 return singlemove_string (operands);
2437 /* Now handle register -> register case. */
2438 if (optype0 == REGOP && optype1 == REGOP
2439 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2441 output_asm_insn (singlemove_string (latehalf), latehalf);
2442 return singlemove_string (operands);
2445 /* Normal case: do the two words, low-numbered first. */
2447 output_asm_insn (singlemove_string (operands), operands);
2449 /* Make any unoffsettable addresses point at high-numbered word. */
2451 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2453 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2456 output_asm_insn (singlemove_string (latehalf), latehalf);
2458 /* Undo the adds we just did. */
2460 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2462 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2468 output_fp_move_double (rtx *operands)
2470 if (FP_REG_P (operands[0]))
2472 if (FP_REG_P (operands[1])
2473 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2474 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2476 output_asm_insn ("fldd%F1 %1,%0", operands);
2478 else if (FP_REG_P (operands[1]))
2480 output_asm_insn ("fstd%F0 %1,%0", operands);
2486 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2488 /* This is a pain. You have to be prepared to deal with an
2489 arbitrary address here including pre/post increment/decrement.
2491 so avoid this in the MD. */
2492 gcc_assert (GET_CODE (operands[0]) == REG);
2494 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2495 xoperands[0] = operands[0];
2496 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2501 /* Return a REG that occurs in ADDR with coefficient 1.
2502 ADDR can be effectively incremented by incrementing REG. */
2505 find_addr_reg (rtx addr)
2507 while (GET_CODE (addr) == PLUS)
2509 if (GET_CODE (XEXP (addr, 0)) == REG)
2510 addr = XEXP (addr, 0);
2511 else if (GET_CODE (XEXP (addr, 1)) == REG)
2512 addr = XEXP (addr, 1);
2513 else if (CONSTANT_P (XEXP (addr, 0)))
2514 addr = XEXP (addr, 1);
2515 else if (CONSTANT_P (XEXP (addr, 1)))
2516 addr = XEXP (addr, 0);
2520 gcc_assert (GET_CODE (addr) == REG);
2524 /* Emit code to perform a block move.
2526 OPERANDS[0] is the destination pointer as a REG, clobbered.
2527 OPERANDS[1] is the source pointer as a REG, clobbered.
2528 OPERANDS[2] is a register for temporary storage.
2529 OPERANDS[3] is a register for temporary storage.
2530 OPERANDS[4] is the size as a CONST_INT
2531 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2532 OPERANDS[6] is another temporary register. */
2535 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2537 int align = INTVAL (operands[5]);
2538 unsigned long n_bytes = INTVAL (operands[4]);
2540 /* We can't move more than a word at a time because the PA
2541 has no longer integer move insns. (Could use fp mem ops?) */
2542 if (align > (TARGET_64BIT ? 8 : 4))
2543 align = (TARGET_64BIT ? 8 : 4);
2545 /* Note that we know each loop below will execute at least twice
2546 (else we would have open-coded the copy). */
2550 /* Pre-adjust the loop counter. */
2551 operands[4] = GEN_INT (n_bytes - 16);
2552 output_asm_insn ("ldi %4,%2", operands);
2555 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2556 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2557 output_asm_insn ("std,ma %3,8(%0)", operands);
2558 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2559 output_asm_insn ("std,ma %6,8(%0)", operands);
2561 /* Handle the residual. There could be up to 7 bytes of
2562 residual to copy! */
2563 if (n_bytes % 16 != 0)
2565 operands[4] = GEN_INT (n_bytes % 8);
2566 if (n_bytes % 16 >= 8)
2567 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2568 if (n_bytes % 8 != 0)
2569 output_asm_insn ("ldd 0(%1),%6", operands);
2570 if (n_bytes % 16 >= 8)
2571 output_asm_insn ("std,ma %3,8(%0)", operands);
2572 if (n_bytes % 8 != 0)
2573 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2578 /* Pre-adjust the loop counter. */
2579 operands[4] = GEN_INT (n_bytes - 8);
2580 output_asm_insn ("ldi %4,%2", operands);
2583 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2584 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2585 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2586 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2587 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2589 /* Handle the residual. There could be up to 7 bytes of
2590 residual to copy! */
2591 if (n_bytes % 8 != 0)
2593 operands[4] = GEN_INT (n_bytes % 4);
2594 if (n_bytes % 8 >= 4)
2595 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2596 if (n_bytes % 4 != 0)
2597 output_asm_insn ("ldw 0(%1),%6", operands);
2598 if (n_bytes % 8 >= 4)
2599 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2600 if (n_bytes % 4 != 0)
2601 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2606 /* Pre-adjust the loop counter. */
2607 operands[4] = GEN_INT (n_bytes - 4);
2608 output_asm_insn ("ldi %4,%2", operands);
2611 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2612 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2613 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2614 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2615 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2617 /* Handle the residual. */
2618 if (n_bytes % 4 != 0)
2620 if (n_bytes % 4 >= 2)
2621 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2622 if (n_bytes % 2 != 0)
2623 output_asm_insn ("ldb 0(%1),%6", operands);
2624 if (n_bytes % 4 >= 2)
2625 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2626 if (n_bytes % 2 != 0)
2627 output_asm_insn ("stb %6,0(%0)", operands);
2632 /* Pre-adjust the loop counter. */
2633 operands[4] = GEN_INT (n_bytes - 2);
2634 output_asm_insn ("ldi %4,%2", operands);
2637 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2638 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2639 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2640 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2641 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2643 /* Handle the residual. */
2644 if (n_bytes % 2 != 0)
2646 output_asm_insn ("ldb 0(%1),%3", operands);
2647 output_asm_insn ("stb %3,0(%0)", operands);
2656 /* Count the number of insns necessary to handle this block move.
2658 Basic structure is the same as emit_block_move, except that we
2659 count insns rather than emit them. */
2662 compute_movmem_length (rtx insn)
2664 rtx pat = PATTERN (insn);
2665 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2666 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2667 unsigned int n_insns = 0;
2669 /* We can't move more than four bytes at a time because the PA
2670 has no longer integer move insns. (Could use fp mem ops?) */
2671 if (align > (TARGET_64BIT ? 8 : 4))
2672 align = (TARGET_64BIT ? 8 : 4);
2674 /* The basic copying loop. */
2678 if (n_bytes % (2 * align) != 0)
2680 if ((n_bytes % (2 * align)) >= align)
2683 if ((n_bytes % align) != 0)
2687 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2691 /* Emit code to perform a block clear.
2693 OPERANDS[0] is the destination pointer as a REG, clobbered.
2694 OPERANDS[1] is a register for temporary storage.
2695 OPERANDS[2] is the size as a CONST_INT
2696 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2699 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2701 int align = INTVAL (operands[3]);
2702 unsigned long n_bytes = INTVAL (operands[2]);
2704 /* We can't clear more than a word at a time because the PA
2705 has no longer integer move insns. */
2706 if (align > (TARGET_64BIT ? 8 : 4))
2707 align = (TARGET_64BIT ? 8 : 4);
2709 /* Note that we know each loop below will execute at least twice
2710 (else we would have open-coded the copy). */
2714 /* Pre-adjust the loop counter. */
2715 operands[2] = GEN_INT (n_bytes - 16);
2716 output_asm_insn ("ldi %2,%1", operands);
2719 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2720 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2721 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2723 /* Handle the residual. There could be up to 7 bytes of
2724 residual to copy! */
2725 if (n_bytes % 16 != 0)
2727 operands[2] = GEN_INT (n_bytes % 8);
2728 if (n_bytes % 16 >= 8)
2729 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2730 if (n_bytes % 8 != 0)
2731 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2736 /* Pre-adjust the loop counter. */
2737 operands[2] = GEN_INT (n_bytes - 8);
2738 output_asm_insn ("ldi %2,%1", operands);
2741 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2742 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2743 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2745 /* Handle the residual. There could be up to 7 bytes of
2746 residual to copy! */
2747 if (n_bytes % 8 != 0)
2749 operands[2] = GEN_INT (n_bytes % 4);
2750 if (n_bytes % 8 >= 4)
2751 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2752 if (n_bytes % 4 != 0)
2753 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2758 /* Pre-adjust the loop counter. */
2759 operands[2] = GEN_INT (n_bytes - 4);
2760 output_asm_insn ("ldi %2,%1", operands);
2763 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2764 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2765 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2767 /* Handle the residual. */
2768 if (n_bytes % 4 != 0)
2770 if (n_bytes % 4 >= 2)
2771 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2772 if (n_bytes % 2 != 0)
2773 output_asm_insn ("stb %%r0,0(%0)", operands);
2778 /* Pre-adjust the loop counter. */
2779 operands[2] = GEN_INT (n_bytes - 2);
2780 output_asm_insn ("ldi %2,%1", operands);
2783 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2784 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2785 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2787 /* Handle the residual. */
2788 if (n_bytes % 2 != 0)
2789 output_asm_insn ("stb %%r0,0(%0)", operands);
2798 /* Count the number of insns necessary to handle this block move.
2800 Basic structure is the same as emit_block_move, except that we
2801 count insns rather than emit them. */
2804 compute_clrmem_length (rtx insn)
2806 rtx pat = PATTERN (insn);
2807 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2808 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2809 unsigned int n_insns = 0;
2811 /* We can't clear more than a word at a time because the PA
2812 has no longer integer move insns. */
2813 if (align > (TARGET_64BIT ? 8 : 4))
2814 align = (TARGET_64BIT ? 8 : 4);
2816 /* The basic loop. */
2820 if (n_bytes % (2 * align) != 0)
2822 if ((n_bytes % (2 * align)) >= align)
2825 if ((n_bytes % align) != 0)
2829 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2835 output_and (rtx *operands)
2837 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2839 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2840 int ls0, ls1, ms0, p, len;
2842 for (ls0 = 0; ls0 < 32; ls0++)
2843 if ((mask & (1 << ls0)) == 0)
2846 for (ls1 = ls0; ls1 < 32; ls1++)
2847 if ((mask & (1 << ls1)) != 0)
2850 for (ms0 = ls1; ms0 < 32; ms0++)
2851 if ((mask & (1 << ms0)) == 0)
2854 gcc_assert (ms0 == 32);
2862 operands[2] = GEN_INT (len);
2863 return "{extru|extrw,u} %1,31,%2,%0";
2867 /* We could use this `depi' for the case above as well, but `depi'
2868 requires one more register file access than an `extru'. */
2873 operands[2] = GEN_INT (p);
2874 operands[3] = GEN_INT (len);
2875 return "{depi|depwi} 0,%2,%3,%0";
2879 return "and %1,%2,%0";
2882 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2883 storing the result in operands[0]. */
2885 output_64bit_and (rtx *operands)
2887 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2889 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2890 int ls0, ls1, ms0, p, len;
2892 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2893 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2896 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2897 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2900 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2901 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2904 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2906 if (ls1 == HOST_BITS_PER_WIDE_INT)
2912 operands[2] = GEN_INT (len);
2913 return "extrd,u %1,63,%2,%0";
2917 /* We could use this `depi' for the case above as well, but `depi'
2918 requires one more register file access than an `extru'. */
2923 operands[2] = GEN_INT (p);
2924 operands[3] = GEN_INT (len);
2925 return "depdi 0,%2,%3,%0";
2929 return "and %1,%2,%0";
2933 output_ior (rtx *operands)
2935 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2936 int bs0, bs1, p, len;
2938 if (INTVAL (operands[2]) == 0)
2939 return "copy %1,%0";
2941 for (bs0 = 0; bs0 < 32; bs0++)
2942 if ((mask & (1 << bs0)) != 0)
2945 for (bs1 = bs0; bs1 < 32; bs1++)
2946 if ((mask & (1 << bs1)) == 0)
2949 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2954 operands[2] = GEN_INT (p);
2955 operands[3] = GEN_INT (len);
2956 return "{depi|depwi} -1,%2,%3,%0";
2959 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2960 storing the result in operands[0]. */
2962 output_64bit_ior (rtx *operands)
2964 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2965 int bs0, bs1, p, len;
2967 if (INTVAL (operands[2]) == 0)
2968 return "copy %1,%0";
2970 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2971 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2974 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2975 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2978 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2979 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2984 operands[2] = GEN_INT (p);
2985 operands[3] = GEN_INT (len);
2986 return "depdi -1,%2,%3,%0";
2989 /* Target hook for assembling integer objects. This code handles
2990 aligned SI and DI integers specially since function references
2991 must be preceded by P%. */
2994 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2996 if (size == UNITS_PER_WORD
2998 && function_label_operand (x, VOIDmode))
3000 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3001 output_addr_const (asm_out_file, x);
3002 fputc ('\n', asm_out_file);
3005 return default_assemble_integer (x, size, aligned_p);
3008 /* Output an ascii string. */
3010 output_ascii (FILE *file, const char *p, int size)
3014 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3016 /* The HP assembler can only take strings of 256 characters at one
3017 time. This is a limitation on input line length, *not* the
3018 length of the string. Sigh. Even worse, it seems that the
3019 restriction is in number of input characters (see \xnn &
3020 \whatever). So we have to do this very carefully. */
3022 fputs ("\t.STRING \"", file);
3025 for (i = 0; i < size; i += 4)
3029 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3031 register unsigned int c = (unsigned char) p[i + io];
3033 if (c == '\"' || c == '\\')
3034 partial_output[co++] = '\\';
3035 if (c >= ' ' && c < 0177)
3036 partial_output[co++] = c;
3040 partial_output[co++] = '\\';
3041 partial_output[co++] = 'x';
3042 hexd = c / 16 - 0 + '0';
3044 hexd -= '9' - 'a' + 1;
3045 partial_output[co++] = hexd;
3046 hexd = c % 16 - 0 + '0';
3048 hexd -= '9' - 'a' + 1;
3049 partial_output[co++] = hexd;
3052 if (chars_output + co > 243)
3054 fputs ("\"\n\t.STRING \"", file);
3057 fwrite (partial_output, 1, (size_t) co, file);
3061 fputs ("\"\n", file);
3064 /* Try to rewrite floating point comparisons & branches to avoid
3065 useless add,tr insns.
3067 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3068 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3069 first attempt to remove useless add,tr insns. It is zero
3070 for the second pass as reorg sometimes leaves bogus REG_DEAD
3073 When CHECK_NOTES is zero we can only eliminate add,tr insns
3074 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3077 remove_useless_addtr_insns (int check_notes)
3080 static int pass = 0;
3082 /* This is fairly cheap, so always run it when optimizing. */
3086 int fbranch_count = 0;
3088 /* Walk all the insns in this function looking for fcmp & fbranch
3089 instructions. Keep track of how many of each we find. */
3090 for (insn = get_insns (); insn; insn = next_insn (insn))
3094 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3095 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3098 tmp = PATTERN (insn);
3100 /* It must be a set. */
3101 if (GET_CODE (tmp) != SET)
3104 /* If the destination is CCFP, then we've found an fcmp insn. */
3105 tmp = SET_DEST (tmp);
3106 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3112 tmp = PATTERN (insn);
3113 /* If this is an fbranch instruction, bump the fbranch counter. */
3114 if (GET_CODE (tmp) == SET
3115 && SET_DEST (tmp) == pc_rtx
3116 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3117 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3118 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3119 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3127 /* Find all floating point compare + branch insns. If possible,
3128 reverse the comparison & the branch to avoid add,tr insns. */
3129 for (insn = get_insns (); insn; insn = next_insn (insn))
3133 /* Ignore anything that isn't an INSN. */
3134 if (GET_CODE (insn) != INSN)
3137 tmp = PATTERN (insn);
3139 /* It must be a set. */
3140 if (GET_CODE (tmp) != SET)
3143 /* The destination must be CCFP, which is register zero. */
3144 tmp = SET_DEST (tmp);
3145 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3148 /* INSN should be a set of CCFP.
3150 See if the result of this insn is used in a reversed FP
3151 conditional branch. If so, reverse our condition and
3152 the branch. Doing so avoids useless add,tr insns. */
3153 next = next_insn (insn);
3156 /* Jumps, calls and labels stop our search. */
3157 if (GET_CODE (next) == JUMP_INSN
3158 || GET_CODE (next) == CALL_INSN
3159 || GET_CODE (next) == CODE_LABEL)
3162 /* As does another fcmp insn. */
3163 if (GET_CODE (next) == INSN
3164 && GET_CODE (PATTERN (next)) == SET
3165 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3166 && REGNO (SET_DEST (PATTERN (next))) == 0)
3169 next = next_insn (next);
3172 /* Is NEXT_INSN a branch? */
3174 && GET_CODE (next) == JUMP_INSN)
3176 rtx pattern = PATTERN (next);
3178 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3179 and CCFP dies, then reverse our conditional and the branch
3180 to avoid the add,tr. */
3181 if (GET_CODE (pattern) == SET
3182 && SET_DEST (pattern) == pc_rtx
3183 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3184 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3185 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3186 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3187 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3188 && (fcmp_count == fbranch_count
3190 && find_regno_note (next, REG_DEAD, 0))))
3192 /* Reverse the branch. */
3193 tmp = XEXP (SET_SRC (pattern), 1);
3194 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3195 XEXP (SET_SRC (pattern), 2) = tmp;
3196 INSN_CODE (next) = -1;
3198 /* Reverse our condition. */
3199 tmp = PATTERN (insn);
3200 PUT_CODE (XEXP (tmp, 1),
3201 (reverse_condition_maybe_unordered
3202 (GET_CODE (XEXP (tmp, 1)))));
3212 /* You may have trouble believing this, but this is the 32 bit HP-PA
3217 Variable arguments (optional; any number may be allocated)
3219 SP-(4*(N+9)) arg word N
3224 Fixed arguments (must be allocated; may remain unused)
3233 SP-32 External Data Pointer (DP)
3235 SP-24 External/stub RP (RP')
3239 SP-8 Calling Stub RP (RP'')
3244 SP-0 Stack Pointer (points to next available address)
3248 /* This function saves registers as follows. Registers marked with ' are
3249 this function's registers (as opposed to the previous function's).
3250 If a frame_pointer isn't needed, r4 is saved as a general register;
3251 the space for the frame pointer is still allocated, though, to keep
3257 SP (FP') Previous FP
3258 SP + 4 Alignment filler (sigh)
3259 SP + 8 Space for locals reserved here.
3263 SP + n All call saved register used.
3267 SP + o All call saved fp registers used.
3271 SP + p (SP') points to next available address.
3275 /* Global variables set by output_function_prologue(). */
3276 /* Size of frame. Need to know this to emit return insns from
3278 static HOST_WIDE_INT actual_fsize, local_fsize;
3279 static int save_fregs;
3281 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3282 Handle case where DISP > 8k by using the add_high_const patterns.
3284 Note in DISP > 8k case, we will leave the high part of the address
3285 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3288 store_reg (int reg, HOST_WIDE_INT disp, int base)
3290 rtx insn, dest, src, basereg;
3292 src = gen_rtx_REG (word_mode, reg);
3293 basereg = gen_rtx_REG (Pmode, base);
3294 if (VAL_14_BITS_P (disp))
3296 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3297 insn = emit_move_insn (dest, src);
3299 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3301 rtx delta = GEN_INT (disp);
3302 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3304 emit_move_insn (tmpreg, delta);
3305 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3309 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3310 gen_rtx_SET (VOIDmode, tmpreg,
3311 gen_rtx_PLUS (Pmode, basereg, delta)),
3313 RTX_FRAME_RELATED_P (insn) = 1;
3315 dest = gen_rtx_MEM (word_mode, tmpreg);
3316 insn = emit_move_insn (dest, src);
3320 rtx delta = GEN_INT (disp);
3321 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3322 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3324 emit_move_insn (tmpreg, high);
3325 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3326 insn = emit_move_insn (dest, src);
3330 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3331 gen_rtx_SET (VOIDmode,
3332 gen_rtx_MEM (word_mode,
3333 gen_rtx_PLUS (word_mode, basereg,
3341 RTX_FRAME_RELATED_P (insn) = 1;
3344 /* Emit RTL to store REG at the memory location specified by BASE and then
3345 add MOD to BASE. MOD must be <= 8k. */
3348 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3350 rtx insn, basereg, srcreg, delta;
3352 gcc_assert (VAL_14_BITS_P (mod));
3354 basereg = gen_rtx_REG (Pmode, base);
3355 srcreg = gen_rtx_REG (word_mode, reg);
3356 delta = GEN_INT (mod);
3358 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3361 RTX_FRAME_RELATED_P (insn) = 1;
3363 /* RTX_FRAME_RELATED_P must be set on each frame related set
3364 in a parallel with more than one element. */
3365 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3366 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3370 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3371 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3372 whether to add a frame note or not.
3374 In the DISP > 8k case, we leave the high part of the address in %r1.
3375 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3378 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3382 if (VAL_14_BITS_P (disp))
3384 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3385 plus_constant (gen_rtx_REG (Pmode, base), disp));
3387 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3389 rtx basereg = gen_rtx_REG (Pmode, base);
3390 rtx delta = GEN_INT (disp);
3391 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3393 emit_move_insn (tmpreg, delta);
3394 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3395 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3398 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3399 gen_rtx_SET (VOIDmode, tmpreg,
3400 gen_rtx_PLUS (Pmode, basereg, delta)),
3405 rtx basereg = gen_rtx_REG (Pmode, base);
3406 rtx delta = GEN_INT (disp);
3407 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3409 emit_move_insn (tmpreg,
3410 gen_rtx_PLUS (Pmode, basereg,
3411 gen_rtx_HIGH (Pmode, delta)));
3412 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3413 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3416 if (DO_FRAME_NOTES && note)
3417 RTX_FRAME_RELATED_P (insn) = 1;
3421 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3426 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3427 be consistent with the rounding and size calculation done here.
3428 Change them at the same time. */
3430 /* We do our own stack alignment. First, round the size of the
3431 stack locals up to a word boundary. */
3432 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3434 /* Space for previous frame pointer + filler. If any frame is
3435 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3436 waste some space here for the sake of HP compatibility. The
3437 first slot is only used when the frame pointer is needed. */
3438 if (size || frame_pointer_needed)
3439 size += STARTING_FRAME_OFFSET;
3441 /* If the current function calls __builtin_eh_return, then we need
3442 to allocate stack space for registers that will hold data for
3443 the exception handler. */
3444 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3448 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3450 size += i * UNITS_PER_WORD;
3453 /* Account for space used by the callee general register saves. */
3454 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3455 if (regs_ever_live[i])
3456 size += UNITS_PER_WORD;
3458 /* Account for space used by the callee floating point register saves. */
3459 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3460 if (regs_ever_live[i]
3461 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3465 /* We always save both halves of the FP register, so always
3466 increment the frame size by 8 bytes. */
3470 /* If any of the floating registers are saved, account for the
3471 alignment needed for the floating point register save block. */
3474 size = (size + 7) & ~7;
3479 /* The various ABIs include space for the outgoing parameters in the
3480 size of the current function's stack frame. We don't need to align
3481 for the outgoing arguments as their alignment is set by the final
3482 rounding for the frame as a whole. */
3483 size += current_function_outgoing_args_size;
3485 /* Allocate space for the fixed frame marker. This space must be
3486 allocated for any function that makes calls or allocates
3488 if (!current_function_is_leaf || size)
3489 size += TARGET_64BIT ? 48 : 32;
3491 /* Finally, round to the preferred stack boundary. */
3492 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3493 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3496 /* Generate the assembly code for function entry. FILE is a stdio
3497 stream to output the code to. SIZE is an int: how many units of
3498 temporary storage to allocate.
3500 Refer to the array `regs_ever_live' to determine which registers to
3501 save; `regs_ever_live[I]' is nonzero if register number I is ever
3502 used in the function. This function is responsible for knowing
3503 which registers should not be saved even if used. */
3505 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3506 of memory. If any fpu reg is used in the function, we allocate
3507 such a block here, at the bottom of the frame, just in case it's needed.
3509 If this function is a leaf procedure, then we may choose not
3510 to do a "save" insn. The decision about whether or not
3511 to do this is made in regclass.c. */
3514 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3516 /* The function's label and associated .PROC must never be
3517 separated and must be output *after* any profiling declarations
3518 to avoid changing spaces/subspaces within a procedure. */
3519 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3520 fputs ("\t.PROC\n", file);
3522 /* hppa_expand_prologue does the dirty work now. We just need
3523 to output the assembler directives which denote the start
3525 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3526 if (regs_ever_live[2])
3527 fputs (",CALLS,SAVE_RP", file);
3529 fputs (",NO_CALLS", file);
3531 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3532 at the beginning of the frame and that it is used as the frame
3533 pointer for the frame. We do this because our current frame
3534 layout doesn't conform to that specified in the HP runtime
3535 documentation and we need a way to indicate to programs such as
3536 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3537 isn't used by HP compilers but is supported by the assembler.
3538 However, SAVE_SP is supposed to indicate that the previous stack
3539 pointer has been saved in the frame marker. */
3540 if (frame_pointer_needed)
3541 fputs (",SAVE_SP", file);
3543 /* Pass on information about the number of callee register saves
3544 performed in the prologue.
3546 The compiler is supposed to pass the highest register number
3547 saved, the assembler then has to adjust that number before
3548 entering it into the unwind descriptor (to account for any
3549 caller saved registers with lower register numbers than the
3550 first callee saved register). */
3552 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3555 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3557 fputs ("\n\t.ENTRY\n", file);
3559 remove_useless_addtr_insns (0);
3563 hppa_expand_prologue (void)
3565 int merge_sp_adjust_with_store = 0;
3566 HOST_WIDE_INT size = get_frame_size ();
3567 HOST_WIDE_INT offset;
3575 /* Compute total size for frame pointer, filler, locals and rounding to
3576 the next word boundary. Similar code appears in compute_frame_size
3577 and must be changed in tandem with this code. */
3578 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3579 if (local_fsize || frame_pointer_needed)
3580 local_fsize += STARTING_FRAME_OFFSET;
3582 actual_fsize = compute_frame_size (size, &save_fregs);
3584 /* Compute a few things we will use often. */
3585 tmpreg = gen_rtx_REG (word_mode, 1);
3587 /* Save RP first. The calling conventions manual states RP will
3588 always be stored into the caller's frame at sp - 20 or sp - 16
3589 depending on which ABI is in use. */
3590 if (regs_ever_live[2] || current_function_calls_eh_return)
3591 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3593 /* Allocate the local frame and set up the frame pointer if needed. */
3594 if (actual_fsize != 0)
3596 if (frame_pointer_needed)
3598 /* Copy the old frame pointer temporarily into %r1. Set up the
3599 new stack pointer, then store away the saved old frame pointer
3600 into the stack at sp and at the same time update the stack
3601 pointer by actual_fsize bytes. Two versions, first
3602 handles small (<8k) frames. The second handles large (>=8k)
3604 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3606 RTX_FRAME_RELATED_P (insn) = 1;
3608 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3610 RTX_FRAME_RELATED_P (insn) = 1;
3612 if (VAL_14_BITS_P (actual_fsize))
3613 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3616 /* It is incorrect to store the saved frame pointer at *sp,
3617 then increment sp (writes beyond the current stack boundary).
3619 So instead use stwm to store at *sp and post-increment the
3620 stack pointer as an atomic operation. Then increment sp to
3621 finish allocating the new frame. */
3622 HOST_WIDE_INT adjust1 = 8192 - 64;
3623 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3625 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3626 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3630 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3631 we need to store the previous stack pointer (frame pointer)
3632 into the frame marker on targets that use the HP unwind
3633 library. This allows the HP unwind library to be used to
3634 unwind GCC frames. However, we are not fully compatible
3635 with the HP library because our frame layout differs from
3636 that specified in the HP runtime specification.
3638 We don't want a frame note on this instruction as the frame
3639 marker moves during dynamic stack allocation.
3641 This instruction also serves as a blockage to prevent
3642 register spills from being scheduled before the stack
3643 pointer is raised. This is necessary as we store
3644 registers using the frame pointer as a base register,
3645 and the frame pointer is set before sp is raised. */
3646 if (TARGET_HPUX_UNWIND_LIBRARY)
3648 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3649 GEN_INT (TARGET_64BIT ? -8 : -4));
3651 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3655 emit_insn (gen_blockage ());
3657 /* no frame pointer needed. */
3660 /* In some cases we can perform the first callee register save
3661 and allocating the stack frame at the same time. If so, just
3662 make a note of it and defer allocating the frame until saving
3663 the callee registers. */
3664 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3665 merge_sp_adjust_with_store = 1;
3666 /* Can not optimize. Adjust the stack frame by actual_fsize
3669 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3674 /* Normal register save.
3676 Do not save the frame pointer in the frame_pointer_needed case. It
3677 was done earlier. */
3678 if (frame_pointer_needed)
3680 offset = local_fsize;
3682 /* Saving the EH return data registers in the frame is the simplest
3683 way to get the frame unwind information emitted. We put them
3684 just before the general registers. */
3685 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3687 unsigned int i, regno;
3691 regno = EH_RETURN_DATA_REGNO (i);
3692 if (regno == INVALID_REGNUM)
3695 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3696 offset += UNITS_PER_WORD;
3700 for (i = 18; i >= 4; i--)
3701 if (regs_ever_live[i] && ! call_used_regs[i])
3703 store_reg (i, offset, FRAME_POINTER_REGNUM);
3704 offset += UNITS_PER_WORD;
3707 /* Account for %r3 which is saved in a special place. */
3710 /* No frame pointer needed. */
3713 offset = local_fsize - actual_fsize;
3715 /* Saving the EH return data registers in the frame is the simplest
3716 way to get the frame unwind information emitted. */
3717 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3719 unsigned int i, regno;
3723 regno = EH_RETURN_DATA_REGNO (i);
3724 if (regno == INVALID_REGNUM)
3727 /* If merge_sp_adjust_with_store is nonzero, then we can
3728 optimize the first save. */
3729 if (merge_sp_adjust_with_store)
3731 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3732 merge_sp_adjust_with_store = 0;
3735 store_reg (regno, offset, STACK_POINTER_REGNUM);
3736 offset += UNITS_PER_WORD;
3740 for (i = 18; i >= 3; i--)
3741 if (regs_ever_live[i] && ! call_used_regs[i])
3743 /* If merge_sp_adjust_with_store is nonzero, then we can
3744 optimize the first GR save. */
3745 if (merge_sp_adjust_with_store)
3747 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3748 merge_sp_adjust_with_store = 0;
3751 store_reg (i, offset, STACK_POINTER_REGNUM);
3752 offset += UNITS_PER_WORD;
3756 /* If we wanted to merge the SP adjustment with a GR save, but we never
3757 did any GR saves, then just emit the adjustment here. */
3758 if (merge_sp_adjust_with_store)
3759 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3763 /* The hppa calling conventions say that %r19, the pic offset
3764 register, is saved at sp - 32 (in this function's frame)
3765 when generating PIC code. FIXME: What is the correct thing
3766 to do for functions which make no calls and allocate no
3767 frame? Do we need to allocate a frame, or can we just omit
3768 the save? For now we'll just omit the save.
3770 We don't want a note on this insn as the frame marker can
3771 move if there is a dynamic stack allocation. */
3772 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3774 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3776 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3780 /* Align pointer properly (doubleword boundary). */
3781 offset = (offset + 7) & ~7;
3783 /* Floating point register store. */
3788 /* First get the frame or stack pointer to the start of the FP register
3790 if (frame_pointer_needed)
3792 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3793 base = frame_pointer_rtx;
3797 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3798 base = stack_pointer_rtx;
3801 /* Now actually save the FP registers. */
3802 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3804 if (regs_ever_live[i]
3805 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3807 rtx addr, insn, reg;
3808 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3809 reg = gen_rtx_REG (DFmode, i);
3810 insn = emit_move_insn (addr, reg);
3813 RTX_FRAME_RELATED_P (insn) = 1;
3816 rtx mem = gen_rtx_MEM (DFmode,
3817 plus_constant (base, offset));
3819 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3820 gen_rtx_SET (VOIDmode, mem, reg),
3825 rtx meml = gen_rtx_MEM (SFmode,
3826 plus_constant (base, offset));
3827 rtx memr = gen_rtx_MEM (SFmode,
3828 plus_constant (base, offset + 4));
3829 rtx regl = gen_rtx_REG (SFmode, i);
3830 rtx regr = gen_rtx_REG (SFmode, i + 1);
3831 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3832 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3835 RTX_FRAME_RELATED_P (setl) = 1;
3836 RTX_FRAME_RELATED_P (setr) = 1;
3837 vec = gen_rtvec (2, setl, setr);
3839 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3840 gen_rtx_SEQUENCE (VOIDmode, vec),
3844 offset += GET_MODE_SIZE (DFmode);
3851 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3852 Handle case where DISP > 8k by using the add_high_const patterns. */
3855 load_reg (int reg, HOST_WIDE_INT disp, int base)
3857 rtx dest = gen_rtx_REG (word_mode, reg);
3858 rtx basereg = gen_rtx_REG (Pmode, base);
3861 if (VAL_14_BITS_P (disp))
3862 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3863 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3865 rtx delta = GEN_INT (disp);
3866 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3868 emit_move_insn (tmpreg, delta);
3869 if (TARGET_DISABLE_INDEXING)
3871 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3872 src = gen_rtx_MEM (word_mode, tmpreg);
3875 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3879 rtx delta = GEN_INT (disp);
3880 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3881 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3883 emit_move_insn (tmpreg, high);
3884 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3887 emit_move_insn (dest, src);
3890 /* Update the total code bytes output to the text section. */
3893 update_total_code_bytes (int nbytes)
3895 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3896 && !IN_NAMED_SECTION_P (cfun->decl))
3898 if (INSN_ADDRESSES_SET_P ())
3900 unsigned long old_total = total_code_bytes;
3902 total_code_bytes += nbytes;
3904 /* Be prepared to handle overflows. */
3905 if (old_total > total_code_bytes)
3906 total_code_bytes = -1;
3909 total_code_bytes = -1;
3913 /* This function generates the assembly code for function exit.
3914 Args are as for output_function_prologue ().
3916 The function epilogue should not depend on the current stack
3917 pointer! It should use the frame pointer only. This is mandatory
3918 because of alloca; we also take advantage of it to omit stack
3919 adjustments before returning. */
3922 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3924 rtx insn = get_last_insn ();
3928 /* hppa_expand_epilogue does the dirty work now. We just need
3929 to output the assembler directives which denote the end
3932 To make debuggers happy, emit a nop if the epilogue was completely
3933 eliminated due to a volatile call as the last insn in the
3934 current function. That way the return address (in %r2) will
3935 always point to a valid instruction in the current function. */
3937 /* Get the last real insn. */
3938 if (GET_CODE (insn) == NOTE)
3939 insn = prev_real_insn (insn);
3941 /* If it is a sequence, then look inside. */
3942 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3943 insn = XVECEXP (PATTERN (insn), 0, 0);
3945 /* If insn is a CALL_INSN, then it must be a call to a volatile
3946 function (otherwise there would be epilogue insns). */
3947 if (insn && GET_CODE (insn) == CALL_INSN)
3949 fputs ("\tnop\n", file);
3953 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3955 if (TARGET_SOM && TARGET_GAS)
3957 /* We done with this subspace except possibly for some additional
3958 debug information. Forget that we are in this subspace to ensure
3959 that the next function is output in its own subspace. */
3961 cfun->machine->in_nsubspa = 2;
3964 if (INSN_ADDRESSES_SET_P ())
3966 insn = get_last_nonnote_insn ();
3967 last_address += INSN_ADDRESSES (INSN_UID (insn));
3969 last_address += insn_default_length (insn);
3970 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3971 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3974 /* Finally, update the total number of code bytes output so far. */
3975 update_total_code_bytes (last_address);
3979 hppa_expand_epilogue (void)
3982 HOST_WIDE_INT offset;
3983 HOST_WIDE_INT ret_off = 0;
3985 int merge_sp_adjust_with_load = 0;
3987 /* We will use this often. */
3988 tmpreg = gen_rtx_REG (word_mode, 1);
3990 /* Try to restore RP early to avoid load/use interlocks when
3991 RP gets used in the return (bv) instruction. This appears to still
3992 be necessary even when we schedule the prologue and epilogue. */
3993 if (regs_ever_live [2] || current_function_calls_eh_return)
3995 ret_off = TARGET_64BIT ? -16 : -20;
3996 if (frame_pointer_needed)
3998 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4003 /* No frame pointer, and stack is smaller than 8k. */
4004 if (VAL_14_BITS_P (ret_off - actual_fsize))
4006 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4012 /* General register restores. */
4013 if (frame_pointer_needed)
4015 offset = local_fsize;
4017 /* If the current function calls __builtin_eh_return, then we need
4018 to restore the saved EH data registers. */
4019 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4021 unsigned int i, regno;
4025 regno = EH_RETURN_DATA_REGNO (i);
4026 if (regno == INVALID_REGNUM)
4029 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4030 offset += UNITS_PER_WORD;
4034 for (i = 18; i >= 4; i--)
4035 if (regs_ever_live[i] && ! call_used_regs[i])
4037 load_reg (i, offset, FRAME_POINTER_REGNUM);
4038 offset += UNITS_PER_WORD;
4043 offset = local_fsize - actual_fsize;
4045 /* If the current function calls __builtin_eh_return, then we need
4046 to restore the saved EH data registers. */
4047 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4049 unsigned int i, regno;
4053 regno = EH_RETURN_DATA_REGNO (i);
4054 if (regno == INVALID_REGNUM)
4057 /* Only for the first load.
4058 merge_sp_adjust_with_load holds the register load
4059 with which we will merge the sp adjustment. */
4060 if (merge_sp_adjust_with_load == 0
4062 && VAL_14_BITS_P (-actual_fsize))
4063 merge_sp_adjust_with_load = regno;
4065 load_reg (regno, offset, STACK_POINTER_REGNUM);
4066 offset += UNITS_PER_WORD;
4070 for (i = 18; i >= 3; i--)
4072 if (regs_ever_live[i] && ! call_used_regs[i])
4074 /* Only for the first load.
4075 merge_sp_adjust_with_load holds the register load
4076 with which we will merge the sp adjustment. */
4077 if (merge_sp_adjust_with_load == 0
4079 && VAL_14_BITS_P (-actual_fsize))
4080 merge_sp_adjust_with_load = i;
4082 load_reg (i, offset, STACK_POINTER_REGNUM);
4083 offset += UNITS_PER_WORD;
4088 /* Align pointer properly (doubleword boundary). */
4089 offset = (offset + 7) & ~7;
4091 /* FP register restores. */
4094 /* Adjust the register to index off of. */
4095 if (frame_pointer_needed)
4096 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4098 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4100 /* Actually do the restores now. */
4101 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4102 if (regs_ever_live[i]
4103 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4105 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4106 rtx dest = gen_rtx_REG (DFmode, i);
4107 emit_move_insn (dest, src);
4111 /* Emit a blockage insn here to keep these insns from being moved to
4112 an earlier spot in the epilogue, or into the main instruction stream.
4114 This is necessary as we must not cut the stack back before all the
4115 restores are finished. */
4116 emit_insn (gen_blockage ());
4118 /* Reset stack pointer (and possibly frame pointer). The stack
4119 pointer is initially set to fp + 64 to avoid a race condition. */
4120 if (frame_pointer_needed)
4122 rtx delta = GEN_INT (-64);
4124 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4125 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4127 /* If we were deferring a callee register restore, do it now. */
4128 else if (merge_sp_adjust_with_load)
4130 rtx delta = GEN_INT (-actual_fsize);
4131 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4133 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4135 else if (actual_fsize != 0)
4136 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4139 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4140 frame greater than 8k), do so now. */
4142 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4144 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4146 rtx sa = EH_RETURN_STACKADJ_RTX;
4148 emit_insn (gen_blockage ());
4149 emit_insn (TARGET_64BIT
4150 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4151 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4156 hppa_pic_save_rtx (void)
4158 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4161 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4162 #define NO_DEFERRED_PROFILE_COUNTERS 0
4166 /* Vector of funcdef numbers. */
4167 static VEC(int,heap) *funcdef_nos;
4169 /* Output deferred profile counters. */
4171 output_deferred_profile_counters (void)
4176 if (VEC_empty (int, funcdef_nos))
4179 switch_to_section (data_section);
4180 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4181 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4183 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4185 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4186 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4189 VEC_free (int, heap, funcdef_nos);
4193 hppa_profile_hook (int label_no)
4195 /* We use SImode for the address of the function in both 32 and
4196 64-bit code to avoid having to provide DImode versions of the
4197 lcla2 and load_offset_label_address insn patterns. */
4198 rtx reg = gen_reg_rtx (SImode);
4199 rtx label_rtx = gen_label_rtx ();
4200 rtx begin_label_rtx, call_insn;
4201 char begin_label_name[16];
4203 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4205 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4208 emit_move_insn (arg_pointer_rtx,
4209 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4212 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4214 /* The address of the function is loaded into %r25 with a instruction-
4215 relative sequence that avoids the use of relocations. The sequence
4216 is split so that the load_offset_label_address instruction can
4217 occupy the delay slot of the call to _mcount. */
4219 emit_insn (gen_lcla2 (reg, label_rtx));
4221 emit_insn (gen_lcla1 (reg, label_rtx));
4223 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4224 reg, begin_label_rtx, label_rtx));
4226 #if !NO_DEFERRED_PROFILE_COUNTERS
4228 rtx count_label_rtx, addr, r24;
4229 char count_label_name[16];
4231 VEC_safe_push (int, heap, funcdef_nos, label_no);
4232 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4233 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4235 addr = force_reg (Pmode, count_label_rtx);
4236 r24 = gen_rtx_REG (Pmode, 24);
4237 emit_move_insn (r24, addr);
4240 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4241 gen_rtx_SYMBOL_REF (Pmode,
4243 GEN_INT (TARGET_64BIT ? 24 : 12)));
4245 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4250 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4251 gen_rtx_SYMBOL_REF (Pmode,
4253 GEN_INT (TARGET_64BIT ? 16 : 8)));
4257 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4258 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4260 /* Indicate the _mcount call cannot throw, nor will it execute a
4262 REG_NOTES (call_insn)
4263 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4266 /* Fetch the return address for the frame COUNT steps up from
4267 the current frame, after the prologue. FRAMEADDR is the
4268 frame pointer of the COUNT frame.
4270 We want to ignore any export stub remnants here. To handle this,
4271 we examine the code at the return address, and if it is an export
4272 stub, we return a memory rtx for the stub return address stored
4275 The value returned is used in two different ways:
4277 1. To find a function's caller.
4279 2. To change the return address for a function.
4281 This function handles most instances of case 1; however, it will
4282 fail if there are two levels of stubs to execute on the return
4283 path. The only way I believe that can happen is if the return value
4284 needs a parameter relocation, which never happens for C code.
4286 This function handles most instances of case 2; however, it will
4287 fail if we did not originally have stub code on the return path
4288 but will need stub code on the new return path. This can happen if
4289 the caller & callee are both in the main program, but the new
4290 return location is in a shared library. */
4293 return_addr_rtx (int count, rtx frameaddr)
4303 rp = get_hard_reg_initial_val (Pmode, 2);
4305 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4308 saved_rp = gen_reg_rtx (Pmode);
4309 emit_move_insn (saved_rp, rp);
4311 /* Get pointer to the instruction stream. We have to mask out the
4312 privilege level from the two low order bits of the return address
4313 pointer here so that ins will point to the start of the first
4314 instruction that would have been executed if we returned. */
4315 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4316 label = gen_label_rtx ();
4318 /* Check the instruction stream at the normal return address for the
4321 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4322 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4323 0x00011820 | stub+16: mtsp r1,sr0
4324 0xe0400002 | stub+20: be,n 0(sr0,rp)
4326 If it is an export stub, than our return address is really in
4329 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4330 NULL_RTX, SImode, 1);
4331 emit_jump_insn (gen_bne (label));
4333 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4334 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4335 emit_jump_insn (gen_bne (label));
4337 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4338 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4339 emit_jump_insn (gen_bne (label));
4341 /* 0xe0400002 must be specified as -532676606 so that it won't be
4342 rejected as an invalid immediate operand on 64-bit hosts. */
4343 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4344 GEN_INT (-532676606), NE, NULL_RTX, SImode, 1);
4346 /* If there is no export stub then just use the value saved from
4347 the return pointer register. */
4349 emit_jump_insn (gen_bne (label));
4351 /* Here we know that our return address points to an export
4352 stub. We don't want to return the address of the export stub,
4353 but rather the return address of the export stub. That return
4354 address is stored at -24[frameaddr]. */
4356 emit_move_insn (saved_rp,
4358 memory_address (Pmode,
4359 plus_constant (frameaddr,
4366 /* This is only valid once reload has completed because it depends on
4367 knowing exactly how much (if any) frame there is and...
4369 It's only valid if there is no frame marker to de-allocate and...
4371 It's only valid if %r2 hasn't been saved into the caller's frame
4372 (we're not profiling and %r2 isn't live anywhere). */
4374 hppa_can_use_return_insn_p (void)
4376 return (reload_completed
4377 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4378 && ! regs_ever_live[2]
4379 && ! frame_pointer_needed);
4383 emit_bcond_fp (enum rtx_code code, rtx operand0)
4385 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4386 gen_rtx_IF_THEN_ELSE (VOIDmode,
4387 gen_rtx_fmt_ee (code,
4389 gen_rtx_REG (CCFPmode, 0),
4391 gen_rtx_LABEL_REF (VOIDmode, operand0),
4397 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4399 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4400 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4403 /* Adjust the cost of a scheduling dependency. Return the new cost of
4404 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4407 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4409 enum attr_type attr_type;
4411 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4412 true dependencies as they are described with bypasses now. */
4413 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4416 if (! recog_memoized (insn))
4419 attr_type = get_attr_type (insn);
4421 switch (REG_NOTE_KIND (link))
4424 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4427 if (attr_type == TYPE_FPLOAD)
4429 rtx pat = PATTERN (insn);
4430 rtx dep_pat = PATTERN (dep_insn);
4431 if (GET_CODE (pat) == PARALLEL)
4433 /* This happens for the fldXs,mb patterns. */
4434 pat = XVECEXP (pat, 0, 0);
4436 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4437 /* If this happens, we have to extend this to schedule
4438 optimally. Return 0 for now. */
4441 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4443 if (! recog_memoized (dep_insn))
4445 switch (get_attr_type (dep_insn))
4452 case TYPE_FPSQRTSGL:
4453 case TYPE_FPSQRTDBL:
4454 /* A fpload can't be issued until one cycle before a
4455 preceding arithmetic operation has finished if
4456 the target of the fpload is any of the sources
4457 (or destination) of the arithmetic operation. */
4458 return insn_default_latency (dep_insn) - 1;
4465 else if (attr_type == TYPE_FPALU)
4467 rtx pat = PATTERN (insn);
4468 rtx dep_pat = PATTERN (dep_insn);
4469 if (GET_CODE (pat) == PARALLEL)
4471 /* This happens for the fldXs,mb patterns. */
4472 pat = XVECEXP (pat, 0, 0);
4474 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4475 /* If this happens, we have to extend this to schedule
4476 optimally. Return 0 for now. */
4479 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4481 if (! recog_memoized (dep_insn))
4483 switch (get_attr_type (dep_insn))
4487 case TYPE_FPSQRTSGL:
4488 case TYPE_FPSQRTDBL:
4489 /* An ALU flop can't be issued until two cycles before a
4490 preceding divide or sqrt operation has finished if
4491 the target of the ALU flop is any of the sources
4492 (or destination) of the divide or sqrt operation. */
4493 return insn_default_latency (dep_insn) - 2;
4501 /* For other anti dependencies, the cost is 0. */
4504 case REG_DEP_OUTPUT:
4505 /* Output dependency; DEP_INSN writes a register that INSN writes some
4507 if (attr_type == TYPE_FPLOAD)
4509 rtx pat = PATTERN (insn);
4510 rtx dep_pat = PATTERN (dep_insn);
4511 if (GET_CODE (pat) == PARALLEL)
4513 /* This happens for the fldXs,mb patterns. */
4514 pat = XVECEXP (pat, 0, 0);
4516 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4517 /* If this happens, we have to extend this to schedule
4518 optimally. Return 0 for now. */
4521 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4523 if (! recog_memoized (dep_insn))
4525 switch (get_attr_type (dep_insn))
4532 case TYPE_FPSQRTSGL:
4533 case TYPE_FPSQRTDBL:
4534 /* A fpload can't be issued until one cycle before a
4535 preceding arithmetic operation has finished if
4536 the target of the fpload is the destination of the
4537 arithmetic operation.
4539 Exception: For PA7100LC, PA7200 and PA7300, the cost
4540 is 3 cycles, unless they bundle together. We also
4541 pay the penalty if the second insn is a fpload. */
4542 return insn_default_latency (dep_insn) - 1;
4549 else if (attr_type == TYPE_FPALU)
4551 rtx pat = PATTERN (insn);
4552 rtx dep_pat = PATTERN (dep_insn);
4553 if (GET_CODE (pat) == PARALLEL)
4555 /* This happens for the fldXs,mb patterns. */
4556 pat = XVECEXP (pat, 0, 0);
4558 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4559 /* If this happens, we have to extend this to schedule
4560 optimally. Return 0 for now. */
4563 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4565 if (! recog_memoized (dep_insn))
4567 switch (get_attr_type (dep_insn))
4571 case TYPE_FPSQRTSGL:
4572 case TYPE_FPSQRTDBL:
4573 /* An ALU flop can't be issued until two cycles before a
4574 preceding divide or sqrt operation has finished if
4575 the target of the ALU flop is also the target of
4576 the divide or sqrt operation. */
4577 return insn_default_latency (dep_insn) - 2;
4585 /* For other output dependencies, the cost is 0. */
4593 /* Adjust scheduling priorities. We use this to try and keep addil
4594 and the next use of %r1 close together. */
4596 pa_adjust_priority (rtx insn, int priority)
4598 rtx set = single_set (insn);
4602 src = SET_SRC (set);
4603 dest = SET_DEST (set);
4604 if (GET_CODE (src) == LO_SUM
4605 && symbolic_operand (XEXP (src, 1), VOIDmode)
4606 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4609 else if (GET_CODE (src) == MEM
4610 && GET_CODE (XEXP (src, 0)) == LO_SUM
4611 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4612 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4615 else if (GET_CODE (dest) == MEM
4616 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4617 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4618 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4624 /* The 700 can only issue a single insn at a time.
4625 The 7XXX processors can issue two insns at a time.
4626 The 8000 can issue 4 insns at a time. */
4628 pa_issue_rate (void)
4632 case PROCESSOR_700: return 1;
4633 case PROCESSOR_7100: return 2;
4634 case PROCESSOR_7100LC: return 2;
4635 case PROCESSOR_7200: return 2;
4636 case PROCESSOR_7300: return 2;
4637 case PROCESSOR_8000: return 4;
4646 /* Return any length adjustment needed by INSN which already has its length
4647 computed as LENGTH. Return zero if no adjustment is necessary.
4649 For the PA: function calls, millicode calls, and backwards short
4650 conditional branches with unfilled delay slots need an adjustment by +1
4651 (to account for the NOP which will be inserted into the instruction stream).
4653 Also compute the length of an inline block move here as it is too
4654 complicated to express as a length attribute in pa.md. */
4656 pa_adjust_insn_length (rtx insn, int length)
4658 rtx pat = PATTERN (insn);
4660 /* Jumps inside switch tables which have unfilled delay slots need
4662 if (GET_CODE (insn) == JUMP_INSN
4663 && GET_CODE (pat) == PARALLEL
4664 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4666 /* Millicode insn with an unfilled delay slot. */
4667 else if (GET_CODE (insn) == INSN
4668 && GET_CODE (pat) != SEQUENCE
4669 && GET_CODE (pat) != USE
4670 && GET_CODE (pat) != CLOBBER
4671 && get_attr_type (insn) == TYPE_MILLI)
4673 /* Block move pattern. */
4674 else if (GET_CODE (insn) == INSN
4675 && GET_CODE (pat) == PARALLEL
4676 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4677 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4678 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4679 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4680 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4681 return compute_movmem_length (insn) - 4;
4682 /* Block clear pattern. */
4683 else if (GET_CODE (insn) == INSN
4684 && GET_CODE (pat) == PARALLEL
4685 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4686 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4687 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4688 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4689 return compute_clrmem_length (insn) - 4;
4690 /* Conditional branch with an unfilled delay slot. */
4691 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4693 /* Adjust a short backwards conditional with an unfilled delay slot. */
4694 if (GET_CODE (pat) == SET
4696 && ! forward_branch_p (insn))
4698 else if (GET_CODE (pat) == PARALLEL
4699 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4702 /* Adjust dbra insn with short backwards conditional branch with
4703 unfilled delay slot -- only for case where counter is in a
4704 general register register. */
4705 else if (GET_CODE (pat) == PARALLEL
4706 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4707 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4708 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4710 && ! forward_branch_p (insn))
4718 /* Print operand X (an rtx) in assembler syntax to file FILE.
4719 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4720 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4723 print_operand (FILE *file, rtx x, int code)
4728 /* Output a 'nop' if there's nothing for the delay slot. */
4729 if (dbr_sequence_length () == 0)
4730 fputs ("\n\tnop", file);
4733 /* Output a nullification completer if there's nothing for the */
4734 /* delay slot or nullification is requested. */
4735 if (dbr_sequence_length () == 0 ||
4737 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4741 /* Print out the second register name of a register pair.
4742 I.e., R (6) => 7. */
4743 fputs (reg_names[REGNO (x) + 1], file);
4746 /* A register or zero. */
4748 || (x == CONST0_RTX (DFmode))
4749 || (x == CONST0_RTX (SFmode)))
4751 fputs ("%r0", file);
4757 /* A register or zero (floating point). */
4759 || (x == CONST0_RTX (DFmode))
4760 || (x == CONST0_RTX (SFmode)))
4762 fputs ("%fr0", file);
4771 xoperands[0] = XEXP (XEXP (x, 0), 0);
4772 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4773 output_global_address (file, xoperands[1], 0);
4774 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4778 case 'C': /* Plain (C)ondition */
4780 switch (GET_CODE (x))
4783 fputs ("=", file); break;
4785 fputs ("<>", file); break;
4787 fputs (">", file); break;
4789 fputs (">=", file); break;
4791 fputs (">>=", file); break;
4793 fputs (">>", file); break;
4795 fputs ("<", file); break;
4797 fputs ("<=", file); break;
4799 fputs ("<<=", file); break;
4801 fputs ("<<", file); break;
4806 case 'N': /* Condition, (N)egated */
4807 switch (GET_CODE (x))
4810 fputs ("<>", file); break;
4812 fputs ("=", file); break;
4814 fputs ("<=", file); break;
4816 fputs ("<", file); break;
4818 fputs ("<<", file); break;
4820 fputs ("<<=", file); break;
4822 fputs (">=", file); break;
4824 fputs (">", file); break;
4826 fputs (">>", file); break;
4828 fputs (">>=", file); break;
4833 /* For floating point comparisons. Note that the output
4834 predicates are the complement of the desired mode. The
4835 conditions for GT, GE, LT, LE and LTGT cause an invalid
4836 operation exception if the result is unordered and this
4837 exception is enabled in the floating-point status register. */
4839 switch (GET_CODE (x))
4842 fputs ("!=", file); break;
4844 fputs ("=", file); break;
4846 fputs ("!>", file); break;
4848 fputs ("!>=", file); break;
4850 fputs ("!<", file); break;
4852 fputs ("!<=", file); break;
4854 fputs ("!<>", file); break;
4856 fputs ("!?<=", file); break;
4858 fputs ("!?<", file); break;
4860 fputs ("!?>=", file); break;
4862 fputs ("!?>", file); break;
4864 fputs ("!?=", file); break;
4866 fputs ("!?", file); break;
4868 fputs ("?", file); break;
4873 case 'S': /* Condition, operands are (S)wapped. */
4874 switch (GET_CODE (x))
4877 fputs ("=", file); break;
4879 fputs ("<>", file); break;
4881 fputs ("<", file); break;
4883 fputs ("<=", file); break;
4885 fputs ("<<=", file); break;
4887 fputs ("<<", file); break;
4889 fputs (">", file); break;
4891 fputs (">=", file); break;
4893 fputs (">>=", file); break;
4895 fputs (">>", file); break;
4900 case 'B': /* Condition, (B)oth swapped and negate. */
4901 switch (GET_CODE (x))
4904 fputs ("<>", file); break;
4906 fputs ("=", file); break;
4908 fputs (">=", file); break;
4910 fputs (">", file); break;
4912 fputs (">>", file); break;
4914 fputs (">>=", file); break;
4916 fputs ("<=", file); break;
4918 fputs ("<", file); break;
4920 fputs ("<<", file); break;
4922 fputs ("<<=", file); break;
4928 gcc_assert (GET_CODE (x) == CONST_INT);
4929 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4932 gcc_assert (GET_CODE (x) == CONST_INT);
4933 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4936 gcc_assert (GET_CODE (x) == CONST_INT);
4937 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4940 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4941 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4944 gcc_assert (GET_CODE (x) == CONST_INT);
4945 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4948 gcc_assert (GET_CODE (x) == CONST_INT);
4949 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4952 if (GET_CODE (x) == CONST_INT)
4957 switch (GET_CODE (XEXP (x, 0)))
4961 if (ASSEMBLER_DIALECT == 0)
4962 fputs ("s,mb", file);
4964 fputs (",mb", file);
4968 if (ASSEMBLER_DIALECT == 0)
4969 fputs ("s,ma", file);
4971 fputs (",ma", file);
4974 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4975 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4977 if (ASSEMBLER_DIALECT == 0)
4980 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4981 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4983 if (ASSEMBLER_DIALECT == 0)
4984 fputs ("x,s", file);
4988 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4992 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4998 output_global_address (file, x, 0);
5001 output_global_address (file, x, 1);
5003 case 0: /* Don't do anything special */
5008 compute_zdepwi_operands (INTVAL (x), op);
5009 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5015 compute_zdepdi_operands (INTVAL (x), op);
5016 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5020 /* We can get here from a .vtable_inherit due to our
5021 CONSTANT_ADDRESS_P rejecting perfectly good constant
5027 if (GET_CODE (x) == REG)
5029 fputs (reg_names [REGNO (x)], file);
5030 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5036 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5037 && (REGNO (x) & 1) == 0)
5040 else if (GET_CODE (x) == MEM)
5042 int size = GET_MODE_SIZE (GET_MODE (x));
5043 rtx base = NULL_RTX;
5044 switch (GET_CODE (XEXP (x, 0)))
5048 base = XEXP (XEXP (x, 0), 0);
5049 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5053 base = XEXP (XEXP (x, 0), 0);
5054 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5057 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5058 fprintf (file, "%s(%s)",
5059 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5060 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5061 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5062 fprintf (file, "%s(%s)",
5063 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5064 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5065 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5066 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5068 /* Because the REG_POINTER flag can get lost during reload,
5069 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5070 index and base registers in the combined move patterns. */
5071 rtx base = XEXP (XEXP (x, 0), 1);
5072 rtx index = XEXP (XEXP (x, 0), 0);
5074 fprintf (file, "%s(%s)",
5075 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5078 output_address (XEXP (x, 0));
5081 output_address (XEXP (x, 0));
5086 output_addr_const (file, x);
5089 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5092 output_global_address (FILE *file, rtx x, int round_constant)
5095 /* Imagine (high (const (plus ...))). */
5096 if (GET_CODE (x) == HIGH)
5099 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5100 output_addr_const (file, x);
5101 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5103 output_addr_const (file, x);
5104 fputs ("-$global$", file);
5106 else if (GET_CODE (x) == CONST)
5108 const char *sep = "";
5109 int offset = 0; /* assembler wants -$global$ at end */
5110 rtx base = NULL_RTX;
5112 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5115 base = XEXP (XEXP (x, 0), 0);
5116 output_addr_const (file, base);
5119 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5125 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5128 base = XEXP (XEXP (x, 0), 1);
5129 output_addr_const (file, base);
5132 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5138 /* How bogus. The compiler is apparently responsible for
5139 rounding the constant if it uses an LR field selector.
5141 The linker and/or assembler seem a better place since
5142 they have to do this kind of thing already.
5144 If we fail to do this, HP's optimizing linker may eliminate
5145 an addil, but not update the ldw/stw/ldo instruction that
5146 uses the result of the addil. */
5148 offset = ((offset + 0x1000) & ~0x1fff);
5150 switch (GET_CODE (XEXP (x, 0)))
5163 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5171 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5172 fputs ("-$global$", file);
5174 fprintf (file, "%s%d", sep, offset);
5177 output_addr_const (file, x);
5180 /* Output boilerplate text to appear at the beginning of the file.
5181 There are several possible versions. */
5182 #define aputs(x) fputs(x, asm_out_file)
5184 pa_file_start_level (void)
5187 aputs ("\t.LEVEL 2.0w\n");
5188 else if (TARGET_PA_20)
5189 aputs ("\t.LEVEL 2.0\n");
5190 else if (TARGET_PA_11)
5191 aputs ("\t.LEVEL 1.1\n");
5193 aputs ("\t.LEVEL 1.0\n");
5197 pa_file_start_space (int sortspace)
5199 aputs ("\t.SPACE $PRIVATE$");
5202 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5203 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5204 "\n\t.SPACE $TEXT$");
5207 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5208 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5212 pa_file_start_file (int want_version)
5214 if (write_symbols != NO_DEBUG)
5216 output_file_directive (asm_out_file, main_input_filename);
5218 aputs ("\t.version\t\"01.01\"\n");
5223 pa_file_start_mcount (const char *aswhat)
5226 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5230 pa_elf_file_start (void)
5232 pa_file_start_level ();
5233 pa_file_start_mcount ("ENTRY");
5234 pa_file_start_file (0);
5238 pa_som_file_start (void)
5240 pa_file_start_level ();
5241 pa_file_start_space (0);
5242 aputs ("\t.IMPORT $global$,DATA\n"
5243 "\t.IMPORT $$dyncall,MILLICODE\n");
5244 pa_file_start_mcount ("CODE");
5245 pa_file_start_file (0);
5249 pa_linux_file_start (void)
5251 pa_file_start_file (1);
5252 pa_file_start_level ();
5253 pa_file_start_mcount ("CODE");
5257 pa_hpux64_gas_file_start (void)
5259 pa_file_start_level ();
5260 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5262 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5264 pa_file_start_file (1);
5268 pa_hpux64_hpas_file_start (void)
5270 pa_file_start_level ();
5271 pa_file_start_space (1);
5272 pa_file_start_mcount ("CODE");
5273 pa_file_start_file (0);
5277 /* Search the deferred plabel list for SYMBOL and return its internal
5278 label. If an entry for SYMBOL is not found, a new entry is created. */
5281 get_deferred_plabel (rtx symbol)
5283 const char *fname = XSTR (symbol, 0);
5286 /* See if we have already put this function on the list of deferred
5287 plabels. This list is generally small, so a liner search is not
5288 too ugly. If it proves too slow replace it with something faster. */
5289 for (i = 0; i < n_deferred_plabels; i++)
5290 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5293 /* If the deferred plabel list is empty, or this entry was not found
5294 on the list, create a new entry on the list. */
5295 if (deferred_plabels == NULL || i == n_deferred_plabels)
5299 if (deferred_plabels == 0)
5300 deferred_plabels = (struct deferred_plabel *)
5301 ggc_alloc (sizeof (struct deferred_plabel));
5303 deferred_plabels = (struct deferred_plabel *)
5304 ggc_realloc (deferred_plabels,
5305 ((n_deferred_plabels + 1)
5306 * sizeof (struct deferred_plabel)));
5308 i = n_deferred_plabels++;
5309 deferred_plabels[i].internal_label = gen_label_rtx ();
5310 deferred_plabels[i].symbol = symbol;
5312 /* Gross. We have just implicitly taken the address of this
5313 function. Mark it in the same manner as assemble_name. */
5314 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5316 mark_referenced (id);
5319 return deferred_plabels[i].internal_label;
5323 output_deferred_plabels (void)
5327 /* If we have some deferred plabels, then we need to switch into the
5328 data or readonly data section, and align it to a 4 byte boundary
5329 before outputting the deferred plabels. */
5330 if (n_deferred_plabels)
5332 switch_to_section (flag_pic ? data_section : readonly_data_section);
5333 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5336 /* Now output the deferred plabels. */
5337 for (i = 0; i < n_deferred_plabels; i++)
5339 targetm.asm_out.internal_label (asm_out_file, "L",
5340 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5341 assemble_integer (deferred_plabels[i].symbol,
5342 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5346 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5347 /* Initialize optabs to point to HPUX long double emulation routines. */
5349 pa_hpux_init_libfuncs (void)
5351 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5352 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5353 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5354 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5355 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5356 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5357 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5358 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5359 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5361 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5362 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5363 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5364 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5365 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5366 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5367 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5369 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5370 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5371 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5372 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5374 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5375 ? "__U_Qfcnvfxt_quad_to_sgl"
5376 : "_U_Qfcnvfxt_quad_to_sgl");
5377 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5378 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5379 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5381 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5382 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5383 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5384 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5388 /* HP's millicode routines mean something special to the assembler.
5389 Keep track of which ones we have used. */
5391 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5392 static void import_milli (enum millicodes);
5393 static char imported[(int) end1000];
5394 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5395 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5396 #define MILLI_START 10
5399 import_milli (enum millicodes code)
5401 char str[sizeof (import_string)];
5403 if (!imported[(int) code])
5405 imported[(int) code] = 1;
5406 strcpy (str, import_string);
5407 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5408 output_asm_insn (str, 0);
5412 /* The register constraints have put the operands and return value in
5413 the proper registers. */
5416 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5418 import_milli (mulI);
5419 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5422 /* Emit the rtl for doing a division by a constant. */
5424 /* Do magic division millicodes exist for this value? */
5425 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5427 /* We'll use an array to keep track of the magic millicodes and
5428 whether or not we've used them already. [n][0] is signed, [n][1] is
5431 static int div_milli[16][2];
5434 emit_hpdiv_const (rtx *operands, int unsignedp)
5436 if (GET_CODE (operands[2]) == CONST_INT
5437 && INTVAL (operands[2]) > 0
5438 && INTVAL (operands[2]) < 16
5439 && magic_milli[INTVAL (operands[2])])
5441 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5443 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5447 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5448 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5450 gen_rtx_REG (SImode, 26),
5452 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5453 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5454 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5455 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5456 gen_rtx_CLOBBER (VOIDmode, ret))));
5457 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5464 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5468 /* If the divisor is a constant, try to use one of the special
5470 if (GET_CODE (operands[0]) == CONST_INT)
5472 static char buf[100];
5473 divisor = INTVAL (operands[0]);
5474 if (!div_milli[divisor][unsignedp])
5476 div_milli[divisor][unsignedp] = 1;
5478 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5480 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5484 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5485 INTVAL (operands[0]));
5486 return output_millicode_call (insn,
5487 gen_rtx_SYMBOL_REF (SImode, buf));
5491 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5492 INTVAL (operands[0]));
5493 return output_millicode_call (insn,
5494 gen_rtx_SYMBOL_REF (SImode, buf));
5497 /* Divisor isn't a special constant. */
5502 import_milli (divU);
5503 return output_millicode_call (insn,
5504 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5508 import_milli (divI);
5509 return output_millicode_call (insn,
5510 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5515 /* Output a $$rem millicode to do mod. */
5518 output_mod_insn (int unsignedp, rtx insn)
5522 import_milli (remU);
5523 return output_millicode_call (insn,
5524 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5528 import_milli (remI);
5529 return output_millicode_call (insn,
5530 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5535 output_arg_descriptor (rtx call_insn)
5537 const char *arg_regs[4];
5538 enum machine_mode arg_mode;
5540 int i, output_flag = 0;
5543 /* We neither need nor want argument location descriptors for the
5544 64bit runtime environment or the ELF32 environment. */
5545 if (TARGET_64BIT || TARGET_ELF32)
5548 for (i = 0; i < 4; i++)
5551 /* Specify explicitly that no argument relocations should take place
5552 if using the portable runtime calling conventions. */
5553 if (TARGET_PORTABLE_RUNTIME)
5555 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5560 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5561 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5562 link; link = XEXP (link, 1))
5564 rtx use = XEXP (link, 0);
5566 if (! (GET_CODE (use) == USE
5567 && GET_CODE (XEXP (use, 0)) == REG
5568 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5571 arg_mode = GET_MODE (XEXP (use, 0));
5572 regno = REGNO (XEXP (use, 0));
5573 if (regno >= 23 && regno <= 26)
5575 arg_regs[26 - regno] = "GR";
5576 if (arg_mode == DImode)
5577 arg_regs[25 - regno] = "GR";
5579 else if (regno >= 32 && regno <= 39)
5581 if (arg_mode == SFmode)
5582 arg_regs[(regno - 32) / 2] = "FR";
5585 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5586 arg_regs[(regno - 34) / 2] = "FR";
5587 arg_regs[(regno - 34) / 2 + 1] = "FU";
5589 arg_regs[(regno - 34) / 2] = "FU";
5590 arg_regs[(regno - 34) / 2 + 1] = "FR";
5595 fputs ("\t.CALL ", asm_out_file);
5596 for (i = 0; i < 4; i++)
5601 fputc (',', asm_out_file);
5602 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5605 fputc ('\n', asm_out_file);
5608 static enum reg_class
5609 pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
5610 enum machine_mode mode, secondary_reload_info *sri)
5612 int is_symbolic, regno;
5614 /* Handle the easy stuff first. */
5615 if (class == R1_REGS)
5621 if (class == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5627 /* If we have something like (mem (mem (...)), we can safely assume the
5628 inner MEM will end up in a general register after reloading, so there's
5629 no need for a secondary reload. */
5630 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5633 /* Trying to load a constant into a FP register during PIC code
5634 generation requires %r1 as a scratch register. */
5636 && (mode == SImode || mode == DImode)
5637 && FP_REG_CLASS_P (class)
5638 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5640 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5641 : CODE_FOR_reload_indi_r1);
5645 /* Profiling showed the PA port spends about 1.3% of its compilation
5646 time in true_regnum from calls inside pa_secondary_reload_class. */
5647 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5648 regno = true_regnum (x);
5650 /* Handle out of range displacement for integer mode loads/stores of
5652 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5653 && GET_MODE_CLASS (mode) == MODE_INT
5654 && FP_REG_CLASS_P (class))
5655 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5657 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5661 /* A SAR<->FP register copy requires a secondary register (GPR) as
5662 well as secondary memory. */
5663 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5664 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5665 || (class == SHIFT_REGS
5666 && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5668 sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
5672 /* Secondary reloads of symbolic operands require %r1 as a scratch
5673 register when we're generating PIC code and the operand isn't
5675 if (GET_CODE (x) == HIGH)
5678 /* Profiling has showed GCC spends about 2.6% of its compilation
5679 time in symbolic_operand from calls inside pa_secondary_reload_class.
5680 So, we use an inline copy to avoid useless work. */
5681 switch (GET_CODE (x))
5686 is_symbolic = !SYMBOL_REF_TLS_MODEL (x);
5693 is_symbolic = (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
5694 && !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
5695 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
5696 && GET_CODE (XEXP (op, 1)) == CONST_INT);
5703 if (is_symbolic && (flag_pic || !read_only_operand (x, VOIDmode)))
5705 gcc_assert (mode == SImode || mode == DImode);
5706 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5707 : CODE_FOR_reload_indi_r1);
5713 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5714 by invisible reference. As a GCC extension, we also pass anything
5715 with a zero or variable size by reference.
5717 The 64-bit runtime does not describe passing any types by invisible
5718 reference. The internals of GCC can't currently handle passing
5719 empty structures, and zero or variable length arrays when they are
5720 not passed entirely on the stack or by reference. Thus, as a GCC
5721 extension, we pass these types by reference. The HP compiler doesn't
5722 support these types, so hopefully there shouldn't be any compatibility
5723 issues. This may have to be revisited when HP releases a C99 compiler
5724 or updates the ABI. */
5727 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5728 enum machine_mode mode, tree type,
5729 bool named ATTRIBUTE_UNUSED)
5734 size = int_size_in_bytes (type);
5736 size = GET_MODE_SIZE (mode);
5741 return size <= 0 || size > 8;
5745 function_arg_padding (enum machine_mode mode, tree type)
5748 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5750 /* Return none if justification is not required. */
5752 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5753 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5756 /* The directions set here are ignored when a BLKmode argument larger
5757 than a word is placed in a register. Different code is used for
5758 the stack and registers. This makes it difficult to have a
5759 consistent data representation for both the stack and registers.
5760 For both runtimes, the justification and padding for arguments on
5761 the stack and in registers should be identical. */
5763 /* The 64-bit runtime specifies left justification for aggregates. */
5766 /* The 32-bit runtime architecture specifies right justification.
5767 When the argument is passed on the stack, the argument is padded
5768 with garbage on the left. The HP compiler pads with zeros. */
5772 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5779 /* Do what is necessary for `va_start'. We look at the current function
5780 to determine if stdargs or varargs is used and fill in an initial
5781 va_list. A pointer to this constructor is returned. */
5784 hppa_builtin_saveregs (void)
5787 tree fntype = TREE_TYPE (current_function_decl);
5788 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5789 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5790 != void_type_node)))
5791 ? UNITS_PER_WORD : 0);
5794 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5796 offset = current_function_arg_offset_rtx;
5802 /* Adjust for varargs/stdarg differences. */
5804 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5806 offset = current_function_arg_offset_rtx;
5808 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5809 from the incoming arg pointer and growing to larger addresses. */
5810 for (i = 26, off = -64; i >= 19; i--, off += 8)
5811 emit_move_insn (gen_rtx_MEM (word_mode,
5812 plus_constant (arg_pointer_rtx, off)),
5813 gen_rtx_REG (word_mode, i));
5815 /* The incoming args pointer points just beyond the flushback area;
5816 normally this is not a serious concern. However, when we are doing
5817 varargs/stdargs we want to make the arg pointer point to the start
5818 of the incoming argument area. */
5819 emit_move_insn (virtual_incoming_args_rtx,
5820 plus_constant (arg_pointer_rtx, -64));
5822 /* Now return a pointer to the first anonymous argument. */
5823 return copy_to_reg (expand_binop (Pmode, add_optab,
5824 virtual_incoming_args_rtx,
5825 offset, 0, 0, OPTAB_LIB_WIDEN));
5828 /* Store general registers on the stack. */
5829 dest = gen_rtx_MEM (BLKmode,
5830 plus_constant (current_function_internal_arg_pointer,
5832 set_mem_alias_set (dest, get_varargs_alias_set ());
5833 set_mem_align (dest, BITS_PER_WORD);
5834 move_block_from_reg (23, dest, 4);
5836 /* move_block_from_reg will emit code to store the argument registers
5837 individually as scalar stores.
5839 However, other insns may later load from the same addresses for
5840 a structure load (passing a struct to a varargs routine).
5842 The alias code assumes that such aliasing can never happen, so we
5843 have to keep memory referencing insns from moving up beyond the
5844 last argument register store. So we emit a blockage insn here. */
5845 emit_insn (gen_blockage ());
5847 return copy_to_reg (expand_binop (Pmode, add_optab,
5848 current_function_internal_arg_pointer,
5849 offset, 0, 0, OPTAB_LIB_WIDEN));
5853 hppa_va_start (tree valist, rtx nextarg)
5855 nextarg = expand_builtin_saveregs ();
5856 std_expand_builtin_va_start (valist, nextarg);
5860 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5864 /* Args grow upward. We can use the generic routines. */
5865 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5867 else /* !TARGET_64BIT */
5869 tree ptr = build_pointer_type (type);
5872 unsigned int size, ofs;
5875 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5879 ptr = build_pointer_type (type);
5881 size = int_size_in_bytes (type);
5882 valist_type = TREE_TYPE (valist);
5884 /* Args grow down. Not handled by generic routines. */
5886 u = fold_convert (valist_type, size_in_bytes (type));
5887 t = build2 (MINUS_EXPR, valist_type, valist, u);
5889 /* Copied from va-pa.h, but we probably don't need to align to
5890 word size, since we generate and preserve that invariant. */
5891 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5892 t = build2 (BIT_AND_EXPR, valist_type, t, u);
5894 t = build2 (MODIFY_EXPR, valist_type, valist, t);
5896 ofs = (8 - size) % 4;
5899 u = fold_convert (valist_type, size_int (ofs));
5900 t = build2 (PLUS_EXPR, valist_type, t, u);
5903 t = fold_convert (ptr, t);
5904 t = build_va_arg_indirect_ref (t);
5907 t = build_va_arg_indirect_ref (t);
5913 /* True if MODE is valid for the target. By "valid", we mean able to
5914 be manipulated in non-trivial ways. In particular, this means all
5915 the arithmetic is supported.
5917 Currently, TImode is not valid as the HP 64-bit runtime documentation
5918 doesn't document the alignment and calling conventions for this type.
5919 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5920 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5923 pa_scalar_mode_supported_p (enum machine_mode mode)
5925 int precision = GET_MODE_PRECISION (mode);
5927 switch (GET_MODE_CLASS (mode))
5929 case MODE_PARTIAL_INT:
5931 if (precision == CHAR_TYPE_SIZE)
5933 if (precision == SHORT_TYPE_SIZE)
5935 if (precision == INT_TYPE_SIZE)
5937 if (precision == LONG_TYPE_SIZE)
5939 if (precision == LONG_LONG_TYPE_SIZE)
5944 if (precision == FLOAT_TYPE_SIZE)
5946 if (precision == DOUBLE_TYPE_SIZE)
5948 if (precision == LONG_DOUBLE_TYPE_SIZE)
5952 case MODE_DECIMAL_FLOAT:
5960 /* This routine handles all the normal conditional branch sequences we
5961 might need to generate. It handles compare immediate vs compare
5962 register, nullification of delay slots, varying length branches,
5963 negated branches, and all combinations of the above. It returns the
5964 output appropriate to emit the branch corresponding to all given
5968 output_cbranch (rtx *operands, int negated, rtx insn)
5970 static char buf[100];
5972 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5973 int length = get_attr_length (insn);
5976 /* A conditional branch to the following instruction (e.g. the delay slot)
5977 is asking for a disaster. This can happen when not optimizing and
5978 when jump optimization fails.
5980 While it is usually safe to emit nothing, this can fail if the
5981 preceding instruction is a nullified branch with an empty delay
5982 slot and the same branch target as this branch. We could check
5983 for this but jump optimization should eliminate nop jumps. It
5984 is always safe to emit a nop. */
5985 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5988 /* The doubleword form of the cmpib instruction doesn't have the LEU
5989 and GTU conditions while the cmpb instruction does. Since we accept
5990 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5991 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5992 operands[2] = gen_rtx_REG (DImode, 0);
5993 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
5994 operands[1] = gen_rtx_REG (DImode, 0);
5996 /* If this is a long branch with its delay slot unfilled, set `nullify'
5997 as it can nullify the delay slot and save a nop. */
5998 if (length == 8 && dbr_sequence_length () == 0)
6001 /* If this is a short forward conditional branch which did not get
6002 its delay slot filled, the delay slot can still be nullified. */
6003 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6004 nullify = forward_branch_p (insn);
6006 /* A forward branch over a single nullified insn can be done with a
6007 comclr instruction. This avoids a single cycle penalty due to
6008 mis-predicted branch if we fall through (branch not taken). */
6010 && next_real_insn (insn) != 0
6011 && get_attr_length (next_real_insn (insn)) == 4
6012 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6018 /* All short conditional branches except backwards with an unfilled
6022 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6024 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6025 if (GET_MODE (operands[1]) == DImode)
6028 strcat (buf, "%B3");
6030 strcat (buf, "%S3");
6032 strcat (buf, " %2,%r1,%%r0");
6034 strcat (buf, ",n %2,%r1,%0");
6036 strcat (buf, " %2,%r1,%0");
6039 /* All long conditionals. Note a short backward branch with an
6040 unfilled delay slot is treated just like a long backward branch
6041 with an unfilled delay slot. */
6043 /* Handle weird backwards branch with a filled delay slot
6044 which is nullified. */
6045 if (dbr_sequence_length () != 0
6046 && ! forward_branch_p (insn)
6049 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6050 if (GET_MODE (operands[1]) == DImode)
6053 strcat (buf, "%S3");
6055 strcat (buf, "%B3");
6056 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6058 /* Handle short backwards branch with an unfilled delay slot.
6059 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6060 taken and untaken branches. */
6061 else if (dbr_sequence_length () == 0
6062 && ! forward_branch_p (insn)
6063 && INSN_ADDRESSES_SET_P ()
6064 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6065 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6067 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6068 if (GET_MODE (operands[1]) == DImode)
6071 strcat (buf, "%B3 %2,%r1,%0%#");
6073 strcat (buf, "%S3 %2,%r1,%0%#");
6077 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6078 if (GET_MODE (operands[1]) == DImode)
6081 strcat (buf, "%S3");
6083 strcat (buf, "%B3");
6085 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6087 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6092 /* The reversed conditional branch must branch over one additional
6093 instruction if the delay slot is filled and needs to be extracted
6094 by output_lbranch. If the delay slot is empty or this is a
6095 nullified forward branch, the instruction after the reversed
6096 condition branch must be nullified. */
6097 if (dbr_sequence_length () == 0
6098 || (nullify && forward_branch_p (insn)))
6102 operands[4] = GEN_INT (length);
6107 operands[4] = GEN_INT (length + 4);
6110 /* Create a reversed conditional branch which branches around
6111 the following insns. */
6112 if (GET_MODE (operands[1]) != DImode)
6118 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6121 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6127 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6130 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6139 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6142 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6148 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6151 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6155 output_asm_insn (buf, operands);
6156 return output_lbranch (operands[0], insn, xdelay);
6161 /* This routine handles output of long unconditional branches that
6162 exceed the maximum range of a simple branch instruction. Since
6163 we don't have a register available for the branch, we save register
6164 %r1 in the frame marker, load the branch destination DEST into %r1,
6165 execute the branch, and restore %r1 in the delay slot of the branch.
6167 Since long branches may have an insn in the delay slot and the
6168 delay slot is used to restore %r1, we in general need to extract
6169 this insn and execute it before the branch. However, to facilitate
6170 use of this function by conditional branches, we also provide an
6171 option to not extract the delay insn so that it will be emitted
6172 after the long branch. So, if there is an insn in the delay slot,
6173 it is extracted if XDELAY is nonzero.
6175 The lengths of the various long-branch sequences are 20, 16 and 24
6176 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6179 output_lbranch (rtx dest, rtx insn, int xdelay)
6183 xoperands[0] = dest;
6185 /* First, free up the delay slot. */
6186 if (xdelay && dbr_sequence_length () != 0)
6188 /* We can't handle a jump in the delay slot. */
6189 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6191 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6194 /* Now delete the delay insn. */
6195 PUT_CODE (NEXT_INSN (insn), NOTE);
6196 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6197 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6200 /* Output an insn to save %r1. The runtime documentation doesn't
6201 specify whether the "Clean Up" slot in the callers frame can
6202 be clobbered by the callee. It isn't copied by HP's builtin
6203 alloca, so this suggests that it can be clobbered if necessary.
6204 The "Static Link" location is copied by HP builtin alloca, so
6205 we avoid using it. Using the cleanup slot might be a problem
6206 if we have to interoperate with languages that pass cleanup
6207 information. However, it should be possible to handle these
6208 situations with GCC's asm feature.
6210 The "Current RP" slot is reserved for the called procedure, so
6211 we try to use it when we don't have a frame of our own. It's
6212 rather unlikely that we won't have a frame when we need to emit
6215 Really the way to go long term is a register scavenger; goto
6216 the target of the jump and find a register which we can use
6217 as a scratch to hold the value in %r1. Then, we wouldn't have
6218 to free up the delay slot or clobber a slot that may be needed
6219 for other purposes. */
6222 if (actual_fsize == 0 && !regs_ever_live[2])
6223 /* Use the return pointer slot in the frame marker. */
6224 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6226 /* Use the slot at -40 in the frame marker since HP builtin
6227 alloca doesn't copy it. */
6228 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6232 if (actual_fsize == 0 && !regs_ever_live[2])
6233 /* Use the return pointer slot in the frame marker. */
6234 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6236 /* Use the "Clean Up" slot in the frame marker. In GCC,
6237 the only other use of this location is for copying a
6238 floating point double argument from a floating-point
6239 register to two general registers. The copy is done
6240 as an "atomic" operation when outputting a call, so it
6241 won't interfere with our using the location here. */
6242 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6245 if (TARGET_PORTABLE_RUNTIME)
6247 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6248 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6249 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6253 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6254 if (TARGET_SOM || !TARGET_GAS)
6256 xoperands[1] = gen_label_rtx ();
6257 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6258 targetm.asm_out.internal_label (asm_out_file, "L",
6259 CODE_LABEL_NUMBER (xoperands[1]));
6260 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6264 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6265 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6267 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6270 /* Now output a very long branch to the original target. */
6271 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6273 /* Now restore the value of %r1 in the delay slot. */
6276 if (actual_fsize == 0 && !regs_ever_live[2])
6277 return "ldd -16(%%r30),%%r1";
6279 return "ldd -40(%%r30),%%r1";
6283 if (actual_fsize == 0 && !regs_ever_live[2])
6284 return "ldw -20(%%r30),%%r1";
6286 return "ldw -12(%%r30),%%r1";
6290 /* This routine handles all the branch-on-bit conditional branch sequences we
6291 might need to generate. It handles nullification of delay slots,
6292 varying length branches, negated branches and all combinations of the
6293 above. it returns the appropriate output template to emit the branch. */
6296 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6298 static char buf[100];
6300 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6301 int length = get_attr_length (insn);
6304 /* A conditional branch to the following instruction (e.g. the delay slot) is
6305 asking for a disaster. I do not think this can happen as this pattern
6306 is only used when optimizing; jump optimization should eliminate the
6307 jump. But be prepared just in case. */
6309 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6312 /* If this is a long branch with its delay slot unfilled, set `nullify'
6313 as it can nullify the delay slot and save a nop. */
6314 if (length == 8 && dbr_sequence_length () == 0)
6317 /* If this is a short forward conditional branch which did not get
6318 its delay slot filled, the delay slot can still be nullified. */
6319 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6320 nullify = forward_branch_p (insn);
6322 /* A forward branch over a single nullified insn can be done with a
6323 extrs instruction. This avoids a single cycle penalty due to
6324 mis-predicted branch if we fall through (branch not taken). */
6327 && next_real_insn (insn) != 0
6328 && get_attr_length (next_real_insn (insn)) == 4
6329 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6336 /* All short conditional branches except backwards with an unfilled
6340 strcpy (buf, "{extrs,|extrw,s,}");
6342 strcpy (buf, "bb,");
6343 if (useskip && GET_MODE (operands[0]) == DImode)
6344 strcpy (buf, "extrd,s,*");
6345 else if (GET_MODE (operands[0]) == DImode)
6346 strcpy (buf, "bb,*");
6347 if ((which == 0 && negated)
6348 || (which == 1 && ! negated))
6353 strcat (buf, " %0,%1,1,%%r0");
6354 else if (nullify && negated)
6355 strcat (buf, ",n %0,%1,%3");
6356 else if (nullify && ! negated)
6357 strcat (buf, ",n %0,%1,%2");
6358 else if (! nullify && negated)
6359 strcat (buf, "%0,%1,%3");
6360 else if (! nullify && ! negated)
6361 strcat (buf, " %0,%1,%2");
6364 /* All long conditionals. Note a short backward branch with an
6365 unfilled delay slot is treated just like a long backward branch
6366 with an unfilled delay slot. */
6368 /* Handle weird backwards branch with a filled delay slot
6369 which is nullified. */
6370 if (dbr_sequence_length () != 0
6371 && ! forward_branch_p (insn)
6374 strcpy (buf, "bb,");
6375 if (GET_MODE (operands[0]) == DImode)
6377 if ((which == 0 && negated)
6378 || (which == 1 && ! negated))
6383 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6385 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6387 /* Handle short backwards branch with an unfilled delay slot.
6388 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6389 taken and untaken branches. */
6390 else if (dbr_sequence_length () == 0
6391 && ! forward_branch_p (insn)
6392 && INSN_ADDRESSES_SET_P ()
6393 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6394 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6396 strcpy (buf, "bb,");
6397 if (GET_MODE (operands[0]) == DImode)
6399 if ((which == 0 && negated)
6400 || (which == 1 && ! negated))
6405 strcat (buf, " %0,%1,%3%#");
6407 strcat (buf, " %0,%1,%2%#");
6411 if (GET_MODE (operands[0]) == DImode)
6412 strcpy (buf, "extrd,s,*");
6414 strcpy (buf, "{extrs,|extrw,s,}");
6415 if ((which == 0 && negated)
6416 || (which == 1 && ! negated))
6420 if (nullify && negated)
6421 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6422 else if (nullify && ! negated)
6423 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6425 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6427 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6432 /* The reversed conditional branch must branch over one additional
6433 instruction if the delay slot is filled and needs to be extracted
6434 by output_lbranch. If the delay slot is empty or this is a
6435 nullified forward branch, the instruction after the reversed
6436 condition branch must be nullified. */
6437 if (dbr_sequence_length () == 0
6438 || (nullify && forward_branch_p (insn)))
6442 operands[4] = GEN_INT (length);
6447 operands[4] = GEN_INT (length + 4);
6450 if (GET_MODE (operands[0]) == DImode)
6451 strcpy (buf, "bb,*");
6453 strcpy (buf, "bb,");
6454 if ((which == 0 && negated)
6455 || (which == 1 && !negated))
6460 strcat (buf, ",n %0,%1,.+%4");
6462 strcat (buf, " %0,%1,.+%4");
6463 output_asm_insn (buf, operands);
6464 return output_lbranch (negated ? operands[3] : operands[2],
6470 /* This routine handles all the branch-on-variable-bit conditional branch
6471 sequences we might need to generate. It handles nullification of delay
6472 slots, varying length branches, negated branches and all combinations
6473 of the above. it returns the appropriate output template to emit the
6477 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6479 static char buf[100];
6481 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6482 int length = get_attr_length (insn);
6485 /* A conditional branch to the following instruction (e.g. the delay slot) is
6486 asking for a disaster. I do not think this can happen as this pattern
6487 is only used when optimizing; jump optimization should eliminate the
6488 jump. But be prepared just in case. */
6490 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6493 /* If this is a long branch with its delay slot unfilled, set `nullify'
6494 as it can nullify the delay slot and save a nop. */
6495 if (length == 8 && dbr_sequence_length () == 0)
6498 /* If this is a short forward conditional branch which did not get
6499 its delay slot filled, the delay slot can still be nullified. */
6500 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6501 nullify = forward_branch_p (insn);
6503 /* A forward branch over a single nullified insn can be done with a
6504 extrs instruction. This avoids a single cycle penalty due to
6505 mis-predicted branch if we fall through (branch not taken). */
6508 && next_real_insn (insn) != 0
6509 && get_attr_length (next_real_insn (insn)) == 4
6510 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6517 /* All short conditional branches except backwards with an unfilled
6521 strcpy (buf, "{vextrs,|extrw,s,}");
6523 strcpy (buf, "{bvb,|bb,}");
6524 if (useskip && GET_MODE (operands[0]) == DImode)
6525 strcpy (buf, "extrd,s,*");
6526 else if (GET_MODE (operands[0]) == DImode)
6527 strcpy (buf, "bb,*");
6528 if ((which == 0 && negated)
6529 || (which == 1 && ! negated))
6534 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6535 else if (nullify && negated)
6536 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6537 else if (nullify && ! negated)
6538 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6539 else if (! nullify && negated)
6540 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6541 else if (! nullify && ! negated)
6542 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6545 /* All long conditionals. Note a short backward branch with an
6546 unfilled delay slot is treated just like a long backward branch
6547 with an unfilled delay slot. */
6549 /* Handle weird backwards branch with a filled delay slot
6550 which is nullified. */
6551 if (dbr_sequence_length () != 0
6552 && ! forward_branch_p (insn)
6555 strcpy (buf, "{bvb,|bb,}");
6556 if (GET_MODE (operands[0]) == DImode)
6558 if ((which == 0 && negated)
6559 || (which == 1 && ! negated))
6564 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6566 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6568 /* Handle short backwards branch with an unfilled delay slot.
6569 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6570 taken and untaken branches. */
6571 else if (dbr_sequence_length () == 0
6572 && ! forward_branch_p (insn)
6573 && INSN_ADDRESSES_SET_P ()
6574 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6575 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6577 strcpy (buf, "{bvb,|bb,}");
6578 if (GET_MODE (operands[0]) == DImode)
6580 if ((which == 0 && negated)
6581 || (which == 1 && ! negated))
6586 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6588 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6592 strcpy (buf, "{vextrs,|extrw,s,}");
6593 if (GET_MODE (operands[0]) == DImode)
6594 strcpy (buf, "extrd,s,*");
6595 if ((which == 0 && negated)
6596 || (which == 1 && ! negated))
6600 if (nullify && negated)
6601 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6602 else if (nullify && ! negated)
6603 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6605 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6607 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6612 /* The reversed conditional branch must branch over one additional
6613 instruction if the delay slot is filled and needs to be extracted
6614 by output_lbranch. If the delay slot is empty or this is a
6615 nullified forward branch, the instruction after the reversed
6616 condition branch must be nullified. */
6617 if (dbr_sequence_length () == 0
6618 || (nullify && forward_branch_p (insn)))
6622 operands[4] = GEN_INT (length);
6627 operands[4] = GEN_INT (length + 4);
6630 if (GET_MODE (operands[0]) == DImode)
6631 strcpy (buf, "bb,*");
6633 strcpy (buf, "{bvb,|bb,}");
6634 if ((which == 0 && negated)
6635 || (which == 1 && !negated))
6640 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6642 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6643 output_asm_insn (buf, operands);
6644 return output_lbranch (negated ? operands[3] : operands[2],
6650 /* Return the output template for emitting a dbra type insn.
6652 Note it may perform some output operations on its own before
6653 returning the final output string. */
6655 output_dbra (rtx *operands, rtx insn, int which_alternative)
6657 int length = get_attr_length (insn);
6659 /* A conditional branch to the following instruction (e.g. the delay slot) is
6660 asking for a disaster. Be prepared! */
6662 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6664 if (which_alternative == 0)
6665 return "ldo %1(%0),%0";
6666 else if (which_alternative == 1)
6668 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6669 output_asm_insn ("ldw -16(%%r30),%4", operands);
6670 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6671 return "{fldws|fldw} -16(%%r30),%0";
6675 output_asm_insn ("ldw %0,%4", operands);
6676 return "ldo %1(%4),%4\n\tstw %4,%0";
6680 if (which_alternative == 0)
6682 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6685 /* If this is a long branch with its delay slot unfilled, set `nullify'
6686 as it can nullify the delay slot and save a nop. */
6687 if (length == 8 && dbr_sequence_length () == 0)
6690 /* If this is a short forward conditional branch which did not get
6691 its delay slot filled, the delay slot can still be nullified. */
6692 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6693 nullify = forward_branch_p (insn);
6699 return "addib,%C2,n %1,%0,%3";
6701 return "addib,%C2 %1,%0,%3";
6704 /* Handle weird backwards branch with a fulled delay slot
6705 which is nullified. */
6706 if (dbr_sequence_length () != 0
6707 && ! forward_branch_p (insn)
6709 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6710 /* Handle short backwards branch with an unfilled delay slot.
6711 Using a addb;nop rather than addi;bl saves 1 cycle for both
6712 taken and untaken branches. */
6713 else if (dbr_sequence_length () == 0
6714 && ! forward_branch_p (insn)
6715 && INSN_ADDRESSES_SET_P ()
6716 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6717 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6718 return "addib,%C2 %1,%0,%3%#";
6720 /* Handle normal cases. */
6722 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6724 return "addi,%N2 %1,%0,%0\n\tb %3";
6727 /* The reversed conditional branch must branch over one additional
6728 instruction if the delay slot is filled and needs to be extracted
6729 by output_lbranch. If the delay slot is empty or this is a
6730 nullified forward branch, the instruction after the reversed
6731 condition branch must be nullified. */
6732 if (dbr_sequence_length () == 0
6733 || (nullify && forward_branch_p (insn)))
6737 operands[4] = GEN_INT (length);
6742 operands[4] = GEN_INT (length + 4);
6746 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
6748 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
6750 return output_lbranch (operands[3], insn, xdelay);
6754 /* Deal with gross reload from FP register case. */
6755 else if (which_alternative == 1)
6757 /* Move loop counter from FP register to MEM then into a GR,
6758 increment the GR, store the GR into MEM, and finally reload
6759 the FP register from MEM from within the branch's delay slot. */
6760 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6762 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6764 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6765 else if (length == 28)
6766 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6769 operands[5] = GEN_INT (length - 16);
6770 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
6771 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6772 return output_lbranch (operands[3], insn, 0);
6775 /* Deal with gross reload from memory case. */
6778 /* Reload loop counter from memory, the store back to memory
6779 happens in the branch's delay slot. */
6780 output_asm_insn ("ldw %0,%4", operands);
6782 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6783 else if (length == 16)
6784 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6787 operands[5] = GEN_INT (length - 4);
6788 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
6789 return output_lbranch (operands[3], insn, 0);
6794 /* Return the output template for emitting a movb type insn.
6796 Note it may perform some output operations on its own before
6797 returning the final output string. */
6799 output_movb (rtx *operands, rtx insn, int which_alternative,
6800 int reverse_comparison)
6802 int length = get_attr_length (insn);
6804 /* A conditional branch to the following instruction (e.g. the delay slot) is
6805 asking for a disaster. Be prepared! */
6807 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6809 if (which_alternative == 0)
6810 return "copy %1,%0";
6811 else if (which_alternative == 1)
6813 output_asm_insn ("stw %1,-16(%%r30)", operands);
6814 return "{fldws|fldw} -16(%%r30),%0";
6816 else if (which_alternative == 2)
6822 /* Support the second variant. */
6823 if (reverse_comparison)
6824 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6826 if (which_alternative == 0)
6828 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6831 /* If this is a long branch with its delay slot unfilled, set `nullify'
6832 as it can nullify the delay slot and save a nop. */
6833 if (length == 8 && dbr_sequence_length () == 0)
6836 /* If this is a short forward conditional branch which did not get
6837 its delay slot filled, the delay slot can still be nullified. */
6838 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6839 nullify = forward_branch_p (insn);
6845 return "movb,%C2,n %1,%0,%3";
6847 return "movb,%C2 %1,%0,%3";
6850 /* Handle weird backwards branch with a filled delay slot
6851 which is nullified. */
6852 if (dbr_sequence_length () != 0
6853 && ! forward_branch_p (insn)
6855 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6857 /* Handle short backwards branch with an unfilled delay slot.
6858 Using a movb;nop rather than or;bl saves 1 cycle for both
6859 taken and untaken branches. */
6860 else if (dbr_sequence_length () == 0
6861 && ! forward_branch_p (insn)
6862 && INSN_ADDRESSES_SET_P ()
6863 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6864 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6865 return "movb,%C2 %1,%0,%3%#";
6866 /* Handle normal cases. */
6868 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6870 return "or,%N2 %1,%%r0,%0\n\tb %3";
6873 /* The reversed conditional branch must branch over one additional
6874 instruction if the delay slot is filled and needs to be extracted
6875 by output_lbranch. If the delay slot is empty or this is a
6876 nullified forward branch, the instruction after the reversed
6877 condition branch must be nullified. */
6878 if (dbr_sequence_length () == 0
6879 || (nullify && forward_branch_p (insn)))
6883 operands[4] = GEN_INT (length);
6888 operands[4] = GEN_INT (length + 4);
6892 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
6894 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
6896 return output_lbranch (operands[3], insn, xdelay);
6899 /* Deal with gross reload for FP destination register case. */
6900 else if (which_alternative == 1)
6902 /* Move source register to MEM, perform the branch test, then
6903 finally load the FP register from MEM from within the branch's
6905 output_asm_insn ("stw %1,-16(%%r30)", operands);
6907 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6908 else if (length == 16)
6909 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6912 operands[4] = GEN_INT (length - 4);
6913 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
6914 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
6915 return output_lbranch (operands[3], insn, 0);
6918 /* Deal with gross reload from memory case. */
6919 else if (which_alternative == 2)
6921 /* Reload loop counter from memory, the store back to memory
6922 happens in the branch's delay slot. */
6924 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6925 else if (length == 12)
6926 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6929 operands[4] = GEN_INT (length);
6930 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
6932 return output_lbranch (operands[3], insn, 0);
6935 /* Handle SAR as a destination. */
6939 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6940 else if (length == 12)
6941 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6944 operands[4] = GEN_INT (length);
6945 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
6947 return output_lbranch (operands[3], insn, 0);
6952 /* Copy any FP arguments in INSN into integer registers. */
6954 copy_fp_args (rtx insn)
6959 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6961 int arg_mode, regno;
6962 rtx use = XEXP (link, 0);
6964 if (! (GET_CODE (use) == USE
6965 && GET_CODE (XEXP (use, 0)) == REG
6966 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6969 arg_mode = GET_MODE (XEXP (use, 0));
6970 regno = REGNO (XEXP (use, 0));
6972 /* Is it a floating point register? */
6973 if (regno >= 32 && regno <= 39)
6975 /* Copy the FP register into an integer register via memory. */
6976 if (arg_mode == SFmode)
6978 xoperands[0] = XEXP (use, 0);
6979 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6980 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6981 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6985 xoperands[0] = XEXP (use, 0);
6986 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6987 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6988 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6989 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6995 /* Compute length of the FP argument copy sequence for INSN. */
6997 length_fp_args (rtx insn)
7002 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7004 int arg_mode, regno;
7005 rtx use = XEXP (link, 0);
7007 if (! (GET_CODE (use) == USE
7008 && GET_CODE (XEXP (use, 0)) == REG
7009 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7012 arg_mode = GET_MODE (XEXP (use, 0));
7013 regno = REGNO (XEXP (use, 0));
7015 /* Is it a floating point register? */
7016 if (regno >= 32 && regno <= 39)
7018 if (arg_mode == SFmode)
7028 /* Return the attribute length for the millicode call instruction INSN.
7029 The length must match the code generated by output_millicode_call.
7030 We include the delay slot in the returned length as it is better to
7031 over estimate the length than to under estimate it. */
7034 attr_length_millicode_call (rtx insn)
7036 unsigned long distance = -1;
7037 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7039 if (INSN_ADDRESSES_SET_P ())
7041 distance = (total + insn_current_reference_address (insn));
7042 if (distance < total)
7048 if (!TARGET_LONG_CALLS && distance < 7600000)
7053 else if (TARGET_PORTABLE_RUNTIME)
7057 if (!TARGET_LONG_CALLS && distance < 240000)
7060 if (TARGET_LONG_ABS_CALL && !flag_pic)
7067 /* INSN is a function call. It may have an unconditional jump
7070 CALL_DEST is the routine we are calling. */
7073 output_millicode_call (rtx insn, rtx call_dest)
7075 int attr_length = get_attr_length (insn);
7076 int seq_length = dbr_sequence_length ();
7081 xoperands[0] = call_dest;
7082 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7084 /* Handle the common case where we are sure that the branch will
7085 reach the beginning of the $CODE$ subspace. The within reach
7086 form of the $$sh_func_adrs call has a length of 28. Because
7087 it has an attribute type of multi, it never has a nonzero
7088 sequence length. The length of the $$sh_func_adrs is the same
7089 as certain out of reach PIC calls to other routines. */
7090 if (!TARGET_LONG_CALLS
7091 && ((seq_length == 0
7092 && (attr_length == 12
7093 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7094 || (seq_length != 0 && attr_length == 8)))
7096 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7102 /* It might seem that one insn could be saved by accessing
7103 the millicode function using the linkage table. However,
7104 this doesn't work in shared libraries and other dynamically
7105 loaded objects. Using a pc-relative sequence also avoids
7106 problems related to the implicit use of the gp register. */
7107 output_asm_insn ("b,l .+8,%%r1", xoperands);
7111 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7112 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7116 xoperands[1] = gen_label_rtx ();
7117 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7118 targetm.asm_out.internal_label (asm_out_file, "L",
7119 CODE_LABEL_NUMBER (xoperands[1]));
7120 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7123 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7125 else if (TARGET_PORTABLE_RUNTIME)
7127 /* Pure portable runtime doesn't allow be/ble; we also don't
7128 have PIC support in the assembler/linker, so this sequence
7131 /* Get the address of our target into %r1. */
7132 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7133 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7135 /* Get our return address into %r31. */
7136 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7137 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7139 /* Jump to our target address in %r1. */
7140 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7144 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7146 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7148 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7152 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7153 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7155 if (TARGET_SOM || !TARGET_GAS)
7157 /* The HP assembler can generate relocations for the
7158 difference of two symbols. GAS can do this for a
7159 millicode symbol but not an arbitrary external
7160 symbol when generating SOM output. */
7161 xoperands[1] = gen_label_rtx ();
7162 targetm.asm_out.internal_label (asm_out_file, "L",
7163 CODE_LABEL_NUMBER (xoperands[1]));
7164 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7165 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7169 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7170 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7174 /* Jump to our target address in %r1. */
7175 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7179 if (seq_length == 0)
7180 output_asm_insn ("nop", xoperands);
7182 /* We are done if there isn't a jump in the delay slot. */
7183 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7186 /* This call has an unconditional jump in its delay slot. */
7187 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7189 /* See if the return address can be adjusted. Use the containing
7190 sequence insn's address. */
7191 if (INSN_ADDRESSES_SET_P ())
7193 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7194 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7195 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7197 if (VAL_14_BITS_P (distance))
7199 xoperands[1] = gen_label_rtx ();
7200 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7201 targetm.asm_out.internal_label (asm_out_file, "L",
7202 CODE_LABEL_NUMBER (xoperands[1]));
7205 /* ??? This branch may not reach its target. */
7206 output_asm_insn ("nop\n\tb,n %0", xoperands);
7209 /* ??? This branch may not reach its target. */
7210 output_asm_insn ("nop\n\tb,n %0", xoperands);
7212 /* Delete the jump. */
7213 PUT_CODE (NEXT_INSN (insn), NOTE);
7214 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7215 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7220 /* Return the attribute length of the call instruction INSN. The SIBCALL
7221 flag indicates whether INSN is a regular call or a sibling call. The
7222 length returned must be longer than the code actually generated by
7223 output_call. Since branch shortening is done before delay branch
7224 sequencing, there is no way to determine whether or not the delay
7225 slot will be filled during branch shortening. Even when the delay
7226 slot is filled, we may have to add a nop if the delay slot contains
7227 a branch that can't reach its target. Thus, we always have to include
7228 the delay slot in the length estimate. This used to be done in
7229 pa_adjust_insn_length but we do it here now as some sequences always
7230 fill the delay slot and we can save four bytes in the estimate for
7234 attr_length_call (rtx insn, int sibcall)
7240 rtx pat = PATTERN (insn);
7241 unsigned long distance = -1;
7243 if (INSN_ADDRESSES_SET_P ())
7245 unsigned long total;
7247 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7248 distance = (total + insn_current_reference_address (insn));
7249 if (distance < total)
7253 /* Determine if this is a local call. */
7254 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7255 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7257 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7259 call_decl = SYMBOL_REF_DECL (call_dest);
7260 local_call = call_decl && targetm.binds_local_p (call_decl);
7262 /* pc-relative branch. */
7263 if (!TARGET_LONG_CALLS
7264 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7265 || distance < 240000))
7268 /* 64-bit plabel sequence. */
7269 else if (TARGET_64BIT && !local_call)
7270 length += sibcall ? 28 : 24;
7272 /* non-pic long absolute branch sequence. */
7273 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7276 /* long pc-relative branch sequence. */
7277 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7278 || (TARGET_64BIT && !TARGET_GAS)
7279 || (TARGET_GAS && !TARGET_SOM
7280 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7284 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7288 /* 32-bit plabel sequence. */
7294 length += length_fp_args (insn);
7304 if (!TARGET_NO_SPACE_REGS)
7312 /* INSN is a function call. It may have an unconditional jump
7315 CALL_DEST is the routine we are calling. */
7318 output_call (rtx insn, rtx call_dest, int sibcall)
7320 int delay_insn_deleted = 0;
7321 int delay_slot_filled = 0;
7322 int seq_length = dbr_sequence_length ();
7323 tree call_decl = SYMBOL_REF_DECL (call_dest);
7324 int local_call = call_decl && targetm.binds_local_p (call_decl);
7327 xoperands[0] = call_dest;
7329 /* Handle the common case where we're sure that the branch will reach
7330 the beginning of the "$CODE$" subspace. This is the beginning of
7331 the current function if we are in a named section. */
7332 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7334 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7335 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7339 if (TARGET_64BIT && !local_call)
7341 /* ??? As far as I can tell, the HP linker doesn't support the
7342 long pc-relative sequence described in the 64-bit runtime
7343 architecture. So, we use a slightly longer indirect call. */
7344 xoperands[0] = get_deferred_plabel (call_dest);
7345 xoperands[1] = gen_label_rtx ();
7347 /* If this isn't a sibcall, we put the load of %r27 into the
7348 delay slot. We can't do this in a sibcall as we don't
7349 have a second call-clobbered scratch register available. */
7351 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7354 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7357 /* Now delete the delay insn. */
7358 PUT_CODE (NEXT_INSN (insn), NOTE);
7359 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7360 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7361 delay_insn_deleted = 1;
7364 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7365 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7366 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7370 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7371 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7372 output_asm_insn ("bve (%%r1)", xoperands);
7376 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7377 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7378 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7379 delay_slot_filled = 1;
7384 int indirect_call = 0;
7386 /* Emit a long call. There are several different sequences
7387 of increasing length and complexity. In most cases,
7388 they don't allow an instruction in the delay slot. */
7389 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7390 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7391 && !(TARGET_GAS && !TARGET_SOM
7392 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7397 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7399 && (!TARGET_PA_20 || indirect_call))
7401 /* A non-jump insn in the delay slot. By definition we can
7402 emit this insn before the call (and in fact before argument
7404 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7407 /* Now delete the delay insn. */
7408 PUT_CODE (NEXT_INSN (insn), NOTE);
7409 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7410 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7411 delay_insn_deleted = 1;
7414 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7416 /* This is the best sequence for making long calls in
7417 non-pic code. Unfortunately, GNU ld doesn't provide
7418 the stub needed for external calls, and GAS's support
7419 for this with the SOM linker is buggy. It is safe
7420 to use this for local calls. */
7421 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7423 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7427 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7430 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7432 output_asm_insn ("copy %%r31,%%r2", xoperands);
7433 delay_slot_filled = 1;
7438 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7439 || (TARGET_64BIT && !TARGET_GAS))
7441 /* The HP assembler and linker can handle relocations
7442 for the difference of two symbols. GAS and the HP
7443 linker can't do this when one of the symbols is
7445 xoperands[1] = gen_label_rtx ();
7446 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7447 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7448 targetm.asm_out.internal_label (asm_out_file, "L",
7449 CODE_LABEL_NUMBER (xoperands[1]));
7450 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7452 else if (TARGET_GAS && !TARGET_SOM
7453 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7455 /* GAS currently can't generate the relocations that
7456 are needed for the SOM linker under HP-UX using this
7457 sequence. The GNU linker doesn't generate the stubs
7458 that are needed for external calls on TARGET_ELF32
7459 with this sequence. For now, we have to use a
7460 longer plabel sequence when using GAS. */
7461 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7462 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7464 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7469 /* Emit a long plabel-based call sequence. This is
7470 essentially an inline implementation of $$dyncall.
7471 We don't actually try to call $$dyncall as this is
7472 as difficult as calling the function itself. */
7473 xoperands[0] = get_deferred_plabel (call_dest);
7474 xoperands[1] = gen_label_rtx ();
7476 /* Since the call is indirect, FP arguments in registers
7477 need to be copied to the general registers. Then, the
7478 argument relocation stub will copy them back. */
7480 copy_fp_args (insn);
7484 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7485 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7486 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7490 output_asm_insn ("addil LR'%0-$global$,%%r27",
7492 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7496 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7497 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7498 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7499 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7501 if (!sibcall && !TARGET_PA_20)
7503 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7504 if (TARGET_NO_SPACE_REGS)
7505 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7507 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7514 output_asm_insn ("bve (%%r1)", xoperands);
7519 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7520 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7521 delay_slot_filled = 1;
7524 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7529 if (!TARGET_NO_SPACE_REGS)
7530 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7535 if (TARGET_NO_SPACE_REGS)
7536 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7538 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7542 if (TARGET_NO_SPACE_REGS)
7543 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7545 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7548 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7550 output_asm_insn ("copy %%r31,%%r2", xoperands);
7551 delay_slot_filled = 1;
7558 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7559 output_asm_insn ("nop", xoperands);
7561 /* We are done if there isn't a jump in the delay slot. */
7563 || delay_insn_deleted
7564 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7567 /* A sibcall should never have a branch in the delay slot. */
7568 gcc_assert (!sibcall);
7570 /* This call has an unconditional jump in its delay slot. */
7571 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7573 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7575 /* See if the return address can be adjusted. Use the containing
7576 sequence insn's address. */
7577 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7578 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7579 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7581 if (VAL_14_BITS_P (distance))
7583 xoperands[1] = gen_label_rtx ();
7584 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7585 targetm.asm_out.internal_label (asm_out_file, "L",
7586 CODE_LABEL_NUMBER (xoperands[1]));
7589 output_asm_insn ("nop\n\tb,n %0", xoperands);
7592 output_asm_insn ("b,n %0", xoperands);
7594 /* Delete the jump. */
7595 PUT_CODE (NEXT_INSN (insn), NOTE);
7596 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7597 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7602 /* Return the attribute length of the indirect call instruction INSN.
7603 The length must match the code generated by output_indirect call.
7604 The returned length includes the delay slot. Currently, the delay
7605 slot of an indirect call sequence is not exposed and it is used by
7606 the sequence itself. */
7609 attr_length_indirect_call (rtx insn)
7611 unsigned long distance = -1;
7612 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7614 if (INSN_ADDRESSES_SET_P ())
7616 distance = (total + insn_current_reference_address (insn));
7617 if (distance < total)
7624 if (TARGET_FAST_INDIRECT_CALLS
7625 || (!TARGET_PORTABLE_RUNTIME
7626 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7627 || distance < 240000)))
7633 if (TARGET_PORTABLE_RUNTIME)
7636 /* Out of reach, can use ble. */
7641 output_indirect_call (rtx insn, rtx call_dest)
7647 xoperands[0] = call_dest;
7648 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7649 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7653 /* First the special case for kernels, level 0 systems, etc. */
7654 if (TARGET_FAST_INDIRECT_CALLS)
7655 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7657 /* Now the normal case -- we can reach $$dyncall directly or
7658 we're sure that we can get there via a long-branch stub.
7660 No need to check target flags as the length uniquely identifies
7661 the remaining cases. */
7662 if (attr_length_indirect_call (insn) == 8)
7664 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7665 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7666 variant of the B,L instruction can't be used on the SOM target. */
7667 if (TARGET_PA_20 && !TARGET_SOM)
7668 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7670 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7673 /* Long millicode call, but we are not generating PIC or portable runtime
7675 if (attr_length_indirect_call (insn) == 12)
7676 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7678 /* Long millicode call for portable runtime. */
7679 if (attr_length_indirect_call (insn) == 20)
7680 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7682 /* We need a long PIC call to $$dyncall. */
7683 xoperands[0] = NULL_RTX;
7684 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7685 if (TARGET_SOM || !TARGET_GAS)
7687 xoperands[0] = gen_label_rtx ();
7688 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7689 targetm.asm_out.internal_label (asm_out_file, "L",
7690 CODE_LABEL_NUMBER (xoperands[0]));
7691 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7695 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7696 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7699 output_asm_insn ("blr %%r0,%%r2", xoperands);
7700 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7704 /* Return the total length of the save and restore instructions needed for
7705 the data linkage table pointer (i.e., the PIC register) across the call
7706 instruction INSN. No-return calls do not require a save and restore.
7707 In addition, we may be able to avoid the save and restore for calls
7708 within the same translation unit. */
7711 attr_length_save_restore_dltp (rtx insn)
7713 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7719 /* In HPUX 8.0's shared library scheme, special relocations are needed
7720 for function labels if they might be passed to a function
7721 in a shared library (because shared libraries don't live in code
7722 space), and special magic is needed to construct their address. */
7725 hppa_encode_label (rtx sym)
7727 const char *str = XSTR (sym, 0);
7728 int len = strlen (str) + 1;
7731 p = newstr = alloca (len + 1);
7735 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7739 pa_encode_section_info (tree decl, rtx rtl, int first)
7741 default_encode_section_info (decl, rtl, first);
7743 if (first && TEXT_SPACE_P (decl))
7745 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7746 if (TREE_CODE (decl) == FUNCTION_DECL)
7747 hppa_encode_label (XEXP (rtl, 0));
7751 /* This is sort of inverse to pa_encode_section_info. */
7754 pa_strip_name_encoding (const char *str)
7756 str += (*str == '@');
7757 str += (*str == '*');
7762 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7764 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7767 /* Returns 1 if OP is a function label involved in a simple addition
7768 with a constant. Used to keep certain patterns from matching
7769 during instruction combination. */
7771 is_function_label_plus_const (rtx op)
7773 /* Strip off any CONST. */
7774 if (GET_CODE (op) == CONST)
7777 return (GET_CODE (op) == PLUS
7778 && function_label_operand (XEXP (op, 0), Pmode)
7779 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7782 /* Output assembly code for a thunk to FUNCTION. */
7785 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7786 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7789 static unsigned int current_thunk_number;
7790 int val_14 = VAL_14_BITS_P (delta);
7795 xoperands[0] = XEXP (DECL_RTL (function), 0);
7796 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7797 xoperands[2] = GEN_INT (delta);
7799 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7800 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7802 /* Output the thunk. We know that the function is in the same
7803 translation unit (i.e., the same space) as the thunk, and that
7804 thunks are output after their method. Thus, we don't need an
7805 external branch to reach the function. With SOM and GAS,
7806 functions and thunks are effectively in different sections.
7807 Thus, we can always use a IA-relative branch and the linker
7808 will add a long branch stub if necessary.
7810 However, we have to be careful when generating PIC code on the
7811 SOM port to ensure that the sequence does not transfer to an
7812 import stub for the target function as this could clobber the
7813 return value saved at SP-24. This would also apply to the
7814 32-bit linux port if the multi-space model is implemented. */
7815 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7816 && !(flag_pic && TREE_PUBLIC (function))
7817 && (TARGET_GAS || last_address < 262132))
7818 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7819 && ((targetm.have_named_sections
7820 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7821 /* The GNU 64-bit linker has rather poor stub management.
7822 So, we use a long branch from thunks that aren't in
7823 the same section as the target function. */
7825 && (DECL_SECTION_NAME (thunk_fndecl)
7826 != DECL_SECTION_NAME (function)))
7827 || ((DECL_SECTION_NAME (thunk_fndecl)
7828 == DECL_SECTION_NAME (function))
7829 && last_address < 262132)))
7830 || (!targetm.have_named_sections && last_address < 262132))))
7833 output_asm_insn ("addil L'%2,%%r26", xoperands);
7835 output_asm_insn ("b %0", xoperands);
7839 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7844 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7848 else if (TARGET_64BIT)
7850 /* We only have one call-clobbered scratch register, so we can't
7851 make use of the delay slot if delta doesn't fit in 14 bits. */
7854 output_asm_insn ("addil L'%2,%%r26", xoperands);
7855 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7858 output_asm_insn ("b,l .+8,%%r1", xoperands);
7862 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7863 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7867 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7868 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7873 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7874 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7879 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7883 else if (TARGET_PORTABLE_RUNTIME)
7885 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7886 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7889 output_asm_insn ("addil L'%2,%%r26", xoperands);
7891 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7895 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7900 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7904 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7906 /* The function is accessible from outside this module. The only
7907 way to avoid an import stub between the thunk and function is to
7908 call the function directly with an indirect sequence similar to
7909 that used by $$dyncall. This is possible because $$dyncall acts
7910 as the import stub in an indirect call. */
7911 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7912 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7913 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7914 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7915 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7916 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7917 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7918 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7919 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7923 output_asm_insn ("addil L'%2,%%r26", xoperands);
7929 output_asm_insn ("bve (%%r22)", xoperands);
7932 else if (TARGET_NO_SPACE_REGS)
7934 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7939 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7940 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7941 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7946 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7948 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7952 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7954 if (TARGET_SOM || !TARGET_GAS)
7956 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7957 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7961 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7962 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7966 output_asm_insn ("addil L'%2,%%r26", xoperands);
7968 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7972 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7977 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7984 output_asm_insn ("addil L'%2,%%r26", xoperands);
7986 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7987 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7991 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7996 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8001 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8003 if (TARGET_SOM && TARGET_GAS)
8005 /* We done with this subspace except possibly for some additional
8006 debug information. Forget that we are in this subspace to ensure
8007 that the next function is output in its own subspace. */
8009 cfun->machine->in_nsubspa = 2;
8012 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8014 switch_to_section (data_section);
8015 output_asm_insn (".align 4", xoperands);
8016 ASM_OUTPUT_LABEL (file, label);
8017 output_asm_insn (".word P'%0", xoperands);
8020 current_thunk_number++;
8021 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8022 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8023 last_address += nbytes;
8024 update_total_code_bytes (nbytes);
8027 /* Only direct calls to static functions are allowed to be sibling (tail)
8030 This restriction is necessary because some linker generated stubs will
8031 store return pointers into rp' in some cases which might clobber a
8032 live value already in rp'.
8034 In a sibcall the current function and the target function share stack
8035 space. Thus if the path to the current function and the path to the
8036 target function save a value in rp', they save the value into the
8037 same stack slot, which has undesirable consequences.
8039 Because of the deferred binding nature of shared libraries any function
8040 with external scope could be in a different load module and thus require
8041 rp' to be saved when calling that function. So sibcall optimizations
8042 can only be safe for static function.
8044 Note that GCC never needs return value relocations, so we don't have to
8045 worry about static calls with return value relocations (which require
8048 It is safe to perform a sibcall optimization when the target function
8049 will never return. */
8051 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8053 if (TARGET_PORTABLE_RUNTIME)
8056 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8057 single subspace mode and the call is not indirect. As far as I know,
8058 there is no operating system support for the multiple subspace mode.
8059 It might be possible to support indirect calls if we didn't use
8060 $$dyncall (see the indirect sequence generated in output_call). */
8062 return (decl != NULL_TREE);
8064 /* Sibcalls are not ok because the arg pointer register is not a fixed
8065 register. This prevents the sibcall optimization from occurring. In
8066 addition, there are problems with stub placement using GNU ld. This
8067 is because a normal sibcall branch uses a 17-bit relocation while
8068 a regular call branch uses a 22-bit relocation. As a result, more
8069 care needs to be taken in the placement of long-branch stubs. */
8073 /* Sibcalls are only ok within a translation unit. */
8074 return (decl && !TREE_PUBLIC (decl));
8077 /* ??? Addition is not commutative on the PA due to the weird implicit
8078 space register selection rules for memory addresses. Therefore, we
8079 don't consider a + b == b + a, as this might be inside a MEM. */
8081 pa_commutative_p (rtx x, int outer_code)
8083 return (COMMUTATIVE_P (x)
8084 && (TARGET_NO_SPACE_REGS
8085 || (outer_code != UNKNOWN && outer_code != MEM)
8086 || GET_CODE (x) != PLUS));
8089 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8090 use in fmpyadd instructions. */
8092 fmpyaddoperands (rtx *operands)
8094 enum machine_mode mode = GET_MODE (operands[0]);
8096 /* Must be a floating point mode. */
8097 if (mode != SFmode && mode != DFmode)
8100 /* All modes must be the same. */
8101 if (! (mode == GET_MODE (operands[1])
8102 && mode == GET_MODE (operands[2])
8103 && mode == GET_MODE (operands[3])
8104 && mode == GET_MODE (operands[4])
8105 && mode == GET_MODE (operands[5])))
8108 /* All operands must be registers. */
8109 if (! (GET_CODE (operands[1]) == REG
8110 && GET_CODE (operands[2]) == REG
8111 && GET_CODE (operands[3]) == REG
8112 && GET_CODE (operands[4]) == REG
8113 && GET_CODE (operands[5]) == REG))
8116 /* Only 2 real operands to the addition. One of the input operands must
8117 be the same as the output operand. */
8118 if (! rtx_equal_p (operands[3], operands[4])
8119 && ! rtx_equal_p (operands[3], operands[5]))
8122 /* Inout operand of add cannot conflict with any operands from multiply. */
8123 if (rtx_equal_p (operands[3], operands[0])
8124 || rtx_equal_p (operands[3], operands[1])
8125 || rtx_equal_p (operands[3], operands[2]))
8128 /* multiply cannot feed into addition operands. */
8129 if (rtx_equal_p (operands[4], operands[0])
8130 || rtx_equal_p (operands[5], operands[0]))
8133 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8135 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8136 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8137 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8138 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8139 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8140 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8143 /* Passed. Operands are suitable for fmpyadd. */
8147 #if !defined(USE_COLLECT2)
8149 pa_asm_out_constructor (rtx symbol, int priority)
8151 if (!function_label_operand (symbol, VOIDmode))
8152 hppa_encode_label (symbol);
8154 #ifdef CTORS_SECTION_ASM_OP
8155 default_ctor_section_asm_out_constructor (symbol, priority);
8157 # ifdef TARGET_ASM_NAMED_SECTION
8158 default_named_section_asm_out_constructor (symbol, priority);
8160 default_stabs_asm_out_constructor (symbol, priority);
8166 pa_asm_out_destructor (rtx symbol, int priority)
8168 if (!function_label_operand (symbol, VOIDmode))
8169 hppa_encode_label (symbol);
8171 #ifdef DTORS_SECTION_ASM_OP
8172 default_dtor_section_asm_out_destructor (symbol, priority);
8174 # ifdef TARGET_ASM_NAMED_SECTION
8175 default_named_section_asm_out_destructor (symbol, priority);
8177 default_stabs_asm_out_destructor (symbol, priority);
8183 /* This function places uninitialized global data in the bss section.
8184 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8185 function on the SOM port to prevent uninitialized global data from
8186 being placed in the data section. */
8189 pa_asm_output_aligned_bss (FILE *stream,
8191 unsigned HOST_WIDE_INT size,
8194 switch_to_section (bss_section);
8195 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8197 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8198 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8201 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8202 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8205 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8206 ASM_OUTPUT_LABEL (stream, name);
8207 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8210 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8211 that doesn't allow the alignment of global common storage to be directly
8212 specified. The SOM linker aligns common storage based on the rounded
8213 value of the NUM_BYTES parameter in the .comm directive. It's not
8214 possible to use the .align directive as it doesn't affect the alignment
8215 of the label associated with a .comm directive. */
8218 pa_asm_output_aligned_common (FILE *stream,
8220 unsigned HOST_WIDE_INT size,
8223 unsigned int max_common_align;
8225 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8226 if (align > max_common_align)
8228 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8229 "for global common data. Using %u",
8230 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8231 align = max_common_align;
8234 switch_to_section (bss_section);
8236 assemble_name (stream, name);
8237 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8238 MAX (size, align / BITS_PER_UNIT));
8241 /* We can't use .comm for local common storage as the SOM linker effectively
8242 treats the symbol as universal and uses the same storage for local symbols
8243 with the same name in different object files. The .block directive
8244 reserves an uninitialized block of storage. However, it's not common
8245 storage. Fortunately, GCC never requests common storage with the same
8246 name in any given translation unit. */
8249 pa_asm_output_aligned_local (FILE *stream,
8251 unsigned HOST_WIDE_INT size,
8254 switch_to_section (bss_section);
8255 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8258 fprintf (stream, "%s", LOCAL_ASM_OP);
8259 assemble_name (stream, name);
8260 fprintf (stream, "\n");
8263 ASM_OUTPUT_LABEL (stream, name);
8264 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8267 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8268 use in fmpysub instructions. */
8270 fmpysuboperands (rtx *operands)
8272 enum machine_mode mode = GET_MODE (operands[0]);
8274 /* Must be a floating point mode. */
8275 if (mode != SFmode && mode != DFmode)
8278 /* All modes must be the same. */
8279 if (! (mode == GET_MODE (operands[1])
8280 && mode == GET_MODE (operands[2])
8281 && mode == GET_MODE (operands[3])
8282 && mode == GET_MODE (operands[4])
8283 && mode == GET_MODE (operands[5])))
8286 /* All operands must be registers. */
8287 if (! (GET_CODE (operands[1]) == REG
8288 && GET_CODE (operands[2]) == REG
8289 && GET_CODE (operands[3]) == REG
8290 && GET_CODE (operands[4]) == REG
8291 && GET_CODE (operands[5]) == REG))
8294 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8295 operation, so operands[4] must be the same as operand[3]. */
8296 if (! rtx_equal_p (operands[3], operands[4]))
8299 /* multiply cannot feed into subtraction. */
8300 if (rtx_equal_p (operands[5], operands[0]))
8303 /* Inout operand of sub cannot conflict with any operands from multiply. */
8304 if (rtx_equal_p (operands[3], operands[0])
8305 || rtx_equal_p (operands[3], operands[1])
8306 || rtx_equal_p (operands[3], operands[2]))
8309 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8311 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8312 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8313 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8314 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8315 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8316 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8319 /* Passed. Operands are suitable for fmpysub. */
8323 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8324 constants for shadd instructions. */
8326 shadd_constant_p (int val)
8328 if (val == 2 || val == 4 || val == 8)
8334 /* Return 1 if OP is valid as a base or index register in a
8338 borx_reg_operand (rtx op, enum machine_mode mode)
8340 if (GET_CODE (op) != REG)
8343 /* We must reject virtual registers as the only expressions that
8344 can be instantiated are REG and REG+CONST. */
8345 if (op == virtual_incoming_args_rtx
8346 || op == virtual_stack_vars_rtx
8347 || op == virtual_stack_dynamic_rtx
8348 || op == virtual_outgoing_args_rtx
8349 || op == virtual_cfa_rtx)
8352 /* While it's always safe to index off the frame pointer, it's not
8353 profitable to do so when the frame pointer is being eliminated. */
8354 if (!reload_completed
8355 && flag_omit_frame_pointer
8356 && !current_function_calls_alloca
8357 && op == frame_pointer_rtx)
8360 return register_operand (op, mode);
8363 /* Return 1 if this operand is anything other than a hard register. */
8366 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8368 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8371 /* Return 1 if INSN branches forward. Should be using insn_addresses
8372 to avoid walking through all the insns... */
8374 forward_branch_p (rtx insn)
8376 rtx label = JUMP_LABEL (insn);
8383 insn = NEXT_INSN (insn);
8386 return (insn == label);
8389 /* Return 1 if OP is an equality comparison, else return 0. */
8391 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8393 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8396 /* Return 1 if INSN is in the delay slot of a call instruction. */
8398 jump_in_call_delay (rtx insn)
8401 if (GET_CODE (insn) != JUMP_INSN)
8404 if (PREV_INSN (insn)
8405 && PREV_INSN (PREV_INSN (insn))
8406 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8408 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8410 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8411 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8418 /* Output an unconditional move and branch insn. */
8421 output_parallel_movb (rtx *operands, rtx insn)
8423 int length = get_attr_length (insn);
8425 /* These are the cases in which we win. */
8427 return "mov%I1b,tr %1,%0,%2";
8429 /* None of the following cases win, but they don't lose either. */
8432 if (dbr_sequence_length () == 0)
8434 /* Nothing in the delay slot, fake it by putting the combined
8435 insn (the copy or add) in the delay slot of a bl. */
8436 if (GET_CODE (operands[1]) == CONST_INT)
8437 return "b %2\n\tldi %1,%0";
8439 return "b %2\n\tcopy %1,%0";
8443 /* Something in the delay slot, but we've got a long branch. */
8444 if (GET_CODE (operands[1]) == CONST_INT)
8445 return "ldi %1,%0\n\tb %2";
8447 return "copy %1,%0\n\tb %2";
8451 if (GET_CODE (operands[1]) == CONST_INT)
8452 output_asm_insn ("ldi %1,%0", operands);
8454 output_asm_insn ("copy %1,%0", operands);
8455 return output_lbranch (operands[2], insn, 1);
8458 /* Output an unconditional add and branch insn. */
8461 output_parallel_addb (rtx *operands, rtx insn)
8463 int length = get_attr_length (insn);
8465 /* To make life easy we want operand0 to be the shared input/output
8466 operand and operand1 to be the readonly operand. */
8467 if (operands[0] == operands[1])
8468 operands[1] = operands[2];
8470 /* These are the cases in which we win. */
8472 return "add%I1b,tr %1,%0,%3";
8474 /* None of the following cases win, but they don't lose either. */
8477 if (dbr_sequence_length () == 0)
8478 /* Nothing in the delay slot, fake it by putting the combined
8479 insn (the copy or add) in the delay slot of a bl. */
8480 return "b %3\n\tadd%I1 %1,%0,%0";
8482 /* Something in the delay slot, but we've got a long branch. */
8483 return "add%I1 %1,%0,%0\n\tb %3";
8486 output_asm_insn ("add%I1 %1,%0,%0", operands);
8487 return output_lbranch (operands[3], insn, 1);
8490 /* Return nonzero if INSN (a jump insn) immediately follows a call
8491 to a named function. This is used to avoid filling the delay slot
8492 of the jump since it can usually be eliminated by modifying RP in
8493 the delay slot of the call. */
8496 following_call (rtx insn)
8498 if (! TARGET_JUMP_IN_DELAY)
8501 /* Find the previous real insn, skipping NOTEs. */
8502 insn = PREV_INSN (insn);
8503 while (insn && GET_CODE (insn) == NOTE)
8504 insn = PREV_INSN (insn);
8506 /* Check for CALL_INSNs and millicode calls. */
8508 && ((GET_CODE (insn) == CALL_INSN
8509 && get_attr_type (insn) != TYPE_DYNCALL)
8510 || (GET_CODE (insn) == INSN
8511 && GET_CODE (PATTERN (insn)) != SEQUENCE
8512 && GET_CODE (PATTERN (insn)) != USE
8513 && GET_CODE (PATTERN (insn)) != CLOBBER
8514 && get_attr_type (insn) == TYPE_MILLI)))
8520 /* We use this hook to perform a PA specific optimization which is difficult
8521 to do in earlier passes.
8523 We want the delay slots of branches within jump tables to be filled.
8524 None of the compiler passes at the moment even has the notion that a
8525 PA jump table doesn't contain addresses, but instead contains actual
8528 Because we actually jump into the table, the addresses of each entry
8529 must stay constant in relation to the beginning of the table (which
8530 itself must stay constant relative to the instruction to jump into
8531 it). I don't believe we can guarantee earlier passes of the compiler
8532 will adhere to those rules.
8534 So, late in the compilation process we find all the jump tables, and
8535 expand them into real code -- e.g. each entry in the jump table vector
8536 will get an appropriate label followed by a jump to the final target.
8538 Reorg and the final jump pass can then optimize these branches and
8539 fill their delay slots. We end up with smaller, more efficient code.
8541 The jump instructions within the table are special; we must be able
8542 to identify them during assembly output (if the jumps don't get filled
8543 we need to emit a nop rather than nullifying the delay slot)). We
8544 identify jumps in switch tables by using insns with the attribute
8545 type TYPE_BTABLE_BRANCH.
8547 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8548 insns. This serves two purposes, first it prevents jump.c from
8549 noticing that the last N entries in the table jump to the instruction
8550 immediately after the table and deleting the jumps. Second, those
8551 insns mark where we should emit .begin_brtab and .end_brtab directives
8552 when using GAS (allows for better link time optimizations). */
8559 remove_useless_addtr_insns (1);
8561 if (pa_cpu < PROCESSOR_8000)
8562 pa_combine_instructions ();
8565 /* This is fairly cheap, so always run it if optimizing. */
8566 if (optimize > 0 && !TARGET_BIG_SWITCH)
8568 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8569 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8571 rtx pattern, tmp, location, label;
8572 unsigned int length, i;
8574 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8575 if (GET_CODE (insn) != JUMP_INSN
8576 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8577 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8580 /* Emit marker for the beginning of the branch table. */
8581 emit_insn_before (gen_begin_brtab (), insn);
8583 pattern = PATTERN (insn);
8584 location = PREV_INSN (insn);
8585 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8587 for (i = 0; i < length; i++)
8589 /* Emit a label before each jump to keep jump.c from
8590 removing this code. */
8591 tmp = gen_label_rtx ();
8592 LABEL_NUSES (tmp) = 1;
8593 emit_label_after (tmp, location);
8594 location = NEXT_INSN (location);
8596 if (GET_CODE (pattern) == ADDR_VEC)
8597 label = XEXP (XVECEXP (pattern, 0, i), 0);
8599 label = XEXP (XVECEXP (pattern, 1, i), 0);
8601 tmp = gen_short_jump (label);
8603 /* Emit the jump itself. */
8604 tmp = emit_jump_insn_after (tmp, location);
8605 JUMP_LABEL (tmp) = label;
8606 LABEL_NUSES (label)++;
8607 location = NEXT_INSN (location);
8609 /* Emit a BARRIER after the jump. */
8610 emit_barrier_after (location);
8611 location = NEXT_INSN (location);
8614 /* Emit marker for the end of the branch table. */
8615 emit_insn_before (gen_end_brtab (), location);
8616 location = NEXT_INSN (location);
8617 emit_barrier_after (location);
8619 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8625 /* Still need brtab marker insns. FIXME: the presence of these
8626 markers disables output of the branch table to readonly memory,
8627 and any alignment directives that might be needed. Possibly,
8628 the begin_brtab insn should be output before the label for the
8629 table. This doesn't matter at the moment since the tables are
8630 always output in the text section. */
8631 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8633 /* Find an ADDR_VEC insn. */
8634 if (GET_CODE (insn) != JUMP_INSN
8635 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8636 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8639 /* Now generate markers for the beginning and end of the
8641 emit_insn_before (gen_begin_brtab (), insn);
8642 emit_insn_after (gen_end_brtab (), insn);
8647 /* The PA has a number of odd instructions which can perform multiple
8648 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8649 it may be profitable to combine two instructions into one instruction
8650 with two outputs. It's not profitable PA2.0 machines because the
8651 two outputs would take two slots in the reorder buffers.
8653 This routine finds instructions which can be combined and combines
8654 them. We only support some of the potential combinations, and we
8655 only try common ways to find suitable instructions.
8657 * addb can add two registers or a register and a small integer
8658 and jump to a nearby (+-8k) location. Normally the jump to the
8659 nearby location is conditional on the result of the add, but by
8660 using the "true" condition we can make the jump unconditional.
8661 Thus addb can perform two independent operations in one insn.
8663 * movb is similar to addb in that it can perform a reg->reg
8664 or small immediate->reg copy and jump to a nearby (+-8k location).
8666 * fmpyadd and fmpysub can perform a FP multiply and either an
8667 FP add or FP sub if the operands of the multiply and add/sub are
8668 independent (there are other minor restrictions). Note both
8669 the fmpy and fadd/fsub can in theory move to better spots according
8670 to data dependencies, but for now we require the fmpy stay at a
8673 * Many of the memory operations can perform pre & post updates
8674 of index registers. GCC's pre/post increment/decrement addressing
8675 is far too simple to take advantage of all the possibilities. This
8676 pass may not be suitable since those insns may not be independent.
8678 * comclr can compare two ints or an int and a register, nullify
8679 the following instruction and zero some other register. This
8680 is more difficult to use as it's harder to find an insn which
8681 will generate a comclr than finding something like an unconditional
8682 branch. (conditional moves & long branches create comclr insns).
8684 * Most arithmetic operations can conditionally skip the next
8685 instruction. They can be viewed as "perform this operation
8686 and conditionally jump to this nearby location" (where nearby
8687 is an insns away). These are difficult to use due to the
8688 branch length restrictions. */
8691 pa_combine_instructions (void)
8695 /* This can get expensive since the basic algorithm is on the
8696 order of O(n^2) (or worse). Only do it for -O2 or higher
8697 levels of optimization. */
8701 /* Walk down the list of insns looking for "anchor" insns which
8702 may be combined with "floating" insns. As the name implies,
8703 "anchor" instructions don't move, while "floating" insns may
8705 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8706 new = make_insn_raw (new);
8708 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8710 enum attr_pa_combine_type anchor_attr;
8711 enum attr_pa_combine_type floater_attr;
8713 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8714 Also ignore any special USE insns. */
8715 if ((GET_CODE (anchor) != INSN
8716 && GET_CODE (anchor) != JUMP_INSN
8717 && GET_CODE (anchor) != CALL_INSN)
8718 || GET_CODE (PATTERN (anchor)) == USE
8719 || GET_CODE (PATTERN (anchor)) == CLOBBER
8720 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8721 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8724 anchor_attr = get_attr_pa_combine_type (anchor);
8725 /* See if anchor is an insn suitable for combination. */
8726 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8727 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8728 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8729 && ! forward_branch_p (anchor)))
8733 for (floater = PREV_INSN (anchor);
8735 floater = PREV_INSN (floater))
8737 if (GET_CODE (floater) == NOTE
8738 || (GET_CODE (floater) == INSN
8739 && (GET_CODE (PATTERN (floater)) == USE
8740 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8743 /* Anything except a regular INSN will stop our search. */
8744 if (GET_CODE (floater) != INSN
8745 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8746 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8752 /* See if FLOATER is suitable for combination with the
8754 floater_attr = get_attr_pa_combine_type (floater);
8755 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8756 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8757 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8758 && floater_attr == PA_COMBINE_TYPE_FMPY))
8760 /* If ANCHOR and FLOATER can be combined, then we're
8761 done with this pass. */
8762 if (pa_can_combine_p (new, anchor, floater, 0,
8763 SET_DEST (PATTERN (floater)),
8764 XEXP (SET_SRC (PATTERN (floater)), 0),
8765 XEXP (SET_SRC (PATTERN (floater)), 1)))
8769 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8770 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8772 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8774 if (pa_can_combine_p (new, anchor, floater, 0,
8775 SET_DEST (PATTERN (floater)),
8776 XEXP (SET_SRC (PATTERN (floater)), 0),
8777 XEXP (SET_SRC (PATTERN (floater)), 1)))
8782 if (pa_can_combine_p (new, anchor, floater, 0,
8783 SET_DEST (PATTERN (floater)),
8784 SET_SRC (PATTERN (floater)),
8785 SET_SRC (PATTERN (floater))))
8791 /* If we didn't find anything on the backwards scan try forwards. */
8793 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8794 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8796 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8798 if (GET_CODE (floater) == NOTE
8799 || (GET_CODE (floater) == INSN
8800 && (GET_CODE (PATTERN (floater)) == USE
8801 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8805 /* Anything except a regular INSN will stop our search. */
8806 if (GET_CODE (floater) != INSN
8807 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8808 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8814 /* See if FLOATER is suitable for combination with the
8816 floater_attr = get_attr_pa_combine_type (floater);
8817 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8818 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8819 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8820 && floater_attr == PA_COMBINE_TYPE_FMPY))
8822 /* If ANCHOR and FLOATER can be combined, then we're
8823 done with this pass. */
8824 if (pa_can_combine_p (new, anchor, floater, 1,
8825 SET_DEST (PATTERN (floater)),
8826 XEXP (SET_SRC (PATTERN (floater)),
8828 XEXP (SET_SRC (PATTERN (floater)),
8835 /* FLOATER will be nonzero if we found a suitable floating
8836 insn for combination with ANCHOR. */
8838 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8839 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8841 /* Emit the new instruction and delete the old anchor. */
8842 emit_insn_before (gen_rtx_PARALLEL
8844 gen_rtvec (2, PATTERN (anchor),
8845 PATTERN (floater))),
8848 PUT_CODE (anchor, NOTE);
8849 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8850 NOTE_SOURCE_FILE (anchor) = 0;
8852 /* Emit a special USE insn for FLOATER, then delete
8853 the floating insn. */
8854 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8855 delete_insn (floater);
8860 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8863 /* Emit the new_jump instruction and delete the old anchor. */
8865 = emit_jump_insn_before (gen_rtx_PARALLEL
8867 gen_rtvec (2, PATTERN (anchor),
8868 PATTERN (floater))),
8871 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8872 PUT_CODE (anchor, NOTE);
8873 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8874 NOTE_SOURCE_FILE (anchor) = 0;
8876 /* Emit a special USE insn for FLOATER, then delete
8877 the floating insn. */
8878 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8879 delete_insn (floater);
8887 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8890 int insn_code_number;
8893 /* Create a PARALLEL with the patterns of ANCHOR and
8894 FLOATER, try to recognize it, then test constraints
8895 for the resulting pattern.
8897 If the pattern doesn't match or the constraints
8898 aren't met keep searching for a suitable floater
8900 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8901 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8902 INSN_CODE (new) = -1;
8903 insn_code_number = recog_memoized (new);
8904 if (insn_code_number < 0
8905 || (extract_insn (new), ! constrain_operands (1)))
8919 /* There's up to three operands to consider. One
8920 output and two inputs.
8922 The output must not be used between FLOATER & ANCHOR
8923 exclusive. The inputs must not be set between
8924 FLOATER and ANCHOR exclusive. */
8926 if (reg_used_between_p (dest, start, end))
8929 if (reg_set_between_p (src1, start, end))
8932 if (reg_set_between_p (src2, start, end))
8935 /* If we get here, then everything is good. */
8939 /* Return nonzero if references for INSN are delayed.
8941 Millicode insns are actually function calls with some special
8942 constraints on arguments and register usage.
8944 Millicode calls always expect their arguments in the integer argument
8945 registers, and always return their result in %r29 (ret1). They
8946 are expected to clobber their arguments, %r1, %r29, and the return
8947 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8949 This function tells reorg that the references to arguments and
8950 millicode calls do not appear to happen until after the millicode call.
8951 This allows reorg to put insns which set the argument registers into the
8952 delay slot of the millicode call -- thus they act more like traditional
8955 Note we cannot consider side effects of the insn to be delayed because
8956 the branch and link insn will clobber the return pointer. If we happened
8957 to use the return pointer in the delay slot of the call, then we lose.
8959 get_attr_type will try to recognize the given insn, so make sure to
8960 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8963 insn_refs_are_delayed (rtx insn)
8965 return ((GET_CODE (insn) == INSN
8966 && GET_CODE (PATTERN (insn)) != SEQUENCE
8967 && GET_CODE (PATTERN (insn)) != USE
8968 && GET_CODE (PATTERN (insn)) != CLOBBER
8969 && get_attr_type (insn) == TYPE_MILLI));
8972 /* On the HP-PA the value is found in register(s) 28(-29), unless
8973 the mode is SF or DF. Then the value is returned in fr4 (32).
8975 This must perform the same promotions as PROMOTE_MODE, else
8976 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8978 Small structures must be returned in a PARALLEL on PA64 in order
8979 to match the HP Compiler ABI. */
8982 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8984 enum machine_mode valmode;
8986 if (AGGREGATE_TYPE_P (valtype)
8987 || TREE_CODE (valtype) == COMPLEX_TYPE
8988 || TREE_CODE (valtype) == VECTOR_TYPE)
8992 /* Aggregates with a size less than or equal to 128 bits are
8993 returned in GR 28(-29). They are left justified. The pad
8994 bits are undefined. Larger aggregates are returned in
8998 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9000 for (i = 0; i < ub; i++)
9002 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9003 gen_rtx_REG (DImode, 28 + i),
9008 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9010 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9012 /* Aggregates 5 to 8 bytes in size are returned in general
9013 registers r28-r29 in the same manner as other non
9014 floating-point objects. The data is right-justified and
9015 zero-extended to 64 bits. This is opposite to the normal
9016 justification used on big endian targets and requires
9017 special treatment. */
9018 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9019 gen_rtx_REG (DImode, 28), const0_rtx);
9020 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9024 if ((INTEGRAL_TYPE_P (valtype)
9025 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9026 || POINTER_TYPE_P (valtype))
9027 valmode = word_mode;
9029 valmode = TYPE_MODE (valtype);
9031 if (TREE_CODE (valtype) == REAL_TYPE
9032 && !AGGREGATE_TYPE_P (valtype)
9033 && TYPE_MODE (valtype) != TFmode
9034 && !TARGET_SOFT_FLOAT)
9035 return gen_rtx_REG (valmode, 32);
9037 return gen_rtx_REG (valmode, 28);
9040 /* Return the location of a parameter that is passed in a register or NULL
9041 if the parameter has any component that is passed in memory.
9043 This is new code and will be pushed to into the net sources after
9046 ??? We might want to restructure this so that it looks more like other
9049 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9050 int named ATTRIBUTE_UNUSED)
9052 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9059 if (mode == VOIDmode)
9062 arg_size = FUNCTION_ARG_SIZE (mode, type);
9064 /* If this arg would be passed partially or totally on the stack, then
9065 this routine should return zero. pa_arg_partial_bytes will
9066 handle arguments which are split between regs and stack slots if
9067 the ABI mandates split arguments. */
9070 /* The 32-bit ABI does not split arguments. */
9071 if (cum->words + arg_size > max_arg_words)
9077 alignment = cum->words & 1;
9078 if (cum->words + alignment >= max_arg_words)
9082 /* The 32bit ABIs and the 64bit ABIs are rather different,
9083 particularly in their handling of FP registers. We might
9084 be able to cleverly share code between them, but I'm not
9085 going to bother in the hope that splitting them up results
9086 in code that is more easily understood. */
9090 /* Advance the base registers to their current locations.
9092 Remember, gprs grow towards smaller register numbers while
9093 fprs grow to higher register numbers. Also remember that
9094 although FP regs are 32-bit addressable, we pretend that
9095 the registers are 64-bits wide. */
9096 gpr_reg_base = 26 - cum->words;
9097 fpr_reg_base = 32 + cum->words;
9099 /* Arguments wider than one word and small aggregates need special
9103 || (type && (AGGREGATE_TYPE_P (type)
9104 || TREE_CODE (type) == COMPLEX_TYPE
9105 || TREE_CODE (type) == VECTOR_TYPE)))
9107 /* Double-extended precision (80-bit), quad-precision (128-bit)
9108 and aggregates including complex numbers are aligned on
9109 128-bit boundaries. The first eight 64-bit argument slots
9110 are associated one-to-one, with general registers r26
9111 through r19, and also with floating-point registers fr4
9112 through fr11. Arguments larger than one word are always
9113 passed in general registers.
9115 Using a PARALLEL with a word mode register results in left
9116 justified data on a big-endian target. */
9119 int i, offset = 0, ub = arg_size;
9121 /* Align the base register. */
9122 gpr_reg_base -= alignment;
9124 ub = MIN (ub, max_arg_words - cum->words - alignment);
9125 for (i = 0; i < ub; i++)
9127 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9128 gen_rtx_REG (DImode, gpr_reg_base),
9134 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9139 /* If the argument is larger than a word, then we know precisely
9140 which registers we must use. */
9154 /* Structures 5 to 8 bytes in size are passed in the general
9155 registers in the same manner as other non floating-point
9156 objects. The data is right-justified and zero-extended
9157 to 64 bits. This is opposite to the normal justification
9158 used on big endian targets and requires special treatment.
9159 We now define BLOCK_REG_PADDING to pad these objects.
9160 Aggregates, complex and vector types are passed in the same
9161 manner as structures. */
9163 || (type && (AGGREGATE_TYPE_P (type)
9164 || TREE_CODE (type) == COMPLEX_TYPE
9165 || TREE_CODE (type) == VECTOR_TYPE)))
9167 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9168 gen_rtx_REG (DImode, gpr_reg_base),
9170 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9175 /* We have a single word (32 bits). A simple computation
9176 will get us the register #s we need. */
9177 gpr_reg_base = 26 - cum->words;
9178 fpr_reg_base = 32 + 2 * cum->words;
9182 /* Determine if the argument needs to be passed in both general and
9183 floating point registers. */
9184 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9185 /* If we are doing soft-float with portable runtime, then there
9186 is no need to worry about FP regs. */
9187 && !TARGET_SOFT_FLOAT
9188 /* The parameter must be some kind of scalar float, else we just
9189 pass it in integer registers. */
9190 && GET_MODE_CLASS (mode) == MODE_FLOAT
9191 /* The target function must not have a prototype. */
9192 && cum->nargs_prototype <= 0
9193 /* libcalls do not need to pass items in both FP and general
9195 && type != NULL_TREE
9196 /* All this hair applies to "outgoing" args only. This includes
9197 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9199 /* Also pass outgoing floating arguments in both registers in indirect
9200 calls with the 32 bit ABI and the HP assembler since there is no
9201 way to the specify argument locations in static functions. */
9206 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9212 gen_rtx_EXPR_LIST (VOIDmode,
9213 gen_rtx_REG (mode, fpr_reg_base),
9215 gen_rtx_EXPR_LIST (VOIDmode,
9216 gen_rtx_REG (mode, gpr_reg_base),
9221 /* See if we should pass this parameter in a general register. */
9222 if (TARGET_SOFT_FLOAT
9223 /* Indirect calls in the normal 32bit ABI require all arguments
9224 to be passed in general registers. */
9225 || (!TARGET_PORTABLE_RUNTIME
9229 /* If the parameter is not a scalar floating-point parameter,
9230 then it belongs in GPRs. */
9231 || GET_MODE_CLASS (mode) != MODE_FLOAT
9232 /* Structure with single SFmode field belongs in GPR. */
9233 || (type && AGGREGATE_TYPE_P (type)))
9234 retval = gen_rtx_REG (mode, gpr_reg_base);
9236 retval = gen_rtx_REG (mode, fpr_reg_base);
9242 /* If this arg would be passed totally in registers or totally on the stack,
9243 then this routine should return zero. */
9246 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9247 tree type, bool named ATTRIBUTE_UNUSED)
9249 unsigned int max_arg_words = 8;
9250 unsigned int offset = 0;
9255 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9258 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9259 /* Arg fits fully into registers. */
9261 else if (cum->words + offset >= max_arg_words)
9262 /* Arg fully on the stack. */
9266 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9270 /* A get_unnamed_section callback for switching to the text section.
9272 This function is only used with SOM. Because we don't support
9273 named subspaces, we can only create a new subspace or switch back
9274 to the default text subspace. */
9277 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9279 gcc_assert (TARGET_SOM);
9282 if (cfun && !cfun->machine->in_nsubspa)
9284 /* We only want to emit a .nsubspa directive once at the
9285 start of the function. */
9286 cfun->machine->in_nsubspa = 1;
9288 /* Create a new subspace for the text. This provides
9289 better stub placement and one-only functions. */
9291 && DECL_ONE_ONLY (cfun->decl)
9292 && !DECL_WEAK (cfun->decl))
9294 output_section_asm_op ("\t.SPACE $TEXT$\n"
9295 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9296 "ACCESS=44,SORT=24,COMDAT");
9302 /* There isn't a current function or the body of the current
9303 function has been completed. So, we are changing to the
9304 text section to output debugging information. Thus, we
9305 need to forget that we are in the text section so that
9306 varasm.c will call us when text_section is selected again. */
9307 gcc_assert (!cfun || cfun->machine->in_nsubspa == 2);
9310 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9313 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9316 /* A get_unnamed_section callback for switching to comdat data
9317 sections. This function is only used with SOM. */
9320 som_output_comdat_data_section_asm_op (const void *data)
9323 output_section_asm_op (data);
9326 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9329 pa_som_asm_init_sections (void)
9332 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9334 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9335 is not being generated. */
9336 som_readonly_data_section
9337 = get_unnamed_section (0, output_section_asm_op,
9338 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9340 /* When secondary definitions are not supported, SOM makes readonly
9341 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9343 som_one_only_readonly_data_section
9344 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9346 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9347 "ACCESS=0x2c,SORT=16,COMDAT");
9350 /* When secondary definitions are not supported, SOM makes data one-only
9351 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9352 som_one_only_data_section
9353 = get_unnamed_section (SECTION_WRITE,
9354 som_output_comdat_data_section_asm_op,
9355 "\t.SPACE $PRIVATE$\n"
9356 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9357 "ACCESS=31,SORT=24,COMDAT");
9359 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9360 which reference data within the $TEXT$ space (for example constant
9361 strings in the $LIT$ subspace).
9363 The assemblers (GAS and HP as) both have problems with handling
9364 the difference of two symbols which is the other correct way to
9365 reference constant data during PIC code generation.
9367 So, there's no way to reference constant data which is in the
9368 $TEXT$ space during PIC generation. Instead place all constant
9369 data into the $PRIVATE$ subspace (this reduces sharing, but it
9370 works correctly). */
9371 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9373 /* We must not have a reference to an external symbol defined in a
9374 shared library in a readonly section, else the SOM linker will
9377 So, we force exception information into the data section. */
9378 exception_section = data_section;
9381 /* On hpux10, the linker will give an error if we have a reference
9382 in the read-only data section to a symbol defined in a shared
9383 library. Therefore, expressions that might require a reloc can
9384 not be placed in the read-only data section. */
9387 pa_select_section (tree exp, int reloc,
9388 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9390 if (TREE_CODE (exp) == VAR_DECL
9391 && TREE_READONLY (exp)
9392 && !TREE_THIS_VOLATILE (exp)
9393 && DECL_INITIAL (exp)
9394 && (DECL_INITIAL (exp) == error_mark_node
9395 || TREE_CONSTANT (DECL_INITIAL (exp)))
9399 && DECL_ONE_ONLY (exp)
9400 && !DECL_WEAK (exp))
9401 return som_one_only_readonly_data_section;
9403 return readonly_data_section;
9405 else if (CONSTANT_CLASS_P (exp) && !reloc)
9406 return readonly_data_section;
9408 && TREE_CODE (exp) == VAR_DECL
9409 && DECL_ONE_ONLY (exp)
9410 && !DECL_WEAK (exp))
9411 return som_one_only_data_section;
9413 return data_section;
9417 pa_globalize_label (FILE *stream, const char *name)
9419 /* We only handle DATA objects here, functions are globalized in
9420 ASM_DECLARE_FUNCTION_NAME. */
9421 if (! FUNCTION_NAME_P (name))
9423 fputs ("\t.EXPORT ", stream);
9424 assemble_name (stream, name);
9425 fputs (",DATA\n", stream);
9429 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9432 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9433 int incoming ATTRIBUTE_UNUSED)
9435 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9438 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9441 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9443 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9444 PA64 ABI says that objects larger than 128 bits are returned in memory.
9445 Note, int_size_in_bytes can return -1 if the size of the object is
9446 variable or larger than the maximum value that can be expressed as
9447 a HOST_WIDE_INT. It can also return zero for an empty type. The
9448 simplest way to handle variable and empty types is to pass them in
9449 memory. This avoids problems in defining the boundaries of argument
9450 slots, allocating registers, etc. */
9451 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9452 || int_size_in_bytes (type) <= 0);
9455 /* Structure to hold declaration and name of external symbols that are
9456 emitted by GCC. We generate a vector of these symbols and output them
9457 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9458 This avoids putting out names that are never really used. */
9460 typedef struct extern_symbol GTY(())
9466 /* Define gc'd vector type for extern_symbol. */
9467 DEF_VEC_O(extern_symbol);
9468 DEF_VEC_ALLOC_O(extern_symbol,gc);
9470 /* Vector of extern_symbol pointers. */
9471 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9473 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9474 /* Mark DECL (name NAME) as an external reference (assembler output
9475 file FILE). This saves the names to output at the end of the file
9476 if actually referenced. */
9479 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9481 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9483 gcc_assert (file == asm_out_file);
9488 /* Output text required at the end of an assembler file.
9489 This includes deferred plabels and .import directives for
9490 all external symbols that were actually referenced. */
9493 pa_hpux_file_end (void)
9498 if (!NO_DEFERRED_PROFILE_COUNTERS)
9499 output_deferred_profile_counters ();
9501 output_deferred_plabels ();
9503 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9505 tree decl = p->decl;
9507 if (!TREE_ASM_WRITTEN (decl)
9508 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9509 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9512 VEC_free (extern_symbol, gc, extern_symbols);