1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
42 #include "diagnostic-core.h"
49 #include "target-def.h"
52 /* Return nonzero if there is a bypass for the output of
53 OUT_INSN and the fp store IN_INSN. */
55 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
57 enum machine_mode store_mode;
58 enum machine_mode other_mode;
61 if (recog_memoized (in_insn) < 0
62 || (get_attr_type (in_insn) != TYPE_FPSTORE
63 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
64 || recog_memoized (out_insn) < 0)
67 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
69 set = single_set (out_insn);
73 other_mode = GET_MODE (SET_SRC (set));
75 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
79 #ifndef DO_FRAME_NOTES
80 #ifdef INCOMING_RETURN_ADDR_RTX
81 #define DO_FRAME_NOTES 1
83 #define DO_FRAME_NOTES 0
87 static void pa_option_override (void);
88 static void copy_reg_pointer (rtx, rtx);
89 static void fix_range (const char *);
90 static bool pa_handle_option (size_t, const char *, int);
91 static int hppa_register_move_cost (enum machine_mode mode, reg_class_t,
93 static int hppa_address_cost (rtx, bool);
94 static bool hppa_rtx_costs (rtx, int, int, int *, bool);
95 static inline rtx force_mode (enum machine_mode, rtx);
96 static void pa_reorg (void);
97 static void pa_combine_instructions (void);
98 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
99 static bool forward_branch_p (rtx);
100 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
101 static int compute_movmem_length (rtx);
102 static int compute_clrmem_length (rtx);
103 static bool pa_assemble_integer (rtx, unsigned int, int);
104 static void remove_useless_addtr_insns (int);
105 static void store_reg (int, HOST_WIDE_INT, int);
106 static void store_reg_modify (int, int, HOST_WIDE_INT);
107 static void load_reg (int, HOST_WIDE_INT, int);
108 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
109 static rtx pa_function_value (const_tree, const_tree, bool);
110 static rtx pa_libcall_value (enum machine_mode, const_rtx);
111 static bool pa_function_value_regno_p (const unsigned int);
112 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
113 static void update_total_code_bytes (unsigned int);
114 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static int pa_adjust_cost (rtx, rtx, rtx, int);
116 static int pa_adjust_priority (rtx, int);
117 static int pa_issue_rate (void);
118 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
119 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
121 static void pa_encode_section_info (tree, rtx, int);
122 static const char *pa_strip_name_encoding (const char *);
123 static bool pa_function_ok_for_sibcall (tree, tree);
124 static void pa_globalize_label (FILE *, const char *)
126 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
127 HOST_WIDE_INT, tree);
128 #if !defined(USE_COLLECT2)
129 static void pa_asm_out_constructor (rtx, int);
130 static void pa_asm_out_destructor (rtx, int);
132 static void pa_init_builtins (void);
133 static rtx hppa_builtin_saveregs (void);
134 static void hppa_va_start (tree, rtx);
135 static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
136 static bool pa_scalar_mode_supported_p (enum machine_mode);
137 static bool pa_commutative_p (const_rtx x, int outer_code);
138 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
139 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
140 static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
141 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
142 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
143 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
144 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
145 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
146 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
147 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
148 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
149 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
150 static void output_deferred_plabels (void);
151 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
152 #ifdef ASM_OUTPUT_EXTERNAL_REAL
153 static void pa_hpux_file_end (void);
155 #ifdef HPUX_LONG_DOUBLE_LIBRARY
156 static void pa_hpux_init_libfuncs (void);
158 static rtx pa_struct_value_rtx (tree, int);
159 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
161 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
163 static void pa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
165 static rtx pa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
167 static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree);
168 static struct machine_function * pa_init_machine_status (void);
169 static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
171 secondary_reload_info *);
172 static void pa_extra_live_on_entry (bitmap);
173 static enum machine_mode pa_promote_function_mode (const_tree,
174 enum machine_mode, int *,
177 static void pa_asm_trampoline_template (FILE *);
178 static void pa_trampoline_init (rtx, tree, rtx);
179 static rtx pa_trampoline_adjust_address (rtx);
180 static rtx pa_delegitimize_address (rtx);
181 static bool pa_print_operand_punct_valid_p (unsigned char);
182 static rtx pa_internal_arg_pointer (void);
183 static bool pa_can_eliminate (const int, const int);
184 static void pa_conditional_register_usage (void);
186 /* The following extra sections are only used for SOM. */
187 static GTY(()) section *som_readonly_data_section;
188 static GTY(()) section *som_one_only_readonly_data_section;
189 static GTY(()) section *som_one_only_data_section;
191 /* Which cpu we are scheduling for. */
192 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
194 /* The UNIX standard to use for predefines and linking. */
195 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
197 /* Counts for the number of callee-saved general and floating point
198 registers which were saved by the current function's prologue. */
199 static int gr_saved, fr_saved;
201 /* Boolean indicating whether the return pointer was saved by the
202 current function's prologue. */
203 static bool rp_saved;
205 static rtx find_addr_reg (rtx);
207 /* Keep track of the number of bytes we have output in the CODE subspace
208 during this compilation so we'll know when to emit inline long-calls. */
209 unsigned long total_code_bytes;
211 /* The last address of the previous function plus the number of bytes in
212 associated thunks that have been output. This is used to determine if
213 a thunk can use an IA-relative branch to reach its target function. */
214 static unsigned int last_address;
216 /* Variables to handle plabels that we discover are necessary at assembly
217 output time. They are output after the current function. */
218 struct GTY(()) deferred_plabel
223 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
225 static size_t n_deferred_plabels = 0;
227 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
228 static const struct default_options pa_option_optimization_table[] =
230 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
231 { OPT_LEVELS_NONE, 0, NULL, 0 }
235 /* Initialize the GCC target structure. */
237 #undef TARGET_OPTION_OVERRIDE
238 #define TARGET_OPTION_OVERRIDE pa_option_override
239 #undef TARGET_OPTION_OPTIMIZATION_TABLE
240 #define TARGET_OPTION_OPTIMIZATION_TABLE pa_option_optimization_table
242 #undef TARGET_ASM_ALIGNED_HI_OP
243 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
244 #undef TARGET_ASM_ALIGNED_SI_OP
245 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
246 #undef TARGET_ASM_ALIGNED_DI_OP
247 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
248 #undef TARGET_ASM_UNALIGNED_HI_OP
249 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
250 #undef TARGET_ASM_UNALIGNED_SI_OP
251 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
252 #undef TARGET_ASM_UNALIGNED_DI_OP
253 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
254 #undef TARGET_ASM_INTEGER
255 #define TARGET_ASM_INTEGER pa_assemble_integer
257 #undef TARGET_ASM_FUNCTION_PROLOGUE
258 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
259 #undef TARGET_ASM_FUNCTION_EPILOGUE
260 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
262 #undef TARGET_FUNCTION_VALUE
263 #define TARGET_FUNCTION_VALUE pa_function_value
264 #undef TARGET_LIBCALL_VALUE
265 #define TARGET_LIBCALL_VALUE pa_libcall_value
266 #undef TARGET_FUNCTION_VALUE_REGNO_P
267 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
269 #undef TARGET_LEGITIMIZE_ADDRESS
270 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
272 #undef TARGET_SCHED_ADJUST_COST
273 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
274 #undef TARGET_SCHED_ADJUST_PRIORITY
275 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
276 #undef TARGET_SCHED_ISSUE_RATE
277 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
279 #undef TARGET_ENCODE_SECTION_INFO
280 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
281 #undef TARGET_STRIP_NAME_ENCODING
282 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
284 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
285 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
287 #undef TARGET_COMMUTATIVE_P
288 #define TARGET_COMMUTATIVE_P pa_commutative_p
290 #undef TARGET_ASM_OUTPUT_MI_THUNK
291 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
292 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
293 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
295 #undef TARGET_ASM_FILE_END
296 #ifdef ASM_OUTPUT_EXTERNAL_REAL
297 #define TARGET_ASM_FILE_END pa_hpux_file_end
299 #define TARGET_ASM_FILE_END output_deferred_plabels
302 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
303 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
305 #if !defined(USE_COLLECT2)
306 #undef TARGET_ASM_CONSTRUCTOR
307 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
308 #undef TARGET_ASM_DESTRUCTOR
309 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
312 #undef TARGET_DEFAULT_TARGET_FLAGS
313 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
314 #undef TARGET_HANDLE_OPTION
315 #define TARGET_HANDLE_OPTION pa_handle_option
317 #undef TARGET_INIT_BUILTINS
318 #define TARGET_INIT_BUILTINS pa_init_builtins
320 #undef TARGET_REGISTER_MOVE_COST
321 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
322 #undef TARGET_RTX_COSTS
323 #define TARGET_RTX_COSTS hppa_rtx_costs
324 #undef TARGET_ADDRESS_COST
325 #define TARGET_ADDRESS_COST hppa_address_cost
327 #undef TARGET_MACHINE_DEPENDENT_REORG
328 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
330 #ifdef HPUX_LONG_DOUBLE_LIBRARY
331 #undef TARGET_INIT_LIBFUNCS
332 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
335 #undef TARGET_PROMOTE_FUNCTION_MODE
336 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
337 #undef TARGET_PROMOTE_PROTOTYPES
338 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
340 #undef TARGET_STRUCT_VALUE_RTX
341 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
342 #undef TARGET_RETURN_IN_MEMORY
343 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
344 #undef TARGET_MUST_PASS_IN_STACK
345 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
346 #undef TARGET_PASS_BY_REFERENCE
347 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
348 #undef TARGET_CALLEE_COPIES
349 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
350 #undef TARGET_ARG_PARTIAL_BYTES
351 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
352 #undef TARGET_FUNCTION_ARG
353 #define TARGET_FUNCTION_ARG pa_function_arg
354 #undef TARGET_FUNCTION_ARG_ADVANCE
355 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
356 #undef TARGET_FUNCTION_ARG_BOUNDARY
357 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
359 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
360 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
361 #undef TARGET_EXPAND_BUILTIN_VA_START
362 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
363 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
364 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
366 #undef TARGET_SCALAR_MODE_SUPPORTED_P
367 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
369 #undef TARGET_CANNOT_FORCE_CONST_MEM
370 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
372 #undef TARGET_SECONDARY_RELOAD
373 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
375 #undef TARGET_EXTRA_LIVE_ON_ENTRY
376 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
378 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
379 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
380 #undef TARGET_TRAMPOLINE_INIT
381 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
382 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
383 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
384 #undef TARGET_DELEGITIMIZE_ADDRESS
385 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
386 #undef TARGET_INTERNAL_ARG_POINTER
387 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
388 #undef TARGET_CAN_ELIMINATE
389 #define TARGET_CAN_ELIMINATE pa_can_eliminate
390 #undef TARGET_CONDITIONAL_REGISTER_USAGE
391 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
393 struct gcc_target targetm = TARGET_INITIALIZER;
395 /* Parse the -mfixed-range= option string. */
398 fix_range (const char *const_str)
401 char *str, *dash, *comma;
403 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
404 REG2 are either register names or register numbers. The effect
405 of this option is to mark the registers in the range from REG1 to
406 REG2 as ``fixed'' so they won't be used by the compiler. This is
407 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
409 i = strlen (const_str);
410 str = (char *) alloca (i + 1);
411 memcpy (str, const_str, i + 1);
415 dash = strchr (str, '-');
418 warning (0, "value of -mfixed-range must have form REG1-REG2");
423 comma = strchr (dash + 1, ',');
427 first = decode_reg_name (str);
430 warning (0, "unknown register name: %s", str);
434 last = decode_reg_name (dash + 1);
437 warning (0, "unknown register name: %s", dash + 1);
445 warning (0, "%s-%s is an empty range", str, dash + 1);
449 for (i = first; i <= last; ++i)
450 fixed_regs[i] = call_used_regs[i] = 1;
459 /* Check if all floating point registers have been fixed. */
460 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
465 target_flags |= MASK_DISABLE_FPREGS;
468 /* Implement TARGET_HANDLE_OPTION. */
471 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
476 case OPT_mpa_risc_1_0:
478 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
482 case OPT_mpa_risc_1_1:
484 target_flags &= ~MASK_PA_20;
485 target_flags |= MASK_PA_11;
488 case OPT_mpa_risc_2_0:
490 target_flags |= MASK_PA_11 | MASK_PA_20;
494 if (strcmp (arg, "8000") == 0)
495 pa_cpu = PROCESSOR_8000;
496 else if (strcmp (arg, "7100") == 0)
497 pa_cpu = PROCESSOR_7100;
498 else if (strcmp (arg, "700") == 0)
499 pa_cpu = PROCESSOR_700;
500 else if (strcmp (arg, "7100LC") == 0)
501 pa_cpu = PROCESSOR_7100LC;
502 else if (strcmp (arg, "7200") == 0)
503 pa_cpu = PROCESSOR_7200;
504 else if (strcmp (arg, "7300") == 0)
505 pa_cpu = PROCESSOR_7300;
510 case OPT_mfixed_range_:
520 #if TARGET_HPUX_10_10
526 #if TARGET_HPUX_11_11
537 /* Implement the TARGET_OPTION_OVERRIDE hook. */
540 pa_option_override (void)
542 /* Unconditional branches in the delay slot are not compatible with dwarf2
543 call frame information. There is no benefit in using this optimization
544 on PA8000 and later processors. */
545 if (pa_cpu >= PROCESSOR_8000
546 || (targetm.except_unwind_info () == UI_DWARF2 && flag_exceptions)
547 || flag_unwind_tables)
548 target_flags &= ~MASK_JUMP_IN_DELAY;
550 if (flag_pic && TARGET_PORTABLE_RUNTIME)
552 warning (0, "PIC code generation is not supported in the portable runtime model");
555 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
557 warning (0, "PIC code generation is not compatible with fast indirect calls");
560 if (! TARGET_GAS && write_symbols != NO_DEBUG)
562 warning (0, "-g is only supported when using GAS on this processor,");
563 warning (0, "-g option disabled");
564 write_symbols = NO_DEBUG;
567 /* We only support the "big PIC" model now. And we always generate PIC
568 code when in 64bit mode. */
569 if (flag_pic == 1 || TARGET_64BIT)
572 /* Disable -freorder-blocks-and-partition as we don't support hot and
573 cold partitioning. */
574 if (flag_reorder_blocks_and_partition)
576 inform (input_location,
577 "-freorder-blocks-and-partition does not work "
578 "on this architecture");
579 flag_reorder_blocks_and_partition = 0;
580 flag_reorder_blocks = 1;
583 /* We can't guarantee that .dword is available for 32-bit targets. */
584 if (UNITS_PER_WORD == 4)
585 targetm.asm_out.aligned_op.di = NULL;
587 /* The unaligned ops are only available when using GAS. */
590 targetm.asm_out.unaligned_op.hi = NULL;
591 targetm.asm_out.unaligned_op.si = NULL;
592 targetm.asm_out.unaligned_op.di = NULL;
595 init_machine_status = pa_init_machine_status;
599 pa_init_builtins (void)
601 #ifdef DONT_HAVE_FPUTC_UNLOCKED
602 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
603 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
604 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
605 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
608 if (built_in_decls [BUILT_IN_FINITE])
609 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
610 if (built_in_decls [BUILT_IN_FINITEF])
611 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
615 /* Function to init struct machine_function.
616 This will be called, via a pointer variable,
617 from push_function_context. */
619 static struct machine_function *
620 pa_init_machine_status (void)
622 return ggc_alloc_cleared_machine_function ();
625 /* If FROM is a probable pointer register, mark TO as a probable
626 pointer register with the same pointer alignment as FROM. */
629 copy_reg_pointer (rtx to, rtx from)
631 if (REG_POINTER (from))
632 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
635 /* Return 1 if X contains a symbolic expression. We know these
636 expressions will have one of a few well defined forms, so
637 we need only check those forms. */
639 symbolic_expression_p (rtx x)
642 /* Strip off any HIGH. */
643 if (GET_CODE (x) == HIGH)
646 return (symbolic_operand (x, VOIDmode));
649 /* Accept any constant that can be moved in one instruction into a
652 cint_ok_for_move (HOST_WIDE_INT ival)
654 /* OK if ldo, ldil, or zdepi, can be used. */
655 return (VAL_14_BITS_P (ival)
656 || ldil_cint_p (ival)
657 || zdepi_cint_p (ival));
660 /* Return truth value of whether OP can be used as an operand in a
663 adddi3_operand (rtx op, enum machine_mode mode)
665 return (register_operand (op, mode)
666 || (GET_CODE (op) == CONST_INT
667 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
670 /* True iff the operand OP can be used as the destination operand of
671 an integer store. This also implies the operand could be used as
672 the source operand of an integer load. Symbolic, lo_sum and indexed
673 memory operands are not allowed. We accept reloading pseudos and
674 other memory operands. */
676 integer_store_memory_operand (rtx op, enum machine_mode mode)
678 return ((reload_in_progress
680 && REGNO (op) >= FIRST_PSEUDO_REGISTER
681 && reg_renumber [REGNO (op)] < 0)
682 || (GET_CODE (op) == MEM
683 && (reload_in_progress || memory_address_p (mode, XEXP (op, 0)))
684 && !symbolic_memory_operand (op, VOIDmode)
685 && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))
686 && !IS_INDEX_ADDR_P (XEXP (op, 0))));
689 /* True iff ldil can be used to load this CONST_INT. The least
690 significant 11 bits of the value must be zero and the value must
691 not change sign when extended from 32 to 64 bits. */
693 ldil_cint_p (HOST_WIDE_INT ival)
695 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
697 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
700 /* True iff zdepi can be used to generate this CONST_INT.
701 zdepi first sign extends a 5-bit signed number to a given field
702 length, then places this field anywhere in a zero. */
704 zdepi_cint_p (unsigned HOST_WIDE_INT x)
706 unsigned HOST_WIDE_INT lsb_mask, t;
708 /* This might not be obvious, but it's at least fast.
709 This function is critical; we don't have the time loops would take. */
711 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
712 /* Return true iff t is a power of two. */
713 return ((t & (t - 1)) == 0);
716 /* True iff depi or extru can be used to compute (reg & mask).
717 Accept bit pattern like these:
722 and_mask_p (unsigned HOST_WIDE_INT mask)
725 mask += mask & -mask;
726 return (mask & (mask - 1)) == 0;
729 /* True iff depi can be used to compute (reg | MASK). */
731 ior_mask_p (unsigned HOST_WIDE_INT mask)
733 mask += mask & -mask;
734 return (mask & (mask - 1)) == 0;
737 /* Legitimize PIC addresses. If the address is already
738 position-independent, we return ORIG. Newly generated
739 position-independent addresses go to REG. If we need more
740 than one register, we lose. */
743 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
747 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
749 /* Labels need special handling. */
750 if (pic_label_operand (orig, mode))
754 /* We do not want to go through the movXX expanders here since that
755 would create recursion.
757 Nor do we really want to call a generator for a named pattern
758 since that requires multiple patterns if we want to support
761 So instead we just emit the raw set, which avoids the movXX
762 expanders completely. */
763 mark_reg_pointer (reg, BITS_PER_UNIT);
764 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
766 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
767 add_reg_note (insn, REG_EQUAL, orig);
769 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
770 and update LABEL_NUSES because this is not done automatically. */
771 if (reload_in_progress || reload_completed)
773 /* Extract LABEL_REF. */
774 if (GET_CODE (orig) == CONST)
775 orig = XEXP (XEXP (orig, 0), 0);
776 /* Extract CODE_LABEL. */
777 orig = XEXP (orig, 0);
778 add_reg_note (insn, REG_LABEL_OPERAND, orig);
779 LABEL_NUSES (orig)++;
781 crtl->uses_pic_offset_table = 1;
784 if (GET_CODE (orig) == SYMBOL_REF)
790 /* Before reload, allocate a temporary register for the intermediate
791 result. This allows the sequence to be deleted when the final
792 result is unused and the insns are trivially dead. */
793 tmp_reg = ((reload_in_progress || reload_completed)
794 ? reg : gen_reg_rtx (Pmode));
796 if (function_label_operand (orig, mode))
798 /* Force function label into memory in word mode. */
799 orig = XEXP (force_const_mem (word_mode, orig), 0);
800 /* Load plabel address from DLT. */
801 emit_move_insn (tmp_reg,
802 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
803 gen_rtx_HIGH (word_mode, orig)));
805 = gen_const_mem (Pmode,
806 gen_rtx_LO_SUM (Pmode, tmp_reg,
807 gen_rtx_UNSPEC (Pmode,
810 emit_move_insn (reg, pic_ref);
811 /* Now load address of function descriptor. */
812 pic_ref = gen_rtx_MEM (Pmode, reg);
816 /* Load symbol reference from DLT. */
817 emit_move_insn (tmp_reg,
818 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
819 gen_rtx_HIGH (word_mode, orig)));
821 = gen_const_mem (Pmode,
822 gen_rtx_LO_SUM (Pmode, tmp_reg,
823 gen_rtx_UNSPEC (Pmode,
828 crtl->uses_pic_offset_table = 1;
829 mark_reg_pointer (reg, BITS_PER_UNIT);
830 insn = emit_move_insn (reg, pic_ref);
832 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
833 set_unique_reg_note (insn, REG_EQUAL, orig);
837 else if (GET_CODE (orig) == CONST)
841 if (GET_CODE (XEXP (orig, 0)) == PLUS
842 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
846 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
848 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
849 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
850 base == reg ? 0 : reg);
852 if (GET_CODE (orig) == CONST_INT)
854 if (INT_14_BITS (orig))
855 return plus_constant (base, INTVAL (orig));
856 orig = force_reg (Pmode, orig);
858 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
859 /* Likewise, should we set special REG_NOTEs here? */
865 static GTY(()) rtx gen_tls_tga;
868 gen_tls_get_addr (void)
871 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
876 hppa_tls_call (rtx arg)
880 ret = gen_reg_rtx (Pmode);
881 emit_library_call_value (gen_tls_get_addr (), ret,
882 LCT_CONST, Pmode, 1, arg, Pmode);
888 legitimize_tls_address (rtx addr)
890 rtx ret, insn, tmp, t1, t2, tp;
891 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
895 case TLS_MODEL_GLOBAL_DYNAMIC:
896 tmp = gen_reg_rtx (Pmode);
898 emit_insn (gen_tgd_load_pic (tmp, addr));
900 emit_insn (gen_tgd_load (tmp, addr));
901 ret = hppa_tls_call (tmp);
904 case TLS_MODEL_LOCAL_DYNAMIC:
905 ret = gen_reg_rtx (Pmode);
906 tmp = gen_reg_rtx (Pmode);
909 emit_insn (gen_tld_load_pic (tmp, addr));
911 emit_insn (gen_tld_load (tmp, addr));
912 t1 = hppa_tls_call (tmp);
915 t2 = gen_reg_rtx (Pmode);
916 emit_libcall_block (insn, t2, t1,
917 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
919 emit_insn (gen_tld_offset_load (ret, addr, t2));
922 case TLS_MODEL_INITIAL_EXEC:
923 tp = gen_reg_rtx (Pmode);
924 tmp = gen_reg_rtx (Pmode);
925 ret = gen_reg_rtx (Pmode);
926 emit_insn (gen_tp_load (tp));
928 emit_insn (gen_tie_load_pic (tmp, addr));
930 emit_insn (gen_tie_load (tmp, addr));
931 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
934 case TLS_MODEL_LOCAL_EXEC:
935 tp = gen_reg_rtx (Pmode);
936 ret = gen_reg_rtx (Pmode);
937 emit_insn (gen_tp_load (tp));
938 emit_insn (gen_tle_load (ret, addr, tp));
948 /* Try machine-dependent ways of modifying an illegitimate address
949 to be legitimate. If we find one, return the new, valid address.
950 This macro is used in only one place: `memory_address' in explow.c.
952 OLDX is the address as it was before break_out_memory_refs was called.
953 In some cases it is useful to look at this to decide what needs to be done.
955 It is always safe for this macro to do nothing. It exists to recognize
956 opportunities to optimize the output.
958 For the PA, transform:
960 memory(X + <large int>)
964 if (<large int> & mask) >= 16
965 Y = (<large int> & ~mask) + mask + 1 Round up.
967 Y = (<large int> & ~mask) Round down.
969 memory (Z + (<large int> - Y));
971 This is for CSE to find several similar references, and only use one Z.
973 X can either be a SYMBOL_REF or REG, but because combine cannot
974 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
975 D will not fit in 14 bits.
977 MODE_FLOAT references allow displacements which fit in 5 bits, so use
980 MODE_INT references allow displacements which fit in 14 bits, so use
983 This relies on the fact that most mode MODE_FLOAT references will use FP
984 registers and most mode MODE_INT references will use integer registers.
985 (In the rare case of an FP register used in an integer MODE, we depend
986 on secondary reloads to clean things up.)
989 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
990 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
991 addressing modes to be used).
993 Put X and Z into registers. Then put the entire expression into
997 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
998 enum machine_mode mode)
1002 /* We need to canonicalize the order of operands in unscaled indexed
1003 addresses since the code that checks if an address is valid doesn't
1004 always try both orders. */
1005 if (!TARGET_NO_SPACE_REGS
1006 && GET_CODE (x) == PLUS
1007 && GET_MODE (x) == Pmode
1008 && REG_P (XEXP (x, 0))
1009 && REG_P (XEXP (x, 1))
1010 && REG_POINTER (XEXP (x, 0))
1011 && !REG_POINTER (XEXP (x, 1)))
1012 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1014 if (PA_SYMBOL_REF_TLS_P (x))
1015 return legitimize_tls_address (x);
1017 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1019 /* Strip off CONST. */
1020 if (GET_CODE (x) == CONST)
1023 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1024 That should always be safe. */
1025 if (GET_CODE (x) == PLUS
1026 && GET_CODE (XEXP (x, 0)) == REG
1027 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1029 rtx reg = force_reg (Pmode, XEXP (x, 1));
1030 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1033 /* Note we must reject symbols which represent function addresses
1034 since the assembler/linker can't handle arithmetic on plabels. */
1035 if (GET_CODE (x) == PLUS
1036 && GET_CODE (XEXP (x, 1)) == CONST_INT
1037 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1038 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1039 || GET_CODE (XEXP (x, 0)) == REG))
1041 rtx int_part, ptr_reg;
1043 int offset = INTVAL (XEXP (x, 1));
1046 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1047 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
1049 /* Choose which way to round the offset. Round up if we
1050 are >= halfway to the next boundary. */
1051 if ((offset & mask) >= ((mask + 1) / 2))
1052 newoffset = (offset & ~ mask) + mask + 1;
1054 newoffset = (offset & ~ mask);
1056 /* If the newoffset will not fit in 14 bits (ldo), then
1057 handling this would take 4 or 5 instructions (2 to load
1058 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1059 add the new offset and the SYMBOL_REF.) Combine can
1060 not handle 4->2 or 5->2 combinations, so do not create
1062 if (! VAL_14_BITS_P (newoffset)
1063 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1065 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1068 gen_rtx_HIGH (Pmode, const_part));
1071 gen_rtx_LO_SUM (Pmode,
1072 tmp_reg, const_part));
1076 if (! VAL_14_BITS_P (newoffset))
1077 int_part = force_reg (Pmode, GEN_INT (newoffset));
1079 int_part = GEN_INT (newoffset);
1081 ptr_reg = force_reg (Pmode,
1082 gen_rtx_PLUS (Pmode,
1083 force_reg (Pmode, XEXP (x, 0)),
1086 return plus_constant (ptr_reg, offset - newoffset);
1089 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1091 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1092 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1093 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1094 && (OBJECT_P (XEXP (x, 1))
1095 || GET_CODE (XEXP (x, 1)) == SUBREG)
1096 && GET_CODE (XEXP (x, 1)) != CONST)
1098 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1102 if (GET_CODE (reg1) != REG)
1103 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1105 reg2 = XEXP (XEXP (x, 0), 0);
1106 if (GET_CODE (reg2) != REG)
1107 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1109 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1110 gen_rtx_MULT (Pmode,
1116 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1118 Only do so for floating point modes since this is more speculative
1119 and we lose if it's an integer store. */
1120 if (GET_CODE (x) == PLUS
1121 && GET_CODE (XEXP (x, 0)) == PLUS
1122 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1123 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1124 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1125 && (mode == SFmode || mode == DFmode))
1128 /* First, try and figure out what to use as a base register. */
1129 rtx reg1, reg2, base, idx;
1131 reg1 = XEXP (XEXP (x, 0), 1);
1136 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1137 then emit_move_sequence will turn on REG_POINTER so we'll know
1138 it's a base register below. */
1139 if (GET_CODE (reg1) != REG)
1140 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1142 if (GET_CODE (reg2) != REG)
1143 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1145 /* Figure out what the base and index are. */
1147 if (GET_CODE (reg1) == REG
1148 && REG_POINTER (reg1))
1151 idx = gen_rtx_PLUS (Pmode,
1152 gen_rtx_MULT (Pmode,
1153 XEXP (XEXP (XEXP (x, 0), 0), 0),
1154 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1157 else if (GET_CODE (reg2) == REG
1158 && REG_POINTER (reg2))
1167 /* If the index adds a large constant, try to scale the
1168 constant so that it can be loaded with only one insn. */
1169 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1170 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1171 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1172 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1174 /* Divide the CONST_INT by the scale factor, then add it to A. */
1175 int val = INTVAL (XEXP (idx, 1));
1177 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1178 reg1 = XEXP (XEXP (idx, 0), 0);
1179 if (GET_CODE (reg1) != REG)
1180 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1182 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1184 /* We can now generate a simple scaled indexed address. */
1187 (Pmode, gen_rtx_PLUS (Pmode,
1188 gen_rtx_MULT (Pmode, reg1,
1189 XEXP (XEXP (idx, 0), 1)),
1193 /* If B + C is still a valid base register, then add them. */
1194 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1195 && INTVAL (XEXP (idx, 1)) <= 4096
1196 && INTVAL (XEXP (idx, 1)) >= -4096)
1198 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1201 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1203 reg2 = XEXP (XEXP (idx, 0), 0);
1204 if (GET_CODE (reg2) != CONST_INT)
1205 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1207 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1208 gen_rtx_MULT (Pmode,
1214 /* Get the index into a register, then add the base + index and
1215 return a register holding the result. */
1217 /* First get A into a register. */
1218 reg1 = XEXP (XEXP (idx, 0), 0);
1219 if (GET_CODE (reg1) != REG)
1220 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1222 /* And get B into a register. */
1223 reg2 = XEXP (idx, 1);
1224 if (GET_CODE (reg2) != REG)
1225 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1227 reg1 = force_reg (Pmode,
1228 gen_rtx_PLUS (Pmode,
1229 gen_rtx_MULT (Pmode, reg1,
1230 XEXP (XEXP (idx, 0), 1)),
1233 /* Add the result to our base register and return. */
1234 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1238 /* Uh-oh. We might have an address for x[n-100000]. This needs
1239 special handling to avoid creating an indexed memory address
1240 with x-100000 as the base.
1242 If the constant part is small enough, then it's still safe because
1243 there is a guard page at the beginning and end of the data segment.
1245 Scaled references are common enough that we want to try and rearrange the
1246 terms so that we can use indexing for these addresses too. Only
1247 do the optimization for floatint point modes. */
1249 if (GET_CODE (x) == PLUS
1250 && symbolic_expression_p (XEXP (x, 1)))
1252 /* Ugly. We modify things here so that the address offset specified
1253 by the index expression is computed first, then added to x to form
1254 the entire address. */
1256 rtx regx1, regx2, regy1, regy2, y;
1258 /* Strip off any CONST. */
1260 if (GET_CODE (y) == CONST)
1263 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1265 /* See if this looks like
1266 (plus (mult (reg) (shadd_const))
1267 (const (plus (symbol_ref) (const_int))))
1269 Where const_int is small. In that case the const
1270 expression is a valid pointer for indexing.
1272 If const_int is big, but can be divided evenly by shadd_const
1273 and added to (reg). This allows more scaled indexed addresses. */
1274 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1275 && GET_CODE (XEXP (x, 0)) == MULT
1276 && GET_CODE (XEXP (y, 1)) == CONST_INT
1277 && INTVAL (XEXP (y, 1)) >= -4096
1278 && INTVAL (XEXP (y, 1)) <= 4095
1279 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1280 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1282 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1286 if (GET_CODE (reg1) != REG)
1287 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1289 reg2 = XEXP (XEXP (x, 0), 0);
1290 if (GET_CODE (reg2) != REG)
1291 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1293 return force_reg (Pmode,
1294 gen_rtx_PLUS (Pmode,
1295 gen_rtx_MULT (Pmode,
1300 else if ((mode == DFmode || mode == SFmode)
1301 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1302 && GET_CODE (XEXP (x, 0)) == MULT
1303 && GET_CODE (XEXP (y, 1)) == CONST_INT
1304 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1305 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1306 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1309 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1310 / INTVAL (XEXP (XEXP (x, 0), 1))));
1311 regx2 = XEXP (XEXP (x, 0), 0);
1312 if (GET_CODE (regx2) != REG)
1313 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1314 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1318 gen_rtx_PLUS (Pmode,
1319 gen_rtx_MULT (Pmode, regx2,
1320 XEXP (XEXP (x, 0), 1)),
1321 force_reg (Pmode, XEXP (y, 0))));
1323 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1324 && INTVAL (XEXP (y, 1)) >= -4096
1325 && INTVAL (XEXP (y, 1)) <= 4095)
1327 /* This is safe because of the guard page at the
1328 beginning and end of the data space. Just
1329 return the original address. */
1334 /* Doesn't look like one we can optimize. */
1335 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1336 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1337 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1338 regx1 = force_reg (Pmode,
1339 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1341 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1349 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1351 Compute extra cost of moving data between one register class
1354 Make moves from SAR so expensive they should never happen. We used to
1355 have 0xffff here, but that generates overflow in rare cases.
1357 Copies involving a FP register and a non-FP register are relatively
1358 expensive because they must go through memory.
1360 Other copies are reasonably cheap. */
1363 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1364 reg_class_t from, reg_class_t to)
1366 if (from == SHIFT_REGS)
1368 else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
1369 || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
1375 /* For the HPPA, REG and REG+CONST is cost 0
1376 and addresses involving symbolic constants are cost 2.
1378 PIC addresses are very expensive.
1380 It is no coincidence that this has the same structure
1381 as GO_IF_LEGITIMATE_ADDRESS. */
1384 hppa_address_cost (rtx X,
1385 bool speed ATTRIBUTE_UNUSED)
1387 switch (GET_CODE (X))
1400 /* Compute a (partial) cost for rtx X. Return true if the complete
1401 cost has been computed, and false if subexpressions should be
1402 scanned. In either case, *TOTAL contains the cost result. */
1405 hppa_rtx_costs (rtx x, int code, int outer_code, int *total,
1406 bool speed ATTRIBUTE_UNUSED)
1411 if (INTVAL (x) == 0)
1413 else if (INT_14_BITS (x))
1430 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1431 && outer_code != SET)
1438 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1439 *total = COSTS_N_INSNS (3);
1440 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1441 *total = COSTS_N_INSNS (8);
1443 *total = COSTS_N_INSNS (20);
1447 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1449 *total = COSTS_N_INSNS (14);
1457 *total = COSTS_N_INSNS (60);
1460 case PLUS: /* this includes shNadd insns */
1462 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1463 *total = COSTS_N_INSNS (3);
1465 *total = COSTS_N_INSNS (1);
1471 *total = COSTS_N_INSNS (1);
1479 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1480 new rtx with the correct mode. */
1482 force_mode (enum machine_mode mode, rtx orig)
1484 if (mode == GET_MODE (orig))
1487 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1489 return gen_rtx_REG (mode, REGNO (orig));
1492 /* Return 1 if *X is a thread-local symbol. */
1495 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1497 return PA_SYMBOL_REF_TLS_P (*x);
1500 /* Return 1 if X contains a thread-local symbol. */
1503 pa_tls_referenced_p (rtx x)
1505 if (!TARGET_HAVE_TLS)
1508 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1511 /* Emit insns to move operands[1] into operands[0].
1513 Return 1 if we have written out everything that needs to be done to
1514 do the move. Otherwise, return 0 and the caller will emit the move
1517 Note SCRATCH_REG may not be in the proper mode depending on how it
1518 will be used. This routine is responsible for creating a new copy
1519 of SCRATCH_REG in the proper mode. */
1522 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1524 register rtx operand0 = operands[0];
1525 register rtx operand1 = operands[1];
1528 /* We can only handle indexed addresses in the destination operand
1529 of floating point stores. Thus, we need to break out indexed
1530 addresses from the destination operand. */
1531 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1533 gcc_assert (can_create_pseudo_p ());
1535 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1536 operand0 = replace_equiv_address (operand0, tem);
1539 /* On targets with non-equivalent space registers, break out unscaled
1540 indexed addresses from the source operand before the final CSE.
1541 We have to do this because the REG_POINTER flag is not correctly
1542 carried through various optimization passes and CSE may substitute
1543 a pseudo without the pointer set for one with the pointer set. As
1544 a result, we loose various opportunities to create insns with
1545 unscaled indexed addresses. */
1546 if (!TARGET_NO_SPACE_REGS
1547 && !cse_not_expected
1548 && GET_CODE (operand1) == MEM
1549 && GET_CODE (XEXP (operand1, 0)) == PLUS
1550 && REG_P (XEXP (XEXP (operand1, 0), 0))
1551 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1553 = replace_equiv_address (operand1,
1554 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1557 && reload_in_progress && GET_CODE (operand0) == REG
1558 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1559 operand0 = reg_equiv_mem[REGNO (operand0)];
1560 else if (scratch_reg
1561 && reload_in_progress && GET_CODE (operand0) == SUBREG
1562 && GET_CODE (SUBREG_REG (operand0)) == REG
1563 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1565 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1566 the code which tracks sets/uses for delete_output_reload. */
1567 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1568 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1569 SUBREG_BYTE (operand0));
1570 operand0 = alter_subreg (&temp);
1574 && reload_in_progress && GET_CODE (operand1) == REG
1575 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1576 operand1 = reg_equiv_mem[REGNO (operand1)];
1577 else if (scratch_reg
1578 && reload_in_progress && GET_CODE (operand1) == SUBREG
1579 && GET_CODE (SUBREG_REG (operand1)) == REG
1580 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1582 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1583 the code which tracks sets/uses for delete_output_reload. */
1584 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1585 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1586 SUBREG_BYTE (operand1));
1587 operand1 = alter_subreg (&temp);
1590 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1591 && ((tem = find_replacement (&XEXP (operand0, 0)))
1592 != XEXP (operand0, 0)))
1593 operand0 = replace_equiv_address (operand0, tem);
1595 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1596 && ((tem = find_replacement (&XEXP (operand1, 0)))
1597 != XEXP (operand1, 0)))
1598 operand1 = replace_equiv_address (operand1, tem);
1600 /* Handle secondary reloads for loads/stores of FP registers from
1601 REG+D addresses where D does not fit in 5 or 14 bits, including
1602 (subreg (mem (addr))) cases. */
1604 && fp_reg_operand (operand0, mode)
1605 && ((GET_CODE (operand1) == MEM
1606 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1607 XEXP (operand1, 0)))
1608 || ((GET_CODE (operand1) == SUBREG
1609 && GET_CODE (XEXP (operand1, 0)) == MEM
1610 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1612 XEXP (XEXP (operand1, 0), 0))))))
1614 if (GET_CODE (operand1) == SUBREG)
1615 operand1 = XEXP (operand1, 0);
1617 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1618 it in WORD_MODE regardless of what mode it was originally given
1620 scratch_reg = force_mode (word_mode, scratch_reg);
1622 /* D might not fit in 14 bits either; for such cases load D into
1624 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1626 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1627 emit_move_insn (scratch_reg,
1628 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1630 XEXP (XEXP (operand1, 0), 0),
1634 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1635 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1636 replace_equiv_address (operand1, scratch_reg)));
1639 else if (scratch_reg
1640 && fp_reg_operand (operand1, mode)
1641 && ((GET_CODE (operand0) == MEM
1642 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1644 XEXP (operand0, 0)))
1645 || ((GET_CODE (operand0) == SUBREG)
1646 && GET_CODE (XEXP (operand0, 0)) == MEM
1647 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1649 XEXP (XEXP (operand0, 0), 0)))))
1651 if (GET_CODE (operand0) == SUBREG)
1652 operand0 = XEXP (operand0, 0);
1654 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1655 it in WORD_MODE regardless of what mode it was originally given
1657 scratch_reg = force_mode (word_mode, scratch_reg);
1659 /* D might not fit in 14 bits either; for such cases load D into
1661 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1663 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1664 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1667 XEXP (XEXP (operand0, 0),
1672 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1673 emit_insn (gen_rtx_SET (VOIDmode,
1674 replace_equiv_address (operand0, scratch_reg),
1678 /* Handle secondary reloads for loads of FP registers from constant
1679 expressions by forcing the constant into memory.
1681 Use scratch_reg to hold the address of the memory location.
1683 The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return
1684 NO_REGS when presented with a const_int and a register class
1685 containing only FP registers. Doing so unfortunately creates
1686 more problems than it solves. Fix this for 2.5. */
1687 else if (scratch_reg
1688 && CONSTANT_P (operand1)
1689 && fp_reg_operand (operand0, mode))
1691 rtx const_mem, xoperands[2];
1693 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1694 it in WORD_MODE regardless of what mode it was originally given
1696 scratch_reg = force_mode (word_mode, scratch_reg);
1698 /* Force the constant into memory and put the address of the
1699 memory location into scratch_reg. */
1700 const_mem = force_const_mem (mode, operand1);
1701 xoperands[0] = scratch_reg;
1702 xoperands[1] = XEXP (const_mem, 0);
1703 emit_move_sequence (xoperands, Pmode, 0);
1705 /* Now load the destination register. */
1706 emit_insn (gen_rtx_SET (mode, operand0,
1707 replace_equiv_address (const_mem, scratch_reg)));
1710 /* Handle secondary reloads for SAR. These occur when trying to load
1711 the SAR from memory, FP register, or with a constant. */
1712 else if (scratch_reg
1713 && GET_CODE (operand0) == REG
1714 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1715 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1716 && (GET_CODE (operand1) == MEM
1717 || GET_CODE (operand1) == CONST_INT
1718 || (GET_CODE (operand1) == REG
1719 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1721 /* D might not fit in 14 bits either; for such cases load D into
1723 if (GET_CODE (operand1) == MEM
1724 && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
1726 /* We are reloading the address into the scratch register, so we
1727 want to make sure the scratch register is a full register. */
1728 scratch_reg = force_mode (word_mode, scratch_reg);
1730 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1731 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1734 XEXP (XEXP (operand1, 0),
1738 /* Now we are going to load the scratch register from memory,
1739 we want to load it in the same width as the original MEM,
1740 which must be the same as the width of the ultimate destination,
1742 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1744 emit_move_insn (scratch_reg,
1745 replace_equiv_address (operand1, scratch_reg));
1749 /* We want to load the scratch register using the same mode as
1750 the ultimate destination. */
1751 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1753 emit_move_insn (scratch_reg, operand1);
1756 /* And emit the insn to set the ultimate destination. We know that
1757 the scratch register has the same mode as the destination at this
1759 emit_move_insn (operand0, scratch_reg);
1762 /* Handle the most common case: storing into a register. */
1763 else if (register_operand (operand0, mode))
1765 if (register_operand (operand1, mode)
1766 || (GET_CODE (operand1) == CONST_INT
1767 && cint_ok_for_move (INTVAL (operand1)))
1768 || (operand1 == CONST0_RTX (mode))
1769 || (GET_CODE (operand1) == HIGH
1770 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1771 /* Only `general_operands' can come here, so MEM is ok. */
1772 || GET_CODE (operand1) == MEM)
1774 /* Various sets are created during RTL generation which don't
1775 have the REG_POINTER flag correctly set. After the CSE pass,
1776 instruction recognition can fail if we don't consistently
1777 set this flag when performing register copies. This should
1778 also improve the opportunities for creating insns that use
1779 unscaled indexing. */
1780 if (REG_P (operand0) && REG_P (operand1))
1782 if (REG_POINTER (operand1)
1783 && !REG_POINTER (operand0)
1784 && !HARD_REGISTER_P (operand0))
1785 copy_reg_pointer (operand0, operand1);
1788 /* When MEMs are broken out, the REG_POINTER flag doesn't
1789 get set. In some cases, we can set the REG_POINTER flag
1790 from the declaration for the MEM. */
1791 if (REG_P (operand0)
1792 && GET_CODE (operand1) == MEM
1793 && !REG_POINTER (operand0))
1795 tree decl = MEM_EXPR (operand1);
1797 /* Set the register pointer flag and register alignment
1798 if the declaration for this memory reference is a
1804 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1806 if (TREE_CODE (decl) == COMPONENT_REF)
1807 decl = TREE_OPERAND (decl, 1);
1809 type = TREE_TYPE (decl);
1810 type = strip_array_types (type);
1812 if (POINTER_TYPE_P (type))
1816 type = TREE_TYPE (type);
1817 /* Using TYPE_ALIGN_OK is rather conservative as
1818 only the ada frontend actually sets it. */
1819 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1821 mark_reg_pointer (operand0, align);
1826 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1830 else if (GET_CODE (operand0) == MEM)
1832 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1833 && !(reload_in_progress || reload_completed))
1835 rtx temp = gen_reg_rtx (DFmode);
1837 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1838 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1841 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1843 /* Run this case quickly. */
1844 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1847 if (! (reload_in_progress || reload_completed))
1849 operands[0] = validize_mem (operand0);
1850 operands[1] = operand1 = force_reg (mode, operand1);
1854 /* Simplify the source if we need to.
1855 Note we do have to handle function labels here, even though we do
1856 not consider them legitimate constants. Loop optimizations can
1857 call the emit_move_xxx with one as a source. */
1858 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1859 || function_label_operand (operand1, mode)
1860 || (GET_CODE (operand1) == HIGH
1861 && symbolic_operand (XEXP (operand1, 0), mode)))
1865 if (GET_CODE (operand1) == HIGH)
1868 operand1 = XEXP (operand1, 0);
1870 if (symbolic_operand (operand1, mode))
1872 /* Argh. The assembler and linker can't handle arithmetic
1875 So we force the plabel into memory, load operand0 from
1876 the memory location, then add in the constant part. */
1877 if ((GET_CODE (operand1) == CONST
1878 && GET_CODE (XEXP (operand1, 0)) == PLUS
1879 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1880 || function_label_operand (operand1, mode))
1882 rtx temp, const_part;
1884 /* Figure out what (if any) scratch register to use. */
1885 if (reload_in_progress || reload_completed)
1887 scratch_reg = scratch_reg ? scratch_reg : operand0;
1888 /* SCRATCH_REG will hold an address and maybe the actual
1889 data. We want it in WORD_MODE regardless of what mode it
1890 was originally given to us. */
1891 scratch_reg = force_mode (word_mode, scratch_reg);
1894 scratch_reg = gen_reg_rtx (Pmode);
1896 if (GET_CODE (operand1) == CONST)
1898 /* Save away the constant part of the expression. */
1899 const_part = XEXP (XEXP (operand1, 0), 1);
1900 gcc_assert (GET_CODE (const_part) == CONST_INT);
1902 /* Force the function label into memory. */
1903 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1907 /* No constant part. */
1908 const_part = NULL_RTX;
1910 /* Force the function label into memory. */
1911 temp = force_const_mem (mode, operand1);
1915 /* Get the address of the memory location. PIC-ify it if
1917 temp = XEXP (temp, 0);
1919 temp = legitimize_pic_address (temp, mode, scratch_reg);
1921 /* Put the address of the memory location into our destination
1924 emit_move_sequence (operands, mode, scratch_reg);
1926 /* Now load from the memory location into our destination
1928 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1929 emit_move_sequence (operands, mode, scratch_reg);
1931 /* And add back in the constant part. */
1932 if (const_part != NULL_RTX)
1933 expand_inc (operand0, const_part);
1942 if (reload_in_progress || reload_completed)
1944 temp = scratch_reg ? scratch_reg : operand0;
1945 /* TEMP will hold an address and maybe the actual
1946 data. We want it in WORD_MODE regardless of what mode it
1947 was originally given to us. */
1948 temp = force_mode (word_mode, temp);
1951 temp = gen_reg_rtx (Pmode);
1953 /* (const (plus (symbol) (const_int))) must be forced to
1954 memory during/after reload if the const_int will not fit
1956 if (GET_CODE (operand1) == CONST
1957 && GET_CODE (XEXP (operand1, 0)) == PLUS
1958 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1959 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1960 && (reload_completed || reload_in_progress)
1963 rtx const_mem = force_const_mem (mode, operand1);
1964 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1966 operands[1] = replace_equiv_address (const_mem, operands[1]);
1967 emit_move_sequence (operands, mode, temp);
1971 operands[1] = legitimize_pic_address (operand1, mode, temp);
1972 if (REG_P (operand0) && REG_P (operands[1]))
1973 copy_reg_pointer (operand0, operands[1]);
1974 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1977 /* On the HPPA, references to data space are supposed to use dp,
1978 register 27, but showing it in the RTL inhibits various cse
1979 and loop optimizations. */
1984 if (reload_in_progress || reload_completed)
1986 temp = scratch_reg ? scratch_reg : operand0;
1987 /* TEMP will hold an address and maybe the actual
1988 data. We want it in WORD_MODE regardless of what mode it
1989 was originally given to us. */
1990 temp = force_mode (word_mode, temp);
1993 temp = gen_reg_rtx (mode);
1995 /* Loading a SYMBOL_REF into a register makes that register
1996 safe to be used as the base in an indexed address.
1998 Don't mark hard registers though. That loses. */
1999 if (GET_CODE (operand0) == REG
2000 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2001 mark_reg_pointer (operand0, BITS_PER_UNIT);
2002 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2003 mark_reg_pointer (temp, BITS_PER_UNIT);
2006 set = gen_rtx_SET (mode, operand0, temp);
2008 set = gen_rtx_SET (VOIDmode,
2010 gen_rtx_LO_SUM (mode, temp, operand1));
2012 emit_insn (gen_rtx_SET (VOIDmode,
2014 gen_rtx_HIGH (mode, operand1)));
2020 else if (pa_tls_referenced_p (operand1))
2025 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
2027 addend = XEXP (XEXP (tmp, 0), 1);
2028 tmp = XEXP (XEXP (tmp, 0), 0);
2031 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
2032 tmp = legitimize_tls_address (tmp);
2035 tmp = gen_rtx_PLUS (mode, tmp, addend);
2036 tmp = force_operand (tmp, operands[0]);
2040 else if (GET_CODE (operand1) != CONST_INT
2041 || !cint_ok_for_move (INTVAL (operand1)))
2045 HOST_WIDE_INT value = 0;
2046 HOST_WIDE_INT insv = 0;
2049 if (GET_CODE (operand1) == CONST_INT)
2050 value = INTVAL (operand1);
2053 && GET_CODE (operand1) == CONST_INT
2054 && HOST_BITS_PER_WIDE_INT > 32
2055 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2059 /* Extract the low order 32 bits of the value and sign extend.
2060 If the new value is the same as the original value, we can
2061 can use the original value as-is. If the new value is
2062 different, we use it and insert the most-significant 32-bits
2063 of the original value into the final result. */
2064 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2065 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2068 #if HOST_BITS_PER_WIDE_INT > 32
2069 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2073 operand1 = GEN_INT (nval);
2077 if (reload_in_progress || reload_completed)
2078 temp = scratch_reg ? scratch_reg : operand0;
2080 temp = gen_reg_rtx (mode);
2082 /* We don't directly split DImode constants on 32-bit targets
2083 because PLUS uses an 11-bit immediate and the insn sequence
2084 generated is not as efficient as the one using HIGH/LO_SUM. */
2085 if (GET_CODE (operand1) == CONST_INT
2086 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
2087 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2090 /* Directly break constant into high and low parts. This
2091 provides better optimization opportunities because various
2092 passes recognize constants split with PLUS but not LO_SUM.
2093 We use a 14-bit signed low part except when the addition
2094 of 0x4000 to the high part might change the sign of the
2096 HOST_WIDE_INT low = value & 0x3fff;
2097 HOST_WIDE_INT high = value & ~ 0x3fff;
2101 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2109 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2110 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2114 emit_insn (gen_rtx_SET (VOIDmode, temp,
2115 gen_rtx_HIGH (mode, operand1)));
2116 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2119 insn = emit_move_insn (operands[0], operands[1]);
2121 /* Now insert the most significant 32 bits of the value
2122 into the register. When we don't have a second register
2123 available, it could take up to nine instructions to load
2124 a 64-bit integer constant. Prior to reload, we force
2125 constants that would take more than three instructions
2126 to load to the constant pool. During and after reload,
2127 we have to handle all possible values. */
2130 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2131 register and the value to be inserted is outside the
2132 range that can be loaded with three depdi instructions. */
2133 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2135 operand1 = GEN_INT (insv);
2137 emit_insn (gen_rtx_SET (VOIDmode, temp,
2138 gen_rtx_HIGH (mode, operand1)));
2139 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2140 emit_insn (gen_insv (operand0, GEN_INT (32),
2145 int len = 5, pos = 27;
2147 /* Insert the bits using the depdi instruction. */
2150 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2151 HOST_WIDE_INT sign = v5 < 0;
2153 /* Left extend the insertion. */
2154 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2155 while (pos > 0 && (insv & 1) == sign)
2157 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2162 emit_insn (gen_insv (operand0, GEN_INT (len),
2163 GEN_INT (pos), GEN_INT (v5)));
2165 len = pos > 0 && pos < 5 ? pos : 5;
2171 set_unique_reg_note (insn, REG_EQUAL, op1);
2176 /* Now have insn-emit do whatever it normally does. */
2180 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2181 it will need a link/runtime reloc). */
2184 reloc_needed (tree exp)
2188 switch (TREE_CODE (exp))
2193 case POINTER_PLUS_EXPR:
2196 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2197 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2201 case NON_LVALUE_EXPR:
2202 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2208 unsigned HOST_WIDE_INT ix;
2210 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2212 reloc |= reloc_needed (value);
2225 /* Does operand (which is a symbolic_operand) live in text space?
2226 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2230 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2232 if (GET_CODE (operand) == CONST)
2233 operand = XEXP (XEXP (operand, 0), 0);
2236 if (GET_CODE (operand) == SYMBOL_REF)
2237 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2241 if (GET_CODE (operand) == SYMBOL_REF)
2242 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2248 /* Return the best assembler insn template
2249 for moving operands[1] into operands[0] as a fullword. */
2251 singlemove_string (rtx *operands)
2253 HOST_WIDE_INT intval;
2255 if (GET_CODE (operands[0]) == MEM)
2256 return "stw %r1,%0";
2257 if (GET_CODE (operands[1]) == MEM)
2259 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2264 gcc_assert (GET_MODE (operands[1]) == SFmode);
2266 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2268 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2269 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2271 operands[1] = GEN_INT (i);
2272 /* Fall through to CONST_INT case. */
2274 if (GET_CODE (operands[1]) == CONST_INT)
2276 intval = INTVAL (operands[1]);
2278 if (VAL_14_BITS_P (intval))
2280 else if ((intval & 0x7ff) == 0)
2281 return "ldil L'%1,%0";
2282 else if (zdepi_cint_p (intval))
2283 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2285 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2287 return "copy %1,%0";
2291 /* Compute position (in OP[1]) and width (in OP[2])
2292 useful for copying IMM to a register using the zdepi
2293 instructions. Store the immediate value to insert in OP[0]. */
2295 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2299 /* Find the least significant set bit in IMM. */
2300 for (lsb = 0; lsb < 32; lsb++)
2307 /* Choose variants based on *sign* of the 5-bit field. */
2308 if ((imm & 0x10) == 0)
2309 len = (lsb <= 28) ? 4 : 32 - lsb;
2312 /* Find the width of the bitstring in IMM. */
2313 for (len = 5; len < 32 - lsb; len++)
2315 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2319 /* Sign extend IMM as a 5-bit value. */
2320 imm = (imm & 0xf) - 0x10;
2328 /* Compute position (in OP[1]) and width (in OP[2])
2329 useful for copying IMM to a register using the depdi,z
2330 instructions. Store the immediate value to insert in OP[0]. */
2332 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2334 int lsb, len, maxlen;
2336 maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64);
2338 /* Find the least significant set bit in IMM. */
2339 for (lsb = 0; lsb < maxlen; lsb++)
2346 /* Choose variants based on *sign* of the 5-bit field. */
2347 if ((imm & 0x10) == 0)
2348 len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb;
2351 /* Find the width of the bitstring in IMM. */
2352 for (len = 5; len < maxlen - lsb; len++)
2354 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2358 /* Extend length if host is narrow and IMM is negative. */
2359 if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb)
2362 /* Sign extend IMM as a 5-bit value. */
2363 imm = (imm & 0xf) - 0x10;
2371 /* Output assembler code to perform a doubleword move insn
2372 with operands OPERANDS. */
2375 output_move_double (rtx *operands)
2377 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2379 rtx addreg0 = 0, addreg1 = 0;
2381 /* First classify both operands. */
2383 if (REG_P (operands[0]))
2385 else if (offsettable_memref_p (operands[0]))
2387 else if (GET_CODE (operands[0]) == MEM)
2392 if (REG_P (operands[1]))
2394 else if (CONSTANT_P (operands[1]))
2396 else if (offsettable_memref_p (operands[1]))
2398 else if (GET_CODE (operands[1]) == MEM)
2403 /* Check for the cases that the operand constraints are not
2404 supposed to allow to happen. */
2405 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2407 /* Handle copies between general and floating registers. */
2409 if (optype0 == REGOP && optype1 == REGOP
2410 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2412 if (FP_REG_P (operands[0]))
2414 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2415 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2416 return "{fldds|fldd} -16(%%sp),%0";
2420 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2421 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2422 return "{ldws|ldw} -12(%%sp),%R0";
2426 /* Handle auto decrementing and incrementing loads and stores
2427 specifically, since the structure of the function doesn't work
2428 for them without major modification. Do it better when we learn
2429 this port about the general inc/dec addressing of PA.
2430 (This was written by tege. Chide him if it doesn't work.) */
2432 if (optype0 == MEMOP)
2434 /* We have to output the address syntax ourselves, since print_operand
2435 doesn't deal with the addresses we want to use. Fix this later. */
2437 rtx addr = XEXP (operands[0], 0);
2438 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2440 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2442 operands[0] = XEXP (addr, 0);
2443 gcc_assert (GET_CODE (operands[1]) == REG
2444 && GET_CODE (operands[0]) == REG);
2446 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2448 /* No overlap between high target register and address
2449 register. (We do this in a non-obvious way to
2450 save a register file writeback) */
2451 if (GET_CODE (addr) == POST_INC)
2452 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2453 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2455 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2457 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2459 operands[0] = XEXP (addr, 0);
2460 gcc_assert (GET_CODE (operands[1]) == REG
2461 && GET_CODE (operands[0]) == REG);
2463 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2464 /* No overlap between high target register and address
2465 register. (We do this in a non-obvious way to save a
2466 register file writeback) */
2467 if (GET_CODE (addr) == PRE_INC)
2468 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2469 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2472 if (optype1 == MEMOP)
2474 /* We have to output the address syntax ourselves, since print_operand
2475 doesn't deal with the addresses we want to use. Fix this later. */
2477 rtx addr = XEXP (operands[1], 0);
2478 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2480 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2482 operands[1] = XEXP (addr, 0);
2483 gcc_assert (GET_CODE (operands[0]) == REG
2484 && GET_CODE (operands[1]) == REG);
2486 if (!reg_overlap_mentioned_p (high_reg, addr))
2488 /* No overlap between high target register and address
2489 register. (We do this in a non-obvious way to
2490 save a register file writeback) */
2491 if (GET_CODE (addr) == POST_INC)
2492 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2493 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2497 /* This is an undefined situation. We should load into the
2498 address register *and* update that register. Probably
2499 we don't need to handle this at all. */
2500 if (GET_CODE (addr) == POST_INC)
2501 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2502 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2505 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2507 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2509 operands[1] = XEXP (addr, 0);
2510 gcc_assert (GET_CODE (operands[0]) == REG
2511 && GET_CODE (operands[1]) == REG);
2513 if (!reg_overlap_mentioned_p (high_reg, addr))
2515 /* No overlap between high target register and address
2516 register. (We do this in a non-obvious way to
2517 save a register file writeback) */
2518 if (GET_CODE (addr) == PRE_INC)
2519 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2520 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2524 /* This is an undefined situation. We should load into the
2525 address register *and* update that register. Probably
2526 we don't need to handle this at all. */
2527 if (GET_CODE (addr) == PRE_INC)
2528 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2529 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2532 else if (GET_CODE (addr) == PLUS
2533 && GET_CODE (XEXP (addr, 0)) == MULT)
2536 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2538 if (!reg_overlap_mentioned_p (high_reg, addr))
2540 xoperands[0] = high_reg;
2541 xoperands[1] = XEXP (addr, 1);
2542 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2543 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2544 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2546 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2550 xoperands[0] = high_reg;
2551 xoperands[1] = XEXP (addr, 1);
2552 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2553 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2554 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2556 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2561 /* If an operand is an unoffsettable memory ref, find a register
2562 we can increment temporarily to make it refer to the second word. */
2564 if (optype0 == MEMOP)
2565 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2567 if (optype1 == MEMOP)
2568 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2570 /* Ok, we can do one word at a time.
2571 Normally we do the low-numbered word first.
2573 In either case, set up in LATEHALF the operands to use
2574 for the high-numbered word and in some cases alter the
2575 operands in OPERANDS to be suitable for the low-numbered word. */
2577 if (optype0 == REGOP)
2578 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2579 else if (optype0 == OFFSOP)
2580 latehalf[0] = adjust_address (operands[0], SImode, 4);
2582 latehalf[0] = operands[0];
2584 if (optype1 == REGOP)
2585 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2586 else if (optype1 == OFFSOP)
2587 latehalf[1] = adjust_address (operands[1], SImode, 4);
2588 else if (optype1 == CNSTOP)
2589 split_double (operands[1], &operands[1], &latehalf[1]);
2591 latehalf[1] = operands[1];
2593 /* If the first move would clobber the source of the second one,
2594 do them in the other order.
2596 This can happen in two cases:
2598 mem -> register where the first half of the destination register
2599 is the same register used in the memory's address. Reload
2600 can create such insns.
2602 mem in this case will be either register indirect or register
2603 indirect plus a valid offset.
2605 register -> register move where REGNO(dst) == REGNO(src + 1)
2606 someone (Tim/Tege?) claimed this can happen for parameter loads.
2608 Handle mem -> register case first. */
2609 if (optype0 == REGOP
2610 && (optype1 == MEMOP || optype1 == OFFSOP)
2611 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2614 /* Do the late half first. */
2616 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2617 output_asm_insn (singlemove_string (latehalf), latehalf);
2621 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2622 return singlemove_string (operands);
2625 /* Now handle register -> register case. */
2626 if (optype0 == REGOP && optype1 == REGOP
2627 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2629 output_asm_insn (singlemove_string (latehalf), latehalf);
2630 return singlemove_string (operands);
2633 /* Normal case: do the two words, low-numbered first. */
2635 output_asm_insn (singlemove_string (operands), operands);
2637 /* Make any unoffsettable addresses point at high-numbered word. */
2639 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2641 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2644 output_asm_insn (singlemove_string (latehalf), latehalf);
2646 /* Undo the adds we just did. */
2648 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2650 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2656 output_fp_move_double (rtx *operands)
2658 if (FP_REG_P (operands[0]))
2660 if (FP_REG_P (operands[1])
2661 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2662 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2664 output_asm_insn ("fldd%F1 %1,%0", operands);
2666 else if (FP_REG_P (operands[1]))
2668 output_asm_insn ("fstd%F0 %1,%0", operands);
2674 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2676 /* This is a pain. You have to be prepared to deal with an
2677 arbitrary address here including pre/post increment/decrement.
2679 so avoid this in the MD. */
2680 gcc_assert (GET_CODE (operands[0]) == REG);
2682 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2683 xoperands[0] = operands[0];
2684 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2689 /* Return a REG that occurs in ADDR with coefficient 1.
2690 ADDR can be effectively incremented by incrementing REG. */
2693 find_addr_reg (rtx addr)
2695 while (GET_CODE (addr) == PLUS)
2697 if (GET_CODE (XEXP (addr, 0)) == REG)
2698 addr = XEXP (addr, 0);
2699 else if (GET_CODE (XEXP (addr, 1)) == REG)
2700 addr = XEXP (addr, 1);
2701 else if (CONSTANT_P (XEXP (addr, 0)))
2702 addr = XEXP (addr, 1);
2703 else if (CONSTANT_P (XEXP (addr, 1)))
2704 addr = XEXP (addr, 0);
2708 gcc_assert (GET_CODE (addr) == REG);
2712 /* Emit code to perform a block move.
2714 OPERANDS[0] is the destination pointer as a REG, clobbered.
2715 OPERANDS[1] is the source pointer as a REG, clobbered.
2716 OPERANDS[2] is a register for temporary storage.
2717 OPERANDS[3] is a register for temporary storage.
2718 OPERANDS[4] is the size as a CONST_INT
2719 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2720 OPERANDS[6] is another temporary register. */
2723 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2725 int align = INTVAL (operands[5]);
2726 unsigned long n_bytes = INTVAL (operands[4]);
2728 /* We can't move more than a word at a time because the PA
2729 has no longer integer move insns. (Could use fp mem ops?) */
2730 if (align > (TARGET_64BIT ? 8 : 4))
2731 align = (TARGET_64BIT ? 8 : 4);
2733 /* Note that we know each loop below will execute at least twice
2734 (else we would have open-coded the copy). */
2738 /* Pre-adjust the loop counter. */
2739 operands[4] = GEN_INT (n_bytes - 16);
2740 output_asm_insn ("ldi %4,%2", operands);
2743 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2744 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2745 output_asm_insn ("std,ma %3,8(%0)", operands);
2746 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2747 output_asm_insn ("std,ma %6,8(%0)", operands);
2749 /* Handle the residual. There could be up to 7 bytes of
2750 residual to copy! */
2751 if (n_bytes % 16 != 0)
2753 operands[4] = GEN_INT (n_bytes % 8);
2754 if (n_bytes % 16 >= 8)
2755 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2756 if (n_bytes % 8 != 0)
2757 output_asm_insn ("ldd 0(%1),%6", operands);
2758 if (n_bytes % 16 >= 8)
2759 output_asm_insn ("std,ma %3,8(%0)", operands);
2760 if (n_bytes % 8 != 0)
2761 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2766 /* Pre-adjust the loop counter. */
2767 operands[4] = GEN_INT (n_bytes - 8);
2768 output_asm_insn ("ldi %4,%2", operands);
2771 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2772 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2773 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2774 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2775 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2777 /* Handle the residual. There could be up to 7 bytes of
2778 residual to copy! */
2779 if (n_bytes % 8 != 0)
2781 operands[4] = GEN_INT (n_bytes % 4);
2782 if (n_bytes % 8 >= 4)
2783 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2784 if (n_bytes % 4 != 0)
2785 output_asm_insn ("ldw 0(%1),%6", operands);
2786 if (n_bytes % 8 >= 4)
2787 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2788 if (n_bytes % 4 != 0)
2789 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2794 /* Pre-adjust the loop counter. */
2795 operands[4] = GEN_INT (n_bytes - 4);
2796 output_asm_insn ("ldi %4,%2", operands);
2799 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2800 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2801 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2802 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2803 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2805 /* Handle the residual. */
2806 if (n_bytes % 4 != 0)
2808 if (n_bytes % 4 >= 2)
2809 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2810 if (n_bytes % 2 != 0)
2811 output_asm_insn ("ldb 0(%1),%6", operands);
2812 if (n_bytes % 4 >= 2)
2813 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2814 if (n_bytes % 2 != 0)
2815 output_asm_insn ("stb %6,0(%0)", operands);
2820 /* Pre-adjust the loop counter. */
2821 operands[4] = GEN_INT (n_bytes - 2);
2822 output_asm_insn ("ldi %4,%2", operands);
2825 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2826 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2827 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2828 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2829 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2831 /* Handle the residual. */
2832 if (n_bytes % 2 != 0)
2834 output_asm_insn ("ldb 0(%1),%3", operands);
2835 output_asm_insn ("stb %3,0(%0)", operands);
2844 /* Count the number of insns necessary to handle this block move.
2846 Basic structure is the same as emit_block_move, except that we
2847 count insns rather than emit them. */
2850 compute_movmem_length (rtx insn)
2852 rtx pat = PATTERN (insn);
2853 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2854 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2855 unsigned int n_insns = 0;
2857 /* We can't move more than four bytes at a time because the PA
2858 has no longer integer move insns. (Could use fp mem ops?) */
2859 if (align > (TARGET_64BIT ? 8 : 4))
2860 align = (TARGET_64BIT ? 8 : 4);
2862 /* The basic copying loop. */
2866 if (n_bytes % (2 * align) != 0)
2868 if ((n_bytes % (2 * align)) >= align)
2871 if ((n_bytes % align) != 0)
2875 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2879 /* Emit code to perform a block clear.
2881 OPERANDS[0] is the destination pointer as a REG, clobbered.
2882 OPERANDS[1] is a register for temporary storage.
2883 OPERANDS[2] is the size as a CONST_INT
2884 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2887 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2889 int align = INTVAL (operands[3]);
2890 unsigned long n_bytes = INTVAL (operands[2]);
2892 /* We can't clear more than a word at a time because the PA
2893 has no longer integer move insns. */
2894 if (align > (TARGET_64BIT ? 8 : 4))
2895 align = (TARGET_64BIT ? 8 : 4);
2897 /* Note that we know each loop below will execute at least twice
2898 (else we would have open-coded the copy). */
2902 /* Pre-adjust the loop counter. */
2903 operands[2] = GEN_INT (n_bytes - 16);
2904 output_asm_insn ("ldi %2,%1", operands);
2907 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2908 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2909 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2911 /* Handle the residual. There could be up to 7 bytes of
2912 residual to copy! */
2913 if (n_bytes % 16 != 0)
2915 operands[2] = GEN_INT (n_bytes % 8);
2916 if (n_bytes % 16 >= 8)
2917 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2918 if (n_bytes % 8 != 0)
2919 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2924 /* Pre-adjust the loop counter. */
2925 operands[2] = GEN_INT (n_bytes - 8);
2926 output_asm_insn ("ldi %2,%1", operands);
2929 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2930 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2931 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2933 /* Handle the residual. There could be up to 7 bytes of
2934 residual to copy! */
2935 if (n_bytes % 8 != 0)
2937 operands[2] = GEN_INT (n_bytes % 4);
2938 if (n_bytes % 8 >= 4)
2939 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2940 if (n_bytes % 4 != 0)
2941 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2946 /* Pre-adjust the loop counter. */
2947 operands[2] = GEN_INT (n_bytes - 4);
2948 output_asm_insn ("ldi %2,%1", operands);
2951 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2952 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2953 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2955 /* Handle the residual. */
2956 if (n_bytes % 4 != 0)
2958 if (n_bytes % 4 >= 2)
2959 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2960 if (n_bytes % 2 != 0)
2961 output_asm_insn ("stb %%r0,0(%0)", operands);
2966 /* Pre-adjust the loop counter. */
2967 operands[2] = GEN_INT (n_bytes - 2);
2968 output_asm_insn ("ldi %2,%1", operands);
2971 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2972 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2973 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2975 /* Handle the residual. */
2976 if (n_bytes % 2 != 0)
2977 output_asm_insn ("stb %%r0,0(%0)", operands);
2986 /* Count the number of insns necessary to handle this block move.
2988 Basic structure is the same as emit_block_move, except that we
2989 count insns rather than emit them. */
2992 compute_clrmem_length (rtx insn)
2994 rtx pat = PATTERN (insn);
2995 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2996 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2997 unsigned int n_insns = 0;
2999 /* We can't clear more than a word at a time because the PA
3000 has no longer integer move insns. */
3001 if (align > (TARGET_64BIT ? 8 : 4))
3002 align = (TARGET_64BIT ? 8 : 4);
3004 /* The basic loop. */
3008 if (n_bytes % (2 * align) != 0)
3010 if ((n_bytes % (2 * align)) >= align)
3013 if ((n_bytes % align) != 0)
3017 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3023 output_and (rtx *operands)
3025 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3027 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3028 int ls0, ls1, ms0, p, len;
3030 for (ls0 = 0; ls0 < 32; ls0++)
3031 if ((mask & (1 << ls0)) == 0)
3034 for (ls1 = ls0; ls1 < 32; ls1++)
3035 if ((mask & (1 << ls1)) != 0)
3038 for (ms0 = ls1; ms0 < 32; ms0++)
3039 if ((mask & (1 << ms0)) == 0)
3042 gcc_assert (ms0 == 32);
3050 operands[2] = GEN_INT (len);
3051 return "{extru|extrw,u} %1,31,%2,%0";
3055 /* We could use this `depi' for the case above as well, but `depi'
3056 requires one more register file access than an `extru'. */
3061 operands[2] = GEN_INT (p);
3062 operands[3] = GEN_INT (len);
3063 return "{depi|depwi} 0,%2,%3,%0";
3067 return "and %1,%2,%0";
3070 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3071 storing the result in operands[0]. */
3073 output_64bit_and (rtx *operands)
3075 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3077 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3078 int ls0, ls1, ms0, p, len;
3080 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3081 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3084 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3085 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3088 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3089 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3092 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
3094 if (ls1 == HOST_BITS_PER_WIDE_INT)
3100 operands[2] = GEN_INT (len);
3101 return "extrd,u %1,63,%2,%0";
3105 /* We could use this `depi' for the case above as well, but `depi'
3106 requires one more register file access than an `extru'. */
3111 operands[2] = GEN_INT (p);
3112 operands[3] = GEN_INT (len);
3113 return "depdi 0,%2,%3,%0";
3117 return "and %1,%2,%0";
3121 output_ior (rtx *operands)
3123 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3124 int bs0, bs1, p, len;
3126 if (INTVAL (operands[2]) == 0)
3127 return "copy %1,%0";
3129 for (bs0 = 0; bs0 < 32; bs0++)
3130 if ((mask & (1 << bs0)) != 0)
3133 for (bs1 = bs0; bs1 < 32; bs1++)
3134 if ((mask & (1 << bs1)) == 0)
3137 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3142 operands[2] = GEN_INT (p);
3143 operands[3] = GEN_INT (len);
3144 return "{depi|depwi} -1,%2,%3,%0";
3147 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3148 storing the result in operands[0]. */
3150 output_64bit_ior (rtx *operands)
3152 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3153 int bs0, bs1, p, len;
3155 if (INTVAL (operands[2]) == 0)
3156 return "copy %1,%0";
3158 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3159 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3162 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3163 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3166 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3167 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3172 operands[2] = GEN_INT (p);
3173 operands[3] = GEN_INT (len);
3174 return "depdi -1,%2,%3,%0";
3177 /* Target hook for assembling integer objects. This code handles
3178 aligned SI and DI integers specially since function references
3179 must be preceded by P%. */
3182 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3184 if (size == UNITS_PER_WORD
3186 && function_label_operand (x, VOIDmode))
3188 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3189 output_addr_const (asm_out_file, x);
3190 fputc ('\n', asm_out_file);
3193 return default_assemble_integer (x, size, aligned_p);
3196 /* Output an ascii string. */
3198 output_ascii (FILE *file, const char *p, int size)
3202 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3204 /* The HP assembler can only take strings of 256 characters at one
3205 time. This is a limitation on input line length, *not* the
3206 length of the string. Sigh. Even worse, it seems that the
3207 restriction is in number of input characters (see \xnn &
3208 \whatever). So we have to do this very carefully. */
3210 fputs ("\t.STRING \"", file);
3213 for (i = 0; i < size; i += 4)
3217 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3219 register unsigned int c = (unsigned char) p[i + io];
3221 if (c == '\"' || c == '\\')
3222 partial_output[co++] = '\\';
3223 if (c >= ' ' && c < 0177)
3224 partial_output[co++] = c;
3228 partial_output[co++] = '\\';
3229 partial_output[co++] = 'x';
3230 hexd = c / 16 - 0 + '0';
3232 hexd -= '9' - 'a' + 1;
3233 partial_output[co++] = hexd;
3234 hexd = c % 16 - 0 + '0';
3236 hexd -= '9' - 'a' + 1;
3237 partial_output[co++] = hexd;
3240 if (chars_output + co > 243)
3242 fputs ("\"\n\t.STRING \"", file);
3245 fwrite (partial_output, 1, (size_t) co, file);
3249 fputs ("\"\n", file);
3252 /* Try to rewrite floating point comparisons & branches to avoid
3253 useless add,tr insns.
3255 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3256 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3257 first attempt to remove useless add,tr insns. It is zero
3258 for the second pass as reorg sometimes leaves bogus REG_DEAD
3261 When CHECK_NOTES is zero we can only eliminate add,tr insns
3262 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3265 remove_useless_addtr_insns (int check_notes)
3268 static int pass = 0;
3270 /* This is fairly cheap, so always run it when optimizing. */
3274 int fbranch_count = 0;
3276 /* Walk all the insns in this function looking for fcmp & fbranch
3277 instructions. Keep track of how many of each we find. */
3278 for (insn = get_insns (); insn; insn = next_insn (insn))
3282 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3283 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3286 tmp = PATTERN (insn);
3288 /* It must be a set. */
3289 if (GET_CODE (tmp) != SET)
3292 /* If the destination is CCFP, then we've found an fcmp insn. */
3293 tmp = SET_DEST (tmp);
3294 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3300 tmp = PATTERN (insn);
3301 /* If this is an fbranch instruction, bump the fbranch counter. */
3302 if (GET_CODE (tmp) == SET
3303 && SET_DEST (tmp) == pc_rtx
3304 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3305 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3306 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3307 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3315 /* Find all floating point compare + branch insns. If possible,
3316 reverse the comparison & the branch to avoid add,tr insns. */
3317 for (insn = get_insns (); insn; insn = next_insn (insn))
3321 /* Ignore anything that isn't an INSN. */
3322 if (GET_CODE (insn) != INSN)
3325 tmp = PATTERN (insn);
3327 /* It must be a set. */
3328 if (GET_CODE (tmp) != SET)
3331 /* The destination must be CCFP, which is register zero. */
3332 tmp = SET_DEST (tmp);
3333 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3336 /* INSN should be a set of CCFP.
3338 See if the result of this insn is used in a reversed FP
3339 conditional branch. If so, reverse our condition and
3340 the branch. Doing so avoids useless add,tr insns. */
3341 next = next_insn (insn);
3344 /* Jumps, calls and labels stop our search. */
3345 if (GET_CODE (next) == JUMP_INSN
3346 || GET_CODE (next) == CALL_INSN
3347 || GET_CODE (next) == CODE_LABEL)
3350 /* As does another fcmp insn. */
3351 if (GET_CODE (next) == INSN
3352 && GET_CODE (PATTERN (next)) == SET
3353 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3354 && REGNO (SET_DEST (PATTERN (next))) == 0)
3357 next = next_insn (next);
3360 /* Is NEXT_INSN a branch? */
3362 && GET_CODE (next) == JUMP_INSN)
3364 rtx pattern = PATTERN (next);
3366 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3367 and CCFP dies, then reverse our conditional and the branch
3368 to avoid the add,tr. */
3369 if (GET_CODE (pattern) == SET
3370 && SET_DEST (pattern) == pc_rtx
3371 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3372 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3373 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3374 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3375 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3376 && (fcmp_count == fbranch_count
3378 && find_regno_note (next, REG_DEAD, 0))))
3380 /* Reverse the branch. */
3381 tmp = XEXP (SET_SRC (pattern), 1);
3382 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3383 XEXP (SET_SRC (pattern), 2) = tmp;
3384 INSN_CODE (next) = -1;
3386 /* Reverse our condition. */
3387 tmp = PATTERN (insn);
3388 PUT_CODE (XEXP (tmp, 1),
3389 (reverse_condition_maybe_unordered
3390 (GET_CODE (XEXP (tmp, 1)))));
3400 /* You may have trouble believing this, but this is the 32 bit HP-PA
3405 Variable arguments (optional; any number may be allocated)
3407 SP-(4*(N+9)) arg word N
3412 Fixed arguments (must be allocated; may remain unused)
3421 SP-32 External Data Pointer (DP)
3423 SP-24 External/stub RP (RP')
3427 SP-8 Calling Stub RP (RP'')
3432 SP-0 Stack Pointer (points to next available address)
3436 /* This function saves registers as follows. Registers marked with ' are
3437 this function's registers (as opposed to the previous function's).
3438 If a frame_pointer isn't needed, r4 is saved as a general register;
3439 the space for the frame pointer is still allocated, though, to keep
3445 SP (FP') Previous FP
3446 SP + 4 Alignment filler (sigh)
3447 SP + 8 Space for locals reserved here.
3451 SP + n All call saved register used.
3455 SP + o All call saved fp registers used.
3459 SP + p (SP') points to next available address.
3463 /* Global variables set by output_function_prologue(). */
3464 /* Size of frame. Need to know this to emit return insns from
3466 static HOST_WIDE_INT actual_fsize, local_fsize;
3467 static int save_fregs;
3469 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3470 Handle case where DISP > 8k by using the add_high_const patterns.
3472 Note in DISP > 8k case, we will leave the high part of the address
3473 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3476 store_reg (int reg, HOST_WIDE_INT disp, int base)
3478 rtx insn, dest, src, basereg;
3480 src = gen_rtx_REG (word_mode, reg);
3481 basereg = gen_rtx_REG (Pmode, base);
3482 if (VAL_14_BITS_P (disp))
3484 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3485 insn = emit_move_insn (dest, src);
3487 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3489 rtx delta = GEN_INT (disp);
3490 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3492 emit_move_insn (tmpreg, delta);
3493 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3496 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3497 gen_rtx_SET (VOIDmode, tmpreg,
3498 gen_rtx_PLUS (Pmode, basereg, delta)));
3499 RTX_FRAME_RELATED_P (insn) = 1;
3501 dest = gen_rtx_MEM (word_mode, tmpreg);
3502 insn = emit_move_insn (dest, src);
3506 rtx delta = GEN_INT (disp);
3507 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3508 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3510 emit_move_insn (tmpreg, high);
3511 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3512 insn = emit_move_insn (dest, src);
3514 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3515 gen_rtx_SET (VOIDmode,
3516 gen_rtx_MEM (word_mode,
3517 gen_rtx_PLUS (word_mode,
3524 RTX_FRAME_RELATED_P (insn) = 1;
3527 /* Emit RTL to store REG at the memory location specified by BASE and then
3528 add MOD to BASE. MOD must be <= 8k. */
3531 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3533 rtx insn, basereg, srcreg, delta;
3535 gcc_assert (VAL_14_BITS_P (mod));
3537 basereg = gen_rtx_REG (Pmode, base);
3538 srcreg = gen_rtx_REG (word_mode, reg);
3539 delta = GEN_INT (mod);
3541 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3544 RTX_FRAME_RELATED_P (insn) = 1;
3546 /* RTX_FRAME_RELATED_P must be set on each frame related set
3547 in a parallel with more than one element. */
3548 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3549 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3553 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3554 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3555 whether to add a frame note or not.
3557 In the DISP > 8k case, we leave the high part of the address in %r1.
3558 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3561 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3565 if (VAL_14_BITS_P (disp))
3567 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3568 plus_constant (gen_rtx_REG (Pmode, base), disp));
3570 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3572 rtx basereg = gen_rtx_REG (Pmode, base);
3573 rtx delta = GEN_INT (disp);
3574 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3576 emit_move_insn (tmpreg, delta);
3577 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3578 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3580 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3581 gen_rtx_SET (VOIDmode, tmpreg,
3582 gen_rtx_PLUS (Pmode, basereg, delta)));
3586 rtx basereg = gen_rtx_REG (Pmode, base);
3587 rtx delta = GEN_INT (disp);
3588 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3590 emit_move_insn (tmpreg,
3591 gen_rtx_PLUS (Pmode, basereg,
3592 gen_rtx_HIGH (Pmode, delta)));
3593 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3594 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3597 if (DO_FRAME_NOTES && note)
3598 RTX_FRAME_RELATED_P (insn) = 1;
3602 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3607 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3608 be consistent with the rounding and size calculation done here.
3609 Change them at the same time. */
3611 /* We do our own stack alignment. First, round the size of the
3612 stack locals up to a word boundary. */
3613 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3615 /* Space for previous frame pointer + filler. If any frame is
3616 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3617 waste some space here for the sake of HP compatibility. The
3618 first slot is only used when the frame pointer is needed. */
3619 if (size || frame_pointer_needed)
3620 size += STARTING_FRAME_OFFSET;
3622 /* If the current function calls __builtin_eh_return, then we need
3623 to allocate stack space for registers that will hold data for
3624 the exception handler. */
3625 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3629 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3631 size += i * UNITS_PER_WORD;
3634 /* Account for space used by the callee general register saves. */
3635 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3636 if (df_regs_ever_live_p (i))
3637 size += UNITS_PER_WORD;
3639 /* Account for space used by the callee floating point register saves. */
3640 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3641 if (df_regs_ever_live_p (i)
3642 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3646 /* We always save both halves of the FP register, so always
3647 increment the frame size by 8 bytes. */
3651 /* If any of the floating registers are saved, account for the
3652 alignment needed for the floating point register save block. */
3655 size = (size + 7) & ~7;
3660 /* The various ABIs include space for the outgoing parameters in the
3661 size of the current function's stack frame. We don't need to align
3662 for the outgoing arguments as their alignment is set by the final
3663 rounding for the frame as a whole. */
3664 size += crtl->outgoing_args_size;
3666 /* Allocate space for the fixed frame marker. This space must be
3667 allocated for any function that makes calls or allocates
3669 if (!current_function_is_leaf || size)
3670 size += TARGET_64BIT ? 48 : 32;
3672 /* Finally, round to the preferred stack boundary. */
3673 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3674 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3677 /* Generate the assembly code for function entry. FILE is a stdio
3678 stream to output the code to. SIZE is an int: how many units of
3679 temporary storage to allocate.
3681 Refer to the array `regs_ever_live' to determine which registers to
3682 save; `regs_ever_live[I]' is nonzero if register number I is ever
3683 used in the function. This function is responsible for knowing
3684 which registers should not be saved even if used. */
3686 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3687 of memory. If any fpu reg is used in the function, we allocate
3688 such a block here, at the bottom of the frame, just in case it's needed.
3690 If this function is a leaf procedure, then we may choose not
3691 to do a "save" insn. The decision about whether or not
3692 to do this is made in regclass.c. */
3695 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3697 /* The function's label and associated .PROC must never be
3698 separated and must be output *after* any profiling declarations
3699 to avoid changing spaces/subspaces within a procedure. */
3700 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3701 fputs ("\t.PROC\n", file);
3703 /* hppa_expand_prologue does the dirty work now. We just need
3704 to output the assembler directives which denote the start
3706 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3707 if (current_function_is_leaf)
3708 fputs (",NO_CALLS", file);
3710 fputs (",CALLS", file);
3712 fputs (",SAVE_RP", file);
3714 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3715 at the beginning of the frame and that it is used as the frame
3716 pointer for the frame. We do this because our current frame
3717 layout doesn't conform to that specified in the HP runtime
3718 documentation and we need a way to indicate to programs such as
3719 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3720 isn't used by HP compilers but is supported by the assembler.
3721 However, SAVE_SP is supposed to indicate that the previous stack
3722 pointer has been saved in the frame marker. */
3723 if (frame_pointer_needed)
3724 fputs (",SAVE_SP", file);
3726 /* Pass on information about the number of callee register saves
3727 performed in the prologue.
3729 The compiler is supposed to pass the highest register number
3730 saved, the assembler then has to adjust that number before
3731 entering it into the unwind descriptor (to account for any
3732 caller saved registers with lower register numbers than the
3733 first callee saved register). */
3735 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3738 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3740 fputs ("\n\t.ENTRY\n", file);
3742 remove_useless_addtr_insns (0);
3746 hppa_expand_prologue (void)
3748 int merge_sp_adjust_with_store = 0;
3749 HOST_WIDE_INT size = get_frame_size ();
3750 HOST_WIDE_INT offset;
3758 /* Compute total size for frame pointer, filler, locals and rounding to
3759 the next word boundary. Similar code appears in compute_frame_size
3760 and must be changed in tandem with this code. */
3761 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3762 if (local_fsize || frame_pointer_needed)
3763 local_fsize += STARTING_FRAME_OFFSET;
3765 actual_fsize = compute_frame_size (size, &save_fregs);
3766 if (flag_stack_usage)
3767 current_function_static_stack_size = actual_fsize;
3769 /* Compute a few things we will use often. */
3770 tmpreg = gen_rtx_REG (word_mode, 1);
3772 /* Save RP first. The calling conventions manual states RP will
3773 always be stored into the caller's frame at sp - 20 or sp - 16
3774 depending on which ABI is in use. */
3775 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3777 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3783 /* Allocate the local frame and set up the frame pointer if needed. */
3784 if (actual_fsize != 0)
3786 if (frame_pointer_needed)
3788 /* Copy the old frame pointer temporarily into %r1. Set up the
3789 new stack pointer, then store away the saved old frame pointer
3790 into the stack at sp and at the same time update the stack
3791 pointer by actual_fsize bytes. Two versions, first
3792 handles small (<8k) frames. The second handles large (>=8k)
3794 insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx);
3796 RTX_FRAME_RELATED_P (insn) = 1;
3798 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3800 RTX_FRAME_RELATED_P (insn) = 1;
3802 if (VAL_14_BITS_P (actual_fsize))
3803 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3806 /* It is incorrect to store the saved frame pointer at *sp,
3807 then increment sp (writes beyond the current stack boundary).
3809 So instead use stwm to store at *sp and post-increment the
3810 stack pointer as an atomic operation. Then increment sp to
3811 finish allocating the new frame. */
3812 HOST_WIDE_INT adjust1 = 8192 - 64;
3813 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3815 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3816 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3820 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3821 we need to store the previous stack pointer (frame pointer)
3822 into the frame marker on targets that use the HP unwind
3823 library. This allows the HP unwind library to be used to
3824 unwind GCC frames. However, we are not fully compatible
3825 with the HP library because our frame layout differs from
3826 that specified in the HP runtime specification.
3828 We don't want a frame note on this instruction as the frame
3829 marker moves during dynamic stack allocation.
3831 This instruction also serves as a blockage to prevent
3832 register spills from being scheduled before the stack
3833 pointer is raised. This is necessary as we store
3834 registers using the frame pointer as a base register,
3835 and the frame pointer is set before sp is raised. */
3836 if (TARGET_HPUX_UNWIND_LIBRARY)
3838 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3839 GEN_INT (TARGET_64BIT ? -8 : -4));
3841 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3842 hard_frame_pointer_rtx);
3845 emit_insn (gen_blockage ());
3847 /* no frame pointer needed. */
3850 /* In some cases we can perform the first callee register save
3851 and allocating the stack frame at the same time. If so, just
3852 make a note of it and defer allocating the frame until saving
3853 the callee registers. */
3854 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3855 merge_sp_adjust_with_store = 1;
3856 /* Can not optimize. Adjust the stack frame by actual_fsize
3859 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3864 /* Normal register save.
3866 Do not save the frame pointer in the frame_pointer_needed case. It
3867 was done earlier. */
3868 if (frame_pointer_needed)
3870 offset = local_fsize;
3872 /* Saving the EH return data registers in the frame is the simplest
3873 way to get the frame unwind information emitted. We put them
3874 just before the general registers. */
3875 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3877 unsigned int i, regno;
3881 regno = EH_RETURN_DATA_REGNO (i);
3882 if (regno == INVALID_REGNUM)
3885 store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
3886 offset += UNITS_PER_WORD;
3890 for (i = 18; i >= 4; i--)
3891 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3893 store_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
3894 offset += UNITS_PER_WORD;
3897 /* Account for %r3 which is saved in a special place. */
3900 /* No frame pointer needed. */
3903 offset = local_fsize - actual_fsize;
3905 /* Saving the EH return data registers in the frame is the simplest
3906 way to get the frame unwind information emitted. */
3907 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3909 unsigned int i, regno;
3913 regno = EH_RETURN_DATA_REGNO (i);
3914 if (regno == INVALID_REGNUM)
3917 /* If merge_sp_adjust_with_store is nonzero, then we can
3918 optimize the first save. */
3919 if (merge_sp_adjust_with_store)
3921 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3922 merge_sp_adjust_with_store = 0;
3925 store_reg (regno, offset, STACK_POINTER_REGNUM);
3926 offset += UNITS_PER_WORD;
3930 for (i = 18; i >= 3; i--)
3931 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3933 /* If merge_sp_adjust_with_store is nonzero, then we can
3934 optimize the first GR save. */
3935 if (merge_sp_adjust_with_store)
3937 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3938 merge_sp_adjust_with_store = 0;
3941 store_reg (i, offset, STACK_POINTER_REGNUM);
3942 offset += UNITS_PER_WORD;
3946 /* If we wanted to merge the SP adjustment with a GR save, but we never
3947 did any GR saves, then just emit the adjustment here. */
3948 if (merge_sp_adjust_with_store)
3949 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3953 /* The hppa calling conventions say that %r19, the pic offset
3954 register, is saved at sp - 32 (in this function's frame)
3955 when generating PIC code. FIXME: What is the correct thing
3956 to do for functions which make no calls and allocate no
3957 frame? Do we need to allocate a frame, or can we just omit
3958 the save? For now we'll just omit the save.
3960 We don't want a note on this insn as the frame marker can
3961 move if there is a dynamic stack allocation. */
3962 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3964 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3966 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3970 /* Align pointer properly (doubleword boundary). */
3971 offset = (offset + 7) & ~7;
3973 /* Floating point register store. */
3978 /* First get the frame or stack pointer to the start of the FP register
3980 if (frame_pointer_needed)
3982 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
3983 base = hard_frame_pointer_rtx;
3987 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3988 base = stack_pointer_rtx;
3991 /* Now actually save the FP registers. */
3992 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3994 if (df_regs_ever_live_p (i)
3995 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3997 rtx addr, insn, reg;
3998 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3999 reg = gen_rtx_REG (DFmode, i);
4000 insn = emit_move_insn (addr, reg);
4003 RTX_FRAME_RELATED_P (insn) = 1;
4006 rtx mem = gen_rtx_MEM (DFmode,
4007 plus_constant (base, offset));
4008 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4009 gen_rtx_SET (VOIDmode, mem, reg));
4013 rtx meml = gen_rtx_MEM (SFmode,
4014 plus_constant (base, offset));
4015 rtx memr = gen_rtx_MEM (SFmode,
4016 plus_constant (base, offset + 4));
4017 rtx regl = gen_rtx_REG (SFmode, i);
4018 rtx regr = gen_rtx_REG (SFmode, i + 1);
4019 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4020 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4023 RTX_FRAME_RELATED_P (setl) = 1;
4024 RTX_FRAME_RELATED_P (setr) = 1;
4025 vec = gen_rtvec (2, setl, setr);
4026 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4027 gen_rtx_SEQUENCE (VOIDmode, vec));
4030 offset += GET_MODE_SIZE (DFmode);
4037 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4038 Handle case where DISP > 8k by using the add_high_const patterns. */
4041 load_reg (int reg, HOST_WIDE_INT disp, int base)
4043 rtx dest = gen_rtx_REG (word_mode, reg);
4044 rtx basereg = gen_rtx_REG (Pmode, base);
4047 if (VAL_14_BITS_P (disp))
4048 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4049 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4051 rtx delta = GEN_INT (disp);
4052 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4054 emit_move_insn (tmpreg, delta);
4055 if (TARGET_DISABLE_INDEXING)
4057 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4058 src = gen_rtx_MEM (word_mode, tmpreg);
4061 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4065 rtx delta = GEN_INT (disp);
4066 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4067 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4069 emit_move_insn (tmpreg, high);
4070 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4073 emit_move_insn (dest, src);
4076 /* Update the total code bytes output to the text section. */
4079 update_total_code_bytes (unsigned int nbytes)
4081 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4082 && !IN_NAMED_SECTION_P (cfun->decl))
4084 unsigned int old_total = total_code_bytes;
4086 total_code_bytes += nbytes;
4088 /* Be prepared to handle overflows. */
4089 if (old_total > total_code_bytes)
4090 total_code_bytes = UINT_MAX;
4094 /* This function generates the assembly code for function exit.
4095 Args are as for output_function_prologue ().
4097 The function epilogue should not depend on the current stack
4098 pointer! It should use the frame pointer only. This is mandatory
4099 because of alloca; we also take advantage of it to omit stack
4100 adjustments before returning. */
4103 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4105 rtx insn = get_last_insn ();
4109 /* hppa_expand_epilogue does the dirty work now. We just need
4110 to output the assembler directives which denote the end
4113 To make debuggers happy, emit a nop if the epilogue was completely
4114 eliminated due to a volatile call as the last insn in the
4115 current function. That way the return address (in %r2) will
4116 always point to a valid instruction in the current function. */
4118 /* Get the last real insn. */
4119 if (GET_CODE (insn) == NOTE)
4120 insn = prev_real_insn (insn);
4122 /* If it is a sequence, then look inside. */
4123 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4124 insn = XVECEXP (PATTERN (insn), 0, 0);
4126 /* If insn is a CALL_INSN, then it must be a call to a volatile
4127 function (otherwise there would be epilogue insns). */
4128 if (insn && GET_CODE (insn) == CALL_INSN)
4130 fputs ("\tnop\n", file);
4134 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4136 if (TARGET_SOM && TARGET_GAS)
4138 /* We done with this subspace except possibly for some additional
4139 debug information. Forget that we are in this subspace to ensure
4140 that the next function is output in its own subspace. */
4142 cfun->machine->in_nsubspa = 2;
4145 if (INSN_ADDRESSES_SET_P ())
4147 insn = get_last_nonnote_insn ();
4148 last_address += INSN_ADDRESSES (INSN_UID (insn));
4150 last_address += insn_default_length (insn);
4151 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4152 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4155 last_address = UINT_MAX;
4157 /* Finally, update the total number of code bytes output so far. */
4158 update_total_code_bytes (last_address);
4162 hppa_expand_epilogue (void)
4165 HOST_WIDE_INT offset;
4166 HOST_WIDE_INT ret_off = 0;
4168 int merge_sp_adjust_with_load = 0;
4170 /* We will use this often. */
4171 tmpreg = gen_rtx_REG (word_mode, 1);
4173 /* Try to restore RP early to avoid load/use interlocks when
4174 RP gets used in the return (bv) instruction. This appears to still
4175 be necessary even when we schedule the prologue and epilogue. */
4178 ret_off = TARGET_64BIT ? -16 : -20;
4179 if (frame_pointer_needed)
4181 load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM);
4186 /* No frame pointer, and stack is smaller than 8k. */
4187 if (VAL_14_BITS_P (ret_off - actual_fsize))
4189 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4195 /* General register restores. */
4196 if (frame_pointer_needed)
4198 offset = local_fsize;
4200 /* If the current function calls __builtin_eh_return, then we need
4201 to restore the saved EH data registers. */
4202 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4204 unsigned int i, regno;
4208 regno = EH_RETURN_DATA_REGNO (i);
4209 if (regno == INVALID_REGNUM)
4212 load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
4213 offset += UNITS_PER_WORD;
4217 for (i = 18; i >= 4; i--)
4218 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4220 load_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
4221 offset += UNITS_PER_WORD;
4226 offset = local_fsize - actual_fsize;
4228 /* If the current function calls __builtin_eh_return, then we need
4229 to restore the saved EH data registers. */
4230 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4232 unsigned int i, regno;
4236 regno = EH_RETURN_DATA_REGNO (i);
4237 if (regno == INVALID_REGNUM)
4240 /* Only for the first load.
4241 merge_sp_adjust_with_load holds the register load
4242 with which we will merge the sp adjustment. */
4243 if (merge_sp_adjust_with_load == 0
4245 && VAL_14_BITS_P (-actual_fsize))
4246 merge_sp_adjust_with_load = regno;
4248 load_reg (regno, offset, STACK_POINTER_REGNUM);
4249 offset += UNITS_PER_WORD;
4253 for (i = 18; i >= 3; i--)
4255 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4257 /* Only for the first load.
4258 merge_sp_adjust_with_load holds the register load
4259 with which we will merge the sp adjustment. */
4260 if (merge_sp_adjust_with_load == 0
4262 && VAL_14_BITS_P (-actual_fsize))
4263 merge_sp_adjust_with_load = i;
4265 load_reg (i, offset, STACK_POINTER_REGNUM);
4266 offset += UNITS_PER_WORD;
4271 /* Align pointer properly (doubleword boundary). */
4272 offset = (offset + 7) & ~7;
4274 /* FP register restores. */
4277 /* Adjust the register to index off of. */
4278 if (frame_pointer_needed)
4279 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4281 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4283 /* Actually do the restores now. */
4284 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4285 if (df_regs_ever_live_p (i)
4286 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4288 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4289 rtx dest = gen_rtx_REG (DFmode, i);
4290 emit_move_insn (dest, src);
4294 /* Emit a blockage insn here to keep these insns from being moved to
4295 an earlier spot in the epilogue, or into the main instruction stream.
4297 This is necessary as we must not cut the stack back before all the
4298 restores are finished. */
4299 emit_insn (gen_blockage ());
4301 /* Reset stack pointer (and possibly frame pointer). The stack
4302 pointer is initially set to fp + 64 to avoid a race condition. */
4303 if (frame_pointer_needed)
4305 rtx delta = GEN_INT (-64);
4307 set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0);
4308 emit_insn (gen_pre_load (hard_frame_pointer_rtx,
4309 stack_pointer_rtx, delta));
4311 /* If we were deferring a callee register restore, do it now. */
4312 else if (merge_sp_adjust_with_load)
4314 rtx delta = GEN_INT (-actual_fsize);
4315 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4317 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4319 else if (actual_fsize != 0)
4320 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4323 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4324 frame greater than 8k), do so now. */
4326 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4328 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4330 rtx sa = EH_RETURN_STACKADJ_RTX;
4332 emit_insn (gen_blockage ());
4333 emit_insn (TARGET_64BIT
4334 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4335 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4340 hppa_pic_save_rtx (void)
4342 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4345 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4346 #define NO_DEFERRED_PROFILE_COUNTERS 0
4350 /* Vector of funcdef numbers. */
4351 static VEC(int,heap) *funcdef_nos;
4353 /* Output deferred profile counters. */
4355 output_deferred_profile_counters (void)
4360 if (VEC_empty (int, funcdef_nos))
4363 switch_to_section (data_section);
4364 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4365 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4367 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4369 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4370 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4373 VEC_free (int, heap, funcdef_nos);
4377 hppa_profile_hook (int label_no)
4379 /* We use SImode for the address of the function in both 32 and
4380 64-bit code to avoid having to provide DImode versions of the
4381 lcla2 and load_offset_label_address insn patterns. */
4382 rtx reg = gen_reg_rtx (SImode);
4383 rtx label_rtx = gen_label_rtx ();
4384 rtx begin_label_rtx, call_insn;
4385 char begin_label_name[16];
4387 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4389 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4392 emit_move_insn (arg_pointer_rtx,
4393 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4396 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4398 /* The address of the function is loaded into %r25 with an instruction-
4399 relative sequence that avoids the use of relocations. The sequence
4400 is split so that the load_offset_label_address instruction can
4401 occupy the delay slot of the call to _mcount. */
4403 emit_insn (gen_lcla2 (reg, label_rtx));
4405 emit_insn (gen_lcla1 (reg, label_rtx));
4407 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4408 reg, begin_label_rtx, label_rtx));
4410 #if !NO_DEFERRED_PROFILE_COUNTERS
4412 rtx count_label_rtx, addr, r24;
4413 char count_label_name[16];
4415 VEC_safe_push (int, heap, funcdef_nos, label_no);
4416 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4417 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4419 addr = force_reg (Pmode, count_label_rtx);
4420 r24 = gen_rtx_REG (Pmode, 24);
4421 emit_move_insn (r24, addr);
4424 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4425 gen_rtx_SYMBOL_REF (Pmode,
4427 GEN_INT (TARGET_64BIT ? 24 : 12)));
4429 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4434 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4435 gen_rtx_SYMBOL_REF (Pmode,
4437 GEN_INT (TARGET_64BIT ? 16 : 8)));
4441 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4442 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4444 /* Indicate the _mcount call cannot throw, nor will it execute a
4446 make_reg_eh_region_note_nothrow_nononlocal (call_insn);
4449 /* Fetch the return address for the frame COUNT steps up from
4450 the current frame, after the prologue. FRAMEADDR is the
4451 frame pointer of the COUNT frame.
4453 We want to ignore any export stub remnants here. To handle this,
4454 we examine the code at the return address, and if it is an export
4455 stub, we return a memory rtx for the stub return address stored
4458 The value returned is used in two different ways:
4460 1. To find a function's caller.
4462 2. To change the return address for a function.
4464 This function handles most instances of case 1; however, it will
4465 fail if there are two levels of stubs to execute on the return
4466 path. The only way I believe that can happen is if the return value
4467 needs a parameter relocation, which never happens for C code.
4469 This function handles most instances of case 2; however, it will
4470 fail if we did not originally have stub code on the return path
4471 but will need stub code on the new return path. This can happen if
4472 the caller & callee are both in the main program, but the new
4473 return location is in a shared library. */
4476 return_addr_rtx (int count, rtx frameaddr)
4483 /* Instruction stream at the normal return address for the export stub:
4485 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4486 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4487 0x00011820 | stub+16: mtsp r1,sr0
4488 0xe0400002 | stub+20: be,n 0(sr0,rp)
4490 0xe0400002 must be specified as -532676606 so that it won't be
4491 rejected as an invalid immediate operand on 64-bit hosts. */
4493 HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606};
4499 rp = get_hard_reg_initial_val (Pmode, 2);
4501 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4504 /* If there is no export stub then just use the value saved from
4505 the return pointer register. */
4507 saved_rp = gen_reg_rtx (Pmode);
4508 emit_move_insn (saved_rp, rp);
4510 /* Get pointer to the instruction stream. We have to mask out the
4511 privilege level from the two low order bits of the return address
4512 pointer here so that ins will point to the start of the first
4513 instruction that would have been executed if we returned. */
4514 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4515 label = gen_label_rtx ();
4517 /* Check the instruction stream at the normal return address for the
4518 export stub. If it is an export stub, than our return address is
4519 really in -24[frameaddr]. */
4521 for (i = 0; i < 3; i++)
4523 rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4));
4524 rtx op1 = GEN_INT (insns[i]);
4525 emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label);
4528 /* Here we know that our return address points to an export
4529 stub. We don't want to return the address of the export stub,
4530 but rather the return address of the export stub. That return
4531 address is stored at -24[frameaddr]. */
4533 emit_move_insn (saved_rp,
4535 memory_address (Pmode,
4536 plus_constant (frameaddr,
4545 emit_bcond_fp (rtx operands[])
4547 enum rtx_code code = GET_CODE (operands[0]);
4548 rtx operand0 = operands[1];
4549 rtx operand1 = operands[2];
4550 rtx label = operands[3];
4552 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4553 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)));
4555 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4556 gen_rtx_IF_THEN_ELSE (VOIDmode,
4559 gen_rtx_REG (CCFPmode, 0),
4561 gen_rtx_LABEL_REF (VOIDmode, label),
4566 /* Adjust the cost of a scheduling dependency. Return the new cost of
4567 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4570 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4572 enum attr_type attr_type;
4574 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4575 true dependencies as they are described with bypasses now. */
4576 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4579 if (! recog_memoized (insn))
4582 attr_type = get_attr_type (insn);
4584 switch (REG_NOTE_KIND (link))
4587 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4590 if (attr_type == TYPE_FPLOAD)
4592 rtx pat = PATTERN (insn);
4593 rtx dep_pat = PATTERN (dep_insn);
4594 if (GET_CODE (pat) == PARALLEL)
4596 /* This happens for the fldXs,mb patterns. */
4597 pat = XVECEXP (pat, 0, 0);
4599 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4600 /* If this happens, we have to extend this to schedule
4601 optimally. Return 0 for now. */
4604 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4606 if (! recog_memoized (dep_insn))
4608 switch (get_attr_type (dep_insn))
4615 case TYPE_FPSQRTSGL:
4616 case TYPE_FPSQRTDBL:
4617 /* A fpload can't be issued until one cycle before a
4618 preceding arithmetic operation has finished if
4619 the target of the fpload is any of the sources
4620 (or destination) of the arithmetic operation. */
4621 return insn_default_latency (dep_insn) - 1;
4628 else if (attr_type == TYPE_FPALU)
4630 rtx pat = PATTERN (insn);
4631 rtx dep_pat = PATTERN (dep_insn);
4632 if (GET_CODE (pat) == PARALLEL)
4634 /* This happens for the fldXs,mb patterns. */
4635 pat = XVECEXP (pat, 0, 0);
4637 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4638 /* If this happens, we have to extend this to schedule
4639 optimally. Return 0 for now. */
4642 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4644 if (! recog_memoized (dep_insn))
4646 switch (get_attr_type (dep_insn))
4650 case TYPE_FPSQRTSGL:
4651 case TYPE_FPSQRTDBL:
4652 /* An ALU flop can't be issued until two cycles before a
4653 preceding divide or sqrt operation has finished if
4654 the target of the ALU flop is any of the sources
4655 (or destination) of the divide or sqrt operation. */
4656 return insn_default_latency (dep_insn) - 2;
4664 /* For other anti dependencies, the cost is 0. */
4667 case REG_DEP_OUTPUT:
4668 /* Output dependency; DEP_INSN writes a register that INSN writes some
4670 if (attr_type == TYPE_FPLOAD)
4672 rtx pat = PATTERN (insn);
4673 rtx dep_pat = PATTERN (dep_insn);
4674 if (GET_CODE (pat) == PARALLEL)
4676 /* This happens for the fldXs,mb patterns. */
4677 pat = XVECEXP (pat, 0, 0);
4679 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4680 /* If this happens, we have to extend this to schedule
4681 optimally. Return 0 for now. */
4684 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4686 if (! recog_memoized (dep_insn))
4688 switch (get_attr_type (dep_insn))
4695 case TYPE_FPSQRTSGL:
4696 case TYPE_FPSQRTDBL:
4697 /* A fpload can't be issued until one cycle before a
4698 preceding arithmetic operation has finished if
4699 the target of the fpload is the destination of the
4700 arithmetic operation.
4702 Exception: For PA7100LC, PA7200 and PA7300, the cost
4703 is 3 cycles, unless they bundle together. We also
4704 pay the penalty if the second insn is a fpload. */
4705 return insn_default_latency (dep_insn) - 1;
4712 else if (attr_type == TYPE_FPALU)
4714 rtx pat = PATTERN (insn);
4715 rtx dep_pat = PATTERN (dep_insn);
4716 if (GET_CODE (pat) == PARALLEL)
4718 /* This happens for the fldXs,mb patterns. */
4719 pat = XVECEXP (pat, 0, 0);
4721 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4722 /* If this happens, we have to extend this to schedule
4723 optimally. Return 0 for now. */
4726 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4728 if (! recog_memoized (dep_insn))
4730 switch (get_attr_type (dep_insn))
4734 case TYPE_FPSQRTSGL:
4735 case TYPE_FPSQRTDBL:
4736 /* An ALU flop can't be issued until two cycles before a
4737 preceding divide or sqrt operation has finished if
4738 the target of the ALU flop is also the target of
4739 the divide or sqrt operation. */
4740 return insn_default_latency (dep_insn) - 2;
4748 /* For other output dependencies, the cost is 0. */
4756 /* Adjust scheduling priorities. We use this to try and keep addil
4757 and the next use of %r1 close together. */
4759 pa_adjust_priority (rtx insn, int priority)
4761 rtx set = single_set (insn);
4765 src = SET_SRC (set);
4766 dest = SET_DEST (set);
4767 if (GET_CODE (src) == LO_SUM
4768 && symbolic_operand (XEXP (src, 1), VOIDmode)
4769 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4772 else if (GET_CODE (src) == MEM
4773 && GET_CODE (XEXP (src, 0)) == LO_SUM
4774 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4775 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4778 else if (GET_CODE (dest) == MEM
4779 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4780 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4781 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4787 /* The 700 can only issue a single insn at a time.
4788 The 7XXX processors can issue two insns at a time.
4789 The 8000 can issue 4 insns at a time. */
4791 pa_issue_rate (void)
4795 case PROCESSOR_700: return 1;
4796 case PROCESSOR_7100: return 2;
4797 case PROCESSOR_7100LC: return 2;
4798 case PROCESSOR_7200: return 2;
4799 case PROCESSOR_7300: return 2;
4800 case PROCESSOR_8000: return 4;
4809 /* Return any length adjustment needed by INSN which already has its length
4810 computed as LENGTH. Return zero if no adjustment is necessary.
4812 For the PA: function calls, millicode calls, and backwards short
4813 conditional branches with unfilled delay slots need an adjustment by +1
4814 (to account for the NOP which will be inserted into the instruction stream).
4816 Also compute the length of an inline block move here as it is too
4817 complicated to express as a length attribute in pa.md. */
4819 pa_adjust_insn_length (rtx insn, int length)
4821 rtx pat = PATTERN (insn);
4823 /* Jumps inside switch tables which have unfilled delay slots need
4825 if (GET_CODE (insn) == JUMP_INSN
4826 && GET_CODE (pat) == PARALLEL
4827 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4829 /* Millicode insn with an unfilled delay slot. */
4830 else if (GET_CODE (insn) == INSN
4831 && GET_CODE (pat) != SEQUENCE
4832 && GET_CODE (pat) != USE
4833 && GET_CODE (pat) != CLOBBER
4834 && get_attr_type (insn) == TYPE_MILLI)
4836 /* Block move pattern. */
4837 else if (GET_CODE (insn) == INSN
4838 && GET_CODE (pat) == PARALLEL
4839 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4840 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4841 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4842 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4843 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4844 return compute_movmem_length (insn) - 4;
4845 /* Block clear pattern. */
4846 else if (GET_CODE (insn) == INSN
4847 && GET_CODE (pat) == PARALLEL
4848 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4849 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4850 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4851 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4852 return compute_clrmem_length (insn) - 4;
4853 /* Conditional branch with an unfilled delay slot. */
4854 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4856 /* Adjust a short backwards conditional with an unfilled delay slot. */
4857 if (GET_CODE (pat) == SET
4859 && JUMP_LABEL (insn) != NULL_RTX
4860 && ! forward_branch_p (insn))
4862 else if (GET_CODE (pat) == PARALLEL
4863 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4866 /* Adjust dbra insn with short backwards conditional branch with
4867 unfilled delay slot -- only for case where counter is in a
4868 general register register. */
4869 else if (GET_CODE (pat) == PARALLEL
4870 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4871 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4872 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4874 && ! forward_branch_p (insn))
4882 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
4885 pa_print_operand_punct_valid_p (unsigned char code)
4896 /* Print operand X (an rtx) in assembler syntax to file FILE.
4897 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4898 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4901 print_operand (FILE *file, rtx x, int code)
4906 /* Output a 'nop' if there's nothing for the delay slot. */
4907 if (dbr_sequence_length () == 0)
4908 fputs ("\n\tnop", file);
4911 /* Output a nullification completer if there's nothing for the */
4912 /* delay slot or nullification is requested. */
4913 if (dbr_sequence_length () == 0 ||
4915 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4919 /* Print out the second register name of a register pair.
4920 I.e., R (6) => 7. */
4921 fputs (reg_names[REGNO (x) + 1], file);
4924 /* A register or zero. */
4926 || (x == CONST0_RTX (DFmode))
4927 || (x == CONST0_RTX (SFmode)))
4929 fputs ("%r0", file);
4935 /* A register or zero (floating point). */
4937 || (x == CONST0_RTX (DFmode))
4938 || (x == CONST0_RTX (SFmode)))
4940 fputs ("%fr0", file);
4949 xoperands[0] = XEXP (XEXP (x, 0), 0);
4950 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4951 output_global_address (file, xoperands[1], 0);
4952 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4956 case 'C': /* Plain (C)ondition */
4958 switch (GET_CODE (x))
4961 fputs ("=", file); break;
4963 fputs ("<>", file); break;
4965 fputs (">", file); break;
4967 fputs (">=", file); break;
4969 fputs (">>=", file); break;
4971 fputs (">>", file); break;
4973 fputs ("<", file); break;
4975 fputs ("<=", file); break;
4977 fputs ("<<=", file); break;
4979 fputs ("<<", file); break;
4984 case 'N': /* Condition, (N)egated */
4985 switch (GET_CODE (x))
4988 fputs ("<>", file); break;
4990 fputs ("=", file); break;
4992 fputs ("<=", file); break;
4994 fputs ("<", file); break;
4996 fputs ("<<", file); break;
4998 fputs ("<<=", file); break;
5000 fputs (">=", file); break;
5002 fputs (">", file); break;
5004 fputs (">>", file); break;
5006 fputs (">>=", file); break;
5011 /* For floating point comparisons. Note that the output
5012 predicates are the complement of the desired mode. The
5013 conditions for GT, GE, LT, LE and LTGT cause an invalid
5014 operation exception if the result is unordered and this
5015 exception is enabled in the floating-point status register. */
5017 switch (GET_CODE (x))
5020 fputs ("!=", file); break;
5022 fputs ("=", file); break;
5024 fputs ("!>", file); break;
5026 fputs ("!>=", file); break;
5028 fputs ("!<", file); break;
5030 fputs ("!<=", file); break;
5032 fputs ("!<>", file); break;
5034 fputs ("!?<=", file); break;
5036 fputs ("!?<", file); break;
5038 fputs ("!?>=", file); break;
5040 fputs ("!?>", file); break;
5042 fputs ("!?=", file); break;
5044 fputs ("!?", file); break;
5046 fputs ("?", file); break;
5051 case 'S': /* Condition, operands are (S)wapped. */
5052 switch (GET_CODE (x))
5055 fputs ("=", file); break;
5057 fputs ("<>", file); break;
5059 fputs ("<", file); break;
5061 fputs ("<=", file); break;
5063 fputs ("<<=", file); break;
5065 fputs ("<<", file); break;
5067 fputs (">", file); break;
5069 fputs (">=", file); break;
5071 fputs (">>=", file); break;
5073 fputs (">>", file); break;
5078 case 'B': /* Condition, (B)oth swapped and negate. */
5079 switch (GET_CODE (x))
5082 fputs ("<>", file); break;
5084 fputs ("=", file); break;
5086 fputs (">=", file); break;
5088 fputs (">", file); break;
5090 fputs (">>", file); break;
5092 fputs (">>=", file); break;
5094 fputs ("<=", file); break;
5096 fputs ("<", file); break;
5098 fputs ("<<", file); break;
5100 fputs ("<<=", file); break;
5106 gcc_assert (GET_CODE (x) == CONST_INT);
5107 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5110 gcc_assert (GET_CODE (x) == CONST_INT);
5111 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5114 gcc_assert (GET_CODE (x) == CONST_INT);
5115 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5118 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5119 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5122 gcc_assert (GET_CODE (x) == CONST_INT);
5123 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5126 gcc_assert (GET_CODE (x) == CONST_INT);
5127 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5130 if (GET_CODE (x) == CONST_INT)
5135 switch (GET_CODE (XEXP (x, 0)))
5139 if (ASSEMBLER_DIALECT == 0)
5140 fputs ("s,mb", file);
5142 fputs (",mb", file);
5146 if (ASSEMBLER_DIALECT == 0)
5147 fputs ("s,ma", file);
5149 fputs (",ma", file);
5152 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5153 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5155 if (ASSEMBLER_DIALECT == 0)
5158 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5159 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5161 if (ASSEMBLER_DIALECT == 0)
5162 fputs ("x,s", file);
5166 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5170 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5176 output_global_address (file, x, 0);
5179 output_global_address (file, x, 1);
5181 case 0: /* Don't do anything special */
5186 compute_zdepwi_operands (INTVAL (x), op);
5187 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5193 compute_zdepdi_operands (INTVAL (x), op);
5194 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5198 /* We can get here from a .vtable_inherit due to our
5199 CONSTANT_ADDRESS_P rejecting perfectly good constant
5205 if (GET_CODE (x) == REG)
5207 fputs (reg_names [REGNO (x)], file);
5208 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5214 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5215 && (REGNO (x) & 1) == 0)
5218 else if (GET_CODE (x) == MEM)
5220 int size = GET_MODE_SIZE (GET_MODE (x));
5221 rtx base = NULL_RTX;
5222 switch (GET_CODE (XEXP (x, 0)))
5226 base = XEXP (XEXP (x, 0), 0);
5227 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5231 base = XEXP (XEXP (x, 0), 0);
5232 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5235 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5236 fprintf (file, "%s(%s)",
5237 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5238 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5239 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5240 fprintf (file, "%s(%s)",
5241 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5242 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5243 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5244 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5246 /* Because the REG_POINTER flag can get lost during reload,
5247 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5248 index and base registers in the combined move patterns. */
5249 rtx base = XEXP (XEXP (x, 0), 1);
5250 rtx index = XEXP (XEXP (x, 0), 0);
5252 fprintf (file, "%s(%s)",
5253 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5256 output_address (XEXP (x, 0));
5259 output_address (XEXP (x, 0));
5264 output_addr_const (file, x);
5267 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5270 output_global_address (FILE *file, rtx x, int round_constant)
5273 /* Imagine (high (const (plus ...))). */
5274 if (GET_CODE (x) == HIGH)
5277 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5278 output_addr_const (file, x);
5279 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5281 output_addr_const (file, x);
5282 fputs ("-$global$", file);
5284 else if (GET_CODE (x) == CONST)
5286 const char *sep = "";
5287 int offset = 0; /* assembler wants -$global$ at end */
5288 rtx base = NULL_RTX;
5290 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5293 base = XEXP (XEXP (x, 0), 0);
5294 output_addr_const (file, base);
5297 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5303 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5306 base = XEXP (XEXP (x, 0), 1);
5307 output_addr_const (file, base);
5310 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5316 /* How bogus. The compiler is apparently responsible for
5317 rounding the constant if it uses an LR field selector.
5319 The linker and/or assembler seem a better place since
5320 they have to do this kind of thing already.
5322 If we fail to do this, HP's optimizing linker may eliminate
5323 an addil, but not update the ldw/stw/ldo instruction that
5324 uses the result of the addil. */
5326 offset = ((offset + 0x1000) & ~0x1fff);
5328 switch (GET_CODE (XEXP (x, 0)))
5341 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5349 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5350 fputs ("-$global$", file);
5352 fprintf (file, "%s%d", sep, offset);
5355 output_addr_const (file, x);
5358 /* Output boilerplate text to appear at the beginning of the file.
5359 There are several possible versions. */
5360 #define aputs(x) fputs(x, asm_out_file)
5362 pa_file_start_level (void)
5365 aputs ("\t.LEVEL 2.0w\n");
5366 else if (TARGET_PA_20)
5367 aputs ("\t.LEVEL 2.0\n");
5368 else if (TARGET_PA_11)
5369 aputs ("\t.LEVEL 1.1\n");
5371 aputs ("\t.LEVEL 1.0\n");
5375 pa_file_start_space (int sortspace)
5377 aputs ("\t.SPACE $PRIVATE$");
5380 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5381 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5382 "\n\t.SPACE $TEXT$");
5385 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5386 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5390 pa_file_start_file (int want_version)
5392 if (write_symbols != NO_DEBUG)
5394 output_file_directive (asm_out_file, main_input_filename);
5396 aputs ("\t.version\t\"01.01\"\n");
5401 pa_file_start_mcount (const char *aswhat)
5404 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5408 pa_elf_file_start (void)
5410 pa_file_start_level ();
5411 pa_file_start_mcount ("ENTRY");
5412 pa_file_start_file (0);
5416 pa_som_file_start (void)
5418 pa_file_start_level ();
5419 pa_file_start_space (0);
5420 aputs ("\t.IMPORT $global$,DATA\n"
5421 "\t.IMPORT $$dyncall,MILLICODE\n");
5422 pa_file_start_mcount ("CODE");
5423 pa_file_start_file (0);
5427 pa_linux_file_start (void)
5429 pa_file_start_file (1);
5430 pa_file_start_level ();
5431 pa_file_start_mcount ("CODE");
5435 pa_hpux64_gas_file_start (void)
5437 pa_file_start_level ();
5438 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5440 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5442 pa_file_start_file (1);
5446 pa_hpux64_hpas_file_start (void)
5448 pa_file_start_level ();
5449 pa_file_start_space (1);
5450 pa_file_start_mcount ("CODE");
5451 pa_file_start_file (0);
5455 /* Search the deferred plabel list for SYMBOL and return its internal
5456 label. If an entry for SYMBOL is not found, a new entry is created. */
5459 get_deferred_plabel (rtx symbol)
5461 const char *fname = XSTR (symbol, 0);
5464 /* See if we have already put this function on the list of deferred
5465 plabels. This list is generally small, so a liner search is not
5466 too ugly. If it proves too slow replace it with something faster. */
5467 for (i = 0; i < n_deferred_plabels; i++)
5468 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5471 /* If the deferred plabel list is empty, or this entry was not found
5472 on the list, create a new entry on the list. */
5473 if (deferred_plabels == NULL || i == n_deferred_plabels)
5477 if (deferred_plabels == 0)
5478 deferred_plabels = ggc_alloc_deferred_plabel ();
5480 deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel,
5482 n_deferred_plabels + 1);
5484 i = n_deferred_plabels++;
5485 deferred_plabels[i].internal_label = gen_label_rtx ();
5486 deferred_plabels[i].symbol = symbol;
5488 /* Gross. We have just implicitly taken the address of this
5489 function. Mark it in the same manner as assemble_name. */
5490 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5492 mark_referenced (id);
5495 return deferred_plabels[i].internal_label;
5499 output_deferred_plabels (void)
5503 /* If we have some deferred plabels, then we need to switch into the
5504 data or readonly data section, and align it to a 4 byte boundary
5505 before outputting the deferred plabels. */
5506 if (n_deferred_plabels)
5508 switch_to_section (flag_pic ? data_section : readonly_data_section);
5509 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5512 /* Now output the deferred plabels. */
5513 for (i = 0; i < n_deferred_plabels; i++)
5515 targetm.asm_out.internal_label (asm_out_file, "L",
5516 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5517 assemble_integer (deferred_plabels[i].symbol,
5518 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5522 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5523 /* Initialize optabs to point to HPUX long double emulation routines. */
5525 pa_hpux_init_libfuncs (void)
5527 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5528 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5529 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5530 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5531 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5532 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5533 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5534 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5535 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5537 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5538 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5539 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5540 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5541 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5542 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5543 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5545 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5546 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5547 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5548 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5550 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5551 ? "__U_Qfcnvfxt_quad_to_sgl"
5552 : "_U_Qfcnvfxt_quad_to_sgl");
5553 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5554 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5555 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5557 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5558 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5559 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5560 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5564 /* HP's millicode routines mean something special to the assembler.
5565 Keep track of which ones we have used. */
5567 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5568 static void import_milli (enum millicodes);
5569 static char imported[(int) end1000];
5570 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5571 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5572 #define MILLI_START 10
5575 import_milli (enum millicodes code)
5577 char str[sizeof (import_string)];
5579 if (!imported[(int) code])
5581 imported[(int) code] = 1;
5582 strcpy (str, import_string);
5583 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5584 output_asm_insn (str, 0);
5588 /* The register constraints have put the operands and return value in
5589 the proper registers. */
5592 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5594 import_milli (mulI);
5595 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5598 /* Emit the rtl for doing a division by a constant. */
5600 /* Do magic division millicodes exist for this value? */
5601 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5603 /* We'll use an array to keep track of the magic millicodes and
5604 whether or not we've used them already. [n][0] is signed, [n][1] is
5607 static int div_milli[16][2];
5610 emit_hpdiv_const (rtx *operands, int unsignedp)
5612 if (GET_CODE (operands[2]) == CONST_INT
5613 && INTVAL (operands[2]) > 0
5614 && INTVAL (operands[2]) < 16
5615 && magic_milli[INTVAL (operands[2])])
5617 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5619 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5623 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5624 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5626 gen_rtx_REG (SImode, 26),
5628 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5629 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5630 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5631 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5632 gen_rtx_CLOBBER (VOIDmode, ret))));
5633 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5640 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5644 /* If the divisor is a constant, try to use one of the special
5646 if (GET_CODE (operands[0]) == CONST_INT)
5648 static char buf[100];
5649 divisor = INTVAL (operands[0]);
5650 if (!div_milli[divisor][unsignedp])
5652 div_milli[divisor][unsignedp] = 1;
5654 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5656 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5660 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5661 INTVAL (operands[0]));
5662 return output_millicode_call (insn,
5663 gen_rtx_SYMBOL_REF (SImode, buf));
5667 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5668 INTVAL (operands[0]));
5669 return output_millicode_call (insn,
5670 gen_rtx_SYMBOL_REF (SImode, buf));
5673 /* Divisor isn't a special constant. */
5678 import_milli (divU);
5679 return output_millicode_call (insn,
5680 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5684 import_milli (divI);
5685 return output_millicode_call (insn,
5686 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5691 /* Output a $$rem millicode to do mod. */
5694 output_mod_insn (int unsignedp, rtx insn)
5698 import_milli (remU);
5699 return output_millicode_call (insn,
5700 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5704 import_milli (remI);
5705 return output_millicode_call (insn,
5706 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5711 output_arg_descriptor (rtx call_insn)
5713 const char *arg_regs[4];
5714 enum machine_mode arg_mode;
5716 int i, output_flag = 0;
5719 /* We neither need nor want argument location descriptors for the
5720 64bit runtime environment or the ELF32 environment. */
5721 if (TARGET_64BIT || TARGET_ELF32)
5724 for (i = 0; i < 4; i++)
5727 /* Specify explicitly that no argument relocations should take place
5728 if using the portable runtime calling conventions. */
5729 if (TARGET_PORTABLE_RUNTIME)
5731 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5736 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5737 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5738 link; link = XEXP (link, 1))
5740 rtx use = XEXP (link, 0);
5742 if (! (GET_CODE (use) == USE
5743 && GET_CODE (XEXP (use, 0)) == REG
5744 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5747 arg_mode = GET_MODE (XEXP (use, 0));
5748 regno = REGNO (XEXP (use, 0));
5749 if (regno >= 23 && regno <= 26)
5751 arg_regs[26 - regno] = "GR";
5752 if (arg_mode == DImode)
5753 arg_regs[25 - regno] = "GR";
5755 else if (regno >= 32 && regno <= 39)
5757 if (arg_mode == SFmode)
5758 arg_regs[(regno - 32) / 2] = "FR";
5761 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5762 arg_regs[(regno - 34) / 2] = "FR";
5763 arg_regs[(regno - 34) / 2 + 1] = "FU";
5765 arg_regs[(regno - 34) / 2] = "FU";
5766 arg_regs[(regno - 34) / 2 + 1] = "FR";
5771 fputs ("\t.CALL ", asm_out_file);
5772 for (i = 0; i < 4; i++)
5777 fputc (',', asm_out_file);
5778 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5781 fputc ('\n', asm_out_file);
5785 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
5786 enum machine_mode mode, secondary_reload_info *sri)
5789 enum reg_class rclass = (enum reg_class) rclass_i;
5791 /* Handle the easy stuff first. */
5792 if (rclass == R1_REGS)
5798 if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5804 /* If we have something like (mem (mem (...)), we can safely assume the
5805 inner MEM will end up in a general register after reloading, so there's
5806 no need for a secondary reload. */
5807 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5810 /* Trying to load a constant into a FP register during PIC code
5811 generation requires %r1 as a scratch register. */
5813 && (mode == SImode || mode == DImode)
5814 && FP_REG_CLASS_P (rclass)
5815 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5817 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5818 : CODE_FOR_reload_indi_r1);
5822 /* Secondary reloads of symbolic operands require %r1 as a scratch
5823 register when we're generating PIC code and when the operand isn't
5825 if (symbolic_expression_p (x))
5827 if (GET_CODE (x) == HIGH)
5830 if (flag_pic || !read_only_operand (x, VOIDmode))
5832 gcc_assert (mode == SImode || mode == DImode);
5833 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5834 : CODE_FOR_reload_indi_r1);
5839 /* Profiling showed the PA port spends about 1.3% of its compilation
5840 time in true_regnum from calls inside pa_secondary_reload_class. */
5841 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5842 regno = true_regnum (x);
5844 /* In order to allow 14-bit displacements in integer loads and stores,
5845 we need to prevent reload from generating out of range integer mode
5846 loads and stores to the floating point registers. Previously, we
5847 used to call for a secondary reload and have emit_move_sequence()
5848 fix the instruction sequence. However, reload occasionally wouldn't
5849 generate the reload and we would end up with an invalid REG+D memory
5850 address. So, now we use an intermediate general register for most
5851 memory loads and stores. */
5852 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5853 && GET_MODE_CLASS (mode) == MODE_INT
5854 && FP_REG_CLASS_P (rclass))
5856 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5857 the secondary reload needed for a pseudo. It never passes a
5859 if (GET_CODE (x) == MEM)
5863 /* We don't need an intermediate for indexed and LO_SUM DLT
5864 memory addresses. When INT14_OK_STRICT is true, it might
5865 appear that we could directly allow register indirect
5866 memory addresses. However, this doesn't work because we
5867 don't support SUBREGs in floating-point register copies
5868 and reload doesn't tell us when it's going to use a SUBREG. */
5869 if (IS_INDEX_ADDR_P (x)
5870 || IS_LO_SUM_DLT_ADDR_P (x))
5873 /* Otherwise, we need an intermediate general register. */
5874 return GENERAL_REGS;
5877 /* Request a secondary reload with a general scratch register
5878 for everthing else. ??? Could symbolic operands be handled
5879 directly when generating non-pic PA 2.0 code? */
5881 ? direct_optab_handler (reload_in_optab, mode)
5882 : direct_optab_handler (reload_out_optab, mode));
5886 /* We need a secondary register (GPR) for copies between the SAR
5887 and anything other than a general register. */
5888 if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32))
5891 ? direct_optab_handler (reload_in_optab, mode)
5892 : direct_optab_handler (reload_out_optab, mode));
5896 /* A SAR<->FP register copy requires a secondary register (GPR) as
5897 well as secondary memory. */
5898 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5899 && (REGNO_REG_CLASS (regno) == SHIFT_REGS
5900 && FP_REG_CLASS_P (rclass)))
5902 ? direct_optab_handler (reload_in_optab, mode)
5903 : direct_optab_handler (reload_out_optab, mode));
5908 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5909 is only marked as live on entry by df-scan when it is a fixed
5910 register. It isn't a fixed register in the 64-bit runtime,
5911 so we need to mark it here. */
5914 pa_extra_live_on_entry (bitmap regs)
5917 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5920 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5921 to prevent it from being deleted. */
5924 pa_eh_return_handler_rtx (void)
5928 tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx,
5929 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5930 tmp = gen_rtx_MEM (word_mode, tmp);
5935 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5936 by invisible reference. As a GCC extension, we also pass anything
5937 with a zero or variable size by reference.
5939 The 64-bit runtime does not describe passing any types by invisible
5940 reference. The internals of GCC can't currently handle passing
5941 empty structures, and zero or variable length arrays when they are
5942 not passed entirely on the stack or by reference. Thus, as a GCC
5943 extension, we pass these types by reference. The HP compiler doesn't
5944 support these types, so hopefully there shouldn't be any compatibility
5945 issues. This may have to be revisited when HP releases a C99 compiler
5946 or updates the ABI. */
5949 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5950 enum machine_mode mode, const_tree type,
5951 bool named ATTRIBUTE_UNUSED)
5956 size = int_size_in_bytes (type);
5958 size = GET_MODE_SIZE (mode);
5963 return size <= 0 || size > 8;
5967 function_arg_padding (enum machine_mode mode, const_tree type)
5972 && (AGGREGATE_TYPE_P (type)
5973 || TREE_CODE (type) == COMPLEX_TYPE
5974 || TREE_CODE (type) == VECTOR_TYPE)))
5976 /* Return none if justification is not required. */
5978 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5979 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5982 /* The directions set here are ignored when a BLKmode argument larger
5983 than a word is placed in a register. Different code is used for
5984 the stack and registers. This makes it difficult to have a
5985 consistent data representation for both the stack and registers.
5986 For both runtimes, the justification and padding for arguments on
5987 the stack and in registers should be identical. */
5989 /* The 64-bit runtime specifies left justification for aggregates. */
5992 /* The 32-bit runtime architecture specifies right justification.
5993 When the argument is passed on the stack, the argument is padded
5994 with garbage on the left. The HP compiler pads with zeros. */
5998 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6005 /* Do what is necessary for `va_start'. We look at the current function
6006 to determine if stdargs or varargs is used and fill in an initial
6007 va_list. A pointer to this constructor is returned. */
6010 hppa_builtin_saveregs (void)
6013 tree fntype = TREE_TYPE (current_function_decl);
6014 int argadj = ((!stdarg_p (fntype))
6015 ? UNITS_PER_WORD : 0);
6018 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
6020 offset = crtl->args.arg_offset_rtx;
6026 /* Adjust for varargs/stdarg differences. */
6028 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
6030 offset = crtl->args.arg_offset_rtx;
6032 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6033 from the incoming arg pointer and growing to larger addresses. */
6034 for (i = 26, off = -64; i >= 19; i--, off += 8)
6035 emit_move_insn (gen_rtx_MEM (word_mode,
6036 plus_constant (arg_pointer_rtx, off)),
6037 gen_rtx_REG (word_mode, i));
6039 /* The incoming args pointer points just beyond the flushback area;
6040 normally this is not a serious concern. However, when we are doing
6041 varargs/stdargs we want to make the arg pointer point to the start
6042 of the incoming argument area. */
6043 emit_move_insn (virtual_incoming_args_rtx,
6044 plus_constant (arg_pointer_rtx, -64));
6046 /* Now return a pointer to the first anonymous argument. */
6047 return copy_to_reg (expand_binop (Pmode, add_optab,
6048 virtual_incoming_args_rtx,
6049 offset, 0, 0, OPTAB_LIB_WIDEN));
6052 /* Store general registers on the stack. */
6053 dest = gen_rtx_MEM (BLKmode,
6054 plus_constant (crtl->args.internal_arg_pointer,
6056 set_mem_alias_set (dest, get_varargs_alias_set ());
6057 set_mem_align (dest, BITS_PER_WORD);
6058 move_block_from_reg (23, dest, 4);
6060 /* move_block_from_reg will emit code to store the argument registers
6061 individually as scalar stores.
6063 However, other insns may later load from the same addresses for
6064 a structure load (passing a struct to a varargs routine).
6066 The alias code assumes that such aliasing can never happen, so we
6067 have to keep memory referencing insns from moving up beyond the
6068 last argument register store. So we emit a blockage insn here. */
6069 emit_insn (gen_blockage ());
6071 return copy_to_reg (expand_binop (Pmode, add_optab,
6072 crtl->args.internal_arg_pointer,
6073 offset, 0, 0, OPTAB_LIB_WIDEN));
6077 hppa_va_start (tree valist, rtx nextarg)
6079 nextarg = expand_builtin_saveregs ();
6080 std_expand_builtin_va_start (valist, nextarg);
6084 hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6089 /* Args grow upward. We can use the generic routines. */
6090 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6092 else /* !TARGET_64BIT */
6094 tree ptr = build_pointer_type (type);
6097 unsigned int size, ofs;
6100 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6104 ptr = build_pointer_type (type);
6106 size = int_size_in_bytes (type);
6107 valist_type = TREE_TYPE (valist);
6109 /* Args grow down. Not handled by generic routines. */
6111 u = fold_convert (sizetype, size_in_bytes (type));
6112 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6113 t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u);
6115 /* Align to 4 or 8 byte boundary depending on argument size. */
6117 u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4));
6118 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6119 t = fold_convert (valist_type, t);
6121 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6123 ofs = (8 - size) % 4;
6127 t = build2 (POINTER_PLUS_EXPR, valist_type, t, u);
6130 t = fold_convert (ptr, t);
6131 t = build_va_arg_indirect_ref (t);
6134 t = build_va_arg_indirect_ref (t);
6140 /* True if MODE is valid for the target. By "valid", we mean able to
6141 be manipulated in non-trivial ways. In particular, this means all
6142 the arithmetic is supported.
6144 Currently, TImode is not valid as the HP 64-bit runtime documentation
6145 doesn't document the alignment and calling conventions for this type.
6146 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6147 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6150 pa_scalar_mode_supported_p (enum machine_mode mode)
6152 int precision = GET_MODE_PRECISION (mode);
6154 switch (GET_MODE_CLASS (mode))
6156 case MODE_PARTIAL_INT:
6158 if (precision == CHAR_TYPE_SIZE)
6160 if (precision == SHORT_TYPE_SIZE)
6162 if (precision == INT_TYPE_SIZE)
6164 if (precision == LONG_TYPE_SIZE)
6166 if (precision == LONG_LONG_TYPE_SIZE)
6171 if (precision == FLOAT_TYPE_SIZE)
6173 if (precision == DOUBLE_TYPE_SIZE)
6175 if (precision == LONG_DOUBLE_TYPE_SIZE)
6179 case MODE_DECIMAL_FLOAT:
6187 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6188 it branches to the next real instruction. Otherwise, return FALSE. */
6191 branch_to_delay_slot_p (rtx insn)
6193 if (dbr_sequence_length ())
6196 return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn);
6199 /* Return TRUE if INSN, a jump insn, needs a nop in its delay slot.
6201 This occurs when INSN has an unfilled delay slot and is followed
6202 by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and
6203 the jump branches into the delay slot. So, we add a nop in the delay
6204 slot just to be safe. This messes up our instruction count, but we
6205 don't know how big the ASM_INPUT insn is anyway. */
6208 branch_needs_nop_p (rtx insn)
6212 if (dbr_sequence_length ())
6215 next_insn = next_real_insn (insn);
6216 return GET_CODE (PATTERN (next_insn)) == ASM_INPUT;
6219 /* This routine handles all the normal conditional branch sequences we
6220 might need to generate. It handles compare immediate vs compare
6221 register, nullification of delay slots, varying length branches,
6222 negated branches, and all combinations of the above. It returns the
6223 output appropriate to emit the branch corresponding to all given
6227 output_cbranch (rtx *operands, int negated, rtx insn)
6229 static char buf[100];
6231 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6232 int length = get_attr_length (insn);
6235 /* A conditional branch to the following instruction (e.g. the delay slot)
6236 is asking for a disaster. This can happen when not optimizing and
6237 when jump optimization fails.
6239 While it is usually safe to emit nothing, this can fail if the
6240 preceding instruction is a nullified branch with an empty delay
6241 slot and the same branch target as this branch. We could check
6242 for this but jump optimization should eliminate nop jumps. It
6243 is always safe to emit a nop. */
6244 if (branch_to_delay_slot_p (insn))
6247 /* The doubleword form of the cmpib instruction doesn't have the LEU
6248 and GTU conditions while the cmpb instruction does. Since we accept
6249 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6250 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6251 operands[2] = gen_rtx_REG (DImode, 0);
6252 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6253 operands[1] = gen_rtx_REG (DImode, 0);
6255 /* If this is a long branch with its delay slot unfilled, set `nullify'
6256 as it can nullify the delay slot and save a nop. */
6257 if (length == 8 && dbr_sequence_length () == 0)
6260 /* If this is a short forward conditional branch which did not get
6261 its delay slot filled, the delay slot can still be nullified. */
6262 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6263 nullify = forward_branch_p (insn);
6265 /* A forward branch over a single nullified insn can be done with a
6266 comclr instruction. This avoids a single cycle penalty due to
6267 mis-predicted branch if we fall through (branch not taken). */
6269 && next_real_insn (insn) != 0
6270 && get_attr_length (next_real_insn (insn)) == 4
6271 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6277 /* All short conditional branches except backwards with an unfilled
6281 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6283 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6284 if (GET_MODE (operands[1]) == DImode)
6287 strcat (buf, "%B3");
6289 strcat (buf, "%S3");
6291 strcat (buf, " %2,%r1,%%r0");
6294 if (branch_needs_nop_p (insn))
6295 strcat (buf, ",n %2,%r1,%0%#");
6297 strcat (buf, ",n %2,%r1,%0");
6300 strcat (buf, " %2,%r1,%0");
6303 /* All long conditionals. Note a short backward branch with an
6304 unfilled delay slot is treated just like a long backward branch
6305 with an unfilled delay slot. */
6307 /* Handle weird backwards branch with a filled delay slot
6308 which is nullified. */
6309 if (dbr_sequence_length () != 0
6310 && ! forward_branch_p (insn)
6313 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6314 if (GET_MODE (operands[1]) == DImode)
6317 strcat (buf, "%S3");
6319 strcat (buf, "%B3");
6320 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6322 /* Handle short backwards branch with an unfilled delay slot.
6323 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6324 taken and untaken branches. */
6325 else if (dbr_sequence_length () == 0
6326 && ! forward_branch_p (insn)
6327 && INSN_ADDRESSES_SET_P ()
6328 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6329 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6331 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6332 if (GET_MODE (operands[1]) == DImode)
6335 strcat (buf, "%B3 %2,%r1,%0%#");
6337 strcat (buf, "%S3 %2,%r1,%0%#");
6341 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6342 if (GET_MODE (operands[1]) == DImode)
6345 strcat (buf, "%S3");
6347 strcat (buf, "%B3");
6349 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6351 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6356 /* The reversed conditional branch must branch over one additional
6357 instruction if the delay slot is filled and needs to be extracted
6358 by output_lbranch. If the delay slot is empty or this is a
6359 nullified forward branch, the instruction after the reversed
6360 condition branch must be nullified. */
6361 if (dbr_sequence_length () == 0
6362 || (nullify && forward_branch_p (insn)))
6366 operands[4] = GEN_INT (length);
6371 operands[4] = GEN_INT (length + 4);
6374 /* Create a reversed conditional branch which branches around
6375 the following insns. */
6376 if (GET_MODE (operands[1]) != DImode)
6382 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6385 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6391 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6394 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6403 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6406 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6412 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6415 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6419 output_asm_insn (buf, operands);
6420 return output_lbranch (operands[0], insn, xdelay);
6425 /* This routine handles output of long unconditional branches that
6426 exceed the maximum range of a simple branch instruction. Since
6427 we don't have a register available for the branch, we save register
6428 %r1 in the frame marker, load the branch destination DEST into %r1,
6429 execute the branch, and restore %r1 in the delay slot of the branch.
6431 Since long branches may have an insn in the delay slot and the
6432 delay slot is used to restore %r1, we in general need to extract
6433 this insn and execute it before the branch. However, to facilitate
6434 use of this function by conditional branches, we also provide an
6435 option to not extract the delay insn so that it will be emitted
6436 after the long branch. So, if there is an insn in the delay slot,
6437 it is extracted if XDELAY is nonzero.
6439 The lengths of the various long-branch sequences are 20, 16 and 24
6440 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6443 output_lbranch (rtx dest, rtx insn, int xdelay)
6447 xoperands[0] = dest;
6449 /* First, free up the delay slot. */
6450 if (xdelay && dbr_sequence_length () != 0)
6452 /* We can't handle a jump in the delay slot. */
6453 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6455 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6458 /* Now delete the delay insn. */
6459 SET_INSN_DELETED (NEXT_INSN (insn));
6462 /* Output an insn to save %r1. The runtime documentation doesn't
6463 specify whether the "Clean Up" slot in the callers frame can
6464 be clobbered by the callee. It isn't copied by HP's builtin
6465 alloca, so this suggests that it can be clobbered if necessary.
6466 The "Static Link" location is copied by HP builtin alloca, so
6467 we avoid using it. Using the cleanup slot might be a problem
6468 if we have to interoperate with languages that pass cleanup
6469 information. However, it should be possible to handle these
6470 situations with GCC's asm feature.
6472 The "Current RP" slot is reserved for the called procedure, so
6473 we try to use it when we don't have a frame of our own. It's
6474 rather unlikely that we won't have a frame when we need to emit
6477 Really the way to go long term is a register scavenger; goto
6478 the target of the jump and find a register which we can use
6479 as a scratch to hold the value in %r1. Then, we wouldn't have
6480 to free up the delay slot or clobber a slot that may be needed
6481 for other purposes. */
6484 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6485 /* Use the return pointer slot in the frame marker. */
6486 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6488 /* Use the slot at -40 in the frame marker since HP builtin
6489 alloca doesn't copy it. */
6490 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6494 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6495 /* Use the return pointer slot in the frame marker. */
6496 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6498 /* Use the "Clean Up" slot in the frame marker. In GCC,
6499 the only other use of this location is for copying a
6500 floating point double argument from a floating-point
6501 register to two general registers. The copy is done
6502 as an "atomic" operation when outputting a call, so it
6503 won't interfere with our using the location here. */
6504 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6507 if (TARGET_PORTABLE_RUNTIME)
6509 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6510 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6511 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6515 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6516 if (TARGET_SOM || !TARGET_GAS)
6518 xoperands[1] = gen_label_rtx ();
6519 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6520 targetm.asm_out.internal_label (asm_out_file, "L",
6521 CODE_LABEL_NUMBER (xoperands[1]));
6522 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6526 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6527 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6529 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6532 /* Now output a very long branch to the original target. */
6533 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6535 /* Now restore the value of %r1 in the delay slot. */
6538 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6539 return "ldd -16(%%r30),%%r1";
6541 return "ldd -40(%%r30),%%r1";
6545 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6546 return "ldw -20(%%r30),%%r1";
6548 return "ldw -12(%%r30),%%r1";
6552 /* This routine handles all the branch-on-bit conditional branch sequences we
6553 might need to generate. It handles nullification of delay slots,
6554 varying length branches, negated branches and all combinations of the
6555 above. it returns the appropriate output template to emit the branch. */
6558 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6560 static char buf[100];
6562 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6563 int length = get_attr_length (insn);
6566 /* A conditional branch to the following instruction (e.g. the delay slot) is
6567 asking for a disaster. I do not think this can happen as this pattern
6568 is only used when optimizing; jump optimization should eliminate the
6569 jump. But be prepared just in case. */
6571 if (branch_to_delay_slot_p (insn))
6574 /* If this is a long branch with its delay slot unfilled, set `nullify'
6575 as it can nullify the delay slot and save a nop. */
6576 if (length == 8 && dbr_sequence_length () == 0)
6579 /* If this is a short forward conditional branch which did not get
6580 its delay slot filled, the delay slot can still be nullified. */
6581 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6582 nullify = forward_branch_p (insn);
6584 /* A forward branch over a single nullified insn can be done with a
6585 extrs instruction. This avoids a single cycle penalty due to
6586 mis-predicted branch if we fall through (branch not taken). */
6589 && next_real_insn (insn) != 0
6590 && get_attr_length (next_real_insn (insn)) == 4
6591 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6598 /* All short conditional branches except backwards with an unfilled
6602 strcpy (buf, "{extrs,|extrw,s,}");
6604 strcpy (buf, "bb,");
6605 if (useskip && GET_MODE (operands[0]) == DImode)
6606 strcpy (buf, "extrd,s,*");
6607 else if (GET_MODE (operands[0]) == DImode)
6608 strcpy (buf, "bb,*");
6609 if ((which == 0 && negated)
6610 || (which == 1 && ! negated))
6615 strcat (buf, " %0,%1,1,%%r0");
6616 else if (nullify && negated)
6618 if (branch_needs_nop_p (insn))
6619 strcat (buf, ",n %0,%1,%3%#");
6621 strcat (buf, ",n %0,%1,%3");
6623 else if (nullify && ! negated)
6625 if (branch_needs_nop_p (insn))
6626 strcat (buf, ",n %0,%1,%2%#");
6628 strcat (buf, ",n %0,%1,%2");
6630 else if (! nullify && negated)
6631 strcat (buf, " %0,%1,%3");
6632 else if (! nullify && ! negated)
6633 strcat (buf, " %0,%1,%2");
6636 /* All long conditionals. Note a short backward branch with an
6637 unfilled delay slot is treated just like a long backward branch
6638 with an unfilled delay slot. */
6640 /* Handle weird backwards branch with a filled delay slot
6641 which is nullified. */
6642 if (dbr_sequence_length () != 0
6643 && ! forward_branch_p (insn)
6646 strcpy (buf, "bb,");
6647 if (GET_MODE (operands[0]) == DImode)
6649 if ((which == 0 && negated)
6650 || (which == 1 && ! negated))
6655 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6657 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6659 /* Handle short backwards branch with an unfilled delay slot.
6660 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6661 taken and untaken branches. */
6662 else if (dbr_sequence_length () == 0
6663 && ! forward_branch_p (insn)
6664 && INSN_ADDRESSES_SET_P ()
6665 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6666 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6668 strcpy (buf, "bb,");
6669 if (GET_MODE (operands[0]) == DImode)
6671 if ((which == 0 && negated)
6672 || (which == 1 && ! negated))
6677 strcat (buf, " %0,%1,%3%#");
6679 strcat (buf, " %0,%1,%2%#");
6683 if (GET_MODE (operands[0]) == DImode)
6684 strcpy (buf, "extrd,s,*");
6686 strcpy (buf, "{extrs,|extrw,s,}");
6687 if ((which == 0 && negated)
6688 || (which == 1 && ! negated))
6692 if (nullify && negated)
6693 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6694 else if (nullify && ! negated)
6695 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6697 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6699 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6704 /* The reversed conditional branch must branch over one additional
6705 instruction if the delay slot is filled and needs to be extracted
6706 by output_lbranch. If the delay slot is empty or this is a
6707 nullified forward branch, the instruction after the reversed
6708 condition branch must be nullified. */
6709 if (dbr_sequence_length () == 0
6710 || (nullify && forward_branch_p (insn)))
6714 operands[4] = GEN_INT (length);
6719 operands[4] = GEN_INT (length + 4);
6722 if (GET_MODE (operands[0]) == DImode)
6723 strcpy (buf, "bb,*");
6725 strcpy (buf, "bb,");
6726 if ((which == 0 && negated)
6727 || (which == 1 && !negated))
6732 strcat (buf, ",n %0,%1,.+%4");
6734 strcat (buf, " %0,%1,.+%4");
6735 output_asm_insn (buf, operands);
6736 return output_lbranch (negated ? operands[3] : operands[2],
6742 /* This routine handles all the branch-on-variable-bit conditional branch
6743 sequences we might need to generate. It handles nullification of delay
6744 slots, varying length branches, negated branches and all combinations
6745 of the above. it returns the appropriate output template to emit the
6749 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6751 static char buf[100];
6753 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6754 int length = get_attr_length (insn);
6757 /* A conditional branch to the following instruction (e.g. the delay slot) is
6758 asking for a disaster. I do not think this can happen as this pattern
6759 is only used when optimizing; jump optimization should eliminate the
6760 jump. But be prepared just in case. */
6762 if (branch_to_delay_slot_p (insn))
6765 /* If this is a long branch with its delay slot unfilled, set `nullify'
6766 as it can nullify the delay slot and save a nop. */
6767 if (length == 8 && dbr_sequence_length () == 0)
6770 /* If this is a short forward conditional branch which did not get
6771 its delay slot filled, the delay slot can still be nullified. */
6772 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6773 nullify = forward_branch_p (insn);
6775 /* A forward branch over a single nullified insn can be done with a
6776 extrs instruction. This avoids a single cycle penalty due to
6777 mis-predicted branch if we fall through (branch not taken). */
6780 && next_real_insn (insn) != 0
6781 && get_attr_length (next_real_insn (insn)) == 4
6782 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6789 /* All short conditional branches except backwards with an unfilled
6793 strcpy (buf, "{vextrs,|extrw,s,}");
6795 strcpy (buf, "{bvb,|bb,}");
6796 if (useskip && GET_MODE (operands[0]) == DImode)
6797 strcpy (buf, "extrd,s,*");
6798 else if (GET_MODE (operands[0]) == DImode)
6799 strcpy (buf, "bb,*");
6800 if ((which == 0 && negated)
6801 || (which == 1 && ! negated))
6806 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6807 else if (nullify && negated)
6809 if (branch_needs_nop_p (insn))
6810 strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
6812 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6814 else if (nullify && ! negated)
6816 if (branch_needs_nop_p (insn))
6817 strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
6819 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6821 else if (! nullify && negated)
6822 strcat (buf, "{ %0,%3| %0,%%sar,%3}");
6823 else if (! nullify && ! negated)
6824 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6827 /* All long conditionals. Note a short backward branch with an
6828 unfilled delay slot is treated just like a long backward branch
6829 with an unfilled delay slot. */
6831 /* Handle weird backwards branch with a filled delay slot
6832 which is nullified. */
6833 if (dbr_sequence_length () != 0
6834 && ! forward_branch_p (insn)
6837 strcpy (buf, "{bvb,|bb,}");
6838 if (GET_MODE (operands[0]) == DImode)
6840 if ((which == 0 && negated)
6841 || (which == 1 && ! negated))
6846 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6848 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6850 /* Handle short backwards branch with an unfilled delay slot.
6851 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6852 taken and untaken branches. */
6853 else if (dbr_sequence_length () == 0
6854 && ! forward_branch_p (insn)
6855 && INSN_ADDRESSES_SET_P ()
6856 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6857 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6859 strcpy (buf, "{bvb,|bb,}");
6860 if (GET_MODE (operands[0]) == DImode)
6862 if ((which == 0 && negated)
6863 || (which == 1 && ! negated))
6868 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6870 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6874 strcpy (buf, "{vextrs,|extrw,s,}");
6875 if (GET_MODE (operands[0]) == DImode)
6876 strcpy (buf, "extrd,s,*");
6877 if ((which == 0 && negated)
6878 || (which == 1 && ! negated))
6882 if (nullify && negated)
6883 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6884 else if (nullify && ! negated)
6885 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6887 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6889 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6894 /* The reversed conditional branch must branch over one additional
6895 instruction if the delay slot is filled and needs to be extracted
6896 by output_lbranch. If the delay slot is empty or this is a
6897 nullified forward branch, the instruction after the reversed
6898 condition branch must be nullified. */
6899 if (dbr_sequence_length () == 0
6900 || (nullify && forward_branch_p (insn)))
6904 operands[4] = GEN_INT (length);
6909 operands[4] = GEN_INT (length + 4);
6912 if (GET_MODE (operands[0]) == DImode)
6913 strcpy (buf, "bb,*");
6915 strcpy (buf, "{bvb,|bb,}");
6916 if ((which == 0 && negated)
6917 || (which == 1 && !negated))
6922 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6924 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6925 output_asm_insn (buf, operands);
6926 return output_lbranch (negated ? operands[3] : operands[2],
6932 /* Return the output template for emitting a dbra type insn.
6934 Note it may perform some output operations on its own before
6935 returning the final output string. */
6937 output_dbra (rtx *operands, rtx insn, int which_alternative)
6939 int length = get_attr_length (insn);
6941 /* A conditional branch to the following instruction (e.g. the delay slot) is
6942 asking for a disaster. Be prepared! */
6944 if (branch_to_delay_slot_p (insn))
6946 if (which_alternative == 0)
6947 return "ldo %1(%0),%0";
6948 else if (which_alternative == 1)
6950 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6951 output_asm_insn ("ldw -16(%%r30),%4", operands);
6952 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6953 return "{fldws|fldw} -16(%%r30),%0";
6957 output_asm_insn ("ldw %0,%4", operands);
6958 return "ldo %1(%4),%4\n\tstw %4,%0";
6962 if (which_alternative == 0)
6964 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6967 /* If this is a long branch with its delay slot unfilled, set `nullify'
6968 as it can nullify the delay slot and save a nop. */
6969 if (length == 8 && dbr_sequence_length () == 0)
6972 /* If this is a short forward conditional branch which did not get
6973 its delay slot filled, the delay slot can still be nullified. */
6974 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6975 nullify = forward_branch_p (insn);
6982 if (branch_needs_nop_p (insn))
6983 return "addib,%C2,n %1,%0,%3%#";
6985 return "addib,%C2,n %1,%0,%3";
6988 return "addib,%C2 %1,%0,%3";
6991 /* Handle weird backwards branch with a fulled delay slot
6992 which is nullified. */
6993 if (dbr_sequence_length () != 0
6994 && ! forward_branch_p (insn)
6996 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6997 /* Handle short backwards branch with an unfilled delay slot.
6998 Using a addb;nop rather than addi;bl saves 1 cycle for both
6999 taken and untaken branches. */
7000 else if (dbr_sequence_length () == 0
7001 && ! forward_branch_p (insn)
7002 && INSN_ADDRESSES_SET_P ()
7003 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7004 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7005 return "addib,%C2 %1,%0,%3%#";
7007 /* Handle normal cases. */
7009 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7011 return "addi,%N2 %1,%0,%0\n\tb %3";
7014 /* The reversed conditional branch must branch over one additional
7015 instruction if the delay slot is filled and needs to be extracted
7016 by output_lbranch. If the delay slot is empty or this is a
7017 nullified forward branch, the instruction after the reversed
7018 condition branch must be nullified. */
7019 if (dbr_sequence_length () == 0
7020 || (nullify && forward_branch_p (insn)))
7024 operands[4] = GEN_INT (length);
7029 operands[4] = GEN_INT (length + 4);
7033 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
7035 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
7037 return output_lbranch (operands[3], insn, xdelay);
7041 /* Deal with gross reload from FP register case. */
7042 else if (which_alternative == 1)
7044 /* Move loop counter from FP register to MEM then into a GR,
7045 increment the GR, store the GR into MEM, and finally reload
7046 the FP register from MEM from within the branch's delay slot. */
7047 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7049 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7051 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7052 else if (length == 28)
7053 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7056 operands[5] = GEN_INT (length - 16);
7057 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
7058 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7059 return output_lbranch (operands[3], insn, 0);
7062 /* Deal with gross reload from memory case. */
7065 /* Reload loop counter from memory, the store back to memory
7066 happens in the branch's delay slot. */
7067 output_asm_insn ("ldw %0,%4", operands);
7069 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7070 else if (length == 16)
7071 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7074 operands[5] = GEN_INT (length - 4);
7075 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
7076 return output_lbranch (operands[3], insn, 0);
7081 /* Return the output template for emitting a movb type insn.
7083 Note it may perform some output operations on its own before
7084 returning the final output string. */
7086 output_movb (rtx *operands, rtx insn, int which_alternative,
7087 int reverse_comparison)
7089 int length = get_attr_length (insn);
7091 /* A conditional branch to the following instruction (e.g. the delay slot) is
7092 asking for a disaster. Be prepared! */
7094 if (branch_to_delay_slot_p (insn))
7096 if (which_alternative == 0)
7097 return "copy %1,%0";
7098 else if (which_alternative == 1)
7100 output_asm_insn ("stw %1,-16(%%r30)", operands);
7101 return "{fldws|fldw} -16(%%r30),%0";
7103 else if (which_alternative == 2)
7109 /* Support the second variant. */
7110 if (reverse_comparison)
7111 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7113 if (which_alternative == 0)
7115 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7118 /* If this is a long branch with its delay slot unfilled, set `nullify'
7119 as it can nullify the delay slot and save a nop. */
7120 if (length == 8 && dbr_sequence_length () == 0)
7123 /* If this is a short forward conditional branch which did not get
7124 its delay slot filled, the delay slot can still be nullified. */
7125 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7126 nullify = forward_branch_p (insn);
7133 if (branch_needs_nop_p (insn))
7134 return "movb,%C2,n %1,%0,%3%#";
7136 return "movb,%C2,n %1,%0,%3";
7139 return "movb,%C2 %1,%0,%3";
7142 /* Handle weird backwards branch with a filled delay slot
7143 which is nullified. */
7144 if (dbr_sequence_length () != 0
7145 && ! forward_branch_p (insn)
7147 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7149 /* Handle short backwards branch with an unfilled delay slot.
7150 Using a movb;nop rather than or;bl saves 1 cycle for both
7151 taken and untaken branches. */
7152 else if (dbr_sequence_length () == 0
7153 && ! forward_branch_p (insn)
7154 && INSN_ADDRESSES_SET_P ()
7155 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7156 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7157 return "movb,%C2 %1,%0,%3%#";
7158 /* Handle normal cases. */
7160 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7162 return "or,%N2 %1,%%r0,%0\n\tb %3";
7165 /* The reversed conditional branch must branch over one additional
7166 instruction if the delay slot is filled and needs to be extracted
7167 by output_lbranch. If the delay slot is empty or this is a
7168 nullified forward branch, the instruction after the reversed
7169 condition branch must be nullified. */
7170 if (dbr_sequence_length () == 0
7171 || (nullify && forward_branch_p (insn)))
7175 operands[4] = GEN_INT (length);
7180 operands[4] = GEN_INT (length + 4);
7184 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7186 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7188 return output_lbranch (operands[3], insn, xdelay);
7191 /* Deal with gross reload for FP destination register case. */
7192 else if (which_alternative == 1)
7194 /* Move source register to MEM, perform the branch test, then
7195 finally load the FP register from MEM from within the branch's
7197 output_asm_insn ("stw %1,-16(%%r30)", operands);
7199 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7200 else if (length == 16)
7201 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7204 operands[4] = GEN_INT (length - 4);
7205 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7206 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7207 return output_lbranch (operands[3], insn, 0);
7210 /* Deal with gross reload from memory case. */
7211 else if (which_alternative == 2)
7213 /* Reload loop counter from memory, the store back to memory
7214 happens in the branch's delay slot. */
7216 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7217 else if (length == 12)
7218 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7221 operands[4] = GEN_INT (length);
7222 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7224 return output_lbranch (operands[3], insn, 0);
7227 /* Handle SAR as a destination. */
7231 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7232 else if (length == 12)
7233 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7236 operands[4] = GEN_INT (length);
7237 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7239 return output_lbranch (operands[3], insn, 0);
7244 /* Copy any FP arguments in INSN into integer registers. */
7246 copy_fp_args (rtx insn)
7251 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7253 int arg_mode, regno;
7254 rtx use = XEXP (link, 0);
7256 if (! (GET_CODE (use) == USE
7257 && GET_CODE (XEXP (use, 0)) == REG
7258 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7261 arg_mode = GET_MODE (XEXP (use, 0));
7262 regno = REGNO (XEXP (use, 0));
7264 /* Is it a floating point register? */
7265 if (regno >= 32 && regno <= 39)
7267 /* Copy the FP register into an integer register via memory. */
7268 if (arg_mode == SFmode)
7270 xoperands[0] = XEXP (use, 0);
7271 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7272 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7273 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7277 xoperands[0] = XEXP (use, 0);
7278 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7279 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7280 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7281 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7287 /* Compute length of the FP argument copy sequence for INSN. */
7289 length_fp_args (rtx insn)
7294 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7296 int arg_mode, regno;
7297 rtx use = XEXP (link, 0);
7299 if (! (GET_CODE (use) == USE
7300 && GET_CODE (XEXP (use, 0)) == REG
7301 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7304 arg_mode = GET_MODE (XEXP (use, 0));
7305 regno = REGNO (XEXP (use, 0));
7307 /* Is it a floating point register? */
7308 if (regno >= 32 && regno <= 39)
7310 if (arg_mode == SFmode)
7320 /* Return the attribute length for the millicode call instruction INSN.
7321 The length must match the code generated by output_millicode_call.
7322 We include the delay slot in the returned length as it is better to
7323 over estimate the length than to under estimate it. */
7326 attr_length_millicode_call (rtx insn)
7328 unsigned long distance = -1;
7329 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7331 if (INSN_ADDRESSES_SET_P ())
7333 distance = (total + insn_current_reference_address (insn));
7334 if (distance < total)
7340 if (!TARGET_LONG_CALLS && distance < 7600000)
7345 else if (TARGET_PORTABLE_RUNTIME)
7349 if (!TARGET_LONG_CALLS && distance < 240000)
7352 if (TARGET_LONG_ABS_CALL && !flag_pic)
7359 /* INSN is a function call. It may have an unconditional jump
7362 CALL_DEST is the routine we are calling. */
7365 output_millicode_call (rtx insn, rtx call_dest)
7367 int attr_length = get_attr_length (insn);
7368 int seq_length = dbr_sequence_length ();
7373 xoperands[0] = call_dest;
7374 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7376 /* Handle the common case where we are sure that the branch will
7377 reach the beginning of the $CODE$ subspace. The within reach
7378 form of the $$sh_func_adrs call has a length of 28. Because
7379 it has an attribute type of multi, it never has a nonzero
7380 sequence length. The length of the $$sh_func_adrs is the same
7381 as certain out of reach PIC calls to other routines. */
7382 if (!TARGET_LONG_CALLS
7383 && ((seq_length == 0
7384 && (attr_length == 12
7385 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7386 || (seq_length != 0 && attr_length == 8)))
7388 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7394 /* It might seem that one insn could be saved by accessing
7395 the millicode function using the linkage table. However,
7396 this doesn't work in shared libraries and other dynamically
7397 loaded objects. Using a pc-relative sequence also avoids
7398 problems related to the implicit use of the gp register. */
7399 output_asm_insn ("b,l .+8,%%r1", xoperands);
7403 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7404 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7408 xoperands[1] = gen_label_rtx ();
7409 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7410 targetm.asm_out.internal_label (asm_out_file, "L",
7411 CODE_LABEL_NUMBER (xoperands[1]));
7412 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7415 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7417 else if (TARGET_PORTABLE_RUNTIME)
7419 /* Pure portable runtime doesn't allow be/ble; we also don't
7420 have PIC support in the assembler/linker, so this sequence
7423 /* Get the address of our target into %r1. */
7424 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7425 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7427 /* Get our return address into %r31. */
7428 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7429 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7431 /* Jump to our target address in %r1. */
7432 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7436 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7438 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7440 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7444 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7445 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7447 if (TARGET_SOM || !TARGET_GAS)
7449 /* The HP assembler can generate relocations for the
7450 difference of two symbols. GAS can do this for a
7451 millicode symbol but not an arbitrary external
7452 symbol when generating SOM output. */
7453 xoperands[1] = gen_label_rtx ();
7454 targetm.asm_out.internal_label (asm_out_file, "L",
7455 CODE_LABEL_NUMBER (xoperands[1]));
7456 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7457 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7461 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7462 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7466 /* Jump to our target address in %r1. */
7467 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7471 if (seq_length == 0)
7472 output_asm_insn ("nop", xoperands);
7474 /* We are done if there isn't a jump in the delay slot. */
7475 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7478 /* This call has an unconditional jump in its delay slot. */
7479 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7481 /* See if the return address can be adjusted. Use the containing
7482 sequence insn's address. */
7483 if (INSN_ADDRESSES_SET_P ())
7485 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7486 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7487 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7489 if (VAL_14_BITS_P (distance))
7491 xoperands[1] = gen_label_rtx ();
7492 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7493 targetm.asm_out.internal_label (asm_out_file, "L",
7494 CODE_LABEL_NUMBER (xoperands[1]));
7497 /* ??? This branch may not reach its target. */
7498 output_asm_insn ("nop\n\tb,n %0", xoperands);
7501 /* ??? This branch may not reach its target. */
7502 output_asm_insn ("nop\n\tb,n %0", xoperands);
7504 /* Delete the jump. */
7505 SET_INSN_DELETED (NEXT_INSN (insn));
7510 /* Return the attribute length of the call instruction INSN. The SIBCALL
7511 flag indicates whether INSN is a regular call or a sibling call. The
7512 length returned must be longer than the code actually generated by
7513 output_call. Since branch shortening is done before delay branch
7514 sequencing, there is no way to determine whether or not the delay
7515 slot will be filled during branch shortening. Even when the delay
7516 slot is filled, we may have to add a nop if the delay slot contains
7517 a branch that can't reach its target. Thus, we always have to include
7518 the delay slot in the length estimate. This used to be done in
7519 pa_adjust_insn_length but we do it here now as some sequences always
7520 fill the delay slot and we can save four bytes in the estimate for
7524 attr_length_call (rtx insn, int sibcall)
7527 rtx call, call_dest;
7530 rtx pat = PATTERN (insn);
7531 unsigned long distance = -1;
7533 gcc_assert (GET_CODE (insn) == CALL_INSN);
7535 if (INSN_ADDRESSES_SET_P ())
7537 unsigned long total;
7539 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7540 distance = (total + insn_current_reference_address (insn));
7541 if (distance < total)
7545 gcc_assert (GET_CODE (pat) == PARALLEL);
7547 /* Get the call rtx. */
7548 call = XVECEXP (pat, 0, 0);
7549 if (GET_CODE (call) == SET)
7550 call = SET_SRC (call);
7552 gcc_assert (GET_CODE (call) == CALL);
7554 /* Determine if this is a local call. */
7555 call_dest = XEXP (XEXP (call, 0), 0);
7556 call_decl = SYMBOL_REF_DECL (call_dest);
7557 local_call = call_decl && targetm.binds_local_p (call_decl);
7559 /* pc-relative branch. */
7560 if (!TARGET_LONG_CALLS
7561 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7562 || distance < 240000))
7565 /* 64-bit plabel sequence. */
7566 else if (TARGET_64BIT && !local_call)
7567 length += sibcall ? 28 : 24;
7569 /* non-pic long absolute branch sequence. */
7570 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7573 /* long pc-relative branch sequence. */
7574 else if (TARGET_LONG_PIC_SDIFF_CALL
7575 || (TARGET_GAS && !TARGET_SOM
7576 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7580 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7584 /* 32-bit plabel sequence. */
7590 length += length_fp_args (insn);
7600 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7608 /* INSN is a function call. It may have an unconditional jump
7611 CALL_DEST is the routine we are calling. */
7614 output_call (rtx insn, rtx call_dest, int sibcall)
7616 int delay_insn_deleted = 0;
7617 int delay_slot_filled = 0;
7618 int seq_length = dbr_sequence_length ();
7619 tree call_decl = SYMBOL_REF_DECL (call_dest);
7620 int local_call = call_decl && targetm.binds_local_p (call_decl);
7623 xoperands[0] = call_dest;
7625 /* Handle the common case where we're sure that the branch will reach
7626 the beginning of the "$CODE$" subspace. This is the beginning of
7627 the current function if we are in a named section. */
7628 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7630 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7631 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7635 if (TARGET_64BIT && !local_call)
7637 /* ??? As far as I can tell, the HP linker doesn't support the
7638 long pc-relative sequence described in the 64-bit runtime
7639 architecture. So, we use a slightly longer indirect call. */
7640 xoperands[0] = get_deferred_plabel (call_dest);
7641 xoperands[1] = gen_label_rtx ();
7643 /* If this isn't a sibcall, we put the load of %r27 into the
7644 delay slot. We can't do this in a sibcall as we don't
7645 have a second call-clobbered scratch register available. */
7647 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7650 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7653 /* Now delete the delay insn. */
7654 SET_INSN_DELETED (NEXT_INSN (insn));
7655 delay_insn_deleted = 1;
7658 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7659 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7660 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7664 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7665 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7666 output_asm_insn ("bve (%%r1)", xoperands);
7670 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7671 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7672 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7673 delay_slot_filled = 1;
7678 int indirect_call = 0;
7680 /* Emit a long call. There are several different sequences
7681 of increasing length and complexity. In most cases,
7682 they don't allow an instruction in the delay slot. */
7683 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7684 && !TARGET_LONG_PIC_SDIFF_CALL
7685 && !(TARGET_GAS && !TARGET_SOM
7686 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7691 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7695 || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)))
7697 /* A non-jump insn in the delay slot. By definition we can
7698 emit this insn before the call (and in fact before argument
7700 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7703 /* Now delete the delay insn. */
7704 SET_INSN_DELETED (NEXT_INSN (insn));
7705 delay_insn_deleted = 1;
7708 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7710 /* This is the best sequence for making long calls in
7711 non-pic code. Unfortunately, GNU ld doesn't provide
7712 the stub needed for external calls, and GAS's support
7713 for this with the SOM linker is buggy. It is safe
7714 to use this for local calls. */
7715 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7717 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7721 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7724 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7726 output_asm_insn ("copy %%r31,%%r2", xoperands);
7727 delay_slot_filled = 1;
7732 if (TARGET_LONG_PIC_SDIFF_CALL)
7734 /* The HP assembler and linker can handle relocations
7735 for the difference of two symbols. The HP assembler
7736 recognizes the sequence as a pc-relative call and
7737 the linker provides stubs when needed. */
7738 xoperands[1] = gen_label_rtx ();
7739 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7740 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7741 targetm.asm_out.internal_label (asm_out_file, "L",
7742 CODE_LABEL_NUMBER (xoperands[1]));
7743 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7745 else if (TARGET_GAS && !TARGET_SOM
7746 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7748 /* GAS currently can't generate the relocations that
7749 are needed for the SOM linker under HP-UX using this
7750 sequence. The GNU linker doesn't generate the stubs
7751 that are needed for external calls on TARGET_ELF32
7752 with this sequence. For now, we have to use a
7753 longer plabel sequence when using GAS. */
7754 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7755 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7757 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7762 /* Emit a long plabel-based call sequence. This is
7763 essentially an inline implementation of $$dyncall.
7764 We don't actually try to call $$dyncall as this is
7765 as difficult as calling the function itself. */
7766 xoperands[0] = get_deferred_plabel (call_dest);
7767 xoperands[1] = gen_label_rtx ();
7769 /* Since the call is indirect, FP arguments in registers
7770 need to be copied to the general registers. Then, the
7771 argument relocation stub will copy them back. */
7773 copy_fp_args (insn);
7777 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7778 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7779 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7783 output_asm_insn ("addil LR'%0-$global$,%%r27",
7785 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7789 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7790 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7791 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7792 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7794 if (!sibcall && !TARGET_PA_20)
7796 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7797 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7798 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7800 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7807 output_asm_insn ("bve (%%r1)", xoperands);
7812 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7813 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7814 delay_slot_filled = 1;
7817 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7822 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7823 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7828 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7829 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7831 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7835 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7836 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7838 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7841 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7843 output_asm_insn ("copy %%r31,%%r2", xoperands);
7844 delay_slot_filled = 1;
7851 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7852 output_asm_insn ("nop", xoperands);
7854 /* We are done if there isn't a jump in the delay slot. */
7856 || delay_insn_deleted
7857 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7860 /* A sibcall should never have a branch in the delay slot. */
7861 gcc_assert (!sibcall);
7863 /* This call has an unconditional jump in its delay slot. */
7864 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7866 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7868 /* See if the return address can be adjusted. Use the containing
7869 sequence insn's address. This would break the regular call/return@
7870 relationship assumed by the table based eh unwinder, so only do that
7871 if the call is not possibly throwing. */
7872 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7873 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7874 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7876 if (VAL_14_BITS_P (distance)
7877 && !(can_throw_internal (insn) || can_throw_external (insn)))
7879 xoperands[1] = gen_label_rtx ();
7880 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7881 targetm.asm_out.internal_label (asm_out_file, "L",
7882 CODE_LABEL_NUMBER (xoperands[1]));
7885 output_asm_insn ("nop\n\tb,n %0", xoperands);
7888 output_asm_insn ("b,n %0", xoperands);
7890 /* Delete the jump. */
7891 SET_INSN_DELETED (NEXT_INSN (insn));
7896 /* Return the attribute length of the indirect call instruction INSN.
7897 The length must match the code generated by output_indirect call.
7898 The returned length includes the delay slot. Currently, the delay
7899 slot of an indirect call sequence is not exposed and it is used by
7900 the sequence itself. */
7903 attr_length_indirect_call (rtx insn)
7905 unsigned long distance = -1;
7906 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7908 if (INSN_ADDRESSES_SET_P ())
7910 distance = (total + insn_current_reference_address (insn));
7911 if (distance < total)
7918 if (TARGET_FAST_INDIRECT_CALLS
7919 || (!TARGET_PORTABLE_RUNTIME
7920 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7921 || distance < 240000)))
7927 if (TARGET_PORTABLE_RUNTIME)
7930 /* Out of reach, can use ble. */
7935 output_indirect_call (rtx insn, rtx call_dest)
7941 xoperands[0] = call_dest;
7942 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7943 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7947 /* First the special case for kernels, level 0 systems, etc. */
7948 if (TARGET_FAST_INDIRECT_CALLS)
7949 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7951 /* Now the normal case -- we can reach $$dyncall directly or
7952 we're sure that we can get there via a long-branch stub.
7954 No need to check target flags as the length uniquely identifies
7955 the remaining cases. */
7956 if (attr_length_indirect_call (insn) == 8)
7958 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7959 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7960 variant of the B,L instruction can't be used on the SOM target. */
7961 if (TARGET_PA_20 && !TARGET_SOM)
7962 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7964 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7967 /* Long millicode call, but we are not generating PIC or portable runtime
7969 if (attr_length_indirect_call (insn) == 12)
7970 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7972 /* Long millicode call for portable runtime. */
7973 if (attr_length_indirect_call (insn) == 20)
7974 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7976 /* We need a long PIC call to $$dyncall. */
7977 xoperands[0] = NULL_RTX;
7978 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7979 if (TARGET_SOM || !TARGET_GAS)
7981 xoperands[0] = gen_label_rtx ();
7982 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7983 targetm.asm_out.internal_label (asm_out_file, "L",
7984 CODE_LABEL_NUMBER (xoperands[0]));
7985 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7989 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7990 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7993 output_asm_insn ("blr %%r0,%%r2", xoperands);
7994 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7998 /* Return the total length of the save and restore instructions needed for
7999 the data linkage table pointer (i.e., the PIC register) across the call
8000 instruction INSN. No-return calls do not require a save and restore.
8001 In addition, we may be able to avoid the save and restore for calls
8002 within the same translation unit. */
8005 attr_length_save_restore_dltp (rtx insn)
8007 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
8013 /* In HPUX 8.0's shared library scheme, special relocations are needed
8014 for function labels if they might be passed to a function
8015 in a shared library (because shared libraries don't live in code
8016 space), and special magic is needed to construct their address. */
8019 hppa_encode_label (rtx sym)
8021 const char *str = XSTR (sym, 0);
8022 int len = strlen (str) + 1;
8025 p = newstr = XALLOCAVEC (char, len + 1);
8029 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
8033 pa_encode_section_info (tree decl, rtx rtl, int first)
8035 int old_referenced = 0;
8037 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
8039 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
8041 default_encode_section_info (decl, rtl, first);
8043 if (first && TEXT_SPACE_P (decl))
8045 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
8046 if (TREE_CODE (decl) == FUNCTION_DECL)
8047 hppa_encode_label (XEXP (rtl, 0));
8049 else if (old_referenced)
8050 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
8053 /* This is sort of inverse to pa_encode_section_info. */
8056 pa_strip_name_encoding (const char *str)
8058 str += (*str == '@');
8059 str += (*str == '*');
8064 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8066 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
8069 /* Returns 1 if OP is a function label involved in a simple addition
8070 with a constant. Used to keep certain patterns from matching
8071 during instruction combination. */
8073 is_function_label_plus_const (rtx op)
8075 /* Strip off any CONST. */
8076 if (GET_CODE (op) == CONST)
8079 return (GET_CODE (op) == PLUS
8080 && function_label_operand (XEXP (op, 0), Pmode)
8081 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8084 /* Output assembly code for a thunk to FUNCTION. */
8087 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
8088 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8091 static unsigned int current_thunk_number;
8092 int val_14 = VAL_14_BITS_P (delta);
8093 unsigned int old_last_address = last_address, nbytes = 0;
8097 xoperands[0] = XEXP (DECL_RTL (function), 0);
8098 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
8099 xoperands[2] = GEN_INT (delta);
8101 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
8102 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
8104 /* Output the thunk. We know that the function is in the same
8105 translation unit (i.e., the same space) as the thunk, and that
8106 thunks are output after their method. Thus, we don't need an
8107 external branch to reach the function. With SOM and GAS,
8108 functions and thunks are effectively in different sections.
8109 Thus, we can always use a IA-relative branch and the linker
8110 will add a long branch stub if necessary.
8112 However, we have to be careful when generating PIC code on the
8113 SOM port to ensure that the sequence does not transfer to an
8114 import stub for the target function as this could clobber the
8115 return value saved at SP-24. This would also apply to the
8116 32-bit linux port if the multi-space model is implemented. */
8117 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8118 && !(flag_pic && TREE_PUBLIC (function))
8119 && (TARGET_GAS || last_address < 262132))
8120 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8121 && ((targetm.have_named_sections
8122 && DECL_SECTION_NAME (thunk_fndecl) != NULL
8123 /* The GNU 64-bit linker has rather poor stub management.
8124 So, we use a long branch from thunks that aren't in
8125 the same section as the target function. */
8127 && (DECL_SECTION_NAME (thunk_fndecl)
8128 != DECL_SECTION_NAME (function)))
8129 || ((DECL_SECTION_NAME (thunk_fndecl)
8130 == DECL_SECTION_NAME (function))
8131 && last_address < 262132)))
8132 || (targetm.have_named_sections
8133 && DECL_SECTION_NAME (thunk_fndecl) == NULL
8134 && DECL_SECTION_NAME (function) == NULL
8135 && last_address < 262132)
8136 || (!targetm.have_named_sections && last_address < 262132))))
8139 output_asm_insn ("addil L'%2,%%r26", xoperands);
8141 output_asm_insn ("b %0", xoperands);
8145 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8150 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8154 else if (TARGET_64BIT)
8156 /* We only have one call-clobbered scratch register, so we can't
8157 make use of the delay slot if delta doesn't fit in 14 bits. */
8160 output_asm_insn ("addil L'%2,%%r26", xoperands);
8161 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8164 output_asm_insn ("b,l .+8,%%r1", xoperands);
8168 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8169 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8173 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8174 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8179 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8180 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8185 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8189 else if (TARGET_PORTABLE_RUNTIME)
8191 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8192 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8195 output_asm_insn ("addil L'%2,%%r26", xoperands);
8197 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8201 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8206 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8210 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8212 /* The function is accessible from outside this module. The only
8213 way to avoid an import stub between the thunk and function is to
8214 call the function directly with an indirect sequence similar to
8215 that used by $$dyncall. This is possible because $$dyncall acts
8216 as the import stub in an indirect call. */
8217 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8218 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8219 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8220 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8221 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8222 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8223 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8224 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8225 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8229 output_asm_insn ("addil L'%2,%%r26", xoperands);
8235 output_asm_insn ("bve (%%r22)", xoperands);
8238 else if (TARGET_NO_SPACE_REGS)
8240 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8245 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8246 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8247 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8252 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8254 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8258 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8260 if (TARGET_SOM || !TARGET_GAS)
8262 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8263 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8267 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8268 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8272 output_asm_insn ("addil L'%2,%%r26", xoperands);
8274 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8278 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8283 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8290 output_asm_insn ("addil L'%2,%%r26", xoperands);
8292 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8293 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8297 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8302 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8307 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8309 if (TARGET_SOM && TARGET_GAS)
8311 /* We done with this subspace except possibly for some additional
8312 debug information. Forget that we are in this subspace to ensure
8313 that the next function is output in its own subspace. */
8315 cfun->machine->in_nsubspa = 2;
8318 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8320 switch_to_section (data_section);
8321 output_asm_insn (".align 4", xoperands);
8322 ASM_OUTPUT_LABEL (file, label);
8323 output_asm_insn (".word P'%0", xoperands);
8326 current_thunk_number++;
8327 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8328 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8329 last_address += nbytes;
8330 if (old_last_address > last_address)
8331 last_address = UINT_MAX;
8332 update_total_code_bytes (nbytes);
8335 /* Only direct calls to static functions are allowed to be sibling (tail)
8338 This restriction is necessary because some linker generated stubs will
8339 store return pointers into rp' in some cases which might clobber a
8340 live value already in rp'.
8342 In a sibcall the current function and the target function share stack
8343 space. Thus if the path to the current function and the path to the
8344 target function save a value in rp', they save the value into the
8345 same stack slot, which has undesirable consequences.
8347 Because of the deferred binding nature of shared libraries any function
8348 with external scope could be in a different load module and thus require
8349 rp' to be saved when calling that function. So sibcall optimizations
8350 can only be safe for static function.
8352 Note that GCC never needs return value relocations, so we don't have to
8353 worry about static calls with return value relocations (which require
8356 It is safe to perform a sibcall optimization when the target function
8357 will never return. */
8359 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8361 if (TARGET_PORTABLE_RUNTIME)
8364 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8365 single subspace mode and the call is not indirect. As far as I know,
8366 there is no operating system support for the multiple subspace mode.
8367 It might be possible to support indirect calls if we didn't use
8368 $$dyncall (see the indirect sequence generated in output_call). */
8370 return (decl != NULL_TREE);
8372 /* Sibcalls are not ok because the arg pointer register is not a fixed
8373 register. This prevents the sibcall optimization from occurring. In
8374 addition, there are problems with stub placement using GNU ld. This
8375 is because a normal sibcall branch uses a 17-bit relocation while
8376 a regular call branch uses a 22-bit relocation. As a result, more
8377 care needs to be taken in the placement of long-branch stubs. */
8381 /* Sibcalls are only ok within a translation unit. */
8382 return (decl && !TREE_PUBLIC (decl));
8385 /* ??? Addition is not commutative on the PA due to the weird implicit
8386 space register selection rules for memory addresses. Therefore, we
8387 don't consider a + b == b + a, as this might be inside a MEM. */
8389 pa_commutative_p (const_rtx x, int outer_code)
8391 return (COMMUTATIVE_P (x)
8392 && (TARGET_NO_SPACE_REGS
8393 || (outer_code != UNKNOWN && outer_code != MEM)
8394 || GET_CODE (x) != PLUS));
8397 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8398 use in fmpyadd instructions. */
8400 fmpyaddoperands (rtx *operands)
8402 enum machine_mode mode = GET_MODE (operands[0]);
8404 /* Must be a floating point mode. */
8405 if (mode != SFmode && mode != DFmode)
8408 /* All modes must be the same. */
8409 if (! (mode == GET_MODE (operands[1])
8410 && mode == GET_MODE (operands[2])
8411 && mode == GET_MODE (operands[3])
8412 && mode == GET_MODE (operands[4])
8413 && mode == GET_MODE (operands[5])))
8416 /* All operands must be registers. */
8417 if (! (GET_CODE (operands[1]) == REG
8418 && GET_CODE (operands[2]) == REG
8419 && GET_CODE (operands[3]) == REG
8420 && GET_CODE (operands[4]) == REG
8421 && GET_CODE (operands[5]) == REG))
8424 /* Only 2 real operands to the addition. One of the input operands must
8425 be the same as the output operand. */
8426 if (! rtx_equal_p (operands[3], operands[4])
8427 && ! rtx_equal_p (operands[3], operands[5]))
8430 /* Inout operand of add cannot conflict with any operands from multiply. */
8431 if (rtx_equal_p (operands[3], operands[0])
8432 || rtx_equal_p (operands[3], operands[1])
8433 || rtx_equal_p (operands[3], operands[2]))
8436 /* multiply cannot feed into addition operands. */
8437 if (rtx_equal_p (operands[4], operands[0])
8438 || rtx_equal_p (operands[5], operands[0]))
8441 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8443 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8444 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8445 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8446 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8447 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8448 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8451 /* Passed. Operands are suitable for fmpyadd. */
8455 #if !defined(USE_COLLECT2)
8457 pa_asm_out_constructor (rtx symbol, int priority)
8459 if (!function_label_operand (symbol, VOIDmode))
8460 hppa_encode_label (symbol);
8462 #ifdef CTORS_SECTION_ASM_OP
8463 default_ctor_section_asm_out_constructor (symbol, priority);
8465 # ifdef TARGET_ASM_NAMED_SECTION
8466 default_named_section_asm_out_constructor (symbol, priority);
8468 default_stabs_asm_out_constructor (symbol, priority);
8474 pa_asm_out_destructor (rtx symbol, int priority)
8476 if (!function_label_operand (symbol, VOIDmode))
8477 hppa_encode_label (symbol);
8479 #ifdef DTORS_SECTION_ASM_OP
8480 default_dtor_section_asm_out_destructor (symbol, priority);
8482 # ifdef TARGET_ASM_NAMED_SECTION
8483 default_named_section_asm_out_destructor (symbol, priority);
8485 default_stabs_asm_out_destructor (symbol, priority);
8491 /* This function places uninitialized global data in the bss section.
8492 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8493 function on the SOM port to prevent uninitialized global data from
8494 being placed in the data section. */
8497 pa_asm_output_aligned_bss (FILE *stream,
8499 unsigned HOST_WIDE_INT size,
8502 switch_to_section (bss_section);
8503 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8505 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8506 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8509 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8510 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8513 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8514 ASM_OUTPUT_LABEL (stream, name);
8515 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8518 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8519 that doesn't allow the alignment of global common storage to be directly
8520 specified. The SOM linker aligns common storage based on the rounded
8521 value of the NUM_BYTES parameter in the .comm directive. It's not
8522 possible to use the .align directive as it doesn't affect the alignment
8523 of the label associated with a .comm directive. */
8526 pa_asm_output_aligned_common (FILE *stream,
8528 unsigned HOST_WIDE_INT size,
8531 unsigned int max_common_align;
8533 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8534 if (align > max_common_align)
8536 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8537 "for global common data. Using %u",
8538 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8539 align = max_common_align;
8542 switch_to_section (bss_section);
8544 assemble_name (stream, name);
8545 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8546 MAX (size, align / BITS_PER_UNIT));
8549 /* We can't use .comm for local common storage as the SOM linker effectively
8550 treats the symbol as universal and uses the same storage for local symbols
8551 with the same name in different object files. The .block directive
8552 reserves an uninitialized block of storage. However, it's not common
8553 storage. Fortunately, GCC never requests common storage with the same
8554 name in any given translation unit. */
8557 pa_asm_output_aligned_local (FILE *stream,
8559 unsigned HOST_WIDE_INT size,
8562 switch_to_section (bss_section);
8563 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8566 fprintf (stream, "%s", LOCAL_ASM_OP);
8567 assemble_name (stream, name);
8568 fprintf (stream, "\n");
8571 ASM_OUTPUT_LABEL (stream, name);
8572 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8575 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8576 use in fmpysub instructions. */
8578 fmpysuboperands (rtx *operands)
8580 enum machine_mode mode = GET_MODE (operands[0]);
8582 /* Must be a floating point mode. */
8583 if (mode != SFmode && mode != DFmode)
8586 /* All modes must be the same. */
8587 if (! (mode == GET_MODE (operands[1])
8588 && mode == GET_MODE (operands[2])
8589 && mode == GET_MODE (operands[3])
8590 && mode == GET_MODE (operands[4])
8591 && mode == GET_MODE (operands[5])))
8594 /* All operands must be registers. */
8595 if (! (GET_CODE (operands[1]) == REG
8596 && GET_CODE (operands[2]) == REG
8597 && GET_CODE (operands[3]) == REG
8598 && GET_CODE (operands[4]) == REG
8599 && GET_CODE (operands[5]) == REG))
8602 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8603 operation, so operands[4] must be the same as operand[3]. */
8604 if (! rtx_equal_p (operands[3], operands[4]))
8607 /* multiply cannot feed into subtraction. */
8608 if (rtx_equal_p (operands[5], operands[0]))
8611 /* Inout operand of sub cannot conflict with any operands from multiply. */
8612 if (rtx_equal_p (operands[3], operands[0])
8613 || rtx_equal_p (operands[3], operands[1])
8614 || rtx_equal_p (operands[3], operands[2]))
8617 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8619 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8620 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8621 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8622 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8623 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8624 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8627 /* Passed. Operands are suitable for fmpysub. */
8631 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8632 constants for shadd instructions. */
8634 shadd_constant_p (int val)
8636 if (val == 2 || val == 4 || val == 8)
8642 /* Return 1 if OP is valid as a base or index register in a
8646 borx_reg_operand (rtx op, enum machine_mode mode)
8648 if (GET_CODE (op) != REG)
8651 /* We must reject virtual registers as the only expressions that
8652 can be instantiated are REG and REG+CONST. */
8653 if (op == virtual_incoming_args_rtx
8654 || op == virtual_stack_vars_rtx
8655 || op == virtual_stack_dynamic_rtx
8656 || op == virtual_outgoing_args_rtx
8657 || op == virtual_cfa_rtx)
8660 /* While it's always safe to index off the frame pointer, it's not
8661 profitable to do so when the frame pointer is being eliminated. */
8662 if (!reload_completed
8663 && flag_omit_frame_pointer
8664 && !cfun->calls_alloca
8665 && op == frame_pointer_rtx)
8668 return register_operand (op, mode);
8671 /* Return 1 if this operand is anything other than a hard register. */
8674 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8676 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8679 /* Return TRUE if INSN branches forward. */
8682 forward_branch_p (rtx insn)
8684 rtx lab = JUMP_LABEL (insn);
8686 /* The INSN must have a jump label. */
8687 gcc_assert (lab != NULL_RTX);
8689 if (INSN_ADDRESSES_SET_P ())
8690 return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn));
8697 insn = NEXT_INSN (insn);
8703 /* Return 1 if OP is an equality comparison, else return 0. */
8705 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8707 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8710 /* Return 1 if INSN is in the delay slot of a call instruction. */
8712 jump_in_call_delay (rtx insn)
8715 if (GET_CODE (insn) != JUMP_INSN)
8718 if (PREV_INSN (insn)
8719 && PREV_INSN (PREV_INSN (insn))
8720 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8722 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8724 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8725 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8732 /* Output an unconditional move and branch insn. */
8735 output_parallel_movb (rtx *operands, rtx insn)
8737 int length = get_attr_length (insn);
8739 /* These are the cases in which we win. */
8741 return "mov%I1b,tr %1,%0,%2";
8743 /* None of the following cases win, but they don't lose either. */
8746 if (dbr_sequence_length () == 0)
8748 /* Nothing in the delay slot, fake it by putting the combined
8749 insn (the copy or add) in the delay slot of a bl. */
8750 if (GET_CODE (operands[1]) == CONST_INT)
8751 return "b %2\n\tldi %1,%0";
8753 return "b %2\n\tcopy %1,%0";
8757 /* Something in the delay slot, but we've got a long branch. */
8758 if (GET_CODE (operands[1]) == CONST_INT)
8759 return "ldi %1,%0\n\tb %2";
8761 return "copy %1,%0\n\tb %2";
8765 if (GET_CODE (operands[1]) == CONST_INT)
8766 output_asm_insn ("ldi %1,%0", operands);
8768 output_asm_insn ("copy %1,%0", operands);
8769 return output_lbranch (operands[2], insn, 1);
8772 /* Output an unconditional add and branch insn. */
8775 output_parallel_addb (rtx *operands, rtx insn)
8777 int length = get_attr_length (insn);
8779 /* To make life easy we want operand0 to be the shared input/output
8780 operand and operand1 to be the readonly operand. */
8781 if (operands[0] == operands[1])
8782 operands[1] = operands[2];
8784 /* These are the cases in which we win. */
8786 return "add%I1b,tr %1,%0,%3";
8788 /* None of the following cases win, but they don't lose either. */
8791 if (dbr_sequence_length () == 0)
8792 /* Nothing in the delay slot, fake it by putting the combined
8793 insn (the copy or add) in the delay slot of a bl. */
8794 return "b %3\n\tadd%I1 %1,%0,%0";
8796 /* Something in the delay slot, but we've got a long branch. */
8797 return "add%I1 %1,%0,%0\n\tb %3";
8800 output_asm_insn ("add%I1 %1,%0,%0", operands);
8801 return output_lbranch (operands[3], insn, 1);
8804 /* Return nonzero if INSN (a jump insn) immediately follows a call
8805 to a named function. This is used to avoid filling the delay slot
8806 of the jump since it can usually be eliminated by modifying RP in
8807 the delay slot of the call. */
8810 following_call (rtx insn)
8812 if (! TARGET_JUMP_IN_DELAY)
8815 /* Find the previous real insn, skipping NOTEs. */
8816 insn = PREV_INSN (insn);
8817 while (insn && GET_CODE (insn) == NOTE)
8818 insn = PREV_INSN (insn);
8820 /* Check for CALL_INSNs and millicode calls. */
8822 && ((GET_CODE (insn) == CALL_INSN
8823 && get_attr_type (insn) != TYPE_DYNCALL)
8824 || (GET_CODE (insn) == INSN
8825 && GET_CODE (PATTERN (insn)) != SEQUENCE
8826 && GET_CODE (PATTERN (insn)) != USE
8827 && GET_CODE (PATTERN (insn)) != CLOBBER
8828 && get_attr_type (insn) == TYPE_MILLI)))
8834 /* We use this hook to perform a PA specific optimization which is difficult
8835 to do in earlier passes.
8837 We want the delay slots of branches within jump tables to be filled.
8838 None of the compiler passes at the moment even has the notion that a
8839 PA jump table doesn't contain addresses, but instead contains actual
8842 Because we actually jump into the table, the addresses of each entry
8843 must stay constant in relation to the beginning of the table (which
8844 itself must stay constant relative to the instruction to jump into
8845 it). I don't believe we can guarantee earlier passes of the compiler
8846 will adhere to those rules.
8848 So, late in the compilation process we find all the jump tables, and
8849 expand them into real code -- e.g. each entry in the jump table vector
8850 will get an appropriate label followed by a jump to the final target.
8852 Reorg and the final jump pass can then optimize these branches and
8853 fill their delay slots. We end up with smaller, more efficient code.
8855 The jump instructions within the table are special; we must be able
8856 to identify them during assembly output (if the jumps don't get filled
8857 we need to emit a nop rather than nullifying the delay slot)). We
8858 identify jumps in switch tables by using insns with the attribute
8859 type TYPE_BTABLE_BRANCH.
8861 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8862 insns. This serves two purposes, first it prevents jump.c from
8863 noticing that the last N entries in the table jump to the instruction
8864 immediately after the table and deleting the jumps. Second, those
8865 insns mark where we should emit .begin_brtab and .end_brtab directives
8866 when using GAS (allows for better link time optimizations). */
8873 remove_useless_addtr_insns (1);
8875 if (pa_cpu < PROCESSOR_8000)
8876 pa_combine_instructions ();
8879 /* This is fairly cheap, so always run it if optimizing. */
8880 if (optimize > 0 && !TARGET_BIG_SWITCH)
8882 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8883 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8885 rtx pattern, tmp, location, label;
8886 unsigned int length, i;
8888 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8889 if (GET_CODE (insn) != JUMP_INSN
8890 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8891 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8894 /* Emit marker for the beginning of the branch table. */
8895 emit_insn_before (gen_begin_brtab (), insn);
8897 pattern = PATTERN (insn);
8898 location = PREV_INSN (insn);
8899 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8901 for (i = 0; i < length; i++)
8903 /* Emit a label before each jump to keep jump.c from
8904 removing this code. */
8905 tmp = gen_label_rtx ();
8906 LABEL_NUSES (tmp) = 1;
8907 emit_label_after (tmp, location);
8908 location = NEXT_INSN (location);
8910 if (GET_CODE (pattern) == ADDR_VEC)
8911 label = XEXP (XVECEXP (pattern, 0, i), 0);
8913 label = XEXP (XVECEXP (pattern, 1, i), 0);
8915 tmp = gen_short_jump (label);
8917 /* Emit the jump itself. */
8918 tmp = emit_jump_insn_after (tmp, location);
8919 JUMP_LABEL (tmp) = label;
8920 LABEL_NUSES (label)++;
8921 location = NEXT_INSN (location);
8923 /* Emit a BARRIER after the jump. */
8924 emit_barrier_after (location);
8925 location = NEXT_INSN (location);
8928 /* Emit marker for the end of the branch table. */
8929 emit_insn_before (gen_end_brtab (), location);
8930 location = NEXT_INSN (location);
8931 emit_barrier_after (location);
8933 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8939 /* Still need brtab marker insns. FIXME: the presence of these
8940 markers disables output of the branch table to readonly memory,
8941 and any alignment directives that might be needed. Possibly,
8942 the begin_brtab insn should be output before the label for the
8943 table. This doesn't matter at the moment since the tables are
8944 always output in the text section. */
8945 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8947 /* Find an ADDR_VEC insn. */
8948 if (GET_CODE (insn) != JUMP_INSN
8949 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8950 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8953 /* Now generate markers for the beginning and end of the
8955 emit_insn_before (gen_begin_brtab (), insn);
8956 emit_insn_after (gen_end_brtab (), insn);
8961 /* The PA has a number of odd instructions which can perform multiple
8962 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8963 it may be profitable to combine two instructions into one instruction
8964 with two outputs. It's not profitable PA2.0 machines because the
8965 two outputs would take two slots in the reorder buffers.
8967 This routine finds instructions which can be combined and combines
8968 them. We only support some of the potential combinations, and we
8969 only try common ways to find suitable instructions.
8971 * addb can add two registers or a register and a small integer
8972 and jump to a nearby (+-8k) location. Normally the jump to the
8973 nearby location is conditional on the result of the add, but by
8974 using the "true" condition we can make the jump unconditional.
8975 Thus addb can perform two independent operations in one insn.
8977 * movb is similar to addb in that it can perform a reg->reg
8978 or small immediate->reg copy and jump to a nearby (+-8k location).
8980 * fmpyadd and fmpysub can perform a FP multiply and either an
8981 FP add or FP sub if the operands of the multiply and add/sub are
8982 independent (there are other minor restrictions). Note both
8983 the fmpy and fadd/fsub can in theory move to better spots according
8984 to data dependencies, but for now we require the fmpy stay at a
8987 * Many of the memory operations can perform pre & post updates
8988 of index registers. GCC's pre/post increment/decrement addressing
8989 is far too simple to take advantage of all the possibilities. This
8990 pass may not be suitable since those insns may not be independent.
8992 * comclr can compare two ints or an int and a register, nullify
8993 the following instruction and zero some other register. This
8994 is more difficult to use as it's harder to find an insn which
8995 will generate a comclr than finding something like an unconditional
8996 branch. (conditional moves & long branches create comclr insns).
8998 * Most arithmetic operations can conditionally skip the next
8999 instruction. They can be viewed as "perform this operation
9000 and conditionally jump to this nearby location" (where nearby
9001 is an insns away). These are difficult to use due to the
9002 branch length restrictions. */
9005 pa_combine_instructions (void)
9007 rtx anchor, new_rtx;
9009 /* This can get expensive since the basic algorithm is on the
9010 order of O(n^2) (or worse). Only do it for -O2 or higher
9011 levels of optimization. */
9015 /* Walk down the list of insns looking for "anchor" insns which
9016 may be combined with "floating" insns. As the name implies,
9017 "anchor" instructions don't move, while "floating" insns may
9019 new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
9020 new_rtx = make_insn_raw (new_rtx);
9022 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
9024 enum attr_pa_combine_type anchor_attr;
9025 enum attr_pa_combine_type floater_attr;
9027 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9028 Also ignore any special USE insns. */
9029 if ((GET_CODE (anchor) != INSN
9030 && GET_CODE (anchor) != JUMP_INSN
9031 && GET_CODE (anchor) != CALL_INSN)
9032 || GET_CODE (PATTERN (anchor)) == USE
9033 || GET_CODE (PATTERN (anchor)) == CLOBBER
9034 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
9035 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
9038 anchor_attr = get_attr_pa_combine_type (anchor);
9039 /* See if anchor is an insn suitable for combination. */
9040 if (anchor_attr == PA_COMBINE_TYPE_FMPY
9041 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
9042 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9043 && ! forward_branch_p (anchor)))
9047 for (floater = PREV_INSN (anchor);
9049 floater = PREV_INSN (floater))
9051 if (GET_CODE (floater) == NOTE
9052 || (GET_CODE (floater) == INSN
9053 && (GET_CODE (PATTERN (floater)) == USE
9054 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9057 /* Anything except a regular INSN will stop our search. */
9058 if (GET_CODE (floater) != INSN
9059 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9060 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9066 /* See if FLOATER is suitable for combination with the
9068 floater_attr = get_attr_pa_combine_type (floater);
9069 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9070 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9071 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9072 && floater_attr == PA_COMBINE_TYPE_FMPY))
9074 /* If ANCHOR and FLOATER can be combined, then we're
9075 done with this pass. */
9076 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9077 SET_DEST (PATTERN (floater)),
9078 XEXP (SET_SRC (PATTERN (floater)), 0),
9079 XEXP (SET_SRC (PATTERN (floater)), 1)))
9083 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9084 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
9086 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
9088 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9089 SET_DEST (PATTERN (floater)),
9090 XEXP (SET_SRC (PATTERN (floater)), 0),
9091 XEXP (SET_SRC (PATTERN (floater)), 1)))
9096 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9097 SET_DEST (PATTERN (floater)),
9098 SET_SRC (PATTERN (floater)),
9099 SET_SRC (PATTERN (floater))))
9105 /* If we didn't find anything on the backwards scan try forwards. */
9107 && (anchor_attr == PA_COMBINE_TYPE_FMPY
9108 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
9110 for (floater = anchor; floater; floater = NEXT_INSN (floater))
9112 if (GET_CODE (floater) == NOTE
9113 || (GET_CODE (floater) == INSN
9114 && (GET_CODE (PATTERN (floater)) == USE
9115 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9119 /* Anything except a regular INSN will stop our search. */
9120 if (GET_CODE (floater) != INSN
9121 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9122 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9128 /* See if FLOATER is suitable for combination with the
9130 floater_attr = get_attr_pa_combine_type (floater);
9131 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9132 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9133 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9134 && floater_attr == PA_COMBINE_TYPE_FMPY))
9136 /* If ANCHOR and FLOATER can be combined, then we're
9137 done with this pass. */
9138 if (pa_can_combine_p (new_rtx, anchor, floater, 1,
9139 SET_DEST (PATTERN (floater)),
9140 XEXP (SET_SRC (PATTERN (floater)),
9142 XEXP (SET_SRC (PATTERN (floater)),
9149 /* FLOATER will be nonzero if we found a suitable floating
9150 insn for combination with ANCHOR. */
9152 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9153 || anchor_attr == PA_COMBINE_TYPE_FMPY))
9155 /* Emit the new instruction and delete the old anchor. */
9156 emit_insn_before (gen_rtx_PARALLEL
9158 gen_rtvec (2, PATTERN (anchor),
9159 PATTERN (floater))),
9162 SET_INSN_DELETED (anchor);
9164 /* Emit a special USE insn for FLOATER, then delete
9165 the floating insn. */
9166 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9167 delete_insn (floater);
9172 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9175 /* Emit the new_jump instruction and delete the old anchor. */
9177 = emit_jump_insn_before (gen_rtx_PARALLEL
9179 gen_rtvec (2, PATTERN (anchor),
9180 PATTERN (floater))),
9183 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9184 SET_INSN_DELETED (anchor);
9186 /* Emit a special USE insn for FLOATER, then delete
9187 the floating insn. */
9188 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9189 delete_insn (floater);
9197 pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
9200 int insn_code_number;
9203 /* Create a PARALLEL with the patterns of ANCHOR and
9204 FLOATER, try to recognize it, then test constraints
9205 for the resulting pattern.
9207 If the pattern doesn't match or the constraints
9208 aren't met keep searching for a suitable floater
9210 XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
9211 XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
9212 INSN_CODE (new_rtx) = -1;
9213 insn_code_number = recog_memoized (new_rtx);
9214 if (insn_code_number < 0
9215 || (extract_insn (new_rtx), ! constrain_operands (1)))
9229 /* There's up to three operands to consider. One
9230 output and two inputs.
9232 The output must not be used between FLOATER & ANCHOR
9233 exclusive. The inputs must not be set between
9234 FLOATER and ANCHOR exclusive. */
9236 if (reg_used_between_p (dest, start, end))
9239 if (reg_set_between_p (src1, start, end))
9242 if (reg_set_between_p (src2, start, end))
9245 /* If we get here, then everything is good. */
9249 /* Return nonzero if references for INSN are delayed.
9251 Millicode insns are actually function calls with some special
9252 constraints on arguments and register usage.
9254 Millicode calls always expect their arguments in the integer argument
9255 registers, and always return their result in %r29 (ret1). They
9256 are expected to clobber their arguments, %r1, %r29, and the return
9257 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9259 This function tells reorg that the references to arguments and
9260 millicode calls do not appear to happen until after the millicode call.
9261 This allows reorg to put insns which set the argument registers into the
9262 delay slot of the millicode call -- thus they act more like traditional
9265 Note we cannot consider side effects of the insn to be delayed because
9266 the branch and link insn will clobber the return pointer. If we happened
9267 to use the return pointer in the delay slot of the call, then we lose.
9269 get_attr_type will try to recognize the given insn, so make sure to
9270 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9273 insn_refs_are_delayed (rtx insn)
9275 return ((GET_CODE (insn) == INSN
9276 && GET_CODE (PATTERN (insn)) != SEQUENCE
9277 && GET_CODE (PATTERN (insn)) != USE
9278 && GET_CODE (PATTERN (insn)) != CLOBBER
9279 && get_attr_type (insn) == TYPE_MILLI));
9282 /* Promote the return value, but not the arguments. */
9284 static enum machine_mode
9285 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
9286 enum machine_mode mode,
9287 int *punsignedp ATTRIBUTE_UNUSED,
9288 const_tree fntype ATTRIBUTE_UNUSED,
9291 if (for_return == 0)
9293 return promote_mode (type, mode, punsignedp);
9296 /* On the HP-PA the value is found in register(s) 28(-29), unless
9297 the mode is SF or DF. Then the value is returned in fr4 (32).
9299 This must perform the same promotions as PROMOTE_MODE, else promoting
9300 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9302 Small structures must be returned in a PARALLEL on PA64 in order
9303 to match the HP Compiler ABI. */
9306 pa_function_value (const_tree valtype,
9307 const_tree func ATTRIBUTE_UNUSED,
9308 bool outgoing ATTRIBUTE_UNUSED)
9310 enum machine_mode valmode;
9312 if (AGGREGATE_TYPE_P (valtype)
9313 || TREE_CODE (valtype) == COMPLEX_TYPE
9314 || TREE_CODE (valtype) == VECTOR_TYPE)
9318 /* Aggregates with a size less than or equal to 128 bits are
9319 returned in GR 28(-29). They are left justified. The pad
9320 bits are undefined. Larger aggregates are returned in
9324 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9326 for (i = 0; i < ub; i++)
9328 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9329 gen_rtx_REG (DImode, 28 + i),
9334 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9336 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9338 /* Aggregates 5 to 8 bytes in size are returned in general
9339 registers r28-r29 in the same manner as other non
9340 floating-point objects. The data is right-justified and
9341 zero-extended to 64 bits. This is opposite to the normal
9342 justification used on big endian targets and requires
9343 special treatment. */
9344 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9345 gen_rtx_REG (DImode, 28), const0_rtx);
9346 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9350 if ((INTEGRAL_TYPE_P (valtype)
9351 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9352 || POINTER_TYPE_P (valtype))
9353 valmode = word_mode;
9355 valmode = TYPE_MODE (valtype);
9357 if (TREE_CODE (valtype) == REAL_TYPE
9358 && !AGGREGATE_TYPE_P (valtype)
9359 && TYPE_MODE (valtype) != TFmode
9360 && !TARGET_SOFT_FLOAT)
9361 return gen_rtx_REG (valmode, 32);
9363 return gen_rtx_REG (valmode, 28);
9366 /* Implement the TARGET_LIBCALL_VALUE hook. */
9369 pa_libcall_value (enum machine_mode mode,
9370 const_rtx fun ATTRIBUTE_UNUSED)
9372 if (! TARGET_SOFT_FLOAT
9373 && (mode == SFmode || mode == DFmode))
9374 return gen_rtx_REG (mode, 32);
9376 return gen_rtx_REG (mode, 28);
9379 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9382 pa_function_value_regno_p (const unsigned int regno)
9385 || (! TARGET_SOFT_FLOAT && regno == 32))
9391 /* Update the data in CUM to advance over an argument
9392 of mode MODE and data type TYPE.
9393 (TYPE is null for libcalls where that information may not be available.) */
9396 pa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9397 const_tree type, bool named ATTRIBUTE_UNUSED)
9399 int arg_size = FUNCTION_ARG_SIZE (mode, type);
9401 cum->nargs_prototype--;
9402 cum->words += (arg_size
9403 + ((cum->words & 01)
9404 && type != NULL_TREE
9408 /* Return the location of a parameter that is passed in a register or NULL
9409 if the parameter has any component that is passed in memory.
9411 This is new code and will be pushed to into the net sources after
9414 ??? We might want to restructure this so that it looks more like other
9417 pa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9418 const_tree type, bool named ATTRIBUTE_UNUSED)
9420 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9427 if (mode == VOIDmode)
9430 arg_size = FUNCTION_ARG_SIZE (mode, type);
9432 /* If this arg would be passed partially or totally on the stack, then
9433 this routine should return zero. pa_arg_partial_bytes will
9434 handle arguments which are split between regs and stack slots if
9435 the ABI mandates split arguments. */
9438 /* The 32-bit ABI does not split arguments. */
9439 if (cum->words + arg_size > max_arg_words)
9445 alignment = cum->words & 1;
9446 if (cum->words + alignment >= max_arg_words)
9450 /* The 32bit ABIs and the 64bit ABIs are rather different,
9451 particularly in their handling of FP registers. We might
9452 be able to cleverly share code between them, but I'm not
9453 going to bother in the hope that splitting them up results
9454 in code that is more easily understood. */
9458 /* Advance the base registers to their current locations.
9460 Remember, gprs grow towards smaller register numbers while
9461 fprs grow to higher register numbers. Also remember that
9462 although FP regs are 32-bit addressable, we pretend that
9463 the registers are 64-bits wide. */
9464 gpr_reg_base = 26 - cum->words;
9465 fpr_reg_base = 32 + cum->words;
9467 /* Arguments wider than one word and small aggregates need special
9471 || (type && (AGGREGATE_TYPE_P (type)
9472 || TREE_CODE (type) == COMPLEX_TYPE
9473 || TREE_CODE (type) == VECTOR_TYPE)))
9475 /* Double-extended precision (80-bit), quad-precision (128-bit)
9476 and aggregates including complex numbers are aligned on
9477 128-bit boundaries. The first eight 64-bit argument slots
9478 are associated one-to-one, with general registers r26
9479 through r19, and also with floating-point registers fr4
9480 through fr11. Arguments larger than one word are always
9481 passed in general registers.
9483 Using a PARALLEL with a word mode register results in left
9484 justified data on a big-endian target. */
9487 int i, offset = 0, ub = arg_size;
9489 /* Align the base register. */
9490 gpr_reg_base -= alignment;
9492 ub = MIN (ub, max_arg_words - cum->words - alignment);
9493 for (i = 0; i < ub; i++)
9495 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9496 gen_rtx_REG (DImode, gpr_reg_base),
9502 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9507 /* If the argument is larger than a word, then we know precisely
9508 which registers we must use. */
9522 /* Structures 5 to 8 bytes in size are passed in the general
9523 registers in the same manner as other non floating-point
9524 objects. The data is right-justified and zero-extended
9525 to 64 bits. This is opposite to the normal justification
9526 used on big endian targets and requires special treatment.
9527 We now define BLOCK_REG_PADDING to pad these objects.
9528 Aggregates, complex and vector types are passed in the same
9529 manner as structures. */
9531 || (type && (AGGREGATE_TYPE_P (type)
9532 || TREE_CODE (type) == COMPLEX_TYPE
9533 || TREE_CODE (type) == VECTOR_TYPE)))
9535 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9536 gen_rtx_REG (DImode, gpr_reg_base),
9538 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9543 /* We have a single word (32 bits). A simple computation
9544 will get us the register #s we need. */
9545 gpr_reg_base = 26 - cum->words;
9546 fpr_reg_base = 32 + 2 * cum->words;
9550 /* Determine if the argument needs to be passed in both general and
9551 floating point registers. */
9552 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9553 /* If we are doing soft-float with portable runtime, then there
9554 is no need to worry about FP regs. */
9555 && !TARGET_SOFT_FLOAT
9556 /* The parameter must be some kind of scalar float, else we just
9557 pass it in integer registers. */
9558 && GET_MODE_CLASS (mode) == MODE_FLOAT
9559 /* The target function must not have a prototype. */
9560 && cum->nargs_prototype <= 0
9561 /* libcalls do not need to pass items in both FP and general
9563 && type != NULL_TREE
9564 /* All this hair applies to "outgoing" args only. This includes
9565 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9567 /* Also pass outgoing floating arguments in both registers in indirect
9568 calls with the 32 bit ABI and the HP assembler since there is no
9569 way to the specify argument locations in static functions. */
9574 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9580 gen_rtx_EXPR_LIST (VOIDmode,
9581 gen_rtx_REG (mode, fpr_reg_base),
9583 gen_rtx_EXPR_LIST (VOIDmode,
9584 gen_rtx_REG (mode, gpr_reg_base),
9589 /* See if we should pass this parameter in a general register. */
9590 if (TARGET_SOFT_FLOAT
9591 /* Indirect calls in the normal 32bit ABI require all arguments
9592 to be passed in general registers. */
9593 || (!TARGET_PORTABLE_RUNTIME
9597 /* If the parameter is not a scalar floating-point parameter,
9598 then it belongs in GPRs. */
9599 || GET_MODE_CLASS (mode) != MODE_FLOAT
9600 /* Structure with single SFmode field belongs in GPR. */
9601 || (type && AGGREGATE_TYPE_P (type)))
9602 retval = gen_rtx_REG (mode, gpr_reg_base);
9604 retval = gen_rtx_REG (mode, fpr_reg_base);
9609 /* Arguments larger than one word are double word aligned. */
9612 pa_function_arg_boundary (enum machine_mode mode, const_tree type)
9614 bool singleword = (type
9615 ? (integer_zerop (TYPE_SIZE (type))
9616 || !TREE_CONSTANT (TYPE_SIZE (type))
9617 || int_size_in_bytes (type) <= UNITS_PER_WORD)
9618 : GET_MODE_SIZE (mode) <= UNITS_PER_WORD);
9620 return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY;
9623 /* If this arg would be passed totally in registers or totally on the stack,
9624 then this routine should return zero. */
9627 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9628 tree type, bool named ATTRIBUTE_UNUSED)
9630 unsigned int max_arg_words = 8;
9631 unsigned int offset = 0;
9636 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9639 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9640 /* Arg fits fully into registers. */
9642 else if (cum->words + offset >= max_arg_words)
9643 /* Arg fully on the stack. */
9647 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9651 /* A get_unnamed_section callback for switching to the text section.
9653 This function is only used with SOM. Because we don't support
9654 named subspaces, we can only create a new subspace or switch back
9655 to the default text subspace. */
9658 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9660 gcc_assert (TARGET_SOM);
9663 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9665 /* We only want to emit a .nsubspa directive once at the
9666 start of the function. */
9667 cfun->machine->in_nsubspa = 1;
9669 /* Create a new subspace for the text. This provides
9670 better stub placement and one-only functions. */
9672 && DECL_ONE_ONLY (cfun->decl)
9673 && !DECL_WEAK (cfun->decl))
9675 output_section_asm_op ("\t.SPACE $TEXT$\n"
9676 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9677 "ACCESS=44,SORT=24,COMDAT");
9683 /* There isn't a current function or the body of the current
9684 function has been completed. So, we are changing to the
9685 text section to output debugging information. Thus, we
9686 need to forget that we are in the text section so that
9687 varasm.c will call us when text_section is selected again. */
9688 gcc_assert (!cfun || !cfun->machine
9689 || cfun->machine->in_nsubspa == 2);
9692 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9695 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9698 /* A get_unnamed_section callback for switching to comdat data
9699 sections. This function is only used with SOM. */
9702 som_output_comdat_data_section_asm_op (const void *data)
9705 output_section_asm_op (data);
9708 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9711 pa_som_asm_init_sections (void)
9714 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9716 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9717 is not being generated. */
9718 som_readonly_data_section
9719 = get_unnamed_section (0, output_section_asm_op,
9720 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9722 /* When secondary definitions are not supported, SOM makes readonly
9723 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9725 som_one_only_readonly_data_section
9726 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9728 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9729 "ACCESS=0x2c,SORT=16,COMDAT");
9732 /* When secondary definitions are not supported, SOM makes data one-only
9733 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9734 som_one_only_data_section
9735 = get_unnamed_section (SECTION_WRITE,
9736 som_output_comdat_data_section_asm_op,
9737 "\t.SPACE $PRIVATE$\n"
9738 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9739 "ACCESS=31,SORT=24,COMDAT");
9741 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9742 which reference data within the $TEXT$ space (for example constant
9743 strings in the $LIT$ subspace).
9745 The assemblers (GAS and HP as) both have problems with handling
9746 the difference of two symbols which is the other correct way to
9747 reference constant data during PIC code generation.
9749 So, there's no way to reference constant data which is in the
9750 $TEXT$ space during PIC generation. Instead place all constant
9751 data into the $PRIVATE$ subspace (this reduces sharing, but it
9752 works correctly). */
9753 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9755 /* We must not have a reference to an external symbol defined in a
9756 shared library in a readonly section, else the SOM linker will
9759 So, we force exception information into the data section. */
9760 exception_section = data_section;
9763 /* On hpux10, the linker will give an error if we have a reference
9764 in the read-only data section to a symbol defined in a shared
9765 library. Therefore, expressions that might require a reloc can
9766 not be placed in the read-only data section. */
9769 pa_select_section (tree exp, int reloc,
9770 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9772 if (TREE_CODE (exp) == VAR_DECL
9773 && TREE_READONLY (exp)
9774 && !TREE_THIS_VOLATILE (exp)
9775 && DECL_INITIAL (exp)
9776 && (DECL_INITIAL (exp) == error_mark_node
9777 || TREE_CONSTANT (DECL_INITIAL (exp)))
9781 && DECL_ONE_ONLY (exp)
9782 && !DECL_WEAK (exp))
9783 return som_one_only_readonly_data_section;
9785 return readonly_data_section;
9787 else if (CONSTANT_CLASS_P (exp) && !reloc)
9788 return readonly_data_section;
9790 && TREE_CODE (exp) == VAR_DECL
9791 && DECL_ONE_ONLY (exp)
9792 && !DECL_WEAK (exp))
9793 return som_one_only_data_section;
9795 return data_section;
9799 pa_globalize_label (FILE *stream, const char *name)
9801 /* We only handle DATA objects here, functions are globalized in
9802 ASM_DECLARE_FUNCTION_NAME. */
9803 if (! FUNCTION_NAME_P (name))
9805 fputs ("\t.EXPORT ", stream);
9806 assemble_name (stream, name);
9807 fputs (",DATA\n", stream);
9811 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9814 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9815 int incoming ATTRIBUTE_UNUSED)
9817 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9820 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9823 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9825 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9826 PA64 ABI says that objects larger than 128 bits are returned in memory.
9827 Note, int_size_in_bytes can return -1 if the size of the object is
9828 variable or larger than the maximum value that can be expressed as
9829 a HOST_WIDE_INT. It can also return zero for an empty type. The
9830 simplest way to handle variable and empty types is to pass them in
9831 memory. This avoids problems in defining the boundaries of argument
9832 slots, allocating registers, etc. */
9833 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9834 || int_size_in_bytes (type) <= 0);
9837 /* Structure to hold declaration and name of external symbols that are
9838 emitted by GCC. We generate a vector of these symbols and output them
9839 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9840 This avoids putting out names that are never really used. */
9842 typedef struct GTY(()) extern_symbol
9848 /* Define gc'd vector type for extern_symbol. */
9849 DEF_VEC_O(extern_symbol);
9850 DEF_VEC_ALLOC_O(extern_symbol,gc);
9852 /* Vector of extern_symbol pointers. */
9853 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9855 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9856 /* Mark DECL (name NAME) as an external reference (assembler output
9857 file FILE). This saves the names to output at the end of the file
9858 if actually referenced. */
9861 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9863 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9865 gcc_assert (file == asm_out_file);
9870 /* Output text required at the end of an assembler file.
9871 This includes deferred plabels and .import directives for
9872 all external symbols that were actually referenced. */
9875 pa_hpux_file_end (void)
9880 if (!NO_DEFERRED_PROFILE_COUNTERS)
9881 output_deferred_profile_counters ();
9883 output_deferred_plabels ();
9885 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9887 tree decl = p->decl;
9889 if (!TREE_ASM_WRITTEN (decl)
9890 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9891 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9894 VEC_free (extern_symbol, gc, extern_symbols);
9898 /* Return true if a change from mode FROM to mode TO for a register
9899 in register class RCLASS is invalid. */
9902 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9903 enum reg_class rclass)
9908 /* Reject changes to/from complex and vector modes. */
9909 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9910 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9913 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9916 /* There is no way to load QImode or HImode values directly from
9917 memory. SImode loads to the FP registers are not zero extended.
9918 On the 64-bit target, this conflicts with the definition of
9919 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9920 with different sizes in the floating-point registers. */
9921 if (MAYBE_FP_REG_CLASS_P (rclass))
9924 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9925 in specific sets of registers. Thus, we cannot allow changing
9926 to a larger mode when it's larger than a word. */
9927 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9928 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9934 /* Returns TRUE if it is a good idea to tie two pseudo registers
9935 when one has mode MODE1 and one has mode MODE2.
9936 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9937 for any hard reg, then this must be FALSE for correct output.
9939 We should return FALSE for QImode and HImode because these modes
9940 are not ok in the floating-point registers. However, this prevents
9941 tieing these modes to SImode and DImode in the general registers.
9942 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9943 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9944 in the floating-point registers. */
9947 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9949 /* Don't tie modes in different classes. */
9950 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))
9957 /* Length in units of the trampoline instruction code. */
9959 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
9962 /* Output assembler code for a block containing the constant parts
9963 of a trampoline, leaving space for the variable parts.\
9965 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
9966 and then branches to the specified routine.
9968 This code template is copied from text segment to stack location
9969 and then patched with pa_trampoline_init to contain valid values,
9970 and then entered as a subroutine.
9972 It is best to keep this as small as possible to avoid having to
9973 flush multiple lines in the cache. */
9976 pa_asm_trampoline_template (FILE *f)
9980 fputs ("\tldw 36(%r22),%r21\n", f);
9981 fputs ("\tbb,>=,n %r21,30,.+16\n", f);
9982 if (ASSEMBLER_DIALECT == 0)
9983 fputs ("\tdepi 0,31,2,%r21\n", f);
9985 fputs ("\tdepwi 0,31,2,%r21\n", f);
9986 fputs ("\tldw 4(%r21),%r19\n", f);
9987 fputs ("\tldw 0(%r21),%r21\n", f);
9990 fputs ("\tbve (%r21)\n", f);
9991 fputs ("\tldw 40(%r22),%r29\n", f);
9992 fputs ("\t.word 0\n", f);
9993 fputs ("\t.word 0\n", f);
9997 fputs ("\tldsid (%r21),%r1\n", f);
9998 fputs ("\tmtsp %r1,%sr0\n", f);
9999 fputs ("\tbe 0(%sr0,%r21)\n", f);
10000 fputs ("\tldw 40(%r22),%r29\n", f);
10002 fputs ("\t.word 0\n", f);
10003 fputs ("\t.word 0\n", f);
10004 fputs ("\t.word 0\n", f);
10005 fputs ("\t.word 0\n", f);
10009 fputs ("\t.dword 0\n", f);
10010 fputs ("\t.dword 0\n", f);
10011 fputs ("\t.dword 0\n", f);
10012 fputs ("\t.dword 0\n", f);
10013 fputs ("\tmfia %r31\n", f);
10014 fputs ("\tldd 24(%r31),%r1\n", f);
10015 fputs ("\tldd 24(%r1),%r27\n", f);
10016 fputs ("\tldd 16(%r1),%r1\n", f);
10017 fputs ("\tbve (%r1)\n", f);
10018 fputs ("\tldd 32(%r31),%r31\n", f);
10019 fputs ("\t.dword 0 ; fptr\n", f);
10020 fputs ("\t.dword 0 ; static link\n", f);
10024 /* Emit RTL insns to initialize the variable parts of a trampoline.
10025 FNADDR is an RTX for the address of the function's pure code.
10026 CXT is an RTX for the static chain value for the function.
10028 Move the function address to the trampoline template at offset 36.
10029 Move the static chain value to trampoline template at offset 40.
10030 Move the trampoline address to trampoline template at offset 44.
10031 Move r19 to trampoline template at offset 48. The latter two
10032 words create a plabel for the indirect call to the trampoline.
10034 A similar sequence is used for the 64-bit port but the plabel is
10035 at the beginning of the trampoline.
10037 Finally, the cache entries for the trampoline code are flushed.
10038 This is necessary to ensure that the trampoline instruction sequence
10039 is written to memory prior to any attempts at prefetching the code
10043 pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
10045 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10046 rtx start_addr = gen_reg_rtx (Pmode);
10047 rtx end_addr = gen_reg_rtx (Pmode);
10048 rtx line_length = gen_reg_rtx (Pmode);
10051 emit_block_move (m_tramp, assemble_trampoline_template (),
10052 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
10053 r_tramp = force_reg (Pmode, XEXP (m_tramp, 0));
10057 tmp = adjust_address (m_tramp, Pmode, 36);
10058 emit_move_insn (tmp, fnaddr);
10059 tmp = adjust_address (m_tramp, Pmode, 40);
10060 emit_move_insn (tmp, chain_value);
10062 /* Create a fat pointer for the trampoline. */
10063 tmp = adjust_address (m_tramp, Pmode, 44);
10064 emit_move_insn (tmp, r_tramp);
10065 tmp = adjust_address (m_tramp, Pmode, 48);
10066 emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
10068 /* fdc and fic only use registers for the address to flush,
10069 they do not accept integer displacements. We align the
10070 start and end addresses to the beginning of their respective
10071 cache lines to minimize the number of lines flushed. */
10072 emit_insn (gen_andsi3 (start_addr, r_tramp,
10073 GEN_INT (-MIN_CACHELINE_SIZE)));
10074 tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1));
10075 emit_insn (gen_andsi3 (end_addr, tmp,
10076 GEN_INT (-MIN_CACHELINE_SIZE)));
10077 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10078 emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
10079 emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
10080 gen_reg_rtx (Pmode),
10081 gen_reg_rtx (Pmode)));
10085 tmp = adjust_address (m_tramp, Pmode, 56);
10086 emit_move_insn (tmp, fnaddr);
10087 tmp = adjust_address (m_tramp, Pmode, 64);
10088 emit_move_insn (tmp, chain_value);
10090 /* Create a fat pointer for the trampoline. */
10091 tmp = adjust_address (m_tramp, Pmode, 16);
10092 emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32)));
10093 tmp = adjust_address (m_tramp, Pmode, 24);
10094 emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
10096 /* fdc and fic only use registers for the address to flush,
10097 they do not accept integer displacements. We align the
10098 start and end addresses to the beginning of their respective
10099 cache lines to minimize the number of lines flushed. */
10100 tmp = force_reg (Pmode, plus_constant (r_tramp, 32));
10101 emit_insn (gen_anddi3 (start_addr, tmp,
10102 GEN_INT (-MIN_CACHELINE_SIZE)));
10103 tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));
10104 emit_insn (gen_anddi3 (end_addr, tmp,
10105 GEN_INT (-MIN_CACHELINE_SIZE)));
10106 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10107 emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
10108 emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
10109 gen_reg_rtx (Pmode),
10110 gen_reg_rtx (Pmode)));
10114 /* Perform any machine-specific adjustment in the address of the trampoline.
10115 ADDR contains the address that was passed to pa_trampoline_init.
10116 Adjust the trampoline address to point to the plabel at offset 44. */
10119 pa_trampoline_adjust_address (rtx addr)
10122 addr = memory_address (Pmode, plus_constant (addr, 46));
10127 pa_delegitimize_address (rtx orig_x)
10129 rtx x = delegitimize_mem_from_attrs (orig_x);
10131 if (GET_CODE (x) == LO_SUM
10132 && GET_CODE (XEXP (x, 1)) == UNSPEC
10133 && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R)
10134 return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0));
10139 pa_internal_arg_pointer (void)
10141 /* The argument pointer and the hard frame pointer are the same in
10142 the 32-bit runtime, so we don't need a copy. */
10144 return copy_to_reg (virtual_incoming_args_rtx);
10146 return virtual_incoming_args_rtx;
10149 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10150 Frame pointer elimination is automatically handled. */
10153 pa_can_eliminate (const int from, const int to)
10155 /* The argument cannot be eliminated in the 64-bit runtime. */
10156 if (TARGET_64BIT && from == ARG_POINTER_REGNUM)
10159 return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM
10160 ? ! frame_pointer_needed
10164 /* Define the offset between two registers, FROM to be eliminated and its
10165 replacement TO, at the start of a routine. */
10167 pa_initial_elimination_offset (int from, int to)
10169 HOST_WIDE_INT offset;
10171 if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
10172 && to == STACK_POINTER_REGNUM)
10173 offset = -compute_frame_size (get_frame_size (), 0);
10174 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10177 gcc_unreachable ();
10183 pa_conditional_register_usage (void)
10187 if (!TARGET_64BIT && !TARGET_PA_11)
10189 for (i = 56; i <= FP_REG_LAST; i++)
10190 fixed_regs[i] = call_used_regs[i] = 1;
10191 for (i = 33; i < 56; i += 2)
10192 fixed_regs[i] = call_used_regs[i] = 1;
10194 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10196 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
10197 fixed_regs[i] = call_used_regs[i] = 1;
10200 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;