1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3, or (at your option)
14 GCC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING3. If not see
21 <http://www.gnu.org/licenses/>. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
32 #include "insn-attr.h"
40 #include "integrate.h"
42 #include "diagnostic-core.h"
49 #include "target-def.h"
52 /* Return nonzero if there is a bypass for the output of
53 OUT_INSN and the fp store IN_INSN. */
55 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
57 enum machine_mode store_mode;
58 enum machine_mode other_mode;
61 if (recog_memoized (in_insn) < 0
62 || (get_attr_type (in_insn) != TYPE_FPSTORE
63 && get_attr_type (in_insn) != TYPE_FPSTORE_LOAD)
64 || recog_memoized (out_insn) < 0)
67 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
69 set = single_set (out_insn);
73 other_mode = GET_MODE (SET_SRC (set));
75 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
79 #ifndef DO_FRAME_NOTES
80 #ifdef INCOMING_RETURN_ADDR_RTX
81 #define DO_FRAME_NOTES 1
83 #define DO_FRAME_NOTES 0
87 static void pa_option_override (void);
88 static void copy_reg_pointer (rtx, rtx);
89 static void fix_range (const char *);
90 static bool pa_handle_option (size_t, const char *, int);
91 static int hppa_register_move_cost (enum machine_mode mode, reg_class_t,
93 static int hppa_address_cost (rtx, bool);
94 static bool hppa_rtx_costs (rtx, int, int, int *, bool);
95 static inline rtx force_mode (enum machine_mode, rtx);
96 static void pa_reorg (void);
97 static void pa_combine_instructions (void);
98 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
99 static bool forward_branch_p (rtx);
100 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
101 static int compute_movmem_length (rtx);
102 static int compute_clrmem_length (rtx);
103 static bool pa_assemble_integer (rtx, unsigned int, int);
104 static void remove_useless_addtr_insns (int);
105 static void store_reg (int, HOST_WIDE_INT, int);
106 static void store_reg_modify (int, int, HOST_WIDE_INT);
107 static void load_reg (int, HOST_WIDE_INT, int);
108 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
109 static rtx pa_function_value (const_tree, const_tree, bool);
110 static rtx pa_libcall_value (enum machine_mode, const_rtx);
111 static bool pa_function_value_regno_p (const unsigned int);
112 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
113 static void update_total_code_bytes (unsigned int);
114 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
115 static int pa_adjust_cost (rtx, rtx, rtx, int);
116 static int pa_adjust_priority (rtx, int);
117 static int pa_issue_rate (void);
118 static void pa_som_asm_init_sections (void) ATTRIBUTE_UNUSED;
119 static section *pa_select_section (tree, int, unsigned HOST_WIDE_INT)
121 static void pa_encode_section_info (tree, rtx, int);
122 static const char *pa_strip_name_encoding (const char *);
123 static bool pa_function_ok_for_sibcall (tree, tree);
124 static void pa_globalize_label (FILE *, const char *)
126 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
127 HOST_WIDE_INT, tree);
128 #if !defined(USE_COLLECT2)
129 static void pa_asm_out_constructor (rtx, int);
130 static void pa_asm_out_destructor (rtx, int);
132 static void pa_init_builtins (void);
133 static rtx hppa_builtin_saveregs (void);
134 static void hppa_va_start (tree, rtx);
135 static tree hppa_gimplify_va_arg_expr (tree, tree, gimple_seq *, gimple_seq *);
136 static bool pa_scalar_mode_supported_p (enum machine_mode);
137 static bool pa_commutative_p (const_rtx x, int outer_code);
138 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
139 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
140 static rtx hppa_legitimize_address (rtx, rtx, enum machine_mode);
141 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
142 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
143 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
144 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
145 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
146 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
147 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
148 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
149 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
150 static void output_deferred_plabels (void);
151 static void output_deferred_profile_counters (void) ATTRIBUTE_UNUSED;
152 #ifdef ASM_OUTPUT_EXTERNAL_REAL
153 static void pa_hpux_file_end (void);
155 #ifdef HPUX_LONG_DOUBLE_LIBRARY
156 static void pa_hpux_init_libfuncs (void);
158 static rtx pa_struct_value_rtx (tree, int);
159 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
161 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
163 static void pa_function_arg_advance (CUMULATIVE_ARGS *, enum machine_mode,
165 static rtx pa_function_arg (CUMULATIVE_ARGS *, enum machine_mode,
167 static unsigned int pa_function_arg_boundary (enum machine_mode, const_tree);
168 static struct machine_function * pa_init_machine_status (void);
169 static reg_class_t pa_secondary_reload (bool, rtx, reg_class_t,
171 secondary_reload_info *);
172 static void pa_extra_live_on_entry (bitmap);
173 static enum machine_mode pa_promote_function_mode (const_tree,
174 enum machine_mode, int *,
177 static void pa_asm_trampoline_template (FILE *);
178 static void pa_trampoline_init (rtx, tree, rtx);
179 static rtx pa_trampoline_adjust_address (rtx);
180 static rtx pa_delegitimize_address (rtx);
181 static bool pa_print_operand_punct_valid_p (unsigned char);
182 static rtx pa_internal_arg_pointer (void);
183 static bool pa_can_eliminate (const int, const int);
184 static void pa_conditional_register_usage (void);
186 /* The following extra sections are only used for SOM. */
187 static GTY(()) section *som_readonly_data_section;
188 static GTY(()) section *som_one_only_readonly_data_section;
189 static GTY(()) section *som_one_only_data_section;
191 /* Which cpu we are scheduling for. */
192 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
194 /* The UNIX standard to use for predefines and linking. */
195 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
197 /* Counts for the number of callee-saved general and floating point
198 registers which were saved by the current function's prologue. */
199 static int gr_saved, fr_saved;
201 /* Boolean indicating whether the return pointer was saved by the
202 current function's prologue. */
203 static bool rp_saved;
205 static rtx find_addr_reg (rtx);
207 /* Keep track of the number of bytes we have output in the CODE subspace
208 during this compilation so we'll know when to emit inline long-calls. */
209 unsigned long total_code_bytes;
211 /* The last address of the previous function plus the number of bytes in
212 associated thunks that have been output. This is used to determine if
213 a thunk can use an IA-relative branch to reach its target function. */
214 static unsigned int last_address;
216 /* Variables to handle plabels that we discover are necessary at assembly
217 output time. They are output after the current function. */
218 struct GTY(()) deferred_plabel
223 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
225 static size_t n_deferred_plabels = 0;
227 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
228 static const struct default_options pa_option_optimization_table[] =
230 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
231 { OPT_LEVELS_NONE, 0, NULL, 0 }
235 /* Initialize the GCC target structure. */
237 #undef TARGET_OPTION_OVERRIDE
238 #define TARGET_OPTION_OVERRIDE pa_option_override
239 #undef TARGET_OPTION_OPTIMIZATION_TABLE
240 #define TARGET_OPTION_OPTIMIZATION_TABLE pa_option_optimization_table
242 #undef TARGET_ASM_ALIGNED_HI_OP
243 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
244 #undef TARGET_ASM_ALIGNED_SI_OP
245 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
246 #undef TARGET_ASM_ALIGNED_DI_OP
247 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
248 #undef TARGET_ASM_UNALIGNED_HI_OP
249 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
250 #undef TARGET_ASM_UNALIGNED_SI_OP
251 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
252 #undef TARGET_ASM_UNALIGNED_DI_OP
253 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
254 #undef TARGET_ASM_INTEGER
255 #define TARGET_ASM_INTEGER pa_assemble_integer
257 #undef TARGET_ASM_FUNCTION_PROLOGUE
258 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
259 #undef TARGET_ASM_FUNCTION_EPILOGUE
260 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
262 #undef TARGET_FUNCTION_VALUE
263 #define TARGET_FUNCTION_VALUE pa_function_value
264 #undef TARGET_LIBCALL_VALUE
265 #define TARGET_LIBCALL_VALUE pa_libcall_value
266 #undef TARGET_FUNCTION_VALUE_REGNO_P
267 #define TARGET_FUNCTION_VALUE_REGNO_P pa_function_value_regno_p
269 #undef TARGET_LEGITIMIZE_ADDRESS
270 #define TARGET_LEGITIMIZE_ADDRESS hppa_legitimize_address
272 #undef TARGET_SCHED_ADJUST_COST
273 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
274 #undef TARGET_SCHED_ADJUST_PRIORITY
275 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
276 #undef TARGET_SCHED_ISSUE_RATE
277 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
279 #undef TARGET_ENCODE_SECTION_INFO
280 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
281 #undef TARGET_STRIP_NAME_ENCODING
282 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
284 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
285 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
287 #undef TARGET_COMMUTATIVE_P
288 #define TARGET_COMMUTATIVE_P pa_commutative_p
290 #undef TARGET_ASM_OUTPUT_MI_THUNK
291 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
292 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
293 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
295 #undef TARGET_ASM_FILE_END
296 #ifdef ASM_OUTPUT_EXTERNAL_REAL
297 #define TARGET_ASM_FILE_END pa_hpux_file_end
299 #define TARGET_ASM_FILE_END output_deferred_plabels
302 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P
303 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pa_print_operand_punct_valid_p
305 #if !defined(USE_COLLECT2)
306 #undef TARGET_ASM_CONSTRUCTOR
307 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
308 #undef TARGET_ASM_DESTRUCTOR
309 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
312 #undef TARGET_DEFAULT_TARGET_FLAGS
313 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
314 #undef TARGET_HANDLE_OPTION
315 #define TARGET_HANDLE_OPTION pa_handle_option
317 #undef TARGET_INIT_BUILTINS
318 #define TARGET_INIT_BUILTINS pa_init_builtins
320 #undef TARGET_REGISTER_MOVE_COST
321 #define TARGET_REGISTER_MOVE_COST hppa_register_move_cost
322 #undef TARGET_RTX_COSTS
323 #define TARGET_RTX_COSTS hppa_rtx_costs
324 #undef TARGET_ADDRESS_COST
325 #define TARGET_ADDRESS_COST hppa_address_cost
327 #undef TARGET_MACHINE_DEPENDENT_REORG
328 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
330 #ifdef HPUX_LONG_DOUBLE_LIBRARY
331 #undef TARGET_INIT_LIBFUNCS
332 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
335 #undef TARGET_PROMOTE_FUNCTION_MODE
336 #define TARGET_PROMOTE_FUNCTION_MODE pa_promote_function_mode
337 #undef TARGET_PROMOTE_PROTOTYPES
338 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
340 #undef TARGET_STRUCT_VALUE_RTX
341 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
342 #undef TARGET_RETURN_IN_MEMORY
343 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
344 #undef TARGET_MUST_PASS_IN_STACK
345 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
346 #undef TARGET_PASS_BY_REFERENCE
347 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
348 #undef TARGET_CALLEE_COPIES
349 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
350 #undef TARGET_ARG_PARTIAL_BYTES
351 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
352 #undef TARGET_FUNCTION_ARG
353 #define TARGET_FUNCTION_ARG pa_function_arg
354 #undef TARGET_FUNCTION_ARG_ADVANCE
355 #define TARGET_FUNCTION_ARG_ADVANCE pa_function_arg_advance
356 #undef TARGET_FUNCTION_ARG_BOUNDARY
357 #define TARGET_FUNCTION_ARG_BOUNDARY pa_function_arg_boundary
359 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
360 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
361 #undef TARGET_EXPAND_BUILTIN_VA_START
362 #define TARGET_EXPAND_BUILTIN_VA_START hppa_va_start
363 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
364 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
366 #undef TARGET_SCALAR_MODE_SUPPORTED_P
367 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
369 #undef TARGET_CANNOT_FORCE_CONST_MEM
370 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
372 #undef TARGET_SECONDARY_RELOAD
373 #define TARGET_SECONDARY_RELOAD pa_secondary_reload
375 #undef TARGET_EXTRA_LIVE_ON_ENTRY
376 #define TARGET_EXTRA_LIVE_ON_ENTRY pa_extra_live_on_entry
378 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
379 #define TARGET_ASM_TRAMPOLINE_TEMPLATE pa_asm_trampoline_template
380 #undef TARGET_TRAMPOLINE_INIT
381 #define TARGET_TRAMPOLINE_INIT pa_trampoline_init
382 #undef TARGET_TRAMPOLINE_ADJUST_ADDRESS
383 #define TARGET_TRAMPOLINE_ADJUST_ADDRESS pa_trampoline_adjust_address
384 #undef TARGET_DELEGITIMIZE_ADDRESS
385 #define TARGET_DELEGITIMIZE_ADDRESS pa_delegitimize_address
386 #undef TARGET_INTERNAL_ARG_POINTER
387 #define TARGET_INTERNAL_ARG_POINTER pa_internal_arg_pointer
388 #undef TARGET_CAN_ELIMINATE
389 #define TARGET_CAN_ELIMINATE pa_can_eliminate
390 #undef TARGET_CONDITIONAL_REGISTER_USAGE
391 #define TARGET_CONDITIONAL_REGISTER_USAGE pa_conditional_register_usage
393 struct gcc_target targetm = TARGET_INITIALIZER;
395 /* Parse the -mfixed-range= option string. */
398 fix_range (const char *const_str)
401 char *str, *dash, *comma;
403 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
404 REG2 are either register names or register numbers. The effect
405 of this option is to mark the registers in the range from REG1 to
406 REG2 as ``fixed'' so they won't be used by the compiler. This is
407 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
409 i = strlen (const_str);
410 str = (char *) alloca (i + 1);
411 memcpy (str, const_str, i + 1);
415 dash = strchr (str, '-');
418 warning (0, "value of -mfixed-range must have form REG1-REG2");
423 comma = strchr (dash + 1, ',');
427 first = decode_reg_name (str);
430 warning (0, "unknown register name: %s", str);
434 last = decode_reg_name (dash + 1);
437 warning (0, "unknown register name: %s", dash + 1);
445 warning (0, "%s-%s is an empty range", str, dash + 1);
449 for (i = first; i <= last; ++i)
450 fixed_regs[i] = call_used_regs[i] = 1;
459 /* Check if all floating point registers have been fixed. */
460 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
465 target_flags |= MASK_DISABLE_FPREGS;
468 /* Implement TARGET_HANDLE_OPTION. */
471 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
476 case OPT_mpa_risc_1_0:
478 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
482 case OPT_mpa_risc_1_1:
484 target_flags &= ~MASK_PA_20;
485 target_flags |= MASK_PA_11;
488 case OPT_mpa_risc_2_0:
490 target_flags |= MASK_PA_11 | MASK_PA_20;
494 if (strcmp (arg, "8000") == 0)
495 pa_cpu = PROCESSOR_8000;
496 else if (strcmp (arg, "7100") == 0)
497 pa_cpu = PROCESSOR_7100;
498 else if (strcmp (arg, "700") == 0)
499 pa_cpu = PROCESSOR_700;
500 else if (strcmp (arg, "7100LC") == 0)
501 pa_cpu = PROCESSOR_7100LC;
502 else if (strcmp (arg, "7200") == 0)
503 pa_cpu = PROCESSOR_7200;
504 else if (strcmp (arg, "7300") == 0)
505 pa_cpu = PROCESSOR_7300;
510 case OPT_mfixed_range_:
520 #if TARGET_HPUX_10_10
526 #if TARGET_HPUX_11_11
537 /* Implement the TARGET_OPTION_OVERRIDE hook. */
540 pa_option_override (void)
542 /* Unconditional branches in the delay slot are not compatible with dwarf2
543 call frame information. There is no benefit in using this optimization
544 on PA8000 and later processors. */
545 if (pa_cpu >= PROCESSOR_8000
546 || (targetm.except_unwind_info (&global_options) == UI_DWARF2
548 || flag_unwind_tables)
549 target_flags &= ~MASK_JUMP_IN_DELAY;
551 if (flag_pic && TARGET_PORTABLE_RUNTIME)
553 warning (0, "PIC code generation is not supported in the portable runtime model");
556 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
558 warning (0, "PIC code generation is not compatible with fast indirect calls");
561 if (! TARGET_GAS && write_symbols != NO_DEBUG)
563 warning (0, "-g is only supported when using GAS on this processor,");
564 warning (0, "-g option disabled");
565 write_symbols = NO_DEBUG;
568 /* We only support the "big PIC" model now. And we always generate PIC
569 code when in 64bit mode. */
570 if (flag_pic == 1 || TARGET_64BIT)
573 /* Disable -freorder-blocks-and-partition as we don't support hot and
574 cold partitioning. */
575 if (flag_reorder_blocks_and_partition)
577 inform (input_location,
578 "-freorder-blocks-and-partition does not work "
579 "on this architecture");
580 flag_reorder_blocks_and_partition = 0;
581 flag_reorder_blocks = 1;
584 /* We can't guarantee that .dword is available for 32-bit targets. */
585 if (UNITS_PER_WORD == 4)
586 targetm.asm_out.aligned_op.di = NULL;
588 /* The unaligned ops are only available when using GAS. */
591 targetm.asm_out.unaligned_op.hi = NULL;
592 targetm.asm_out.unaligned_op.si = NULL;
593 targetm.asm_out.unaligned_op.di = NULL;
596 init_machine_status = pa_init_machine_status;
600 pa_init_builtins (void)
602 #ifdef DONT_HAVE_FPUTC_UNLOCKED
603 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] =
604 built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
605 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED]
606 = implicit_built_in_decls[(int) BUILT_IN_PUTC_UNLOCKED];
609 if (built_in_decls [BUILT_IN_FINITE])
610 set_user_assembler_name (built_in_decls [BUILT_IN_FINITE], "_Isfinite");
611 if (built_in_decls [BUILT_IN_FINITEF])
612 set_user_assembler_name (built_in_decls [BUILT_IN_FINITEF], "_Isfinitef");
616 /* Function to init struct machine_function.
617 This will be called, via a pointer variable,
618 from push_function_context. */
620 static struct machine_function *
621 pa_init_machine_status (void)
623 return ggc_alloc_cleared_machine_function ();
626 /* If FROM is a probable pointer register, mark TO as a probable
627 pointer register with the same pointer alignment as FROM. */
630 copy_reg_pointer (rtx to, rtx from)
632 if (REG_POINTER (from))
633 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
636 /* Return 1 if X contains a symbolic expression. We know these
637 expressions will have one of a few well defined forms, so
638 we need only check those forms. */
640 symbolic_expression_p (rtx x)
643 /* Strip off any HIGH. */
644 if (GET_CODE (x) == HIGH)
647 return (symbolic_operand (x, VOIDmode));
650 /* Accept any constant that can be moved in one instruction into a
653 cint_ok_for_move (HOST_WIDE_INT ival)
655 /* OK if ldo, ldil, or zdepi, can be used. */
656 return (VAL_14_BITS_P (ival)
657 || ldil_cint_p (ival)
658 || zdepi_cint_p (ival));
661 /* Return truth value of whether OP can be used as an operand in a
664 adddi3_operand (rtx op, enum machine_mode mode)
666 return (register_operand (op, mode)
667 || (GET_CODE (op) == CONST_INT
668 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
671 /* True iff the operand OP can be used as the destination operand of
672 an integer store. This also implies the operand could be used as
673 the source operand of an integer load. Symbolic, lo_sum and indexed
674 memory operands are not allowed. We accept reloading pseudos and
675 other memory operands. */
677 integer_store_memory_operand (rtx op, enum machine_mode mode)
679 return ((reload_in_progress
681 && REGNO (op) >= FIRST_PSEUDO_REGISTER
682 && reg_renumber [REGNO (op)] < 0)
683 || (GET_CODE (op) == MEM
684 && (reload_in_progress || memory_address_p (mode, XEXP (op, 0)))
685 && !symbolic_memory_operand (op, VOIDmode)
686 && !IS_LO_SUM_DLT_ADDR_P (XEXP (op, 0))
687 && !IS_INDEX_ADDR_P (XEXP (op, 0))));
690 /* True iff ldil can be used to load this CONST_INT. The least
691 significant 11 bits of the value must be zero and the value must
692 not change sign when extended from 32 to 64 bits. */
694 ldil_cint_p (HOST_WIDE_INT ival)
696 HOST_WIDE_INT x = ival & (((HOST_WIDE_INT) -1 << 31) | 0x7ff);
698 return x == 0 || x == ((HOST_WIDE_INT) -1 << 31);
701 /* True iff zdepi can be used to generate this CONST_INT.
702 zdepi first sign extends a 5-bit signed number to a given field
703 length, then places this field anywhere in a zero. */
705 zdepi_cint_p (unsigned HOST_WIDE_INT x)
707 unsigned HOST_WIDE_INT lsb_mask, t;
709 /* This might not be obvious, but it's at least fast.
710 This function is critical; we don't have the time loops would take. */
712 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
713 /* Return true iff t is a power of two. */
714 return ((t & (t - 1)) == 0);
717 /* True iff depi or extru can be used to compute (reg & mask).
718 Accept bit pattern like these:
723 and_mask_p (unsigned HOST_WIDE_INT mask)
726 mask += mask & -mask;
727 return (mask & (mask - 1)) == 0;
730 /* True iff depi can be used to compute (reg | MASK). */
732 ior_mask_p (unsigned HOST_WIDE_INT mask)
734 mask += mask & -mask;
735 return (mask & (mask - 1)) == 0;
738 /* Legitimize PIC addresses. If the address is already
739 position-independent, we return ORIG. Newly generated
740 position-independent addresses go to REG. If we need more
741 than one register, we lose. */
744 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
748 gcc_assert (!PA_SYMBOL_REF_TLS_P (orig));
750 /* Labels need special handling. */
751 if (pic_label_operand (orig, mode))
755 /* We do not want to go through the movXX expanders here since that
756 would create recursion.
758 Nor do we really want to call a generator for a named pattern
759 since that requires multiple patterns if we want to support
762 So instead we just emit the raw set, which avoids the movXX
763 expanders completely. */
764 mark_reg_pointer (reg, BITS_PER_UNIT);
765 insn = emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
767 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
768 add_reg_note (insn, REG_EQUAL, orig);
770 /* During and after reload, we need to generate a REG_LABEL_OPERAND note
771 and update LABEL_NUSES because this is not done automatically. */
772 if (reload_in_progress || reload_completed)
774 /* Extract LABEL_REF. */
775 if (GET_CODE (orig) == CONST)
776 orig = XEXP (XEXP (orig, 0), 0);
777 /* Extract CODE_LABEL. */
778 orig = XEXP (orig, 0);
779 add_reg_note (insn, REG_LABEL_OPERAND, orig);
780 LABEL_NUSES (orig)++;
782 crtl->uses_pic_offset_table = 1;
785 if (GET_CODE (orig) == SYMBOL_REF)
791 /* Before reload, allocate a temporary register for the intermediate
792 result. This allows the sequence to be deleted when the final
793 result is unused and the insns are trivially dead. */
794 tmp_reg = ((reload_in_progress || reload_completed)
795 ? reg : gen_reg_rtx (Pmode));
797 if (function_label_operand (orig, mode))
799 /* Force function label into memory in word mode. */
800 orig = XEXP (force_const_mem (word_mode, orig), 0);
801 /* Load plabel address from DLT. */
802 emit_move_insn (tmp_reg,
803 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
804 gen_rtx_HIGH (word_mode, orig)));
806 = gen_const_mem (Pmode,
807 gen_rtx_LO_SUM (Pmode, tmp_reg,
808 gen_rtx_UNSPEC (Pmode,
811 emit_move_insn (reg, pic_ref);
812 /* Now load address of function descriptor. */
813 pic_ref = gen_rtx_MEM (Pmode, reg);
817 /* Load symbol reference from DLT. */
818 emit_move_insn (tmp_reg,
819 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
820 gen_rtx_HIGH (word_mode, orig)));
822 = gen_const_mem (Pmode,
823 gen_rtx_LO_SUM (Pmode, tmp_reg,
824 gen_rtx_UNSPEC (Pmode,
829 crtl->uses_pic_offset_table = 1;
830 mark_reg_pointer (reg, BITS_PER_UNIT);
831 insn = emit_move_insn (reg, pic_ref);
833 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
834 set_unique_reg_note (insn, REG_EQUAL, orig);
838 else if (GET_CODE (orig) == CONST)
842 if (GET_CODE (XEXP (orig, 0)) == PLUS
843 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
847 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
849 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
850 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
851 base == reg ? 0 : reg);
853 if (GET_CODE (orig) == CONST_INT)
855 if (INT_14_BITS (orig))
856 return plus_constant (base, INTVAL (orig));
857 orig = force_reg (Pmode, orig);
859 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
860 /* Likewise, should we set special REG_NOTEs here? */
866 static GTY(()) rtx gen_tls_tga;
869 gen_tls_get_addr (void)
872 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
877 hppa_tls_call (rtx arg)
881 ret = gen_reg_rtx (Pmode);
882 emit_library_call_value (gen_tls_get_addr (), ret,
883 LCT_CONST, Pmode, 1, arg, Pmode);
889 legitimize_tls_address (rtx addr)
891 rtx ret, insn, tmp, t1, t2, tp;
892 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
896 case TLS_MODEL_GLOBAL_DYNAMIC:
897 tmp = gen_reg_rtx (Pmode);
899 emit_insn (gen_tgd_load_pic (tmp, addr));
901 emit_insn (gen_tgd_load (tmp, addr));
902 ret = hppa_tls_call (tmp);
905 case TLS_MODEL_LOCAL_DYNAMIC:
906 ret = gen_reg_rtx (Pmode);
907 tmp = gen_reg_rtx (Pmode);
910 emit_insn (gen_tld_load_pic (tmp, addr));
912 emit_insn (gen_tld_load (tmp, addr));
913 t1 = hppa_tls_call (tmp);
916 t2 = gen_reg_rtx (Pmode);
917 emit_libcall_block (insn, t2, t1,
918 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
920 emit_insn (gen_tld_offset_load (ret, addr, t2));
923 case TLS_MODEL_INITIAL_EXEC:
924 tp = gen_reg_rtx (Pmode);
925 tmp = gen_reg_rtx (Pmode);
926 ret = gen_reg_rtx (Pmode);
927 emit_insn (gen_tp_load (tp));
929 emit_insn (gen_tie_load_pic (tmp, addr));
931 emit_insn (gen_tie_load (tmp, addr));
932 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
935 case TLS_MODEL_LOCAL_EXEC:
936 tp = gen_reg_rtx (Pmode);
937 ret = gen_reg_rtx (Pmode);
938 emit_insn (gen_tp_load (tp));
939 emit_insn (gen_tle_load (ret, addr, tp));
949 /* Try machine-dependent ways of modifying an illegitimate address
950 to be legitimate. If we find one, return the new, valid address.
951 This macro is used in only one place: `memory_address' in explow.c.
953 OLDX is the address as it was before break_out_memory_refs was called.
954 In some cases it is useful to look at this to decide what needs to be done.
956 It is always safe for this macro to do nothing. It exists to recognize
957 opportunities to optimize the output.
959 For the PA, transform:
961 memory(X + <large int>)
965 if (<large int> & mask) >= 16
966 Y = (<large int> & ~mask) + mask + 1 Round up.
968 Y = (<large int> & ~mask) Round down.
970 memory (Z + (<large int> - Y));
972 This is for CSE to find several similar references, and only use one Z.
974 X can either be a SYMBOL_REF or REG, but because combine cannot
975 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
976 D will not fit in 14 bits.
978 MODE_FLOAT references allow displacements which fit in 5 bits, so use
981 MODE_INT references allow displacements which fit in 14 bits, so use
984 This relies on the fact that most mode MODE_FLOAT references will use FP
985 registers and most mode MODE_INT references will use integer registers.
986 (In the rare case of an FP register used in an integer MODE, we depend
987 on secondary reloads to clean things up.)
990 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
991 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
992 addressing modes to be used).
994 Put X and Z into registers. Then put the entire expression into
998 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
999 enum machine_mode mode)
1003 /* We need to canonicalize the order of operands in unscaled indexed
1004 addresses since the code that checks if an address is valid doesn't
1005 always try both orders. */
1006 if (!TARGET_NO_SPACE_REGS
1007 && GET_CODE (x) == PLUS
1008 && GET_MODE (x) == Pmode
1009 && REG_P (XEXP (x, 0))
1010 && REG_P (XEXP (x, 1))
1011 && REG_POINTER (XEXP (x, 0))
1012 && !REG_POINTER (XEXP (x, 1)))
1013 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1015 if (PA_SYMBOL_REF_TLS_P (x))
1016 return legitimize_tls_address (x);
1018 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1020 /* Strip off CONST. */
1021 if (GET_CODE (x) == CONST)
1024 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1025 That should always be safe. */
1026 if (GET_CODE (x) == PLUS
1027 && GET_CODE (XEXP (x, 0)) == REG
1028 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1030 rtx reg = force_reg (Pmode, XEXP (x, 1));
1031 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1034 /* Note we must reject symbols which represent function addresses
1035 since the assembler/linker can't handle arithmetic on plabels. */
1036 if (GET_CODE (x) == PLUS
1037 && GET_CODE (XEXP (x, 1)) == CONST_INT
1038 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1039 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1040 || GET_CODE (XEXP (x, 0)) == REG))
1042 rtx int_part, ptr_reg;
1044 int offset = INTVAL (XEXP (x, 1));
1047 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1048 ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);
1050 /* Choose which way to round the offset. Round up if we
1051 are >= halfway to the next boundary. */
1052 if ((offset & mask) >= ((mask + 1) / 2))
1053 newoffset = (offset & ~ mask) + mask + 1;
1055 newoffset = (offset & ~ mask);
1057 /* If the newoffset will not fit in 14 bits (ldo), then
1058 handling this would take 4 or 5 instructions (2 to load
1059 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1060 add the new offset and the SYMBOL_REF.) Combine can
1061 not handle 4->2 or 5->2 combinations, so do not create
1063 if (! VAL_14_BITS_P (newoffset)
1064 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1066 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1069 gen_rtx_HIGH (Pmode, const_part));
1072 gen_rtx_LO_SUM (Pmode,
1073 tmp_reg, const_part));
1077 if (! VAL_14_BITS_P (newoffset))
1078 int_part = force_reg (Pmode, GEN_INT (newoffset));
1080 int_part = GEN_INT (newoffset);
1082 ptr_reg = force_reg (Pmode,
1083 gen_rtx_PLUS (Pmode,
1084 force_reg (Pmode, XEXP (x, 0)),
1087 return plus_constant (ptr_reg, offset - newoffset);
1090 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1092 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1093 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1094 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1095 && (OBJECT_P (XEXP (x, 1))
1096 || GET_CODE (XEXP (x, 1)) == SUBREG)
1097 && GET_CODE (XEXP (x, 1)) != CONST)
1099 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1103 if (GET_CODE (reg1) != REG)
1104 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1106 reg2 = XEXP (XEXP (x, 0), 0);
1107 if (GET_CODE (reg2) != REG)
1108 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1110 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1111 gen_rtx_MULT (Pmode,
1117 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1119 Only do so for floating point modes since this is more speculative
1120 and we lose if it's an integer store. */
1121 if (GET_CODE (x) == PLUS
1122 && GET_CODE (XEXP (x, 0)) == PLUS
1123 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1124 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1125 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1126 && (mode == SFmode || mode == DFmode))
1129 /* First, try and figure out what to use as a base register. */
1130 rtx reg1, reg2, base, idx;
1132 reg1 = XEXP (XEXP (x, 0), 1);
1137 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1138 then emit_move_sequence will turn on REG_POINTER so we'll know
1139 it's a base register below. */
1140 if (GET_CODE (reg1) != REG)
1141 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1143 if (GET_CODE (reg2) != REG)
1144 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1146 /* Figure out what the base and index are. */
1148 if (GET_CODE (reg1) == REG
1149 && REG_POINTER (reg1))
1152 idx = gen_rtx_PLUS (Pmode,
1153 gen_rtx_MULT (Pmode,
1154 XEXP (XEXP (XEXP (x, 0), 0), 0),
1155 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1158 else if (GET_CODE (reg2) == REG
1159 && REG_POINTER (reg2))
1168 /* If the index adds a large constant, try to scale the
1169 constant so that it can be loaded with only one insn. */
1170 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1171 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1172 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1173 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1175 /* Divide the CONST_INT by the scale factor, then add it to A. */
1176 int val = INTVAL (XEXP (idx, 1));
1178 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1179 reg1 = XEXP (XEXP (idx, 0), 0);
1180 if (GET_CODE (reg1) != REG)
1181 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1183 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1185 /* We can now generate a simple scaled indexed address. */
1188 (Pmode, gen_rtx_PLUS (Pmode,
1189 gen_rtx_MULT (Pmode, reg1,
1190 XEXP (XEXP (idx, 0), 1)),
1194 /* If B + C is still a valid base register, then add them. */
1195 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1196 && INTVAL (XEXP (idx, 1)) <= 4096
1197 && INTVAL (XEXP (idx, 1)) >= -4096)
1199 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1202 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1204 reg2 = XEXP (XEXP (idx, 0), 0);
1205 if (GET_CODE (reg2) != CONST_INT)
1206 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1208 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1209 gen_rtx_MULT (Pmode,
1215 /* Get the index into a register, then add the base + index and
1216 return a register holding the result. */
1218 /* First get A into a register. */
1219 reg1 = XEXP (XEXP (idx, 0), 0);
1220 if (GET_CODE (reg1) != REG)
1221 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1223 /* And get B into a register. */
1224 reg2 = XEXP (idx, 1);
1225 if (GET_CODE (reg2) != REG)
1226 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1228 reg1 = force_reg (Pmode,
1229 gen_rtx_PLUS (Pmode,
1230 gen_rtx_MULT (Pmode, reg1,
1231 XEXP (XEXP (idx, 0), 1)),
1234 /* Add the result to our base register and return. */
1235 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1239 /* Uh-oh. We might have an address for x[n-100000]. This needs
1240 special handling to avoid creating an indexed memory address
1241 with x-100000 as the base.
1243 If the constant part is small enough, then it's still safe because
1244 there is a guard page at the beginning and end of the data segment.
1246 Scaled references are common enough that we want to try and rearrange the
1247 terms so that we can use indexing for these addresses too. Only
1248 do the optimization for floatint point modes. */
1250 if (GET_CODE (x) == PLUS
1251 && symbolic_expression_p (XEXP (x, 1)))
1253 /* Ugly. We modify things here so that the address offset specified
1254 by the index expression is computed first, then added to x to form
1255 the entire address. */
1257 rtx regx1, regx2, regy1, regy2, y;
1259 /* Strip off any CONST. */
1261 if (GET_CODE (y) == CONST)
1264 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1266 /* See if this looks like
1267 (plus (mult (reg) (shadd_const))
1268 (const (plus (symbol_ref) (const_int))))
1270 Where const_int is small. In that case the const
1271 expression is a valid pointer for indexing.
1273 If const_int is big, but can be divided evenly by shadd_const
1274 and added to (reg). This allows more scaled indexed addresses. */
1275 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1276 && GET_CODE (XEXP (x, 0)) == MULT
1277 && GET_CODE (XEXP (y, 1)) == CONST_INT
1278 && INTVAL (XEXP (y, 1)) >= -4096
1279 && INTVAL (XEXP (y, 1)) <= 4095
1280 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1281 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1283 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1287 if (GET_CODE (reg1) != REG)
1288 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1290 reg2 = XEXP (XEXP (x, 0), 0);
1291 if (GET_CODE (reg2) != REG)
1292 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1294 return force_reg (Pmode,
1295 gen_rtx_PLUS (Pmode,
1296 gen_rtx_MULT (Pmode,
1301 else if ((mode == DFmode || mode == SFmode)
1302 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1303 && GET_CODE (XEXP (x, 0)) == MULT
1304 && GET_CODE (XEXP (y, 1)) == CONST_INT
1305 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1306 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1307 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1310 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1311 / INTVAL (XEXP (XEXP (x, 0), 1))));
1312 regx2 = XEXP (XEXP (x, 0), 0);
1313 if (GET_CODE (regx2) != REG)
1314 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1315 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1319 gen_rtx_PLUS (Pmode,
1320 gen_rtx_MULT (Pmode, regx2,
1321 XEXP (XEXP (x, 0), 1)),
1322 force_reg (Pmode, XEXP (y, 0))));
1324 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1325 && INTVAL (XEXP (y, 1)) >= -4096
1326 && INTVAL (XEXP (y, 1)) <= 4095)
1328 /* This is safe because of the guard page at the
1329 beginning and end of the data space. Just
1330 return the original address. */
1335 /* Doesn't look like one we can optimize. */
1336 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1337 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1338 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1339 regx1 = force_reg (Pmode,
1340 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1342 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1350 /* Implement the TARGET_REGISTER_MOVE_COST hook.
1352 Compute extra cost of moving data between one register class
1355 Make moves from SAR so expensive they should never happen. We used to
1356 have 0xffff here, but that generates overflow in rare cases.
1358 Copies involving a FP register and a non-FP register are relatively
1359 expensive because they must go through memory.
1361 Other copies are reasonably cheap. */
1364 hppa_register_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
1365 reg_class_t from, reg_class_t to)
1367 if (from == SHIFT_REGS)
1369 else if ((FP_REG_CLASS_P (from) && ! FP_REG_CLASS_P (to))
1370 || (FP_REG_CLASS_P (to) && ! FP_REG_CLASS_P (from)))
1376 /* For the HPPA, REG and REG+CONST is cost 0
1377 and addresses involving symbolic constants are cost 2.
1379 PIC addresses are very expensive.
1381 It is no coincidence that this has the same structure
1382 as GO_IF_LEGITIMATE_ADDRESS. */
1385 hppa_address_cost (rtx X,
1386 bool speed ATTRIBUTE_UNUSED)
1388 switch (GET_CODE (X))
1401 /* Compute a (partial) cost for rtx X. Return true if the complete
1402 cost has been computed, and false if subexpressions should be
1403 scanned. In either case, *TOTAL contains the cost result. */
1406 hppa_rtx_costs (rtx x, int code, int outer_code, int *total,
1407 bool speed ATTRIBUTE_UNUSED)
1412 if (INTVAL (x) == 0)
1414 else if (INT_14_BITS (x))
1431 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1432 && outer_code != SET)
1439 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1440 *total = COSTS_N_INSNS (3);
1441 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1442 *total = COSTS_N_INSNS (8);
1444 *total = COSTS_N_INSNS (20);
1448 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1450 *total = COSTS_N_INSNS (14);
1458 *total = COSTS_N_INSNS (60);
1461 case PLUS: /* this includes shNadd insns */
1463 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1464 *total = COSTS_N_INSNS (3);
1466 *total = COSTS_N_INSNS (1);
1472 *total = COSTS_N_INSNS (1);
1480 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1481 new rtx with the correct mode. */
1483 force_mode (enum machine_mode mode, rtx orig)
1485 if (mode == GET_MODE (orig))
1488 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1490 return gen_rtx_REG (mode, REGNO (orig));
1493 /* Return 1 if *X is a thread-local symbol. */
1496 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1498 return PA_SYMBOL_REF_TLS_P (*x);
1501 /* Return 1 if X contains a thread-local symbol. */
1504 pa_tls_referenced_p (rtx x)
1506 if (!TARGET_HAVE_TLS)
1509 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1512 /* Emit insns to move operands[1] into operands[0].
1514 Return 1 if we have written out everything that needs to be done to
1515 do the move. Otherwise, return 0 and the caller will emit the move
1518 Note SCRATCH_REG may not be in the proper mode depending on how it
1519 will be used. This routine is responsible for creating a new copy
1520 of SCRATCH_REG in the proper mode. */
1523 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1525 register rtx operand0 = operands[0];
1526 register rtx operand1 = operands[1];
1529 /* We can only handle indexed addresses in the destination operand
1530 of floating point stores. Thus, we need to break out indexed
1531 addresses from the destination operand. */
1532 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1534 gcc_assert (can_create_pseudo_p ());
1536 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1537 operand0 = replace_equiv_address (operand0, tem);
1540 /* On targets with non-equivalent space registers, break out unscaled
1541 indexed addresses from the source operand before the final CSE.
1542 We have to do this because the REG_POINTER flag is not correctly
1543 carried through various optimization passes and CSE may substitute
1544 a pseudo without the pointer set for one with the pointer set. As
1545 a result, we loose various opportunities to create insns with
1546 unscaled indexed addresses. */
1547 if (!TARGET_NO_SPACE_REGS
1548 && !cse_not_expected
1549 && GET_CODE (operand1) == MEM
1550 && GET_CODE (XEXP (operand1, 0)) == PLUS
1551 && REG_P (XEXP (XEXP (operand1, 0), 0))
1552 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1554 = replace_equiv_address (operand1,
1555 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1558 && reload_in_progress && GET_CODE (operand0) == REG
1559 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1560 operand0 = reg_equiv_mem[REGNO (operand0)];
1561 else if (scratch_reg
1562 && reload_in_progress && GET_CODE (operand0) == SUBREG
1563 && GET_CODE (SUBREG_REG (operand0)) == REG
1564 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1566 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1567 the code which tracks sets/uses for delete_output_reload. */
1568 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1569 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1570 SUBREG_BYTE (operand0));
1571 operand0 = alter_subreg (&temp);
1575 && reload_in_progress && GET_CODE (operand1) == REG
1576 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1577 operand1 = reg_equiv_mem[REGNO (operand1)];
1578 else if (scratch_reg
1579 && reload_in_progress && GET_CODE (operand1) == SUBREG
1580 && GET_CODE (SUBREG_REG (operand1)) == REG
1581 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1583 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1584 the code which tracks sets/uses for delete_output_reload. */
1585 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1586 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1587 SUBREG_BYTE (operand1));
1588 operand1 = alter_subreg (&temp);
1591 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1592 && ((tem = find_replacement (&XEXP (operand0, 0)))
1593 != XEXP (operand0, 0)))
1594 operand0 = replace_equiv_address (operand0, tem);
1596 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1597 && ((tem = find_replacement (&XEXP (operand1, 0)))
1598 != XEXP (operand1, 0)))
1599 operand1 = replace_equiv_address (operand1, tem);
1601 /* Handle secondary reloads for loads/stores of FP registers from
1602 REG+D addresses where D does not fit in 5 or 14 bits, including
1603 (subreg (mem (addr))) cases. */
1605 && fp_reg_operand (operand0, mode)
1606 && ((GET_CODE (operand1) == MEM
1607 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1608 XEXP (operand1, 0)))
1609 || ((GET_CODE (operand1) == SUBREG
1610 && GET_CODE (XEXP (operand1, 0)) == MEM
1611 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1613 XEXP (XEXP (operand1, 0), 0))))))
1615 if (GET_CODE (operand1) == SUBREG)
1616 operand1 = XEXP (operand1, 0);
1618 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1619 it in WORD_MODE regardless of what mode it was originally given
1621 scratch_reg = force_mode (word_mode, scratch_reg);
1623 /* D might not fit in 14 bits either; for such cases load D into
1625 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1627 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1628 emit_move_insn (scratch_reg,
1629 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1631 XEXP (XEXP (operand1, 0), 0),
1635 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1636 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1637 replace_equiv_address (operand1, scratch_reg)));
1640 else if (scratch_reg
1641 && fp_reg_operand (operand1, mode)
1642 && ((GET_CODE (operand0) == MEM
1643 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1645 XEXP (operand0, 0)))
1646 || ((GET_CODE (operand0) == SUBREG)
1647 && GET_CODE (XEXP (operand0, 0)) == MEM
1648 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1650 XEXP (XEXP (operand0, 0), 0)))))
1652 if (GET_CODE (operand0) == SUBREG)
1653 operand0 = XEXP (operand0, 0);
1655 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1656 it in WORD_MODE regardless of what mode it was originally given
1658 scratch_reg = force_mode (word_mode, scratch_reg);
1660 /* D might not fit in 14 bits either; for such cases load D into
1662 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1664 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1665 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1668 XEXP (XEXP (operand0, 0),
1673 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1674 emit_insn (gen_rtx_SET (VOIDmode,
1675 replace_equiv_address (operand0, scratch_reg),
1679 /* Handle secondary reloads for loads of FP registers from constant
1680 expressions by forcing the constant into memory.
1682 Use scratch_reg to hold the address of the memory location.
1684 The proper fix is to change TARGET_PREFERRED_RELOAD_CLASS to return
1685 NO_REGS when presented with a const_int and a register class
1686 containing only FP registers. Doing so unfortunately creates
1687 more problems than it solves. Fix this for 2.5. */
1688 else if (scratch_reg
1689 && CONSTANT_P (operand1)
1690 && fp_reg_operand (operand0, mode))
1692 rtx const_mem, xoperands[2];
1694 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1695 it in WORD_MODE regardless of what mode it was originally given
1697 scratch_reg = force_mode (word_mode, scratch_reg);
1699 /* Force the constant into memory and put the address of the
1700 memory location into scratch_reg. */
1701 const_mem = force_const_mem (mode, operand1);
1702 xoperands[0] = scratch_reg;
1703 xoperands[1] = XEXP (const_mem, 0);
1704 emit_move_sequence (xoperands, Pmode, 0);
1706 /* Now load the destination register. */
1707 emit_insn (gen_rtx_SET (mode, operand0,
1708 replace_equiv_address (const_mem, scratch_reg)));
1711 /* Handle secondary reloads for SAR. These occur when trying to load
1712 the SAR from memory, FP register, or with a constant. */
1713 else if (scratch_reg
1714 && GET_CODE (operand0) == REG
1715 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1716 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1717 && (GET_CODE (operand1) == MEM
1718 || GET_CODE (operand1) == CONST_INT
1719 || (GET_CODE (operand1) == REG
1720 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1722 /* D might not fit in 14 bits either; for such cases load D into
1724 if (GET_CODE (operand1) == MEM
1725 && !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
1727 /* We are reloading the address into the scratch register, so we
1728 want to make sure the scratch register is a full register. */
1729 scratch_reg = force_mode (word_mode, scratch_reg);
1731 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1732 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1735 XEXP (XEXP (operand1, 0),
1739 /* Now we are going to load the scratch register from memory,
1740 we want to load it in the same width as the original MEM,
1741 which must be the same as the width of the ultimate destination,
1743 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1745 emit_move_insn (scratch_reg,
1746 replace_equiv_address (operand1, scratch_reg));
1750 /* We want to load the scratch register using the same mode as
1751 the ultimate destination. */
1752 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1754 emit_move_insn (scratch_reg, operand1);
1757 /* And emit the insn to set the ultimate destination. We know that
1758 the scratch register has the same mode as the destination at this
1760 emit_move_insn (operand0, scratch_reg);
1763 /* Handle the most common case: storing into a register. */
1764 else if (register_operand (operand0, mode))
1766 if (register_operand (operand1, mode)
1767 || (GET_CODE (operand1) == CONST_INT
1768 && cint_ok_for_move (INTVAL (operand1)))
1769 || (operand1 == CONST0_RTX (mode))
1770 || (GET_CODE (operand1) == HIGH
1771 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1772 /* Only `general_operands' can come here, so MEM is ok. */
1773 || GET_CODE (operand1) == MEM)
1775 /* Various sets are created during RTL generation which don't
1776 have the REG_POINTER flag correctly set. After the CSE pass,
1777 instruction recognition can fail if we don't consistently
1778 set this flag when performing register copies. This should
1779 also improve the opportunities for creating insns that use
1780 unscaled indexing. */
1781 if (REG_P (operand0) && REG_P (operand1))
1783 if (REG_POINTER (operand1)
1784 && !REG_POINTER (operand0)
1785 && !HARD_REGISTER_P (operand0))
1786 copy_reg_pointer (operand0, operand1);
1789 /* When MEMs are broken out, the REG_POINTER flag doesn't
1790 get set. In some cases, we can set the REG_POINTER flag
1791 from the declaration for the MEM. */
1792 if (REG_P (operand0)
1793 && GET_CODE (operand1) == MEM
1794 && !REG_POINTER (operand0))
1796 tree decl = MEM_EXPR (operand1);
1798 /* Set the register pointer flag and register alignment
1799 if the declaration for this memory reference is a
1805 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1807 if (TREE_CODE (decl) == COMPONENT_REF)
1808 decl = TREE_OPERAND (decl, 1);
1810 type = TREE_TYPE (decl);
1811 type = strip_array_types (type);
1813 if (POINTER_TYPE_P (type))
1817 type = TREE_TYPE (type);
1818 /* Using TYPE_ALIGN_OK is rather conservative as
1819 only the ada frontend actually sets it. */
1820 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1822 mark_reg_pointer (operand0, align);
1827 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1831 else if (GET_CODE (operand0) == MEM)
1833 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1834 && !(reload_in_progress || reload_completed))
1836 rtx temp = gen_reg_rtx (DFmode);
1838 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1839 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1842 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1844 /* Run this case quickly. */
1845 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1848 if (! (reload_in_progress || reload_completed))
1850 operands[0] = validize_mem (operand0);
1851 operands[1] = operand1 = force_reg (mode, operand1);
1855 /* Simplify the source if we need to.
1856 Note we do have to handle function labels here, even though we do
1857 not consider them legitimate constants. Loop optimizations can
1858 call the emit_move_xxx with one as a source. */
1859 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1860 || function_label_operand (operand1, mode)
1861 || (GET_CODE (operand1) == HIGH
1862 && symbolic_operand (XEXP (operand1, 0), mode)))
1866 if (GET_CODE (operand1) == HIGH)
1869 operand1 = XEXP (operand1, 0);
1871 if (symbolic_operand (operand1, mode))
1873 /* Argh. The assembler and linker can't handle arithmetic
1876 So we force the plabel into memory, load operand0 from
1877 the memory location, then add in the constant part. */
1878 if ((GET_CODE (operand1) == CONST
1879 && GET_CODE (XEXP (operand1, 0)) == PLUS
1880 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1881 || function_label_operand (operand1, mode))
1883 rtx temp, const_part;
1885 /* Figure out what (if any) scratch register to use. */
1886 if (reload_in_progress || reload_completed)
1888 scratch_reg = scratch_reg ? scratch_reg : operand0;
1889 /* SCRATCH_REG will hold an address and maybe the actual
1890 data. We want it in WORD_MODE regardless of what mode it
1891 was originally given to us. */
1892 scratch_reg = force_mode (word_mode, scratch_reg);
1895 scratch_reg = gen_reg_rtx (Pmode);
1897 if (GET_CODE (operand1) == CONST)
1899 /* Save away the constant part of the expression. */
1900 const_part = XEXP (XEXP (operand1, 0), 1);
1901 gcc_assert (GET_CODE (const_part) == CONST_INT);
1903 /* Force the function label into memory. */
1904 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1908 /* No constant part. */
1909 const_part = NULL_RTX;
1911 /* Force the function label into memory. */
1912 temp = force_const_mem (mode, operand1);
1916 /* Get the address of the memory location. PIC-ify it if
1918 temp = XEXP (temp, 0);
1920 temp = legitimize_pic_address (temp, mode, scratch_reg);
1922 /* Put the address of the memory location into our destination
1925 emit_move_sequence (operands, mode, scratch_reg);
1927 /* Now load from the memory location into our destination
1929 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1930 emit_move_sequence (operands, mode, scratch_reg);
1932 /* And add back in the constant part. */
1933 if (const_part != NULL_RTX)
1934 expand_inc (operand0, const_part);
1943 if (reload_in_progress || reload_completed)
1945 temp = scratch_reg ? scratch_reg : operand0;
1946 /* TEMP will hold an address and maybe the actual
1947 data. We want it in WORD_MODE regardless of what mode it
1948 was originally given to us. */
1949 temp = force_mode (word_mode, temp);
1952 temp = gen_reg_rtx (Pmode);
1954 /* (const (plus (symbol) (const_int))) must be forced to
1955 memory during/after reload if the const_int will not fit
1957 if (GET_CODE (operand1) == CONST
1958 && GET_CODE (XEXP (operand1, 0)) == PLUS
1959 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1960 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1961 && (reload_completed || reload_in_progress)
1964 rtx const_mem = force_const_mem (mode, operand1);
1965 operands[1] = legitimize_pic_address (XEXP (const_mem, 0),
1967 operands[1] = replace_equiv_address (const_mem, operands[1]);
1968 emit_move_sequence (operands, mode, temp);
1972 operands[1] = legitimize_pic_address (operand1, mode, temp);
1973 if (REG_P (operand0) && REG_P (operands[1]))
1974 copy_reg_pointer (operand0, operands[1]);
1975 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1978 /* On the HPPA, references to data space are supposed to use dp,
1979 register 27, but showing it in the RTL inhibits various cse
1980 and loop optimizations. */
1985 if (reload_in_progress || reload_completed)
1987 temp = scratch_reg ? scratch_reg : operand0;
1988 /* TEMP will hold an address and maybe the actual
1989 data. We want it in WORD_MODE regardless of what mode it
1990 was originally given to us. */
1991 temp = force_mode (word_mode, temp);
1994 temp = gen_reg_rtx (mode);
1996 /* Loading a SYMBOL_REF into a register makes that register
1997 safe to be used as the base in an indexed address.
1999 Don't mark hard registers though. That loses. */
2000 if (GET_CODE (operand0) == REG
2001 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2002 mark_reg_pointer (operand0, BITS_PER_UNIT);
2003 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2004 mark_reg_pointer (temp, BITS_PER_UNIT);
2007 set = gen_rtx_SET (mode, operand0, temp);
2009 set = gen_rtx_SET (VOIDmode,
2011 gen_rtx_LO_SUM (mode, temp, operand1));
2013 emit_insn (gen_rtx_SET (VOIDmode,
2015 gen_rtx_HIGH (mode, operand1)));
2021 else if (pa_tls_referenced_p (operand1))
2026 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
2028 addend = XEXP (XEXP (tmp, 0), 1);
2029 tmp = XEXP (XEXP (tmp, 0), 0);
2032 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
2033 tmp = legitimize_tls_address (tmp);
2036 tmp = gen_rtx_PLUS (mode, tmp, addend);
2037 tmp = force_operand (tmp, operands[0]);
2041 else if (GET_CODE (operand1) != CONST_INT
2042 || !cint_ok_for_move (INTVAL (operand1)))
2046 HOST_WIDE_INT value = 0;
2047 HOST_WIDE_INT insv = 0;
2050 if (GET_CODE (operand1) == CONST_INT)
2051 value = INTVAL (operand1);
2054 && GET_CODE (operand1) == CONST_INT
2055 && HOST_BITS_PER_WIDE_INT > 32
2056 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2060 /* Extract the low order 32 bits of the value and sign extend.
2061 If the new value is the same as the original value, we can
2062 can use the original value as-is. If the new value is
2063 different, we use it and insert the most-significant 32-bits
2064 of the original value into the final result. */
2065 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2066 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2069 #if HOST_BITS_PER_WIDE_INT > 32
2070 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2074 operand1 = GEN_INT (nval);
2078 if (reload_in_progress || reload_completed)
2079 temp = scratch_reg ? scratch_reg : operand0;
2081 temp = gen_reg_rtx (mode);
2083 /* We don't directly split DImode constants on 32-bit targets
2084 because PLUS uses an 11-bit immediate and the insn sequence
2085 generated is not as efficient as the one using HIGH/LO_SUM. */
2086 if (GET_CODE (operand1) == CONST_INT
2087 && GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
2088 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2091 /* Directly break constant into high and low parts. This
2092 provides better optimization opportunities because various
2093 passes recognize constants split with PLUS but not LO_SUM.
2094 We use a 14-bit signed low part except when the addition
2095 of 0x4000 to the high part might change the sign of the
2097 HOST_WIDE_INT low = value & 0x3fff;
2098 HOST_WIDE_INT high = value & ~ 0x3fff;
2102 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2110 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2111 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2115 emit_insn (gen_rtx_SET (VOIDmode, temp,
2116 gen_rtx_HIGH (mode, operand1)));
2117 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2120 insn = emit_move_insn (operands[0], operands[1]);
2122 /* Now insert the most significant 32 bits of the value
2123 into the register. When we don't have a second register
2124 available, it could take up to nine instructions to load
2125 a 64-bit integer constant. Prior to reload, we force
2126 constants that would take more than three instructions
2127 to load to the constant pool. During and after reload,
2128 we have to handle all possible values. */
2131 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2132 register and the value to be inserted is outside the
2133 range that can be loaded with three depdi instructions. */
2134 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2136 operand1 = GEN_INT (insv);
2138 emit_insn (gen_rtx_SET (VOIDmode, temp,
2139 gen_rtx_HIGH (mode, operand1)));
2140 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2141 emit_insn (gen_insv (operand0, GEN_INT (32),
2146 int len = 5, pos = 27;
2148 /* Insert the bits using the depdi instruction. */
2151 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2152 HOST_WIDE_INT sign = v5 < 0;
2154 /* Left extend the insertion. */
2155 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2156 while (pos > 0 && (insv & 1) == sign)
2158 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2163 emit_insn (gen_insv (operand0, GEN_INT (len),
2164 GEN_INT (pos), GEN_INT (v5)));
2166 len = pos > 0 && pos < 5 ? pos : 5;
2172 set_unique_reg_note (insn, REG_EQUAL, op1);
2177 /* Now have insn-emit do whatever it normally does. */
2181 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2182 it will need a link/runtime reloc). */
2185 reloc_needed (tree exp)
2189 switch (TREE_CODE (exp))
2194 case POINTER_PLUS_EXPR:
2197 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2198 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2202 case NON_LVALUE_EXPR:
2203 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2209 unsigned HOST_WIDE_INT ix;
2211 FOR_EACH_CONSTRUCTOR_VALUE (CONSTRUCTOR_ELTS (exp), ix, value)
2213 reloc |= reloc_needed (value);
2226 /* Does operand (which is a symbolic_operand) live in text space?
2227 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2231 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2233 if (GET_CODE (operand) == CONST)
2234 operand = XEXP (XEXP (operand, 0), 0);
2237 if (GET_CODE (operand) == SYMBOL_REF)
2238 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2242 if (GET_CODE (operand) == SYMBOL_REF)
2243 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2249 /* Return the best assembler insn template
2250 for moving operands[1] into operands[0] as a fullword. */
2252 singlemove_string (rtx *operands)
2254 HOST_WIDE_INT intval;
2256 if (GET_CODE (operands[0]) == MEM)
2257 return "stw %r1,%0";
2258 if (GET_CODE (operands[1]) == MEM)
2260 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2265 gcc_assert (GET_MODE (operands[1]) == SFmode);
2267 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2269 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2270 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2272 operands[1] = GEN_INT (i);
2273 /* Fall through to CONST_INT case. */
2275 if (GET_CODE (operands[1]) == CONST_INT)
2277 intval = INTVAL (operands[1]);
2279 if (VAL_14_BITS_P (intval))
2281 else if ((intval & 0x7ff) == 0)
2282 return "ldil L'%1,%0";
2283 else if (zdepi_cint_p (intval))
2284 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2286 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2288 return "copy %1,%0";
2292 /* Compute position (in OP[1]) and width (in OP[2])
2293 useful for copying IMM to a register using the zdepi
2294 instructions. Store the immediate value to insert in OP[0]. */
2296 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2300 /* Find the least significant set bit in IMM. */
2301 for (lsb = 0; lsb < 32; lsb++)
2308 /* Choose variants based on *sign* of the 5-bit field. */
2309 if ((imm & 0x10) == 0)
2310 len = (lsb <= 28) ? 4 : 32 - lsb;
2313 /* Find the width of the bitstring in IMM. */
2314 for (len = 5; len < 32 - lsb; len++)
2316 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2320 /* Sign extend IMM as a 5-bit value. */
2321 imm = (imm & 0xf) - 0x10;
2329 /* Compute position (in OP[1]) and width (in OP[2])
2330 useful for copying IMM to a register using the depdi,z
2331 instructions. Store the immediate value to insert in OP[0]. */
2333 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2335 int lsb, len, maxlen;
2337 maxlen = MIN (HOST_BITS_PER_WIDE_INT, 64);
2339 /* Find the least significant set bit in IMM. */
2340 for (lsb = 0; lsb < maxlen; lsb++)
2347 /* Choose variants based on *sign* of the 5-bit field. */
2348 if ((imm & 0x10) == 0)
2349 len = (lsb <= maxlen - 4) ? 4 : maxlen - lsb;
2352 /* Find the width of the bitstring in IMM. */
2353 for (len = 5; len < maxlen - lsb; len++)
2355 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2359 /* Extend length if host is narrow and IMM is negative. */
2360 if (HOST_BITS_PER_WIDE_INT == 32 && len == maxlen - lsb)
2363 /* Sign extend IMM as a 5-bit value. */
2364 imm = (imm & 0xf) - 0x10;
2372 /* Output assembler code to perform a doubleword move insn
2373 with operands OPERANDS. */
2376 output_move_double (rtx *operands)
2378 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2380 rtx addreg0 = 0, addreg1 = 0;
2382 /* First classify both operands. */
2384 if (REG_P (operands[0]))
2386 else if (offsettable_memref_p (operands[0]))
2388 else if (GET_CODE (operands[0]) == MEM)
2393 if (REG_P (operands[1]))
2395 else if (CONSTANT_P (operands[1]))
2397 else if (offsettable_memref_p (operands[1]))
2399 else if (GET_CODE (operands[1]) == MEM)
2404 /* Check for the cases that the operand constraints are not
2405 supposed to allow to happen. */
2406 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2408 /* Handle copies between general and floating registers. */
2410 if (optype0 == REGOP && optype1 == REGOP
2411 && FP_REG_P (operands[0]) ^ FP_REG_P (operands[1]))
2413 if (FP_REG_P (operands[0]))
2415 output_asm_insn ("{stws|stw} %1,-16(%%sp)", operands);
2416 output_asm_insn ("{stws|stw} %R1,-12(%%sp)", operands);
2417 return "{fldds|fldd} -16(%%sp),%0";
2421 output_asm_insn ("{fstds|fstd} %1,-16(%%sp)", operands);
2422 output_asm_insn ("{ldws|ldw} -16(%%sp),%0", operands);
2423 return "{ldws|ldw} -12(%%sp),%R0";
2427 /* Handle auto decrementing and incrementing loads and stores
2428 specifically, since the structure of the function doesn't work
2429 for them without major modification. Do it better when we learn
2430 this port about the general inc/dec addressing of PA.
2431 (This was written by tege. Chide him if it doesn't work.) */
2433 if (optype0 == MEMOP)
2435 /* We have to output the address syntax ourselves, since print_operand
2436 doesn't deal with the addresses we want to use. Fix this later. */
2438 rtx addr = XEXP (operands[0], 0);
2439 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2441 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2443 operands[0] = XEXP (addr, 0);
2444 gcc_assert (GET_CODE (operands[1]) == REG
2445 && GET_CODE (operands[0]) == REG);
2447 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2449 /* No overlap between high target register and address
2450 register. (We do this in a non-obvious way to
2451 save a register file writeback) */
2452 if (GET_CODE (addr) == POST_INC)
2453 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2454 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2456 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2458 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2460 operands[0] = XEXP (addr, 0);
2461 gcc_assert (GET_CODE (operands[1]) == REG
2462 && GET_CODE (operands[0]) == REG);
2464 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2465 /* No overlap between high target register and address
2466 register. (We do this in a non-obvious way to save a
2467 register file writeback) */
2468 if (GET_CODE (addr) == PRE_INC)
2469 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2470 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2473 if (optype1 == MEMOP)
2475 /* We have to output the address syntax ourselves, since print_operand
2476 doesn't deal with the addresses we want to use. Fix this later. */
2478 rtx addr = XEXP (operands[1], 0);
2479 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2481 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2483 operands[1] = XEXP (addr, 0);
2484 gcc_assert (GET_CODE (operands[0]) == REG
2485 && GET_CODE (operands[1]) == REG);
2487 if (!reg_overlap_mentioned_p (high_reg, addr))
2489 /* No overlap between high target register and address
2490 register. (We do this in a non-obvious way to
2491 save a register file writeback) */
2492 if (GET_CODE (addr) == POST_INC)
2493 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2494 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2498 /* This is an undefined situation. We should load into the
2499 address register *and* update that register. Probably
2500 we don't need to handle this at all. */
2501 if (GET_CODE (addr) == POST_INC)
2502 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2503 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2506 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2508 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2510 operands[1] = XEXP (addr, 0);
2511 gcc_assert (GET_CODE (operands[0]) == REG
2512 && GET_CODE (operands[1]) == REG);
2514 if (!reg_overlap_mentioned_p (high_reg, addr))
2516 /* No overlap between high target register and address
2517 register. (We do this in a non-obvious way to
2518 save a register file writeback) */
2519 if (GET_CODE (addr) == PRE_INC)
2520 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2521 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2525 /* This is an undefined situation. We should load into the
2526 address register *and* update that register. Probably
2527 we don't need to handle this at all. */
2528 if (GET_CODE (addr) == PRE_INC)
2529 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2530 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2533 else if (GET_CODE (addr) == PLUS
2534 && GET_CODE (XEXP (addr, 0)) == MULT)
2537 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2539 if (!reg_overlap_mentioned_p (high_reg, addr))
2541 xoperands[0] = high_reg;
2542 xoperands[1] = XEXP (addr, 1);
2543 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2544 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2545 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2547 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2551 xoperands[0] = high_reg;
2552 xoperands[1] = XEXP (addr, 1);
2553 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2554 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2555 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2557 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2562 /* If an operand is an unoffsettable memory ref, find a register
2563 we can increment temporarily to make it refer to the second word. */
2565 if (optype0 == MEMOP)
2566 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2568 if (optype1 == MEMOP)
2569 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2571 /* Ok, we can do one word at a time.
2572 Normally we do the low-numbered word first.
2574 In either case, set up in LATEHALF the operands to use
2575 for the high-numbered word and in some cases alter the
2576 operands in OPERANDS to be suitable for the low-numbered word. */
2578 if (optype0 == REGOP)
2579 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2580 else if (optype0 == OFFSOP)
2581 latehalf[0] = adjust_address (operands[0], SImode, 4);
2583 latehalf[0] = operands[0];
2585 if (optype1 == REGOP)
2586 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2587 else if (optype1 == OFFSOP)
2588 latehalf[1] = adjust_address (operands[1], SImode, 4);
2589 else if (optype1 == CNSTOP)
2590 split_double (operands[1], &operands[1], &latehalf[1]);
2592 latehalf[1] = operands[1];
2594 /* If the first move would clobber the source of the second one,
2595 do them in the other order.
2597 This can happen in two cases:
2599 mem -> register where the first half of the destination register
2600 is the same register used in the memory's address. Reload
2601 can create such insns.
2603 mem in this case will be either register indirect or register
2604 indirect plus a valid offset.
2606 register -> register move where REGNO(dst) == REGNO(src + 1)
2607 someone (Tim/Tege?) claimed this can happen for parameter loads.
2609 Handle mem -> register case first. */
2610 if (optype0 == REGOP
2611 && (optype1 == MEMOP || optype1 == OFFSOP)
2612 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2615 /* Do the late half first. */
2617 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2618 output_asm_insn (singlemove_string (latehalf), latehalf);
2622 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2623 return singlemove_string (operands);
2626 /* Now handle register -> register case. */
2627 if (optype0 == REGOP && optype1 == REGOP
2628 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2630 output_asm_insn (singlemove_string (latehalf), latehalf);
2631 return singlemove_string (operands);
2634 /* Normal case: do the two words, low-numbered first. */
2636 output_asm_insn (singlemove_string (operands), operands);
2638 /* Make any unoffsettable addresses point at high-numbered word. */
2640 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2642 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2645 output_asm_insn (singlemove_string (latehalf), latehalf);
2647 /* Undo the adds we just did. */
2649 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2651 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2657 output_fp_move_double (rtx *operands)
2659 if (FP_REG_P (operands[0]))
2661 if (FP_REG_P (operands[1])
2662 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2663 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2665 output_asm_insn ("fldd%F1 %1,%0", operands);
2667 else if (FP_REG_P (operands[1]))
2669 output_asm_insn ("fstd%F0 %1,%0", operands);
2675 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2677 /* This is a pain. You have to be prepared to deal with an
2678 arbitrary address here including pre/post increment/decrement.
2680 so avoid this in the MD. */
2681 gcc_assert (GET_CODE (operands[0]) == REG);
2683 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2684 xoperands[0] = operands[0];
2685 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2690 /* Return a REG that occurs in ADDR with coefficient 1.
2691 ADDR can be effectively incremented by incrementing REG. */
2694 find_addr_reg (rtx addr)
2696 while (GET_CODE (addr) == PLUS)
2698 if (GET_CODE (XEXP (addr, 0)) == REG)
2699 addr = XEXP (addr, 0);
2700 else if (GET_CODE (XEXP (addr, 1)) == REG)
2701 addr = XEXP (addr, 1);
2702 else if (CONSTANT_P (XEXP (addr, 0)))
2703 addr = XEXP (addr, 1);
2704 else if (CONSTANT_P (XEXP (addr, 1)))
2705 addr = XEXP (addr, 0);
2709 gcc_assert (GET_CODE (addr) == REG);
2713 /* Emit code to perform a block move.
2715 OPERANDS[0] is the destination pointer as a REG, clobbered.
2716 OPERANDS[1] is the source pointer as a REG, clobbered.
2717 OPERANDS[2] is a register for temporary storage.
2718 OPERANDS[3] is a register for temporary storage.
2719 OPERANDS[4] is the size as a CONST_INT
2720 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2721 OPERANDS[6] is another temporary register. */
2724 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2726 int align = INTVAL (operands[5]);
2727 unsigned long n_bytes = INTVAL (operands[4]);
2729 /* We can't move more than a word at a time because the PA
2730 has no longer integer move insns. (Could use fp mem ops?) */
2731 if (align > (TARGET_64BIT ? 8 : 4))
2732 align = (TARGET_64BIT ? 8 : 4);
2734 /* Note that we know each loop below will execute at least twice
2735 (else we would have open-coded the copy). */
2739 /* Pre-adjust the loop counter. */
2740 operands[4] = GEN_INT (n_bytes - 16);
2741 output_asm_insn ("ldi %4,%2", operands);
2744 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2745 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2746 output_asm_insn ("std,ma %3,8(%0)", operands);
2747 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2748 output_asm_insn ("std,ma %6,8(%0)", operands);
2750 /* Handle the residual. There could be up to 7 bytes of
2751 residual to copy! */
2752 if (n_bytes % 16 != 0)
2754 operands[4] = GEN_INT (n_bytes % 8);
2755 if (n_bytes % 16 >= 8)
2756 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2757 if (n_bytes % 8 != 0)
2758 output_asm_insn ("ldd 0(%1),%6", operands);
2759 if (n_bytes % 16 >= 8)
2760 output_asm_insn ("std,ma %3,8(%0)", operands);
2761 if (n_bytes % 8 != 0)
2762 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2767 /* Pre-adjust the loop counter. */
2768 operands[4] = GEN_INT (n_bytes - 8);
2769 output_asm_insn ("ldi %4,%2", operands);
2772 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2773 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2774 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2775 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2776 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2778 /* Handle the residual. There could be up to 7 bytes of
2779 residual to copy! */
2780 if (n_bytes % 8 != 0)
2782 operands[4] = GEN_INT (n_bytes % 4);
2783 if (n_bytes % 8 >= 4)
2784 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2785 if (n_bytes % 4 != 0)
2786 output_asm_insn ("ldw 0(%1),%6", operands);
2787 if (n_bytes % 8 >= 4)
2788 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2789 if (n_bytes % 4 != 0)
2790 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2795 /* Pre-adjust the loop counter. */
2796 operands[4] = GEN_INT (n_bytes - 4);
2797 output_asm_insn ("ldi %4,%2", operands);
2800 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2801 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2802 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2803 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2804 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2806 /* Handle the residual. */
2807 if (n_bytes % 4 != 0)
2809 if (n_bytes % 4 >= 2)
2810 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2811 if (n_bytes % 2 != 0)
2812 output_asm_insn ("ldb 0(%1),%6", operands);
2813 if (n_bytes % 4 >= 2)
2814 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2815 if (n_bytes % 2 != 0)
2816 output_asm_insn ("stb %6,0(%0)", operands);
2821 /* Pre-adjust the loop counter. */
2822 operands[4] = GEN_INT (n_bytes - 2);
2823 output_asm_insn ("ldi %4,%2", operands);
2826 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2827 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2828 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2829 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2830 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2832 /* Handle the residual. */
2833 if (n_bytes % 2 != 0)
2835 output_asm_insn ("ldb 0(%1),%3", operands);
2836 output_asm_insn ("stb %3,0(%0)", operands);
2845 /* Count the number of insns necessary to handle this block move.
2847 Basic structure is the same as emit_block_move, except that we
2848 count insns rather than emit them. */
2851 compute_movmem_length (rtx insn)
2853 rtx pat = PATTERN (insn);
2854 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2855 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2856 unsigned int n_insns = 0;
2858 /* We can't move more than four bytes at a time because the PA
2859 has no longer integer move insns. (Could use fp mem ops?) */
2860 if (align > (TARGET_64BIT ? 8 : 4))
2861 align = (TARGET_64BIT ? 8 : 4);
2863 /* The basic copying loop. */
2867 if (n_bytes % (2 * align) != 0)
2869 if ((n_bytes % (2 * align)) >= align)
2872 if ((n_bytes % align) != 0)
2876 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2880 /* Emit code to perform a block clear.
2882 OPERANDS[0] is the destination pointer as a REG, clobbered.
2883 OPERANDS[1] is a register for temporary storage.
2884 OPERANDS[2] is the size as a CONST_INT
2885 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2888 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2890 int align = INTVAL (operands[3]);
2891 unsigned long n_bytes = INTVAL (operands[2]);
2893 /* We can't clear more than a word at a time because the PA
2894 has no longer integer move insns. */
2895 if (align > (TARGET_64BIT ? 8 : 4))
2896 align = (TARGET_64BIT ? 8 : 4);
2898 /* Note that we know each loop below will execute at least twice
2899 (else we would have open-coded the copy). */
2903 /* Pre-adjust the loop counter. */
2904 operands[2] = GEN_INT (n_bytes - 16);
2905 output_asm_insn ("ldi %2,%1", operands);
2908 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2909 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2910 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2912 /* Handle the residual. There could be up to 7 bytes of
2913 residual to copy! */
2914 if (n_bytes % 16 != 0)
2916 operands[2] = GEN_INT (n_bytes % 8);
2917 if (n_bytes % 16 >= 8)
2918 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2919 if (n_bytes % 8 != 0)
2920 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2925 /* Pre-adjust the loop counter. */
2926 operands[2] = GEN_INT (n_bytes - 8);
2927 output_asm_insn ("ldi %2,%1", operands);
2930 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2931 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2932 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2934 /* Handle the residual. There could be up to 7 bytes of
2935 residual to copy! */
2936 if (n_bytes % 8 != 0)
2938 operands[2] = GEN_INT (n_bytes % 4);
2939 if (n_bytes % 8 >= 4)
2940 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2941 if (n_bytes % 4 != 0)
2942 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2947 /* Pre-adjust the loop counter. */
2948 operands[2] = GEN_INT (n_bytes - 4);
2949 output_asm_insn ("ldi %2,%1", operands);
2952 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2953 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2954 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2956 /* Handle the residual. */
2957 if (n_bytes % 4 != 0)
2959 if (n_bytes % 4 >= 2)
2960 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2961 if (n_bytes % 2 != 0)
2962 output_asm_insn ("stb %%r0,0(%0)", operands);
2967 /* Pre-adjust the loop counter. */
2968 operands[2] = GEN_INT (n_bytes - 2);
2969 output_asm_insn ("ldi %2,%1", operands);
2972 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2973 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2974 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2976 /* Handle the residual. */
2977 if (n_bytes % 2 != 0)
2978 output_asm_insn ("stb %%r0,0(%0)", operands);
2987 /* Count the number of insns necessary to handle this block move.
2989 Basic structure is the same as emit_block_move, except that we
2990 count insns rather than emit them. */
2993 compute_clrmem_length (rtx insn)
2995 rtx pat = PATTERN (insn);
2996 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2997 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2998 unsigned int n_insns = 0;
3000 /* We can't clear more than a word at a time because the PA
3001 has no longer integer move insns. */
3002 if (align > (TARGET_64BIT ? 8 : 4))
3003 align = (TARGET_64BIT ? 8 : 4);
3005 /* The basic loop. */
3009 if (n_bytes % (2 * align) != 0)
3011 if ((n_bytes % (2 * align)) >= align)
3014 if ((n_bytes % align) != 0)
3018 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3024 output_and (rtx *operands)
3026 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3028 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3029 int ls0, ls1, ms0, p, len;
3031 for (ls0 = 0; ls0 < 32; ls0++)
3032 if ((mask & (1 << ls0)) == 0)
3035 for (ls1 = ls0; ls1 < 32; ls1++)
3036 if ((mask & (1 << ls1)) != 0)
3039 for (ms0 = ls1; ms0 < 32; ms0++)
3040 if ((mask & (1 << ms0)) == 0)
3043 gcc_assert (ms0 == 32);
3051 operands[2] = GEN_INT (len);
3052 return "{extru|extrw,u} %1,31,%2,%0";
3056 /* We could use this `depi' for the case above as well, but `depi'
3057 requires one more register file access than an `extru'. */
3062 operands[2] = GEN_INT (p);
3063 operands[3] = GEN_INT (len);
3064 return "{depi|depwi} 0,%2,%3,%0";
3068 return "and %1,%2,%0";
3071 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3072 storing the result in operands[0]. */
3074 output_64bit_and (rtx *operands)
3076 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3078 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3079 int ls0, ls1, ms0, p, len;
3081 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3082 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3085 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3086 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3089 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3090 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3093 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
3095 if (ls1 == HOST_BITS_PER_WIDE_INT)
3101 operands[2] = GEN_INT (len);
3102 return "extrd,u %1,63,%2,%0";
3106 /* We could use this `depi' for the case above as well, but `depi'
3107 requires one more register file access than an `extru'. */
3112 operands[2] = GEN_INT (p);
3113 operands[3] = GEN_INT (len);
3114 return "depdi 0,%2,%3,%0";
3118 return "and %1,%2,%0";
3122 output_ior (rtx *operands)
3124 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3125 int bs0, bs1, p, len;
3127 if (INTVAL (operands[2]) == 0)
3128 return "copy %1,%0";
3130 for (bs0 = 0; bs0 < 32; bs0++)
3131 if ((mask & (1 << bs0)) != 0)
3134 for (bs1 = bs0; bs1 < 32; bs1++)
3135 if ((mask & (1 << bs1)) == 0)
3138 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3143 operands[2] = GEN_INT (p);
3144 operands[3] = GEN_INT (len);
3145 return "{depi|depwi} -1,%2,%3,%0";
3148 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3149 storing the result in operands[0]. */
3151 output_64bit_ior (rtx *operands)
3153 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3154 int bs0, bs1, p, len;
3156 if (INTVAL (operands[2]) == 0)
3157 return "copy %1,%0";
3159 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3160 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3163 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3164 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3167 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
3168 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
3173 operands[2] = GEN_INT (p);
3174 operands[3] = GEN_INT (len);
3175 return "depdi -1,%2,%3,%0";
3178 /* Target hook for assembling integer objects. This code handles
3179 aligned SI and DI integers specially since function references
3180 must be preceded by P%. */
3183 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3185 if (size == UNITS_PER_WORD
3187 && function_label_operand (x, VOIDmode))
3189 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3190 output_addr_const (asm_out_file, x);
3191 fputc ('\n', asm_out_file);
3194 return default_assemble_integer (x, size, aligned_p);
3197 /* Output an ascii string. */
3199 output_ascii (FILE *file, const char *p, int size)
3203 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3205 /* The HP assembler can only take strings of 256 characters at one
3206 time. This is a limitation on input line length, *not* the
3207 length of the string. Sigh. Even worse, it seems that the
3208 restriction is in number of input characters (see \xnn &
3209 \whatever). So we have to do this very carefully. */
3211 fputs ("\t.STRING \"", file);
3214 for (i = 0; i < size; i += 4)
3218 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3220 register unsigned int c = (unsigned char) p[i + io];
3222 if (c == '\"' || c == '\\')
3223 partial_output[co++] = '\\';
3224 if (c >= ' ' && c < 0177)
3225 partial_output[co++] = c;
3229 partial_output[co++] = '\\';
3230 partial_output[co++] = 'x';
3231 hexd = c / 16 - 0 + '0';
3233 hexd -= '9' - 'a' + 1;
3234 partial_output[co++] = hexd;
3235 hexd = c % 16 - 0 + '0';
3237 hexd -= '9' - 'a' + 1;
3238 partial_output[co++] = hexd;
3241 if (chars_output + co > 243)
3243 fputs ("\"\n\t.STRING \"", file);
3246 fwrite (partial_output, 1, (size_t) co, file);
3250 fputs ("\"\n", file);
3253 /* Try to rewrite floating point comparisons & branches to avoid
3254 useless add,tr insns.
3256 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3257 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3258 first attempt to remove useless add,tr insns. It is zero
3259 for the second pass as reorg sometimes leaves bogus REG_DEAD
3262 When CHECK_NOTES is zero we can only eliminate add,tr insns
3263 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3266 remove_useless_addtr_insns (int check_notes)
3269 static int pass = 0;
3271 /* This is fairly cheap, so always run it when optimizing. */
3275 int fbranch_count = 0;
3277 /* Walk all the insns in this function looking for fcmp & fbranch
3278 instructions. Keep track of how many of each we find. */
3279 for (insn = get_insns (); insn; insn = next_insn (insn))
3283 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3284 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3287 tmp = PATTERN (insn);
3289 /* It must be a set. */
3290 if (GET_CODE (tmp) != SET)
3293 /* If the destination is CCFP, then we've found an fcmp insn. */
3294 tmp = SET_DEST (tmp);
3295 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3301 tmp = PATTERN (insn);
3302 /* If this is an fbranch instruction, bump the fbranch counter. */
3303 if (GET_CODE (tmp) == SET
3304 && SET_DEST (tmp) == pc_rtx
3305 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3306 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3307 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3308 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3316 /* Find all floating point compare + branch insns. If possible,
3317 reverse the comparison & the branch to avoid add,tr insns. */
3318 for (insn = get_insns (); insn; insn = next_insn (insn))
3322 /* Ignore anything that isn't an INSN. */
3323 if (GET_CODE (insn) != INSN)
3326 tmp = PATTERN (insn);
3328 /* It must be a set. */
3329 if (GET_CODE (tmp) != SET)
3332 /* The destination must be CCFP, which is register zero. */
3333 tmp = SET_DEST (tmp);
3334 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3337 /* INSN should be a set of CCFP.
3339 See if the result of this insn is used in a reversed FP
3340 conditional branch. If so, reverse our condition and
3341 the branch. Doing so avoids useless add,tr insns. */
3342 next = next_insn (insn);
3345 /* Jumps, calls and labels stop our search. */
3346 if (GET_CODE (next) == JUMP_INSN
3347 || GET_CODE (next) == CALL_INSN
3348 || GET_CODE (next) == CODE_LABEL)
3351 /* As does another fcmp insn. */
3352 if (GET_CODE (next) == INSN
3353 && GET_CODE (PATTERN (next)) == SET
3354 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3355 && REGNO (SET_DEST (PATTERN (next))) == 0)
3358 next = next_insn (next);
3361 /* Is NEXT_INSN a branch? */
3363 && GET_CODE (next) == JUMP_INSN)
3365 rtx pattern = PATTERN (next);
3367 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3368 and CCFP dies, then reverse our conditional and the branch
3369 to avoid the add,tr. */
3370 if (GET_CODE (pattern) == SET
3371 && SET_DEST (pattern) == pc_rtx
3372 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3373 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3374 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3375 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3376 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3377 && (fcmp_count == fbranch_count
3379 && find_regno_note (next, REG_DEAD, 0))))
3381 /* Reverse the branch. */
3382 tmp = XEXP (SET_SRC (pattern), 1);
3383 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3384 XEXP (SET_SRC (pattern), 2) = tmp;
3385 INSN_CODE (next) = -1;
3387 /* Reverse our condition. */
3388 tmp = PATTERN (insn);
3389 PUT_CODE (XEXP (tmp, 1),
3390 (reverse_condition_maybe_unordered
3391 (GET_CODE (XEXP (tmp, 1)))));
3401 /* You may have trouble believing this, but this is the 32 bit HP-PA
3406 Variable arguments (optional; any number may be allocated)
3408 SP-(4*(N+9)) arg word N
3413 Fixed arguments (must be allocated; may remain unused)
3422 SP-32 External Data Pointer (DP)
3424 SP-24 External/stub RP (RP')
3428 SP-8 Calling Stub RP (RP'')
3433 SP-0 Stack Pointer (points to next available address)
3437 /* This function saves registers as follows. Registers marked with ' are
3438 this function's registers (as opposed to the previous function's).
3439 If a frame_pointer isn't needed, r4 is saved as a general register;
3440 the space for the frame pointer is still allocated, though, to keep
3446 SP (FP') Previous FP
3447 SP + 4 Alignment filler (sigh)
3448 SP + 8 Space for locals reserved here.
3452 SP + n All call saved register used.
3456 SP + o All call saved fp registers used.
3460 SP + p (SP') points to next available address.
3464 /* Global variables set by output_function_prologue(). */
3465 /* Size of frame. Need to know this to emit return insns from
3467 static HOST_WIDE_INT actual_fsize, local_fsize;
3468 static int save_fregs;
3470 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3471 Handle case where DISP > 8k by using the add_high_const patterns.
3473 Note in DISP > 8k case, we will leave the high part of the address
3474 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3477 store_reg (int reg, HOST_WIDE_INT disp, int base)
3479 rtx insn, dest, src, basereg;
3481 src = gen_rtx_REG (word_mode, reg);
3482 basereg = gen_rtx_REG (Pmode, base);
3483 if (VAL_14_BITS_P (disp))
3485 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3486 insn = emit_move_insn (dest, src);
3488 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3490 rtx delta = GEN_INT (disp);
3491 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3493 emit_move_insn (tmpreg, delta);
3494 insn = emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3497 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3498 gen_rtx_SET (VOIDmode, tmpreg,
3499 gen_rtx_PLUS (Pmode, basereg, delta)));
3500 RTX_FRAME_RELATED_P (insn) = 1;
3502 dest = gen_rtx_MEM (word_mode, tmpreg);
3503 insn = emit_move_insn (dest, src);
3507 rtx delta = GEN_INT (disp);
3508 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3509 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3511 emit_move_insn (tmpreg, high);
3512 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3513 insn = emit_move_insn (dest, src);
3515 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3516 gen_rtx_SET (VOIDmode,
3517 gen_rtx_MEM (word_mode,
3518 gen_rtx_PLUS (word_mode,
3525 RTX_FRAME_RELATED_P (insn) = 1;
3528 /* Emit RTL to store REG at the memory location specified by BASE and then
3529 add MOD to BASE. MOD must be <= 8k. */
3532 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3534 rtx insn, basereg, srcreg, delta;
3536 gcc_assert (VAL_14_BITS_P (mod));
3538 basereg = gen_rtx_REG (Pmode, base);
3539 srcreg = gen_rtx_REG (word_mode, reg);
3540 delta = GEN_INT (mod);
3542 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3545 RTX_FRAME_RELATED_P (insn) = 1;
3547 /* RTX_FRAME_RELATED_P must be set on each frame related set
3548 in a parallel with more than one element. */
3549 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3550 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3554 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3555 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3556 whether to add a frame note or not.
3558 In the DISP > 8k case, we leave the high part of the address in %r1.
3559 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3562 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3566 if (VAL_14_BITS_P (disp))
3568 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3569 plus_constant (gen_rtx_REG (Pmode, base), disp));
3571 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3573 rtx basereg = gen_rtx_REG (Pmode, base);
3574 rtx delta = GEN_INT (disp);
3575 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3577 emit_move_insn (tmpreg, delta);
3578 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3579 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3581 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
3582 gen_rtx_SET (VOIDmode, tmpreg,
3583 gen_rtx_PLUS (Pmode, basereg, delta)));
3587 rtx basereg = gen_rtx_REG (Pmode, base);
3588 rtx delta = GEN_INT (disp);
3589 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3591 emit_move_insn (tmpreg,
3592 gen_rtx_PLUS (Pmode, basereg,
3593 gen_rtx_HIGH (Pmode, delta)));
3594 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3595 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3598 if (DO_FRAME_NOTES && note)
3599 RTX_FRAME_RELATED_P (insn) = 1;
3603 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3608 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3609 be consistent with the rounding and size calculation done here.
3610 Change them at the same time. */
3612 /* We do our own stack alignment. First, round the size of the
3613 stack locals up to a word boundary. */
3614 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3616 /* Space for previous frame pointer + filler. If any frame is
3617 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3618 waste some space here for the sake of HP compatibility. The
3619 first slot is only used when the frame pointer is needed. */
3620 if (size || frame_pointer_needed)
3621 size += STARTING_FRAME_OFFSET;
3623 /* If the current function calls __builtin_eh_return, then we need
3624 to allocate stack space for registers that will hold data for
3625 the exception handler. */
3626 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3630 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3632 size += i * UNITS_PER_WORD;
3635 /* Account for space used by the callee general register saves. */
3636 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3637 if (df_regs_ever_live_p (i))
3638 size += UNITS_PER_WORD;
3640 /* Account for space used by the callee floating point register saves. */
3641 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3642 if (df_regs_ever_live_p (i)
3643 || (!TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3647 /* We always save both halves of the FP register, so always
3648 increment the frame size by 8 bytes. */
3652 /* If any of the floating registers are saved, account for the
3653 alignment needed for the floating point register save block. */
3656 size = (size + 7) & ~7;
3661 /* The various ABIs include space for the outgoing parameters in the
3662 size of the current function's stack frame. We don't need to align
3663 for the outgoing arguments as their alignment is set by the final
3664 rounding for the frame as a whole. */
3665 size += crtl->outgoing_args_size;
3667 /* Allocate space for the fixed frame marker. This space must be
3668 allocated for any function that makes calls or allocates
3670 if (!current_function_is_leaf || size)
3671 size += TARGET_64BIT ? 48 : 32;
3673 /* Finally, round to the preferred stack boundary. */
3674 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3675 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3678 /* Generate the assembly code for function entry. FILE is a stdio
3679 stream to output the code to. SIZE is an int: how many units of
3680 temporary storage to allocate.
3682 Refer to the array `regs_ever_live' to determine which registers to
3683 save; `regs_ever_live[I]' is nonzero if register number I is ever
3684 used in the function. This function is responsible for knowing
3685 which registers should not be saved even if used. */
3687 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3688 of memory. If any fpu reg is used in the function, we allocate
3689 such a block here, at the bottom of the frame, just in case it's needed.
3691 If this function is a leaf procedure, then we may choose not
3692 to do a "save" insn. The decision about whether or not
3693 to do this is made in regclass.c. */
3696 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3698 /* The function's label and associated .PROC must never be
3699 separated and must be output *after* any profiling declarations
3700 to avoid changing spaces/subspaces within a procedure. */
3701 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3702 fputs ("\t.PROC\n", file);
3704 /* hppa_expand_prologue does the dirty work now. We just need
3705 to output the assembler directives which denote the start
3707 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3708 if (current_function_is_leaf)
3709 fputs (",NO_CALLS", file);
3711 fputs (",CALLS", file);
3713 fputs (",SAVE_RP", file);
3715 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3716 at the beginning of the frame and that it is used as the frame
3717 pointer for the frame. We do this because our current frame
3718 layout doesn't conform to that specified in the HP runtime
3719 documentation and we need a way to indicate to programs such as
3720 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3721 isn't used by HP compilers but is supported by the assembler.
3722 However, SAVE_SP is supposed to indicate that the previous stack
3723 pointer has been saved in the frame marker. */
3724 if (frame_pointer_needed)
3725 fputs (",SAVE_SP", file);
3727 /* Pass on information about the number of callee register saves
3728 performed in the prologue.
3730 The compiler is supposed to pass the highest register number
3731 saved, the assembler then has to adjust that number before
3732 entering it into the unwind descriptor (to account for any
3733 caller saved registers with lower register numbers than the
3734 first callee saved register). */
3736 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3739 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3741 fputs ("\n\t.ENTRY\n", file);
3743 remove_useless_addtr_insns (0);
3747 hppa_expand_prologue (void)
3749 int merge_sp_adjust_with_store = 0;
3750 HOST_WIDE_INT size = get_frame_size ();
3751 HOST_WIDE_INT offset;
3759 /* Compute total size for frame pointer, filler, locals and rounding to
3760 the next word boundary. Similar code appears in compute_frame_size
3761 and must be changed in tandem with this code. */
3762 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3763 if (local_fsize || frame_pointer_needed)
3764 local_fsize += STARTING_FRAME_OFFSET;
3766 actual_fsize = compute_frame_size (size, &save_fregs);
3767 if (flag_stack_usage)
3768 current_function_static_stack_size = actual_fsize;
3770 /* Compute a few things we will use often. */
3771 tmpreg = gen_rtx_REG (word_mode, 1);
3773 /* Save RP first. The calling conventions manual states RP will
3774 always be stored into the caller's frame at sp - 20 or sp - 16
3775 depending on which ABI is in use. */
3776 if (df_regs_ever_live_p (2) || crtl->calls_eh_return)
3778 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3784 /* Allocate the local frame and set up the frame pointer if needed. */
3785 if (actual_fsize != 0)
3787 if (frame_pointer_needed)
3789 /* Copy the old frame pointer temporarily into %r1. Set up the
3790 new stack pointer, then store away the saved old frame pointer
3791 into the stack at sp and at the same time update the stack
3792 pointer by actual_fsize bytes. Two versions, first
3793 handles small (<8k) frames. The second handles large (>=8k)
3795 insn = emit_move_insn (tmpreg, hard_frame_pointer_rtx);
3797 RTX_FRAME_RELATED_P (insn) = 1;
3799 insn = emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
3801 RTX_FRAME_RELATED_P (insn) = 1;
3803 if (VAL_14_BITS_P (actual_fsize))
3804 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3807 /* It is incorrect to store the saved frame pointer at *sp,
3808 then increment sp (writes beyond the current stack boundary).
3810 So instead use stwm to store at *sp and post-increment the
3811 stack pointer as an atomic operation. Then increment sp to
3812 finish allocating the new frame. */
3813 HOST_WIDE_INT adjust1 = 8192 - 64;
3814 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3816 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3817 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3821 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3822 we need to store the previous stack pointer (frame pointer)
3823 into the frame marker on targets that use the HP unwind
3824 library. This allows the HP unwind library to be used to
3825 unwind GCC frames. However, we are not fully compatible
3826 with the HP library because our frame layout differs from
3827 that specified in the HP runtime specification.
3829 We don't want a frame note on this instruction as the frame
3830 marker moves during dynamic stack allocation.
3832 This instruction also serves as a blockage to prevent
3833 register spills from being scheduled before the stack
3834 pointer is raised. This is necessary as we store
3835 registers using the frame pointer as a base register,
3836 and the frame pointer is set before sp is raised. */
3837 if (TARGET_HPUX_UNWIND_LIBRARY)
3839 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3840 GEN_INT (TARGET_64BIT ? -8 : -4));
3842 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3843 hard_frame_pointer_rtx);
3846 emit_insn (gen_blockage ());
3848 /* no frame pointer needed. */
3851 /* In some cases we can perform the first callee register save
3852 and allocating the stack frame at the same time. If so, just
3853 make a note of it and defer allocating the frame until saving
3854 the callee registers. */
3855 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3856 merge_sp_adjust_with_store = 1;
3857 /* Can not optimize. Adjust the stack frame by actual_fsize
3860 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3865 /* Normal register save.
3867 Do not save the frame pointer in the frame_pointer_needed case. It
3868 was done earlier. */
3869 if (frame_pointer_needed)
3871 offset = local_fsize;
3873 /* Saving the EH return data registers in the frame is the simplest
3874 way to get the frame unwind information emitted. We put them
3875 just before the general registers. */
3876 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3878 unsigned int i, regno;
3882 regno = EH_RETURN_DATA_REGNO (i);
3883 if (regno == INVALID_REGNUM)
3886 store_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
3887 offset += UNITS_PER_WORD;
3891 for (i = 18; i >= 4; i--)
3892 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3894 store_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
3895 offset += UNITS_PER_WORD;
3898 /* Account for %r3 which is saved in a special place. */
3901 /* No frame pointer needed. */
3904 offset = local_fsize - actual_fsize;
3906 /* Saving the EH return data registers in the frame is the simplest
3907 way to get the frame unwind information emitted. */
3908 if (DO_FRAME_NOTES && crtl->calls_eh_return)
3910 unsigned int i, regno;
3914 regno = EH_RETURN_DATA_REGNO (i);
3915 if (regno == INVALID_REGNUM)
3918 /* If merge_sp_adjust_with_store is nonzero, then we can
3919 optimize the first save. */
3920 if (merge_sp_adjust_with_store)
3922 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3923 merge_sp_adjust_with_store = 0;
3926 store_reg (regno, offset, STACK_POINTER_REGNUM);
3927 offset += UNITS_PER_WORD;
3931 for (i = 18; i >= 3; i--)
3932 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
3934 /* If merge_sp_adjust_with_store is nonzero, then we can
3935 optimize the first GR save. */
3936 if (merge_sp_adjust_with_store)
3938 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3939 merge_sp_adjust_with_store = 0;
3942 store_reg (i, offset, STACK_POINTER_REGNUM);
3943 offset += UNITS_PER_WORD;
3947 /* If we wanted to merge the SP adjustment with a GR save, but we never
3948 did any GR saves, then just emit the adjustment here. */
3949 if (merge_sp_adjust_with_store)
3950 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3954 /* The hppa calling conventions say that %r19, the pic offset
3955 register, is saved at sp - 32 (in this function's frame)
3956 when generating PIC code. FIXME: What is the correct thing
3957 to do for functions which make no calls and allocate no
3958 frame? Do we need to allocate a frame, or can we just omit
3959 the save? For now we'll just omit the save.
3961 We don't want a note on this insn as the frame marker can
3962 move if there is a dynamic stack allocation. */
3963 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3965 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3967 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3971 /* Align pointer properly (doubleword boundary). */
3972 offset = (offset + 7) & ~7;
3974 /* Floating point register store. */
3979 /* First get the frame or stack pointer to the start of the FP register
3981 if (frame_pointer_needed)
3983 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
3984 base = hard_frame_pointer_rtx;
3988 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3989 base = stack_pointer_rtx;
3992 /* Now actually save the FP registers. */
3993 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3995 if (df_regs_ever_live_p (i)
3996 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
3998 rtx addr, insn, reg;
3999 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4000 reg = gen_rtx_REG (DFmode, i);
4001 insn = emit_move_insn (addr, reg);
4004 RTX_FRAME_RELATED_P (insn) = 1;
4007 rtx mem = gen_rtx_MEM (DFmode,
4008 plus_constant (base, offset));
4009 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4010 gen_rtx_SET (VOIDmode, mem, reg));
4014 rtx meml = gen_rtx_MEM (SFmode,
4015 plus_constant (base, offset));
4016 rtx memr = gen_rtx_MEM (SFmode,
4017 plus_constant (base, offset + 4));
4018 rtx regl = gen_rtx_REG (SFmode, i);
4019 rtx regr = gen_rtx_REG (SFmode, i + 1);
4020 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4021 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4024 RTX_FRAME_RELATED_P (setl) = 1;
4025 RTX_FRAME_RELATED_P (setr) = 1;
4026 vec = gen_rtvec (2, setl, setr);
4027 add_reg_note (insn, REG_FRAME_RELATED_EXPR,
4028 gen_rtx_SEQUENCE (VOIDmode, vec));
4031 offset += GET_MODE_SIZE (DFmode);
4038 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4039 Handle case where DISP > 8k by using the add_high_const patterns. */
4042 load_reg (int reg, HOST_WIDE_INT disp, int base)
4044 rtx dest = gen_rtx_REG (word_mode, reg);
4045 rtx basereg = gen_rtx_REG (Pmode, base);
4048 if (VAL_14_BITS_P (disp))
4049 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4050 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4052 rtx delta = GEN_INT (disp);
4053 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4055 emit_move_insn (tmpreg, delta);
4056 if (TARGET_DISABLE_INDEXING)
4058 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4059 src = gen_rtx_MEM (word_mode, tmpreg);
4062 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4066 rtx delta = GEN_INT (disp);
4067 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4068 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4070 emit_move_insn (tmpreg, high);
4071 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4074 emit_move_insn (dest, src);
4077 /* Update the total code bytes output to the text section. */
4080 update_total_code_bytes (unsigned int nbytes)
4082 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4083 && !IN_NAMED_SECTION_P (cfun->decl))
4085 unsigned int old_total = total_code_bytes;
4087 total_code_bytes += nbytes;
4089 /* Be prepared to handle overflows. */
4090 if (old_total > total_code_bytes)
4091 total_code_bytes = UINT_MAX;
4095 /* This function generates the assembly code for function exit.
4096 Args are as for output_function_prologue ().
4098 The function epilogue should not depend on the current stack
4099 pointer! It should use the frame pointer only. This is mandatory
4100 because of alloca; we also take advantage of it to omit stack
4101 adjustments before returning. */
4104 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4106 rtx insn = get_last_insn ();
4110 /* hppa_expand_epilogue does the dirty work now. We just need
4111 to output the assembler directives which denote the end
4114 To make debuggers happy, emit a nop if the epilogue was completely
4115 eliminated due to a volatile call as the last insn in the
4116 current function. That way the return address (in %r2) will
4117 always point to a valid instruction in the current function. */
4119 /* Get the last real insn. */
4120 if (GET_CODE (insn) == NOTE)
4121 insn = prev_real_insn (insn);
4123 /* If it is a sequence, then look inside. */
4124 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4125 insn = XVECEXP (PATTERN (insn), 0, 0);
4127 /* If insn is a CALL_INSN, then it must be a call to a volatile
4128 function (otherwise there would be epilogue insns). */
4129 if (insn && GET_CODE (insn) == CALL_INSN)
4131 fputs ("\tnop\n", file);
4135 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4137 if (TARGET_SOM && TARGET_GAS)
4139 /* We done with this subspace except possibly for some additional
4140 debug information. Forget that we are in this subspace to ensure
4141 that the next function is output in its own subspace. */
4143 cfun->machine->in_nsubspa = 2;
4146 if (INSN_ADDRESSES_SET_P ())
4148 insn = get_last_nonnote_insn ();
4149 last_address += INSN_ADDRESSES (INSN_UID (insn));
4151 last_address += insn_default_length (insn);
4152 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4153 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4156 last_address = UINT_MAX;
4158 /* Finally, update the total number of code bytes output so far. */
4159 update_total_code_bytes (last_address);
4163 hppa_expand_epilogue (void)
4166 HOST_WIDE_INT offset;
4167 HOST_WIDE_INT ret_off = 0;
4169 int merge_sp_adjust_with_load = 0;
4171 /* We will use this often. */
4172 tmpreg = gen_rtx_REG (word_mode, 1);
4174 /* Try to restore RP early to avoid load/use interlocks when
4175 RP gets used in the return (bv) instruction. This appears to still
4176 be necessary even when we schedule the prologue and epilogue. */
4179 ret_off = TARGET_64BIT ? -16 : -20;
4180 if (frame_pointer_needed)
4182 load_reg (2, ret_off, HARD_FRAME_POINTER_REGNUM);
4187 /* No frame pointer, and stack is smaller than 8k. */
4188 if (VAL_14_BITS_P (ret_off - actual_fsize))
4190 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4196 /* General register restores. */
4197 if (frame_pointer_needed)
4199 offset = local_fsize;
4201 /* If the current function calls __builtin_eh_return, then we need
4202 to restore the saved EH data registers. */
4203 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4205 unsigned int i, regno;
4209 regno = EH_RETURN_DATA_REGNO (i);
4210 if (regno == INVALID_REGNUM)
4213 load_reg (regno, offset, HARD_FRAME_POINTER_REGNUM);
4214 offset += UNITS_PER_WORD;
4218 for (i = 18; i >= 4; i--)
4219 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4221 load_reg (i, offset, HARD_FRAME_POINTER_REGNUM);
4222 offset += UNITS_PER_WORD;
4227 offset = local_fsize - actual_fsize;
4229 /* If the current function calls __builtin_eh_return, then we need
4230 to restore the saved EH data registers. */
4231 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4233 unsigned int i, regno;
4237 regno = EH_RETURN_DATA_REGNO (i);
4238 if (regno == INVALID_REGNUM)
4241 /* Only for the first load.
4242 merge_sp_adjust_with_load holds the register load
4243 with which we will merge the sp adjustment. */
4244 if (merge_sp_adjust_with_load == 0
4246 && VAL_14_BITS_P (-actual_fsize))
4247 merge_sp_adjust_with_load = regno;
4249 load_reg (regno, offset, STACK_POINTER_REGNUM);
4250 offset += UNITS_PER_WORD;
4254 for (i = 18; i >= 3; i--)
4256 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
4258 /* Only for the first load.
4259 merge_sp_adjust_with_load holds the register load
4260 with which we will merge the sp adjustment. */
4261 if (merge_sp_adjust_with_load == 0
4263 && VAL_14_BITS_P (-actual_fsize))
4264 merge_sp_adjust_with_load = i;
4266 load_reg (i, offset, STACK_POINTER_REGNUM);
4267 offset += UNITS_PER_WORD;
4272 /* Align pointer properly (doubleword boundary). */
4273 offset = (offset + 7) & ~7;
4275 /* FP register restores. */
4278 /* Adjust the register to index off of. */
4279 if (frame_pointer_needed)
4280 set_reg_plus_d (1, HARD_FRAME_POINTER_REGNUM, offset, 0);
4282 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4284 /* Actually do the restores now. */
4285 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4286 if (df_regs_ever_live_p (i)
4287 || (! TARGET_64BIT && df_regs_ever_live_p (i + 1)))
4289 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4290 rtx dest = gen_rtx_REG (DFmode, i);
4291 emit_move_insn (dest, src);
4295 /* Emit a blockage insn here to keep these insns from being moved to
4296 an earlier spot in the epilogue, or into the main instruction stream.
4298 This is necessary as we must not cut the stack back before all the
4299 restores are finished. */
4300 emit_insn (gen_blockage ());
4302 /* Reset stack pointer (and possibly frame pointer). The stack
4303 pointer is initially set to fp + 64 to avoid a race condition. */
4304 if (frame_pointer_needed)
4306 rtx delta = GEN_INT (-64);
4308 set_reg_plus_d (STACK_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM, 64, 0);
4309 emit_insn (gen_pre_load (hard_frame_pointer_rtx,
4310 stack_pointer_rtx, delta));
4312 /* If we were deferring a callee register restore, do it now. */
4313 else if (merge_sp_adjust_with_load)
4315 rtx delta = GEN_INT (-actual_fsize);
4316 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4318 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4320 else if (actual_fsize != 0)
4321 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4324 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4325 frame greater than 8k), do so now. */
4327 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4329 if (DO_FRAME_NOTES && crtl->calls_eh_return)
4331 rtx sa = EH_RETURN_STACKADJ_RTX;
4333 emit_insn (gen_blockage ());
4334 emit_insn (TARGET_64BIT
4335 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4336 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4341 hppa_pic_save_rtx (void)
4343 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4346 #ifndef NO_DEFERRED_PROFILE_COUNTERS
4347 #define NO_DEFERRED_PROFILE_COUNTERS 0
4351 /* Vector of funcdef numbers. */
4352 static VEC(int,heap) *funcdef_nos;
4354 /* Output deferred profile counters. */
4356 output_deferred_profile_counters (void)
4361 if (VEC_empty (int, funcdef_nos))
4364 switch_to_section (data_section);
4365 align = MIN (BIGGEST_ALIGNMENT, LONG_TYPE_SIZE);
4366 ASM_OUTPUT_ALIGN (asm_out_file, floor_log2 (align / BITS_PER_UNIT));
4368 for (i = 0; VEC_iterate (int, funcdef_nos, i, n); i++)
4370 targetm.asm_out.internal_label (asm_out_file, "LP", n);
4371 assemble_integer (const0_rtx, LONG_TYPE_SIZE / BITS_PER_UNIT, align, 1);
4374 VEC_free (int, heap, funcdef_nos);
4378 hppa_profile_hook (int label_no)
4380 /* We use SImode for the address of the function in both 32 and
4381 64-bit code to avoid having to provide DImode versions of the
4382 lcla2 and load_offset_label_address insn patterns. */
4383 rtx reg = gen_reg_rtx (SImode);
4384 rtx label_rtx = gen_label_rtx ();
4385 rtx begin_label_rtx, call_insn;
4386 char begin_label_name[16];
4388 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4390 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4393 emit_move_insn (arg_pointer_rtx,
4394 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4397 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4399 /* The address of the function is loaded into %r25 with an instruction-
4400 relative sequence that avoids the use of relocations. The sequence
4401 is split so that the load_offset_label_address instruction can
4402 occupy the delay slot of the call to _mcount. */
4404 emit_insn (gen_lcla2 (reg, label_rtx));
4406 emit_insn (gen_lcla1 (reg, label_rtx));
4408 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4409 reg, begin_label_rtx, label_rtx));
4411 #if !NO_DEFERRED_PROFILE_COUNTERS
4413 rtx count_label_rtx, addr, r24;
4414 char count_label_name[16];
4416 VEC_safe_push (int, heap, funcdef_nos, label_no);
4417 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4418 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4420 addr = force_reg (Pmode, count_label_rtx);
4421 r24 = gen_rtx_REG (Pmode, 24);
4422 emit_move_insn (r24, addr);
4425 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4426 gen_rtx_SYMBOL_REF (Pmode,
4428 GEN_INT (TARGET_64BIT ? 24 : 12)));
4430 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4435 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4436 gen_rtx_SYMBOL_REF (Pmode,
4438 GEN_INT (TARGET_64BIT ? 16 : 8)));
4442 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4443 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4445 /* Indicate the _mcount call cannot throw, nor will it execute a
4447 make_reg_eh_region_note_nothrow_nononlocal (call_insn);
4450 /* Fetch the return address for the frame COUNT steps up from
4451 the current frame, after the prologue. FRAMEADDR is the
4452 frame pointer of the COUNT frame.
4454 We want to ignore any export stub remnants here. To handle this,
4455 we examine the code at the return address, and if it is an export
4456 stub, we return a memory rtx for the stub return address stored
4459 The value returned is used in two different ways:
4461 1. To find a function's caller.
4463 2. To change the return address for a function.
4465 This function handles most instances of case 1; however, it will
4466 fail if there are two levels of stubs to execute on the return
4467 path. The only way I believe that can happen is if the return value
4468 needs a parameter relocation, which never happens for C code.
4470 This function handles most instances of case 2; however, it will
4471 fail if we did not originally have stub code on the return path
4472 but will need stub code on the new return path. This can happen if
4473 the caller & callee are both in the main program, but the new
4474 return location is in a shared library. */
4477 return_addr_rtx (int count, rtx frameaddr)
4484 /* Instruction stream at the normal return address for the export stub:
4486 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4487 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4488 0x00011820 | stub+16: mtsp r1,sr0
4489 0xe0400002 | stub+20: be,n 0(sr0,rp)
4491 0xe0400002 must be specified as -532676606 so that it won't be
4492 rejected as an invalid immediate operand on 64-bit hosts. */
4494 HOST_WIDE_INT insns[4] = {0x4bc23fd1, 0x004010a1, 0x00011820, -532676606};
4500 rp = get_hard_reg_initial_val (Pmode, 2);
4502 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4505 /* If there is no export stub then just use the value saved from
4506 the return pointer register. */
4508 saved_rp = gen_reg_rtx (Pmode);
4509 emit_move_insn (saved_rp, rp);
4511 /* Get pointer to the instruction stream. We have to mask out the
4512 privilege level from the two low order bits of the return address
4513 pointer here so that ins will point to the start of the first
4514 instruction that would have been executed if we returned. */
4515 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4516 label = gen_label_rtx ();
4518 /* Check the instruction stream at the normal return address for the
4519 export stub. If it is an export stub, than our return address is
4520 really in -24[frameaddr]. */
4522 for (i = 0; i < 3; i++)
4524 rtx op0 = gen_rtx_MEM (SImode, plus_constant (ins, i * 4));
4525 rtx op1 = GEN_INT (insns[i]);
4526 emit_cmp_and_jump_insns (op0, op1, NE, NULL, SImode, 0, label);
4529 /* Here we know that our return address points to an export
4530 stub. We don't want to return the address of the export stub,
4531 but rather the return address of the export stub. That return
4532 address is stored at -24[frameaddr]. */
4534 emit_move_insn (saved_rp,
4536 memory_address (Pmode,
4537 plus_constant (frameaddr,
4546 emit_bcond_fp (rtx operands[])
4548 enum rtx_code code = GET_CODE (operands[0]);
4549 rtx operand0 = operands[1];
4550 rtx operand1 = operands[2];
4551 rtx label = operands[3];
4553 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4554 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1)));
4556 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4557 gen_rtx_IF_THEN_ELSE (VOIDmode,
4560 gen_rtx_REG (CCFPmode, 0),
4562 gen_rtx_LABEL_REF (VOIDmode, label),
4567 /* Adjust the cost of a scheduling dependency. Return the new cost of
4568 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4571 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4573 enum attr_type attr_type;
4575 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4576 true dependencies as they are described with bypasses now. */
4577 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4580 if (! recog_memoized (insn))
4583 attr_type = get_attr_type (insn);
4585 switch (REG_NOTE_KIND (link))
4588 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4591 if (attr_type == TYPE_FPLOAD)
4593 rtx pat = PATTERN (insn);
4594 rtx dep_pat = PATTERN (dep_insn);
4595 if (GET_CODE (pat) == PARALLEL)
4597 /* This happens for the fldXs,mb patterns. */
4598 pat = XVECEXP (pat, 0, 0);
4600 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4601 /* If this happens, we have to extend this to schedule
4602 optimally. Return 0 for now. */
4605 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4607 if (! recog_memoized (dep_insn))
4609 switch (get_attr_type (dep_insn))
4616 case TYPE_FPSQRTSGL:
4617 case TYPE_FPSQRTDBL:
4618 /* A fpload can't be issued until one cycle before a
4619 preceding arithmetic operation has finished if
4620 the target of the fpload is any of the sources
4621 (or destination) of the arithmetic operation. */
4622 return insn_default_latency (dep_insn) - 1;
4629 else if (attr_type == TYPE_FPALU)
4631 rtx pat = PATTERN (insn);
4632 rtx dep_pat = PATTERN (dep_insn);
4633 if (GET_CODE (pat) == PARALLEL)
4635 /* This happens for the fldXs,mb patterns. */
4636 pat = XVECEXP (pat, 0, 0);
4638 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4639 /* If this happens, we have to extend this to schedule
4640 optimally. Return 0 for now. */
4643 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4645 if (! recog_memoized (dep_insn))
4647 switch (get_attr_type (dep_insn))
4651 case TYPE_FPSQRTSGL:
4652 case TYPE_FPSQRTDBL:
4653 /* An ALU flop can't be issued until two cycles before a
4654 preceding divide or sqrt operation has finished if
4655 the target of the ALU flop is any of the sources
4656 (or destination) of the divide or sqrt operation. */
4657 return insn_default_latency (dep_insn) - 2;
4665 /* For other anti dependencies, the cost is 0. */
4668 case REG_DEP_OUTPUT:
4669 /* Output dependency; DEP_INSN writes a register that INSN writes some
4671 if (attr_type == TYPE_FPLOAD)
4673 rtx pat = PATTERN (insn);
4674 rtx dep_pat = PATTERN (dep_insn);
4675 if (GET_CODE (pat) == PARALLEL)
4677 /* This happens for the fldXs,mb patterns. */
4678 pat = XVECEXP (pat, 0, 0);
4680 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4681 /* If this happens, we have to extend this to schedule
4682 optimally. Return 0 for now. */
4685 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4687 if (! recog_memoized (dep_insn))
4689 switch (get_attr_type (dep_insn))
4696 case TYPE_FPSQRTSGL:
4697 case TYPE_FPSQRTDBL:
4698 /* A fpload can't be issued until one cycle before a
4699 preceding arithmetic operation has finished if
4700 the target of the fpload is the destination of the
4701 arithmetic operation.
4703 Exception: For PA7100LC, PA7200 and PA7300, the cost
4704 is 3 cycles, unless they bundle together. We also
4705 pay the penalty if the second insn is a fpload. */
4706 return insn_default_latency (dep_insn) - 1;
4713 else if (attr_type == TYPE_FPALU)
4715 rtx pat = PATTERN (insn);
4716 rtx dep_pat = PATTERN (dep_insn);
4717 if (GET_CODE (pat) == PARALLEL)
4719 /* This happens for the fldXs,mb patterns. */
4720 pat = XVECEXP (pat, 0, 0);
4722 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4723 /* If this happens, we have to extend this to schedule
4724 optimally. Return 0 for now. */
4727 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4729 if (! recog_memoized (dep_insn))
4731 switch (get_attr_type (dep_insn))
4735 case TYPE_FPSQRTSGL:
4736 case TYPE_FPSQRTDBL:
4737 /* An ALU flop can't be issued until two cycles before a
4738 preceding divide or sqrt operation has finished if
4739 the target of the ALU flop is also the target of
4740 the divide or sqrt operation. */
4741 return insn_default_latency (dep_insn) - 2;
4749 /* For other output dependencies, the cost is 0. */
4757 /* Adjust scheduling priorities. We use this to try and keep addil
4758 and the next use of %r1 close together. */
4760 pa_adjust_priority (rtx insn, int priority)
4762 rtx set = single_set (insn);
4766 src = SET_SRC (set);
4767 dest = SET_DEST (set);
4768 if (GET_CODE (src) == LO_SUM
4769 && symbolic_operand (XEXP (src, 1), VOIDmode)
4770 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4773 else if (GET_CODE (src) == MEM
4774 && GET_CODE (XEXP (src, 0)) == LO_SUM
4775 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4776 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4779 else if (GET_CODE (dest) == MEM
4780 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4781 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4782 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4788 /* The 700 can only issue a single insn at a time.
4789 The 7XXX processors can issue two insns at a time.
4790 The 8000 can issue 4 insns at a time. */
4792 pa_issue_rate (void)
4796 case PROCESSOR_700: return 1;
4797 case PROCESSOR_7100: return 2;
4798 case PROCESSOR_7100LC: return 2;
4799 case PROCESSOR_7200: return 2;
4800 case PROCESSOR_7300: return 2;
4801 case PROCESSOR_8000: return 4;
4810 /* Return any length adjustment needed by INSN which already has its length
4811 computed as LENGTH. Return zero if no adjustment is necessary.
4813 For the PA: function calls, millicode calls, and backwards short
4814 conditional branches with unfilled delay slots need an adjustment by +1
4815 (to account for the NOP which will be inserted into the instruction stream).
4817 Also compute the length of an inline block move here as it is too
4818 complicated to express as a length attribute in pa.md. */
4820 pa_adjust_insn_length (rtx insn, int length)
4822 rtx pat = PATTERN (insn);
4824 /* Jumps inside switch tables which have unfilled delay slots need
4826 if (GET_CODE (insn) == JUMP_INSN
4827 && GET_CODE (pat) == PARALLEL
4828 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4830 /* Millicode insn with an unfilled delay slot. */
4831 else if (GET_CODE (insn) == INSN
4832 && GET_CODE (pat) != SEQUENCE
4833 && GET_CODE (pat) != USE
4834 && GET_CODE (pat) != CLOBBER
4835 && get_attr_type (insn) == TYPE_MILLI)
4837 /* Block move pattern. */
4838 else if (GET_CODE (insn) == INSN
4839 && GET_CODE (pat) == PARALLEL
4840 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4841 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4842 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4843 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4844 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4845 return compute_movmem_length (insn) - 4;
4846 /* Block clear pattern. */
4847 else if (GET_CODE (insn) == INSN
4848 && GET_CODE (pat) == PARALLEL
4849 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4850 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4851 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4852 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4853 return compute_clrmem_length (insn) - 4;
4854 /* Conditional branch with an unfilled delay slot. */
4855 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4857 /* Adjust a short backwards conditional with an unfilled delay slot. */
4858 if (GET_CODE (pat) == SET
4860 && JUMP_LABEL (insn) != NULL_RTX
4861 && ! forward_branch_p (insn))
4863 else if (GET_CODE (pat) == PARALLEL
4864 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4867 /* Adjust dbra insn with short backwards conditional branch with
4868 unfilled delay slot -- only for case where counter is in a
4869 general register register. */
4870 else if (GET_CODE (pat) == PARALLEL
4871 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4872 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4873 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4875 && ! forward_branch_p (insn))
4883 /* Implement the TARGET_PRINT_OPERAND_PUNCT_VALID_P hook. */
4886 pa_print_operand_punct_valid_p (unsigned char code)
4897 /* Print operand X (an rtx) in assembler syntax to file FILE.
4898 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4899 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4902 print_operand (FILE *file, rtx x, int code)
4907 /* Output a 'nop' if there's nothing for the delay slot. */
4908 if (dbr_sequence_length () == 0)
4909 fputs ("\n\tnop", file);
4912 /* Output a nullification completer if there's nothing for the */
4913 /* delay slot or nullification is requested. */
4914 if (dbr_sequence_length () == 0 ||
4916 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4920 /* Print out the second register name of a register pair.
4921 I.e., R (6) => 7. */
4922 fputs (reg_names[REGNO (x) + 1], file);
4925 /* A register or zero. */
4927 || (x == CONST0_RTX (DFmode))
4928 || (x == CONST0_RTX (SFmode)))
4930 fputs ("%r0", file);
4936 /* A register or zero (floating point). */
4938 || (x == CONST0_RTX (DFmode))
4939 || (x == CONST0_RTX (SFmode)))
4941 fputs ("%fr0", file);
4950 xoperands[0] = XEXP (XEXP (x, 0), 0);
4951 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4952 output_global_address (file, xoperands[1], 0);
4953 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4957 case 'C': /* Plain (C)ondition */
4959 switch (GET_CODE (x))
4962 fputs ("=", file); break;
4964 fputs ("<>", file); break;
4966 fputs (">", file); break;
4968 fputs (">=", file); break;
4970 fputs (">>=", file); break;
4972 fputs (">>", file); break;
4974 fputs ("<", file); break;
4976 fputs ("<=", file); break;
4978 fputs ("<<=", file); break;
4980 fputs ("<<", file); break;
4985 case 'N': /* Condition, (N)egated */
4986 switch (GET_CODE (x))
4989 fputs ("<>", file); break;
4991 fputs ("=", file); break;
4993 fputs ("<=", file); break;
4995 fputs ("<", file); break;
4997 fputs ("<<", file); break;
4999 fputs ("<<=", file); break;
5001 fputs (">=", file); break;
5003 fputs (">", file); break;
5005 fputs (">>", file); break;
5007 fputs (">>=", file); break;
5012 /* For floating point comparisons. Note that the output
5013 predicates are the complement of the desired mode. The
5014 conditions for GT, GE, LT, LE and LTGT cause an invalid
5015 operation exception if the result is unordered and this
5016 exception is enabled in the floating-point status register. */
5018 switch (GET_CODE (x))
5021 fputs ("!=", file); break;
5023 fputs ("=", file); break;
5025 fputs ("!>", file); break;
5027 fputs ("!>=", file); break;
5029 fputs ("!<", file); break;
5031 fputs ("!<=", file); break;
5033 fputs ("!<>", file); break;
5035 fputs ("!?<=", file); break;
5037 fputs ("!?<", file); break;
5039 fputs ("!?>=", file); break;
5041 fputs ("!?>", file); break;
5043 fputs ("!?=", file); break;
5045 fputs ("!?", file); break;
5047 fputs ("?", file); break;
5052 case 'S': /* Condition, operands are (S)wapped. */
5053 switch (GET_CODE (x))
5056 fputs ("=", file); break;
5058 fputs ("<>", file); break;
5060 fputs ("<", file); break;
5062 fputs ("<=", file); break;
5064 fputs ("<<=", file); break;
5066 fputs ("<<", file); break;
5068 fputs (">", file); break;
5070 fputs (">=", file); break;
5072 fputs (">>=", file); break;
5074 fputs (">>", file); break;
5079 case 'B': /* Condition, (B)oth swapped and negate. */
5080 switch (GET_CODE (x))
5083 fputs ("<>", file); break;
5085 fputs ("=", file); break;
5087 fputs (">=", file); break;
5089 fputs (">", file); break;
5091 fputs (">>", file); break;
5093 fputs (">>=", file); break;
5095 fputs ("<=", file); break;
5097 fputs ("<", file); break;
5099 fputs ("<<", file); break;
5101 fputs ("<<=", file); break;
5107 gcc_assert (GET_CODE (x) == CONST_INT);
5108 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5111 gcc_assert (GET_CODE (x) == CONST_INT);
5112 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5115 gcc_assert (GET_CODE (x) == CONST_INT);
5116 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5119 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
5120 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5123 gcc_assert (GET_CODE (x) == CONST_INT);
5124 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5127 gcc_assert (GET_CODE (x) == CONST_INT);
5128 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5131 if (GET_CODE (x) == CONST_INT)
5136 switch (GET_CODE (XEXP (x, 0)))
5140 if (ASSEMBLER_DIALECT == 0)
5141 fputs ("s,mb", file);
5143 fputs (",mb", file);
5147 if (ASSEMBLER_DIALECT == 0)
5148 fputs ("s,ma", file);
5150 fputs (",ma", file);
5153 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5154 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5156 if (ASSEMBLER_DIALECT == 0)
5159 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5160 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5162 if (ASSEMBLER_DIALECT == 0)
5163 fputs ("x,s", file);
5167 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5171 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5177 output_global_address (file, x, 0);
5180 output_global_address (file, x, 1);
5182 case 0: /* Don't do anything special */
5187 compute_zdepwi_operands (INTVAL (x), op);
5188 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5194 compute_zdepdi_operands (INTVAL (x), op);
5195 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5199 /* We can get here from a .vtable_inherit due to our
5200 CONSTANT_ADDRESS_P rejecting perfectly good constant
5206 if (GET_CODE (x) == REG)
5208 fputs (reg_names [REGNO (x)], file);
5209 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5215 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5216 && (REGNO (x) & 1) == 0)
5219 else if (GET_CODE (x) == MEM)
5221 int size = GET_MODE_SIZE (GET_MODE (x));
5222 rtx base = NULL_RTX;
5223 switch (GET_CODE (XEXP (x, 0)))
5227 base = XEXP (XEXP (x, 0), 0);
5228 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5232 base = XEXP (XEXP (x, 0), 0);
5233 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5236 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5237 fprintf (file, "%s(%s)",
5238 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5239 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5240 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5241 fprintf (file, "%s(%s)",
5242 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5243 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5244 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5245 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5247 /* Because the REG_POINTER flag can get lost during reload,
5248 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5249 index and base registers in the combined move patterns. */
5250 rtx base = XEXP (XEXP (x, 0), 1);
5251 rtx index = XEXP (XEXP (x, 0), 0);
5253 fprintf (file, "%s(%s)",
5254 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5257 output_address (XEXP (x, 0));
5260 output_address (XEXP (x, 0));
5265 output_addr_const (file, x);
5268 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5271 output_global_address (FILE *file, rtx x, int round_constant)
5274 /* Imagine (high (const (plus ...))). */
5275 if (GET_CODE (x) == HIGH)
5278 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5279 output_addr_const (file, x);
5280 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5282 output_addr_const (file, x);
5283 fputs ("-$global$", file);
5285 else if (GET_CODE (x) == CONST)
5287 const char *sep = "";
5288 int offset = 0; /* assembler wants -$global$ at end */
5289 rtx base = NULL_RTX;
5291 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5294 base = XEXP (XEXP (x, 0), 0);
5295 output_addr_const (file, base);
5298 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5304 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5307 base = XEXP (XEXP (x, 0), 1);
5308 output_addr_const (file, base);
5311 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5317 /* How bogus. The compiler is apparently responsible for
5318 rounding the constant if it uses an LR field selector.
5320 The linker and/or assembler seem a better place since
5321 they have to do this kind of thing already.
5323 If we fail to do this, HP's optimizing linker may eliminate
5324 an addil, but not update the ldw/stw/ldo instruction that
5325 uses the result of the addil. */
5327 offset = ((offset + 0x1000) & ~0x1fff);
5329 switch (GET_CODE (XEXP (x, 0)))
5342 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5350 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5351 fputs ("-$global$", file);
5353 fprintf (file, "%s%d", sep, offset);
5356 output_addr_const (file, x);
5359 /* Output boilerplate text to appear at the beginning of the file.
5360 There are several possible versions. */
5361 #define aputs(x) fputs(x, asm_out_file)
5363 pa_file_start_level (void)
5366 aputs ("\t.LEVEL 2.0w\n");
5367 else if (TARGET_PA_20)
5368 aputs ("\t.LEVEL 2.0\n");
5369 else if (TARGET_PA_11)
5370 aputs ("\t.LEVEL 1.1\n");
5372 aputs ("\t.LEVEL 1.0\n");
5376 pa_file_start_space (int sortspace)
5378 aputs ("\t.SPACE $PRIVATE$");
5381 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5382 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5383 "\n\t.SPACE $TEXT$");
5386 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5387 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5391 pa_file_start_file (int want_version)
5393 if (write_symbols != NO_DEBUG)
5395 output_file_directive (asm_out_file, main_input_filename);
5397 aputs ("\t.version\t\"01.01\"\n");
5402 pa_file_start_mcount (const char *aswhat)
5405 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5409 pa_elf_file_start (void)
5411 pa_file_start_level ();
5412 pa_file_start_mcount ("ENTRY");
5413 pa_file_start_file (0);
5417 pa_som_file_start (void)
5419 pa_file_start_level ();
5420 pa_file_start_space (0);
5421 aputs ("\t.IMPORT $global$,DATA\n"
5422 "\t.IMPORT $$dyncall,MILLICODE\n");
5423 pa_file_start_mcount ("CODE");
5424 pa_file_start_file (0);
5428 pa_linux_file_start (void)
5430 pa_file_start_file (1);
5431 pa_file_start_level ();
5432 pa_file_start_mcount ("CODE");
5436 pa_hpux64_gas_file_start (void)
5438 pa_file_start_level ();
5439 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5441 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5443 pa_file_start_file (1);
5447 pa_hpux64_hpas_file_start (void)
5449 pa_file_start_level ();
5450 pa_file_start_space (1);
5451 pa_file_start_mcount ("CODE");
5452 pa_file_start_file (0);
5456 /* Search the deferred plabel list for SYMBOL and return its internal
5457 label. If an entry for SYMBOL is not found, a new entry is created. */
5460 get_deferred_plabel (rtx symbol)
5462 const char *fname = XSTR (symbol, 0);
5465 /* See if we have already put this function on the list of deferred
5466 plabels. This list is generally small, so a liner search is not
5467 too ugly. If it proves too slow replace it with something faster. */
5468 for (i = 0; i < n_deferred_plabels; i++)
5469 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5472 /* If the deferred plabel list is empty, or this entry was not found
5473 on the list, create a new entry on the list. */
5474 if (deferred_plabels == NULL || i == n_deferred_plabels)
5478 if (deferred_plabels == 0)
5479 deferred_plabels = ggc_alloc_deferred_plabel ();
5481 deferred_plabels = GGC_RESIZEVEC (struct deferred_plabel,
5483 n_deferred_plabels + 1);
5485 i = n_deferred_plabels++;
5486 deferred_plabels[i].internal_label = gen_label_rtx ();
5487 deferred_plabels[i].symbol = symbol;
5489 /* Gross. We have just implicitly taken the address of this
5490 function. Mark it in the same manner as assemble_name. */
5491 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5493 mark_referenced (id);
5496 return deferred_plabels[i].internal_label;
5500 output_deferred_plabels (void)
5504 /* If we have some deferred plabels, then we need to switch into the
5505 data or readonly data section, and align it to a 4 byte boundary
5506 before outputting the deferred plabels. */
5507 if (n_deferred_plabels)
5509 switch_to_section (flag_pic ? data_section : readonly_data_section);
5510 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5513 /* Now output the deferred plabels. */
5514 for (i = 0; i < n_deferred_plabels; i++)
5516 targetm.asm_out.internal_label (asm_out_file, "L",
5517 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5518 assemble_integer (deferred_plabels[i].symbol,
5519 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5523 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5524 /* Initialize optabs to point to HPUX long double emulation routines. */
5526 pa_hpux_init_libfuncs (void)
5528 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5529 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5530 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5531 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5532 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5533 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5534 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5535 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5536 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5538 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5539 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5540 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5541 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5542 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5543 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5544 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5546 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5547 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5548 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5549 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5551 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5552 ? "__U_Qfcnvfxt_quad_to_sgl"
5553 : "_U_Qfcnvfxt_quad_to_sgl");
5554 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5555 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5556 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5558 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5559 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5560 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_U_Qfcnvxf_usgl_to_quad");
5561 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_U_Qfcnvxf_udbl_to_quad");
5565 /* HP's millicode routines mean something special to the assembler.
5566 Keep track of which ones we have used. */
5568 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5569 static void import_milli (enum millicodes);
5570 static char imported[(int) end1000];
5571 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5572 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5573 #define MILLI_START 10
5576 import_milli (enum millicodes code)
5578 char str[sizeof (import_string)];
5580 if (!imported[(int) code])
5582 imported[(int) code] = 1;
5583 strcpy (str, import_string);
5584 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5585 output_asm_insn (str, 0);
5589 /* The register constraints have put the operands and return value in
5590 the proper registers. */
5593 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5595 import_milli (mulI);
5596 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5599 /* Emit the rtl for doing a division by a constant. */
5601 /* Do magic division millicodes exist for this value? */
5602 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5604 /* We'll use an array to keep track of the magic millicodes and
5605 whether or not we've used them already. [n][0] is signed, [n][1] is
5608 static int div_milli[16][2];
5611 emit_hpdiv_const (rtx *operands, int unsignedp)
5613 if (GET_CODE (operands[2]) == CONST_INT
5614 && INTVAL (operands[2]) > 0
5615 && INTVAL (operands[2]) < 16
5616 && magic_milli[INTVAL (operands[2])])
5618 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5620 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5624 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5625 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5627 gen_rtx_REG (SImode, 26),
5629 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5630 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5631 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5632 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5633 gen_rtx_CLOBBER (VOIDmode, ret))));
5634 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5641 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5645 /* If the divisor is a constant, try to use one of the special
5647 if (GET_CODE (operands[0]) == CONST_INT)
5649 static char buf[100];
5650 divisor = INTVAL (operands[0]);
5651 if (!div_milli[divisor][unsignedp])
5653 div_milli[divisor][unsignedp] = 1;
5655 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5657 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5661 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5662 INTVAL (operands[0]));
5663 return output_millicode_call (insn,
5664 gen_rtx_SYMBOL_REF (SImode, buf));
5668 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5669 INTVAL (operands[0]));
5670 return output_millicode_call (insn,
5671 gen_rtx_SYMBOL_REF (SImode, buf));
5674 /* Divisor isn't a special constant. */
5679 import_milli (divU);
5680 return output_millicode_call (insn,
5681 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5685 import_milli (divI);
5686 return output_millicode_call (insn,
5687 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5692 /* Output a $$rem millicode to do mod. */
5695 output_mod_insn (int unsignedp, rtx insn)
5699 import_milli (remU);
5700 return output_millicode_call (insn,
5701 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5705 import_milli (remI);
5706 return output_millicode_call (insn,
5707 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5712 output_arg_descriptor (rtx call_insn)
5714 const char *arg_regs[4];
5715 enum machine_mode arg_mode;
5717 int i, output_flag = 0;
5720 /* We neither need nor want argument location descriptors for the
5721 64bit runtime environment or the ELF32 environment. */
5722 if (TARGET_64BIT || TARGET_ELF32)
5725 for (i = 0; i < 4; i++)
5728 /* Specify explicitly that no argument relocations should take place
5729 if using the portable runtime calling conventions. */
5730 if (TARGET_PORTABLE_RUNTIME)
5732 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5737 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5738 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5739 link; link = XEXP (link, 1))
5741 rtx use = XEXP (link, 0);
5743 if (! (GET_CODE (use) == USE
5744 && GET_CODE (XEXP (use, 0)) == REG
5745 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5748 arg_mode = GET_MODE (XEXP (use, 0));
5749 regno = REGNO (XEXP (use, 0));
5750 if (regno >= 23 && regno <= 26)
5752 arg_regs[26 - regno] = "GR";
5753 if (arg_mode == DImode)
5754 arg_regs[25 - regno] = "GR";
5756 else if (regno >= 32 && regno <= 39)
5758 if (arg_mode == SFmode)
5759 arg_regs[(regno - 32) / 2] = "FR";
5762 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5763 arg_regs[(regno - 34) / 2] = "FR";
5764 arg_regs[(regno - 34) / 2 + 1] = "FU";
5766 arg_regs[(regno - 34) / 2] = "FU";
5767 arg_regs[(regno - 34) / 2 + 1] = "FR";
5772 fputs ("\t.CALL ", asm_out_file);
5773 for (i = 0; i < 4; i++)
5778 fputc (',', asm_out_file);
5779 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5782 fputc ('\n', asm_out_file);
5786 pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
5787 enum machine_mode mode, secondary_reload_info *sri)
5790 enum reg_class rclass = (enum reg_class) rclass_i;
5792 /* Handle the easy stuff first. */
5793 if (rclass == R1_REGS)
5799 if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
5805 /* If we have something like (mem (mem (...)), we can safely assume the
5806 inner MEM will end up in a general register after reloading, so there's
5807 no need for a secondary reload. */
5808 if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
5811 /* Trying to load a constant into a FP register during PIC code
5812 generation requires %r1 as a scratch register. */
5814 && (mode == SImode || mode == DImode)
5815 && FP_REG_CLASS_P (rclass)
5816 && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
5818 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5819 : CODE_FOR_reload_indi_r1);
5823 /* Secondary reloads of symbolic operands require %r1 as a scratch
5824 register when we're generating PIC code and when the operand isn't
5826 if (symbolic_expression_p (x))
5828 if (GET_CODE (x) == HIGH)
5831 if (flag_pic || !read_only_operand (x, VOIDmode))
5833 gcc_assert (mode == SImode || mode == DImode);
5834 sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
5835 : CODE_FOR_reload_indi_r1);
5840 /* Profiling showed the PA port spends about 1.3% of its compilation
5841 time in true_regnum from calls inside pa_secondary_reload_class. */
5842 if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
5843 regno = true_regnum (x);
5845 /* In order to allow 14-bit displacements in integer loads and stores,
5846 we need to prevent reload from generating out of range integer mode
5847 loads and stores to the floating point registers. Previously, we
5848 used to call for a secondary reload and have emit_move_sequence()
5849 fix the instruction sequence. However, reload occasionally wouldn't
5850 generate the reload and we would end up with an invalid REG+D memory
5851 address. So, now we use an intermediate general register for most
5852 memory loads and stores. */
5853 if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5854 && GET_MODE_CLASS (mode) == MODE_INT
5855 && FP_REG_CLASS_P (rclass))
5857 /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
5858 the secondary reload needed for a pseudo. It never passes a
5860 if (GET_CODE (x) == MEM)
5864 /* We don't need an intermediate for indexed and LO_SUM DLT
5865 memory addresses. When INT14_OK_STRICT is true, it might
5866 appear that we could directly allow register indirect
5867 memory addresses. However, this doesn't work because we
5868 don't support SUBREGs in floating-point register copies
5869 and reload doesn't tell us when it's going to use a SUBREG. */
5870 if (IS_INDEX_ADDR_P (x)
5871 || IS_LO_SUM_DLT_ADDR_P (x))
5874 /* Otherwise, we need an intermediate general register. */
5875 return GENERAL_REGS;
5878 /* Request a secondary reload with a general scratch register
5879 for everthing else. ??? Could symbolic operands be handled
5880 directly when generating non-pic PA 2.0 code? */
5882 ? direct_optab_handler (reload_in_optab, mode)
5883 : direct_optab_handler (reload_out_optab, mode));
5887 /* We need a secondary register (GPR) for copies between the SAR
5888 and anything other than a general register. */
5889 if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32))
5892 ? direct_optab_handler (reload_in_optab, mode)
5893 : direct_optab_handler (reload_out_optab, mode));
5897 /* A SAR<->FP register copy requires a secondary register (GPR) as
5898 well as secondary memory. */
5899 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5900 && (REGNO_REG_CLASS (regno) == SHIFT_REGS
5901 && FP_REG_CLASS_P (rclass)))
5903 ? direct_optab_handler (reload_in_optab, mode)
5904 : direct_optab_handler (reload_out_optab, mode));
5909 /* Implement TARGET_EXTRA_LIVE_ON_ENTRY. The argument pointer
5910 is only marked as live on entry by df-scan when it is a fixed
5911 register. It isn't a fixed register in the 64-bit runtime,
5912 so we need to mark it here. */
5915 pa_extra_live_on_entry (bitmap regs)
5918 bitmap_set_bit (regs, ARG_POINTER_REGNUM);
5921 /* Implement EH_RETURN_HANDLER_RTX. The MEM needs to be volatile
5922 to prevent it from being deleted. */
5925 pa_eh_return_handler_rtx (void)
5929 tmp = gen_rtx_PLUS (word_mode, hard_frame_pointer_rtx,
5930 TARGET_64BIT ? GEN_INT (-16) : GEN_INT (-20));
5931 tmp = gen_rtx_MEM (word_mode, tmp);
5936 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5937 by invisible reference. As a GCC extension, we also pass anything
5938 with a zero or variable size by reference.
5940 The 64-bit runtime does not describe passing any types by invisible
5941 reference. The internals of GCC can't currently handle passing
5942 empty structures, and zero or variable length arrays when they are
5943 not passed entirely on the stack or by reference. Thus, as a GCC
5944 extension, we pass these types by reference. The HP compiler doesn't
5945 support these types, so hopefully there shouldn't be any compatibility
5946 issues. This may have to be revisited when HP releases a C99 compiler
5947 or updates the ABI. */
5950 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5951 enum machine_mode mode, const_tree type,
5952 bool named ATTRIBUTE_UNUSED)
5957 size = int_size_in_bytes (type);
5959 size = GET_MODE_SIZE (mode);
5964 return size <= 0 || size > 8;
5968 function_arg_padding (enum machine_mode mode, const_tree type)
5973 && (AGGREGATE_TYPE_P (type)
5974 || TREE_CODE (type) == COMPLEX_TYPE
5975 || TREE_CODE (type) == VECTOR_TYPE)))
5977 /* Return none if justification is not required. */
5979 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5980 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5983 /* The directions set here are ignored when a BLKmode argument larger
5984 than a word is placed in a register. Different code is used for
5985 the stack and registers. This makes it difficult to have a
5986 consistent data representation for both the stack and registers.
5987 For both runtimes, the justification and padding for arguments on
5988 the stack and in registers should be identical. */
5990 /* The 64-bit runtime specifies left justification for aggregates. */
5993 /* The 32-bit runtime architecture specifies right justification.
5994 When the argument is passed on the stack, the argument is padded
5995 with garbage on the left. The HP compiler pads with zeros. */
5999 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6006 /* Do what is necessary for `va_start'. We look at the current function
6007 to determine if stdargs or varargs is used and fill in an initial
6008 va_list. A pointer to this constructor is returned. */
6011 hppa_builtin_saveregs (void)
6014 tree fntype = TREE_TYPE (current_function_decl);
6015 int argadj = ((!stdarg_p (fntype))
6016 ? UNITS_PER_WORD : 0);
6019 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
6021 offset = crtl->args.arg_offset_rtx;
6027 /* Adjust for varargs/stdarg differences. */
6029 offset = plus_constant (crtl->args.arg_offset_rtx, -argadj);
6031 offset = crtl->args.arg_offset_rtx;
6033 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6034 from the incoming arg pointer and growing to larger addresses. */
6035 for (i = 26, off = -64; i >= 19; i--, off += 8)
6036 emit_move_insn (gen_rtx_MEM (word_mode,
6037 plus_constant (arg_pointer_rtx, off)),
6038 gen_rtx_REG (word_mode, i));
6040 /* The incoming args pointer points just beyond the flushback area;
6041 normally this is not a serious concern. However, when we are doing
6042 varargs/stdargs we want to make the arg pointer point to the start
6043 of the incoming argument area. */
6044 emit_move_insn (virtual_incoming_args_rtx,
6045 plus_constant (arg_pointer_rtx, -64));
6047 /* Now return a pointer to the first anonymous argument. */
6048 return copy_to_reg (expand_binop (Pmode, add_optab,
6049 virtual_incoming_args_rtx,
6050 offset, 0, 0, OPTAB_LIB_WIDEN));
6053 /* Store general registers on the stack. */
6054 dest = gen_rtx_MEM (BLKmode,
6055 plus_constant (crtl->args.internal_arg_pointer,
6057 set_mem_alias_set (dest, get_varargs_alias_set ());
6058 set_mem_align (dest, BITS_PER_WORD);
6059 move_block_from_reg (23, dest, 4);
6061 /* move_block_from_reg will emit code to store the argument registers
6062 individually as scalar stores.
6064 However, other insns may later load from the same addresses for
6065 a structure load (passing a struct to a varargs routine).
6067 The alias code assumes that such aliasing can never happen, so we
6068 have to keep memory referencing insns from moving up beyond the
6069 last argument register store. So we emit a blockage insn here. */
6070 emit_insn (gen_blockage ());
6072 return copy_to_reg (expand_binop (Pmode, add_optab,
6073 crtl->args.internal_arg_pointer,
6074 offset, 0, 0, OPTAB_LIB_WIDEN));
6078 hppa_va_start (tree valist, rtx nextarg)
6080 nextarg = expand_builtin_saveregs ();
6081 std_expand_builtin_va_start (valist, nextarg);
6085 hppa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p,
6090 /* Args grow upward. We can use the generic routines. */
6091 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6093 else /* !TARGET_64BIT */
6095 tree ptr = build_pointer_type (type);
6098 unsigned int size, ofs;
6101 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6105 ptr = build_pointer_type (type);
6107 size = int_size_in_bytes (type);
6108 valist_type = TREE_TYPE (valist);
6110 /* Args grow down. Not handled by generic routines. */
6112 u = fold_convert (sizetype, size_in_bytes (type));
6113 u = fold_build1 (NEGATE_EXPR, sizetype, u);
6114 t = build2 (POINTER_PLUS_EXPR, valist_type, valist, u);
6116 /* Align to 4 or 8 byte boundary depending on argument size. */
6118 u = build_int_cst (TREE_TYPE (t), (HOST_WIDE_INT)(size > 4 ? -8 : -4));
6119 t = build2 (BIT_AND_EXPR, TREE_TYPE (t), t, u);
6120 t = fold_convert (valist_type, t);
6122 t = build2 (MODIFY_EXPR, valist_type, valist, t);
6124 ofs = (8 - size) % 4;
6128 t = build2 (POINTER_PLUS_EXPR, valist_type, t, u);
6131 t = fold_convert (ptr, t);
6132 t = build_va_arg_indirect_ref (t);
6135 t = build_va_arg_indirect_ref (t);
6141 /* True if MODE is valid for the target. By "valid", we mean able to
6142 be manipulated in non-trivial ways. In particular, this means all
6143 the arithmetic is supported.
6145 Currently, TImode is not valid as the HP 64-bit runtime documentation
6146 doesn't document the alignment and calling conventions for this type.
6147 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
6148 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
6151 pa_scalar_mode_supported_p (enum machine_mode mode)
6153 int precision = GET_MODE_PRECISION (mode);
6155 switch (GET_MODE_CLASS (mode))
6157 case MODE_PARTIAL_INT:
6159 if (precision == CHAR_TYPE_SIZE)
6161 if (precision == SHORT_TYPE_SIZE)
6163 if (precision == INT_TYPE_SIZE)
6165 if (precision == LONG_TYPE_SIZE)
6167 if (precision == LONG_LONG_TYPE_SIZE)
6172 if (precision == FLOAT_TYPE_SIZE)
6174 if (precision == DOUBLE_TYPE_SIZE)
6176 if (precision == LONG_DOUBLE_TYPE_SIZE)
6180 case MODE_DECIMAL_FLOAT:
6188 /* Return TRUE if INSN, a jump insn, has an unfilled delay slot and
6189 it branches to the next real instruction. Otherwise, return FALSE. */
6192 branch_to_delay_slot_p (rtx insn)
6194 if (dbr_sequence_length ())
6197 return next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn);
6200 /* Return TRUE if INSN, a jump insn, needs a nop in its delay slot.
6202 This occurs when INSN has an unfilled delay slot and is followed
6203 by an ASM_INPUT. Disaster can occur if the ASM_INPUT is empty and
6204 the jump branches into the delay slot. So, we add a nop in the delay
6205 slot just to be safe. This messes up our instruction count, but we
6206 don't know how big the ASM_INPUT insn is anyway. */
6209 branch_needs_nop_p (rtx insn)
6213 if (dbr_sequence_length ())
6216 next_insn = next_real_insn (insn);
6217 return GET_CODE (PATTERN (next_insn)) == ASM_INPUT;
6220 /* This routine handles all the normal conditional branch sequences we
6221 might need to generate. It handles compare immediate vs compare
6222 register, nullification of delay slots, varying length branches,
6223 negated branches, and all combinations of the above. It returns the
6224 output appropriate to emit the branch corresponding to all given
6228 output_cbranch (rtx *operands, int negated, rtx insn)
6230 static char buf[100];
6232 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6233 int length = get_attr_length (insn);
6236 /* A conditional branch to the following instruction (e.g. the delay slot)
6237 is asking for a disaster. This can happen when not optimizing and
6238 when jump optimization fails.
6240 While it is usually safe to emit nothing, this can fail if the
6241 preceding instruction is a nullified branch with an empty delay
6242 slot and the same branch target as this branch. We could check
6243 for this but jump optimization should eliminate nop jumps. It
6244 is always safe to emit a nop. */
6245 if (branch_to_delay_slot_p (insn))
6248 /* The doubleword form of the cmpib instruction doesn't have the LEU
6249 and GTU conditions while the cmpb instruction does. Since we accept
6250 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6251 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6252 operands[2] = gen_rtx_REG (DImode, 0);
6253 if (GET_MODE (operands[2]) == DImode && operands[1] == const0_rtx)
6254 operands[1] = gen_rtx_REG (DImode, 0);
6256 /* If this is a long branch with its delay slot unfilled, set `nullify'
6257 as it can nullify the delay slot and save a nop. */
6258 if (length == 8 && dbr_sequence_length () == 0)
6261 /* If this is a short forward conditional branch which did not get
6262 its delay slot filled, the delay slot can still be nullified. */
6263 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6264 nullify = forward_branch_p (insn);
6266 /* A forward branch over a single nullified insn can be done with a
6267 comclr instruction. This avoids a single cycle penalty due to
6268 mis-predicted branch if we fall through (branch not taken). */
6270 && next_real_insn (insn) != 0
6271 && get_attr_length (next_real_insn (insn)) == 4
6272 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6278 /* All short conditional branches except backwards with an unfilled
6282 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6284 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6285 if (GET_MODE (operands[1]) == DImode)
6288 strcat (buf, "%B3");
6290 strcat (buf, "%S3");
6292 strcat (buf, " %2,%r1,%%r0");
6295 if (branch_needs_nop_p (insn))
6296 strcat (buf, ",n %2,%r1,%0%#");
6298 strcat (buf, ",n %2,%r1,%0");
6301 strcat (buf, " %2,%r1,%0");
6304 /* All long conditionals. Note a short backward branch with an
6305 unfilled delay slot is treated just like a long backward branch
6306 with an unfilled delay slot. */
6308 /* Handle weird backwards branch with a filled delay slot
6309 which is nullified. */
6310 if (dbr_sequence_length () != 0
6311 && ! forward_branch_p (insn)
6314 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6315 if (GET_MODE (operands[1]) == DImode)
6318 strcat (buf, "%S3");
6320 strcat (buf, "%B3");
6321 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6323 /* Handle short backwards branch with an unfilled delay slot.
6324 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6325 taken and untaken branches. */
6326 else if (dbr_sequence_length () == 0
6327 && ! forward_branch_p (insn)
6328 && INSN_ADDRESSES_SET_P ()
6329 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6330 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6332 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6333 if (GET_MODE (operands[1]) == DImode)
6336 strcat (buf, "%B3 %2,%r1,%0%#");
6338 strcat (buf, "%S3 %2,%r1,%0%#");
6342 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6343 if (GET_MODE (operands[1]) == DImode)
6346 strcat (buf, "%S3");
6348 strcat (buf, "%B3");
6350 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6352 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6357 /* The reversed conditional branch must branch over one additional
6358 instruction if the delay slot is filled and needs to be extracted
6359 by output_lbranch. If the delay slot is empty or this is a
6360 nullified forward branch, the instruction after the reversed
6361 condition branch must be nullified. */
6362 if (dbr_sequence_length () == 0
6363 || (nullify && forward_branch_p (insn)))
6367 operands[4] = GEN_INT (length);
6372 operands[4] = GEN_INT (length + 4);
6375 /* Create a reversed conditional branch which branches around
6376 the following insns. */
6377 if (GET_MODE (operands[1]) != DImode)
6383 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6386 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6392 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6395 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6404 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6407 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6413 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6416 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6420 output_asm_insn (buf, operands);
6421 return output_lbranch (operands[0], insn, xdelay);
6426 /* This routine handles output of long unconditional branches that
6427 exceed the maximum range of a simple branch instruction. Since
6428 we don't have a register available for the branch, we save register
6429 %r1 in the frame marker, load the branch destination DEST into %r1,
6430 execute the branch, and restore %r1 in the delay slot of the branch.
6432 Since long branches may have an insn in the delay slot and the
6433 delay slot is used to restore %r1, we in general need to extract
6434 this insn and execute it before the branch. However, to facilitate
6435 use of this function by conditional branches, we also provide an
6436 option to not extract the delay insn so that it will be emitted
6437 after the long branch. So, if there is an insn in the delay slot,
6438 it is extracted if XDELAY is nonzero.
6440 The lengths of the various long-branch sequences are 20, 16 and 24
6441 bytes for the portable runtime, non-PIC and PIC cases, respectively. */
6444 output_lbranch (rtx dest, rtx insn, int xdelay)
6448 xoperands[0] = dest;
6450 /* First, free up the delay slot. */
6451 if (xdelay && dbr_sequence_length () != 0)
6453 /* We can't handle a jump in the delay slot. */
6454 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6456 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6459 /* Now delete the delay insn. */
6460 SET_INSN_DELETED (NEXT_INSN (insn));
6463 /* Output an insn to save %r1. The runtime documentation doesn't
6464 specify whether the "Clean Up" slot in the callers frame can
6465 be clobbered by the callee. It isn't copied by HP's builtin
6466 alloca, so this suggests that it can be clobbered if necessary.
6467 The "Static Link" location is copied by HP builtin alloca, so
6468 we avoid using it. Using the cleanup slot might be a problem
6469 if we have to interoperate with languages that pass cleanup
6470 information. However, it should be possible to handle these
6471 situations with GCC's asm feature.
6473 The "Current RP" slot is reserved for the called procedure, so
6474 we try to use it when we don't have a frame of our own. It's
6475 rather unlikely that we won't have a frame when we need to emit
6478 Really the way to go long term is a register scavenger; goto
6479 the target of the jump and find a register which we can use
6480 as a scratch to hold the value in %r1. Then, we wouldn't have
6481 to free up the delay slot or clobber a slot that may be needed
6482 for other purposes. */
6485 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6486 /* Use the return pointer slot in the frame marker. */
6487 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6489 /* Use the slot at -40 in the frame marker since HP builtin
6490 alloca doesn't copy it. */
6491 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6495 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6496 /* Use the return pointer slot in the frame marker. */
6497 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6499 /* Use the "Clean Up" slot in the frame marker. In GCC,
6500 the only other use of this location is for copying a
6501 floating point double argument from a floating-point
6502 register to two general registers. The copy is done
6503 as an "atomic" operation when outputting a call, so it
6504 won't interfere with our using the location here. */
6505 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6508 if (TARGET_PORTABLE_RUNTIME)
6510 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6511 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6512 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6516 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6517 if (TARGET_SOM || !TARGET_GAS)
6519 xoperands[1] = gen_label_rtx ();
6520 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6521 targetm.asm_out.internal_label (asm_out_file, "L",
6522 CODE_LABEL_NUMBER (xoperands[1]));
6523 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6527 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6528 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6530 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6533 /* Now output a very long branch to the original target. */
6534 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6536 /* Now restore the value of %r1 in the delay slot. */
6539 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6540 return "ldd -16(%%r30),%%r1";
6542 return "ldd -40(%%r30),%%r1";
6546 if (actual_fsize == 0 && !df_regs_ever_live_p (2))
6547 return "ldw -20(%%r30),%%r1";
6549 return "ldw -12(%%r30),%%r1";
6553 /* This routine handles all the branch-on-bit conditional branch sequences we
6554 might need to generate. It handles nullification of delay slots,
6555 varying length branches, negated branches and all combinations of the
6556 above. it returns the appropriate output template to emit the branch. */
6559 output_bb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6561 static char buf[100];
6563 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6564 int length = get_attr_length (insn);
6567 /* A conditional branch to the following instruction (e.g. the delay slot) is
6568 asking for a disaster. I do not think this can happen as this pattern
6569 is only used when optimizing; jump optimization should eliminate the
6570 jump. But be prepared just in case. */
6572 if (branch_to_delay_slot_p (insn))
6575 /* If this is a long branch with its delay slot unfilled, set `nullify'
6576 as it can nullify the delay slot and save a nop. */
6577 if (length == 8 && dbr_sequence_length () == 0)
6580 /* If this is a short forward conditional branch which did not get
6581 its delay slot filled, the delay slot can still be nullified. */
6582 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6583 nullify = forward_branch_p (insn);
6585 /* A forward branch over a single nullified insn can be done with a
6586 extrs instruction. This avoids a single cycle penalty due to
6587 mis-predicted branch if we fall through (branch not taken). */
6590 && next_real_insn (insn) != 0
6591 && get_attr_length (next_real_insn (insn)) == 4
6592 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6599 /* All short conditional branches except backwards with an unfilled
6603 strcpy (buf, "{extrs,|extrw,s,}");
6605 strcpy (buf, "bb,");
6606 if (useskip && GET_MODE (operands[0]) == DImode)
6607 strcpy (buf, "extrd,s,*");
6608 else if (GET_MODE (operands[0]) == DImode)
6609 strcpy (buf, "bb,*");
6610 if ((which == 0 && negated)
6611 || (which == 1 && ! negated))
6616 strcat (buf, " %0,%1,1,%%r0");
6617 else if (nullify && negated)
6619 if (branch_needs_nop_p (insn))
6620 strcat (buf, ",n %0,%1,%3%#");
6622 strcat (buf, ",n %0,%1,%3");
6624 else if (nullify && ! negated)
6626 if (branch_needs_nop_p (insn))
6627 strcat (buf, ",n %0,%1,%2%#");
6629 strcat (buf, ",n %0,%1,%2");
6631 else if (! nullify && negated)
6632 strcat (buf, " %0,%1,%3");
6633 else if (! nullify && ! negated)
6634 strcat (buf, " %0,%1,%2");
6637 /* All long conditionals. Note a short backward branch with an
6638 unfilled delay slot is treated just like a long backward branch
6639 with an unfilled delay slot. */
6641 /* Handle weird backwards branch with a filled delay slot
6642 which is nullified. */
6643 if (dbr_sequence_length () != 0
6644 && ! forward_branch_p (insn)
6647 strcpy (buf, "bb,");
6648 if (GET_MODE (operands[0]) == DImode)
6650 if ((which == 0 && negated)
6651 || (which == 1 && ! negated))
6656 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6658 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6660 /* Handle short backwards branch with an unfilled delay slot.
6661 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6662 taken and untaken branches. */
6663 else if (dbr_sequence_length () == 0
6664 && ! forward_branch_p (insn)
6665 && INSN_ADDRESSES_SET_P ()
6666 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6667 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6669 strcpy (buf, "bb,");
6670 if (GET_MODE (operands[0]) == DImode)
6672 if ((which == 0 && negated)
6673 || (which == 1 && ! negated))
6678 strcat (buf, " %0,%1,%3%#");
6680 strcat (buf, " %0,%1,%2%#");
6684 if (GET_MODE (operands[0]) == DImode)
6685 strcpy (buf, "extrd,s,*");
6687 strcpy (buf, "{extrs,|extrw,s,}");
6688 if ((which == 0 && negated)
6689 || (which == 1 && ! negated))
6693 if (nullify && negated)
6694 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6695 else if (nullify && ! negated)
6696 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6698 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6700 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6705 /* The reversed conditional branch must branch over one additional
6706 instruction if the delay slot is filled and needs to be extracted
6707 by output_lbranch. If the delay slot is empty or this is a
6708 nullified forward branch, the instruction after the reversed
6709 condition branch must be nullified. */
6710 if (dbr_sequence_length () == 0
6711 || (nullify && forward_branch_p (insn)))
6715 operands[4] = GEN_INT (length);
6720 operands[4] = GEN_INT (length + 4);
6723 if (GET_MODE (operands[0]) == DImode)
6724 strcpy (buf, "bb,*");
6726 strcpy (buf, "bb,");
6727 if ((which == 0 && negated)
6728 || (which == 1 && !negated))
6733 strcat (buf, ",n %0,%1,.+%4");
6735 strcat (buf, " %0,%1,.+%4");
6736 output_asm_insn (buf, operands);
6737 return output_lbranch (negated ? operands[3] : operands[2],
6743 /* This routine handles all the branch-on-variable-bit conditional branch
6744 sequences we might need to generate. It handles nullification of delay
6745 slots, varying length branches, negated branches and all combinations
6746 of the above. it returns the appropriate output template to emit the
6750 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int negated, rtx insn, int which)
6752 static char buf[100];
6754 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6755 int length = get_attr_length (insn);
6758 /* A conditional branch to the following instruction (e.g. the delay slot) is
6759 asking for a disaster. I do not think this can happen as this pattern
6760 is only used when optimizing; jump optimization should eliminate the
6761 jump. But be prepared just in case. */
6763 if (branch_to_delay_slot_p (insn))
6766 /* If this is a long branch with its delay slot unfilled, set `nullify'
6767 as it can nullify the delay slot and save a nop. */
6768 if (length == 8 && dbr_sequence_length () == 0)
6771 /* If this is a short forward conditional branch which did not get
6772 its delay slot filled, the delay slot can still be nullified. */
6773 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6774 nullify = forward_branch_p (insn);
6776 /* A forward branch over a single nullified insn can be done with a
6777 extrs instruction. This avoids a single cycle penalty due to
6778 mis-predicted branch if we fall through (branch not taken). */
6781 && next_real_insn (insn) != 0
6782 && get_attr_length (next_real_insn (insn)) == 4
6783 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6790 /* All short conditional branches except backwards with an unfilled
6794 strcpy (buf, "{vextrs,|extrw,s,}");
6796 strcpy (buf, "{bvb,|bb,}");
6797 if (useskip && GET_MODE (operands[0]) == DImode)
6798 strcpy (buf, "extrd,s,*");
6799 else if (GET_MODE (operands[0]) == DImode)
6800 strcpy (buf, "bb,*");
6801 if ((which == 0 && negated)
6802 || (which == 1 && ! negated))
6807 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6808 else if (nullify && negated)
6810 if (branch_needs_nop_p (insn))
6811 strcat (buf, "{,n %0,%3%#|,n %0,%%sar,%3%#}");
6813 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6815 else if (nullify && ! negated)
6817 if (branch_needs_nop_p (insn))
6818 strcat (buf, "{,n %0,%2%#|,n %0,%%sar,%2%#}");
6820 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6822 else if (! nullify && negated)
6823 strcat (buf, "{ %0,%3| %0,%%sar,%3}");
6824 else if (! nullify && ! negated)
6825 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6828 /* All long conditionals. Note a short backward branch with an
6829 unfilled delay slot is treated just like a long backward branch
6830 with an unfilled delay slot. */
6832 /* Handle weird backwards branch with a filled delay slot
6833 which is nullified. */
6834 if (dbr_sequence_length () != 0
6835 && ! forward_branch_p (insn)
6838 strcpy (buf, "{bvb,|bb,}");
6839 if (GET_MODE (operands[0]) == DImode)
6841 if ((which == 0 && negated)
6842 || (which == 1 && ! negated))
6847 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6849 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6851 /* Handle short backwards branch with an unfilled delay slot.
6852 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6853 taken and untaken branches. */
6854 else if (dbr_sequence_length () == 0
6855 && ! forward_branch_p (insn)
6856 && INSN_ADDRESSES_SET_P ()
6857 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6858 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6860 strcpy (buf, "{bvb,|bb,}");
6861 if (GET_MODE (operands[0]) == DImode)
6863 if ((which == 0 && negated)
6864 || (which == 1 && ! negated))
6869 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6871 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6875 strcpy (buf, "{vextrs,|extrw,s,}");
6876 if (GET_MODE (operands[0]) == DImode)
6877 strcpy (buf, "extrd,s,*");
6878 if ((which == 0 && negated)
6879 || (which == 1 && ! negated))
6883 if (nullify && negated)
6884 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6885 else if (nullify && ! negated)
6886 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6888 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6890 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6895 /* The reversed conditional branch must branch over one additional
6896 instruction if the delay slot is filled and needs to be extracted
6897 by output_lbranch. If the delay slot is empty or this is a
6898 nullified forward branch, the instruction after the reversed
6899 condition branch must be nullified. */
6900 if (dbr_sequence_length () == 0
6901 || (nullify && forward_branch_p (insn)))
6905 operands[4] = GEN_INT (length);
6910 operands[4] = GEN_INT (length + 4);
6913 if (GET_MODE (operands[0]) == DImode)
6914 strcpy (buf, "bb,*");
6916 strcpy (buf, "{bvb,|bb,}");
6917 if ((which == 0 && negated)
6918 || (which == 1 && !negated))
6923 strcat (buf, ",n {%0,.+%4|%0,%%sar,.+%4}");
6925 strcat (buf, " {%0,.+%4|%0,%%sar,.+%4}");
6926 output_asm_insn (buf, operands);
6927 return output_lbranch (negated ? operands[3] : operands[2],
6933 /* Return the output template for emitting a dbra type insn.
6935 Note it may perform some output operations on its own before
6936 returning the final output string. */
6938 output_dbra (rtx *operands, rtx insn, int which_alternative)
6940 int length = get_attr_length (insn);
6942 /* A conditional branch to the following instruction (e.g. the delay slot) is
6943 asking for a disaster. Be prepared! */
6945 if (branch_to_delay_slot_p (insn))
6947 if (which_alternative == 0)
6948 return "ldo %1(%0),%0";
6949 else if (which_alternative == 1)
6951 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6952 output_asm_insn ("ldw -16(%%r30),%4", operands);
6953 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6954 return "{fldws|fldw} -16(%%r30),%0";
6958 output_asm_insn ("ldw %0,%4", operands);
6959 return "ldo %1(%4),%4\n\tstw %4,%0";
6963 if (which_alternative == 0)
6965 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6968 /* If this is a long branch with its delay slot unfilled, set `nullify'
6969 as it can nullify the delay slot and save a nop. */
6970 if (length == 8 && dbr_sequence_length () == 0)
6973 /* If this is a short forward conditional branch which did not get
6974 its delay slot filled, the delay slot can still be nullified. */
6975 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6976 nullify = forward_branch_p (insn);
6983 if (branch_needs_nop_p (insn))
6984 return "addib,%C2,n %1,%0,%3%#";
6986 return "addib,%C2,n %1,%0,%3";
6989 return "addib,%C2 %1,%0,%3";
6992 /* Handle weird backwards branch with a fulled delay slot
6993 which is nullified. */
6994 if (dbr_sequence_length () != 0
6995 && ! forward_branch_p (insn)
6997 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6998 /* Handle short backwards branch with an unfilled delay slot.
6999 Using a addb;nop rather than addi;bl saves 1 cycle for both
7000 taken and untaken branches. */
7001 else if (dbr_sequence_length () == 0
7002 && ! forward_branch_p (insn)
7003 && INSN_ADDRESSES_SET_P ()
7004 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7005 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7006 return "addib,%C2 %1,%0,%3%#";
7008 /* Handle normal cases. */
7010 return "addi,%N2 %1,%0,%0\n\tb,n %3";
7012 return "addi,%N2 %1,%0,%0\n\tb %3";
7015 /* The reversed conditional branch must branch over one additional
7016 instruction if the delay slot is filled and needs to be extracted
7017 by output_lbranch. If the delay slot is empty or this is a
7018 nullified forward branch, the instruction after the reversed
7019 condition branch must be nullified. */
7020 if (dbr_sequence_length () == 0
7021 || (nullify && forward_branch_p (insn)))
7025 operands[4] = GEN_INT (length);
7030 operands[4] = GEN_INT (length + 4);
7034 output_asm_insn ("addib,%N2,n %1,%0,.+%4", operands);
7036 output_asm_insn ("addib,%N2 %1,%0,.+%4", operands);
7038 return output_lbranch (operands[3], insn, xdelay);
7042 /* Deal with gross reload from FP register case. */
7043 else if (which_alternative == 1)
7045 /* Move loop counter from FP register to MEM then into a GR,
7046 increment the GR, store the GR into MEM, and finally reload
7047 the FP register from MEM from within the branch's delay slot. */
7048 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
7050 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
7052 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
7053 else if (length == 28)
7054 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7057 operands[5] = GEN_INT (length - 16);
7058 output_asm_insn ("{comb|cmpb},%B2 %%r0,%4,.+%5", operands);
7059 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7060 return output_lbranch (operands[3], insn, 0);
7063 /* Deal with gross reload from memory case. */
7066 /* Reload loop counter from memory, the store back to memory
7067 happens in the branch's delay slot. */
7068 output_asm_insn ("ldw %0,%4", operands);
7070 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
7071 else if (length == 16)
7072 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
7075 operands[5] = GEN_INT (length - 4);
7076 output_asm_insn ("addib,%N2 %1,%4,.+%5\n\tstw %4,%0", operands);
7077 return output_lbranch (operands[3], insn, 0);
7082 /* Return the output template for emitting a movb type insn.
7084 Note it may perform some output operations on its own before
7085 returning the final output string. */
7087 output_movb (rtx *operands, rtx insn, int which_alternative,
7088 int reverse_comparison)
7090 int length = get_attr_length (insn);
7092 /* A conditional branch to the following instruction (e.g. the delay slot) is
7093 asking for a disaster. Be prepared! */
7095 if (branch_to_delay_slot_p (insn))
7097 if (which_alternative == 0)
7098 return "copy %1,%0";
7099 else if (which_alternative == 1)
7101 output_asm_insn ("stw %1,-16(%%r30)", operands);
7102 return "{fldws|fldw} -16(%%r30),%0";
7104 else if (which_alternative == 2)
7110 /* Support the second variant. */
7111 if (reverse_comparison)
7112 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
7114 if (which_alternative == 0)
7116 int nullify = INSN_ANNULLED_BRANCH_P (insn);
7119 /* If this is a long branch with its delay slot unfilled, set `nullify'
7120 as it can nullify the delay slot and save a nop. */
7121 if (length == 8 && dbr_sequence_length () == 0)
7124 /* If this is a short forward conditional branch which did not get
7125 its delay slot filled, the delay slot can still be nullified. */
7126 if (! nullify && length == 4 && dbr_sequence_length () == 0)
7127 nullify = forward_branch_p (insn);
7134 if (branch_needs_nop_p (insn))
7135 return "movb,%C2,n %1,%0,%3%#";
7137 return "movb,%C2,n %1,%0,%3";
7140 return "movb,%C2 %1,%0,%3";
7143 /* Handle weird backwards branch with a filled delay slot
7144 which is nullified. */
7145 if (dbr_sequence_length () != 0
7146 && ! forward_branch_p (insn)
7148 return "movb,%N2,n %1,%0,.+12\n\tb %3";
7150 /* Handle short backwards branch with an unfilled delay slot.
7151 Using a movb;nop rather than or;bl saves 1 cycle for both
7152 taken and untaken branches. */
7153 else if (dbr_sequence_length () == 0
7154 && ! forward_branch_p (insn)
7155 && INSN_ADDRESSES_SET_P ()
7156 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
7157 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
7158 return "movb,%C2 %1,%0,%3%#";
7159 /* Handle normal cases. */
7161 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
7163 return "or,%N2 %1,%%r0,%0\n\tb %3";
7166 /* The reversed conditional branch must branch over one additional
7167 instruction if the delay slot is filled and needs to be extracted
7168 by output_lbranch. If the delay slot is empty or this is a
7169 nullified forward branch, the instruction after the reversed
7170 condition branch must be nullified. */
7171 if (dbr_sequence_length () == 0
7172 || (nullify && forward_branch_p (insn)))
7176 operands[4] = GEN_INT (length);
7181 operands[4] = GEN_INT (length + 4);
7185 output_asm_insn ("movb,%N2,n %1,%0,.+%4", operands);
7187 output_asm_insn ("movb,%N2 %1,%0,.+%4", operands);
7189 return output_lbranch (operands[3], insn, xdelay);
7192 /* Deal with gross reload for FP destination register case. */
7193 else if (which_alternative == 1)
7195 /* Move source register to MEM, perform the branch test, then
7196 finally load the FP register from MEM from within the branch's
7198 output_asm_insn ("stw %1,-16(%%r30)", operands);
7200 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7201 else if (length == 16)
7202 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7205 operands[4] = GEN_INT (length - 4);
7206 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4", operands);
7207 output_asm_insn ("{fldws|fldw} -16(%%r30),%0", operands);
7208 return output_lbranch (operands[3], insn, 0);
7211 /* Deal with gross reload from memory case. */
7212 else if (which_alternative == 2)
7214 /* Reload loop counter from memory, the store back to memory
7215 happens in the branch's delay slot. */
7217 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7218 else if (length == 12)
7219 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7222 operands[4] = GEN_INT (length);
7223 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tstw %1,%0",
7225 return output_lbranch (operands[3], insn, 0);
7228 /* Handle SAR as a destination. */
7232 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7233 else if (length == 12)
7234 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7237 operands[4] = GEN_INT (length);
7238 output_asm_insn ("{comb|cmpb},%B2 %%r0,%1,.+%4\n\tmtsar %r1",
7240 return output_lbranch (operands[3], insn, 0);
7245 /* Copy any FP arguments in INSN into integer registers. */
7247 copy_fp_args (rtx insn)
7252 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7254 int arg_mode, regno;
7255 rtx use = XEXP (link, 0);
7257 if (! (GET_CODE (use) == USE
7258 && GET_CODE (XEXP (use, 0)) == REG
7259 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7262 arg_mode = GET_MODE (XEXP (use, 0));
7263 regno = REGNO (XEXP (use, 0));
7265 /* Is it a floating point register? */
7266 if (regno >= 32 && regno <= 39)
7268 /* Copy the FP register into an integer register via memory. */
7269 if (arg_mode == SFmode)
7271 xoperands[0] = XEXP (use, 0);
7272 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7273 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7274 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7278 xoperands[0] = XEXP (use, 0);
7279 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7280 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7281 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7282 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7288 /* Compute length of the FP argument copy sequence for INSN. */
7290 length_fp_args (rtx insn)
7295 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7297 int arg_mode, regno;
7298 rtx use = XEXP (link, 0);
7300 if (! (GET_CODE (use) == USE
7301 && GET_CODE (XEXP (use, 0)) == REG
7302 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7305 arg_mode = GET_MODE (XEXP (use, 0));
7306 regno = REGNO (XEXP (use, 0));
7308 /* Is it a floating point register? */
7309 if (regno >= 32 && regno <= 39)
7311 if (arg_mode == SFmode)
7321 /* Return the attribute length for the millicode call instruction INSN.
7322 The length must match the code generated by output_millicode_call.
7323 We include the delay slot in the returned length as it is better to
7324 over estimate the length than to under estimate it. */
7327 attr_length_millicode_call (rtx insn)
7329 unsigned long distance = -1;
7330 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7332 if (INSN_ADDRESSES_SET_P ())
7334 distance = (total + insn_current_reference_address (insn));
7335 if (distance < total)
7341 if (!TARGET_LONG_CALLS && distance < 7600000)
7346 else if (TARGET_PORTABLE_RUNTIME)
7350 if (!TARGET_LONG_CALLS && distance < 240000)
7353 if (TARGET_LONG_ABS_CALL && !flag_pic)
7360 /* INSN is a function call. It may have an unconditional jump
7363 CALL_DEST is the routine we are calling. */
7366 output_millicode_call (rtx insn, rtx call_dest)
7368 int attr_length = get_attr_length (insn);
7369 int seq_length = dbr_sequence_length ();
7374 xoperands[0] = call_dest;
7375 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7377 /* Handle the common case where we are sure that the branch will
7378 reach the beginning of the $CODE$ subspace. The within reach
7379 form of the $$sh_func_adrs call has a length of 28. Because
7380 it has an attribute type of multi, it never has a nonzero
7381 sequence length. The length of the $$sh_func_adrs is the same
7382 as certain out of reach PIC calls to other routines. */
7383 if (!TARGET_LONG_CALLS
7384 && ((seq_length == 0
7385 && (attr_length == 12
7386 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7387 || (seq_length != 0 && attr_length == 8)))
7389 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7395 /* It might seem that one insn could be saved by accessing
7396 the millicode function using the linkage table. However,
7397 this doesn't work in shared libraries and other dynamically
7398 loaded objects. Using a pc-relative sequence also avoids
7399 problems related to the implicit use of the gp register. */
7400 output_asm_insn ("b,l .+8,%%r1", xoperands);
7404 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7405 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7409 xoperands[1] = gen_label_rtx ();
7410 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7411 targetm.asm_out.internal_label (asm_out_file, "L",
7412 CODE_LABEL_NUMBER (xoperands[1]));
7413 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7416 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7418 else if (TARGET_PORTABLE_RUNTIME)
7420 /* Pure portable runtime doesn't allow be/ble; we also don't
7421 have PIC support in the assembler/linker, so this sequence
7424 /* Get the address of our target into %r1. */
7425 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7426 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7428 /* Get our return address into %r31. */
7429 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7430 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7432 /* Jump to our target address in %r1. */
7433 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7437 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7439 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7441 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7445 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7446 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7448 if (TARGET_SOM || !TARGET_GAS)
7450 /* The HP assembler can generate relocations for the
7451 difference of two symbols. GAS can do this for a
7452 millicode symbol but not an arbitrary external
7453 symbol when generating SOM output. */
7454 xoperands[1] = gen_label_rtx ();
7455 targetm.asm_out.internal_label (asm_out_file, "L",
7456 CODE_LABEL_NUMBER (xoperands[1]));
7457 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7458 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7462 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7463 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7467 /* Jump to our target address in %r1. */
7468 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7472 if (seq_length == 0)
7473 output_asm_insn ("nop", xoperands);
7475 /* We are done if there isn't a jump in the delay slot. */
7476 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7479 /* This call has an unconditional jump in its delay slot. */
7480 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7482 /* See if the return address can be adjusted. Use the containing
7483 sequence insn's address. */
7484 if (INSN_ADDRESSES_SET_P ())
7486 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7487 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7488 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7490 if (VAL_14_BITS_P (distance))
7492 xoperands[1] = gen_label_rtx ();
7493 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7494 targetm.asm_out.internal_label (asm_out_file, "L",
7495 CODE_LABEL_NUMBER (xoperands[1]));
7498 /* ??? This branch may not reach its target. */
7499 output_asm_insn ("nop\n\tb,n %0", xoperands);
7502 /* ??? This branch may not reach its target. */
7503 output_asm_insn ("nop\n\tb,n %0", xoperands);
7505 /* Delete the jump. */
7506 SET_INSN_DELETED (NEXT_INSN (insn));
7511 /* Return the attribute length of the call instruction INSN. The SIBCALL
7512 flag indicates whether INSN is a regular call or a sibling call. The
7513 length returned must be longer than the code actually generated by
7514 output_call. Since branch shortening is done before delay branch
7515 sequencing, there is no way to determine whether or not the delay
7516 slot will be filled during branch shortening. Even when the delay
7517 slot is filled, we may have to add a nop if the delay slot contains
7518 a branch that can't reach its target. Thus, we always have to include
7519 the delay slot in the length estimate. This used to be done in
7520 pa_adjust_insn_length but we do it here now as some sequences always
7521 fill the delay slot and we can save four bytes in the estimate for
7525 attr_length_call (rtx insn, int sibcall)
7528 rtx call, call_dest;
7531 rtx pat = PATTERN (insn);
7532 unsigned long distance = -1;
7534 gcc_assert (GET_CODE (insn) == CALL_INSN);
7536 if (INSN_ADDRESSES_SET_P ())
7538 unsigned long total;
7540 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7541 distance = (total + insn_current_reference_address (insn));
7542 if (distance < total)
7546 gcc_assert (GET_CODE (pat) == PARALLEL);
7548 /* Get the call rtx. */
7549 call = XVECEXP (pat, 0, 0);
7550 if (GET_CODE (call) == SET)
7551 call = SET_SRC (call);
7553 gcc_assert (GET_CODE (call) == CALL);
7555 /* Determine if this is a local call. */
7556 call_dest = XEXP (XEXP (call, 0), 0);
7557 call_decl = SYMBOL_REF_DECL (call_dest);
7558 local_call = call_decl && targetm.binds_local_p (call_decl);
7560 /* pc-relative branch. */
7561 if (!TARGET_LONG_CALLS
7562 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7563 || distance < 240000))
7566 /* 64-bit plabel sequence. */
7567 else if (TARGET_64BIT && !local_call)
7568 length += sibcall ? 28 : 24;
7570 /* non-pic long absolute branch sequence. */
7571 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7574 /* long pc-relative branch sequence. */
7575 else if (TARGET_LONG_PIC_SDIFF_CALL
7576 || (TARGET_GAS && !TARGET_SOM
7577 && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7581 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7585 /* 32-bit plabel sequence. */
7591 length += length_fp_args (insn);
7601 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7609 /* INSN is a function call. It may have an unconditional jump
7612 CALL_DEST is the routine we are calling. */
7615 output_call (rtx insn, rtx call_dest, int sibcall)
7617 int delay_insn_deleted = 0;
7618 int delay_slot_filled = 0;
7619 int seq_length = dbr_sequence_length ();
7620 tree call_decl = SYMBOL_REF_DECL (call_dest);
7621 int local_call = call_decl && targetm.binds_local_p (call_decl);
7624 xoperands[0] = call_dest;
7626 /* Handle the common case where we're sure that the branch will reach
7627 the beginning of the "$CODE$" subspace. This is the beginning of
7628 the current function if we are in a named section. */
7629 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7631 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7632 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7636 if (TARGET_64BIT && !local_call)
7638 /* ??? As far as I can tell, the HP linker doesn't support the
7639 long pc-relative sequence described in the 64-bit runtime
7640 architecture. So, we use a slightly longer indirect call. */
7641 xoperands[0] = get_deferred_plabel (call_dest);
7642 xoperands[1] = gen_label_rtx ();
7644 /* If this isn't a sibcall, we put the load of %r27 into the
7645 delay slot. We can't do this in a sibcall as we don't
7646 have a second call-clobbered scratch register available. */
7648 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7651 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7654 /* Now delete the delay insn. */
7655 SET_INSN_DELETED (NEXT_INSN (insn));
7656 delay_insn_deleted = 1;
7659 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7660 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7661 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7665 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7666 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7667 output_asm_insn ("bve (%%r1)", xoperands);
7671 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7672 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7673 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7674 delay_slot_filled = 1;
7679 int indirect_call = 0;
7681 /* Emit a long call. There are several different sequences
7682 of increasing length and complexity. In most cases,
7683 they don't allow an instruction in the delay slot. */
7684 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7685 && !TARGET_LONG_PIC_SDIFF_CALL
7686 && !(TARGET_GAS && !TARGET_SOM
7687 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7692 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7696 || ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)))
7698 /* A non-jump insn in the delay slot. By definition we can
7699 emit this insn before the call (and in fact before argument
7701 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7704 /* Now delete the delay insn. */
7705 SET_INSN_DELETED (NEXT_INSN (insn));
7706 delay_insn_deleted = 1;
7709 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7711 /* This is the best sequence for making long calls in
7712 non-pic code. Unfortunately, GNU ld doesn't provide
7713 the stub needed for external calls, and GAS's support
7714 for this with the SOM linker is buggy. It is safe
7715 to use this for local calls. */
7716 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7718 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7722 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7725 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7727 output_asm_insn ("copy %%r31,%%r2", xoperands);
7728 delay_slot_filled = 1;
7733 if (TARGET_LONG_PIC_SDIFF_CALL)
7735 /* The HP assembler and linker can handle relocations
7736 for the difference of two symbols. The HP assembler
7737 recognizes the sequence as a pc-relative call and
7738 the linker provides stubs when needed. */
7739 xoperands[1] = gen_label_rtx ();
7740 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7741 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7742 targetm.asm_out.internal_label (asm_out_file, "L",
7743 CODE_LABEL_NUMBER (xoperands[1]));
7744 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7746 else if (TARGET_GAS && !TARGET_SOM
7747 && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7749 /* GAS currently can't generate the relocations that
7750 are needed for the SOM linker under HP-UX using this
7751 sequence. The GNU linker doesn't generate the stubs
7752 that are needed for external calls on TARGET_ELF32
7753 with this sequence. For now, we have to use a
7754 longer plabel sequence when using GAS. */
7755 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7756 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7758 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7763 /* Emit a long plabel-based call sequence. This is
7764 essentially an inline implementation of $$dyncall.
7765 We don't actually try to call $$dyncall as this is
7766 as difficult as calling the function itself. */
7767 xoperands[0] = get_deferred_plabel (call_dest);
7768 xoperands[1] = gen_label_rtx ();
7770 /* Since the call is indirect, FP arguments in registers
7771 need to be copied to the general registers. Then, the
7772 argument relocation stub will copy them back. */
7774 copy_fp_args (insn);
7778 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7779 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7780 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7784 output_asm_insn ("addil LR'%0-$global$,%%r27",
7786 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7790 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7791 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7792 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7793 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7795 if (!sibcall && !TARGET_PA_20)
7797 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7798 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7799 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7801 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7808 output_asm_insn ("bve (%%r1)", xoperands);
7813 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7814 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7815 delay_slot_filled = 1;
7818 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7823 if (!TARGET_NO_SPACE_REGS && (!local_call || flag_pic))
7824 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7829 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7830 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7832 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7836 if (TARGET_NO_SPACE_REGS || (local_call && !flag_pic))
7837 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7839 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7842 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7844 output_asm_insn ("copy %%r31,%%r2", xoperands);
7845 delay_slot_filled = 1;
7852 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7853 output_asm_insn ("nop", xoperands);
7855 /* We are done if there isn't a jump in the delay slot. */
7857 || delay_insn_deleted
7858 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7861 /* A sibcall should never have a branch in the delay slot. */
7862 gcc_assert (!sibcall);
7864 /* This call has an unconditional jump in its delay slot. */
7865 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7867 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7869 /* See if the return address can be adjusted. Use the containing
7870 sequence insn's address. This would break the regular call/return@
7871 relationship assumed by the table based eh unwinder, so only do that
7872 if the call is not possibly throwing. */
7873 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7874 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7875 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7877 if (VAL_14_BITS_P (distance)
7878 && !(can_throw_internal (insn) || can_throw_external (insn)))
7880 xoperands[1] = gen_label_rtx ();
7881 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7882 targetm.asm_out.internal_label (asm_out_file, "L",
7883 CODE_LABEL_NUMBER (xoperands[1]));
7886 output_asm_insn ("nop\n\tb,n %0", xoperands);
7889 output_asm_insn ("b,n %0", xoperands);
7891 /* Delete the jump. */
7892 SET_INSN_DELETED (NEXT_INSN (insn));
7897 /* Return the attribute length of the indirect call instruction INSN.
7898 The length must match the code generated by output_indirect call.
7899 The returned length includes the delay slot. Currently, the delay
7900 slot of an indirect call sequence is not exposed and it is used by
7901 the sequence itself. */
7904 attr_length_indirect_call (rtx insn)
7906 unsigned long distance = -1;
7907 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7909 if (INSN_ADDRESSES_SET_P ())
7911 distance = (total + insn_current_reference_address (insn));
7912 if (distance < total)
7919 if (TARGET_FAST_INDIRECT_CALLS
7920 || (!TARGET_PORTABLE_RUNTIME
7921 && ((TARGET_PA_20 && !TARGET_SOM && distance < 7600000)
7922 || distance < 240000)))
7928 if (TARGET_PORTABLE_RUNTIME)
7931 /* Out of reach, can use ble. */
7936 output_indirect_call (rtx insn, rtx call_dest)
7942 xoperands[0] = call_dest;
7943 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7944 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7948 /* First the special case for kernels, level 0 systems, etc. */
7949 if (TARGET_FAST_INDIRECT_CALLS)
7950 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7952 /* Now the normal case -- we can reach $$dyncall directly or
7953 we're sure that we can get there via a long-branch stub.
7955 No need to check target flags as the length uniquely identifies
7956 the remaining cases. */
7957 if (attr_length_indirect_call (insn) == 8)
7959 /* The HP linker sometimes substitutes a BLE for BL/B,L calls to
7960 $$dyncall. Since BLE uses %r31 as the link register, the 22-bit
7961 variant of the B,L instruction can't be used on the SOM target. */
7962 if (TARGET_PA_20 && !TARGET_SOM)
7963 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7965 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7968 /* Long millicode call, but we are not generating PIC or portable runtime
7970 if (attr_length_indirect_call (insn) == 12)
7971 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7973 /* Long millicode call for portable runtime. */
7974 if (attr_length_indirect_call (insn) == 20)
7975 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7977 /* We need a long PIC call to $$dyncall. */
7978 xoperands[0] = NULL_RTX;
7979 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7980 if (TARGET_SOM || !TARGET_GAS)
7982 xoperands[0] = gen_label_rtx ();
7983 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7984 targetm.asm_out.internal_label (asm_out_file, "L",
7985 CODE_LABEL_NUMBER (xoperands[0]));
7986 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7990 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7991 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7994 output_asm_insn ("blr %%r0,%%r2", xoperands);
7995 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7999 /* Return the total length of the save and restore instructions needed for
8000 the data linkage table pointer (i.e., the PIC register) across the call
8001 instruction INSN. No-return calls do not require a save and restore.
8002 In addition, we may be able to avoid the save and restore for calls
8003 within the same translation unit. */
8006 attr_length_save_restore_dltp (rtx insn)
8008 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
8014 /* In HPUX 8.0's shared library scheme, special relocations are needed
8015 for function labels if they might be passed to a function
8016 in a shared library (because shared libraries don't live in code
8017 space), and special magic is needed to construct their address. */
8020 hppa_encode_label (rtx sym)
8022 const char *str = XSTR (sym, 0);
8023 int len = strlen (str) + 1;
8026 p = newstr = XALLOCAVEC (char, len + 1);
8030 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
8034 pa_encode_section_info (tree decl, rtx rtl, int first)
8036 int old_referenced = 0;
8038 if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
8040 = SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
8042 default_encode_section_info (decl, rtl, first);
8044 if (first && TEXT_SPACE_P (decl))
8046 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
8047 if (TREE_CODE (decl) == FUNCTION_DECL)
8048 hppa_encode_label (XEXP (rtl, 0));
8050 else if (old_referenced)
8051 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= old_referenced;
8054 /* This is sort of inverse to pa_encode_section_info. */
8057 pa_strip_name_encoding (const char *str)
8059 str += (*str == '@');
8060 str += (*str == '*');
8065 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8067 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
8070 /* Returns 1 if OP is a function label involved in a simple addition
8071 with a constant. Used to keep certain patterns from matching
8072 during instruction combination. */
8074 is_function_label_plus_const (rtx op)
8076 /* Strip off any CONST. */
8077 if (GET_CODE (op) == CONST)
8080 return (GET_CODE (op) == PLUS
8081 && function_label_operand (XEXP (op, 0), Pmode)
8082 && GET_CODE (XEXP (op, 1)) == CONST_INT);
8085 /* Output assembly code for a thunk to FUNCTION. */
8088 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
8089 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
8092 static unsigned int current_thunk_number;
8093 int val_14 = VAL_14_BITS_P (delta);
8094 unsigned int old_last_address = last_address, nbytes = 0;
8098 xoperands[0] = XEXP (DECL_RTL (function), 0);
8099 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
8100 xoperands[2] = GEN_INT (delta);
8102 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
8103 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
8105 /* Output the thunk. We know that the function is in the same
8106 translation unit (i.e., the same space) as the thunk, and that
8107 thunks are output after their method. Thus, we don't need an
8108 external branch to reach the function. With SOM and GAS,
8109 functions and thunks are effectively in different sections.
8110 Thus, we can always use a IA-relative branch and the linker
8111 will add a long branch stub if necessary.
8113 However, we have to be careful when generating PIC code on the
8114 SOM port to ensure that the sequence does not transfer to an
8115 import stub for the target function as this could clobber the
8116 return value saved at SP-24. This would also apply to the
8117 32-bit linux port if the multi-space model is implemented. */
8118 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8119 && !(flag_pic && TREE_PUBLIC (function))
8120 && (TARGET_GAS || last_address < 262132))
8121 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
8122 && ((targetm.have_named_sections
8123 && DECL_SECTION_NAME (thunk_fndecl) != NULL
8124 /* The GNU 64-bit linker has rather poor stub management.
8125 So, we use a long branch from thunks that aren't in
8126 the same section as the target function. */
8128 && (DECL_SECTION_NAME (thunk_fndecl)
8129 != DECL_SECTION_NAME (function)))
8130 || ((DECL_SECTION_NAME (thunk_fndecl)
8131 == DECL_SECTION_NAME (function))
8132 && last_address < 262132)))
8133 || (targetm.have_named_sections
8134 && DECL_SECTION_NAME (thunk_fndecl) == NULL
8135 && DECL_SECTION_NAME (function) == NULL
8136 && last_address < 262132)
8137 || (!targetm.have_named_sections && last_address < 262132))))
8140 output_asm_insn ("addil L'%2,%%r26", xoperands);
8142 output_asm_insn ("b %0", xoperands);
8146 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8151 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8155 else if (TARGET_64BIT)
8157 /* We only have one call-clobbered scratch register, so we can't
8158 make use of the delay slot if delta doesn't fit in 14 bits. */
8161 output_asm_insn ("addil L'%2,%%r26", xoperands);
8162 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8165 output_asm_insn ("b,l .+8,%%r1", xoperands);
8169 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8170 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
8174 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
8175 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
8180 output_asm_insn ("bv %%r0(%%r1)", xoperands);
8181 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8186 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
8190 else if (TARGET_PORTABLE_RUNTIME)
8192 output_asm_insn ("ldil L'%0,%%r1", xoperands);
8193 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
8196 output_asm_insn ("addil L'%2,%%r26", xoperands);
8198 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8202 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8207 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8211 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8213 /* The function is accessible from outside this module. The only
8214 way to avoid an import stub between the thunk and function is to
8215 call the function directly with an indirect sequence similar to
8216 that used by $$dyncall. This is possible because $$dyncall acts
8217 as the import stub in an indirect call. */
8218 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
8219 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
8220 output_asm_insn ("addil LT'%3,%%r19", xoperands);
8221 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
8222 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8223 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
8224 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
8225 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
8226 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
8230 output_asm_insn ("addil L'%2,%%r26", xoperands);
8236 output_asm_insn ("bve (%%r22)", xoperands);
8239 else if (TARGET_NO_SPACE_REGS)
8241 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
8246 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
8247 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
8248 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
8253 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8255 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8259 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
8261 if (TARGET_SOM || !TARGET_GAS)
8263 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
8264 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
8268 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
8269 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
8273 output_asm_insn ("addil L'%2,%%r26", xoperands);
8275 output_asm_insn ("bv %%r0(%%r22)", xoperands);
8279 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8284 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8291 output_asm_insn ("addil L'%2,%%r26", xoperands);
8293 output_asm_insn ("ldil L'%0,%%r22", xoperands);
8294 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
8298 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
8303 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
8308 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8310 if (TARGET_SOM && TARGET_GAS)
8312 /* We done with this subspace except possibly for some additional
8313 debug information. Forget that we are in this subspace to ensure
8314 that the next function is output in its own subspace. */
8316 cfun->machine->in_nsubspa = 2;
8319 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8321 switch_to_section (data_section);
8322 output_asm_insn (".align 4", xoperands);
8323 ASM_OUTPUT_LABEL (file, label);
8324 output_asm_insn (".word P'%0", xoperands);
8327 current_thunk_number++;
8328 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8329 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8330 last_address += nbytes;
8331 if (old_last_address > last_address)
8332 last_address = UINT_MAX;
8333 update_total_code_bytes (nbytes);
8336 /* Only direct calls to static functions are allowed to be sibling (tail)
8339 This restriction is necessary because some linker generated stubs will
8340 store return pointers into rp' in some cases which might clobber a
8341 live value already in rp'.
8343 In a sibcall the current function and the target function share stack
8344 space. Thus if the path to the current function and the path to the
8345 target function save a value in rp', they save the value into the
8346 same stack slot, which has undesirable consequences.
8348 Because of the deferred binding nature of shared libraries any function
8349 with external scope could be in a different load module and thus require
8350 rp' to be saved when calling that function. So sibcall optimizations
8351 can only be safe for static function.
8353 Note that GCC never needs return value relocations, so we don't have to
8354 worry about static calls with return value relocations (which require
8357 It is safe to perform a sibcall optimization when the target function
8358 will never return. */
8360 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8362 if (TARGET_PORTABLE_RUNTIME)
8365 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8366 single subspace mode and the call is not indirect. As far as I know,
8367 there is no operating system support for the multiple subspace mode.
8368 It might be possible to support indirect calls if we didn't use
8369 $$dyncall (see the indirect sequence generated in output_call). */
8371 return (decl != NULL_TREE);
8373 /* Sibcalls are not ok because the arg pointer register is not a fixed
8374 register. This prevents the sibcall optimization from occurring. In
8375 addition, there are problems with stub placement using GNU ld. This
8376 is because a normal sibcall branch uses a 17-bit relocation while
8377 a regular call branch uses a 22-bit relocation. As a result, more
8378 care needs to be taken in the placement of long-branch stubs. */
8382 /* Sibcalls are only ok within a translation unit. */
8383 return (decl && !TREE_PUBLIC (decl));
8386 /* ??? Addition is not commutative on the PA due to the weird implicit
8387 space register selection rules for memory addresses. Therefore, we
8388 don't consider a + b == b + a, as this might be inside a MEM. */
8390 pa_commutative_p (const_rtx x, int outer_code)
8392 return (COMMUTATIVE_P (x)
8393 && (TARGET_NO_SPACE_REGS
8394 || (outer_code != UNKNOWN && outer_code != MEM)
8395 || GET_CODE (x) != PLUS));
8398 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8399 use in fmpyadd instructions. */
8401 fmpyaddoperands (rtx *operands)
8403 enum machine_mode mode = GET_MODE (operands[0]);
8405 /* Must be a floating point mode. */
8406 if (mode != SFmode && mode != DFmode)
8409 /* All modes must be the same. */
8410 if (! (mode == GET_MODE (operands[1])
8411 && mode == GET_MODE (operands[2])
8412 && mode == GET_MODE (operands[3])
8413 && mode == GET_MODE (operands[4])
8414 && mode == GET_MODE (operands[5])))
8417 /* All operands must be registers. */
8418 if (! (GET_CODE (operands[1]) == REG
8419 && GET_CODE (operands[2]) == REG
8420 && GET_CODE (operands[3]) == REG
8421 && GET_CODE (operands[4]) == REG
8422 && GET_CODE (operands[5]) == REG))
8425 /* Only 2 real operands to the addition. One of the input operands must
8426 be the same as the output operand. */
8427 if (! rtx_equal_p (operands[3], operands[4])
8428 && ! rtx_equal_p (operands[3], operands[5]))
8431 /* Inout operand of add cannot conflict with any operands from multiply. */
8432 if (rtx_equal_p (operands[3], operands[0])
8433 || rtx_equal_p (operands[3], operands[1])
8434 || rtx_equal_p (operands[3], operands[2]))
8437 /* multiply cannot feed into addition operands. */
8438 if (rtx_equal_p (operands[4], operands[0])
8439 || rtx_equal_p (operands[5], operands[0]))
8442 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8444 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8445 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8446 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8447 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8448 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8449 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8452 /* Passed. Operands are suitable for fmpyadd. */
8456 #if !defined(USE_COLLECT2)
8458 pa_asm_out_constructor (rtx symbol, int priority)
8460 if (!function_label_operand (symbol, VOIDmode))
8461 hppa_encode_label (symbol);
8463 #ifdef CTORS_SECTION_ASM_OP
8464 default_ctor_section_asm_out_constructor (symbol, priority);
8466 # ifdef TARGET_ASM_NAMED_SECTION
8467 default_named_section_asm_out_constructor (symbol, priority);
8469 default_stabs_asm_out_constructor (symbol, priority);
8475 pa_asm_out_destructor (rtx symbol, int priority)
8477 if (!function_label_operand (symbol, VOIDmode))
8478 hppa_encode_label (symbol);
8480 #ifdef DTORS_SECTION_ASM_OP
8481 default_dtor_section_asm_out_destructor (symbol, priority);
8483 # ifdef TARGET_ASM_NAMED_SECTION
8484 default_named_section_asm_out_destructor (symbol, priority);
8486 default_stabs_asm_out_destructor (symbol, priority);
8492 /* This function places uninitialized global data in the bss section.
8493 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8494 function on the SOM port to prevent uninitialized global data from
8495 being placed in the data section. */
8498 pa_asm_output_aligned_bss (FILE *stream,
8500 unsigned HOST_WIDE_INT size,
8503 switch_to_section (bss_section);
8504 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8506 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8507 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8510 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8511 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8514 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8515 ASM_OUTPUT_LABEL (stream, name);
8516 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8519 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8520 that doesn't allow the alignment of global common storage to be directly
8521 specified. The SOM linker aligns common storage based on the rounded
8522 value of the NUM_BYTES parameter in the .comm directive. It's not
8523 possible to use the .align directive as it doesn't affect the alignment
8524 of the label associated with a .comm directive. */
8527 pa_asm_output_aligned_common (FILE *stream,
8529 unsigned HOST_WIDE_INT size,
8532 unsigned int max_common_align;
8534 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8535 if (align > max_common_align)
8537 warning (0, "alignment (%u) for %s exceeds maximum alignment "
8538 "for global common data. Using %u",
8539 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8540 align = max_common_align;
8543 switch_to_section (bss_section);
8545 assemble_name (stream, name);
8546 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8547 MAX (size, align / BITS_PER_UNIT));
8550 /* We can't use .comm for local common storage as the SOM linker effectively
8551 treats the symbol as universal and uses the same storage for local symbols
8552 with the same name in different object files. The .block directive
8553 reserves an uninitialized block of storage. However, it's not common
8554 storage. Fortunately, GCC never requests common storage with the same
8555 name in any given translation unit. */
8558 pa_asm_output_aligned_local (FILE *stream,
8560 unsigned HOST_WIDE_INT size,
8563 switch_to_section (bss_section);
8564 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8567 fprintf (stream, "%s", LOCAL_ASM_OP);
8568 assemble_name (stream, name);
8569 fprintf (stream, "\n");
8572 ASM_OUTPUT_LABEL (stream, name);
8573 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8576 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8577 use in fmpysub instructions. */
8579 fmpysuboperands (rtx *operands)
8581 enum machine_mode mode = GET_MODE (operands[0]);
8583 /* Must be a floating point mode. */
8584 if (mode != SFmode && mode != DFmode)
8587 /* All modes must be the same. */
8588 if (! (mode == GET_MODE (operands[1])
8589 && mode == GET_MODE (operands[2])
8590 && mode == GET_MODE (operands[3])
8591 && mode == GET_MODE (operands[4])
8592 && mode == GET_MODE (operands[5])))
8595 /* All operands must be registers. */
8596 if (! (GET_CODE (operands[1]) == REG
8597 && GET_CODE (operands[2]) == REG
8598 && GET_CODE (operands[3]) == REG
8599 && GET_CODE (operands[4]) == REG
8600 && GET_CODE (operands[5]) == REG))
8603 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8604 operation, so operands[4] must be the same as operand[3]. */
8605 if (! rtx_equal_p (operands[3], operands[4]))
8608 /* multiply cannot feed into subtraction. */
8609 if (rtx_equal_p (operands[5], operands[0]))
8612 /* Inout operand of sub cannot conflict with any operands from multiply. */
8613 if (rtx_equal_p (operands[3], operands[0])
8614 || rtx_equal_p (operands[3], operands[1])
8615 || rtx_equal_p (operands[3], operands[2]))
8618 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8620 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8621 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8622 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8623 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8624 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8625 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8628 /* Passed. Operands are suitable for fmpysub. */
8632 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8633 constants for shadd instructions. */
8635 shadd_constant_p (int val)
8637 if (val == 2 || val == 4 || val == 8)
8643 /* Return 1 if OP is valid as a base or index register in a
8647 borx_reg_operand (rtx op, enum machine_mode mode)
8649 if (GET_CODE (op) != REG)
8652 /* We must reject virtual registers as the only expressions that
8653 can be instantiated are REG and REG+CONST. */
8654 if (op == virtual_incoming_args_rtx
8655 || op == virtual_stack_vars_rtx
8656 || op == virtual_stack_dynamic_rtx
8657 || op == virtual_outgoing_args_rtx
8658 || op == virtual_cfa_rtx)
8661 /* While it's always safe to index off the frame pointer, it's not
8662 profitable to do so when the frame pointer is being eliminated. */
8663 if (!reload_completed
8664 && flag_omit_frame_pointer
8665 && !cfun->calls_alloca
8666 && op == frame_pointer_rtx)
8669 return register_operand (op, mode);
8672 /* Return 1 if this operand is anything other than a hard register. */
8675 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8677 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8680 /* Return TRUE if INSN branches forward. */
8683 forward_branch_p (rtx insn)
8685 rtx lab = JUMP_LABEL (insn);
8687 /* The INSN must have a jump label. */
8688 gcc_assert (lab != NULL_RTX);
8690 if (INSN_ADDRESSES_SET_P ())
8691 return INSN_ADDRESSES (INSN_UID (lab)) > INSN_ADDRESSES (INSN_UID (insn));
8698 insn = NEXT_INSN (insn);
8704 /* Return 1 if OP is an equality comparison, else return 0. */
8706 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8708 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8711 /* Return 1 if INSN is in the delay slot of a call instruction. */
8713 jump_in_call_delay (rtx insn)
8716 if (GET_CODE (insn) != JUMP_INSN)
8719 if (PREV_INSN (insn)
8720 && PREV_INSN (PREV_INSN (insn))
8721 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8723 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8725 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8726 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8733 /* Output an unconditional move and branch insn. */
8736 output_parallel_movb (rtx *operands, rtx insn)
8738 int length = get_attr_length (insn);
8740 /* These are the cases in which we win. */
8742 return "mov%I1b,tr %1,%0,%2";
8744 /* None of the following cases win, but they don't lose either. */
8747 if (dbr_sequence_length () == 0)
8749 /* Nothing in the delay slot, fake it by putting the combined
8750 insn (the copy or add) in the delay slot of a bl. */
8751 if (GET_CODE (operands[1]) == CONST_INT)
8752 return "b %2\n\tldi %1,%0";
8754 return "b %2\n\tcopy %1,%0";
8758 /* Something in the delay slot, but we've got a long branch. */
8759 if (GET_CODE (operands[1]) == CONST_INT)
8760 return "ldi %1,%0\n\tb %2";
8762 return "copy %1,%0\n\tb %2";
8766 if (GET_CODE (operands[1]) == CONST_INT)
8767 output_asm_insn ("ldi %1,%0", operands);
8769 output_asm_insn ("copy %1,%0", operands);
8770 return output_lbranch (operands[2], insn, 1);
8773 /* Output an unconditional add and branch insn. */
8776 output_parallel_addb (rtx *operands, rtx insn)
8778 int length = get_attr_length (insn);
8780 /* To make life easy we want operand0 to be the shared input/output
8781 operand and operand1 to be the readonly operand. */
8782 if (operands[0] == operands[1])
8783 operands[1] = operands[2];
8785 /* These are the cases in which we win. */
8787 return "add%I1b,tr %1,%0,%3";
8789 /* None of the following cases win, but they don't lose either. */
8792 if (dbr_sequence_length () == 0)
8793 /* Nothing in the delay slot, fake it by putting the combined
8794 insn (the copy or add) in the delay slot of a bl. */
8795 return "b %3\n\tadd%I1 %1,%0,%0";
8797 /* Something in the delay slot, but we've got a long branch. */
8798 return "add%I1 %1,%0,%0\n\tb %3";
8801 output_asm_insn ("add%I1 %1,%0,%0", operands);
8802 return output_lbranch (operands[3], insn, 1);
8805 /* Return nonzero if INSN (a jump insn) immediately follows a call
8806 to a named function. This is used to avoid filling the delay slot
8807 of the jump since it can usually be eliminated by modifying RP in
8808 the delay slot of the call. */
8811 following_call (rtx insn)
8813 if (! TARGET_JUMP_IN_DELAY)
8816 /* Find the previous real insn, skipping NOTEs. */
8817 insn = PREV_INSN (insn);
8818 while (insn && GET_CODE (insn) == NOTE)
8819 insn = PREV_INSN (insn);
8821 /* Check for CALL_INSNs and millicode calls. */
8823 && ((GET_CODE (insn) == CALL_INSN
8824 && get_attr_type (insn) != TYPE_DYNCALL)
8825 || (GET_CODE (insn) == INSN
8826 && GET_CODE (PATTERN (insn)) != SEQUENCE
8827 && GET_CODE (PATTERN (insn)) != USE
8828 && GET_CODE (PATTERN (insn)) != CLOBBER
8829 && get_attr_type (insn) == TYPE_MILLI)))
8835 /* We use this hook to perform a PA specific optimization which is difficult
8836 to do in earlier passes.
8838 We want the delay slots of branches within jump tables to be filled.
8839 None of the compiler passes at the moment even has the notion that a
8840 PA jump table doesn't contain addresses, but instead contains actual
8843 Because we actually jump into the table, the addresses of each entry
8844 must stay constant in relation to the beginning of the table (which
8845 itself must stay constant relative to the instruction to jump into
8846 it). I don't believe we can guarantee earlier passes of the compiler
8847 will adhere to those rules.
8849 So, late in the compilation process we find all the jump tables, and
8850 expand them into real code -- e.g. each entry in the jump table vector
8851 will get an appropriate label followed by a jump to the final target.
8853 Reorg and the final jump pass can then optimize these branches and
8854 fill their delay slots. We end up with smaller, more efficient code.
8856 The jump instructions within the table are special; we must be able
8857 to identify them during assembly output (if the jumps don't get filled
8858 we need to emit a nop rather than nullifying the delay slot)). We
8859 identify jumps in switch tables by using insns with the attribute
8860 type TYPE_BTABLE_BRANCH.
8862 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8863 insns. This serves two purposes, first it prevents jump.c from
8864 noticing that the last N entries in the table jump to the instruction
8865 immediately after the table and deleting the jumps. Second, those
8866 insns mark where we should emit .begin_brtab and .end_brtab directives
8867 when using GAS (allows for better link time optimizations). */
8874 remove_useless_addtr_insns (1);
8876 if (pa_cpu < PROCESSOR_8000)
8877 pa_combine_instructions ();
8880 /* This is fairly cheap, so always run it if optimizing. */
8881 if (optimize > 0 && !TARGET_BIG_SWITCH)
8883 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8884 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8886 rtx pattern, tmp, location, label;
8887 unsigned int length, i;
8889 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8890 if (GET_CODE (insn) != JUMP_INSN
8891 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8892 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8895 /* Emit marker for the beginning of the branch table. */
8896 emit_insn_before (gen_begin_brtab (), insn);
8898 pattern = PATTERN (insn);
8899 location = PREV_INSN (insn);
8900 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8902 for (i = 0; i < length; i++)
8904 /* Emit a label before each jump to keep jump.c from
8905 removing this code. */
8906 tmp = gen_label_rtx ();
8907 LABEL_NUSES (tmp) = 1;
8908 emit_label_after (tmp, location);
8909 location = NEXT_INSN (location);
8911 if (GET_CODE (pattern) == ADDR_VEC)
8912 label = XEXP (XVECEXP (pattern, 0, i), 0);
8914 label = XEXP (XVECEXP (pattern, 1, i), 0);
8916 tmp = gen_short_jump (label);
8918 /* Emit the jump itself. */
8919 tmp = emit_jump_insn_after (tmp, location);
8920 JUMP_LABEL (tmp) = label;
8921 LABEL_NUSES (label)++;
8922 location = NEXT_INSN (location);
8924 /* Emit a BARRIER after the jump. */
8925 emit_barrier_after (location);
8926 location = NEXT_INSN (location);
8929 /* Emit marker for the end of the branch table. */
8930 emit_insn_before (gen_end_brtab (), location);
8931 location = NEXT_INSN (location);
8932 emit_barrier_after (location);
8934 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8940 /* Still need brtab marker insns. FIXME: the presence of these
8941 markers disables output of the branch table to readonly memory,
8942 and any alignment directives that might be needed. Possibly,
8943 the begin_brtab insn should be output before the label for the
8944 table. This doesn't matter at the moment since the tables are
8945 always output in the text section. */
8946 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8948 /* Find an ADDR_VEC insn. */
8949 if (GET_CODE (insn) != JUMP_INSN
8950 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8951 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8954 /* Now generate markers for the beginning and end of the
8956 emit_insn_before (gen_begin_brtab (), insn);
8957 emit_insn_after (gen_end_brtab (), insn);
8962 /* The PA has a number of odd instructions which can perform multiple
8963 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8964 it may be profitable to combine two instructions into one instruction
8965 with two outputs. It's not profitable PA2.0 machines because the
8966 two outputs would take two slots in the reorder buffers.
8968 This routine finds instructions which can be combined and combines
8969 them. We only support some of the potential combinations, and we
8970 only try common ways to find suitable instructions.
8972 * addb can add two registers or a register and a small integer
8973 and jump to a nearby (+-8k) location. Normally the jump to the
8974 nearby location is conditional on the result of the add, but by
8975 using the "true" condition we can make the jump unconditional.
8976 Thus addb can perform two independent operations in one insn.
8978 * movb is similar to addb in that it can perform a reg->reg
8979 or small immediate->reg copy and jump to a nearby (+-8k location).
8981 * fmpyadd and fmpysub can perform a FP multiply and either an
8982 FP add or FP sub if the operands of the multiply and add/sub are
8983 independent (there are other minor restrictions). Note both
8984 the fmpy and fadd/fsub can in theory move to better spots according
8985 to data dependencies, but for now we require the fmpy stay at a
8988 * Many of the memory operations can perform pre & post updates
8989 of index registers. GCC's pre/post increment/decrement addressing
8990 is far too simple to take advantage of all the possibilities. This
8991 pass may not be suitable since those insns may not be independent.
8993 * comclr can compare two ints or an int and a register, nullify
8994 the following instruction and zero some other register. This
8995 is more difficult to use as it's harder to find an insn which
8996 will generate a comclr than finding something like an unconditional
8997 branch. (conditional moves & long branches create comclr insns).
8999 * Most arithmetic operations can conditionally skip the next
9000 instruction. They can be viewed as "perform this operation
9001 and conditionally jump to this nearby location" (where nearby
9002 is an insns away). These are difficult to use due to the
9003 branch length restrictions. */
9006 pa_combine_instructions (void)
9008 rtx anchor, new_rtx;
9010 /* This can get expensive since the basic algorithm is on the
9011 order of O(n^2) (or worse). Only do it for -O2 or higher
9012 levels of optimization. */
9016 /* Walk down the list of insns looking for "anchor" insns which
9017 may be combined with "floating" insns. As the name implies,
9018 "anchor" instructions don't move, while "floating" insns may
9020 new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
9021 new_rtx = make_insn_raw (new_rtx);
9023 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
9025 enum attr_pa_combine_type anchor_attr;
9026 enum attr_pa_combine_type floater_attr;
9028 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
9029 Also ignore any special USE insns. */
9030 if ((GET_CODE (anchor) != INSN
9031 && GET_CODE (anchor) != JUMP_INSN
9032 && GET_CODE (anchor) != CALL_INSN)
9033 || GET_CODE (PATTERN (anchor)) == USE
9034 || GET_CODE (PATTERN (anchor)) == CLOBBER
9035 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
9036 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
9039 anchor_attr = get_attr_pa_combine_type (anchor);
9040 /* See if anchor is an insn suitable for combination. */
9041 if (anchor_attr == PA_COMBINE_TYPE_FMPY
9042 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
9043 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9044 && ! forward_branch_p (anchor)))
9048 for (floater = PREV_INSN (anchor);
9050 floater = PREV_INSN (floater))
9052 if (GET_CODE (floater) == NOTE
9053 || (GET_CODE (floater) == INSN
9054 && (GET_CODE (PATTERN (floater)) == USE
9055 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9058 /* Anything except a regular INSN will stop our search. */
9059 if (GET_CODE (floater) != INSN
9060 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9061 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9067 /* See if FLOATER is suitable for combination with the
9069 floater_attr = get_attr_pa_combine_type (floater);
9070 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9071 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9072 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9073 && floater_attr == PA_COMBINE_TYPE_FMPY))
9075 /* If ANCHOR and FLOATER can be combined, then we're
9076 done with this pass. */
9077 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9078 SET_DEST (PATTERN (floater)),
9079 XEXP (SET_SRC (PATTERN (floater)), 0),
9080 XEXP (SET_SRC (PATTERN (floater)), 1)))
9084 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
9085 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
9087 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
9089 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9090 SET_DEST (PATTERN (floater)),
9091 XEXP (SET_SRC (PATTERN (floater)), 0),
9092 XEXP (SET_SRC (PATTERN (floater)), 1)))
9097 if (pa_can_combine_p (new_rtx, anchor, floater, 0,
9098 SET_DEST (PATTERN (floater)),
9099 SET_SRC (PATTERN (floater)),
9100 SET_SRC (PATTERN (floater))))
9106 /* If we didn't find anything on the backwards scan try forwards. */
9108 && (anchor_attr == PA_COMBINE_TYPE_FMPY
9109 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
9111 for (floater = anchor; floater; floater = NEXT_INSN (floater))
9113 if (GET_CODE (floater) == NOTE
9114 || (GET_CODE (floater) == INSN
9115 && (GET_CODE (PATTERN (floater)) == USE
9116 || GET_CODE (PATTERN (floater)) == CLOBBER)))
9120 /* Anything except a regular INSN will stop our search. */
9121 if (GET_CODE (floater) != INSN
9122 || GET_CODE (PATTERN (floater)) == ADDR_VEC
9123 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
9129 /* See if FLOATER is suitable for combination with the
9131 floater_attr = get_attr_pa_combine_type (floater);
9132 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
9133 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
9134 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9135 && floater_attr == PA_COMBINE_TYPE_FMPY))
9137 /* If ANCHOR and FLOATER can be combined, then we're
9138 done with this pass. */
9139 if (pa_can_combine_p (new_rtx, anchor, floater, 1,
9140 SET_DEST (PATTERN (floater)),
9141 XEXP (SET_SRC (PATTERN (floater)),
9143 XEXP (SET_SRC (PATTERN (floater)),
9150 /* FLOATER will be nonzero if we found a suitable floating
9151 insn for combination with ANCHOR. */
9153 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
9154 || anchor_attr == PA_COMBINE_TYPE_FMPY))
9156 /* Emit the new instruction and delete the old anchor. */
9157 emit_insn_before (gen_rtx_PARALLEL
9159 gen_rtvec (2, PATTERN (anchor),
9160 PATTERN (floater))),
9163 SET_INSN_DELETED (anchor);
9165 /* Emit a special USE insn for FLOATER, then delete
9166 the floating insn. */
9167 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9168 delete_insn (floater);
9173 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
9176 /* Emit the new_jump instruction and delete the old anchor. */
9178 = emit_jump_insn_before (gen_rtx_PARALLEL
9180 gen_rtvec (2, PATTERN (anchor),
9181 PATTERN (floater))),
9184 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
9185 SET_INSN_DELETED (anchor);
9187 /* Emit a special USE insn for FLOATER, then delete
9188 the floating insn. */
9189 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
9190 delete_insn (floater);
9198 pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
9201 int insn_code_number;
9204 /* Create a PARALLEL with the patterns of ANCHOR and
9205 FLOATER, try to recognize it, then test constraints
9206 for the resulting pattern.
9208 If the pattern doesn't match or the constraints
9209 aren't met keep searching for a suitable floater
9211 XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
9212 XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
9213 INSN_CODE (new_rtx) = -1;
9214 insn_code_number = recog_memoized (new_rtx);
9215 if (insn_code_number < 0
9216 || (extract_insn (new_rtx), ! constrain_operands (1)))
9230 /* There's up to three operands to consider. One
9231 output and two inputs.
9233 The output must not be used between FLOATER & ANCHOR
9234 exclusive. The inputs must not be set between
9235 FLOATER and ANCHOR exclusive. */
9237 if (reg_used_between_p (dest, start, end))
9240 if (reg_set_between_p (src1, start, end))
9243 if (reg_set_between_p (src2, start, end))
9246 /* If we get here, then everything is good. */
9250 /* Return nonzero if references for INSN are delayed.
9252 Millicode insns are actually function calls with some special
9253 constraints on arguments and register usage.
9255 Millicode calls always expect their arguments in the integer argument
9256 registers, and always return their result in %r29 (ret1). They
9257 are expected to clobber their arguments, %r1, %r29, and the return
9258 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9260 This function tells reorg that the references to arguments and
9261 millicode calls do not appear to happen until after the millicode call.
9262 This allows reorg to put insns which set the argument registers into the
9263 delay slot of the millicode call -- thus they act more like traditional
9266 Note we cannot consider side effects of the insn to be delayed because
9267 the branch and link insn will clobber the return pointer. If we happened
9268 to use the return pointer in the delay slot of the call, then we lose.
9270 get_attr_type will try to recognize the given insn, so make sure to
9271 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9274 insn_refs_are_delayed (rtx insn)
9276 return ((GET_CODE (insn) == INSN
9277 && GET_CODE (PATTERN (insn)) != SEQUENCE
9278 && GET_CODE (PATTERN (insn)) != USE
9279 && GET_CODE (PATTERN (insn)) != CLOBBER
9280 && get_attr_type (insn) == TYPE_MILLI));
9283 /* Promote the return value, but not the arguments. */
9285 static enum machine_mode
9286 pa_promote_function_mode (const_tree type ATTRIBUTE_UNUSED,
9287 enum machine_mode mode,
9288 int *punsignedp ATTRIBUTE_UNUSED,
9289 const_tree fntype ATTRIBUTE_UNUSED,
9292 if (for_return == 0)
9294 return promote_mode (type, mode, punsignedp);
9297 /* On the HP-PA the value is found in register(s) 28(-29), unless
9298 the mode is SF or DF. Then the value is returned in fr4 (32).
9300 This must perform the same promotions as PROMOTE_MODE, else promoting
9301 return values in TARGET_PROMOTE_FUNCTION_MODE will not work correctly.
9303 Small structures must be returned in a PARALLEL on PA64 in order
9304 to match the HP Compiler ABI. */
9307 pa_function_value (const_tree valtype,
9308 const_tree func ATTRIBUTE_UNUSED,
9309 bool outgoing ATTRIBUTE_UNUSED)
9311 enum machine_mode valmode;
9313 if (AGGREGATE_TYPE_P (valtype)
9314 || TREE_CODE (valtype) == COMPLEX_TYPE
9315 || TREE_CODE (valtype) == VECTOR_TYPE)
9319 /* Aggregates with a size less than or equal to 128 bits are
9320 returned in GR 28(-29). They are left justified. The pad
9321 bits are undefined. Larger aggregates are returned in
9325 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9327 for (i = 0; i < ub; i++)
9329 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9330 gen_rtx_REG (DImode, 28 + i),
9335 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9337 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
9339 /* Aggregates 5 to 8 bytes in size are returned in general
9340 registers r28-r29 in the same manner as other non
9341 floating-point objects. The data is right-justified and
9342 zero-extended to 64 bits. This is opposite to the normal
9343 justification used on big endian targets and requires
9344 special treatment. */
9345 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9346 gen_rtx_REG (DImode, 28), const0_rtx);
9347 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9351 if ((INTEGRAL_TYPE_P (valtype)
9352 && GET_MODE_BITSIZE (TYPE_MODE (valtype)) < BITS_PER_WORD)
9353 || POINTER_TYPE_P (valtype))
9354 valmode = word_mode;
9356 valmode = TYPE_MODE (valtype);
9358 if (TREE_CODE (valtype) == REAL_TYPE
9359 && !AGGREGATE_TYPE_P (valtype)
9360 && TYPE_MODE (valtype) != TFmode
9361 && !TARGET_SOFT_FLOAT)
9362 return gen_rtx_REG (valmode, 32);
9364 return gen_rtx_REG (valmode, 28);
9367 /* Implement the TARGET_LIBCALL_VALUE hook. */
9370 pa_libcall_value (enum machine_mode mode,
9371 const_rtx fun ATTRIBUTE_UNUSED)
9373 if (! TARGET_SOFT_FLOAT
9374 && (mode == SFmode || mode == DFmode))
9375 return gen_rtx_REG (mode, 32);
9377 return gen_rtx_REG (mode, 28);
9380 /* Implement the TARGET_FUNCTION_VALUE_REGNO_P hook. */
9383 pa_function_value_regno_p (const unsigned int regno)
9386 || (! TARGET_SOFT_FLOAT && regno == 32))
9392 /* Update the data in CUM to advance over an argument
9393 of mode MODE and data type TYPE.
9394 (TYPE is null for libcalls where that information may not be available.) */
9397 pa_function_arg_advance (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9398 const_tree type, bool named ATTRIBUTE_UNUSED)
9400 int arg_size = FUNCTION_ARG_SIZE (mode, type);
9402 cum->nargs_prototype--;
9403 cum->words += (arg_size
9404 + ((cum->words & 01)
9405 && type != NULL_TREE
9409 /* Return the location of a parameter that is passed in a register or NULL
9410 if the parameter has any component that is passed in memory.
9412 This is new code and will be pushed to into the net sources after
9415 ??? We might want to restructure this so that it looks more like other
9418 pa_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9419 const_tree type, bool named ATTRIBUTE_UNUSED)
9421 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9428 if (mode == VOIDmode)
9431 arg_size = FUNCTION_ARG_SIZE (mode, type);
9433 /* If this arg would be passed partially or totally on the stack, then
9434 this routine should return zero. pa_arg_partial_bytes will
9435 handle arguments which are split between regs and stack slots if
9436 the ABI mandates split arguments. */
9439 /* The 32-bit ABI does not split arguments. */
9440 if (cum->words + arg_size > max_arg_words)
9446 alignment = cum->words & 1;
9447 if (cum->words + alignment >= max_arg_words)
9451 /* The 32bit ABIs and the 64bit ABIs are rather different,
9452 particularly in their handling of FP registers. We might
9453 be able to cleverly share code between them, but I'm not
9454 going to bother in the hope that splitting them up results
9455 in code that is more easily understood. */
9459 /* Advance the base registers to their current locations.
9461 Remember, gprs grow towards smaller register numbers while
9462 fprs grow to higher register numbers. Also remember that
9463 although FP regs are 32-bit addressable, we pretend that
9464 the registers are 64-bits wide. */
9465 gpr_reg_base = 26 - cum->words;
9466 fpr_reg_base = 32 + cum->words;
9468 /* Arguments wider than one word and small aggregates need special
9472 || (type && (AGGREGATE_TYPE_P (type)
9473 || TREE_CODE (type) == COMPLEX_TYPE
9474 || TREE_CODE (type) == VECTOR_TYPE)))
9476 /* Double-extended precision (80-bit), quad-precision (128-bit)
9477 and aggregates including complex numbers are aligned on
9478 128-bit boundaries. The first eight 64-bit argument slots
9479 are associated one-to-one, with general registers r26
9480 through r19, and also with floating-point registers fr4
9481 through fr11. Arguments larger than one word are always
9482 passed in general registers.
9484 Using a PARALLEL with a word mode register results in left
9485 justified data on a big-endian target. */
9488 int i, offset = 0, ub = arg_size;
9490 /* Align the base register. */
9491 gpr_reg_base -= alignment;
9493 ub = MIN (ub, max_arg_words - cum->words - alignment);
9494 for (i = 0; i < ub; i++)
9496 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9497 gen_rtx_REG (DImode, gpr_reg_base),
9503 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9508 /* If the argument is larger than a word, then we know precisely
9509 which registers we must use. */
9523 /* Structures 5 to 8 bytes in size are passed in the general
9524 registers in the same manner as other non floating-point
9525 objects. The data is right-justified and zero-extended
9526 to 64 bits. This is opposite to the normal justification
9527 used on big endian targets and requires special treatment.
9528 We now define BLOCK_REG_PADDING to pad these objects.
9529 Aggregates, complex and vector types are passed in the same
9530 manner as structures. */
9532 || (type && (AGGREGATE_TYPE_P (type)
9533 || TREE_CODE (type) == COMPLEX_TYPE
9534 || TREE_CODE (type) == VECTOR_TYPE)))
9536 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9537 gen_rtx_REG (DImode, gpr_reg_base),
9539 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
9544 /* We have a single word (32 bits). A simple computation
9545 will get us the register #s we need. */
9546 gpr_reg_base = 26 - cum->words;
9547 fpr_reg_base = 32 + 2 * cum->words;
9551 /* Determine if the argument needs to be passed in both general and
9552 floating point registers. */
9553 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9554 /* If we are doing soft-float with portable runtime, then there
9555 is no need to worry about FP regs. */
9556 && !TARGET_SOFT_FLOAT
9557 /* The parameter must be some kind of scalar float, else we just
9558 pass it in integer registers. */
9559 && GET_MODE_CLASS (mode) == MODE_FLOAT
9560 /* The target function must not have a prototype. */
9561 && cum->nargs_prototype <= 0
9562 /* libcalls do not need to pass items in both FP and general
9564 && type != NULL_TREE
9565 /* All this hair applies to "outgoing" args only. This includes
9566 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9568 /* Also pass outgoing floating arguments in both registers in indirect
9569 calls with the 32 bit ABI and the HP assembler since there is no
9570 way to the specify argument locations in static functions. */
9575 && GET_MODE_CLASS (mode) == MODE_FLOAT))
9581 gen_rtx_EXPR_LIST (VOIDmode,
9582 gen_rtx_REG (mode, fpr_reg_base),
9584 gen_rtx_EXPR_LIST (VOIDmode,
9585 gen_rtx_REG (mode, gpr_reg_base),
9590 /* See if we should pass this parameter in a general register. */
9591 if (TARGET_SOFT_FLOAT
9592 /* Indirect calls in the normal 32bit ABI require all arguments
9593 to be passed in general registers. */
9594 || (!TARGET_PORTABLE_RUNTIME
9598 /* If the parameter is not a scalar floating-point parameter,
9599 then it belongs in GPRs. */
9600 || GET_MODE_CLASS (mode) != MODE_FLOAT
9601 /* Structure with single SFmode field belongs in GPR. */
9602 || (type && AGGREGATE_TYPE_P (type)))
9603 retval = gen_rtx_REG (mode, gpr_reg_base);
9605 retval = gen_rtx_REG (mode, fpr_reg_base);
9610 /* Arguments larger than one word are double word aligned. */
9613 pa_function_arg_boundary (enum machine_mode mode, const_tree type)
9615 bool singleword = (type
9616 ? (integer_zerop (TYPE_SIZE (type))
9617 || !TREE_CONSTANT (TYPE_SIZE (type))
9618 || int_size_in_bytes (type) <= UNITS_PER_WORD)
9619 : GET_MODE_SIZE (mode) <= UNITS_PER_WORD);
9621 return singleword ? PARM_BOUNDARY : MAX_PARM_BOUNDARY;
9624 /* If this arg would be passed totally in registers or totally on the stack,
9625 then this routine should return zero. */
9628 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9629 tree type, bool named ATTRIBUTE_UNUSED)
9631 unsigned int max_arg_words = 8;
9632 unsigned int offset = 0;
9637 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9640 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9641 /* Arg fits fully into registers. */
9643 else if (cum->words + offset >= max_arg_words)
9644 /* Arg fully on the stack. */
9648 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9652 /* A get_unnamed_section callback for switching to the text section.
9654 This function is only used with SOM. Because we don't support
9655 named subspaces, we can only create a new subspace or switch back
9656 to the default text subspace. */
9659 som_output_text_section_asm_op (const void *data ATTRIBUTE_UNUSED)
9661 gcc_assert (TARGET_SOM);
9664 if (cfun && cfun->machine && !cfun->machine->in_nsubspa)
9666 /* We only want to emit a .nsubspa directive once at the
9667 start of the function. */
9668 cfun->machine->in_nsubspa = 1;
9670 /* Create a new subspace for the text. This provides
9671 better stub placement and one-only functions. */
9673 && DECL_ONE_ONLY (cfun->decl)
9674 && !DECL_WEAK (cfun->decl))
9676 output_section_asm_op ("\t.SPACE $TEXT$\n"
9677 "\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,"
9678 "ACCESS=44,SORT=24,COMDAT");
9684 /* There isn't a current function or the body of the current
9685 function has been completed. So, we are changing to the
9686 text section to output debugging information. Thus, we
9687 need to forget that we are in the text section so that
9688 varasm.c will call us when text_section is selected again. */
9689 gcc_assert (!cfun || !cfun->machine
9690 || cfun->machine->in_nsubspa == 2);
9693 output_section_asm_op ("\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$");
9696 output_section_asm_op ("\t.SPACE $TEXT$\n\t.SUBSPA $CODE$");
9699 /* A get_unnamed_section callback for switching to comdat data
9700 sections. This function is only used with SOM. */
9703 som_output_comdat_data_section_asm_op (const void *data)
9706 output_section_asm_op (data);
9709 /* Implement TARGET_ASM_INITIALIZE_SECTIONS */
9712 pa_som_asm_init_sections (void)
9715 = get_unnamed_section (0, som_output_text_section_asm_op, NULL);
9717 /* SOM puts readonly data in the default $LIT$ subspace when PIC code
9718 is not being generated. */
9719 som_readonly_data_section
9720 = get_unnamed_section (0, output_section_asm_op,
9721 "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$");
9723 /* When secondary definitions are not supported, SOM makes readonly
9724 data one-only by creating a new $LIT$ subspace in $TEXT$ with
9726 som_one_only_readonly_data_section
9727 = get_unnamed_section (0, som_output_comdat_data_section_asm_op,
9729 "\t.NSUBSPA $LIT$,QUAD=0,ALIGN=8,"
9730 "ACCESS=0x2c,SORT=16,COMDAT");
9733 /* When secondary definitions are not supported, SOM makes data one-only
9734 by creating a new $DATA$ subspace in $PRIVATE$ with the comdat flag. */
9735 som_one_only_data_section
9736 = get_unnamed_section (SECTION_WRITE,
9737 som_output_comdat_data_section_asm_op,
9738 "\t.SPACE $PRIVATE$\n"
9739 "\t.NSUBSPA $DATA$,QUAD=1,ALIGN=8,"
9740 "ACCESS=31,SORT=24,COMDAT");
9742 /* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups
9743 which reference data within the $TEXT$ space (for example constant
9744 strings in the $LIT$ subspace).
9746 The assemblers (GAS and HP as) both have problems with handling
9747 the difference of two symbols which is the other correct way to
9748 reference constant data during PIC code generation.
9750 So, there's no way to reference constant data which is in the
9751 $TEXT$ space during PIC generation. Instead place all constant
9752 data into the $PRIVATE$ subspace (this reduces sharing, but it
9753 works correctly). */
9754 readonly_data_section = flag_pic ? data_section : som_readonly_data_section;
9756 /* We must not have a reference to an external symbol defined in a
9757 shared library in a readonly section, else the SOM linker will
9760 So, we force exception information into the data section. */
9761 exception_section = data_section;
9764 /* On hpux10, the linker will give an error if we have a reference
9765 in the read-only data section to a symbol defined in a shared
9766 library. Therefore, expressions that might require a reloc can
9767 not be placed in the read-only data section. */
9770 pa_select_section (tree exp, int reloc,
9771 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9773 if (TREE_CODE (exp) == VAR_DECL
9774 && TREE_READONLY (exp)
9775 && !TREE_THIS_VOLATILE (exp)
9776 && DECL_INITIAL (exp)
9777 && (DECL_INITIAL (exp) == error_mark_node
9778 || TREE_CONSTANT (DECL_INITIAL (exp)))
9782 && DECL_ONE_ONLY (exp)
9783 && !DECL_WEAK (exp))
9784 return som_one_only_readonly_data_section;
9786 return readonly_data_section;
9788 else if (CONSTANT_CLASS_P (exp) && !reloc)
9789 return readonly_data_section;
9791 && TREE_CODE (exp) == VAR_DECL
9792 && DECL_ONE_ONLY (exp)
9793 && !DECL_WEAK (exp))
9794 return som_one_only_data_section;
9796 return data_section;
9800 pa_globalize_label (FILE *stream, const char *name)
9802 /* We only handle DATA objects here, functions are globalized in
9803 ASM_DECLARE_FUNCTION_NAME. */
9804 if (! FUNCTION_NAME_P (name))
9806 fputs ("\t.EXPORT ", stream);
9807 assemble_name (stream, name);
9808 fputs (",DATA\n", stream);
9812 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9815 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9816 int incoming ATTRIBUTE_UNUSED)
9818 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9821 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9824 pa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
9826 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9827 PA64 ABI says that objects larger than 128 bits are returned in memory.
9828 Note, int_size_in_bytes can return -1 if the size of the object is
9829 variable or larger than the maximum value that can be expressed as
9830 a HOST_WIDE_INT. It can also return zero for an empty type. The
9831 simplest way to handle variable and empty types is to pass them in
9832 memory. This avoids problems in defining the boundaries of argument
9833 slots, allocating registers, etc. */
9834 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9835 || int_size_in_bytes (type) <= 0);
9838 /* Structure to hold declaration and name of external symbols that are
9839 emitted by GCC. We generate a vector of these symbols and output them
9840 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9841 This avoids putting out names that are never really used. */
9843 typedef struct GTY(()) extern_symbol
9849 /* Define gc'd vector type for extern_symbol. */
9850 DEF_VEC_O(extern_symbol);
9851 DEF_VEC_ALLOC_O(extern_symbol,gc);
9853 /* Vector of extern_symbol pointers. */
9854 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9856 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9857 /* Mark DECL (name NAME) as an external reference (assembler output
9858 file FILE). This saves the names to output at the end of the file
9859 if actually referenced. */
9862 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9864 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9866 gcc_assert (file == asm_out_file);
9871 /* Output text required at the end of an assembler file.
9872 This includes deferred plabels and .import directives for
9873 all external symbols that were actually referenced. */
9876 pa_hpux_file_end (void)
9881 if (!NO_DEFERRED_PROFILE_COUNTERS)
9882 output_deferred_profile_counters ();
9884 output_deferred_plabels ();
9886 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9888 tree decl = p->decl;
9890 if (!TREE_ASM_WRITTEN (decl)
9891 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9892 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9895 VEC_free (extern_symbol, gc, extern_symbols);
9899 /* Return true if a change from mode FROM to mode TO for a register
9900 in register class RCLASS is invalid. */
9903 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
9904 enum reg_class rclass)
9909 /* Reject changes to/from complex and vector modes. */
9910 if (COMPLEX_MODE_P (from) || VECTOR_MODE_P (from)
9911 || COMPLEX_MODE_P (to) || VECTOR_MODE_P (to))
9914 if (GET_MODE_SIZE (from) == GET_MODE_SIZE (to))
9917 /* There is no way to load QImode or HImode values directly from
9918 memory. SImode loads to the FP registers are not zero extended.
9919 On the 64-bit target, this conflicts with the definition of
9920 LOAD_EXTEND_OP. Thus, we can't allow changing between modes
9921 with different sizes in the floating-point registers. */
9922 if (MAYBE_FP_REG_CLASS_P (rclass))
9925 /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
9926 in specific sets of registers. Thus, we cannot allow changing
9927 to a larger mode when it's larger than a word. */
9928 if (GET_MODE_SIZE (to) > UNITS_PER_WORD
9929 && GET_MODE_SIZE (to) > GET_MODE_SIZE (from))
9935 /* Returns TRUE if it is a good idea to tie two pseudo registers
9936 when one has mode MODE1 and one has mode MODE2.
9937 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
9938 for any hard reg, then this must be FALSE for correct output.
9940 We should return FALSE for QImode and HImode because these modes
9941 are not ok in the floating-point registers. However, this prevents
9942 tieing these modes to SImode and DImode in the general registers.
9943 So, this isn't a good idea. We rely on HARD_REGNO_MODE_OK and
9944 CANNOT_CHANGE_MODE_CLASS to prevent these modes from being used
9945 in the floating-point registers. */
9948 pa_modes_tieable_p (enum machine_mode mode1, enum machine_mode mode2)
9950 /* Don't tie modes in different classes. */
9951 if (GET_MODE_CLASS (mode1) != GET_MODE_CLASS (mode2))
9958 /* Length in units of the trampoline instruction code. */
9960 #define TRAMPOLINE_CODE_SIZE (TARGET_64BIT ? 24 : (TARGET_PA_20 ? 32 : 40))
9963 /* Output assembler code for a block containing the constant parts
9964 of a trampoline, leaving space for the variable parts.\
9966 The trampoline sets the static chain pointer to STATIC_CHAIN_REGNUM
9967 and then branches to the specified routine.
9969 This code template is copied from text segment to stack location
9970 and then patched with pa_trampoline_init to contain valid values,
9971 and then entered as a subroutine.
9973 It is best to keep this as small as possible to avoid having to
9974 flush multiple lines in the cache. */
9977 pa_asm_trampoline_template (FILE *f)
9981 fputs ("\tldw 36(%r22),%r21\n", f);
9982 fputs ("\tbb,>=,n %r21,30,.+16\n", f);
9983 if (ASSEMBLER_DIALECT == 0)
9984 fputs ("\tdepi 0,31,2,%r21\n", f);
9986 fputs ("\tdepwi 0,31,2,%r21\n", f);
9987 fputs ("\tldw 4(%r21),%r19\n", f);
9988 fputs ("\tldw 0(%r21),%r21\n", f);
9991 fputs ("\tbve (%r21)\n", f);
9992 fputs ("\tldw 40(%r22),%r29\n", f);
9993 fputs ("\t.word 0\n", f);
9994 fputs ("\t.word 0\n", f);
9998 fputs ("\tldsid (%r21),%r1\n", f);
9999 fputs ("\tmtsp %r1,%sr0\n", f);
10000 fputs ("\tbe 0(%sr0,%r21)\n", f);
10001 fputs ("\tldw 40(%r22),%r29\n", f);
10003 fputs ("\t.word 0\n", f);
10004 fputs ("\t.word 0\n", f);
10005 fputs ("\t.word 0\n", f);
10006 fputs ("\t.word 0\n", f);
10010 fputs ("\t.dword 0\n", f);
10011 fputs ("\t.dword 0\n", f);
10012 fputs ("\t.dword 0\n", f);
10013 fputs ("\t.dword 0\n", f);
10014 fputs ("\tmfia %r31\n", f);
10015 fputs ("\tldd 24(%r31),%r1\n", f);
10016 fputs ("\tldd 24(%r1),%r27\n", f);
10017 fputs ("\tldd 16(%r1),%r1\n", f);
10018 fputs ("\tbve (%r1)\n", f);
10019 fputs ("\tldd 32(%r31),%r31\n", f);
10020 fputs ("\t.dword 0 ; fptr\n", f);
10021 fputs ("\t.dword 0 ; static link\n", f);
10025 /* Emit RTL insns to initialize the variable parts of a trampoline.
10026 FNADDR is an RTX for the address of the function's pure code.
10027 CXT is an RTX for the static chain value for the function.
10029 Move the function address to the trampoline template at offset 36.
10030 Move the static chain value to trampoline template at offset 40.
10031 Move the trampoline address to trampoline template at offset 44.
10032 Move r19 to trampoline template at offset 48. The latter two
10033 words create a plabel for the indirect call to the trampoline.
10035 A similar sequence is used for the 64-bit port but the plabel is
10036 at the beginning of the trampoline.
10038 Finally, the cache entries for the trampoline code are flushed.
10039 This is necessary to ensure that the trampoline instruction sequence
10040 is written to memory prior to any attempts at prefetching the code
10044 pa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
10046 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
10047 rtx start_addr = gen_reg_rtx (Pmode);
10048 rtx end_addr = gen_reg_rtx (Pmode);
10049 rtx line_length = gen_reg_rtx (Pmode);
10052 emit_block_move (m_tramp, assemble_trampoline_template (),
10053 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
10054 r_tramp = force_reg (Pmode, XEXP (m_tramp, 0));
10058 tmp = adjust_address (m_tramp, Pmode, 36);
10059 emit_move_insn (tmp, fnaddr);
10060 tmp = adjust_address (m_tramp, Pmode, 40);
10061 emit_move_insn (tmp, chain_value);
10063 /* Create a fat pointer for the trampoline. */
10064 tmp = adjust_address (m_tramp, Pmode, 44);
10065 emit_move_insn (tmp, r_tramp);
10066 tmp = adjust_address (m_tramp, Pmode, 48);
10067 emit_move_insn (tmp, gen_rtx_REG (Pmode, 19));
10069 /* fdc and fic only use registers for the address to flush,
10070 they do not accept integer displacements. We align the
10071 start and end addresses to the beginning of their respective
10072 cache lines to minimize the number of lines flushed. */
10073 emit_insn (gen_andsi3 (start_addr, r_tramp,
10074 GEN_INT (-MIN_CACHELINE_SIZE)));
10075 tmp = force_reg (Pmode, plus_constant (r_tramp, TRAMPOLINE_CODE_SIZE-1));
10076 emit_insn (gen_andsi3 (end_addr, tmp,
10077 GEN_INT (-MIN_CACHELINE_SIZE)));
10078 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10079 emit_insn (gen_dcacheflushsi (start_addr, end_addr, line_length));
10080 emit_insn (gen_icacheflushsi (start_addr, end_addr, line_length,
10081 gen_reg_rtx (Pmode),
10082 gen_reg_rtx (Pmode)));
10086 tmp = adjust_address (m_tramp, Pmode, 56);
10087 emit_move_insn (tmp, fnaddr);
10088 tmp = adjust_address (m_tramp, Pmode, 64);
10089 emit_move_insn (tmp, chain_value);
10091 /* Create a fat pointer for the trampoline. */
10092 tmp = adjust_address (m_tramp, Pmode, 16);
10093 emit_move_insn (tmp, force_reg (Pmode, plus_constant (r_tramp, 32)));
10094 tmp = adjust_address (m_tramp, Pmode, 24);
10095 emit_move_insn (tmp, gen_rtx_REG (Pmode, 27));
10097 /* fdc and fic only use registers for the address to flush,
10098 they do not accept integer displacements. We align the
10099 start and end addresses to the beginning of their respective
10100 cache lines to minimize the number of lines flushed. */
10101 tmp = force_reg (Pmode, plus_constant (r_tramp, 32));
10102 emit_insn (gen_anddi3 (start_addr, tmp,
10103 GEN_INT (-MIN_CACHELINE_SIZE)));
10104 tmp = force_reg (Pmode, plus_constant (tmp, TRAMPOLINE_CODE_SIZE - 1));
10105 emit_insn (gen_anddi3 (end_addr, tmp,
10106 GEN_INT (-MIN_CACHELINE_SIZE)));
10107 emit_move_insn (line_length, GEN_INT (MIN_CACHELINE_SIZE));
10108 emit_insn (gen_dcacheflushdi (start_addr, end_addr, line_length));
10109 emit_insn (gen_icacheflushdi (start_addr, end_addr, line_length,
10110 gen_reg_rtx (Pmode),
10111 gen_reg_rtx (Pmode)));
10115 /* Perform any machine-specific adjustment in the address of the trampoline.
10116 ADDR contains the address that was passed to pa_trampoline_init.
10117 Adjust the trampoline address to point to the plabel at offset 44. */
10120 pa_trampoline_adjust_address (rtx addr)
10123 addr = memory_address (Pmode, plus_constant (addr, 46));
10128 pa_delegitimize_address (rtx orig_x)
10130 rtx x = delegitimize_mem_from_attrs (orig_x);
10132 if (GET_CODE (x) == LO_SUM
10133 && GET_CODE (XEXP (x, 1)) == UNSPEC
10134 && XINT (XEXP (x, 1), 1) == UNSPEC_DLTIND14R)
10135 return gen_const_mem (Pmode, XVECEXP (XEXP (x, 1), 0, 0));
10140 pa_internal_arg_pointer (void)
10142 /* The argument pointer and the hard frame pointer are the same in
10143 the 32-bit runtime, so we don't need a copy. */
10145 return copy_to_reg (virtual_incoming_args_rtx);
10147 return virtual_incoming_args_rtx;
10150 /* Given FROM and TO register numbers, say whether this elimination is allowed.
10151 Frame pointer elimination is automatically handled. */
10154 pa_can_eliminate (const int from, const int to)
10156 /* The argument cannot be eliminated in the 64-bit runtime. */
10157 if (TARGET_64BIT && from == ARG_POINTER_REGNUM)
10160 return (from == HARD_FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM
10161 ? ! frame_pointer_needed
10165 /* Define the offset between two registers, FROM to be eliminated and its
10166 replacement TO, at the start of a routine. */
10168 pa_initial_elimination_offset (int from, int to)
10170 HOST_WIDE_INT offset;
10172 if ((from == HARD_FRAME_POINTER_REGNUM || from == FRAME_POINTER_REGNUM)
10173 && to == STACK_POINTER_REGNUM)
10174 offset = -compute_frame_size (get_frame_size (), 0);
10175 else if (from == FRAME_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM)
10178 gcc_unreachable ();
10184 pa_conditional_register_usage (void)
10188 if (!TARGET_64BIT && !TARGET_PA_11)
10190 for (i = 56; i <= FP_REG_LAST; i++)
10191 fixed_regs[i] = call_used_regs[i] = 1;
10192 for (i = 33; i < 56; i += 2)
10193 fixed_regs[i] = call_used_regs[i] = 1;
10195 if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)
10197 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
10198 fixed_regs[i] = call_used_regs[i] = 1;
10201 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1;