1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 51 Franklin Street, Fifth Floor,
21 Boston, MA 02110-1301, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static bool pa_handle_option (size_t, const char *, int);
88 static int hppa_address_cost (rtx);
89 static bool hppa_rtx_costs (rtx, int, int, int *);
90 static inline rtx force_mode (enum machine_mode, rtx);
91 static void pa_reorg (void);
92 static void pa_combine_instructions (void);
93 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
94 static int forward_branch_p (rtx);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static bool pa_scalar_mode_supported_p (enum machine_mode);
127 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
129 static struct deferred_plabel *get_plabel (rtx) ATTRIBUTE_UNUSED;
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef ASM_OUTPUT_EXTERNAL_REAL
141 static void pa_hpux_file_end (void);
143 #ifdef HPUX_LONG_DOUBLE_LIBRARY
144 static void pa_hpux_init_libfuncs (void);
146 static rtx pa_struct_value_rtx (tree, int);
147 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
149 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
151 static struct machine_function * pa_init_machine_status (void);
154 /* Save the operands last given to a compare for use when we
155 generate a scc or bcc insn. */
156 rtx hppa_compare_op0, hppa_compare_op1;
157 enum cmp_type hppa_branch_type;
159 /* Which cpu we are scheduling for. */
160 enum processor_type pa_cpu = TARGET_SCHED_DEFAULT;
162 /* The UNIX standard to use for predefines and linking. */
163 int flag_pa_unix = TARGET_HPUX_11_11 ? 1998 : TARGET_HPUX_10_10 ? 1995 : 1993;
165 /* Counts for the number of callee-saved general and floating point
166 registers which were saved by the current function's prologue. */
167 static int gr_saved, fr_saved;
169 static rtx find_addr_reg (rtx);
171 /* Keep track of the number of bytes we have output in the CODE subspace
172 during this compilation so we'll know when to emit inline long-calls. */
173 unsigned long total_code_bytes;
175 /* The last address of the previous function plus the number of bytes in
176 associated thunks that have been output. This is used to determine if
177 a thunk can use an IA-relative branch to reach its target function. */
178 static int last_address;
180 /* Variables to handle plabels that we discover are necessary at assembly
181 output time. They are output after the current function. */
182 struct deferred_plabel GTY(())
187 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
189 static size_t n_deferred_plabels = 0;
192 /* Initialize the GCC target structure. */
194 #undef TARGET_ASM_ALIGNED_HI_OP
195 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
196 #undef TARGET_ASM_ALIGNED_SI_OP
197 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
198 #undef TARGET_ASM_ALIGNED_DI_OP
199 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
200 #undef TARGET_ASM_UNALIGNED_HI_OP
201 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
202 #undef TARGET_ASM_UNALIGNED_SI_OP
203 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
204 #undef TARGET_ASM_UNALIGNED_DI_OP
205 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
206 #undef TARGET_ASM_INTEGER
207 #define TARGET_ASM_INTEGER pa_assemble_integer
209 #undef TARGET_ASM_FUNCTION_PROLOGUE
210 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
211 #undef TARGET_ASM_FUNCTION_EPILOGUE
212 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
214 #undef TARGET_SCHED_ADJUST_COST
215 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
216 #undef TARGET_SCHED_ADJUST_PRIORITY
217 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
218 #undef TARGET_SCHED_ISSUE_RATE
219 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
221 #undef TARGET_ENCODE_SECTION_INFO
222 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
223 #undef TARGET_STRIP_NAME_ENCODING
224 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
226 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
227 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
229 #undef TARGET_ASM_OUTPUT_MI_THUNK
230 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
231 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
232 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
234 #undef TARGET_ASM_FILE_END
235 #ifdef ASM_OUTPUT_EXTERNAL_REAL
236 #define TARGET_ASM_FILE_END pa_hpux_file_end
238 #define TARGET_ASM_FILE_END output_deferred_plabels
241 #if !defined(USE_COLLECT2)
242 #undef TARGET_ASM_CONSTRUCTOR
243 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
244 #undef TARGET_ASM_DESTRUCTOR
245 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
248 #undef TARGET_DEFAULT_TARGET_FLAGS
249 #define TARGET_DEFAULT_TARGET_FLAGS (TARGET_DEFAULT | TARGET_CPU_DEFAULT)
250 #undef TARGET_HANDLE_OPTION
251 #define TARGET_HANDLE_OPTION pa_handle_option
253 #undef TARGET_INIT_BUILTINS
254 #define TARGET_INIT_BUILTINS pa_init_builtins
256 #undef TARGET_RTX_COSTS
257 #define TARGET_RTX_COSTS hppa_rtx_costs
258 #undef TARGET_ADDRESS_COST
259 #define TARGET_ADDRESS_COST hppa_address_cost
261 #undef TARGET_MACHINE_DEPENDENT_REORG
262 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
264 #ifdef HPUX_LONG_DOUBLE_LIBRARY
265 #undef TARGET_INIT_LIBFUNCS
266 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
269 #undef TARGET_PROMOTE_FUNCTION_RETURN
270 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
271 #undef TARGET_PROMOTE_PROTOTYPES
272 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
274 #undef TARGET_STRUCT_VALUE_RTX
275 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
276 #undef TARGET_RETURN_IN_MEMORY
277 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
278 #undef TARGET_MUST_PASS_IN_STACK
279 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
280 #undef TARGET_PASS_BY_REFERENCE
281 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
282 #undef TARGET_CALLEE_COPIES
283 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
284 #undef TARGET_ARG_PARTIAL_BYTES
285 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
287 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
288 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
289 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
290 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
292 #undef TARGET_SCALAR_MODE_SUPPORTED_P
293 #define TARGET_SCALAR_MODE_SUPPORTED_P pa_scalar_mode_supported_p
295 #undef TARGET_CANNOT_FORCE_CONST_MEM
296 #define TARGET_CANNOT_FORCE_CONST_MEM pa_tls_referenced_p
298 struct gcc_target targetm = TARGET_INITIALIZER;
300 /* Parse the -mfixed-range= option string. */
303 fix_range (const char *const_str)
306 char *str, *dash, *comma;
308 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
309 REG2 are either register names or register numbers. The effect
310 of this option is to mark the registers in the range from REG1 to
311 REG2 as ``fixed'' so they won't be used by the compiler. This is
312 used, e.g., to ensure that kernel mode code doesn't use fr4-fr31. */
314 i = strlen (const_str);
315 str = (char *) alloca (i + 1);
316 memcpy (str, const_str, i + 1);
320 dash = strchr (str, '-');
323 warning (0, "value of -mfixed-range must have form REG1-REG2");
328 comma = strchr (dash + 1, ',');
332 first = decode_reg_name (str);
335 warning (0, "unknown register name: %s", str);
339 last = decode_reg_name (dash + 1);
342 warning (0, "unknown register name: %s", dash + 1);
350 warning (0, "%s-%s is an empty range", str, dash + 1);
354 for (i = first; i <= last; ++i)
355 fixed_regs[i] = call_used_regs[i] = 1;
364 /* Check if all floating point registers have been fixed. */
365 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
370 target_flags |= MASK_DISABLE_FPREGS;
373 /* Implement TARGET_HANDLE_OPTION. */
376 pa_handle_option (size_t code, const char *arg, int value ATTRIBUTE_UNUSED)
381 case OPT_mpa_risc_1_0:
383 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
387 case OPT_mpa_risc_1_1:
389 target_flags &= ~MASK_PA_20;
390 target_flags |= MASK_PA_11;
393 case OPT_mpa_risc_2_0:
395 target_flags |= MASK_PA_11 | MASK_PA_20;
399 if (strcmp (arg, "8000") == 0)
400 pa_cpu = PROCESSOR_8000;
401 else if (strcmp (arg, "7100") == 0)
402 pa_cpu = PROCESSOR_7100;
403 else if (strcmp (arg, "700") == 0)
404 pa_cpu = PROCESSOR_700;
405 else if (strcmp (arg, "7100LC") == 0)
406 pa_cpu = PROCESSOR_7100LC;
407 else if (strcmp (arg, "7200") == 0)
408 pa_cpu = PROCESSOR_7200;
409 else if (strcmp (arg, "7300") == 0)
410 pa_cpu = PROCESSOR_7300;
415 case OPT_mfixed_range_:
425 #if TARGET_HPUX_10_10
431 #if TARGET_HPUX_11_11
443 override_options (void)
445 /* Unconditional branches in the delay slot are not compatible with dwarf2
446 call frame information. There is no benefit in using this optimization
447 on PA8000 and later processors. */
448 if (pa_cpu >= PROCESSOR_8000
449 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
450 || flag_unwind_tables)
451 target_flags &= ~MASK_JUMP_IN_DELAY;
453 if (flag_pic && TARGET_PORTABLE_RUNTIME)
455 warning (0, "PIC code generation is not supported in the portable runtime model");
458 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
460 warning (0, "PIC code generation is not compatible with fast indirect calls");
463 if (! TARGET_GAS && write_symbols != NO_DEBUG)
465 warning (0, "-g is only supported when using GAS on this processor,");
466 warning (0, "-g option disabled");
467 write_symbols = NO_DEBUG;
470 /* We only support the "big PIC" model now. And we always generate PIC
471 code when in 64bit mode. */
472 if (flag_pic == 1 || TARGET_64BIT)
475 /* We can't guarantee that .dword is available for 32-bit targets. */
476 if (UNITS_PER_WORD == 4)
477 targetm.asm_out.aligned_op.di = NULL;
479 /* The unaligned ops are only available when using GAS. */
482 targetm.asm_out.unaligned_op.hi = NULL;
483 targetm.asm_out.unaligned_op.si = NULL;
484 targetm.asm_out.unaligned_op.di = NULL;
487 init_machine_status = pa_init_machine_status;
491 pa_init_builtins (void)
493 #ifdef DONT_HAVE_FPUTC_UNLOCKED
494 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
495 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
499 /* Function to init struct machine_function.
500 This will be called, via a pointer variable,
501 from push_function_context. */
503 static struct machine_function *
504 pa_init_machine_status (void)
506 return ggc_alloc_cleared (sizeof (machine_function));
509 /* If FROM is a probable pointer register, mark TO as a probable
510 pointer register with the same pointer alignment as FROM. */
513 copy_reg_pointer (rtx to, rtx from)
515 if (REG_POINTER (from))
516 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
519 /* Return 1 if X contains a symbolic expression. We know these
520 expressions will have one of a few well defined forms, so
521 we need only check those forms. */
523 symbolic_expression_p (rtx x)
526 /* Strip off any HIGH. */
527 if (GET_CODE (x) == HIGH)
530 return (symbolic_operand (x, VOIDmode));
533 /* Accept any constant that can be moved in one instruction into a
536 cint_ok_for_move (HOST_WIDE_INT intval)
538 /* OK if ldo, ldil, or zdepi, can be used. */
539 return (CONST_OK_FOR_LETTER_P (intval, 'J')
540 || CONST_OK_FOR_LETTER_P (intval, 'N')
541 || CONST_OK_FOR_LETTER_P (intval, 'K'));
544 /* Return truth value of whether OP can be used as an operand in a
547 adddi3_operand (rtx op, enum machine_mode mode)
549 return (register_operand (op, mode)
550 || (GET_CODE (op) == CONST_INT
551 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
554 /* True iff zdepi can be used to generate this CONST_INT.
555 zdepi first sign extends a 5 bit signed number to a given field
556 length, then places this field anywhere in a zero. */
558 zdepi_cint_p (unsigned HOST_WIDE_INT x)
560 unsigned HOST_WIDE_INT lsb_mask, t;
562 /* This might not be obvious, but it's at least fast.
563 This function is critical; we don't have the time loops would take. */
565 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
566 /* Return true iff t is a power of two. */
567 return ((t & (t - 1)) == 0);
570 /* True iff depi or extru can be used to compute (reg & mask).
571 Accept bit pattern like these:
576 and_mask_p (unsigned HOST_WIDE_INT mask)
579 mask += mask & -mask;
580 return (mask & (mask - 1)) == 0;
583 /* True iff depi can be used to compute (reg | MASK). */
585 ior_mask_p (unsigned HOST_WIDE_INT mask)
587 mask += mask & -mask;
588 return (mask & (mask - 1)) == 0;
591 /* Legitimize PIC addresses. If the address is already
592 position-independent, we return ORIG. Newly generated
593 position-independent addresses go to REG. If we need more
594 than one register, we lose. */
597 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
601 if (PA_SYMBOL_REF_TLS_P (orig))
604 /* Labels need special handling. */
605 if (pic_label_operand (orig, mode))
607 /* We do not want to go through the movXX expanders here since that
608 would create recursion.
610 Nor do we really want to call a generator for a named pattern
611 since that requires multiple patterns if we want to support
614 So instead we just emit the raw set, which avoids the movXX
615 expanders completely. */
616 mark_reg_pointer (reg, BITS_PER_UNIT);
617 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
618 current_function_uses_pic_offset_table = 1;
621 if (GET_CODE (orig) == SYMBOL_REF)
627 /* Before reload, allocate a temporary register for the intermediate
628 result. This allows the sequence to be deleted when the final
629 result is unused and the insns are trivially dead. */
630 tmp_reg = ((reload_in_progress || reload_completed)
631 ? reg : gen_reg_rtx (Pmode));
633 emit_move_insn (tmp_reg,
634 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
635 gen_rtx_HIGH (word_mode, orig)));
637 = gen_const_mem (Pmode,
638 gen_rtx_LO_SUM (Pmode, tmp_reg,
639 gen_rtx_UNSPEC (Pmode,
643 current_function_uses_pic_offset_table = 1;
644 mark_reg_pointer (reg, BITS_PER_UNIT);
645 insn = emit_move_insn (reg, pic_ref);
647 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
648 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
652 else if (GET_CODE (orig) == CONST)
656 if (GET_CODE (XEXP (orig, 0)) == PLUS
657 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
661 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS);
663 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
664 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
665 base == reg ? 0 : reg);
667 if (GET_CODE (orig) == CONST_INT)
669 if (INT_14_BITS (orig))
670 return plus_constant (base, INTVAL (orig));
671 orig = force_reg (Pmode, orig);
673 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
674 /* Likewise, should we set special REG_NOTEs here? */
680 static GTY(()) rtx gen_tls_tga;
683 gen_tls_get_addr (void)
686 gen_tls_tga = init_one_libfunc ("__tls_get_addr");
691 hppa_tls_call (rtx arg)
695 ret = gen_reg_rtx (Pmode);
696 emit_library_call_value (gen_tls_get_addr (), ret,
697 LCT_CONST, Pmode, 1, arg, Pmode);
703 legitimize_tls_address (rtx addr)
705 rtx ret, insn, tmp, t1, t2, tp;
706 enum tls_model model = SYMBOL_REF_TLS_MODEL (addr);
710 case TLS_MODEL_GLOBAL_DYNAMIC:
711 tmp = gen_reg_rtx (Pmode);
712 emit_insn (gen_tgd_load (tmp, addr));
713 ret = hppa_tls_call (tmp);
716 case TLS_MODEL_LOCAL_DYNAMIC:
717 ret = gen_reg_rtx (Pmode);
718 tmp = gen_reg_rtx (Pmode);
720 emit_insn (gen_tld_load (tmp, addr));
721 t1 = hppa_tls_call (tmp);
724 t2 = gen_reg_rtx (Pmode);
725 emit_libcall_block (insn, t2, t1,
726 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx),
728 emit_insn (gen_tld_offset_load (ret, addr, t2));
731 case TLS_MODEL_INITIAL_EXEC:
732 tp = gen_reg_rtx (Pmode);
733 tmp = gen_reg_rtx (Pmode);
734 ret = gen_reg_rtx (Pmode);
735 emit_insn (gen_tp_load (tp));
736 emit_insn (gen_tie_load (tmp, addr));
737 emit_move_insn (ret, gen_rtx_PLUS (Pmode, tp, tmp));
740 case TLS_MODEL_LOCAL_EXEC:
741 tp = gen_reg_rtx (Pmode);
742 ret = gen_reg_rtx (Pmode);
743 emit_insn (gen_tp_load (tp));
744 emit_insn (gen_tle_load (ret, addr, tp));
754 /* Try machine-dependent ways of modifying an illegitimate address
755 to be legitimate. If we find one, return the new, valid address.
756 This macro is used in only one place: `memory_address' in explow.c.
758 OLDX is the address as it was before break_out_memory_refs was called.
759 In some cases it is useful to look at this to decide what needs to be done.
761 MODE and WIN are passed so that this macro can use
762 GO_IF_LEGITIMATE_ADDRESS.
764 It is always safe for this macro to do nothing. It exists to recognize
765 opportunities to optimize the output.
767 For the PA, transform:
769 memory(X + <large int>)
773 if (<large int> & mask) >= 16
774 Y = (<large int> & ~mask) + mask + 1 Round up.
776 Y = (<large int> & ~mask) Round down.
778 memory (Z + (<large int> - Y));
780 This is for CSE to find several similar references, and only use one Z.
782 X can either be a SYMBOL_REF or REG, but because combine cannot
783 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
784 D will not fit in 14 bits.
786 MODE_FLOAT references allow displacements which fit in 5 bits, so use
789 MODE_INT references allow displacements which fit in 14 bits, so use
792 This relies on the fact that most mode MODE_FLOAT references will use FP
793 registers and most mode MODE_INT references will use integer registers.
794 (In the rare case of an FP register used in an integer MODE, we depend
795 on secondary reloads to clean things up.)
798 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
799 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
800 addressing modes to be used).
802 Put X and Z into registers. Then put the entire expression into
806 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
807 enum machine_mode mode)
811 /* We need to canonicalize the order of operands in unscaled indexed
812 addresses since the code that checks if an address is valid doesn't
813 always try both orders. */
814 if (!TARGET_NO_SPACE_REGS
815 && GET_CODE (x) == PLUS
816 && GET_MODE (x) == Pmode
817 && REG_P (XEXP (x, 0))
818 && REG_P (XEXP (x, 1))
819 && REG_POINTER (XEXP (x, 0))
820 && !REG_POINTER (XEXP (x, 1)))
821 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
823 if (PA_SYMBOL_REF_TLS_P (x))
824 return legitimize_tls_address (x);
826 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
828 /* Strip off CONST. */
829 if (GET_CODE (x) == CONST)
832 /* Special case. Get the SYMBOL_REF into a register and use indexing.
833 That should always be safe. */
834 if (GET_CODE (x) == PLUS
835 && GET_CODE (XEXP (x, 0)) == REG
836 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
838 rtx reg = force_reg (Pmode, XEXP (x, 1));
839 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
842 /* Note we must reject symbols which represent function addresses
843 since the assembler/linker can't handle arithmetic on plabels. */
844 if (GET_CODE (x) == PLUS
845 && GET_CODE (XEXP (x, 1)) == CONST_INT
846 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
847 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
848 || GET_CODE (XEXP (x, 0)) == REG))
850 rtx int_part, ptr_reg;
852 int offset = INTVAL (XEXP (x, 1));
855 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
856 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
858 /* Choose which way to round the offset. Round up if we
859 are >= halfway to the next boundary. */
860 if ((offset & mask) >= ((mask + 1) / 2))
861 newoffset = (offset & ~ mask) + mask + 1;
863 newoffset = (offset & ~ mask);
865 /* If the newoffset will not fit in 14 bits (ldo), then
866 handling this would take 4 or 5 instructions (2 to load
867 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
868 add the new offset and the SYMBOL_REF.) Combine can
869 not handle 4->2 or 5->2 combinations, so do not create
871 if (! VAL_14_BITS_P (newoffset)
872 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
874 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
877 gen_rtx_HIGH (Pmode, const_part));
880 gen_rtx_LO_SUM (Pmode,
881 tmp_reg, const_part));
885 if (! VAL_14_BITS_P (newoffset))
886 int_part = force_reg (Pmode, GEN_INT (newoffset));
888 int_part = GEN_INT (newoffset);
890 ptr_reg = force_reg (Pmode,
892 force_reg (Pmode, XEXP (x, 0)),
895 return plus_constant (ptr_reg, offset - newoffset);
898 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
900 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
901 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
902 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
903 && (OBJECT_P (XEXP (x, 1))
904 || GET_CODE (XEXP (x, 1)) == SUBREG)
905 && GET_CODE (XEXP (x, 1)) != CONST)
907 int val = INTVAL (XEXP (XEXP (x, 0), 1));
911 if (GET_CODE (reg1) != REG)
912 reg1 = force_reg (Pmode, force_operand (reg1, 0));
914 reg2 = XEXP (XEXP (x, 0), 0);
915 if (GET_CODE (reg2) != REG)
916 reg2 = force_reg (Pmode, force_operand (reg2, 0));
918 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
925 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
927 Only do so for floating point modes since this is more speculative
928 and we lose if it's an integer store. */
929 if (GET_CODE (x) == PLUS
930 && GET_CODE (XEXP (x, 0)) == PLUS
931 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
932 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
933 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
934 && (mode == SFmode || mode == DFmode))
937 /* First, try and figure out what to use as a base register. */
938 rtx reg1, reg2, base, idx, orig_base;
940 reg1 = XEXP (XEXP (x, 0), 1);
945 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
946 then emit_move_sequence will turn on REG_POINTER so we'll know
947 it's a base register below. */
948 if (GET_CODE (reg1) != REG)
949 reg1 = force_reg (Pmode, force_operand (reg1, 0));
951 if (GET_CODE (reg2) != REG)
952 reg2 = force_reg (Pmode, force_operand (reg2, 0));
954 /* Figure out what the base and index are. */
956 if (GET_CODE (reg1) == REG
957 && REG_POINTER (reg1))
960 orig_base = XEXP (XEXP (x, 0), 1);
961 idx = gen_rtx_PLUS (Pmode,
963 XEXP (XEXP (XEXP (x, 0), 0), 0),
964 XEXP (XEXP (XEXP (x, 0), 0), 1)),
967 else if (GET_CODE (reg2) == REG
968 && REG_POINTER (reg2))
971 orig_base = XEXP (x, 1);
978 /* If the index adds a large constant, try to scale the
979 constant so that it can be loaded with only one insn. */
980 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
981 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
982 / INTVAL (XEXP (XEXP (idx, 0), 1)))
983 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
985 /* Divide the CONST_INT by the scale factor, then add it to A. */
986 int val = INTVAL (XEXP (idx, 1));
988 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
989 reg1 = XEXP (XEXP (idx, 0), 0);
990 if (GET_CODE (reg1) != REG)
991 reg1 = force_reg (Pmode, force_operand (reg1, 0));
993 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
995 /* We can now generate a simple scaled indexed address. */
998 (Pmode, gen_rtx_PLUS (Pmode,
999 gen_rtx_MULT (Pmode, reg1,
1000 XEXP (XEXP (idx, 0), 1)),
1004 /* If B + C is still a valid base register, then add them. */
1005 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1006 && INTVAL (XEXP (idx, 1)) <= 4096
1007 && INTVAL (XEXP (idx, 1)) >= -4096)
1009 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1012 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1014 reg2 = XEXP (XEXP (idx, 0), 0);
1015 if (GET_CODE (reg2) != CONST_INT)
1016 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1018 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1019 gen_rtx_MULT (Pmode,
1025 /* Get the index into a register, then add the base + index and
1026 return a register holding the result. */
1028 /* First get A into a register. */
1029 reg1 = XEXP (XEXP (idx, 0), 0);
1030 if (GET_CODE (reg1) != REG)
1031 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1033 /* And get B into a register. */
1034 reg2 = XEXP (idx, 1);
1035 if (GET_CODE (reg2) != REG)
1036 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1038 reg1 = force_reg (Pmode,
1039 gen_rtx_PLUS (Pmode,
1040 gen_rtx_MULT (Pmode, reg1,
1041 XEXP (XEXP (idx, 0), 1)),
1044 /* Add the result to our base register and return. */
1045 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1049 /* Uh-oh. We might have an address for x[n-100000]. This needs
1050 special handling to avoid creating an indexed memory address
1051 with x-100000 as the base.
1053 If the constant part is small enough, then it's still safe because
1054 there is a guard page at the beginning and end of the data segment.
1056 Scaled references are common enough that we want to try and rearrange the
1057 terms so that we can use indexing for these addresses too. Only
1058 do the optimization for floatint point modes. */
1060 if (GET_CODE (x) == PLUS
1061 && symbolic_expression_p (XEXP (x, 1)))
1063 /* Ugly. We modify things here so that the address offset specified
1064 by the index expression is computed first, then added to x to form
1065 the entire address. */
1067 rtx regx1, regx2, regy1, regy2, y;
1069 /* Strip off any CONST. */
1071 if (GET_CODE (y) == CONST)
1074 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1076 /* See if this looks like
1077 (plus (mult (reg) (shadd_const))
1078 (const (plus (symbol_ref) (const_int))))
1080 Where const_int is small. In that case the const
1081 expression is a valid pointer for indexing.
1083 If const_int is big, but can be divided evenly by shadd_const
1084 and added to (reg). This allows more scaled indexed addresses. */
1085 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1086 && GET_CODE (XEXP (x, 0)) == MULT
1087 && GET_CODE (XEXP (y, 1)) == CONST_INT
1088 && INTVAL (XEXP (y, 1)) >= -4096
1089 && INTVAL (XEXP (y, 1)) <= 4095
1090 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1091 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1093 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1097 if (GET_CODE (reg1) != REG)
1098 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1100 reg2 = XEXP (XEXP (x, 0), 0);
1101 if (GET_CODE (reg2) != REG)
1102 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1104 return force_reg (Pmode,
1105 gen_rtx_PLUS (Pmode,
1106 gen_rtx_MULT (Pmode,
1111 else if ((mode == DFmode || mode == SFmode)
1112 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1113 && GET_CODE (XEXP (x, 0)) == MULT
1114 && GET_CODE (XEXP (y, 1)) == CONST_INT
1115 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1116 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1117 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1120 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1121 / INTVAL (XEXP (XEXP (x, 0), 1))));
1122 regx2 = XEXP (XEXP (x, 0), 0);
1123 if (GET_CODE (regx2) != REG)
1124 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1125 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1129 gen_rtx_PLUS (Pmode,
1130 gen_rtx_MULT (Pmode, regx2,
1131 XEXP (XEXP (x, 0), 1)),
1132 force_reg (Pmode, XEXP (y, 0))));
1134 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1135 && INTVAL (XEXP (y, 1)) >= -4096
1136 && INTVAL (XEXP (y, 1)) <= 4095)
1138 /* This is safe because of the guard page at the
1139 beginning and end of the data space. Just
1140 return the original address. */
1145 /* Doesn't look like one we can optimize. */
1146 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1147 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1148 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1149 regx1 = force_reg (Pmode,
1150 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1152 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1160 /* For the HPPA, REG and REG+CONST is cost 0
1161 and addresses involving symbolic constants are cost 2.
1163 PIC addresses are very expensive.
1165 It is no coincidence that this has the same structure
1166 as GO_IF_LEGITIMATE_ADDRESS. */
1169 hppa_address_cost (rtx X)
1171 switch (GET_CODE (X))
1184 /* Compute a (partial) cost for rtx X. Return true if the complete
1185 cost has been computed, and false if subexpressions should be
1186 scanned. In either case, *TOTAL contains the cost result. */
1189 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1194 if (INTVAL (x) == 0)
1196 else if (INT_14_BITS (x))
1213 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1214 && outer_code != SET)
1221 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1222 *total = COSTS_N_INSNS (3);
1223 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1224 *total = COSTS_N_INSNS (8);
1226 *total = COSTS_N_INSNS (20);
1230 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1232 *total = COSTS_N_INSNS (14);
1240 *total = COSTS_N_INSNS (60);
1243 case PLUS: /* this includes shNadd insns */
1245 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1246 *total = COSTS_N_INSNS (3);
1248 *total = COSTS_N_INSNS (1);
1254 *total = COSTS_N_INSNS (1);
1262 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1263 new rtx with the correct mode. */
1265 force_mode (enum machine_mode mode, rtx orig)
1267 if (mode == GET_MODE (orig))
1270 gcc_assert (REGNO (orig) < FIRST_PSEUDO_REGISTER);
1272 return gen_rtx_REG (mode, REGNO (orig));
1275 /* Return 1 if *X is a thread-local symbol. */
1278 pa_tls_symbol_ref_1 (rtx *x, void *data ATTRIBUTE_UNUSED)
1280 return PA_SYMBOL_REF_TLS_P (*x);
1283 /* Return 1 if X contains a thread-local symbol. */
1286 pa_tls_referenced_p (rtx x)
1288 if (!TARGET_HAVE_TLS)
1291 return for_each_rtx (&x, &pa_tls_symbol_ref_1, 0);
1294 /* Emit insns to move operands[1] into operands[0].
1296 Return 1 if we have written out everything that needs to be done to
1297 do the move. Otherwise, return 0 and the caller will emit the move
1300 Note SCRATCH_REG may not be in the proper mode depending on how it
1301 will be used. This routine is responsible for creating a new copy
1302 of SCRATCH_REG in the proper mode. */
1305 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1307 register rtx operand0 = operands[0];
1308 register rtx operand1 = operands[1];
1311 /* We can only handle indexed addresses in the destination operand
1312 of floating point stores. Thus, we need to break out indexed
1313 addresses from the destination operand. */
1314 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1316 /* This is only safe up to the beginning of life analysis. */
1317 gcc_assert (!no_new_pseudos);
1319 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1320 operand0 = replace_equiv_address (operand0, tem);
1323 /* On targets with non-equivalent space registers, break out unscaled
1324 indexed addresses from the source operand before the final CSE.
1325 We have to do this because the REG_POINTER flag is not correctly
1326 carried through various optimization passes and CSE may substitute
1327 a pseudo without the pointer set for one with the pointer set. As
1328 a result, we loose various opportunities to create insns with
1329 unscaled indexed addresses. */
1330 if (!TARGET_NO_SPACE_REGS
1331 && !cse_not_expected
1332 && GET_CODE (operand1) == MEM
1333 && GET_CODE (XEXP (operand1, 0)) == PLUS
1334 && REG_P (XEXP (XEXP (operand1, 0), 0))
1335 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1337 = replace_equiv_address (operand1,
1338 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1341 && reload_in_progress && GET_CODE (operand0) == REG
1342 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1343 operand0 = reg_equiv_mem[REGNO (operand0)];
1344 else if (scratch_reg
1345 && reload_in_progress && GET_CODE (operand0) == SUBREG
1346 && GET_CODE (SUBREG_REG (operand0)) == REG
1347 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1349 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1350 the code which tracks sets/uses for delete_output_reload. */
1351 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1352 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1353 SUBREG_BYTE (operand0));
1354 operand0 = alter_subreg (&temp);
1358 && reload_in_progress && GET_CODE (operand1) == REG
1359 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1360 operand1 = reg_equiv_mem[REGNO (operand1)];
1361 else if (scratch_reg
1362 && reload_in_progress && GET_CODE (operand1) == SUBREG
1363 && GET_CODE (SUBREG_REG (operand1)) == REG
1364 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1366 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1367 the code which tracks sets/uses for delete_output_reload. */
1368 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1369 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1370 SUBREG_BYTE (operand1));
1371 operand1 = alter_subreg (&temp);
1374 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1375 && ((tem = find_replacement (&XEXP (operand0, 0)))
1376 != XEXP (operand0, 0)))
1377 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1379 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1380 && ((tem = find_replacement (&XEXP (operand1, 0)))
1381 != XEXP (operand1, 0)))
1382 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1384 /* Handle secondary reloads for loads/stores of FP registers from
1385 REG+D addresses where D does not fit in 5 or 14 bits, including
1386 (subreg (mem (addr))) cases. */
1388 && fp_reg_operand (operand0, mode)
1389 && ((GET_CODE (operand1) == MEM
1390 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1391 XEXP (operand1, 0)))
1392 || ((GET_CODE (operand1) == SUBREG
1393 && GET_CODE (XEXP (operand1, 0)) == MEM
1394 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1396 XEXP (XEXP (operand1, 0), 0))))))
1398 if (GET_CODE (operand1) == SUBREG)
1399 operand1 = XEXP (operand1, 0);
1401 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1402 it in WORD_MODE regardless of what mode it was originally given
1404 scratch_reg = force_mode (word_mode, scratch_reg);
1406 /* D might not fit in 14 bits either; for such cases load D into
1408 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1410 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1411 emit_move_insn (scratch_reg,
1412 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1414 XEXP (XEXP (operand1, 0), 0),
1418 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1419 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1420 gen_rtx_MEM (mode, scratch_reg)));
1423 else if (scratch_reg
1424 && fp_reg_operand (operand1, mode)
1425 && ((GET_CODE (operand0) == MEM
1426 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1428 XEXP (operand0, 0)))
1429 || ((GET_CODE (operand0) == SUBREG)
1430 && GET_CODE (XEXP (operand0, 0)) == MEM
1431 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1433 XEXP (XEXP (operand0, 0), 0)))))
1435 if (GET_CODE (operand0) == SUBREG)
1436 operand0 = XEXP (operand0, 0);
1438 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1439 it in WORD_MODE regardless of what mode it was originally given
1441 scratch_reg = force_mode (word_mode, scratch_reg);
1443 /* D might not fit in 14 bits either; for such cases load D into
1445 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1447 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1448 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1451 XEXP (XEXP (operand0, 0),
1456 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1457 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1461 /* Handle secondary reloads for loads of FP registers from constant
1462 expressions by forcing the constant into memory.
1464 Use scratch_reg to hold the address of the memory location.
1466 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1467 NO_REGS when presented with a const_int and a register class
1468 containing only FP registers. Doing so unfortunately creates
1469 more problems than it solves. Fix this for 2.5. */
1470 else if (scratch_reg
1471 && CONSTANT_P (operand1)
1472 && fp_reg_operand (operand0, mode))
1476 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1477 it in WORD_MODE regardless of what mode it was originally given
1479 scratch_reg = force_mode (word_mode, scratch_reg);
1481 /* Force the constant into memory and put the address of the
1482 memory location into scratch_reg. */
1483 xoperands[0] = scratch_reg;
1484 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1485 emit_move_sequence (xoperands, Pmode, 0);
1487 /* Now load the destination register. */
1488 emit_insn (gen_rtx_SET (mode, operand0,
1489 gen_rtx_MEM (mode, scratch_reg)));
1492 /* Handle secondary reloads for SAR. These occur when trying to load
1493 the SAR from memory, FP register, or with a constant. */
1494 else if (scratch_reg
1495 && GET_CODE (operand0) == REG
1496 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1497 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1498 && (GET_CODE (operand1) == MEM
1499 || GET_CODE (operand1) == CONST_INT
1500 || (GET_CODE (operand1) == REG
1501 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1503 /* D might not fit in 14 bits either; for such cases load D into
1505 if (GET_CODE (operand1) == MEM
1506 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1508 /* We are reloading the address into the scratch register, so we
1509 want to make sure the scratch register is a full register. */
1510 scratch_reg = force_mode (word_mode, scratch_reg);
1512 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1513 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1516 XEXP (XEXP (operand1, 0),
1520 /* Now we are going to load the scratch register from memory,
1521 we want to load it in the same width as the original MEM,
1522 which must be the same as the width of the ultimate destination,
1524 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1526 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1531 /* We want to load the scratch register using the same mode as
1532 the ultimate destination. */
1533 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1535 emit_move_insn (scratch_reg, operand1);
1538 /* And emit the insn to set the ultimate destination. We know that
1539 the scratch register has the same mode as the destination at this
1541 emit_move_insn (operand0, scratch_reg);
1544 /* Handle the most common case: storing into a register. */
1545 else if (register_operand (operand0, mode))
1547 if (register_operand (operand1, mode)
1548 || (GET_CODE (operand1) == CONST_INT
1549 && cint_ok_for_move (INTVAL (operand1)))
1550 || (operand1 == CONST0_RTX (mode))
1551 || (GET_CODE (operand1) == HIGH
1552 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1553 /* Only `general_operands' can come here, so MEM is ok. */
1554 || GET_CODE (operand1) == MEM)
1556 /* Various sets are created during RTL generation which don't
1557 have the REG_POINTER flag correctly set. After the CSE pass,
1558 instruction recognition can fail if we don't consistently
1559 set this flag when performing register copies. This should
1560 also improve the opportunities for creating insns that use
1561 unscaled indexing. */
1562 if (REG_P (operand0) && REG_P (operand1))
1564 if (REG_POINTER (operand1)
1565 && !REG_POINTER (operand0)
1566 && !HARD_REGISTER_P (operand0))
1567 copy_reg_pointer (operand0, operand1);
1568 else if (REG_POINTER (operand0)
1569 && !REG_POINTER (operand1)
1570 && !HARD_REGISTER_P (operand1))
1571 copy_reg_pointer (operand1, operand0);
1574 /* When MEMs are broken out, the REG_POINTER flag doesn't
1575 get set. In some cases, we can set the REG_POINTER flag
1576 from the declaration for the MEM. */
1577 if (REG_P (operand0)
1578 && GET_CODE (operand1) == MEM
1579 && !REG_POINTER (operand0))
1581 tree decl = MEM_EXPR (operand1);
1583 /* Set the register pointer flag and register alignment
1584 if the declaration for this memory reference is a
1585 pointer type. Fortran indirect argument references
1588 && !(flag_argument_noalias > 1
1589 && TREE_CODE (decl) == INDIRECT_REF
1590 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1594 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1596 if (TREE_CODE (decl) == COMPONENT_REF)
1597 decl = TREE_OPERAND (decl, 1);
1599 type = TREE_TYPE (decl);
1600 if (TREE_CODE (type) == ARRAY_TYPE)
1601 type = get_inner_array_type (type);
1603 if (POINTER_TYPE_P (type))
1607 type = TREE_TYPE (type);
1608 /* Using TYPE_ALIGN_OK is rather conservative as
1609 only the ada frontend actually sets it. */
1610 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1612 mark_reg_pointer (operand0, align);
1617 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1621 else if (GET_CODE (operand0) == MEM)
1623 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1624 && !(reload_in_progress || reload_completed))
1626 rtx temp = gen_reg_rtx (DFmode);
1628 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1629 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1632 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1634 /* Run this case quickly. */
1635 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1638 if (! (reload_in_progress || reload_completed))
1640 operands[0] = validize_mem (operand0);
1641 operands[1] = operand1 = force_reg (mode, operand1);
1645 /* Simplify the source if we need to.
1646 Note we do have to handle function labels here, even though we do
1647 not consider them legitimate constants. Loop optimizations can
1648 call the emit_move_xxx with one as a source. */
1649 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1650 || function_label_operand (operand1, mode)
1651 || (GET_CODE (operand1) == HIGH
1652 && symbolic_operand (XEXP (operand1, 0), mode)))
1656 if (GET_CODE (operand1) == HIGH)
1659 operand1 = XEXP (operand1, 0);
1661 if (symbolic_operand (operand1, mode))
1663 /* Argh. The assembler and linker can't handle arithmetic
1666 So we force the plabel into memory, load operand0 from
1667 the memory location, then add in the constant part. */
1668 if ((GET_CODE (operand1) == CONST
1669 && GET_CODE (XEXP (operand1, 0)) == PLUS
1670 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1671 || function_label_operand (operand1, mode))
1673 rtx temp, const_part;
1675 /* Figure out what (if any) scratch register to use. */
1676 if (reload_in_progress || reload_completed)
1678 scratch_reg = scratch_reg ? scratch_reg : operand0;
1679 /* SCRATCH_REG will hold an address and maybe the actual
1680 data. We want it in WORD_MODE regardless of what mode it
1681 was originally given to us. */
1682 scratch_reg = force_mode (word_mode, scratch_reg);
1685 scratch_reg = gen_reg_rtx (Pmode);
1687 if (GET_CODE (operand1) == CONST)
1689 /* Save away the constant part of the expression. */
1690 const_part = XEXP (XEXP (operand1, 0), 1);
1691 gcc_assert (GET_CODE (const_part) == CONST_INT);
1693 /* Force the function label into memory. */
1694 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1698 /* No constant part. */
1699 const_part = NULL_RTX;
1701 /* Force the function label into memory. */
1702 temp = force_const_mem (mode, operand1);
1706 /* Get the address of the memory location. PIC-ify it if
1708 temp = XEXP (temp, 0);
1710 temp = legitimize_pic_address (temp, mode, scratch_reg);
1712 /* Put the address of the memory location into our destination
1715 emit_move_sequence (operands, mode, scratch_reg);
1717 /* Now load from the memory location into our destination
1719 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1720 emit_move_sequence (operands, mode, scratch_reg);
1722 /* And add back in the constant part. */
1723 if (const_part != NULL_RTX)
1724 expand_inc (operand0, const_part);
1733 if (reload_in_progress || reload_completed)
1735 temp = scratch_reg ? scratch_reg : operand0;
1736 /* TEMP will hold an address and maybe the actual
1737 data. We want it in WORD_MODE regardless of what mode it
1738 was originally given to us. */
1739 temp = force_mode (word_mode, temp);
1742 temp = gen_reg_rtx (Pmode);
1744 /* (const (plus (symbol) (const_int))) must be forced to
1745 memory during/after reload if the const_int will not fit
1747 if (GET_CODE (operand1) == CONST
1748 && GET_CODE (XEXP (operand1, 0)) == PLUS
1749 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1750 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1751 && (reload_completed || reload_in_progress)
1754 operands[1] = force_const_mem (mode, operand1);
1755 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1757 operands[1] = gen_rtx_MEM (mode, operands[1]);
1758 emit_move_sequence (operands, mode, temp);
1762 operands[1] = legitimize_pic_address (operand1, mode, temp);
1763 if (REG_P (operand0) && REG_P (operands[1]))
1764 copy_reg_pointer (operand0, operands[1]);
1765 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1768 /* On the HPPA, references to data space are supposed to use dp,
1769 register 27, but showing it in the RTL inhibits various cse
1770 and loop optimizations. */
1775 if (reload_in_progress || reload_completed)
1777 temp = scratch_reg ? scratch_reg : operand0;
1778 /* TEMP will hold an address and maybe the actual
1779 data. We want it in WORD_MODE regardless of what mode it
1780 was originally given to us. */
1781 temp = force_mode (word_mode, temp);
1784 temp = gen_reg_rtx (mode);
1786 /* Loading a SYMBOL_REF into a register makes that register
1787 safe to be used as the base in an indexed address.
1789 Don't mark hard registers though. That loses. */
1790 if (GET_CODE (operand0) == REG
1791 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1792 mark_reg_pointer (operand0, BITS_PER_UNIT);
1793 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1794 mark_reg_pointer (temp, BITS_PER_UNIT);
1797 set = gen_rtx_SET (mode, operand0, temp);
1799 set = gen_rtx_SET (VOIDmode,
1801 gen_rtx_LO_SUM (mode, temp, operand1));
1803 emit_insn (gen_rtx_SET (VOIDmode,
1805 gen_rtx_HIGH (mode, operand1)));
1811 else if (pa_tls_referenced_p (operand1))
1816 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS)
1818 addend = XEXP (XEXP (tmp, 0), 1);
1819 tmp = XEXP (XEXP (tmp, 0), 0);
1822 gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
1823 tmp = legitimize_tls_address (tmp);
1826 tmp = gen_rtx_PLUS (mode, tmp, addend);
1827 tmp = force_operand (tmp, operands[0]);
1831 else if (GET_CODE (operand1) != CONST_INT
1832 || !cint_ok_for_move (INTVAL (operand1)))
1836 HOST_WIDE_INT value = 0;
1837 HOST_WIDE_INT insv = 0;
1840 if (GET_CODE (operand1) == CONST_INT)
1841 value = INTVAL (operand1);
1844 && GET_CODE (operand1) == CONST_INT
1845 && HOST_BITS_PER_WIDE_INT > 32
1846 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1850 /* Extract the low order 32 bits of the value and sign extend.
1851 If the new value is the same as the original value, we can
1852 can use the original value as-is. If the new value is
1853 different, we use it and insert the most-significant 32-bits
1854 of the original value into the final result. */
1855 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
1856 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1859 #if HOST_BITS_PER_WIDE_INT > 32
1860 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
1864 operand1 = GEN_INT (nval);
1868 if (reload_in_progress || reload_completed)
1869 temp = scratch_reg ? scratch_reg : operand0;
1871 temp = gen_reg_rtx (mode);
1873 /* We don't directly split DImode constants on 32-bit targets
1874 because PLUS uses an 11-bit immediate and the insn sequence
1875 generated is not as efficient as the one using HIGH/LO_SUM. */
1876 if (GET_CODE (operand1) == CONST_INT
1877 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
1880 /* Directly break constant into high and low parts. This
1881 provides better optimization opportunities because various
1882 passes recognize constants split with PLUS but not LO_SUM.
1883 We use a 14-bit signed low part except when the addition
1884 of 0x4000 to the high part might change the sign of the
1886 HOST_WIDE_INT low = value & 0x3fff;
1887 HOST_WIDE_INT high = value & ~ 0x3fff;
1891 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1899 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1900 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1904 emit_insn (gen_rtx_SET (VOIDmode, temp,
1905 gen_rtx_HIGH (mode, operand1)));
1906 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1909 insn = emit_move_insn (operands[0], operands[1]);
1911 /* Now insert the most significant 32 bits of the value
1912 into the register. When we don't have a second register
1913 available, it could take up to nine instructions to load
1914 a 64-bit integer constant. Prior to reload, we force
1915 constants that would take more than three instructions
1916 to load to the constant pool. During and after reload,
1917 we have to handle all possible values. */
1920 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
1921 register and the value to be inserted is outside the
1922 range that can be loaded with three depdi instructions. */
1923 if (temp != operand0 && (insv >= 16384 || insv < -16384))
1925 operand1 = GEN_INT (insv);
1927 emit_insn (gen_rtx_SET (VOIDmode, temp,
1928 gen_rtx_HIGH (mode, operand1)));
1929 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
1930 emit_insn (gen_insv (operand0, GEN_INT (32),
1935 int len = 5, pos = 27;
1937 /* Insert the bits using the depdi instruction. */
1940 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
1941 HOST_WIDE_INT sign = v5 < 0;
1943 /* Left extend the insertion. */
1944 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
1945 while (pos > 0 && (insv & 1) == sign)
1947 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
1952 emit_insn (gen_insv (operand0, GEN_INT (len),
1953 GEN_INT (pos), GEN_INT (v5)));
1955 len = pos > 0 && pos < 5 ? pos : 5;
1962 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
1967 /* Now have insn-emit do whatever it normally does. */
1971 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1972 it will need a link/runtime reloc). */
1975 reloc_needed (tree exp)
1979 switch (TREE_CODE (exp))
1986 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1987 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1992 case NON_LVALUE_EXPR:
1993 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1999 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2000 if (TREE_VALUE (link) != 0)
2001 reloc |= reloc_needed (TREE_VALUE (link));
2014 /* Does operand (which is a symbolic_operand) live in text space?
2015 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2019 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2021 if (GET_CODE (operand) == CONST)
2022 operand = XEXP (XEXP (operand, 0), 0);
2025 if (GET_CODE (operand) == SYMBOL_REF)
2026 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2030 if (GET_CODE (operand) == SYMBOL_REF)
2031 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2037 /* Return the best assembler insn template
2038 for moving operands[1] into operands[0] as a fullword. */
2040 singlemove_string (rtx *operands)
2042 HOST_WIDE_INT intval;
2044 if (GET_CODE (operands[0]) == MEM)
2045 return "stw %r1,%0";
2046 if (GET_CODE (operands[1]) == MEM)
2048 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2053 gcc_assert (GET_MODE (operands[1]) == SFmode);
2055 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2057 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2058 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2060 operands[1] = GEN_INT (i);
2061 /* Fall through to CONST_INT case. */
2063 if (GET_CODE (operands[1]) == CONST_INT)
2065 intval = INTVAL (operands[1]);
2067 if (VAL_14_BITS_P (intval))
2069 else if ((intval & 0x7ff) == 0)
2070 return "ldil L'%1,%0";
2071 else if (zdepi_cint_p (intval))
2072 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2074 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2076 return "copy %1,%0";
2080 /* Compute position (in OP[1]) and width (in OP[2])
2081 useful for copying IMM to a register using the zdepi
2082 instructions. Store the immediate value to insert in OP[0]. */
2084 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2088 /* Find the least significant set bit in IMM. */
2089 for (lsb = 0; lsb < 32; lsb++)
2096 /* Choose variants based on *sign* of the 5-bit field. */
2097 if ((imm & 0x10) == 0)
2098 len = (lsb <= 28) ? 4 : 32 - lsb;
2101 /* Find the width of the bitstring in IMM. */
2102 for (len = 5; len < 32; len++)
2104 if ((imm & (1 << len)) == 0)
2108 /* Sign extend IMM as a 5-bit value. */
2109 imm = (imm & 0xf) - 0x10;
2117 /* Compute position (in OP[1]) and width (in OP[2])
2118 useful for copying IMM to a register using the depdi,z
2119 instructions. Store the immediate value to insert in OP[0]. */
2121 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2123 HOST_WIDE_INT lsb, len;
2125 /* Find the least significant set bit in IMM. */
2126 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2133 /* Choose variants based on *sign* of the 5-bit field. */
2134 if ((imm & 0x10) == 0)
2135 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2136 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2139 /* Find the width of the bitstring in IMM. */
2140 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2142 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2146 /* Sign extend IMM as a 5-bit value. */
2147 imm = (imm & 0xf) - 0x10;
2155 /* Output assembler code to perform a doubleword move insn
2156 with operands OPERANDS. */
2159 output_move_double (rtx *operands)
2161 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2163 rtx addreg0 = 0, addreg1 = 0;
2165 /* First classify both operands. */
2167 if (REG_P (operands[0]))
2169 else if (offsettable_memref_p (operands[0]))
2171 else if (GET_CODE (operands[0]) == MEM)
2176 if (REG_P (operands[1]))
2178 else if (CONSTANT_P (operands[1]))
2180 else if (offsettable_memref_p (operands[1]))
2182 else if (GET_CODE (operands[1]) == MEM)
2187 /* Check for the cases that the operand constraints are not
2188 supposed to allow to happen. */
2189 gcc_assert (optype0 == REGOP || optype1 == REGOP);
2191 /* Handle auto decrementing and incrementing loads and stores
2192 specifically, since the structure of the function doesn't work
2193 for them without major modification. Do it better when we learn
2194 this port about the general inc/dec addressing of PA.
2195 (This was written by tege. Chide him if it doesn't work.) */
2197 if (optype0 == MEMOP)
2199 /* We have to output the address syntax ourselves, since print_operand
2200 doesn't deal with the addresses we want to use. Fix this later. */
2202 rtx addr = XEXP (operands[0], 0);
2203 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2205 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2207 operands[0] = XEXP (addr, 0);
2208 gcc_assert (GET_CODE (operands[1]) == REG
2209 && GET_CODE (operands[0]) == REG);
2211 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2213 /* No overlap between high target register and address
2214 register. (We do this in a non-obvious way to
2215 save a register file writeback) */
2216 if (GET_CODE (addr) == POST_INC)
2217 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2218 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2220 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2222 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2224 operands[0] = XEXP (addr, 0);
2225 gcc_assert (GET_CODE (operands[1]) == REG
2226 && GET_CODE (operands[0]) == REG);
2228 gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
2229 /* No overlap between high target register and address
2230 register. (We do this in a non-obvious way to save a
2231 register file writeback) */
2232 if (GET_CODE (addr) == PRE_INC)
2233 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2234 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2237 if (optype1 == MEMOP)
2239 /* We have to output the address syntax ourselves, since print_operand
2240 doesn't deal with the addresses we want to use. Fix this later. */
2242 rtx addr = XEXP (operands[1], 0);
2243 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2245 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2247 operands[1] = XEXP (addr, 0);
2248 gcc_assert (GET_CODE (operands[0]) == REG
2249 && GET_CODE (operands[1]) == REG);
2251 if (!reg_overlap_mentioned_p (high_reg, addr))
2253 /* No overlap between high target register and address
2254 register. (We do this in a non-obvious way to
2255 save a register file writeback) */
2256 if (GET_CODE (addr) == POST_INC)
2257 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2258 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2262 /* This is an undefined situation. We should load into the
2263 address register *and* update that register. Probably
2264 we don't need to handle this at all. */
2265 if (GET_CODE (addr) == POST_INC)
2266 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2267 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2270 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2272 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2274 operands[1] = XEXP (addr, 0);
2275 gcc_assert (GET_CODE (operands[0]) == REG
2276 && GET_CODE (operands[1]) == REG);
2278 if (!reg_overlap_mentioned_p (high_reg, addr))
2280 /* No overlap between high target register and address
2281 register. (We do this in a non-obvious way to
2282 save a register file writeback) */
2283 if (GET_CODE (addr) == PRE_INC)
2284 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2285 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2289 /* This is an undefined situation. We should load into the
2290 address register *and* update that register. Probably
2291 we don't need to handle this at all. */
2292 if (GET_CODE (addr) == PRE_INC)
2293 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2294 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2297 else if (GET_CODE (addr) == PLUS
2298 && GET_CODE (XEXP (addr, 0)) == MULT)
2300 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2302 if (!reg_overlap_mentioned_p (high_reg, addr))
2306 xoperands[0] = high_reg;
2307 xoperands[1] = XEXP (addr, 1);
2308 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2309 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2310 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2312 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2318 xoperands[0] = high_reg;
2319 xoperands[1] = XEXP (addr, 1);
2320 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2321 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2322 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2324 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2329 /* If an operand is an unoffsettable memory ref, find a register
2330 we can increment temporarily to make it refer to the second word. */
2332 if (optype0 == MEMOP)
2333 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2335 if (optype1 == MEMOP)
2336 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2338 /* Ok, we can do one word at a time.
2339 Normally we do the low-numbered word first.
2341 In either case, set up in LATEHALF the operands to use
2342 for the high-numbered word and in some cases alter the
2343 operands in OPERANDS to be suitable for the low-numbered word. */
2345 if (optype0 == REGOP)
2346 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2347 else if (optype0 == OFFSOP)
2348 latehalf[0] = adjust_address (operands[0], SImode, 4);
2350 latehalf[0] = operands[0];
2352 if (optype1 == REGOP)
2353 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2354 else if (optype1 == OFFSOP)
2355 latehalf[1] = adjust_address (operands[1], SImode, 4);
2356 else if (optype1 == CNSTOP)
2357 split_double (operands[1], &operands[1], &latehalf[1]);
2359 latehalf[1] = operands[1];
2361 /* If the first move would clobber the source of the second one,
2362 do them in the other order.
2364 This can happen in two cases:
2366 mem -> register where the first half of the destination register
2367 is the same register used in the memory's address. Reload
2368 can create such insns.
2370 mem in this case will be either register indirect or register
2371 indirect plus a valid offset.
2373 register -> register move where REGNO(dst) == REGNO(src + 1)
2374 someone (Tim/Tege?) claimed this can happen for parameter loads.
2376 Handle mem -> register case first. */
2377 if (optype0 == REGOP
2378 && (optype1 == MEMOP || optype1 == OFFSOP)
2379 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2382 /* Do the late half first. */
2384 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2385 output_asm_insn (singlemove_string (latehalf), latehalf);
2389 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2390 return singlemove_string (operands);
2393 /* Now handle register -> register case. */
2394 if (optype0 == REGOP && optype1 == REGOP
2395 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2397 output_asm_insn (singlemove_string (latehalf), latehalf);
2398 return singlemove_string (operands);
2401 /* Normal case: do the two words, low-numbered first. */
2403 output_asm_insn (singlemove_string (operands), operands);
2405 /* Make any unoffsettable addresses point at high-numbered word. */
2407 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2409 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2412 output_asm_insn (singlemove_string (latehalf), latehalf);
2414 /* Undo the adds we just did. */
2416 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2418 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2424 output_fp_move_double (rtx *operands)
2426 if (FP_REG_P (operands[0]))
2428 if (FP_REG_P (operands[1])
2429 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2430 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2432 output_asm_insn ("fldd%F1 %1,%0", operands);
2434 else if (FP_REG_P (operands[1]))
2436 output_asm_insn ("fstd%F0 %1,%0", operands);
2442 gcc_assert (operands[1] == CONST0_RTX (GET_MODE (operands[0])));
2444 /* This is a pain. You have to be prepared to deal with an
2445 arbitrary address here including pre/post increment/decrement.
2447 so avoid this in the MD. */
2448 gcc_assert (GET_CODE (operands[0]) == REG);
2450 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2451 xoperands[0] = operands[0];
2452 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2457 /* Return a REG that occurs in ADDR with coefficient 1.
2458 ADDR can be effectively incremented by incrementing REG. */
2461 find_addr_reg (rtx addr)
2463 while (GET_CODE (addr) == PLUS)
2465 if (GET_CODE (XEXP (addr, 0)) == REG)
2466 addr = XEXP (addr, 0);
2467 else if (GET_CODE (XEXP (addr, 1)) == REG)
2468 addr = XEXP (addr, 1);
2469 else if (CONSTANT_P (XEXP (addr, 0)))
2470 addr = XEXP (addr, 1);
2471 else if (CONSTANT_P (XEXP (addr, 1)))
2472 addr = XEXP (addr, 0);
2476 gcc_assert (GET_CODE (addr) == REG);
2480 /* Emit code to perform a block move.
2482 OPERANDS[0] is the destination pointer as a REG, clobbered.
2483 OPERANDS[1] is the source pointer as a REG, clobbered.
2484 OPERANDS[2] is a register for temporary storage.
2485 OPERANDS[3] is a register for temporary storage.
2486 OPERANDS[4] is the size as a CONST_INT
2487 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2488 OPERANDS[6] is another temporary register. */
2491 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2493 int align = INTVAL (operands[5]);
2494 unsigned long n_bytes = INTVAL (operands[4]);
2496 /* We can't move more than a word at a time because the PA
2497 has no longer integer move insns. (Could use fp mem ops?) */
2498 if (align > (TARGET_64BIT ? 8 : 4))
2499 align = (TARGET_64BIT ? 8 : 4);
2501 /* Note that we know each loop below will execute at least twice
2502 (else we would have open-coded the copy). */
2506 /* Pre-adjust the loop counter. */
2507 operands[4] = GEN_INT (n_bytes - 16);
2508 output_asm_insn ("ldi %4,%2", operands);
2511 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2512 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2513 output_asm_insn ("std,ma %3,8(%0)", operands);
2514 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2515 output_asm_insn ("std,ma %6,8(%0)", operands);
2517 /* Handle the residual. There could be up to 7 bytes of
2518 residual to copy! */
2519 if (n_bytes % 16 != 0)
2521 operands[4] = GEN_INT (n_bytes % 8);
2522 if (n_bytes % 16 >= 8)
2523 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2524 if (n_bytes % 8 != 0)
2525 output_asm_insn ("ldd 0(%1),%6", operands);
2526 if (n_bytes % 16 >= 8)
2527 output_asm_insn ("std,ma %3,8(%0)", operands);
2528 if (n_bytes % 8 != 0)
2529 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2534 /* Pre-adjust the loop counter. */
2535 operands[4] = GEN_INT (n_bytes - 8);
2536 output_asm_insn ("ldi %4,%2", operands);
2539 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2540 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2541 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2542 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2543 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2545 /* Handle the residual. There could be up to 7 bytes of
2546 residual to copy! */
2547 if (n_bytes % 8 != 0)
2549 operands[4] = GEN_INT (n_bytes % 4);
2550 if (n_bytes % 8 >= 4)
2551 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2552 if (n_bytes % 4 != 0)
2553 output_asm_insn ("ldw 0(%1),%6", operands);
2554 if (n_bytes % 8 >= 4)
2555 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2556 if (n_bytes % 4 != 0)
2557 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2562 /* Pre-adjust the loop counter. */
2563 operands[4] = GEN_INT (n_bytes - 4);
2564 output_asm_insn ("ldi %4,%2", operands);
2567 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2568 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2569 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2570 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2571 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2573 /* Handle the residual. */
2574 if (n_bytes % 4 != 0)
2576 if (n_bytes % 4 >= 2)
2577 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2578 if (n_bytes % 2 != 0)
2579 output_asm_insn ("ldb 0(%1),%6", operands);
2580 if (n_bytes % 4 >= 2)
2581 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2582 if (n_bytes % 2 != 0)
2583 output_asm_insn ("stb %6,0(%0)", operands);
2588 /* Pre-adjust the loop counter. */
2589 operands[4] = GEN_INT (n_bytes - 2);
2590 output_asm_insn ("ldi %4,%2", operands);
2593 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2594 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2595 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2596 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2597 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2599 /* Handle the residual. */
2600 if (n_bytes % 2 != 0)
2602 output_asm_insn ("ldb 0(%1),%3", operands);
2603 output_asm_insn ("stb %3,0(%0)", operands);
2612 /* Count the number of insns necessary to handle this block move.
2614 Basic structure is the same as emit_block_move, except that we
2615 count insns rather than emit them. */
2618 compute_movmem_length (rtx insn)
2620 rtx pat = PATTERN (insn);
2621 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2622 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2623 unsigned int n_insns = 0;
2625 /* We can't move more than four bytes at a time because the PA
2626 has no longer integer move insns. (Could use fp mem ops?) */
2627 if (align > (TARGET_64BIT ? 8 : 4))
2628 align = (TARGET_64BIT ? 8 : 4);
2630 /* The basic copying loop. */
2634 if (n_bytes % (2 * align) != 0)
2636 if ((n_bytes % (2 * align)) >= align)
2639 if ((n_bytes % align) != 0)
2643 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2647 /* Emit code to perform a block clear.
2649 OPERANDS[0] is the destination pointer as a REG, clobbered.
2650 OPERANDS[1] is a register for temporary storage.
2651 OPERANDS[2] is the size as a CONST_INT
2652 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
2655 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2657 int align = INTVAL (operands[3]);
2658 unsigned long n_bytes = INTVAL (operands[2]);
2660 /* We can't clear more than a word at a time because the PA
2661 has no longer integer move insns. */
2662 if (align > (TARGET_64BIT ? 8 : 4))
2663 align = (TARGET_64BIT ? 8 : 4);
2665 /* Note that we know each loop below will execute at least twice
2666 (else we would have open-coded the copy). */
2670 /* Pre-adjust the loop counter. */
2671 operands[2] = GEN_INT (n_bytes - 16);
2672 output_asm_insn ("ldi %2,%1", operands);
2675 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2676 output_asm_insn ("addib,>= -16,%1,.-4", operands);
2677 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2679 /* Handle the residual. There could be up to 7 bytes of
2680 residual to copy! */
2681 if (n_bytes % 16 != 0)
2683 operands[2] = GEN_INT (n_bytes % 8);
2684 if (n_bytes % 16 >= 8)
2685 output_asm_insn ("std,ma %%r0,8(%0)", operands);
2686 if (n_bytes % 8 != 0)
2687 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
2692 /* Pre-adjust the loop counter. */
2693 operands[2] = GEN_INT (n_bytes - 8);
2694 output_asm_insn ("ldi %2,%1", operands);
2697 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2698 output_asm_insn ("addib,>= -8,%1,.-4", operands);
2699 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2701 /* Handle the residual. There could be up to 7 bytes of
2702 residual to copy! */
2703 if (n_bytes % 8 != 0)
2705 operands[2] = GEN_INT (n_bytes % 4);
2706 if (n_bytes % 8 >= 4)
2707 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
2708 if (n_bytes % 4 != 0)
2709 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
2714 /* Pre-adjust the loop counter. */
2715 operands[2] = GEN_INT (n_bytes - 4);
2716 output_asm_insn ("ldi %2,%1", operands);
2719 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2720 output_asm_insn ("addib,>= -4,%1,.-4", operands);
2721 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2723 /* Handle the residual. */
2724 if (n_bytes % 4 != 0)
2726 if (n_bytes % 4 >= 2)
2727 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
2728 if (n_bytes % 2 != 0)
2729 output_asm_insn ("stb %%r0,0(%0)", operands);
2734 /* Pre-adjust the loop counter. */
2735 operands[2] = GEN_INT (n_bytes - 2);
2736 output_asm_insn ("ldi %2,%1", operands);
2739 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2740 output_asm_insn ("addib,>= -2,%1,.-4", operands);
2741 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
2743 /* Handle the residual. */
2744 if (n_bytes % 2 != 0)
2745 output_asm_insn ("stb %%r0,0(%0)", operands);
2754 /* Count the number of insns necessary to handle this block move.
2756 Basic structure is the same as emit_block_move, except that we
2757 count insns rather than emit them. */
2760 compute_clrmem_length (rtx insn)
2762 rtx pat = PATTERN (insn);
2763 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
2764 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
2765 unsigned int n_insns = 0;
2767 /* We can't clear more than a word at a time because the PA
2768 has no longer integer move insns. */
2769 if (align > (TARGET_64BIT ? 8 : 4))
2770 align = (TARGET_64BIT ? 8 : 4);
2772 /* The basic loop. */
2776 if (n_bytes % (2 * align) != 0)
2778 if ((n_bytes % (2 * align)) >= align)
2781 if ((n_bytes % align) != 0)
2785 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2791 output_and (rtx *operands)
2793 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2795 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2796 int ls0, ls1, ms0, p, len;
2798 for (ls0 = 0; ls0 < 32; ls0++)
2799 if ((mask & (1 << ls0)) == 0)
2802 for (ls1 = ls0; ls1 < 32; ls1++)
2803 if ((mask & (1 << ls1)) != 0)
2806 for (ms0 = ls1; ms0 < 32; ms0++)
2807 if ((mask & (1 << ms0)) == 0)
2810 gcc_assert (ms0 == 32);
2818 operands[2] = GEN_INT (len);
2819 return "{extru|extrw,u} %1,31,%2,%0";
2823 /* We could use this `depi' for the case above as well, but `depi'
2824 requires one more register file access than an `extru'. */
2829 operands[2] = GEN_INT (p);
2830 operands[3] = GEN_INT (len);
2831 return "{depi|depwi} 0,%2,%3,%0";
2835 return "and %1,%2,%0";
2838 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2839 storing the result in operands[0]. */
2841 output_64bit_and (rtx *operands)
2843 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2845 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2846 int ls0, ls1, ms0, p, len;
2848 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2849 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2852 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2853 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2856 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2857 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2860 gcc_assert (ms0 == HOST_BITS_PER_WIDE_INT);
2862 if (ls1 == HOST_BITS_PER_WIDE_INT)
2868 operands[2] = GEN_INT (len);
2869 return "extrd,u %1,63,%2,%0";
2873 /* We could use this `depi' for the case above as well, but `depi'
2874 requires one more register file access than an `extru'. */
2879 operands[2] = GEN_INT (p);
2880 operands[3] = GEN_INT (len);
2881 return "depdi 0,%2,%3,%0";
2885 return "and %1,%2,%0";
2889 output_ior (rtx *operands)
2891 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2892 int bs0, bs1, p, len;
2894 if (INTVAL (operands[2]) == 0)
2895 return "copy %1,%0";
2897 for (bs0 = 0; bs0 < 32; bs0++)
2898 if ((mask & (1 << bs0)) != 0)
2901 for (bs1 = bs0; bs1 < 32; bs1++)
2902 if ((mask & (1 << bs1)) == 0)
2905 gcc_assert (bs1 == 32 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2910 operands[2] = GEN_INT (p);
2911 operands[3] = GEN_INT (len);
2912 return "{depi|depwi} -1,%2,%3,%0";
2915 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2916 storing the result in operands[0]. */
2918 output_64bit_ior (rtx *operands)
2920 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2921 int bs0, bs1, p, len;
2923 if (INTVAL (operands[2]) == 0)
2924 return "copy %1,%0";
2926 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2927 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2930 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2931 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2934 gcc_assert (bs1 == HOST_BITS_PER_WIDE_INT
2935 || ((unsigned HOST_WIDE_INT) 1 << bs1) > mask);
2940 operands[2] = GEN_INT (p);
2941 operands[3] = GEN_INT (len);
2942 return "depdi -1,%2,%3,%0";
2945 /* Target hook for assembling integer objects. This code handles
2946 aligned SI and DI integers specially since function references
2947 must be preceded by P%. */
2950 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
2952 if (size == UNITS_PER_WORD
2954 && function_label_operand (x, VOIDmode))
2956 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2957 output_addr_const (asm_out_file, x);
2958 fputc ('\n', asm_out_file);
2961 return default_assemble_integer (x, size, aligned_p);
2964 /* Output an ascii string. */
2966 output_ascii (FILE *file, const char *p, int size)
2970 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2972 /* The HP assembler can only take strings of 256 characters at one
2973 time. This is a limitation on input line length, *not* the
2974 length of the string. Sigh. Even worse, it seems that the
2975 restriction is in number of input characters (see \xnn &
2976 \whatever). So we have to do this very carefully. */
2978 fputs ("\t.STRING \"", file);
2981 for (i = 0; i < size; i += 4)
2985 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2987 register unsigned int c = (unsigned char) p[i + io];
2989 if (c == '\"' || c == '\\')
2990 partial_output[co++] = '\\';
2991 if (c >= ' ' && c < 0177)
2992 partial_output[co++] = c;
2996 partial_output[co++] = '\\';
2997 partial_output[co++] = 'x';
2998 hexd = c / 16 - 0 + '0';
3000 hexd -= '9' - 'a' + 1;
3001 partial_output[co++] = hexd;
3002 hexd = c % 16 - 0 + '0';
3004 hexd -= '9' - 'a' + 1;
3005 partial_output[co++] = hexd;
3008 if (chars_output + co > 243)
3010 fputs ("\"\n\t.STRING \"", file);
3013 fwrite (partial_output, 1, (size_t) co, file);
3017 fputs ("\"\n", file);
3020 /* Try to rewrite floating point comparisons & branches to avoid
3021 useless add,tr insns.
3023 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3024 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3025 first attempt to remove useless add,tr insns. It is zero
3026 for the second pass as reorg sometimes leaves bogus REG_DEAD
3029 When CHECK_NOTES is zero we can only eliminate add,tr insns
3030 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3033 remove_useless_addtr_insns (int check_notes)
3036 static int pass = 0;
3038 /* This is fairly cheap, so always run it when optimizing. */
3042 int fbranch_count = 0;
3044 /* Walk all the insns in this function looking for fcmp & fbranch
3045 instructions. Keep track of how many of each we find. */
3046 for (insn = get_insns (); insn; insn = next_insn (insn))
3050 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3051 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3054 tmp = PATTERN (insn);
3056 /* It must be a set. */
3057 if (GET_CODE (tmp) != SET)
3060 /* If the destination is CCFP, then we've found an fcmp insn. */
3061 tmp = SET_DEST (tmp);
3062 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3068 tmp = PATTERN (insn);
3069 /* If this is an fbranch instruction, bump the fbranch counter. */
3070 if (GET_CODE (tmp) == SET
3071 && SET_DEST (tmp) == pc_rtx
3072 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3073 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3074 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3075 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3083 /* Find all floating point compare + branch insns. If possible,
3084 reverse the comparison & the branch to avoid add,tr insns. */
3085 for (insn = get_insns (); insn; insn = next_insn (insn))
3089 /* Ignore anything that isn't an INSN. */
3090 if (GET_CODE (insn) != INSN)
3093 tmp = PATTERN (insn);
3095 /* It must be a set. */
3096 if (GET_CODE (tmp) != SET)
3099 /* The destination must be CCFP, which is register zero. */
3100 tmp = SET_DEST (tmp);
3101 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3104 /* INSN should be a set of CCFP.
3106 See if the result of this insn is used in a reversed FP
3107 conditional branch. If so, reverse our condition and
3108 the branch. Doing so avoids useless add,tr insns. */
3109 next = next_insn (insn);
3112 /* Jumps, calls and labels stop our search. */
3113 if (GET_CODE (next) == JUMP_INSN
3114 || GET_CODE (next) == CALL_INSN
3115 || GET_CODE (next) == CODE_LABEL)
3118 /* As does another fcmp insn. */
3119 if (GET_CODE (next) == INSN
3120 && GET_CODE (PATTERN (next)) == SET
3121 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3122 && REGNO (SET_DEST (PATTERN (next))) == 0)
3125 next = next_insn (next);
3128 /* Is NEXT_INSN a branch? */
3130 && GET_CODE (next) == JUMP_INSN)
3132 rtx pattern = PATTERN (next);
3134 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3135 and CCFP dies, then reverse our conditional and the branch
3136 to avoid the add,tr. */
3137 if (GET_CODE (pattern) == SET
3138 && SET_DEST (pattern) == pc_rtx
3139 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3140 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3141 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3142 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3143 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3144 && (fcmp_count == fbranch_count
3146 && find_regno_note (next, REG_DEAD, 0))))
3148 /* Reverse the branch. */
3149 tmp = XEXP (SET_SRC (pattern), 1);
3150 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3151 XEXP (SET_SRC (pattern), 2) = tmp;
3152 INSN_CODE (next) = -1;
3154 /* Reverse our condition. */
3155 tmp = PATTERN (insn);
3156 PUT_CODE (XEXP (tmp, 1),
3157 (reverse_condition_maybe_unordered
3158 (GET_CODE (XEXP (tmp, 1)))));
3168 /* You may have trouble believing this, but this is the 32 bit HP-PA
3173 Variable arguments (optional; any number may be allocated)
3175 SP-(4*(N+9)) arg word N
3180 Fixed arguments (must be allocated; may remain unused)
3189 SP-32 External Data Pointer (DP)
3191 SP-24 External/stub RP (RP')
3195 SP-8 Calling Stub RP (RP'')
3200 SP-0 Stack Pointer (points to next available address)
3204 /* This function saves registers as follows. Registers marked with ' are
3205 this function's registers (as opposed to the previous function's).
3206 If a frame_pointer isn't needed, r4 is saved as a general register;
3207 the space for the frame pointer is still allocated, though, to keep
3213 SP (FP') Previous FP
3214 SP + 4 Alignment filler (sigh)
3215 SP + 8 Space for locals reserved here.
3219 SP + n All call saved register used.
3223 SP + o All call saved fp registers used.
3227 SP + p (SP') points to next available address.
3231 /* Global variables set by output_function_prologue(). */
3232 /* Size of frame. Need to know this to emit return insns from
3234 static HOST_WIDE_INT actual_fsize, local_fsize;
3235 static int save_fregs;
3237 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3238 Handle case where DISP > 8k by using the add_high_const patterns.
3240 Note in DISP > 8k case, we will leave the high part of the address
3241 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3244 store_reg (int reg, HOST_WIDE_INT disp, int base)
3246 rtx insn, dest, src, basereg;
3248 src = gen_rtx_REG (word_mode, reg);
3249 basereg = gen_rtx_REG (Pmode, base);
3250 if (VAL_14_BITS_P (disp))
3252 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3253 insn = emit_move_insn (dest, src);
3255 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3257 rtx delta = GEN_INT (disp);
3258 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3260 emit_move_insn (tmpreg, delta);
3261 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3262 dest = gen_rtx_MEM (word_mode, tmpreg);
3263 insn = emit_move_insn (dest, src);
3267 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3268 gen_rtx_SET (VOIDmode,
3269 gen_rtx_MEM (word_mode,
3270 gen_rtx_PLUS (word_mode, basereg,
3278 rtx delta = GEN_INT (disp);
3279 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3280 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3282 emit_move_insn (tmpreg, high);
3283 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3284 insn = emit_move_insn (dest, src);
3288 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3289 gen_rtx_SET (VOIDmode,
3290 gen_rtx_MEM (word_mode,
3291 gen_rtx_PLUS (word_mode, basereg,
3299 RTX_FRAME_RELATED_P (insn) = 1;
3302 /* Emit RTL to store REG at the memory location specified by BASE and then
3303 add MOD to BASE. MOD must be <= 8k. */
3306 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3308 rtx insn, basereg, srcreg, delta;
3310 gcc_assert (VAL_14_BITS_P (mod));
3312 basereg = gen_rtx_REG (Pmode, base);
3313 srcreg = gen_rtx_REG (word_mode, reg);
3314 delta = GEN_INT (mod);
3316 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3319 RTX_FRAME_RELATED_P (insn) = 1;
3321 /* RTX_FRAME_RELATED_P must be set on each frame related set
3322 in a parallel with more than one element. Don't set
3323 RTX_FRAME_RELATED_P in the first set if reg is temporary
3324 register 1. The effect of this operation is recorded in
3325 the initial copy. */
3328 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3329 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3333 /* The first element of a PARALLEL is always processed if it is
3334 a SET. Thus, we need an expression list for this case. */
3336 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3337 gen_rtx_SET (VOIDmode, basereg,
3338 gen_rtx_PLUS (word_mode, basereg, delta)),
3344 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3345 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3346 whether to add a frame note or not.
3348 In the DISP > 8k case, we leave the high part of the address in %r1.
3349 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3352 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3356 if (VAL_14_BITS_P (disp))
3358 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3359 plus_constant (gen_rtx_REG (Pmode, base), disp));
3361 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3363 rtx basereg = gen_rtx_REG (Pmode, base);
3364 rtx delta = GEN_INT (disp);
3365 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3367 emit_move_insn (tmpreg, delta);
3368 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3369 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3373 rtx basereg = gen_rtx_REG (Pmode, base);
3374 rtx delta = GEN_INT (disp);
3375 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3377 emit_move_insn (tmpreg,
3378 gen_rtx_PLUS (Pmode, basereg,
3379 gen_rtx_HIGH (Pmode, delta)));
3380 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3381 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3384 if (DO_FRAME_NOTES && note)
3385 RTX_FRAME_RELATED_P (insn) = 1;
3389 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3394 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3395 be consistent with the rounding and size calculation done here.
3396 Change them at the same time. */
3398 /* We do our own stack alignment. First, round the size of the
3399 stack locals up to a word boundary. */
3400 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3402 /* Space for previous frame pointer + filler. If any frame is
3403 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3404 waste some space here for the sake of HP compatibility. The
3405 first slot is only used when the frame pointer is needed. */
3406 if (size || frame_pointer_needed)
3407 size += STARTING_FRAME_OFFSET;
3409 /* If the current function calls __builtin_eh_return, then we need
3410 to allocate stack space for registers that will hold data for
3411 the exception handler. */
3412 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3416 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3418 size += i * UNITS_PER_WORD;
3421 /* Account for space used by the callee general register saves. */
3422 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3423 if (regs_ever_live[i])
3424 size += UNITS_PER_WORD;
3426 /* Account for space used by the callee floating point register saves. */
3427 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3428 if (regs_ever_live[i]
3429 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3433 /* We always save both halves of the FP register, so always
3434 increment the frame size by 8 bytes. */
3438 /* If any of the floating registers are saved, account for the
3439 alignment needed for the floating point register save block. */
3442 size = (size + 7) & ~7;
3447 /* The various ABIs include space for the outgoing parameters in the
3448 size of the current function's stack frame. We don't need to align
3449 for the outgoing arguments as their alignment is set by the final
3450 rounding for the frame as a whole. */
3451 size += current_function_outgoing_args_size;
3453 /* Allocate space for the fixed frame marker. This space must be
3454 allocated for any function that makes calls or allocates
3456 if (!current_function_is_leaf || size)
3457 size += TARGET_64BIT ? 48 : 32;
3459 /* Finally, round to the preferred stack boundary. */
3460 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3461 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3464 /* Generate the assembly code for function entry. FILE is a stdio
3465 stream to output the code to. SIZE is an int: how many units of
3466 temporary storage to allocate.
3468 Refer to the array `regs_ever_live' to determine which registers to
3469 save; `regs_ever_live[I]' is nonzero if register number I is ever
3470 used in the function. This function is responsible for knowing
3471 which registers should not be saved even if used. */
3473 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3474 of memory. If any fpu reg is used in the function, we allocate
3475 such a block here, at the bottom of the frame, just in case it's needed.
3477 If this function is a leaf procedure, then we may choose not
3478 to do a "save" insn. The decision about whether or not
3479 to do this is made in regclass.c. */
3482 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3484 /* The function's label and associated .PROC must never be
3485 separated and must be output *after* any profiling declarations
3486 to avoid changing spaces/subspaces within a procedure. */
3487 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3488 fputs ("\t.PROC\n", file);
3490 /* hppa_expand_prologue does the dirty work now. We just need
3491 to output the assembler directives which denote the start
3493 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3494 if (regs_ever_live[2])
3495 fputs (",CALLS,SAVE_RP", file);
3497 fputs (",NO_CALLS", file);
3499 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3500 at the beginning of the frame and that it is used as the frame
3501 pointer for the frame. We do this because our current frame
3502 layout doesn't conform to that specified in the the HP runtime
3503 documentation and we need a way to indicate to programs such as
3504 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3505 isn't used by HP compilers but is supported by the assembler.
3506 However, SAVE_SP is supposed to indicate that the previous stack
3507 pointer has been saved in the frame marker. */
3508 if (frame_pointer_needed)
3509 fputs (",SAVE_SP", file);
3511 /* Pass on information about the number of callee register saves
3512 performed in the prologue.
3514 The compiler is supposed to pass the highest register number
3515 saved, the assembler then has to adjust that number before
3516 entering it into the unwind descriptor (to account for any
3517 caller saved registers with lower register numbers than the
3518 first callee saved register). */
3520 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3523 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3525 fputs ("\n\t.ENTRY\n", file);
3527 remove_useless_addtr_insns (0);
3531 hppa_expand_prologue (void)
3533 int merge_sp_adjust_with_store = 0;
3534 HOST_WIDE_INT size = get_frame_size ();
3535 HOST_WIDE_INT offset;
3543 /* Compute total size for frame pointer, filler, locals and rounding to
3544 the next word boundary. Similar code appears in compute_frame_size
3545 and must be changed in tandem with this code. */
3546 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3547 if (local_fsize || frame_pointer_needed)
3548 local_fsize += STARTING_FRAME_OFFSET;
3550 actual_fsize = compute_frame_size (size, &save_fregs);
3552 /* Compute a few things we will use often. */
3553 tmpreg = gen_rtx_REG (word_mode, 1);
3555 /* Save RP first. The calling conventions manual states RP will
3556 always be stored into the caller's frame at sp - 20 or sp - 16
3557 depending on which ABI is in use. */
3558 if (regs_ever_live[2] || current_function_calls_eh_return)
3559 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3561 /* Allocate the local frame and set up the frame pointer if needed. */
3562 if (actual_fsize != 0)
3564 if (frame_pointer_needed)
3566 /* Copy the old frame pointer temporarily into %r1. Set up the
3567 new stack pointer, then store away the saved old frame pointer
3568 into the stack at sp and at the same time update the stack
3569 pointer by actual_fsize bytes. Two versions, first
3570 handles small (<8k) frames. The second handles large (>=8k)
3572 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3575 /* We need to record the frame pointer save here since the
3576 new frame pointer is set in the following insn. */
3577 RTX_FRAME_RELATED_P (insn) = 1;
3579 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3580 gen_rtx_SET (VOIDmode,
3581 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3586 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3588 RTX_FRAME_RELATED_P (insn) = 1;
3590 if (VAL_14_BITS_P (actual_fsize))
3591 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3594 /* It is incorrect to store the saved frame pointer at *sp,
3595 then increment sp (writes beyond the current stack boundary).
3597 So instead use stwm to store at *sp and post-increment the
3598 stack pointer as an atomic operation. Then increment sp to
3599 finish allocating the new frame. */
3600 HOST_WIDE_INT adjust1 = 8192 - 64;
3601 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3603 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3604 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3608 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3609 we need to store the previous stack pointer (frame pointer)
3610 into the frame marker on targets that use the HP unwind
3611 library. This allows the HP unwind library to be used to
3612 unwind GCC frames. However, we are not fully compatible
3613 with the HP library because our frame layout differs from
3614 that specified in the HP runtime specification.
3616 We don't want a frame note on this instruction as the frame
3617 marker moves during dynamic stack allocation.
3619 This instruction also serves as a blockage to prevent
3620 register spills from being scheduled before the stack
3621 pointer is raised. This is necessary as we store
3622 registers using the frame pointer as a base register,
3623 and the frame pointer is set before sp is raised. */
3624 if (TARGET_HPUX_UNWIND_LIBRARY)
3626 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3627 GEN_INT (TARGET_64BIT ? -8 : -4));
3629 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3633 emit_insn (gen_blockage ());
3635 /* no frame pointer needed. */
3638 /* In some cases we can perform the first callee register save
3639 and allocating the stack frame at the same time. If so, just
3640 make a note of it and defer allocating the frame until saving
3641 the callee registers. */
3642 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3643 merge_sp_adjust_with_store = 1;
3644 /* Can not optimize. Adjust the stack frame by actual_fsize
3647 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3652 /* Normal register save.
3654 Do not save the frame pointer in the frame_pointer_needed case. It
3655 was done earlier. */
3656 if (frame_pointer_needed)
3658 offset = local_fsize;
3660 /* Saving the EH return data registers in the frame is the simplest
3661 way to get the frame unwind information emitted. We put them
3662 just before the general registers. */
3663 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3665 unsigned int i, regno;
3669 regno = EH_RETURN_DATA_REGNO (i);
3670 if (regno == INVALID_REGNUM)
3673 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3674 offset += UNITS_PER_WORD;
3678 for (i = 18; i >= 4; i--)
3679 if (regs_ever_live[i] && ! call_used_regs[i])
3681 store_reg (i, offset, FRAME_POINTER_REGNUM);
3682 offset += UNITS_PER_WORD;
3685 /* Account for %r3 which is saved in a special place. */
3688 /* No frame pointer needed. */
3691 offset = local_fsize - actual_fsize;
3693 /* Saving the EH return data registers in the frame is the simplest
3694 way to get the frame unwind information emitted. */
3695 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3697 unsigned int i, regno;
3701 regno = EH_RETURN_DATA_REGNO (i);
3702 if (regno == INVALID_REGNUM)
3705 /* If merge_sp_adjust_with_store is nonzero, then we can
3706 optimize the first save. */
3707 if (merge_sp_adjust_with_store)
3709 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3710 merge_sp_adjust_with_store = 0;
3713 store_reg (regno, offset, STACK_POINTER_REGNUM);
3714 offset += UNITS_PER_WORD;
3718 for (i = 18; i >= 3; i--)
3719 if (regs_ever_live[i] && ! call_used_regs[i])
3721 /* If merge_sp_adjust_with_store is nonzero, then we can
3722 optimize the first GR save. */
3723 if (merge_sp_adjust_with_store)
3725 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3726 merge_sp_adjust_with_store = 0;
3729 store_reg (i, offset, STACK_POINTER_REGNUM);
3730 offset += UNITS_PER_WORD;
3734 /* If we wanted to merge the SP adjustment with a GR save, but we never
3735 did any GR saves, then just emit the adjustment here. */
3736 if (merge_sp_adjust_with_store)
3737 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3741 /* The hppa calling conventions say that %r19, the pic offset
3742 register, is saved at sp - 32 (in this function's frame)
3743 when generating PIC code. FIXME: What is the correct thing
3744 to do for functions which make no calls and allocate no
3745 frame? Do we need to allocate a frame, or can we just omit
3746 the save? For now we'll just omit the save.
3748 We don't want a note on this insn as the frame marker can
3749 move if there is a dynamic stack allocation. */
3750 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3752 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
3754 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
3758 /* Align pointer properly (doubleword boundary). */
3759 offset = (offset + 7) & ~7;
3761 /* Floating point register store. */
3766 /* First get the frame or stack pointer to the start of the FP register
3768 if (frame_pointer_needed)
3770 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3771 base = frame_pointer_rtx;
3775 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3776 base = stack_pointer_rtx;
3779 /* Now actually save the FP registers. */
3780 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3782 if (regs_ever_live[i]
3783 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3785 rtx addr, insn, reg;
3786 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3787 reg = gen_rtx_REG (DFmode, i);
3788 insn = emit_move_insn (addr, reg);
3791 RTX_FRAME_RELATED_P (insn) = 1;
3794 rtx mem = gen_rtx_MEM (DFmode,
3795 plus_constant (base, offset));
3797 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3798 gen_rtx_SET (VOIDmode, mem, reg),
3803 rtx meml = gen_rtx_MEM (SFmode,
3804 plus_constant (base, offset));
3805 rtx memr = gen_rtx_MEM (SFmode,
3806 plus_constant (base, offset + 4));
3807 rtx regl = gen_rtx_REG (SFmode, i);
3808 rtx regr = gen_rtx_REG (SFmode, i + 1);
3809 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3810 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3813 RTX_FRAME_RELATED_P (setl) = 1;
3814 RTX_FRAME_RELATED_P (setr) = 1;
3815 vec = gen_rtvec (2, setl, setr);
3817 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3818 gen_rtx_SEQUENCE (VOIDmode, vec),
3822 offset += GET_MODE_SIZE (DFmode);
3829 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3830 Handle case where DISP > 8k by using the add_high_const patterns. */
3833 load_reg (int reg, HOST_WIDE_INT disp, int base)
3835 rtx dest = gen_rtx_REG (word_mode, reg);
3836 rtx basereg = gen_rtx_REG (Pmode, base);
3839 if (VAL_14_BITS_P (disp))
3840 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3841 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3843 rtx delta = GEN_INT (disp);
3844 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3846 emit_move_insn (tmpreg, delta);
3847 if (TARGET_DISABLE_INDEXING)
3849 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3850 src = gen_rtx_MEM (word_mode, tmpreg);
3853 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3857 rtx delta = GEN_INT (disp);
3858 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3859 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3861 emit_move_insn (tmpreg, high);
3862 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3865 emit_move_insn (dest, src);
3868 /* Update the total code bytes output to the text section. */
3871 update_total_code_bytes (int nbytes)
3873 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3874 && !IN_NAMED_SECTION_P (cfun->decl))
3876 if (INSN_ADDRESSES_SET_P ())
3878 unsigned long old_total = total_code_bytes;
3880 total_code_bytes += nbytes;
3882 /* Be prepared to handle overflows. */
3883 if (old_total > total_code_bytes)
3884 total_code_bytes = -1;
3887 total_code_bytes = -1;
3891 /* This function generates the assembly code for function exit.
3892 Args are as for output_function_prologue ().
3894 The function epilogue should not depend on the current stack
3895 pointer! It should use the frame pointer only. This is mandatory
3896 because of alloca; we also take advantage of it to omit stack
3897 adjustments before returning. */
3900 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3902 rtx insn = get_last_insn ();
3906 /* hppa_expand_epilogue does the dirty work now. We just need
3907 to output the assembler directives which denote the end
3910 To make debuggers happy, emit a nop if the epilogue was completely
3911 eliminated due to a volatile call as the last insn in the
3912 current function. That way the return address (in %r2) will
3913 always point to a valid instruction in the current function. */
3915 /* Get the last real insn. */
3916 if (GET_CODE (insn) == NOTE)
3917 insn = prev_real_insn (insn);
3919 /* If it is a sequence, then look inside. */
3920 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3921 insn = XVECEXP (PATTERN (insn), 0, 0);
3923 /* If insn is a CALL_INSN, then it must be a call to a volatile
3924 function (otherwise there would be epilogue insns). */
3925 if (insn && GET_CODE (insn) == CALL_INSN)
3927 fputs ("\tnop\n", file);
3931 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3933 if (TARGET_SOM && TARGET_GAS)
3935 /* We done with this subspace except possibly for some additional
3936 debug information. Forget that we are in this subspace to ensure
3937 that the next function is output in its own subspace. */
3941 if (INSN_ADDRESSES_SET_P ())
3943 insn = get_last_nonnote_insn ();
3944 last_address += INSN_ADDRESSES (INSN_UID (insn));
3946 last_address += insn_default_length (insn);
3947 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
3948 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
3951 /* Finally, update the total number of code bytes output so far. */
3952 update_total_code_bytes (last_address);
3956 hppa_expand_epilogue (void)
3959 HOST_WIDE_INT offset;
3960 HOST_WIDE_INT ret_off = 0;
3962 int merge_sp_adjust_with_load = 0;
3964 /* We will use this often. */
3965 tmpreg = gen_rtx_REG (word_mode, 1);
3967 /* Try to restore RP early to avoid load/use interlocks when
3968 RP gets used in the return (bv) instruction. This appears to still
3969 be necessary even when we schedule the prologue and epilogue. */
3970 if (regs_ever_live [2] || current_function_calls_eh_return)
3972 ret_off = TARGET_64BIT ? -16 : -20;
3973 if (frame_pointer_needed)
3975 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3980 /* No frame pointer, and stack is smaller than 8k. */
3981 if (VAL_14_BITS_P (ret_off - actual_fsize))
3983 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3989 /* General register restores. */
3990 if (frame_pointer_needed)
3992 offset = local_fsize;
3994 /* If the current function calls __builtin_eh_return, then we need
3995 to restore the saved EH data registers. */
3996 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3998 unsigned int i, regno;
4002 regno = EH_RETURN_DATA_REGNO (i);
4003 if (regno == INVALID_REGNUM)
4006 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4007 offset += UNITS_PER_WORD;
4011 for (i = 18; i >= 4; i--)
4012 if (regs_ever_live[i] && ! call_used_regs[i])
4014 load_reg (i, offset, FRAME_POINTER_REGNUM);
4015 offset += UNITS_PER_WORD;
4020 offset = local_fsize - actual_fsize;
4022 /* If the current function calls __builtin_eh_return, then we need
4023 to restore the saved EH data registers. */
4024 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4026 unsigned int i, regno;
4030 regno = EH_RETURN_DATA_REGNO (i);
4031 if (regno == INVALID_REGNUM)
4034 /* Only for the first load.
4035 merge_sp_adjust_with_load holds the register load
4036 with which we will merge the sp adjustment. */
4037 if (merge_sp_adjust_with_load == 0
4039 && VAL_14_BITS_P (-actual_fsize))
4040 merge_sp_adjust_with_load = regno;
4042 load_reg (regno, offset, STACK_POINTER_REGNUM);
4043 offset += UNITS_PER_WORD;
4047 for (i = 18; i >= 3; i--)
4049 if (regs_ever_live[i] && ! call_used_regs[i])
4051 /* Only for the first load.
4052 merge_sp_adjust_with_load holds the register load
4053 with which we will merge the sp adjustment. */
4054 if (merge_sp_adjust_with_load == 0
4056 && VAL_14_BITS_P (-actual_fsize))
4057 merge_sp_adjust_with_load = i;
4059 load_reg (i, offset, STACK_POINTER_REGNUM);
4060 offset += UNITS_PER_WORD;
4065 /* Align pointer properly (doubleword boundary). */
4066 offset = (offset + 7) & ~7;
4068 /* FP register restores. */
4071 /* Adjust the register to index off of. */
4072 if (frame_pointer_needed)
4073 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4075 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4077 /* Actually do the restores now. */
4078 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4079 if (regs_ever_live[i]
4080 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4082 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4083 rtx dest = gen_rtx_REG (DFmode, i);
4084 emit_move_insn (dest, src);
4088 /* Emit a blockage insn here to keep these insns from being moved to
4089 an earlier spot in the epilogue, or into the main instruction stream.
4091 This is necessary as we must not cut the stack back before all the
4092 restores are finished. */
4093 emit_insn (gen_blockage ());
4095 /* Reset stack pointer (and possibly frame pointer). The stack
4096 pointer is initially set to fp + 64 to avoid a race condition. */
4097 if (frame_pointer_needed)
4099 rtx delta = GEN_INT (-64);
4101 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4102 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4104 /* If we were deferring a callee register restore, do it now. */
4105 else if (merge_sp_adjust_with_load)
4107 rtx delta = GEN_INT (-actual_fsize);
4108 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4110 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4112 else if (actual_fsize != 0)
4113 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4116 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4117 frame greater than 8k), do so now. */
4119 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4121 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4123 rtx sa = EH_RETURN_STACKADJ_RTX;
4125 emit_insn (gen_blockage ());
4126 emit_insn (TARGET_64BIT
4127 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4128 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4133 hppa_pic_save_rtx (void)
4135 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4139 hppa_profile_hook (int label_no)
4141 /* We use SImode for the address of the function in both 32 and
4142 64-bit code to avoid having to provide DImode versions of the
4143 lcla2 and load_offset_label_address insn patterns. */
4144 rtx reg = gen_reg_rtx (SImode);
4145 rtx label_rtx = gen_label_rtx ();
4146 rtx begin_label_rtx, call_insn;
4147 char begin_label_name[16];
4149 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4151 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4154 emit_move_insn (arg_pointer_rtx,
4155 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4158 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4160 /* The address of the function is loaded into %r25 with a instruction-
4161 relative sequence that avoids the use of relocations. The sequence
4162 is split so that the load_offset_label_address instruction can
4163 occupy the delay slot of the call to _mcount. */
4165 emit_insn (gen_lcla2 (reg, label_rtx));
4167 emit_insn (gen_lcla1 (reg, label_rtx));
4169 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4170 reg, begin_label_rtx, label_rtx));
4172 #ifndef NO_PROFILE_COUNTERS
4174 rtx count_label_rtx, addr, r24;
4175 char count_label_name[16];
4177 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4178 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4180 addr = force_reg (Pmode, count_label_rtx);
4181 r24 = gen_rtx_REG (Pmode, 24);
4182 emit_move_insn (r24, addr);
4185 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4186 gen_rtx_SYMBOL_REF (Pmode,
4188 GEN_INT (TARGET_64BIT ? 24 : 12)));
4190 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4195 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4196 gen_rtx_SYMBOL_REF (Pmode,
4198 GEN_INT (TARGET_64BIT ? 16 : 8)));
4202 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4203 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4205 /* Indicate the _mcount call cannot throw, nor will it execute a
4207 REG_NOTES (call_insn)
4208 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4211 /* Fetch the return address for the frame COUNT steps up from
4212 the current frame, after the prologue. FRAMEADDR is the
4213 frame pointer of the COUNT frame.
4215 We want to ignore any export stub remnants here. To handle this,
4216 we examine the code at the return address, and if it is an export
4217 stub, we return a memory rtx for the stub return address stored
4220 The value returned is used in two different ways:
4222 1. To find a function's caller.
4224 2. To change the return address for a function.
4226 This function handles most instances of case 1; however, it will
4227 fail if there are two levels of stubs to execute on the return
4228 path. The only way I believe that can happen is if the return value
4229 needs a parameter relocation, which never happens for C code.
4231 This function handles most instances of case 2; however, it will
4232 fail if we did not originally have stub code on the return path
4233 but will need stub code on the new return path. This can happen if
4234 the caller & callee are both in the main program, but the new
4235 return location is in a shared library. */
4238 return_addr_rtx (int count, rtx frameaddr)
4248 rp = get_hard_reg_initial_val (Pmode, 2);
4250 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4253 saved_rp = gen_reg_rtx (Pmode);
4254 emit_move_insn (saved_rp, rp);
4256 /* Get pointer to the instruction stream. We have to mask out the
4257 privilege level from the two low order bits of the return address
4258 pointer here so that ins will point to the start of the first
4259 instruction that would have been executed if we returned. */
4260 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4261 label = gen_label_rtx ();
4263 /* Check the instruction stream at the normal return address for the
4266 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4267 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4268 0x00011820 | stub+16: mtsp r1,sr0
4269 0xe0400002 | stub+20: be,n 0(sr0,rp)
4271 If it is an export stub, than our return address is really in
4274 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4275 NULL_RTX, SImode, 1);
4276 emit_jump_insn (gen_bne (label));
4278 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4279 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4280 emit_jump_insn (gen_bne (label));
4282 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4283 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4284 emit_jump_insn (gen_bne (label));
4286 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4287 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4289 /* If there is no export stub then just use the value saved from
4290 the return pointer register. */
4292 emit_jump_insn (gen_bne (label));
4294 /* Here we know that our return address points to an export
4295 stub. We don't want to return the address of the export stub,
4296 but rather the return address of the export stub. That return
4297 address is stored at -24[frameaddr]. */
4299 emit_move_insn (saved_rp,
4301 memory_address (Pmode,
4302 plus_constant (frameaddr,
4309 /* This is only valid once reload has completed because it depends on
4310 knowing exactly how much (if any) frame there is and...
4312 It's only valid if there is no frame marker to de-allocate and...
4314 It's only valid if %r2 hasn't been saved into the caller's frame
4315 (we're not profiling and %r2 isn't live anywhere). */
4317 hppa_can_use_return_insn_p (void)
4319 return (reload_completed
4320 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4321 && ! regs_ever_live[2]
4322 && ! frame_pointer_needed);
4326 emit_bcond_fp (enum rtx_code code, rtx operand0)
4328 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4329 gen_rtx_IF_THEN_ELSE (VOIDmode,
4330 gen_rtx_fmt_ee (code,
4332 gen_rtx_REG (CCFPmode, 0),
4334 gen_rtx_LABEL_REF (VOIDmode, operand0),
4340 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4342 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4343 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4346 /* Adjust the cost of a scheduling dependency. Return the new cost of
4347 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4350 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4352 enum attr_type attr_type;
4354 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4355 true dependencies as they are described with bypasses now. */
4356 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4359 if (! recog_memoized (insn))
4362 attr_type = get_attr_type (insn);
4364 switch (REG_NOTE_KIND (link))
4367 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4370 if (attr_type == TYPE_FPLOAD)
4372 rtx pat = PATTERN (insn);
4373 rtx dep_pat = PATTERN (dep_insn);
4374 if (GET_CODE (pat) == PARALLEL)
4376 /* This happens for the fldXs,mb patterns. */
4377 pat = XVECEXP (pat, 0, 0);
4379 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4380 /* If this happens, we have to extend this to schedule
4381 optimally. Return 0 for now. */
4384 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4386 if (! recog_memoized (dep_insn))
4388 switch (get_attr_type (dep_insn))
4395 case TYPE_FPSQRTSGL:
4396 case TYPE_FPSQRTDBL:
4397 /* A fpload can't be issued until one cycle before a
4398 preceding arithmetic operation has finished if
4399 the target of the fpload is any of the sources
4400 (or destination) of the arithmetic operation. */
4401 return insn_default_latency (dep_insn) - 1;
4408 else if (attr_type == TYPE_FPALU)
4410 rtx pat = PATTERN (insn);
4411 rtx dep_pat = PATTERN (dep_insn);
4412 if (GET_CODE (pat) == PARALLEL)
4414 /* This happens for the fldXs,mb patterns. */
4415 pat = XVECEXP (pat, 0, 0);
4417 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4418 /* If this happens, we have to extend this to schedule
4419 optimally. Return 0 for now. */
4422 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4424 if (! recog_memoized (dep_insn))
4426 switch (get_attr_type (dep_insn))
4430 case TYPE_FPSQRTSGL:
4431 case TYPE_FPSQRTDBL:
4432 /* An ALU flop can't be issued until two cycles before a
4433 preceding divide or sqrt operation has finished if
4434 the target of the ALU flop is any of the sources
4435 (or destination) of the divide or sqrt operation. */
4436 return insn_default_latency (dep_insn) - 2;
4444 /* For other anti dependencies, the cost is 0. */
4447 case REG_DEP_OUTPUT:
4448 /* Output dependency; DEP_INSN writes a register that INSN writes some
4450 if (attr_type == TYPE_FPLOAD)
4452 rtx pat = PATTERN (insn);
4453 rtx dep_pat = PATTERN (dep_insn);
4454 if (GET_CODE (pat) == PARALLEL)
4456 /* This happens for the fldXs,mb patterns. */
4457 pat = XVECEXP (pat, 0, 0);
4459 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4460 /* If this happens, we have to extend this to schedule
4461 optimally. Return 0 for now. */
4464 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4466 if (! recog_memoized (dep_insn))
4468 switch (get_attr_type (dep_insn))
4475 case TYPE_FPSQRTSGL:
4476 case TYPE_FPSQRTDBL:
4477 /* A fpload can't be issued until one cycle before a
4478 preceding arithmetic operation has finished if
4479 the target of the fpload is the destination of the
4480 arithmetic operation.
4482 Exception: For PA7100LC, PA7200 and PA7300, the cost
4483 is 3 cycles, unless they bundle together. We also
4484 pay the penalty if the second insn is a fpload. */
4485 return insn_default_latency (dep_insn) - 1;
4492 else if (attr_type == TYPE_FPALU)
4494 rtx pat = PATTERN (insn);
4495 rtx dep_pat = PATTERN (dep_insn);
4496 if (GET_CODE (pat) == PARALLEL)
4498 /* This happens for the fldXs,mb patterns. */
4499 pat = XVECEXP (pat, 0, 0);
4501 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4502 /* If this happens, we have to extend this to schedule
4503 optimally. Return 0 for now. */
4506 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4508 if (! recog_memoized (dep_insn))
4510 switch (get_attr_type (dep_insn))
4514 case TYPE_FPSQRTSGL:
4515 case TYPE_FPSQRTDBL:
4516 /* An ALU flop can't be issued until two cycles before a
4517 preceding divide or sqrt operation has finished if
4518 the target of the ALU flop is also the target of
4519 the divide or sqrt operation. */
4520 return insn_default_latency (dep_insn) - 2;
4528 /* For other output dependencies, the cost is 0. */
4536 /* Adjust scheduling priorities. We use this to try and keep addil
4537 and the next use of %r1 close together. */
4539 pa_adjust_priority (rtx insn, int priority)
4541 rtx set = single_set (insn);
4545 src = SET_SRC (set);
4546 dest = SET_DEST (set);
4547 if (GET_CODE (src) == LO_SUM
4548 && symbolic_operand (XEXP (src, 1), VOIDmode)
4549 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4552 else if (GET_CODE (src) == MEM
4553 && GET_CODE (XEXP (src, 0)) == LO_SUM
4554 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4555 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4558 else if (GET_CODE (dest) == MEM
4559 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4560 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4561 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4567 /* The 700 can only issue a single insn at a time.
4568 The 7XXX processors can issue two insns at a time.
4569 The 8000 can issue 4 insns at a time. */
4571 pa_issue_rate (void)
4575 case PROCESSOR_700: return 1;
4576 case PROCESSOR_7100: return 2;
4577 case PROCESSOR_7100LC: return 2;
4578 case PROCESSOR_7200: return 2;
4579 case PROCESSOR_7300: return 2;
4580 case PROCESSOR_8000: return 4;
4589 /* Return any length adjustment needed by INSN which already has its length
4590 computed as LENGTH. Return zero if no adjustment is necessary.
4592 For the PA: function calls, millicode calls, and backwards short
4593 conditional branches with unfilled delay slots need an adjustment by +1
4594 (to account for the NOP which will be inserted into the instruction stream).
4596 Also compute the length of an inline block move here as it is too
4597 complicated to express as a length attribute in pa.md. */
4599 pa_adjust_insn_length (rtx insn, int length)
4601 rtx pat = PATTERN (insn);
4603 /* Jumps inside switch tables which have unfilled delay slots need
4605 if (GET_CODE (insn) == JUMP_INSN
4606 && GET_CODE (pat) == PARALLEL
4607 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4609 /* Millicode insn with an unfilled delay slot. */
4610 else if (GET_CODE (insn) == INSN
4611 && GET_CODE (pat) != SEQUENCE
4612 && GET_CODE (pat) != USE
4613 && GET_CODE (pat) != CLOBBER
4614 && get_attr_type (insn) == TYPE_MILLI)
4616 /* Block move pattern. */
4617 else if (GET_CODE (insn) == INSN
4618 && GET_CODE (pat) == PARALLEL
4619 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4620 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4621 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4622 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4623 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4624 return compute_movmem_length (insn) - 4;
4625 /* Block clear pattern. */
4626 else if (GET_CODE (insn) == INSN
4627 && GET_CODE (pat) == PARALLEL
4628 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4629 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4630 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4631 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4632 return compute_clrmem_length (insn) - 4;
4633 /* Conditional branch with an unfilled delay slot. */
4634 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4636 /* Adjust a short backwards conditional with an unfilled delay slot. */
4637 if (GET_CODE (pat) == SET
4639 && ! forward_branch_p (insn))
4641 else if (GET_CODE (pat) == PARALLEL
4642 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4645 /* Adjust dbra insn with short backwards conditional branch with
4646 unfilled delay slot -- only for case where counter is in a
4647 general register register. */
4648 else if (GET_CODE (pat) == PARALLEL
4649 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4650 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4651 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4653 && ! forward_branch_p (insn))
4661 /* Print operand X (an rtx) in assembler syntax to file FILE.
4662 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4663 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4666 print_operand (FILE *file, rtx x, int code)
4671 /* Output a 'nop' if there's nothing for the delay slot. */
4672 if (dbr_sequence_length () == 0)
4673 fputs ("\n\tnop", file);
4676 /* Output a nullification completer if there's nothing for the */
4677 /* delay slot or nullification is requested. */
4678 if (dbr_sequence_length () == 0 ||
4680 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4684 /* Print out the second register name of a register pair.
4685 I.e., R (6) => 7. */
4686 fputs (reg_names[REGNO (x) + 1], file);
4689 /* A register or zero. */
4691 || (x == CONST0_RTX (DFmode))
4692 || (x == CONST0_RTX (SFmode)))
4694 fputs ("%r0", file);
4700 /* A register or zero (floating point). */
4702 || (x == CONST0_RTX (DFmode))
4703 || (x == CONST0_RTX (SFmode)))
4705 fputs ("%fr0", file);
4714 xoperands[0] = XEXP (XEXP (x, 0), 0);
4715 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4716 output_global_address (file, xoperands[1], 0);
4717 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4721 case 'C': /* Plain (C)ondition */
4723 switch (GET_CODE (x))
4726 fputs ("=", file); break;
4728 fputs ("<>", file); break;
4730 fputs (">", file); break;
4732 fputs (">=", file); break;
4734 fputs (">>=", file); break;
4736 fputs (">>", file); break;
4738 fputs ("<", file); break;
4740 fputs ("<=", file); break;
4742 fputs ("<<=", file); break;
4744 fputs ("<<", file); break;
4749 case 'N': /* Condition, (N)egated */
4750 switch (GET_CODE (x))
4753 fputs ("<>", file); break;
4755 fputs ("=", file); break;
4757 fputs ("<=", file); break;
4759 fputs ("<", file); break;
4761 fputs ("<<", file); break;
4763 fputs ("<<=", file); break;
4765 fputs (">=", file); break;
4767 fputs (">", file); break;
4769 fputs (">>", file); break;
4771 fputs (">>=", file); break;
4776 /* For floating point comparisons. Note that the output
4777 predicates are the complement of the desired mode. The
4778 conditions for GT, GE, LT, LE and LTGT cause an invalid
4779 operation exception if the result is unordered and this
4780 exception is enabled in the floating-point status register. */
4782 switch (GET_CODE (x))
4785 fputs ("!=", file); break;
4787 fputs ("=", file); break;
4789 fputs ("!>", file); break;
4791 fputs ("!>=", file); break;
4793 fputs ("!<", file); break;
4795 fputs ("!<=", file); break;
4797 fputs ("!<>", file); break;
4799 fputs ("!?<=", file); break;
4801 fputs ("!?<", file); break;
4803 fputs ("!?>=", file); break;
4805 fputs ("!?>", file); break;
4807 fputs ("!?=", file); break;
4809 fputs ("!?", file); break;
4811 fputs ("?", file); break;
4816 case 'S': /* Condition, operands are (S)wapped. */
4817 switch (GET_CODE (x))
4820 fputs ("=", file); break;
4822 fputs ("<>", file); break;
4824 fputs ("<", file); break;
4826 fputs ("<=", file); break;
4828 fputs ("<<=", file); break;
4830 fputs ("<<", file); break;
4832 fputs (">", file); break;
4834 fputs (">=", file); break;
4836 fputs (">>=", file); break;
4838 fputs (">>", file); break;
4843 case 'B': /* Condition, (B)oth swapped and negate. */
4844 switch (GET_CODE (x))
4847 fputs ("<>", file); break;
4849 fputs ("=", file); break;
4851 fputs (">=", file); break;
4853 fputs (">", file); break;
4855 fputs (">>", file); break;
4857 fputs (">>=", file); break;
4859 fputs ("<=", file); break;
4861 fputs ("<", file); break;
4863 fputs ("<<", file); break;
4865 fputs ("<<=", file); break;
4871 gcc_assert (GET_CODE (x) == CONST_INT);
4872 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4875 gcc_assert (GET_CODE (x) == CONST_INT);
4876 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4879 gcc_assert (GET_CODE (x) == CONST_INT);
4880 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4883 gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
4884 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4887 gcc_assert (GET_CODE (x) == CONST_INT);
4888 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4891 gcc_assert (GET_CODE (x) == CONST_INT);
4892 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4895 if (GET_CODE (x) == CONST_INT)
4900 switch (GET_CODE (XEXP (x, 0)))
4904 if (ASSEMBLER_DIALECT == 0)
4905 fputs ("s,mb", file);
4907 fputs (",mb", file);
4911 if (ASSEMBLER_DIALECT == 0)
4912 fputs ("s,ma", file);
4914 fputs (",ma", file);
4917 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
4918 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
4920 if (ASSEMBLER_DIALECT == 0)
4923 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4924 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4926 if (ASSEMBLER_DIALECT == 0)
4927 fputs ("x,s", file);
4931 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4935 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4941 output_global_address (file, x, 0);
4944 output_global_address (file, x, 1);
4946 case 0: /* Don't do anything special */
4951 compute_zdepwi_operands (INTVAL (x), op);
4952 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4958 compute_zdepdi_operands (INTVAL (x), op);
4959 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4963 /* We can get here from a .vtable_inherit due to our
4964 CONSTANT_ADDRESS_P rejecting perfectly good constant
4970 if (GET_CODE (x) == REG)
4972 fputs (reg_names [REGNO (x)], file);
4973 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4979 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4980 && (REGNO (x) & 1) == 0)
4983 else if (GET_CODE (x) == MEM)
4985 int size = GET_MODE_SIZE (GET_MODE (x));
4986 rtx base = NULL_RTX;
4987 switch (GET_CODE (XEXP (x, 0)))
4991 base = XEXP (XEXP (x, 0), 0);
4992 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4996 base = XEXP (XEXP (x, 0), 0);
4997 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5000 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5001 fprintf (file, "%s(%s)",
5002 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5003 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5004 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5005 fprintf (file, "%s(%s)",
5006 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5007 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5008 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5009 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5011 /* Because the REG_POINTER flag can get lost during reload,
5012 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5013 index and base registers in the combined move patterns. */
5014 rtx base = XEXP (XEXP (x, 0), 1);
5015 rtx index = XEXP (XEXP (x, 0), 0);
5017 fprintf (file, "%s(%s)",
5018 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5021 output_address (XEXP (x, 0));
5024 output_address (XEXP (x, 0));
5029 output_addr_const (file, x);
5032 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5035 output_global_address (FILE *file, rtx x, int round_constant)
5038 /* Imagine (high (const (plus ...))). */
5039 if (GET_CODE (x) == HIGH)
5042 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5043 output_addr_const (file, x);
5044 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5046 output_addr_const (file, x);
5047 fputs ("-$global$", file);
5049 else if (GET_CODE (x) == CONST)
5051 const char *sep = "";
5052 int offset = 0; /* assembler wants -$global$ at end */
5053 rtx base = NULL_RTX;
5055 switch (GET_CODE (XEXP (XEXP (x, 0), 0)))
5058 base = XEXP (XEXP (x, 0), 0);
5059 output_addr_const (file, base);
5062 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5068 switch (GET_CODE (XEXP (XEXP (x, 0), 1)))
5071 base = XEXP (XEXP (x, 0), 1);
5072 output_addr_const (file, base);
5075 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5081 /* How bogus. The compiler is apparently responsible for
5082 rounding the constant if it uses an LR field selector.
5084 The linker and/or assembler seem a better place since
5085 they have to do this kind of thing already.
5087 If we fail to do this, HP's optimizing linker may eliminate
5088 an addil, but not update the ldw/stw/ldo instruction that
5089 uses the result of the addil. */
5091 offset = ((offset + 0x1000) & ~0x1fff);
5093 switch (GET_CODE (XEXP (x, 0)))
5106 gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
5114 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5115 fputs ("-$global$", file);
5117 fprintf (file, "%s%d", sep, offset);
5120 output_addr_const (file, x);
5123 /* Output boilerplate text to appear at the beginning of the file.
5124 There are several possible versions. */
5125 #define aputs(x) fputs(x, asm_out_file)
5127 pa_file_start_level (void)
5130 aputs ("\t.LEVEL 2.0w\n");
5131 else if (TARGET_PA_20)
5132 aputs ("\t.LEVEL 2.0\n");
5133 else if (TARGET_PA_11)
5134 aputs ("\t.LEVEL 1.1\n");
5136 aputs ("\t.LEVEL 1.0\n");
5140 pa_file_start_space (int sortspace)
5142 aputs ("\t.SPACE $PRIVATE$");
5145 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5146 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5147 "\n\t.SPACE $TEXT$");
5150 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5151 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5155 pa_file_start_file (int want_version)
5157 if (write_symbols != NO_DEBUG)
5159 output_file_directive (asm_out_file, main_input_filename);
5161 aputs ("\t.version\t\"01.01\"\n");
5166 pa_file_start_mcount (const char *aswhat)
5169 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5173 pa_elf_file_start (void)
5175 pa_file_start_level ();
5176 pa_file_start_mcount ("ENTRY");
5177 pa_file_start_file (0);
5181 pa_som_file_start (void)
5183 pa_file_start_level ();
5184 pa_file_start_space (0);
5185 aputs ("\t.IMPORT $global$,DATA\n"
5186 "\t.IMPORT $$dyncall,MILLICODE\n");
5187 pa_file_start_mcount ("CODE");
5188 pa_file_start_file (0);
5192 pa_linux_file_start (void)
5194 pa_file_start_file (1);
5195 pa_file_start_level ();
5196 pa_file_start_mcount ("CODE");
5200 pa_hpux64_gas_file_start (void)
5202 pa_file_start_level ();
5203 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5205 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5207 pa_file_start_file (1);
5211 pa_hpux64_hpas_file_start (void)
5213 pa_file_start_level ();
5214 pa_file_start_space (1);
5215 pa_file_start_mcount ("CODE");
5216 pa_file_start_file (0);
5220 static struct deferred_plabel *
5221 get_plabel (rtx symbol)
5223 const char *fname = XSTR (symbol, 0);
5226 /* See if we have already put this function on the list of deferred
5227 plabels. This list is generally small, so a liner search is not
5228 too ugly. If it proves too slow replace it with something faster. */
5229 for (i = 0; i < n_deferred_plabels; i++)
5230 if (strcmp (fname, XSTR (deferred_plabels[i].symbol, 0)) == 0)
5233 /* If the deferred plabel list is empty, or this entry was not found
5234 on the list, create a new entry on the list. */
5235 if (deferred_plabels == NULL || i == n_deferred_plabels)
5239 if (deferred_plabels == 0)
5240 deferred_plabels = (struct deferred_plabel *)
5241 ggc_alloc (sizeof (struct deferred_plabel));
5243 deferred_plabels = (struct deferred_plabel *)
5244 ggc_realloc (deferred_plabels,
5245 ((n_deferred_plabels + 1)
5246 * sizeof (struct deferred_plabel)));
5248 i = n_deferred_plabels++;
5249 deferred_plabels[i].internal_label = gen_label_rtx ();
5250 deferred_plabels[i].symbol = symbol;
5252 /* Gross. We have just implicitly taken the address of this
5253 function. Mark it in the same manner as assemble_name. */
5254 id = maybe_get_identifier (targetm.strip_name_encoding (fname));
5256 mark_referenced (id);
5259 return &deferred_plabels[i];
5263 output_deferred_plabels (void)
5266 /* If we have deferred plabels, then we need to switch into the data
5267 section and align it to a 4 byte boundary before we output the
5268 deferred plabels. */
5269 if (n_deferred_plabels)
5272 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5275 /* Now output the deferred plabels. */
5276 for (i = 0; i < n_deferred_plabels; i++)
5278 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5279 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5280 assemble_integer (deferred_plabels[i].symbol,
5281 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5285 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5286 /* Initialize optabs to point to HPUX long double emulation routines. */
5288 pa_hpux_init_libfuncs (void)
5290 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5291 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5292 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5293 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5294 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5295 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5296 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5297 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5298 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5300 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5301 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5302 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5303 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5304 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5305 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5306 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5308 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5309 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5310 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5311 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5313 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5314 ? "__U_Qfcnvfxt_quad_to_sgl"
5315 : "_U_Qfcnvfxt_quad_to_sgl");
5316 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5317 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5318 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5320 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5321 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5325 /* HP's millicode routines mean something special to the assembler.
5326 Keep track of which ones we have used. */
5328 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5329 static void import_milli (enum millicodes);
5330 static char imported[(int) end1000];
5331 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5332 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5333 #define MILLI_START 10
5336 import_milli (enum millicodes code)
5338 char str[sizeof (import_string)];
5340 if (!imported[(int) code])
5342 imported[(int) code] = 1;
5343 strcpy (str, import_string);
5344 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5345 output_asm_insn (str, 0);
5349 /* The register constraints have put the operands and return value in
5350 the proper registers. */
5353 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5355 import_milli (mulI);
5356 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5359 /* Emit the rtl for doing a division by a constant. */
5361 /* Do magic division millicodes exist for this value? */
5362 const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0, 1, 1};
5364 /* We'll use an array to keep track of the magic millicodes and
5365 whether or not we've used them already. [n][0] is signed, [n][1] is
5368 static int div_milli[16][2];
5371 emit_hpdiv_const (rtx *operands, int unsignedp)
5373 if (GET_CODE (operands[2]) == CONST_INT
5374 && INTVAL (operands[2]) > 0
5375 && INTVAL (operands[2]) < 16
5376 && magic_milli[INTVAL (operands[2])])
5378 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5380 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5384 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5385 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5387 gen_rtx_REG (SImode, 26),
5389 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5390 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5391 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5392 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5393 gen_rtx_CLOBBER (VOIDmode, ret))));
5394 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5401 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5405 /* If the divisor is a constant, try to use one of the special
5407 if (GET_CODE (operands[0]) == CONST_INT)
5409 static char buf[100];
5410 divisor = INTVAL (operands[0]);
5411 if (!div_milli[divisor][unsignedp])
5413 div_milli[divisor][unsignedp] = 1;
5415 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5417 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5421 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5422 INTVAL (operands[0]));
5423 return output_millicode_call (insn,
5424 gen_rtx_SYMBOL_REF (SImode, buf));
5428 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5429 INTVAL (operands[0]));
5430 return output_millicode_call (insn,
5431 gen_rtx_SYMBOL_REF (SImode, buf));
5434 /* Divisor isn't a special constant. */
5439 import_milli (divU);
5440 return output_millicode_call (insn,
5441 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5445 import_milli (divI);
5446 return output_millicode_call (insn,
5447 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5452 /* Output a $$rem millicode to do mod. */
5455 output_mod_insn (int unsignedp, rtx insn)
5459 import_milli (remU);
5460 return output_millicode_call (insn,
5461 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5465 import_milli (remI);
5466 return output_millicode_call (insn,
5467 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5472 output_arg_descriptor (rtx call_insn)
5474 const char *arg_regs[4];
5475 enum machine_mode arg_mode;
5477 int i, output_flag = 0;
5480 /* We neither need nor want argument location descriptors for the
5481 64bit runtime environment or the ELF32 environment. */
5482 if (TARGET_64BIT || TARGET_ELF32)
5485 for (i = 0; i < 4; i++)
5488 /* Specify explicitly that no argument relocations should take place
5489 if using the portable runtime calling conventions. */
5490 if (TARGET_PORTABLE_RUNTIME)
5492 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5497 gcc_assert (GET_CODE (call_insn) == CALL_INSN);
5498 for (link = CALL_INSN_FUNCTION_USAGE (call_insn);
5499 link; link = XEXP (link, 1))
5501 rtx use = XEXP (link, 0);
5503 if (! (GET_CODE (use) == USE
5504 && GET_CODE (XEXP (use, 0)) == REG
5505 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5508 arg_mode = GET_MODE (XEXP (use, 0));
5509 regno = REGNO (XEXP (use, 0));
5510 if (regno >= 23 && regno <= 26)
5512 arg_regs[26 - regno] = "GR";
5513 if (arg_mode == DImode)
5514 arg_regs[25 - regno] = "GR";
5516 else if (regno >= 32 && regno <= 39)
5518 if (arg_mode == SFmode)
5519 arg_regs[(regno - 32) / 2] = "FR";
5522 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5523 arg_regs[(regno - 34) / 2] = "FR";
5524 arg_regs[(regno - 34) / 2 + 1] = "FU";
5526 arg_regs[(regno - 34) / 2] = "FU";
5527 arg_regs[(regno - 34) / 2 + 1] = "FR";
5532 fputs ("\t.CALL ", asm_out_file);
5533 for (i = 0; i < 4; i++)
5538 fputc (',', asm_out_file);
5539 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5542 fputc ('\n', asm_out_file);
5545 /* Return the class of any secondary reload register that is needed to
5546 move IN into a register in class CLASS using mode MODE.
5548 Profiling has showed this routine and its descendants account for
5549 a significant amount of compile time (~7%). So it has been
5550 optimized to reduce redundant computations and eliminate useless
5553 It might be worthwhile to try and make this a leaf function too. */
5556 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5558 int regno, is_symbolic;
5560 /* Trying to load a constant into a FP register during PIC code
5561 generation will require %r1 as a scratch register. */
5563 && GET_MODE_CLASS (mode) == MODE_INT
5564 && FP_REG_CLASS_P (class)
5565 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5568 /* Profiling showed the PA port spends about 1.3% of its compilation
5569 time in true_regnum from calls inside secondary_reload_class. */
5571 if (GET_CODE (in) == REG)
5574 if (regno >= FIRST_PSEUDO_REGISTER)
5575 regno = true_regnum (in);
5577 else if (GET_CODE (in) == SUBREG)
5578 regno = true_regnum (in);
5582 /* If we have something like (mem (mem (...)), we can safely assume the
5583 inner MEM will end up in a general register after reloading, so there's
5584 no need for a secondary reload. */
5585 if (GET_CODE (in) == MEM
5586 && GET_CODE (XEXP (in, 0)) == MEM)
5589 /* Handle out of range displacement for integer mode loads/stores of
5591 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5592 && GET_MODE_CLASS (mode) == MODE_INT
5593 && FP_REG_CLASS_P (class))
5594 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5595 return GENERAL_REGS;
5597 /* A SAR<->FP register copy requires a secondary register (GPR) as
5598 well as secondary memory. */
5599 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5600 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5601 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5602 return GENERAL_REGS;
5604 if (GET_CODE (in) == HIGH)
5607 /* Profiling has showed GCC spends about 2.6% of its compilation
5608 time in symbolic_operand from calls inside secondary_reload_class.
5610 We use an inline copy and only compute its return value once to avoid
5612 switch (GET_CODE (in))
5622 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5623 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5624 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5634 && read_only_operand (in, VOIDmode))
5637 if (class != R1_REGS && is_symbolic)
5643 /* In the 32-bit runtime, arguments larger than eight bytes are passed
5644 by invisible reference. As a GCC extension, we also pass anything
5645 with a zero or variable size by reference.
5647 The 64-bit runtime does not describe passing any types by invisible
5648 reference. The internals of GCC can't currently handle passing
5649 empty structures, and zero or variable length arrays when they are
5650 not passed entirely on the stack or by reference. Thus, as a GCC
5651 extension, we pass these types by reference. The HP compiler doesn't
5652 support these types, so hopefully there shouldn't be any compatibility
5653 issues. This may have to be revisited when HP releases a C99 compiler
5654 or updates the ABI. */
5657 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
5658 enum machine_mode mode, tree type,
5659 bool named ATTRIBUTE_UNUSED)
5664 size = int_size_in_bytes (type);
5666 size = GET_MODE_SIZE (mode);
5671 return size <= 0 || size > 8;
5675 function_arg_padding (enum machine_mode mode, tree type)
5678 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5680 /* Return none if justification is not required. */
5682 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5683 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5686 /* The directions set here are ignored when a BLKmode argument larger
5687 than a word is placed in a register. Different code is used for
5688 the stack and registers. This makes it difficult to have a
5689 consistent data representation for both the stack and registers.
5690 For both runtimes, the justification and padding for arguments on
5691 the stack and in registers should be identical. */
5693 /* The 64-bit runtime specifies left justification for aggregates. */
5696 /* The 32-bit runtime architecture specifies right justification.
5697 When the argument is passed on the stack, the argument is padded
5698 with garbage on the left. The HP compiler pads with zeros. */
5702 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5709 /* Do what is necessary for `va_start'. We look at the current function
5710 to determine if stdargs or varargs is used and fill in an initial
5711 va_list. A pointer to this constructor is returned. */
5714 hppa_builtin_saveregs (void)
5717 tree fntype = TREE_TYPE (current_function_decl);
5718 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5719 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5720 != void_type_node)))
5721 ? UNITS_PER_WORD : 0);
5724 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5726 offset = current_function_arg_offset_rtx;
5732 /* Adjust for varargs/stdarg differences. */
5734 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5736 offset = current_function_arg_offset_rtx;
5738 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5739 from the incoming arg pointer and growing to larger addresses. */
5740 for (i = 26, off = -64; i >= 19; i--, off += 8)
5741 emit_move_insn (gen_rtx_MEM (word_mode,
5742 plus_constant (arg_pointer_rtx, off)),
5743 gen_rtx_REG (word_mode, i));
5745 /* The incoming args pointer points just beyond the flushback area;
5746 normally this is not a serious concern. However, when we are doing
5747 varargs/stdargs we want to make the arg pointer point to the start
5748 of the incoming argument area. */
5749 emit_move_insn (virtual_incoming_args_rtx,
5750 plus_constant (arg_pointer_rtx, -64));
5752 /* Now return a pointer to the first anonymous argument. */
5753 return copy_to_reg (expand_binop (Pmode, add_optab,
5754 virtual_incoming_args_rtx,
5755 offset, 0, 0, OPTAB_LIB_WIDEN));
5758 /* Store general registers on the stack. */
5759 dest = gen_rtx_MEM (BLKmode,
5760 plus_constant (current_function_internal_arg_pointer,
5762 set_mem_alias_set (dest, get_varargs_alias_set ());
5763 set_mem_align (dest, BITS_PER_WORD);
5764 move_block_from_reg (23, dest, 4);
5766 /* move_block_from_reg will emit code to store the argument registers
5767 individually as scalar stores.
5769 However, other insns may later load from the same addresses for
5770 a structure load (passing a struct to a varargs routine).
5772 The alias code assumes that such aliasing can never happen, so we
5773 have to keep memory referencing insns from moving up beyond the
5774 last argument register store. So we emit a blockage insn here. */
5775 emit_insn (gen_blockage ());
5777 return copy_to_reg (expand_binop (Pmode, add_optab,
5778 current_function_internal_arg_pointer,
5779 offset, 0, 0, OPTAB_LIB_WIDEN));
5783 hppa_va_start (tree valist, rtx nextarg)
5785 nextarg = expand_builtin_saveregs ();
5786 std_expand_builtin_va_start (valist, nextarg);
5790 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
5794 /* Args grow upward. We can use the generic routines. */
5795 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
5797 else /* !TARGET_64BIT */
5799 tree ptr = build_pointer_type (type);
5802 unsigned int size, ofs;
5805 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
5809 ptr = build_pointer_type (type);
5811 size = int_size_in_bytes (type);
5812 valist_type = TREE_TYPE (valist);
5814 /* Args grow down. Not handled by generic routines. */
5816 u = fold_convert (valist_type, size_in_bytes (type));
5817 t = build (MINUS_EXPR, valist_type, valist, u);
5819 /* Copied from va-pa.h, but we probably don't need to align to
5820 word size, since we generate and preserve that invariant. */
5821 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
5822 t = build (BIT_AND_EXPR, valist_type, t, u);
5824 t = build (MODIFY_EXPR, valist_type, valist, t);
5826 ofs = (8 - size) % 4;
5829 u = fold_convert (valist_type, size_int (ofs));
5830 t = build (PLUS_EXPR, valist_type, t, u);
5833 t = fold_convert (ptr, t);
5834 t = build_fold_indirect_ref (t);
5837 t = build_fold_indirect_ref (t);
5843 /* True if MODE is valid for the target. By "valid", we mean able to
5844 be manipulated in non-trivial ways. In particular, this means all
5845 the arithmetic is supported.
5847 Currently, TImode is not valid as the HP 64-bit runtime documentation
5848 doesn't document the alignment and calling conventions for this type.
5849 Thus, we return false when PRECISION is 2 * BITS_PER_WORD and
5850 2 * BITS_PER_WORD isn't equal LONG_LONG_TYPE_SIZE. */
5853 pa_scalar_mode_supported_p (enum machine_mode mode)
5855 int precision = GET_MODE_PRECISION (mode);
5857 switch (GET_MODE_CLASS (mode))
5859 case MODE_PARTIAL_INT:
5861 if (precision == CHAR_TYPE_SIZE)
5863 if (precision == SHORT_TYPE_SIZE)
5865 if (precision == INT_TYPE_SIZE)
5867 if (precision == LONG_TYPE_SIZE)
5869 if (precision == LONG_LONG_TYPE_SIZE)
5874 if (precision == FLOAT_TYPE_SIZE)
5876 if (precision == DOUBLE_TYPE_SIZE)
5878 if (precision == LONG_DOUBLE_TYPE_SIZE)
5887 /* This routine handles all the normal conditional branch sequences we
5888 might need to generate. It handles compare immediate vs compare
5889 register, nullification of delay slots, varying length branches,
5890 negated branches, and all combinations of the above. It returns the
5891 output appropriate to emit the branch corresponding to all given
5895 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
5897 static char buf[100];
5901 /* A conditional branch to the following instruction (e.g. the delay slot)
5902 is asking for a disaster. This can happen when not optimizing and
5903 when jump optimization fails.
5905 While it is usually safe to emit nothing, this can fail if the
5906 preceding instruction is a nullified branch with an empty delay
5907 slot and the same branch target as this branch. We could check
5908 for this but jump optimization should eliminate nop jumps. It
5909 is always safe to emit a nop. */
5910 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5913 /* The doubleword form of the cmpib instruction doesn't have the LEU
5914 and GTU conditions while the cmpb instruction does. Since we accept
5915 zero for cmpb, we must ensure that we use cmpb for the comparison. */
5916 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
5917 operands[2] = gen_rtx_REG (DImode, 0);
5919 /* If this is a long branch with its delay slot unfilled, set `nullify'
5920 as it can nullify the delay slot and save a nop. */
5921 if (length == 8 && dbr_sequence_length () == 0)
5924 /* If this is a short forward conditional branch which did not get
5925 its delay slot filled, the delay slot can still be nullified. */
5926 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5927 nullify = forward_branch_p (insn);
5929 /* A forward branch over a single nullified insn can be done with a
5930 comclr instruction. This avoids a single cycle penalty due to
5931 mis-predicted branch if we fall through (branch not taken). */
5933 && next_real_insn (insn) != 0
5934 && get_attr_length (next_real_insn (insn)) == 4
5935 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5941 /* All short conditional branches except backwards with an unfilled
5945 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5947 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5948 if (GET_MODE (operands[1]) == DImode)
5951 strcat (buf, "%B3");
5953 strcat (buf, "%S3");
5955 strcat (buf, " %2,%r1,%%r0");
5957 strcat (buf, ",n %2,%r1,%0");
5959 strcat (buf, " %2,%r1,%0");
5962 /* All long conditionals. Note a short backward branch with an
5963 unfilled delay slot is treated just like a long backward branch
5964 with an unfilled delay slot. */
5966 /* Handle weird backwards branch with a filled delay slot
5967 with is nullified. */
5968 if (dbr_sequence_length () != 0
5969 && ! forward_branch_p (insn)
5972 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5973 if (GET_MODE (operands[1]) == DImode)
5976 strcat (buf, "%S3");
5978 strcat (buf, "%B3");
5979 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5981 /* Handle short backwards branch with an unfilled delay slot.
5982 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5983 taken and untaken branches. */
5984 else if (dbr_sequence_length () == 0
5985 && ! forward_branch_p (insn)
5986 && INSN_ADDRESSES_SET_P ()
5987 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5988 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5990 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5991 if (GET_MODE (operands[1]) == DImode)
5994 strcat (buf, "%B3 %2,%r1,%0%#");
5996 strcat (buf, "%S3 %2,%r1,%0%#");
6000 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6001 if (GET_MODE (operands[1]) == DImode)
6004 strcat (buf, "%S3");
6006 strcat (buf, "%B3");
6008 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6010 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6016 xoperands[0] = operands[0];
6017 xoperands[1] = operands[1];
6018 xoperands[2] = operands[2];
6019 xoperands[3] = operands[3];
6021 /* The reversed conditional branch must branch over one additional
6022 instruction if the delay slot is filled. If the delay slot
6023 is empty, the instruction after the reversed condition branch
6024 must be nullified. */
6025 nullify = dbr_sequence_length () == 0;
6026 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6028 /* Create a reversed conditional branch which branches around
6029 the following insns. */
6030 if (GET_MODE (operands[1]) != DImode)
6036 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6039 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6045 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6048 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6057 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6060 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6066 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6069 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6073 output_asm_insn (buf, xoperands);
6074 return output_lbranch (operands[0], insn);
6082 /* This routine handles long unconditional branches that exceed the
6083 maximum range of a simple branch instruction. */
6086 output_lbranch (rtx dest, rtx insn)
6090 xoperands[0] = dest;
6092 /* First, free up the delay slot. */
6093 if (dbr_sequence_length () != 0)
6095 /* We can't handle a jump in the delay slot. */
6096 gcc_assert (GET_CODE (NEXT_INSN (insn)) != JUMP_INSN);
6098 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6101 /* Now delete the delay insn. */
6102 PUT_CODE (NEXT_INSN (insn), NOTE);
6103 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6104 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6107 /* Output an insn to save %r1. The runtime documentation doesn't
6108 specify whether the "Clean Up" slot in the callers frame can
6109 be clobbered by the callee. It isn't copied by HP's builtin
6110 alloca, so this suggests that it can be clobbered if necessary.
6111 The "Static Link" location is copied by HP builtin alloca, so
6112 we avoid using it. Using the cleanup slot might be a problem
6113 if we have to interoperate with languages that pass cleanup
6114 information. However, it should be possible to handle these
6115 situations with GCC's asm feature.
6117 The "Current RP" slot is reserved for the called procedure, so
6118 we try to use it when we don't have a frame of our own. It's
6119 rather unlikely that we won't have a frame when we need to emit
6122 Really the way to go long term is a register scavenger; goto
6123 the target of the jump and find a register which we can use
6124 as a scratch to hold the value in %r1. Then, we wouldn't have
6125 to free up the delay slot or clobber a slot that may be needed
6126 for other purposes. */
6129 if (actual_fsize == 0 && !regs_ever_live[2])
6130 /* Use the return pointer slot in the frame marker. */
6131 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6133 /* Use the slot at -40 in the frame marker since HP builtin
6134 alloca doesn't copy it. */
6135 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6139 if (actual_fsize == 0 && !regs_ever_live[2])
6140 /* Use the return pointer slot in the frame marker. */
6141 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6143 /* Use the "Clean Up" slot in the frame marker. In GCC,
6144 the only other use of this location is for copying a
6145 floating point double argument from a floating-point
6146 register to two general registers. The copy is done
6147 as an "atomic" operation when outputting a call, so it
6148 won't interfere with our using the location here. */
6149 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6152 if (TARGET_PORTABLE_RUNTIME)
6154 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6155 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6156 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6160 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6161 if (TARGET_SOM || !TARGET_GAS)
6163 xoperands[1] = gen_label_rtx ();
6164 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6165 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6166 CODE_LABEL_NUMBER (xoperands[1]));
6167 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6171 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6172 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6174 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6177 /* Now output a very long branch to the original target. */
6178 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6180 /* Now restore the value of %r1 in the delay slot. */
6183 if (actual_fsize == 0 && !regs_ever_live[2])
6184 return "ldd -16(%%r30),%%r1";
6186 return "ldd -40(%%r30),%%r1";
6190 if (actual_fsize == 0 && !regs_ever_live[2])
6191 return "ldw -20(%%r30),%%r1";
6193 return "ldw -12(%%r30),%%r1";
6197 /* This routine handles all the branch-on-bit conditional branch sequences we
6198 might need to generate. It handles nullification of delay slots,
6199 varying length branches, negated branches and all combinations of the
6200 above. it returns the appropriate output template to emit the branch. */
6203 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6204 int negated, rtx insn, int which)
6206 static char buf[100];
6209 /* A conditional branch to the following instruction (e.g. the delay slot) is
6210 asking for a disaster. I do not think this can happen as this pattern
6211 is only used when optimizing; jump optimization should eliminate the
6212 jump. But be prepared just in case. */
6214 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6217 /* If this is a long branch with its delay slot unfilled, set `nullify'
6218 as it can nullify the delay slot and save a nop. */
6219 if (length == 8 && dbr_sequence_length () == 0)
6222 /* If this is a short forward conditional branch which did not get
6223 its delay slot filled, the delay slot can still be nullified. */
6224 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6225 nullify = forward_branch_p (insn);
6227 /* A forward branch over a single nullified insn can be done with a
6228 extrs instruction. This avoids a single cycle penalty due to
6229 mis-predicted branch if we fall through (branch not taken). */
6232 && next_real_insn (insn) != 0
6233 && get_attr_length (next_real_insn (insn)) == 4
6234 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6241 /* All short conditional branches except backwards with an unfilled
6245 strcpy (buf, "{extrs,|extrw,s,}");
6247 strcpy (buf, "bb,");
6248 if (useskip && GET_MODE (operands[0]) == DImode)
6249 strcpy (buf, "extrd,s,*");
6250 else if (GET_MODE (operands[0]) == DImode)
6251 strcpy (buf, "bb,*");
6252 if ((which == 0 && negated)
6253 || (which == 1 && ! negated))
6258 strcat (buf, " %0,%1,1,%%r0");
6259 else if (nullify && negated)
6260 strcat (buf, ",n %0,%1,%3");
6261 else if (nullify && ! negated)
6262 strcat (buf, ",n %0,%1,%2");
6263 else if (! nullify && negated)
6264 strcat (buf, "%0,%1,%3");
6265 else if (! nullify && ! negated)
6266 strcat (buf, " %0,%1,%2");
6269 /* All long conditionals. Note a short backward branch with an
6270 unfilled delay slot is treated just like a long backward branch
6271 with an unfilled delay slot. */
6273 /* Handle weird backwards branch with a filled delay slot
6274 with is nullified. */
6275 if (dbr_sequence_length () != 0
6276 && ! forward_branch_p (insn)
6279 strcpy (buf, "bb,");
6280 if (GET_MODE (operands[0]) == DImode)
6282 if ((which == 0 && negated)
6283 || (which == 1 && ! negated))
6288 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6290 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6292 /* Handle short backwards branch with an unfilled delay slot.
6293 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6294 taken and untaken branches. */
6295 else if (dbr_sequence_length () == 0
6296 && ! forward_branch_p (insn)
6297 && INSN_ADDRESSES_SET_P ()
6298 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6299 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6301 strcpy (buf, "bb,");
6302 if (GET_MODE (operands[0]) == DImode)
6304 if ((which == 0 && negated)
6305 || (which == 1 && ! negated))
6310 strcat (buf, " %0,%1,%3%#");
6312 strcat (buf, " %0,%1,%2%#");
6316 strcpy (buf, "{extrs,|extrw,s,}");
6317 if (GET_MODE (operands[0]) == DImode)
6318 strcpy (buf, "extrd,s,*");
6319 if ((which == 0 && negated)
6320 || (which == 1 && ! negated))
6324 if (nullify && negated)
6325 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6326 else if (nullify && ! negated)
6327 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6329 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6331 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6341 /* This routine handles all the branch-on-variable-bit conditional branch
6342 sequences we might need to generate. It handles nullification of delay
6343 slots, varying length branches, negated branches and all combinations
6344 of the above. it returns the appropriate output template to emit the
6348 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6349 int negated, rtx insn, int which)
6351 static char buf[100];
6354 /* A conditional branch to the following instruction (e.g. the delay slot) is
6355 asking for a disaster. I do not think this can happen as this pattern
6356 is only used when optimizing; jump optimization should eliminate the
6357 jump. But be prepared just in case. */
6359 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6362 /* If this is a long branch with its delay slot unfilled, set `nullify'
6363 as it can nullify the delay slot and save a nop. */
6364 if (length == 8 && dbr_sequence_length () == 0)
6367 /* If this is a short forward conditional branch which did not get
6368 its delay slot filled, the delay slot can still be nullified. */
6369 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6370 nullify = forward_branch_p (insn);
6372 /* A forward branch over a single nullified insn can be done with a
6373 extrs instruction. This avoids a single cycle penalty due to
6374 mis-predicted branch if we fall through (branch not taken). */
6377 && next_real_insn (insn) != 0
6378 && get_attr_length (next_real_insn (insn)) == 4
6379 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6386 /* All short conditional branches except backwards with an unfilled
6390 strcpy (buf, "{vextrs,|extrw,s,}");
6392 strcpy (buf, "{bvb,|bb,}");
6393 if (useskip && GET_MODE (operands[0]) == DImode)
6394 strcpy (buf, "extrd,s,*");
6395 else if (GET_MODE (operands[0]) == DImode)
6396 strcpy (buf, "bb,*");
6397 if ((which == 0 && negated)
6398 || (which == 1 && ! negated))
6403 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6404 else if (nullify && negated)
6405 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6406 else if (nullify && ! negated)
6407 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6408 else if (! nullify && negated)
6409 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6410 else if (! nullify && ! negated)
6411 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6414 /* All long conditionals. Note a short backward branch with an
6415 unfilled delay slot is treated just like a long backward branch
6416 with an unfilled delay slot. */
6418 /* Handle weird backwards branch with a filled delay slot
6419 with is nullified. */
6420 if (dbr_sequence_length () != 0
6421 && ! forward_branch_p (insn)
6424 strcpy (buf, "{bvb,|bb,}");
6425 if (GET_MODE (operands[0]) == DImode)
6427 if ((which == 0 && negated)
6428 || (which == 1 && ! negated))
6433 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6435 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6437 /* Handle short backwards branch with an unfilled delay slot.
6438 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6439 taken and untaken branches. */
6440 else if (dbr_sequence_length () == 0
6441 && ! forward_branch_p (insn)
6442 && INSN_ADDRESSES_SET_P ()
6443 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6444 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6446 strcpy (buf, "{bvb,|bb,}");
6447 if (GET_MODE (operands[0]) == DImode)
6449 if ((which == 0 && negated)
6450 || (which == 1 && ! negated))
6455 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6457 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6461 strcpy (buf, "{vextrs,|extrw,s,}");
6462 if (GET_MODE (operands[0]) == DImode)
6463 strcpy (buf, "extrd,s,*");
6464 if ((which == 0 && negated)
6465 || (which == 1 && ! negated))
6469 if (nullify && negated)
6470 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6471 else if (nullify && ! negated)
6472 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6474 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6476 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6486 /* Return the output template for emitting a dbra type insn.
6488 Note it may perform some output operations on its own before
6489 returning the final output string. */
6491 output_dbra (rtx *operands, rtx insn, int which_alternative)
6494 /* A conditional branch to the following instruction (e.g. the delay slot) is
6495 asking for a disaster. Be prepared! */
6497 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6499 if (which_alternative == 0)
6500 return "ldo %1(%0),%0";
6501 else if (which_alternative == 1)
6503 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6504 output_asm_insn ("ldw -16(%%r30),%4", operands);
6505 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6506 return "{fldws|fldw} -16(%%r30),%0";
6510 output_asm_insn ("ldw %0,%4", operands);
6511 return "ldo %1(%4),%4\n\tstw %4,%0";
6515 if (which_alternative == 0)
6517 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6518 int length = get_attr_length (insn);
6520 /* If this is a long branch with its delay slot unfilled, set `nullify'
6521 as it can nullify the delay slot and save a nop. */
6522 if (length == 8 && dbr_sequence_length () == 0)
6525 /* If this is a short forward conditional branch which did not get
6526 its delay slot filled, the delay slot can still be nullified. */
6527 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6528 nullify = forward_branch_p (insn);
6534 return "addib,%C2,n %1,%0,%3";
6536 return "addib,%C2 %1,%0,%3";
6539 /* Handle weird backwards branch with a fulled delay slot
6540 which is nullified. */
6541 if (dbr_sequence_length () != 0
6542 && ! forward_branch_p (insn)
6544 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6545 /* Handle short backwards branch with an unfilled delay slot.
6546 Using a addb;nop rather than addi;bl saves 1 cycle for both
6547 taken and untaken branches. */
6548 else if (dbr_sequence_length () == 0
6549 && ! forward_branch_p (insn)
6550 && INSN_ADDRESSES_SET_P ()
6551 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6552 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6553 return "addib,%C2 %1,%0,%3%#";
6555 /* Handle normal cases. */
6557 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6559 return "addi,%N2 %1,%0,%0\n\tb %3";
6566 /* Deal with gross reload from FP register case. */
6567 else if (which_alternative == 1)
6569 /* Move loop counter from FP register to MEM then into a GR,
6570 increment the GR, store the GR into MEM, and finally reload
6571 the FP register from MEM from within the branch's delay slot. */
6572 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6574 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6575 if (get_attr_length (insn) == 24)
6576 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6578 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6580 /* Deal with gross reload from memory case. */
6583 /* Reload loop counter from memory, the store back to memory
6584 happens in the branch's delay slot. */
6585 output_asm_insn ("ldw %0,%4", operands);
6586 if (get_attr_length (insn) == 12)
6587 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6589 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6593 /* Return the output template for emitting a dbra type insn.
6595 Note it may perform some output operations on its own before
6596 returning the final output string. */
6598 output_movb (rtx *operands, rtx insn, int which_alternative,
6599 int reverse_comparison)
6602 /* A conditional branch to the following instruction (e.g. the delay slot) is
6603 asking for a disaster. Be prepared! */
6605 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6607 if (which_alternative == 0)
6608 return "copy %1,%0";
6609 else if (which_alternative == 1)
6611 output_asm_insn ("stw %1,-16(%%r30)", operands);
6612 return "{fldws|fldw} -16(%%r30),%0";
6614 else if (which_alternative == 2)
6620 /* Support the second variant. */
6621 if (reverse_comparison)
6622 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6624 if (which_alternative == 0)
6626 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6627 int length = get_attr_length (insn);
6629 /* If this is a long branch with its delay slot unfilled, set `nullify'
6630 as it can nullify the delay slot and save a nop. */
6631 if (length == 8 && dbr_sequence_length () == 0)
6634 /* If this is a short forward conditional branch which did not get
6635 its delay slot filled, the delay slot can still be nullified. */
6636 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6637 nullify = forward_branch_p (insn);
6643 return "movb,%C2,n %1,%0,%3";
6645 return "movb,%C2 %1,%0,%3";
6648 /* Handle weird backwards branch with a filled delay slot
6649 which is nullified. */
6650 if (dbr_sequence_length () != 0
6651 && ! forward_branch_p (insn)
6653 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6655 /* Handle short backwards branch with an unfilled delay slot.
6656 Using a movb;nop rather than or;bl saves 1 cycle for both
6657 taken and untaken branches. */
6658 else if (dbr_sequence_length () == 0
6659 && ! forward_branch_p (insn)
6660 && INSN_ADDRESSES_SET_P ()
6661 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6662 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6663 return "movb,%C2 %1,%0,%3%#";
6664 /* Handle normal cases. */
6666 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6668 return "or,%N2 %1,%%r0,%0\n\tb %3";
6674 /* Deal with gross reload from FP register case. */
6675 else if (which_alternative == 1)
6677 /* Move loop counter from FP register to MEM then into a GR,
6678 increment the GR, store the GR into MEM, and finally reload
6679 the FP register from MEM from within the branch's delay slot. */
6680 output_asm_insn ("stw %1,-16(%%r30)", operands);
6681 if (get_attr_length (insn) == 12)
6682 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6684 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6686 /* Deal with gross reload from memory case. */
6687 else if (which_alternative == 2)
6689 /* Reload loop counter from memory, the store back to memory
6690 happens in the branch's delay slot. */
6691 if (get_attr_length (insn) == 8)
6692 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6694 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6696 /* Handle SAR as a destination. */
6699 if (get_attr_length (insn) == 8)
6700 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6702 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
6706 /* Copy any FP arguments in INSN into integer registers. */
6708 copy_fp_args (rtx insn)
6713 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6715 int arg_mode, regno;
6716 rtx use = XEXP (link, 0);
6718 if (! (GET_CODE (use) == USE
6719 && GET_CODE (XEXP (use, 0)) == REG
6720 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6723 arg_mode = GET_MODE (XEXP (use, 0));
6724 regno = REGNO (XEXP (use, 0));
6726 /* Is it a floating point register? */
6727 if (regno >= 32 && regno <= 39)
6729 /* Copy the FP register into an integer register via memory. */
6730 if (arg_mode == SFmode)
6732 xoperands[0] = XEXP (use, 0);
6733 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6734 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6735 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6739 xoperands[0] = XEXP (use, 0);
6740 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6741 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6742 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6743 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6749 /* Compute length of the FP argument copy sequence for INSN. */
6751 length_fp_args (rtx insn)
6756 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6758 int arg_mode, regno;
6759 rtx use = XEXP (link, 0);
6761 if (! (GET_CODE (use) == USE
6762 && GET_CODE (XEXP (use, 0)) == REG
6763 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6766 arg_mode = GET_MODE (XEXP (use, 0));
6767 regno = REGNO (XEXP (use, 0));
6769 /* Is it a floating point register? */
6770 if (regno >= 32 && regno <= 39)
6772 if (arg_mode == SFmode)
6782 /* Return the attribute length for the millicode call instruction INSN.
6783 The length must match the code generated by output_millicode_call.
6784 We include the delay slot in the returned length as it is better to
6785 over estimate the length than to under estimate it. */
6788 attr_length_millicode_call (rtx insn)
6790 unsigned long distance = -1;
6791 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
6793 if (INSN_ADDRESSES_SET_P ())
6795 distance = (total + insn_current_reference_address (insn));
6796 if (distance < total)
6802 if (!TARGET_LONG_CALLS && distance < 7600000)
6807 else if (TARGET_PORTABLE_RUNTIME)
6811 if (!TARGET_LONG_CALLS && distance < 240000)
6814 if (TARGET_LONG_ABS_CALL && !flag_pic)
6821 /* INSN is a function call. It may have an unconditional jump
6824 CALL_DEST is the routine we are calling. */
6827 output_millicode_call (rtx insn, rtx call_dest)
6829 int attr_length = get_attr_length (insn);
6830 int seq_length = dbr_sequence_length ();
6835 xoperands[0] = call_dest;
6836 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6838 /* Handle the common case where we are sure that the branch will
6839 reach the beginning of the $CODE$ subspace. The within reach
6840 form of the $$sh_func_adrs call has a length of 28. Because
6841 it has an attribute type of multi, it never has a nonzero
6842 sequence length. The length of the $$sh_func_adrs is the same
6843 as certain out of reach PIC calls to other routines. */
6844 if (!TARGET_LONG_CALLS
6845 && ((seq_length == 0
6846 && (attr_length == 12
6847 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6848 || (seq_length != 0 && attr_length == 8)))
6850 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6856 /* It might seem that one insn could be saved by accessing
6857 the millicode function using the linkage table. However,
6858 this doesn't work in shared libraries and other dynamically
6859 loaded objects. Using a pc-relative sequence also avoids
6860 problems related to the implicit use of the gp register. */
6861 output_asm_insn ("b,l .+8,%%r1", xoperands);
6865 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6866 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6870 xoperands[1] = gen_label_rtx ();
6871 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6872 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6873 CODE_LABEL_NUMBER (xoperands[1]));
6874 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6877 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6879 else if (TARGET_PORTABLE_RUNTIME)
6881 /* Pure portable runtime doesn't allow be/ble; we also don't
6882 have PIC support in the assembler/linker, so this sequence
6885 /* Get the address of our target into %r1. */
6886 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6887 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6889 /* Get our return address into %r31. */
6890 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6891 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6893 /* Jump to our target address in %r1. */
6894 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6898 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6900 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6902 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6906 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6907 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6909 if (TARGET_SOM || !TARGET_GAS)
6911 /* The HP assembler can generate relocations for the
6912 difference of two symbols. GAS can do this for a
6913 millicode symbol but not an arbitrary external
6914 symbol when generating SOM output. */
6915 xoperands[1] = gen_label_rtx ();
6916 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6917 CODE_LABEL_NUMBER (xoperands[1]));
6918 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6919 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6923 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6924 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6928 /* Jump to our target address in %r1. */
6929 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6933 if (seq_length == 0)
6934 output_asm_insn ("nop", xoperands);
6936 /* We are done if there isn't a jump in the delay slot. */
6937 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6940 /* This call has an unconditional jump in its delay slot. */
6941 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6943 /* See if the return address can be adjusted. Use the containing
6944 sequence insn's address. */
6945 if (INSN_ADDRESSES_SET_P ())
6947 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6948 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6949 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6951 if (VAL_14_BITS_P (distance))
6953 xoperands[1] = gen_label_rtx ();
6954 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6955 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6956 CODE_LABEL_NUMBER (xoperands[1]));
6959 /* ??? This branch may not reach its target. */
6960 output_asm_insn ("nop\n\tb,n %0", xoperands);
6963 /* ??? This branch may not reach its target. */
6964 output_asm_insn ("nop\n\tb,n %0", xoperands);
6966 /* Delete the jump. */
6967 PUT_CODE (NEXT_INSN (insn), NOTE);
6968 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6969 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6974 /* Return the attribute length of the call instruction INSN. The SIBCALL
6975 flag indicates whether INSN is a regular call or a sibling call. The
6976 length returned must be longer than the code actually generated by
6977 output_call. Since branch shortening is done before delay branch
6978 sequencing, there is no way to determine whether or not the delay
6979 slot will be filled during branch shortening. Even when the delay
6980 slot is filled, we may have to add a nop if the delay slot contains
6981 a branch that can't reach its target. Thus, we always have to include
6982 the delay slot in the length estimate. This used to be done in
6983 pa_adjust_insn_length but we do it here now as some sequences always
6984 fill the delay slot and we can save four bytes in the estimate for
6988 attr_length_call (rtx insn, int sibcall)
6994 rtx pat = PATTERN (insn);
6995 unsigned long distance = -1;
6997 if (INSN_ADDRESSES_SET_P ())
6999 unsigned long total;
7001 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7002 distance = (total + insn_current_reference_address (insn));
7003 if (distance < total)
7007 /* Determine if this is a local call. */
7008 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7009 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7011 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7013 call_decl = SYMBOL_REF_DECL (call_dest);
7014 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7016 /* pc-relative branch. */
7017 if (!TARGET_LONG_CALLS
7018 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7019 || distance < 240000))
7022 /* 64-bit plabel sequence. */
7023 else if (TARGET_64BIT && !local_call)
7024 length += sibcall ? 28 : 24;
7026 /* non-pic long absolute branch sequence. */
7027 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7030 /* long pc-relative branch sequence. */
7031 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7032 || (TARGET_64BIT && !TARGET_GAS)
7033 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7037 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7041 /* 32-bit plabel sequence. */
7047 length += length_fp_args (insn);
7057 if (!TARGET_NO_SPACE_REGS)
7065 /* INSN is a function call. It may have an unconditional jump
7068 CALL_DEST is the routine we are calling. */
7071 output_call (rtx insn, rtx call_dest, int sibcall)
7073 int delay_insn_deleted = 0;
7074 int delay_slot_filled = 0;
7075 int seq_length = dbr_sequence_length ();
7076 tree call_decl = SYMBOL_REF_DECL (call_dest);
7077 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7080 xoperands[0] = call_dest;
7082 /* Handle the common case where we're sure that the branch will reach
7083 the beginning of the "$CODE$" subspace. This is the beginning of
7084 the current function if we are in a named section. */
7085 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7087 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7088 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7092 if (TARGET_64BIT && !local_call)
7094 /* ??? As far as I can tell, the HP linker doesn't support the
7095 long pc-relative sequence described in the 64-bit runtime
7096 architecture. So, we use a slightly longer indirect call. */
7097 struct deferred_plabel *p = get_plabel (call_dest);
7099 xoperands[0] = p->internal_label;
7100 xoperands[1] = gen_label_rtx ();
7102 /* If this isn't a sibcall, we put the load of %r27 into the
7103 delay slot. We can't do this in a sibcall as we don't
7104 have a second call-clobbered scratch register available. */
7106 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7109 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7112 /* Now delete the delay insn. */
7113 PUT_CODE (NEXT_INSN (insn), NOTE);
7114 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7115 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7116 delay_insn_deleted = 1;
7119 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7120 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7121 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7125 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7126 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7127 output_asm_insn ("bve (%%r1)", xoperands);
7131 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7132 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7133 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7134 delay_slot_filled = 1;
7139 int indirect_call = 0;
7141 /* Emit a long call. There are several different sequences
7142 of increasing length and complexity. In most cases,
7143 they don't allow an instruction in the delay slot. */
7144 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7145 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7146 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7151 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7153 && (!TARGET_PA_20 || indirect_call))
7155 /* A non-jump insn in the delay slot. By definition we can
7156 emit this insn before the call (and in fact before argument
7158 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0,
7161 /* Now delete the delay insn. */
7162 PUT_CODE (NEXT_INSN (insn), NOTE);
7163 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7164 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7165 delay_insn_deleted = 1;
7168 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7170 /* This is the best sequence for making long calls in
7171 non-pic code. Unfortunately, GNU ld doesn't provide
7172 the stub needed for external calls, and GAS's support
7173 for this with the SOM linker is buggy. It is safe
7174 to use this for local calls. */
7175 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7177 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7181 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7184 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7186 output_asm_insn ("copy %%r31,%%r2", xoperands);
7187 delay_slot_filled = 1;
7192 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7193 || (TARGET_64BIT && !TARGET_GAS))
7195 /* The HP assembler and linker can handle relocations
7196 for the difference of two symbols. GAS and the HP
7197 linker can't do this when one of the symbols is
7199 xoperands[1] = gen_label_rtx ();
7200 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7201 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7202 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7203 CODE_LABEL_NUMBER (xoperands[1]));
7204 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7206 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7208 /* GAS currently can't generate the relocations that
7209 are needed for the SOM linker under HP-UX using this
7210 sequence. The GNU linker doesn't generate the stubs
7211 that are needed for external calls on TARGET_ELF32
7212 with this sequence. For now, we have to use a
7213 longer plabel sequence when using GAS. */
7214 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7215 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7217 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7222 /* Emit a long plabel-based call sequence. This is
7223 essentially an inline implementation of $$dyncall.
7224 We don't actually try to call $$dyncall as this is
7225 as difficult as calling the function itself. */
7226 struct deferred_plabel *p = get_plabel (call_dest);
7228 xoperands[0] = p->internal_label;
7229 xoperands[1] = gen_label_rtx ();
7231 /* Since the call is indirect, FP arguments in registers
7232 need to be copied to the general registers. Then, the
7233 argument relocation stub will copy them back. */
7235 copy_fp_args (insn);
7239 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7240 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7241 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7245 output_asm_insn ("addil LR'%0-$global$,%%r27",
7247 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7251 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7252 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7253 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7254 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7256 if (!sibcall && !TARGET_PA_20)
7258 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7259 if (TARGET_NO_SPACE_REGS)
7260 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7262 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7269 output_asm_insn ("bve (%%r1)", xoperands);
7274 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7275 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7276 delay_slot_filled = 1;
7279 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7284 if (!TARGET_NO_SPACE_REGS)
7285 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7290 if (TARGET_NO_SPACE_REGS)
7291 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7293 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7297 if (TARGET_NO_SPACE_REGS)
7298 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7300 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7303 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7305 output_asm_insn ("copy %%r31,%%r2", xoperands);
7306 delay_slot_filled = 1;
7313 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7314 output_asm_insn ("nop", xoperands);
7316 /* We are done if there isn't a jump in the delay slot. */
7318 || delay_insn_deleted
7319 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7322 /* A sibcall should never have a branch in the delay slot. */
7323 gcc_assert (!sibcall);
7325 /* This call has an unconditional jump in its delay slot. */
7326 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7328 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7330 /* See if the return address can be adjusted. Use the containing
7331 sequence insn's address. */
7332 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7333 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7334 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7336 if (VAL_14_BITS_P (distance))
7338 xoperands[1] = gen_label_rtx ();
7339 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7340 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7341 CODE_LABEL_NUMBER (xoperands[1]));
7344 output_asm_insn ("nop\n\tb,n %0", xoperands);
7347 output_asm_insn ("b,n %0", xoperands);
7349 /* Delete the jump. */
7350 PUT_CODE (NEXT_INSN (insn), NOTE);
7351 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7352 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7357 /* Return the attribute length of the indirect call instruction INSN.
7358 The length must match the code generated by output_indirect call.
7359 The returned length includes the delay slot. Currently, the delay
7360 slot of an indirect call sequence is not exposed and it is used by
7361 the sequence itself. */
7364 attr_length_indirect_call (rtx insn)
7366 unsigned long distance = -1;
7367 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7369 if (INSN_ADDRESSES_SET_P ())
7371 distance = (total + insn_current_reference_address (insn));
7372 if (distance < total)
7379 if (TARGET_FAST_INDIRECT_CALLS
7380 || (!TARGET_PORTABLE_RUNTIME
7381 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7387 if (TARGET_PORTABLE_RUNTIME)
7390 /* Out of reach, can use ble. */
7395 output_indirect_call (rtx insn, rtx call_dest)
7401 xoperands[0] = call_dest;
7402 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7403 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7407 /* First the special case for kernels, level 0 systems, etc. */
7408 if (TARGET_FAST_INDIRECT_CALLS)
7409 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7411 /* Now the normal case -- we can reach $$dyncall directly or
7412 we're sure that we can get there via a long-branch stub.
7414 No need to check target flags as the length uniquely identifies
7415 the remaining cases. */
7416 if (attr_length_indirect_call (insn) == 8)
7418 /* The HP linker substitutes a BLE for millicode calls using
7419 the short PIC PCREL form. Thus, we must use %r31 as the
7420 link register when generating PA 1.x code. */
7422 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7424 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7427 /* Long millicode call, but we are not generating PIC or portable runtime
7429 if (attr_length_indirect_call (insn) == 12)
7430 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7432 /* Long millicode call for portable runtime. */
7433 if (attr_length_indirect_call (insn) == 20)
7434 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7436 /* We need a long PIC call to $$dyncall. */
7437 xoperands[0] = NULL_RTX;
7438 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7439 if (TARGET_SOM || !TARGET_GAS)
7441 xoperands[0] = gen_label_rtx ();
7442 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7443 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7444 CODE_LABEL_NUMBER (xoperands[0]));
7445 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7449 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7450 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7453 output_asm_insn ("blr %%r0,%%r2", xoperands);
7454 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7458 /* Return the total length of the save and restore instructions needed for
7459 the data linkage table pointer (i.e., the PIC register) across the call
7460 instruction INSN. No-return calls do not require a save and restore.
7461 In addition, we may be able to avoid the save and restore for calls
7462 within the same translation unit. */
7465 attr_length_save_restore_dltp (rtx insn)
7467 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7473 /* In HPUX 8.0's shared library scheme, special relocations are needed
7474 for function labels if they might be passed to a function
7475 in a shared library (because shared libraries don't live in code
7476 space), and special magic is needed to construct their address. */
7479 hppa_encode_label (rtx sym)
7481 const char *str = XSTR (sym, 0);
7482 int len = strlen (str) + 1;
7485 p = newstr = alloca (len + 1);
7489 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7493 pa_encode_section_info (tree decl, rtx rtl, int first)
7495 default_encode_section_info (decl, rtl, first);
7497 if (first && TEXT_SPACE_P (decl))
7499 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7500 if (TREE_CODE (decl) == FUNCTION_DECL)
7501 hppa_encode_label (XEXP (rtl, 0));
7505 /* This is sort of inverse to pa_encode_section_info. */
7508 pa_strip_name_encoding (const char *str)
7510 str += (*str == '@');
7511 str += (*str == '*');
7516 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7518 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7521 /* Returns 1 if OP is a function label involved in a simple addition
7522 with a constant. Used to keep certain patterns from matching
7523 during instruction combination. */
7525 is_function_label_plus_const (rtx op)
7527 /* Strip off any CONST. */
7528 if (GET_CODE (op) == CONST)
7531 return (GET_CODE (op) == PLUS
7532 && function_label_operand (XEXP (op, 0), Pmode)
7533 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7536 /* Output assembly code for a thunk to FUNCTION. */
7539 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7540 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7543 static unsigned int current_thunk_number;
7544 int val_14 = VAL_14_BITS_P (delta);
7549 xoperands[0] = XEXP (DECL_RTL (function), 0);
7550 xoperands[1] = XEXP (DECL_RTL (thunk_fndecl), 0);
7551 xoperands[2] = GEN_INT (delta);
7553 ASM_OUTPUT_LABEL (file, XSTR (xoperands[1], 0));
7554 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7556 /* Output the thunk. We know that the function is in the same
7557 translation unit (i.e., the same space) as the thunk, and that
7558 thunks are output after their method. Thus, we don't need an
7559 external branch to reach the function. With SOM and GAS,
7560 functions and thunks are effectively in different sections.
7561 Thus, we can always use a IA-relative branch and the linker
7562 will add a long branch stub if necessary.
7564 However, we have to be careful when generating PIC code on the
7565 SOM port to ensure that the sequence does not transfer to an
7566 import stub for the target function as this could clobber the
7567 return value saved at SP-24. This would also apply to the
7568 32-bit linux port if the multi-space model is implemented. */
7569 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7570 && !(flag_pic && TREE_PUBLIC (function))
7571 && (TARGET_GAS || last_address < 262132))
7572 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7573 && ((targetm.have_named_sections
7574 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7575 /* The GNU 64-bit linker has rather poor stub management.
7576 So, we use a long branch from thunks that aren't in
7577 the same section as the target function. */
7579 && (DECL_SECTION_NAME (thunk_fndecl)
7580 != DECL_SECTION_NAME (function)))
7581 || ((DECL_SECTION_NAME (thunk_fndecl)
7582 == DECL_SECTION_NAME (function))
7583 && last_address < 262132)))
7584 || (!targetm.have_named_sections && last_address < 262132))))
7587 output_asm_insn ("addil L'%2,%%r26", xoperands);
7589 output_asm_insn ("b %0", xoperands);
7593 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7598 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7602 else if (TARGET_64BIT)
7604 /* We only have one call-clobbered scratch register, so we can't
7605 make use of the delay slot if delta doesn't fit in 14 bits. */
7608 output_asm_insn ("addil L'%2,%%r26", xoperands);
7609 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7612 output_asm_insn ("b,l .+8,%%r1", xoperands);
7616 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7617 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7621 xoperands[3] = GEN_INT (val_14 ? 8 : 16);
7622 output_asm_insn ("addil L'%0-%1-%3,%%r1", xoperands);
7627 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7628 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7633 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
7637 else if (TARGET_PORTABLE_RUNTIME)
7639 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7640 output_asm_insn ("ldo R'%0(%%r1),%%r22", xoperands);
7643 output_asm_insn ("addil L'%2,%%r26", xoperands);
7645 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7649 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7654 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7658 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7660 /* The function is accessible from outside this module. The only
7661 way to avoid an import stub between the thunk and function is to
7662 call the function directly with an indirect sequence similar to
7663 that used by $$dyncall. This is possible because $$dyncall acts
7664 as the import stub in an indirect call. */
7665 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7666 xoperands[3] = gen_rtx_SYMBOL_REF (Pmode, label);
7667 output_asm_insn ("addil LT'%3,%%r19", xoperands);
7668 output_asm_insn ("ldw RT'%3(%%r1),%%r22", xoperands);
7669 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7670 output_asm_insn ("bb,>=,n %%r22,30,.+16", xoperands);
7671 output_asm_insn ("depi 0,31,2,%%r22", xoperands);
7672 output_asm_insn ("ldw 4(%%sr0,%%r22),%%r19", xoperands);
7673 output_asm_insn ("ldw 0(%%sr0,%%r22),%%r22", xoperands);
7677 output_asm_insn ("addil L'%2,%%r26", xoperands);
7683 output_asm_insn ("bve (%%r22)", xoperands);
7686 else if (TARGET_NO_SPACE_REGS)
7688 output_asm_insn ("be 0(%%sr4,%%r22)", xoperands);
7693 output_asm_insn ("ldsid (%%sr0,%%r22),%%r21", xoperands);
7694 output_asm_insn ("mtsp %%r21,%%sr0", xoperands);
7695 output_asm_insn ("be 0(%%sr0,%%r22)", xoperands);
7700 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7702 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7706 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7708 if (TARGET_SOM || !TARGET_GAS)
7710 output_asm_insn ("addil L'%0-%1-8,%%r1", xoperands);
7711 output_asm_insn ("ldo R'%0-%1-8(%%r1),%%r22", xoperands);
7715 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7716 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r22", xoperands);
7720 output_asm_insn ("addil L'%2,%%r26", xoperands);
7722 output_asm_insn ("bv %%r0(%%r22)", xoperands);
7726 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7731 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7738 output_asm_insn ("addil L'%2,%%r26", xoperands);
7740 output_asm_insn ("ldil L'%0,%%r22", xoperands);
7741 output_asm_insn ("be R'%0(%%sr4,%%r22)", xoperands);
7745 output_asm_insn ("ldo %2(%%r26),%%r26", xoperands);
7750 output_asm_insn ("ldo R'%2(%%r1),%%r26", xoperands);
7755 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7757 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7760 output_asm_insn (".align 4", xoperands);
7761 ASM_OUTPUT_LABEL (file, label);
7762 output_asm_insn (".word P'%0", xoperands);
7764 else if (TARGET_SOM && TARGET_GAS)
7767 current_thunk_number++;
7768 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
7769 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
7770 last_address += nbytes;
7771 update_total_code_bytes (nbytes);
7774 /* Only direct calls to static functions are allowed to be sibling (tail)
7777 This restriction is necessary because some linker generated stubs will
7778 store return pointers into rp' in some cases which might clobber a
7779 live value already in rp'.
7781 In a sibcall the current function and the target function share stack
7782 space. Thus if the path to the current function and the path to the
7783 target function save a value in rp', they save the value into the
7784 same stack slot, which has undesirable consequences.
7786 Because of the deferred binding nature of shared libraries any function
7787 with external scope could be in a different load module and thus require
7788 rp' to be saved when calling that function. So sibcall optimizations
7789 can only be safe for static function.
7791 Note that GCC never needs return value relocations, so we don't have to
7792 worry about static calls with return value relocations (which require
7795 It is safe to perform a sibcall optimization when the target function
7796 will never return. */
7798 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
7800 if (TARGET_PORTABLE_RUNTIME)
7803 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7804 single subspace mode and the call is not indirect. As far as I know,
7805 there is no operating system support for the multiple subspace mode.
7806 It might be possible to support indirect calls if we didn't use
7807 $$dyncall (see the indirect sequence generated in output_call). */
7809 return (decl != NULL_TREE);
7811 /* Sibcalls are not ok because the arg pointer register is not a fixed
7812 register. This prevents the sibcall optimization from occurring. In
7813 addition, there are problems with stub placement using GNU ld. This
7814 is because a normal sibcall branch uses a 17-bit relocation while
7815 a regular call branch uses a 22-bit relocation. As a result, more
7816 care needs to be taken in the placement of long-branch stubs. */
7820 /* Sibcalls are only ok within a translation unit. */
7821 return (decl && !TREE_PUBLIC (decl));
7824 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7825 use in fmpyadd instructions. */
7827 fmpyaddoperands (rtx *operands)
7829 enum machine_mode mode = GET_MODE (operands[0]);
7831 /* Must be a floating point mode. */
7832 if (mode != SFmode && mode != DFmode)
7835 /* All modes must be the same. */
7836 if (! (mode == GET_MODE (operands[1])
7837 && mode == GET_MODE (operands[2])
7838 && mode == GET_MODE (operands[3])
7839 && mode == GET_MODE (operands[4])
7840 && mode == GET_MODE (operands[5])))
7843 /* All operands must be registers. */
7844 if (! (GET_CODE (operands[1]) == REG
7845 && GET_CODE (operands[2]) == REG
7846 && GET_CODE (operands[3]) == REG
7847 && GET_CODE (operands[4]) == REG
7848 && GET_CODE (operands[5]) == REG))
7851 /* Only 2 real operands to the addition. One of the input operands must
7852 be the same as the output operand. */
7853 if (! rtx_equal_p (operands[3], operands[4])
7854 && ! rtx_equal_p (operands[3], operands[5]))
7857 /* Inout operand of add cannot conflict with any operands from multiply. */
7858 if (rtx_equal_p (operands[3], operands[0])
7859 || rtx_equal_p (operands[3], operands[1])
7860 || rtx_equal_p (operands[3], operands[2]))
7863 /* multiply cannot feed into addition operands. */
7864 if (rtx_equal_p (operands[4], operands[0])
7865 || rtx_equal_p (operands[5], operands[0]))
7868 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7870 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7871 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7872 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7873 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7874 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7875 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7878 /* Passed. Operands are suitable for fmpyadd. */
7882 #if !defined(USE_COLLECT2)
7884 pa_asm_out_constructor (rtx symbol, int priority)
7886 if (!function_label_operand (symbol, VOIDmode))
7887 hppa_encode_label (symbol);
7889 #ifdef CTORS_SECTION_ASM_OP
7890 default_ctor_section_asm_out_constructor (symbol, priority);
7892 # ifdef TARGET_ASM_NAMED_SECTION
7893 default_named_section_asm_out_constructor (symbol, priority);
7895 default_stabs_asm_out_constructor (symbol, priority);
7901 pa_asm_out_destructor (rtx symbol, int priority)
7903 if (!function_label_operand (symbol, VOIDmode))
7904 hppa_encode_label (symbol);
7906 #ifdef DTORS_SECTION_ASM_OP
7907 default_dtor_section_asm_out_destructor (symbol, priority);
7909 # ifdef TARGET_ASM_NAMED_SECTION
7910 default_named_section_asm_out_destructor (symbol, priority);
7912 default_stabs_asm_out_destructor (symbol, priority);
7918 /* This function places uninitialized global data in the bss section.
7919 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
7920 function on the SOM port to prevent uninitialized global data from
7921 being placed in the data section. */
7924 pa_asm_output_aligned_bss (FILE *stream,
7926 unsigned HOST_WIDE_INT size,
7930 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7932 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
7933 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
7936 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
7937 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
7940 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7941 ASM_OUTPUT_LABEL (stream, name);
7942 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
7945 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
7946 that doesn't allow the alignment of global common storage to be directly
7947 specified. The SOM linker aligns common storage based on the rounded
7948 value of the NUM_BYTES parameter in the .comm directive. It's not
7949 possible to use the .align directive as it doesn't affect the alignment
7950 of the label associated with a .comm directive. */
7953 pa_asm_output_aligned_common (FILE *stream,
7955 unsigned HOST_WIDE_INT size,
7958 unsigned int max_common_align;
7960 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
7961 if (align > max_common_align)
7963 warning (0, "alignment (%u) for %s exceeds maximum alignment "
7964 "for global common data. Using %u",
7965 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
7966 align = max_common_align;
7971 assemble_name (stream, name);
7972 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
7973 MAX (size, align / BITS_PER_UNIT));
7976 /* We can't use .comm for local common storage as the SOM linker effectively
7977 treats the symbol as universal and uses the same storage for local symbols
7978 with the same name in different object files. The .block directive
7979 reserves an uninitialized block of storage. However, it's not common
7980 storage. Fortunately, GCC never requests common storage with the same
7981 name in any given translation unit. */
7984 pa_asm_output_aligned_local (FILE *stream,
7986 unsigned HOST_WIDE_INT size,
7990 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
7993 fprintf (stream, "%s", LOCAL_ASM_OP);
7994 assemble_name (stream, name);
7995 fprintf (stream, "\n");
7998 ASM_OUTPUT_LABEL (stream, name);
7999 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8002 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8003 use in fmpysub instructions. */
8005 fmpysuboperands (rtx *operands)
8007 enum machine_mode mode = GET_MODE (operands[0]);
8009 /* Must be a floating point mode. */
8010 if (mode != SFmode && mode != DFmode)
8013 /* All modes must be the same. */
8014 if (! (mode == GET_MODE (operands[1])
8015 && mode == GET_MODE (operands[2])
8016 && mode == GET_MODE (operands[3])
8017 && mode == GET_MODE (operands[4])
8018 && mode == GET_MODE (operands[5])))
8021 /* All operands must be registers. */
8022 if (! (GET_CODE (operands[1]) == REG
8023 && GET_CODE (operands[2]) == REG
8024 && GET_CODE (operands[3]) == REG
8025 && GET_CODE (operands[4]) == REG
8026 && GET_CODE (operands[5]) == REG))
8029 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8030 operation, so operands[4] must be the same as operand[3]. */
8031 if (! rtx_equal_p (operands[3], operands[4]))
8034 /* multiply cannot feed into subtraction. */
8035 if (rtx_equal_p (operands[5], operands[0]))
8038 /* Inout operand of sub cannot conflict with any operands from multiply. */
8039 if (rtx_equal_p (operands[3], operands[0])
8040 || rtx_equal_p (operands[3], operands[1])
8041 || rtx_equal_p (operands[3], operands[2]))
8044 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8046 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8047 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8048 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8049 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8050 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8051 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8054 /* Passed. Operands are suitable for fmpysub. */
8058 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8059 constants for shadd instructions. */
8061 shadd_constant_p (int val)
8063 if (val == 2 || val == 4 || val == 8)
8069 /* Return 1 if OP is valid as a base or index register in a
8073 borx_reg_operand (rtx op, enum machine_mode mode)
8075 if (GET_CODE (op) != REG)
8078 /* We must reject virtual registers as the only expressions that
8079 can be instantiated are REG and REG+CONST. */
8080 if (op == virtual_incoming_args_rtx
8081 || op == virtual_stack_vars_rtx
8082 || op == virtual_stack_dynamic_rtx
8083 || op == virtual_outgoing_args_rtx
8084 || op == virtual_cfa_rtx)
8087 /* While it's always safe to index off the frame pointer, it's not
8088 profitable to do so when the frame pointer is being eliminated. */
8089 if (!reload_completed
8090 && flag_omit_frame_pointer
8091 && !current_function_calls_alloca
8092 && op == frame_pointer_rtx)
8095 return register_operand (op, mode);
8098 /* Return 1 if this operand is anything other than a hard register. */
8101 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8103 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8106 /* Return 1 if INSN branches forward. Should be using insn_addresses
8107 to avoid walking through all the insns... */
8109 forward_branch_p (rtx insn)
8111 rtx label = JUMP_LABEL (insn);
8118 insn = NEXT_INSN (insn);
8121 return (insn == label);
8124 /* Return 1 if OP is an equality comparison, else return 0. */
8126 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8128 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8131 /* Return 1 if INSN is in the delay slot of a call instruction. */
8133 jump_in_call_delay (rtx insn)
8136 if (GET_CODE (insn) != JUMP_INSN)
8139 if (PREV_INSN (insn)
8140 && PREV_INSN (PREV_INSN (insn))
8141 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8143 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8145 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8146 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8153 /* Output an unconditional move and branch insn. */
8156 output_parallel_movb (rtx *operands, int length)
8158 /* These are the cases in which we win. */
8160 return "mov%I1b,tr %1,%0,%2";
8162 /* None of these cases wins, but they don't lose either. */
8163 if (dbr_sequence_length () == 0)
8165 /* Nothing in the delay slot, fake it by putting the combined
8166 insn (the copy or add) in the delay slot of a bl. */
8167 if (GET_CODE (operands[1]) == CONST_INT)
8168 return "b %2\n\tldi %1,%0";
8170 return "b %2\n\tcopy %1,%0";
8174 /* Something in the delay slot, but we've got a long branch. */
8175 if (GET_CODE (operands[1]) == CONST_INT)
8176 return "ldi %1,%0\n\tb %2";
8178 return "copy %1,%0\n\tb %2";
8182 /* Output an unconditional add and branch insn. */
8185 output_parallel_addb (rtx *operands, int length)
8187 /* To make life easy we want operand0 to be the shared input/output
8188 operand and operand1 to be the readonly operand. */
8189 if (operands[0] == operands[1])
8190 operands[1] = operands[2];
8192 /* These are the cases in which we win. */
8194 return "add%I1b,tr %1,%0,%3";
8196 /* None of these cases win, but they don't lose either. */
8197 if (dbr_sequence_length () == 0)
8199 /* Nothing in the delay slot, fake it by putting the combined
8200 insn (the copy or add) in the delay slot of a bl. */
8201 return "b %3\n\tadd%I1 %1,%0,%0";
8205 /* Something in the delay slot, but we've got a long branch. */
8206 return "add%I1 %1,%0,%0\n\tb %3";
8210 /* Return nonzero if INSN (a jump insn) immediately follows a call
8211 to a named function. This is used to avoid filling the delay slot
8212 of the jump since it can usually be eliminated by modifying RP in
8213 the delay slot of the call. */
8216 following_call (rtx insn)
8218 if (! TARGET_JUMP_IN_DELAY)
8221 /* Find the previous real insn, skipping NOTEs. */
8222 insn = PREV_INSN (insn);
8223 while (insn && GET_CODE (insn) == NOTE)
8224 insn = PREV_INSN (insn);
8226 /* Check for CALL_INSNs and millicode calls. */
8228 && ((GET_CODE (insn) == CALL_INSN
8229 && get_attr_type (insn) != TYPE_DYNCALL)
8230 || (GET_CODE (insn) == INSN
8231 && GET_CODE (PATTERN (insn)) != SEQUENCE
8232 && GET_CODE (PATTERN (insn)) != USE
8233 && GET_CODE (PATTERN (insn)) != CLOBBER
8234 && get_attr_type (insn) == TYPE_MILLI)))
8240 /* We use this hook to perform a PA specific optimization which is difficult
8241 to do in earlier passes.
8243 We want the delay slots of branches within jump tables to be filled.
8244 None of the compiler passes at the moment even has the notion that a
8245 PA jump table doesn't contain addresses, but instead contains actual
8248 Because we actually jump into the table, the addresses of each entry
8249 must stay constant in relation to the beginning of the table (which
8250 itself must stay constant relative to the instruction to jump into
8251 it). I don't believe we can guarantee earlier passes of the compiler
8252 will adhere to those rules.
8254 So, late in the compilation process we find all the jump tables, and
8255 expand them into real code -- e.g. each entry in the jump table vector
8256 will get an appropriate label followed by a jump to the final target.
8258 Reorg and the final jump pass can then optimize these branches and
8259 fill their delay slots. We end up with smaller, more efficient code.
8261 The jump instructions within the table are special; we must be able
8262 to identify them during assembly output (if the jumps don't get filled
8263 we need to emit a nop rather than nullifying the delay slot)). We
8264 identify jumps in switch tables by using insns with the attribute
8265 type TYPE_BTABLE_BRANCH.
8267 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8268 insns. This serves two purposes, first it prevents jump.c from
8269 noticing that the last N entries in the table jump to the instruction
8270 immediately after the table and deleting the jumps. Second, those
8271 insns mark where we should emit .begin_brtab and .end_brtab directives
8272 when using GAS (allows for better link time optimizations). */
8279 remove_useless_addtr_insns (1);
8281 if (pa_cpu < PROCESSOR_8000)
8282 pa_combine_instructions ();
8285 /* This is fairly cheap, so always run it if optimizing. */
8286 if (optimize > 0 && !TARGET_BIG_SWITCH)
8288 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8289 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8291 rtx pattern, tmp, location, label;
8292 unsigned int length, i;
8294 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8295 if (GET_CODE (insn) != JUMP_INSN
8296 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8297 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8300 /* Emit marker for the beginning of the branch table. */
8301 emit_insn_before (gen_begin_brtab (), insn);
8303 pattern = PATTERN (insn);
8304 location = PREV_INSN (insn);
8305 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8307 for (i = 0; i < length; i++)
8309 /* Emit a label before each jump to keep jump.c from
8310 removing this code. */
8311 tmp = gen_label_rtx ();
8312 LABEL_NUSES (tmp) = 1;
8313 emit_label_after (tmp, location);
8314 location = NEXT_INSN (location);
8316 if (GET_CODE (pattern) == ADDR_VEC)
8317 label = XEXP (XVECEXP (pattern, 0, i), 0);
8319 label = XEXP (XVECEXP (pattern, 1, i), 0);
8321 tmp = gen_short_jump (label);
8323 /* Emit the jump itself. */
8324 tmp = emit_jump_insn_after (tmp, location);
8325 JUMP_LABEL (tmp) = label;
8326 LABEL_NUSES (label)++;
8327 location = NEXT_INSN (location);
8329 /* Emit a BARRIER after the jump. */
8330 emit_barrier_after (location);
8331 location = NEXT_INSN (location);
8334 /* Emit marker for the end of the branch table. */
8335 emit_insn_before (gen_end_brtab (), location);
8336 location = NEXT_INSN (location);
8337 emit_barrier_after (location);
8339 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8345 /* Still need brtab marker insns. FIXME: the presence of these
8346 markers disables output of the branch table to readonly memory,
8347 and any alignment directives that might be needed. Possibly,
8348 the begin_brtab insn should be output before the label for the
8349 table. This doesn't matter at the moment since the tables are
8350 always output in the text section. */
8351 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8353 /* Find an ADDR_VEC insn. */
8354 if (GET_CODE (insn) != JUMP_INSN
8355 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8356 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8359 /* Now generate markers for the beginning and end of the
8361 emit_insn_before (gen_begin_brtab (), insn);
8362 emit_insn_after (gen_end_brtab (), insn);
8367 /* The PA has a number of odd instructions which can perform multiple
8368 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8369 it may be profitable to combine two instructions into one instruction
8370 with two outputs. It's not profitable PA2.0 machines because the
8371 two outputs would take two slots in the reorder buffers.
8373 This routine finds instructions which can be combined and combines
8374 them. We only support some of the potential combinations, and we
8375 only try common ways to find suitable instructions.
8377 * addb can add two registers or a register and a small integer
8378 and jump to a nearby (+-8k) location. Normally the jump to the
8379 nearby location is conditional on the result of the add, but by
8380 using the "true" condition we can make the jump unconditional.
8381 Thus addb can perform two independent operations in one insn.
8383 * movb is similar to addb in that it can perform a reg->reg
8384 or small immediate->reg copy and jump to a nearby (+-8k location).
8386 * fmpyadd and fmpysub can perform a FP multiply and either an
8387 FP add or FP sub if the operands of the multiply and add/sub are
8388 independent (there are other minor restrictions). Note both
8389 the fmpy and fadd/fsub can in theory move to better spots according
8390 to data dependencies, but for now we require the fmpy stay at a
8393 * Many of the memory operations can perform pre & post updates
8394 of index registers. GCC's pre/post increment/decrement addressing
8395 is far too simple to take advantage of all the possibilities. This
8396 pass may not be suitable since those insns may not be independent.
8398 * comclr can compare two ints or an int and a register, nullify
8399 the following instruction and zero some other register. This
8400 is more difficult to use as it's harder to find an insn which
8401 will generate a comclr than finding something like an unconditional
8402 branch. (conditional moves & long branches create comclr insns).
8404 * Most arithmetic operations can conditionally skip the next
8405 instruction. They can be viewed as "perform this operation
8406 and conditionally jump to this nearby location" (where nearby
8407 is an insns away). These are difficult to use due to the
8408 branch length restrictions. */
8411 pa_combine_instructions (void)
8415 /* This can get expensive since the basic algorithm is on the
8416 order of O(n^2) (or worse). Only do it for -O2 or higher
8417 levels of optimization. */
8421 /* Walk down the list of insns looking for "anchor" insns which
8422 may be combined with "floating" insns. As the name implies,
8423 "anchor" instructions don't move, while "floating" insns may
8425 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8426 new = make_insn_raw (new);
8428 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8430 enum attr_pa_combine_type anchor_attr;
8431 enum attr_pa_combine_type floater_attr;
8433 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8434 Also ignore any special USE insns. */
8435 if ((GET_CODE (anchor) != INSN
8436 && GET_CODE (anchor) != JUMP_INSN
8437 && GET_CODE (anchor) != CALL_INSN)
8438 || GET_CODE (PATTERN (anchor)) == USE
8439 || GET_CODE (PATTERN (anchor)) == CLOBBER
8440 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8441 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8444 anchor_attr = get_attr_pa_combine_type (anchor);
8445 /* See if anchor is an insn suitable for combination. */
8446 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8447 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8448 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8449 && ! forward_branch_p (anchor)))
8453 for (floater = PREV_INSN (anchor);
8455 floater = PREV_INSN (floater))
8457 if (GET_CODE (floater) == NOTE
8458 || (GET_CODE (floater) == INSN
8459 && (GET_CODE (PATTERN (floater)) == USE
8460 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8463 /* Anything except a regular INSN will stop our search. */
8464 if (GET_CODE (floater) != INSN
8465 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8466 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8472 /* See if FLOATER is suitable for combination with the
8474 floater_attr = get_attr_pa_combine_type (floater);
8475 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8476 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8477 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8478 && floater_attr == PA_COMBINE_TYPE_FMPY))
8480 /* If ANCHOR and FLOATER can be combined, then we're
8481 done with this pass. */
8482 if (pa_can_combine_p (new, anchor, floater, 0,
8483 SET_DEST (PATTERN (floater)),
8484 XEXP (SET_SRC (PATTERN (floater)), 0),
8485 XEXP (SET_SRC (PATTERN (floater)), 1)))
8489 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8490 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8492 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8494 if (pa_can_combine_p (new, anchor, floater, 0,
8495 SET_DEST (PATTERN (floater)),
8496 XEXP (SET_SRC (PATTERN (floater)), 0),
8497 XEXP (SET_SRC (PATTERN (floater)), 1)))
8502 if (pa_can_combine_p (new, anchor, floater, 0,
8503 SET_DEST (PATTERN (floater)),
8504 SET_SRC (PATTERN (floater)),
8505 SET_SRC (PATTERN (floater))))
8511 /* If we didn't find anything on the backwards scan try forwards. */
8513 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8514 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8516 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8518 if (GET_CODE (floater) == NOTE
8519 || (GET_CODE (floater) == INSN
8520 && (GET_CODE (PATTERN (floater)) == USE
8521 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8525 /* Anything except a regular INSN will stop our search. */
8526 if (GET_CODE (floater) != INSN
8527 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8528 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8534 /* See if FLOATER is suitable for combination with the
8536 floater_attr = get_attr_pa_combine_type (floater);
8537 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8538 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8539 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8540 && floater_attr == PA_COMBINE_TYPE_FMPY))
8542 /* If ANCHOR and FLOATER can be combined, then we're
8543 done with this pass. */
8544 if (pa_can_combine_p (new, anchor, floater, 1,
8545 SET_DEST (PATTERN (floater)),
8546 XEXP (SET_SRC (PATTERN (floater)),
8548 XEXP (SET_SRC (PATTERN (floater)),
8555 /* FLOATER will be nonzero if we found a suitable floating
8556 insn for combination with ANCHOR. */
8558 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8559 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8561 /* Emit the new instruction and delete the old anchor. */
8562 emit_insn_before (gen_rtx_PARALLEL
8564 gen_rtvec (2, PATTERN (anchor),
8565 PATTERN (floater))),
8568 PUT_CODE (anchor, NOTE);
8569 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8570 NOTE_SOURCE_FILE (anchor) = 0;
8572 /* Emit a special USE insn for FLOATER, then delete
8573 the floating insn. */
8574 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8575 delete_insn (floater);
8580 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8583 /* Emit the new_jump instruction and delete the old anchor. */
8585 = emit_jump_insn_before (gen_rtx_PARALLEL
8587 gen_rtvec (2, PATTERN (anchor),
8588 PATTERN (floater))),
8591 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8592 PUT_CODE (anchor, NOTE);
8593 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8594 NOTE_SOURCE_FILE (anchor) = 0;
8596 /* Emit a special USE insn for FLOATER, then delete
8597 the floating insn. */
8598 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8599 delete_insn (floater);
8607 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8610 int insn_code_number;
8613 /* Create a PARALLEL with the patterns of ANCHOR and
8614 FLOATER, try to recognize it, then test constraints
8615 for the resulting pattern.
8617 If the pattern doesn't match or the constraints
8618 aren't met keep searching for a suitable floater
8620 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8621 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8622 INSN_CODE (new) = -1;
8623 insn_code_number = recog_memoized (new);
8624 if (insn_code_number < 0
8625 || (extract_insn (new), ! constrain_operands (1)))
8639 /* There's up to three operands to consider. One
8640 output and two inputs.
8642 The output must not be used between FLOATER & ANCHOR
8643 exclusive. The inputs must not be set between
8644 FLOATER and ANCHOR exclusive. */
8646 if (reg_used_between_p (dest, start, end))
8649 if (reg_set_between_p (src1, start, end))
8652 if (reg_set_between_p (src2, start, end))
8655 /* If we get here, then everything is good. */
8659 /* Return nonzero if references for INSN are delayed.
8661 Millicode insns are actually function calls with some special
8662 constraints on arguments and register usage.
8664 Millicode calls always expect their arguments in the integer argument
8665 registers, and always return their result in %r29 (ret1). They
8666 are expected to clobber their arguments, %r1, %r29, and the return
8667 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8669 This function tells reorg that the references to arguments and
8670 millicode calls do not appear to happen until after the millicode call.
8671 This allows reorg to put insns which set the argument registers into the
8672 delay slot of the millicode call -- thus they act more like traditional
8675 Note we cannot consider side effects of the insn to be delayed because
8676 the branch and link insn will clobber the return pointer. If we happened
8677 to use the return pointer in the delay slot of the call, then we lose.
8679 get_attr_type will try to recognize the given insn, so make sure to
8680 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8683 insn_refs_are_delayed (rtx insn)
8685 return ((GET_CODE (insn) == INSN
8686 && GET_CODE (PATTERN (insn)) != SEQUENCE
8687 && GET_CODE (PATTERN (insn)) != USE
8688 && GET_CODE (PATTERN (insn)) != CLOBBER
8689 && get_attr_type (insn) == TYPE_MILLI));
8692 /* On the HP-PA the value is found in register(s) 28(-29), unless
8693 the mode is SF or DF. Then the value is returned in fr4 (32).
8695 This must perform the same promotions as PROMOTE_MODE, else
8696 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
8698 Small structures must be returned in a PARALLEL on PA64 in order
8699 to match the HP Compiler ABI. */
8702 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
8704 enum machine_mode valmode;
8706 if (AGGREGATE_TYPE_P (valtype))
8710 /* Aggregates with a size less than or equal to 128 bits are
8711 returned in GR 28(-29). They are left justified. The pad
8712 bits are undefined. Larger aggregates are returned in
8716 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8718 for (i = 0; i < ub; i++)
8720 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8721 gen_rtx_REG (DImode, 28 + i),
8726 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8728 else if (int_size_in_bytes (valtype) > UNITS_PER_WORD)
8730 /* Aggregates 5 to 8 bytes in size are returned in general
8731 registers r28-r29 in the same manner as other non
8732 floating-point objects. The data is right-justified and
8733 zero-extended to 64 bits. This is opposite to the normal
8734 justification used on big endian targets and requires
8735 special treatment. */
8736 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8737 gen_rtx_REG (DImode, 28), const0_rtx);
8738 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8742 if ((INTEGRAL_TYPE_P (valtype)
8743 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8744 || POINTER_TYPE_P (valtype))
8745 valmode = word_mode;
8747 valmode = TYPE_MODE (valtype);
8749 if (TREE_CODE (valtype) == REAL_TYPE
8750 && !AGGREGATE_TYPE_P (valtype)
8751 && TYPE_MODE (valtype) != TFmode
8752 && !TARGET_SOFT_FLOAT)
8753 return gen_rtx_REG (valmode, 32);
8755 return gen_rtx_REG (valmode, 28);
8758 /* Return the location of a parameter that is passed in a register or NULL
8759 if the parameter has any component that is passed in memory.
8761 This is new code and will be pushed to into the net sources after
8764 ??? We might want to restructure this so that it looks more like other
8767 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
8768 int named ATTRIBUTE_UNUSED)
8770 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8777 if (mode == VOIDmode)
8780 arg_size = FUNCTION_ARG_SIZE (mode, type);
8782 /* If this arg would be passed partially or totally on the stack, then
8783 this routine should return zero. pa_arg_partial_bytes will
8784 handle arguments which are split between regs and stack slots if
8785 the ABI mandates split arguments. */
8788 /* The 32-bit ABI does not split arguments. */
8789 if (cum->words + arg_size > max_arg_words)
8795 alignment = cum->words & 1;
8796 if (cum->words + alignment >= max_arg_words)
8800 /* The 32bit ABIs and the 64bit ABIs are rather different,
8801 particularly in their handling of FP registers. We might
8802 be able to cleverly share code between them, but I'm not
8803 going to bother in the hope that splitting them up results
8804 in code that is more easily understood. */
8808 /* Advance the base registers to their current locations.
8810 Remember, gprs grow towards smaller register numbers while
8811 fprs grow to higher register numbers. Also remember that
8812 although FP regs are 32-bit addressable, we pretend that
8813 the registers are 64-bits wide. */
8814 gpr_reg_base = 26 - cum->words;
8815 fpr_reg_base = 32 + cum->words;
8817 /* Arguments wider than one word and small aggregates need special
8821 || (type && AGGREGATE_TYPE_P (type)))
8823 /* Double-extended precision (80-bit), quad-precision (128-bit)
8824 and aggregates including complex numbers are aligned on
8825 128-bit boundaries. The first eight 64-bit argument slots
8826 are associated one-to-one, with general registers r26
8827 through r19, and also with floating-point registers fr4
8828 through fr11. Arguments larger than one word are always
8829 passed in general registers.
8831 Using a PARALLEL with a word mode register results in left
8832 justified data on a big-endian target. */
8835 int i, offset = 0, ub = arg_size;
8837 /* Align the base register. */
8838 gpr_reg_base -= alignment;
8840 ub = MIN (ub, max_arg_words - cum->words - alignment);
8841 for (i = 0; i < ub; i++)
8843 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8844 gen_rtx_REG (DImode, gpr_reg_base),
8850 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8855 /* If the argument is larger than a word, then we know precisely
8856 which registers we must use. */
8870 /* Structures 5 to 8 bytes in size are passed in the general
8871 registers in the same manner as other non floating-point
8872 objects. The data is right-justified and zero-extended
8873 to 64 bits. This is opposite to the normal justification
8874 used on big endian targets and requires special treatment.
8875 We now define BLOCK_REG_PADDING to pad these objects. */
8876 if (mode == BLKmode || (type && AGGREGATE_TYPE_P (type)))
8878 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8879 gen_rtx_REG (DImode, gpr_reg_base),
8881 return gen_rtx_PARALLEL (BLKmode, gen_rtvec (1, loc));
8886 /* We have a single word (32 bits). A simple computation
8887 will get us the register #s we need. */
8888 gpr_reg_base = 26 - cum->words;
8889 fpr_reg_base = 32 + 2 * cum->words;
8893 /* Determine if the argument needs to be passed in both general and
8894 floating point registers. */
8895 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8896 /* If we are doing soft-float with portable runtime, then there
8897 is no need to worry about FP regs. */
8898 && !TARGET_SOFT_FLOAT
8899 /* The parameter must be some kind of float, else we can just
8900 pass it in integer registers. */
8901 && FLOAT_MODE_P (mode)
8902 /* The target function must not have a prototype. */
8903 && cum->nargs_prototype <= 0
8904 /* libcalls do not need to pass items in both FP and general
8906 && type != NULL_TREE
8907 /* All this hair applies to "outgoing" args only. This includes
8908 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8910 /* Also pass outgoing floating arguments in both registers in indirect
8911 calls with the 32 bit ABI and the HP assembler since there is no
8912 way to the specify argument locations in static functions. */
8917 && FLOAT_MODE_P (mode)))
8923 gen_rtx_EXPR_LIST (VOIDmode,
8924 gen_rtx_REG (mode, fpr_reg_base),
8926 gen_rtx_EXPR_LIST (VOIDmode,
8927 gen_rtx_REG (mode, gpr_reg_base),
8932 /* See if we should pass this parameter in a general register. */
8933 if (TARGET_SOFT_FLOAT
8934 /* Indirect calls in the normal 32bit ABI require all arguments
8935 to be passed in general registers. */
8936 || (!TARGET_PORTABLE_RUNTIME
8940 /* If the parameter is not a floating point parameter, then
8941 it belongs in GPRs. */
8942 || !FLOAT_MODE_P (mode)
8943 /* Structure with single SFmode field belongs in GPR. */
8944 || (type && AGGREGATE_TYPE_P (type)))
8945 retval = gen_rtx_REG (mode, gpr_reg_base);
8947 retval = gen_rtx_REG (mode, fpr_reg_base);
8953 /* If this arg would be passed totally in registers or totally on the stack,
8954 then this routine should return zero. */
8957 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
8958 tree type, bool named ATTRIBUTE_UNUSED)
8960 unsigned int max_arg_words = 8;
8961 unsigned int offset = 0;
8966 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8969 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8970 /* Arg fits fully into registers. */
8972 else if (cum->words + offset >= max_arg_words)
8973 /* Arg fully on the stack. */
8977 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
8981 /* Return a string to output before text in the current function.
8983 This function is only used with SOM. Because we don't support
8984 named subspaces, we can only create a new subspace or switch back
8985 to the default text subspace. */
8987 som_text_section_asm_op (void)
8994 if (cfun && !cfun->machine->in_nsubspa)
8996 /* We only want to emit a .nsubspa directive once at the
8997 start of the function. */
8998 cfun->machine->in_nsubspa = 1;
9000 /* Create a new subspace for the text. This provides
9001 better stub placement and one-only functions. */
9003 && DECL_ONE_ONLY (cfun->decl)
9004 && !DECL_WEAK (cfun->decl))
9006 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9008 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9012 /* There isn't a current function or the body of the current
9013 function has been completed. So, we are changing to the
9014 text section to output debugging information. Do this in
9015 the default text section. We need to forget that we are
9016 in the text section so that the function text_section in
9017 varasm.c will call us the next time around. */
9022 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9025 /* On hpux10, the linker will give an error if we have a reference
9026 in the read-only data section to a symbol defined in a shared
9027 library. Therefore, expressions that might require a reloc can
9028 not be placed in the read-only data section. */
9031 pa_select_section (tree exp, int reloc,
9032 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9034 if (TREE_CODE (exp) == VAR_DECL
9035 && TREE_READONLY (exp)
9036 && !TREE_THIS_VOLATILE (exp)
9037 && DECL_INITIAL (exp)
9038 && (DECL_INITIAL (exp) == error_mark_node
9039 || TREE_CONSTANT (DECL_INITIAL (exp)))
9043 && DECL_ONE_ONLY (exp)
9044 && !DECL_WEAK (exp))
9045 som_one_only_readonly_data_section ();
9047 readonly_data_section ();
9049 else if (CONSTANT_CLASS_P (exp) && !reloc)
9050 readonly_data_section ();
9052 && TREE_CODE (exp) == VAR_DECL
9053 && DECL_ONE_ONLY (exp)
9054 && !DECL_WEAK (exp))
9055 som_one_only_data_section ();
9061 pa_globalize_label (FILE *stream, const char *name)
9063 /* We only handle DATA objects here, functions are globalized in
9064 ASM_DECLARE_FUNCTION_NAME. */
9065 if (! FUNCTION_NAME_P (name))
9067 fputs ("\t.EXPORT ", stream);
9068 assemble_name (stream, name);
9069 fputs (",DATA\n", stream);
9073 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9076 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9077 int incoming ATTRIBUTE_UNUSED)
9079 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9082 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9085 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9087 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9088 PA64 ABI says that objects larger than 128 bits are returned in memory.
9089 Note, int_size_in_bytes can return -1 if the size of the object is
9090 variable or larger than the maximum value that can be expressed as
9091 a HOST_WIDE_INT. It can also return zero for an empty type. The
9092 simplest way to handle variable and empty types is to pass them in
9093 memory. This avoids problems in defining the boundaries of argument
9094 slots, allocating registers, etc. */
9095 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9096 || int_size_in_bytes (type) <= 0);
9099 /* Structure to hold declaration and name of external symbols that are
9100 emitted by GCC. We generate a vector of these symbols and output them
9101 at the end of the file if and only if SYMBOL_REF_REFERENCED_P is true.
9102 This avoids putting out names that are never really used. */
9104 typedef struct extern_symbol GTY(())
9110 /* Define gc'd vector type for extern_symbol. */
9111 DEF_VEC_O(extern_symbol);
9112 DEF_VEC_ALLOC_O(extern_symbol,gc);
9114 /* Vector of extern_symbol pointers. */
9115 static GTY(()) VEC(extern_symbol,gc) *extern_symbols;
9117 #ifdef ASM_OUTPUT_EXTERNAL_REAL
9118 /* Mark DECL (name NAME) as an external reference (assembler output
9119 file FILE). This saves the names to output at the end of the file
9120 if actually referenced. */
9123 pa_hpux_asm_output_external (FILE *file, tree decl, const char *name)
9125 extern_symbol * p = VEC_safe_push (extern_symbol, gc, extern_symbols, NULL);
9127 gcc_assert (file == asm_out_file);
9132 /* Output text required at the end of an assembler file.
9133 This includes deferred plabels and .import directives for
9134 all external symbols that were actually referenced. */
9137 pa_hpux_file_end (void)
9142 output_deferred_plabels ();
9144 for (i = 0; VEC_iterate (extern_symbol, extern_symbols, i, p); i++)
9146 tree decl = p->decl;
9148 if (!TREE_ASM_WRITTEN (decl)
9149 && SYMBOL_REF_REFERENCED_P (XEXP (DECL_RTL (decl), 0)))
9150 ASM_OUTPUT_EXTERNAL_REAL (asm_out_file, decl, p->name);
9153 VEC_free (extern_symbol, gc, extern_symbols);