1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003, 2004 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "integrate.h"
49 #include "target-def.h"
51 /* Return nonzero if there is a bypass for the output of
52 OUT_INSN and the fp store IN_INSN. */
54 hppa_fpstore_bypass_p (rtx out_insn, rtx in_insn)
56 enum machine_mode store_mode;
57 enum machine_mode other_mode;
60 if (recog_memoized (in_insn) < 0
61 || get_attr_type (in_insn) != TYPE_FPSTORE
62 || recog_memoized (out_insn) < 0)
65 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
67 set = single_set (out_insn);
71 other_mode = GET_MODE (SET_SRC (set));
73 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
77 #ifndef DO_FRAME_NOTES
78 #ifdef INCOMING_RETURN_ADDR_RTX
79 #define DO_FRAME_NOTES 1
81 #define DO_FRAME_NOTES 0
85 static void copy_reg_pointer (rtx, rtx);
86 static void fix_range (const char *);
87 static int hppa_address_cost (rtx);
88 static bool hppa_rtx_costs (rtx, int, int, int *);
89 static inline rtx force_mode (enum machine_mode, rtx);
90 static void pa_reorg (void);
91 static void pa_combine_instructions (void);
92 static int pa_can_combine_p (rtx, rtx, rtx, int, rtx, rtx, rtx);
93 static int forward_branch_p (rtx);
94 static int shadd_constant_p (int);
95 static void compute_zdepwi_operands (unsigned HOST_WIDE_INT, unsigned *);
96 static int compute_movmem_length (rtx);
97 static int compute_clrmem_length (rtx);
98 static bool pa_assemble_integer (rtx, unsigned int, int);
99 static void remove_useless_addtr_insns (int);
100 static void store_reg (int, HOST_WIDE_INT, int);
101 static void store_reg_modify (int, int, HOST_WIDE_INT);
102 static void load_reg (int, HOST_WIDE_INT, int);
103 static void set_reg_plus_d (int, int, HOST_WIDE_INT, int);
104 static void pa_output_function_prologue (FILE *, HOST_WIDE_INT);
105 static void update_total_code_bytes (int);
106 static void pa_output_function_epilogue (FILE *, HOST_WIDE_INT);
107 static int pa_adjust_cost (rtx, rtx, rtx, int);
108 static int pa_adjust_priority (rtx, int);
109 static int pa_issue_rate (void);
110 static void pa_select_section (tree, int, unsigned HOST_WIDE_INT)
112 static void pa_encode_section_info (tree, rtx, int);
113 static const char *pa_strip_name_encoding (const char *);
114 static bool pa_function_ok_for_sibcall (tree, tree);
115 static void pa_globalize_label (FILE *, const char *)
117 static void pa_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT,
118 HOST_WIDE_INT, tree);
119 #if !defined(USE_COLLECT2)
120 static void pa_asm_out_constructor (rtx, int);
121 static void pa_asm_out_destructor (rtx, int);
123 static void pa_init_builtins (void);
124 static rtx hppa_builtin_saveregs (void);
125 static tree hppa_gimplify_va_arg_expr (tree, tree, tree *, tree *);
126 static void copy_fp_args (rtx) ATTRIBUTE_UNUSED;
127 static int length_fp_args (rtx) ATTRIBUTE_UNUSED;
128 static struct deferred_plabel *get_plabel (const char *)
130 static inline void pa_file_start_level (void) ATTRIBUTE_UNUSED;
131 static inline void pa_file_start_space (int) ATTRIBUTE_UNUSED;
132 static inline void pa_file_start_file (int) ATTRIBUTE_UNUSED;
133 static inline void pa_file_start_mcount (const char*) ATTRIBUTE_UNUSED;
134 static void pa_elf_file_start (void) ATTRIBUTE_UNUSED;
135 static void pa_som_file_start (void) ATTRIBUTE_UNUSED;
136 static void pa_linux_file_start (void) ATTRIBUTE_UNUSED;
137 static void pa_hpux64_gas_file_start (void) ATTRIBUTE_UNUSED;
138 static void pa_hpux64_hpas_file_start (void) ATTRIBUTE_UNUSED;
139 static void output_deferred_plabels (void);
140 #ifdef HPUX_LONG_DOUBLE_LIBRARY
141 static void pa_hpux_init_libfuncs (void);
143 static rtx pa_struct_value_rtx (tree, int);
144 static bool pa_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
146 static int pa_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
148 static struct machine_function * pa_init_machine_status (void);
151 /* Save the operands last given to a compare for use when we
152 generate a scc or bcc insn. */
153 rtx hppa_compare_op0, hppa_compare_op1;
154 enum cmp_type hppa_branch_type;
156 /* Which architecture we are generating code for. */
157 enum architecture_type pa_arch;
159 /* String to hold which architecture we are generating code for. */
160 const char *pa_arch_string;
162 /* String used with the -mfixed-range= option. */
163 const char *pa_fixed_range_string;
165 /* Which cpu we are scheduling for. */
166 enum processor_type pa_cpu;
168 /* String to hold which cpu we are scheduling for. */
169 const char *pa_cpu_string;
171 /* String used with the -munix= option. */
172 const char *pa_unix_string;
174 /* The UNIX standard to use for predefines and linking. */
177 /* Counts for the number of callee-saved general and floating point
178 registers which were saved by the current function's prologue. */
179 static int gr_saved, fr_saved;
181 static rtx find_addr_reg (rtx);
183 /* Keep track of the number of bytes we have output in the CODE subspace
184 during this compilation so we'll know when to emit inline long-calls. */
185 unsigned long total_code_bytes;
187 /* The last address of the previous function plus the number of bytes in
188 associated thunks that have been output. This is used to determine if
189 a thunk can use an IA-relative branch to reach its target function. */
190 static int last_address;
192 /* Variables to handle plabels that we discover are necessary at assembly
193 output time. They are output after the current function. */
194 struct deferred_plabel GTY(())
199 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
201 static size_t n_deferred_plabels = 0;
204 /* Initialize the GCC target structure. */
206 #undef TARGET_ASM_ALIGNED_HI_OP
207 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
208 #undef TARGET_ASM_ALIGNED_SI_OP
209 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
210 #undef TARGET_ASM_ALIGNED_DI_OP
211 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
212 #undef TARGET_ASM_UNALIGNED_HI_OP
213 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
214 #undef TARGET_ASM_UNALIGNED_SI_OP
215 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
216 #undef TARGET_ASM_UNALIGNED_DI_OP
217 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
218 #undef TARGET_ASM_INTEGER
219 #define TARGET_ASM_INTEGER pa_assemble_integer
221 #undef TARGET_ASM_FUNCTION_PROLOGUE
222 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
223 #undef TARGET_ASM_FUNCTION_EPILOGUE
224 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
226 #undef TARGET_SCHED_ADJUST_COST
227 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
228 #undef TARGET_SCHED_ADJUST_PRIORITY
229 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
230 #undef TARGET_SCHED_ISSUE_RATE
231 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
233 #undef TARGET_ENCODE_SECTION_INFO
234 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
235 #undef TARGET_STRIP_NAME_ENCODING
236 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
238 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
239 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
241 #undef TARGET_ASM_OUTPUT_MI_THUNK
242 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
243 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
244 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
246 #undef TARGET_ASM_FILE_END
247 #define TARGET_ASM_FILE_END output_deferred_plabels
249 #if !defined(USE_COLLECT2)
250 #undef TARGET_ASM_CONSTRUCTOR
251 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
252 #undef TARGET_ASM_DESTRUCTOR
253 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
256 #undef TARGET_INIT_BUILTINS
257 #define TARGET_INIT_BUILTINS pa_init_builtins
259 #undef TARGET_RTX_COSTS
260 #define TARGET_RTX_COSTS hppa_rtx_costs
261 #undef TARGET_ADDRESS_COST
262 #define TARGET_ADDRESS_COST hppa_address_cost
264 #undef TARGET_MACHINE_DEPENDENT_REORG
265 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
267 #ifdef HPUX_LONG_DOUBLE_LIBRARY
268 #undef TARGET_INIT_LIBFUNCS
269 #define TARGET_INIT_LIBFUNCS pa_hpux_init_libfuncs
272 #undef TARGET_PROMOTE_FUNCTION_RETURN
273 #define TARGET_PROMOTE_FUNCTION_RETURN hook_bool_tree_true
274 #undef TARGET_PROMOTE_PROTOTYPES
275 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
277 #undef TARGET_STRUCT_VALUE_RTX
278 #define TARGET_STRUCT_VALUE_RTX pa_struct_value_rtx
279 #undef TARGET_RETURN_IN_MEMORY
280 #define TARGET_RETURN_IN_MEMORY pa_return_in_memory
281 #undef TARGET_MUST_PASS_IN_STACK
282 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size
283 #undef TARGET_PASS_BY_REFERENCE
284 #define TARGET_PASS_BY_REFERENCE pa_pass_by_reference
285 #undef TARGET_CALLEE_COPIES
286 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
287 #undef TARGET_ARG_PARTIAL_BYTES
288 #define TARGET_ARG_PARTIAL_BYTES pa_arg_partial_bytes
290 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
291 #define TARGET_EXPAND_BUILTIN_SAVEREGS hppa_builtin_saveregs
292 #undef TARGET_GIMPLIFY_VA_ARG_EXPR
293 #define TARGET_GIMPLIFY_VA_ARG_EXPR hppa_gimplify_va_arg_expr
295 struct gcc_target targetm = TARGET_INITIALIZER;
297 /* Parse the -mfixed-range= option string. */
300 fix_range (const char *const_str)
303 char *str, *dash, *comma;
305 /* str must be of the form REG1'-'REG2{,REG1'-'REG} where REG1 and
306 REG2 are either register names or register numbers. The effect
307 of this option is to mark the registers in the range from REG1 to
308 REG2 as ``fixed'' so they won't be used by the compiler. This is
309 used, e.g., to ensure that kernel mode code doesn't use f32-f127. */
311 i = strlen (const_str);
312 str = (char *) alloca (i + 1);
313 memcpy (str, const_str, i + 1);
317 dash = strchr (str, '-');
320 warning ("value of -mfixed-range must have form REG1-REG2");
325 comma = strchr (dash + 1, ',');
329 first = decode_reg_name (str);
332 warning ("unknown register name: %s", str);
336 last = decode_reg_name (dash + 1);
339 warning ("unknown register name: %s", dash + 1);
347 warning ("%s-%s is an empty range", str, dash + 1);
351 for (i = first; i <= last; ++i)
352 fixed_regs[i] = call_used_regs[i] = 1;
361 /* Check if all floating point registers have been fixed. */
362 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
367 target_flags |= MASK_DISABLE_FPREGS;
371 override_options (void)
373 if (pa_cpu_string == NULL)
374 pa_cpu_string = TARGET_SCHED_DEFAULT;
376 if (! strcmp (pa_cpu_string, "8000"))
378 pa_cpu_string = "8000";
379 pa_cpu = PROCESSOR_8000;
381 else if (! strcmp (pa_cpu_string, "7100"))
383 pa_cpu_string = "7100";
384 pa_cpu = PROCESSOR_7100;
386 else if (! strcmp (pa_cpu_string, "700"))
388 pa_cpu_string = "700";
389 pa_cpu = PROCESSOR_700;
391 else if (! strcmp (pa_cpu_string, "7100LC"))
393 pa_cpu_string = "7100LC";
394 pa_cpu = PROCESSOR_7100LC;
396 else if (! strcmp (pa_cpu_string, "7200"))
398 pa_cpu_string = "7200";
399 pa_cpu = PROCESSOR_7200;
401 else if (! strcmp (pa_cpu_string, "7300"))
403 pa_cpu_string = "7300";
404 pa_cpu = PROCESSOR_7300;
408 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
411 /* Set the instruction architecture. */
412 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
414 pa_arch_string = "1.0";
415 pa_arch = ARCHITECTURE_10;
416 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
418 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
420 pa_arch_string = "1.1";
421 pa_arch = ARCHITECTURE_11;
422 target_flags &= ~MASK_PA_20;
423 target_flags |= MASK_PA_11;
425 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
427 pa_arch_string = "2.0";
428 pa_arch = ARCHITECTURE_20;
429 target_flags |= MASK_PA_11 | MASK_PA_20;
431 else if (pa_arch_string)
433 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
438 /* Set the default UNIX standard for HP-UX. This affects the
439 predefines and startfiles used for the target. */
440 if (pa_unix_string == NULL)
442 = TARGET_HPUX_11_11 ? "98" : (TARGET_HPUX_10_10 ? "95" : "93");
444 if (!strcmp (pa_unix_string, "93"))
446 else if (!strcmp (pa_unix_string, "95"))
448 else if (TARGET_HPUX_11_11)
450 if (!strcmp (pa_unix_string, "98"))
453 warning ("unknown -munix= option (%s).\n"
454 "Valid options are 93, 95 and 98.\n",
457 else if (TARGET_HPUX_10_10)
458 warning ("unknown -munix= option (%s)."
459 "\nValid options are 93 and 95.\n",
462 warning ("unknown -munix= option (%s).\nValid option is 93.\n",
466 if (pa_fixed_range_string)
467 fix_range (pa_fixed_range_string);
469 /* Unconditional branches in the delay slot are not compatible with dwarf2
470 call frame information. There is no benefit in using this optimization
471 on PA8000 and later processors. */
472 if (pa_cpu >= PROCESSOR_8000
473 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
474 || flag_unwind_tables)
475 target_flags &= ~MASK_JUMP_IN_DELAY;
477 if (flag_pic && TARGET_PORTABLE_RUNTIME)
479 warning ("PIC code generation is not supported in the portable runtime model\n");
482 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
484 warning ("PIC code generation is not compatible with fast indirect calls\n");
487 if (! TARGET_GAS && write_symbols != NO_DEBUG)
489 warning ("-g is only supported when using GAS on this processor,");
490 warning ("-g option disabled");
491 write_symbols = NO_DEBUG;
494 /* We only support the "big PIC" model now. And we always generate PIC
495 code when in 64bit mode. */
496 if (flag_pic == 1 || TARGET_64BIT)
499 /* We can't guarantee that .dword is available for 32-bit targets. */
500 if (UNITS_PER_WORD == 4)
501 targetm.asm_out.aligned_op.di = NULL;
503 /* The unaligned ops are only available when using GAS. */
506 targetm.asm_out.unaligned_op.hi = NULL;
507 targetm.asm_out.unaligned_op.si = NULL;
508 targetm.asm_out.unaligned_op.di = NULL;
511 init_machine_status = pa_init_machine_status;
515 pa_init_builtins (void)
517 #ifdef DONT_HAVE_FPUTC_UNLOCKED
518 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
519 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
523 /* Function to init struct machine_function.
524 This will be called, via a pointer variable,
525 from push_function_context. */
527 static struct machine_function *
528 pa_init_machine_status (void)
530 return ggc_alloc_cleared (sizeof (machine_function));
533 /* If FROM is a probable pointer register, mark TO as a probable
534 pointer register with the same pointer alignment as FROM. */
537 copy_reg_pointer (rtx to, rtx from)
539 if (REG_POINTER (from))
540 mark_reg_pointer (to, REGNO_POINTER_ALIGN (REGNO (from)));
543 /* Return nonzero only if OP is a register of mode MODE,
546 reg_or_0_operand (rtx op, enum machine_mode mode)
548 return (op == CONST0_RTX (mode) || register_operand (op, mode));
551 /* Return nonzero if OP is suitable for use in a call to a named
554 For 2.5 try to eliminate either call_operand_address or
555 function_label_operand, they perform very similar functions. */
557 call_operand_address (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
559 return (GET_MODE (op) == word_mode
560 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
563 /* Return 1 if X contains a symbolic expression. We know these
564 expressions will have one of a few well defined forms, so
565 we need only check those forms. */
567 symbolic_expression_p (rtx x)
570 /* Strip off any HIGH. */
571 if (GET_CODE (x) == HIGH)
574 return (symbolic_operand (x, VOIDmode));
578 symbolic_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
580 switch (GET_CODE (op))
587 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
588 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
589 && GET_CODE (XEXP (op, 1)) == CONST_INT);
595 /* Return truth value of statement that OP is a symbolic memory
596 operand of mode MODE. */
599 symbolic_memory_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
601 if (GET_CODE (op) == SUBREG)
602 op = SUBREG_REG (op);
603 if (GET_CODE (op) != MEM)
606 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
607 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
610 /* Return 1 if the operand is either a register, zero, or a memory operand
611 that is not symbolic. */
614 reg_or_0_or_nonsymb_mem_operand (rtx op, enum machine_mode mode)
616 if (register_operand (op, mode))
619 if (op == CONST0_RTX (mode))
622 if (GET_CODE (op) == SUBREG)
623 op = SUBREG_REG (op);
625 if (GET_CODE (op) != MEM)
628 /* Until problems with management of the REG_POINTER flag are resolved,
629 we need to delay creating move insns with unscaled indexed addresses
630 until CSE is not expected. */
631 if (!TARGET_NO_SPACE_REGS
633 && GET_CODE (XEXP (op, 0)) == PLUS
634 && REG_P (XEXP (XEXP (op, 0), 0))
635 && REG_P (XEXP (XEXP (op, 0), 1)))
638 return (!symbolic_memory_operand (op, mode)
639 && memory_address_p (mode, XEXP (op, 0)));
642 /* Return 1 if the operand is a register operand or a non-symbolic memory
643 operand after reload. This predicate is used for branch patterns that
644 internally handle register reloading. We need to accept non-symbolic
645 memory operands after reload to ensure that the pattern is still valid
646 if reload didn't find a hard register for the operand. */
649 reg_before_reload_operand (rtx op, enum machine_mode mode)
651 /* Don't accept a SUBREG since it will need a reload. */
652 if (GET_CODE (op) == SUBREG)
655 if (register_operand (op, mode))
659 && memory_operand (op, mode)
660 && !symbolic_memory_operand (op, mode))
666 /* Accept any constant that can be moved in one instruction into a
669 cint_ok_for_move (HOST_WIDE_INT intval)
671 /* OK if ldo, ldil, or zdepi, can be used. */
672 return (CONST_OK_FOR_LETTER_P (intval, 'J')
673 || CONST_OK_FOR_LETTER_P (intval, 'N')
674 || CONST_OK_FOR_LETTER_P (intval, 'K'));
677 /* Return 1 iff OP is an indexed memory operand. */
679 indexed_memory_operand (rtx op, enum machine_mode mode)
681 if (GET_MODE (op) != mode)
684 /* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
685 if (reload_completed && GET_CODE (op) == SUBREG)
686 op = SUBREG_REG (op);
688 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
693 return (memory_address_p (mode, op) && IS_INDEX_ADDR_P (op));
696 /* Accept anything that can be used as a destination operand for a
697 move instruction. We don't accept indexed memory operands since
698 they are supported only for floating point stores. */
700 move_dest_operand (rtx op, enum machine_mode mode)
702 if (register_operand (op, mode))
705 if (GET_MODE (op) != mode)
708 if (GET_CODE (op) == SUBREG)
709 op = SUBREG_REG (op);
711 if (GET_CODE (op) != MEM || symbolic_memory_operand (op, mode))
716 return (memory_address_p (mode, op)
717 && !IS_INDEX_ADDR_P (op)
718 && !IS_LO_SUM_DLT_ADDR_P (op));
721 /* Accept anything that can be used as a source operand for a move
724 move_src_operand (rtx op, enum machine_mode mode)
726 if (register_operand (op, mode))
729 if (GET_CODE (op) == CONST_INT)
730 return cint_ok_for_move (INTVAL (op));
732 if (GET_MODE (op) != mode)
735 if (GET_CODE (op) == SUBREG)
736 op = SUBREG_REG (op);
738 if (GET_CODE (op) != MEM)
741 /* Until problems with management of the REG_POINTER flag are resolved,
742 we need to delay creating move insns with unscaled indexed addresses
743 until CSE is not expected. */
744 if (!TARGET_NO_SPACE_REGS
746 && GET_CODE (XEXP (op, 0)) == PLUS
747 && REG_P (XEXP (XEXP (op, 0), 0))
748 && REG_P (XEXP (XEXP (op, 0), 1)))
751 return memory_address_p (mode, XEXP (op, 0));
754 /* Accept anything that can be used as the source operand for a prefetch
755 instruction with a cache-control completer. */
757 prefetch_cc_operand (rtx op, enum machine_mode mode)
759 if (GET_CODE (op) != MEM)
764 /* We must reject virtual registers as we don't allow REG+D. */
765 if (op == virtual_incoming_args_rtx
766 || op == virtual_stack_vars_rtx
767 || op == virtual_stack_dynamic_rtx
768 || op == virtual_outgoing_args_rtx
769 || op == virtual_cfa_rtx)
772 if (!REG_P (op) && !IS_INDEX_ADDR_P (op))
775 /* Until problems with management of the REG_POINTER flag are resolved,
776 we need to delay creating prefetch insns with unscaled indexed addresses
777 until CSE is not expected. */
778 if (!TARGET_NO_SPACE_REGS
780 && GET_CODE (op) == PLUS
781 && REG_P (XEXP (op, 0)))
784 return memory_address_p (mode, op);
787 /* Accept anything that can be used as the source operand for a prefetch
788 instruction with no cache-control completer. */
790 prefetch_nocc_operand (rtx op, enum machine_mode mode)
792 if (GET_CODE (op) != MEM)
797 /* Until problems with management of the REG_POINTER flag are resolved,
798 we need to delay creating prefetch insns with unscaled indexed addresses
799 until CSE is not expected. */
800 if (!TARGET_NO_SPACE_REGS
802 && GET_CODE (op) == PLUS
803 && REG_P (XEXP (op, 0))
804 && REG_P (XEXP (op, 1)))
807 return memory_address_p (mode, op);
810 /* Accept REG and any CONST_INT that can be moved in one instruction into a
813 reg_or_cint_move_operand (rtx op, enum machine_mode mode)
815 if (register_operand (op, mode))
818 return (GET_CODE (op) == CONST_INT && cint_ok_for_move (INTVAL (op)));
822 pic_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
827 switch (GET_CODE (op))
833 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
834 && GET_CODE (XEXP (op, 1)) == CONST_INT);
841 fp_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
843 return reg_renumber && FP_REG_P (op);
848 /* Return truth value of whether OP can be used as an operand in a
849 three operand arithmetic insn that accepts registers of mode MODE
850 or 14-bit signed integers. */
852 arith_operand (rtx op, enum machine_mode mode)
854 return (register_operand (op, mode)
855 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
858 /* Return truth value of whether OP can be used as an operand in a
859 three operand arithmetic insn that accepts registers of mode MODE
860 or 11-bit signed integers. */
862 arith11_operand (rtx op, enum machine_mode mode)
864 return (register_operand (op, mode)
865 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
868 /* Return truth value of whether OP can be used as an operand in a
871 adddi3_operand (rtx op, enum machine_mode mode)
873 return (register_operand (op, mode)
874 || (GET_CODE (op) == CONST_INT
875 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
878 /* A constant integer suitable for use in a PRE_MODIFY memory
881 pre_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
883 return (GET_CODE (op) == CONST_INT
884 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
887 /* A constant integer suitable for use in a POST_MODIFY memory
890 post_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
892 return (GET_CODE (op) == CONST_INT
893 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
897 arith_double_operand (rtx op, enum machine_mode mode)
899 return (register_operand (op, mode)
900 || (GET_CODE (op) == CONST_DOUBLE
901 && GET_MODE (op) == mode
902 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
903 && ((CONST_DOUBLE_HIGH (op) >= 0)
904 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
907 /* Return truth value of whether OP is an integer which fits the
908 range constraining immediate operands in three-address insns, or
909 is an integer register. */
912 ireg_or_int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
914 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
915 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
918 /* Return nonzero if OP is an integer register, else return zero. */
920 ireg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
922 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
925 /* Return truth value of whether OP is an integer which fits the
926 range constraining immediate operands in three-address insns. */
929 int5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
931 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
935 uint5_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
937 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
941 int11_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
943 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
947 uint32_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
949 #if HOST_BITS_PER_WIDE_INT > 32
950 /* All allowed constants will fit a CONST_INT. */
951 return (GET_CODE (op) == CONST_INT
952 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
954 return (GET_CODE (op) == CONST_INT
955 || (GET_CODE (op) == CONST_DOUBLE
956 && CONST_DOUBLE_HIGH (op) == 0));
961 arith5_operand (rtx op, enum machine_mode mode)
963 return register_operand (op, mode) || int5_operand (op, mode);
966 /* True iff zdepi can be used to generate this CONST_INT.
967 zdepi first sign extends a 5 bit signed number to a given field
968 length, then places this field anywhere in a zero. */
970 zdepi_cint_p (unsigned HOST_WIDE_INT x)
972 unsigned HOST_WIDE_INT lsb_mask, t;
974 /* This might not be obvious, but it's at least fast.
975 This function is critical; we don't have the time loops would take. */
977 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
978 /* Return true iff t is a power of two. */
979 return ((t & (t - 1)) == 0);
982 /* True iff depi or extru can be used to compute (reg & mask).
983 Accept bit pattern like these:
988 and_mask_p (unsigned HOST_WIDE_INT mask)
991 mask += mask & -mask;
992 return (mask & (mask - 1)) == 0;
995 /* True iff depi or extru can be used to compute (reg & OP). */
997 and_operand (rtx op, enum machine_mode mode)
999 return (register_operand (op, mode)
1000 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
1003 /* True iff depi can be used to compute (reg | MASK). */
1005 ior_mask_p (unsigned HOST_WIDE_INT mask)
1007 mask += mask & -mask;
1008 return (mask & (mask - 1)) == 0;
1011 /* True iff depi can be used to compute (reg | OP). */
1013 ior_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1015 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
1019 lhs_lshift_operand (rtx op, enum machine_mode mode)
1021 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
1024 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
1025 Such values can be the left hand side x in (x << r), using the zvdepi
1028 lhs_lshift_cint_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1030 unsigned HOST_WIDE_INT x;
1031 if (GET_CODE (op) != CONST_INT)
1033 x = INTVAL (op) >> 4;
1034 return (x & (x + 1)) == 0;
1038 arith32_operand (rtx op, enum machine_mode mode)
1040 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
1044 pc_or_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1046 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
1049 /* Legitimize PIC addresses. If the address is already
1050 position-independent, we return ORIG. Newly generated
1051 position-independent addresses go to REG. If we need more
1052 than one register, we lose. */
1055 legitimize_pic_address (rtx orig, enum machine_mode mode, rtx reg)
1059 /* Labels need special handling. */
1060 if (pic_label_operand (orig, mode))
1062 /* We do not want to go through the movXX expanders here since that
1063 would create recursion.
1065 Nor do we really want to call a generator for a named pattern
1066 since that requires multiple patterns if we want to support
1067 multiple word sizes.
1069 So instead we just emit the raw set, which avoids the movXX
1070 expanders completely. */
1071 mark_reg_pointer (reg, BITS_PER_UNIT);
1072 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
1073 current_function_uses_pic_offset_table = 1;
1076 if (GET_CODE (orig) == SYMBOL_REF)
1083 /* Before reload, allocate a temporary register for the intermediate
1084 result. This allows the sequence to be deleted when the final
1085 result is unused and the insns are trivially dead. */
1086 tmp_reg = ((reload_in_progress || reload_completed)
1087 ? reg : gen_reg_rtx (Pmode));
1089 emit_move_insn (tmp_reg,
1090 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
1091 gen_rtx_HIGH (word_mode, orig)));
1093 = gen_const_mem (Pmode,
1094 gen_rtx_LO_SUM (Pmode, tmp_reg,
1095 gen_rtx_UNSPEC (Pmode,
1096 gen_rtvec (1, orig),
1097 UNSPEC_DLTIND14R)));
1099 current_function_uses_pic_offset_table = 1;
1100 mark_reg_pointer (reg, BITS_PER_UNIT);
1101 insn = emit_move_insn (reg, pic_ref);
1103 /* Put a REG_EQUAL note on this insn, so that it can be optimized. */
1104 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUAL, orig, REG_NOTES (insn));
1108 else if (GET_CODE (orig) == CONST)
1112 if (GET_CODE (XEXP (orig, 0)) == PLUS
1113 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
1119 if (GET_CODE (XEXP (orig, 0)) == PLUS)
1121 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
1122 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
1123 base == reg ? 0 : reg);
1128 if (GET_CODE (orig) == CONST_INT)
1130 if (INT_14_BITS (orig))
1131 return plus_constant (base, INTVAL (orig));
1132 orig = force_reg (Pmode, orig);
1134 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
1135 /* Likewise, should we set special REG_NOTEs here? */
1141 /* Try machine-dependent ways of modifying an illegitimate address
1142 to be legitimate. If we find one, return the new, valid address.
1143 This macro is used in only one place: `memory_address' in explow.c.
1145 OLDX is the address as it was before break_out_memory_refs was called.
1146 In some cases it is useful to look at this to decide what needs to be done.
1148 MODE and WIN are passed so that this macro can use
1149 GO_IF_LEGITIMATE_ADDRESS.
1151 It is always safe for this macro to do nothing. It exists to recognize
1152 opportunities to optimize the output.
1154 For the PA, transform:
1156 memory(X + <large int>)
1160 if (<large int> & mask) >= 16
1161 Y = (<large int> & ~mask) + mask + 1 Round up.
1163 Y = (<large int> & ~mask) Round down.
1165 memory (Z + (<large int> - Y));
1167 This is for CSE to find several similar references, and only use one Z.
1169 X can either be a SYMBOL_REF or REG, but because combine cannot
1170 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
1171 D will not fit in 14 bits.
1173 MODE_FLOAT references allow displacements which fit in 5 bits, so use
1176 MODE_INT references allow displacements which fit in 14 bits, so use
1179 This relies on the fact that most mode MODE_FLOAT references will use FP
1180 registers and most mode MODE_INT references will use integer registers.
1181 (In the rare case of an FP register used in an integer MODE, we depend
1182 on secondary reloads to clean things up.)
1185 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
1186 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
1187 addressing modes to be used).
1189 Put X and Z into registers. Then put the entire expression into
1193 hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1194 enum machine_mode mode)
1198 /* We need to canonicalize the order of operands in unscaled indexed
1199 addresses since the code that checks if an address is valid doesn't
1200 always try both orders. */
1201 if (!TARGET_NO_SPACE_REGS
1202 && GET_CODE (x) == PLUS
1203 && GET_MODE (x) == Pmode
1204 && REG_P (XEXP (x, 0))
1205 && REG_P (XEXP (x, 1))
1206 && REG_POINTER (XEXP (x, 0))
1207 && !REG_POINTER (XEXP (x, 1)))
1208 return gen_rtx_PLUS (Pmode, XEXP (x, 1), XEXP (x, 0));
1211 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
1213 /* Strip off CONST. */
1214 if (GET_CODE (x) == CONST)
1217 /* Special case. Get the SYMBOL_REF into a register and use indexing.
1218 That should always be safe. */
1219 if (GET_CODE (x) == PLUS
1220 && GET_CODE (XEXP (x, 0)) == REG
1221 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1223 rtx reg = force_reg (Pmode, XEXP (x, 1));
1224 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1227 /* Note we must reject symbols which represent function addresses
1228 since the assembler/linker can't handle arithmetic on plabels. */
1229 if (GET_CODE (x) == PLUS
1230 && GET_CODE (XEXP (x, 1)) == CONST_INT
1231 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1232 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1233 || GET_CODE (XEXP (x, 0)) == REG))
1235 rtx int_part, ptr_reg;
1237 int offset = INTVAL (XEXP (x, 1));
1240 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1241 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1243 /* Choose which way to round the offset. Round up if we
1244 are >= halfway to the next boundary. */
1245 if ((offset & mask) >= ((mask + 1) / 2))
1246 newoffset = (offset & ~ mask) + mask + 1;
1248 newoffset = (offset & ~ mask);
1250 /* If the newoffset will not fit in 14 bits (ldo), then
1251 handling this would take 4 or 5 instructions (2 to load
1252 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1253 add the new offset and the SYMBOL_REF.) Combine can
1254 not handle 4->2 or 5->2 combinations, so do not create
1256 if (! VAL_14_BITS_P (newoffset)
1257 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1259 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1262 gen_rtx_HIGH (Pmode, const_part));
1265 gen_rtx_LO_SUM (Pmode,
1266 tmp_reg, const_part));
1270 if (! VAL_14_BITS_P (newoffset))
1271 int_part = force_reg (Pmode, GEN_INT (newoffset));
1273 int_part = GEN_INT (newoffset);
1275 ptr_reg = force_reg (Pmode,
1276 gen_rtx_PLUS (Pmode,
1277 force_reg (Pmode, XEXP (x, 0)),
1280 return plus_constant (ptr_reg, offset - newoffset);
1283 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1285 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1286 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1287 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1288 && (OBJECT_P (XEXP (x, 1))
1289 || GET_CODE (XEXP (x, 1)) == SUBREG)
1290 && GET_CODE (XEXP (x, 1)) != CONST)
1292 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1296 if (GET_CODE (reg1) != REG)
1297 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1299 reg2 = XEXP (XEXP (x, 0), 0);
1300 if (GET_CODE (reg2) != REG)
1301 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1303 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1304 gen_rtx_MULT (Pmode,
1310 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1312 Only do so for floating point modes since this is more speculative
1313 and we lose if it's an integer store. */
1314 if (GET_CODE (x) == PLUS
1315 && GET_CODE (XEXP (x, 0)) == PLUS
1316 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1317 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1318 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1319 && (mode == SFmode || mode == DFmode))
1322 /* First, try and figure out what to use as a base register. */
1323 rtx reg1, reg2, base, idx, orig_base;
1325 reg1 = XEXP (XEXP (x, 0), 1);
1330 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1331 then emit_move_sequence will turn on REG_POINTER so we'll know
1332 it's a base register below. */
1333 if (GET_CODE (reg1) != REG)
1334 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1336 if (GET_CODE (reg2) != REG)
1337 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1339 /* Figure out what the base and index are. */
1341 if (GET_CODE (reg1) == REG
1342 && REG_POINTER (reg1))
1345 orig_base = XEXP (XEXP (x, 0), 1);
1346 idx = gen_rtx_PLUS (Pmode,
1347 gen_rtx_MULT (Pmode,
1348 XEXP (XEXP (XEXP (x, 0), 0), 0),
1349 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1352 else if (GET_CODE (reg2) == REG
1353 && REG_POINTER (reg2))
1356 orig_base = XEXP (x, 1);
1363 /* If the index adds a large constant, try to scale the
1364 constant so that it can be loaded with only one insn. */
1365 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1366 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1367 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1368 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1370 /* Divide the CONST_INT by the scale factor, then add it to A. */
1371 int val = INTVAL (XEXP (idx, 1));
1373 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1374 reg1 = XEXP (XEXP (idx, 0), 0);
1375 if (GET_CODE (reg1) != REG)
1376 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1378 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1380 /* We can now generate a simple scaled indexed address. */
1383 (Pmode, gen_rtx_PLUS (Pmode,
1384 gen_rtx_MULT (Pmode, reg1,
1385 XEXP (XEXP (idx, 0), 1)),
1389 /* If B + C is still a valid base register, then add them. */
1390 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1391 && INTVAL (XEXP (idx, 1)) <= 4096
1392 && INTVAL (XEXP (idx, 1)) >= -4096)
1394 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1397 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1399 reg2 = XEXP (XEXP (idx, 0), 0);
1400 if (GET_CODE (reg2) != CONST_INT)
1401 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1403 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1404 gen_rtx_MULT (Pmode,
1410 /* Get the index into a register, then add the base + index and
1411 return a register holding the result. */
1413 /* First get A into a register. */
1414 reg1 = XEXP (XEXP (idx, 0), 0);
1415 if (GET_CODE (reg1) != REG)
1416 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1418 /* And get B into a register. */
1419 reg2 = XEXP (idx, 1);
1420 if (GET_CODE (reg2) != REG)
1421 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1423 reg1 = force_reg (Pmode,
1424 gen_rtx_PLUS (Pmode,
1425 gen_rtx_MULT (Pmode, reg1,
1426 XEXP (XEXP (idx, 0), 1)),
1429 /* Add the result to our base register and return. */
1430 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1434 /* Uh-oh. We might have an address for x[n-100000]. This needs
1435 special handling to avoid creating an indexed memory address
1436 with x-100000 as the base.
1438 If the constant part is small enough, then it's still safe because
1439 there is a guard page at the beginning and end of the data segment.
1441 Scaled references are common enough that we want to try and rearrange the
1442 terms so that we can use indexing for these addresses too. Only
1443 do the optimization for floatint point modes. */
1445 if (GET_CODE (x) == PLUS
1446 && symbolic_expression_p (XEXP (x, 1)))
1448 /* Ugly. We modify things here so that the address offset specified
1449 by the index expression is computed first, then added to x to form
1450 the entire address. */
1452 rtx regx1, regx2, regy1, regy2, y;
1454 /* Strip off any CONST. */
1456 if (GET_CODE (y) == CONST)
1459 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1461 /* See if this looks like
1462 (plus (mult (reg) (shadd_const))
1463 (const (plus (symbol_ref) (const_int))))
1465 Where const_int is small. In that case the const
1466 expression is a valid pointer for indexing.
1468 If const_int is big, but can be divided evenly by shadd_const
1469 and added to (reg). This allows more scaled indexed addresses. */
1470 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1471 && GET_CODE (XEXP (x, 0)) == MULT
1472 && GET_CODE (XEXP (y, 1)) == CONST_INT
1473 && INTVAL (XEXP (y, 1)) >= -4096
1474 && INTVAL (XEXP (y, 1)) <= 4095
1475 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1476 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1478 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1482 if (GET_CODE (reg1) != REG)
1483 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1485 reg2 = XEXP (XEXP (x, 0), 0);
1486 if (GET_CODE (reg2) != REG)
1487 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1489 return force_reg (Pmode,
1490 gen_rtx_PLUS (Pmode,
1491 gen_rtx_MULT (Pmode,
1496 else if ((mode == DFmode || mode == SFmode)
1497 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1498 && GET_CODE (XEXP (x, 0)) == MULT
1499 && GET_CODE (XEXP (y, 1)) == CONST_INT
1500 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1501 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1502 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1505 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1506 / INTVAL (XEXP (XEXP (x, 0), 1))));
1507 regx2 = XEXP (XEXP (x, 0), 0);
1508 if (GET_CODE (regx2) != REG)
1509 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1510 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1514 gen_rtx_PLUS (Pmode,
1515 gen_rtx_MULT (Pmode, regx2,
1516 XEXP (XEXP (x, 0), 1)),
1517 force_reg (Pmode, XEXP (y, 0))));
1519 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1520 && INTVAL (XEXP (y, 1)) >= -4096
1521 && INTVAL (XEXP (y, 1)) <= 4095)
1523 /* This is safe because of the guard page at the
1524 beginning and end of the data space. Just
1525 return the original address. */
1530 /* Doesn't look like one we can optimize. */
1531 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1532 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1533 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1534 regx1 = force_reg (Pmode,
1535 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1537 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1545 /* For the HPPA, REG and REG+CONST is cost 0
1546 and addresses involving symbolic constants are cost 2.
1548 PIC addresses are very expensive.
1550 It is no coincidence that this has the same structure
1551 as GO_IF_LEGITIMATE_ADDRESS. */
1554 hppa_address_cost (rtx X)
1556 switch (GET_CODE (X))
1569 /* Compute a (partial) cost for rtx X. Return true if the complete
1570 cost has been computed, and false if subexpressions should be
1571 scanned. In either case, *TOTAL contains the cost result. */
1574 hppa_rtx_costs (rtx x, int code, int outer_code, int *total)
1579 if (INTVAL (x) == 0)
1581 else if (INT_14_BITS (x))
1598 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1599 && outer_code != SET)
1606 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1607 *total = COSTS_N_INSNS (3);
1608 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1609 *total = COSTS_N_INSNS (8);
1611 *total = COSTS_N_INSNS (20);
1615 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1617 *total = COSTS_N_INSNS (14);
1625 *total = COSTS_N_INSNS (60);
1628 case PLUS: /* this includes shNadd insns */
1630 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1631 *total = COSTS_N_INSNS (3);
1633 *total = COSTS_N_INSNS (1);
1639 *total = COSTS_N_INSNS (1);
1647 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1648 new rtx with the correct mode. */
1650 force_mode (enum machine_mode mode, rtx orig)
1652 if (mode == GET_MODE (orig))
1655 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1658 return gen_rtx_REG (mode, REGNO (orig));
1661 /* Emit insns to move operands[1] into operands[0].
1663 Return 1 if we have written out everything that needs to be done to
1664 do the move. Otherwise, return 0 and the caller will emit the move
1667 Note SCRATCH_REG may not be in the proper mode depending on how it
1668 will be used. This routine is responsible for creating a new copy
1669 of SCRATCH_REG in the proper mode. */
1672 emit_move_sequence (rtx *operands, enum machine_mode mode, rtx scratch_reg)
1674 register rtx operand0 = operands[0];
1675 register rtx operand1 = operands[1];
1678 /* We can only handle indexed addresses in the destination operand
1679 of floating point stores. Thus, we need to break out indexed
1680 addresses from the destination operand. */
1681 if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
1683 /* This is only safe up to the beginning of life analysis. */
1687 tem = copy_to_mode_reg (Pmode, XEXP (operand0, 0));
1688 operand0 = replace_equiv_address (operand0, tem);
1691 /* On targets with non-equivalent space registers, break out unscaled
1692 indexed addresses from the source operand before the final CSE.
1693 We have to do this because the REG_POINTER flag is not correctly
1694 carried through various optimization passes and CSE may substitute
1695 a pseudo without the pointer set for one with the pointer set. As
1696 a result, we loose various opportunities to create insns with
1697 unscaled indexed addresses. */
1698 if (!TARGET_NO_SPACE_REGS
1699 && !cse_not_expected
1700 && GET_CODE (operand1) == MEM
1701 && GET_CODE (XEXP (operand1, 0)) == PLUS
1702 && REG_P (XEXP (XEXP (operand1, 0), 0))
1703 && REG_P (XEXP (XEXP (operand1, 0), 1)))
1705 = replace_equiv_address (operand1,
1706 copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
1709 && reload_in_progress && GET_CODE (operand0) == REG
1710 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1711 operand0 = reg_equiv_mem[REGNO (operand0)];
1712 else if (scratch_reg
1713 && reload_in_progress && GET_CODE (operand0) == SUBREG
1714 && GET_CODE (SUBREG_REG (operand0)) == REG
1715 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1717 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1718 the code which tracks sets/uses for delete_output_reload. */
1719 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1720 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1721 SUBREG_BYTE (operand0));
1722 operand0 = alter_subreg (&temp);
1726 && reload_in_progress && GET_CODE (operand1) == REG
1727 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1728 operand1 = reg_equiv_mem[REGNO (operand1)];
1729 else if (scratch_reg
1730 && reload_in_progress && GET_CODE (operand1) == SUBREG
1731 && GET_CODE (SUBREG_REG (operand1)) == REG
1732 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1734 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1735 the code which tracks sets/uses for delete_output_reload. */
1736 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1737 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1738 SUBREG_BYTE (operand1));
1739 operand1 = alter_subreg (&temp);
1742 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1743 && ((tem = find_replacement (&XEXP (operand0, 0)))
1744 != XEXP (operand0, 0)))
1745 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1747 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1748 && ((tem = find_replacement (&XEXP (operand1, 0)))
1749 != XEXP (operand1, 0)))
1750 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1752 /* Handle secondary reloads for loads/stores of FP registers from
1753 REG+D addresses where D does not fit in 5 or 14 bits, including
1754 (subreg (mem (addr))) cases. */
1756 && fp_reg_operand (operand0, mode)
1757 && ((GET_CODE (operand1) == MEM
1758 && !memory_address_p ((GET_MODE_SIZE (mode) == 4 ? SFmode : DFmode),
1759 XEXP (operand1, 0)))
1760 || ((GET_CODE (operand1) == SUBREG
1761 && GET_CODE (XEXP (operand1, 0)) == MEM
1762 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1764 XEXP (XEXP (operand1, 0), 0))))))
1766 if (GET_CODE (operand1) == SUBREG)
1767 operand1 = XEXP (operand1, 0);
1769 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1770 it in WORD_MODE regardless of what mode it was originally given
1772 scratch_reg = force_mode (word_mode, scratch_reg);
1774 /* D might not fit in 14 bits either; for such cases load D into
1776 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1778 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1779 emit_move_insn (scratch_reg,
1780 gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1782 XEXP (XEXP (operand1, 0), 0),
1786 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1787 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1788 gen_rtx_MEM (mode, scratch_reg)));
1791 else if (scratch_reg
1792 && fp_reg_operand (operand1, mode)
1793 && ((GET_CODE (operand0) == MEM
1794 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1796 XEXP (operand0, 0)))
1797 || ((GET_CODE (operand0) == SUBREG)
1798 && GET_CODE (XEXP (operand0, 0)) == MEM
1799 && !memory_address_p ((GET_MODE_SIZE (mode) == 4
1801 XEXP (XEXP (operand0, 0), 0)))))
1803 if (GET_CODE (operand0) == SUBREG)
1804 operand0 = XEXP (operand0, 0);
1806 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1807 it in WORD_MODE regardless of what mode it was originally given
1809 scratch_reg = force_mode (word_mode, scratch_reg);
1811 /* D might not fit in 14 bits either; for such cases load D into
1813 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1815 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1816 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1819 XEXP (XEXP (operand0, 0),
1824 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1825 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1829 /* Handle secondary reloads for loads of FP registers from constant
1830 expressions by forcing the constant into memory.
1832 Use scratch_reg to hold the address of the memory location.
1834 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1835 NO_REGS when presented with a const_int and a register class
1836 containing only FP registers. Doing so unfortunately creates
1837 more problems than it solves. Fix this for 2.5. */
1838 else if (scratch_reg
1839 && CONSTANT_P (operand1)
1840 && fp_reg_operand (operand0, mode))
1844 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1845 it in WORD_MODE regardless of what mode it was originally given
1847 scratch_reg = force_mode (word_mode, scratch_reg);
1849 /* Force the constant into memory and put the address of the
1850 memory location into scratch_reg. */
1851 xoperands[0] = scratch_reg;
1852 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1853 emit_move_sequence (xoperands, Pmode, 0);
1855 /* Now load the destination register. */
1856 emit_insn (gen_rtx_SET (mode, operand0,
1857 gen_rtx_MEM (mode, scratch_reg)));
1860 /* Handle secondary reloads for SAR. These occur when trying to load
1861 the SAR from memory, FP register, or with a constant. */
1862 else if (scratch_reg
1863 && GET_CODE (operand0) == REG
1864 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1865 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1866 && (GET_CODE (operand1) == MEM
1867 || GET_CODE (operand1) == CONST_INT
1868 || (GET_CODE (operand1) == REG
1869 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1))))))
1871 /* D might not fit in 14 bits either; for such cases load D into
1873 if (GET_CODE (operand1) == MEM
1874 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1876 /* We are reloading the address into the scratch register, so we
1877 want to make sure the scratch register is a full register. */
1878 scratch_reg = force_mode (word_mode, scratch_reg);
1880 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1881 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1884 XEXP (XEXP (operand1, 0),
1888 /* Now we are going to load the scratch register from memory,
1889 we want to load it in the same width as the original MEM,
1890 which must be the same as the width of the ultimate destination,
1892 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1894 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1899 /* We want to load the scratch register using the same mode as
1900 the ultimate destination. */
1901 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1903 emit_move_insn (scratch_reg, operand1);
1906 /* And emit the insn to set the ultimate destination. We know that
1907 the scratch register has the same mode as the destination at this
1909 emit_move_insn (operand0, scratch_reg);
1912 /* Handle the most common case: storing into a register. */
1913 else if (register_operand (operand0, mode))
1915 if (register_operand (operand1, mode)
1916 || (GET_CODE (operand1) == CONST_INT
1917 && cint_ok_for_move (INTVAL (operand1)))
1918 || (operand1 == CONST0_RTX (mode))
1919 || (GET_CODE (operand1) == HIGH
1920 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1921 /* Only `general_operands' can come here, so MEM is ok. */
1922 || GET_CODE (operand1) == MEM)
1924 /* Various sets are created during RTL generation which don't
1925 have the REG_POINTER flag correctly set. After the CSE pass,
1926 instruction recognition can fail if we don't consistently
1927 set this flag when performing register copies. This should
1928 also improve the opportunities for creating insns that use
1929 unscaled indexing. */
1930 if (REG_P (operand0) && REG_P (operand1))
1932 if (REG_POINTER (operand1)
1933 && !REG_POINTER (operand0)
1934 && !HARD_REGISTER_P (operand0))
1935 copy_reg_pointer (operand0, operand1);
1936 else if (REG_POINTER (operand0)
1937 && !REG_POINTER (operand1)
1938 && !HARD_REGISTER_P (operand1))
1939 copy_reg_pointer (operand1, operand0);
1942 /* When MEMs are broken out, the REG_POINTER flag doesn't
1943 get set. In some cases, we can set the REG_POINTER flag
1944 from the declaration for the MEM. */
1945 if (REG_P (operand0)
1946 && GET_CODE (operand1) == MEM
1947 && !REG_POINTER (operand0))
1949 tree decl = MEM_EXPR (operand1);
1951 /* Set the register pointer flag and register alignment
1952 if the declaration for this memory reference is a
1953 pointer type. Fortran indirect argument references
1956 && !(flag_argument_noalias > 1
1957 && TREE_CODE (decl) == INDIRECT_REF
1958 && TREE_CODE (TREE_OPERAND (decl, 0)) == PARM_DECL))
1962 /* If this is a COMPONENT_REF, use the FIELD_DECL from
1964 if (TREE_CODE (decl) == COMPONENT_REF)
1965 decl = TREE_OPERAND (decl, 1);
1967 type = TREE_TYPE (decl);
1968 if (TREE_CODE (type) == ARRAY_TYPE)
1969 type = get_inner_array_type (type);
1971 if (POINTER_TYPE_P (type))
1975 type = TREE_TYPE (type);
1976 /* Using TYPE_ALIGN_OK is rather conservative as
1977 only the ada frontend actually sets it. */
1978 align = (TYPE_ALIGN_OK (type) ? TYPE_ALIGN (type)
1980 mark_reg_pointer (operand0, align);
1985 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1989 else if (GET_CODE (operand0) == MEM)
1991 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1992 && !(reload_in_progress || reload_completed))
1994 rtx temp = gen_reg_rtx (DFmode);
1996 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1997 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
2000 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
2002 /* Run this case quickly. */
2003 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
2006 if (! (reload_in_progress || reload_completed))
2008 operands[0] = validize_mem (operand0);
2009 operands[1] = operand1 = force_reg (mode, operand1);
2013 /* Simplify the source if we need to.
2014 Note we do have to handle function labels here, even though we do
2015 not consider them legitimate constants. Loop optimizations can
2016 call the emit_move_xxx with one as a source. */
2017 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
2018 || function_label_operand (operand1, mode)
2019 || (GET_CODE (operand1) == HIGH
2020 && symbolic_operand (XEXP (operand1, 0), mode)))
2024 if (GET_CODE (operand1) == HIGH)
2027 operand1 = XEXP (operand1, 0);
2029 if (symbolic_operand (operand1, mode))
2031 /* Argh. The assembler and linker can't handle arithmetic
2034 So we force the plabel into memory, load operand0 from
2035 the memory location, then add in the constant part. */
2036 if ((GET_CODE (operand1) == CONST
2037 && GET_CODE (XEXP (operand1, 0)) == PLUS
2038 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
2039 || function_label_operand (operand1, mode))
2041 rtx temp, const_part;
2043 /* Figure out what (if any) scratch register to use. */
2044 if (reload_in_progress || reload_completed)
2046 scratch_reg = scratch_reg ? scratch_reg : operand0;
2047 /* SCRATCH_REG will hold an address and maybe the actual
2048 data. We want it in WORD_MODE regardless of what mode it
2049 was originally given to us. */
2050 scratch_reg = force_mode (word_mode, scratch_reg);
2053 scratch_reg = gen_reg_rtx (Pmode);
2055 if (GET_CODE (operand1) == CONST)
2057 /* Save away the constant part of the expression. */
2058 const_part = XEXP (XEXP (operand1, 0), 1);
2059 if (GET_CODE (const_part) != CONST_INT)
2062 /* Force the function label into memory. */
2063 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
2067 /* No constant part. */
2068 const_part = NULL_RTX;
2070 /* Force the function label into memory. */
2071 temp = force_const_mem (mode, operand1);
2075 /* Get the address of the memory location. PIC-ify it if
2077 temp = XEXP (temp, 0);
2079 temp = legitimize_pic_address (temp, mode, scratch_reg);
2081 /* Put the address of the memory location into our destination
2084 emit_move_sequence (operands, mode, scratch_reg);
2086 /* Now load from the memory location into our destination
2088 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
2089 emit_move_sequence (operands, mode, scratch_reg);
2091 /* And add back in the constant part. */
2092 if (const_part != NULL_RTX)
2093 expand_inc (operand0, const_part);
2102 if (reload_in_progress || reload_completed)
2104 temp = scratch_reg ? scratch_reg : operand0;
2105 /* TEMP will hold an address and maybe the actual
2106 data. We want it in WORD_MODE regardless of what mode it
2107 was originally given to us. */
2108 temp = force_mode (word_mode, temp);
2111 temp = gen_reg_rtx (Pmode);
2113 /* (const (plus (symbol) (const_int))) must be forced to
2114 memory during/after reload if the const_int will not fit
2116 if (GET_CODE (operand1) == CONST
2117 && GET_CODE (XEXP (operand1, 0)) == PLUS
2118 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
2119 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
2120 && (reload_completed || reload_in_progress)
2123 operands[1] = force_const_mem (mode, operand1);
2124 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
2126 operands[1] = gen_rtx_MEM (mode, operands[1]);
2127 emit_move_sequence (operands, mode, temp);
2131 operands[1] = legitimize_pic_address (operand1, mode, temp);
2132 if (REG_P (operand0) && REG_P (operands[1]))
2133 copy_reg_pointer (operand0, operands[1]);
2134 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
2137 /* On the HPPA, references to data space are supposed to use dp,
2138 register 27, but showing it in the RTL inhibits various cse
2139 and loop optimizations. */
2144 if (reload_in_progress || reload_completed)
2146 temp = scratch_reg ? scratch_reg : operand0;
2147 /* TEMP will hold an address and maybe the actual
2148 data. We want it in WORD_MODE regardless of what mode it
2149 was originally given to us. */
2150 temp = force_mode (word_mode, temp);
2153 temp = gen_reg_rtx (mode);
2155 /* Loading a SYMBOL_REF into a register makes that register
2156 safe to be used as the base in an indexed address.
2158 Don't mark hard registers though. That loses. */
2159 if (GET_CODE (operand0) == REG
2160 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
2161 mark_reg_pointer (operand0, BITS_PER_UNIT);
2162 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
2163 mark_reg_pointer (temp, BITS_PER_UNIT);
2166 set = gen_rtx_SET (mode, operand0, temp);
2168 set = gen_rtx_SET (VOIDmode,
2170 gen_rtx_LO_SUM (mode, temp, operand1));
2172 emit_insn (gen_rtx_SET (VOIDmode,
2174 gen_rtx_HIGH (mode, operand1)));
2180 else if (GET_CODE (operand1) != CONST_INT
2181 || !cint_ok_for_move (INTVAL (operand1)))
2185 HOST_WIDE_INT value = 0;
2186 HOST_WIDE_INT insv = 0;
2189 if (GET_CODE (operand1) == CONST_INT)
2190 value = INTVAL (operand1);
2193 && GET_CODE (operand1) == CONST_INT
2194 && HOST_BITS_PER_WIDE_INT > 32
2195 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
2199 /* Extract the low order 32 bits of the value and sign extend.
2200 If the new value is the same as the original value, we can
2201 can use the original value as-is. If the new value is
2202 different, we use it and insert the most-significant 32-bits
2203 of the original value into the final result. */
2204 nval = ((value & (((HOST_WIDE_INT) 2 << 31) - 1))
2205 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
2208 #if HOST_BITS_PER_WIDE_INT > 32
2209 insv = value >= 0 ? value >> 32 : ~(~value >> 32);
2213 operand1 = GEN_INT (nval);
2217 if (reload_in_progress || reload_completed)
2218 temp = scratch_reg ? scratch_reg : operand0;
2220 temp = gen_reg_rtx (mode);
2222 /* We don't directly split DImode constants on 32-bit targets
2223 because PLUS uses an 11-bit immediate and the insn sequence
2224 generated is not as efficient as the one using HIGH/LO_SUM. */
2225 if (GET_CODE (operand1) == CONST_INT
2226 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
2229 /* Directly break constant into high and low parts. This
2230 provides better optimization opportunities because various
2231 passes recognize constants split with PLUS but not LO_SUM.
2232 We use a 14-bit signed low part except when the addition
2233 of 0x4000 to the high part might change the sign of the
2235 HOST_WIDE_INT low = value & 0x3fff;
2236 HOST_WIDE_INT high = value & ~ 0x3fff;
2240 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
2248 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
2249 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
2253 emit_insn (gen_rtx_SET (VOIDmode, temp,
2254 gen_rtx_HIGH (mode, operand1)));
2255 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
2258 insn = emit_move_insn (operands[0], operands[1]);
2260 /* Now insert the most significant 32 bits of the value
2261 into the register. When we don't have a second register
2262 available, it could take up to nine instructions to load
2263 a 64-bit integer constant. Prior to reload, we force
2264 constants that would take more than three instructions
2265 to load to the constant pool. During and after reload,
2266 we have to handle all possible values. */
2269 /* Use a HIGH/LO_SUM/INSV sequence if we have a second
2270 register and the value to be inserted is outside the
2271 range that can be loaded with three depdi instructions. */
2272 if (temp != operand0 && (insv >= 16384 || insv < -16384))
2274 operand1 = GEN_INT (insv);
2276 emit_insn (gen_rtx_SET (VOIDmode, temp,
2277 gen_rtx_HIGH (mode, operand1)));
2278 emit_move_insn (temp, gen_rtx_LO_SUM (mode, temp, operand1));
2279 emit_insn (gen_insv (operand0, GEN_INT (32),
2284 int len = 5, pos = 27;
2286 /* Insert the bits using the depdi instruction. */
2289 HOST_WIDE_INT v5 = ((insv & 31) ^ 16) - 16;
2290 HOST_WIDE_INT sign = v5 < 0;
2292 /* Left extend the insertion. */
2293 insv = (insv >= 0 ? insv >> len : ~(~insv >> len));
2294 while (pos > 0 && (insv & 1) == sign)
2296 insv = (insv >= 0 ? insv >> 1 : ~(~insv >> 1));
2301 emit_insn (gen_insv (operand0, GEN_INT (len),
2302 GEN_INT (pos), GEN_INT (v5)));
2304 len = pos > 0 && pos < 5 ? pos : 5;
2311 = gen_rtx_EXPR_LIST (REG_EQUAL, op1, REG_NOTES (insn));
2316 /* Now have insn-emit do whatever it normally does. */
2320 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
2321 it will need a link/runtime reloc). */
2324 reloc_needed (tree exp)
2328 switch (TREE_CODE (exp))
2335 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2336 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
2341 case NON_LVALUE_EXPR:
2342 reloc = reloc_needed (TREE_OPERAND (exp, 0));
2348 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
2349 if (TREE_VALUE (link) != 0)
2350 reloc |= reloc_needed (TREE_VALUE (link));
2363 /* Does operand (which is a symbolic_operand) live in text space?
2364 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
2368 read_only_operand (rtx operand, enum machine_mode mode ATTRIBUTE_UNUSED)
2370 if (GET_CODE (operand) == CONST)
2371 operand = XEXP (XEXP (operand, 0), 0);
2374 if (GET_CODE (operand) == SYMBOL_REF)
2375 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2379 if (GET_CODE (operand) == SYMBOL_REF)
2380 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2386 /* Return the best assembler insn template
2387 for moving operands[1] into operands[0] as a fullword. */
2389 singlemove_string (rtx *operands)
2391 HOST_WIDE_INT intval;
2393 if (GET_CODE (operands[0]) == MEM)
2394 return "stw %r1,%0";
2395 if (GET_CODE (operands[1]) == MEM)
2397 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2402 if (GET_MODE (operands[1]) != SFmode)
2405 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2407 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2408 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2410 operands[1] = GEN_INT (i);
2411 /* Fall through to CONST_INT case. */
2413 if (GET_CODE (operands[1]) == CONST_INT)
2415 intval = INTVAL (operands[1]);
2417 if (VAL_14_BITS_P (intval))
2419 else if ((intval & 0x7ff) == 0)
2420 return "ldil L'%1,%0";
2421 else if (zdepi_cint_p (intval))
2422 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2424 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2426 return "copy %1,%0";
2430 /* Compute position (in OP[1]) and width (in OP[2])
2431 useful for copying IMM to a register using the zdepi
2432 instructions. Store the immediate value to insert in OP[0]. */
2434 compute_zdepwi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2438 /* Find the least significant set bit in IMM. */
2439 for (lsb = 0; lsb < 32; lsb++)
2446 /* Choose variants based on *sign* of the 5-bit field. */
2447 if ((imm & 0x10) == 0)
2448 len = (lsb <= 28) ? 4 : 32 - lsb;
2451 /* Find the width of the bitstring in IMM. */
2452 for (len = 5; len < 32; len++)
2454 if ((imm & (1 << len)) == 0)
2458 /* Sign extend IMM as a 5-bit value. */
2459 imm = (imm & 0xf) - 0x10;
2467 /* Compute position (in OP[1]) and width (in OP[2])
2468 useful for copying IMM to a register using the depdi,z
2469 instructions. Store the immediate value to insert in OP[0]. */
2471 compute_zdepdi_operands (unsigned HOST_WIDE_INT imm, unsigned *op)
2473 HOST_WIDE_INT lsb, len;
2475 /* Find the least significant set bit in IMM. */
2476 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2483 /* Choose variants based on *sign* of the 5-bit field. */
2484 if ((imm & 0x10) == 0)
2485 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2486 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2489 /* Find the width of the bitstring in IMM. */
2490 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2492 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2496 /* Sign extend IMM as a 5-bit value. */
2497 imm = (imm & 0xf) - 0x10;
2505 /* Output assembler code to perform a doubleword move insn
2506 with operands OPERANDS. */
2509 output_move_double (rtx *operands)
2511 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2513 rtx addreg0 = 0, addreg1 = 0;
2515 /* First classify both operands. */
2517 if (REG_P (operands[0]))
2519 else if (offsettable_memref_p (operands[0]))
2521 else if (GET_CODE (operands[0]) == MEM)
2526 if (REG_P (operands[1]))
2528 else if (CONSTANT_P (operands[1]))
2530 else if (offsettable_memref_p (operands[1]))
2532 else if (GET_CODE (operands[1]) == MEM)
2537 /* Check for the cases that the operand constraints are not
2538 supposed to allow to happen. Abort if we get one,
2539 because generating code for these cases is painful. */
2541 if (optype0 != REGOP && optype1 != REGOP)
2544 /* Handle auto decrementing and incrementing loads and stores
2545 specifically, since the structure of the function doesn't work
2546 for them without major modification. Do it better when we learn
2547 this port about the general inc/dec addressing of PA.
2548 (This was written by tege. Chide him if it doesn't work.) */
2550 if (optype0 == MEMOP)
2552 /* We have to output the address syntax ourselves, since print_operand
2553 doesn't deal with the addresses we want to use. Fix this later. */
2555 rtx addr = XEXP (operands[0], 0);
2556 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2558 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2560 operands[0] = XEXP (addr, 0);
2561 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2564 if (!reg_overlap_mentioned_p (high_reg, addr))
2566 /* No overlap between high target register and address
2567 register. (We do this in a non-obvious way to
2568 save a register file writeback) */
2569 if (GET_CODE (addr) == POST_INC)
2570 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2571 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2576 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2578 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2580 operands[0] = XEXP (addr, 0);
2581 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2584 if (!reg_overlap_mentioned_p (high_reg, addr))
2586 /* No overlap between high target register and address
2587 register. (We do this in a non-obvious way to
2588 save a register file writeback) */
2589 if (GET_CODE (addr) == PRE_INC)
2590 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2591 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2597 if (optype1 == MEMOP)
2599 /* We have to output the address syntax ourselves, since print_operand
2600 doesn't deal with the addresses we want to use. Fix this later. */
2602 rtx addr = XEXP (operands[1], 0);
2603 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2605 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2607 operands[1] = XEXP (addr, 0);
2608 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2611 if (!reg_overlap_mentioned_p (high_reg, addr))
2613 /* No overlap between high target register and address
2614 register. (We do this in a non-obvious way to
2615 save a register file writeback) */
2616 if (GET_CODE (addr) == POST_INC)
2617 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2618 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2622 /* This is an undefined situation. We should load into the
2623 address register *and* update that register. Probably
2624 we don't need to handle this at all. */
2625 if (GET_CODE (addr) == POST_INC)
2626 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2627 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2630 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2632 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2634 operands[1] = XEXP (addr, 0);
2635 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2638 if (!reg_overlap_mentioned_p (high_reg, addr))
2640 /* No overlap between high target register and address
2641 register. (We do this in a non-obvious way to
2642 save a register file writeback) */
2643 if (GET_CODE (addr) == PRE_INC)
2644 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2645 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2649 /* This is an undefined situation. We should load into the
2650 address register *and* update that register. Probably
2651 we don't need to handle this at all. */
2652 if (GET_CODE (addr) == PRE_INC)
2653 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2654 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2657 else if (GET_CODE (addr) == PLUS
2658 && GET_CODE (XEXP (addr, 0)) == MULT)
2660 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2662 if (!reg_overlap_mentioned_p (high_reg, addr))
2666 xoperands[0] = high_reg;
2667 xoperands[1] = XEXP (addr, 1);
2668 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2669 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2670 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2672 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2678 xoperands[0] = high_reg;
2679 xoperands[1] = XEXP (addr, 1);
2680 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2681 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2682 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2684 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2689 /* If an operand is an unoffsettable memory ref, find a register
2690 we can increment temporarily to make it refer to the second word. */
2692 if (optype0 == MEMOP)
2693 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2695 if (optype1 == MEMOP)
2696 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2698 /* Ok, we can do one word at a time.
2699 Normally we do the low-numbered word first.
2701 In either case, set up in LATEHALF the operands to use
2702 for the high-numbered word and in some cases alter the
2703 operands in OPERANDS to be suitable for the low-numbered word. */
2705 if (optype0 == REGOP)
2706 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2707 else if (optype0 == OFFSOP)
2708 latehalf[0] = adjust_address (operands[0], SImode, 4);
2710 latehalf[0] = operands[0];
2712 if (optype1 == REGOP)
2713 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2714 else if (optype1 == OFFSOP)
2715 latehalf[1] = adjust_address (operands[1], SImode, 4);
2716 else if (optype1 == CNSTOP)
2717 split_double (operands[1], &operands[1], &latehalf[1]);
2719 latehalf[1] = operands[1];
2721 /* If the first move would clobber the source of the second one,
2722 do them in the other order.
2724 This can happen in two cases:
2726 mem -> register where the first half of the destination register
2727 is the same register used in the memory's address. Reload
2728 can create such insns.
2730 mem in this case will be either register indirect or register
2731 indirect plus a valid offset.
2733 register -> register move where REGNO(dst) == REGNO(src + 1)
2734 someone (Tim/Tege?) claimed this can happen for parameter loads.
2736 Handle mem -> register case first. */
2737 if (optype0 == REGOP
2738 && (optype1 == MEMOP || optype1 == OFFSOP)
2739 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2742 /* Do the late half first. */
2744 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2745 output_asm_insn (singlemove_string (latehalf), latehalf);
2749 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2750 return singlemove_string (operands);
2753 /* Now handle register -> register case. */
2754 if (optype0 == REGOP && optype1 == REGOP
2755 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2757 output_asm_insn (singlemove_string (latehalf), latehalf);
2758 return singlemove_string (operands);
2761 /* Normal case: do the two words, low-numbered first. */
2763 output_asm_insn (singlemove_string (operands), operands);
2765 /* Make any unoffsettable addresses point at high-numbered word. */
2767 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2769 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2772 output_asm_insn (singlemove_string (latehalf), latehalf);
2774 /* Undo the adds we just did. */
2776 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2778 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2784 output_fp_move_double (rtx *operands)
2786 if (FP_REG_P (operands[0]))
2788 if (FP_REG_P (operands[1])
2789 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2790 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2792 output_asm_insn ("fldd%F1 %1,%0", operands);
2794 else if (FP_REG_P (operands[1]))
2796 output_asm_insn ("fstd%F0 %1,%0", operands);
2798 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2800 if (GET_CODE (operands[0]) == REG)
2803 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2804 xoperands[0] = operands[0];
2805 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2807 /* This is a pain. You have to be prepared to deal with an
2808 arbitrary address here including pre/post increment/decrement.
2810 so avoid this in the MD. */
2818 /* Return a REG that occurs in ADDR with coefficient 1.
2819 ADDR can be effectively incremented by incrementing REG. */
2822 find_addr_reg (rtx addr)
2824 while (GET_CODE (addr) == PLUS)
2826 if (GET_CODE (XEXP (addr, 0)) == REG)
2827 addr = XEXP (addr, 0);
2828 else if (GET_CODE (XEXP (addr, 1)) == REG)
2829 addr = XEXP (addr, 1);
2830 else if (CONSTANT_P (XEXP (addr, 0)))
2831 addr = XEXP (addr, 1);
2832 else if (CONSTANT_P (XEXP (addr, 1)))
2833 addr = XEXP (addr, 0);
2837 if (GET_CODE (addr) == REG)
2842 /* Emit code to perform a block move.
2844 OPERANDS[0] is the destination pointer as a REG, clobbered.
2845 OPERANDS[1] is the source pointer as a REG, clobbered.
2846 OPERANDS[2] is a register for temporary storage.
2847 OPERANDS[3] is a register for temporary storage.
2848 OPERANDS[4] is the size as a CONST_INT
2849 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2850 OPERANDS[6] is another temporary register. */
2853 output_block_move (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
2855 int align = INTVAL (operands[5]);
2856 unsigned long n_bytes = INTVAL (operands[4]);
2858 /* We can't move more than a word at a time because the PA
2859 has no longer integer move insns. (Could use fp mem ops?) */
2860 if (align > (TARGET_64BIT ? 8 : 4))
2861 align = (TARGET_64BIT ? 8 : 4);
2863 /* Note that we know each loop below will execute at least twice
2864 (else we would have open-coded the copy). */
2868 /* Pre-adjust the loop counter. */
2869 operands[4] = GEN_INT (n_bytes - 16);
2870 output_asm_insn ("ldi %4,%2", operands);
2873 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2874 output_asm_insn ("ldd,ma 8(%1),%6", operands);
2875 output_asm_insn ("std,ma %3,8(%0)", operands);
2876 output_asm_insn ("addib,>= -16,%2,.-12", operands);
2877 output_asm_insn ("std,ma %6,8(%0)", operands);
2879 /* Handle the residual. There could be up to 7 bytes of
2880 residual to copy! */
2881 if (n_bytes % 16 != 0)
2883 operands[4] = GEN_INT (n_bytes % 8);
2884 if (n_bytes % 16 >= 8)
2885 output_asm_insn ("ldd,ma 8(%1),%3", operands);
2886 if (n_bytes % 8 != 0)
2887 output_asm_insn ("ldd 0(%1),%6", operands);
2888 if (n_bytes % 16 >= 8)
2889 output_asm_insn ("std,ma %3,8(%0)", operands);
2890 if (n_bytes % 8 != 0)
2891 output_asm_insn ("stdby,e %6,%4(%0)", operands);
2896 /* Pre-adjust the loop counter. */
2897 operands[4] = GEN_INT (n_bytes - 8);
2898 output_asm_insn ("ldi %4,%2", operands);
2901 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2902 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2903 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2904 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2905 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2907 /* Handle the residual. There could be up to 7 bytes of
2908 residual to copy! */
2909 if (n_bytes % 8 != 0)
2911 operands[4] = GEN_INT (n_bytes % 4);
2912 if (n_bytes % 8 >= 4)
2913 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2914 if (n_bytes % 4 != 0)
2915 output_asm_insn ("ldw 0(%1),%6", operands);
2916 if (n_bytes % 8 >= 4)
2917 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2918 if (n_bytes % 4 != 0)
2919 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2924 /* Pre-adjust the loop counter. */
2925 operands[4] = GEN_INT (n_bytes - 4);
2926 output_asm_insn ("ldi %4,%2", operands);
2929 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2930 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2931 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2932 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2933 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2935 /* Handle the residual. */
2936 if (n_bytes % 4 != 0)
2938 if (n_bytes % 4 >= 2)
2939 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2940 if (n_bytes % 2 != 0)
2941 output_asm_insn ("ldb 0(%1),%6", operands);
2942 if (n_bytes % 4 >= 2)
2943 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2944 if (n_bytes % 2 != 0)
2945 output_asm_insn ("stb %6,0(%0)", operands);
2950 /* Pre-adjust the loop counter. */
2951 operands[4] = GEN_INT (n_bytes - 2);
2952 output_asm_insn ("ldi %4,%2", operands);
2955 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2956 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2957 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2958 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2959 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2961 /* Handle the residual. */
2962 if (n_bytes % 2 != 0)
2964 output_asm_insn ("ldb 0(%1),%3", operands);
2965 output_asm_insn ("stb %3,0(%0)", operands);
2974 /* Count the number of insns necessary to handle this block move.
2976 Basic structure is the same as emit_block_move, except that we
2977 count insns rather than emit them. */
2980 compute_movmem_length (rtx insn)
2982 rtx pat = PATTERN (insn);
2983 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2984 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2985 unsigned int n_insns = 0;
2987 /* We can't move more than four bytes at a time because the PA
2988 has no longer integer move insns. (Could use fp mem ops?) */
2989 if (align > (TARGET_64BIT ? 8 : 4))
2990 align = (TARGET_64BIT ? 8 : 4);
2992 /* The basic copying loop. */
2996 if (n_bytes % (2 * align) != 0)
2998 if ((n_bytes % (2 * align)) >= align)
3001 if ((n_bytes % align) != 0)
3005 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3009 /* Emit code to perform a block clear.
3011 OPERANDS[0] is the destination pointer as a REG, clobbered.
3012 OPERANDS[1] is a register for temporary storage.
3013 OPERANDS[2] is the size as a CONST_INT
3014 OPERANDS[3] is the alignment safe to use, as a CONST_INT. */
3017 output_block_clear (rtx *operands, int size_is_constant ATTRIBUTE_UNUSED)
3019 int align = INTVAL (operands[3]);
3020 unsigned long n_bytes = INTVAL (operands[2]);
3022 /* We can't clear more than a word at a time because the PA
3023 has no longer integer move insns. */
3024 if (align > (TARGET_64BIT ? 8 : 4))
3025 align = (TARGET_64BIT ? 8 : 4);
3027 /* Note that we know each loop below will execute at least twice
3028 (else we would have open-coded the copy). */
3032 /* Pre-adjust the loop counter. */
3033 operands[2] = GEN_INT (n_bytes - 16);
3034 output_asm_insn ("ldi %2,%1", operands);
3037 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3038 output_asm_insn ("addib,>= -16,%1,.-4", operands);
3039 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3041 /* Handle the residual. There could be up to 7 bytes of
3042 residual to copy! */
3043 if (n_bytes % 16 != 0)
3045 operands[2] = GEN_INT (n_bytes % 8);
3046 if (n_bytes % 16 >= 8)
3047 output_asm_insn ("std,ma %%r0,8(%0)", operands);
3048 if (n_bytes % 8 != 0)
3049 output_asm_insn ("stdby,e %%r0,%2(%0)", operands);
3054 /* Pre-adjust the loop counter. */
3055 operands[2] = GEN_INT (n_bytes - 8);
3056 output_asm_insn ("ldi %2,%1", operands);
3059 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3060 output_asm_insn ("addib,>= -8,%1,.-4", operands);
3061 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3063 /* Handle the residual. There could be up to 7 bytes of
3064 residual to copy! */
3065 if (n_bytes % 8 != 0)
3067 operands[2] = GEN_INT (n_bytes % 4);
3068 if (n_bytes % 8 >= 4)
3069 output_asm_insn ("{stws|stw},ma %%r0,4(%0)", operands);
3070 if (n_bytes % 4 != 0)
3071 output_asm_insn ("{stbys|stby},e %%r0,%2(%0)", operands);
3076 /* Pre-adjust the loop counter. */
3077 operands[2] = GEN_INT (n_bytes - 4);
3078 output_asm_insn ("ldi %2,%1", operands);
3081 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3082 output_asm_insn ("addib,>= -4,%1,.-4", operands);
3083 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3085 /* Handle the residual. */
3086 if (n_bytes % 4 != 0)
3088 if (n_bytes % 4 >= 2)
3089 output_asm_insn ("{sths|sth},ma %%r0,2(%0)", operands);
3090 if (n_bytes % 2 != 0)
3091 output_asm_insn ("stb %%r0,0(%0)", operands);
3096 /* Pre-adjust the loop counter. */
3097 operands[2] = GEN_INT (n_bytes - 2);
3098 output_asm_insn ("ldi %2,%1", operands);
3101 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3102 output_asm_insn ("addib,>= -2,%1,.-4", operands);
3103 output_asm_insn ("{stbs|stb},ma %%r0,1(%0)", operands);
3105 /* Handle the residual. */
3106 if (n_bytes % 2 != 0)
3107 output_asm_insn ("stb %%r0,0(%0)", operands);
3116 /* Count the number of insns necessary to handle this block move.
3118 Basic structure is the same as emit_block_move, except that we
3119 count insns rather than emit them. */
3122 compute_clrmem_length (rtx insn)
3124 rtx pat = PATTERN (insn);
3125 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 4), 0));
3126 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 3), 0));
3127 unsigned int n_insns = 0;
3129 /* We can't clear more than a word at a time because the PA
3130 has no longer integer move insns. */
3131 if (align > (TARGET_64BIT ? 8 : 4))
3132 align = (TARGET_64BIT ? 8 : 4);
3134 /* The basic loop. */
3138 if (n_bytes % (2 * align) != 0)
3140 if ((n_bytes % (2 * align)) >= align)
3143 if ((n_bytes % align) != 0)
3147 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
3153 output_and (rtx *operands)
3155 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3157 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3158 int ls0, ls1, ms0, p, len;
3160 for (ls0 = 0; ls0 < 32; ls0++)
3161 if ((mask & (1 << ls0)) == 0)
3164 for (ls1 = ls0; ls1 < 32; ls1++)
3165 if ((mask & (1 << ls1)) != 0)
3168 for (ms0 = ls1; ms0 < 32; ms0++)
3169 if ((mask & (1 << ms0)) == 0)
3182 operands[2] = GEN_INT (len);
3183 return "{extru|extrw,u} %1,31,%2,%0";
3187 /* We could use this `depi' for the case above as well, but `depi'
3188 requires one more register file access than an `extru'. */
3193 operands[2] = GEN_INT (p);
3194 operands[3] = GEN_INT (len);
3195 return "{depi|depwi} 0,%2,%3,%0";
3199 return "and %1,%2,%0";
3202 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3203 storing the result in operands[0]. */
3205 output_64bit_and (rtx *operands)
3207 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
3209 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3210 int ls0, ls1, ms0, p, len;
3212 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
3213 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
3216 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
3217 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
3220 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
3221 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
3224 if (ms0 != HOST_BITS_PER_WIDE_INT)
3227 if (ls1 == HOST_BITS_PER_WIDE_INT)
3234 operands[2] = GEN_INT (len);
3235 return "extrd,u %1,63,%2,%0";
3239 /* We could use this `depi' for the case above as well, but `depi'
3240 requires one more register file access than an `extru'. */
3245 operands[2] = GEN_INT (p);
3246 operands[3] = GEN_INT (len);
3247 return "depdi 0,%2,%3,%0";
3251 return "and %1,%2,%0";
3255 output_ior (rtx *operands)
3257 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3258 int bs0, bs1, p, len;
3260 if (INTVAL (operands[2]) == 0)
3261 return "copy %1,%0";
3263 for (bs0 = 0; bs0 < 32; bs0++)
3264 if ((mask & (1 << bs0)) != 0)
3267 for (bs1 = bs0; bs1 < 32; bs1++)
3268 if ((mask & (1 << bs1)) == 0)
3271 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3277 operands[2] = GEN_INT (p);
3278 operands[3] = GEN_INT (len);
3279 return "{depi|depwi} -1,%2,%3,%0";
3282 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
3283 storing the result in operands[0]. */
3285 output_64bit_ior (rtx *operands)
3287 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
3288 int bs0, bs1, p, len;
3290 if (INTVAL (operands[2]) == 0)
3291 return "copy %1,%0";
3293 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
3294 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
3297 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
3298 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
3301 if (bs1 != HOST_BITS_PER_WIDE_INT
3302 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
3308 operands[2] = GEN_INT (p);
3309 operands[3] = GEN_INT (len);
3310 return "depdi -1,%2,%3,%0";
3313 /* Target hook for assembling integer objects. This code handles
3314 aligned SI and DI integers specially, since function references must
3315 be preceded by P%. */
3318 pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
3320 if (size == UNITS_PER_WORD && aligned_p
3321 && function_label_operand (x, VOIDmode))
3323 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
3324 output_addr_const (asm_out_file, x);
3325 fputc ('\n', asm_out_file);
3328 return default_assemble_integer (x, size, aligned_p);
3331 /* Output an ascii string. */
3333 output_ascii (FILE *file, const char *p, int size)
3337 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
3339 /* The HP assembler can only take strings of 256 characters at one
3340 time. This is a limitation on input line length, *not* the
3341 length of the string. Sigh. Even worse, it seems that the
3342 restriction is in number of input characters (see \xnn &
3343 \whatever). So we have to do this very carefully. */
3345 fputs ("\t.STRING \"", file);
3348 for (i = 0; i < size; i += 4)
3352 for (io = 0, co = 0; io < MIN (4, size - i); io++)
3354 register unsigned int c = (unsigned char) p[i + io];
3356 if (c == '\"' || c == '\\')
3357 partial_output[co++] = '\\';
3358 if (c >= ' ' && c < 0177)
3359 partial_output[co++] = c;
3363 partial_output[co++] = '\\';
3364 partial_output[co++] = 'x';
3365 hexd = c / 16 - 0 + '0';
3367 hexd -= '9' - 'a' + 1;
3368 partial_output[co++] = hexd;
3369 hexd = c % 16 - 0 + '0';
3371 hexd -= '9' - 'a' + 1;
3372 partial_output[co++] = hexd;
3375 if (chars_output + co > 243)
3377 fputs ("\"\n\t.STRING \"", file);
3380 fwrite (partial_output, 1, (size_t) co, file);
3384 fputs ("\"\n", file);
3387 /* Try to rewrite floating point comparisons & branches to avoid
3388 useless add,tr insns.
3390 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
3391 to see if FPCC is dead. CHECK_NOTES is nonzero for the
3392 first attempt to remove useless add,tr insns. It is zero
3393 for the second pass as reorg sometimes leaves bogus REG_DEAD
3396 When CHECK_NOTES is zero we can only eliminate add,tr insns
3397 when there's a 1:1 correspondence between fcmp and ftest/fbranch
3400 remove_useless_addtr_insns (int check_notes)
3403 static int pass = 0;
3405 /* This is fairly cheap, so always run it when optimizing. */
3409 int fbranch_count = 0;
3411 /* Walk all the insns in this function looking for fcmp & fbranch
3412 instructions. Keep track of how many of each we find. */
3413 for (insn = get_insns (); insn; insn = next_insn (insn))
3417 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
3418 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
3421 tmp = PATTERN (insn);
3423 /* It must be a set. */
3424 if (GET_CODE (tmp) != SET)
3427 /* If the destination is CCFP, then we've found an fcmp insn. */
3428 tmp = SET_DEST (tmp);
3429 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
3435 tmp = PATTERN (insn);
3436 /* If this is an fbranch instruction, bump the fbranch counter. */
3437 if (GET_CODE (tmp) == SET
3438 && SET_DEST (tmp) == pc_rtx
3439 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
3440 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
3441 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
3442 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
3450 /* Find all floating point compare + branch insns. If possible,
3451 reverse the comparison & the branch to avoid add,tr insns. */
3452 for (insn = get_insns (); insn; insn = next_insn (insn))
3456 /* Ignore anything that isn't an INSN. */
3457 if (GET_CODE (insn) != INSN)
3460 tmp = PATTERN (insn);
3462 /* It must be a set. */
3463 if (GET_CODE (tmp) != SET)
3466 /* The destination must be CCFP, which is register zero. */
3467 tmp = SET_DEST (tmp);
3468 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
3471 /* INSN should be a set of CCFP.
3473 See if the result of this insn is used in a reversed FP
3474 conditional branch. If so, reverse our condition and
3475 the branch. Doing so avoids useless add,tr insns. */
3476 next = next_insn (insn);
3479 /* Jumps, calls and labels stop our search. */
3480 if (GET_CODE (next) == JUMP_INSN
3481 || GET_CODE (next) == CALL_INSN
3482 || GET_CODE (next) == CODE_LABEL)
3485 /* As does another fcmp insn. */
3486 if (GET_CODE (next) == INSN
3487 && GET_CODE (PATTERN (next)) == SET
3488 && GET_CODE (SET_DEST (PATTERN (next))) == REG
3489 && REGNO (SET_DEST (PATTERN (next))) == 0)
3492 next = next_insn (next);
3495 /* Is NEXT_INSN a branch? */
3497 && GET_CODE (next) == JUMP_INSN)
3499 rtx pattern = PATTERN (next);
3501 /* If it a reversed fp conditional branch (e.g. uses add,tr)
3502 and CCFP dies, then reverse our conditional and the branch
3503 to avoid the add,tr. */
3504 if (GET_CODE (pattern) == SET
3505 && SET_DEST (pattern) == pc_rtx
3506 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
3507 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
3508 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
3509 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
3510 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
3511 && (fcmp_count == fbranch_count
3513 && find_regno_note (next, REG_DEAD, 0))))
3515 /* Reverse the branch. */
3516 tmp = XEXP (SET_SRC (pattern), 1);
3517 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3518 XEXP (SET_SRC (pattern), 2) = tmp;
3519 INSN_CODE (next) = -1;
3521 /* Reverse our condition. */
3522 tmp = PATTERN (insn);
3523 PUT_CODE (XEXP (tmp, 1),
3524 (reverse_condition_maybe_unordered
3525 (GET_CODE (XEXP (tmp, 1)))));
3535 /* You may have trouble believing this, but this is the 32 bit HP-PA
3540 Variable arguments (optional; any number may be allocated)
3542 SP-(4*(N+9)) arg word N
3547 Fixed arguments (must be allocated; may remain unused)
3556 SP-32 External Data Pointer (DP)
3558 SP-24 External/stub RP (RP')
3562 SP-8 Calling Stub RP (RP'')
3567 SP-0 Stack Pointer (points to next available address)
3571 /* This function saves registers as follows. Registers marked with ' are
3572 this function's registers (as opposed to the previous function's).
3573 If a frame_pointer isn't needed, r4 is saved as a general register;
3574 the space for the frame pointer is still allocated, though, to keep
3580 SP (FP') Previous FP
3581 SP + 4 Alignment filler (sigh)
3582 SP + 8 Space for locals reserved here.
3586 SP + n All call saved register used.
3590 SP + o All call saved fp registers used.
3594 SP + p (SP') points to next available address.
3598 /* Global variables set by output_function_prologue(). */
3599 /* Size of frame. Need to know this to emit return insns from
3601 static HOST_WIDE_INT actual_fsize, local_fsize;
3602 static int save_fregs;
3604 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3605 Handle case where DISP > 8k by using the add_high_const patterns.
3607 Note in DISP > 8k case, we will leave the high part of the address
3608 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3611 store_reg (int reg, HOST_WIDE_INT disp, int base)
3613 rtx insn, dest, src, basereg;
3615 src = gen_rtx_REG (word_mode, reg);
3616 basereg = gen_rtx_REG (Pmode, base);
3617 if (VAL_14_BITS_P (disp))
3619 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3620 insn = emit_move_insn (dest, src);
3622 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3624 rtx delta = GEN_INT (disp);
3625 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3627 emit_move_insn (tmpreg, delta);
3628 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
3629 dest = gen_rtx_MEM (word_mode, tmpreg);
3630 insn = emit_move_insn (dest, src);
3634 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3635 gen_rtx_SET (VOIDmode,
3636 gen_rtx_MEM (word_mode,
3637 gen_rtx_PLUS (word_mode, basereg,
3645 rtx delta = GEN_INT (disp);
3646 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3647 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3649 emit_move_insn (tmpreg, high);
3650 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3651 insn = emit_move_insn (dest, src);
3655 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3656 gen_rtx_SET (VOIDmode,
3657 gen_rtx_MEM (word_mode,
3658 gen_rtx_PLUS (word_mode, basereg,
3666 RTX_FRAME_RELATED_P (insn) = 1;
3669 /* Emit RTL to store REG at the memory location specified by BASE and then
3670 add MOD to BASE. MOD must be <= 8k. */
3673 store_reg_modify (int base, int reg, HOST_WIDE_INT mod)
3675 rtx insn, basereg, srcreg, delta;
3677 if (!VAL_14_BITS_P (mod))
3680 basereg = gen_rtx_REG (Pmode, base);
3681 srcreg = gen_rtx_REG (word_mode, reg);
3682 delta = GEN_INT (mod);
3684 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3687 RTX_FRAME_RELATED_P (insn) = 1;
3689 /* RTX_FRAME_RELATED_P must be set on each frame related set
3690 in a parallel with more than one element. Don't set
3691 RTX_FRAME_RELATED_P in the first set if reg is temporary
3692 register 1. The effect of this operation is recorded in
3693 the initial copy. */
3696 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3697 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3701 /* The first element of a PARALLEL is always processed if it is
3702 a SET. Thus, we need an expression list for this case. */
3704 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3705 gen_rtx_SET (VOIDmode, basereg,
3706 gen_rtx_PLUS (word_mode, basereg, delta)),
3712 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3713 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3714 whether to add a frame note or not.
3716 In the DISP > 8k case, we leave the high part of the address in %r1.
3717 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3720 set_reg_plus_d (int reg, int base, HOST_WIDE_INT disp, int note)
3724 if (VAL_14_BITS_P (disp))
3726 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3727 plus_constant (gen_rtx_REG (Pmode, base), disp));
3729 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
3731 rtx basereg = gen_rtx_REG (Pmode, base);
3732 rtx delta = GEN_INT (disp);
3733 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3735 emit_move_insn (tmpreg, delta);
3736 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3737 gen_rtx_PLUS (Pmode, tmpreg, basereg));
3741 rtx basereg = gen_rtx_REG (Pmode, base);
3742 rtx delta = GEN_INT (disp);
3743 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3745 emit_move_insn (tmpreg,
3746 gen_rtx_PLUS (Pmode, basereg,
3747 gen_rtx_HIGH (Pmode, delta)));
3748 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3749 gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3752 if (DO_FRAME_NOTES && note)
3753 RTX_FRAME_RELATED_P (insn) = 1;
3757 compute_frame_size (HOST_WIDE_INT size, int *fregs_live)
3762 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3763 be consistent with the rounding and size calculation done here.
3764 Change them at the same time. */
3766 /* We do our own stack alignment. First, round the size of the
3767 stack locals up to a word boundary. */
3768 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3770 /* Space for previous frame pointer + filler. If any frame is
3771 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3772 waste some space here for the sake of HP compatibility. The
3773 first slot is only used when the frame pointer is needed. */
3774 if (size || frame_pointer_needed)
3775 size += STARTING_FRAME_OFFSET;
3777 /* If the current function calls __builtin_eh_return, then we need
3778 to allocate stack space for registers that will hold data for
3779 the exception handler. */
3780 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3784 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3786 size += i * UNITS_PER_WORD;
3789 /* Account for space used by the callee general register saves. */
3790 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3791 if (regs_ever_live[i])
3792 size += UNITS_PER_WORD;
3794 /* Account for space used by the callee floating point register saves. */
3795 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3796 if (regs_ever_live[i]
3797 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3801 /* We always save both halves of the FP register, so always
3802 increment the frame size by 8 bytes. */
3806 /* If any of the floating registers are saved, account for the
3807 alignment needed for the floating point register save block. */
3810 size = (size + 7) & ~7;
3815 /* The various ABIs include space for the outgoing parameters in the
3816 size of the current function's stack frame. We don't need to align
3817 for the outgoing arguments as their alignment is set by the final
3818 rounding for the frame as a whole. */
3819 size += current_function_outgoing_args_size;
3821 /* Allocate space for the fixed frame marker. This space must be
3822 allocated for any function that makes calls or allocates
3824 if (!current_function_is_leaf || size)
3825 size += TARGET_64BIT ? 48 : 32;
3827 /* Finally, round to the preferred stack boundary. */
3828 return ((size + PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1)
3829 & ~(PREFERRED_STACK_BOUNDARY / BITS_PER_UNIT - 1));
3832 /* Generate the assembly code for function entry. FILE is a stdio
3833 stream to output the code to. SIZE is an int: how many units of
3834 temporary storage to allocate.
3836 Refer to the array `regs_ever_live' to determine which registers to
3837 save; `regs_ever_live[I]' is nonzero if register number I is ever
3838 used in the function. This function is responsible for knowing
3839 which registers should not be saved even if used. */
3841 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3842 of memory. If any fpu reg is used in the function, we allocate
3843 such a block here, at the bottom of the frame, just in case it's needed.
3845 If this function is a leaf procedure, then we may choose not
3846 to do a "save" insn. The decision about whether or not
3847 to do this is made in regclass.c. */
3850 pa_output_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
3852 /* The function's label and associated .PROC must never be
3853 separated and must be output *after* any profiling declarations
3854 to avoid changing spaces/subspaces within a procedure. */
3855 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3856 fputs ("\t.PROC\n", file);
3858 /* hppa_expand_prologue does the dirty work now. We just need
3859 to output the assembler directives which denote the start
3861 fprintf (file, "\t.CALLINFO FRAME=" HOST_WIDE_INT_PRINT_DEC, actual_fsize);
3862 if (regs_ever_live[2])
3863 fputs (",CALLS,SAVE_RP", file);
3865 fputs (",NO_CALLS", file);
3867 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3868 at the beginning of the frame and that it is used as the frame
3869 pointer for the frame. We do this because our current frame
3870 layout doesn't conform to that specified in the the HP runtime
3871 documentation and we need a way to indicate to programs such as
3872 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3873 isn't used by HP compilers but is supported by the assembler.
3874 However, SAVE_SP is supposed to indicate that the previous stack
3875 pointer has been saved in the frame marker. */
3876 if (frame_pointer_needed)
3877 fputs (",SAVE_SP", file);
3879 /* Pass on information about the number of callee register saves
3880 performed in the prologue.
3882 The compiler is supposed to pass the highest register number
3883 saved, the assembler then has to adjust that number before
3884 entering it into the unwind descriptor (to account for any
3885 caller saved registers with lower register numbers than the
3886 first callee saved register). */
3888 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3891 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3893 fputs ("\n\t.ENTRY\n", file);
3895 remove_useless_addtr_insns (0);
3899 hppa_expand_prologue (void)
3901 int merge_sp_adjust_with_store = 0;
3902 HOST_WIDE_INT size = get_frame_size ();
3903 HOST_WIDE_INT offset;
3911 /* Compute total size for frame pointer, filler, locals and rounding to
3912 the next word boundary. Similar code appears in compute_frame_size
3913 and must be changed in tandem with this code. */
3914 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3915 if (local_fsize || frame_pointer_needed)
3916 local_fsize += STARTING_FRAME_OFFSET;
3918 actual_fsize = compute_frame_size (size, &save_fregs);
3920 /* Compute a few things we will use often. */
3921 tmpreg = gen_rtx_REG (word_mode, 1);
3923 /* Save RP first. The calling conventions manual states RP will
3924 always be stored into the caller's frame at sp - 20 or sp - 16
3925 depending on which ABI is in use. */
3926 if (regs_ever_live[2] || current_function_calls_eh_return)
3927 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3929 /* Allocate the local frame and set up the frame pointer if needed. */
3930 if (actual_fsize != 0)
3932 if (frame_pointer_needed)
3934 /* Copy the old frame pointer temporarily into %r1. Set up the
3935 new stack pointer, then store away the saved old frame pointer
3936 into the stack at sp and at the same time update the stack
3937 pointer by actual_fsize bytes. Two versions, first
3938 handles small (<8k) frames. The second handles large (>=8k)
3940 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3943 /* We need to record the frame pointer save here since the
3944 new frame pointer is set in the following insn. */
3945 RTX_FRAME_RELATED_P (insn) = 1;
3947 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3948 gen_rtx_SET (VOIDmode,
3949 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3954 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3956 RTX_FRAME_RELATED_P (insn) = 1;
3958 if (VAL_14_BITS_P (actual_fsize))
3959 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3962 /* It is incorrect to store the saved frame pointer at *sp,
3963 then increment sp (writes beyond the current stack boundary).
3965 So instead use stwm to store at *sp and post-increment the
3966 stack pointer as an atomic operation. Then increment sp to
3967 finish allocating the new frame. */
3968 HOST_WIDE_INT adjust1 = 8192 - 64;
3969 HOST_WIDE_INT adjust2 = actual_fsize - adjust1;
3971 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3972 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3976 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3977 we need to store the previous stack pointer (frame pointer)
3978 into the frame marker on targets that use the HP unwind
3979 library. This allows the HP unwind library to be used to
3980 unwind GCC frames. However, we are not fully compatible
3981 with the HP library because our frame layout differs from
3982 that specified in the HP runtime specification.
3984 We don't want a frame note on this instruction as the frame
3985 marker moves during dynamic stack allocation.
3987 This instruction also serves as a blockage to prevent
3988 register spills from being scheduled before the stack
3989 pointer is raised. This is necessary as we store
3990 registers using the frame pointer as a base register,
3991 and the frame pointer is set before sp is raised. */
3992 if (TARGET_HPUX_UNWIND_LIBRARY)
3994 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3995 GEN_INT (TARGET_64BIT ? -8 : -4));
3997 emit_move_insn (gen_rtx_MEM (word_mode, addr),
4001 emit_insn (gen_blockage ());
4003 /* no frame pointer needed. */
4006 /* In some cases we can perform the first callee register save
4007 and allocating the stack frame at the same time. If so, just
4008 make a note of it and defer allocating the frame until saving
4009 the callee registers. */
4010 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
4011 merge_sp_adjust_with_store = 1;
4012 /* Can not optimize. Adjust the stack frame by actual_fsize
4015 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4020 /* Normal register save.
4022 Do not save the frame pointer in the frame_pointer_needed case. It
4023 was done earlier. */
4024 if (frame_pointer_needed)
4026 offset = local_fsize;
4028 /* Saving the EH return data registers in the frame is the simplest
4029 way to get the frame unwind information emitted. We put them
4030 just before the general registers. */
4031 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4033 unsigned int i, regno;
4037 regno = EH_RETURN_DATA_REGNO (i);
4038 if (regno == INVALID_REGNUM)
4041 store_reg (regno, offset, FRAME_POINTER_REGNUM);
4042 offset += UNITS_PER_WORD;
4046 for (i = 18; i >= 4; i--)
4047 if (regs_ever_live[i] && ! call_used_regs[i])
4049 store_reg (i, offset, FRAME_POINTER_REGNUM);
4050 offset += UNITS_PER_WORD;
4053 /* Account for %r3 which is saved in a special place. */
4056 /* No frame pointer needed. */
4059 offset = local_fsize - actual_fsize;
4061 /* Saving the EH return data registers in the frame is the simplest
4062 way to get the frame unwind information emitted. */
4063 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4065 unsigned int i, regno;
4069 regno = EH_RETURN_DATA_REGNO (i);
4070 if (regno == INVALID_REGNUM)
4073 /* If merge_sp_adjust_with_store is nonzero, then we can
4074 optimize the first save. */
4075 if (merge_sp_adjust_with_store)
4077 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
4078 merge_sp_adjust_with_store = 0;
4081 store_reg (regno, offset, STACK_POINTER_REGNUM);
4082 offset += UNITS_PER_WORD;
4086 for (i = 18; i >= 3; i--)
4087 if (regs_ever_live[i] && ! call_used_regs[i])
4089 /* If merge_sp_adjust_with_store is nonzero, then we can
4090 optimize the first GR save. */
4091 if (merge_sp_adjust_with_store)
4093 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
4094 merge_sp_adjust_with_store = 0;
4097 store_reg (i, offset, STACK_POINTER_REGNUM);
4098 offset += UNITS_PER_WORD;
4102 /* If we wanted to merge the SP adjustment with a GR save, but we never
4103 did any GR saves, then just emit the adjustment here. */
4104 if (merge_sp_adjust_with_store)
4105 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4109 /* The hppa calling conventions say that %r19, the pic offset
4110 register, is saved at sp - 32 (in this function's frame)
4111 when generating PIC code. FIXME: What is the correct thing
4112 to do for functions which make no calls and allocate no
4113 frame? Do we need to allocate a frame, or can we just omit
4114 the save? For now we'll just omit the save.
4116 We don't want a note on this insn as the frame marker can
4117 move if there is a dynamic stack allocation. */
4118 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
4120 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx, GEN_INT (-32));
4122 emit_move_insn (gen_rtx_MEM (word_mode, addr), pic_offset_table_rtx);
4126 /* Align pointer properly (doubleword boundary). */
4127 offset = (offset + 7) & ~7;
4129 /* Floating point register store. */
4134 /* First get the frame or stack pointer to the start of the FP register
4136 if (frame_pointer_needed)
4138 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4139 base = frame_pointer_rtx;
4143 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4144 base = stack_pointer_rtx;
4147 /* Now actually save the FP registers. */
4148 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4150 if (regs_ever_live[i]
4151 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4153 rtx addr, insn, reg;
4154 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4155 reg = gen_rtx_REG (DFmode, i);
4156 insn = emit_move_insn (addr, reg);
4159 RTX_FRAME_RELATED_P (insn) = 1;
4162 rtx mem = gen_rtx_MEM (DFmode,
4163 plus_constant (base, offset));
4165 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4166 gen_rtx_SET (VOIDmode, mem, reg),
4171 rtx meml = gen_rtx_MEM (SFmode,
4172 plus_constant (base, offset));
4173 rtx memr = gen_rtx_MEM (SFmode,
4174 plus_constant (base, offset + 4));
4175 rtx regl = gen_rtx_REG (SFmode, i);
4176 rtx regr = gen_rtx_REG (SFmode, i + 1);
4177 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
4178 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
4181 RTX_FRAME_RELATED_P (setl) = 1;
4182 RTX_FRAME_RELATED_P (setr) = 1;
4183 vec = gen_rtvec (2, setl, setr);
4185 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
4186 gen_rtx_SEQUENCE (VOIDmode, vec),
4190 offset += GET_MODE_SIZE (DFmode);
4197 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
4198 Handle case where DISP > 8k by using the add_high_const patterns. */
4201 load_reg (int reg, HOST_WIDE_INT disp, int base)
4203 rtx dest = gen_rtx_REG (word_mode, reg);
4204 rtx basereg = gen_rtx_REG (Pmode, base);
4207 if (VAL_14_BITS_P (disp))
4208 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
4209 else if (TARGET_64BIT && !VAL_32_BITS_P (disp))
4211 rtx delta = GEN_INT (disp);
4212 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4214 emit_move_insn (tmpreg, delta);
4215 if (TARGET_DISABLE_INDEXING)
4217 emit_move_insn (tmpreg, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4218 src = gen_rtx_MEM (word_mode, tmpreg);
4221 src = gen_rtx_MEM (word_mode, gen_rtx_PLUS (Pmode, tmpreg, basereg));
4225 rtx delta = GEN_INT (disp);
4226 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
4227 rtx tmpreg = gen_rtx_REG (Pmode, 1);
4229 emit_move_insn (tmpreg, high);
4230 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
4233 emit_move_insn (dest, src);
4236 /* Update the total code bytes output to the text section. */
4239 update_total_code_bytes (int nbytes)
4241 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
4242 && !IN_NAMED_SECTION_P (cfun->decl))
4244 if (INSN_ADDRESSES_SET_P ())
4246 unsigned long old_total = total_code_bytes;
4248 total_code_bytes += nbytes;
4250 /* Be prepared to handle overflows. */
4251 if (old_total > total_code_bytes)
4252 total_code_bytes = -1;
4255 total_code_bytes = -1;
4259 /* This function generates the assembly code for function exit.
4260 Args are as for output_function_prologue ().
4262 The function epilogue should not depend on the current stack
4263 pointer! It should use the frame pointer only. This is mandatory
4264 because of alloca; we also take advantage of it to omit stack
4265 adjustments before returning. */
4268 pa_output_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED)
4270 rtx insn = get_last_insn ();
4274 /* hppa_expand_epilogue does the dirty work now. We just need
4275 to output the assembler directives which denote the end
4278 To make debuggers happy, emit a nop if the epilogue was completely
4279 eliminated due to a volatile call as the last insn in the
4280 current function. That way the return address (in %r2) will
4281 always point to a valid instruction in the current function. */
4283 /* Get the last real insn. */
4284 if (GET_CODE (insn) == NOTE)
4285 insn = prev_real_insn (insn);
4287 /* If it is a sequence, then look inside. */
4288 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
4289 insn = XVECEXP (PATTERN (insn), 0, 0);
4291 /* If insn is a CALL_INSN, then it must be a call to a volatile
4292 function (otherwise there would be epilogue insns). */
4293 if (insn && GET_CODE (insn) == CALL_INSN)
4295 fputs ("\tnop\n", file);
4299 fputs ("\t.EXIT\n\t.PROCEND\n", file);
4301 if (TARGET_SOM && TARGET_GAS)
4303 /* We done with this subspace except possibly for some additional
4304 debug information. Forget that we are in this subspace to ensure
4305 that the next function is output in its own subspace. */
4309 if (INSN_ADDRESSES_SET_P ())
4311 insn = get_last_nonnote_insn ();
4312 last_address += INSN_ADDRESSES (INSN_UID (insn));
4314 last_address += insn_default_length (insn);
4315 last_address = ((last_address + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
4316 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
4319 /* Finally, update the total number of code bytes output so far. */
4320 update_total_code_bytes (last_address);
4324 hppa_expand_epilogue (void)
4327 HOST_WIDE_INT offset;
4328 HOST_WIDE_INT ret_off = 0;
4330 int merge_sp_adjust_with_load = 0;
4332 /* We will use this often. */
4333 tmpreg = gen_rtx_REG (word_mode, 1);
4335 /* Try to restore RP early to avoid load/use interlocks when
4336 RP gets used in the return (bv) instruction. This appears to still
4337 be necessary even when we schedule the prologue and epilogue. */
4338 if (regs_ever_live [2] || current_function_calls_eh_return)
4340 ret_off = TARGET_64BIT ? -16 : -20;
4341 if (frame_pointer_needed)
4343 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
4348 /* No frame pointer, and stack is smaller than 8k. */
4349 if (VAL_14_BITS_P (ret_off - actual_fsize))
4351 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
4357 /* General register restores. */
4358 if (frame_pointer_needed)
4360 offset = local_fsize;
4362 /* If the current function calls __builtin_eh_return, then we need
4363 to restore the saved EH data registers. */
4364 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4366 unsigned int i, regno;
4370 regno = EH_RETURN_DATA_REGNO (i);
4371 if (regno == INVALID_REGNUM)
4374 load_reg (regno, offset, FRAME_POINTER_REGNUM);
4375 offset += UNITS_PER_WORD;
4379 for (i = 18; i >= 4; i--)
4380 if (regs_ever_live[i] && ! call_used_regs[i])
4382 load_reg (i, offset, FRAME_POINTER_REGNUM);
4383 offset += UNITS_PER_WORD;
4388 offset = local_fsize - actual_fsize;
4390 /* If the current function calls __builtin_eh_return, then we need
4391 to restore the saved EH data registers. */
4392 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4394 unsigned int i, regno;
4398 regno = EH_RETURN_DATA_REGNO (i);
4399 if (regno == INVALID_REGNUM)
4402 /* Only for the first load.
4403 merge_sp_adjust_with_load holds the register load
4404 with which we will merge the sp adjustment. */
4405 if (merge_sp_adjust_with_load == 0
4407 && VAL_14_BITS_P (-actual_fsize))
4408 merge_sp_adjust_with_load = regno;
4410 load_reg (regno, offset, STACK_POINTER_REGNUM);
4411 offset += UNITS_PER_WORD;
4415 for (i = 18; i >= 3; i--)
4417 if (regs_ever_live[i] && ! call_used_regs[i])
4419 /* Only for the first load.
4420 merge_sp_adjust_with_load holds the register load
4421 with which we will merge the sp adjustment. */
4422 if (merge_sp_adjust_with_load == 0
4424 && VAL_14_BITS_P (-actual_fsize))
4425 merge_sp_adjust_with_load = i;
4427 load_reg (i, offset, STACK_POINTER_REGNUM);
4428 offset += UNITS_PER_WORD;
4433 /* Align pointer properly (doubleword boundary). */
4434 offset = (offset + 7) & ~7;
4436 /* FP register restores. */
4439 /* Adjust the register to index off of. */
4440 if (frame_pointer_needed)
4441 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
4443 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
4445 /* Actually do the restores now. */
4446 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
4447 if (regs_ever_live[i]
4448 || (! TARGET_64BIT && regs_ever_live[i + 1]))
4450 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
4451 rtx dest = gen_rtx_REG (DFmode, i);
4452 emit_move_insn (dest, src);
4456 /* Emit a blockage insn here to keep these insns from being moved to
4457 an earlier spot in the epilogue, or into the main instruction stream.
4459 This is necessary as we must not cut the stack back before all the
4460 restores are finished. */
4461 emit_insn (gen_blockage ());
4463 /* Reset stack pointer (and possibly frame pointer). The stack
4464 pointer is initially set to fp + 64 to avoid a race condition. */
4465 if (frame_pointer_needed)
4467 rtx delta = GEN_INT (-64);
4469 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
4470 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
4472 /* If we were deferring a callee register restore, do it now. */
4473 else if (merge_sp_adjust_with_load)
4475 rtx delta = GEN_INT (-actual_fsize);
4476 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
4478 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
4480 else if (actual_fsize != 0)
4481 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
4484 /* If we haven't restored %r2 yet (no frame pointer, and a stack
4485 frame greater than 8k), do so now. */
4487 load_reg (2, ret_off, STACK_POINTER_REGNUM);
4489 if (DO_FRAME_NOTES && current_function_calls_eh_return)
4491 rtx sa = EH_RETURN_STACKADJ_RTX;
4493 emit_insn (gen_blockage ());
4494 emit_insn (TARGET_64BIT
4495 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
4496 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
4501 hppa_pic_save_rtx (void)
4503 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
4507 hppa_profile_hook (int label_no)
4509 /* We use SImode for the address of the function in both 32 and
4510 64-bit code to avoid having to provide DImode versions of the
4511 lcla2 and load_offset_label_address insn patterns. */
4512 rtx reg = gen_reg_rtx (SImode);
4513 rtx label_rtx = gen_label_rtx ();
4514 rtx begin_label_rtx, call_insn;
4515 char begin_label_name[16];
4517 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
4519 begin_label_rtx = gen_rtx_SYMBOL_REF (SImode, ggc_strdup (begin_label_name));
4522 emit_move_insn (arg_pointer_rtx,
4523 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
4526 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
4528 /* The address of the function is loaded into %r25 with a instruction-
4529 relative sequence that avoids the use of relocations. The sequence
4530 is split so that the load_offset_label_address instruction can
4531 occupy the delay slot of the call to _mcount. */
4533 emit_insn (gen_lcla2 (reg, label_rtx));
4535 emit_insn (gen_lcla1 (reg, label_rtx));
4537 emit_insn (gen_load_offset_label_address (gen_rtx_REG (SImode, 25),
4538 reg, begin_label_rtx, label_rtx));
4540 #ifndef NO_PROFILE_COUNTERS
4542 rtx count_label_rtx, addr, r24;
4543 char count_label_name[16];
4545 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
4546 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
4548 addr = force_reg (Pmode, count_label_rtx);
4549 r24 = gen_rtx_REG (Pmode, 24);
4550 emit_move_insn (r24, addr);
4553 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4554 gen_rtx_SYMBOL_REF (Pmode,
4556 GEN_INT (TARGET_64BIT ? 24 : 12)));
4558 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
4563 emit_call_insn (gen_call (gen_rtx_MEM (Pmode,
4564 gen_rtx_SYMBOL_REF (Pmode,
4566 GEN_INT (TARGET_64BIT ? 16 : 8)));
4570 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 25));
4571 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), gen_rtx_REG (SImode, 26));
4573 /* Indicate the _mcount call cannot throw, nor will it execute a
4575 REG_NOTES (call_insn)
4576 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
4579 /* Fetch the return address for the frame COUNT steps up from
4580 the current frame, after the prologue. FRAMEADDR is the
4581 frame pointer of the COUNT frame.
4583 We want to ignore any export stub remnants here. To handle this,
4584 we examine the code at the return address, and if it is an export
4585 stub, we return a memory rtx for the stub return address stored
4588 The value returned is used in two different ways:
4590 1. To find a function's caller.
4592 2. To change the return address for a function.
4594 This function handles most instances of case 1; however, it will
4595 fail if there are two levels of stubs to execute on the return
4596 path. The only way I believe that can happen is if the return value
4597 needs a parameter relocation, which never happens for C code.
4599 This function handles most instances of case 2; however, it will
4600 fail if we did not originally have stub code on the return path
4601 but will need stub code on the new return path. This can happen if
4602 the caller & callee are both in the main program, but the new
4603 return location is in a shared library. */
4606 return_addr_rtx (int count, rtx frameaddr)
4616 rp = get_hard_reg_initial_val (Pmode, 2);
4618 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4621 saved_rp = gen_reg_rtx (Pmode);
4622 emit_move_insn (saved_rp, rp);
4624 /* Get pointer to the instruction stream. We have to mask out the
4625 privilege level from the two low order bits of the return address
4626 pointer here so that ins will point to the start of the first
4627 instruction that would have been executed if we returned. */
4628 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4629 label = gen_label_rtx ();
4631 /* Check the instruction stream at the normal return address for the
4634 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4635 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4636 0x00011820 | stub+16: mtsp r1,sr0
4637 0xe0400002 | stub+20: be,n 0(sr0,rp)
4639 If it is an export stub, than our return address is really in
4642 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4643 NULL_RTX, SImode, 1);
4644 emit_jump_insn (gen_bne (label));
4646 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4647 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4648 emit_jump_insn (gen_bne (label));
4650 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4651 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4652 emit_jump_insn (gen_bne (label));
4654 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4655 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4657 /* If there is no export stub then just use the value saved from
4658 the return pointer register. */
4660 emit_jump_insn (gen_bne (label));
4662 /* Here we know that our return address points to an export
4663 stub. We don't want to return the address of the export stub,
4664 but rather the return address of the export stub. That return
4665 address is stored at -24[frameaddr]. */
4667 emit_move_insn (saved_rp,
4669 memory_address (Pmode,
4670 plus_constant (frameaddr,
4677 /* This is only valid once reload has completed because it depends on
4678 knowing exactly how much (if any) frame there is and...
4680 It's only valid if there is no frame marker to de-allocate and...
4682 It's only valid if %r2 hasn't been saved into the caller's frame
4683 (we're not profiling and %r2 isn't live anywhere). */
4685 hppa_can_use_return_insn_p (void)
4687 return (reload_completed
4688 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4689 && ! regs_ever_live[2]
4690 && ! frame_pointer_needed);
4694 emit_bcond_fp (enum rtx_code code, rtx operand0)
4696 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4697 gen_rtx_IF_THEN_ELSE (VOIDmode,
4698 gen_rtx_fmt_ee (code,
4700 gen_rtx_REG (CCFPmode, 0),
4702 gen_rtx_LABEL_REF (VOIDmode, operand0),
4708 gen_cmp_fp (enum rtx_code code, rtx operand0, rtx operand1)
4710 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4711 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4714 /* Adjust the cost of a scheduling dependency. Return the new cost of
4715 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4718 pa_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
4720 enum attr_type attr_type;
4722 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4723 true dependencies as they are described with bypasses now. */
4724 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4727 if (! recog_memoized (insn))
4730 attr_type = get_attr_type (insn);
4732 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4734 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4737 if (attr_type == TYPE_FPLOAD)
4739 rtx pat = PATTERN (insn);
4740 rtx dep_pat = PATTERN (dep_insn);
4741 if (GET_CODE (pat) == PARALLEL)
4743 /* This happens for the fldXs,mb patterns. */
4744 pat = XVECEXP (pat, 0, 0);
4746 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4747 /* If this happens, we have to extend this to schedule
4748 optimally. Return 0 for now. */
4751 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4753 if (! recog_memoized (dep_insn))
4755 switch (get_attr_type (dep_insn))
4762 case TYPE_FPSQRTSGL:
4763 case TYPE_FPSQRTDBL:
4764 /* A fpload can't be issued until one cycle before a
4765 preceding arithmetic operation has finished if
4766 the target of the fpload is any of the sources
4767 (or destination) of the arithmetic operation. */
4768 return insn_default_latency (dep_insn) - 1;
4775 else if (attr_type == TYPE_FPALU)
4777 rtx pat = PATTERN (insn);
4778 rtx dep_pat = PATTERN (dep_insn);
4779 if (GET_CODE (pat) == PARALLEL)
4781 /* This happens for the fldXs,mb patterns. */
4782 pat = XVECEXP (pat, 0, 0);
4784 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4785 /* If this happens, we have to extend this to schedule
4786 optimally. Return 0 for now. */
4789 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4791 if (! recog_memoized (dep_insn))
4793 switch (get_attr_type (dep_insn))
4797 case TYPE_FPSQRTSGL:
4798 case TYPE_FPSQRTDBL:
4799 /* An ALU flop can't be issued until two cycles before a
4800 preceding divide or sqrt operation has finished if
4801 the target of the ALU flop is any of the sources
4802 (or destination) of the divide or sqrt operation. */
4803 return insn_default_latency (dep_insn) - 2;
4811 /* For other anti dependencies, the cost is 0. */
4814 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4816 /* Output dependency; DEP_INSN writes a register that INSN writes some
4818 if (attr_type == TYPE_FPLOAD)
4820 rtx pat = PATTERN (insn);
4821 rtx dep_pat = PATTERN (dep_insn);
4822 if (GET_CODE (pat) == PARALLEL)
4824 /* This happens for the fldXs,mb patterns. */
4825 pat = XVECEXP (pat, 0, 0);
4827 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4828 /* If this happens, we have to extend this to schedule
4829 optimally. Return 0 for now. */
4832 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4834 if (! recog_memoized (dep_insn))
4836 switch (get_attr_type (dep_insn))
4843 case TYPE_FPSQRTSGL:
4844 case TYPE_FPSQRTDBL:
4845 /* A fpload can't be issued until one cycle before a
4846 preceding arithmetic operation has finished if
4847 the target of the fpload is the destination of the
4848 arithmetic operation.
4850 Exception: For PA7100LC, PA7200 and PA7300, the cost
4851 is 3 cycles, unless they bundle together. We also
4852 pay the penalty if the second insn is a fpload. */
4853 return insn_default_latency (dep_insn) - 1;
4860 else if (attr_type == TYPE_FPALU)
4862 rtx pat = PATTERN (insn);
4863 rtx dep_pat = PATTERN (dep_insn);
4864 if (GET_CODE (pat) == PARALLEL)
4866 /* This happens for the fldXs,mb patterns. */
4867 pat = XVECEXP (pat, 0, 0);
4869 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4870 /* If this happens, we have to extend this to schedule
4871 optimally. Return 0 for now. */
4874 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4876 if (! recog_memoized (dep_insn))
4878 switch (get_attr_type (dep_insn))
4882 case TYPE_FPSQRTSGL:
4883 case TYPE_FPSQRTDBL:
4884 /* An ALU flop can't be issued until two cycles before a
4885 preceding divide or sqrt operation has finished if
4886 the target of the ALU flop is also the target of
4887 the divide or sqrt operation. */
4888 return insn_default_latency (dep_insn) - 2;
4896 /* For other output dependencies, the cost is 0. */
4903 /* Adjust scheduling priorities. We use this to try and keep addil
4904 and the next use of %r1 close together. */
4906 pa_adjust_priority (rtx insn, int priority)
4908 rtx set = single_set (insn);
4912 src = SET_SRC (set);
4913 dest = SET_DEST (set);
4914 if (GET_CODE (src) == LO_SUM
4915 && symbolic_operand (XEXP (src, 1), VOIDmode)
4916 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4919 else if (GET_CODE (src) == MEM
4920 && GET_CODE (XEXP (src, 0)) == LO_SUM
4921 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4922 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4925 else if (GET_CODE (dest) == MEM
4926 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4927 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4928 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4934 /* The 700 can only issue a single insn at a time.
4935 The 7XXX processors can issue two insns at a time.
4936 The 8000 can issue 4 insns at a time. */
4938 pa_issue_rate (void)
4942 case PROCESSOR_700: return 1;
4943 case PROCESSOR_7100: return 2;
4944 case PROCESSOR_7100LC: return 2;
4945 case PROCESSOR_7200: return 2;
4946 case PROCESSOR_7300: return 2;
4947 case PROCESSOR_8000: return 4;
4956 /* Return any length adjustment needed by INSN which already has its length
4957 computed as LENGTH. Return zero if no adjustment is necessary.
4959 For the PA: function calls, millicode calls, and backwards short
4960 conditional branches with unfilled delay slots need an adjustment by +1
4961 (to account for the NOP which will be inserted into the instruction stream).
4963 Also compute the length of an inline block move here as it is too
4964 complicated to express as a length attribute in pa.md. */
4966 pa_adjust_insn_length (rtx insn, int length)
4968 rtx pat = PATTERN (insn);
4970 /* Jumps inside switch tables which have unfilled delay slots need
4972 if (GET_CODE (insn) == JUMP_INSN
4973 && GET_CODE (pat) == PARALLEL
4974 && get_attr_type (insn) == TYPE_BTABLE_BRANCH)
4976 /* Millicode insn with an unfilled delay slot. */
4977 else if (GET_CODE (insn) == INSN
4978 && GET_CODE (pat) != SEQUENCE
4979 && GET_CODE (pat) != USE
4980 && GET_CODE (pat) != CLOBBER
4981 && get_attr_type (insn) == TYPE_MILLI)
4983 /* Block move pattern. */
4984 else if (GET_CODE (insn) == INSN
4985 && GET_CODE (pat) == PARALLEL
4986 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4987 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4988 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4989 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4990 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4991 return compute_movmem_length (insn) - 4;
4992 /* Block clear pattern. */
4993 else if (GET_CODE (insn) == INSN
4994 && GET_CODE (pat) == PARALLEL
4995 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4996 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4997 && XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
4998 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
4999 return compute_clrmem_length (insn) - 4;
5000 /* Conditional branch with an unfilled delay slot. */
5001 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
5003 /* Adjust a short backwards conditional with an unfilled delay slot. */
5004 if (GET_CODE (pat) == SET
5006 && ! forward_branch_p (insn))
5008 else if (GET_CODE (pat) == PARALLEL
5009 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
5012 /* Adjust dbra insn with short backwards conditional branch with
5013 unfilled delay slot -- only for case where counter is in a
5014 general register register. */
5015 else if (GET_CODE (pat) == PARALLEL
5016 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
5017 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
5018 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
5020 && ! forward_branch_p (insn))
5028 /* Print operand X (an rtx) in assembler syntax to file FILE.
5029 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
5030 For `%' followed by punctuation, CODE is the punctuation and X is null. */
5033 print_operand (FILE *file, rtx x, int code)
5038 /* Output a 'nop' if there's nothing for the delay slot. */
5039 if (dbr_sequence_length () == 0)
5040 fputs ("\n\tnop", file);
5043 /* Output a nullification completer if there's nothing for the */
5044 /* delay slot or nullification is requested. */
5045 if (dbr_sequence_length () == 0 ||
5047 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
5051 /* Print out the second register name of a register pair.
5052 I.e., R (6) => 7. */
5053 fputs (reg_names[REGNO (x) + 1], file);
5056 /* A register or zero. */
5058 || (x == CONST0_RTX (DFmode))
5059 || (x == CONST0_RTX (SFmode)))
5061 fputs ("%r0", file);
5067 /* A register or zero (floating point). */
5069 || (x == CONST0_RTX (DFmode))
5070 || (x == CONST0_RTX (SFmode)))
5072 fputs ("%fr0", file);
5081 xoperands[0] = XEXP (XEXP (x, 0), 0);
5082 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
5083 output_global_address (file, xoperands[1], 0);
5084 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
5088 case 'C': /* Plain (C)ondition */
5090 switch (GET_CODE (x))
5093 fputs ("=", file); break;
5095 fputs ("<>", file); break;
5097 fputs (">", file); break;
5099 fputs (">=", file); break;
5101 fputs (">>=", file); break;
5103 fputs (">>", file); break;
5105 fputs ("<", file); break;
5107 fputs ("<=", file); break;
5109 fputs ("<<=", file); break;
5111 fputs ("<<", file); break;
5116 case 'N': /* Condition, (N)egated */
5117 switch (GET_CODE (x))
5120 fputs ("<>", file); break;
5122 fputs ("=", file); break;
5124 fputs ("<=", file); break;
5126 fputs ("<", file); break;
5128 fputs ("<<", file); break;
5130 fputs ("<<=", file); break;
5132 fputs (">=", file); break;
5134 fputs (">", file); break;
5136 fputs (">>", file); break;
5138 fputs (">>=", file); break;
5143 /* For floating point comparisons. Note that the output
5144 predicates are the complement of the desired mode. The
5145 conditions for GT, GE, LT, LE and LTGT cause an invalid
5146 operation exception if the result is unordered and this
5147 exception is enabled in the floating-point status register. */
5149 switch (GET_CODE (x))
5152 fputs ("!=", file); break;
5154 fputs ("=", file); break;
5156 fputs ("!>", file); break;
5158 fputs ("!>=", file); break;
5160 fputs ("!<", file); break;
5162 fputs ("!<=", file); break;
5164 fputs ("!<>", file); break;
5166 fputs ("!?<=", file); break;
5168 fputs ("!?<", file); break;
5170 fputs ("!?>=", file); break;
5172 fputs ("!?>", file); break;
5174 fputs ("!?=", file); break;
5176 fputs ("!?", file); break;
5178 fputs ("?", file); break;
5183 case 'S': /* Condition, operands are (S)wapped. */
5184 switch (GET_CODE (x))
5187 fputs ("=", file); break;
5189 fputs ("<>", file); break;
5191 fputs ("<", file); break;
5193 fputs ("<=", file); break;
5195 fputs ("<<=", file); break;
5197 fputs ("<<", file); break;
5199 fputs (">", file); break;
5201 fputs (">=", file); break;
5203 fputs (">>=", file); break;
5205 fputs (">>", file); break;
5210 case 'B': /* Condition, (B)oth swapped and negate. */
5211 switch (GET_CODE (x))
5214 fputs ("<>", file); break;
5216 fputs ("=", file); break;
5218 fputs (">=", file); break;
5220 fputs (">", file); break;
5222 fputs (">>", file); break;
5224 fputs (">>=", file); break;
5226 fputs ("<=", file); break;
5228 fputs ("<", file); break;
5230 fputs ("<<", file); break;
5232 fputs ("<<=", file); break;
5238 if (GET_CODE (x) == CONST_INT)
5240 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
5245 if (GET_CODE (x) == CONST_INT)
5247 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
5252 if (GET_CODE (x) == CONST_INT)
5254 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
5259 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
5261 fprintf (file, "%d", exact_log2 (INTVAL (x)));
5266 if (GET_CODE (x) == CONST_INT)
5268 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
5273 if (GET_CODE (x) == CONST_INT)
5275 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
5280 if (GET_CODE (x) == CONST_INT)
5285 switch (GET_CODE (XEXP (x, 0)))
5289 if (ASSEMBLER_DIALECT == 0)
5290 fputs ("s,mb", file);
5292 fputs (",mb", file);
5296 if (ASSEMBLER_DIALECT == 0)
5297 fputs ("s,ma", file);
5299 fputs (",ma", file);
5302 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5303 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5305 if (ASSEMBLER_DIALECT == 0)
5308 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
5309 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5311 if (ASSEMBLER_DIALECT == 0)
5312 fputs ("x,s", file);
5316 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
5320 if (code == 'F' && ASSEMBLER_DIALECT == 0)
5326 output_global_address (file, x, 0);
5329 output_global_address (file, x, 1);
5331 case 0: /* Don't do anything special */
5336 compute_zdepwi_operands (INTVAL (x), op);
5337 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5343 compute_zdepdi_operands (INTVAL (x), op);
5344 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
5348 /* We can get here from a .vtable_inherit due to our
5349 CONSTANT_ADDRESS_P rejecting perfectly good constant
5355 if (GET_CODE (x) == REG)
5357 fputs (reg_names [REGNO (x)], file);
5358 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
5364 && GET_MODE_SIZE (GET_MODE (x)) <= 4
5365 && (REGNO (x) & 1) == 0)
5368 else if (GET_CODE (x) == MEM)
5370 int size = GET_MODE_SIZE (GET_MODE (x));
5371 rtx base = NULL_RTX;
5372 switch (GET_CODE (XEXP (x, 0)))
5376 base = XEXP (XEXP (x, 0), 0);
5377 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
5381 base = XEXP (XEXP (x, 0), 0);
5382 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
5385 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
5386 fprintf (file, "%s(%s)",
5387 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
5388 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
5389 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
5390 fprintf (file, "%s(%s)",
5391 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
5392 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
5393 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
5394 && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
5396 /* Because the REG_POINTER flag can get lost during reload,
5397 GO_IF_LEGITIMATE_ADDRESS canonicalizes the order of the
5398 index and base registers in the combined move patterns. */
5399 rtx base = XEXP (XEXP (x, 0), 1);
5400 rtx index = XEXP (XEXP (x, 0), 0);
5402 fprintf (file, "%s(%s)",
5403 reg_names [REGNO (index)], reg_names [REGNO (base)]);
5406 output_address (XEXP (x, 0));
5409 output_address (XEXP (x, 0));
5414 output_addr_const (file, x);
5417 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
5420 output_global_address (FILE *file, rtx x, int round_constant)
5423 /* Imagine (high (const (plus ...))). */
5424 if (GET_CODE (x) == HIGH)
5427 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
5428 assemble_name (file, XSTR (x, 0));
5429 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
5431 assemble_name (file, XSTR (x, 0));
5432 fputs ("-$global$", file);
5434 else if (GET_CODE (x) == CONST)
5436 const char *sep = "";
5437 int offset = 0; /* assembler wants -$global$ at end */
5438 rtx base = NULL_RTX;
5440 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
5442 base = XEXP (XEXP (x, 0), 0);
5443 output_addr_const (file, base);
5445 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
5446 offset = INTVAL (XEXP (XEXP (x, 0), 0));
5449 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
5451 base = XEXP (XEXP (x, 0), 1);
5452 output_addr_const (file, base);
5454 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
5455 offset = INTVAL (XEXP (XEXP (x, 0), 1));
5458 /* How bogus. The compiler is apparently responsible for
5459 rounding the constant if it uses an LR field selector.
5461 The linker and/or assembler seem a better place since
5462 they have to do this kind of thing already.
5464 If we fail to do this, HP's optimizing linker may eliminate
5465 an addil, but not update the ldw/stw/ldo instruction that
5466 uses the result of the addil. */
5468 offset = ((offset + 0x1000) & ~0x1fff);
5470 if (GET_CODE (XEXP (x, 0)) == PLUS)
5480 else if (GET_CODE (XEXP (x, 0)) == MINUS
5481 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
5485 if (!read_only_operand (base, VOIDmode) && !flag_pic)
5486 fputs ("-$global$", file);
5488 fprintf (file, "%s%d", sep, offset);
5491 output_addr_const (file, x);
5494 /* Output boilerplate text to appear at the beginning of the file.
5495 There are several possible versions. */
5496 #define aputs(x) fputs(x, asm_out_file)
5498 pa_file_start_level (void)
5501 aputs ("\t.LEVEL 2.0w\n");
5502 else if (TARGET_PA_20)
5503 aputs ("\t.LEVEL 2.0\n");
5504 else if (TARGET_PA_11)
5505 aputs ("\t.LEVEL 1.1\n");
5507 aputs ("\t.LEVEL 1.0\n");
5511 pa_file_start_space (int sortspace)
5513 aputs ("\t.SPACE $PRIVATE$");
5516 aputs ("\n\t.SUBSPA $DATA$,QUAD=1,ALIGN=8,ACCESS=31"
5517 "\n\t.SUBSPA $BSS$,QUAD=1,ALIGN=8,ACCESS=31,ZERO,SORT=82"
5518 "\n\t.SPACE $TEXT$");
5521 aputs ("\n\t.SUBSPA $LIT$,QUAD=0,ALIGN=8,ACCESS=44"
5522 "\n\t.SUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,CODE_ONLY\n");
5526 pa_file_start_file (int want_version)
5528 if (write_symbols != NO_DEBUG)
5530 output_file_directive (asm_out_file, main_input_filename);
5532 aputs ("\t.version\t\"01.01\"\n");
5537 pa_file_start_mcount (const char *aswhat)
5540 fprintf (asm_out_file, "\t.IMPORT _mcount,%s\n", aswhat);
5544 pa_elf_file_start (void)
5546 pa_file_start_level ();
5547 pa_file_start_mcount ("ENTRY");
5548 pa_file_start_file (0);
5552 pa_som_file_start (void)
5554 pa_file_start_level ();
5555 pa_file_start_space (0);
5556 aputs ("\t.IMPORT $global$,DATA\n"
5557 "\t.IMPORT $$dyncall,MILLICODE\n");
5558 pa_file_start_mcount ("CODE");
5559 pa_file_start_file (0);
5563 pa_linux_file_start (void)
5565 pa_file_start_file (1);
5566 pa_file_start_level ();
5567 pa_file_start_mcount ("CODE");
5571 pa_hpux64_gas_file_start (void)
5573 pa_file_start_level ();
5574 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
5576 ASM_OUTPUT_TYPE_DIRECTIVE (asm_out_file, "_mcount", "function");
5578 pa_file_start_file (1);
5582 pa_hpux64_hpas_file_start (void)
5584 pa_file_start_level ();
5585 pa_file_start_space (1);
5586 pa_file_start_mcount ("CODE");
5587 pa_file_start_file (0);
5591 static struct deferred_plabel *
5592 get_plabel (const char *fname)
5596 /* See if we have already put this function on the list of deferred
5597 plabels. This list is generally small, so a liner search is not
5598 too ugly. If it proves too slow replace it with something faster. */
5599 for (i = 0; i < n_deferred_plabels; i++)
5600 if (strcmp (fname, deferred_plabels[i].name) == 0)
5603 /* If the deferred plabel list is empty, or this entry was not found
5604 on the list, create a new entry on the list. */
5605 if (deferred_plabels == NULL || i == n_deferred_plabels)
5607 const char *real_name;
5609 if (deferred_plabels == 0)
5610 deferred_plabels = (struct deferred_plabel *)
5611 ggc_alloc (sizeof (struct deferred_plabel));
5613 deferred_plabels = (struct deferred_plabel *)
5614 ggc_realloc (deferred_plabels,
5615 ((n_deferred_plabels + 1)
5616 * sizeof (struct deferred_plabel)));
5618 i = n_deferred_plabels++;
5619 deferred_plabels[i].internal_label = gen_label_rtx ();
5620 deferred_plabels[i].name = ggc_strdup (fname);
5622 /* Gross. We have just implicitly taken the address of this function,
5624 real_name = (*targetm.strip_name_encoding) (fname);
5625 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
5628 return &deferred_plabels[i];
5632 output_deferred_plabels (void)
5635 /* If we have deferred plabels, then we need to switch into the data
5636 section and align it to a 4 byte boundary before we output the
5637 deferred plabels. */
5638 if (n_deferred_plabels)
5641 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
5644 /* Now output the deferred plabels. */
5645 for (i = 0; i < n_deferred_plabels; i++)
5647 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5648 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
5649 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
5650 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
5654 #ifdef HPUX_LONG_DOUBLE_LIBRARY
5655 /* Initialize optabs to point to HPUX long double emulation routines. */
5657 pa_hpux_init_libfuncs (void)
5659 set_optab_libfunc (add_optab, TFmode, "_U_Qfadd");
5660 set_optab_libfunc (sub_optab, TFmode, "_U_Qfsub");
5661 set_optab_libfunc (smul_optab, TFmode, "_U_Qfmpy");
5662 set_optab_libfunc (sdiv_optab, TFmode, "_U_Qfdiv");
5663 set_optab_libfunc (smin_optab, TFmode, "_U_Qmin");
5664 set_optab_libfunc (smax_optab, TFmode, "_U_Qfmax");
5665 set_optab_libfunc (sqrt_optab, TFmode, "_U_Qfsqrt");
5666 set_optab_libfunc (abs_optab, TFmode, "_U_Qfabs");
5667 set_optab_libfunc (neg_optab, TFmode, "_U_Qfneg");
5669 set_optab_libfunc (eq_optab, TFmode, "_U_Qfeq");
5670 set_optab_libfunc (ne_optab, TFmode, "_U_Qfne");
5671 set_optab_libfunc (gt_optab, TFmode, "_U_Qfgt");
5672 set_optab_libfunc (ge_optab, TFmode, "_U_Qfge");
5673 set_optab_libfunc (lt_optab, TFmode, "_U_Qflt");
5674 set_optab_libfunc (le_optab, TFmode, "_U_Qfle");
5675 set_optab_libfunc (unord_optab, TFmode, "_U_Qfunord");
5677 set_conv_libfunc (sext_optab, TFmode, SFmode, "_U_Qfcnvff_sgl_to_quad");
5678 set_conv_libfunc (sext_optab, TFmode, DFmode, "_U_Qfcnvff_dbl_to_quad");
5679 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_U_Qfcnvff_quad_to_sgl");
5680 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_U_Qfcnvff_quad_to_dbl");
5682 set_conv_libfunc (sfix_optab, SImode, TFmode, TARGET_64BIT
5683 ? "__U_Qfcnvfxt_quad_to_sgl"
5684 : "_U_Qfcnvfxt_quad_to_sgl");
5685 set_conv_libfunc (sfix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_dbl");
5686 set_conv_libfunc (ufix_optab, SImode, TFmode, "_U_Qfcnvfxt_quad_to_usgl");
5687 set_conv_libfunc (ufix_optab, DImode, TFmode, "_U_Qfcnvfxt_quad_to_udbl");
5689 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_U_Qfcnvxf_sgl_to_quad");
5690 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_U_Qfcnvxf_dbl_to_quad");
5694 /* HP's millicode routines mean something special to the assembler.
5695 Keep track of which ones we have used. */
5697 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
5698 static void import_milli (enum millicodes);
5699 static char imported[(int) end1000];
5700 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
5701 static const char import_string[] = ".IMPORT $$....,MILLICODE";
5702 #define MILLI_START 10
5705 import_milli (enum millicodes code)
5707 char str[sizeof (import_string)];
5709 if (!imported[(int) code])
5711 imported[(int) code] = 1;
5712 strcpy (str, import_string);
5713 strncpy (str + MILLI_START, milli_names[(int) code], 4);
5714 output_asm_insn (str, 0);
5718 /* The register constraints have put the operands and return value in
5719 the proper registers. */
5722 output_mul_insn (int unsignedp ATTRIBUTE_UNUSED, rtx insn)
5724 import_milli (mulI);
5725 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5728 /* Emit the rtl for doing a division by a constant. */
5730 /* Do magic division millicodes exist for this value? */
5731 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5734 /* We'll use an array to keep track of the magic millicodes and
5735 whether or not we've used them already. [n][0] is signed, [n][1] is
5738 static int div_milli[16][2];
5741 div_operand (rtx op, enum machine_mode mode)
5743 return (mode == SImode
5744 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5745 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5746 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5750 emit_hpdiv_const (rtx *operands, int unsignedp)
5752 if (GET_CODE (operands[2]) == CONST_INT
5753 && INTVAL (operands[2]) > 0
5754 && INTVAL (operands[2]) < 16
5755 && magic_milli[INTVAL (operands[2])])
5757 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5759 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5763 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5764 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5766 gen_rtx_REG (SImode, 26),
5768 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5769 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5770 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5771 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5772 gen_rtx_CLOBBER (VOIDmode, ret))));
5773 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5780 output_div_insn (rtx *operands, int unsignedp, rtx insn)
5784 /* If the divisor is a constant, try to use one of the special
5786 if (GET_CODE (operands[0]) == CONST_INT)
5788 static char buf[100];
5789 divisor = INTVAL (operands[0]);
5790 if (!div_milli[divisor][unsignedp])
5792 div_milli[divisor][unsignedp] = 1;
5794 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5796 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5800 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5801 INTVAL (operands[0]));
5802 return output_millicode_call (insn,
5803 gen_rtx_SYMBOL_REF (SImode, buf));
5807 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5808 INTVAL (operands[0]));
5809 return output_millicode_call (insn,
5810 gen_rtx_SYMBOL_REF (SImode, buf));
5813 /* Divisor isn't a special constant. */
5818 import_milli (divU);
5819 return output_millicode_call (insn,
5820 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5824 import_milli (divI);
5825 return output_millicode_call (insn,
5826 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5831 /* Output a $$rem millicode to do mod. */
5834 output_mod_insn (int unsignedp, rtx insn)
5838 import_milli (remU);
5839 return output_millicode_call (insn,
5840 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5844 import_milli (remI);
5845 return output_millicode_call (insn,
5846 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5851 output_arg_descriptor (rtx call_insn)
5853 const char *arg_regs[4];
5854 enum machine_mode arg_mode;
5856 int i, output_flag = 0;
5859 /* We neither need nor want argument location descriptors for the
5860 64bit runtime environment or the ELF32 environment. */
5861 if (TARGET_64BIT || TARGET_ELF32)
5864 for (i = 0; i < 4; i++)
5867 /* Specify explicitly that no argument relocations should take place
5868 if using the portable runtime calling conventions. */
5869 if (TARGET_PORTABLE_RUNTIME)
5871 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5876 if (GET_CODE (call_insn) != CALL_INSN)
5878 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5880 rtx use = XEXP (link, 0);
5882 if (! (GET_CODE (use) == USE
5883 && GET_CODE (XEXP (use, 0)) == REG
5884 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5887 arg_mode = GET_MODE (XEXP (use, 0));
5888 regno = REGNO (XEXP (use, 0));
5889 if (regno >= 23 && regno <= 26)
5891 arg_regs[26 - regno] = "GR";
5892 if (arg_mode == DImode)
5893 arg_regs[25 - regno] = "GR";
5895 else if (regno >= 32 && regno <= 39)
5897 if (arg_mode == SFmode)
5898 arg_regs[(regno - 32) / 2] = "FR";
5901 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5902 arg_regs[(regno - 34) / 2] = "FR";
5903 arg_regs[(regno - 34) / 2 + 1] = "FU";
5905 arg_regs[(regno - 34) / 2] = "FU";
5906 arg_regs[(regno - 34) / 2 + 1] = "FR";
5911 fputs ("\t.CALL ", asm_out_file);
5912 for (i = 0; i < 4; i++)
5917 fputc (',', asm_out_file);
5918 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5921 fputc ('\n', asm_out_file);
5924 /* Return the class of any secondary reload register that is needed to
5925 move IN into a register in class CLASS using mode MODE.
5927 Profiling has showed this routine and its descendants account for
5928 a significant amount of compile time (~7%). So it has been
5929 optimized to reduce redundant computations and eliminate useless
5932 It might be worthwhile to try and make this a leaf function too. */
5935 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
5937 int regno, is_symbolic;
5939 /* Trying to load a constant into a FP register during PIC code
5940 generation will require %r1 as a scratch register. */
5942 && GET_MODE_CLASS (mode) == MODE_INT
5943 && FP_REG_CLASS_P (class)
5944 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5947 /* Profiling showed the PA port spends about 1.3% of its compilation
5948 time in true_regnum from calls inside secondary_reload_class. */
5950 if (GET_CODE (in) == REG)
5953 if (regno >= FIRST_PSEUDO_REGISTER)
5954 regno = true_regnum (in);
5956 else if (GET_CODE (in) == SUBREG)
5957 regno = true_regnum (in);
5961 /* If we have something like (mem (mem (...)), we can safely assume the
5962 inner MEM will end up in a general register after reloading, so there's
5963 no need for a secondary reload. */
5964 if (GET_CODE (in) == MEM
5965 && GET_CODE (XEXP (in, 0)) == MEM)
5968 /* Handle out of range displacement for integer mode loads/stores of
5970 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5971 && GET_MODE_CLASS (mode) == MODE_INT
5972 && FP_REG_CLASS_P (class))
5973 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5974 return GENERAL_REGS;
5976 /* A SAR<->FP register copy requires a secondary register (GPR) as
5977 well as secondary memory. */
5978 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5979 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5980 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5981 return GENERAL_REGS;
5983 if (GET_CODE (in) == HIGH)
5986 /* Profiling has showed GCC spends about 2.6% of its compilation
5987 time in symbolic_operand from calls inside secondary_reload_class.
5989 We use an inline copy and only compute its return value once to avoid
5991 switch (GET_CODE (in))
6001 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
6002 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
6003 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
6013 && read_only_operand (in, VOIDmode))
6016 if (class != R1_REGS && is_symbolic)
6022 /* In the 32-bit runtime, arguments larger than eight bytes are passed
6023 by invisible reference. As a GCC extension, we also pass anything
6024 with a zero or variable size by reference.
6026 The 64-bit runtime does not describe passing any types by invisible
6027 reference. The internals of GCC can't currently handle passing
6028 empty structures, and zero or variable length arrays when they are
6029 not passed entirely on the stack or by reference. Thus, as a GCC
6030 extension, we pass these types by reference. The HP compiler doesn't
6031 support these types, so hopefully there shouldn't be any compatibility
6032 issues. This may have to be revisited when HP releases a C99 compiler
6033 or updates the ABI. */
6036 pa_pass_by_reference (CUMULATIVE_ARGS *ca ATTRIBUTE_UNUSED,
6037 enum machine_mode mode, tree type,
6038 bool named ATTRIBUTE_UNUSED)
6043 size = int_size_in_bytes (type);
6045 size = GET_MODE_SIZE (mode);
6050 return size <= 0 || size > 8;
6054 function_arg_padding (enum machine_mode mode, tree type)
6057 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
6059 /* Return none if justification is not required. */
6061 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
6062 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
6065 /* The directions set here are ignored when a BLKmode argument larger
6066 than a word is placed in a register. Different code is used for
6067 the stack and registers. This makes it difficult to have a
6068 consistent data representation for both the stack and registers.
6069 For both runtimes, the justification and padding for arguments on
6070 the stack and in registers should be identical. */
6072 /* The 64-bit runtime specifies left justification for aggregates. */
6075 /* The 32-bit runtime architecture specifies right justification.
6076 When the argument is passed on the stack, the argument is padded
6077 with garbage on the left. The HP compiler pads with zeros. */
6081 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
6088 /* Do what is necessary for `va_start'. We look at the current function
6089 to determine if stdargs or varargs is used and fill in an initial
6090 va_list. A pointer to this constructor is returned. */
6093 hppa_builtin_saveregs (void)
6096 tree fntype = TREE_TYPE (current_function_decl);
6097 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
6098 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
6099 != void_type_node)))
6100 ? UNITS_PER_WORD : 0);
6103 offset = plus_constant (current_function_arg_offset_rtx, argadj);
6105 offset = current_function_arg_offset_rtx;
6111 /* Adjust for varargs/stdarg differences. */
6113 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
6115 offset = current_function_arg_offset_rtx;
6117 /* We need to save %r26 .. %r19 inclusive starting at offset -64
6118 from the incoming arg pointer and growing to larger addresses. */
6119 for (i = 26, off = -64; i >= 19; i--, off += 8)
6120 emit_move_insn (gen_rtx_MEM (word_mode,
6121 plus_constant (arg_pointer_rtx, off)),
6122 gen_rtx_REG (word_mode, i));
6124 /* The incoming args pointer points just beyond the flushback area;
6125 normally this is not a serious concern. However, when we are doing
6126 varargs/stdargs we want to make the arg pointer point to the start
6127 of the incoming argument area. */
6128 emit_move_insn (virtual_incoming_args_rtx,
6129 plus_constant (arg_pointer_rtx, -64));
6131 /* Now return a pointer to the first anonymous argument. */
6132 return copy_to_reg (expand_binop (Pmode, add_optab,
6133 virtual_incoming_args_rtx,
6134 offset, 0, 0, OPTAB_LIB_WIDEN));
6137 /* Store general registers on the stack. */
6138 dest = gen_rtx_MEM (BLKmode,
6139 plus_constant (current_function_internal_arg_pointer,
6141 set_mem_alias_set (dest, get_varargs_alias_set ());
6142 set_mem_align (dest, BITS_PER_WORD);
6143 move_block_from_reg (23, dest, 4);
6145 /* move_block_from_reg will emit code to store the argument registers
6146 individually as scalar stores.
6148 However, other insns may later load from the same addresses for
6149 a structure load (passing a struct to a varargs routine).
6151 The alias code assumes that such aliasing can never happen, so we
6152 have to keep memory referencing insns from moving up beyond the
6153 last argument register store. So we emit a blockage insn here. */
6154 emit_insn (gen_blockage ());
6156 return copy_to_reg (expand_binop (Pmode, add_optab,
6157 current_function_internal_arg_pointer,
6158 offset, 0, 0, OPTAB_LIB_WIDEN));
6162 hppa_va_start (tree valist, rtx nextarg)
6164 nextarg = expand_builtin_saveregs ();
6165 std_expand_builtin_va_start (valist, nextarg);
6169 hppa_gimplify_va_arg_expr (tree valist, tree type, tree *pre_p, tree *post_p)
6173 /* Args grow upward. We can use the generic routines. */
6174 return std_gimplify_va_arg_expr (valist, type, pre_p, post_p);
6176 else /* !TARGET_64BIT */
6178 tree ptr = build_pointer_type (type);
6181 unsigned int size, ofs;
6184 indirect = pass_by_reference (NULL, TYPE_MODE (type), type, 0);
6188 ptr = build_pointer_type (type);
6190 size = int_size_in_bytes (type);
6191 valist_type = TREE_TYPE (valist);
6193 /* Args grow down. Not handled by generic routines. */
6195 u = fold_convert (valist_type, size_in_bytes (type));
6196 t = build (MINUS_EXPR, valist_type, valist, u);
6198 /* Copied from va-pa.h, but we probably don't need to align to
6199 word size, since we generate and preserve that invariant. */
6200 u = build_int_cst (valist_type, (size > 4 ? -8 : -4));
6201 t = build (BIT_AND_EXPR, valist_type, t, u);
6203 t = build (MODIFY_EXPR, valist_type, valist, t);
6205 ofs = (8 - size) % 4;
6208 u = fold_convert (valist_type, size_int (ofs));
6209 t = build (PLUS_EXPR, valist_type, t, u);
6212 t = fold_convert (ptr, t);
6213 t = build_fold_indirect_ref (t);
6216 t = build_fold_indirect_ref (t);
6222 /* This routine handles all the normal conditional branch sequences we
6223 might need to generate. It handles compare immediate vs compare
6224 register, nullification of delay slots, varying length branches,
6225 negated branches, and all combinations of the above. It returns the
6226 output appropriate to emit the branch corresponding to all given
6230 output_cbranch (rtx *operands, int nullify, int length, int negated, rtx insn)
6232 static char buf[100];
6236 /* A conditional branch to the following instruction (e.g. the delay slot)
6237 is asking for a disaster. This can happen when not optimizing and
6238 when jump optimization fails.
6240 While it is usually safe to emit nothing, this can fail if the
6241 preceding instruction is a nullified branch with an empty delay
6242 slot and the same branch target as this branch. We could check
6243 for this but jump optimization should eliminate nop jumps. It
6244 is always safe to emit a nop. */
6245 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6248 /* The doubleword form of the cmpib instruction doesn't have the LEU
6249 and GTU conditions while the cmpb instruction does. Since we accept
6250 zero for cmpb, we must ensure that we use cmpb for the comparison. */
6251 if (GET_MODE (operands[1]) == DImode && operands[2] == const0_rtx)
6252 operands[2] = gen_rtx_REG (DImode, 0);
6254 /* If this is a long branch with its delay slot unfilled, set `nullify'
6255 as it can nullify the delay slot and save a nop. */
6256 if (length == 8 && dbr_sequence_length () == 0)
6259 /* If this is a short forward conditional branch which did not get
6260 its delay slot filled, the delay slot can still be nullified. */
6261 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6262 nullify = forward_branch_p (insn);
6264 /* A forward branch over a single nullified insn can be done with a
6265 comclr instruction. This avoids a single cycle penalty due to
6266 mis-predicted branch if we fall through (branch not taken). */
6268 && next_real_insn (insn) != 0
6269 && get_attr_length (next_real_insn (insn)) == 4
6270 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6276 /* All short conditional branches except backwards with an unfilled
6280 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6282 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6283 if (GET_MODE (operands[1]) == DImode)
6286 strcat (buf, "%B3");
6288 strcat (buf, "%S3");
6290 strcat (buf, " %2,%r1,%%r0");
6292 strcat (buf, ",n %2,%r1,%0");
6294 strcat (buf, " %2,%r1,%0");
6297 /* All long conditionals. Note a short backward branch with an
6298 unfilled delay slot is treated just like a long backward branch
6299 with an unfilled delay slot. */
6301 /* Handle weird backwards branch with a filled delay slot
6302 with is nullified. */
6303 if (dbr_sequence_length () != 0
6304 && ! forward_branch_p (insn)
6307 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6308 if (GET_MODE (operands[1]) == DImode)
6311 strcat (buf, "%S3");
6313 strcat (buf, "%B3");
6314 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
6316 /* Handle short backwards branch with an unfilled delay slot.
6317 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
6318 taken and untaken branches. */
6319 else if (dbr_sequence_length () == 0
6320 && ! forward_branch_p (insn)
6321 && INSN_ADDRESSES_SET_P ()
6322 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6323 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6325 strcpy (buf, "{com%I2b,|cmp%I2b,}");
6326 if (GET_MODE (operands[1]) == DImode)
6329 strcat (buf, "%B3 %2,%r1,%0%#");
6331 strcat (buf, "%S3 %2,%r1,%0%#");
6335 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
6336 if (GET_MODE (operands[1]) == DImode)
6339 strcat (buf, "%S3");
6341 strcat (buf, "%B3");
6343 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
6345 strcat (buf, " %2,%r1,%%r0\n\tb %0");
6351 xoperands[0] = operands[0];
6352 xoperands[1] = operands[1];
6353 xoperands[2] = operands[2];
6354 xoperands[3] = operands[3];
6356 /* The reversed conditional branch must branch over one additional
6357 instruction if the delay slot is filled. If the delay slot
6358 is empty, the instruction after the reversed condition branch
6359 must be nullified. */
6360 nullify = dbr_sequence_length () == 0;
6361 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
6363 /* Create a reversed conditional branch which branches around
6364 the following insns. */
6365 if (GET_MODE (operands[1]) != DImode)
6371 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
6374 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
6380 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
6383 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
6392 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
6395 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
6401 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
6404 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
6408 output_asm_insn (buf, xoperands);
6409 return output_lbranch (operands[0], insn);
6417 /* This routine handles long unconditional branches that exceed the
6418 maximum range of a simple branch instruction. */
6421 output_lbranch (rtx dest, rtx insn)
6425 xoperands[0] = dest;
6427 /* First, free up the delay slot. */
6428 if (dbr_sequence_length () != 0)
6430 /* We can't handle a jump in the delay slot. */
6431 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
6434 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6435 optimize, 0, 0, NULL);
6437 /* Now delete the delay insn. */
6438 PUT_CODE (NEXT_INSN (insn), NOTE);
6439 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6440 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6443 /* Output an insn to save %r1. The runtime documentation doesn't
6444 specify whether the "Clean Up" slot in the callers frame can
6445 be clobbered by the callee. It isn't copied by HP's builtin
6446 alloca, so this suggests that it can be clobbered if necessary.
6447 The "Static Link" location is copied by HP builtin alloca, so
6448 we avoid using it. Using the cleanup slot might be a problem
6449 if we have to interoperate with languages that pass cleanup
6450 information. However, it should be possible to handle these
6451 situations with GCC's asm feature.
6453 The "Current RP" slot is reserved for the called procedure, so
6454 we try to use it when we don't have a frame of our own. It's
6455 rather unlikely that we won't have a frame when we need to emit
6458 Really the way to go long term is a register scavenger; goto
6459 the target of the jump and find a register which we can use
6460 as a scratch to hold the value in %r1. Then, we wouldn't have
6461 to free up the delay slot or clobber a slot that may be needed
6462 for other purposes. */
6465 if (actual_fsize == 0 && !regs_ever_live[2])
6466 /* Use the return pointer slot in the frame marker. */
6467 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
6469 /* Use the slot at -40 in the frame marker since HP builtin
6470 alloca doesn't copy it. */
6471 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
6475 if (actual_fsize == 0 && !regs_ever_live[2])
6476 /* Use the return pointer slot in the frame marker. */
6477 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
6479 /* Use the "Clean Up" slot in the frame marker. In GCC,
6480 the only other use of this location is for copying a
6481 floating point double argument from a floating-point
6482 register to two general registers. The copy is done
6483 as an "atomic" operation when outputting a call, so it
6484 won't interfere with our using the location here. */
6485 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
6488 if (TARGET_PORTABLE_RUNTIME)
6490 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6491 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6492 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6496 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6497 if (TARGET_SOM || !TARGET_GAS)
6499 xoperands[1] = gen_label_rtx ();
6500 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
6501 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6502 CODE_LABEL_NUMBER (xoperands[1]));
6503 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
6507 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
6508 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6510 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6513 /* Now output a very long branch to the original target. */
6514 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
6516 /* Now restore the value of %r1 in the delay slot. */
6519 if (actual_fsize == 0 && !regs_ever_live[2])
6520 return "ldd -16(%%r30),%%r1";
6522 return "ldd -40(%%r30),%%r1";
6526 if (actual_fsize == 0 && !regs_ever_live[2])
6527 return "ldw -20(%%r30),%%r1";
6529 return "ldw -12(%%r30),%%r1";
6533 /* This routine handles all the branch-on-bit conditional branch sequences we
6534 might need to generate. It handles nullification of delay slots,
6535 varying length branches, negated branches and all combinations of the
6536 above. it returns the appropriate output template to emit the branch. */
6539 output_bb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6540 int negated, rtx insn, int which)
6542 static char buf[100];
6545 /* A conditional branch to the following instruction (e.g. the delay slot) is
6546 asking for a disaster. I do not think this can happen as this pattern
6547 is only used when optimizing; jump optimization should eliminate the
6548 jump. But be prepared just in case. */
6550 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6553 /* If this is a long branch with its delay slot unfilled, set `nullify'
6554 as it can nullify the delay slot and save a nop. */
6555 if (length == 8 && dbr_sequence_length () == 0)
6558 /* If this is a short forward conditional branch which did not get
6559 its delay slot filled, the delay slot can still be nullified. */
6560 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6561 nullify = forward_branch_p (insn);
6563 /* A forward branch over a single nullified insn can be done with a
6564 extrs instruction. This avoids a single cycle penalty due to
6565 mis-predicted branch if we fall through (branch not taken). */
6568 && next_real_insn (insn) != 0
6569 && get_attr_length (next_real_insn (insn)) == 4
6570 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6577 /* All short conditional branches except backwards with an unfilled
6581 strcpy (buf, "{extrs,|extrw,s,}");
6583 strcpy (buf, "bb,");
6584 if (useskip && GET_MODE (operands[0]) == DImode)
6585 strcpy (buf, "extrd,s,*");
6586 else if (GET_MODE (operands[0]) == DImode)
6587 strcpy (buf, "bb,*");
6588 if ((which == 0 && negated)
6589 || (which == 1 && ! negated))
6594 strcat (buf, " %0,%1,1,%%r0");
6595 else if (nullify && negated)
6596 strcat (buf, ",n %0,%1,%3");
6597 else if (nullify && ! negated)
6598 strcat (buf, ",n %0,%1,%2");
6599 else if (! nullify && negated)
6600 strcat (buf, "%0,%1,%3");
6601 else if (! nullify && ! negated)
6602 strcat (buf, " %0,%1,%2");
6605 /* All long conditionals. Note a short backward branch with an
6606 unfilled delay slot is treated just like a long backward branch
6607 with an unfilled delay slot. */
6609 /* Handle weird backwards branch with a filled delay slot
6610 with is nullified. */
6611 if (dbr_sequence_length () != 0
6612 && ! forward_branch_p (insn)
6615 strcpy (buf, "bb,");
6616 if (GET_MODE (operands[0]) == DImode)
6618 if ((which == 0 && negated)
6619 || (which == 1 && ! negated))
6624 strcat (buf, ",n %0,%1,.+12\n\tb %3");
6626 strcat (buf, ",n %0,%1,.+12\n\tb %2");
6628 /* Handle short backwards branch with an unfilled delay slot.
6629 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6630 taken and untaken branches. */
6631 else if (dbr_sequence_length () == 0
6632 && ! forward_branch_p (insn)
6633 && INSN_ADDRESSES_SET_P ()
6634 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6635 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6637 strcpy (buf, "bb,");
6638 if (GET_MODE (operands[0]) == DImode)
6640 if ((which == 0 && negated)
6641 || (which == 1 && ! negated))
6646 strcat (buf, " %0,%1,%3%#");
6648 strcat (buf, " %0,%1,%2%#");
6652 strcpy (buf, "{extrs,|extrw,s,}");
6653 if (GET_MODE (operands[0]) == DImode)
6654 strcpy (buf, "extrd,s,*");
6655 if ((which == 0 && negated)
6656 || (which == 1 && ! negated))
6660 if (nullify && negated)
6661 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
6662 else if (nullify && ! negated)
6663 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
6665 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
6667 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
6677 /* This routine handles all the branch-on-variable-bit conditional branch
6678 sequences we might need to generate. It handles nullification of delay
6679 slots, varying length branches, negated branches and all combinations
6680 of the above. it returns the appropriate output template to emit the
6684 output_bvb (rtx *operands ATTRIBUTE_UNUSED, int nullify, int length,
6685 int negated, rtx insn, int which)
6687 static char buf[100];
6690 /* A conditional branch to the following instruction (e.g. the delay slot) is
6691 asking for a disaster. I do not think this can happen as this pattern
6692 is only used when optimizing; jump optimization should eliminate the
6693 jump. But be prepared just in case. */
6695 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6698 /* If this is a long branch with its delay slot unfilled, set `nullify'
6699 as it can nullify the delay slot and save a nop. */
6700 if (length == 8 && dbr_sequence_length () == 0)
6703 /* If this is a short forward conditional branch which did not get
6704 its delay slot filled, the delay slot can still be nullified. */
6705 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6706 nullify = forward_branch_p (insn);
6708 /* A forward branch over a single nullified insn can be done with a
6709 extrs instruction. This avoids a single cycle penalty due to
6710 mis-predicted branch if we fall through (branch not taken). */
6713 && next_real_insn (insn) != 0
6714 && get_attr_length (next_real_insn (insn)) == 4
6715 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6722 /* All short conditional branches except backwards with an unfilled
6726 strcpy (buf, "{vextrs,|extrw,s,}");
6728 strcpy (buf, "{bvb,|bb,}");
6729 if (useskip && GET_MODE (operands[0]) == DImode)
6730 strcpy (buf, "extrd,s,*");
6731 else if (GET_MODE (operands[0]) == DImode)
6732 strcpy (buf, "bb,*");
6733 if ((which == 0 && negated)
6734 || (which == 1 && ! negated))
6739 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6740 else if (nullify && negated)
6741 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6742 else if (nullify && ! negated)
6743 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6744 else if (! nullify && negated)
6745 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6746 else if (! nullify && ! negated)
6747 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6750 /* All long conditionals. Note a short backward branch with an
6751 unfilled delay slot is treated just like a long backward branch
6752 with an unfilled delay slot. */
6754 /* Handle weird backwards branch with a filled delay slot
6755 with is nullified. */
6756 if (dbr_sequence_length () != 0
6757 && ! forward_branch_p (insn)
6760 strcpy (buf, "{bvb,|bb,}");
6761 if (GET_MODE (operands[0]) == DImode)
6763 if ((which == 0 && negated)
6764 || (which == 1 && ! negated))
6769 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6771 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6773 /* Handle short backwards branch with an unfilled delay slot.
6774 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6775 taken and untaken branches. */
6776 else if (dbr_sequence_length () == 0
6777 && ! forward_branch_p (insn)
6778 && INSN_ADDRESSES_SET_P ()
6779 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6780 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6782 strcpy (buf, "{bvb,|bb,}");
6783 if (GET_MODE (operands[0]) == DImode)
6785 if ((which == 0 && negated)
6786 || (which == 1 && ! negated))
6791 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6793 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6797 strcpy (buf, "{vextrs,|extrw,s,}");
6798 if (GET_MODE (operands[0]) == DImode)
6799 strcpy (buf, "extrd,s,*");
6800 if ((which == 0 && negated)
6801 || (which == 1 && ! negated))
6805 if (nullify && negated)
6806 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6807 else if (nullify && ! negated)
6808 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6810 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6812 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6822 /* Return the output template for emitting a dbra type insn.
6824 Note it may perform some output operations on its own before
6825 returning the final output string. */
6827 output_dbra (rtx *operands, rtx insn, int which_alternative)
6830 /* A conditional branch to the following instruction (e.g. the delay slot) is
6831 asking for a disaster. Be prepared! */
6833 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6835 if (which_alternative == 0)
6836 return "ldo %1(%0),%0";
6837 else if (which_alternative == 1)
6839 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6840 output_asm_insn ("ldw -16(%%r30),%4", operands);
6841 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6842 return "{fldws|fldw} -16(%%r30),%0";
6846 output_asm_insn ("ldw %0,%4", operands);
6847 return "ldo %1(%4),%4\n\tstw %4,%0";
6851 if (which_alternative == 0)
6853 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6854 int length = get_attr_length (insn);
6856 /* If this is a long branch with its delay slot unfilled, set `nullify'
6857 as it can nullify the delay slot and save a nop. */
6858 if (length == 8 && dbr_sequence_length () == 0)
6861 /* If this is a short forward conditional branch which did not get
6862 its delay slot filled, the delay slot can still be nullified. */
6863 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6864 nullify = forward_branch_p (insn);
6866 /* Handle short versions first. */
6867 if (length == 4 && nullify)
6868 return "addib,%C2,n %1,%0,%3";
6869 else if (length == 4 && ! nullify)
6870 return "addib,%C2 %1,%0,%3";
6871 else if (length == 8)
6873 /* Handle weird backwards branch with a fulled delay slot
6874 which is nullified. */
6875 if (dbr_sequence_length () != 0
6876 && ! forward_branch_p (insn)
6878 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6879 /* Handle short backwards branch with an unfilled delay slot.
6880 Using a addb;nop rather than addi;bl saves 1 cycle for both
6881 taken and untaken branches. */
6882 else if (dbr_sequence_length () == 0
6883 && ! forward_branch_p (insn)
6884 && INSN_ADDRESSES_SET_P ()
6885 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6886 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6887 return "addib,%C2 %1,%0,%3%#";
6889 /* Handle normal cases. */
6891 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6893 return "addi,%N2 %1,%0,%0\n\tb %3";
6898 /* Deal with gross reload from FP register case. */
6899 else if (which_alternative == 1)
6901 /* Move loop counter from FP register to MEM then into a GR,
6902 increment the GR, store the GR into MEM, and finally reload
6903 the FP register from MEM from within the branch's delay slot. */
6904 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6906 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6907 if (get_attr_length (insn) == 24)
6908 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6910 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6912 /* Deal with gross reload from memory case. */
6915 /* Reload loop counter from memory, the store back to memory
6916 happens in the branch's delay slot. */
6917 output_asm_insn ("ldw %0,%4", operands);
6918 if (get_attr_length (insn) == 12)
6919 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6921 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6925 /* Return the output template for emitting a dbra type insn.
6927 Note it may perform some output operations on its own before
6928 returning the final output string. */
6930 output_movb (rtx *operands, rtx insn, int which_alternative,
6931 int reverse_comparison)
6934 /* A conditional branch to the following instruction (e.g. the delay slot) is
6935 asking for a disaster. Be prepared! */
6937 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6939 if (which_alternative == 0)
6940 return "copy %1,%0";
6941 else if (which_alternative == 1)
6943 output_asm_insn ("stw %1,-16(%%r30)", operands);
6944 return "{fldws|fldw} -16(%%r30),%0";
6946 else if (which_alternative == 2)
6952 /* Support the second variant. */
6953 if (reverse_comparison)
6954 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6956 if (which_alternative == 0)
6958 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6959 int length = get_attr_length (insn);
6961 /* If this is a long branch with its delay slot unfilled, set `nullify'
6962 as it can nullify the delay slot and save a nop. */
6963 if (length == 8 && dbr_sequence_length () == 0)
6966 /* If this is a short forward conditional branch which did not get
6967 its delay slot filled, the delay slot can still be nullified. */
6968 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6969 nullify = forward_branch_p (insn);
6971 /* Handle short versions first. */
6972 if (length == 4 && nullify)
6973 return "movb,%C2,n %1,%0,%3";
6974 else if (length == 4 && ! nullify)
6975 return "movb,%C2 %1,%0,%3";
6976 else if (length == 8)
6978 /* Handle weird backwards branch with a filled delay slot
6979 which is nullified. */
6980 if (dbr_sequence_length () != 0
6981 && ! forward_branch_p (insn)
6983 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6985 /* Handle short backwards branch with an unfilled delay slot.
6986 Using a movb;nop rather than or;bl saves 1 cycle for both
6987 taken and untaken branches. */
6988 else if (dbr_sequence_length () == 0
6989 && ! forward_branch_p (insn)
6990 && INSN_ADDRESSES_SET_P ()
6991 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6992 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6993 return "movb,%C2 %1,%0,%3%#";
6994 /* Handle normal cases. */
6996 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6998 return "or,%N2 %1,%%r0,%0\n\tb %3";
7003 /* Deal with gross reload from FP register case. */
7004 else if (which_alternative == 1)
7006 /* Move loop counter from FP register to MEM then into a GR,
7007 increment the GR, store the GR into MEM, and finally reload
7008 the FP register from MEM from within the branch's delay slot. */
7009 output_asm_insn ("stw %1,-16(%%r30)", operands);
7010 if (get_attr_length (insn) == 12)
7011 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
7013 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
7015 /* Deal with gross reload from memory case. */
7016 else if (which_alternative == 2)
7018 /* Reload loop counter from memory, the store back to memory
7019 happens in the branch's delay slot. */
7020 if (get_attr_length (insn) == 8)
7021 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
7023 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
7025 /* Handle SAR as a destination. */
7028 if (get_attr_length (insn) == 8)
7029 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
7031 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tmtsar %r1";
7035 /* Copy any FP arguments in INSN into integer registers. */
7037 copy_fp_args (rtx insn)
7042 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7044 int arg_mode, regno;
7045 rtx use = XEXP (link, 0);
7047 if (! (GET_CODE (use) == USE
7048 && GET_CODE (XEXP (use, 0)) == REG
7049 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7052 arg_mode = GET_MODE (XEXP (use, 0));
7053 regno = REGNO (XEXP (use, 0));
7055 /* Is it a floating point register? */
7056 if (regno >= 32 && regno <= 39)
7058 /* Copy the FP register into an integer register via memory. */
7059 if (arg_mode == SFmode)
7061 xoperands[0] = XEXP (use, 0);
7062 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
7063 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
7064 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7068 xoperands[0] = XEXP (use, 0);
7069 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
7070 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
7071 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
7072 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
7078 /* Compute length of the FP argument copy sequence for INSN. */
7080 length_fp_args (rtx insn)
7085 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
7087 int arg_mode, regno;
7088 rtx use = XEXP (link, 0);
7090 if (! (GET_CODE (use) == USE
7091 && GET_CODE (XEXP (use, 0)) == REG
7092 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
7095 arg_mode = GET_MODE (XEXP (use, 0));
7096 regno = REGNO (XEXP (use, 0));
7098 /* Is it a floating point register? */
7099 if (regno >= 32 && regno <= 39)
7101 if (arg_mode == SFmode)
7111 /* Return the attribute length for the millicode call instruction INSN.
7112 The length must match the code generated by output_millicode_call.
7113 We include the delay slot in the returned length as it is better to
7114 over estimate the length than to under estimate it. */
7117 attr_length_millicode_call (rtx insn)
7119 unsigned long distance = -1;
7120 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7122 if (INSN_ADDRESSES_SET_P ())
7124 distance = (total + insn_current_reference_address (insn));
7125 if (distance < total)
7131 if (!TARGET_LONG_CALLS && distance < 7600000)
7136 else if (TARGET_PORTABLE_RUNTIME)
7140 if (!TARGET_LONG_CALLS && distance < 240000)
7143 if (TARGET_LONG_ABS_CALL && !flag_pic)
7150 /* INSN is a function call. It may have an unconditional jump
7153 CALL_DEST is the routine we are calling. */
7156 output_millicode_call (rtx insn, rtx call_dest)
7158 int attr_length = get_attr_length (insn);
7159 int seq_length = dbr_sequence_length ();
7164 xoperands[0] = call_dest;
7165 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
7167 /* Handle the common case where we are sure that the branch will
7168 reach the beginning of the $CODE$ subspace. The within reach
7169 form of the $$sh_func_adrs call has a length of 28. Because
7170 it has an attribute type of multi, it never has a nonzero
7171 sequence length. The length of the $$sh_func_adrs is the same
7172 as certain out of reach PIC calls to other routines. */
7173 if (!TARGET_LONG_CALLS
7174 && ((seq_length == 0
7175 && (attr_length == 12
7176 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
7177 || (seq_length != 0 && attr_length == 8)))
7179 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
7185 /* It might seem that one insn could be saved by accessing
7186 the millicode function using the linkage table. However,
7187 this doesn't work in shared libraries and other dynamically
7188 loaded objects. Using a pc-relative sequence also avoids
7189 problems related to the implicit use of the gp register. */
7190 output_asm_insn ("b,l .+8,%%r1", xoperands);
7194 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
7195 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
7199 xoperands[1] = gen_label_rtx ();
7200 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7201 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7202 CODE_LABEL_NUMBER (xoperands[1]));
7203 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7206 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7208 else if (TARGET_PORTABLE_RUNTIME)
7210 /* Pure portable runtime doesn't allow be/ble; we also don't
7211 have PIC support in the assembler/linker, so this sequence
7214 /* Get the address of our target into %r1. */
7215 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7216 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
7218 /* Get our return address into %r31. */
7219 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
7220 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
7222 /* Jump to our target address in %r1. */
7223 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7227 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7229 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
7231 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7235 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7236 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
7238 if (TARGET_SOM || !TARGET_GAS)
7240 /* The HP assembler can generate relocations for the
7241 difference of two symbols. GAS can do this for a
7242 millicode symbol but not an arbitrary external
7243 symbol when generating SOM output. */
7244 xoperands[1] = gen_label_rtx ();
7245 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7246 CODE_LABEL_NUMBER (xoperands[1]));
7247 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7248 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7252 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
7253 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
7257 /* Jump to our target address in %r1. */
7258 output_asm_insn ("bv %%r0(%%r1)", xoperands);
7262 if (seq_length == 0)
7263 output_asm_insn ("nop", xoperands);
7265 /* We are done if there isn't a jump in the delay slot. */
7266 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7269 /* This call has an unconditional jump in its delay slot. */
7270 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7272 /* See if the return address can be adjusted. Use the containing
7273 sequence insn's address. */
7274 if (INSN_ADDRESSES_SET_P ())
7276 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7277 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7278 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7280 if (VAL_14_BITS_P (distance))
7282 xoperands[1] = gen_label_rtx ();
7283 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
7284 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7285 CODE_LABEL_NUMBER (xoperands[1]));
7288 /* ??? This branch may not reach its target. */
7289 output_asm_insn ("nop\n\tb,n %0", xoperands);
7292 /* ??? This branch may not reach its target. */
7293 output_asm_insn ("nop\n\tb,n %0", xoperands);
7295 /* Delete the jump. */
7296 PUT_CODE (NEXT_INSN (insn), NOTE);
7297 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7298 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7303 /* Return the attribute length of the call instruction INSN. The SIBCALL
7304 flag indicates whether INSN is a regular call or a sibling call. The
7305 length returned must be longer than the code actually generated by
7306 output_call. Since branch shortening is done before delay branch
7307 sequencing, there is no way to determine whether or not the delay
7308 slot will be filled during branch shortening. Even when the delay
7309 slot is filled, we may have to add a nop if the delay slot contains
7310 a branch that can't reach its target. Thus, we always have to include
7311 the delay slot in the length estimate. This used to be done in
7312 pa_adjust_insn_length but we do it here now as some sequences always
7313 fill the delay slot and we can save four bytes in the estimate for
7317 attr_length_call (rtx insn, int sibcall)
7323 rtx pat = PATTERN (insn);
7324 unsigned long distance = -1;
7326 if (INSN_ADDRESSES_SET_P ())
7328 unsigned long total;
7330 total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7331 distance = (total + insn_current_reference_address (insn));
7332 if (distance < total)
7336 /* Determine if this is a local call. */
7337 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL)
7338 call_dest = XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0);
7340 call_dest = XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0);
7342 call_decl = SYMBOL_REF_DECL (call_dest);
7343 local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7345 /* pc-relative branch. */
7346 if (!TARGET_LONG_CALLS
7347 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
7348 || distance < 240000))
7351 /* 64-bit plabel sequence. */
7352 else if (TARGET_64BIT && !local_call)
7353 length += sibcall ? 28 : 24;
7355 /* non-pic long absolute branch sequence. */
7356 else if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7359 /* long pc-relative branch sequence. */
7360 else if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7361 || (TARGET_64BIT && !TARGET_GAS)
7362 || (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call)))
7366 if (!TARGET_PA_20 && !TARGET_NO_SPACE_REGS)
7370 /* 32-bit plabel sequence. */
7376 length += length_fp_args (insn);
7386 if (!TARGET_NO_SPACE_REGS)
7394 /* INSN is a function call. It may have an unconditional jump
7397 CALL_DEST is the routine we are calling. */
7400 output_call (rtx insn, rtx call_dest, int sibcall)
7402 int delay_insn_deleted = 0;
7403 int delay_slot_filled = 0;
7404 int seq_length = dbr_sequence_length ();
7405 tree call_decl = SYMBOL_REF_DECL (call_dest);
7406 int local_call = call_decl && (*targetm.binds_local_p) (call_decl);
7409 xoperands[0] = call_dest;
7411 /* Handle the common case where we're sure that the branch will reach
7412 the beginning of the "$CODE$" subspace. This is the beginning of
7413 the current function if we are in a named section. */
7414 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
7416 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
7417 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
7421 if (TARGET_64BIT && !local_call)
7423 /* ??? As far as I can tell, the HP linker doesn't support the
7424 long pc-relative sequence described in the 64-bit runtime
7425 architecture. So, we use a slightly longer indirect call. */
7426 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7428 xoperands[0] = p->internal_label;
7429 xoperands[1] = gen_label_rtx ();
7431 /* If this isn't a sibcall, we put the load of %r27 into the
7432 delay slot. We can't do this in a sibcall as we don't
7433 have a second call-clobbered scratch register available. */
7435 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7438 final_scan_insn (NEXT_INSN (insn), asm_out_file,
7439 optimize, 0, 0, NULL);
7441 /* Now delete the delay insn. */
7442 PUT_CODE (NEXT_INSN (insn), NOTE);
7443 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7444 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7445 delay_insn_deleted = 1;
7448 output_asm_insn ("addil LT'%0,%%r27", xoperands);
7449 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
7450 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
7454 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7455 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
7456 output_asm_insn ("bve (%%r1)", xoperands);
7460 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
7461 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
7462 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
7463 delay_slot_filled = 1;
7468 int indirect_call = 0;
7470 /* Emit a long call. There are several different sequences
7471 of increasing length and complexity. In most cases,
7472 they don't allow an instruction in the delay slot. */
7473 if (!((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7474 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7475 && !(TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7480 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
7482 && (!TARGET_PA_20 || indirect_call))
7484 /* A non-jump insn in the delay slot. By definition we can
7485 emit this insn before the call (and in fact before argument
7487 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0,
7490 /* Now delete the delay insn. */
7491 PUT_CODE (NEXT_INSN (insn), NOTE);
7492 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7493 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7494 delay_insn_deleted = 1;
7497 if ((TARGET_LONG_ABS_CALL || local_call) && !flag_pic)
7499 /* This is the best sequence for making long calls in
7500 non-pic code. Unfortunately, GNU ld doesn't provide
7501 the stub needed for external calls, and GAS's support
7502 for this with the SOM linker is buggy. It is safe
7503 to use this for local calls. */
7504 output_asm_insn ("ldil L'%0,%%r1", xoperands);
7506 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
7510 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
7513 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
7515 output_asm_insn ("copy %%r31,%%r2", xoperands);
7516 delay_slot_filled = 1;
7521 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
7522 || (TARGET_64BIT && !TARGET_GAS))
7524 /* The HP assembler and linker can handle relocations
7525 for the difference of two symbols. GAS and the HP
7526 linker can't do this when one of the symbols is
7528 xoperands[1] = gen_label_rtx ();
7529 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7530 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
7531 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7532 CODE_LABEL_NUMBER (xoperands[1]));
7533 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
7535 else if (TARGET_GAS && (TARGET_LONG_PIC_PCREL_CALL || local_call))
7537 /* GAS currently can't generate the relocations that
7538 are needed for the SOM linker under HP-UX using this
7539 sequence. The GNU linker doesn't generate the stubs
7540 that are needed for external calls on TARGET_ELF32
7541 with this sequence. For now, we have to use a
7542 longer plabel sequence when using GAS. */
7543 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7544 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
7546 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
7551 /* Emit a long plabel-based call sequence. This is
7552 essentially an inline implementation of $$dyncall.
7553 We don't actually try to call $$dyncall as this is
7554 as difficult as calling the function itself. */
7555 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
7557 xoperands[0] = p->internal_label;
7558 xoperands[1] = gen_label_rtx ();
7560 /* Since the call is indirect, FP arguments in registers
7561 need to be copied to the general registers. Then, the
7562 argument relocation stub will copy them back. */
7564 copy_fp_args (insn);
7568 output_asm_insn ("addil LT'%0,%%r19", xoperands);
7569 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
7570 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
7574 output_asm_insn ("addil LR'%0-$global$,%%r27",
7576 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
7580 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
7581 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
7582 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
7583 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
7585 if (!sibcall && !TARGET_PA_20)
7587 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
7588 if (TARGET_NO_SPACE_REGS)
7589 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
7591 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
7598 output_asm_insn ("bve (%%r1)", xoperands);
7603 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7604 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
7605 delay_slot_filled = 1;
7608 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
7613 if (!TARGET_NO_SPACE_REGS)
7614 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
7619 if (TARGET_NO_SPACE_REGS)
7620 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
7622 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
7626 if (TARGET_NO_SPACE_REGS)
7627 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
7629 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
7632 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
7634 output_asm_insn ("copy %%r31,%%r2", xoperands);
7635 delay_slot_filled = 1;
7642 if (!delay_slot_filled && (seq_length == 0 || delay_insn_deleted))
7643 output_asm_insn ("nop", xoperands);
7645 /* We are done if there isn't a jump in the delay slot. */
7647 || delay_insn_deleted
7648 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
7651 /* A sibcall should never have a branch in the delay slot. */
7655 /* This call has an unconditional jump in its delay slot. */
7656 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
7658 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
7660 /* See if the return address can be adjusted. Use the containing
7661 sequence insn's address. */
7662 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
7663 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
7664 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
7666 if (VAL_14_BITS_P (distance))
7668 xoperands[1] = gen_label_rtx ();
7669 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
7670 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7671 CODE_LABEL_NUMBER (xoperands[1]));
7674 output_asm_insn ("nop\n\tb,n %0", xoperands);
7677 output_asm_insn ("b,n %0", xoperands);
7679 /* Delete the jump. */
7680 PUT_CODE (NEXT_INSN (insn), NOTE);
7681 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
7682 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
7687 /* Return the attribute length of the indirect call instruction INSN.
7688 The length must match the code generated by output_indirect call.
7689 The returned length includes the delay slot. Currently, the delay
7690 slot of an indirect call sequence is not exposed and it is used by
7691 the sequence itself. */
7694 attr_length_indirect_call (rtx insn)
7696 unsigned long distance = -1;
7697 unsigned long total = IN_NAMED_SECTION_P (cfun->decl) ? 0 : total_code_bytes;
7699 if (INSN_ADDRESSES_SET_P ())
7701 distance = (total + insn_current_reference_address (insn));
7702 if (distance < total)
7709 if (TARGET_FAST_INDIRECT_CALLS
7710 || (!TARGET_PORTABLE_RUNTIME
7711 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7717 if (TARGET_PORTABLE_RUNTIME)
7720 /* Out of reach, can use ble. */
7725 output_indirect_call (rtx insn, rtx call_dest)
7731 xoperands[0] = call_dest;
7732 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7733 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7737 /* First the special case for kernels, level 0 systems, etc. */
7738 if (TARGET_FAST_INDIRECT_CALLS)
7739 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7741 /* Now the normal case -- we can reach $$dyncall directly or
7742 we're sure that we can get there via a long-branch stub.
7744 No need to check target flags as the length uniquely identifies
7745 the remaining cases. */
7746 if (attr_length_indirect_call (insn) == 8)
7748 /* The HP linker substitutes a BLE for millicode calls using
7749 the short PIC PCREL form. Thus, we must use %r31 as the
7750 link register when generating PA 1.x code. */
7752 return ".CALL\tARGW0=GR\n\tb,l $$dyncall,%%r2\n\tcopy %%r2,%%r31";
7754 return ".CALL\tARGW0=GR\n\tbl $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7757 /* Long millicode call, but we are not generating PIC or portable runtime
7759 if (attr_length_indirect_call (insn) == 12)
7760 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7762 /* Long millicode call for portable runtime. */
7763 if (attr_length_indirect_call (insn) == 20)
7764 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7766 /* We need a long PIC call to $$dyncall. */
7767 xoperands[0] = NULL_RTX;
7768 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7769 if (TARGET_SOM || !TARGET_GAS)
7771 xoperands[0] = gen_label_rtx ();
7772 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7773 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7774 CODE_LABEL_NUMBER (xoperands[0]));
7775 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7779 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7780 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7783 output_asm_insn ("blr %%r0,%%r2", xoperands);
7784 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7788 /* Return the total length of the save and restore instructions needed for
7789 the data linkage table pointer (i.e., the PIC register) across the call
7790 instruction INSN. No-return calls do not require a save and restore.
7791 In addition, we may be able to avoid the save and restore for calls
7792 within the same translation unit. */
7795 attr_length_save_restore_dltp (rtx insn)
7797 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7803 /* In HPUX 8.0's shared library scheme, special relocations are needed
7804 for function labels if they might be passed to a function
7805 in a shared library (because shared libraries don't live in code
7806 space), and special magic is needed to construct their address. */
7809 hppa_encode_label (rtx sym)
7811 const char *str = XSTR (sym, 0);
7812 int len = strlen (str) + 1;
7815 p = newstr = alloca (len + 1);
7819 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7823 pa_encode_section_info (tree decl, rtx rtl, int first)
7825 if (first && TEXT_SPACE_P (decl))
7827 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7828 if (TREE_CODE (decl) == FUNCTION_DECL)
7829 hppa_encode_label (XEXP (rtl, 0));
7833 /* This is sort of inverse to pa_encode_section_info. */
7836 pa_strip_name_encoding (const char *str)
7838 str += (*str == '@');
7839 str += (*str == '*');
7844 function_label_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
7846 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7849 /* Returns 1 if OP is a function label involved in a simple addition
7850 with a constant. Used to keep certain patterns from matching
7851 during instruction combination. */
7853 is_function_label_plus_const (rtx op)
7855 /* Strip off any CONST. */
7856 if (GET_CODE (op) == CONST)
7859 return (GET_CODE (op) == PLUS
7860 && function_label_operand (XEXP (op, 0), Pmode)
7861 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7864 /* Output assembly code for a thunk to FUNCTION. */
7867 pa_asm_output_mi_thunk (FILE *file, tree thunk_fndecl, HOST_WIDE_INT delta,
7868 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
7871 const char *fname = XSTR (XEXP (DECL_RTL (function), 0), 0);
7872 const char *tname = XSTR (XEXP (DECL_RTL (thunk_fndecl), 0), 0);
7873 int val_14 = VAL_14_BITS_P (delta);
7875 static unsigned int current_thunk_number;
7878 ASM_OUTPUT_LABEL (file, tname);
7879 fprintf (file, "\t.PROC\n\t.CALLINFO FRAME=0,NO_CALLS\n\t.ENTRY\n");
7881 fname = (*targetm.strip_name_encoding) (fname);
7882 tname = (*targetm.strip_name_encoding) (tname);
7884 /* Output the thunk. We know that the function is in the same
7885 translation unit (i.e., the same space) as the thunk, and that
7886 thunks are output after their method. Thus, we don't need an
7887 external branch to reach the function. With SOM and GAS,
7888 functions and thunks are effectively in different sections.
7889 Thus, we can always use a IA-relative branch and the linker
7890 will add a long branch stub if necessary.
7892 However, we have to be careful when generating PIC code on the
7893 SOM port to ensure that the sequence does not transfer to an
7894 import stub for the target function as this could clobber the
7895 return value saved at SP-24. This would also apply to the
7896 32-bit linux port if the multi-space model is implemented. */
7897 if ((!TARGET_LONG_CALLS && TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7898 && !(flag_pic && TREE_PUBLIC (function))
7899 && (TARGET_GAS || last_address < 262132))
7900 || (!TARGET_LONG_CALLS && !TARGET_SOM && !TARGET_PORTABLE_RUNTIME
7901 && ((targetm.have_named_sections
7902 && DECL_SECTION_NAME (thunk_fndecl) != NULL
7903 /* The GNU 64-bit linker has rather poor stub management.
7904 So, we use a long branch from thunks that aren't in
7905 the same section as the target function. */
7907 && (DECL_SECTION_NAME (thunk_fndecl)
7908 != DECL_SECTION_NAME (function)))
7909 || ((DECL_SECTION_NAME (thunk_fndecl)
7910 == DECL_SECTION_NAME (function))
7911 && last_address < 262132)))
7912 || (!targetm.have_named_sections && last_address < 262132))))
7916 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7917 "(%%r26),%%r26\n", fname, delta);
7922 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7924 fprintf (file, "\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7925 "(%%r1),%%r26\n", fname, delta);
7929 else if (TARGET_64BIT)
7931 /* We only have one call-clobbered scratch register, so we can't
7932 make use of the delay slot if delta doesn't fit in 14 bits. */
7934 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7935 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7936 "(%%r1),%%r26\n", delta, delta);
7938 fprintf (file, "\tb,l .+8,%%r1\n");
7942 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
7943 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r1\n", fname);
7947 int off = val_14 ? 8 : 16;
7948 fprintf (file, "\taddil L'%s-%s-%d,%%r1\n", fname, tname, off);
7949 fprintf (file, "\tldo R'%s-%s-%d(%%r1),%%r1\n", fname, tname, off);
7954 fprintf (file, "\tbv %%r0(%%r1)\n\tldo ");
7955 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7960 fprintf (file, "\tbv,n %%r0(%%r1)\n");
7964 else if (TARGET_PORTABLE_RUNTIME)
7966 fprintf (file, "\tldil L'%s,%%r1\n", fname);
7967 fprintf (file, "\tldo R'%s(%%r1),%%r22\n", fname);
7971 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7972 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7977 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7979 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
7980 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
7984 else if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
7986 /* The function is accessible from outside this module. The only
7987 way to avoid an import stub between the thunk and function is to
7988 call the function directly with an indirect sequence similar to
7989 that used by $$dyncall. This is possible because $$dyncall acts
7990 as the import stub in an indirect call. */
7993 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7994 lab = (*targetm.strip_name_encoding) (label);
7996 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7997 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7998 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7999 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
8000 fprintf (file, "\tdepi 0,31,2,%%r22\n");
8001 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
8002 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
8005 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
8011 fprintf (file, "\tbve (%%r22)\n\tldo ");
8016 if (TARGET_NO_SPACE_REGS)
8018 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
8023 fprintf (file, "\tldsid (%%sr0,%%r22),%%r21\n");
8024 fprintf (file, "\tmtsp %%r21,%%sr0\n");
8025 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
8031 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8033 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8038 fprintf (file, "\tb,l .+8,%%r1\n");
8040 fprintf (file, "\tbl .+8,%%r1\n");
8042 if (TARGET_SOM || !TARGET_GAS)
8044 fprintf (file, "\taddil L'%s-%s-8,%%r1\n", fname, tname);
8045 fprintf (file, "\tldo R'%s-%s-8(%%r1),%%r22\n", fname, tname);
8049 fprintf (file, "\taddil L'%s-$PIC_pcrel$0+4,%%r1\n", fname);
8050 fprintf (file, "\tldo R'%s-$PIC_pcrel$0+8(%%r1),%%r22\n", fname);
8055 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8056 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8061 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
8063 fprintf (file, "\tbv %%r0(%%r22)\n\tldo ");
8064 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8071 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC ",%%r26\n", delta);
8073 fprintf (file, "\tldil L'%s,%%r22\n", fname);
8074 fprintf (file, "\tbe R'%s(%%sr4,%%r22)\n\tldo ", fname);
8078 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
8083 fprintf (file, "R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n", delta);
8088 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
8090 if (TARGET_SOM && flag_pic && TREE_PUBLIC (function))
8093 fprintf (file, "\t.align 4\n");
8094 ASM_OUTPUT_LABEL (file, label);
8095 fprintf (file, "\t.word P'%s\n", fname);
8097 else if (TARGET_SOM && TARGET_GAS)
8100 current_thunk_number++;
8101 nbytes = ((nbytes + FUNCTION_BOUNDARY / BITS_PER_UNIT - 1)
8102 & ~(FUNCTION_BOUNDARY / BITS_PER_UNIT - 1));
8103 last_address += nbytes;
8104 update_total_code_bytes (nbytes);
8107 /* Only direct calls to static functions are allowed to be sibling (tail)
8110 This restriction is necessary because some linker generated stubs will
8111 store return pointers into rp' in some cases which might clobber a
8112 live value already in rp'.
8114 In a sibcall the current function and the target function share stack
8115 space. Thus if the path to the current function and the path to the
8116 target function save a value in rp', they save the value into the
8117 same stack slot, which has undesirable consequences.
8119 Because of the deferred binding nature of shared libraries any function
8120 with external scope could be in a different load module and thus require
8121 rp' to be saved when calling that function. So sibcall optimizations
8122 can only be safe for static function.
8124 Note that GCC never needs return value relocations, so we don't have to
8125 worry about static calls with return value relocations (which require
8128 It is safe to perform a sibcall optimization when the target function
8129 will never return. */
8131 pa_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED)
8133 if (TARGET_PORTABLE_RUNTIME)
8136 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
8137 single subspace mode and the call is not indirect. As far as I know,
8138 there is no operating system support for the multiple subspace mode.
8139 It might be possible to support indirect calls if we didn't use
8140 $$dyncall (see the indirect sequence generated in output_call). */
8142 return (decl != NULL_TREE);
8144 /* Sibcalls are not ok because the arg pointer register is not a fixed
8145 register. This prevents the sibcall optimization from occurring. In
8146 addition, there are problems with stub placement using GNU ld. This
8147 is because a normal sibcall branch uses a 17-bit relocation while
8148 a regular call branch uses a 22-bit relocation. As a result, more
8149 care needs to be taken in the placement of long-branch stubs. */
8153 /* Sibcalls are only ok within a translation unit. */
8154 return (decl && !TREE_PUBLIC (decl));
8157 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8158 use in fmpyadd instructions. */
8160 fmpyaddoperands (rtx *operands)
8162 enum machine_mode mode = GET_MODE (operands[0]);
8164 /* Must be a floating point mode. */
8165 if (mode != SFmode && mode != DFmode)
8168 /* All modes must be the same. */
8169 if (! (mode == GET_MODE (operands[1])
8170 && mode == GET_MODE (operands[2])
8171 && mode == GET_MODE (operands[3])
8172 && mode == GET_MODE (operands[4])
8173 && mode == GET_MODE (operands[5])))
8176 /* All operands must be registers. */
8177 if (! (GET_CODE (operands[1]) == REG
8178 && GET_CODE (operands[2]) == REG
8179 && GET_CODE (operands[3]) == REG
8180 && GET_CODE (operands[4]) == REG
8181 && GET_CODE (operands[5]) == REG))
8184 /* Only 2 real operands to the addition. One of the input operands must
8185 be the same as the output operand. */
8186 if (! rtx_equal_p (operands[3], operands[4])
8187 && ! rtx_equal_p (operands[3], operands[5]))
8190 /* Inout operand of add cannot conflict with any operands from multiply. */
8191 if (rtx_equal_p (operands[3], operands[0])
8192 || rtx_equal_p (operands[3], operands[1])
8193 || rtx_equal_p (operands[3], operands[2]))
8196 /* multiply cannot feed into addition operands. */
8197 if (rtx_equal_p (operands[4], operands[0])
8198 || rtx_equal_p (operands[5], operands[0]))
8201 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8203 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8204 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8205 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8206 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8207 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8208 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8211 /* Passed. Operands are suitable for fmpyadd. */
8215 #if !defined(USE_COLLECT2)
8217 pa_asm_out_constructor (rtx symbol, int priority)
8219 if (!function_label_operand (symbol, VOIDmode))
8220 hppa_encode_label (symbol);
8222 #ifdef CTORS_SECTION_ASM_OP
8223 default_ctor_section_asm_out_constructor (symbol, priority);
8225 # ifdef TARGET_ASM_NAMED_SECTION
8226 default_named_section_asm_out_constructor (symbol, priority);
8228 default_stabs_asm_out_constructor (symbol, priority);
8234 pa_asm_out_destructor (rtx symbol, int priority)
8236 if (!function_label_operand (symbol, VOIDmode))
8237 hppa_encode_label (symbol);
8239 #ifdef DTORS_SECTION_ASM_OP
8240 default_dtor_section_asm_out_destructor (symbol, priority);
8242 # ifdef TARGET_ASM_NAMED_SECTION
8243 default_named_section_asm_out_destructor (symbol, priority);
8245 default_stabs_asm_out_destructor (symbol, priority);
8251 /* This function places uninitialized global data in the bss section.
8252 The ASM_OUTPUT_ALIGNED_BSS macro needs to be defined to call this
8253 function on the SOM port to prevent uninitialized global data from
8254 being placed in the data section. */
8257 pa_asm_output_aligned_bss (FILE *stream,
8259 unsigned HOST_WIDE_INT size,
8263 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8265 #ifdef ASM_OUTPUT_TYPE_DIRECTIVE
8266 ASM_OUTPUT_TYPE_DIRECTIVE (stream, name, "object");
8269 #ifdef ASM_OUTPUT_SIZE_DIRECTIVE
8270 ASM_OUTPUT_SIZE_DIRECTIVE (stream, name, size);
8273 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8274 ASM_OUTPUT_LABEL (stream, name);
8275 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8278 /* Both the HP and GNU assemblers under HP-UX provide a .comm directive
8279 that doesn't allow the alignment of global common storage to be directly
8280 specified. The SOM linker aligns common storage based on the rounded
8281 value of the NUM_BYTES parameter in the .comm directive. It's not
8282 possible to use the .align directive as it doesn't affect the alignment
8283 of the label associated with a .comm directive. */
8286 pa_asm_output_aligned_common (FILE *stream,
8288 unsigned HOST_WIDE_INT size,
8291 unsigned int max_common_align;
8293 max_common_align = TARGET_64BIT ? 128 : (size >= 4096 ? 256 : 64);
8294 if (align > max_common_align)
8296 warning ("alignment (%u) for %s exceeds maximum alignment "
8297 "for global common data. Using %u",
8298 align / BITS_PER_UNIT, name, max_common_align / BITS_PER_UNIT);
8299 align = max_common_align;
8304 assemble_name (stream, name);
8305 fprintf (stream, "\t.comm "HOST_WIDE_INT_PRINT_UNSIGNED"\n",
8306 MAX (size, align / BITS_PER_UNIT));
8309 /* We can't use .comm for local common storage as the SOM linker effectively
8310 treats the symbol as universal and uses the same storage for local symbols
8311 with the same name in different object files. The .block directive
8312 reserves an uninitialized block of storage. However, it's not common
8313 storage. Fortunately, GCC never requests common storage with the same
8314 name in any given translation unit. */
8317 pa_asm_output_aligned_local (FILE *stream,
8319 unsigned HOST_WIDE_INT size,
8323 fprintf (stream, "\t.align %u\n", align / BITS_PER_UNIT);
8326 fprintf (stream, "%s", LOCAL_ASM_OP);
8327 assemble_name (stream, name);
8328 fprintf (stream, "\n");
8331 ASM_OUTPUT_LABEL (stream, name);
8332 fprintf (stream, "\t.block "HOST_WIDE_INT_PRINT_UNSIGNED"\n", size);
8335 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
8336 use in fmpysub instructions. */
8338 fmpysuboperands (rtx *operands)
8340 enum machine_mode mode = GET_MODE (operands[0]);
8342 /* Must be a floating point mode. */
8343 if (mode != SFmode && mode != DFmode)
8346 /* All modes must be the same. */
8347 if (! (mode == GET_MODE (operands[1])
8348 && mode == GET_MODE (operands[2])
8349 && mode == GET_MODE (operands[3])
8350 && mode == GET_MODE (operands[4])
8351 && mode == GET_MODE (operands[5])))
8354 /* All operands must be registers. */
8355 if (! (GET_CODE (operands[1]) == REG
8356 && GET_CODE (operands[2]) == REG
8357 && GET_CODE (operands[3]) == REG
8358 && GET_CODE (operands[4]) == REG
8359 && GET_CODE (operands[5]) == REG))
8362 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
8363 operation, so operands[4] must be the same as operand[3]. */
8364 if (! rtx_equal_p (operands[3], operands[4]))
8367 /* multiply cannot feed into subtraction. */
8368 if (rtx_equal_p (operands[5], operands[0]))
8371 /* Inout operand of sub cannot conflict with any operands from multiply. */
8372 if (rtx_equal_p (operands[3], operands[0])
8373 || rtx_equal_p (operands[3], operands[1])
8374 || rtx_equal_p (operands[3], operands[2]))
8377 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
8379 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
8380 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
8381 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
8382 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
8383 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
8384 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
8387 /* Passed. Operands are suitable for fmpysub. */
8392 plus_xor_ior_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8394 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
8395 || GET_CODE (op) == IOR);
8398 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
8399 constants for shadd instructions. */
8401 shadd_constant_p (int val)
8403 if (val == 2 || val == 4 || val == 8)
8409 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
8410 the valid constant for shadd instructions. */
8412 shadd_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8414 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
8417 /* Return 1 if OP is valid as a base or index register in a
8421 borx_reg_operand (rtx op, enum machine_mode mode)
8423 if (GET_CODE (op) != REG)
8426 /* We must reject virtual registers as the only expressions that
8427 can be instantiated are REG and REG+CONST. */
8428 if (op == virtual_incoming_args_rtx
8429 || op == virtual_stack_vars_rtx
8430 || op == virtual_stack_dynamic_rtx
8431 || op == virtual_outgoing_args_rtx
8432 || op == virtual_cfa_rtx)
8435 /* While it's always safe to index off the frame pointer, it's not
8436 profitable to do so when the frame pointer is being eliminated. */
8437 if (!reload_completed
8438 && flag_omit_frame_pointer
8439 && !current_function_calls_alloca
8440 && op == frame_pointer_rtx)
8443 return register_operand (op, mode);
8446 /* Return 1 if this operand is anything other than a hard register. */
8449 non_hard_reg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8451 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
8454 /* Return 1 if INSN branches forward. Should be using insn_addresses
8455 to avoid walking through all the insns... */
8457 forward_branch_p (rtx insn)
8459 rtx label = JUMP_LABEL (insn);
8466 insn = NEXT_INSN (insn);
8469 return (insn == label);
8472 /* Return 1 if OP is an equality comparison, else return 0. */
8474 eq_neq_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8476 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
8479 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
8481 movb_comparison_operator (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
8483 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
8484 || GET_CODE (op) == LT || GET_CODE (op) == GE);
8487 /* Return 1 if INSN is in the delay slot of a call instruction. */
8489 jump_in_call_delay (rtx insn)
8492 if (GET_CODE (insn) != JUMP_INSN)
8495 if (PREV_INSN (insn)
8496 && PREV_INSN (PREV_INSN (insn))
8497 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
8499 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
8501 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
8502 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
8509 /* Output an unconditional move and branch insn. */
8512 output_parallel_movb (rtx *operands, int length)
8514 /* These are the cases in which we win. */
8516 return "mov%I1b,tr %1,%0,%2";
8518 /* None of these cases wins, but they don't lose either. */
8519 if (dbr_sequence_length () == 0)
8521 /* Nothing in the delay slot, fake it by putting the combined
8522 insn (the copy or add) in the delay slot of a bl. */
8523 if (GET_CODE (operands[1]) == CONST_INT)
8524 return "b %2\n\tldi %1,%0";
8526 return "b %2\n\tcopy %1,%0";
8530 /* Something in the delay slot, but we've got a long branch. */
8531 if (GET_CODE (operands[1]) == CONST_INT)
8532 return "ldi %1,%0\n\tb %2";
8534 return "copy %1,%0\n\tb %2";
8538 /* Output an unconditional add and branch insn. */
8541 output_parallel_addb (rtx *operands, int length)
8543 /* To make life easy we want operand0 to be the shared input/output
8544 operand and operand1 to be the readonly operand. */
8545 if (operands[0] == operands[1])
8546 operands[1] = operands[2];
8548 /* These are the cases in which we win. */
8550 return "add%I1b,tr %1,%0,%3";
8552 /* None of these cases win, but they don't lose either. */
8553 if (dbr_sequence_length () == 0)
8555 /* Nothing in the delay slot, fake it by putting the combined
8556 insn (the copy or add) in the delay slot of a bl. */
8557 return "b %3\n\tadd%I1 %1,%0,%0";
8561 /* Something in the delay slot, but we've got a long branch. */
8562 return "add%I1 %1,%0,%0\n\tb %3";
8566 /* Return nonzero if INSN (a jump insn) immediately follows a call
8567 to a named function. This is used to avoid filling the delay slot
8568 of the jump since it can usually be eliminated by modifying RP in
8569 the delay slot of the call. */
8572 following_call (rtx insn)
8574 if (! TARGET_JUMP_IN_DELAY)
8577 /* Find the previous real insn, skipping NOTEs. */
8578 insn = PREV_INSN (insn);
8579 while (insn && GET_CODE (insn) == NOTE)
8580 insn = PREV_INSN (insn);
8582 /* Check for CALL_INSNs and millicode calls. */
8584 && ((GET_CODE (insn) == CALL_INSN
8585 && get_attr_type (insn) != TYPE_DYNCALL)
8586 || (GET_CODE (insn) == INSN
8587 && GET_CODE (PATTERN (insn)) != SEQUENCE
8588 && GET_CODE (PATTERN (insn)) != USE
8589 && GET_CODE (PATTERN (insn)) != CLOBBER
8590 && get_attr_type (insn) == TYPE_MILLI)))
8596 /* We use this hook to perform a PA specific optimization which is difficult
8597 to do in earlier passes.
8599 We want the delay slots of branches within jump tables to be filled.
8600 None of the compiler passes at the moment even has the notion that a
8601 PA jump table doesn't contain addresses, but instead contains actual
8604 Because we actually jump into the table, the addresses of each entry
8605 must stay constant in relation to the beginning of the table (which
8606 itself must stay constant relative to the instruction to jump into
8607 it). I don't believe we can guarantee earlier passes of the compiler
8608 will adhere to those rules.
8610 So, late in the compilation process we find all the jump tables, and
8611 expand them into real code -- e.g. each entry in the jump table vector
8612 will get an appropriate label followed by a jump to the final target.
8614 Reorg and the final jump pass can then optimize these branches and
8615 fill their delay slots. We end up with smaller, more efficient code.
8617 The jump instructions within the table are special; we must be able
8618 to identify them during assembly output (if the jumps don't get filled
8619 we need to emit a nop rather than nullifying the delay slot)). We
8620 identify jumps in switch tables by using insns with the attribute
8621 type TYPE_BTABLE_BRANCH.
8623 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
8624 insns. This serves two purposes, first it prevents jump.c from
8625 noticing that the last N entries in the table jump to the instruction
8626 immediately after the table and deleting the jumps. Second, those
8627 insns mark where we should emit .begin_brtab and .end_brtab directives
8628 when using GAS (allows for better link time optimizations). */
8635 remove_useless_addtr_insns (1);
8637 if (pa_cpu < PROCESSOR_8000)
8638 pa_combine_instructions ();
8641 /* This is fairly cheap, so always run it if optimizing. */
8642 if (optimize > 0 && !TARGET_BIG_SWITCH)
8644 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
8645 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8647 rtx pattern, tmp, location, label;
8648 unsigned int length, i;
8650 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
8651 if (GET_CODE (insn) != JUMP_INSN
8652 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8653 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8656 /* Emit marker for the beginning of the branch table. */
8657 emit_insn_before (gen_begin_brtab (), insn);
8659 pattern = PATTERN (insn);
8660 location = PREV_INSN (insn);
8661 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
8663 for (i = 0; i < length; i++)
8665 /* Emit a label before each jump to keep jump.c from
8666 removing this code. */
8667 tmp = gen_label_rtx ();
8668 LABEL_NUSES (tmp) = 1;
8669 emit_label_after (tmp, location);
8670 location = NEXT_INSN (location);
8672 if (GET_CODE (pattern) == ADDR_VEC)
8673 label = XEXP (XVECEXP (pattern, 0, i), 0);
8675 label = XEXP (XVECEXP (pattern, 1, i), 0);
8677 tmp = gen_short_jump (label);
8679 /* Emit the jump itself. */
8680 tmp = emit_jump_insn_after (tmp, location);
8681 JUMP_LABEL (tmp) = label;
8682 LABEL_NUSES (label)++;
8683 location = NEXT_INSN (location);
8685 /* Emit a BARRIER after the jump. */
8686 emit_barrier_after (location);
8687 location = NEXT_INSN (location);
8690 /* Emit marker for the end of the branch table. */
8691 emit_insn_before (gen_end_brtab (), location);
8692 location = NEXT_INSN (location);
8693 emit_barrier_after (location);
8695 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
8701 /* Still need brtab marker insns. FIXME: the presence of these
8702 markers disables output of the branch table to readonly memory,
8703 and any alignment directives that might be needed. Possibly,
8704 the begin_brtab insn should be output before the label for the
8705 table. This doesn't matter at the moment since the tables are
8706 always output in the text section. */
8707 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
8709 /* Find an ADDR_VEC insn. */
8710 if (GET_CODE (insn) != JUMP_INSN
8711 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
8712 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
8715 /* Now generate markers for the beginning and end of the
8717 emit_insn_before (gen_begin_brtab (), insn);
8718 emit_insn_after (gen_end_brtab (), insn);
8723 /* The PA has a number of odd instructions which can perform multiple
8724 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
8725 it may be profitable to combine two instructions into one instruction
8726 with two outputs. It's not profitable PA2.0 machines because the
8727 two outputs would take two slots in the reorder buffers.
8729 This routine finds instructions which can be combined and combines
8730 them. We only support some of the potential combinations, and we
8731 only try common ways to find suitable instructions.
8733 * addb can add two registers or a register and a small integer
8734 and jump to a nearby (+-8k) location. Normally the jump to the
8735 nearby location is conditional on the result of the add, but by
8736 using the "true" condition we can make the jump unconditional.
8737 Thus addb can perform two independent operations in one insn.
8739 * movb is similar to addb in that it can perform a reg->reg
8740 or small immediate->reg copy and jump to a nearby (+-8k location).
8742 * fmpyadd and fmpysub can perform a FP multiply and either an
8743 FP add or FP sub if the operands of the multiply and add/sub are
8744 independent (there are other minor restrictions). Note both
8745 the fmpy and fadd/fsub can in theory move to better spots according
8746 to data dependencies, but for now we require the fmpy stay at a
8749 * Many of the memory operations can perform pre & post updates
8750 of index registers. GCC's pre/post increment/decrement addressing
8751 is far too simple to take advantage of all the possibilities. This
8752 pass may not be suitable since those insns may not be independent.
8754 * comclr can compare two ints or an int and a register, nullify
8755 the following instruction and zero some other register. This
8756 is more difficult to use as it's harder to find an insn which
8757 will generate a comclr than finding something like an unconditional
8758 branch. (conditional moves & long branches create comclr insns).
8760 * Most arithmetic operations can conditionally skip the next
8761 instruction. They can be viewed as "perform this operation
8762 and conditionally jump to this nearby location" (where nearby
8763 is an insns away). These are difficult to use due to the
8764 branch length restrictions. */
8767 pa_combine_instructions (void)
8771 /* This can get expensive since the basic algorithm is on the
8772 order of O(n^2) (or worse). Only do it for -O2 or higher
8773 levels of optimization. */
8777 /* Walk down the list of insns looking for "anchor" insns which
8778 may be combined with "floating" insns. As the name implies,
8779 "anchor" instructions don't move, while "floating" insns may
8781 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
8782 new = make_insn_raw (new);
8784 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
8786 enum attr_pa_combine_type anchor_attr;
8787 enum attr_pa_combine_type floater_attr;
8789 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
8790 Also ignore any special USE insns. */
8791 if ((GET_CODE (anchor) != INSN
8792 && GET_CODE (anchor) != JUMP_INSN
8793 && GET_CODE (anchor) != CALL_INSN)
8794 || GET_CODE (PATTERN (anchor)) == USE
8795 || GET_CODE (PATTERN (anchor)) == CLOBBER
8796 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
8797 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
8800 anchor_attr = get_attr_pa_combine_type (anchor);
8801 /* See if anchor is an insn suitable for combination. */
8802 if (anchor_attr == PA_COMBINE_TYPE_FMPY
8803 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
8804 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8805 && ! forward_branch_p (anchor)))
8809 for (floater = PREV_INSN (anchor);
8811 floater = PREV_INSN (floater))
8813 if (GET_CODE (floater) == NOTE
8814 || (GET_CODE (floater) == INSN
8815 && (GET_CODE (PATTERN (floater)) == USE
8816 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8819 /* Anything except a regular INSN will stop our search. */
8820 if (GET_CODE (floater) != INSN
8821 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8822 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8828 /* See if FLOATER is suitable for combination with the
8830 floater_attr = get_attr_pa_combine_type (floater);
8831 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8832 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8833 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8834 && floater_attr == PA_COMBINE_TYPE_FMPY))
8836 /* If ANCHOR and FLOATER can be combined, then we're
8837 done with this pass. */
8838 if (pa_can_combine_p (new, anchor, floater, 0,
8839 SET_DEST (PATTERN (floater)),
8840 XEXP (SET_SRC (PATTERN (floater)), 0),
8841 XEXP (SET_SRC (PATTERN (floater)), 1)))
8845 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
8846 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
8848 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
8850 if (pa_can_combine_p (new, anchor, floater, 0,
8851 SET_DEST (PATTERN (floater)),
8852 XEXP (SET_SRC (PATTERN (floater)), 0),
8853 XEXP (SET_SRC (PATTERN (floater)), 1)))
8858 if (pa_can_combine_p (new, anchor, floater, 0,
8859 SET_DEST (PATTERN (floater)),
8860 SET_SRC (PATTERN (floater)),
8861 SET_SRC (PATTERN (floater))))
8867 /* If we didn't find anything on the backwards scan try forwards. */
8869 && (anchor_attr == PA_COMBINE_TYPE_FMPY
8870 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
8872 for (floater = anchor; floater; floater = NEXT_INSN (floater))
8874 if (GET_CODE (floater) == NOTE
8875 || (GET_CODE (floater) == INSN
8876 && (GET_CODE (PATTERN (floater)) == USE
8877 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8881 /* Anything except a regular INSN will stop our search. */
8882 if (GET_CODE (floater) != INSN
8883 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8884 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8890 /* See if FLOATER is suitable for combination with the
8892 floater_attr = get_attr_pa_combine_type (floater);
8893 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8894 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8895 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8896 && floater_attr == PA_COMBINE_TYPE_FMPY))
8898 /* If ANCHOR and FLOATER can be combined, then we're
8899 done with this pass. */
8900 if (pa_can_combine_p (new, anchor, floater, 1,
8901 SET_DEST (PATTERN (floater)),
8902 XEXP (SET_SRC (PATTERN (floater)),
8904 XEXP (SET_SRC (PATTERN (floater)),
8911 /* FLOATER will be nonzero if we found a suitable floating
8912 insn for combination with ANCHOR. */
8914 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8915 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8917 /* Emit the new instruction and delete the old anchor. */
8918 emit_insn_before (gen_rtx_PARALLEL
8920 gen_rtvec (2, PATTERN (anchor),
8921 PATTERN (floater))),
8924 PUT_CODE (anchor, NOTE);
8925 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8926 NOTE_SOURCE_FILE (anchor) = 0;
8928 /* Emit a special USE insn for FLOATER, then delete
8929 the floating insn. */
8930 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8931 delete_insn (floater);
8936 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8939 /* Emit the new_jump instruction and delete the old anchor. */
8941 = emit_jump_insn_before (gen_rtx_PARALLEL
8943 gen_rtvec (2, PATTERN (anchor),
8944 PATTERN (floater))),
8947 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8948 PUT_CODE (anchor, NOTE);
8949 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8950 NOTE_SOURCE_FILE (anchor) = 0;
8952 /* Emit a special USE insn for FLOATER, then delete
8953 the floating insn. */
8954 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8955 delete_insn (floater);
8963 pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
8966 int insn_code_number;
8969 /* Create a PARALLEL with the patterns of ANCHOR and
8970 FLOATER, try to recognize it, then test constraints
8971 for the resulting pattern.
8973 If the pattern doesn't match or the constraints
8974 aren't met keep searching for a suitable floater
8976 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8977 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8978 INSN_CODE (new) = -1;
8979 insn_code_number = recog_memoized (new);
8980 if (insn_code_number < 0
8981 || (extract_insn (new), ! constrain_operands (1)))
8995 /* There's up to three operands to consider. One
8996 output and two inputs.
8998 The output must not be used between FLOATER & ANCHOR
8999 exclusive. The inputs must not be set between
9000 FLOATER and ANCHOR exclusive. */
9002 if (reg_used_between_p (dest, start, end))
9005 if (reg_set_between_p (src1, start, end))
9008 if (reg_set_between_p (src2, start, end))
9011 /* If we get here, then everything is good. */
9015 /* Return nonzero if references for INSN are delayed.
9017 Millicode insns are actually function calls with some special
9018 constraints on arguments and register usage.
9020 Millicode calls always expect their arguments in the integer argument
9021 registers, and always return their result in %r29 (ret1). They
9022 are expected to clobber their arguments, %r1, %r29, and the return
9023 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
9025 This function tells reorg that the references to arguments and
9026 millicode calls do not appear to happen until after the millicode call.
9027 This allows reorg to put insns which set the argument registers into the
9028 delay slot of the millicode call -- thus they act more like traditional
9031 Note we cannot consider side effects of the insn to be delayed because
9032 the branch and link insn will clobber the return pointer. If we happened
9033 to use the return pointer in the delay slot of the call, then we lose.
9035 get_attr_type will try to recognize the given insn, so make sure to
9036 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
9039 insn_refs_are_delayed (rtx insn)
9041 return ((GET_CODE (insn) == INSN
9042 && GET_CODE (PATTERN (insn)) != SEQUENCE
9043 && GET_CODE (PATTERN (insn)) != USE
9044 && GET_CODE (PATTERN (insn)) != CLOBBER
9045 && get_attr_type (insn) == TYPE_MILLI));
9048 /* On the HP-PA the value is found in register(s) 28(-29), unless
9049 the mode is SF or DF. Then the value is returned in fr4 (32).
9051 This must perform the same promotions as PROMOTE_MODE, else
9052 TARGET_PROMOTE_FUNCTION_RETURN will not work correctly.
9054 Small structures must be returned in a PARALLEL on PA64 in order
9055 to match the HP Compiler ABI. */
9058 function_value (tree valtype, tree func ATTRIBUTE_UNUSED)
9060 enum machine_mode valmode;
9062 /* Aggregates with a size less than or equal to 128 bits are returned
9063 in GR 28(-29). They are left justified. The pad bits are undefined.
9064 Larger aggregates are returned in memory. */
9065 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
9069 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
9071 for (i = 0; i < ub; i++)
9073 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9074 gen_rtx_REG (DImode, 28 + i),
9079 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
9082 if ((INTEGRAL_TYPE_P (valtype)
9083 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
9084 || POINTER_TYPE_P (valtype))
9085 valmode = word_mode;
9087 valmode = TYPE_MODE (valtype);
9089 if (TREE_CODE (valtype) == REAL_TYPE
9090 && TYPE_MODE (valtype) != TFmode
9091 && !TARGET_SOFT_FLOAT)
9092 return gen_rtx_REG (valmode, 32);
9094 return gen_rtx_REG (valmode, 28);
9097 /* Return the location of a parameter that is passed in a register or NULL
9098 if the parameter has any component that is passed in memory.
9100 This is new code and will be pushed to into the net sources after
9103 ??? We might want to restructure this so that it looks more like other
9106 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode, tree type,
9107 int named ATTRIBUTE_UNUSED)
9109 int max_arg_words = (TARGET_64BIT ? 8 : 4);
9116 if (mode == VOIDmode)
9119 arg_size = FUNCTION_ARG_SIZE (mode, type);
9121 /* If this arg would be passed partially or totally on the stack, then
9122 this routine should return zero. pa_arg_partial_bytes will
9123 handle arguments which are split between regs and stack slots if
9124 the ABI mandates split arguments. */
9127 /* The 32-bit ABI does not split arguments. */
9128 if (cum->words + arg_size > max_arg_words)
9134 alignment = cum->words & 1;
9135 if (cum->words + alignment >= max_arg_words)
9139 /* The 32bit ABIs and the 64bit ABIs are rather different,
9140 particularly in their handling of FP registers. We might
9141 be able to cleverly share code between them, but I'm not
9142 going to bother in the hope that splitting them up results
9143 in code that is more easily understood. */
9147 /* Advance the base registers to their current locations.
9149 Remember, gprs grow towards smaller register numbers while
9150 fprs grow to higher register numbers. Also remember that
9151 although FP regs are 32-bit addressable, we pretend that
9152 the registers are 64-bits wide. */
9153 gpr_reg_base = 26 - cum->words;
9154 fpr_reg_base = 32 + cum->words;
9156 /* Arguments wider than one word and small aggregates need special
9160 || (type && AGGREGATE_TYPE_P (type)))
9162 /* Double-extended precision (80-bit), quad-precision (128-bit)
9163 and aggregates including complex numbers are aligned on
9164 128-bit boundaries. The first eight 64-bit argument slots
9165 are associated one-to-one, with general registers r26
9166 through r19, and also with floating-point registers fr4
9167 through fr11. Arguments larger than one word are always
9168 passed in general registers.
9170 Using a PARALLEL with a word mode register results in left
9171 justified data on a big-endian target. */
9174 int i, offset = 0, ub = arg_size;
9176 /* Align the base register. */
9177 gpr_reg_base -= alignment;
9179 ub = MIN (ub, max_arg_words - cum->words - alignment);
9180 for (i = 0; i < ub; i++)
9182 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
9183 gen_rtx_REG (DImode, gpr_reg_base),
9189 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
9194 /* If the argument is larger than a word, then we know precisely
9195 which registers we must use. */
9209 /* Structures 5 to 8 bytes in size are passed in the general
9210 registers in the same manner as other non floating-point
9211 objects. The data is right-justified and zero-extended
9212 to 64 bits. This is opposite to the normal justification
9213 used on big endian targets and requires special treatment.
9214 We now define BLOCK_REG_PADDING to pad these objects. */
9215 if (mode == BLKmode)
9217 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
9218 gen_rtx_REG (DImode, gpr_reg_base),
9220 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
9225 /* We have a single word (32 bits). A simple computation
9226 will get us the register #s we need. */
9227 gpr_reg_base = 26 - cum->words;
9228 fpr_reg_base = 32 + 2 * cum->words;
9232 /* Determine if the argument needs to be passed in both general and
9233 floating point registers. */
9234 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
9235 /* If we are doing soft-float with portable runtime, then there
9236 is no need to worry about FP regs. */
9237 && !TARGET_SOFT_FLOAT
9238 /* The parameter must be some kind of float, else we can just
9239 pass it in integer registers. */
9240 && FLOAT_MODE_P (mode)
9241 /* The target function must not have a prototype. */
9242 && cum->nargs_prototype <= 0
9243 /* libcalls do not need to pass items in both FP and general
9245 && type != NULL_TREE
9246 /* All this hair applies to "outgoing" args only. This includes
9247 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
9249 /* Also pass outgoing floating arguments in both registers in indirect
9250 calls with the 32 bit ABI and the HP assembler since there is no
9251 way to the specify argument locations in static functions. */
9256 && FLOAT_MODE_P (mode)))
9262 gen_rtx_EXPR_LIST (VOIDmode,
9263 gen_rtx_REG (mode, fpr_reg_base),
9265 gen_rtx_EXPR_LIST (VOIDmode,
9266 gen_rtx_REG (mode, gpr_reg_base),
9271 /* See if we should pass this parameter in a general register. */
9272 if (TARGET_SOFT_FLOAT
9273 /* Indirect calls in the normal 32bit ABI require all arguments
9274 to be passed in general registers. */
9275 || (!TARGET_PORTABLE_RUNTIME
9279 /* If the parameter is not a floating point parameter, then
9280 it belongs in GPRs. */
9281 || !FLOAT_MODE_P (mode))
9282 retval = gen_rtx_REG (mode, gpr_reg_base);
9284 retval = gen_rtx_REG (mode, fpr_reg_base);
9290 /* If this arg would be passed totally in registers or totally on the stack,
9291 then this routine should return zero. */
9294 pa_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
9295 tree type, bool named ATTRIBUTE_UNUSED)
9297 unsigned int max_arg_words = 8;
9298 unsigned int offset = 0;
9303 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
9306 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
9307 /* Arg fits fully into registers. */
9309 else if (cum->words + offset >= max_arg_words)
9310 /* Arg fully on the stack. */
9314 return (max_arg_words - cum->words - offset) * UNITS_PER_WORD;
9318 /* Return 1 if this is a comparison operator. This allows the use of
9319 MATCH_OPERATOR to recognize all the branch insns. */
9322 cmpib_comparison_operator (rtx op, enum machine_mode mode)
9324 return ((mode == VOIDmode || GET_MODE (op) == mode)
9325 && (GET_CODE (op) == EQ
9326 || GET_CODE (op) == NE
9327 || GET_CODE (op) == GT
9328 || GET_CODE (op) == GTU
9329 || GET_CODE (op) == GE
9330 || GET_CODE (op) == LT
9331 || GET_CODE (op) == LE
9332 || GET_CODE (op) == LEU));
9335 /* Return a string to output before text in the current function.
9337 This function is only used with SOM. Because we don't support
9338 named subspaces, we can only create a new subspace or switch back
9339 to the default text subspace. */
9341 som_text_section_asm_op (void)
9348 if (cfun && !cfun->machine->in_nsubspa)
9350 /* We only want to emit a .nsubspa directive once at the
9351 start of the function. */
9352 cfun->machine->in_nsubspa = 1;
9354 /* Create a new subspace for the text. This provides
9355 better stub placement and one-only functions. */
9357 && DECL_ONE_ONLY (cfun->decl)
9358 && !DECL_WEAK (cfun->decl))
9360 "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$,QUAD=0,ALIGN=8,ACCESS=44,SORT=24,COMDAT";
9362 return "\t.SPACE $TEXT$\n\t.NSUBSPA $CODE$";
9366 /* There isn't a current function or the body of the current
9367 function has been completed. So, we are changing to the
9368 text section to output debugging information. Do this in
9369 the default text section. We need to forget that we are
9370 in the text section so that the function text_section in
9371 varasm.c will call us the next time around. */
9376 return "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$";
9379 /* On hpux10, the linker will give an error if we have a reference
9380 in the read-only data section to a symbol defined in a shared
9381 library. Therefore, expressions that might require a reloc can
9382 not be placed in the read-only data section. */
9385 pa_select_section (tree exp, int reloc,
9386 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
9388 if (TREE_CODE (exp) == VAR_DECL
9389 && TREE_READONLY (exp)
9390 && !TREE_THIS_VOLATILE (exp)
9391 && DECL_INITIAL (exp)
9392 && (DECL_INITIAL (exp) == error_mark_node
9393 || TREE_CONSTANT (DECL_INITIAL (exp)))
9397 && DECL_ONE_ONLY (exp)
9398 && !DECL_WEAK (exp))
9399 som_one_only_readonly_data_section ();
9401 readonly_data_section ();
9403 else if (CONSTANT_CLASS_P (exp) && !reloc)
9404 readonly_data_section ();
9406 && TREE_CODE (exp) == VAR_DECL
9407 && DECL_ONE_ONLY (exp)
9408 && !DECL_WEAK (exp))
9409 som_one_only_data_section ();
9415 pa_globalize_label (FILE *stream, const char *name)
9417 /* We only handle DATA objects here, functions are globalized in
9418 ASM_DECLARE_FUNCTION_NAME. */
9419 if (! FUNCTION_NAME_P (name))
9421 fputs ("\t.EXPORT ", stream);
9422 assemble_name (stream, name);
9423 fputs (",DATA\n", stream);
9427 /* Worker function for TARGET_STRUCT_VALUE_RTX. */
9430 pa_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED,
9431 int incoming ATTRIBUTE_UNUSED)
9433 return gen_rtx_REG (Pmode, PA_STRUCT_VALUE_REGNUM);
9436 /* Worker function for TARGET_RETURN_IN_MEMORY. */
9439 pa_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
9441 /* SOM ABI says that objects larger than 64 bits are returned in memory.
9442 PA64 ABI says that objects larger than 128 bits are returned in memory.
9443 Note, int_size_in_bytes can return -1 if the size of the object is
9444 variable or larger than the maximum value that can be expressed as
9445 a HOST_WIDE_INT. It can also return zero for an empty type. The
9446 simplest way to handle variable and empty types is to pass them in
9447 memory. This avoids problems in defining the boundaries of argument
9448 slots, allocating registers, etc. */
9449 return (int_size_in_bytes (type) > (TARGET_64BIT ? 16 : 8)
9450 || int_size_in_bytes (type) <= 0);