1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
31 #include "insn-attr.h"
41 #include "integrate.h"
50 #include "target-def.h"
52 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
54 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
55 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
58 hppa_use_dfa_pipeline_interface ()
63 /* Return nonzero if there is a bypass for the output of
64 OUT_INSN and the fp store IN_INSN. */
66 hppa_fpstore_bypass_p (out_insn, in_insn)
67 rtx out_insn, in_insn;
69 enum machine_mode store_mode;
70 enum machine_mode other_mode;
73 if (recog_memoized (in_insn) < 0
74 || get_attr_type (in_insn) != TYPE_FPSTORE
75 || recog_memoized (out_insn) < 0)
78 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
80 set = single_set (out_insn);
84 other_mode = GET_MODE (SET_SRC (set));
86 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
90 #ifndef DO_FRAME_NOTES
91 #ifdef INCOMING_RETURN_ADDR_RTX
92 #define DO_FRAME_NOTES 1
94 #define DO_FRAME_NOTES 0
98 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
99 static void pa_combine_instructions PARAMS ((rtx));
100 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
101 static int forward_branch_p PARAMS ((rtx));
102 static int shadd_constant_p PARAMS ((int));
103 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
104 static int compute_movstrsi_length PARAMS ((rtx));
105 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
106 static void remove_useless_addtr_insns PARAMS ((rtx, int));
107 static void store_reg PARAMS ((int, int, int));
108 static void store_reg_modify PARAMS ((int, int, int));
109 static void load_reg PARAMS ((int, int, int));
110 static void set_reg_plus_d PARAMS ((int, int, int, int));
111 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
112 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
113 static int pa_adjust_priority PARAMS ((rtx, int));
114 static int pa_issue_rate PARAMS ((void));
115 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
117 static void pa_encode_section_info PARAMS ((tree, int));
118 static const char *pa_strip_name_encoding PARAMS ((const char *));
120 /* Save the operands last given to a compare for use when we
121 generate a scc or bcc insn. */
123 rtx hppa_compare_op0, hppa_compare_op1;
124 enum cmp_type hppa_branch_type;
126 /* Which cpu we are scheduling for. */
127 enum processor_type pa_cpu;
129 /* String to hold which cpu we are scheduling for. */
130 const char *pa_cpu_string;
132 /* Which architecture we are generating code for. */
133 enum architecture_type pa_arch;
135 /* String to hold which architecture we are generating code for. */
136 const char *pa_arch_string;
138 /* Counts for the number of callee-saved general and floating point
139 registers which were saved by the current function's prologue. */
140 static int gr_saved, fr_saved;
142 static rtx find_addr_reg PARAMS ((rtx));
144 /* Keep track of the number of bytes we have output in the CODE subspaces
145 during this compilation so we'll know when to emit inline long-calls. */
147 unsigned int total_code_bytes;
149 /* Variables to handle plabels that we discover are necessary at assembly
150 output time. They are output after the current function. */
152 struct deferred_plabel GTY(())
157 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
159 static size_t n_deferred_plabels = 0;
161 /* Initialize the GCC target structure. */
163 #undef TARGET_ASM_ALIGNED_HI_OP
164 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
165 #undef TARGET_ASM_ALIGNED_SI_OP
166 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
167 #undef TARGET_ASM_ALIGNED_DI_OP
168 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
169 #undef TARGET_ASM_UNALIGNED_HI_OP
170 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
171 #undef TARGET_ASM_UNALIGNED_SI_OP
172 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
173 #undef TARGET_ASM_UNALIGNED_DI_OP
174 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
175 #undef TARGET_ASM_INTEGER
176 #define TARGET_ASM_INTEGER pa_assemble_integer
178 #undef TARGET_ASM_FUNCTION_PROLOGUE
179 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
180 #undef TARGET_ASM_FUNCTION_EPILOGUE
181 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
183 #undef TARGET_SCHED_ADJUST_COST
184 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
185 #undef TARGET_SCHED_ADJUST_PRIORITY
186 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
187 #undef TARGET_SCHED_ISSUE_RATE
188 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
190 #undef TARGET_ENCODE_SECTION_INFO
191 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
192 #undef TARGET_STRIP_NAME_ENCODING
193 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
195 struct gcc_target targetm = TARGET_INITIALIZER;
200 if (pa_cpu_string == NULL)
201 pa_cpu_string = TARGET_SCHED_DEFAULT;
203 if (! strcmp (pa_cpu_string, "8000"))
205 pa_cpu_string = "8000";
206 pa_cpu = PROCESSOR_8000;
208 else if (! strcmp (pa_cpu_string, "7100"))
210 pa_cpu_string = "7100";
211 pa_cpu = PROCESSOR_7100;
213 else if (! strcmp (pa_cpu_string, "700"))
215 pa_cpu_string = "700";
216 pa_cpu = PROCESSOR_700;
218 else if (! strcmp (pa_cpu_string, "7100LC"))
220 pa_cpu_string = "7100LC";
221 pa_cpu = PROCESSOR_7100LC;
223 else if (! strcmp (pa_cpu_string, "7200"))
225 pa_cpu_string = "7200";
226 pa_cpu = PROCESSOR_7200;
228 else if (! strcmp (pa_cpu_string, "7300"))
230 pa_cpu_string = "7300";
231 pa_cpu = PROCESSOR_7300;
235 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
238 /* Set the instruction set architecture. */
239 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
241 pa_arch_string = "1.0";
242 pa_arch = ARCHITECTURE_10;
243 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
245 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
247 pa_arch_string = "1.1";
248 pa_arch = ARCHITECTURE_11;
249 target_flags &= ~MASK_PA_20;
250 target_flags |= MASK_PA_11;
252 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
254 pa_arch_string = "2.0";
255 pa_arch = ARCHITECTURE_20;
256 target_flags |= MASK_PA_11 | MASK_PA_20;
258 else if (pa_arch_string)
260 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
263 /* Unconditional branches in the delay slot are not compatible with dwarf2
264 call frame information. There is no benefit in using this optimization
265 on PA8000 and later processors. */
266 if (pa_cpu >= PROCESSOR_8000
267 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
268 || flag_unwind_tables)
269 target_flags &= ~MASK_JUMP_IN_DELAY;
271 if (flag_pic && TARGET_PORTABLE_RUNTIME)
273 warning ("PIC code generation is not supported in the portable runtime model\n");
276 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
278 warning ("PIC code generation is not compatible with fast indirect calls\n");
281 if (! TARGET_GAS && write_symbols != NO_DEBUG)
283 warning ("-g is only supported when using GAS on this processor,");
284 warning ("-g option disabled");
285 write_symbols = NO_DEBUG;
288 /* We only support the "big PIC" model now. And we always generate PIC
289 code when in 64bit mode. */
290 if (flag_pic == 1 || TARGET_64BIT)
293 /* We can't guarantee that .dword is available for 32-bit targets. */
294 if (UNITS_PER_WORD == 4)
295 targetm.asm_out.aligned_op.di = NULL;
297 /* The unaligned ops are only available when using GAS. */
300 targetm.asm_out.unaligned_op.hi = NULL;
301 targetm.asm_out.unaligned_op.si = NULL;
302 targetm.asm_out.unaligned_op.di = NULL;
306 /* Return non-zero only if OP is a register of mode MODE,
309 reg_or_0_operand (op, mode)
311 enum machine_mode mode;
313 return (op == CONST0_RTX (mode) || register_operand (op, mode));
316 /* Return non-zero if OP is suitable for use in a call to a named
319 For 2.5 try to eliminate either call_operand_address or
320 function_label_operand, they perform very similar functions. */
322 call_operand_address (op, mode)
324 enum machine_mode mode ATTRIBUTE_UNUSED;
326 return (GET_MODE (op) == word_mode
327 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
330 /* Return 1 if X contains a symbolic expression. We know these
331 expressions will have one of a few well defined forms, so
332 we need only check those forms. */
334 symbolic_expression_p (x)
338 /* Strip off any HIGH. */
339 if (GET_CODE (x) == HIGH)
342 return (symbolic_operand (x, VOIDmode));
346 symbolic_operand (op, mode)
348 enum machine_mode mode ATTRIBUTE_UNUSED;
350 switch (GET_CODE (op))
357 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
358 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
359 && GET_CODE (XEXP (op, 1)) == CONST_INT);
365 /* Return truth value of statement that OP is a symbolic memory
366 operand of mode MODE. */
369 symbolic_memory_operand (op, mode)
371 enum machine_mode mode ATTRIBUTE_UNUSED;
373 if (GET_CODE (op) == SUBREG)
374 op = SUBREG_REG (op);
375 if (GET_CODE (op) != MEM)
378 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
379 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
382 /* Return 1 if the operand is either a register or a memory operand that is
386 reg_or_nonsymb_mem_operand (op, mode)
388 enum machine_mode mode;
390 if (register_operand (op, mode))
393 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
399 /* Return 1 if the operand is either a register, zero, or a memory operand
400 that is not symbolic. */
403 reg_or_0_or_nonsymb_mem_operand (op, mode)
405 enum machine_mode mode;
407 if (register_operand (op, mode))
410 if (op == CONST0_RTX (mode))
413 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
419 /* Return 1 if the operand is a register operand or a non-symbolic memory
420 operand after reload. This predicate is used for branch patterns that
421 internally handle register reloading. We need to accept non-symbolic
422 memory operands after reload to ensure that the pattern is still valid
423 if reload didn't find a hard register for the operand. */
426 reg_before_reload_operand (op, mode)
428 enum machine_mode mode;
430 /* Don't accept a SUBREG since it will need a reload. */
431 if (GET_CODE (op) == SUBREG)
434 if (register_operand (op, mode))
438 && memory_operand (op, mode)
439 && ! symbolic_memory_operand (op, mode))
445 /* Accept any constant that can be moved in one instruction into a
448 cint_ok_for_move (intval)
449 HOST_WIDE_INT intval;
451 /* OK if ldo, ldil, or zdepi, can be used. */
452 return (CONST_OK_FOR_LETTER_P (intval, 'J')
453 || CONST_OK_FOR_LETTER_P (intval, 'N')
454 || CONST_OK_FOR_LETTER_P (intval, 'K'));
457 /* Accept anything that can be moved in one instruction into a general
460 move_operand (op, mode)
462 enum machine_mode mode;
464 if (register_operand (op, mode))
467 if (GET_CODE (op) == CONSTANT_P_RTX)
470 if (GET_CODE (op) == CONST_INT)
471 return cint_ok_for_move (INTVAL (op));
473 if (GET_CODE (op) == SUBREG)
474 op = SUBREG_REG (op);
475 if (GET_CODE (op) != MEM)
480 /* We consider a LO_SUM DLT reference a move_operand now since it has
481 been merged into the normal movsi/movdi patterns. */
482 if (GET_CODE (op) == LO_SUM
483 && GET_CODE (XEXP (op, 0)) == REG
484 && REG_OK_FOR_BASE_P (XEXP (op, 0))
485 && GET_CODE (XEXP (op, 1)) == UNSPEC
486 && GET_MODE (op) == Pmode)
489 /* Since move_operand is only used for source operands, we can always
490 allow scaled indexing! */
491 if (! TARGET_DISABLE_INDEXING
492 && GET_CODE (op) == PLUS
493 && ((GET_CODE (XEXP (op, 0)) == MULT
494 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
495 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
496 && INTVAL (XEXP (XEXP (op, 0), 1))
497 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
498 && GET_CODE (XEXP (op, 1)) == REG)
499 || (GET_CODE (XEXP (op, 1)) == MULT
500 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
501 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
502 && INTVAL (XEXP (XEXP (op, 1), 1))
503 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
504 && GET_CODE (XEXP (op, 0)) == REG)))
507 return memory_address_p (mode, op);
510 /* Accept REG and any CONST_INT that can be moved in one instruction into a
513 reg_or_cint_move_operand (op, mode)
515 enum machine_mode mode;
517 if (register_operand (op, mode))
520 if (GET_CODE (op) == CONST_INT)
521 return cint_ok_for_move (INTVAL (op));
527 pic_label_operand (op, mode)
529 enum machine_mode mode ATTRIBUTE_UNUSED;
534 switch (GET_CODE (op))
540 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
541 && GET_CODE (XEXP (op, 1)) == CONST_INT);
548 fp_reg_operand (op, mode)
550 enum machine_mode mode ATTRIBUTE_UNUSED;
552 return reg_renumber && FP_REG_P (op);
557 /* Return truth value of whether OP can be used as an operand in a
558 three operand arithmetic insn that accepts registers of mode MODE
559 or 14-bit signed integers. */
561 arith_operand (op, mode)
563 enum machine_mode mode;
565 return (register_operand (op, mode)
566 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
569 /* Return truth value of whether OP can be used as an operand in a
570 three operand arithmetic insn that accepts registers of mode MODE
571 or 11-bit signed integers. */
573 arith11_operand (op, mode)
575 enum machine_mode mode;
577 return (register_operand (op, mode)
578 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
581 /* Return truth value of whether OP can be used as an operand in a
584 adddi3_operand (op, mode)
586 enum machine_mode mode;
588 return (register_operand (op, mode)
589 || (GET_CODE (op) == CONST_INT
590 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
593 /* A constant integer suitable for use in a PRE_MODIFY memory
596 pre_cint_operand (op, mode)
598 enum machine_mode mode ATTRIBUTE_UNUSED;
600 return (GET_CODE (op) == CONST_INT
601 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
604 /* A constant integer suitable for use in a POST_MODIFY memory
607 post_cint_operand (op, mode)
609 enum machine_mode mode ATTRIBUTE_UNUSED;
611 return (GET_CODE (op) == CONST_INT
612 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
616 arith_double_operand (op, mode)
618 enum machine_mode mode;
620 return (register_operand (op, mode)
621 || (GET_CODE (op) == CONST_DOUBLE
622 && GET_MODE (op) == mode
623 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
624 && ((CONST_DOUBLE_HIGH (op) >= 0)
625 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
628 /* Return truth value of whether OP is an integer which fits the
629 range constraining immediate operands in three-address insns, or
630 is an integer register. */
633 ireg_or_int5_operand (op, mode)
635 enum machine_mode mode ATTRIBUTE_UNUSED;
637 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
638 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
641 /* Return nonzero if OP is an integer register, else return zero. */
643 ireg_operand (op, mode)
645 enum machine_mode mode ATTRIBUTE_UNUSED;
647 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
650 /* Return truth value of whether OP is an integer which fits the
651 range constraining immediate operands in three-address insns. */
654 int5_operand (op, mode)
656 enum machine_mode mode ATTRIBUTE_UNUSED;
658 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
662 uint5_operand (op, mode)
664 enum machine_mode mode ATTRIBUTE_UNUSED;
666 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
670 int11_operand (op, mode)
672 enum machine_mode mode ATTRIBUTE_UNUSED;
674 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
678 uint32_operand (op, mode)
680 enum machine_mode mode ATTRIBUTE_UNUSED;
682 #if HOST_BITS_PER_WIDE_INT > 32
683 /* All allowed constants will fit a CONST_INT. */
684 return (GET_CODE (op) == CONST_INT
685 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
687 return (GET_CODE (op) == CONST_INT
688 || (GET_CODE (op) == CONST_DOUBLE
689 && CONST_DOUBLE_HIGH (op) == 0));
694 arith5_operand (op, mode)
696 enum machine_mode mode;
698 return register_operand (op, mode) || int5_operand (op, mode);
701 /* True iff zdepi can be used to generate this CONST_INT.
702 zdepi first sign extends a 5 bit signed number to a given field
703 length, then places this field anywhere in a zero. */
706 unsigned HOST_WIDE_INT x;
708 unsigned HOST_WIDE_INT lsb_mask, t;
710 /* This might not be obvious, but it's at least fast.
711 This function is critical; we don't have the time loops would take. */
713 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
714 /* Return true iff t is a power of two. */
715 return ((t & (t - 1)) == 0);
718 /* True iff depi or extru can be used to compute (reg & mask).
719 Accept bit pattern like these:
725 unsigned HOST_WIDE_INT mask;
728 mask += mask & -mask;
729 return (mask & (mask - 1)) == 0;
732 /* True iff depi or extru can be used to compute (reg & OP). */
734 and_operand (op, mode)
736 enum machine_mode mode;
738 return (register_operand (op, mode)
739 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
742 /* True iff depi can be used to compute (reg | MASK). */
745 unsigned HOST_WIDE_INT mask;
747 mask += mask & -mask;
748 return (mask & (mask - 1)) == 0;
751 /* True iff depi can be used to compute (reg | OP). */
753 ior_operand (op, mode)
755 enum machine_mode mode ATTRIBUTE_UNUSED;
757 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
761 lhs_lshift_operand (op, mode)
763 enum machine_mode mode;
765 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
768 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
769 Such values can be the left hand side x in (x << r), using the zvdepi
772 lhs_lshift_cint_operand (op, mode)
774 enum machine_mode mode ATTRIBUTE_UNUSED;
776 unsigned HOST_WIDE_INT x;
777 if (GET_CODE (op) != CONST_INT)
779 x = INTVAL (op) >> 4;
780 return (x & (x + 1)) == 0;
784 arith32_operand (op, mode)
786 enum machine_mode mode;
788 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
792 pc_or_label_operand (op, mode)
794 enum machine_mode mode ATTRIBUTE_UNUSED;
796 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
799 /* Legitimize PIC addresses. If the address is already
800 position-independent, we return ORIG. Newly generated
801 position-independent addresses go to REG. If we need more
802 than one register, we lose. */
805 legitimize_pic_address (orig, mode, reg)
807 enum machine_mode mode;
811 /* Labels need special handling. */
812 if (pic_label_operand (orig, mode))
814 /* We do not want to go through the movXX expanders here since that
815 would create recursion.
817 Nor do we really want to call a generator for a named pattern
818 since that requires multiple patterns if we want to support
821 So instead we just emit the raw set, which avoids the movXX
822 expanders completely. */
823 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
824 current_function_uses_pic_offset_table = 1;
827 if (GET_CODE (orig) == SYMBOL_REF)
833 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
834 gen_rtx_HIGH (word_mode, orig)));
836 = gen_rtx_MEM (Pmode,
837 gen_rtx_LO_SUM (Pmode, reg,
838 gen_rtx_UNSPEC (Pmode,
842 current_function_uses_pic_offset_table = 1;
843 RTX_UNCHANGING_P (pic_ref) = 1;
844 emit_move_insn (reg, pic_ref);
847 else if (GET_CODE (orig) == CONST)
851 if (GET_CODE (XEXP (orig, 0)) == PLUS
852 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
858 if (GET_CODE (XEXP (orig, 0)) == PLUS)
860 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
861 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
862 base == reg ? 0 : reg);
865 if (GET_CODE (orig) == CONST_INT)
867 if (INT_14_BITS (orig))
868 return plus_constant (base, INTVAL (orig));
869 orig = force_reg (Pmode, orig);
871 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
872 /* Likewise, should we set special REG_NOTEs here? */
877 /* Try machine-dependent ways of modifying an illegitimate address
878 to be legitimate. If we find one, return the new, valid address.
879 This macro is used in only one place: `memory_address' in explow.c.
881 OLDX is the address as it was before break_out_memory_refs was called.
882 In some cases it is useful to look at this to decide what needs to be done.
884 MODE and WIN are passed so that this macro can use
885 GO_IF_LEGITIMATE_ADDRESS.
887 It is always safe for this macro to do nothing. It exists to recognize
888 opportunities to optimize the output.
890 For the PA, transform:
892 memory(X + <large int>)
896 if (<large int> & mask) >= 16
897 Y = (<large int> & ~mask) + mask + 1 Round up.
899 Y = (<large int> & ~mask) Round down.
901 memory (Z + (<large int> - Y));
903 This is for CSE to find several similar references, and only use one Z.
905 X can either be a SYMBOL_REF or REG, but because combine can not
906 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
907 D will not fit in 14 bits.
909 MODE_FLOAT references allow displacements which fit in 5 bits, so use
912 MODE_INT references allow displacements which fit in 14 bits, so use
915 This relies on the fact that most mode MODE_FLOAT references will use FP
916 registers and most mode MODE_INT references will use integer registers.
917 (In the rare case of an FP register used in an integer MODE, we depend
918 on secondary reloads to clean things up.)
921 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
922 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
923 addressing modes to be used).
925 Put X and Z into registers. Then put the entire expression into
929 hppa_legitimize_address (x, oldx, mode)
930 rtx x, oldx ATTRIBUTE_UNUSED;
931 enum machine_mode mode;
936 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
938 /* Strip off CONST. */
939 if (GET_CODE (x) == CONST)
942 /* Special case. Get the SYMBOL_REF into a register and use indexing.
943 That should always be safe. */
944 if (GET_CODE (x) == PLUS
945 && GET_CODE (XEXP (x, 0)) == REG
946 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
948 rtx reg = force_reg (Pmode, XEXP (x, 1));
949 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
952 /* Note we must reject symbols which represent function addresses
953 since the assembler/linker can't handle arithmetic on plabels. */
954 if (GET_CODE (x) == PLUS
955 && GET_CODE (XEXP (x, 1)) == CONST_INT
956 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
957 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
958 || GET_CODE (XEXP (x, 0)) == REG))
960 rtx int_part, ptr_reg;
962 int offset = INTVAL (XEXP (x, 1));
965 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
966 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
968 /* Choose which way to round the offset. Round up if we
969 are >= halfway to the next boundary. */
970 if ((offset & mask) >= ((mask + 1) / 2))
971 newoffset = (offset & ~ mask) + mask + 1;
973 newoffset = (offset & ~ mask);
975 /* If the newoffset will not fit in 14 bits (ldo), then
976 handling this would take 4 or 5 instructions (2 to load
977 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
978 add the new offset and the SYMBOL_REF.) Combine can
979 not handle 4->2 or 5->2 combinations, so do not create
981 if (! VAL_14_BITS_P (newoffset)
982 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
984 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
987 gen_rtx_HIGH (Pmode, const_part));
990 gen_rtx_LO_SUM (Pmode,
991 tmp_reg, const_part));
995 if (! VAL_14_BITS_P (newoffset))
996 int_part = force_reg (Pmode, GEN_INT (newoffset));
998 int_part = GEN_INT (newoffset);
1000 ptr_reg = force_reg (Pmode,
1001 gen_rtx_PLUS (Pmode,
1002 force_reg (Pmode, XEXP (x, 0)),
1005 return plus_constant (ptr_reg, offset - newoffset);
1008 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1010 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1011 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1012 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1013 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1014 || GET_CODE (XEXP (x, 1)) == SUBREG)
1015 && GET_CODE (XEXP (x, 1)) != CONST)
1017 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1021 if (GET_CODE (reg1) != REG)
1022 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1024 reg2 = XEXP (XEXP (x, 0), 0);
1025 if (GET_CODE (reg2) != REG)
1026 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1028 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1029 gen_rtx_MULT (Pmode,
1035 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1037 Only do so for floating point modes since this is more speculative
1038 and we lose if it's an integer store. */
1039 if (GET_CODE (x) == PLUS
1040 && GET_CODE (XEXP (x, 0)) == PLUS
1041 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1042 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1043 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1044 && (mode == SFmode || mode == DFmode))
1047 /* First, try and figure out what to use as a base register. */
1048 rtx reg1, reg2, base, idx, orig_base;
1050 reg1 = XEXP (XEXP (x, 0), 1);
1055 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1056 then emit_move_sequence will turn on REG_POINTER so we'll know
1057 it's a base register below. */
1058 if (GET_CODE (reg1) != REG)
1059 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1061 if (GET_CODE (reg2) != REG)
1062 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1064 /* Figure out what the base and index are. */
1066 if (GET_CODE (reg1) == REG
1067 && REG_POINTER (reg1))
1070 orig_base = XEXP (XEXP (x, 0), 1);
1071 idx = gen_rtx_PLUS (Pmode,
1072 gen_rtx_MULT (Pmode,
1073 XEXP (XEXP (XEXP (x, 0), 0), 0),
1074 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1077 else if (GET_CODE (reg2) == REG
1078 && REG_POINTER (reg2))
1081 orig_base = XEXP (x, 1);
1088 /* If the index adds a large constant, try to scale the
1089 constant so that it can be loaded with only one insn. */
1090 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1091 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1092 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1093 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1095 /* Divide the CONST_INT by the scale factor, then add it to A. */
1096 int val = INTVAL (XEXP (idx, 1));
1098 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1099 reg1 = XEXP (XEXP (idx, 0), 0);
1100 if (GET_CODE (reg1) != REG)
1101 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1103 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1105 /* We can now generate a simple scaled indexed address. */
1108 (Pmode, gen_rtx_PLUS (Pmode,
1109 gen_rtx_MULT (Pmode, reg1,
1110 XEXP (XEXP (idx, 0), 1)),
1114 /* If B + C is still a valid base register, then add them. */
1115 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1116 && INTVAL (XEXP (idx, 1)) <= 4096
1117 && INTVAL (XEXP (idx, 1)) >= -4096)
1119 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1122 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1124 reg2 = XEXP (XEXP (idx, 0), 0);
1125 if (GET_CODE (reg2) != CONST_INT)
1126 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1128 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1129 gen_rtx_MULT (Pmode,
1135 /* Get the index into a register, then add the base + index and
1136 return a register holding the result. */
1138 /* First get A into a register. */
1139 reg1 = XEXP (XEXP (idx, 0), 0);
1140 if (GET_CODE (reg1) != REG)
1141 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1143 /* And get B into a register. */
1144 reg2 = XEXP (idx, 1);
1145 if (GET_CODE (reg2) != REG)
1146 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1148 reg1 = force_reg (Pmode,
1149 gen_rtx_PLUS (Pmode,
1150 gen_rtx_MULT (Pmode, reg1,
1151 XEXP (XEXP (idx, 0), 1)),
1154 /* Add the result to our base register and return. */
1155 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1159 /* Uh-oh. We might have an address for x[n-100000]. This needs
1160 special handling to avoid creating an indexed memory address
1161 with x-100000 as the base.
1163 If the constant part is small enough, then it's still safe because
1164 there is a guard page at the beginning and end of the data segment.
1166 Scaled references are common enough that we want to try and rearrange the
1167 terms so that we can use indexing for these addresses too. Only
1168 do the optimization for floatint point modes. */
1170 if (GET_CODE (x) == PLUS
1171 && symbolic_expression_p (XEXP (x, 1)))
1173 /* Ugly. We modify things here so that the address offset specified
1174 by the index expression is computed first, then added to x to form
1175 the entire address. */
1177 rtx regx1, regx2, regy1, regy2, y;
1179 /* Strip off any CONST. */
1181 if (GET_CODE (y) == CONST)
1184 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1186 /* See if this looks like
1187 (plus (mult (reg) (shadd_const))
1188 (const (plus (symbol_ref) (const_int))))
1190 Where const_int is small. In that case the const
1191 expression is a valid pointer for indexing.
1193 If const_int is big, but can be divided evenly by shadd_const
1194 and added to (reg). This allows more scaled indexed addresses. */
1195 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1196 && GET_CODE (XEXP (x, 0)) == MULT
1197 && GET_CODE (XEXP (y, 1)) == CONST_INT
1198 && INTVAL (XEXP (y, 1)) >= -4096
1199 && INTVAL (XEXP (y, 1)) <= 4095
1200 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1201 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1203 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1207 if (GET_CODE (reg1) != REG)
1208 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1210 reg2 = XEXP (XEXP (x, 0), 0);
1211 if (GET_CODE (reg2) != REG)
1212 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1214 return force_reg (Pmode,
1215 gen_rtx_PLUS (Pmode,
1216 gen_rtx_MULT (Pmode,
1221 else if ((mode == DFmode || mode == SFmode)
1222 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1223 && GET_CODE (XEXP (x, 0)) == MULT
1224 && GET_CODE (XEXP (y, 1)) == CONST_INT
1225 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1226 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1227 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1230 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1231 / INTVAL (XEXP (XEXP (x, 0), 1))));
1232 regx2 = XEXP (XEXP (x, 0), 0);
1233 if (GET_CODE (regx2) != REG)
1234 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1235 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1239 gen_rtx_PLUS (Pmode,
1240 gen_rtx_MULT (Pmode, regx2,
1241 XEXP (XEXP (x, 0), 1)),
1242 force_reg (Pmode, XEXP (y, 0))));
1244 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1245 && INTVAL (XEXP (y, 1)) >= -4096
1246 && INTVAL (XEXP (y, 1)) <= 4095)
1248 /* This is safe because of the guard page at the
1249 beginning and end of the data space. Just
1250 return the original address. */
1255 /* Doesn't look like one we can optimize. */
1256 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1257 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1258 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1259 regx1 = force_reg (Pmode,
1260 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1262 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1270 /* For the HPPA, REG and REG+CONST is cost 0
1271 and addresses involving symbolic constants are cost 2.
1273 PIC addresses are very expensive.
1275 It is no coincidence that this has the same structure
1276 as GO_IF_LEGITIMATE_ADDRESS. */
1278 hppa_address_cost (X)
1281 if (GET_CODE (X) == PLUS)
1283 else if (GET_CODE (X) == LO_SUM)
1285 else if (GET_CODE (X) == HIGH)
1290 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1291 new rtx with the correct mode. */
1293 force_mode (mode, orig)
1294 enum machine_mode mode;
1297 if (mode == GET_MODE (orig))
1300 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1303 return gen_rtx_REG (mode, REGNO (orig));
1306 /* Emit insns to move operands[1] into operands[0].
1308 Return 1 if we have written out everything that needs to be done to
1309 do the move. Otherwise, return 0 and the caller will emit the move
1312 Note SCRATCH_REG may not be in the proper mode depending on how it
1313 will be used. This routine is resposible for creating a new copy
1314 of SCRATCH_REG in the proper mode. */
1317 emit_move_sequence (operands, mode, scratch_reg)
1319 enum machine_mode mode;
1322 register rtx operand0 = operands[0];
1323 register rtx operand1 = operands[1];
1327 && reload_in_progress && GET_CODE (operand0) == REG
1328 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1329 operand0 = reg_equiv_mem[REGNO (operand0)];
1330 else if (scratch_reg
1331 && reload_in_progress && GET_CODE (operand0) == SUBREG
1332 && GET_CODE (SUBREG_REG (operand0)) == REG
1333 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1335 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1336 the code which tracks sets/uses for delete_output_reload. */
1337 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1338 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1339 SUBREG_BYTE (operand0));
1340 operand0 = alter_subreg (&temp);
1344 && reload_in_progress && GET_CODE (operand1) == REG
1345 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1346 operand1 = reg_equiv_mem[REGNO (operand1)];
1347 else if (scratch_reg
1348 && reload_in_progress && GET_CODE (operand1) == SUBREG
1349 && GET_CODE (SUBREG_REG (operand1)) == REG
1350 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1352 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1353 the code which tracks sets/uses for delete_output_reload. */
1354 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1355 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1356 SUBREG_BYTE (operand1));
1357 operand1 = alter_subreg (&temp);
1360 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1361 && ((tem = find_replacement (&XEXP (operand0, 0)))
1362 != XEXP (operand0, 0)))
1363 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1364 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1365 && ((tem = find_replacement (&XEXP (operand1, 0)))
1366 != XEXP (operand1, 0)))
1367 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1369 /* Handle secondary reloads for loads/stores of FP registers from
1370 REG+D addresses where D does not fit in 5 bits, including
1371 (subreg (mem (addr))) cases. */
1372 if (fp_reg_operand (operand0, mode)
1373 && ((GET_CODE (operand1) == MEM
1374 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1375 || ((GET_CODE (operand1) == SUBREG
1376 && GET_CODE (XEXP (operand1, 0)) == MEM
1377 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1380 if (GET_CODE (operand1) == SUBREG)
1381 operand1 = XEXP (operand1, 0);
1383 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1384 it in WORD_MODE regardless of what mode it was originally given
1386 scratch_reg = force_mode (word_mode, scratch_reg);
1388 /* D might not fit in 14 bits either; for such cases load D into
1390 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1392 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1393 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1395 XEXP (XEXP (operand1, 0), 0),
1399 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1400 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1401 gen_rtx_MEM (mode, scratch_reg)));
1404 else if (fp_reg_operand (operand1, mode)
1405 && ((GET_CODE (operand0) == MEM
1406 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1407 || ((GET_CODE (operand0) == SUBREG)
1408 && GET_CODE (XEXP (operand0, 0)) == MEM
1409 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1412 if (GET_CODE (operand0) == SUBREG)
1413 operand0 = XEXP (operand0, 0);
1415 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1416 it in WORD_MODE regardless of what mode it was originally given
1418 scratch_reg = force_mode (word_mode, scratch_reg);
1420 /* D might not fit in 14 bits either; for such cases load D into
1422 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1424 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1425 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1428 XEXP (XEXP (operand0, 0),
1433 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1434 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1438 /* Handle secondary reloads for loads of FP registers from constant
1439 expressions by forcing the constant into memory.
1441 use scratch_reg to hold the address of the memory location.
1443 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1444 NO_REGS when presented with a const_int and an register class
1445 containing only FP registers. Doing so unfortunately creates
1446 more problems than it solves. Fix this for 2.5. */
1447 else if (fp_reg_operand (operand0, mode)
1448 && CONSTANT_P (operand1)
1453 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1454 it in WORD_MODE regardless of what mode it was originally given
1456 scratch_reg = force_mode (word_mode, scratch_reg);
1458 /* Force the constant into memory and put the address of the
1459 memory location into scratch_reg. */
1460 xoperands[0] = scratch_reg;
1461 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1462 emit_move_sequence (xoperands, Pmode, 0);
1464 /* Now load the destination register. */
1465 emit_insn (gen_rtx_SET (mode, operand0,
1466 gen_rtx_MEM (mode, scratch_reg)));
1469 /* Handle secondary reloads for SAR. These occur when trying to load
1470 the SAR from memory, FP register, or with a constant. */
1471 else if (GET_CODE (operand0) == REG
1472 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1473 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1474 && (GET_CODE (operand1) == MEM
1475 || GET_CODE (operand1) == CONST_INT
1476 || (GET_CODE (operand1) == REG
1477 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1480 /* D might not fit in 14 bits either; for such cases load D into
1482 if (GET_CODE (operand1) == MEM
1483 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1485 /* We are reloading the address into the scratch register, so we
1486 want to make sure the scratch register is a full register. */
1487 scratch_reg = force_mode (word_mode, scratch_reg);
1489 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1490 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1493 XEXP (XEXP (operand1, 0),
1497 /* Now we are going to load the scratch register from memory,
1498 we want to load it in the same width as the original MEM,
1499 which must be the same as the width of the ultimate destination,
1501 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1503 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1508 /* We want to load the scratch register using the same mode as
1509 the ultimate destination. */
1510 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1512 emit_move_insn (scratch_reg, operand1);
1515 /* And emit the insn to set the ultimate destination. We know that
1516 the scratch register has the same mode as the destination at this
1518 emit_move_insn (operand0, scratch_reg);
1521 /* Handle most common case: storing into a register. */
1522 else if (register_operand (operand0, mode))
1524 if (register_operand (operand1, mode)
1525 || (GET_CODE (operand1) == CONST_INT
1526 && cint_ok_for_move (INTVAL (operand1)))
1527 || (operand1 == CONST0_RTX (mode))
1528 || (GET_CODE (operand1) == HIGH
1529 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1530 /* Only `general_operands' can come here, so MEM is ok. */
1531 || GET_CODE (operand1) == MEM)
1533 /* Run this case quickly. */
1534 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1538 else if (GET_CODE (operand0) == MEM)
1540 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1541 && !(reload_in_progress || reload_completed))
1543 rtx temp = gen_reg_rtx (DFmode);
1545 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1546 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1549 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1551 /* Run this case quickly. */
1552 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1555 if (! (reload_in_progress || reload_completed))
1557 operands[0] = validize_mem (operand0);
1558 operands[1] = operand1 = force_reg (mode, operand1);
1562 /* Simplify the source if we need to.
1563 Note we do have to handle function labels here, even though we do
1564 not consider them legitimate constants. Loop optimizations can
1565 call the emit_move_xxx with one as a source. */
1566 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1567 || function_label_operand (operand1, mode)
1568 || (GET_CODE (operand1) == HIGH
1569 && symbolic_operand (XEXP (operand1, 0), mode)))
1573 if (GET_CODE (operand1) == HIGH)
1576 operand1 = XEXP (operand1, 0);
1578 if (symbolic_operand (operand1, mode))
1580 /* Argh. The assembler and linker can't handle arithmetic
1583 So we force the plabel into memory, load operand0 from
1584 the memory location, then add in the constant part. */
1585 if ((GET_CODE (operand1) == CONST
1586 && GET_CODE (XEXP (operand1, 0)) == PLUS
1587 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1588 || function_label_operand (operand1, mode))
1590 rtx temp, const_part;
1592 /* Figure out what (if any) scratch register to use. */
1593 if (reload_in_progress || reload_completed)
1595 scratch_reg = scratch_reg ? scratch_reg : operand0;
1596 /* SCRATCH_REG will hold an address and maybe the actual
1597 data. We want it in WORD_MODE regardless of what mode it
1598 was originally given to us. */
1599 scratch_reg = force_mode (word_mode, scratch_reg);
1602 scratch_reg = gen_reg_rtx (Pmode);
1604 if (GET_CODE (operand1) == CONST)
1606 /* Save away the constant part of the expression. */
1607 const_part = XEXP (XEXP (operand1, 0), 1);
1608 if (GET_CODE (const_part) != CONST_INT)
1611 /* Force the function label into memory. */
1612 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1616 /* No constant part. */
1617 const_part = NULL_RTX;
1619 /* Force the function label into memory. */
1620 temp = force_const_mem (mode, operand1);
1624 /* Get the address of the memory location. PIC-ify it if
1626 temp = XEXP (temp, 0);
1628 temp = legitimize_pic_address (temp, mode, scratch_reg);
1630 /* Put the address of the memory location into our destination
1633 emit_move_sequence (operands, mode, scratch_reg);
1635 /* Now load from the memory location into our destination
1637 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1638 emit_move_sequence (operands, mode, scratch_reg);
1640 /* And add back in the constant part. */
1641 if (const_part != NULL_RTX)
1642 expand_inc (operand0, const_part);
1651 if (reload_in_progress || reload_completed)
1653 temp = scratch_reg ? scratch_reg : operand0;
1654 /* TEMP will hold an address and maybe the actual
1655 data. We want it in WORD_MODE regardless of what mode it
1656 was originally given to us. */
1657 temp = force_mode (word_mode, temp);
1660 temp = gen_reg_rtx (Pmode);
1662 /* (const (plus (symbol) (const_int))) must be forced to
1663 memory during/after reload if the const_int will not fit
1665 if (GET_CODE (operand1) == CONST
1666 && GET_CODE (XEXP (operand1, 0)) == PLUS
1667 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1668 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1669 && (reload_completed || reload_in_progress)
1672 operands[1] = force_const_mem (mode, operand1);
1673 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1675 emit_move_sequence (operands, mode, temp);
1679 operands[1] = legitimize_pic_address (operand1, mode, temp);
1680 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1683 /* On the HPPA, references to data space are supposed to use dp,
1684 register 27, but showing it in the RTL inhibits various cse
1685 and loop optimizations. */
1690 if (reload_in_progress || reload_completed)
1692 temp = scratch_reg ? scratch_reg : operand0;
1693 /* TEMP will hold an address and maybe the actual
1694 data. We want it in WORD_MODE regardless of what mode it
1695 was originally given to us. */
1696 temp = force_mode (word_mode, temp);
1699 temp = gen_reg_rtx (mode);
1701 /* Loading a SYMBOL_REF into a register makes that register
1702 safe to be used as the base in an indexed address.
1704 Don't mark hard registers though. That loses. */
1705 if (GET_CODE (operand0) == REG
1706 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1707 REG_POINTER (operand0) = 1;
1708 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1709 REG_POINTER (temp) = 1;
1711 set = gen_rtx_SET (mode, operand0, temp);
1713 set = gen_rtx_SET (VOIDmode,
1715 gen_rtx_LO_SUM (mode, temp, operand1));
1717 emit_insn (gen_rtx_SET (VOIDmode,
1719 gen_rtx_HIGH (mode, operand1)));
1725 else if (GET_CODE (operand1) != CONST_INT
1726 || ! cint_ok_for_move (INTVAL (operand1)))
1728 rtx extend = NULL_RTX;
1731 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1732 && HOST_BITS_PER_WIDE_INT > 32
1733 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1735 HOST_WIDE_INT val = INTVAL (operand1);
1738 /* Extract the low order 32 bits of the value and sign extend.
1739 If the new value is the same as the original value, we can
1740 can use the original value as-is. If the new value is
1741 different, we use it and insert the most-significant 32-bits
1742 of the original value into the final result. */
1743 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1744 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1747 #if HOST_BITS_PER_WIDE_INT > 32
1748 extend = GEN_INT (val >> 32);
1750 operand1 = GEN_INT (nval);
1754 if (reload_in_progress || reload_completed)
1757 temp = gen_reg_rtx (mode);
1759 /* We don't directly split DImode constants on 32-bit targets
1760 because PLUS uses an 11-bit immediate and the insn sequence
1761 generated is not as efficient as the one using HIGH/LO_SUM. */
1762 if (GET_CODE (operand1) == CONST_INT
1763 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1765 /* Directly break constant into high and low parts. This
1766 provides better optimization opportunities because various
1767 passes recognize constants split with PLUS but not LO_SUM.
1768 We use a 14-bit signed low part except when the addition
1769 of 0x4000 to the high part might change the sign of the
1771 HOST_WIDE_INT value = INTVAL (operand1);
1772 HOST_WIDE_INT low = value & 0x3fff;
1773 HOST_WIDE_INT high = value & ~ 0x3fff;
1777 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1785 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1786 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1790 emit_insn (gen_rtx_SET (VOIDmode, temp,
1791 gen_rtx_HIGH (mode, operand1)));
1792 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1795 emit_move_insn (operands[0], operands[1]);
1797 if (extend != NULL_RTX)
1798 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1804 /* Now have insn-emit do whatever it normally does. */
1808 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1809 it will need a link/runtime reloc). */
1817 switch (TREE_CODE (exp))
1824 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1825 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1830 case NON_LVALUE_EXPR:
1831 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1837 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1838 if (TREE_VALUE (link) != 0)
1839 reloc |= reloc_needed (TREE_VALUE (link));
1852 /* Does operand (which is a symbolic_operand) live in text space?
1853 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1857 read_only_operand (operand, mode)
1859 enum machine_mode mode ATTRIBUTE_UNUSED;
1861 if (GET_CODE (operand) == CONST)
1862 operand = XEXP (XEXP (operand, 0), 0);
1865 if (GET_CODE (operand) == SYMBOL_REF)
1866 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
1870 if (GET_CODE (operand) == SYMBOL_REF)
1871 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
1877 /* Return the best assembler insn template
1878 for moving operands[1] into operands[0] as a fullword. */
1880 singlemove_string (operands)
1883 HOST_WIDE_INT intval;
1885 if (GET_CODE (operands[0]) == MEM)
1886 return "stw %r1,%0";
1887 if (GET_CODE (operands[1]) == MEM)
1889 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1894 if (GET_MODE (operands[1]) != SFmode)
1897 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
1899 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
1900 REAL_VALUE_TO_TARGET_SINGLE (d, i);
1902 operands[1] = GEN_INT (i);
1903 /* Fall through to CONST_INT case. */
1905 if (GET_CODE (operands[1]) == CONST_INT)
1907 intval = INTVAL (operands[1]);
1909 if (VAL_14_BITS_P (intval))
1911 else if ((intval & 0x7ff) == 0)
1912 return "ldil L'%1,%0";
1913 else if (zdepi_cint_p (intval))
1914 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
1916 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
1918 return "copy %1,%0";
1922 /* Compute position (in OP[1]) and width (in OP[2])
1923 useful for copying IMM to a register using the zdepi
1924 instructions. Store the immediate value to insert in OP[0]. */
1926 compute_zdepwi_operands (imm, op)
1927 unsigned HOST_WIDE_INT imm;
1932 /* Find the least significant set bit in IMM. */
1933 for (lsb = 0; lsb < 32; lsb++)
1940 /* Choose variants based on *sign* of the 5-bit field. */
1941 if ((imm & 0x10) == 0)
1942 len = (lsb <= 28) ? 4 : 32 - lsb;
1945 /* Find the width of the bitstring in IMM. */
1946 for (len = 5; len < 32; len++)
1948 if ((imm & (1 << len)) == 0)
1952 /* Sign extend IMM as a 5-bit value. */
1953 imm = (imm & 0xf) - 0x10;
1961 /* Compute position (in OP[1]) and width (in OP[2])
1962 useful for copying IMM to a register using the depdi,z
1963 instructions. Store the immediate value to insert in OP[0]. */
1965 compute_zdepdi_operands (imm, op)
1966 unsigned HOST_WIDE_INT imm;
1969 HOST_WIDE_INT lsb, len;
1971 /* Find the least significant set bit in IMM. */
1972 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
1979 /* Choose variants based on *sign* of the 5-bit field. */
1980 if ((imm & 0x10) == 0)
1981 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
1982 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
1985 /* Find the width of the bitstring in IMM. */
1986 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
1988 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
1992 /* Sign extend IMM as a 5-bit value. */
1993 imm = (imm & 0xf) - 0x10;
2001 /* Output assembler code to perform a doubleword move insn
2002 with operands OPERANDS. */
2005 output_move_double (operands)
2008 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2010 rtx addreg0 = 0, addreg1 = 0;
2012 /* First classify both operands. */
2014 if (REG_P (operands[0]))
2016 else if (offsettable_memref_p (operands[0]))
2018 else if (GET_CODE (operands[0]) == MEM)
2023 if (REG_P (operands[1]))
2025 else if (CONSTANT_P (operands[1]))
2027 else if (offsettable_memref_p (operands[1]))
2029 else if (GET_CODE (operands[1]) == MEM)
2034 /* Check for the cases that the operand constraints are not
2035 supposed to allow to happen. Abort if we get one,
2036 because generating code for these cases is painful. */
2038 if (optype0 != REGOP && optype1 != REGOP)
2041 /* Handle auto decrementing and incrementing loads and stores
2042 specifically, since the structure of the function doesn't work
2043 for them without major modification. Do it better when we learn
2044 this port about the general inc/dec addressing of PA.
2045 (This was written by tege. Chide him if it doesn't work.) */
2047 if (optype0 == MEMOP)
2049 /* We have to output the address syntax ourselves, since print_operand
2050 doesn't deal with the addresses we want to use. Fix this later. */
2052 rtx addr = XEXP (operands[0], 0);
2053 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2055 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2057 operands[0] = XEXP (addr, 0);
2058 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2061 if (!reg_overlap_mentioned_p (high_reg, addr))
2063 /* No overlap between high target register and address
2064 register. (We do this in a non-obvious way to
2065 save a register file writeback) */
2066 if (GET_CODE (addr) == POST_INC)
2067 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2068 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2073 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2075 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2077 operands[0] = XEXP (addr, 0);
2078 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2081 if (!reg_overlap_mentioned_p (high_reg, addr))
2083 /* No overlap between high target register and address
2084 register. (We do this in a non-obvious way to
2085 save a register file writeback) */
2086 if (GET_CODE (addr) == PRE_INC)
2087 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2088 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2094 if (optype1 == MEMOP)
2096 /* We have to output the address syntax ourselves, since print_operand
2097 doesn't deal with the addresses we want to use. Fix this later. */
2099 rtx addr = XEXP (operands[1], 0);
2100 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2102 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2104 operands[1] = XEXP (addr, 0);
2105 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2108 if (!reg_overlap_mentioned_p (high_reg, addr))
2110 /* No overlap between high target register and address
2111 register. (We do this in a non-obvious way to
2112 save a register file writeback) */
2113 if (GET_CODE (addr) == POST_INC)
2114 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2115 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2119 /* This is an undefined situation. We should load into the
2120 address register *and* update that register. Probably
2121 we don't need to handle this at all. */
2122 if (GET_CODE (addr) == POST_INC)
2123 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2124 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2127 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2129 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2131 operands[1] = XEXP (addr, 0);
2132 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2135 if (!reg_overlap_mentioned_p (high_reg, addr))
2137 /* No overlap between high target register and address
2138 register. (We do this in a non-obvious way to
2139 save a register file writeback) */
2140 if (GET_CODE (addr) == PRE_INC)
2141 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2142 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2146 /* This is an undefined situation. We should load into the
2147 address register *and* update that register. Probably
2148 we don't need to handle this at all. */
2149 if (GET_CODE (addr) == PRE_INC)
2150 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2151 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2154 else if (GET_CODE (addr) == PLUS
2155 && GET_CODE (XEXP (addr, 0)) == MULT)
2157 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2159 if (!reg_overlap_mentioned_p (high_reg, addr))
2163 xoperands[0] = high_reg;
2164 xoperands[1] = XEXP (addr, 1);
2165 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2166 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2167 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2169 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2175 xoperands[0] = high_reg;
2176 xoperands[1] = XEXP (addr, 1);
2177 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2178 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2179 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2181 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2186 /* If an operand is an unoffsettable memory ref, find a register
2187 we can increment temporarily to make it refer to the second word. */
2189 if (optype0 == MEMOP)
2190 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2192 if (optype1 == MEMOP)
2193 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2195 /* Ok, we can do one word at a time.
2196 Normally we do the low-numbered word first.
2198 In either case, set up in LATEHALF the operands to use
2199 for the high-numbered word and in some cases alter the
2200 operands in OPERANDS to be suitable for the low-numbered word. */
2202 if (optype0 == REGOP)
2203 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2204 else if (optype0 == OFFSOP)
2205 latehalf[0] = adjust_address (operands[0], SImode, 4);
2207 latehalf[0] = operands[0];
2209 if (optype1 == REGOP)
2210 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2211 else if (optype1 == OFFSOP)
2212 latehalf[1] = adjust_address (operands[1], SImode, 4);
2213 else if (optype1 == CNSTOP)
2214 split_double (operands[1], &operands[1], &latehalf[1]);
2216 latehalf[1] = operands[1];
2218 /* If the first move would clobber the source of the second one,
2219 do them in the other order.
2221 This can happen in two cases:
2223 mem -> register where the first half of the destination register
2224 is the same register used in the memory's address. Reload
2225 can create such insns.
2227 mem in this case will be either register indirect or register
2228 indirect plus a valid offset.
2230 register -> register move where REGNO(dst) == REGNO(src + 1)
2231 someone (Tim/Tege?) claimed this can happen for parameter loads.
2233 Handle mem -> register case first. */
2234 if (optype0 == REGOP
2235 && (optype1 == MEMOP || optype1 == OFFSOP)
2236 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2239 /* Do the late half first. */
2241 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2242 output_asm_insn (singlemove_string (latehalf), latehalf);
2246 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2247 return singlemove_string (operands);
2250 /* Now handle register -> register case. */
2251 if (optype0 == REGOP && optype1 == REGOP
2252 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2254 output_asm_insn (singlemove_string (latehalf), latehalf);
2255 return singlemove_string (operands);
2258 /* Normal case: do the two words, low-numbered first. */
2260 output_asm_insn (singlemove_string (operands), operands);
2262 /* Make any unoffsettable addresses point at high-numbered word. */
2264 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2266 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2269 output_asm_insn (singlemove_string (latehalf), latehalf);
2271 /* Undo the adds we just did. */
2273 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2275 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2281 output_fp_move_double (operands)
2284 if (FP_REG_P (operands[0]))
2286 if (FP_REG_P (operands[1])
2287 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2288 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2290 output_asm_insn ("fldd%F1 %1,%0", operands);
2292 else if (FP_REG_P (operands[1]))
2294 output_asm_insn ("fstd%F0 %1,%0", operands);
2296 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2298 if (GET_CODE (operands[0]) == REG)
2301 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2302 xoperands[0] = operands[0];
2303 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2305 /* This is a pain. You have to be prepared to deal with an
2306 arbitrary address here including pre/post increment/decrement.
2308 so avoid this in the MD. */
2316 /* Return a REG that occurs in ADDR with coefficient 1.
2317 ADDR can be effectively incremented by incrementing REG. */
2320 find_addr_reg (addr)
2323 while (GET_CODE (addr) == PLUS)
2325 if (GET_CODE (XEXP (addr, 0)) == REG)
2326 addr = XEXP (addr, 0);
2327 else if (GET_CODE (XEXP (addr, 1)) == REG)
2328 addr = XEXP (addr, 1);
2329 else if (CONSTANT_P (XEXP (addr, 0)))
2330 addr = XEXP (addr, 1);
2331 else if (CONSTANT_P (XEXP (addr, 1)))
2332 addr = XEXP (addr, 0);
2336 if (GET_CODE (addr) == REG)
2341 /* Emit code to perform a block move.
2343 OPERANDS[0] is the destination pointer as a REG, clobbered.
2344 OPERANDS[1] is the source pointer as a REG, clobbered.
2345 OPERANDS[2] is a register for temporary storage.
2346 OPERANDS[4] is the size as a CONST_INT
2347 OPERANDS[3] is a register for temporary storage.
2348 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2349 OPERANDS[6] is another temporary register. */
2352 output_block_move (operands, size_is_constant)
2354 int size_is_constant ATTRIBUTE_UNUSED;
2356 int align = INTVAL (operands[5]);
2357 unsigned long n_bytes = INTVAL (operands[4]);
2359 /* We can't move more than four bytes at a time because the PA
2360 has no longer integer move insns. (Could use fp mem ops?) */
2364 /* Note that we know each loop below will execute at least twice
2365 (else we would have open-coded the copy). */
2369 /* Pre-adjust the loop counter. */
2370 operands[4] = GEN_INT (n_bytes - 8);
2371 output_asm_insn ("ldi %4,%2", operands);
2374 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2375 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2376 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2377 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2378 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2380 /* Handle the residual. There could be up to 7 bytes of
2381 residual to copy! */
2382 if (n_bytes % 8 != 0)
2384 operands[4] = GEN_INT (n_bytes % 4);
2385 if (n_bytes % 8 >= 4)
2386 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2387 if (n_bytes % 4 != 0)
2388 output_asm_insn ("ldw 0(%1),%6", operands);
2389 if (n_bytes % 8 >= 4)
2390 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2391 if (n_bytes % 4 != 0)
2392 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2397 /* Pre-adjust the loop counter. */
2398 operands[4] = GEN_INT (n_bytes - 4);
2399 output_asm_insn ("ldi %4,%2", operands);
2402 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2403 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2404 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2405 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2406 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2408 /* Handle the residual. */
2409 if (n_bytes % 4 != 0)
2411 if (n_bytes % 4 >= 2)
2412 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2413 if (n_bytes % 2 != 0)
2414 output_asm_insn ("ldb 0(%1),%6", operands);
2415 if (n_bytes % 4 >= 2)
2416 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2417 if (n_bytes % 2 != 0)
2418 output_asm_insn ("stb %6,0(%0)", operands);
2423 /* Pre-adjust the loop counter. */
2424 operands[4] = GEN_INT (n_bytes - 2);
2425 output_asm_insn ("ldi %4,%2", operands);
2428 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2429 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2430 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2431 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2432 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2434 /* Handle the residual. */
2435 if (n_bytes % 2 != 0)
2437 output_asm_insn ("ldb 0(%1),%3", operands);
2438 output_asm_insn ("stb %3,0(%0)", operands);
2447 /* Count the number of insns necessary to handle this block move.
2449 Basic structure is the same as emit_block_move, except that we
2450 count insns rather than emit them. */
2453 compute_movstrsi_length (insn)
2456 rtx pat = PATTERN (insn);
2457 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2458 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2459 unsigned int n_insns = 0;
2461 /* We can't move more than four bytes at a time because the PA
2462 has no longer integer move insns. (Could use fp mem ops?) */
2466 /* The basic copying loop. */
2470 if (n_bytes % (2 * align) != 0)
2472 if ((n_bytes % (2 * align)) >= align)
2475 if ((n_bytes % align) != 0)
2479 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2485 output_and (operands)
2488 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2490 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2491 int ls0, ls1, ms0, p, len;
2493 for (ls0 = 0; ls0 < 32; ls0++)
2494 if ((mask & (1 << ls0)) == 0)
2497 for (ls1 = ls0; ls1 < 32; ls1++)
2498 if ((mask & (1 << ls1)) != 0)
2501 for (ms0 = ls1; ms0 < 32; ms0++)
2502 if ((mask & (1 << ms0)) == 0)
2515 operands[2] = GEN_INT (len);
2516 return "{extru|extrw,u} %1,31,%2,%0";
2520 /* We could use this `depi' for the case above as well, but `depi'
2521 requires one more register file access than an `extru'. */
2526 operands[2] = GEN_INT (p);
2527 operands[3] = GEN_INT (len);
2528 return "{depi|depwi} 0,%2,%3,%0";
2532 return "and %1,%2,%0";
2535 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2536 storing the result in operands[0]. */
2538 output_64bit_and (operands)
2541 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2543 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2544 int ls0, ls1, ms0, p, len;
2546 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2547 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2550 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2551 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2554 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2555 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2558 if (ms0 != HOST_BITS_PER_WIDE_INT)
2561 if (ls1 == HOST_BITS_PER_WIDE_INT)
2568 operands[2] = GEN_INT (len);
2569 return "extrd,u %1,63,%2,%0";
2573 /* We could use this `depi' for the case above as well, but `depi'
2574 requires one more register file access than an `extru'. */
2579 operands[2] = GEN_INT (p);
2580 operands[3] = GEN_INT (len);
2581 return "depdi 0,%2,%3,%0";
2585 return "and %1,%2,%0";
2589 output_ior (operands)
2592 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2593 int bs0, bs1, p, len;
2595 if (INTVAL (operands[2]) == 0)
2596 return "copy %1,%0";
2598 for (bs0 = 0; bs0 < 32; bs0++)
2599 if ((mask & (1 << bs0)) != 0)
2602 for (bs1 = bs0; bs1 < 32; bs1++)
2603 if ((mask & (1 << bs1)) == 0)
2606 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2612 operands[2] = GEN_INT (p);
2613 operands[3] = GEN_INT (len);
2614 return "{depi|depwi} -1,%2,%3,%0";
2617 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2618 storing the result in operands[0]. */
2620 output_64bit_ior (operands)
2623 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2624 int bs0, bs1, p, len;
2626 if (INTVAL (operands[2]) == 0)
2627 return "copy %1,%0";
2629 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2630 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2633 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2634 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2637 if (bs1 != HOST_BITS_PER_WIDE_INT
2638 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2644 operands[2] = GEN_INT (p);
2645 operands[3] = GEN_INT (len);
2646 return "depdi -1,%2,%3,%0";
2649 /* Target hook for assembling integer objects. This code handles
2650 aligned SI and DI integers specially, since function references must
2651 be preceded by P%. */
2654 pa_assemble_integer (x, size, aligned_p)
2659 if (size == UNITS_PER_WORD && aligned_p
2660 && function_label_operand (x, VOIDmode))
2662 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2663 output_addr_const (asm_out_file, x);
2664 fputc ('\n', asm_out_file);
2667 return default_assemble_integer (x, size, aligned_p);
2670 /* Output an ascii string. */
2672 output_ascii (file, p, size)
2679 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2681 /* The HP assembler can only take strings of 256 characters at one
2682 time. This is a limitation on input line length, *not* the
2683 length of the string. Sigh. Even worse, it seems that the
2684 restriction is in number of input characters (see \xnn &
2685 \whatever). So we have to do this very carefully. */
2687 fputs ("\t.STRING \"", file);
2690 for (i = 0; i < size; i += 4)
2694 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2696 register unsigned int c = (unsigned char) p[i + io];
2698 if (c == '\"' || c == '\\')
2699 partial_output[co++] = '\\';
2700 if (c >= ' ' && c < 0177)
2701 partial_output[co++] = c;
2705 partial_output[co++] = '\\';
2706 partial_output[co++] = 'x';
2707 hexd = c / 16 - 0 + '0';
2709 hexd -= '9' - 'a' + 1;
2710 partial_output[co++] = hexd;
2711 hexd = c % 16 - 0 + '0';
2713 hexd -= '9' - 'a' + 1;
2714 partial_output[co++] = hexd;
2717 if (chars_output + co > 243)
2719 fputs ("\"\n\t.STRING \"", file);
2722 fwrite (partial_output, 1, (size_t) co, file);
2726 fputs ("\"\n", file);
2729 /* Try to rewrite floating point comparisons & branches to avoid
2730 useless add,tr insns.
2732 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2733 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2734 first attempt to remove useless add,tr insns. It is zero
2735 for the second pass as reorg sometimes leaves bogus REG_DEAD
2738 When CHECK_NOTES is zero we can only eliminate add,tr insns
2739 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2742 remove_useless_addtr_insns (insns, check_notes)
2747 static int pass = 0;
2749 /* This is fairly cheap, so always run it when optimizing. */
2753 int fbranch_count = 0;
2755 /* Walk all the insns in this function looking for fcmp & fbranch
2756 instructions. Keep track of how many of each we find. */
2757 insns = get_insns ();
2758 for (insn = insns; insn; insn = next_insn (insn))
2762 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2763 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2766 tmp = PATTERN (insn);
2768 /* It must be a set. */
2769 if (GET_CODE (tmp) != SET)
2772 /* If the destination is CCFP, then we've found an fcmp insn. */
2773 tmp = SET_DEST (tmp);
2774 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2780 tmp = PATTERN (insn);
2781 /* If this is an fbranch instruction, bump the fbranch counter. */
2782 if (GET_CODE (tmp) == SET
2783 && SET_DEST (tmp) == pc_rtx
2784 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2785 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2786 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2787 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2795 /* Find all floating point compare + branch insns. If possible,
2796 reverse the comparison & the branch to avoid add,tr insns. */
2797 for (insn = insns; insn; insn = next_insn (insn))
2801 /* Ignore anything that isn't an INSN. */
2802 if (GET_CODE (insn) != INSN)
2805 tmp = PATTERN (insn);
2807 /* It must be a set. */
2808 if (GET_CODE (tmp) != SET)
2811 /* The destination must be CCFP, which is register zero. */
2812 tmp = SET_DEST (tmp);
2813 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2816 /* INSN should be a set of CCFP.
2818 See if the result of this insn is used in a reversed FP
2819 conditional branch. If so, reverse our condition and
2820 the branch. Doing so avoids useless add,tr insns. */
2821 next = next_insn (insn);
2824 /* Jumps, calls and labels stop our search. */
2825 if (GET_CODE (next) == JUMP_INSN
2826 || GET_CODE (next) == CALL_INSN
2827 || GET_CODE (next) == CODE_LABEL)
2830 /* As does another fcmp insn. */
2831 if (GET_CODE (next) == INSN
2832 && GET_CODE (PATTERN (next)) == SET
2833 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2834 && REGNO (SET_DEST (PATTERN (next))) == 0)
2837 next = next_insn (next);
2840 /* Is NEXT_INSN a branch? */
2842 && GET_CODE (next) == JUMP_INSN)
2844 rtx pattern = PATTERN (next);
2846 /* If it a reversed fp conditional branch (eg uses add,tr)
2847 and CCFP dies, then reverse our conditional and the branch
2848 to avoid the add,tr. */
2849 if (GET_CODE (pattern) == SET
2850 && SET_DEST (pattern) == pc_rtx
2851 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2852 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2853 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2854 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2855 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2856 && (fcmp_count == fbranch_count
2858 && find_regno_note (next, REG_DEAD, 0))))
2860 /* Reverse the branch. */
2861 tmp = XEXP (SET_SRC (pattern), 1);
2862 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
2863 XEXP (SET_SRC (pattern), 2) = tmp;
2864 INSN_CODE (next) = -1;
2866 /* Reverse our condition. */
2867 tmp = PATTERN (insn);
2868 PUT_CODE (XEXP (tmp, 1),
2869 (reverse_condition_maybe_unordered
2870 (GET_CODE (XEXP (tmp, 1)))));
2880 /* You may have trouble believing this, but this is the 32 bit HP-PA
2885 Variable arguments (optional; any number may be allocated)
2887 SP-(4*(N+9)) arg word N
2892 Fixed arguments (must be allocated; may remain unused)
2901 SP-32 External Data Pointer (DP)
2903 SP-24 External/stub RP (RP')
2907 SP-8 Calling Stub RP (RP'')
2912 SP-0 Stack Pointer (points to next available address)
2916 /* This function saves registers as follows. Registers marked with ' are
2917 this function's registers (as opposed to the previous function's).
2918 If a frame_pointer isn't needed, r4 is saved as a general register;
2919 the space for the frame pointer is still allocated, though, to keep
2925 SP (FP') Previous FP
2926 SP + 4 Alignment filler (sigh)
2927 SP + 8 Space for locals reserved here.
2931 SP + n All call saved register used.
2935 SP + o All call saved fp registers used.
2939 SP + p (SP') points to next available address.
2943 /* Global variables set by output_function_prologue(). */
2944 /* Size of frame. Need to know this to emit return insns from
2946 static int actual_fsize;
2947 static int local_fsize, save_fregs;
2949 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
2950 Handle case where DISP > 8k by using the add_high_const patterns.
2952 Note in DISP > 8k case, we will leave the high part of the address
2953 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
2956 store_reg (reg, disp, base)
2957 int reg, disp, base;
2959 rtx insn, dest, src, basereg;
2961 src = gen_rtx_REG (word_mode, reg);
2962 basereg = gen_rtx_REG (Pmode, base);
2963 if (VAL_14_BITS_P (disp))
2965 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
2966 insn = emit_move_insn (dest, src);
2970 rtx delta = GEN_INT (disp);
2971 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
2972 rtx tmpreg = gen_rtx_REG (Pmode, 1);
2973 emit_move_insn (tmpreg, high);
2974 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
2975 insn = emit_move_insn (dest, src);
2979 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
2980 gen_rtx_SET (VOIDmode,
2981 gen_rtx_MEM (word_mode,
2982 gen_rtx_PLUS (word_mode, basereg,
2990 RTX_FRAME_RELATED_P (insn) = 1;
2993 /* Emit RTL to store REG at the memory location specified by BASE and then
2994 add MOD to BASE. MOD must be <= 8k. */
2997 store_reg_modify (base, reg, mod)
3000 rtx insn, basereg, srcreg, delta;
3002 if (! VAL_14_BITS_P (mod))
3005 basereg = gen_rtx_REG (Pmode, base);
3006 srcreg = gen_rtx_REG (word_mode, reg);
3007 delta = GEN_INT (mod);
3009 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3012 RTX_FRAME_RELATED_P (insn) = 1;
3014 /* RTX_FRAME_RELATED_P must be set on each frame related set
3015 in a parallel with more than one element. Don't set
3016 RTX_FRAME_RELATED_P in the first set if reg is temporary
3017 register 1. The effect of this operation is recorded in
3018 the initial copy. */
3021 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3022 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3026 /* The first element of a PARALLEL is always processed if it is
3027 a SET. Thus, we need an expression list for this case. */
3029 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3030 gen_rtx_SET (VOIDmode, basereg,
3031 gen_rtx_PLUS (word_mode, basereg, delta)),
3037 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3038 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3039 whether to add a frame note or not.
3041 In the DISP > 8k case, we leave the high part of the address in %r1.
3042 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3045 set_reg_plus_d (reg, base, disp, note)
3046 int reg, base, disp, note;
3050 if (VAL_14_BITS_P (disp))
3052 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3053 plus_constant (gen_rtx_REG (Pmode, base), disp));
3057 rtx basereg = gen_rtx_REG (Pmode, base);
3058 rtx delta = GEN_INT (disp);
3060 emit_move_insn (gen_rtx_REG (Pmode, 1),
3061 gen_rtx_PLUS (Pmode, basereg,
3062 gen_rtx_HIGH (Pmode, delta)));
3063 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3064 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3068 if (DO_FRAME_NOTES && note)
3069 RTX_FRAME_RELATED_P (insn) = 1;
3073 compute_frame_size (size, fregs_live)
3079 /* Space for frame pointer + filler. If any frame is allocated
3080 we need to add this in because of STARTING_FRAME_OFFSET.
3082 Similar code also appears in hppa_expand_prologue. Change both
3083 of them at the same time. */
3084 fsize = size + (size || frame_pointer_needed ? STARTING_FRAME_OFFSET : 0);
3086 /* If the current function calls __builtin_eh_return, then we need
3087 to allocate stack space for registers that will hold data for
3088 the exception handler. */
3089 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3093 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3095 fsize += i * UNITS_PER_WORD;
3098 /* Account for space used by the callee general register saves. */
3099 for (i = 18; i >= 3; i--)
3100 if (regs_ever_live[i])
3101 fsize += UNITS_PER_WORD;
3103 /* Round the stack. */
3104 fsize = (fsize + 7) & ~7;
3106 /* Account for space used by the callee floating point register saves. */
3107 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3108 if (regs_ever_live[i]
3109 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3114 /* We always save both halves of the FP register, so always
3115 increment the frame size by 8 bytes. */
3119 /* The various ABIs include space for the outgoing parameters in the
3120 size of the current function's stack frame. */
3121 fsize += current_function_outgoing_args_size;
3123 /* Allocate space for the fixed frame marker. This space must be
3124 allocated for any function that makes calls or otherwise allocates
3126 if (!current_function_is_leaf || fsize)
3127 fsize += TARGET_64BIT ? 16 : 32;
3129 return (fsize + STACK_BOUNDARY - 1) & ~(STACK_BOUNDARY - 1);
3132 /* Generate the assembly code for function entry. FILE is a stdio
3133 stream to output the code to. SIZE is an int: how many units of
3134 temporary storage to allocate.
3136 Refer to the array `regs_ever_live' to determine which registers to
3137 save; `regs_ever_live[I]' is nonzero if register number I is ever
3138 used in the function. This function is responsible for knowing
3139 which registers should not be saved even if used. */
3141 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3142 of memory. If any fpu reg is used in the function, we allocate
3143 such a block here, at the bottom of the frame, just in case it's needed.
3145 If this function is a leaf procedure, then we may choose not
3146 to do a "save" insn. The decision about whether or not
3147 to do this is made in regclass.c. */
3150 pa_output_function_prologue (file, size)
3152 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3154 /* The function's label and associated .PROC must never be
3155 separated and must be output *after* any profiling declarations
3156 to avoid changing spaces/subspaces within a procedure. */
3157 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3158 fputs ("\t.PROC\n", file);
3160 /* hppa_expand_prologue does the dirty work now. We just need
3161 to output the assembler directives which denote the start
3163 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3164 if (regs_ever_live[2])
3165 fputs (",CALLS,SAVE_RP", file);
3167 fputs (",NO_CALLS", file);
3169 if (frame_pointer_needed)
3170 fputs (",SAVE_SP", file);
3172 /* Pass on information about the number of callee register saves
3173 performed in the prologue.
3175 The compiler is supposed to pass the highest register number
3176 saved, the assembler then has to adjust that number before
3177 entering it into the unwind descriptor (to account for any
3178 caller saved registers with lower register numbers than the
3179 first callee saved register). */
3181 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3184 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3186 fputs ("\n\t.ENTRY\n", file);
3188 /* If we're using GAS and SOM, and not using the portable runtime model,
3189 then we don't need to accumulate the total number of code bytes. */
3190 if ((TARGET_GAS && TARGET_SOM && ! TARGET_PORTABLE_RUNTIME)
3191 /* FIXME: we can't handle long calls for TARGET_64BIT. */
3193 total_code_bytes = 0;
3194 else if (INSN_ADDRESSES_SET_P ())
3196 unsigned int old_total = total_code_bytes;
3198 total_code_bytes += INSN_ADDRESSES (INSN_UID (get_last_nonnote_insn ()));
3199 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3201 /* Be prepared to handle overflows. */
3202 if (old_total > total_code_bytes)
3203 total_code_bytes = -1;
3206 total_code_bytes = -1;
3208 remove_useless_addtr_insns (get_insns (), 0);
3212 hppa_expand_prologue ()
3214 int size = get_frame_size ();
3215 int merge_sp_adjust_with_store = 0;
3223 /* Allocate space for frame pointer + filler. If any frame is allocated
3224 we need to add this in because of STARTING_FRAME_OFFSET.
3226 Similar code also appears in compute_frame_size. Change both
3227 of them at the same time. */
3228 local_fsize = size + (size || frame_pointer_needed
3229 ? STARTING_FRAME_OFFSET : 0);
3231 actual_fsize = compute_frame_size (size, &save_fregs);
3233 /* Compute a few things we will use often. */
3234 tmpreg = gen_rtx_REG (word_mode, 1);
3236 /* Save RP first. The calling conventions manual states RP will
3237 always be stored into the caller's frame at sp - 20 or sp - 16
3238 depending on which ABI is in use. */
3239 if (regs_ever_live[2] || current_function_calls_eh_return)
3240 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3242 /* Allocate the local frame and set up the frame pointer if needed. */
3243 if (actual_fsize != 0)
3245 if (frame_pointer_needed)
3247 /* Copy the old frame pointer temporarily into %r1. Set up the
3248 new stack pointer, then store away the saved old frame pointer
3249 into the stack at sp and at the same time update the stack
3250 pointer by actual_fsize bytes. Two versions, first
3251 handles small (<8k) frames. The second handles large (>=8k)
3253 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3256 /* We need to record the frame pointer save here since the
3257 new frame pointer is set in the following insn. */
3258 RTX_FRAME_RELATED_P (insn) = 1;
3260 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3261 gen_rtx_SET (VOIDmode,
3262 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3267 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3269 RTX_FRAME_RELATED_P (insn) = 1;
3271 if (VAL_14_BITS_P (actual_fsize))
3272 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3275 /* It is incorrect to store the saved frame pointer at *sp,
3276 then increment sp (writes beyond the current stack boundary).
3278 So instead use stwm to store at *sp and post-increment the
3279 stack pointer as an atomic operation. Then increment sp to
3280 finish allocating the new frame. */
3281 int adjust1 = 8192 - 64;
3282 int adjust2 = actual_fsize - adjust1;
3284 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3285 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3289 /* Prevent register spills from being scheduled before the
3290 stack pointer is raised. Necessary as we will be storing
3291 registers using the frame pointer as a base register, and
3292 we happen to set fp before raising sp. */
3293 emit_insn (gen_blockage ());
3295 /* no frame pointer needed. */
3298 /* In some cases we can perform the first callee register save
3299 and allocating the stack frame at the same time. If so, just
3300 make a note of it and defer allocating the frame until saving
3301 the callee registers. */
3302 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3303 merge_sp_adjust_with_store = 1;
3304 /* Can not optimize. Adjust the stack frame by actual_fsize
3307 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3312 /* Normal register save.
3314 Do not save the frame pointer in the frame_pointer_needed case. It
3315 was done earlier. */
3316 if (frame_pointer_needed)
3318 offset = local_fsize;
3320 /* Saving the EH return data registers in the frame is the simplest
3321 way to get the frame unwind information emitted. We put them
3322 just before the general registers. */
3323 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3325 unsigned int i, regno;
3329 regno = EH_RETURN_DATA_REGNO (i);
3330 if (regno == INVALID_REGNUM)
3333 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3334 offset += UNITS_PER_WORD;
3338 for (i = 18; i >= 4; i--)
3339 if (regs_ever_live[i] && ! call_used_regs[i])
3341 store_reg (i, offset, FRAME_POINTER_REGNUM);
3342 offset += UNITS_PER_WORD;
3345 /* Account for %r3 which is saved in a special place. */
3348 /* No frame pointer needed. */
3351 offset = local_fsize - actual_fsize;
3353 /* Saving the EH return data registers in the frame is the simplest
3354 way to get the frame unwind information emitted. */
3355 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3357 unsigned int i, regno;
3361 regno = EH_RETURN_DATA_REGNO (i);
3362 if (regno == INVALID_REGNUM)
3365 /* If merge_sp_adjust_with_store is nonzero, then we can
3366 optimize the first save. */
3367 if (merge_sp_adjust_with_store)
3369 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3370 merge_sp_adjust_with_store = 0;
3373 store_reg (regno, offset, STACK_POINTER_REGNUM);
3374 offset += UNITS_PER_WORD;
3378 for (i = 18; i >= 3; i--)
3379 if (regs_ever_live[i] && ! call_used_regs[i])
3381 /* If merge_sp_adjust_with_store is nonzero, then we can
3382 optimize the first GR save. */
3383 if (merge_sp_adjust_with_store)
3385 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3386 merge_sp_adjust_with_store = 0;
3389 store_reg (i, offset, STACK_POINTER_REGNUM);
3390 offset += UNITS_PER_WORD;
3394 /* If we wanted to merge the SP adjustment with a GR save, but we never
3395 did any GR saves, then just emit the adjustment here. */
3396 if (merge_sp_adjust_with_store)
3397 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3401 /* The hppa calling conventions say that %r19, the pic offset
3402 register, is saved at sp - 32 (in this function's frame)
3403 when generating PIC code. FIXME: What is the correct thing
3404 to do for functions which make no calls and allocate no
3405 frame? Do we need to allocate a frame, or can we just omit
3406 the save? For now we'll just omit the save. */
3407 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3408 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3410 /* Align pointer properly (doubleword boundary). */
3411 offset = (offset + 7) & ~7;
3413 /* Floating point register store. */
3418 /* First get the frame or stack pointer to the start of the FP register
3420 if (frame_pointer_needed)
3422 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3423 base = frame_pointer_rtx;
3427 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3428 base = stack_pointer_rtx;
3431 /* Now actually save the FP registers. */
3432 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3434 if (regs_ever_live[i]
3435 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3437 rtx addr, insn, reg;
3438 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3439 reg = gen_rtx_REG (DFmode, i);
3440 insn = emit_move_insn (addr, reg);
3443 RTX_FRAME_RELATED_P (insn) = 1;
3446 rtx mem = gen_rtx_MEM (DFmode,
3447 plus_constant (base, offset));
3449 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3450 gen_rtx_SET (VOIDmode, mem, reg),
3455 rtx meml = gen_rtx_MEM (SFmode,
3456 plus_constant (base, offset));
3457 rtx memr = gen_rtx_MEM (SFmode,
3458 plus_constant (base, offset + 4));
3459 rtx regl = gen_rtx_REG (SFmode, i);
3460 rtx regr = gen_rtx_REG (SFmode, i + 1);
3461 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3462 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3465 RTX_FRAME_RELATED_P (setl) = 1;
3466 RTX_FRAME_RELATED_P (setr) = 1;
3467 vec = gen_rtvec (2, setl, setr);
3469 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3470 gen_rtx_SEQUENCE (VOIDmode, vec),
3474 offset += GET_MODE_SIZE (DFmode);
3480 /* FIXME: expand_call and expand_millicode_call need to be fixed to
3481 prevent insns with frame notes being scheduled in the delay slot
3482 of calls. This causes problems because the dwarf2 output code
3483 processes the insn list serially. For now, limit the migration
3484 of prologue insns with a blockage. */
3486 emit_insn (gen_blockage ());
3489 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3490 Handle case where DISP > 8k by using the add_high_const patterns. */
3493 load_reg (reg, disp, base)
3494 int reg, disp, base;
3496 rtx src, dest, basereg;
3498 dest = gen_rtx_REG (word_mode, reg);
3499 basereg = gen_rtx_REG (Pmode, base);
3500 if (VAL_14_BITS_P (disp))
3502 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3503 emit_move_insn (dest, src);
3507 rtx delta = GEN_INT (disp);
3508 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3509 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3510 emit_move_insn (tmpreg, high);
3511 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3512 emit_move_insn (dest, src);
3516 /* This function generates the assembly code for function exit.
3517 Args are as for output_function_prologue ().
3519 The function epilogue should not depend on the current stack
3520 pointer! It should use the frame pointer only. This is mandatory
3521 because of alloca; we also take advantage of it to omit stack
3522 adjustments before returning. */
3525 pa_output_function_epilogue (file, size)
3527 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3529 rtx insn = get_last_insn ();
3531 /* hppa_expand_epilogue does the dirty work now. We just need
3532 to output the assembler directives which denote the end
3535 To make debuggers happy, emit a nop if the epilogue was completely
3536 eliminated due to a volatile call as the last insn in the
3537 current function. That way the return address (in %r2) will
3538 always point to a valid instruction in the current function. */
3540 /* Get the last real insn. */
3541 if (GET_CODE (insn) == NOTE)
3542 insn = prev_real_insn (insn);
3544 /* If it is a sequence, then look inside. */
3545 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3546 insn = XVECEXP (PATTERN (insn), 0, 0);
3548 /* If insn is a CALL_INSN, then it must be a call to a volatile
3549 function (otherwise there would be epilogue insns). */
3550 if (insn && GET_CODE (insn) == CALL_INSN)
3551 fputs ("\tnop\n", file);
3553 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3557 hppa_expand_epilogue ()
3561 int merge_sp_adjust_with_load = 0;
3564 /* We will use this often. */
3565 tmpreg = gen_rtx_REG (word_mode, 1);
3567 /* Try to restore RP early to avoid load/use interlocks when
3568 RP gets used in the return (bv) instruction. This appears to still
3569 be necessary even when we schedule the prologue and epilogue. */
3570 if (regs_ever_live [2] || current_function_calls_eh_return)
3572 ret_off = TARGET_64BIT ? -16 : -20;
3573 if (frame_pointer_needed)
3575 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3580 /* No frame pointer, and stack is smaller than 8k. */
3581 if (VAL_14_BITS_P (ret_off - actual_fsize))
3583 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3589 /* General register restores. */
3590 if (frame_pointer_needed)
3592 offset = local_fsize;
3594 /* If the current function calls __builtin_eh_return, then we need
3595 to restore the saved EH data registers. */
3596 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3598 unsigned int i, regno;
3602 regno = EH_RETURN_DATA_REGNO (i);
3603 if (regno == INVALID_REGNUM)
3606 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3607 offset += UNITS_PER_WORD;
3611 for (i = 18; i >= 4; i--)
3612 if (regs_ever_live[i] && ! call_used_regs[i])
3614 load_reg (i, offset, FRAME_POINTER_REGNUM);
3615 offset += UNITS_PER_WORD;
3620 offset = local_fsize - actual_fsize;
3622 /* If the current function calls __builtin_eh_return, then we need
3623 to restore the saved EH data registers. */
3624 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3626 unsigned int i, regno;
3630 regno = EH_RETURN_DATA_REGNO (i);
3631 if (regno == INVALID_REGNUM)
3634 /* Only for the first load.
3635 merge_sp_adjust_with_load holds the register load
3636 with which we will merge the sp adjustment. */
3637 if (merge_sp_adjust_with_load == 0
3639 && VAL_14_BITS_P (-actual_fsize))
3640 merge_sp_adjust_with_load = regno;
3642 load_reg (regno, offset, STACK_POINTER_REGNUM);
3643 offset += UNITS_PER_WORD;
3647 for (i = 18; i >= 3; i--)
3649 if (regs_ever_live[i] && ! call_used_regs[i])
3651 /* Only for the first load.
3652 merge_sp_adjust_with_load holds the register load
3653 with which we will merge the sp adjustment. */
3654 if (merge_sp_adjust_with_load == 0
3656 && VAL_14_BITS_P (-actual_fsize))
3657 merge_sp_adjust_with_load = i;
3659 load_reg (i, offset, STACK_POINTER_REGNUM);
3660 offset += UNITS_PER_WORD;
3665 /* Align pointer properly (doubleword boundary). */
3666 offset = (offset + 7) & ~7;
3668 /* FP register restores. */
3671 /* Adjust the register to index off of. */
3672 if (frame_pointer_needed)
3673 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3675 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3677 /* Actually do the restores now. */
3678 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3679 if (regs_ever_live[i]
3680 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3682 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3683 rtx dest = gen_rtx_REG (DFmode, i);
3684 emit_move_insn (dest, src);
3688 /* Emit a blockage insn here to keep these insns from being moved to
3689 an earlier spot in the epilogue, or into the main instruction stream.
3691 This is necessary as we must not cut the stack back before all the
3692 restores are finished. */
3693 emit_insn (gen_blockage ());
3695 /* Reset stack pointer (and possibly frame pointer). The stack
3696 pointer is initially set to fp + 64 to avoid a race condition. */
3697 if (frame_pointer_needed)
3699 rtx delta = GEN_INT (-64);
3701 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3702 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3704 /* If we were deferring a callee register restore, do it now. */
3705 else if (merge_sp_adjust_with_load)
3707 rtx delta = GEN_INT (-actual_fsize);
3708 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3710 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3712 else if (actual_fsize != 0)
3713 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3716 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3717 frame greater than 8k), do so now. */
3719 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3721 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3723 rtx sa = EH_RETURN_STACKADJ_RTX;
3725 emit_insn (gen_blockage ());
3726 emit_insn (TARGET_64BIT
3727 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3728 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3733 hppa_pic_save_rtx ()
3735 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3739 hppa_profile_hook (label_no)
3742 rtx begin_label_rtx, call_insn;
3743 char begin_label_name[16];
3745 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3747 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3750 emit_move_insn (arg_pointer_rtx,
3751 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3754 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3756 #ifndef NO_PROFILE_COUNTERS
3758 rtx count_label_rtx, addr, r24;
3759 char count_label_name[16];
3761 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3762 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3764 addr = force_reg (Pmode, count_label_rtx);
3765 r24 = gen_rtx_REG (Pmode, 24);
3766 emit_move_insn (r24, addr);
3768 /* %r25 is set from within the output pattern. */
3770 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3771 GEN_INT (TARGET_64BIT ? 24 : 12),
3774 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3777 /* %r25 is set from within the output pattern. */
3779 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3780 GEN_INT (TARGET_64BIT ? 16 : 8),
3784 /* Indicate the _mcount call cannot throw, nor will it execute a
3786 REG_NOTES (call_insn)
3787 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3791 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3793 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3795 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3799 /* Fetch the return address for the frame COUNT steps up from
3800 the current frame, after the prologue. FRAMEADDR is the
3801 frame pointer of the COUNT frame.
3803 We want to ignore any export stub remnants here. To handle this,
3804 we examine the code at the return address, and if it is an export
3805 stub, we return a memory rtx for the stub return address stored
3808 The value returned is used in two different ways:
3810 1. To find a function's caller.
3812 2. To change the return address for a function.
3814 This function handles most instances of case 1; however, it will
3815 fail if there are two levels of stubs to execute on the return
3816 path. The only way I believe that can happen is if the return value
3817 needs a parameter relocation, which never happens for C code.
3819 This function handles most instances of case 2; however, it will
3820 fail if we did not originally have stub code on the return path
3821 but will need stub code on the new return path. This can happen if
3822 the caller & callee are both in the main program, but the new
3823 return location is in a shared library. */
3826 return_addr_rtx (count, frameaddr)
3838 rp = get_hard_reg_initial_val (Pmode, 2);
3840 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
3843 saved_rp = gen_reg_rtx (Pmode);
3844 emit_move_insn (saved_rp, rp);
3846 /* Get pointer to the instruction stream. We have to mask out the
3847 privilege level from the two low order bits of the return address
3848 pointer here so that ins will point to the start of the first
3849 instruction that would have been executed if we returned. */
3850 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
3851 label = gen_label_rtx ();
3853 /* Check the instruction stream at the normal return address for the
3856 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
3857 0x004010a1 | stub+12: ldsid (sr0,rp),r1
3858 0x00011820 | stub+16: mtsp r1,sr0
3859 0xe0400002 | stub+20: be,n 0(sr0,rp)
3861 If it is an export stub, than our return address is really in
3864 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
3865 NULL_RTX, SImode, 1);
3866 emit_jump_insn (gen_bne (label));
3868 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
3869 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
3870 emit_jump_insn (gen_bne (label));
3872 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
3873 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
3874 emit_jump_insn (gen_bne (label));
3876 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
3877 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
3879 /* If there is no export stub then just use the value saved from
3880 the return pointer register. */
3882 emit_jump_insn (gen_bne (label));
3884 /* Here we know that our return address points to an export
3885 stub. We don't want to return the address of the export stub,
3886 but rather the return address of the export stub. That return
3887 address is stored at -24[frameaddr]. */
3889 emit_move_insn (saved_rp,
3891 memory_address (Pmode,
3892 plus_constant (frameaddr,
3899 /* This is only valid once reload has completed because it depends on
3900 knowing exactly how much (if any) frame there is and...
3902 It's only valid if there is no frame marker to de-allocate and...
3904 It's only valid if %r2 hasn't been saved into the caller's frame
3905 (we're not profiling and %r2 isn't live anywhere). */
3907 hppa_can_use_return_insn_p ()
3909 return (reload_completed
3910 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
3911 && ! regs_ever_live[2]
3912 && ! frame_pointer_needed);
3916 emit_bcond_fp (code, operand0)
3920 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
3921 gen_rtx_IF_THEN_ELSE (VOIDmode,
3922 gen_rtx_fmt_ee (code,
3924 gen_rtx_REG (CCFPmode, 0),
3926 gen_rtx_LABEL_REF (VOIDmode, operand0),
3932 gen_cmp_fp (code, operand0, operand1)
3934 rtx operand0, operand1;
3936 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
3937 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
3940 /* Adjust the cost of a scheduling dependency. Return the new cost of
3941 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
3944 pa_adjust_cost (insn, link, dep_insn, cost)
3950 enum attr_type attr_type;
3952 /* Don't adjust costs for a pa8000 chip, also do not adjust any
3953 true dependencies as they are described with bypasses now. */
3954 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
3957 if (! recog_memoized (insn))
3960 attr_type = get_attr_type (insn);
3962 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
3964 /* Anti dependency; DEP_INSN reads a register that INSN writes some
3967 if (attr_type == TYPE_FPLOAD)
3969 rtx pat = PATTERN (insn);
3970 rtx dep_pat = PATTERN (dep_insn);
3971 if (GET_CODE (pat) == PARALLEL)
3973 /* This happens for the fldXs,mb patterns. */
3974 pat = XVECEXP (pat, 0, 0);
3976 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
3977 /* If this happens, we have to extend this to schedule
3978 optimally. Return 0 for now. */
3981 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
3983 if (! recog_memoized (dep_insn))
3985 switch (get_attr_type (dep_insn))
3992 case TYPE_FPSQRTSGL:
3993 case TYPE_FPSQRTDBL:
3994 /* A fpload can't be issued until one cycle before a
3995 preceding arithmetic operation has finished if
3996 the target of the fpload is any of the sources
3997 (or destination) of the arithmetic operation. */
3998 return insn_default_latency (dep_insn) - 1;
4005 else if (attr_type == TYPE_FPALU)
4007 rtx pat = PATTERN (insn);
4008 rtx dep_pat = PATTERN (dep_insn);
4009 if (GET_CODE (pat) == PARALLEL)
4011 /* This happens for the fldXs,mb patterns. */
4012 pat = XVECEXP (pat, 0, 0);
4014 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4015 /* If this happens, we have to extend this to schedule
4016 optimally. Return 0 for now. */
4019 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4021 if (! recog_memoized (dep_insn))
4023 switch (get_attr_type (dep_insn))
4027 case TYPE_FPSQRTSGL:
4028 case TYPE_FPSQRTDBL:
4029 /* An ALU flop can't be issued until two cycles before a
4030 preceding divide or sqrt operation has finished if
4031 the target of the ALU flop is any of the sources
4032 (or destination) of the divide or sqrt operation. */
4033 return insn_default_latency (dep_insn) - 2;
4041 /* For other anti dependencies, the cost is 0. */
4044 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4046 /* Output dependency; DEP_INSN writes a register that INSN writes some
4048 if (attr_type == TYPE_FPLOAD)
4050 rtx pat = PATTERN (insn);
4051 rtx dep_pat = PATTERN (dep_insn);
4052 if (GET_CODE (pat) == PARALLEL)
4054 /* This happens for the fldXs,mb patterns. */
4055 pat = XVECEXP (pat, 0, 0);
4057 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4058 /* If this happens, we have to extend this to schedule
4059 optimally. Return 0 for now. */
4062 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4064 if (! recog_memoized (dep_insn))
4066 switch (get_attr_type (dep_insn))
4073 case TYPE_FPSQRTSGL:
4074 case TYPE_FPSQRTDBL:
4075 /* A fpload can't be issued until one cycle before a
4076 preceding arithmetic operation has finished if
4077 the target of the fpload is the destination of the
4078 arithmetic operation.
4080 Exception: For PA7100LC, PA7200 and PA7300, the cost
4081 is 3 cycles, unless they bundle together. We also
4082 pay the penalty if the second insn is a fpload. */
4083 return insn_default_latency (dep_insn) - 1;
4090 else if (attr_type == TYPE_FPALU)
4092 rtx pat = PATTERN (insn);
4093 rtx dep_pat = PATTERN (dep_insn);
4094 if (GET_CODE (pat) == PARALLEL)
4096 /* This happens for the fldXs,mb patterns. */
4097 pat = XVECEXP (pat, 0, 0);
4099 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4100 /* If this happens, we have to extend this to schedule
4101 optimally. Return 0 for now. */
4104 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4106 if (! recog_memoized (dep_insn))
4108 switch (get_attr_type (dep_insn))
4112 case TYPE_FPSQRTSGL:
4113 case TYPE_FPSQRTDBL:
4114 /* An ALU flop can't be issued until two cycles before a
4115 preceding divide or sqrt operation has finished if
4116 the target of the ALU flop is also the target of
4117 the divide or sqrt operation. */
4118 return insn_default_latency (dep_insn) - 2;
4126 /* For other output dependencies, the cost is 0. */
4133 /* Adjust scheduling priorities. We use this to try and keep addil
4134 and the next use of %r1 close together. */
4136 pa_adjust_priority (insn, priority)
4140 rtx set = single_set (insn);
4144 src = SET_SRC (set);
4145 dest = SET_DEST (set);
4146 if (GET_CODE (src) == LO_SUM
4147 && symbolic_operand (XEXP (src, 1), VOIDmode)
4148 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4151 else if (GET_CODE (src) == MEM
4152 && GET_CODE (XEXP (src, 0)) == LO_SUM
4153 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4154 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4157 else if (GET_CODE (dest) == MEM
4158 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4159 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4160 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4166 /* The 700 can only issue a single insn at a time.
4167 The 7XXX processors can issue two insns at a time.
4168 The 8000 can issue 4 insns at a time. */
4174 case PROCESSOR_700: return 1;
4175 case PROCESSOR_7100: return 2;
4176 case PROCESSOR_7100LC: return 2;
4177 case PROCESSOR_7200: return 2;
4178 case PROCESSOR_7300: return 2;
4179 case PROCESSOR_8000: return 4;
4188 /* Return any length adjustment needed by INSN which already has its length
4189 computed as LENGTH. Return zero if no adjustment is necessary.
4191 For the PA: function calls, millicode calls, and backwards short
4192 conditional branches with unfilled delay slots need an adjustment by +1
4193 (to account for the NOP which will be inserted into the instruction stream).
4195 Also compute the length of an inline block move here as it is too
4196 complicated to express as a length attribute in pa.md. */
4198 pa_adjust_insn_length (insn, length)
4202 rtx pat = PATTERN (insn);
4204 /* Call insns which are *not* indirect and have unfilled delay slots. */
4205 if (GET_CODE (insn) == CALL_INSN)
4208 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4209 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4211 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4212 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4218 /* Jumps inside switch tables which have unfilled delay slots
4219 also need adjustment. */
4220 else if (GET_CODE (insn) == JUMP_INSN
4221 && simplejump_p (insn)
4222 && GET_MODE (insn) == SImode)
4224 /* Millicode insn with an unfilled delay slot. */
4225 else if (GET_CODE (insn) == INSN
4226 && GET_CODE (pat) != SEQUENCE
4227 && GET_CODE (pat) != USE
4228 && GET_CODE (pat) != CLOBBER
4229 && get_attr_type (insn) == TYPE_MILLI)
4231 /* Block move pattern. */
4232 else if (GET_CODE (insn) == INSN
4233 && GET_CODE (pat) == PARALLEL
4234 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4235 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4236 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4237 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4238 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4239 return compute_movstrsi_length (insn) - 4;
4240 /* Conditional branch with an unfilled delay slot. */
4241 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4243 /* Adjust a short backwards conditional with an unfilled delay slot. */
4244 if (GET_CODE (pat) == SET
4246 && ! forward_branch_p (insn))
4248 else if (GET_CODE (pat) == PARALLEL
4249 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4252 /* Adjust dbra insn with short backwards conditional branch with
4253 unfilled delay slot -- only for case where counter is in a
4254 general register register. */
4255 else if (GET_CODE (pat) == PARALLEL
4256 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4257 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4258 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4260 && ! forward_branch_p (insn))
4268 /* Print operand X (an rtx) in assembler syntax to file FILE.
4269 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4270 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4273 print_operand (file, x, code)
4281 /* Output a 'nop' if there's nothing for the delay slot. */
4282 if (dbr_sequence_length () == 0)
4283 fputs ("\n\tnop", file);
4286 /* Output an nullification completer if there's nothing for the */
4287 /* delay slot or nullification is requested. */
4288 if (dbr_sequence_length () == 0 ||
4290 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4294 /* Print out the second register name of a register pair.
4295 I.e., R (6) => 7. */
4296 fputs (reg_names[REGNO (x) + 1], file);
4299 /* A register or zero. */
4301 || (x == CONST0_RTX (DFmode))
4302 || (x == CONST0_RTX (SFmode)))
4304 fputs ("%r0", file);
4310 /* A register or zero (floating point). */
4312 || (x == CONST0_RTX (DFmode))
4313 || (x == CONST0_RTX (SFmode)))
4315 fputs ("%fr0", file);
4324 xoperands[0] = XEXP (XEXP (x, 0), 0);
4325 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4326 output_global_address (file, xoperands[1], 0);
4327 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4331 case 'C': /* Plain (C)ondition */
4333 switch (GET_CODE (x))
4336 fputs ("=", file); break;
4338 fputs ("<>", file); break;
4340 fputs (">", file); break;
4342 fputs (">=", file); break;
4344 fputs (">>=", file); break;
4346 fputs (">>", file); break;
4348 fputs ("<", file); break;
4350 fputs ("<=", file); break;
4352 fputs ("<<=", file); break;
4354 fputs ("<<", file); break;
4359 case 'N': /* Condition, (N)egated */
4360 switch (GET_CODE (x))
4363 fputs ("<>", file); break;
4365 fputs ("=", file); break;
4367 fputs ("<=", file); break;
4369 fputs ("<", file); break;
4371 fputs ("<<", file); break;
4373 fputs ("<<=", file); break;
4375 fputs (">=", file); break;
4377 fputs (">", file); break;
4379 fputs (">>", file); break;
4381 fputs (">>=", file); break;
4386 /* For floating point comparisons. Note that the output
4387 predicates are the complement of the desired mode. */
4389 switch (GET_CODE (x))
4392 fputs ("!=", file); break;
4394 fputs ("=", file); break;
4396 fputs ("!>", file); break;
4398 fputs ("!>=", file); break;
4400 fputs ("!<", file); break;
4402 fputs ("!<=", file); break;
4404 fputs ("!<>", file); break;
4406 fputs (">", file); break;
4408 fputs (">=", file); break;
4410 fputs ("<", file); break;
4412 fputs ("<=", file); break;
4414 fputs ("<>", file); break;
4416 fputs ("<=>", file); break;
4418 fputs ("!<=>", file); break;
4423 case 'S': /* Condition, operands are (S)wapped. */
4424 switch (GET_CODE (x))
4427 fputs ("=", file); break;
4429 fputs ("<>", file); break;
4431 fputs ("<", file); break;
4433 fputs ("<=", file); break;
4435 fputs ("<<=", file); break;
4437 fputs ("<<", file); break;
4439 fputs (">", file); break;
4441 fputs (">=", file); break;
4443 fputs (">>=", file); break;
4445 fputs (">>", file); break;
4450 case 'B': /* Condition, (B)oth swapped and negate. */
4451 switch (GET_CODE (x))
4454 fputs ("<>", file); break;
4456 fputs ("=", file); break;
4458 fputs (">=", file); break;
4460 fputs (">", file); break;
4462 fputs (">>", file); break;
4464 fputs (">>=", file); break;
4466 fputs ("<=", file); break;
4468 fputs ("<", file); break;
4470 fputs ("<<", file); break;
4472 fputs ("<<=", file); break;
4478 if (GET_CODE (x) == CONST_INT)
4480 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4485 if (GET_CODE (x) == CONST_INT)
4487 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4492 if (GET_CODE (x) == CONST_INT)
4494 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4499 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4501 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4506 if (GET_CODE (x) == CONST_INT)
4508 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4513 if (GET_CODE (x) == CONST_INT)
4515 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4520 if (GET_CODE (x) == CONST_INT)
4525 switch (GET_CODE (XEXP (x, 0)))
4529 if (ASSEMBLER_DIALECT == 0)
4530 fputs ("s,mb", file);
4532 fputs (",mb", file);
4536 if (ASSEMBLER_DIALECT == 0)
4537 fputs ("s,ma", file);
4539 fputs (",ma", file);
4542 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4543 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4545 if (ASSEMBLER_DIALECT == 0)
4546 fputs ("x,s", file);
4550 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4554 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4560 output_global_address (file, x, 0);
4563 output_global_address (file, x, 1);
4565 case 0: /* Don't do anything special */
4570 compute_zdepwi_operands (INTVAL (x), op);
4571 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4577 compute_zdepdi_operands (INTVAL (x), op);
4578 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4582 /* We can get here from a .vtable_inherit due to our
4583 CONSTANT_ADDRESS_P rejecting perfectly good constant
4589 if (GET_CODE (x) == REG)
4591 fputs (reg_names [REGNO (x)], file);
4592 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4598 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4599 && (REGNO (x) & 1) == 0)
4602 else if (GET_CODE (x) == MEM)
4604 int size = GET_MODE_SIZE (GET_MODE (x));
4605 rtx base = NULL_RTX;
4606 switch (GET_CODE (XEXP (x, 0)))
4610 base = XEXP (XEXP (x, 0), 0);
4611 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4615 base = XEXP (XEXP (x, 0), 0);
4616 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4619 if (GET_CODE (XEXP (x, 0)) == PLUS
4620 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4621 fprintf (file, "%s(%s)",
4622 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4623 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4624 else if (GET_CODE (XEXP (x, 0)) == PLUS
4625 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4626 fprintf (file, "%s(%s)",
4627 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4628 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4630 output_address (XEXP (x, 0));
4635 output_addr_const (file, x);
4638 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4641 output_global_address (file, x, round_constant)
4647 /* Imagine (high (const (plus ...))). */
4648 if (GET_CODE (x) == HIGH)
4651 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4652 assemble_name (file, XSTR (x, 0));
4653 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4655 assemble_name (file, XSTR (x, 0));
4656 fputs ("-$global$", file);
4658 else if (GET_CODE (x) == CONST)
4660 const char *sep = "";
4661 int offset = 0; /* assembler wants -$global$ at end */
4662 rtx base = NULL_RTX;
4664 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4666 base = XEXP (XEXP (x, 0), 0);
4667 output_addr_const (file, base);
4669 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4670 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4673 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4675 base = XEXP (XEXP (x, 0), 1);
4676 output_addr_const (file, base);
4678 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4679 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4682 /* How bogus. The compiler is apparently responsible for
4683 rounding the constant if it uses an LR field selector.
4685 The linker and/or assembler seem a better place since
4686 they have to do this kind of thing already.
4688 If we fail to do this, HP's optimizing linker may eliminate
4689 an addil, but not update the ldw/stw/ldo instruction that
4690 uses the result of the addil. */
4692 offset = ((offset + 0x1000) & ~0x1fff);
4694 if (GET_CODE (XEXP (x, 0)) == PLUS)
4704 else if (GET_CODE (XEXP (x, 0)) == MINUS
4705 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4709 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4710 fputs ("-$global$", file);
4712 fprintf (file, "%s%d", sep, offset);
4715 output_addr_const (file, x);
4719 output_deferred_plabels (file)
4723 /* If we have deferred plabels, then we need to switch into the data
4724 section and align it to a 4 byte boundary before we output the
4725 deferred plabels. */
4726 if (n_deferred_plabels)
4729 ASM_OUTPUT_ALIGN (file, 2);
4732 /* Now output the deferred plabels. */
4733 for (i = 0; i < n_deferred_plabels; i++)
4735 ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4736 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4737 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4741 /* HP's millicode routines mean something special to the assembler.
4742 Keep track of which ones we have used. */
4744 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4745 static void import_milli PARAMS ((enum millicodes));
4746 static char imported[(int) end1000];
4747 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4748 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4749 #define MILLI_START 10
4753 enum millicodes code;
4755 char str[sizeof (import_string)];
4757 if (!imported[(int) code])
4759 imported[(int) code] = 1;
4760 strcpy (str, import_string);
4761 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4762 output_asm_insn (str, 0);
4766 /* The register constraints have put the operands and return value in
4767 the proper registers. */
4770 output_mul_insn (unsignedp, insn)
4771 int unsignedp ATTRIBUTE_UNUSED;
4774 import_milli (mulI);
4775 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
4778 /* Emit the rtl for doing a division by a constant. */
4780 /* Do magic division millicodes exist for this value? */
4781 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
4784 /* We'll use an array to keep track of the magic millicodes and
4785 whether or not we've used them already. [n][0] is signed, [n][1] is
4788 static int div_milli[16][2];
4791 div_operand (op, mode)
4793 enum machine_mode mode;
4795 return (mode == SImode
4796 && ((GET_CODE (op) == REG && REGNO (op) == 25)
4797 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
4798 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
4802 emit_hpdiv_const (operands, unsignedp)
4806 if (GET_CODE (operands[2]) == CONST_INT
4807 && INTVAL (operands[2]) > 0
4808 && INTVAL (operands[2]) < 16
4809 && magic_milli[INTVAL (operands[2])])
4811 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
4813 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
4816 (PARALLEL, VOIDmode,
4817 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
4818 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
4820 gen_rtx_REG (SImode, 26),
4822 gen_rtx_CLOBBER (VOIDmode, operands[4]),
4823 gen_rtx_CLOBBER (VOIDmode, operands[3]),
4824 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
4825 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
4826 gen_rtx_CLOBBER (VOIDmode, ret))));
4827 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
4834 output_div_insn (operands, unsignedp, insn)
4841 /* If the divisor is a constant, try to use one of the special
4843 if (GET_CODE (operands[0]) == CONST_INT)
4845 static char buf[100];
4846 divisor = INTVAL (operands[0]);
4847 if (!div_milli[divisor][unsignedp])
4849 div_milli[divisor][unsignedp] = 1;
4851 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
4853 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
4857 sprintf (buf, "$$divU_");
4858 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4859 return output_millicode_call (insn,
4860 gen_rtx_SYMBOL_REF (SImode, buf));
4864 sprintf (buf, "$$divI_");
4865 sprintf (buf + 7, HOST_WIDE_INT_PRINT_DEC, INTVAL (operands[0]));
4866 return output_millicode_call (insn,
4867 gen_rtx_SYMBOL_REF (SImode, buf));
4870 /* Divisor isn't a special constant. */
4875 import_milli (divU);
4876 return output_millicode_call (insn,
4877 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
4881 import_milli (divI);
4882 return output_millicode_call (insn,
4883 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
4888 /* Output a $$rem millicode to do mod. */
4891 output_mod_insn (unsignedp, insn)
4897 import_milli (remU);
4898 return output_millicode_call (insn,
4899 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
4903 import_milli (remI);
4904 return output_millicode_call (insn,
4905 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
4910 output_arg_descriptor (call_insn)
4913 const char *arg_regs[4];
4914 enum machine_mode arg_mode;
4916 int i, output_flag = 0;
4919 /* We neither need nor want argument location descriptors for the
4920 64bit runtime environment or the ELF32 environment. */
4921 if (TARGET_64BIT || TARGET_ELF32)
4924 for (i = 0; i < 4; i++)
4927 /* Specify explicitly that no argument relocations should take place
4928 if using the portable runtime calling conventions. */
4929 if (TARGET_PORTABLE_RUNTIME)
4931 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
4936 if (GET_CODE (call_insn) != CALL_INSN)
4938 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
4940 rtx use = XEXP (link, 0);
4942 if (! (GET_CODE (use) == USE
4943 && GET_CODE (XEXP (use, 0)) == REG
4944 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
4947 arg_mode = GET_MODE (XEXP (use, 0));
4948 regno = REGNO (XEXP (use, 0));
4949 if (regno >= 23 && regno <= 26)
4951 arg_regs[26 - regno] = "GR";
4952 if (arg_mode == DImode)
4953 arg_regs[25 - regno] = "GR";
4955 else if (regno >= 32 && regno <= 39)
4957 if (arg_mode == SFmode)
4958 arg_regs[(regno - 32) / 2] = "FR";
4961 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
4962 arg_regs[(regno - 34) / 2] = "FR";
4963 arg_regs[(regno - 34) / 2 + 1] = "FU";
4965 arg_regs[(regno - 34) / 2] = "FU";
4966 arg_regs[(regno - 34) / 2 + 1] = "FR";
4971 fputs ("\t.CALL ", asm_out_file);
4972 for (i = 0; i < 4; i++)
4977 fputc (',', asm_out_file);
4978 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
4981 fputc ('\n', asm_out_file);
4984 /* Return the class of any secondary reload register that is needed to
4985 move IN into a register in class CLASS using mode MODE.
4987 Profiling has showed this routine and its descendants account for
4988 a significant amount of compile time (~7%). So it has been
4989 optimized to reduce redundant computations and eliminate useless
4992 It might be worthwhile to try and make this a leaf function too. */
4995 secondary_reload_class (class, mode, in)
4996 enum reg_class class;
4997 enum machine_mode mode;
5000 int regno, is_symbolic;
5002 /* Trying to load a constant into a FP register during PIC code
5003 generation will require %r1 as a scratch register. */
5005 && GET_MODE_CLASS (mode) == MODE_INT
5006 && FP_REG_CLASS_P (class)
5007 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5010 /* Profiling showed the PA port spends about 1.3% of its compilation
5011 time in true_regnum from calls inside secondary_reload_class. */
5013 if (GET_CODE (in) == REG)
5016 if (regno >= FIRST_PSEUDO_REGISTER)
5017 regno = true_regnum (in);
5019 else if (GET_CODE (in) == SUBREG)
5020 regno = true_regnum (in);
5024 /* If we have something like (mem (mem (...)), we can safely assume the
5025 inner MEM will end up in a general register after reloading, so there's
5026 no need for a secondary reload. */
5027 if (GET_CODE (in) == MEM
5028 && GET_CODE (XEXP (in, 0)) == MEM)
5031 /* Handle out of range displacement for integer mode loads/stores of
5033 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5034 && GET_MODE_CLASS (mode) == MODE_INT
5035 && FP_REG_CLASS_P (class))
5036 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5037 return GENERAL_REGS;
5039 /* A SAR<->FP register copy requires a secondary register (GPR) as
5040 well as secondary memory. */
5041 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5042 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5043 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5044 return GENERAL_REGS;
5046 if (GET_CODE (in) == HIGH)
5049 /* Profiling has showed GCC spends about 2.6% of its compilation
5050 time in symbolic_operand from calls inside secondary_reload_class.
5052 We use an inline copy and only compute its return value once to avoid
5054 switch (GET_CODE (in))
5064 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5065 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5066 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5076 && read_only_operand (in, VOIDmode))
5079 if (class != R1_REGS && is_symbolic)
5086 function_arg_padding (mode, type)
5087 enum machine_mode mode;
5092 if (mode == BLKmode)
5094 if (type && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST)
5095 size = int_size_in_bytes (type) * BITS_PER_UNIT;
5097 return upward; /* Don't know if this is right, but */
5098 /* same as old definition. */
5101 size = GET_MODE_BITSIZE (mode);
5102 if (size < PARM_BOUNDARY)
5104 else if (size % PARM_BOUNDARY)
5111 /* Do what is necessary for `va_start'. We look at the current function
5112 to determine if stdargs or varargs is used and fill in an initial
5113 va_list. A pointer to this constructor is returned. */
5116 hppa_builtin_saveregs ()
5119 tree fntype = TREE_TYPE (current_function_decl);
5120 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5121 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5122 != void_type_node)))
5123 ? UNITS_PER_WORD : 0);
5126 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5128 offset = current_function_arg_offset_rtx;
5134 /* Adjust for varargs/stdarg differences. */
5136 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5138 offset = current_function_arg_offset_rtx;
5140 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5141 from the incoming arg pointer and growing to larger addresses. */
5142 for (i = 26, off = -64; i >= 19; i--, off += 8)
5143 emit_move_insn (gen_rtx_MEM (word_mode,
5144 plus_constant (arg_pointer_rtx, off)),
5145 gen_rtx_REG (word_mode, i));
5147 /* The incoming args pointer points just beyond the flushback area;
5148 normally this is not a serious concern. However, when we are doing
5149 varargs/stdargs we want to make the arg pointer point to the start
5150 of the incoming argument area. */
5151 emit_move_insn (virtual_incoming_args_rtx,
5152 plus_constant (arg_pointer_rtx, -64));
5154 /* Now return a pointer to the first anonymous argument. */
5155 return copy_to_reg (expand_binop (Pmode, add_optab,
5156 virtual_incoming_args_rtx,
5157 offset, 0, 0, OPTAB_LIB_WIDEN));
5160 /* Store general registers on the stack. */
5161 dest = gen_rtx_MEM (BLKmode,
5162 plus_constant (current_function_internal_arg_pointer,
5164 set_mem_alias_set (dest, get_varargs_alias_set ());
5165 set_mem_align (dest, BITS_PER_WORD);
5166 move_block_from_reg (23, dest, 4, 4 * UNITS_PER_WORD);
5168 /* move_block_from_reg will emit code to store the argument registers
5169 individually as scalar stores.
5171 However, other insns may later load from the same addresses for
5172 a structure load (passing a struct to a varargs routine).
5174 The alias code assumes that such aliasing can never happen, so we
5175 have to keep memory referencing insns from moving up beyond the
5176 last argument register store. So we emit a blockage insn here. */
5177 emit_insn (gen_blockage ());
5179 return copy_to_reg (expand_binop (Pmode, add_optab,
5180 current_function_internal_arg_pointer,
5181 offset, 0, 0, OPTAB_LIB_WIDEN));
5185 hppa_va_start (valist, nextarg)
5189 nextarg = expand_builtin_saveregs ();
5190 std_expand_builtin_va_start (valist, nextarg);
5194 hppa_va_arg (valist, type)
5197 HOST_WIDE_INT align, size, ofs;
5202 /* Every argument in PA64 is passed by value (including large structs).
5203 Arguments with size greater than 8 must be aligned 0 MOD 16. */
5205 size = int_size_in_bytes (type);
5206 if (size > UNITS_PER_WORD)
5208 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5209 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5210 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5211 build_int_2 (-2 * UNITS_PER_WORD, -1));
5212 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5213 TREE_SIDE_EFFECTS (t) = 1;
5214 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5216 return std_expand_builtin_va_arg (valist, type);
5219 /* Compute the rounded size of the type. */
5220 align = PARM_BOUNDARY / BITS_PER_UNIT;
5221 size = int_size_in_bytes (type);
5223 ptr = build_pointer_type (type);
5225 /* "Large" types are passed by reference. */
5228 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5229 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5230 TREE_SIDE_EFFECTS (t) = 1;
5232 pptr = build_pointer_type (ptr);
5233 t = build1 (NOP_EXPR, pptr, t);
5234 TREE_SIDE_EFFECTS (t) = 1;
5236 t = build1 (INDIRECT_REF, ptr, t);
5237 TREE_SIDE_EFFECTS (t) = 1;
5241 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5242 build_int_2 (-size, -1));
5244 /* Copied from va-pa.h, but we probably don't need to align
5245 to word size, since we generate and preserve that invariant. */
5246 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5247 build_int_2 ((size > 4 ? -8 : -4), -1));
5249 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5250 TREE_SIDE_EFFECTS (t) = 1;
5252 ofs = (8 - size) % 4;
5255 t = build (PLUS_EXPR, TREE_TYPE (valist), t, build_int_2 (ofs, 0));
5256 TREE_SIDE_EFFECTS (t) = 1;
5259 t = build1 (NOP_EXPR, ptr, t);
5260 TREE_SIDE_EFFECTS (t) = 1;
5264 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
5269 /* This routine handles all the normal conditional branch sequences we
5270 might need to generate. It handles compare immediate vs compare
5271 register, nullification of delay slots, varying length branches,
5272 negated branches, and all combinations of the above. It returns the
5273 output appropriate to emit the branch corresponding to all given
5277 output_cbranch (operands, nullify, length, negated, insn)
5279 int nullify, length, negated;
5282 static char buf[100];
5285 /* A conditional branch to the following instruction (eg the delay slot) is
5286 asking for a disaster. This can happen when not optimizing.
5288 In such cases it is safe to emit nothing. */
5290 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5293 /* If this is a long branch with its delay slot unfilled, set `nullify'
5294 as it can nullify the delay slot and save a nop. */
5295 if (length == 8 && dbr_sequence_length () == 0)
5298 /* If this is a short forward conditional branch which did not get
5299 its delay slot filled, the delay slot can still be nullified. */
5300 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5301 nullify = forward_branch_p (insn);
5303 /* A forward branch over a single nullified insn can be done with a
5304 comclr instruction. This avoids a single cycle penalty due to
5305 mis-predicted branch if we fall through (branch not taken). */
5307 && next_real_insn (insn) != 0
5308 && get_attr_length (next_real_insn (insn)) == 4
5309 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5315 /* All short conditional branches except backwards with an unfilled
5319 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5321 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5322 if (GET_MODE (operands[1]) == DImode)
5325 strcat (buf, "%B3");
5327 strcat (buf, "%S3");
5329 strcat (buf, " %2,%r1,%%r0");
5331 strcat (buf, ",n %2,%r1,%0");
5333 strcat (buf, " %2,%r1,%0");
5336 /* All long conditionals. Note an short backward branch with an
5337 unfilled delay slot is treated just like a long backward branch
5338 with an unfilled delay slot. */
5340 /* Handle weird backwards branch with a filled delay slot
5341 with is nullified. */
5342 if (dbr_sequence_length () != 0
5343 && ! forward_branch_p (insn)
5346 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5347 if (GET_MODE (operands[1]) == DImode)
5350 strcat (buf, "%S3");
5352 strcat (buf, "%B3");
5353 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5355 /* Handle short backwards branch with an unfilled delay slot.
5356 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5357 taken and untaken branches. */
5358 else if (dbr_sequence_length () == 0
5359 && ! forward_branch_p (insn)
5360 && INSN_ADDRESSES_SET_P ()
5361 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5362 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5364 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5365 if (GET_MODE (operands[1]) == DImode)
5368 strcat (buf, "%B3 %2,%r1,%0%#");
5370 strcat (buf, "%S3 %2,%r1,%0%#");
5374 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5375 if (GET_MODE (operands[1]) == DImode)
5378 strcat (buf, "%S3");
5380 strcat (buf, "%B3");
5382 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5384 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5389 /* Very long branch. Right now we only handle these when not
5390 optimizing. See "jump" pattern in pa.md for details. */
5394 /* Create a reversed conditional branch which branches around
5395 the following insns. */
5397 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+20|cmp%I2b,%S3,n %2,%r1,.+20}");
5399 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+20|cmp%I2b,%B3,n %2,%r1,.+20}");
5400 if (GET_MODE (operands[1]) == DImode)
5404 "{com%I2b,*%S3,n %2,%r1,.+20|cmp%I2b,*%S3,n %2,%r1,.+20}");
5407 "{com%I2b,*%B3,n %2,%r1,.+20|cmp%I2b,*%B3,n %2,%r1,.+20}");
5409 output_asm_insn (buf, operands);
5411 /* Output an insn to save %r1. */
5412 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5414 /* Now output a very long branch to the original target. */
5415 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", operands);
5417 /* Now restore the value of %r1 in the delay slot. We're not
5418 optimizing so we know nothing else can be in the delay slot. */
5419 return "ldw -16(%%r30),%%r1";
5422 /* Very long branch when generating PIC code. Right now we only
5423 handle these when not optimizing. See "jump" pattern in pa.md
5428 /* Create a reversed conditional branch which branches around
5429 the following insns. */
5431 strcpy (buf, "{com%I2b,%S3,n %2,%r1,.+28|cmp%I2b,%S3,n %2,%r1,.+28}");
5433 strcpy (buf, "{com%I2b,%B3,n %2,%r1,.+28|cmp%I2b,%B3,n %2,%r1,.+28}");
5434 if (GET_MODE (operands[1]) == DImode)
5437 strcpy (buf, "{com%I2b,*%S3,n %2,%r1,.+28|cmp%I2b,*%S3,n %2,%r1,.+28}");
5439 strcpy (buf, "{com%I2b,*%B3,n %2,%r1,.+28|cmp%I2b,*%B3,n %2,%r1,.+28}");
5441 output_asm_insn (buf, operands);
5443 /* Output an insn to save %r1. */
5444 output_asm_insn ("stw %%r1,-16(%%r30)", operands);
5446 /* Now output a very long PIC branch to the original target. */
5450 xoperands[0] = operands[0];
5451 xoperands[1] = operands[1];
5452 xoperands[2] = operands[2];
5453 xoperands[3] = operands[3];
5454 if (TARGET_SOM || ! TARGET_GAS)
5455 xoperands[4] = gen_label_rtx ();
5457 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5458 if (TARGET_SOM || ! TARGET_GAS)
5460 output_asm_insn ("addil L'%l0-%l4,%%r1", xoperands);
5461 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
5462 CODE_LABEL_NUMBER (xoperands[4]));
5463 output_asm_insn ("ldo R'%l0-%l4(%%r1),%%r1", xoperands);
5467 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5468 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1",
5471 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5474 /* Now restore the value of %r1 in the delay slot. We're not
5475 optimizing so we know nothing else can be in the delay slot. */
5476 return "ldw -16(%%r30),%%r1";
5484 /* This routine handles all the branch-on-bit conditional branch sequences we
5485 might need to generate. It handles nullification of delay slots,
5486 varying length branches, negated branches and all combinations of the
5487 above. it returns the appropriate output template to emit the branch. */
5490 output_bb (operands, nullify, length, negated, insn, which)
5491 rtx *operands ATTRIBUTE_UNUSED;
5492 int nullify, length, negated;
5496 static char buf[100];
5499 /* A conditional branch to the following instruction (eg the delay slot) is
5500 asking for a disaster. I do not think this can happen as this pattern
5501 is only used when optimizing; jump optimization should eliminate the
5502 jump. But be prepared just in case. */
5504 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5507 /* If this is a long branch with its delay slot unfilled, set `nullify'
5508 as it can nullify the delay slot and save a nop. */
5509 if (length == 8 && dbr_sequence_length () == 0)
5512 /* If this is a short forward conditional branch which did not get
5513 its delay slot filled, the delay slot can still be nullified. */
5514 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5515 nullify = forward_branch_p (insn);
5517 /* A forward branch over a single nullified insn can be done with a
5518 extrs instruction. This avoids a single cycle penalty due to
5519 mis-predicted branch if we fall through (branch not taken). */
5522 && next_real_insn (insn) != 0
5523 && get_attr_length (next_real_insn (insn)) == 4
5524 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5531 /* All short conditional branches except backwards with an unfilled
5535 strcpy (buf, "{extrs,|extrw,s,}");
5537 strcpy (buf, "bb,");
5538 if (useskip && GET_MODE (operands[0]) == DImode)
5539 strcpy (buf, "extrd,s,*");
5540 else if (GET_MODE (operands[0]) == DImode)
5541 strcpy (buf, "bb,*");
5542 if ((which == 0 && negated)
5543 || (which == 1 && ! negated))
5548 strcat (buf, " %0,%1,1,%%r0");
5549 else if (nullify && negated)
5550 strcat (buf, ",n %0,%1,%3");
5551 else if (nullify && ! negated)
5552 strcat (buf, ",n %0,%1,%2");
5553 else if (! nullify && negated)
5554 strcat (buf, "%0,%1,%3");
5555 else if (! nullify && ! negated)
5556 strcat (buf, " %0,%1,%2");
5559 /* All long conditionals. Note an short backward branch with an
5560 unfilled delay slot is treated just like a long backward branch
5561 with an unfilled delay slot. */
5563 /* Handle weird backwards branch with a filled delay slot
5564 with is nullified. */
5565 if (dbr_sequence_length () != 0
5566 && ! forward_branch_p (insn)
5569 strcpy (buf, "bb,");
5570 if (GET_MODE (operands[0]) == DImode)
5572 if ((which == 0 && negated)
5573 || (which == 1 && ! negated))
5578 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5580 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5582 /* Handle short backwards branch with an unfilled delay slot.
5583 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5584 taken and untaken branches. */
5585 else if (dbr_sequence_length () == 0
5586 && ! forward_branch_p (insn)
5587 && INSN_ADDRESSES_SET_P ()
5588 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5589 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5591 strcpy (buf, "bb,");
5592 if (GET_MODE (operands[0]) == DImode)
5594 if ((which == 0 && negated)
5595 || (which == 1 && ! negated))
5600 strcat (buf, " %0,%1,%3%#");
5602 strcat (buf, " %0,%1,%2%#");
5606 strcpy (buf, "{extrs,|extrw,s,}");
5607 if (GET_MODE (operands[0]) == DImode)
5608 strcpy (buf, "extrd,s,*");
5609 if ((which == 0 && negated)
5610 || (which == 1 && ! negated))
5614 if (nullify && negated)
5615 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5616 else if (nullify && ! negated)
5617 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5619 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5621 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5631 /* This routine handles all the branch-on-variable-bit conditional branch
5632 sequences we might need to generate. It handles nullification of delay
5633 slots, varying length branches, negated branches and all combinations
5634 of the above. it returns the appropriate output template to emit the
5638 output_bvb (operands, nullify, length, negated, insn, which)
5639 rtx *operands ATTRIBUTE_UNUSED;
5640 int nullify, length, negated;
5644 static char buf[100];
5647 /* A conditional branch to the following instruction (eg the delay slot) is
5648 asking for a disaster. I do not think this can happen as this pattern
5649 is only used when optimizing; jump optimization should eliminate the
5650 jump. But be prepared just in case. */
5652 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5655 /* If this is a long branch with its delay slot unfilled, set `nullify'
5656 as it can nullify the delay slot and save a nop. */
5657 if (length == 8 && dbr_sequence_length () == 0)
5660 /* If this is a short forward conditional branch which did not get
5661 its delay slot filled, the delay slot can still be nullified. */
5662 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5663 nullify = forward_branch_p (insn);
5665 /* A forward branch over a single nullified insn can be done with a
5666 extrs instruction. This avoids a single cycle penalty due to
5667 mis-predicted branch if we fall through (branch not taken). */
5670 && next_real_insn (insn) != 0
5671 && get_attr_length (next_real_insn (insn)) == 4
5672 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5679 /* All short conditional branches except backwards with an unfilled
5683 strcpy (buf, "{vextrs,|extrw,s,}");
5685 strcpy (buf, "{bvb,|bb,}");
5686 if (useskip && GET_MODE (operands[0]) == DImode)
5687 strcpy (buf, "extrd,s,*}");
5688 else if (GET_MODE (operands[0]) == DImode)
5689 strcpy (buf, "bb,*");
5690 if ((which == 0 && negated)
5691 || (which == 1 && ! negated))
5696 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
5697 else if (nullify && negated)
5698 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
5699 else if (nullify && ! negated)
5700 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
5701 else if (! nullify && negated)
5702 strcat (buf, "{%0,%3|%0,%%sar,%3}");
5703 else if (! nullify && ! negated)
5704 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
5707 /* All long conditionals. Note an short backward branch with an
5708 unfilled delay slot is treated just like a long backward branch
5709 with an unfilled delay slot. */
5711 /* Handle weird backwards branch with a filled delay slot
5712 with is nullified. */
5713 if (dbr_sequence_length () != 0
5714 && ! forward_branch_p (insn)
5717 strcpy (buf, "{bvb,|bb,}");
5718 if (GET_MODE (operands[0]) == DImode)
5720 if ((which == 0 && negated)
5721 || (which == 1 && ! negated))
5726 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
5728 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
5730 /* Handle short backwards branch with an unfilled delay slot.
5731 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5732 taken and untaken branches. */
5733 else if (dbr_sequence_length () == 0
5734 && ! forward_branch_p (insn)
5735 && INSN_ADDRESSES_SET_P ()
5736 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5737 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5739 strcpy (buf, "{bvb,|bb,}");
5740 if (GET_MODE (operands[0]) == DImode)
5742 if ((which == 0 && negated)
5743 || (which == 1 && ! negated))
5748 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
5750 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
5754 strcpy (buf, "{vextrs,|extrw,s,}");
5755 if (GET_MODE (operands[0]) == DImode)
5756 strcpy (buf, "extrd,s,*");
5757 if ((which == 0 && negated)
5758 || (which == 1 && ! negated))
5762 if (nullify && negated)
5763 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
5764 else if (nullify && ! negated)
5765 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
5767 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
5769 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
5779 /* Return the output template for emitting a dbra type insn.
5781 Note it may perform some output operations on its own before
5782 returning the final output string. */
5784 output_dbra (operands, insn, which_alternative)
5787 int which_alternative;
5790 /* A conditional branch to the following instruction (eg the delay slot) is
5791 asking for a disaster. Be prepared! */
5793 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5795 if (which_alternative == 0)
5796 return "ldo %1(%0),%0";
5797 else if (which_alternative == 1)
5799 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
5800 output_asm_insn ("ldw -16(%%r30),%4", operands);
5801 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5802 return "{fldws|fldw} -16(%%r30),%0";
5806 output_asm_insn ("ldw %0,%4", operands);
5807 return "ldo %1(%4),%4\n\tstw %4,%0";
5811 if (which_alternative == 0)
5813 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5814 int length = get_attr_length (insn);
5816 /* If this is a long branch with its delay slot unfilled, set `nullify'
5817 as it can nullify the delay slot and save a nop. */
5818 if (length == 8 && dbr_sequence_length () == 0)
5821 /* If this is a short forward conditional branch which did not get
5822 its delay slot filled, the delay slot can still be nullified. */
5823 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5824 nullify = forward_branch_p (insn);
5826 /* Handle short versions first. */
5827 if (length == 4 && nullify)
5828 return "addib,%C2,n %1,%0,%3";
5829 else if (length == 4 && ! nullify)
5830 return "addib,%C2 %1,%0,%3";
5831 else if (length == 8)
5833 /* Handle weird backwards branch with a fulled delay slot
5834 which is nullified. */
5835 if (dbr_sequence_length () != 0
5836 && ! forward_branch_p (insn)
5838 return "addib,%N2,n %1,%0,.+12\n\tb %3";
5839 /* Handle short backwards branch with an unfilled delay slot.
5840 Using a addb;nop rather than addi;bl saves 1 cycle for both
5841 taken and untaken branches. */
5842 else if (dbr_sequence_length () == 0
5843 && ! forward_branch_p (insn)
5844 && INSN_ADDRESSES_SET_P ()
5845 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5846 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5847 return "addib,%C2 %1,%0,%3%#";
5849 /* Handle normal cases. */
5851 return "addi,%N2 %1,%0,%0\n\tb,n %3";
5853 return "addi,%N2 %1,%0,%0\n\tb %3";
5858 /* Deal with gross reload from FP register case. */
5859 else if (which_alternative == 1)
5861 /* Move loop counter from FP register to MEM then into a GR,
5862 increment the GR, store the GR into MEM, and finally reload
5863 the FP register from MEM from within the branch's delay slot. */
5864 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
5866 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
5867 if (get_attr_length (insn) == 24)
5868 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
5870 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5872 /* Deal with gross reload from memory case. */
5875 /* Reload loop counter from memory, the store back to memory
5876 happens in the branch's delay slot. */
5877 output_asm_insn ("ldw %0,%4", operands);
5878 if (get_attr_length (insn) == 12)
5879 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
5881 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
5885 /* Return the output template for emitting a dbra type insn.
5887 Note it may perform some output operations on its own before
5888 returning the final output string. */
5890 output_movb (operands, insn, which_alternative, reverse_comparison)
5893 int which_alternative;
5894 int reverse_comparison;
5897 /* A conditional branch to the following instruction (eg the delay slot) is
5898 asking for a disaster. Be prepared! */
5900 if (next_active_insn (JUMP_LABEL (insn)) == next_active_insn (insn))
5902 if (which_alternative == 0)
5903 return "copy %1,%0";
5904 else if (which_alternative == 1)
5906 output_asm_insn ("stw %1,-16(%%r30)", operands);
5907 return "{fldws|fldw} -16(%%r30),%0";
5909 else if (which_alternative == 2)
5915 /* Support the second variant. */
5916 if (reverse_comparison)
5917 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
5919 if (which_alternative == 0)
5921 int nullify = INSN_ANNULLED_BRANCH_P (insn);
5922 int length = get_attr_length (insn);
5924 /* If this is a long branch with its delay slot unfilled, set `nullify'
5925 as it can nullify the delay slot and save a nop. */
5926 if (length == 8 && dbr_sequence_length () == 0)
5929 /* If this is a short forward conditional branch which did not get
5930 its delay slot filled, the delay slot can still be nullified. */
5931 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5932 nullify = forward_branch_p (insn);
5934 /* Handle short versions first. */
5935 if (length == 4 && nullify)
5936 return "movb,%C2,n %1,%0,%3";
5937 else if (length == 4 && ! nullify)
5938 return "movb,%C2 %1,%0,%3";
5939 else if (length == 8)
5941 /* Handle weird backwards branch with a filled delay slot
5942 which is nullified. */
5943 if (dbr_sequence_length () != 0
5944 && ! forward_branch_p (insn)
5946 return "movb,%N2,n %1,%0,.+12\n\tb %3";
5948 /* Handle short backwards branch with an unfilled delay slot.
5949 Using a movb;nop rather than or;bl saves 1 cycle for both
5950 taken and untaken branches. */
5951 else if (dbr_sequence_length () == 0
5952 && ! forward_branch_p (insn)
5953 && INSN_ADDRESSES_SET_P ()
5954 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5955 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5956 return "movb,%C2 %1,%0,%3%#";
5957 /* Handle normal cases. */
5959 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
5961 return "or,%N2 %1,%%r0,%0\n\tb %3";
5966 /* Deal with gross reload from FP register case. */
5967 else if (which_alternative == 1)
5969 /* Move loop counter from FP register to MEM then into a GR,
5970 increment the GR, store the GR into MEM, and finally reload
5971 the FP register from MEM from within the branch's delay slot. */
5972 output_asm_insn ("stw %1,-16(%%r30)", operands);
5973 if (get_attr_length (insn) == 12)
5974 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
5976 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
5978 /* Deal with gross reload from memory case. */
5979 else if (which_alternative == 2)
5981 /* Reload loop counter from memory, the store back to memory
5982 happens in the branch's delay slot. */
5983 if (get_attr_length (insn) == 8)
5984 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
5986 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
5988 /* Handle SAR as a destination. */
5991 if (get_attr_length (insn) == 8)
5992 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
5994 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
5999 /* INSN is a millicode call. It may have an unconditional jump in its delay
6002 CALL_DEST is the routine we are calling. */
6005 output_millicode_call (insn, call_dest)
6009 int attr_length = get_attr_length (insn);
6010 int seq_length = dbr_sequence_length ();
6015 xoperands[3] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6017 /* Handle common case -- empty delay slot or no jump in the delay slot,
6018 and we're sure that the branch will reach the beginning of the $CODE$
6019 subspace. The within reach form of the $$sh_func_adrs call has
6020 a length of 28 and attribute type of multi. This length is the
6021 same as the maximum length of an out of reach PIC call to $$div. */
6022 if ((seq_length == 0
6023 && (attr_length == 8
6024 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6026 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6027 && attr_length == 4))
6029 xoperands[0] = call_dest;
6030 output_asm_insn ("{bl|b,l} %0,%3%#", xoperands);
6034 /* This call may not reach the beginning of the $CODE$ subspace. */
6035 if (attr_length > 8)
6037 int delay_insn_deleted = 0;
6039 /* We need to emit an inline long-call branch. */
6041 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6043 /* A non-jump insn in the delay slot. By definition we can
6044 emit this insn before the call. */
6045 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6047 /* Now delete the delay insn. */
6048 PUT_CODE (NEXT_INSN (insn), NOTE);
6049 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6050 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6051 delay_insn_deleted = 1;
6054 /* PIC long millicode call sequence. */
6057 xoperands[0] = call_dest;
6058 if (TARGET_SOM || ! TARGET_GAS)
6059 xoperands[1] = gen_label_rtx ();
6061 /* Get our address + 8 into %r1. */
6062 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6064 if (TARGET_SOM || ! TARGET_GAS)
6066 /* Add %r1 to the offset of our target from the next insn. */
6067 output_asm_insn ("addil L%%%0-%1,%%r1", xoperands);
6068 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6069 CODE_LABEL_NUMBER (xoperands[1]));
6070 output_asm_insn ("ldo R%%%0-%1(%%r1),%%r1", xoperands);
6074 output_asm_insn ("addil L%%%0-$PIC_pcrel$0+4,%%r1", xoperands);
6075 output_asm_insn ("ldo R%%%0-$PIC_pcrel$0+8(%%r1),%%r1",
6079 /* Get the return address into %r31. */
6080 output_asm_insn ("blr 0,%3", xoperands);
6082 /* Branch to our target which is in %r1. */
6083 output_asm_insn ("bv,n %%r0(%%r1)", xoperands);
6085 /* Empty delay slot. Note this insn gets fetched twice and
6086 executed once. To be safe we use a nop. */
6087 output_asm_insn ("nop", xoperands);
6089 /* Pure portable runtime doesn't allow be/ble; we also don't have
6090 PIC support in the assembler/linker, so this sequence is needed. */
6091 else if (TARGET_PORTABLE_RUNTIME)
6093 xoperands[0] = call_dest;
6094 /* Get the address of our target into %r29. */
6095 output_asm_insn ("ldil L%%%0,%%r29", xoperands);
6096 output_asm_insn ("ldo R%%%0(%%r29),%%r29", xoperands);
6098 /* Get our return address into %r31. */
6099 output_asm_insn ("blr %%r0,%3", xoperands);
6101 /* Jump to our target address in %r29. */
6102 output_asm_insn ("bv,n %%r0(%%r29)", xoperands);
6104 /* Empty delay slot. Note this insn gets fetched twice and
6105 executed once. To be safe we use a nop. */
6106 output_asm_insn ("nop", xoperands);
6108 /* If we're allowed to use be/ble instructions, then this is the
6109 best sequence to use for a long millicode call. */
6112 xoperands[0] = call_dest;
6113 output_asm_insn ("ldil L%%%0,%3", xoperands);
6115 output_asm_insn ("be,l R%%%0(%%sr4,%3),%%sr0,%%r31", xoperands);
6117 output_asm_insn ("ble R%%%0(%%sr4,%3)", xoperands);
6118 output_asm_insn ("nop", xoperands);
6121 /* If we had a jump in the call's delay slot, output it now. */
6122 if (seq_length != 0 && !delay_insn_deleted)
6124 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6125 output_asm_insn ("b,n %0", xoperands);
6127 /* Now delete the delay insn. */
6128 PUT_CODE (NEXT_INSN (insn), NOTE);
6129 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6130 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6135 /* This call has an unconditional jump in its delay slot and the
6136 call is known to reach its target or the beginning of the current
6139 /* Use the containing sequence insn's address. */
6140 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6142 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6143 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6145 /* If the branch was too far away, emit a normal call followed
6146 by a nop, followed by the unconditional branch.
6148 If the branch is close, then adjust %r2 from within the
6149 call's delay slot. */
6151 xoperands[0] = call_dest;
6152 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6153 if (! VAL_14_BITS_P (distance))
6154 output_asm_insn ("{bl|b,l} %0,%3\n\tnop\n\tb,n %1", xoperands);
6157 xoperands[2] = gen_label_rtx ();
6158 output_asm_insn ("\n\t{bl|b,l} %0,%3\n\tldo %1-%2(%3),%3",
6160 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6161 CODE_LABEL_NUMBER (xoperands[2]));
6164 /* Delete the jump. */
6165 PUT_CODE (NEXT_INSN (insn), NOTE);
6166 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6167 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6171 /* INSN is either a function call. It may have an unconditional jump
6174 CALL_DEST is the routine we are calling. */
6177 output_call (insn, call_dest, sibcall)
6182 int attr_length = get_attr_length (insn);
6183 int seq_length = dbr_sequence_length ();
6188 /* Handle common case -- empty delay slot or no jump in the delay slot,
6189 and we're sure that the branch will reach the beginning of the $CODE$
6191 if ((seq_length == 0 && attr_length == 12)
6193 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6194 && attr_length == 8))
6196 xoperands[0] = call_dest;
6197 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6198 output_asm_insn ("{bl|b,l} %0,%1%#", xoperands);
6202 /* This call may not reach the beginning of the $CODE$ subspace. */
6203 if (attr_length > 12)
6205 int delay_insn_deleted = 0;
6209 /* We need to emit an inline long-call branch. Furthermore,
6210 because we're changing a named function call into an indirect
6211 function call well after the parameters have been set up, we
6212 need to make sure any FP args appear in both the integer
6213 and FP registers. Also, we need move any delay slot insn
6214 out of the delay slot. And finally, we can't rely on the linker
6215 being able to fix the call to $$dyncall! -- Yuk!. */
6217 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6219 /* A non-jump insn in the delay slot. By definition we can
6220 emit this insn before the call (and in fact before argument
6222 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6224 /* Now delete the delay insn. */
6225 PUT_CODE (NEXT_INSN (insn), NOTE);
6226 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6227 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6228 delay_insn_deleted = 1;
6231 /* Now copy any FP arguments into integer registers. */
6232 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6234 int arg_mode, regno;
6235 rtx use = XEXP (link, 0);
6236 if (! (GET_CODE (use) == USE
6237 && GET_CODE (XEXP (use, 0)) == REG
6238 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6241 arg_mode = GET_MODE (XEXP (use, 0));
6242 regno = REGNO (XEXP (use, 0));
6243 /* Is it a floating point register? */
6244 if (regno >= 32 && regno <= 39)
6246 /* Copy from the FP register into an integer register
6248 if (arg_mode == SFmode)
6250 xoperands[0] = XEXP (use, 0);
6251 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6252 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)",
6254 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6258 xoperands[0] = XEXP (use, 0);
6259 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6260 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)",
6262 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6263 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6268 /* Don't have to worry about TARGET_PORTABLE_RUNTIME here since
6269 we don't have any direct calls in that case. */
6272 const char *name = XSTR (call_dest, 0);
6274 /* See if we have already put this function on the list
6275 of deferred plabels. This list is generally small,
6276 so a liner search is not too ugly. If it proves too
6277 slow replace it with something faster. */
6278 for (i = 0; i < n_deferred_plabels; i++)
6279 if (strcmp (name, deferred_plabels[i].name) == 0)
6282 /* If the deferred plabel list is empty, or this entry was
6283 not found on the list, create a new entry on the list. */
6284 if (deferred_plabels == NULL || i == n_deferred_plabels)
6286 const char *real_name;
6288 if (deferred_plabels == 0)
6289 deferred_plabels = (struct deferred_plabel *)
6290 ggc_alloc (sizeof (struct deferred_plabel));
6292 deferred_plabels = (struct deferred_plabel *)
6293 ggc_realloc (deferred_plabels,
6294 ((n_deferred_plabels + 1)
6295 * sizeof (struct deferred_plabel)));
6297 i = n_deferred_plabels++;
6298 deferred_plabels[i].internal_label = gen_label_rtx ();
6299 deferred_plabels[i].name = ggc_strdup (name);
6301 /* Gross. We have just implicitly taken the address of this
6302 function, mark it as such. */
6303 real_name = (*targetm.strip_name_encoding) (name);
6304 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
6307 /* We have to load the address of the function using a procedure
6308 label (plabel). Inline plabels can lose for PIC and other
6309 cases, so avoid them by creating a 32bit plabel in the data
6313 xoperands[0] = deferred_plabels[i].internal_label;
6314 if (TARGET_SOM || ! TARGET_GAS)
6315 xoperands[1] = gen_label_rtx ();
6317 output_asm_insn ("addil LT%%%0,%%r19", xoperands);
6318 output_asm_insn ("ldw RT%%%0(%%r1),%%r22", xoperands);
6319 output_asm_insn ("ldw 0(%%r22),%%r22", xoperands);
6321 /* Get our address + 8 into %r1. */
6322 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6324 if (TARGET_SOM || ! TARGET_GAS)
6326 /* Add %r1 to the offset of dyncall from the next insn. */
6327 output_asm_insn ("addil L%%$$dyncall-%1,%%r1", xoperands);
6328 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6329 CODE_LABEL_NUMBER (xoperands[1]));
6330 output_asm_insn ("ldo R%%$$dyncall-%1(%%r1),%%r1", xoperands);
6334 output_asm_insn ("addil L%%$$dyncall-$PIC_pcrel$0+4,%%r1",
6336 output_asm_insn ("ldo R%%$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
6340 /* Get the return address into %r31. */
6341 output_asm_insn ("blr %%r0,%%r31", xoperands);
6343 /* Branch to our target which is in %r1. */
6344 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6348 /* This call never returns, so we do not need to fix the
6350 output_asm_insn ("nop", xoperands);
6354 /* Copy the return address into %r2 also. */
6355 output_asm_insn ("copy %%r31,%%r2", xoperands);
6360 xoperands[0] = deferred_plabels[i].internal_label;
6362 /* Get the address of our target into %r22. */
6363 output_asm_insn ("addil LR%%%0-$global$,%%r27", xoperands);
6364 output_asm_insn ("ldw RR%%%0-$global$(%%r1),%%r22", xoperands);
6366 /* Get the high part of the address of $dyncall into %r2, then
6367 add in the low part in the branch instruction. */
6368 output_asm_insn ("ldil L%%$$dyncall,%%r2", xoperands);
6370 output_asm_insn ("be,l R%%$$dyncall(%%sr4,%%r2),%%sr0,%%r31",
6373 output_asm_insn ("ble R%%$$dyncall(%%sr4,%%r2)", xoperands);
6377 /* This call never returns, so we do not need to fix the
6379 output_asm_insn ("nop", xoperands);
6383 /* Copy the return address into %r2 also. */
6384 output_asm_insn ("copy %%r31,%%r2", xoperands);
6389 /* If we had a jump in the call's delay slot, output it now. */
6390 if (seq_length != 0 && !delay_insn_deleted)
6392 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6393 output_asm_insn ("b,n %0", xoperands);
6395 /* Now delete the delay insn. */
6396 PUT_CODE (NEXT_INSN (insn), NOTE);
6397 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6398 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6403 /* This call has an unconditional jump in its delay slot and the
6404 call is known to reach its target or the beginning of the current
6407 /* Use the containing sequence insn's address. */
6408 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6410 distance = INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6411 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8;
6413 /* If the branch is too far away, emit a normal call followed
6414 by a nop, followed by the unconditional branch. If the branch
6415 is close, then adjust %r2 in the call's delay slot. */
6417 xoperands[0] = call_dest;
6418 xoperands[1] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6419 if (! VAL_14_BITS_P (distance))
6420 output_asm_insn ("{bl|b,l} %0,%%r2\n\tnop\n\tb,n %1", xoperands);
6423 xoperands[3] = gen_label_rtx ();
6424 output_asm_insn ("\n\t{bl|b,l} %0,%%r2\n\tldo %1-%3(%%r2),%%r2",
6426 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
6427 CODE_LABEL_NUMBER (xoperands[3]));
6430 /* Delete the jump. */
6431 PUT_CODE (NEXT_INSN (insn), NOTE);
6432 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6433 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6437 /* In HPUX 8.0's shared library scheme, special relocations are needed
6438 for function labels if they might be passed to a function
6439 in a shared library (because shared libraries don't live in code
6440 space), and special magic is needed to construct their address. */
6443 hppa_encode_label (sym)
6446 const char *str = XSTR (sym, 0);
6447 int len = strlen (str) + 1;
6450 p = newstr = alloca (len + 1);
6459 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
6463 pa_encode_section_info (decl, first)
6467 if (first && TEXT_SPACE_P (decl))
6470 if (TREE_CODE (decl) == FUNCTION_DECL
6471 || TREE_CODE (decl) == VAR_DECL)
6472 rtl = DECL_RTL (decl);
6474 rtl = TREE_CST_RTL (decl);
6475 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
6476 if (TREE_CODE (decl) == FUNCTION_DECL)
6477 hppa_encode_label (XEXP (DECL_RTL (decl), 0));
6481 /* This is sort of inverse to pa_encode_section_info. */
6484 pa_strip_name_encoding (str)
6487 return str + (*str == '*' || *str == '@');
6491 function_label_operand (op, mode)
6493 enum machine_mode mode ATTRIBUTE_UNUSED;
6495 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
6498 /* Returns 1 if OP is a function label involved in a simple addition
6499 with a constant. Used to keep certain patterns from matching
6500 during instruction combination. */
6502 is_function_label_plus_const (op)
6505 /* Strip off any CONST. */
6506 if (GET_CODE (op) == CONST)
6509 return (GET_CODE (op) == PLUS
6510 && function_label_operand (XEXP (op, 0), Pmode)
6511 && GET_CODE (XEXP (op, 1)) == CONST_INT);
6514 /* Output assembly code for a thunk to FUNCTION. */
6517 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, function)
6520 HOST_WIDE_INT delta;
6523 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
6524 static unsigned int current_thunk_number;
6527 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
6528 lab = (*targetm.strip_name_encoding) (label);
6529 target_name = (*targetm.strip_name_encoding) (target_name);
6530 /* FIXME: total_code_bytes is not handled correctly in files with
6532 pa_output_function_prologue (file, 0);
6533 if (VAL_14_BITS_P (delta))
6535 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6537 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6538 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6539 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6540 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6541 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6542 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6543 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6544 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6545 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
6546 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6547 fprintf (file, "(%%r26),%%r26\n");
6551 fprintf (file, "\tb %s\n\tldo ", target_name);
6552 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6553 fprintf (file, "(%%r26),%%r26\n");
6558 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6560 fprintf (file, "\taddil L%%");
6561 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6562 fprintf (file, ",%%r26\n\tldo R%%");
6563 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6564 fprintf (file, "(%%r1),%%r26\n");
6565 fprintf (file, "\taddil LT%%%s,%%r19\n", lab);
6566 fprintf (file, "\tldw RT%%%s(%%r1),%%r22\n", lab);
6567 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6568 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
6569 fprintf (file, "\tdepi 0,31,2,%%r22\n");
6570 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
6571 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
6572 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n\tmtsp %%r1,%%sr0\n");
6573 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
6577 fprintf (file, "\taddil L%%");
6578 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6579 fprintf (file, ",%%r26\n\tb %s\n\tldo R%%", target_name);
6580 fprintf (file, HOST_WIDE_INT_PRINT_DEC, delta);
6581 fprintf (file, "(%%r1),%%r26\n");
6585 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
6586 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
6589 fprintf (file, "\t.align 4\n");
6590 ASM_OUTPUT_INTERNAL_LABEL (file, "LTHN", current_thunk_number);
6591 fprintf (file, "\t.word P%%%s\n", target_name);
6592 function_section (thunk_fndecl);
6594 current_thunk_number++;
6597 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6598 use in fmpyadd instructions. */
6600 fmpyaddoperands (operands)
6603 enum machine_mode mode = GET_MODE (operands[0]);
6605 /* Must be a floating point mode. */
6606 if (mode != SFmode && mode != DFmode)
6609 /* All modes must be the same. */
6610 if (! (mode == GET_MODE (operands[1])
6611 && mode == GET_MODE (operands[2])
6612 && mode == GET_MODE (operands[3])
6613 && mode == GET_MODE (operands[4])
6614 && mode == GET_MODE (operands[5])))
6617 /* All operands must be registers. */
6618 if (! (GET_CODE (operands[1]) == REG
6619 && GET_CODE (operands[2]) == REG
6620 && GET_CODE (operands[3]) == REG
6621 && GET_CODE (operands[4]) == REG
6622 && GET_CODE (operands[5]) == REG))
6625 /* Only 2 real operands to the addition. One of the input operands must
6626 be the same as the output operand. */
6627 if (! rtx_equal_p (operands[3], operands[4])
6628 && ! rtx_equal_p (operands[3], operands[5]))
6631 /* Inout operand of add can not conflict with any operands from multiply. */
6632 if (rtx_equal_p (operands[3], operands[0])
6633 || rtx_equal_p (operands[3], operands[1])
6634 || rtx_equal_p (operands[3], operands[2]))
6637 /* multiply can not feed into addition operands. */
6638 if (rtx_equal_p (operands[4], operands[0])
6639 || rtx_equal_p (operands[5], operands[0]))
6642 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6644 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6645 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6646 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6647 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6648 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6649 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6652 /* Passed. Operands are suitable for fmpyadd. */
6656 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
6657 use in fmpysub instructions. */
6659 fmpysuboperands (operands)
6662 enum machine_mode mode = GET_MODE (operands[0]);
6664 /* Must be a floating point mode. */
6665 if (mode != SFmode && mode != DFmode)
6668 /* All modes must be the same. */
6669 if (! (mode == GET_MODE (operands[1])
6670 && mode == GET_MODE (operands[2])
6671 && mode == GET_MODE (operands[3])
6672 && mode == GET_MODE (operands[4])
6673 && mode == GET_MODE (operands[5])))
6676 /* All operands must be registers. */
6677 if (! (GET_CODE (operands[1]) == REG
6678 && GET_CODE (operands[2]) == REG
6679 && GET_CODE (operands[3]) == REG
6680 && GET_CODE (operands[4]) == REG
6681 && GET_CODE (operands[5]) == REG))
6684 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
6685 operation, so operands[4] must be the same as operand[3]. */
6686 if (! rtx_equal_p (operands[3], operands[4]))
6689 /* multiply can not feed into subtraction. */
6690 if (rtx_equal_p (operands[5], operands[0]))
6693 /* Inout operand of sub can not conflict with any operands from multiply. */
6694 if (rtx_equal_p (operands[3], operands[0])
6695 || rtx_equal_p (operands[3], operands[1])
6696 || rtx_equal_p (operands[3], operands[2]))
6699 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
6701 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
6702 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
6703 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
6704 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
6705 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
6706 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
6709 /* Passed. Operands are suitable for fmpysub. */
6714 plus_xor_ior_operator (op, mode)
6716 enum machine_mode mode ATTRIBUTE_UNUSED;
6718 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
6719 || GET_CODE (op) == IOR);
6722 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
6723 constants for shadd instructions. */
6725 shadd_constant_p (val)
6728 if (val == 2 || val == 4 || val == 8)
6734 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
6735 the valid constant for shadd instructions. */
6737 shadd_operand (op, mode)
6739 enum machine_mode mode ATTRIBUTE_UNUSED;
6741 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
6744 /* Return 1 if OP is valid as a base register in a reg + reg address. */
6747 basereg_operand (op, mode)
6749 enum machine_mode mode;
6751 /* cse will create some unscaled indexed addresses, however; it
6752 generally isn't a win on the PA, so avoid creating unscaled
6753 indexed addresses until after cse is finished. */
6754 if (!cse_not_expected)
6757 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
6758 we don't have to worry about the braindamaged implicit space
6759 register selection from the basereg. */
6760 if (TARGET_NO_SPACE_REGS)
6761 return (GET_CODE (op) == REG);
6763 /* While it's always safe to index off the frame pointer, it's not
6764 always profitable, particularly when the frame pointer is being
6766 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
6769 return (GET_CODE (op) == REG
6771 && register_operand (op, mode));
6774 /* Return 1 if this operand is anything other than a hard register. */
6777 non_hard_reg_operand (op, mode)
6779 enum machine_mode mode ATTRIBUTE_UNUSED;
6781 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
6784 /* Return 1 if INSN branches forward. Should be using insn_addresses
6785 to avoid walking through all the insns... */
6787 forward_branch_p (insn)
6790 rtx label = JUMP_LABEL (insn);
6797 insn = NEXT_INSN (insn);
6800 return (insn == label);
6803 /* Return 1 if OP is an equality comparison, else return 0. */
6805 eq_neq_comparison_operator (op, mode)
6807 enum machine_mode mode ATTRIBUTE_UNUSED;
6809 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
6812 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
6814 movb_comparison_operator (op, mode)
6816 enum machine_mode mode ATTRIBUTE_UNUSED;
6818 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
6819 || GET_CODE (op) == LT || GET_CODE (op) == GE);
6822 /* Return 1 if INSN is in the delay slot of a call instruction. */
6824 jump_in_call_delay (insn)
6828 if (GET_CODE (insn) != JUMP_INSN)
6831 if (PREV_INSN (insn)
6832 && PREV_INSN (PREV_INSN (insn))
6833 && GET_CODE (next_active_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
6835 rtx test_insn = next_active_insn (PREV_INSN (PREV_INSN (insn)));
6837 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
6838 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
6845 /* Output an unconditional move and branch insn. */
6848 output_parallel_movb (operands, length)
6852 /* These are the cases in which we win. */
6854 return "mov%I1b,tr %1,%0,%2";
6856 /* None of these cases wins, but they don't lose either. */
6857 if (dbr_sequence_length () == 0)
6859 /* Nothing in the delay slot, fake it by putting the combined
6860 insn (the copy or add) in the delay slot of a bl. */
6861 if (GET_CODE (operands[1]) == CONST_INT)
6862 return "b %2\n\tldi %1,%0";
6864 return "b %2\n\tcopy %1,%0";
6868 /* Something in the delay slot, but we've got a long branch. */
6869 if (GET_CODE (operands[1]) == CONST_INT)
6870 return "ldi %1,%0\n\tb %2";
6872 return "copy %1,%0\n\tb %2";
6876 /* Output an unconditional add and branch insn. */
6879 output_parallel_addb (operands, length)
6883 /* To make life easy we want operand0 to be the shared input/output
6884 operand and operand1 to be the readonly operand. */
6885 if (operands[0] == operands[1])
6886 operands[1] = operands[2];
6888 /* These are the cases in which we win. */
6890 return "add%I1b,tr %1,%0,%3";
6892 /* None of these cases win, but they don't lose either. */
6893 if (dbr_sequence_length () == 0)
6895 /* Nothing in the delay slot, fake it by putting the combined
6896 insn (the copy or add) in the delay slot of a bl. */
6897 return "b %3\n\tadd%I1 %1,%0,%0";
6901 /* Something in the delay slot, but we've got a long branch. */
6902 return "add%I1 %1,%0,%0\n\tb %3";
6906 /* Return nonzero if INSN (a jump insn) immediately follows a call
6907 to a named function. This is used to avoid filling the delay slot
6908 of the jump since it can usually be eliminated by modifying RP in
6909 the delay slot of the call. */
6912 following_call (insn)
6915 if (! TARGET_JUMP_IN_DELAY)
6918 /* Find the previous real insn, skipping NOTEs. */
6919 insn = PREV_INSN (insn);
6920 while (insn && GET_CODE (insn) == NOTE)
6921 insn = PREV_INSN (insn);
6923 /* Check for CALL_INSNs and millicode calls. */
6925 && ((GET_CODE (insn) == CALL_INSN
6926 && get_attr_type (insn) != TYPE_DYNCALL)
6927 || (GET_CODE (insn) == INSN
6928 && GET_CODE (PATTERN (insn)) != SEQUENCE
6929 && GET_CODE (PATTERN (insn)) != USE
6930 && GET_CODE (PATTERN (insn)) != CLOBBER
6931 && get_attr_type (insn) == TYPE_MILLI)))
6937 /* We use this hook to perform a PA specific optimization which is difficult
6938 to do in earlier passes.
6940 We want the delay slots of branches within jump tables to be filled.
6941 None of the compiler passes at the moment even has the notion that a
6942 PA jump table doesn't contain addresses, but instead contains actual
6945 Because we actually jump into the table, the addresses of each entry
6946 must stay constant in relation to the beginning of the table (which
6947 itself must stay constant relative to the instruction to jump into
6948 it). I don't believe we can guarantee earlier passes of the compiler
6949 will adhere to those rules.
6951 So, late in the compilation process we find all the jump tables, and
6952 expand them into real code -- eg each entry in the jump table vector
6953 will get an appropriate label followed by a jump to the final target.
6955 Reorg and the final jump pass can then optimize these branches and
6956 fill their delay slots. We end up with smaller, more efficient code.
6958 The jump instructions within the table are special; we must be able
6959 to identify them during assembly output (if the jumps don't get filled
6960 we need to emit a nop rather than nullifying the delay slot)). We
6961 identify jumps in switch tables by marking the SET with DImode.
6963 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
6964 insns. This serves two purposes, first it prevents jump.c from
6965 noticing that the last N entries in the table jump to the instruction
6966 immediately after the table and deleting the jumps. Second, those
6967 insns mark where we should emit .begin_brtab and .end_brtab directives
6968 when using GAS (allows for better link time optimizations). */
6976 remove_useless_addtr_insns (insns, 1);
6978 if (pa_cpu < PROCESSOR_8000)
6979 pa_combine_instructions (get_insns ());
6982 /* This is fairly cheap, so always run it if optimizing. */
6983 if (optimize > 0 && !TARGET_BIG_SWITCH)
6985 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
6986 insns = get_insns ();
6987 for (insn = insns; insn; insn = NEXT_INSN (insn))
6989 rtx pattern, tmp, location;
6990 unsigned int length, i;
6992 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
6993 if (GET_CODE (insn) != JUMP_INSN
6994 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
6995 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
6998 /* Emit marker for the beginning of the branch table. */
6999 emit_insn_before (gen_begin_brtab (), insn);
7001 pattern = PATTERN (insn);
7002 location = PREV_INSN (insn);
7003 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7005 for (i = 0; i < length; i++)
7007 /* Emit a label before each jump to keep jump.c from
7008 removing this code. */
7009 tmp = gen_label_rtx ();
7010 LABEL_NUSES (tmp) = 1;
7011 emit_label_after (tmp, location);
7012 location = NEXT_INSN (location);
7014 if (GET_CODE (pattern) == ADDR_VEC)
7016 /* Emit the jump itself. */
7017 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7018 tmp = emit_jump_insn_after (tmp, location);
7019 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7020 /* It is easy to rely on the branch table markers
7021 during assembly output to trigger the correct code
7022 for a switch table jump with an unfilled delay slot,
7024 However, that requires state and assumes that we look
7027 We can't make such assumptions when computing the length
7028 of instructions. Ugh. We could walk the insn chain to
7029 determine if this instruction is in a branch table, but
7030 that can get rather expensive, particularly during the
7031 branch shortening phase of the compiler.
7033 So instead we mark this jump as being special. This is
7034 far from ideal and knows that no code after this will
7035 muck around with the mode of the JUMP_INSN itself. */
7036 PUT_MODE (tmp, SImode);
7037 LABEL_NUSES (JUMP_LABEL (tmp))++;
7038 location = NEXT_INSN (location);
7042 /* Emit the jump itself. */
7043 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7044 tmp = emit_jump_insn_after (tmp, location);
7045 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7046 /* It is easy to rely on the branch table markers
7047 during assembly output to trigger the correct code
7048 for a switch table jump with an unfilled delay slot,
7050 However, that requires state and assumes that we look
7053 We can't make such assumptions when computing the length
7054 of instructions. Ugh. We could walk the insn chain to
7055 determine if this instruction is in a branch table, but
7056 that can get rather expensive, particularly during the
7057 branch shortening phase of the compiler.
7059 So instead we mark this jump as being special. This is
7060 far from ideal and knows that no code after this will
7061 muck around with the mode of the JUMP_INSN itself. */
7062 PUT_MODE (tmp, SImode);
7063 LABEL_NUSES (JUMP_LABEL (tmp))++;
7064 location = NEXT_INSN (location);
7067 /* Emit a BARRIER after the jump. */
7068 emit_barrier_after (location);
7069 location = NEXT_INSN (location);
7072 /* Emit marker for the end of the branch table. */
7073 emit_insn_before (gen_end_brtab (), location);
7074 location = NEXT_INSN (location);
7075 emit_barrier_after (location);
7077 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7083 /* Sill need an end_brtab insn. */
7084 insns = get_insns ();
7085 for (insn = insns; insn; insn = NEXT_INSN (insn))
7087 /* Find an ADDR_VEC insn. */
7088 if (GET_CODE (insn) != JUMP_INSN
7089 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7090 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7093 /* Now generate markers for the beginning and end of the
7095 emit_insn_before (gen_begin_brtab (), insn);
7096 emit_insn_after (gen_end_brtab (), insn);
7101 /* The PA has a number of odd instructions which can perform multiple
7102 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7103 it may be profitable to combine two instructions into one instruction
7104 with two outputs. It's not profitable PA2.0 machines because the
7105 two outputs would take two slots in the reorder buffers.
7107 This routine finds instructions which can be combined and combines
7108 them. We only support some of the potential combinations, and we
7109 only try common ways to find suitable instructions.
7111 * addb can add two registers or a register and a small integer
7112 and jump to a nearby (+-8k) location. Normally the jump to the
7113 nearby location is conditional on the result of the add, but by
7114 using the "true" condition we can make the jump unconditional.
7115 Thus addb can perform two independent operations in one insn.
7117 * movb is similar to addb in that it can perform a reg->reg
7118 or small immediate->reg copy and jump to a nearby (+-8k location).
7120 * fmpyadd and fmpysub can perform a FP multiply and either an
7121 FP add or FP sub if the operands of the multiply and add/sub are
7122 independent (there are other minor restrictions). Note both
7123 the fmpy and fadd/fsub can in theory move to better spots according
7124 to data dependencies, but for now we require the fmpy stay at a
7127 * Many of the memory operations can perform pre & post updates
7128 of index registers. GCC's pre/post increment/decrement addressing
7129 is far too simple to take advantage of all the possibilities. This
7130 pass may not be suitable since those insns may not be independent.
7132 * comclr can compare two ints or an int and a register, nullify
7133 the following instruction and zero some other register. This
7134 is more difficult to use as it's harder to find an insn which
7135 will generate a comclr than finding something like an unconditional
7136 branch. (conditional moves & long branches create comclr insns).
7138 * Most arithmetic operations can conditionally skip the next
7139 instruction. They can be viewed as "perform this operation
7140 and conditionally jump to this nearby location" (where nearby
7141 is an insns away). These are difficult to use due to the
7142 branch length restrictions. */
7145 pa_combine_instructions (insns)
7146 rtx insns ATTRIBUTE_UNUSED;
7150 /* This can get expensive since the basic algorithm is on the
7151 order of O(n^2) (or worse). Only do it for -O2 or higher
7152 levels of optimization. */
7156 /* Walk down the list of insns looking for "anchor" insns which
7157 may be combined with "floating" insns. As the name implies,
7158 "anchor" instructions don't move, while "floating" insns may
7160 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7161 new = make_insn_raw (new);
7163 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7165 enum attr_pa_combine_type anchor_attr;
7166 enum attr_pa_combine_type floater_attr;
7168 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7169 Also ignore any special USE insns. */
7170 if ((GET_CODE (anchor) != INSN
7171 && GET_CODE (anchor) != JUMP_INSN
7172 && GET_CODE (anchor) != CALL_INSN)
7173 || GET_CODE (PATTERN (anchor)) == USE
7174 || GET_CODE (PATTERN (anchor)) == CLOBBER
7175 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7176 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7179 anchor_attr = get_attr_pa_combine_type (anchor);
7180 /* See if anchor is an insn suitable for combination. */
7181 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7182 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7183 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7184 && ! forward_branch_p (anchor)))
7188 for (floater = PREV_INSN (anchor);
7190 floater = PREV_INSN (floater))
7192 if (GET_CODE (floater) == NOTE
7193 || (GET_CODE (floater) == INSN
7194 && (GET_CODE (PATTERN (floater)) == USE
7195 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7198 /* Anything except a regular INSN will stop our search. */
7199 if (GET_CODE (floater) != INSN
7200 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7201 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7207 /* See if FLOATER is suitable for combination with the
7209 floater_attr = get_attr_pa_combine_type (floater);
7210 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7211 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7212 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7213 && floater_attr == PA_COMBINE_TYPE_FMPY))
7215 /* If ANCHOR and FLOATER can be combined, then we're
7216 done with this pass. */
7217 if (pa_can_combine_p (new, anchor, floater, 0,
7218 SET_DEST (PATTERN (floater)),
7219 XEXP (SET_SRC (PATTERN (floater)), 0),
7220 XEXP (SET_SRC (PATTERN (floater)), 1)))
7224 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7225 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7227 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7229 if (pa_can_combine_p (new, anchor, floater, 0,
7230 SET_DEST (PATTERN (floater)),
7231 XEXP (SET_SRC (PATTERN (floater)), 0),
7232 XEXP (SET_SRC (PATTERN (floater)), 1)))
7237 if (pa_can_combine_p (new, anchor, floater, 0,
7238 SET_DEST (PATTERN (floater)),
7239 SET_SRC (PATTERN (floater)),
7240 SET_SRC (PATTERN (floater))))
7246 /* If we didn't find anything on the backwards scan try forwards. */
7248 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7249 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7251 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7253 if (GET_CODE (floater) == NOTE
7254 || (GET_CODE (floater) == INSN
7255 && (GET_CODE (PATTERN (floater)) == USE
7256 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7260 /* Anything except a regular INSN will stop our search. */
7261 if (GET_CODE (floater) != INSN
7262 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7263 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7269 /* See if FLOATER is suitable for combination with the
7271 floater_attr = get_attr_pa_combine_type (floater);
7272 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7273 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7274 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7275 && floater_attr == PA_COMBINE_TYPE_FMPY))
7277 /* If ANCHOR and FLOATER can be combined, then we're
7278 done with this pass. */
7279 if (pa_can_combine_p (new, anchor, floater, 1,
7280 SET_DEST (PATTERN (floater)),
7281 XEXP (SET_SRC (PATTERN (floater)),
7283 XEXP (SET_SRC (PATTERN (floater)),
7290 /* FLOATER will be nonzero if we found a suitable floating
7291 insn for combination with ANCHOR. */
7293 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7294 || anchor_attr == PA_COMBINE_TYPE_FMPY))
7296 /* Emit the new instruction and delete the old anchor. */
7297 emit_insn_before (gen_rtx_PARALLEL
7299 gen_rtvec (2, PATTERN (anchor),
7300 PATTERN (floater))),
7303 PUT_CODE (anchor, NOTE);
7304 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7305 NOTE_SOURCE_FILE (anchor) = 0;
7307 /* Emit a special USE insn for FLOATER, then delete
7308 the floating insn. */
7309 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7310 delete_insn (floater);
7315 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
7318 /* Emit the new_jump instruction and delete the old anchor. */
7320 = emit_jump_insn_before (gen_rtx_PARALLEL
7322 gen_rtvec (2, PATTERN (anchor),
7323 PATTERN (floater))),
7326 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
7327 PUT_CODE (anchor, NOTE);
7328 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
7329 NOTE_SOURCE_FILE (anchor) = 0;
7331 /* Emit a special USE insn for FLOATER, then delete
7332 the floating insn. */
7333 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
7334 delete_insn (floater);
7342 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
7343 rtx new, anchor, floater;
7345 rtx dest, src1, src2;
7347 int insn_code_number;
7350 /* Create a PARALLEL with the patterns of ANCHOR and
7351 FLOATER, try to recognize it, then test constraints
7352 for the resulting pattern.
7354 If the pattern doesn't match or the constraints
7355 aren't met keep searching for a suitable floater
7357 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
7358 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
7359 INSN_CODE (new) = -1;
7360 insn_code_number = recog_memoized (new);
7361 if (insn_code_number < 0
7362 || (extract_insn (new), ! constrain_operands (1)))
7376 /* There's up to three operands to consider. One
7377 output and two inputs.
7379 The output must not be used between FLOATER & ANCHOR
7380 exclusive. The inputs must not be set between
7381 FLOATER and ANCHOR exclusive. */
7383 if (reg_used_between_p (dest, start, end))
7386 if (reg_set_between_p (src1, start, end))
7389 if (reg_set_between_p (src2, start, end))
7392 /* If we get here, then everything is good. */
7396 /* Return nonzero if references for INSN are delayed.
7398 Millicode insns are actually function calls with some special
7399 constraints on arguments and register usage.
7401 Millicode calls always expect their arguments in the integer argument
7402 registers, and always return their result in %r29 (ret1). They
7403 are expected to clobber their arguments, %r1, %r29, and the return
7404 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
7406 This function tells reorg that the references to arguments and
7407 millicode calls do not appear to happen until after the millicode call.
7408 This allows reorg to put insns which set the argument registers into the
7409 delay slot of the millicode call -- thus they act more like traditional
7412 Note we can not consider side effects of the insn to be delayed because
7413 the branch and link insn will clobber the return pointer. If we happened
7414 to use the return pointer in the delay slot of the call, then we lose.
7416 get_attr_type will try to recognize the given insn, so make sure to
7417 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
7420 insn_refs_are_delayed (insn)
7423 return ((GET_CODE (insn) == INSN
7424 && GET_CODE (PATTERN (insn)) != SEQUENCE
7425 && GET_CODE (PATTERN (insn)) != USE
7426 && GET_CODE (PATTERN (insn)) != CLOBBER
7427 && get_attr_type (insn) == TYPE_MILLI));
7430 /* Return the location of a parameter that is passed in a register or NULL
7431 if the parameter has any component that is passed in memory.
7433 This is new code and will be pushed to into the net sources after
7436 ??? We might want to restructure this so that it looks more like other
7439 function_arg (cum, mode, type, named, incoming)
7440 CUMULATIVE_ARGS *cum;
7441 enum machine_mode mode;
7443 int named ATTRIBUTE_UNUSED;
7446 int max_arg_words = (TARGET_64BIT ? 8 : 4);
7453 /* If this arg would be passed partially or totally on the stack, then
7454 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
7455 handle arguments which are split between regs and stack slots if
7456 the ABI mandates split arguments. */
7457 if (cum->words + FUNCTION_ARG_SIZE (mode, type) > max_arg_words
7458 || mode == VOIDmode)
7464 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7466 if (cum->words + offset >= max_arg_words
7467 || mode == VOIDmode)
7471 /* The 32bit ABIs and the 64bit ABIs are rather different,
7472 particularly in their handling of FP registers. We might
7473 be able to cleverly share code between them, but I'm not
7474 going to bother in the hope that splitting them up results
7475 in code that is more easily understood.
7477 The 64bit code probably is very wrong for structure passing. */
7480 /* Advance the base registers to their current locations.
7482 Remember, gprs grow towards smaller register numbers while
7483 fprs grow to higher register numbers. Also remember FP regs
7484 are always 4 bytes wide, while the size of an integer register
7485 varies based on the size of the target word. */
7486 gpr_reg_base = 26 - cum->words;
7487 fpr_reg_base = 32 + cum->words;
7489 /* If the argument is more than a word long, then we need to align
7490 the base registers. Same caveats as above. */
7491 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7493 if (mode != BLKmode)
7495 /* First deal with alignment of the doubleword. */
7496 gpr_reg_base -= (cum->words & 1);
7498 /* This seems backwards, but it is what HP specifies. We need
7499 gpr_reg_base to point to the smaller numbered register of
7500 the integer register pair. So if we have an even register
7501 number, then decrement the gpr base. */
7502 gpr_reg_base -= ((gpr_reg_base % 2) == 0);
7504 /* FP values behave sanely, except that each FP reg is only
7506 fpr_reg_base += ((fpr_reg_base % 2) == 0);
7511 int i, offset = 0, ub;
7512 ub = FUNCTION_ARG_SIZE (mode, type);
7514 MAX (0, max_arg_words - cum->words - (cum->words & 1)));
7515 gpr_reg_base -= (cum->words & 1);
7516 for (i = 0; i < ub; i++)
7518 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
7519 gen_rtx_REG (DImode,
7528 return XEXP (loc[0], 0);
7530 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
7536 /* If the argument is larger than a word, then we know precisely
7537 which registers we must use. */
7538 if (FUNCTION_ARG_SIZE (mode, type) > 1)
7553 /* We have a single word (32 bits). A simple computation
7554 will get us the register #s we need. */
7555 gpr_reg_base = 26 - cum->words;
7556 fpr_reg_base = 32 + 2 * cum->words;
7560 if (TARGET_64BIT && mode == TFmode)
7566 gen_rtx_EXPR_LIST (VOIDmode,
7567 gen_rtx_REG (DImode, gpr_reg_base + 1),
7569 gen_rtx_EXPR_LIST (VOIDmode,
7570 gen_rtx_REG (DImode, gpr_reg_base),
7573 /* Determine if the argument needs to be passed in both general and
7574 floating point registers. */
7575 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
7576 /* If we are doing soft-float with portable runtime, then there
7577 is no need to worry about FP regs. */
7578 && ! TARGET_SOFT_FLOAT
7579 /* The parameter must be some kind of float, else we can just
7580 pass it in integer registers. */
7581 && FLOAT_MODE_P (mode)
7582 /* The target function must not have a prototype. */
7583 && cum->nargs_prototype <= 0
7584 /* libcalls do not need to pass items in both FP and general
7586 && type != NULL_TREE
7587 /* All this hair applies to outgoing args only. */
7589 /* Also pass outgoing floating arguments in both registers in indirect
7590 calls with the 32 bit ABI and the HP assembler since there is no
7591 way to the specify argument locations in static functions. */
7596 && FLOAT_MODE_P (mode)))
7602 gen_rtx_EXPR_LIST (VOIDmode,
7603 gen_rtx_REG (mode, fpr_reg_base),
7605 gen_rtx_EXPR_LIST (VOIDmode,
7606 gen_rtx_REG (mode, gpr_reg_base),
7611 /* See if we should pass this parameter in a general register. */
7612 if (TARGET_SOFT_FLOAT
7613 /* Indirect calls in the normal 32bit ABI require all arguments
7614 to be passed in general registers. */
7615 || (!TARGET_PORTABLE_RUNTIME
7619 /* If the parameter is not a floating point parameter, then
7620 it belongs in GPRs. */
7621 || !FLOAT_MODE_P (mode))
7622 retval = gen_rtx_REG (mode, gpr_reg_base);
7624 retval = gen_rtx_REG (mode, fpr_reg_base);
7630 /* If this arg would be passed totally in registers or totally on the stack,
7631 then this routine should return zero. It is currently called only for
7632 the 64-bit target. */
7634 function_arg_partial_nregs (cum, mode, type, named)
7635 CUMULATIVE_ARGS *cum;
7636 enum machine_mode mode;
7638 int named ATTRIBUTE_UNUSED;
7640 unsigned int max_arg_words = 8;
7641 unsigned int offset = 0;
7643 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
7646 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
7647 /* Arg fits fully into registers. */
7649 else if (cum->words + offset >= max_arg_words)
7650 /* Arg fully on the stack. */
7654 return max_arg_words - cum->words - offset;
7658 /* Return 1 if this is a comparison operator. This allows the use of
7659 MATCH_OPERATOR to recognize all the branch insns. */
7662 cmpib_comparison_operator (op, mode)
7664 enum machine_mode mode;
7666 return ((mode == VOIDmode || GET_MODE (op) == mode)
7667 && (GET_CODE (op) == EQ
7668 || GET_CODE (op) == NE
7669 || GET_CODE (op) == GT
7670 || GET_CODE (op) == GTU
7671 || GET_CODE (op) == GE
7672 || GET_CODE (op) == LT
7673 || GET_CODE (op) == LE
7674 || GET_CODE (op) == LEU));
7677 /* On hpux10, the linker will give an error if we have a reference
7678 in the read-only data section to a symbol defined in a shared
7679 library. Therefore, expressions that might require a reloc can
7680 not be placed in the read-only data section. */
7683 pa_select_section (exp, reloc, align)
7686 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
7688 if (TREE_CODE (exp) == VAR_DECL
7689 && TREE_READONLY (exp)
7690 && !TREE_THIS_VOLATILE (exp)
7691 && DECL_INITIAL (exp)
7692 && (DECL_INITIAL (exp) == error_mark_node
7693 || TREE_CONSTANT (DECL_INITIAL (exp)))
7695 readonly_data_section ();
7696 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
7697 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
7699 readonly_data_section ();