1 /* Subroutines for insn-output.c for HPPA.
2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001,
3 2002, 2003 Free Software Foundation, Inc.
4 Contributed by Tim Moore (moore@cs.utah.edu), based on sparc.c
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
33 #include "insn-attr.h"
42 #include "integrate.h"
51 #include "target-def.h"
53 static int hppa_use_dfa_pipeline_interface PARAMS ((void));
55 #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
56 #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hppa_use_dfa_pipeline_interface
59 hppa_use_dfa_pipeline_interface ()
64 /* Return nonzero if there is a bypass for the output of
65 OUT_INSN and the fp store IN_INSN. */
67 hppa_fpstore_bypass_p (out_insn, in_insn)
68 rtx out_insn, in_insn;
70 enum machine_mode store_mode;
71 enum machine_mode other_mode;
74 if (recog_memoized (in_insn) < 0
75 || get_attr_type (in_insn) != TYPE_FPSTORE
76 || recog_memoized (out_insn) < 0)
79 store_mode = GET_MODE (SET_SRC (PATTERN (in_insn)));
81 set = single_set (out_insn);
85 other_mode = GET_MODE (SET_SRC (set));
87 return (GET_MODE_SIZE (store_mode) == GET_MODE_SIZE (other_mode));
91 #ifndef DO_FRAME_NOTES
92 #ifdef INCOMING_RETURN_ADDR_RTX
93 #define DO_FRAME_NOTES 1
95 #define DO_FRAME_NOTES 0
99 static int hppa_address_cost PARAMS ((rtx));
100 static bool hppa_rtx_costs PARAMS ((rtx, int, int, int *));
101 static inline rtx force_mode PARAMS ((enum machine_mode, rtx));
102 static void pa_reorg PARAMS ((void));
103 static void pa_combine_instructions PARAMS ((void));
104 static int pa_can_combine_p PARAMS ((rtx, rtx, rtx, int, rtx, rtx, rtx));
105 static int forward_branch_p PARAMS ((rtx));
106 static int shadd_constant_p PARAMS ((int));
107 static void compute_zdepwi_operands PARAMS ((unsigned HOST_WIDE_INT, unsigned *));
108 static int compute_movstrsi_length PARAMS ((rtx));
109 static bool pa_assemble_integer PARAMS ((rtx, unsigned int, int));
110 static void remove_useless_addtr_insns PARAMS ((int));
111 static void store_reg PARAMS ((int, int, int));
112 static void store_reg_modify PARAMS ((int, int, int));
113 static void load_reg PARAMS ((int, int, int));
114 static void set_reg_plus_d PARAMS ((int, int, int, int));
115 static void pa_output_function_prologue PARAMS ((FILE *, HOST_WIDE_INT));
116 static void pa_output_function_epilogue PARAMS ((FILE *, HOST_WIDE_INT));
117 static int pa_adjust_cost PARAMS ((rtx, rtx, rtx, int));
118 static int pa_adjust_priority PARAMS ((rtx, int));
119 static int pa_issue_rate PARAMS ((void));
120 static void pa_select_section PARAMS ((tree, int, unsigned HOST_WIDE_INT))
122 static void pa_encode_section_info PARAMS ((tree, rtx, int));
123 static const char *pa_strip_name_encoding PARAMS ((const char *));
124 static bool pa_function_ok_for_sibcall PARAMS ((tree, tree));
125 static void pa_globalize_label PARAMS ((FILE *, const char *))
127 static void pa_asm_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT,
128 HOST_WIDE_INT, tree));
129 #if !defined(USE_COLLECT2)
130 static void pa_asm_out_constructor PARAMS ((rtx, int));
131 static void pa_asm_out_destructor PARAMS ((rtx, int));
133 static void pa_init_builtins PARAMS ((void));
134 static void copy_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
135 static int length_fp_args PARAMS ((rtx)) ATTRIBUTE_UNUSED;
136 static struct deferred_plabel *get_plabel PARAMS ((const char *))
138 static void output_deferred_plabels PARAMS ((void));
140 /* Save the operands last given to a compare for use when we
141 generate a scc or bcc insn. */
142 rtx hppa_compare_op0, hppa_compare_op1;
143 enum cmp_type hppa_branch_type;
145 /* Which cpu we are scheduling for. */
146 enum processor_type pa_cpu;
148 /* String to hold which cpu we are scheduling for. */
149 const char *pa_cpu_string;
151 /* Which architecture we are generating code for. */
152 enum architecture_type pa_arch;
154 /* String to hold which architecture we are generating code for. */
155 const char *pa_arch_string;
157 /* Counts for the number of callee-saved general and floating point
158 registers which were saved by the current function's prologue. */
159 static int gr_saved, fr_saved;
161 static rtx find_addr_reg PARAMS ((rtx));
163 /* Keep track of the number of bytes we have output in the CODE subspaces
164 during this compilation so we'll know when to emit inline long-calls. */
165 unsigned long total_code_bytes;
167 /* Variables to handle plabels that we discover are necessary at assembly
168 output time. They are output after the current function. */
169 struct deferred_plabel GTY(())
174 static GTY((length ("n_deferred_plabels"))) struct deferred_plabel *
176 static size_t n_deferred_plabels = 0;
179 /* Initialize the GCC target structure. */
181 #undef TARGET_ASM_ALIGNED_HI_OP
182 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t"
183 #undef TARGET_ASM_ALIGNED_SI_OP
184 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t"
185 #undef TARGET_ASM_ALIGNED_DI_OP
186 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t"
187 #undef TARGET_ASM_UNALIGNED_HI_OP
188 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP
189 #undef TARGET_ASM_UNALIGNED_SI_OP
190 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP
191 #undef TARGET_ASM_UNALIGNED_DI_OP
192 #define TARGET_ASM_UNALIGNED_DI_OP TARGET_ASM_ALIGNED_DI_OP
193 #undef TARGET_ASM_INTEGER
194 #define TARGET_ASM_INTEGER pa_assemble_integer
196 #undef TARGET_ASM_FUNCTION_PROLOGUE
197 #define TARGET_ASM_FUNCTION_PROLOGUE pa_output_function_prologue
198 #undef TARGET_ASM_FUNCTION_EPILOGUE
199 #define TARGET_ASM_FUNCTION_EPILOGUE pa_output_function_epilogue
201 #undef TARGET_SCHED_ADJUST_COST
202 #define TARGET_SCHED_ADJUST_COST pa_adjust_cost
203 #undef TARGET_SCHED_ADJUST_PRIORITY
204 #define TARGET_SCHED_ADJUST_PRIORITY pa_adjust_priority
205 #undef TARGET_SCHED_ISSUE_RATE
206 #define TARGET_SCHED_ISSUE_RATE pa_issue_rate
208 #undef TARGET_ENCODE_SECTION_INFO
209 #define TARGET_ENCODE_SECTION_INFO pa_encode_section_info
210 #undef TARGET_STRIP_NAME_ENCODING
211 #define TARGET_STRIP_NAME_ENCODING pa_strip_name_encoding
213 #undef TARGET_FUNCTION_OK_FOR_SIBCALL
214 #define TARGET_FUNCTION_OK_FOR_SIBCALL pa_function_ok_for_sibcall
216 #undef TARGET_ASM_OUTPUT_MI_THUNK
217 #define TARGET_ASM_OUTPUT_MI_THUNK pa_asm_output_mi_thunk
218 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
219 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall
221 #undef TARGET_ASM_FILE_END
222 #define TARGET_ASM_FILE_END output_deferred_plabels
224 #if !defined(USE_COLLECT2)
225 #undef TARGET_ASM_CONSTRUCTOR
226 #define TARGET_ASM_CONSTRUCTOR pa_asm_out_constructor
227 #undef TARGET_ASM_DESTRUCTOR
228 #define TARGET_ASM_DESTRUCTOR pa_asm_out_destructor
231 #undef TARGET_INIT_BUILTINS
232 #define TARGET_INIT_BUILTINS pa_init_builtins
234 #undef TARGET_RTX_COSTS
235 #define TARGET_RTX_COSTS hppa_rtx_costs
236 #undef TARGET_ADDRESS_COST
237 #define TARGET_ADDRESS_COST hppa_address_cost
239 #undef TARGET_MACHINE_DEPENDENT_REORG
240 #define TARGET_MACHINE_DEPENDENT_REORG pa_reorg
242 struct gcc_target targetm = TARGET_INITIALIZER;
247 if (pa_cpu_string == NULL)
248 pa_cpu_string = TARGET_SCHED_DEFAULT;
250 if (! strcmp (pa_cpu_string, "8000"))
252 pa_cpu_string = "8000";
253 pa_cpu = PROCESSOR_8000;
255 else if (! strcmp (pa_cpu_string, "7100"))
257 pa_cpu_string = "7100";
258 pa_cpu = PROCESSOR_7100;
260 else if (! strcmp (pa_cpu_string, "700"))
262 pa_cpu_string = "700";
263 pa_cpu = PROCESSOR_700;
265 else if (! strcmp (pa_cpu_string, "7100LC"))
267 pa_cpu_string = "7100LC";
268 pa_cpu = PROCESSOR_7100LC;
270 else if (! strcmp (pa_cpu_string, "7200"))
272 pa_cpu_string = "7200";
273 pa_cpu = PROCESSOR_7200;
275 else if (! strcmp (pa_cpu_string, "7300"))
277 pa_cpu_string = "7300";
278 pa_cpu = PROCESSOR_7300;
282 warning ("unknown -mschedule= option (%s).\nValid options are 700, 7100, 7100LC, 7200, 7300, and 8000\n", pa_cpu_string);
285 /* Set the instruction set architecture. */
286 if (pa_arch_string && ! strcmp (pa_arch_string, "1.0"))
288 pa_arch_string = "1.0";
289 pa_arch = ARCHITECTURE_10;
290 target_flags &= ~(MASK_PA_11 | MASK_PA_20);
292 else if (pa_arch_string && ! strcmp (pa_arch_string, "1.1"))
294 pa_arch_string = "1.1";
295 pa_arch = ARCHITECTURE_11;
296 target_flags &= ~MASK_PA_20;
297 target_flags |= MASK_PA_11;
299 else if (pa_arch_string && ! strcmp (pa_arch_string, "2.0"))
301 pa_arch_string = "2.0";
302 pa_arch = ARCHITECTURE_20;
303 target_flags |= MASK_PA_11 | MASK_PA_20;
305 else if (pa_arch_string)
307 warning ("unknown -march= option (%s).\nValid options are 1.0, 1.1, and 2.0\n", pa_arch_string);
310 /* Unconditional branches in the delay slot are not compatible with dwarf2
311 call frame information. There is no benefit in using this optimization
312 on PA8000 and later processors. */
313 if (pa_cpu >= PROCESSOR_8000
314 || (! USING_SJLJ_EXCEPTIONS && flag_exceptions)
315 || flag_unwind_tables)
316 target_flags &= ~MASK_JUMP_IN_DELAY;
318 if (flag_pic && TARGET_PORTABLE_RUNTIME)
320 warning ("PIC code generation is not supported in the portable runtime model\n");
323 if (flag_pic && TARGET_FAST_INDIRECT_CALLS)
325 warning ("PIC code generation is not compatible with fast indirect calls\n");
328 if (! TARGET_GAS && write_symbols != NO_DEBUG)
330 warning ("-g is only supported when using GAS on this processor,");
331 warning ("-g option disabled");
332 write_symbols = NO_DEBUG;
335 /* We only support the "big PIC" model now. And we always generate PIC
336 code when in 64bit mode. */
337 if (flag_pic == 1 || TARGET_64BIT)
340 /* We can't guarantee that .dword is available for 32-bit targets. */
341 if (UNITS_PER_WORD == 4)
342 targetm.asm_out.aligned_op.di = NULL;
344 /* The unaligned ops are only available when using GAS. */
347 targetm.asm_out.unaligned_op.hi = NULL;
348 targetm.asm_out.unaligned_op.si = NULL;
349 targetm.asm_out.unaligned_op.di = NULL;
356 #ifdef DONT_HAVE_FPUTC_UNLOCKED
357 built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
358 implicit_built_in_decls[(int) BUILT_IN_FPUTC_UNLOCKED] = NULL_TREE;
362 /* Return nonzero only if OP is a register of mode MODE,
365 reg_or_0_operand (op, mode)
367 enum machine_mode mode;
369 return (op == CONST0_RTX (mode) || register_operand (op, mode));
372 /* Return nonzero if OP is suitable for use in a call to a named
375 For 2.5 try to eliminate either call_operand_address or
376 function_label_operand, they perform very similar functions. */
378 call_operand_address (op, mode)
380 enum machine_mode mode ATTRIBUTE_UNUSED;
382 return (GET_MODE (op) == word_mode
383 && CONSTANT_P (op) && ! TARGET_PORTABLE_RUNTIME);
386 /* Return 1 if X contains a symbolic expression. We know these
387 expressions will have one of a few well defined forms, so
388 we need only check those forms. */
390 symbolic_expression_p (x)
394 /* Strip off any HIGH. */
395 if (GET_CODE (x) == HIGH)
398 return (symbolic_operand (x, VOIDmode));
402 symbolic_operand (op, mode)
404 enum machine_mode mode ATTRIBUTE_UNUSED;
406 switch (GET_CODE (op))
413 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
414 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
415 && GET_CODE (XEXP (op, 1)) == CONST_INT);
421 /* Return truth value of statement that OP is a symbolic memory
422 operand of mode MODE. */
425 symbolic_memory_operand (op, mode)
427 enum machine_mode mode ATTRIBUTE_UNUSED;
429 if (GET_CODE (op) == SUBREG)
430 op = SUBREG_REG (op);
431 if (GET_CODE (op) != MEM)
434 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST
435 || GET_CODE (op) == HIGH || GET_CODE (op) == LABEL_REF);
438 /* Return 1 if the operand is either a register or a memory operand that is
442 reg_or_nonsymb_mem_operand (op, mode)
444 enum machine_mode mode;
446 if (register_operand (op, mode))
449 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
455 /* Return 1 if the operand is either a register, zero, or a memory operand
456 that is not symbolic. */
459 reg_or_0_or_nonsymb_mem_operand (op, mode)
461 enum machine_mode mode;
463 if (register_operand (op, mode))
466 if (op == CONST0_RTX (mode))
469 if (memory_operand (op, mode) && ! symbolic_memory_operand (op, mode))
475 /* Return 1 if the operand is a register operand or a non-symbolic memory
476 operand after reload. This predicate is used for branch patterns that
477 internally handle register reloading. We need to accept non-symbolic
478 memory operands after reload to ensure that the pattern is still valid
479 if reload didn't find a hard register for the operand. */
482 reg_before_reload_operand (op, mode)
484 enum machine_mode mode;
486 /* Don't accept a SUBREG since it will need a reload. */
487 if (GET_CODE (op) == SUBREG)
490 if (register_operand (op, mode))
494 && memory_operand (op, mode)
495 && ! symbolic_memory_operand (op, mode))
501 /* Accept any constant that can be moved in one instruction into a
504 cint_ok_for_move (intval)
505 HOST_WIDE_INT intval;
507 /* OK if ldo, ldil, or zdepi, can be used. */
508 return (CONST_OK_FOR_LETTER_P (intval, 'J')
509 || CONST_OK_FOR_LETTER_P (intval, 'N')
510 || CONST_OK_FOR_LETTER_P (intval, 'K'));
513 /* Accept anything that can be moved in one instruction into a general
516 move_operand (op, mode)
518 enum machine_mode mode;
520 if (register_operand (op, mode))
523 if (GET_CODE (op) == CONSTANT_P_RTX)
526 if (GET_CODE (op) == CONST_INT)
527 return cint_ok_for_move (INTVAL (op));
529 if (GET_CODE (op) == SUBREG)
530 op = SUBREG_REG (op);
531 if (GET_CODE (op) != MEM)
536 /* We consider a LO_SUM DLT reference a move_operand now since it has
537 been merged into the normal movsi/movdi patterns. */
538 if (GET_CODE (op) == LO_SUM
539 && GET_CODE (XEXP (op, 0)) == REG
540 && REG_OK_FOR_BASE_P (XEXP (op, 0))
541 && GET_CODE (XEXP (op, 1)) == UNSPEC
542 && GET_MODE (op) == Pmode)
545 /* Since move_operand is only used for source operands, we can always
546 allow scaled indexing! */
547 if (! TARGET_DISABLE_INDEXING
548 && GET_CODE (op) == PLUS
549 && ((GET_CODE (XEXP (op, 0)) == MULT
550 && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
551 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
552 && INTVAL (XEXP (XEXP (op, 0), 1))
553 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
554 && GET_CODE (XEXP (op, 1)) == REG)
555 || (GET_CODE (XEXP (op, 1)) == MULT
556 &&GET_CODE (XEXP (XEXP (op, 1), 0)) == REG
557 && GET_CODE (XEXP (XEXP (op, 1), 1)) == CONST_INT
558 && INTVAL (XEXP (XEXP (op, 1), 1))
559 == (HOST_WIDE_INT) GET_MODE_SIZE (mode)
560 && GET_CODE (XEXP (op, 0)) == REG)))
563 return memory_address_p (mode, op);
566 /* Accept REG and any CONST_INT that can be moved in one instruction into a
569 reg_or_cint_move_operand (op, mode)
571 enum machine_mode mode;
573 if (register_operand (op, mode))
576 if (GET_CODE (op) == CONST_INT)
577 return cint_ok_for_move (INTVAL (op));
583 pic_label_operand (op, mode)
585 enum machine_mode mode ATTRIBUTE_UNUSED;
590 switch (GET_CODE (op))
596 return (GET_CODE (XEXP (op, 0)) == LABEL_REF
597 && GET_CODE (XEXP (op, 1)) == CONST_INT);
604 fp_reg_operand (op, mode)
606 enum machine_mode mode ATTRIBUTE_UNUSED;
608 return reg_renumber && FP_REG_P (op);
613 /* Return truth value of whether OP can be used as an operand in a
614 three operand arithmetic insn that accepts registers of mode MODE
615 or 14-bit signed integers. */
617 arith_operand (op, mode)
619 enum machine_mode mode;
621 return (register_operand (op, mode)
622 || (GET_CODE (op) == CONST_INT && INT_14_BITS (op)));
625 /* Return truth value of whether OP can be used as an operand in a
626 three operand arithmetic insn that accepts registers of mode MODE
627 or 11-bit signed integers. */
629 arith11_operand (op, mode)
631 enum machine_mode mode;
633 return (register_operand (op, mode)
634 || (GET_CODE (op) == CONST_INT && INT_11_BITS (op)));
637 /* Return truth value of whether OP can be used as an operand in a
640 adddi3_operand (op, mode)
642 enum machine_mode mode;
644 return (register_operand (op, mode)
645 || (GET_CODE (op) == CONST_INT
646 && (TARGET_64BIT ? INT_14_BITS (op) : INT_11_BITS (op))));
649 /* A constant integer suitable for use in a PRE_MODIFY memory
652 pre_cint_operand (op, mode)
654 enum machine_mode mode ATTRIBUTE_UNUSED;
656 return (GET_CODE (op) == CONST_INT
657 && INTVAL (op) >= -0x2000 && INTVAL (op) < 0x10);
660 /* A constant integer suitable for use in a POST_MODIFY memory
663 post_cint_operand (op, mode)
665 enum machine_mode mode ATTRIBUTE_UNUSED;
667 return (GET_CODE (op) == CONST_INT
668 && INTVAL (op) < 0x2000 && INTVAL (op) >= -0x10);
672 arith_double_operand (op, mode)
674 enum machine_mode mode;
676 return (register_operand (op, mode)
677 || (GET_CODE (op) == CONST_DOUBLE
678 && GET_MODE (op) == mode
679 && VAL_14_BITS_P (CONST_DOUBLE_LOW (op))
680 && ((CONST_DOUBLE_HIGH (op) >= 0)
681 == ((CONST_DOUBLE_LOW (op) & 0x1000) == 0))));
684 /* Return truth value of whether OP is an integer which fits the
685 range constraining immediate operands in three-address insns, or
686 is an integer register. */
689 ireg_or_int5_operand (op, mode)
691 enum machine_mode mode ATTRIBUTE_UNUSED;
693 return ((GET_CODE (op) == CONST_INT && INT_5_BITS (op))
694 || (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32));
697 /* Return nonzero if OP is an integer register, else return zero. */
699 ireg_operand (op, mode)
701 enum machine_mode mode ATTRIBUTE_UNUSED;
703 return (GET_CODE (op) == REG && REGNO (op) > 0 && REGNO (op) < 32);
706 /* Return truth value of whether OP is an integer which fits the
707 range constraining immediate operands in three-address insns. */
710 int5_operand (op, mode)
712 enum machine_mode mode ATTRIBUTE_UNUSED;
714 return (GET_CODE (op) == CONST_INT && INT_5_BITS (op));
718 uint5_operand (op, mode)
720 enum machine_mode mode ATTRIBUTE_UNUSED;
722 return (GET_CODE (op) == CONST_INT && INT_U5_BITS (op));
726 int11_operand (op, mode)
728 enum machine_mode mode ATTRIBUTE_UNUSED;
730 return (GET_CODE (op) == CONST_INT && INT_11_BITS (op));
734 uint32_operand (op, mode)
736 enum machine_mode mode ATTRIBUTE_UNUSED;
738 #if HOST_BITS_PER_WIDE_INT > 32
739 /* All allowed constants will fit a CONST_INT. */
740 return (GET_CODE (op) == CONST_INT
741 && (INTVAL (op) >= 0 && INTVAL (op) < (HOST_WIDE_INT) 1 << 32));
743 return (GET_CODE (op) == CONST_INT
744 || (GET_CODE (op) == CONST_DOUBLE
745 && CONST_DOUBLE_HIGH (op) == 0));
750 arith5_operand (op, mode)
752 enum machine_mode mode;
754 return register_operand (op, mode) || int5_operand (op, mode);
757 /* True iff zdepi can be used to generate this CONST_INT.
758 zdepi first sign extends a 5 bit signed number to a given field
759 length, then places this field anywhere in a zero. */
762 unsigned HOST_WIDE_INT x;
764 unsigned HOST_WIDE_INT lsb_mask, t;
766 /* This might not be obvious, but it's at least fast.
767 This function is critical; we don't have the time loops would take. */
769 t = ((x >> 4) + lsb_mask) & ~(lsb_mask - 1);
770 /* Return true iff t is a power of two. */
771 return ((t & (t - 1)) == 0);
774 /* True iff depi or extru can be used to compute (reg & mask).
775 Accept bit pattern like these:
781 unsigned HOST_WIDE_INT mask;
784 mask += mask & -mask;
785 return (mask & (mask - 1)) == 0;
788 /* True iff depi or extru can be used to compute (reg & OP). */
790 and_operand (op, mode)
792 enum machine_mode mode;
794 return (register_operand (op, mode)
795 || (GET_CODE (op) == CONST_INT && and_mask_p (INTVAL (op))));
798 /* True iff depi can be used to compute (reg | MASK). */
801 unsigned HOST_WIDE_INT mask;
803 mask += mask & -mask;
804 return (mask & (mask - 1)) == 0;
807 /* True iff depi can be used to compute (reg | OP). */
809 ior_operand (op, mode)
811 enum machine_mode mode ATTRIBUTE_UNUSED;
813 return (GET_CODE (op) == CONST_INT && ior_mask_p (INTVAL (op)));
817 lhs_lshift_operand (op, mode)
819 enum machine_mode mode;
821 return register_operand (op, mode) || lhs_lshift_cint_operand (op, mode);
824 /* True iff OP is a CONST_INT of the forms 0...0xxxx or 0...01...1xxxx.
825 Such values can be the left hand side x in (x << r), using the zvdepi
828 lhs_lshift_cint_operand (op, mode)
830 enum machine_mode mode ATTRIBUTE_UNUSED;
832 unsigned HOST_WIDE_INT x;
833 if (GET_CODE (op) != CONST_INT)
835 x = INTVAL (op) >> 4;
836 return (x & (x + 1)) == 0;
840 arith32_operand (op, mode)
842 enum machine_mode mode;
844 return register_operand (op, mode) || GET_CODE (op) == CONST_INT;
848 pc_or_label_operand (op, mode)
850 enum machine_mode mode ATTRIBUTE_UNUSED;
852 return (GET_CODE (op) == PC || GET_CODE (op) == LABEL_REF);
855 /* Legitimize PIC addresses. If the address is already
856 position-independent, we return ORIG. Newly generated
857 position-independent addresses go to REG. If we need more
858 than one register, we lose. */
861 legitimize_pic_address (orig, mode, reg)
863 enum machine_mode mode;
867 /* Labels need special handling. */
868 if (pic_label_operand (orig, mode))
870 /* We do not want to go through the movXX expanders here since that
871 would create recursion.
873 Nor do we really want to call a generator for a named pattern
874 since that requires multiple patterns if we want to support
877 So instead we just emit the raw set, which avoids the movXX
878 expanders completely. */
879 emit_insn (gen_rtx_SET (VOIDmode, reg, orig));
880 current_function_uses_pic_offset_table = 1;
883 if (GET_CODE (orig) == SYMBOL_REF)
889 gen_rtx_PLUS (word_mode, pic_offset_table_rtx,
890 gen_rtx_HIGH (word_mode, orig)));
892 = gen_rtx_MEM (Pmode,
893 gen_rtx_LO_SUM (Pmode, reg,
894 gen_rtx_UNSPEC (Pmode,
898 current_function_uses_pic_offset_table = 1;
899 RTX_UNCHANGING_P (pic_ref) = 1;
900 emit_move_insn (reg, pic_ref);
903 else if (GET_CODE (orig) == CONST)
907 if (GET_CODE (XEXP (orig, 0)) == PLUS
908 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx)
914 if (GET_CODE (XEXP (orig, 0)) == PLUS)
916 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg);
917 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
918 base == reg ? 0 : reg);
921 if (GET_CODE (orig) == CONST_INT)
923 if (INT_14_BITS (orig))
924 return plus_constant (base, INTVAL (orig));
925 orig = force_reg (Pmode, orig);
927 pic_ref = gen_rtx_PLUS (Pmode, base, orig);
928 /* Likewise, should we set special REG_NOTEs here? */
933 /* Try machine-dependent ways of modifying an illegitimate address
934 to be legitimate. If we find one, return the new, valid address.
935 This macro is used in only one place: `memory_address' in explow.c.
937 OLDX is the address as it was before break_out_memory_refs was called.
938 In some cases it is useful to look at this to decide what needs to be done.
940 MODE and WIN are passed so that this macro can use
941 GO_IF_LEGITIMATE_ADDRESS.
943 It is always safe for this macro to do nothing. It exists to recognize
944 opportunities to optimize the output.
946 For the PA, transform:
948 memory(X + <large int>)
952 if (<large int> & mask) >= 16
953 Y = (<large int> & ~mask) + mask + 1 Round up.
955 Y = (<large int> & ~mask) Round down.
957 memory (Z + (<large int> - Y));
959 This is for CSE to find several similar references, and only use one Z.
961 X can either be a SYMBOL_REF or REG, but because combine can not
962 perform a 4->2 combination we do nothing for SYMBOL_REF + D where
963 D will not fit in 14 bits.
965 MODE_FLOAT references allow displacements which fit in 5 bits, so use
968 MODE_INT references allow displacements which fit in 14 bits, so use
971 This relies on the fact that most mode MODE_FLOAT references will use FP
972 registers and most mode MODE_INT references will use integer registers.
973 (In the rare case of an FP register used in an integer MODE, we depend
974 on secondary reloads to clean things up.)
977 It is also beneficial to handle (plus (mult (X) (Y)) (Z)) in a special
978 manner if Y is 2, 4, or 8. (allows more shadd insns and shifted indexed
979 addressing modes to be used).
981 Put X and Z into registers. Then put the entire expression into
985 hppa_legitimize_address (x, oldx, mode)
986 rtx x, oldx ATTRIBUTE_UNUSED;
987 enum machine_mode mode;
992 return legitimize_pic_address (x, mode, gen_reg_rtx (Pmode));
994 /* Strip off CONST. */
995 if (GET_CODE (x) == CONST)
998 /* Special case. Get the SYMBOL_REF into a register and use indexing.
999 That should always be safe. */
1000 if (GET_CODE (x) == PLUS
1001 && GET_CODE (XEXP (x, 0)) == REG
1002 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
1004 rtx reg = force_reg (Pmode, XEXP (x, 1));
1005 return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
1008 /* Note we must reject symbols which represent function addresses
1009 since the assembler/linker can't handle arithmetic on plabels. */
1010 if (GET_CODE (x) == PLUS
1011 && GET_CODE (XEXP (x, 1)) == CONST_INT
1012 && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
1013 && !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
1014 || GET_CODE (XEXP (x, 0)) == REG))
1016 rtx int_part, ptr_reg;
1018 int offset = INTVAL (XEXP (x, 1));
1021 mask = (GET_MODE_CLASS (mode) == MODE_FLOAT
1022 ? (TARGET_PA_20 ? 0x3fff : 0x1f) : 0x3fff);
1024 /* Choose which way to round the offset. Round up if we
1025 are >= halfway to the next boundary. */
1026 if ((offset & mask) >= ((mask + 1) / 2))
1027 newoffset = (offset & ~ mask) + mask + 1;
1029 newoffset = (offset & ~ mask);
1031 /* If the newoffset will not fit in 14 bits (ldo), then
1032 handling this would take 4 or 5 instructions (2 to load
1033 the SYMBOL_REF + 1 or 2 to load the newoffset + 1 to
1034 add the new offset and the SYMBOL_REF.) Combine can
1035 not handle 4->2 or 5->2 combinations, so do not create
1037 if (! VAL_14_BITS_P (newoffset)
1038 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
1040 rtx const_part = plus_constant (XEXP (x, 0), newoffset);
1043 gen_rtx_HIGH (Pmode, const_part));
1046 gen_rtx_LO_SUM (Pmode,
1047 tmp_reg, const_part));
1051 if (! VAL_14_BITS_P (newoffset))
1052 int_part = force_reg (Pmode, GEN_INT (newoffset));
1054 int_part = GEN_INT (newoffset);
1056 ptr_reg = force_reg (Pmode,
1057 gen_rtx_PLUS (Pmode,
1058 force_reg (Pmode, XEXP (x, 0)),
1061 return plus_constant (ptr_reg, offset - newoffset);
1064 /* Handle (plus (mult (a) (shadd_constant)) (b)). */
1066 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT
1067 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1068 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1)))
1069 && (GET_RTX_CLASS (GET_CODE (XEXP (x, 1))) == 'o'
1070 || GET_CODE (XEXP (x, 1)) == SUBREG)
1071 && GET_CODE (XEXP (x, 1)) != CONST)
1073 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1077 if (GET_CODE (reg1) != REG)
1078 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1080 reg2 = XEXP (XEXP (x, 0), 0);
1081 if (GET_CODE (reg2) != REG)
1082 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1084 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1085 gen_rtx_MULT (Pmode,
1091 /* Similarly for (plus (plus (mult (a) (shadd_constant)) (b)) (c)).
1093 Only do so for floating point modes since this is more speculative
1094 and we lose if it's an integer store. */
1095 if (GET_CODE (x) == PLUS
1096 && GET_CODE (XEXP (x, 0)) == PLUS
1097 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
1098 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
1099 && shadd_constant_p (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1)))
1100 && (mode == SFmode || mode == DFmode))
1103 /* First, try and figure out what to use as a base register. */
1104 rtx reg1, reg2, base, idx, orig_base;
1106 reg1 = XEXP (XEXP (x, 0), 1);
1111 /* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
1112 then emit_move_sequence will turn on REG_POINTER so we'll know
1113 it's a base register below. */
1114 if (GET_CODE (reg1) != REG)
1115 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1117 if (GET_CODE (reg2) != REG)
1118 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1120 /* Figure out what the base and index are. */
1122 if (GET_CODE (reg1) == REG
1123 && REG_POINTER (reg1))
1126 orig_base = XEXP (XEXP (x, 0), 1);
1127 idx = gen_rtx_PLUS (Pmode,
1128 gen_rtx_MULT (Pmode,
1129 XEXP (XEXP (XEXP (x, 0), 0), 0),
1130 XEXP (XEXP (XEXP (x, 0), 0), 1)),
1133 else if (GET_CODE (reg2) == REG
1134 && REG_POINTER (reg2))
1137 orig_base = XEXP (x, 1);
1144 /* If the index adds a large constant, try to scale the
1145 constant so that it can be loaded with only one insn. */
1146 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1147 && VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
1148 / INTVAL (XEXP (XEXP (idx, 0), 1)))
1149 && INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
1151 /* Divide the CONST_INT by the scale factor, then add it to A. */
1152 int val = INTVAL (XEXP (idx, 1));
1154 val /= INTVAL (XEXP (XEXP (idx, 0), 1));
1155 reg1 = XEXP (XEXP (idx, 0), 0);
1156 if (GET_CODE (reg1) != REG)
1157 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1159 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
1161 /* We can now generate a simple scaled indexed address. */
1164 (Pmode, gen_rtx_PLUS (Pmode,
1165 gen_rtx_MULT (Pmode, reg1,
1166 XEXP (XEXP (idx, 0), 1)),
1170 /* If B + C is still a valid base register, then add them. */
1171 if (GET_CODE (XEXP (idx, 1)) == CONST_INT
1172 && INTVAL (XEXP (idx, 1)) <= 4096
1173 && INTVAL (XEXP (idx, 1)) >= -4096)
1175 int val = INTVAL (XEXP (XEXP (idx, 0), 1));
1178 reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
1180 reg2 = XEXP (XEXP (idx, 0), 0);
1181 if (GET_CODE (reg2) != CONST_INT)
1182 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1184 return force_reg (Pmode, gen_rtx_PLUS (Pmode,
1185 gen_rtx_MULT (Pmode,
1191 /* Get the index into a register, then add the base + index and
1192 return a register holding the result. */
1194 /* First get A into a register. */
1195 reg1 = XEXP (XEXP (idx, 0), 0);
1196 if (GET_CODE (reg1) != REG)
1197 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1199 /* And get B into a register. */
1200 reg2 = XEXP (idx, 1);
1201 if (GET_CODE (reg2) != REG)
1202 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1204 reg1 = force_reg (Pmode,
1205 gen_rtx_PLUS (Pmode,
1206 gen_rtx_MULT (Pmode, reg1,
1207 XEXP (XEXP (idx, 0), 1)),
1210 /* Add the result to our base register and return. */
1211 return force_reg (Pmode, gen_rtx_PLUS (Pmode, base, reg1));
1215 /* Uh-oh. We might have an address for x[n-100000]. This needs
1216 special handling to avoid creating an indexed memory address
1217 with x-100000 as the base.
1219 If the constant part is small enough, then it's still safe because
1220 there is a guard page at the beginning and end of the data segment.
1222 Scaled references are common enough that we want to try and rearrange the
1223 terms so that we can use indexing for these addresses too. Only
1224 do the optimization for floatint point modes. */
1226 if (GET_CODE (x) == PLUS
1227 && symbolic_expression_p (XEXP (x, 1)))
1229 /* Ugly. We modify things here so that the address offset specified
1230 by the index expression is computed first, then added to x to form
1231 the entire address. */
1233 rtx regx1, regx2, regy1, regy2, y;
1235 /* Strip off any CONST. */
1237 if (GET_CODE (y) == CONST)
1240 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1242 /* See if this looks like
1243 (plus (mult (reg) (shadd_const))
1244 (const (plus (symbol_ref) (const_int))))
1246 Where const_int is small. In that case the const
1247 expression is a valid pointer for indexing.
1249 If const_int is big, but can be divided evenly by shadd_const
1250 and added to (reg). This allows more scaled indexed addresses. */
1251 if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1252 && GET_CODE (XEXP (x, 0)) == MULT
1253 && GET_CODE (XEXP (y, 1)) == CONST_INT
1254 && INTVAL (XEXP (y, 1)) >= -4096
1255 && INTVAL (XEXP (y, 1)) <= 4095
1256 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1257 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1259 int val = INTVAL (XEXP (XEXP (x, 0), 1));
1263 if (GET_CODE (reg1) != REG)
1264 reg1 = force_reg (Pmode, force_operand (reg1, 0));
1266 reg2 = XEXP (XEXP (x, 0), 0);
1267 if (GET_CODE (reg2) != REG)
1268 reg2 = force_reg (Pmode, force_operand (reg2, 0));
1270 return force_reg (Pmode,
1271 gen_rtx_PLUS (Pmode,
1272 gen_rtx_MULT (Pmode,
1277 else if ((mode == DFmode || mode == SFmode)
1278 && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
1279 && GET_CODE (XEXP (x, 0)) == MULT
1280 && GET_CODE (XEXP (y, 1)) == CONST_INT
1281 && INTVAL (XEXP (y, 1)) % INTVAL (XEXP (XEXP (x, 0), 1)) == 0
1282 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
1283 && shadd_constant_p (INTVAL (XEXP (XEXP (x, 0), 1))))
1286 = force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
1287 / INTVAL (XEXP (XEXP (x, 0), 1))));
1288 regx2 = XEXP (XEXP (x, 0), 0);
1289 if (GET_CODE (regx2) != REG)
1290 regx2 = force_reg (Pmode, force_operand (regx2, 0));
1291 regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1295 gen_rtx_PLUS (Pmode,
1296 gen_rtx_MULT (Pmode, regx2,
1297 XEXP (XEXP (x, 0), 1)),
1298 force_reg (Pmode, XEXP (y, 0))));
1300 else if (GET_CODE (XEXP (y, 1)) == CONST_INT
1301 && INTVAL (XEXP (y, 1)) >= -4096
1302 && INTVAL (XEXP (y, 1)) <= 4095)
1304 /* This is safe because of the guard page at the
1305 beginning and end of the data space. Just
1306 return the original address. */
1311 /* Doesn't look like one we can optimize. */
1312 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1313 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1314 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1315 regx1 = force_reg (Pmode,
1316 gen_rtx_fmt_ee (GET_CODE (y), Pmode,
1318 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1326 /* For the HPPA, REG and REG+CONST is cost 0
1327 and addresses involving symbolic constants are cost 2.
1329 PIC addresses are very expensive.
1331 It is no coincidence that this has the same structure
1332 as GO_IF_LEGITIMATE_ADDRESS. */
1335 hppa_address_cost (X)
1338 switch (GET_CODE (X))
1351 /* Compute a (partial) cost for rtx X. Return true if the complete
1352 cost has been computed, and false if subexpressions should be
1353 scanned. In either case, *TOTAL contains the cost result. */
1356 hppa_rtx_costs (x, code, outer_code, total)
1358 int code, outer_code;
1364 if (INTVAL (x) == 0)
1366 else if (INT_14_BITS (x))
1383 if ((x == CONST0_RTX (DFmode) || x == CONST0_RTX (SFmode))
1384 && outer_code != SET)
1391 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1392 *total = COSTS_N_INSNS (3);
1393 else if (TARGET_PA_11 && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT)
1394 *total = COSTS_N_INSNS (8);
1396 *total = COSTS_N_INSNS (20);
1400 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1402 *total = COSTS_N_INSNS (14);
1410 *total = COSTS_N_INSNS (60);
1413 case PLUS: /* this includes shNadd insns */
1415 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
1416 *total = COSTS_N_INSNS (3);
1418 *total = COSTS_N_INSNS (1);
1424 *total = COSTS_N_INSNS (1);
1432 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a
1433 new rtx with the correct mode. */
1435 force_mode (mode, orig)
1436 enum machine_mode mode;
1439 if (mode == GET_MODE (orig))
1442 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER)
1445 return gen_rtx_REG (mode, REGNO (orig));
1448 /* Emit insns to move operands[1] into operands[0].
1450 Return 1 if we have written out everything that needs to be done to
1451 do the move. Otherwise, return 0 and the caller will emit the move
1454 Note SCRATCH_REG may not be in the proper mode depending on how it
1455 will be used. This routine is resposible for creating a new copy
1456 of SCRATCH_REG in the proper mode. */
1459 emit_move_sequence (operands, mode, scratch_reg)
1461 enum machine_mode mode;
1464 register rtx operand0 = operands[0];
1465 register rtx operand1 = operands[1];
1469 && reload_in_progress && GET_CODE (operand0) == REG
1470 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1471 operand0 = reg_equiv_mem[REGNO (operand0)];
1472 else if (scratch_reg
1473 && reload_in_progress && GET_CODE (operand0) == SUBREG
1474 && GET_CODE (SUBREG_REG (operand0)) == REG
1475 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
1477 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1478 the code which tracks sets/uses for delete_output_reload. */
1479 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0),
1480 reg_equiv_mem [REGNO (SUBREG_REG (operand0))],
1481 SUBREG_BYTE (operand0));
1482 operand0 = alter_subreg (&temp);
1486 && reload_in_progress && GET_CODE (operand1) == REG
1487 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
1488 operand1 = reg_equiv_mem[REGNO (operand1)];
1489 else if (scratch_reg
1490 && reload_in_progress && GET_CODE (operand1) == SUBREG
1491 && GET_CODE (SUBREG_REG (operand1)) == REG
1492 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
1494 /* We must not alter SUBREG_BYTE (operand0) since that would confuse
1495 the code which tracks sets/uses for delete_output_reload. */
1496 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1),
1497 reg_equiv_mem [REGNO (SUBREG_REG (operand1))],
1498 SUBREG_BYTE (operand1));
1499 operand1 = alter_subreg (&temp);
1502 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
1503 && ((tem = find_replacement (&XEXP (operand0, 0)))
1504 != XEXP (operand0, 0)))
1505 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
1506 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
1507 && ((tem = find_replacement (&XEXP (operand1, 0)))
1508 != XEXP (operand1, 0)))
1509 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
1511 /* Handle secondary reloads for loads/stores of FP registers from
1512 REG+D addresses where D does not fit in 5 bits, including
1513 (subreg (mem (addr))) cases. */
1514 if (fp_reg_operand (operand0, mode)
1515 && ((GET_CODE (operand1) == MEM
1516 && ! memory_address_p (DFmode, XEXP (operand1, 0)))
1517 || ((GET_CODE (operand1) == SUBREG
1518 && GET_CODE (XEXP (operand1, 0)) == MEM
1519 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
1522 if (GET_CODE (operand1) == SUBREG)
1523 operand1 = XEXP (operand1, 0);
1525 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1526 it in WORD_MODE regardless of what mode it was originally given
1528 scratch_reg = force_mode (word_mode, scratch_reg);
1530 /* D might not fit in 14 bits either; for such cases load D into
1532 if (!memory_address_p (Pmode, XEXP (operand1, 0)))
1534 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1535 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)),
1537 XEXP (XEXP (operand1, 0), 0),
1541 emit_move_insn (scratch_reg, XEXP (operand1, 0));
1542 emit_insn (gen_rtx_SET (VOIDmode, operand0,
1543 gen_rtx_MEM (mode, scratch_reg)));
1546 else if (fp_reg_operand (operand1, mode)
1547 && ((GET_CODE (operand0) == MEM
1548 && ! memory_address_p (DFmode, XEXP (operand0, 0)))
1549 || ((GET_CODE (operand0) == SUBREG)
1550 && GET_CODE (XEXP (operand0, 0)) == MEM
1551 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
1554 if (GET_CODE (operand0) == SUBREG)
1555 operand0 = XEXP (operand0, 0);
1557 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1558 it in WORD_MODE regardless of what mode it was originally given
1560 scratch_reg = force_mode (word_mode, scratch_reg);
1562 /* D might not fit in 14 bits either; for such cases load D into
1564 if (!memory_address_p (Pmode, XEXP (operand0, 0)))
1566 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1));
1567 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0,
1570 XEXP (XEXP (operand0, 0),
1575 emit_move_insn (scratch_reg, XEXP (operand0, 0));
1576 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg),
1580 /* Handle secondary reloads for loads of FP registers from constant
1581 expressions by forcing the constant into memory.
1583 use scratch_reg to hold the address of the memory location.
1585 The proper fix is to change PREFERRED_RELOAD_CLASS to return
1586 NO_REGS when presented with a const_int and a register class
1587 containing only FP registers. Doing so unfortunately creates
1588 more problems than it solves. Fix this for 2.5. */
1589 else if (fp_reg_operand (operand0, mode)
1590 && CONSTANT_P (operand1)
1595 /* SCRATCH_REG will hold an address and maybe the actual data. We want
1596 it in WORD_MODE regardless of what mode it was originally given
1598 scratch_reg = force_mode (word_mode, scratch_reg);
1600 /* Force the constant into memory and put the address of the
1601 memory location into scratch_reg. */
1602 xoperands[0] = scratch_reg;
1603 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0);
1604 emit_move_sequence (xoperands, Pmode, 0);
1606 /* Now load the destination register. */
1607 emit_insn (gen_rtx_SET (mode, operand0,
1608 gen_rtx_MEM (mode, scratch_reg)));
1611 /* Handle secondary reloads for SAR. These occur when trying to load
1612 the SAR from memory, FP register, or with a constant. */
1613 else if (GET_CODE (operand0) == REG
1614 && REGNO (operand0) < FIRST_PSEUDO_REGISTER
1615 && REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
1616 && (GET_CODE (operand1) == MEM
1617 || GET_CODE (operand1) == CONST_INT
1618 || (GET_CODE (operand1) == REG
1619 && FP_REG_CLASS_P (REGNO_REG_CLASS (REGNO (operand1)))))
1622 /* D might not fit in 14 bits either; for such cases load D into
1624 if (GET_CODE (operand1) == MEM
1625 && !memory_address_p (Pmode, XEXP (operand1, 0)))
1627 /* We are reloading the address into the scratch register, so we
1628 want to make sure the scratch register is a full register. */
1629 scratch_reg = force_mode (word_mode, scratch_reg);
1631 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1));
1632 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1,
1635 XEXP (XEXP (operand1, 0),
1639 /* Now we are going to load the scratch register from memory,
1640 we want to load it in the same width as the original MEM,
1641 which must be the same as the width of the ultimate destination,
1643 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1645 emit_move_insn (scratch_reg, gen_rtx_MEM (GET_MODE (operand0),
1650 /* We want to load the scratch register using the same mode as
1651 the ultimate destination. */
1652 scratch_reg = force_mode (GET_MODE (operand0), scratch_reg);
1654 emit_move_insn (scratch_reg, operand1);
1657 /* And emit the insn to set the ultimate destination. We know that
1658 the scratch register has the same mode as the destination at this
1660 emit_move_insn (operand0, scratch_reg);
1663 /* Handle most common case: storing into a register. */
1664 else if (register_operand (operand0, mode))
1666 if (register_operand (operand1, mode)
1667 || (GET_CODE (operand1) == CONST_INT
1668 && cint_ok_for_move (INTVAL (operand1)))
1669 || (operand1 == CONST0_RTX (mode))
1670 || (GET_CODE (operand1) == HIGH
1671 && !symbolic_operand (XEXP (operand1, 0), VOIDmode))
1672 /* Only `general_operands' can come here, so MEM is ok. */
1673 || GET_CODE (operand1) == MEM)
1675 /* Run this case quickly. */
1676 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1680 else if (GET_CODE (operand0) == MEM)
1682 if (mode == DFmode && operand1 == CONST0_RTX (mode)
1683 && !(reload_in_progress || reload_completed))
1685 rtx temp = gen_reg_rtx (DFmode);
1687 emit_insn (gen_rtx_SET (VOIDmode, temp, operand1));
1688 emit_insn (gen_rtx_SET (VOIDmode, operand0, temp));
1691 if (register_operand (operand1, mode) || operand1 == CONST0_RTX (mode))
1693 /* Run this case quickly. */
1694 emit_insn (gen_rtx_SET (VOIDmode, operand0, operand1));
1697 if (! (reload_in_progress || reload_completed))
1699 operands[0] = validize_mem (operand0);
1700 operands[1] = operand1 = force_reg (mode, operand1);
1704 /* Simplify the source if we need to.
1705 Note we do have to handle function labels here, even though we do
1706 not consider them legitimate constants. Loop optimizations can
1707 call the emit_move_xxx with one as a source. */
1708 if ((GET_CODE (operand1) != HIGH && immediate_operand (operand1, mode))
1709 || function_label_operand (operand1, mode)
1710 || (GET_CODE (operand1) == HIGH
1711 && symbolic_operand (XEXP (operand1, 0), mode)))
1715 if (GET_CODE (operand1) == HIGH)
1718 operand1 = XEXP (operand1, 0);
1720 if (symbolic_operand (operand1, mode))
1722 /* Argh. The assembler and linker can't handle arithmetic
1725 So we force the plabel into memory, load operand0 from
1726 the memory location, then add in the constant part. */
1727 if ((GET_CODE (operand1) == CONST
1728 && GET_CODE (XEXP (operand1, 0)) == PLUS
1729 && function_label_operand (XEXP (XEXP (operand1, 0), 0), Pmode))
1730 || function_label_operand (operand1, mode))
1732 rtx temp, const_part;
1734 /* Figure out what (if any) scratch register to use. */
1735 if (reload_in_progress || reload_completed)
1737 scratch_reg = scratch_reg ? scratch_reg : operand0;
1738 /* SCRATCH_REG will hold an address and maybe the actual
1739 data. We want it in WORD_MODE regardless of what mode it
1740 was originally given to us. */
1741 scratch_reg = force_mode (word_mode, scratch_reg);
1744 scratch_reg = gen_reg_rtx (Pmode);
1746 if (GET_CODE (operand1) == CONST)
1748 /* Save away the constant part of the expression. */
1749 const_part = XEXP (XEXP (operand1, 0), 1);
1750 if (GET_CODE (const_part) != CONST_INT)
1753 /* Force the function label into memory. */
1754 temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
1758 /* No constant part. */
1759 const_part = NULL_RTX;
1761 /* Force the function label into memory. */
1762 temp = force_const_mem (mode, operand1);
1766 /* Get the address of the memory location. PIC-ify it if
1768 temp = XEXP (temp, 0);
1770 temp = legitimize_pic_address (temp, mode, scratch_reg);
1772 /* Put the address of the memory location into our destination
1775 emit_move_sequence (operands, mode, scratch_reg);
1777 /* Now load from the memory location into our destination
1779 operands[1] = gen_rtx_MEM (Pmode, operands[0]);
1780 emit_move_sequence (operands, mode, scratch_reg);
1782 /* And add back in the constant part. */
1783 if (const_part != NULL_RTX)
1784 expand_inc (operand0, const_part);
1793 if (reload_in_progress || reload_completed)
1795 temp = scratch_reg ? scratch_reg : operand0;
1796 /* TEMP will hold an address and maybe the actual
1797 data. We want it in WORD_MODE regardless of what mode it
1798 was originally given to us. */
1799 temp = force_mode (word_mode, temp);
1802 temp = gen_reg_rtx (Pmode);
1804 /* (const (plus (symbol) (const_int))) must be forced to
1805 memory during/after reload if the const_int will not fit
1807 if (GET_CODE (operand1) == CONST
1808 && GET_CODE (XEXP (operand1, 0)) == PLUS
1809 && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
1810 && !INT_14_BITS (XEXP (XEXP (operand1, 0), 1))
1811 && (reload_completed || reload_in_progress)
1814 operands[1] = force_const_mem (mode, operand1);
1815 operands[1] = legitimize_pic_address (XEXP (operands[1], 0),
1817 emit_move_sequence (operands, mode, temp);
1821 operands[1] = legitimize_pic_address (operand1, mode, temp);
1822 emit_insn (gen_rtx_SET (VOIDmode, operand0, operands[1]));
1825 /* On the HPPA, references to data space are supposed to use dp,
1826 register 27, but showing it in the RTL inhibits various cse
1827 and loop optimizations. */
1832 if (reload_in_progress || reload_completed)
1834 temp = scratch_reg ? scratch_reg : operand0;
1835 /* TEMP will hold an address and maybe the actual
1836 data. We want it in WORD_MODE regardless of what mode it
1837 was originally given to us. */
1838 temp = force_mode (word_mode, temp);
1841 temp = gen_reg_rtx (mode);
1843 /* Loading a SYMBOL_REF into a register makes that register
1844 safe to be used as the base in an indexed address.
1846 Don't mark hard registers though. That loses. */
1847 if (GET_CODE (operand0) == REG
1848 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
1849 REG_POINTER (operand0) = 1;
1850 if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
1851 REG_POINTER (temp) = 1;
1853 set = gen_rtx_SET (mode, operand0, temp);
1855 set = gen_rtx_SET (VOIDmode,
1857 gen_rtx_LO_SUM (mode, temp, operand1));
1859 emit_insn (gen_rtx_SET (VOIDmode,
1861 gen_rtx_HIGH (mode, operand1)));
1867 else if (GET_CODE (operand1) != CONST_INT
1868 || ! cint_ok_for_move (INTVAL (operand1)))
1870 rtx extend = NULL_RTX;
1873 if (TARGET_64BIT && GET_CODE (operand1) == CONST_INT
1874 && HOST_BITS_PER_WIDE_INT > 32
1875 && GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
1877 HOST_WIDE_INT val = INTVAL (operand1);
1880 /* Extract the low order 32 bits of the value and sign extend.
1881 If the new value is the same as the original value, we can
1882 can use the original value as-is. If the new value is
1883 different, we use it and insert the most-significant 32-bits
1884 of the original value into the final result. */
1885 nval = ((val & (((HOST_WIDE_INT) 2 << 31) - 1))
1886 ^ ((HOST_WIDE_INT) 1 << 31)) - ((HOST_WIDE_INT) 1 << 31);
1889 #if HOST_BITS_PER_WIDE_INT > 32
1890 extend = GEN_INT (val >> 32);
1892 operand1 = GEN_INT (nval);
1896 if (reload_in_progress || reload_completed)
1899 temp = gen_reg_rtx (mode);
1901 /* We don't directly split DImode constants on 32-bit targets
1902 because PLUS uses an 11-bit immediate and the insn sequence
1903 generated is not as efficient as the one using HIGH/LO_SUM. */
1904 if (GET_CODE (operand1) == CONST_INT
1905 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
1907 /* Directly break constant into high and low parts. This
1908 provides better optimization opportunities because various
1909 passes recognize constants split with PLUS but not LO_SUM.
1910 We use a 14-bit signed low part except when the addition
1911 of 0x4000 to the high part might change the sign of the
1913 HOST_WIDE_INT value = INTVAL (operand1);
1914 HOST_WIDE_INT low = value & 0x3fff;
1915 HOST_WIDE_INT high = value & ~ 0x3fff;
1919 if (high == 0x7fffc000 || (mode == HImode && high == 0x4000))
1927 emit_insn (gen_rtx_SET (VOIDmode, temp, GEN_INT (high)));
1928 operands[1] = gen_rtx_PLUS (mode, temp, GEN_INT (low));
1932 emit_insn (gen_rtx_SET (VOIDmode, temp,
1933 gen_rtx_HIGH (mode, operand1)));
1934 operands[1] = gen_rtx_LO_SUM (mode, temp, operand1);
1937 emit_move_insn (operands[0], operands[1]);
1939 if (extend != NULL_RTX)
1940 emit_insn (gen_insv (operands[0], GEN_INT (32), const0_rtx,
1946 /* Now have insn-emit do whatever it normally does. */
1950 /* Examine EXP and return nonzero if it contains an ADDR_EXPR (meaning
1951 it will need a link/runtime reloc). */
1959 switch (TREE_CODE (exp))
1966 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1967 reloc |= reloc_needed (TREE_OPERAND (exp, 1));
1972 case NON_LVALUE_EXPR:
1973 reloc = reloc_needed (TREE_OPERAND (exp, 0));
1979 for (link = CONSTRUCTOR_ELTS (exp); link; link = TREE_CHAIN (link))
1980 if (TREE_VALUE (link) != 0)
1981 reloc |= reloc_needed (TREE_VALUE (link));
1994 /* Does operand (which is a symbolic_operand) live in text space?
1995 If so, SYMBOL_REF_FLAG, which is set by pa_encode_section_info,
1999 read_only_operand (operand, mode)
2001 enum machine_mode mode ATTRIBUTE_UNUSED;
2003 if (GET_CODE (operand) == CONST)
2004 operand = XEXP (XEXP (operand, 0), 0);
2007 if (GET_CODE (operand) == SYMBOL_REF)
2008 return SYMBOL_REF_FLAG (operand) && !CONSTANT_POOL_ADDRESS_P (operand);
2012 if (GET_CODE (operand) == SYMBOL_REF)
2013 return SYMBOL_REF_FLAG (operand) || CONSTANT_POOL_ADDRESS_P (operand);
2019 /* Return the best assembler insn template
2020 for moving operands[1] into operands[0] as a fullword. */
2022 singlemove_string (operands)
2025 HOST_WIDE_INT intval;
2027 if (GET_CODE (operands[0]) == MEM)
2028 return "stw %r1,%0";
2029 if (GET_CODE (operands[1]) == MEM)
2031 if (GET_CODE (operands[1]) == CONST_DOUBLE)
2036 if (GET_MODE (operands[1]) != SFmode)
2039 /* Translate the CONST_DOUBLE to a CONST_INT with the same target
2041 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[1]);
2042 REAL_VALUE_TO_TARGET_SINGLE (d, i);
2044 operands[1] = GEN_INT (i);
2045 /* Fall through to CONST_INT case. */
2047 if (GET_CODE (operands[1]) == CONST_INT)
2049 intval = INTVAL (operands[1]);
2051 if (VAL_14_BITS_P (intval))
2053 else if ((intval & 0x7ff) == 0)
2054 return "ldil L'%1,%0";
2055 else if (zdepi_cint_p (intval))
2056 return "{zdepi %Z1,%0|depwi,z %Z1,%0}";
2058 return "ldil L'%1,%0\n\tldo R'%1(%0),%0";
2060 return "copy %1,%0";
2064 /* Compute position (in OP[1]) and width (in OP[2])
2065 useful for copying IMM to a register using the zdepi
2066 instructions. Store the immediate value to insert in OP[0]. */
2068 compute_zdepwi_operands (imm, op)
2069 unsigned HOST_WIDE_INT imm;
2074 /* Find the least significant set bit in IMM. */
2075 for (lsb = 0; lsb < 32; lsb++)
2082 /* Choose variants based on *sign* of the 5-bit field. */
2083 if ((imm & 0x10) == 0)
2084 len = (lsb <= 28) ? 4 : 32 - lsb;
2087 /* Find the width of the bitstring in IMM. */
2088 for (len = 5; len < 32; len++)
2090 if ((imm & (1 << len)) == 0)
2094 /* Sign extend IMM as a 5-bit value. */
2095 imm = (imm & 0xf) - 0x10;
2103 /* Compute position (in OP[1]) and width (in OP[2])
2104 useful for copying IMM to a register using the depdi,z
2105 instructions. Store the immediate value to insert in OP[0]. */
2107 compute_zdepdi_operands (imm, op)
2108 unsigned HOST_WIDE_INT imm;
2111 HOST_WIDE_INT lsb, len;
2113 /* Find the least significant set bit in IMM. */
2114 for (lsb = 0; lsb < HOST_BITS_PER_WIDE_INT; lsb++)
2121 /* Choose variants based on *sign* of the 5-bit field. */
2122 if ((imm & 0x10) == 0)
2123 len = ((lsb <= HOST_BITS_PER_WIDE_INT - 4)
2124 ? 4 : HOST_BITS_PER_WIDE_INT - lsb);
2127 /* Find the width of the bitstring in IMM. */
2128 for (len = 5; len < HOST_BITS_PER_WIDE_INT; len++)
2130 if ((imm & ((unsigned HOST_WIDE_INT) 1 << len)) == 0)
2134 /* Sign extend IMM as a 5-bit value. */
2135 imm = (imm & 0xf) - 0x10;
2143 /* Output assembler code to perform a doubleword move insn
2144 with operands OPERANDS. */
2147 output_move_double (operands)
2150 enum { REGOP, OFFSOP, MEMOP, CNSTOP, RNDOP } optype0, optype1;
2152 rtx addreg0 = 0, addreg1 = 0;
2154 /* First classify both operands. */
2156 if (REG_P (operands[0]))
2158 else if (offsettable_memref_p (operands[0]))
2160 else if (GET_CODE (operands[0]) == MEM)
2165 if (REG_P (operands[1]))
2167 else if (CONSTANT_P (operands[1]))
2169 else if (offsettable_memref_p (operands[1]))
2171 else if (GET_CODE (operands[1]) == MEM)
2176 /* Check for the cases that the operand constraints are not
2177 supposed to allow to happen. Abort if we get one,
2178 because generating code for these cases is painful. */
2180 if (optype0 != REGOP && optype1 != REGOP)
2183 /* Handle auto decrementing and incrementing loads and stores
2184 specifically, since the structure of the function doesn't work
2185 for them without major modification. Do it better when we learn
2186 this port about the general inc/dec addressing of PA.
2187 (This was written by tege. Chide him if it doesn't work.) */
2189 if (optype0 == MEMOP)
2191 /* We have to output the address syntax ourselves, since print_operand
2192 doesn't deal with the addresses we want to use. Fix this later. */
2194 rtx addr = XEXP (operands[0], 0);
2195 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2197 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2199 operands[0] = XEXP (addr, 0);
2200 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2203 if (!reg_overlap_mentioned_p (high_reg, addr))
2205 /* No overlap between high target register and address
2206 register. (We do this in a non-obvious way to
2207 save a register file writeback) */
2208 if (GET_CODE (addr) == POST_INC)
2209 return "{stws|stw},ma %1,8(%0)\n\tstw %R1,-4(%0)";
2210 return "{stws|stw},ma %1,-8(%0)\n\tstw %R1,12(%0)";
2215 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2217 rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
2219 operands[0] = XEXP (addr, 0);
2220 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[0]) != REG)
2223 if (!reg_overlap_mentioned_p (high_reg, addr))
2225 /* No overlap between high target register and address
2226 register. (We do this in a non-obvious way to
2227 save a register file writeback) */
2228 if (GET_CODE (addr) == PRE_INC)
2229 return "{stws|stw},mb %1,8(%0)\n\tstw %R1,4(%0)";
2230 return "{stws|stw},mb %1,-8(%0)\n\tstw %R1,4(%0)";
2236 if (optype1 == MEMOP)
2238 /* We have to output the address syntax ourselves, since print_operand
2239 doesn't deal with the addresses we want to use. Fix this later. */
2241 rtx addr = XEXP (operands[1], 0);
2242 if (GET_CODE (addr) == POST_INC || GET_CODE (addr) == POST_DEC)
2244 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2246 operands[1] = XEXP (addr, 0);
2247 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2250 if (!reg_overlap_mentioned_p (high_reg, addr))
2252 /* No overlap between high target register and address
2253 register. (We do this in a non-obvious way to
2254 save a register file writeback) */
2255 if (GET_CODE (addr) == POST_INC)
2256 return "{ldws|ldw},ma 8(%1),%0\n\tldw -4(%1),%R0";
2257 return "{ldws|ldw},ma -8(%1),%0\n\tldw 12(%1),%R0";
2261 /* This is an undefined situation. We should load into the
2262 address register *and* update that register. Probably
2263 we don't need to handle this at all. */
2264 if (GET_CODE (addr) == POST_INC)
2265 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma 8(%1),%0";
2266 return "ldw 4(%1),%R0\n\t{ldws|ldw},ma -8(%1),%0";
2269 else if (GET_CODE (addr) == PRE_INC || GET_CODE (addr) == PRE_DEC)
2271 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2273 operands[1] = XEXP (addr, 0);
2274 if (GET_CODE (operands[0]) != REG || GET_CODE (operands[1]) != REG)
2277 if (!reg_overlap_mentioned_p (high_reg, addr))
2279 /* No overlap between high target register and address
2280 register. (We do this in a non-obvious way to
2281 save a register file writeback) */
2282 if (GET_CODE (addr) == PRE_INC)
2283 return "{ldws|ldw},mb 8(%1),%0\n\tldw 4(%1),%R0";
2284 return "{ldws|ldw},mb -8(%1),%0\n\tldw 4(%1),%R0";
2288 /* This is an undefined situation. We should load into the
2289 address register *and* update that register. Probably
2290 we don't need to handle this at all. */
2291 if (GET_CODE (addr) == PRE_INC)
2292 return "ldw 12(%1),%R0\n\t{ldws|ldw},mb 8(%1),%0";
2293 return "ldw -4(%1),%R0\n\t{ldws|ldw},mb -8(%1),%0";
2296 else if (GET_CODE (addr) == PLUS
2297 && GET_CODE (XEXP (addr, 0)) == MULT)
2299 rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
2301 if (!reg_overlap_mentioned_p (high_reg, addr))
2305 xoperands[0] = high_reg;
2306 xoperands[1] = XEXP (addr, 1);
2307 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2308 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2309 output_asm_insn ("{sh%O3addl %2,%1,%0|shladd,l %2,%O3,%1,%0}",
2311 return "ldw 4(%0),%R0\n\tldw 0(%0),%0";
2317 xoperands[0] = high_reg;
2318 xoperands[1] = XEXP (addr, 1);
2319 xoperands[2] = XEXP (XEXP (addr, 0), 0);
2320 xoperands[3] = XEXP (XEXP (addr, 0), 1);
2321 output_asm_insn ("{sh%O3addl %2,%1,%R0|shladd,l %2,%O3,%1,%R0}",
2323 return "ldw 0(%R0),%0\n\tldw 4(%R0),%R0";
2328 /* If an operand is an unoffsettable memory ref, find a register
2329 we can increment temporarily to make it refer to the second word. */
2331 if (optype0 == MEMOP)
2332 addreg0 = find_addr_reg (XEXP (operands[0], 0));
2334 if (optype1 == MEMOP)
2335 addreg1 = find_addr_reg (XEXP (operands[1], 0));
2337 /* Ok, we can do one word at a time.
2338 Normally we do the low-numbered word first.
2340 In either case, set up in LATEHALF the operands to use
2341 for the high-numbered word and in some cases alter the
2342 operands in OPERANDS to be suitable for the low-numbered word. */
2344 if (optype0 == REGOP)
2345 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2346 else if (optype0 == OFFSOP)
2347 latehalf[0] = adjust_address (operands[0], SImode, 4);
2349 latehalf[0] = operands[0];
2351 if (optype1 == REGOP)
2352 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2353 else if (optype1 == OFFSOP)
2354 latehalf[1] = adjust_address (operands[1], SImode, 4);
2355 else if (optype1 == CNSTOP)
2356 split_double (operands[1], &operands[1], &latehalf[1]);
2358 latehalf[1] = operands[1];
2360 /* If the first move would clobber the source of the second one,
2361 do them in the other order.
2363 This can happen in two cases:
2365 mem -> register where the first half of the destination register
2366 is the same register used in the memory's address. Reload
2367 can create such insns.
2369 mem in this case will be either register indirect or register
2370 indirect plus a valid offset.
2372 register -> register move where REGNO(dst) == REGNO(src + 1)
2373 someone (Tim/Tege?) claimed this can happen for parameter loads.
2375 Handle mem -> register case first. */
2376 if (optype0 == REGOP
2377 && (optype1 == MEMOP || optype1 == OFFSOP)
2378 && refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2381 /* Do the late half first. */
2383 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2384 output_asm_insn (singlemove_string (latehalf), latehalf);
2388 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2389 return singlemove_string (operands);
2392 /* Now handle register -> register case. */
2393 if (optype0 == REGOP && optype1 == REGOP
2394 && REGNO (operands[0]) == REGNO (operands[1]) + 1)
2396 output_asm_insn (singlemove_string (latehalf), latehalf);
2397 return singlemove_string (operands);
2400 /* Normal case: do the two words, low-numbered first. */
2402 output_asm_insn (singlemove_string (operands), operands);
2404 /* Make any unoffsettable addresses point at high-numbered word. */
2406 output_asm_insn ("ldo 4(%0),%0", &addreg0);
2408 output_asm_insn ("ldo 4(%0),%0", &addreg1);
2411 output_asm_insn (singlemove_string (latehalf), latehalf);
2413 /* Undo the adds we just did. */
2415 output_asm_insn ("ldo -4(%0),%0", &addreg0);
2417 output_asm_insn ("ldo -4(%0),%0", &addreg1);
2423 output_fp_move_double (operands)
2426 if (FP_REG_P (operands[0]))
2428 if (FP_REG_P (operands[1])
2429 || operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2430 output_asm_insn ("fcpy,dbl %f1,%0", operands);
2432 output_asm_insn ("fldd%F1 %1,%0", operands);
2434 else if (FP_REG_P (operands[1]))
2436 output_asm_insn ("fstd%F0 %1,%0", operands);
2438 else if (operands[1] == CONST0_RTX (GET_MODE (operands[0])))
2440 if (GET_CODE (operands[0]) == REG)
2443 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2444 xoperands[0] = operands[0];
2445 output_asm_insn ("copy %%r0,%0\n\tcopy %%r0,%1", xoperands);
2447 /* This is a pain. You have to be prepared to deal with an
2448 arbitrary address here including pre/post increment/decrement.
2450 so avoid this in the MD. */
2458 /* Return a REG that occurs in ADDR with coefficient 1.
2459 ADDR can be effectively incremented by incrementing REG. */
2462 find_addr_reg (addr)
2465 while (GET_CODE (addr) == PLUS)
2467 if (GET_CODE (XEXP (addr, 0)) == REG)
2468 addr = XEXP (addr, 0);
2469 else if (GET_CODE (XEXP (addr, 1)) == REG)
2470 addr = XEXP (addr, 1);
2471 else if (CONSTANT_P (XEXP (addr, 0)))
2472 addr = XEXP (addr, 1);
2473 else if (CONSTANT_P (XEXP (addr, 1)))
2474 addr = XEXP (addr, 0);
2478 if (GET_CODE (addr) == REG)
2483 /* Emit code to perform a block move.
2485 OPERANDS[0] is the destination pointer as a REG, clobbered.
2486 OPERANDS[1] is the source pointer as a REG, clobbered.
2487 OPERANDS[2] is a register for temporary storage.
2488 OPERANDS[4] is the size as a CONST_INT
2489 OPERANDS[3] is a register for temporary storage.
2490 OPERANDS[5] is the alignment safe to use, as a CONST_INT.
2491 OPERANDS[6] is another temporary register. */
2494 output_block_move (operands, size_is_constant)
2496 int size_is_constant ATTRIBUTE_UNUSED;
2498 int align = INTVAL (operands[5]);
2499 unsigned long n_bytes = INTVAL (operands[4]);
2501 /* We can't move more than four bytes at a time because the PA
2502 has no longer integer move insns. (Could use fp mem ops?) */
2506 /* Note that we know each loop below will execute at least twice
2507 (else we would have open-coded the copy). */
2511 /* Pre-adjust the loop counter. */
2512 operands[4] = GEN_INT (n_bytes - 8);
2513 output_asm_insn ("ldi %4,%2", operands);
2516 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2517 output_asm_insn ("{ldws|ldw},ma 4(%1),%6", operands);
2518 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2519 output_asm_insn ("addib,>= -8,%2,.-12", operands);
2520 output_asm_insn ("{stws|stw},ma %6,4(%0)", operands);
2522 /* Handle the residual. There could be up to 7 bytes of
2523 residual to copy! */
2524 if (n_bytes % 8 != 0)
2526 operands[4] = GEN_INT (n_bytes % 4);
2527 if (n_bytes % 8 >= 4)
2528 output_asm_insn ("{ldws|ldw},ma 4(%1),%3", operands);
2529 if (n_bytes % 4 != 0)
2530 output_asm_insn ("ldw 0(%1),%6", operands);
2531 if (n_bytes % 8 >= 4)
2532 output_asm_insn ("{stws|stw},ma %3,4(%0)", operands);
2533 if (n_bytes % 4 != 0)
2534 output_asm_insn ("{stbys|stby},e %6,%4(%0)", operands);
2539 /* Pre-adjust the loop counter. */
2540 operands[4] = GEN_INT (n_bytes - 4);
2541 output_asm_insn ("ldi %4,%2", operands);
2544 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2545 output_asm_insn ("{ldhs|ldh},ma 2(%1),%6", operands);
2546 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2547 output_asm_insn ("addib,>= -4,%2,.-12", operands);
2548 output_asm_insn ("{sths|sth},ma %6,2(%0)", operands);
2550 /* Handle the residual. */
2551 if (n_bytes % 4 != 0)
2553 if (n_bytes % 4 >= 2)
2554 output_asm_insn ("{ldhs|ldh},ma 2(%1),%3", operands);
2555 if (n_bytes % 2 != 0)
2556 output_asm_insn ("ldb 0(%1),%6", operands);
2557 if (n_bytes % 4 >= 2)
2558 output_asm_insn ("{sths|sth},ma %3,2(%0)", operands);
2559 if (n_bytes % 2 != 0)
2560 output_asm_insn ("stb %6,0(%0)", operands);
2565 /* Pre-adjust the loop counter. */
2566 operands[4] = GEN_INT (n_bytes - 2);
2567 output_asm_insn ("ldi %4,%2", operands);
2570 output_asm_insn ("{ldbs|ldb},ma 1(%1),%3", operands);
2571 output_asm_insn ("{ldbs|ldb},ma 1(%1),%6", operands);
2572 output_asm_insn ("{stbs|stb},ma %3,1(%0)", operands);
2573 output_asm_insn ("addib,>= -2,%2,.-12", operands);
2574 output_asm_insn ("{stbs|stb},ma %6,1(%0)", operands);
2576 /* Handle the residual. */
2577 if (n_bytes % 2 != 0)
2579 output_asm_insn ("ldb 0(%1),%3", operands);
2580 output_asm_insn ("stb %3,0(%0)", operands);
2589 /* Count the number of insns necessary to handle this block move.
2591 Basic structure is the same as emit_block_move, except that we
2592 count insns rather than emit them. */
2595 compute_movstrsi_length (insn)
2598 rtx pat = PATTERN (insn);
2599 unsigned int align = INTVAL (XEXP (XVECEXP (pat, 0, 7), 0));
2600 unsigned long n_bytes = INTVAL (XEXP (XVECEXP (pat, 0, 6), 0));
2601 unsigned int n_insns = 0;
2603 /* We can't move more than four bytes at a time because the PA
2604 has no longer integer move insns. (Could use fp mem ops?) */
2608 /* The basic copying loop. */
2612 if (n_bytes % (2 * align) != 0)
2614 if ((n_bytes % (2 * align)) >= align)
2617 if ((n_bytes % align) != 0)
2621 /* Lengths are expressed in bytes now; each insn is 4 bytes. */
2627 output_and (operands)
2630 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2632 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2633 int ls0, ls1, ms0, p, len;
2635 for (ls0 = 0; ls0 < 32; ls0++)
2636 if ((mask & (1 << ls0)) == 0)
2639 for (ls1 = ls0; ls1 < 32; ls1++)
2640 if ((mask & (1 << ls1)) != 0)
2643 for (ms0 = ls1; ms0 < 32; ms0++)
2644 if ((mask & (1 << ms0)) == 0)
2657 operands[2] = GEN_INT (len);
2658 return "{extru|extrw,u} %1,31,%2,%0";
2662 /* We could use this `depi' for the case above as well, but `depi'
2663 requires one more register file access than an `extru'. */
2668 operands[2] = GEN_INT (p);
2669 operands[3] = GEN_INT (len);
2670 return "{depi|depwi} 0,%2,%3,%0";
2674 return "and %1,%2,%0";
2677 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2678 storing the result in operands[0]. */
2680 output_64bit_and (operands)
2683 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
2685 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2686 int ls0, ls1, ms0, p, len;
2688 for (ls0 = 0; ls0 < HOST_BITS_PER_WIDE_INT; ls0++)
2689 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls0)) == 0)
2692 for (ls1 = ls0; ls1 < HOST_BITS_PER_WIDE_INT; ls1++)
2693 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ls1)) != 0)
2696 for (ms0 = ls1; ms0 < HOST_BITS_PER_WIDE_INT; ms0++)
2697 if ((mask & ((unsigned HOST_WIDE_INT) 1 << ms0)) == 0)
2700 if (ms0 != HOST_BITS_PER_WIDE_INT)
2703 if (ls1 == HOST_BITS_PER_WIDE_INT)
2710 operands[2] = GEN_INT (len);
2711 return "extrd,u %1,63,%2,%0";
2715 /* We could use this `depi' for the case above as well, but `depi'
2716 requires one more register file access than an `extru'. */
2721 operands[2] = GEN_INT (p);
2722 operands[3] = GEN_INT (len);
2723 return "depdi 0,%2,%3,%0";
2727 return "and %1,%2,%0";
2731 output_ior (operands)
2734 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2735 int bs0, bs1, p, len;
2737 if (INTVAL (operands[2]) == 0)
2738 return "copy %1,%0";
2740 for (bs0 = 0; bs0 < 32; bs0++)
2741 if ((mask & (1 << bs0)) != 0)
2744 for (bs1 = bs0; bs1 < 32; bs1++)
2745 if ((mask & (1 << bs1)) == 0)
2748 if (bs1 != 32 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2754 operands[2] = GEN_INT (p);
2755 operands[3] = GEN_INT (len);
2756 return "{depi|depwi} -1,%2,%3,%0";
2759 /* Return a string to perform a bitwise-and of operands[1] with operands[2]
2760 storing the result in operands[0]. */
2762 output_64bit_ior (operands)
2765 unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
2766 int bs0, bs1, p, len;
2768 if (INTVAL (operands[2]) == 0)
2769 return "copy %1,%0";
2771 for (bs0 = 0; bs0 < HOST_BITS_PER_WIDE_INT; bs0++)
2772 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs0)) != 0)
2775 for (bs1 = bs0; bs1 < HOST_BITS_PER_WIDE_INT; bs1++)
2776 if ((mask & ((unsigned HOST_WIDE_INT) 1 << bs1)) == 0)
2779 if (bs1 != HOST_BITS_PER_WIDE_INT
2780 && ((unsigned HOST_WIDE_INT) 1 << bs1) <= mask)
2786 operands[2] = GEN_INT (p);
2787 operands[3] = GEN_INT (len);
2788 return "depdi -1,%2,%3,%0";
2791 /* Target hook for assembling integer objects. This code handles
2792 aligned SI and DI integers specially, since function references must
2793 be preceded by P%. */
2796 pa_assemble_integer (x, size, aligned_p)
2801 if (size == UNITS_PER_WORD && aligned_p
2802 && function_label_operand (x, VOIDmode))
2804 fputs (size == 8? "\t.dword\tP%" : "\t.word\tP%", asm_out_file);
2805 output_addr_const (asm_out_file, x);
2806 fputc ('\n', asm_out_file);
2809 return default_assemble_integer (x, size, aligned_p);
2812 /* Output an ascii string. */
2814 output_ascii (file, p, size)
2821 unsigned char partial_output[16]; /* Max space 4 chars can occupy. */
2823 /* The HP assembler can only take strings of 256 characters at one
2824 time. This is a limitation on input line length, *not* the
2825 length of the string. Sigh. Even worse, it seems that the
2826 restriction is in number of input characters (see \xnn &
2827 \whatever). So we have to do this very carefully. */
2829 fputs ("\t.STRING \"", file);
2832 for (i = 0; i < size; i += 4)
2836 for (io = 0, co = 0; io < MIN (4, size - i); io++)
2838 register unsigned int c = (unsigned char) p[i + io];
2840 if (c == '\"' || c == '\\')
2841 partial_output[co++] = '\\';
2842 if (c >= ' ' && c < 0177)
2843 partial_output[co++] = c;
2847 partial_output[co++] = '\\';
2848 partial_output[co++] = 'x';
2849 hexd = c / 16 - 0 + '0';
2851 hexd -= '9' - 'a' + 1;
2852 partial_output[co++] = hexd;
2853 hexd = c % 16 - 0 + '0';
2855 hexd -= '9' - 'a' + 1;
2856 partial_output[co++] = hexd;
2859 if (chars_output + co > 243)
2861 fputs ("\"\n\t.STRING \"", file);
2864 fwrite (partial_output, 1, (size_t) co, file);
2868 fputs ("\"\n", file);
2871 /* Try to rewrite floating point comparisons & branches to avoid
2872 useless add,tr insns.
2874 CHECK_NOTES is nonzero if we should examine REG_DEAD notes
2875 to see if FPCC is dead. CHECK_NOTES is nonzero for the
2876 first attempt to remove useless add,tr insns. It is zero
2877 for the second pass as reorg sometimes leaves bogus REG_DEAD
2880 When CHECK_NOTES is zero we can only eliminate add,tr insns
2881 when there's a 1:1 correspondence between fcmp and ftest/fbranch
2884 remove_useless_addtr_insns (check_notes)
2888 static int pass = 0;
2890 /* This is fairly cheap, so always run it when optimizing. */
2894 int fbranch_count = 0;
2896 /* Walk all the insns in this function looking for fcmp & fbranch
2897 instructions. Keep track of how many of each we find. */
2898 for (insn = get_insns (); insn; insn = next_insn (insn))
2902 /* Ignore anything that isn't an INSN or a JUMP_INSN. */
2903 if (GET_CODE (insn) != INSN && GET_CODE (insn) != JUMP_INSN)
2906 tmp = PATTERN (insn);
2908 /* It must be a set. */
2909 if (GET_CODE (tmp) != SET)
2912 /* If the destination is CCFP, then we've found an fcmp insn. */
2913 tmp = SET_DEST (tmp);
2914 if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
2920 tmp = PATTERN (insn);
2921 /* If this is an fbranch instruction, bump the fbranch counter. */
2922 if (GET_CODE (tmp) == SET
2923 && SET_DEST (tmp) == pc_rtx
2924 && GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
2925 && GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
2926 && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
2927 && REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
2935 /* Find all floating point compare + branch insns. If possible,
2936 reverse the comparison & the branch to avoid add,tr insns. */
2937 for (insn = get_insns (); insn; insn = next_insn (insn))
2941 /* Ignore anything that isn't an INSN. */
2942 if (GET_CODE (insn) != INSN)
2945 tmp = PATTERN (insn);
2947 /* It must be a set. */
2948 if (GET_CODE (tmp) != SET)
2951 /* The destination must be CCFP, which is register zero. */
2952 tmp = SET_DEST (tmp);
2953 if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
2956 /* INSN should be a set of CCFP.
2958 See if the result of this insn is used in a reversed FP
2959 conditional branch. If so, reverse our condition and
2960 the branch. Doing so avoids useless add,tr insns. */
2961 next = next_insn (insn);
2964 /* Jumps, calls and labels stop our search. */
2965 if (GET_CODE (next) == JUMP_INSN
2966 || GET_CODE (next) == CALL_INSN
2967 || GET_CODE (next) == CODE_LABEL)
2970 /* As does another fcmp insn. */
2971 if (GET_CODE (next) == INSN
2972 && GET_CODE (PATTERN (next)) == SET
2973 && GET_CODE (SET_DEST (PATTERN (next))) == REG
2974 && REGNO (SET_DEST (PATTERN (next))) == 0)
2977 next = next_insn (next);
2980 /* Is NEXT_INSN a branch? */
2982 && GET_CODE (next) == JUMP_INSN)
2984 rtx pattern = PATTERN (next);
2986 /* If it a reversed fp conditional branch (eg uses add,tr)
2987 and CCFP dies, then reverse our conditional and the branch
2988 to avoid the add,tr. */
2989 if (GET_CODE (pattern) == SET
2990 && SET_DEST (pattern) == pc_rtx
2991 && GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
2992 && GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
2993 && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
2994 && REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
2995 && GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
2996 && (fcmp_count == fbranch_count
2998 && find_regno_note (next, REG_DEAD, 0))))
3000 /* Reverse the branch. */
3001 tmp = XEXP (SET_SRC (pattern), 1);
3002 XEXP (SET_SRC (pattern), 1) = XEXP (SET_SRC (pattern), 2);
3003 XEXP (SET_SRC (pattern), 2) = tmp;
3004 INSN_CODE (next) = -1;
3006 /* Reverse our condition. */
3007 tmp = PATTERN (insn);
3008 PUT_CODE (XEXP (tmp, 1),
3009 (reverse_condition_maybe_unordered
3010 (GET_CODE (XEXP (tmp, 1)))));
3020 /* You may have trouble believing this, but this is the 32 bit HP-PA
3025 Variable arguments (optional; any number may be allocated)
3027 SP-(4*(N+9)) arg word N
3032 Fixed arguments (must be allocated; may remain unused)
3041 SP-32 External Data Pointer (DP)
3043 SP-24 External/stub RP (RP')
3047 SP-8 Calling Stub RP (RP'')
3052 SP-0 Stack Pointer (points to next available address)
3056 /* This function saves registers as follows. Registers marked with ' are
3057 this function's registers (as opposed to the previous function's).
3058 If a frame_pointer isn't needed, r4 is saved as a general register;
3059 the space for the frame pointer is still allocated, though, to keep
3065 SP (FP') Previous FP
3066 SP + 4 Alignment filler (sigh)
3067 SP + 8 Space for locals reserved here.
3071 SP + n All call saved register used.
3075 SP + o All call saved fp registers used.
3079 SP + p (SP') points to next available address.
3083 /* Global variables set by output_function_prologue(). */
3084 /* Size of frame. Need to know this to emit return insns from
3086 static int actual_fsize;
3087 static int local_fsize, save_fregs;
3089 /* Emit RTL to store REG at the memory location specified by BASE+DISP.
3090 Handle case where DISP > 8k by using the add_high_const patterns.
3092 Note in DISP > 8k case, we will leave the high part of the address
3093 in %r1. There is code in expand_hppa_{prologue,epilogue} that knows this.*/
3096 store_reg (reg, disp, base)
3097 int reg, disp, base;
3099 rtx insn, dest, src, basereg;
3101 src = gen_rtx_REG (word_mode, reg);
3102 basereg = gen_rtx_REG (Pmode, base);
3103 if (VAL_14_BITS_P (disp))
3105 dest = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3106 insn = emit_move_insn (dest, src);
3110 rtx delta = GEN_INT (disp);
3111 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3112 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3113 emit_move_insn (tmpreg, high);
3114 dest = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3115 insn = emit_move_insn (dest, src);
3119 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3120 gen_rtx_SET (VOIDmode,
3121 gen_rtx_MEM (word_mode,
3122 gen_rtx_PLUS (word_mode, basereg,
3130 RTX_FRAME_RELATED_P (insn) = 1;
3133 /* Emit RTL to store REG at the memory location specified by BASE and then
3134 add MOD to BASE. MOD must be <= 8k. */
3137 store_reg_modify (base, reg, mod)
3140 rtx insn, basereg, srcreg, delta;
3142 if (! VAL_14_BITS_P (mod))
3145 basereg = gen_rtx_REG (Pmode, base);
3146 srcreg = gen_rtx_REG (word_mode, reg);
3147 delta = GEN_INT (mod);
3149 insn = emit_insn (gen_post_store (basereg, srcreg, delta));
3152 RTX_FRAME_RELATED_P (insn) = 1;
3154 /* RTX_FRAME_RELATED_P must be set on each frame related set
3155 in a parallel with more than one element. Don't set
3156 RTX_FRAME_RELATED_P in the first set if reg is temporary
3157 register 1. The effect of this operation is recorded in
3158 the initial copy. */
3161 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 0)) = 1;
3162 RTX_FRAME_RELATED_P (XVECEXP (PATTERN (insn), 0, 1)) = 1;
3166 /* The first element of a PARALLEL is always processed if it is
3167 a SET. Thus, we need an expression list for this case. */
3169 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3170 gen_rtx_SET (VOIDmode, basereg,
3171 gen_rtx_PLUS (word_mode, basereg, delta)),
3177 /* Emit RTL to set REG to the value specified by BASE+DISP. Handle case
3178 where DISP > 8k by using the add_high_const patterns. NOTE indicates
3179 whether to add a frame note or not.
3181 In the DISP > 8k case, we leave the high part of the address in %r1.
3182 There is code in expand_hppa_{prologue,epilogue} that knows about this. */
3185 set_reg_plus_d (reg, base, disp, note)
3186 int reg, base, disp, note;
3190 if (VAL_14_BITS_P (disp))
3192 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3193 plus_constant (gen_rtx_REG (Pmode, base), disp));
3197 rtx basereg = gen_rtx_REG (Pmode, base);
3198 rtx delta = GEN_INT (disp);
3200 emit_move_insn (gen_rtx_REG (Pmode, 1),
3201 gen_rtx_PLUS (Pmode, basereg,
3202 gen_rtx_HIGH (Pmode, delta)));
3203 insn = emit_move_insn (gen_rtx_REG (Pmode, reg),
3204 gen_rtx_LO_SUM (Pmode, gen_rtx_REG (Pmode, 1),
3208 if (DO_FRAME_NOTES && note)
3209 RTX_FRAME_RELATED_P (insn) = 1;
3213 compute_frame_size (size, fregs_live)
3220 /* The code in hppa_expand_prologue and hppa_expand_epilogue must
3221 be consistent with the rounding and size calculation done here.
3222 Change them at the same time. */
3224 /* We do our own stack alignment. First, round the size of the
3225 stack locals up to a word boundary. */
3226 size = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3228 /* Space for previous frame pointer + filler. If any frame is
3229 allocated, we need to add in the STARTING_FRAME_OFFSET. We
3230 waste some space here for the sake of HP compatibility. The
3231 first slot is only used when the frame pointer is needed. */
3232 if (size || frame_pointer_needed)
3233 size += STARTING_FRAME_OFFSET;
3235 /* If the current function calls __builtin_eh_return, then we need
3236 to allocate stack space for registers that will hold data for
3237 the exception handler. */
3238 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3242 for (i = 0; EH_RETURN_DATA_REGNO (i) != INVALID_REGNUM; ++i)
3244 size += i * UNITS_PER_WORD;
3247 /* Account for space used by the callee general register saves. */
3248 for (i = 18, j = frame_pointer_needed ? 4 : 3; i >= j; i--)
3249 if (regs_ever_live[i])
3250 size += UNITS_PER_WORD;
3252 /* Account for space used by the callee floating point register saves. */
3253 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3254 if (regs_ever_live[i]
3255 || (!TARGET_64BIT && regs_ever_live[i + 1]))
3259 /* We always save both halves of the FP register, so always
3260 increment the frame size by 8 bytes. */
3264 /* If any of the floating registers are saved, account for the
3265 alignment needed for the floating point register save block. */
3268 size = (size + 7) & ~7;
3273 /* The various ABIs include space for the outgoing parameters in the
3274 size of the current function's stack frame. We don't need to align
3275 for the outgoing arguments as their alignment is set by the final
3276 rounding for the frame as a whole. */
3277 size += current_function_outgoing_args_size;
3279 /* Allocate space for the fixed frame marker. This space must be
3280 allocated for any function that makes calls or allocates
3282 if (!current_function_is_leaf || size)
3283 size += TARGET_64BIT ? 48 : 32;
3285 /* Finally, round to the preferred stack boundary. */
3286 return ((size + PREFERRED_STACK_BOUNDARY / 8 - 1)
3287 & ~(PREFERRED_STACK_BOUNDARY / 8 - 1));
3290 /* Generate the assembly code for function entry. FILE is a stdio
3291 stream to output the code to. SIZE is an int: how many units of
3292 temporary storage to allocate.
3294 Refer to the array `regs_ever_live' to determine which registers to
3295 save; `regs_ever_live[I]' is nonzero if register number I is ever
3296 used in the function. This function is responsible for knowing
3297 which registers should not be saved even if used. */
3299 /* On HP-PA, move-double insns between fpu and cpu need an 8-byte block
3300 of memory. If any fpu reg is used in the function, we allocate
3301 such a block here, at the bottom of the frame, just in case it's needed.
3303 If this function is a leaf procedure, then we may choose not
3304 to do a "save" insn. The decision about whether or not
3305 to do this is made in regclass.c. */
3308 pa_output_function_prologue (file, size)
3310 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3312 /* The function's label and associated .PROC must never be
3313 separated and must be output *after* any profiling declarations
3314 to avoid changing spaces/subspaces within a procedure. */
3315 ASM_OUTPUT_LABEL (file, XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));
3316 fputs ("\t.PROC\n", file);
3318 /* hppa_expand_prologue does the dirty work now. We just need
3319 to output the assembler directives which denote the start
3321 fprintf (file, "\t.CALLINFO FRAME=%d", actual_fsize);
3322 if (regs_ever_live[2])
3323 fputs (",CALLS,SAVE_RP", file);
3325 fputs (",NO_CALLS", file);
3327 /* The SAVE_SP flag is used to indicate that register %r3 is stored
3328 at the beginning of the frame and that it is used as the frame
3329 pointer for the frame. We do this because our current frame
3330 layout doesn't conform to that specified in the the HP runtime
3331 documentation and we need a way to indicate to programs such as
3332 GDB where %r3 is saved. The SAVE_SP flag was chosen because it
3333 isn't used by HP compilers but is supported by the assembler.
3334 However, SAVE_SP is supposed to indicate that the previous stack
3335 pointer has been saved in the frame marker. */
3336 if (frame_pointer_needed)
3337 fputs (",SAVE_SP", file);
3339 /* Pass on information about the number of callee register saves
3340 performed in the prologue.
3342 The compiler is supposed to pass the highest register number
3343 saved, the assembler then has to adjust that number before
3344 entering it into the unwind descriptor (to account for any
3345 caller saved registers with lower register numbers than the
3346 first callee saved register). */
3348 fprintf (file, ",ENTRY_GR=%d", gr_saved + 2);
3351 fprintf (file, ",ENTRY_FR=%d", fr_saved + 11);
3353 fputs ("\n\t.ENTRY\n", file);
3355 remove_useless_addtr_insns (0);
3359 hppa_expand_prologue ()
3361 int merge_sp_adjust_with_store = 0;
3362 int size = get_frame_size ();
3370 /* Compute total size for frame pointer, filler, locals and rounding to
3371 the next word boundary. Similar code appears in compute_frame_size
3372 and must be changed in tandem with this code. */
3373 local_fsize = (size + UNITS_PER_WORD - 1) & ~(UNITS_PER_WORD - 1);
3374 if (local_fsize || frame_pointer_needed)
3375 local_fsize += STARTING_FRAME_OFFSET;
3377 actual_fsize = compute_frame_size (size, &save_fregs);
3379 /* Compute a few things we will use often. */
3380 tmpreg = gen_rtx_REG (word_mode, 1);
3382 /* Save RP first. The calling conventions manual states RP will
3383 always be stored into the caller's frame at sp - 20 or sp - 16
3384 depending on which ABI is in use. */
3385 if (regs_ever_live[2] || current_function_calls_eh_return)
3386 store_reg (2, TARGET_64BIT ? -16 : -20, STACK_POINTER_REGNUM);
3388 /* Allocate the local frame and set up the frame pointer if needed. */
3389 if (actual_fsize != 0)
3391 if (frame_pointer_needed)
3393 /* Copy the old frame pointer temporarily into %r1. Set up the
3394 new stack pointer, then store away the saved old frame pointer
3395 into the stack at sp and at the same time update the stack
3396 pointer by actual_fsize bytes. Two versions, first
3397 handles small (<8k) frames. The second handles large (>=8k)
3399 insn = emit_move_insn (tmpreg, frame_pointer_rtx);
3402 /* We need to record the frame pointer save here since the
3403 new frame pointer is set in the following insn. */
3404 RTX_FRAME_RELATED_P (insn) = 1;
3406 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3407 gen_rtx_SET (VOIDmode,
3408 gen_rtx_MEM (word_mode, stack_pointer_rtx),
3413 insn = emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
3415 RTX_FRAME_RELATED_P (insn) = 1;
3417 if (VAL_14_BITS_P (actual_fsize))
3418 store_reg_modify (STACK_POINTER_REGNUM, 1, actual_fsize);
3421 /* It is incorrect to store the saved frame pointer at *sp,
3422 then increment sp (writes beyond the current stack boundary).
3424 So instead use stwm to store at *sp and post-increment the
3425 stack pointer as an atomic operation. Then increment sp to
3426 finish allocating the new frame. */
3427 int adjust1 = 8192 - 64;
3428 int adjust2 = actual_fsize - adjust1;
3430 store_reg_modify (STACK_POINTER_REGNUM, 1, adjust1);
3431 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3435 /* We set SAVE_SP in frames that need a frame pointer. Thus,
3436 we need to store the previous stack pointer (frame pointer)
3437 into the frame marker on targets that use the HP unwind
3438 library. This allows the HP unwind library to be used to
3439 unwind GCC frames. However, we are not fully compatible
3440 with the HP library because our frame layout differs from
3441 that specified in the HP runtime specification.
3443 We don't want a frame note on this instruction as the frame
3444 marker moves during dynamic stack allocation.
3446 This instruction also serves as a blockage to prevent
3447 register spills from being scheduled before the stack
3448 pointer is raised. This is necessary as we store
3449 registers using the frame pointer as a base register,
3450 and the frame pointer is set before sp is raised. */
3451 if (TARGET_HPUX_UNWIND_LIBRARY)
3453 rtx addr = gen_rtx_PLUS (word_mode, stack_pointer_rtx,
3454 GEN_INT (TARGET_64BIT ? -8 : -4));
3456 emit_move_insn (gen_rtx_MEM (word_mode, addr),
3460 emit_insn (gen_blockage ());
3462 /* no frame pointer needed. */
3465 /* In some cases we can perform the first callee register save
3466 and allocating the stack frame at the same time. If so, just
3467 make a note of it and defer allocating the frame until saving
3468 the callee registers. */
3469 if (VAL_14_BITS_P (actual_fsize) && local_fsize == 0)
3470 merge_sp_adjust_with_store = 1;
3471 /* Can not optimize. Adjust the stack frame by actual_fsize
3474 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3479 /* Normal register save.
3481 Do not save the frame pointer in the frame_pointer_needed case. It
3482 was done earlier. */
3483 if (frame_pointer_needed)
3485 offset = local_fsize;
3487 /* Saving the EH return data registers in the frame is the simplest
3488 way to get the frame unwind information emitted. We put them
3489 just before the general registers. */
3490 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3492 unsigned int i, regno;
3496 regno = EH_RETURN_DATA_REGNO (i);
3497 if (regno == INVALID_REGNUM)
3500 store_reg (regno, offset, FRAME_POINTER_REGNUM);
3501 offset += UNITS_PER_WORD;
3505 for (i = 18; i >= 4; i--)
3506 if (regs_ever_live[i] && ! call_used_regs[i])
3508 store_reg (i, offset, FRAME_POINTER_REGNUM);
3509 offset += UNITS_PER_WORD;
3512 /* Account for %r3 which is saved in a special place. */
3515 /* No frame pointer needed. */
3518 offset = local_fsize - actual_fsize;
3520 /* Saving the EH return data registers in the frame is the simplest
3521 way to get the frame unwind information emitted. */
3522 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3524 unsigned int i, regno;
3528 regno = EH_RETURN_DATA_REGNO (i);
3529 if (regno == INVALID_REGNUM)
3532 /* If merge_sp_adjust_with_store is nonzero, then we can
3533 optimize the first save. */
3534 if (merge_sp_adjust_with_store)
3536 store_reg_modify (STACK_POINTER_REGNUM, regno, -offset);
3537 merge_sp_adjust_with_store = 0;
3540 store_reg (regno, offset, STACK_POINTER_REGNUM);
3541 offset += UNITS_PER_WORD;
3545 for (i = 18; i >= 3; i--)
3546 if (regs_ever_live[i] && ! call_used_regs[i])
3548 /* If merge_sp_adjust_with_store is nonzero, then we can
3549 optimize the first GR save. */
3550 if (merge_sp_adjust_with_store)
3552 store_reg_modify (STACK_POINTER_REGNUM, i, -offset);
3553 merge_sp_adjust_with_store = 0;
3556 store_reg (i, offset, STACK_POINTER_REGNUM);
3557 offset += UNITS_PER_WORD;
3561 /* If we wanted to merge the SP adjustment with a GR save, but we never
3562 did any GR saves, then just emit the adjustment here. */
3563 if (merge_sp_adjust_with_store)
3564 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3568 /* The hppa calling conventions say that %r19, the pic offset
3569 register, is saved at sp - 32 (in this function's frame)
3570 when generating PIC code. FIXME: What is the correct thing
3571 to do for functions which make no calls and allocate no
3572 frame? Do we need to allocate a frame, or can we just omit
3573 the save? For now we'll just omit the save. */
3574 if (flag_pic && actual_fsize != 0 && !TARGET_64BIT)
3575 store_reg (PIC_OFFSET_TABLE_REGNUM, -32, STACK_POINTER_REGNUM);
3577 /* Align pointer properly (doubleword boundary). */
3578 offset = (offset + 7) & ~7;
3580 /* Floating point register store. */
3585 /* First get the frame or stack pointer to the start of the FP register
3587 if (frame_pointer_needed)
3589 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3590 base = frame_pointer_rtx;
3594 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3595 base = stack_pointer_rtx;
3598 /* Now actually save the FP registers. */
3599 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3601 if (regs_ever_live[i]
3602 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3604 rtx addr, insn, reg;
3605 addr = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3606 reg = gen_rtx_REG (DFmode, i);
3607 insn = emit_move_insn (addr, reg);
3610 RTX_FRAME_RELATED_P (insn) = 1;
3613 rtx mem = gen_rtx_MEM (DFmode,
3614 plus_constant (base, offset));
3616 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3617 gen_rtx_SET (VOIDmode, mem, reg),
3622 rtx meml = gen_rtx_MEM (SFmode,
3623 plus_constant (base, offset));
3624 rtx memr = gen_rtx_MEM (SFmode,
3625 plus_constant (base, offset + 4));
3626 rtx regl = gen_rtx_REG (SFmode, i);
3627 rtx regr = gen_rtx_REG (SFmode, i + 1);
3628 rtx setl = gen_rtx_SET (VOIDmode, meml, regl);
3629 rtx setr = gen_rtx_SET (VOIDmode, memr, regr);
3632 RTX_FRAME_RELATED_P (setl) = 1;
3633 RTX_FRAME_RELATED_P (setr) = 1;
3634 vec = gen_rtvec (2, setl, setr);
3636 = gen_rtx_EXPR_LIST (REG_FRAME_RELATED_EXPR,
3637 gen_rtx_SEQUENCE (VOIDmode, vec),
3641 offset += GET_MODE_SIZE (DFmode);
3648 /* Emit RTL to load REG from the memory location specified by BASE+DISP.
3649 Handle case where DISP > 8k by using the add_high_const patterns. */
3652 load_reg (reg, disp, base)
3653 int reg, disp, base;
3655 rtx src, dest, basereg;
3657 dest = gen_rtx_REG (word_mode, reg);
3658 basereg = gen_rtx_REG (Pmode, base);
3659 if (VAL_14_BITS_P (disp))
3661 src = gen_rtx_MEM (word_mode, plus_constant (basereg, disp));
3662 emit_move_insn (dest, src);
3666 rtx delta = GEN_INT (disp);
3667 rtx high = gen_rtx_PLUS (Pmode, basereg, gen_rtx_HIGH (Pmode, delta));
3668 rtx tmpreg = gen_rtx_REG (Pmode, 1);
3669 emit_move_insn (tmpreg, high);
3670 src = gen_rtx_MEM (word_mode, gen_rtx_LO_SUM (Pmode, tmpreg, delta));
3671 emit_move_insn (dest, src);
3675 /* This function generates the assembly code for function exit.
3676 Args are as for output_function_prologue ().
3678 The function epilogue should not depend on the current stack
3679 pointer! It should use the frame pointer only. This is mandatory
3680 because of alloca; we also take advantage of it to omit stack
3681 adjustments before returning. */
3684 pa_output_function_epilogue (file, size)
3686 HOST_WIDE_INT size ATTRIBUTE_UNUSED;
3688 int last_address = 0;
3689 rtx insn = get_last_insn ();
3691 /* hppa_expand_epilogue does the dirty work now. We just need
3692 to output the assembler directives which denote the end
3695 To make debuggers happy, emit a nop if the epilogue was completely
3696 eliminated due to a volatile call as the last insn in the
3697 current function. That way the return address (in %r2) will
3698 always point to a valid instruction in the current function. */
3700 /* Get the last real insn. */
3701 if (GET_CODE (insn) == NOTE)
3702 insn = prev_real_insn (insn);
3704 /* If it is a sequence, then look inside. */
3705 if (insn && GET_CODE (insn) == INSN && GET_CODE (PATTERN (insn)) == SEQUENCE)
3706 insn = XVECEXP (PATTERN (insn), 0, 0);
3708 /* If insn is a CALL_INSN, then it must be a call to a volatile
3709 function (otherwise there would be epilogue insns). */
3710 if (insn && GET_CODE (insn) == CALL_INSN)
3712 fputs ("\tnop\n", file);
3716 fputs ("\t.EXIT\n\t.PROCEND\n", file);
3718 /* Finally, update the total number of code bytes output so far. */
3719 if ((TARGET_PORTABLE_RUNTIME || !TARGET_GAS || !TARGET_SOM)
3720 && !flag_function_sections)
3722 if (INSN_ADDRESSES_SET_P ())
3724 unsigned long old_total = total_code_bytes;
3726 insn = get_last_nonnote_insn ();
3727 last_address += INSN_ADDRESSES (INSN_UID (insn));
3729 last_address += insn_default_length (insn);
3731 total_code_bytes += last_address;
3732 total_code_bytes += FUNCTION_BOUNDARY / BITS_PER_UNIT;
3734 /* Be prepared to handle overflows. */
3735 if (old_total > total_code_bytes)
3736 total_code_bytes = -1;
3739 total_code_bytes = -1;
3744 hppa_expand_epilogue ()
3748 int merge_sp_adjust_with_load = 0;
3751 /* We will use this often. */
3752 tmpreg = gen_rtx_REG (word_mode, 1);
3754 /* Try to restore RP early to avoid load/use interlocks when
3755 RP gets used in the return (bv) instruction. This appears to still
3756 be necessary even when we schedule the prologue and epilogue. */
3757 if (regs_ever_live [2] || current_function_calls_eh_return)
3759 ret_off = TARGET_64BIT ? -16 : -20;
3760 if (frame_pointer_needed)
3762 load_reg (2, ret_off, FRAME_POINTER_REGNUM);
3767 /* No frame pointer, and stack is smaller than 8k. */
3768 if (VAL_14_BITS_P (ret_off - actual_fsize))
3770 load_reg (2, ret_off - actual_fsize, STACK_POINTER_REGNUM);
3776 /* General register restores. */
3777 if (frame_pointer_needed)
3779 offset = local_fsize;
3781 /* If the current function calls __builtin_eh_return, then we need
3782 to restore the saved EH data registers. */
3783 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3785 unsigned int i, regno;
3789 regno = EH_RETURN_DATA_REGNO (i);
3790 if (regno == INVALID_REGNUM)
3793 load_reg (regno, offset, FRAME_POINTER_REGNUM);
3794 offset += UNITS_PER_WORD;
3798 for (i = 18; i >= 4; i--)
3799 if (regs_ever_live[i] && ! call_used_regs[i])
3801 load_reg (i, offset, FRAME_POINTER_REGNUM);
3802 offset += UNITS_PER_WORD;
3807 offset = local_fsize - actual_fsize;
3809 /* If the current function calls __builtin_eh_return, then we need
3810 to restore the saved EH data registers. */
3811 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3813 unsigned int i, regno;
3817 regno = EH_RETURN_DATA_REGNO (i);
3818 if (regno == INVALID_REGNUM)
3821 /* Only for the first load.
3822 merge_sp_adjust_with_load holds the register load
3823 with which we will merge the sp adjustment. */
3824 if (merge_sp_adjust_with_load == 0
3826 && VAL_14_BITS_P (-actual_fsize))
3827 merge_sp_adjust_with_load = regno;
3829 load_reg (regno, offset, STACK_POINTER_REGNUM);
3830 offset += UNITS_PER_WORD;
3834 for (i = 18; i >= 3; i--)
3836 if (regs_ever_live[i] && ! call_used_regs[i])
3838 /* Only for the first load.
3839 merge_sp_adjust_with_load holds the register load
3840 with which we will merge the sp adjustment. */
3841 if (merge_sp_adjust_with_load == 0
3843 && VAL_14_BITS_P (-actual_fsize))
3844 merge_sp_adjust_with_load = i;
3846 load_reg (i, offset, STACK_POINTER_REGNUM);
3847 offset += UNITS_PER_WORD;
3852 /* Align pointer properly (doubleword boundary). */
3853 offset = (offset + 7) & ~7;
3855 /* FP register restores. */
3858 /* Adjust the register to index off of. */
3859 if (frame_pointer_needed)
3860 set_reg_plus_d (1, FRAME_POINTER_REGNUM, offset, 0);
3862 set_reg_plus_d (1, STACK_POINTER_REGNUM, offset, 0);
3864 /* Actually do the restores now. */
3865 for (i = FP_SAVED_REG_LAST; i >= FP_SAVED_REG_FIRST; i -= FP_REG_STEP)
3866 if (regs_ever_live[i]
3867 || (! TARGET_64BIT && regs_ever_live[i + 1]))
3869 rtx src = gen_rtx_MEM (DFmode, gen_rtx_POST_INC (DFmode, tmpreg));
3870 rtx dest = gen_rtx_REG (DFmode, i);
3871 emit_move_insn (dest, src);
3875 /* Emit a blockage insn here to keep these insns from being moved to
3876 an earlier spot in the epilogue, or into the main instruction stream.
3878 This is necessary as we must not cut the stack back before all the
3879 restores are finished. */
3880 emit_insn (gen_blockage ());
3882 /* Reset stack pointer (and possibly frame pointer). The stack
3883 pointer is initially set to fp + 64 to avoid a race condition. */
3884 if (frame_pointer_needed)
3886 rtx delta = GEN_INT (-64);
3888 set_reg_plus_d (STACK_POINTER_REGNUM, FRAME_POINTER_REGNUM, 64, 0);
3889 emit_insn (gen_pre_load (frame_pointer_rtx, stack_pointer_rtx, delta));
3891 /* If we were deferring a callee register restore, do it now. */
3892 else if (merge_sp_adjust_with_load)
3894 rtx delta = GEN_INT (-actual_fsize);
3895 rtx dest = gen_rtx_REG (word_mode, merge_sp_adjust_with_load);
3897 emit_insn (gen_pre_load (dest, stack_pointer_rtx, delta));
3899 else if (actual_fsize != 0)
3900 set_reg_plus_d (STACK_POINTER_REGNUM, STACK_POINTER_REGNUM,
3903 /* If we haven't restored %r2 yet (no frame pointer, and a stack
3904 frame greater than 8k), do so now. */
3906 load_reg (2, ret_off, STACK_POINTER_REGNUM);
3908 if (DO_FRAME_NOTES && current_function_calls_eh_return)
3910 rtx sa = EH_RETURN_STACKADJ_RTX;
3912 emit_insn (gen_blockage ());
3913 emit_insn (TARGET_64BIT
3914 ? gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx, sa)
3915 : gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, sa));
3920 hppa_pic_save_rtx ()
3922 return get_hard_reg_initial_val (word_mode, PIC_OFFSET_TABLE_REGNUM);
3926 hppa_profile_hook (label_no)
3929 rtx begin_label_rtx, call_insn;
3930 char begin_label_name[16];
3932 ASM_GENERATE_INTERNAL_LABEL (begin_label_name, FUNC_BEGIN_PROLOG_LABEL,
3934 begin_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (begin_label_name));
3937 emit_move_insn (arg_pointer_rtx,
3938 gen_rtx_PLUS (word_mode, virtual_outgoing_args_rtx,
3941 emit_move_insn (gen_rtx_REG (word_mode, 26), gen_rtx_REG (word_mode, 2));
3943 #ifndef NO_PROFILE_COUNTERS
3945 rtx count_label_rtx, addr, r24;
3946 char count_label_name[16];
3948 ASM_GENERATE_INTERNAL_LABEL (count_label_name, "LP", label_no);
3949 count_label_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (count_label_name));
3951 addr = force_reg (Pmode, count_label_rtx);
3952 r24 = gen_rtx_REG (Pmode, 24);
3953 emit_move_insn (r24, addr);
3955 /* %r25 is set from within the output pattern. */
3957 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3958 GEN_INT (TARGET_64BIT ? 24 : 12),
3961 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), r24);
3964 /* %r25 is set from within the output pattern. */
3966 emit_call_insn (gen_call_profiler (gen_rtx_SYMBOL_REF (Pmode, "_mcount"),
3967 GEN_INT (TARGET_64BIT ? 16 : 8),
3971 /* Indicate the _mcount call cannot throw, nor will it execute a
3973 REG_NOTES (call_insn)
3974 = gen_rtx_EXPR_LIST (REG_EH_REGION, constm1_rtx, REG_NOTES (call_insn));
3978 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), pic_offset_table_rtx);
3980 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), arg_pointer_rtx);
3982 emit_move_insn (pic_offset_table_rtx, hppa_pic_save_rtx ());
3986 /* Fetch the return address for the frame COUNT steps up from
3987 the current frame, after the prologue. FRAMEADDR is the
3988 frame pointer of the COUNT frame.
3990 We want to ignore any export stub remnants here. To handle this,
3991 we examine the code at the return address, and if it is an export
3992 stub, we return a memory rtx for the stub return address stored
3995 The value returned is used in two different ways:
3997 1. To find a function's caller.
3999 2. To change the return address for a function.
4001 This function handles most instances of case 1; however, it will
4002 fail if there are two levels of stubs to execute on the return
4003 path. The only way I believe that can happen is if the return value
4004 needs a parameter relocation, which never happens for C code.
4006 This function handles most instances of case 2; however, it will
4007 fail if we did not originally have stub code on the return path
4008 but will need stub code on the new return path. This can happen if
4009 the caller & callee are both in the main program, but the new
4010 return location is in a shared library. */
4013 return_addr_rtx (count, frameaddr)
4025 rp = get_hard_reg_initial_val (Pmode, 2);
4027 if (TARGET_64BIT || TARGET_NO_SPACE_REGS)
4030 saved_rp = gen_reg_rtx (Pmode);
4031 emit_move_insn (saved_rp, rp);
4033 /* Get pointer to the instruction stream. We have to mask out the
4034 privilege level from the two low order bits of the return address
4035 pointer here so that ins will point to the start of the first
4036 instruction that would have been executed if we returned. */
4037 ins = copy_to_reg (gen_rtx_AND (Pmode, rp, MASK_RETURN_ADDR));
4038 label = gen_label_rtx ();
4040 /* Check the instruction stream at the normal return address for the
4043 0x4bc23fd1 | stub+8: ldw -18(sr0,sp),rp
4044 0x004010a1 | stub+12: ldsid (sr0,rp),r1
4045 0x00011820 | stub+16: mtsp r1,sr0
4046 0xe0400002 | stub+20: be,n 0(sr0,rp)
4048 If it is an export stub, than our return address is really in
4051 emit_cmp_insn (gen_rtx_MEM (SImode, ins), GEN_INT (0x4bc23fd1), NE,
4052 NULL_RTX, SImode, 1);
4053 emit_jump_insn (gen_bne (label));
4055 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 4)),
4056 GEN_INT (0x004010a1), NE, NULL_RTX, SImode, 1);
4057 emit_jump_insn (gen_bne (label));
4059 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 8)),
4060 GEN_INT (0x00011820), NE, NULL_RTX, SImode, 1);
4061 emit_jump_insn (gen_bne (label));
4063 emit_cmp_insn (gen_rtx_MEM (SImode, plus_constant (ins, 12)),
4064 GEN_INT (0xe0400002), NE, NULL_RTX, SImode, 1);
4066 /* If there is no export stub then just use the value saved from
4067 the return pointer register. */
4069 emit_jump_insn (gen_bne (label));
4071 /* Here we know that our return address points to an export
4072 stub. We don't want to return the address of the export stub,
4073 but rather the return address of the export stub. That return
4074 address is stored at -24[frameaddr]. */
4076 emit_move_insn (saved_rp,
4078 memory_address (Pmode,
4079 plus_constant (frameaddr,
4086 /* This is only valid once reload has completed because it depends on
4087 knowing exactly how much (if any) frame there is and...
4089 It's only valid if there is no frame marker to de-allocate and...
4091 It's only valid if %r2 hasn't been saved into the caller's frame
4092 (we're not profiling and %r2 isn't live anywhere). */
4094 hppa_can_use_return_insn_p ()
4096 return (reload_completed
4097 && (compute_frame_size (get_frame_size (), 0) ? 0 : 1)
4098 && ! regs_ever_live[2]
4099 && ! frame_pointer_needed);
4103 emit_bcond_fp (code, operand0)
4107 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
4108 gen_rtx_IF_THEN_ELSE (VOIDmode,
4109 gen_rtx_fmt_ee (code,
4111 gen_rtx_REG (CCFPmode, 0),
4113 gen_rtx_LABEL_REF (VOIDmode, operand0),
4119 gen_cmp_fp (code, operand0, operand1)
4121 rtx operand0, operand1;
4123 return gen_rtx_SET (VOIDmode, gen_rtx_REG (CCFPmode, 0),
4124 gen_rtx_fmt_ee (code, CCFPmode, operand0, operand1));
4127 /* Adjust the cost of a scheduling dependency. Return the new cost of
4128 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */
4131 pa_adjust_cost (insn, link, dep_insn, cost)
4137 enum attr_type attr_type;
4139 /* Don't adjust costs for a pa8000 chip, also do not adjust any
4140 true dependencies as they are described with bypasses now. */
4141 if (pa_cpu >= PROCESSOR_8000 || REG_NOTE_KIND (link) == 0)
4144 if (! recog_memoized (insn))
4147 attr_type = get_attr_type (insn);
4149 if (REG_NOTE_KIND (link) == REG_DEP_ANTI)
4151 /* Anti dependency; DEP_INSN reads a register that INSN writes some
4154 if (attr_type == TYPE_FPLOAD)
4156 rtx pat = PATTERN (insn);
4157 rtx dep_pat = PATTERN (dep_insn);
4158 if (GET_CODE (pat) == PARALLEL)
4160 /* This happens for the fldXs,mb patterns. */
4161 pat = XVECEXP (pat, 0, 0);
4163 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4164 /* If this happens, we have to extend this to schedule
4165 optimally. Return 0 for now. */
4168 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4170 if (! recog_memoized (dep_insn))
4172 switch (get_attr_type (dep_insn))
4179 case TYPE_FPSQRTSGL:
4180 case TYPE_FPSQRTDBL:
4181 /* A fpload can't be issued until one cycle before a
4182 preceding arithmetic operation has finished if
4183 the target of the fpload is any of the sources
4184 (or destination) of the arithmetic operation. */
4185 return insn_default_latency (dep_insn) - 1;
4192 else if (attr_type == TYPE_FPALU)
4194 rtx pat = PATTERN (insn);
4195 rtx dep_pat = PATTERN (dep_insn);
4196 if (GET_CODE (pat) == PARALLEL)
4198 /* This happens for the fldXs,mb patterns. */
4199 pat = XVECEXP (pat, 0, 0);
4201 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4202 /* If this happens, we have to extend this to schedule
4203 optimally. Return 0 for now. */
4206 if (reg_mentioned_p (SET_DEST (pat), SET_SRC (dep_pat)))
4208 if (! recog_memoized (dep_insn))
4210 switch (get_attr_type (dep_insn))
4214 case TYPE_FPSQRTSGL:
4215 case TYPE_FPSQRTDBL:
4216 /* An ALU flop can't be issued until two cycles before a
4217 preceding divide or sqrt operation has finished if
4218 the target of the ALU flop is any of the sources
4219 (or destination) of the divide or sqrt operation. */
4220 return insn_default_latency (dep_insn) - 2;
4228 /* For other anti dependencies, the cost is 0. */
4231 else if (REG_NOTE_KIND (link) == REG_DEP_OUTPUT)
4233 /* Output dependency; DEP_INSN writes a register that INSN writes some
4235 if (attr_type == TYPE_FPLOAD)
4237 rtx pat = PATTERN (insn);
4238 rtx dep_pat = PATTERN (dep_insn);
4239 if (GET_CODE (pat) == PARALLEL)
4241 /* This happens for the fldXs,mb patterns. */
4242 pat = XVECEXP (pat, 0, 0);
4244 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4245 /* If this happens, we have to extend this to schedule
4246 optimally. Return 0 for now. */
4249 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4251 if (! recog_memoized (dep_insn))
4253 switch (get_attr_type (dep_insn))
4260 case TYPE_FPSQRTSGL:
4261 case TYPE_FPSQRTDBL:
4262 /* A fpload can't be issued until one cycle before a
4263 preceding arithmetic operation has finished if
4264 the target of the fpload is the destination of the
4265 arithmetic operation.
4267 Exception: For PA7100LC, PA7200 and PA7300, the cost
4268 is 3 cycles, unless they bundle together. We also
4269 pay the penalty if the second insn is a fpload. */
4270 return insn_default_latency (dep_insn) - 1;
4277 else if (attr_type == TYPE_FPALU)
4279 rtx pat = PATTERN (insn);
4280 rtx dep_pat = PATTERN (dep_insn);
4281 if (GET_CODE (pat) == PARALLEL)
4283 /* This happens for the fldXs,mb patterns. */
4284 pat = XVECEXP (pat, 0, 0);
4286 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET)
4287 /* If this happens, we have to extend this to schedule
4288 optimally. Return 0 for now. */
4291 if (reg_mentioned_p (SET_DEST (pat), SET_DEST (dep_pat)))
4293 if (! recog_memoized (dep_insn))
4295 switch (get_attr_type (dep_insn))
4299 case TYPE_FPSQRTSGL:
4300 case TYPE_FPSQRTDBL:
4301 /* An ALU flop can't be issued until two cycles before a
4302 preceding divide or sqrt operation has finished if
4303 the target of the ALU flop is also the target of
4304 the divide or sqrt operation. */
4305 return insn_default_latency (dep_insn) - 2;
4313 /* For other output dependencies, the cost is 0. */
4320 /* Adjust scheduling priorities. We use this to try and keep addil
4321 and the next use of %r1 close together. */
4323 pa_adjust_priority (insn, priority)
4327 rtx set = single_set (insn);
4331 src = SET_SRC (set);
4332 dest = SET_DEST (set);
4333 if (GET_CODE (src) == LO_SUM
4334 && symbolic_operand (XEXP (src, 1), VOIDmode)
4335 && ! read_only_operand (XEXP (src, 1), VOIDmode))
4338 else if (GET_CODE (src) == MEM
4339 && GET_CODE (XEXP (src, 0)) == LO_SUM
4340 && symbolic_operand (XEXP (XEXP (src, 0), 1), VOIDmode)
4341 && ! read_only_operand (XEXP (XEXP (src, 0), 1), VOIDmode))
4344 else if (GET_CODE (dest) == MEM
4345 && GET_CODE (XEXP (dest, 0)) == LO_SUM
4346 && symbolic_operand (XEXP (XEXP (dest, 0), 1), VOIDmode)
4347 && ! read_only_operand (XEXP (XEXP (dest, 0), 1), VOIDmode))
4353 /* The 700 can only issue a single insn at a time.
4354 The 7XXX processors can issue two insns at a time.
4355 The 8000 can issue 4 insns at a time. */
4361 case PROCESSOR_700: return 1;
4362 case PROCESSOR_7100: return 2;
4363 case PROCESSOR_7100LC: return 2;
4364 case PROCESSOR_7200: return 2;
4365 case PROCESSOR_7300: return 2;
4366 case PROCESSOR_8000: return 4;
4375 /* Return any length adjustment needed by INSN which already has its length
4376 computed as LENGTH. Return zero if no adjustment is necessary.
4378 For the PA: function calls, millicode calls, and backwards short
4379 conditional branches with unfilled delay slots need an adjustment by +1
4380 (to account for the NOP which will be inserted into the instruction stream).
4382 Also compute the length of an inline block move here as it is too
4383 complicated to express as a length attribute in pa.md. */
4385 pa_adjust_insn_length (insn, length)
4389 rtx pat = PATTERN (insn);
4391 /* Call insns which are *not* indirect and have unfilled delay slots. */
4392 if (GET_CODE (insn) == CALL_INSN)
4395 if (GET_CODE (XVECEXP (pat, 0, 0)) == CALL
4396 && GET_CODE (XEXP (XEXP (XVECEXP (pat, 0, 0), 0), 0)) == SYMBOL_REF)
4398 else if (GET_CODE (XVECEXP (pat, 0, 0)) == SET
4399 && GET_CODE (XEXP (XEXP (XEXP (XVECEXP (pat, 0, 0), 1), 0), 0))
4405 /* Jumps inside switch tables which have unfilled delay slots
4406 also need adjustment. */
4407 else if (GET_CODE (insn) == JUMP_INSN
4408 && simplejump_p (insn)
4409 && GET_MODE (insn) == SImode)
4411 /* Millicode insn with an unfilled delay slot. */
4412 else if (GET_CODE (insn) == INSN
4413 && GET_CODE (pat) != SEQUENCE
4414 && GET_CODE (pat) != USE
4415 && GET_CODE (pat) != CLOBBER
4416 && get_attr_type (insn) == TYPE_MILLI)
4418 /* Block move pattern. */
4419 else if (GET_CODE (insn) == INSN
4420 && GET_CODE (pat) == PARALLEL
4421 && GET_CODE (XVECEXP (pat, 0, 0)) == SET
4422 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
4423 && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
4424 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
4425 && GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
4426 return compute_movstrsi_length (insn) - 4;
4427 /* Conditional branch with an unfilled delay slot. */
4428 else if (GET_CODE (insn) == JUMP_INSN && ! simplejump_p (insn))
4430 /* Adjust a short backwards conditional with an unfilled delay slot. */
4431 if (GET_CODE (pat) == SET
4433 && ! forward_branch_p (insn))
4435 else if (GET_CODE (pat) == PARALLEL
4436 && get_attr_type (insn) == TYPE_PARALLEL_BRANCH
4439 /* Adjust dbra insn with short backwards conditional branch with
4440 unfilled delay slot -- only for case where counter is in a
4441 general register register. */
4442 else if (GET_CODE (pat) == PARALLEL
4443 && GET_CODE (XVECEXP (pat, 0, 1)) == SET
4444 && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
4445 && ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
4447 && ! forward_branch_p (insn))
4455 /* Print operand X (an rtx) in assembler syntax to file FILE.
4456 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
4457 For `%' followed by punctuation, CODE is the punctuation and X is null. */
4460 print_operand (file, x, code)
4468 /* Output a 'nop' if there's nothing for the delay slot. */
4469 if (dbr_sequence_length () == 0)
4470 fputs ("\n\tnop", file);
4473 /* Output a nullification completer if there's nothing for the */
4474 /* delay slot or nullification is requested. */
4475 if (dbr_sequence_length () == 0 ||
4477 INSN_ANNULLED_BRANCH_P (XVECEXP (final_sequence, 0, 0))))
4481 /* Print out the second register name of a register pair.
4482 I.e., R (6) => 7. */
4483 fputs (reg_names[REGNO (x) + 1], file);
4486 /* A register or zero. */
4488 || (x == CONST0_RTX (DFmode))
4489 || (x == CONST0_RTX (SFmode)))
4491 fputs ("%r0", file);
4497 /* A register or zero (floating point). */
4499 || (x == CONST0_RTX (DFmode))
4500 || (x == CONST0_RTX (SFmode)))
4502 fputs ("%fr0", file);
4511 xoperands[0] = XEXP (XEXP (x, 0), 0);
4512 xoperands[1] = XVECEXP (XEXP (XEXP (x, 0), 1), 0, 0);
4513 output_global_address (file, xoperands[1], 0);
4514 fprintf (file, "(%s)", reg_names [REGNO (xoperands[0])]);
4518 case 'C': /* Plain (C)ondition */
4520 switch (GET_CODE (x))
4523 fputs ("=", file); break;
4525 fputs ("<>", file); break;
4527 fputs (">", file); break;
4529 fputs (">=", file); break;
4531 fputs (">>=", file); break;
4533 fputs (">>", file); break;
4535 fputs ("<", file); break;
4537 fputs ("<=", file); break;
4539 fputs ("<<=", file); break;
4541 fputs ("<<", file); break;
4546 case 'N': /* Condition, (N)egated */
4547 switch (GET_CODE (x))
4550 fputs ("<>", file); break;
4552 fputs ("=", file); break;
4554 fputs ("<=", file); break;
4556 fputs ("<", file); break;
4558 fputs ("<<", file); break;
4560 fputs ("<<=", file); break;
4562 fputs (">=", file); break;
4564 fputs (">", file); break;
4566 fputs (">>", file); break;
4568 fputs (">>=", file); break;
4573 /* For floating point comparisons. Note that the output
4574 predicates are the complement of the desired mode. */
4576 switch (GET_CODE (x))
4579 fputs ("!=", file); break;
4581 fputs ("=", file); break;
4583 fputs ("!>", file); break;
4585 fputs ("!>=", file); break;
4587 fputs ("!<", file); break;
4589 fputs ("!<=", file); break;
4591 fputs ("!<>", file); break;
4593 fputs (">", file); break;
4595 fputs (">=", file); break;
4597 fputs ("<", file); break;
4599 fputs ("<=", file); break;
4601 fputs ("<>", file); break;
4603 fputs ("<=>", file); break;
4605 fputs ("!<=>", file); break;
4610 case 'S': /* Condition, operands are (S)wapped. */
4611 switch (GET_CODE (x))
4614 fputs ("=", file); break;
4616 fputs ("<>", file); break;
4618 fputs ("<", file); break;
4620 fputs ("<=", file); break;
4622 fputs ("<<=", file); break;
4624 fputs ("<<", file); break;
4626 fputs (">", file); break;
4628 fputs (">=", file); break;
4630 fputs (">>=", file); break;
4632 fputs (">>", file); break;
4637 case 'B': /* Condition, (B)oth swapped and negate. */
4638 switch (GET_CODE (x))
4641 fputs ("<>", file); break;
4643 fputs ("=", file); break;
4645 fputs (">=", file); break;
4647 fputs (">", file); break;
4649 fputs (">>", file); break;
4651 fputs (">>=", file); break;
4653 fputs ("<=", file); break;
4655 fputs ("<", file); break;
4657 fputs ("<<", file); break;
4659 fputs ("<<=", file); break;
4665 if (GET_CODE (x) == CONST_INT)
4667 fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
4672 if (GET_CODE (x) == CONST_INT)
4674 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
4679 if (GET_CODE (x) == CONST_INT)
4681 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
4686 if (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0)
4688 fprintf (file, "%d", exact_log2 (INTVAL (x)));
4693 if (GET_CODE (x) == CONST_INT)
4695 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
4700 if (GET_CODE (x) == CONST_INT)
4702 fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
4707 if (GET_CODE (x) == CONST_INT)
4712 switch (GET_CODE (XEXP (x, 0)))
4716 if (ASSEMBLER_DIALECT == 0)
4717 fputs ("s,mb", file);
4719 fputs (",mb", file);
4723 if (ASSEMBLER_DIALECT == 0)
4724 fputs ("s,ma", file);
4726 fputs (",ma", file);
4729 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
4730 || GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4732 if (ASSEMBLER_DIALECT == 0)
4733 fputs ("x,s", file);
4737 else if (code == 'F' && ASSEMBLER_DIALECT == 0)
4741 if (code == 'F' && ASSEMBLER_DIALECT == 0)
4747 output_global_address (file, x, 0);
4750 output_global_address (file, x, 1);
4752 case 0: /* Don't do anything special */
4757 compute_zdepwi_operands (INTVAL (x), op);
4758 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4764 compute_zdepdi_operands (INTVAL (x), op);
4765 fprintf (file, "%d,%d,%d", op[0], op[1], op[2]);
4769 /* We can get here from a .vtable_inherit due to our
4770 CONSTANT_ADDRESS_P rejecting perfectly good constant
4776 if (GET_CODE (x) == REG)
4778 fputs (reg_names [REGNO (x)], file);
4779 if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
4785 && GET_MODE_SIZE (GET_MODE (x)) <= 4
4786 && (REGNO (x) & 1) == 0)
4789 else if (GET_CODE (x) == MEM)
4791 int size = GET_MODE_SIZE (GET_MODE (x));
4792 rtx base = NULL_RTX;
4793 switch (GET_CODE (XEXP (x, 0)))
4797 base = XEXP (XEXP (x, 0), 0);
4798 fprintf (file, "-%d(%s)", size, reg_names [REGNO (base)]);
4802 base = XEXP (XEXP (x, 0), 0);
4803 fprintf (file, "%d(%s)", size, reg_names [REGNO (base)]);
4806 if (GET_CODE (XEXP (x, 0)) == PLUS
4807 && GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT)
4808 fprintf (file, "%s(%s)",
4809 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 0), 0))],
4810 reg_names [REGNO (XEXP (XEXP (x, 0), 1))]);
4811 else if (GET_CODE (XEXP (x, 0)) == PLUS
4812 && GET_CODE (XEXP (XEXP (x, 0), 1)) == MULT)
4813 fprintf (file, "%s(%s)",
4814 reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
4815 reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
4817 output_address (XEXP (x, 0));
4822 output_addr_const (file, x);
4825 /* output a SYMBOL_REF or a CONST expression involving a SYMBOL_REF. */
4828 output_global_address (file, x, round_constant)
4834 /* Imagine (high (const (plus ...))). */
4835 if (GET_CODE (x) == HIGH)
4838 if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
4839 assemble_name (file, XSTR (x, 0));
4840 else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
4842 assemble_name (file, XSTR (x, 0));
4843 fputs ("-$global$", file);
4845 else if (GET_CODE (x) == CONST)
4847 const char *sep = "";
4848 int offset = 0; /* assembler wants -$global$ at end */
4849 rtx base = NULL_RTX;
4851 if (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
4853 base = XEXP (XEXP (x, 0), 0);
4854 output_addr_const (file, base);
4856 else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == CONST_INT)
4857 offset = INTVAL (XEXP (XEXP (x, 0), 0));
4860 if (GET_CODE (XEXP (XEXP (x, 0), 1)) == SYMBOL_REF)
4862 base = XEXP (XEXP (x, 0), 1);
4863 output_addr_const (file, base);
4865 else if (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
4866 offset = INTVAL (XEXP (XEXP (x, 0), 1));
4869 /* How bogus. The compiler is apparently responsible for
4870 rounding the constant if it uses an LR field selector.
4872 The linker and/or assembler seem a better place since
4873 they have to do this kind of thing already.
4875 If we fail to do this, HP's optimizing linker may eliminate
4876 an addil, but not update the ldw/stw/ldo instruction that
4877 uses the result of the addil. */
4879 offset = ((offset + 0x1000) & ~0x1fff);
4881 if (GET_CODE (XEXP (x, 0)) == PLUS)
4891 else if (GET_CODE (XEXP (x, 0)) == MINUS
4892 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
4896 if (!read_only_operand (base, VOIDmode) && !flag_pic)
4897 fputs ("-$global$", file);
4899 fprintf (file, "%s%d", sep, offset);
4902 output_addr_const (file, x);
4905 static struct deferred_plabel *
4911 /* See if we have already put this function on the list of deferred
4912 plabels. This list is generally small, so a liner search is not
4913 too ugly. If it proves too slow replace it with something faster. */
4914 for (i = 0; i < n_deferred_plabels; i++)
4915 if (strcmp (fname, deferred_plabels[i].name) == 0)
4918 /* If the deferred plabel list is empty, or this entry was not found
4919 on the list, create a new entry on the list. */
4920 if (deferred_plabels == NULL || i == n_deferred_plabels)
4922 const char *real_name;
4924 if (deferred_plabels == 0)
4925 deferred_plabels = (struct deferred_plabel *)
4926 ggc_alloc (sizeof (struct deferred_plabel));
4928 deferred_plabels = (struct deferred_plabel *)
4929 ggc_realloc (deferred_plabels,
4930 ((n_deferred_plabels + 1)
4931 * sizeof (struct deferred_plabel)));
4933 i = n_deferred_plabels++;
4934 deferred_plabels[i].internal_label = gen_label_rtx ();
4935 deferred_plabels[i].name = ggc_strdup (fname);
4937 /* Gross. We have just implicitly taken the address of this function,
4939 real_name = (*targetm.strip_name_encoding) (fname);
4940 TREE_SYMBOL_REFERENCED (get_identifier (real_name)) = 1;
4943 return &deferred_plabels[i];
4947 output_deferred_plabels ()
4950 /* If we have deferred plabels, then we need to switch into the data
4951 section and align it to a 4 byte boundary before we output the
4952 deferred plabels. */
4953 if (n_deferred_plabels)
4956 ASM_OUTPUT_ALIGN (asm_out_file, TARGET_64BIT ? 3 : 2);
4959 /* Now output the deferred plabels. */
4960 for (i = 0; i < n_deferred_plabels; i++)
4962 (*targetm.asm_out.internal_label) (asm_out_file, "L",
4963 CODE_LABEL_NUMBER (deferred_plabels[i].internal_label));
4964 assemble_integer (gen_rtx_SYMBOL_REF (Pmode, deferred_plabels[i].name),
4965 TARGET_64BIT ? 8 : 4, TARGET_64BIT ? 64 : 32, 1);
4969 /* HP's millicode routines mean something special to the assembler.
4970 Keep track of which ones we have used. */
4972 enum millicodes { remI, remU, divI, divU, mulI, end1000 };
4973 static void import_milli PARAMS ((enum millicodes));
4974 static char imported[(int) end1000];
4975 static const char * const milli_names[] = {"remI", "remU", "divI", "divU", "mulI"};
4976 static const char import_string[] = ".IMPORT $$....,MILLICODE";
4977 #define MILLI_START 10
4981 enum millicodes code;
4983 char str[sizeof (import_string)];
4985 if (!imported[(int) code])
4987 imported[(int) code] = 1;
4988 strcpy (str, import_string);
4989 strncpy (str + MILLI_START, milli_names[(int) code], 4);
4990 output_asm_insn (str, 0);
4994 /* The register constraints have put the operands and return value in
4995 the proper registers. */
4998 output_mul_insn (unsignedp, insn)
4999 int unsignedp ATTRIBUTE_UNUSED;
5002 import_milli (mulI);
5003 return output_millicode_call (insn, gen_rtx_SYMBOL_REF (Pmode, "$$mulI"));
5006 /* Emit the rtl for doing a division by a constant. */
5008 /* Do magic division millicodes exist for this value? */
5009 static const int magic_milli[]= {0, 0, 0, 1, 0, 1, 1, 1, 0, 1, 1, 0, 1, 0,
5012 /* We'll use an array to keep track of the magic millicodes and
5013 whether or not we've used them already. [n][0] is signed, [n][1] is
5016 static int div_milli[16][2];
5019 div_operand (op, mode)
5021 enum machine_mode mode;
5023 return (mode == SImode
5024 && ((GET_CODE (op) == REG && REGNO (op) == 25)
5025 || (GET_CODE (op) == CONST_INT && INTVAL (op) > 0
5026 && INTVAL (op) < 16 && magic_milli[INTVAL (op)])));
5030 emit_hpdiv_const (operands, unsignedp)
5034 if (GET_CODE (operands[2]) == CONST_INT
5035 && INTVAL (operands[2]) > 0
5036 && INTVAL (operands[2]) < 16
5037 && magic_milli[INTVAL (operands[2])])
5039 rtx ret = gen_rtx_REG (SImode, TARGET_64BIT ? 2 : 31);
5041 emit_move_insn (gen_rtx_REG (SImode, 26), operands[1]);
5044 (PARALLEL, VOIDmode,
5045 gen_rtvec (6, gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, 29),
5046 gen_rtx_fmt_ee (unsignedp ? UDIV : DIV,
5048 gen_rtx_REG (SImode, 26),
5050 gen_rtx_CLOBBER (VOIDmode, operands[4]),
5051 gen_rtx_CLOBBER (VOIDmode, operands[3]),
5052 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 26)),
5053 gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (SImode, 25)),
5054 gen_rtx_CLOBBER (VOIDmode, ret))));
5055 emit_move_insn (operands[0], gen_rtx_REG (SImode, 29));
5062 output_div_insn (operands, unsignedp, insn)
5069 /* If the divisor is a constant, try to use one of the special
5071 if (GET_CODE (operands[0]) == CONST_INT)
5073 static char buf[100];
5074 divisor = INTVAL (operands[0]);
5075 if (!div_milli[divisor][unsignedp])
5077 div_milli[divisor][unsignedp] = 1;
5079 output_asm_insn (".IMPORT $$divU_%0,MILLICODE", operands);
5081 output_asm_insn (".IMPORT $$divI_%0,MILLICODE", operands);
5085 sprintf (buf, "$$divU_" HOST_WIDE_INT_PRINT_DEC,
5086 INTVAL (operands[0]));
5087 return output_millicode_call (insn,
5088 gen_rtx_SYMBOL_REF (SImode, buf));
5092 sprintf (buf, "$$divI_" HOST_WIDE_INT_PRINT_DEC,
5093 INTVAL (operands[0]));
5094 return output_millicode_call (insn,
5095 gen_rtx_SYMBOL_REF (SImode, buf));
5098 /* Divisor isn't a special constant. */
5103 import_milli (divU);
5104 return output_millicode_call (insn,
5105 gen_rtx_SYMBOL_REF (SImode, "$$divU"));
5109 import_milli (divI);
5110 return output_millicode_call (insn,
5111 gen_rtx_SYMBOL_REF (SImode, "$$divI"));
5116 /* Output a $$rem millicode to do mod. */
5119 output_mod_insn (unsignedp, insn)
5125 import_milli (remU);
5126 return output_millicode_call (insn,
5127 gen_rtx_SYMBOL_REF (SImode, "$$remU"));
5131 import_milli (remI);
5132 return output_millicode_call (insn,
5133 gen_rtx_SYMBOL_REF (SImode, "$$remI"));
5138 output_arg_descriptor (call_insn)
5141 const char *arg_regs[4];
5142 enum machine_mode arg_mode;
5144 int i, output_flag = 0;
5147 /* We neither need nor want argument location descriptors for the
5148 64bit runtime environment or the ELF32 environment. */
5149 if (TARGET_64BIT || TARGET_ELF32)
5152 for (i = 0; i < 4; i++)
5155 /* Specify explicitly that no argument relocations should take place
5156 if using the portable runtime calling conventions. */
5157 if (TARGET_PORTABLE_RUNTIME)
5159 fputs ("\t.CALL ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,RETVAL=NO\n",
5164 if (GET_CODE (call_insn) != CALL_INSN)
5166 for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1))
5168 rtx use = XEXP (link, 0);
5170 if (! (GET_CODE (use) == USE
5171 && GET_CODE (XEXP (use, 0)) == REG
5172 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
5175 arg_mode = GET_MODE (XEXP (use, 0));
5176 regno = REGNO (XEXP (use, 0));
5177 if (regno >= 23 && regno <= 26)
5179 arg_regs[26 - regno] = "GR";
5180 if (arg_mode == DImode)
5181 arg_regs[25 - regno] = "GR";
5183 else if (regno >= 32 && regno <= 39)
5185 if (arg_mode == SFmode)
5186 arg_regs[(regno - 32) / 2] = "FR";
5189 #ifndef HP_FP_ARG_DESCRIPTOR_REVERSED
5190 arg_regs[(regno - 34) / 2] = "FR";
5191 arg_regs[(regno - 34) / 2 + 1] = "FU";
5193 arg_regs[(regno - 34) / 2] = "FU";
5194 arg_regs[(regno - 34) / 2 + 1] = "FR";
5199 fputs ("\t.CALL ", asm_out_file);
5200 for (i = 0; i < 4; i++)
5205 fputc (',', asm_out_file);
5206 fprintf (asm_out_file, "ARGW%d=%s", i, arg_regs[i]);
5209 fputc ('\n', asm_out_file);
5212 /* Return the class of any secondary reload register that is needed to
5213 move IN into a register in class CLASS using mode MODE.
5215 Profiling has showed this routine and its descendants account for
5216 a significant amount of compile time (~7%). So it has been
5217 optimized to reduce redundant computations and eliminate useless
5220 It might be worthwhile to try and make this a leaf function too. */
5223 secondary_reload_class (class, mode, in)
5224 enum reg_class class;
5225 enum machine_mode mode;
5228 int regno, is_symbolic;
5230 /* Trying to load a constant into a FP register during PIC code
5231 generation will require %r1 as a scratch register. */
5233 && GET_MODE_CLASS (mode) == MODE_INT
5234 && FP_REG_CLASS_P (class)
5235 && (GET_CODE (in) == CONST_INT || GET_CODE (in) == CONST_DOUBLE))
5238 /* Profiling showed the PA port spends about 1.3% of its compilation
5239 time in true_regnum from calls inside secondary_reload_class. */
5241 if (GET_CODE (in) == REG)
5244 if (regno >= FIRST_PSEUDO_REGISTER)
5245 regno = true_regnum (in);
5247 else if (GET_CODE (in) == SUBREG)
5248 regno = true_regnum (in);
5252 /* If we have something like (mem (mem (...)), we can safely assume the
5253 inner MEM will end up in a general register after reloading, so there's
5254 no need for a secondary reload. */
5255 if (GET_CODE (in) == MEM
5256 && GET_CODE (XEXP (in, 0)) == MEM)
5259 /* Handle out of range displacement for integer mode loads/stores of
5261 if (((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
5262 && GET_MODE_CLASS (mode) == MODE_INT
5263 && FP_REG_CLASS_P (class))
5264 || (class == SHIFT_REGS && (regno <= 0 || regno >= 32)))
5265 return GENERAL_REGS;
5267 /* A SAR<->FP register copy requires a secondary register (GPR) as
5268 well as secondary memory. */
5269 if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
5270 && ((REGNO_REG_CLASS (regno) == SHIFT_REGS && FP_REG_CLASS_P (class))
5271 || (class == SHIFT_REGS && FP_REG_CLASS_P (REGNO_REG_CLASS (regno)))))
5272 return GENERAL_REGS;
5274 if (GET_CODE (in) == HIGH)
5277 /* Profiling has showed GCC spends about 2.6% of its compilation
5278 time in symbolic_operand from calls inside secondary_reload_class.
5280 We use an inline copy and only compute its return value once to avoid
5282 switch (GET_CODE (in))
5292 is_symbolic = ((GET_CODE (XEXP (tmp, 0)) == SYMBOL_REF
5293 || GET_CODE (XEXP (tmp, 0)) == LABEL_REF)
5294 && GET_CODE (XEXP (tmp, 1)) == CONST_INT);
5304 && read_only_operand (in, VOIDmode))
5307 if (class != R1_REGS && is_symbolic)
5314 function_arg_padding (mode, type)
5315 enum machine_mode mode;
5319 || (TARGET_64BIT && type && AGGREGATE_TYPE_P (type)))
5321 /* Return none if justification is not required. */
5323 && TREE_CODE (TYPE_SIZE (type)) == INTEGER_CST
5324 && (int_size_in_bytes (type) * BITS_PER_UNIT) % PARM_BOUNDARY == 0)
5327 /* The directions set here are ignored when a BLKmode argument larger
5328 than a word is placed in a register. Different code is used for
5329 the stack and registers. This makes it difficult to have a
5330 consistent data representation for both the stack and registers.
5331 For both runtimes, the justification and padding for arguments on
5332 the stack and in registers should be identical. */
5334 /* The 64-bit runtime specifies left justification for aggregates. */
5337 /* The 32-bit runtime architecture specifies right justification.
5338 When the argument is passed on the stack, the argument is padded
5339 with garbage on the left. The HP compiler pads with zeros. */
5343 if (GET_MODE_BITSIZE (mode) < PARM_BOUNDARY)
5350 /* Do what is necessary for `va_start'. We look at the current function
5351 to determine if stdargs or varargs is used and fill in an initial
5352 va_list. A pointer to this constructor is returned. */
5355 hppa_builtin_saveregs ()
5358 tree fntype = TREE_TYPE (current_function_decl);
5359 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
5360 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
5361 != void_type_node)))
5362 ? UNITS_PER_WORD : 0);
5365 offset = plus_constant (current_function_arg_offset_rtx, argadj);
5367 offset = current_function_arg_offset_rtx;
5373 /* Adjust for varargs/stdarg differences. */
5375 offset = plus_constant (current_function_arg_offset_rtx, -argadj);
5377 offset = current_function_arg_offset_rtx;
5379 /* We need to save %r26 .. %r19 inclusive starting at offset -64
5380 from the incoming arg pointer and growing to larger addresses. */
5381 for (i = 26, off = -64; i >= 19; i--, off += 8)
5382 emit_move_insn (gen_rtx_MEM (word_mode,
5383 plus_constant (arg_pointer_rtx, off)),
5384 gen_rtx_REG (word_mode, i));
5386 /* The incoming args pointer points just beyond the flushback area;
5387 normally this is not a serious concern. However, when we are doing
5388 varargs/stdargs we want to make the arg pointer point to the start
5389 of the incoming argument area. */
5390 emit_move_insn (virtual_incoming_args_rtx,
5391 plus_constant (arg_pointer_rtx, -64));
5393 /* Now return a pointer to the first anonymous argument. */
5394 return copy_to_reg (expand_binop (Pmode, add_optab,
5395 virtual_incoming_args_rtx,
5396 offset, 0, 0, OPTAB_LIB_WIDEN));
5399 /* Store general registers on the stack. */
5400 dest = gen_rtx_MEM (BLKmode,
5401 plus_constant (current_function_internal_arg_pointer,
5403 set_mem_alias_set (dest, get_varargs_alias_set ());
5404 set_mem_align (dest, BITS_PER_WORD);
5405 move_block_from_reg (23, dest, 4);
5407 /* move_block_from_reg will emit code to store the argument registers
5408 individually as scalar stores.
5410 However, other insns may later load from the same addresses for
5411 a structure load (passing a struct to a varargs routine).
5413 The alias code assumes that such aliasing can never happen, so we
5414 have to keep memory referencing insns from moving up beyond the
5415 last argument register store. So we emit a blockage insn here. */
5416 emit_insn (gen_blockage ());
5418 return copy_to_reg (expand_binop (Pmode, add_optab,
5419 current_function_internal_arg_pointer,
5420 offset, 0, 0, OPTAB_LIB_WIDEN));
5424 hppa_va_start (valist, nextarg)
5428 nextarg = expand_builtin_saveregs ();
5429 std_expand_builtin_va_start (valist, nextarg);
5433 hppa_va_arg (valist, type)
5436 HOST_WIDE_INT size = int_size_in_bytes (type);
5442 /* Every argument in PA64 is supposed to be passed by value
5443 (including large structs). However, as a GCC extension, we
5444 pass zero and variable sized arguments by reference. Empty
5445 structures are a GCC extension not supported by the HP
5446 compilers. Thus, passing them by reference isn't likely
5447 to conflict with the ABI. For variable sized arguments,
5448 GCC doesn't have the infrastructure to allocate these to
5451 /* Arguments with a size greater than 8 must be aligned 0 MOD 16. */
5453 if (size > UNITS_PER_WORD)
5455 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5456 build_int_2 (2 * UNITS_PER_WORD - 1, 0));
5457 t = build (BIT_AND_EXPR, TREE_TYPE (t), t,
5458 build_int_2 (-2 * UNITS_PER_WORD, -1));
5459 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5460 TREE_SIDE_EFFECTS (t) = 1;
5461 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL);
5465 return std_expand_builtin_va_arg (valist, type);
5468 ptr = build_pointer_type (type);
5470 /* Args grow upward. */
5471 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
5472 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5473 TREE_SIDE_EFFECTS (t) = 1;
5475 pptr = build_pointer_type (ptr);
5476 t = build1 (NOP_EXPR, pptr, t);
5477 TREE_SIDE_EFFECTS (t) = 1;
5479 t = build1 (INDIRECT_REF, ptr, t);
5480 TREE_SIDE_EFFECTS (t) = 1;
5483 else /* !TARGET_64BIT */
5485 ptr = build_pointer_type (type);
5487 /* "Large" and variable sized types are passed by reference. */
5488 if (size > 8 || size <= 0)
5490 /* Args grow downward. */
5491 t = build (PREDECREMENT_EXPR, TREE_TYPE (valist), valist,
5492 build_int_2 (POINTER_SIZE / BITS_PER_UNIT, 0));
5493 TREE_SIDE_EFFECTS (t) = 1;
5495 pptr = build_pointer_type (ptr);
5496 t = build1 (NOP_EXPR, pptr, t);
5497 TREE_SIDE_EFFECTS (t) = 1;
5499 t = build1 (INDIRECT_REF, ptr, t);
5500 TREE_SIDE_EFFECTS (t) = 1;
5504 t = build (PLUS_EXPR, TREE_TYPE (valist), valist,
5505 build_int_2 (-size, -1));
5507 /* Copied from va-pa.h, but we probably don't need to align to
5508 word size, since we generate and preserve that invariant. */
5509 t = build (BIT_AND_EXPR, TREE_TYPE (valist), t,
5510 build_int_2 ((size > 4 ? -8 : -4), -1));
5512 t = build (MODIFY_EXPR, TREE_TYPE (valist), valist, t);
5513 TREE_SIDE_EFFECTS (t) = 1;
5515 ofs = (8 - size) % 4;
5518 t = build (PLUS_EXPR, TREE_TYPE (valist), t,
5519 build_int_2 (ofs, 0));
5520 TREE_SIDE_EFFECTS (t) = 1;
5523 t = build1 (NOP_EXPR, ptr, t);
5524 TREE_SIDE_EFFECTS (t) = 1;
5529 return expand_expr (t, NULL_RTX, VOIDmode, EXPAND_NORMAL);
5534 /* This routine handles all the normal conditional branch sequences we
5535 might need to generate. It handles compare immediate vs compare
5536 register, nullification of delay slots, varying length branches,
5537 negated branches, and all combinations of the above. It returns the
5538 output appropriate to emit the branch corresponding to all given
5542 output_cbranch (operands, nullify, length, negated, insn)
5544 int nullify, length, negated;
5547 static char buf[100];
5551 /* A conditional branch to the following instruction (eg the delay slot)
5552 is asking for a disaster. This can happen when not optimizing and
5553 when jump optimization fails.
5555 While it is usually safe to emit nothing, this can fail if the
5556 preceding instruction is a nullified branch with an empty delay
5557 slot and the same branch target as this branch. We could check
5558 for this but jump optimization should eliminate nop jumps. It
5559 is always safe to emit a nop. */
5560 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5563 /* If this is a long branch with its delay slot unfilled, set `nullify'
5564 as it can nullify the delay slot and save a nop. */
5565 if (length == 8 && dbr_sequence_length () == 0)
5568 /* If this is a short forward conditional branch which did not get
5569 its delay slot filled, the delay slot can still be nullified. */
5570 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5571 nullify = forward_branch_p (insn);
5573 /* A forward branch over a single nullified insn can be done with a
5574 comclr instruction. This avoids a single cycle penalty due to
5575 mis-predicted branch if we fall through (branch not taken). */
5577 && next_real_insn (insn) != 0
5578 && get_attr_length (next_real_insn (insn)) == 4
5579 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5585 /* All short conditional branches except backwards with an unfilled
5589 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5591 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5592 if (GET_MODE (operands[1]) == DImode)
5595 strcat (buf, "%B3");
5597 strcat (buf, "%S3");
5599 strcat (buf, " %2,%r1,%%r0");
5601 strcat (buf, ",n %2,%r1,%0");
5603 strcat (buf, " %2,%r1,%0");
5606 /* All long conditionals. Note a short backward branch with an
5607 unfilled delay slot is treated just like a long backward branch
5608 with an unfilled delay slot. */
5610 /* Handle weird backwards branch with a filled delay slot
5611 with is nullified. */
5612 if (dbr_sequence_length () != 0
5613 && ! forward_branch_p (insn)
5616 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5617 if (GET_MODE (operands[1]) == DImode)
5620 strcat (buf, "%S3");
5622 strcat (buf, "%B3");
5623 strcat (buf, ",n %2,%r1,.+12\n\tb %0");
5625 /* Handle short backwards branch with an unfilled delay slot.
5626 Using a comb;nop rather than comiclr;bl saves 1 cycle for both
5627 taken and untaken branches. */
5628 else if (dbr_sequence_length () == 0
5629 && ! forward_branch_p (insn)
5630 && INSN_ADDRESSES_SET_P ()
5631 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5632 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5634 strcpy (buf, "{com%I2b,|cmp%I2b,}");
5635 if (GET_MODE (operands[1]) == DImode)
5638 strcat (buf, "%B3 %2,%r1,%0%#");
5640 strcat (buf, "%S3 %2,%r1,%0%#");
5644 strcpy (buf, "{com%I2clr,|cmp%I2clr,}");
5645 if (GET_MODE (operands[1]) == DImode)
5648 strcat (buf, "%S3");
5650 strcat (buf, "%B3");
5652 strcat (buf, " %2,%r1,%%r0\n\tb,n %0");
5654 strcat (buf, " %2,%r1,%%r0\n\tb %0");
5660 xoperands[0] = operands[0];
5661 xoperands[1] = operands[1];
5662 xoperands[2] = operands[2];
5663 xoperands[3] = operands[3];
5665 /* The reversed conditional branch must branch over one additional
5666 instruction if the delay slot is filled. If the delay slot
5667 is empty, the instruction after the reversed condition branch
5668 must be nullified. */
5669 nullify = dbr_sequence_length () == 0;
5670 xoperands[4] = nullify ? GEN_INT (length) : GEN_INT (length + 4);
5672 /* Create a reversed conditional branch which branches around
5673 the following insns. */
5674 if (GET_MODE (operands[1]) != DImode)
5680 "{com%I2b,%S3,n %2,%r1,.+%4|cmp%I2b,%S3,n %2,%r1,.+%4}");
5683 "{com%I2b,%B3,n %2,%r1,.+%4|cmp%I2b,%B3,n %2,%r1,.+%4}");
5689 "{com%I2b,%S3 %2,%r1,.+%4|cmp%I2b,%S3 %2,%r1,.+%4}");
5692 "{com%I2b,%B3 %2,%r1,.+%4|cmp%I2b,%B3 %2,%r1,.+%4}");
5701 "{com%I2b,*%S3,n %2,%r1,.+%4|cmp%I2b,*%S3,n %2,%r1,.+%4}");
5704 "{com%I2b,*%B3,n %2,%r1,.+%4|cmp%I2b,*%B3,n %2,%r1,.+%4}");
5710 "{com%I2b,*%S3 %2,%r1,.+%4|cmp%I2b,*%S3 %2,%r1,.+%4}");
5713 "{com%I2b,*%B3 %2,%r1,.+%4|cmp%I2b,*%B3 %2,%r1,.+%4}");
5717 output_asm_insn (buf, xoperands);
5718 return output_lbranch (operands[0], insn);
5726 /* This routine handles long unconditional branches that exceed the
5727 maximum range of a simple branch instruction. */
5730 output_lbranch (dest, insn)
5735 xoperands[0] = dest;
5737 /* First, free up the delay slot. */
5738 if (dbr_sequence_length () != 0)
5740 /* We can't handle a jump in the delay slot. */
5741 if (GET_CODE (NEXT_INSN (insn)) == JUMP_INSN)
5744 final_scan_insn (NEXT_INSN (insn), asm_out_file,
5747 /* Now delete the delay insn. */
5748 PUT_CODE (NEXT_INSN (insn), NOTE);
5749 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
5750 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
5753 /* Output an insn to save %r1. The runtime documentation doesn't
5754 specify whether the "Clean Up" slot in the callers frame can
5755 be clobbered by the callee. It isn't copied by HP's builtin
5756 alloca, so this suggests that it can be clobbered if necessary.
5757 The "Static Link" location is copied by HP builtin alloca, so
5758 we avoid using it. Using the cleanup slot might be a problem
5759 if we have to interoperate with languages that pass cleanup
5760 information. However, it should be possible to handle these
5761 situations with GCC's asm feature.
5763 The "Current RP" slot is reserved for the called procedure, so
5764 we try to use it when we don't have a frame of our own. It's
5765 rather unlikely that we won't have a frame when we need to emit
5768 Really the way to go long term is a register scavenger; goto
5769 the target of the jump and find a register which we can use
5770 as a scratch to hold the value in %r1. Then, we wouldn't have
5771 to free up the delay slot or clobber a slot that may be needed
5772 for other purposes. */
5775 if (actual_fsize == 0 && !regs_ever_live[2])
5776 /* Use the return pointer slot in the frame marker. */
5777 output_asm_insn ("std %%r1,-16(%%r30)", xoperands);
5779 /* Use the slot at -40 in the frame marker since HP builtin
5780 alloca doesn't copy it. */
5781 output_asm_insn ("std %%r1,-40(%%r30)", xoperands);
5785 if (actual_fsize == 0 && !regs_ever_live[2])
5786 /* Use the return pointer slot in the frame marker. */
5787 output_asm_insn ("stw %%r1,-20(%%r30)", xoperands);
5789 /* Use the "Clean Up" slot in the frame marker. In GCC,
5790 the only other use of this location is for copying a
5791 floating point double argument from a floating-point
5792 register to two general registers. The copy is done
5793 as an "atomic" operation when outputting a call, so it
5794 won't interfere with our using the location here. */
5795 output_asm_insn ("stw %%r1,-12(%%r30)", xoperands);
5800 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
5801 if (TARGET_SOM || !TARGET_GAS)
5803 xoperands[1] = gen_label_rtx ();
5804 output_asm_insn ("addil L'%l0-%l1,%%r1", xoperands);
5805 (*targetm.asm_out.internal_label) (asm_out_file, "L",
5806 CODE_LABEL_NUMBER (xoperands[1]));
5807 output_asm_insn ("ldo R'%l0-%l1(%%r1),%%r1", xoperands);
5811 output_asm_insn ("addil L'%l0-$PIC_pcrel$0+4,%%r1", xoperands);
5812 output_asm_insn ("ldo R'%l0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
5814 output_asm_insn ("bv %%r0(%%r1)", xoperands);
5817 /* Now output a very long branch to the original target. */
5818 output_asm_insn ("ldil L'%l0,%%r1\n\tbe R'%l0(%%sr4,%%r1)", xoperands);
5820 /* Now restore the value of %r1 in the delay slot. */
5823 if (actual_fsize == 0 && !regs_ever_live[2])
5824 return "ldd -16(%%r30),%%r1";
5826 return "ldd -40(%%r30),%%r1";
5830 if (actual_fsize == 0 && !regs_ever_live[2])
5831 return "ldw -20(%%r30),%%r1";
5833 return "ldw -12(%%r30),%%r1";
5837 /* This routine handles all the branch-on-bit conditional branch sequences we
5838 might need to generate. It handles nullification of delay slots,
5839 varying length branches, negated branches and all combinations of the
5840 above. it returns the appropriate output template to emit the branch. */
5843 output_bb (operands, nullify, length, negated, insn, which)
5844 rtx *operands ATTRIBUTE_UNUSED;
5845 int nullify, length, negated;
5849 static char buf[100];
5852 /* A conditional branch to the following instruction (eg the delay slot) is
5853 asking for a disaster. I do not think this can happen as this pattern
5854 is only used when optimizing; jump optimization should eliminate the
5855 jump. But be prepared just in case. */
5857 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
5860 /* If this is a long branch with its delay slot unfilled, set `nullify'
5861 as it can nullify the delay slot and save a nop. */
5862 if (length == 8 && dbr_sequence_length () == 0)
5865 /* If this is a short forward conditional branch which did not get
5866 its delay slot filled, the delay slot can still be nullified. */
5867 if (! nullify && length == 4 && dbr_sequence_length () == 0)
5868 nullify = forward_branch_p (insn);
5870 /* A forward branch over a single nullified insn can be done with a
5871 extrs instruction. This avoids a single cycle penalty due to
5872 mis-predicted branch if we fall through (branch not taken). */
5875 && next_real_insn (insn) != 0
5876 && get_attr_length (next_real_insn (insn)) == 4
5877 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
5884 /* All short conditional branches except backwards with an unfilled
5888 strcpy (buf, "{extrs,|extrw,s,}");
5890 strcpy (buf, "bb,");
5891 if (useskip && GET_MODE (operands[0]) == DImode)
5892 strcpy (buf, "extrd,s,*");
5893 else if (GET_MODE (operands[0]) == DImode)
5894 strcpy (buf, "bb,*");
5895 if ((which == 0 && negated)
5896 || (which == 1 && ! negated))
5901 strcat (buf, " %0,%1,1,%%r0");
5902 else if (nullify && negated)
5903 strcat (buf, ",n %0,%1,%3");
5904 else if (nullify && ! negated)
5905 strcat (buf, ",n %0,%1,%2");
5906 else if (! nullify && negated)
5907 strcat (buf, "%0,%1,%3");
5908 else if (! nullify && ! negated)
5909 strcat (buf, " %0,%1,%2");
5912 /* All long conditionals. Note a short backward branch with an
5913 unfilled delay slot is treated just like a long backward branch
5914 with an unfilled delay slot. */
5916 /* Handle weird backwards branch with a filled delay slot
5917 with is nullified. */
5918 if (dbr_sequence_length () != 0
5919 && ! forward_branch_p (insn)
5922 strcpy (buf, "bb,");
5923 if (GET_MODE (operands[0]) == DImode)
5925 if ((which == 0 && negated)
5926 || (which == 1 && ! negated))
5931 strcat (buf, ",n %0,%1,.+12\n\tb %3");
5933 strcat (buf, ",n %0,%1,.+12\n\tb %2");
5935 /* Handle short backwards branch with an unfilled delay slot.
5936 Using a bb;nop rather than extrs;bl saves 1 cycle for both
5937 taken and untaken branches. */
5938 else if (dbr_sequence_length () == 0
5939 && ! forward_branch_p (insn)
5940 && INSN_ADDRESSES_SET_P ()
5941 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
5942 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
5944 strcpy (buf, "bb,");
5945 if (GET_MODE (operands[0]) == DImode)
5947 if ((which == 0 && negated)
5948 || (which == 1 && ! negated))
5953 strcat (buf, " %0,%1,%3%#");
5955 strcat (buf, " %0,%1,%2%#");
5959 strcpy (buf, "{extrs,|extrw,s,}");
5960 if (GET_MODE (operands[0]) == DImode)
5961 strcpy (buf, "extrd,s,*");
5962 if ((which == 0 && negated)
5963 || (which == 1 && ! negated))
5967 if (nullify && negated)
5968 strcat (buf, " %0,%1,1,%%r0\n\tb,n %3");
5969 else if (nullify && ! negated)
5970 strcat (buf, " %0,%1,1,%%r0\n\tb,n %2");
5972 strcat (buf, " %0,%1,1,%%r0\n\tb %3");
5974 strcat (buf, " %0,%1,1,%%r0\n\tb %2");
5984 /* This routine handles all the branch-on-variable-bit conditional branch
5985 sequences we might need to generate. It handles nullification of delay
5986 slots, varying length branches, negated branches and all combinations
5987 of the above. it returns the appropriate output template to emit the
5991 output_bvb (operands, nullify, length, negated, insn, which)
5992 rtx *operands ATTRIBUTE_UNUSED;
5993 int nullify, length, negated;
5997 static char buf[100];
6000 /* A conditional branch to the following instruction (eg the delay slot) is
6001 asking for a disaster. I do not think this can happen as this pattern
6002 is only used when optimizing; jump optimization should eliminate the
6003 jump. But be prepared just in case. */
6005 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6008 /* If this is a long branch with its delay slot unfilled, set `nullify'
6009 as it can nullify the delay slot and save a nop. */
6010 if (length == 8 && dbr_sequence_length () == 0)
6013 /* If this is a short forward conditional branch which did not get
6014 its delay slot filled, the delay slot can still be nullified. */
6015 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6016 nullify = forward_branch_p (insn);
6018 /* A forward branch over a single nullified insn can be done with a
6019 extrs instruction. This avoids a single cycle penalty due to
6020 mis-predicted branch if we fall through (branch not taken). */
6023 && next_real_insn (insn) != 0
6024 && get_attr_length (next_real_insn (insn)) == 4
6025 && JUMP_LABEL (insn) == next_nonnote_insn (next_real_insn (insn))
6032 /* All short conditional branches except backwards with an unfilled
6036 strcpy (buf, "{vextrs,|extrw,s,}");
6038 strcpy (buf, "{bvb,|bb,}");
6039 if (useskip && GET_MODE (operands[0]) == DImode)
6040 strcpy (buf, "extrd,s,*}");
6041 else if (GET_MODE (operands[0]) == DImode)
6042 strcpy (buf, "bb,*");
6043 if ((which == 0 && negated)
6044 || (which == 1 && ! negated))
6049 strcat (buf, "{ %0,1,%%r0| %0,%%sar,1,%%r0}");
6050 else if (nullify && negated)
6051 strcat (buf, "{,n %0,%3|,n %0,%%sar,%3}");
6052 else if (nullify && ! negated)
6053 strcat (buf, "{,n %0,%2|,n %0,%%sar,%2}");
6054 else if (! nullify && negated)
6055 strcat (buf, "{%0,%3|%0,%%sar,%3}");
6056 else if (! nullify && ! negated)
6057 strcat (buf, "{ %0,%2| %0,%%sar,%2}");
6060 /* All long conditionals. Note a short backward branch with an
6061 unfilled delay slot is treated just like a long backward branch
6062 with an unfilled delay slot. */
6064 /* Handle weird backwards branch with a filled delay slot
6065 with is nullified. */
6066 if (dbr_sequence_length () != 0
6067 && ! forward_branch_p (insn)
6070 strcpy (buf, "{bvb,|bb,}");
6071 if (GET_MODE (operands[0]) == DImode)
6073 if ((which == 0 && negated)
6074 || (which == 1 && ! negated))
6079 strcat (buf, "{,n %0,.+12\n\tb %3|,n %0,%%sar,.+12\n\tb %3}");
6081 strcat (buf, "{,n %0,.+12\n\tb %2|,n %0,%%sar,.+12\n\tb %2}");
6083 /* Handle short backwards branch with an unfilled delay slot.
6084 Using a bb;nop rather than extrs;bl saves 1 cycle for both
6085 taken and untaken branches. */
6086 else if (dbr_sequence_length () == 0
6087 && ! forward_branch_p (insn)
6088 && INSN_ADDRESSES_SET_P ()
6089 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6090 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6092 strcpy (buf, "{bvb,|bb,}");
6093 if (GET_MODE (operands[0]) == DImode)
6095 if ((which == 0 && negated)
6096 || (which == 1 && ! negated))
6101 strcat (buf, "{ %0,%3%#| %0,%%sar,%3%#}");
6103 strcat (buf, "{ %0,%2%#| %0,%%sar,%2%#}");
6107 strcpy (buf, "{vextrs,|extrw,s,}");
6108 if (GET_MODE (operands[0]) == DImode)
6109 strcpy (buf, "extrd,s,*");
6110 if ((which == 0 && negated)
6111 || (which == 1 && ! negated))
6115 if (nullify && negated)
6116 strcat (buf, "{ %0,1,%%r0\n\tb,n %3| %0,%%sar,1,%%r0\n\tb,n %3}");
6117 else if (nullify && ! negated)
6118 strcat (buf, "{ %0,1,%%r0\n\tb,n %2| %0,%%sar,1,%%r0\n\tb,n %2}");
6120 strcat (buf, "{ %0,1,%%r0\n\tb %3| %0,%%sar,1,%%r0\n\tb %3}");
6122 strcat (buf, "{ %0,1,%%r0\n\tb %2| %0,%%sar,1,%%r0\n\tb %2}");
6132 /* Return the output template for emitting a dbra type insn.
6134 Note it may perform some output operations on its own before
6135 returning the final output string. */
6137 output_dbra (operands, insn, which_alternative)
6140 int which_alternative;
6143 /* A conditional branch to the following instruction (eg the delay slot) is
6144 asking for a disaster. Be prepared! */
6146 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6148 if (which_alternative == 0)
6149 return "ldo %1(%0),%0";
6150 else if (which_alternative == 1)
6152 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)", operands);
6153 output_asm_insn ("ldw -16(%%r30),%4", operands);
6154 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6155 return "{fldws|fldw} -16(%%r30),%0";
6159 output_asm_insn ("ldw %0,%4", operands);
6160 return "ldo %1(%4),%4\n\tstw %4,%0";
6164 if (which_alternative == 0)
6166 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6167 int length = get_attr_length (insn);
6169 /* If this is a long branch with its delay slot unfilled, set `nullify'
6170 as it can nullify the delay slot and save a nop. */
6171 if (length == 8 && dbr_sequence_length () == 0)
6174 /* If this is a short forward conditional branch which did not get
6175 its delay slot filled, the delay slot can still be nullified. */
6176 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6177 nullify = forward_branch_p (insn);
6179 /* Handle short versions first. */
6180 if (length == 4 && nullify)
6181 return "addib,%C2,n %1,%0,%3";
6182 else if (length == 4 && ! nullify)
6183 return "addib,%C2 %1,%0,%3";
6184 else if (length == 8)
6186 /* Handle weird backwards branch with a fulled delay slot
6187 which is nullified. */
6188 if (dbr_sequence_length () != 0
6189 && ! forward_branch_p (insn)
6191 return "addib,%N2,n %1,%0,.+12\n\tb %3";
6192 /* Handle short backwards branch with an unfilled delay slot.
6193 Using a addb;nop rather than addi;bl saves 1 cycle for both
6194 taken and untaken branches. */
6195 else if (dbr_sequence_length () == 0
6196 && ! forward_branch_p (insn)
6197 && INSN_ADDRESSES_SET_P ()
6198 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6199 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6200 return "addib,%C2 %1,%0,%3%#";
6202 /* Handle normal cases. */
6204 return "addi,%N2 %1,%0,%0\n\tb,n %3";
6206 return "addi,%N2 %1,%0,%0\n\tb %3";
6211 /* Deal with gross reload from FP register case. */
6212 else if (which_alternative == 1)
6214 /* Move loop counter from FP register to MEM then into a GR,
6215 increment the GR, store the GR into MEM, and finally reload
6216 the FP register from MEM from within the branch's delay slot. */
6217 output_asm_insn ("{fstws|fstw} %0,-16(%%r30)\n\tldw -16(%%r30),%4",
6219 output_asm_insn ("ldo %1(%4),%4\n\tstw %4,-16(%%r30)", operands);
6220 if (get_attr_length (insn) == 24)
6221 return "{comb|cmpb},%S2 %%r0,%4,%3\n\t{fldws|fldw} -16(%%r30),%0";
6223 return "{comclr|cmpclr},%B2 %%r0,%4,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6225 /* Deal with gross reload from memory case. */
6228 /* Reload loop counter from memory, the store back to memory
6229 happens in the branch's delay slot. */
6230 output_asm_insn ("ldw %0,%4", operands);
6231 if (get_attr_length (insn) == 12)
6232 return "addib,%C2 %1,%4,%3\n\tstw %4,%0";
6234 return "addi,%N2 %1,%4,%4\n\tb %3\n\tstw %4,%0";
6238 /* Return the output template for emitting a dbra type insn.
6240 Note it may perform some output operations on its own before
6241 returning the final output string. */
6243 output_movb (operands, insn, which_alternative, reverse_comparison)
6246 int which_alternative;
6247 int reverse_comparison;
6250 /* A conditional branch to the following instruction (eg the delay slot) is
6251 asking for a disaster. Be prepared! */
6253 if (next_real_insn (JUMP_LABEL (insn)) == next_real_insn (insn))
6255 if (which_alternative == 0)
6256 return "copy %1,%0";
6257 else if (which_alternative == 1)
6259 output_asm_insn ("stw %1,-16(%%r30)", operands);
6260 return "{fldws|fldw} -16(%%r30),%0";
6262 else if (which_alternative == 2)
6268 /* Support the second variant. */
6269 if (reverse_comparison)
6270 PUT_CODE (operands[2], reverse_condition (GET_CODE (operands[2])));
6272 if (which_alternative == 0)
6274 int nullify = INSN_ANNULLED_BRANCH_P (insn);
6275 int length = get_attr_length (insn);
6277 /* If this is a long branch with its delay slot unfilled, set `nullify'
6278 as it can nullify the delay slot and save a nop. */
6279 if (length == 8 && dbr_sequence_length () == 0)
6282 /* If this is a short forward conditional branch which did not get
6283 its delay slot filled, the delay slot can still be nullified. */
6284 if (! nullify && length == 4 && dbr_sequence_length () == 0)
6285 nullify = forward_branch_p (insn);
6287 /* Handle short versions first. */
6288 if (length == 4 && nullify)
6289 return "movb,%C2,n %1,%0,%3";
6290 else if (length == 4 && ! nullify)
6291 return "movb,%C2 %1,%0,%3";
6292 else if (length == 8)
6294 /* Handle weird backwards branch with a filled delay slot
6295 which is nullified. */
6296 if (dbr_sequence_length () != 0
6297 && ! forward_branch_p (insn)
6299 return "movb,%N2,n %1,%0,.+12\n\tb %3";
6301 /* Handle short backwards branch with an unfilled delay slot.
6302 Using a movb;nop rather than or;bl saves 1 cycle for both
6303 taken and untaken branches. */
6304 else if (dbr_sequence_length () == 0
6305 && ! forward_branch_p (insn)
6306 && INSN_ADDRESSES_SET_P ()
6307 && VAL_14_BITS_P (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (insn)))
6308 - INSN_ADDRESSES (INSN_UID (insn)) - 8))
6309 return "movb,%C2 %1,%0,%3%#";
6310 /* Handle normal cases. */
6312 return "or,%N2 %1,%%r0,%0\n\tb,n %3";
6314 return "or,%N2 %1,%%r0,%0\n\tb %3";
6319 /* Deal with gross reload from FP register case. */
6320 else if (which_alternative == 1)
6322 /* Move loop counter from FP register to MEM then into a GR,
6323 increment the GR, store the GR into MEM, and finally reload
6324 the FP register from MEM from within the branch's delay slot. */
6325 output_asm_insn ("stw %1,-16(%%r30)", operands);
6326 if (get_attr_length (insn) == 12)
6327 return "{comb|cmpb},%S2 %%r0,%1,%3\n\t{fldws|fldw} -16(%%r30),%0";
6329 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\t{fldws|fldw} -16(%%r30),%0";
6331 /* Deal with gross reload from memory case. */
6332 else if (which_alternative == 2)
6334 /* Reload loop counter from memory, the store back to memory
6335 happens in the branch's delay slot. */
6336 if (get_attr_length (insn) == 8)
6337 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tstw %1,%0";
6339 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tb %3\n\tstw %1,%0";
6341 /* Handle SAR as a destination. */
6344 if (get_attr_length (insn) == 8)
6345 return "{comb|cmpb},%S2 %%r0,%1,%3\n\tmtsar %r1";
6347 return "{comclr|cmpclr},%B2 %%r0,%1,%%r0\n\tbl %3\n\tmtsar %r1";
6351 /* Copy any FP arguments in INSN into integer registers. */
6359 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6361 int arg_mode, regno;
6362 rtx use = XEXP (link, 0);
6364 if (! (GET_CODE (use) == USE
6365 && GET_CODE (XEXP (use, 0)) == REG
6366 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6369 arg_mode = GET_MODE (XEXP (use, 0));
6370 regno = REGNO (XEXP (use, 0));
6372 /* Is it a floating point register? */
6373 if (regno >= 32 && regno <= 39)
6375 /* Copy the FP register into an integer register via memory. */
6376 if (arg_mode == SFmode)
6378 xoperands[0] = XEXP (use, 0);
6379 xoperands[1] = gen_rtx_REG (SImode, 26 - (regno - 32) / 2);
6380 output_asm_insn ("{fstws|fstw} %0,-16(%%sr0,%%r30)", xoperands);
6381 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6385 xoperands[0] = XEXP (use, 0);
6386 xoperands[1] = gen_rtx_REG (DImode, 25 - (regno - 34) / 2);
6387 output_asm_insn ("{fstds|fstd} %0,-16(%%sr0,%%r30)", xoperands);
6388 output_asm_insn ("ldw -12(%%sr0,%%r30),%R1", xoperands);
6389 output_asm_insn ("ldw -16(%%sr0,%%r30),%1", xoperands);
6395 /* Compute length of the FP argument copy sequence for INSN. */
6397 length_fp_args (insn)
6403 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1))
6405 int arg_mode, regno;
6406 rtx use = XEXP (link, 0);
6408 if (! (GET_CODE (use) == USE
6409 && GET_CODE (XEXP (use, 0)) == REG
6410 && FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
6413 arg_mode = GET_MODE (XEXP (use, 0));
6414 regno = REGNO (XEXP (use, 0));
6416 /* Is it a floating point register? */
6417 if (regno >= 32 && regno <= 39)
6419 if (arg_mode == SFmode)
6429 /* Return the attribute length for the millicode call instruction INSN.
6430 The length must match the code generated by output_millicode_call.
6431 We include the delay slot in the returned length as it is better to
6432 over estimate the length than to under estimate it. */
6435 attr_length_millicode_call (insn)
6438 unsigned long distance = -1;
6440 if (INSN_ADDRESSES_SET_P ())
6442 distance = (total_code_bytes + insn_current_reference_address (insn));
6443 if (distance < total_code_bytes)
6449 if (!TARGET_LONG_CALLS && distance < 7600000)
6454 else if (TARGET_PORTABLE_RUNTIME)
6458 if (!TARGET_LONG_CALLS && distance < 240000)
6461 if (TARGET_LONG_ABS_CALL && !flag_pic)
6468 /* INSN is a function call. It may have an unconditional jump
6471 CALL_DEST is the routine we are calling. */
6474 output_millicode_call (insn, call_dest)
6478 int attr_length = get_attr_length (insn);
6479 int seq_length = dbr_sequence_length ();
6484 xoperands[0] = call_dest;
6485 xoperands[2] = gen_rtx_REG (Pmode, TARGET_64BIT ? 2 : 31);
6487 /* Handle the common case where we are sure that the branch will
6488 reach the beginning of the $CODE$ subspace. The within reach
6489 form of the $$sh_func_adrs call has a length of 28. Because
6490 it has an attribute type of multi, it never has a nonzero
6491 sequence length. The length of the $$sh_func_adrs is the same
6492 as certain out of reach PIC calls to other routines. */
6493 if (!TARGET_LONG_CALLS
6494 && ((seq_length == 0
6495 && (attr_length == 12
6496 || (attr_length == 28 && get_attr_type (insn) == TYPE_MULTI)))
6497 || (seq_length != 0 && attr_length == 8)))
6499 output_asm_insn ("{bl|b,l} %0,%2", xoperands);
6505 /* It might seem that one insn could be saved by accessing
6506 the millicode function using the linkage table. However,
6507 this doesn't work in shared libraries and other dynamically
6508 loaded objects. Using a pc-relative sequence also avoids
6509 problems related to the implicit use of the gp register. */
6510 output_asm_insn ("b,l .+8,%%r1", xoperands);
6514 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1", xoperands);
6515 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1", xoperands);
6519 xoperands[1] = gen_label_rtx ();
6520 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6521 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6522 CODE_LABEL_NUMBER (xoperands[1]));
6523 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6526 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6528 else if (TARGET_PORTABLE_RUNTIME)
6530 /* Pure portable runtime doesn't allow be/ble; we also don't
6531 have PIC support in the assembler/linker, so this sequence
6534 /* Get the address of our target into %r1. */
6535 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6536 output_asm_insn ("ldo R'%0(%%r1),%%r1", xoperands);
6538 /* Get our return address into %r31. */
6539 output_asm_insn ("{bl|b,l} .+8,%%r31", xoperands);
6540 output_asm_insn ("addi 8,%%r31,%%r31", xoperands);
6542 /* Jump to our target address in %r1. */
6543 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6547 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6549 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31", xoperands);
6551 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6555 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6556 output_asm_insn ("addi 16,%%r1,%%r31", xoperands);
6558 if (TARGET_SOM || !TARGET_GAS)
6560 /* The HP assembler can generate relocations for the
6561 difference of two symbols. GAS can do this for a
6562 millicode symbol but not an arbitrary external
6563 symbol when generating SOM output. */
6564 xoperands[1] = gen_label_rtx ();
6565 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6566 CODE_LABEL_NUMBER (xoperands[1]));
6567 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6568 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6572 output_asm_insn ("addil L'%0-$PIC_pcrel$0+8,%%r1", xoperands);
6573 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+12(%%r1),%%r1",
6577 /* Jump to our target address in %r1. */
6578 output_asm_insn ("bv %%r0(%%r1)", xoperands);
6582 if (seq_length == 0)
6583 output_asm_insn ("nop", xoperands);
6585 /* We are done if there isn't a jump in the delay slot. */
6586 if (seq_length == 0 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6589 /* This call has an unconditional jump in its delay slot. */
6590 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6592 /* See if the return address can be adjusted. Use the containing
6593 sequence insn's address. */
6594 if (INSN_ADDRESSES_SET_P ())
6596 seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6597 distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6598 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6600 if (VAL_14_BITS_P (distance))
6602 xoperands[1] = gen_label_rtx ();
6603 output_asm_insn ("ldo %0-%1(%2),%2", xoperands);
6604 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6605 CODE_LABEL_NUMBER (xoperands[1]));
6608 /* ??? This branch may not reach its target. */
6609 output_asm_insn ("nop\n\tb,n %0", xoperands);
6612 /* ??? This branch may not reach its target. */
6613 output_asm_insn ("nop\n\tb,n %0", xoperands);
6615 /* Delete the jump. */
6616 PUT_CODE (NEXT_INSN (insn), NOTE);
6617 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6618 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6623 /* Return the attribute length of the call instruction INSN. The SIBCALL
6624 flag indicates whether INSN is a regular call or a sibling call. The
6625 length must match the code generated by output_call. We include the delay
6626 slot in the returned length as it is better to over estimate the length
6627 than to under estimate it. */
6630 attr_length_call (insn, sibcall)
6634 unsigned long distance = -1;
6636 if (INSN_ADDRESSES_SET_P ())
6638 distance = (total_code_bytes + insn_current_reference_address (insn));
6639 if (distance < total_code_bytes)
6645 if (!TARGET_LONG_CALLS
6646 && ((!sibcall && distance < 7600000) || distance < 240000))
6649 return (sibcall ? 28 : 24);
6653 if (!TARGET_LONG_CALLS
6654 && ((TARGET_PA_20 && !sibcall && distance < 7600000)
6655 || distance < 240000))
6658 if (TARGET_LONG_ABS_CALL && !flag_pic)
6661 if ((TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6662 || (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6674 length += length_fp_args (insn);
6680 return (length + 32);
6682 if (!TARGET_NO_SPACE_REGS)
6688 return (length + 32);
6693 /* INSN is a function call. It may have an unconditional jump
6696 CALL_DEST is the routine we are calling. */
6699 output_call (insn, call_dest, sibcall)
6704 int delay_insn_deleted = 0;
6705 int delay_slot_filled = 0;
6706 int seq_length = dbr_sequence_length ();
6709 xoperands[0] = call_dest;
6711 /* Handle the common case where we're sure that the branch will reach
6712 the beginning of the $CODE$ subspace. */
6713 if (!TARGET_LONG_CALLS && attr_length_call (insn, sibcall) == 8)
6715 xoperands[1] = gen_rtx_REG (word_mode, sibcall ? 0 : 2);
6716 output_asm_insn ("{bl|b,l} %0,%1", xoperands);
6722 /* ??? As far as I can tell, the HP linker doesn't support the
6723 long pc-relative sequence described in the 64-bit runtime
6724 architecture. So, we use a slightly longer indirect call. */
6725 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6727 xoperands[0] = p->internal_label;
6728 xoperands[1] = gen_label_rtx ();
6730 /* If this isn't a sibcall, we put the load of %r27 into the
6731 delay slot. We can't do this in a sibcall as we don't
6732 have a second call-clobbered scratch register available. */
6734 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6737 final_scan_insn (NEXT_INSN (insn), asm_out_file,
6740 /* Now delete the delay insn. */
6741 PUT_CODE (NEXT_INSN (insn), NOTE);
6742 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6743 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6744 delay_insn_deleted = 1;
6747 output_asm_insn ("addil LT'%0,%%r27", xoperands);
6748 output_asm_insn ("ldd RT'%0(%%r1),%%r1", xoperands);
6749 output_asm_insn ("ldd 0(%%r1),%%r1", xoperands);
6753 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6754 output_asm_insn ("ldd 16(%%r1),%%r1", xoperands);
6755 output_asm_insn ("bve (%%r1)", xoperands);
6759 output_asm_insn ("ldd 16(%%r1),%%r2", xoperands);
6760 output_asm_insn ("bve,l (%%r2),%%r2", xoperands);
6761 output_asm_insn ("ldd 24(%%r1),%%r27", xoperands);
6762 delay_slot_filled = 1;
6767 int indirect_call = 0;
6769 /* Emit a long call. There are several different sequences
6770 of increasing length and complexity. In most cases,
6771 they don't allow an instruction in the delay slot. */
6772 if (!(TARGET_LONG_ABS_CALL && !flag_pic)
6773 && !(TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6774 && !(TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL))
6778 && GET_CODE (NEXT_INSN (insn)) != JUMP_INSN
6780 && (!TARGET_PA_20 || indirect_call))
6782 /* A non-jump insn in the delay slot. By definition we can
6783 emit this insn before the call (and in fact before argument
6785 final_scan_insn (NEXT_INSN (insn), asm_out_file, optimize, 0, 0);
6787 /* Now delete the delay insn. */
6788 PUT_CODE (NEXT_INSN (insn), NOTE);
6789 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6790 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6791 delay_insn_deleted = 1;
6794 if (TARGET_LONG_ABS_CALL && !flag_pic)
6796 /* This is the best sequence for making long calls in
6797 non-pic code. Unfortunately, GNU ld doesn't provide
6798 the stub needed for external calls, and GAS's support
6799 for this with the SOM linker is buggy. */
6800 output_asm_insn ("ldil L'%0,%%r1", xoperands);
6802 output_asm_insn ("be R'%0(%%sr4,%%r1)", xoperands);
6806 output_asm_insn ("be,l R'%0(%%sr4,%%r1),%%sr0,%%r31",
6809 output_asm_insn ("ble R'%0(%%sr4,%%r1)", xoperands);
6811 output_asm_insn ("copy %%r31,%%r2", xoperands);
6812 delay_slot_filled = 1;
6817 if (TARGET_SOM && TARGET_LONG_PIC_SDIFF_CALL)
6819 /* The HP assembler and linker can handle relocations
6820 for the difference of two symbols. GAS and the HP
6821 linker can't do this when one of the symbols is
6823 xoperands[1] = gen_label_rtx ();
6824 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6825 output_asm_insn ("addil L'%0-%l1,%%r1", xoperands);
6826 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6827 CODE_LABEL_NUMBER (xoperands[1]));
6828 output_asm_insn ("ldo R'%0-%l1(%%r1),%%r1", xoperands);
6830 else if (TARGET_GAS && TARGET_LONG_PIC_PCREL_CALL)
6832 /* GAS currently can't generate the relocations that
6833 are needed for the SOM linker under HP-UX using this
6834 sequence. The GNU linker doesn't generate the stubs
6835 that are needed for external calls on TARGET_ELF32
6836 with this sequence. For now, we have to use a
6837 longer plabel sequence when using GAS. */
6838 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
6839 output_asm_insn ("addil L'%0-$PIC_pcrel$0+4,%%r1",
6841 output_asm_insn ("ldo R'%0-$PIC_pcrel$0+8(%%r1),%%r1",
6846 /* Emit a long plabel-based call sequence. This is
6847 essentially an inline implementation of $$dyncall.
6848 We don't actually try to call $$dyncall as this is
6849 as difficult as calling the function itself. */
6850 struct deferred_plabel *p = get_plabel (XSTR (call_dest, 0));
6852 xoperands[0] = p->internal_label;
6853 xoperands[1] = gen_label_rtx ();
6855 /* Since the call is indirect, FP arguments in registers
6856 need to be copied to the general registers. Then, the
6857 argument relocation stub will copy them back. */
6859 copy_fp_args (insn);
6863 output_asm_insn ("addil LT'%0,%%r19", xoperands);
6864 output_asm_insn ("ldw RT'%0(%%r1),%%r1", xoperands);
6865 output_asm_insn ("ldw 0(%%r1),%%r1", xoperands);
6869 output_asm_insn ("addil LR'%0-$global$,%%r27",
6871 output_asm_insn ("ldw RR'%0-$global$(%%r1),%%r1",
6875 output_asm_insn ("bb,>=,n %%r1,30,.+16", xoperands);
6876 output_asm_insn ("depi 0,31,2,%%r1", xoperands);
6877 output_asm_insn ("ldw 4(%%sr0,%%r1),%%r19", xoperands);
6878 output_asm_insn ("ldw 0(%%sr0,%%r1),%%r1", xoperands);
6880 if (!sibcall && !TARGET_PA_20)
6882 output_asm_insn ("{bl|b,l} .+8,%%r2", xoperands);
6883 if (TARGET_NO_SPACE_REGS)
6884 output_asm_insn ("addi 8,%%r2,%%r2", xoperands);
6886 output_asm_insn ("addi 16,%%r2,%%r2", xoperands);
6893 output_asm_insn ("bve (%%r1)", xoperands);
6898 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6899 output_asm_insn ("stw %%r2,-24(%%sp)", xoperands);
6900 delay_slot_filled = 1;
6903 output_asm_insn ("bve,l (%%r1),%%r2", xoperands);
6908 if (!TARGET_NO_SPACE_REGS)
6909 output_asm_insn ("ldsid (%%r1),%%r31\n\tmtsp %%r31,%%sr0",
6914 if (TARGET_NO_SPACE_REGS)
6915 output_asm_insn ("be 0(%%sr4,%%r1)", xoperands);
6917 output_asm_insn ("be 0(%%sr0,%%r1)", xoperands);
6921 if (TARGET_NO_SPACE_REGS)
6922 output_asm_insn ("ble 0(%%sr4,%%r1)", xoperands);
6924 output_asm_insn ("ble 0(%%sr0,%%r1)", xoperands);
6927 output_asm_insn ("stw %%r31,-24(%%sp)", xoperands);
6929 output_asm_insn ("copy %%r31,%%r2", xoperands);
6930 delay_slot_filled = 1;
6937 if (seq_length == 0 || (delay_insn_deleted && !delay_slot_filled))
6938 output_asm_insn ("nop", xoperands);
6940 /* We are done if there isn't a jump in the delay slot. */
6942 || delay_insn_deleted
6943 || GET_CODE (NEXT_INSN (insn)) != JUMP_INSN)
6946 /* A sibcall should never have a branch in the delay slot. */
6950 /* This call has an unconditional jump in its delay slot. */
6951 xoperands[0] = XEXP (PATTERN (NEXT_INSN (insn)), 1);
6953 if (!delay_slot_filled && INSN_ADDRESSES_SET_P ())
6955 /* See if the return address can be adjusted. Use the containing
6956 sequence insn's address. */
6957 rtx seq_insn = NEXT_INSN (PREV_INSN (XVECEXP (final_sequence, 0, 0)));
6958 int distance = (INSN_ADDRESSES (INSN_UID (JUMP_LABEL (NEXT_INSN (insn))))
6959 - INSN_ADDRESSES (INSN_UID (seq_insn)) - 8);
6961 if (VAL_14_BITS_P (distance))
6963 xoperands[1] = gen_label_rtx ();
6964 output_asm_insn ("ldo %0-%1(%%r2),%%r2", xoperands);
6965 (*targetm.asm_out.internal_label) (asm_out_file, "L",
6966 CODE_LABEL_NUMBER (xoperands[1]));
6969 /* ??? This branch may not reach its target. */
6970 output_asm_insn ("nop\n\tb,n %0", xoperands);
6973 /* ??? This branch may not reach its target. */
6974 output_asm_insn ("b,n %0", xoperands);
6976 /* Delete the jump. */
6977 PUT_CODE (NEXT_INSN (insn), NOTE);
6978 NOTE_LINE_NUMBER (NEXT_INSN (insn)) = NOTE_INSN_DELETED;
6979 NOTE_SOURCE_FILE (NEXT_INSN (insn)) = 0;
6984 /* Return the attribute length of the indirect call instruction INSN.
6985 The length must match the code generated by output_indirect call.
6986 The returned length includes the delay slot. Currently, the delay
6987 slot of an indirect call sequence is not exposed and it is used by
6988 the sequence itself. */
6991 attr_length_indirect_call (insn)
6994 unsigned long distance = -1;
6996 if (INSN_ADDRESSES_SET_P ())
6998 distance = (total_code_bytes + insn_current_reference_address (insn));
6999 if (distance < total_code_bytes)
7006 if (TARGET_FAST_INDIRECT_CALLS
7007 || (!TARGET_PORTABLE_RUNTIME
7008 && ((TARGET_PA_20 && distance < 7600000) || distance < 240000)))
7014 if (TARGET_PORTABLE_RUNTIME)
7017 /* Out of reach, can use ble. */
7022 output_indirect_call (insn, call_dest)
7030 xoperands[0] = call_dest;
7031 output_asm_insn ("ldd 16(%0),%%r2", xoperands);
7032 output_asm_insn ("bve,l (%%r2),%%r2\n\tldd 24(%0),%%r27", xoperands);
7036 /* First the special case for kernels, level 0 systems, etc. */
7037 if (TARGET_FAST_INDIRECT_CALLS)
7038 return "ble 0(%%sr4,%%r22)\n\tcopy %%r31,%%r2";
7040 /* Now the normal case -- we can reach $$dyncall directly or
7041 we're sure that we can get there via a long-branch stub.
7043 No need to check target flags as the length uniquely identifies
7044 the remaining cases. */
7045 if (attr_length_indirect_call (insn) == 8)
7046 return ".CALL\tARGW0=GR\n\t{bl|b,l} $$dyncall,%%r31\n\tcopy %%r31,%%r2";
7048 /* Long millicode call, but we are not generating PIC or portable runtime
7050 if (attr_length_indirect_call (insn) == 12)
7051 return ".CALL\tARGW0=GR\n\tldil L'$$dyncall,%%r2\n\tble R'$$dyncall(%%sr4,%%r2)\n\tcopy %%r31,%%r2";
7053 /* Long millicode call for portable runtime. */
7054 if (attr_length_indirect_call (insn) == 20)
7055 return "ldil L'$$dyncall,%%r31\n\tldo R'$$dyncall(%%r31),%%r31\n\tblr %%r0,%%r2\n\tbv,n %%r0(%%r31)\n\tnop";
7057 /* We need a long PIC call to $$dyncall. */
7058 xoperands[0] = NULL_RTX;
7059 output_asm_insn ("{bl|b,l} .+8,%%r1", xoperands);
7060 if (TARGET_SOM || !TARGET_GAS)
7062 xoperands[0] = gen_label_rtx ();
7063 output_asm_insn ("addil L'$$dyncall-%0,%%r1", xoperands);
7064 (*targetm.asm_out.internal_label) (asm_out_file, "L",
7065 CODE_LABEL_NUMBER (xoperands[0]));
7066 output_asm_insn ("ldo R'$$dyncall-%0(%%r1),%%r1", xoperands);
7070 output_asm_insn ("addil L'$$dyncall-$PIC_pcrel$0+4,%%r1", xoperands);
7071 output_asm_insn ("ldo R'$$dyncall-$PIC_pcrel$0+8(%%r1),%%r1",
7074 output_asm_insn ("blr %%r0,%%r2", xoperands);
7075 output_asm_insn ("bv,n %%r0(%%r1)\n\tnop", xoperands);
7079 /* Return the total length of the save and restore instructions needed for
7080 the data linkage table pointer (i.e., the PIC register) across the call
7081 instruction INSN. No-return calls do not require a save and restore.
7082 In addition, we may be able to avoid the save and restore for calls
7083 within the same translation unit. */
7086 attr_length_save_restore_dltp (insn)
7089 if (find_reg_note (insn, REG_NORETURN, NULL_RTX))
7095 /* In HPUX 8.0's shared library scheme, special relocations are needed
7096 for function labels if they might be passed to a function
7097 in a shared library (because shared libraries don't live in code
7098 space), and special magic is needed to construct their address. */
7101 hppa_encode_label (sym)
7104 const char *str = XSTR (sym, 0);
7105 int len = strlen (str) + 1;
7108 p = newstr = alloca (len + 1);
7112 XSTR (sym, 0) = ggc_alloc_string (newstr, len);
7116 pa_encode_section_info (decl, rtl, first)
7121 if (first && TEXT_SPACE_P (decl))
7123 SYMBOL_REF_FLAG (XEXP (rtl, 0)) = 1;
7124 if (TREE_CODE (decl) == FUNCTION_DECL)
7125 hppa_encode_label (XEXP (rtl, 0));
7129 /* This is sort of inverse to pa_encode_section_info. */
7132 pa_strip_name_encoding (str)
7135 str += (*str == '@');
7136 str += (*str == '*');
7141 function_label_operand (op, mode)
7143 enum machine_mode mode ATTRIBUTE_UNUSED;
7145 return GET_CODE (op) == SYMBOL_REF && FUNCTION_NAME_P (XSTR (op, 0));
7148 /* Returns 1 if OP is a function label involved in a simple addition
7149 with a constant. Used to keep certain patterns from matching
7150 during instruction combination. */
7152 is_function_label_plus_const (op)
7155 /* Strip off any CONST. */
7156 if (GET_CODE (op) == CONST)
7159 return (GET_CODE (op) == PLUS
7160 && function_label_operand (XEXP (op, 0), Pmode)
7161 && GET_CODE (XEXP (op, 1)) == CONST_INT);
7164 /* Output assembly code for a thunk to FUNCTION. */
7167 pa_asm_output_mi_thunk (file, thunk_fndecl, delta, vcall_offset, function)
7170 HOST_WIDE_INT delta;
7171 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED;
7174 const char *target_name = XSTR (XEXP (DECL_RTL (function), 0), 0);
7175 static unsigned int current_thunk_number;
7178 ASM_GENERATE_INTERNAL_LABEL (label, "LTHN", current_thunk_number);
7179 lab = (*targetm.strip_name_encoding) (label);
7180 target_name = (*targetm.strip_name_encoding) (target_name);
7181 /* FIXME: total_code_bytes is not handled correctly in files with
7183 pa_output_function_prologue (file, 0);
7184 if (VAL_14_BITS_P (delta))
7186 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7188 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7189 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7190 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7191 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7192 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7193 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7194 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7195 if (TARGET_NO_SPACE_REGS)
7196 fprintf (file, "\tbe 0(%%sr4,%%r22)\n\tldo ");
7199 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7200 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7201 fprintf (file, "\tbe 0(%%sr0,%%r22)\n\tldo ");
7203 fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%%r26),%%r26\n", delta);
7206 fprintf (file, "\tb %s\n\tldo " HOST_WIDE_INT_PRINT_DEC
7208 target_name, delta);
7212 if (!TARGET_64BIT && !TARGET_PORTABLE_RUNTIME && flag_pic)
7214 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7215 ",%%r26\n\tldo R'" HOST_WIDE_INT_PRINT_DEC "(%%r1),%%r26\n",
7217 fprintf (file, "\taddil LT'%s,%%r19\n", lab);
7218 fprintf (file, "\tldw RT'%s(%%r1),%%r22\n", lab);
7219 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7220 fprintf (file, "\tbb,>=,n %%r22,30,.+16\n");
7221 fprintf (file, "\tdepi 0,31,2,%%r22\n");
7222 fprintf (file, "\tldw 4(%%sr0,%%r22),%%r19\n");
7223 fprintf (file, "\tldw 0(%%sr0,%%r22),%%r22\n");
7224 if (TARGET_NO_SPACE_REGS)
7225 fprintf (file, "\tbe 0(%%sr4,%%r22)");
7228 fprintf (file, "\tldsid (%%sr0,%%r22),%%r1\n");
7229 fprintf (file, "\tmtsp %%r1,%%sr0\n");
7230 fprintf (file, "\tbe,n 0(%%sr0,%%r22)\n");
7234 fprintf (file, "\taddil L'" HOST_WIDE_INT_PRINT_DEC
7235 ",%%r26\n\tb %s\n\tldo R'" HOST_WIDE_INT_PRINT_DEC
7236 "(%%r1),%%r26\n", delta, target_name, delta);
7239 fprintf (file, "\t.EXIT\n\t.PROCEND\n");
7240 if (! TARGET_64BIT && ! TARGET_PORTABLE_RUNTIME && flag_pic)
7243 fprintf (file, "\t.align 4\n");
7244 (*targetm.asm_out.internal_label) (file, "LTHN", current_thunk_number);
7245 fprintf (file, "\t.word P'%s\n", target_name);
7246 function_section (thunk_fndecl);
7248 current_thunk_number++;
7251 /* Only direct calls to static functions are allowed to be sibling (tail)
7254 This restriction is necessary because some linker generated stubs will
7255 store return pointers into rp' in some cases which might clobber a
7256 live value already in rp'.
7258 In a sibcall the current function and the target function share stack
7259 space. Thus if the path to the current function and the path to the
7260 target function save a value in rp', they save the value into the
7261 same stack slot, which has undesirable consequences.
7263 Because of the deferred binding nature of shared libraries any function
7264 with external scope could be in a different load module and thus require
7265 rp' to be saved when calling that function. So sibcall optimizations
7266 can only be safe for static function.
7268 Note that GCC never needs return value relocations, so we don't have to
7269 worry about static calls with return value relocations (which require
7272 It is safe to perform a sibcall optimization when the target function
7273 will never return. */
7275 pa_function_ok_for_sibcall (decl, exp)
7277 tree exp ATTRIBUTE_UNUSED;
7279 /* Sibcalls are ok for TARGET_ELF32 as along as the linker is used in
7280 single subspace mode and the call is not indirect. As far as I know,
7281 there is no operating system support for the multiple subspace mode.
7282 It might be possible to support indirect calls if we didn't use
7283 $$dyncall (see the indirect sequence generated in output_call). */
7285 return (decl != NULL_TREE);
7287 /* Sibcalls are not ok because the arg pointer register is not a fixed
7288 register. This prevents the sibcall optimization from occuring. In
7289 addition, there are problems with stub placement using GNU ld. This
7290 is because a normal sibcall branch uses a 17-bit relocation while
7291 a regular call branch uses a 22-bit relocation. As a result, more
7292 care needs to be taken in the placement of long-branch stubs. */
7297 && !TARGET_PORTABLE_RUNTIME
7298 && !TREE_PUBLIC (decl));
7301 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7302 use in fmpyadd instructions. */
7304 fmpyaddoperands (operands)
7307 enum machine_mode mode = GET_MODE (operands[0]);
7309 /* Must be a floating point mode. */
7310 if (mode != SFmode && mode != DFmode)
7313 /* All modes must be the same. */
7314 if (! (mode == GET_MODE (operands[1])
7315 && mode == GET_MODE (operands[2])
7316 && mode == GET_MODE (operands[3])
7317 && mode == GET_MODE (operands[4])
7318 && mode == GET_MODE (operands[5])))
7321 /* All operands must be registers. */
7322 if (! (GET_CODE (operands[1]) == REG
7323 && GET_CODE (operands[2]) == REG
7324 && GET_CODE (operands[3]) == REG
7325 && GET_CODE (operands[4]) == REG
7326 && GET_CODE (operands[5]) == REG))
7329 /* Only 2 real operands to the addition. One of the input operands must
7330 be the same as the output operand. */
7331 if (! rtx_equal_p (operands[3], operands[4])
7332 && ! rtx_equal_p (operands[3], operands[5]))
7335 /* Inout operand of add can not conflict with any operands from multiply. */
7336 if (rtx_equal_p (operands[3], operands[0])
7337 || rtx_equal_p (operands[3], operands[1])
7338 || rtx_equal_p (operands[3], operands[2]))
7341 /* multiply can not feed into addition operands. */
7342 if (rtx_equal_p (operands[4], operands[0])
7343 || rtx_equal_p (operands[5], operands[0]))
7346 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7348 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7349 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7350 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7351 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7352 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7353 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7356 /* Passed. Operands are suitable for fmpyadd. */
7360 #if !defined(USE_COLLECT2)
7362 pa_asm_out_constructor (symbol, priority)
7366 if (!function_label_operand (symbol, VOIDmode))
7367 hppa_encode_label (symbol);
7369 #ifdef CTORS_SECTION_ASM_OP
7370 default_ctor_section_asm_out_constructor (symbol, priority);
7372 # ifdef TARGET_ASM_NAMED_SECTION
7373 default_named_section_asm_out_constructor (symbol, priority);
7375 default_stabs_asm_out_constructor (symbol, priority);
7381 pa_asm_out_destructor (symbol, priority)
7385 if (!function_label_operand (symbol, VOIDmode))
7386 hppa_encode_label (symbol);
7388 #ifdef DTORS_SECTION_ASM_OP
7389 default_dtor_section_asm_out_destructor (symbol, priority);
7391 # ifdef TARGET_ASM_NAMED_SECTION
7392 default_named_section_asm_out_destructor (symbol, priority);
7394 default_stabs_asm_out_destructor (symbol, priority);
7400 /* Returns 1 if the 6 operands specified in OPERANDS are suitable for
7401 use in fmpysub instructions. */
7403 fmpysuboperands (operands)
7406 enum machine_mode mode = GET_MODE (operands[0]);
7408 /* Must be a floating point mode. */
7409 if (mode != SFmode && mode != DFmode)
7412 /* All modes must be the same. */
7413 if (! (mode == GET_MODE (operands[1])
7414 && mode == GET_MODE (operands[2])
7415 && mode == GET_MODE (operands[3])
7416 && mode == GET_MODE (operands[4])
7417 && mode == GET_MODE (operands[5])))
7420 /* All operands must be registers. */
7421 if (! (GET_CODE (operands[1]) == REG
7422 && GET_CODE (operands[2]) == REG
7423 && GET_CODE (operands[3]) == REG
7424 && GET_CODE (operands[4]) == REG
7425 && GET_CODE (operands[5]) == REG))
7428 /* Only 2 real operands to the subtraction. Subtraction is not a commutative
7429 operation, so operands[4] must be the same as operand[3]. */
7430 if (! rtx_equal_p (operands[3], operands[4]))
7433 /* multiply can not feed into subtraction. */
7434 if (rtx_equal_p (operands[5], operands[0]))
7437 /* Inout operand of sub can not conflict with any operands from multiply. */
7438 if (rtx_equal_p (operands[3], operands[0])
7439 || rtx_equal_p (operands[3], operands[1])
7440 || rtx_equal_p (operands[3], operands[2]))
7443 /* SFmode limits the registers to the upper 32 of the 32bit FP regs. */
7445 && (REGNO_REG_CLASS (REGNO (operands[0])) != FPUPPER_REGS
7446 || REGNO_REG_CLASS (REGNO (operands[1])) != FPUPPER_REGS
7447 || REGNO_REG_CLASS (REGNO (operands[2])) != FPUPPER_REGS
7448 || REGNO_REG_CLASS (REGNO (operands[3])) != FPUPPER_REGS
7449 || REGNO_REG_CLASS (REGNO (operands[4])) != FPUPPER_REGS
7450 || REGNO_REG_CLASS (REGNO (operands[5])) != FPUPPER_REGS))
7453 /* Passed. Operands are suitable for fmpysub. */
7458 plus_xor_ior_operator (op, mode)
7460 enum machine_mode mode ATTRIBUTE_UNUSED;
7462 return (GET_CODE (op) == PLUS || GET_CODE (op) == XOR
7463 || GET_CODE (op) == IOR);
7466 /* Return 1 if the given constant is 2, 4, or 8. These are the valid
7467 constants for shadd instructions. */
7469 shadd_constant_p (val)
7472 if (val == 2 || val == 4 || val == 8)
7478 /* Return 1 if OP is a CONST_INT with the value 2, 4, or 8. These are
7479 the valid constant for shadd instructions. */
7481 shadd_operand (op, mode)
7483 enum machine_mode mode ATTRIBUTE_UNUSED;
7485 return (GET_CODE (op) == CONST_INT && shadd_constant_p (INTVAL (op)));
7488 /* Return 1 if OP is valid as a base register in a reg + reg address. */
7491 basereg_operand (op, mode)
7493 enum machine_mode mode;
7495 /* cse will create some unscaled indexed addresses, however; it
7496 generally isn't a win on the PA, so avoid creating unscaled
7497 indexed addresses until after cse is finished. */
7498 if (!cse_not_expected)
7501 /* Allow any register when TARGET_NO_SPACE_REGS is in effect since
7502 we don't have to worry about the braindamaged implicit space
7503 register selection from the basereg. */
7504 if (TARGET_NO_SPACE_REGS)
7505 return (GET_CODE (op) == REG);
7507 /* While it's always safe to index off the frame pointer, it's not
7508 always profitable, particularly when the frame pointer is being
7510 if (! flag_omit_frame_pointer && op == frame_pointer_rtx)
7513 return (GET_CODE (op) == REG
7515 && register_operand (op, mode));
7518 /* Return 1 if this operand is anything other than a hard register. */
7521 non_hard_reg_operand (op, mode)
7523 enum machine_mode mode ATTRIBUTE_UNUSED;
7525 return ! (GET_CODE (op) == REG && REGNO (op) < FIRST_PSEUDO_REGISTER);
7528 /* Return 1 if INSN branches forward. Should be using insn_addresses
7529 to avoid walking through all the insns... */
7531 forward_branch_p (insn)
7534 rtx label = JUMP_LABEL (insn);
7541 insn = NEXT_INSN (insn);
7544 return (insn == label);
7547 /* Return 1 if OP is an equality comparison, else return 0. */
7549 eq_neq_comparison_operator (op, mode)
7551 enum machine_mode mode ATTRIBUTE_UNUSED;
7553 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
7556 /* Return 1 if OP is an operator suitable for use in a movb instruction. */
7558 movb_comparison_operator (op, mode)
7560 enum machine_mode mode ATTRIBUTE_UNUSED;
7562 return (GET_CODE (op) == EQ || GET_CODE (op) == NE
7563 || GET_CODE (op) == LT || GET_CODE (op) == GE);
7566 /* Return 1 if INSN is in the delay slot of a call instruction. */
7568 jump_in_call_delay (insn)
7572 if (GET_CODE (insn) != JUMP_INSN)
7575 if (PREV_INSN (insn)
7576 && PREV_INSN (PREV_INSN (insn))
7577 && GET_CODE (next_real_insn (PREV_INSN (PREV_INSN (insn)))) == INSN)
7579 rtx test_insn = next_real_insn (PREV_INSN (PREV_INSN (insn)));
7581 return (GET_CODE (PATTERN (test_insn)) == SEQUENCE
7582 && XVECEXP (PATTERN (test_insn), 0, 1) == insn);
7589 /* Output an unconditional move and branch insn. */
7592 output_parallel_movb (operands, length)
7596 /* These are the cases in which we win. */
7598 return "mov%I1b,tr %1,%0,%2";
7600 /* None of these cases wins, but they don't lose either. */
7601 if (dbr_sequence_length () == 0)
7603 /* Nothing in the delay slot, fake it by putting the combined
7604 insn (the copy or add) in the delay slot of a bl. */
7605 if (GET_CODE (operands[1]) == CONST_INT)
7606 return "b %2\n\tldi %1,%0";
7608 return "b %2\n\tcopy %1,%0";
7612 /* Something in the delay slot, but we've got a long branch. */
7613 if (GET_CODE (operands[1]) == CONST_INT)
7614 return "ldi %1,%0\n\tb %2";
7616 return "copy %1,%0\n\tb %2";
7620 /* Output an unconditional add and branch insn. */
7623 output_parallel_addb (operands, length)
7627 /* To make life easy we want operand0 to be the shared input/output
7628 operand and operand1 to be the readonly operand. */
7629 if (operands[0] == operands[1])
7630 operands[1] = operands[2];
7632 /* These are the cases in which we win. */
7634 return "add%I1b,tr %1,%0,%3";
7636 /* None of these cases win, but they don't lose either. */
7637 if (dbr_sequence_length () == 0)
7639 /* Nothing in the delay slot, fake it by putting the combined
7640 insn (the copy or add) in the delay slot of a bl. */
7641 return "b %3\n\tadd%I1 %1,%0,%0";
7645 /* Something in the delay slot, but we've got a long branch. */
7646 return "add%I1 %1,%0,%0\n\tb %3";
7650 /* Return nonzero if INSN (a jump insn) immediately follows a call
7651 to a named function. This is used to avoid filling the delay slot
7652 of the jump since it can usually be eliminated by modifying RP in
7653 the delay slot of the call. */
7656 following_call (insn)
7659 if (! TARGET_JUMP_IN_DELAY)
7662 /* Find the previous real insn, skipping NOTEs. */
7663 insn = PREV_INSN (insn);
7664 while (insn && GET_CODE (insn) == NOTE)
7665 insn = PREV_INSN (insn);
7667 /* Check for CALL_INSNs and millicode calls. */
7669 && ((GET_CODE (insn) == CALL_INSN
7670 && get_attr_type (insn) != TYPE_DYNCALL)
7671 || (GET_CODE (insn) == INSN
7672 && GET_CODE (PATTERN (insn)) != SEQUENCE
7673 && GET_CODE (PATTERN (insn)) != USE
7674 && GET_CODE (PATTERN (insn)) != CLOBBER
7675 && get_attr_type (insn) == TYPE_MILLI)))
7681 /* We use this hook to perform a PA specific optimization which is difficult
7682 to do in earlier passes.
7684 We want the delay slots of branches within jump tables to be filled.
7685 None of the compiler passes at the moment even has the notion that a
7686 PA jump table doesn't contain addresses, but instead contains actual
7689 Because we actually jump into the table, the addresses of each entry
7690 must stay constant in relation to the beginning of the table (which
7691 itself must stay constant relative to the instruction to jump into
7692 it). I don't believe we can guarantee earlier passes of the compiler
7693 will adhere to those rules.
7695 So, late in the compilation process we find all the jump tables, and
7696 expand them into real code -- eg each entry in the jump table vector
7697 will get an appropriate label followed by a jump to the final target.
7699 Reorg and the final jump pass can then optimize these branches and
7700 fill their delay slots. We end up with smaller, more efficient code.
7702 The jump instructions within the table are special; we must be able
7703 to identify them during assembly output (if the jumps don't get filled
7704 we need to emit a nop rather than nullifying the delay slot)). We
7705 identify jumps in switch tables by marking the SET with DImode.
7707 We also surround the jump table itself with BEGIN_BRTAB and END_BRTAB
7708 insns. This serves two purposes, first it prevents jump.c from
7709 noticing that the last N entries in the table jump to the instruction
7710 immediately after the table and deleting the jumps. Second, those
7711 insns mark where we should emit .begin_brtab and .end_brtab directives
7712 when using GAS (allows for better link time optimizations). */
7719 remove_useless_addtr_insns (1);
7721 if (pa_cpu < PROCESSOR_8000)
7722 pa_combine_instructions ();
7725 /* This is fairly cheap, so always run it if optimizing. */
7726 if (optimize > 0 && !TARGET_BIG_SWITCH)
7728 /* Find and explode all ADDR_VEC or ADDR_DIFF_VEC insns. */
7729 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7731 rtx pattern, tmp, location;
7732 unsigned int length, i;
7734 /* Find an ADDR_VEC or ADDR_DIFF_VEC insn to explode. */
7735 if (GET_CODE (insn) != JUMP_INSN
7736 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7737 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7740 /* Emit marker for the beginning of the branch table. */
7741 emit_insn_before (gen_begin_brtab (), insn);
7743 pattern = PATTERN (insn);
7744 location = PREV_INSN (insn);
7745 length = XVECLEN (pattern, GET_CODE (pattern) == ADDR_DIFF_VEC);
7747 for (i = 0; i < length; i++)
7749 /* Emit a label before each jump to keep jump.c from
7750 removing this code. */
7751 tmp = gen_label_rtx ();
7752 LABEL_NUSES (tmp) = 1;
7753 emit_label_after (tmp, location);
7754 location = NEXT_INSN (location);
7756 if (GET_CODE (pattern) == ADDR_VEC)
7758 /* Emit the jump itself. */
7759 tmp = gen_jump (XEXP (XVECEXP (pattern, 0, i), 0));
7760 tmp = emit_jump_insn_after (tmp, location);
7761 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 0, i), 0);
7762 /* It is easy to rely on the branch table markers
7763 during assembly output to trigger the correct code
7764 for a switch table jump with an unfilled delay slot,
7766 However, that requires state and assumes that we look
7769 We can't make such assumptions when computing the length
7770 of instructions. Ugh. We could walk the insn chain to
7771 determine if this instruction is in a branch table, but
7772 that can get rather expensive, particularly during the
7773 branch shortening phase of the compiler.
7775 So instead we mark this jump as being special. This is
7776 far from ideal and knows that no code after this will
7777 muck around with the mode of the JUMP_INSN itself. */
7778 PUT_MODE (tmp, SImode);
7779 LABEL_NUSES (JUMP_LABEL (tmp))++;
7780 location = NEXT_INSN (location);
7784 /* Emit the jump itself. */
7785 tmp = gen_jump (XEXP (XVECEXP (pattern, 1, i), 0));
7786 tmp = emit_jump_insn_after (tmp, location);
7787 JUMP_LABEL (tmp) = XEXP (XVECEXP (pattern, 1, i), 0);
7788 /* It is easy to rely on the branch table markers
7789 during assembly output to trigger the correct code
7790 for a switch table jump with an unfilled delay slot,
7792 However, that requires state and assumes that we look
7795 We can't make such assumptions when computing the length
7796 of instructions. Ugh. We could walk the insn chain to
7797 determine if this instruction is in a branch table, but
7798 that can get rather expensive, particularly during the
7799 branch shortening phase of the compiler.
7801 So instead we mark this jump as being special. This is
7802 far from ideal and knows that no code after this will
7803 muck around with the mode of the JUMP_INSN itself. */
7804 PUT_MODE (tmp, SImode);
7805 LABEL_NUSES (JUMP_LABEL (tmp))++;
7806 location = NEXT_INSN (location);
7809 /* Emit a BARRIER after the jump. */
7810 emit_barrier_after (location);
7811 location = NEXT_INSN (location);
7814 /* Emit marker for the end of the branch table. */
7815 emit_insn_before (gen_end_brtab (), location);
7816 location = NEXT_INSN (location);
7817 emit_barrier_after (location);
7819 /* Delete the ADDR_VEC or ADDR_DIFF_VEC. */
7825 /* Sill need an end_brtab insn. */
7826 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
7828 /* Find an ADDR_VEC insn. */
7829 if (GET_CODE (insn) != JUMP_INSN
7830 || (GET_CODE (PATTERN (insn)) != ADDR_VEC
7831 && GET_CODE (PATTERN (insn)) != ADDR_DIFF_VEC))
7834 /* Now generate markers for the beginning and end of the
7836 emit_insn_before (gen_begin_brtab (), insn);
7837 emit_insn_after (gen_end_brtab (), insn);
7842 /* The PA has a number of odd instructions which can perform multiple
7843 tasks at once. On first generation PA machines (PA1.0 and PA1.1)
7844 it may be profitable to combine two instructions into one instruction
7845 with two outputs. It's not profitable PA2.0 machines because the
7846 two outputs would take two slots in the reorder buffers.
7848 This routine finds instructions which can be combined and combines
7849 them. We only support some of the potential combinations, and we
7850 only try common ways to find suitable instructions.
7852 * addb can add two registers or a register and a small integer
7853 and jump to a nearby (+-8k) location. Normally the jump to the
7854 nearby location is conditional on the result of the add, but by
7855 using the "true" condition we can make the jump unconditional.
7856 Thus addb can perform two independent operations in one insn.
7858 * movb is similar to addb in that it can perform a reg->reg
7859 or small immediate->reg copy and jump to a nearby (+-8k location).
7861 * fmpyadd and fmpysub can perform a FP multiply and either an
7862 FP add or FP sub if the operands of the multiply and add/sub are
7863 independent (there are other minor restrictions). Note both
7864 the fmpy and fadd/fsub can in theory move to better spots according
7865 to data dependencies, but for now we require the fmpy stay at a
7868 * Many of the memory operations can perform pre & post updates
7869 of index registers. GCC's pre/post increment/decrement addressing
7870 is far too simple to take advantage of all the possibilities. This
7871 pass may not be suitable since those insns may not be independent.
7873 * comclr can compare two ints or an int and a register, nullify
7874 the following instruction and zero some other register. This
7875 is more difficult to use as it's harder to find an insn which
7876 will generate a comclr than finding something like an unconditional
7877 branch. (conditional moves & long branches create comclr insns).
7879 * Most arithmetic operations can conditionally skip the next
7880 instruction. They can be viewed as "perform this operation
7881 and conditionally jump to this nearby location" (where nearby
7882 is an insns away). These are difficult to use due to the
7883 branch length restrictions. */
7886 pa_combine_instructions ()
7890 /* This can get expensive since the basic algorithm is on the
7891 order of O(n^2) (or worse). Only do it for -O2 or higher
7892 levels of optimization. */
7896 /* Walk down the list of insns looking for "anchor" insns which
7897 may be combined with "floating" insns. As the name implies,
7898 "anchor" instructions don't move, while "floating" insns may
7900 new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
7901 new = make_insn_raw (new);
7903 for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
7905 enum attr_pa_combine_type anchor_attr;
7906 enum attr_pa_combine_type floater_attr;
7908 /* We only care about INSNs, JUMP_INSNs, and CALL_INSNs.
7909 Also ignore any special USE insns. */
7910 if ((GET_CODE (anchor) != INSN
7911 && GET_CODE (anchor) != JUMP_INSN
7912 && GET_CODE (anchor) != CALL_INSN)
7913 || GET_CODE (PATTERN (anchor)) == USE
7914 || GET_CODE (PATTERN (anchor)) == CLOBBER
7915 || GET_CODE (PATTERN (anchor)) == ADDR_VEC
7916 || GET_CODE (PATTERN (anchor)) == ADDR_DIFF_VEC)
7919 anchor_attr = get_attr_pa_combine_type (anchor);
7920 /* See if anchor is an insn suitable for combination. */
7921 if (anchor_attr == PA_COMBINE_TYPE_FMPY
7922 || anchor_attr == PA_COMBINE_TYPE_FADDSUB
7923 || (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7924 && ! forward_branch_p (anchor)))
7928 for (floater = PREV_INSN (anchor);
7930 floater = PREV_INSN (floater))
7932 if (GET_CODE (floater) == NOTE
7933 || (GET_CODE (floater) == INSN
7934 && (GET_CODE (PATTERN (floater)) == USE
7935 || GET_CODE (PATTERN (floater)) == CLOBBER)))
7938 /* Anything except a regular INSN will stop our search. */
7939 if (GET_CODE (floater) != INSN
7940 || GET_CODE (PATTERN (floater)) == ADDR_VEC
7941 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
7947 /* See if FLOATER is suitable for combination with the
7949 floater_attr = get_attr_pa_combine_type (floater);
7950 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
7951 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
7952 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
7953 && floater_attr == PA_COMBINE_TYPE_FMPY))
7955 /* If ANCHOR and FLOATER can be combined, then we're
7956 done with this pass. */
7957 if (pa_can_combine_p (new, anchor, floater, 0,
7958 SET_DEST (PATTERN (floater)),
7959 XEXP (SET_SRC (PATTERN (floater)), 0),
7960 XEXP (SET_SRC (PATTERN (floater)), 1)))
7964 else if (anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH
7965 && floater_attr == PA_COMBINE_TYPE_ADDMOVE)
7967 if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
7969 if (pa_can_combine_p (new, anchor, floater, 0,
7970 SET_DEST (PATTERN (floater)),
7971 XEXP (SET_SRC (PATTERN (floater)), 0),
7972 XEXP (SET_SRC (PATTERN (floater)), 1)))
7977 if (pa_can_combine_p (new, anchor, floater, 0,
7978 SET_DEST (PATTERN (floater)),
7979 SET_SRC (PATTERN (floater)),
7980 SET_SRC (PATTERN (floater))))
7986 /* If we didn't find anything on the backwards scan try forwards. */
7988 && (anchor_attr == PA_COMBINE_TYPE_FMPY
7989 || anchor_attr == PA_COMBINE_TYPE_FADDSUB))
7991 for (floater = anchor; floater; floater = NEXT_INSN (floater))
7993 if (GET_CODE (floater) == NOTE
7994 || (GET_CODE (floater) == INSN
7995 && (GET_CODE (PATTERN (floater)) == USE
7996 || GET_CODE (PATTERN (floater)) == CLOBBER)))
8000 /* Anything except a regular INSN will stop our search. */
8001 if (GET_CODE (floater) != INSN
8002 || GET_CODE (PATTERN (floater)) == ADDR_VEC
8003 || GET_CODE (PATTERN (floater)) == ADDR_DIFF_VEC)
8009 /* See if FLOATER is suitable for combination with the
8011 floater_attr = get_attr_pa_combine_type (floater);
8012 if ((anchor_attr == PA_COMBINE_TYPE_FMPY
8013 && floater_attr == PA_COMBINE_TYPE_FADDSUB)
8014 || (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8015 && floater_attr == PA_COMBINE_TYPE_FMPY))
8017 /* If ANCHOR and FLOATER can be combined, then we're
8018 done with this pass. */
8019 if (pa_can_combine_p (new, anchor, floater, 1,
8020 SET_DEST (PATTERN (floater)),
8021 XEXP (SET_SRC (PATTERN (floater)),
8023 XEXP (SET_SRC (PATTERN (floater)),
8030 /* FLOATER will be nonzero if we found a suitable floating
8031 insn for combination with ANCHOR. */
8033 && (anchor_attr == PA_COMBINE_TYPE_FADDSUB
8034 || anchor_attr == PA_COMBINE_TYPE_FMPY))
8036 /* Emit the new instruction and delete the old anchor. */
8037 emit_insn_before (gen_rtx_PARALLEL
8039 gen_rtvec (2, PATTERN (anchor),
8040 PATTERN (floater))),
8043 PUT_CODE (anchor, NOTE);
8044 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8045 NOTE_SOURCE_FILE (anchor) = 0;
8047 /* Emit a special USE insn for FLOATER, then delete
8048 the floating insn. */
8049 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8050 delete_insn (floater);
8055 && anchor_attr == PA_COMBINE_TYPE_UNCOND_BRANCH)
8058 /* Emit the new_jump instruction and delete the old anchor. */
8060 = emit_jump_insn_before (gen_rtx_PARALLEL
8062 gen_rtvec (2, PATTERN (anchor),
8063 PATTERN (floater))),
8066 JUMP_LABEL (temp) = JUMP_LABEL (anchor);
8067 PUT_CODE (anchor, NOTE);
8068 NOTE_LINE_NUMBER (anchor) = NOTE_INSN_DELETED;
8069 NOTE_SOURCE_FILE (anchor) = 0;
8071 /* Emit a special USE insn for FLOATER, then delete
8072 the floating insn. */
8073 emit_insn_before (gen_rtx_USE (VOIDmode, floater), floater);
8074 delete_insn (floater);
8082 pa_can_combine_p (new, anchor, floater, reversed, dest, src1, src2)
8083 rtx new, anchor, floater;
8085 rtx dest, src1, src2;
8087 int insn_code_number;
8090 /* Create a PARALLEL with the patterns of ANCHOR and
8091 FLOATER, try to recognize it, then test constraints
8092 for the resulting pattern.
8094 If the pattern doesn't match or the constraints
8095 aren't met keep searching for a suitable floater
8097 XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
8098 XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
8099 INSN_CODE (new) = -1;
8100 insn_code_number = recog_memoized (new);
8101 if (insn_code_number < 0
8102 || (extract_insn (new), ! constrain_operands (1)))
8116 /* There's up to three operands to consider. One
8117 output and two inputs.
8119 The output must not be used between FLOATER & ANCHOR
8120 exclusive. The inputs must not be set between
8121 FLOATER and ANCHOR exclusive. */
8123 if (reg_used_between_p (dest, start, end))
8126 if (reg_set_between_p (src1, start, end))
8129 if (reg_set_between_p (src2, start, end))
8132 /* If we get here, then everything is good. */
8136 /* Return nonzero if references for INSN are delayed.
8138 Millicode insns are actually function calls with some special
8139 constraints on arguments and register usage.
8141 Millicode calls always expect their arguments in the integer argument
8142 registers, and always return their result in %r29 (ret1). They
8143 are expected to clobber their arguments, %r1, %r29, and the return
8144 pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
8146 This function tells reorg that the references to arguments and
8147 millicode calls do not appear to happen until after the millicode call.
8148 This allows reorg to put insns which set the argument registers into the
8149 delay slot of the millicode call -- thus they act more like traditional
8152 Note we can not consider side effects of the insn to be delayed because
8153 the branch and link insn will clobber the return pointer. If we happened
8154 to use the return pointer in the delay slot of the call, then we lose.
8156 get_attr_type will try to recognize the given insn, so make sure to
8157 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
8160 insn_refs_are_delayed (insn)
8163 return ((GET_CODE (insn) == INSN
8164 && GET_CODE (PATTERN (insn)) != SEQUENCE
8165 && GET_CODE (PATTERN (insn)) != USE
8166 && GET_CODE (PATTERN (insn)) != CLOBBER
8167 && get_attr_type (insn) == TYPE_MILLI));
8170 /* On the HP-PA the value is found in register(s) 28(-29), unless
8171 the mode is SF or DF. Then the value is returned in fr4 (32).
8173 This must perform the same promotions as PROMOTE_MODE, else
8174 PROMOTE_FUNCTION_RETURN will not work correctly.
8176 Small structures must be returned in a PARALLEL on PA64 in order
8177 to match the HP Compiler ABI. */
8180 function_value (valtype, func)
8182 tree func ATTRIBUTE_UNUSED;
8184 enum machine_mode valmode;
8186 /* Aggregates with a size less than or equal to 128 bits are returned
8187 in GR 28(-29). They are left justified. The pad bits are undefined.
8188 Larger aggregates are returned in memory. */
8189 if (TARGET_64BIT && AGGREGATE_TYPE_P (valtype))
8193 int ub = int_size_in_bytes (valtype) <= UNITS_PER_WORD ? 1 : 2;
8195 for (i = 0; i < ub; i++)
8197 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8198 gen_rtx_REG (DImode, 28 + i),
8203 return gen_rtx_PARALLEL (BLKmode, gen_rtvec_v (ub, loc));
8206 if ((INTEGRAL_TYPE_P (valtype)
8207 && TYPE_PRECISION (valtype) < BITS_PER_WORD)
8208 || POINTER_TYPE_P (valtype))
8209 valmode = word_mode;
8211 valmode = TYPE_MODE (valtype);
8213 if (TREE_CODE (valtype) == REAL_TYPE
8214 && TYPE_MODE (valtype) != TFmode
8215 && !TARGET_SOFT_FLOAT)
8216 return gen_rtx_REG (valmode, 32);
8218 return gen_rtx_REG (valmode, 28);
8221 /* Return the location of a parameter that is passed in a register or NULL
8222 if the parameter has any component that is passed in memory.
8224 This is new code and will be pushed to into the net sources after
8227 ??? We might want to restructure this so that it looks more like other
8230 function_arg (cum, mode, type, named)
8231 CUMULATIVE_ARGS *cum;
8232 enum machine_mode mode;
8234 int named ATTRIBUTE_UNUSED;
8236 int max_arg_words = (TARGET_64BIT ? 8 : 4);
8243 if (mode == VOIDmode)
8246 arg_size = FUNCTION_ARG_SIZE (mode, type);
8248 /* If this arg would be passed partially or totally on the stack, then
8249 this routine should return zero. FUNCTION_ARG_PARTIAL_NREGS will
8250 handle arguments which are split between regs and stack slots if
8251 the ABI mandates split arguments. */
8254 /* The 32-bit ABI does not split arguments. */
8255 if (cum->words + arg_size > max_arg_words)
8261 alignment = cum->words & 1;
8262 if (cum->words + alignment >= max_arg_words)
8266 /* The 32bit ABIs and the 64bit ABIs are rather different,
8267 particularly in their handling of FP registers. We might
8268 be able to cleverly share code between them, but I'm not
8269 going to bother in the hope that splitting them up results
8270 in code that is more easily understood. */
8274 /* Advance the base registers to their current locations.
8276 Remember, gprs grow towards smaller register numbers while
8277 fprs grow to higher register numbers. Also remember that
8278 although FP regs are 32-bit addressable, we pretend that
8279 the registers are 64-bits wide. */
8280 gpr_reg_base = 26 - cum->words;
8281 fpr_reg_base = 32 + cum->words;
8283 /* Arguments wider than one word and small aggregates need special
8287 || (type && AGGREGATE_TYPE_P (type)))
8289 /* Double-extended precision (80-bit), quad-precision (128-bit)
8290 and aggregates including complex numbers are aligned on
8291 128-bit boundaries. The first eight 64-bit argument slots
8292 are associated one-to-one, with general registers r26
8293 through r19, and also with floating-point registers fr4
8294 through fr11. Arguments larger than one word are always
8295 passed in general registers.
8297 Using a PARALLEL with a word mode register results in left
8298 justified data on a big-endian target. */
8301 int i, offset = 0, ub = arg_size;
8303 /* Align the base register. */
8304 gpr_reg_base -= alignment;
8306 ub = MIN (ub, max_arg_words - cum->words - alignment);
8307 for (i = 0; i < ub; i++)
8309 loc[i] = gen_rtx_EXPR_LIST (VOIDmode,
8310 gen_rtx_REG (DImode, gpr_reg_base),
8316 return gen_rtx_PARALLEL (mode, gen_rtvec_v (ub, loc));
8321 /* If the argument is larger than a word, then we know precisely
8322 which registers we must use. */
8336 /* Structures 5 to 8 bytes in size are passed in the general
8337 registers in the same manner as other non floating-point
8338 objects. The data is right-justified and zero-extended
8341 This is magic. Normally, using a PARALLEL results in left
8342 justified data on a big-endian target. However, using a
8343 single double-word register provides the required right
8344 justication for 5 to 8 byte structures. This has nothing
8345 to do with the direction of padding specified for the argument.
8346 It has to do with how the data is widened and shifted into
8347 and from the register.
8349 Aside from adding load_multiple and store_multiple patterns,
8350 this is the only way that I have found to obtain right
8351 justification of BLKmode data when it has a size greater
8352 than one word. Splitting the operation into two SImode loads
8353 or returning a DImode REG results in left justified data. */
8354 if (mode == BLKmode)
8356 rtx loc = gen_rtx_EXPR_LIST (VOIDmode,
8357 gen_rtx_REG (DImode, gpr_reg_base),
8359 return gen_rtx_PARALLEL (mode, gen_rtvec (1, loc));
8364 /* We have a single word (32 bits). A simple computation
8365 will get us the register #s we need. */
8366 gpr_reg_base = 26 - cum->words;
8367 fpr_reg_base = 32 + 2 * cum->words;
8371 /* Determine if the argument needs to be passed in both general and
8372 floating point registers. */
8373 if (((TARGET_PORTABLE_RUNTIME || TARGET_64BIT || TARGET_ELF32)
8374 /* If we are doing soft-float with portable runtime, then there
8375 is no need to worry about FP regs. */
8376 && !TARGET_SOFT_FLOAT
8377 /* The parameter must be some kind of float, else we can just
8378 pass it in integer registers. */
8379 && FLOAT_MODE_P (mode)
8380 /* The target function must not have a prototype. */
8381 && cum->nargs_prototype <= 0
8382 /* libcalls do not need to pass items in both FP and general
8384 && type != NULL_TREE
8385 /* All this hair applies to "outgoing" args only. This includes
8386 sibcall arguments setup with FUNCTION_INCOMING_ARG. */
8388 /* Also pass outgoing floating arguments in both registers in indirect
8389 calls with the 32 bit ABI and the HP assembler since there is no
8390 way to the specify argument locations in static functions. */
8395 && FLOAT_MODE_P (mode)))
8401 gen_rtx_EXPR_LIST (VOIDmode,
8402 gen_rtx_REG (mode, fpr_reg_base),
8404 gen_rtx_EXPR_LIST (VOIDmode,
8405 gen_rtx_REG (mode, gpr_reg_base),
8410 /* See if we should pass this parameter in a general register. */
8411 if (TARGET_SOFT_FLOAT
8412 /* Indirect calls in the normal 32bit ABI require all arguments
8413 to be passed in general registers. */
8414 || (!TARGET_PORTABLE_RUNTIME
8418 /* If the parameter is not a floating point parameter, then
8419 it belongs in GPRs. */
8420 || !FLOAT_MODE_P (mode))
8421 retval = gen_rtx_REG (mode, gpr_reg_base);
8423 retval = gen_rtx_REG (mode, fpr_reg_base);
8429 /* If this arg would be passed totally in registers or totally on the stack,
8430 then this routine should return zero. It is currently called only for
8431 the 64-bit target. */
8433 function_arg_partial_nregs (cum, mode, type, named)
8434 CUMULATIVE_ARGS *cum;
8435 enum machine_mode mode;
8437 int named ATTRIBUTE_UNUSED;
8439 unsigned int max_arg_words = 8;
8440 unsigned int offset = 0;
8442 if (FUNCTION_ARG_SIZE (mode, type) > 1 && (cum->words & 1))
8445 if (cum->words + offset + FUNCTION_ARG_SIZE (mode, type) <= max_arg_words)
8446 /* Arg fits fully into registers. */
8448 else if (cum->words + offset >= max_arg_words)
8449 /* Arg fully on the stack. */
8453 return max_arg_words - cum->words - offset;
8457 /* Return 1 if this is a comparison operator. This allows the use of
8458 MATCH_OPERATOR to recognize all the branch insns. */
8461 cmpib_comparison_operator (op, mode)
8463 enum machine_mode mode;
8465 return ((mode == VOIDmode || GET_MODE (op) == mode)
8466 && (GET_CODE (op) == EQ
8467 || GET_CODE (op) == NE
8468 || GET_CODE (op) == GT
8469 || GET_CODE (op) == GTU
8470 || GET_CODE (op) == GE
8471 || GET_CODE (op) == LT
8472 || GET_CODE (op) == LE
8473 || GET_CODE (op) == LEU));
8476 /* On hpux10, the linker will give an error if we have a reference
8477 in the read-only data section to a symbol defined in a shared
8478 library. Therefore, expressions that might require a reloc can
8479 not be placed in the read-only data section. */
8482 pa_select_section (exp, reloc, align)
8485 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED;
8487 if (TREE_CODE (exp) == VAR_DECL
8488 && TREE_READONLY (exp)
8489 && !TREE_THIS_VOLATILE (exp)
8490 && DECL_INITIAL (exp)
8491 && (DECL_INITIAL (exp) == error_mark_node
8492 || TREE_CONSTANT (DECL_INITIAL (exp)))
8494 readonly_data_section ();
8495 else if (TREE_CODE_CLASS (TREE_CODE (exp)) == 'c'
8496 && !(TREE_CODE (exp) == STRING_CST && flag_writable_strings)
8498 readonly_data_section ();
8504 pa_globalize_label (stream, name)
8508 /* We only handle DATA objects here, functions are globalized in
8509 ASM_DECLARE_FUNCTION_NAME. */
8510 if (! FUNCTION_NAME_P (name))
8512 fputs ("\t.EXPORT ", stream);
8513 assemble_name (stream, name);
8514 fputs (",DATA\n", stream);