1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "conditions.h"
34 #include "insn-attr.h"
44 #include "target-def.h"
46 /* This is used by GOTaddr2picreg to uniquely identify
48 int mn10300_unspec_int_label_counter;
50 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
51 names are not prefixed by underscores, to tell whether to prefix a
52 label with a plus sign or not, so that the assembler can tell
53 symbol names from register names. */
54 int mn10300_protect_label;
56 /* The selected processor. */
57 enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
59 /* The size of the callee register save area. Right now we save everything
60 on entry since it costs us nothing in code size. It does cost us from a
61 speed standpoint, so we want to optimize this sooner or later. */
62 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
63 + 4 * df_regs_ever_live_p (3) \
64 + 4 * df_regs_ever_live_p (6) \
65 + 4 * df_regs_ever_live_p (7) \
66 + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
67 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
70 static bool mn10300_handle_option (size_t, const char *, int);
71 static int mn10300_address_cost_1 (rtx, int *);
72 static int mn10300_address_cost (rtx);
73 static bool mn10300_rtx_costs (rtx, int, int, int *);
74 static void mn10300_file_start (void);
75 static bool mn10300_return_in_memory (const_tree, const_tree);
76 static rtx mn10300_builtin_saveregs (void);
77 static void mn10300_va_start (tree, rtx);
78 static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
80 static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
83 /* Initialize the GCC target structure. */
84 #undef TARGET_ASM_ALIGNED_HI_OP
85 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
87 #undef TARGET_RTX_COSTS
88 #define TARGET_RTX_COSTS mn10300_rtx_costs
89 #undef TARGET_ADDRESS_COST
90 #define TARGET_ADDRESS_COST mn10300_address_cost
92 #undef TARGET_ASM_FILE_START
93 #define TARGET_ASM_FILE_START mn10300_file_start
94 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
95 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
97 #undef TARGET_DEFAULT_TARGET_FLAGS
98 #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
99 #undef TARGET_HANDLE_OPTION
100 #define TARGET_HANDLE_OPTION mn10300_handle_option
102 #undef TARGET_ENCODE_SECTION_INFO
103 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
105 #undef TARGET_PROMOTE_PROTOTYPES
106 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
107 #undef TARGET_RETURN_IN_MEMORY
108 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
109 #undef TARGET_PASS_BY_REFERENCE
110 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
111 #undef TARGET_CALLEE_COPIES
112 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
113 #undef TARGET_ARG_PARTIAL_BYTES
114 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
116 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
117 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
118 #undef TARGET_EXPAND_BUILTIN_VA_START
119 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
121 static void mn10300_encode_section_info (tree, rtx, int);
122 struct gcc_target targetm = TARGET_INITIALIZER;
124 /* Implement TARGET_HANDLE_OPTION. */
127 mn10300_handle_option (size_t code,
128 const char *arg ATTRIBUTE_UNUSED,
134 mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
137 mn10300_processor = (value
139 : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
146 /* Implement OVERRIDE_OPTIONS. */
149 mn10300_override_options (void)
152 target_flags &= ~MASK_MULT_BUG;
156 mn10300_file_start (void)
158 default_file_start ();
161 fprintf (asm_out_file, "\t.am33_2\n");
162 else if (TARGET_AM33)
163 fprintf (asm_out_file, "\t.am33\n");
167 /* Print operand X using operand code CODE to assembly language output file
171 print_operand (FILE *file, rtx x, int code)
177 if (cc_status.mdep.fpCC)
179 switch (code == 'b' ? GET_CODE (x)
180 : reverse_condition_maybe_unordered (GET_CODE (x)))
183 fprintf (file, "ne");
186 fprintf (file, "eq");
189 fprintf (file, "ge");
192 fprintf (file, "gt");
195 fprintf (file, "le");
198 fprintf (file, "lt");
201 fprintf (file, "lge");
204 fprintf (file, "uo");
207 fprintf (file, "lg");
210 fprintf (file, "ue");
213 fprintf (file, "uge");
216 fprintf (file, "ug");
219 fprintf (file, "ule");
222 fprintf (file, "ul");
229 /* These are normal and reversed branches. */
230 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
233 fprintf (file, "ne");
236 fprintf (file, "eq");
239 fprintf (file, "ge");
242 fprintf (file, "gt");
245 fprintf (file, "le");
248 fprintf (file, "lt");
251 fprintf (file, "cc");
254 fprintf (file, "hi");
257 fprintf (file, "ls");
260 fprintf (file, "cs");
267 /* This is used for the operand to a call instruction;
268 if it's a REG, enclose it in parens, else output
269 the operand normally. */
270 if (GET_CODE (x) == REG)
273 print_operand (file, x, 0);
277 print_operand (file, x, 0);
281 switch (GET_CODE (x))
285 output_address (XEXP (x, 0));
290 fprintf (file, "fd%d", REGNO (x) - 18);
298 /* These are the least significant word in a 64bit value. */
300 switch (GET_CODE (x))
304 output_address (XEXP (x, 0));
309 fprintf (file, "%s", reg_names[REGNO (x)]);
313 fprintf (file, "%s", reg_names[subreg_regno (x)]);
321 switch (GET_MODE (x))
324 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
325 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
326 fprintf (file, "0x%lx", val[0]);
329 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
330 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
331 fprintf (file, "0x%lx", val[0]);
335 print_operand_address (file,
336 GEN_INT (CONST_DOUBLE_LOW (x)));
347 split_double (x, &low, &high);
348 fprintf (file, "%ld", (long)INTVAL (low));
357 /* Similarly, but for the most significant word. */
359 switch (GET_CODE (x))
363 x = adjust_address (x, SImode, 4);
364 output_address (XEXP (x, 0));
369 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
373 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
381 switch (GET_MODE (x))
384 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
385 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
386 fprintf (file, "0x%lx", val[1]);
392 print_operand_address (file,
393 GEN_INT (CONST_DOUBLE_HIGH (x)));
404 split_double (x, &low, &high);
405 fprintf (file, "%ld", (long)INTVAL (high));
416 if (GET_CODE (XEXP (x, 0)) == REG)
417 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
419 output_address (XEXP (x, 0));
424 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
425 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
429 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
430 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
433 /* For shift counts. The hardware ignores the upper bits of
434 any immediate, but the assembler will flag an out of range
435 shift count as an error. So we mask off the high bits
436 of the immediate here. */
438 if (GET_CODE (x) == CONST_INT)
440 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
446 switch (GET_CODE (x))
450 output_address (XEXP (x, 0));
459 fprintf (file, "%s", reg_names[REGNO (x)]);
463 fprintf (file, "%s", reg_names[subreg_regno (x)]);
466 /* This will only be single precision.... */
472 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
473 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
474 fprintf (file, "0x%lx", val);
484 print_operand_address (file, x);
493 /* Output assembly language output for the address ADDR to FILE. */
496 print_operand_address (FILE *file, rtx addr)
498 switch (GET_CODE (addr))
501 print_operand_address (file, XEXP (addr, 0));
505 print_operand (file, addr, 0);
510 if (REG_P (XEXP (addr, 0))
511 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
512 base = XEXP (addr, 0), index = XEXP (addr, 1);
513 else if (REG_P (XEXP (addr, 1))
514 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
515 base = XEXP (addr, 1), index = XEXP (addr, 0);
518 print_operand (file, index, 0);
520 print_operand (file, base, 0);;
524 output_addr_const (file, addr);
527 output_addr_const (file, addr);
532 /* Count the number of FP registers that have to be saved. */
534 fp_regs_to_save (void)
541 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
542 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
548 /* Print a set of registers in the format required by "movm" and "ret".
549 Register K is saved if bit K of MASK is set. The data and address
550 registers can be stored individually, but the extended registers cannot.
551 We assume that the mask already takes that into account. For instance,
552 bits 14 to 17 must have the same value. */
555 mn10300_print_reg_list (FILE *file, int mask)
563 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
564 if ((mask & (1 << i)) != 0)
568 fputs (reg_names [i], file);
572 if ((mask & 0x3c000) != 0)
574 gcc_assert ((mask & 0x3c000) == 0x3c000);
577 fputs ("exreg1", file);
585 can_use_return_insn (void)
587 /* size includes the fixed stack space needed for function calls. */
588 int size = get_frame_size () + current_function_outgoing_args_size;
590 /* And space for the return pointer. */
591 size += current_function_outgoing_args_size ? 4 : 0;
593 return (reload_completed
595 && !df_regs_ever_live_p (2)
596 && !df_regs_ever_live_p (3)
597 && !df_regs_ever_live_p (6)
598 && !df_regs_ever_live_p (7)
599 && !df_regs_ever_live_p (14)
600 && !df_regs_ever_live_p (15)
601 && !df_regs_ever_live_p (16)
602 && !df_regs_ever_live_p (17)
603 && fp_regs_to_save () == 0
604 && !frame_pointer_needed);
607 /* Returns the set of live, callee-saved registers as a bitmask. The
608 callee-saved extended registers cannot be stored individually, so
609 all of them will be included in the mask if any one of them is used. */
612 mn10300_get_live_callee_saved_regs (void)
618 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
619 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
621 if ((mask & 0x3c000) != 0)
627 /* Generate an instruction that pushes several registers onto the stack.
628 Register K will be saved if bit K in MASK is set. The function does
629 nothing if MASK is zero.
631 To be compatible with the "movm" instruction, the lowest-numbered
632 register must be stored in the lowest slot. If MASK is the set
633 { R1,...,RN }, where R1...RN are ordered least first, the generated
634 instruction will have the form:
637 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
638 (set (mem:SI (plus:SI (reg:SI 9)
642 (set (mem:SI (plus:SI (reg:SI 9)
647 mn10300_gen_multiple_store (int mask)
656 /* Count how many registers need to be saved. */
658 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
659 if ((mask & (1 << i)) != 0)
662 /* We need one PARALLEL element to update the stack pointer and
663 an additional element for each register that is stored. */
664 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
666 /* Create the instruction that updates the stack pointer. */
668 = gen_rtx_SET (SImode,
670 gen_rtx_PLUS (SImode,
672 GEN_INT (-count * 4)));
674 /* Create each store. */
676 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
677 if ((mask & (1 << i)) != 0)
679 rtx address = gen_rtx_PLUS (SImode,
681 GEN_INT (-pari * 4));
682 XVECEXP(par, 0, pari)
683 = gen_rtx_SET (VOIDmode,
684 gen_rtx_MEM (SImode, address),
685 gen_rtx_REG (SImode, i));
689 par = emit_insn (par);
690 RTX_FRAME_RELATED_P (par) = 1;
695 expand_prologue (void)
699 /* SIZE includes the fixed stack space needed for function calls. */
700 size = get_frame_size () + current_function_outgoing_args_size;
701 size += (current_function_outgoing_args_size ? 4 : 0);
703 /* If we use any of the callee-saved registers, save them now. */
704 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
706 if (TARGET_AM33_2 && fp_regs_to_save ())
708 int num_regs_to_save = fp_regs_to_save (), i;
710 enum { save_sp_merge,
712 save_sp_partial_merge,
714 save_a0_no_merge } strategy;
715 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
719 /* We have several different strategies to save FP registers.
720 We can store them using SP offsets, which is beneficial if
721 there are just a few registers to save, or we can use `a0' in
722 post-increment mode (`a0' is the only call-clobbered address
723 register that is never used to pass information to a
724 function). Furthermore, if we don't need a frame pointer, we
725 can merge the two SP adds into a single one, but this isn't
726 always beneficial; sometimes we can just split the two adds
727 so that we don't exceed a 16-bit constant size. The code
728 below will select which strategy to use, so as to generate
729 smallest code. Ties are broken in favor or shorter sequences
730 (in terms of number of instructions). */
732 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
733 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
734 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
735 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
736 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
737 (((S) >= (L)) ? (SIZE1) * (N) \
738 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
739 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
741 #define SIZE_FMOV_SP_(S,N) \
742 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
743 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
744 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
745 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
747 /* Consider alternative save_sp_merge only if we don't need the
748 frame pointer and size is nonzero. */
749 if (! frame_pointer_needed && size)
751 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
752 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
753 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
754 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
756 if (this_strategy_size < strategy_size)
758 strategy = save_sp_merge;
759 strategy_size = this_strategy_size;
763 /* Consider alternative save_sp_no_merge unconditionally. */
764 /* Insn: add -4 * num_regs_to_save, sp. */
765 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
766 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
767 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
770 /* Insn: add -size, sp. */
771 this_strategy_size += SIZE_ADD_SP (-size);
774 if (this_strategy_size < strategy_size)
776 strategy = save_sp_no_merge;
777 strategy_size = this_strategy_size;
780 /* Consider alternative save_sp_partial_merge only if we don't
781 need a frame pointer and size is reasonably large. */
782 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
784 /* Insn: add -128, sp. */
785 this_strategy_size = SIZE_ADD_SP (-128);
786 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
787 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
791 /* Insn: add 128-size, sp. */
792 this_strategy_size += SIZE_ADD_SP (128 - size);
795 if (this_strategy_size < strategy_size)
797 strategy = save_sp_partial_merge;
798 strategy_size = this_strategy_size;
802 /* Consider alternative save_a0_merge only if we don't need a
803 frame pointer, size is nonzero and the user hasn't
804 changed the calling conventions of a0. */
805 if (! frame_pointer_needed && size
806 && call_used_regs[FIRST_ADDRESS_REGNUM]
807 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
809 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
810 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
811 /* Insn: mov sp, a0. */
812 this_strategy_size++;
815 /* Insn: add size, a0. */
816 this_strategy_size += SIZE_ADD_AX (size);
818 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
819 this_strategy_size += 3 * num_regs_to_save;
821 if (this_strategy_size < strategy_size)
823 strategy = save_a0_merge;
824 strategy_size = this_strategy_size;
828 /* Consider alternative save_a0_no_merge if the user hasn't
829 changed the calling conventions of a0. */
830 if (call_used_regs[FIRST_ADDRESS_REGNUM]
831 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
833 /* Insn: add -4 * num_regs_to_save, sp. */
834 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
835 /* Insn: mov sp, a0. */
836 this_strategy_size++;
837 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
838 this_strategy_size += 3 * num_regs_to_save;
841 /* Insn: add -size, sp. */
842 this_strategy_size += SIZE_ADD_SP (-size);
845 if (this_strategy_size < strategy_size)
847 strategy = save_a0_no_merge;
848 strategy_size = this_strategy_size;
852 /* Emit the initial SP add, common to all strategies. */
855 case save_sp_no_merge:
856 case save_a0_no_merge:
857 emit_insn (gen_addsi3 (stack_pointer_rtx,
859 GEN_INT (-4 * num_regs_to_save)));
863 case save_sp_partial_merge:
864 emit_insn (gen_addsi3 (stack_pointer_rtx,
867 xsize = 128 - 4 * num_regs_to_save;
873 emit_insn (gen_addsi3 (stack_pointer_rtx,
875 GEN_INT (-(size + 4 * num_regs_to_save))));
876 /* We'll have to adjust FP register saves according to the
879 /* Since we've already created the stack frame, don't do it
880 again at the end of the function. */
888 /* Now prepare register a0, if we have decided to use it. */
892 case save_sp_no_merge:
893 case save_sp_partial_merge:
898 case save_a0_no_merge:
899 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
900 emit_insn (gen_movsi (reg, stack_pointer_rtx));
902 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
903 reg = gen_rtx_POST_INC (SImode, reg);
910 /* Now actually save the FP registers. */
911 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
912 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
920 /* If we aren't using `a0', use an SP offset. */
923 addr = gen_rtx_PLUS (SImode,
928 addr = stack_pointer_rtx;
933 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
934 gen_rtx_REG (SImode, i)));
936 RTX_FRAME_RELATED_P (insn) = 1;
940 /* Now put the frame pointer into the frame pointer register. */
941 if (frame_pointer_needed)
942 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
944 /* Allocate stack for this frame. */
946 emit_insn (gen_addsi3 (stack_pointer_rtx,
949 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
950 emit_insn (gen_GOTaddr2picreg ());
954 expand_epilogue (void)
958 /* SIZE includes the fixed stack space needed for function calls. */
959 size = get_frame_size () + current_function_outgoing_args_size;
960 size += (current_function_outgoing_args_size ? 4 : 0);
962 if (TARGET_AM33_2 && fp_regs_to_save ())
964 int num_regs_to_save = fp_regs_to_save (), i;
967 /* We have several options to restore FP registers. We could
968 load them from SP offsets, but, if there are enough FP
969 registers to restore, we win if we use a post-increment
972 /* If we have a frame pointer, it's the best option, because we
973 already know it has the value we want. */
974 if (frame_pointer_needed)
975 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
976 /* Otherwise, we may use `a1', since it's call-clobbered and
977 it's never used for return values. But only do so if it's
978 smaller than using SP offsets. */
981 enum { restore_sp_post_adjust,
982 restore_sp_pre_adjust,
983 restore_sp_partial_adjust,
984 restore_a1 } strategy;
985 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
987 /* Consider using sp offsets before adjusting sp. */
988 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
989 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
990 /* If size is too large, we'll have to adjust SP with an
992 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
994 /* Insn: add size + 4 * num_regs_to_save, sp. */
995 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
997 /* If we don't have to restore any non-FP registers,
998 we'll be able to save one byte by using rets. */
999 if (! REG_SAVE_BYTES)
1000 this_strategy_size--;
1002 if (this_strategy_size < strategy_size)
1004 strategy = restore_sp_post_adjust;
1005 strategy_size = this_strategy_size;
1008 /* Consider using sp offsets after adjusting sp. */
1009 /* Insn: add size, sp. */
1010 this_strategy_size = SIZE_ADD_SP (size);
1011 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1012 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1013 /* We're going to use ret to release the FP registers
1014 save area, so, no savings. */
1016 if (this_strategy_size < strategy_size)
1018 strategy = restore_sp_pre_adjust;
1019 strategy_size = this_strategy_size;
1022 /* Consider using sp offsets after partially adjusting sp.
1023 When size is close to 32Kb, we may be able to adjust SP
1024 with an imm16 add instruction while still using fmov
1026 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1028 /* Insn: add size + 4 * num_regs_to_save
1029 + REG_SAVE_BYTES - 252,sp. */
1030 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1031 + REG_SAVE_BYTES - 252);
1032 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1033 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1034 - 4 * num_regs_to_save,
1036 /* We're going to use ret to release the FP registers
1037 save area, so, no savings. */
1039 if (this_strategy_size < strategy_size)
1041 strategy = restore_sp_partial_adjust;
1042 strategy_size = this_strategy_size;
1046 /* Consider using a1 in post-increment mode, as long as the
1047 user hasn't changed the calling conventions of a1. */
1048 if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
1049 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1051 /* Insn: mov sp,a1. */
1052 this_strategy_size = 1;
1055 /* Insn: add size,a1. */
1056 this_strategy_size += SIZE_ADD_AX (size);
1058 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1059 this_strategy_size += 3 * num_regs_to_save;
1060 /* If size is large enough, we may be able to save a
1062 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1064 /* Insn: mov a1,sp. */
1065 this_strategy_size += 2;
1067 /* If we don't have to restore any non-FP registers,
1068 we'll be able to save one byte by using rets. */
1069 if (! REG_SAVE_BYTES)
1070 this_strategy_size--;
1072 if (this_strategy_size < strategy_size)
1074 strategy = restore_a1;
1075 strategy_size = this_strategy_size;
1081 case restore_sp_post_adjust:
1084 case restore_sp_pre_adjust:
1085 emit_insn (gen_addsi3 (stack_pointer_rtx,
1091 case restore_sp_partial_adjust:
1092 emit_insn (gen_addsi3 (stack_pointer_rtx,
1094 GEN_INT (size + 4 * num_regs_to_save
1095 + REG_SAVE_BYTES - 252)));
1096 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1100 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1101 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1103 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1111 /* Adjust the selected register, if any, for post-increment. */
1113 reg = gen_rtx_POST_INC (SImode, reg);
1115 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1116 if (df_regs_ever_live_p (i) && ! call_used_regs[i])
1124 /* If we aren't using a post-increment register, use an
1126 addr = gen_rtx_PLUS (SImode,
1131 addr = stack_pointer_rtx;
1135 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1136 gen_rtx_MEM (SImode, addr)));
1139 /* If we were using the restore_a1 strategy and the number of
1140 bytes to be released won't fit in the `ret' byte, copy `a1'
1141 to `sp', to avoid having to use `add' to adjust it. */
1142 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1144 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1149 /* Maybe cut back the stack, except for the register save area.
1151 If the frame pointer exists, then use the frame pointer to
1154 If the stack size + register save area is more than 255 bytes,
1155 then the stack must be cut back here since the size + register
1156 save size is too big for a ret/retf instruction.
1158 Else leave it alone, it will be cut back as part of the
1159 ret/retf instruction, or there wasn't any stack to begin with.
1161 Under no circumstances should the register save area be
1162 deallocated here, that would leave a window where an interrupt
1163 could occur and trash the register save area. */
1164 if (frame_pointer_needed)
1166 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1169 else if (size + REG_SAVE_BYTES > 255)
1171 emit_insn (gen_addsi3 (stack_pointer_rtx,
1177 /* Adjust the stack and restore callee-saved registers, if any. */
1178 if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1179 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1180 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1181 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1182 || frame_pointer_needed)
1183 emit_jump_insn (gen_return_internal_regs
1184 (GEN_INT (size + REG_SAVE_BYTES)));
1186 emit_jump_insn (gen_return_internal ());
1189 /* Update the condition code from the insn. */
1192 notice_update_cc (rtx body, rtx insn)
1194 switch (get_attr_cc (insn))
1197 /* Insn does not affect CC at all. */
1201 /* Insn does not change CC, but the 0'th operand has been changed. */
1202 if (cc_status.value1 != 0
1203 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1204 cc_status.value1 = 0;
1208 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1209 V,C are unusable. */
1211 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1212 cc_status.value1 = recog_data.operand[0];
1216 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1219 cc_status.flags |= CC_NO_CARRY;
1220 cc_status.value1 = recog_data.operand[0];
1224 /* The insn is a compare instruction. */
1226 cc_status.value1 = SET_SRC (body);
1227 if (GET_CODE (cc_status.value1) == COMPARE
1228 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1229 cc_status.mdep.fpCC = 1;
1233 /* Insn doesn't leave CC in a usable state. */
1242 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1243 This function is for MATCH_PARALLEL and so assumes OP is known to be
1244 parallel. If OP is a multiple store, return a mask indicating which
1245 registers it saves. Return 0 otherwise. */
1248 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1256 count = XVECLEN (op, 0);
1260 /* Check that first instruction has the form (set (sp) (plus A B)) */
1261 elt = XVECEXP (op, 0, 0);
1262 if (GET_CODE (elt) != SET
1263 || GET_CODE (SET_DEST (elt)) != REG
1264 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1265 || GET_CODE (SET_SRC (elt)) != PLUS)
1268 /* Check that A is the stack pointer and B is the expected stack size.
1269 For OP to match, each subsequent instruction should push a word onto
1270 the stack. We therefore expect the first instruction to create
1271 COUNT-1 stack slots. */
1272 elt = SET_SRC (elt);
1273 if (GET_CODE (XEXP (elt, 0)) != REG
1274 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1275 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1276 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1279 /* Now go through the rest of the vector elements. They must be
1280 ordered so that the first instruction stores the highest-numbered
1281 register to the highest stack slot and that subsequent instructions
1282 store a lower-numbered register to the slot below.
1284 LAST keeps track of the smallest-numbered register stored so far.
1285 MASK is the set of stored registers. */
1286 last = LAST_EXTENDED_REGNUM + 1;
1288 for (i = 1; i < count; i++)
1290 /* Check that element i is a (set (mem M) R) and that R is valid. */
1291 elt = XVECEXP (op, 0, i);
1292 if (GET_CODE (elt) != SET
1293 || GET_CODE (SET_DEST (elt)) != MEM
1294 || GET_CODE (SET_SRC (elt)) != REG
1295 || REGNO (SET_SRC (elt)) >= last)
1298 /* R was OK, so provisionally add it to MASK. We return 0 in any
1299 case if the rest of the instruction has a flaw. */
1300 last = REGNO (SET_SRC (elt));
1301 mask |= (1 << last);
1303 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1304 elt = XEXP (SET_DEST (elt), 0);
1305 if (GET_CODE (elt) != PLUS
1306 || GET_CODE (XEXP (elt, 0)) != REG
1307 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1308 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1309 || INTVAL (XEXP (elt, 1)) != -i * 4)
1313 /* All or none of the callee-saved extended registers must be in the set. */
1314 if ((mask & 0x3c000) != 0
1315 && (mask & 0x3c000) != 0x3c000)
1321 /* What (if any) secondary registers are needed to move IN with mode
1322 MODE into a register in register class CLASS.
1324 We might be able to simplify this. */
1326 mn10300_secondary_reload_class (enum reg_class class, enum machine_mode mode,
1329 /* Memory loads less than a full word wide can't have an
1330 address or stack pointer destination. They must use
1331 a data register as an intermediate register. */
1332 if ((GET_CODE (in) == MEM
1333 || (GET_CODE (in) == REG
1334 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
1335 || (GET_CODE (in) == SUBREG
1336 && GET_CODE (SUBREG_REG (in)) == REG
1337 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
1338 && (mode == QImode || mode == HImode)
1339 && (class == ADDRESS_REGS || class == SP_REGS
1340 || class == SP_OR_ADDRESS_REGS))
1343 return DATA_OR_EXTENDED_REGS;
1347 /* We can't directly load sp + const_int into a data register;
1348 we must use an address register as an intermediate. */
1349 if (class != SP_REGS
1350 && class != ADDRESS_REGS
1351 && class != SP_OR_ADDRESS_REGS
1352 && class != SP_OR_EXTENDED_REGS
1353 && class != ADDRESS_OR_EXTENDED_REGS
1354 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1355 && (in == stack_pointer_rtx
1356 || (GET_CODE (in) == PLUS
1357 && (XEXP (in, 0) == stack_pointer_rtx
1358 || XEXP (in, 1) == stack_pointer_rtx))))
1359 return ADDRESS_REGS;
1361 if (GET_CODE (in) == PLUS
1362 && (XEXP (in, 0) == stack_pointer_rtx
1363 || XEXP (in, 1) == stack_pointer_rtx))
1366 return DATA_OR_EXTENDED_REGS;
1370 if (TARGET_AM33_2 && class == FP_REGS
1371 && GET_CODE (in) == MEM
1372 && ! (GET_CODE (in) == MEM && !CONSTANT_ADDRESS_P (XEXP (in, 0))))
1375 return DATA_OR_EXTENDED_REGS;
1379 /* Otherwise assume no secondary reloads are needed. */
1384 initial_offset (int from, int to)
1386 /* The difference between the argument pointer and the frame pointer
1387 is the size of the callee register save area. */
1388 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1390 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1391 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1392 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1393 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1394 || fp_regs_to_save ()
1395 || frame_pointer_needed)
1396 return REG_SAVE_BYTES
1397 + 4 * fp_regs_to_save ();
1402 /* The difference between the argument pointer and the stack pointer is
1403 the sum of the size of this function's frame, the callee register save
1404 area, and the fixed stack space needed for function calls (if any). */
1405 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1407 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1408 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1409 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1410 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1411 || fp_regs_to_save ()
1412 || frame_pointer_needed)
1413 return (get_frame_size () + REG_SAVE_BYTES
1414 + 4 * fp_regs_to_save ()
1415 + (current_function_outgoing_args_size
1416 ? current_function_outgoing_args_size + 4 : 0));
1418 return (get_frame_size ()
1419 + (current_function_outgoing_args_size
1420 ? current_function_outgoing_args_size + 4 : 0));
1423 /* The difference between the frame pointer and stack pointer is the sum
1424 of the size of this function's frame and the fixed stack space needed
1425 for function calls (if any). */
1426 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1427 return (get_frame_size ()
1428 + (current_function_outgoing_args_size
1429 ? current_function_outgoing_args_size + 4 : 0));
1434 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1437 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1439 /* Return values > 8 bytes in length in memory. */
1440 return (int_size_in_bytes (type) > 8
1441 || int_size_in_bytes (type) == 0
1442 || TYPE_MODE (type) == BLKmode);
1445 /* Flush the argument registers to the stack for a stdarg function;
1446 return the new argument pointer. */
1448 mn10300_builtin_saveregs (void)
1451 tree fntype = TREE_TYPE (current_function_decl);
1452 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1453 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1454 != void_type_node)))
1455 ? UNITS_PER_WORD : 0);
1456 alias_set_type set = get_varargs_alias_set ();
1459 offset = plus_constant (current_function_arg_offset_rtx, argadj);
1461 offset = current_function_arg_offset_rtx;
1463 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
1464 set_mem_alias_set (mem, set);
1465 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1467 mem = gen_rtx_MEM (SImode,
1468 plus_constant (current_function_internal_arg_pointer, 4));
1469 set_mem_alias_set (mem, set);
1470 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1472 return copy_to_reg (expand_binop (Pmode, add_optab,
1473 current_function_internal_arg_pointer,
1474 offset, 0, 0, OPTAB_LIB_WIDEN));
1478 mn10300_va_start (tree valist, rtx nextarg)
1480 nextarg = expand_builtin_saveregs ();
1481 std_expand_builtin_va_start (valist, nextarg);
1484 /* Return true when a parameter should be passed by reference. */
1487 mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1488 enum machine_mode mode, const_tree type,
1489 bool named ATTRIBUTE_UNUSED)
1491 unsigned HOST_WIDE_INT size;
1494 size = int_size_in_bytes (type);
1496 size = GET_MODE_SIZE (mode);
1498 return (size > 8 || size == 0);
1501 /* Return an RTX to represent where a value with mode MODE will be returned
1502 from a function. If the result is 0, the argument is pushed. */
1505 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1506 tree type, int named ATTRIBUTE_UNUSED)
1511 /* We only support using 2 data registers as argument registers. */
1514 /* Figure out the size of the object to be passed. */
1515 if (mode == BLKmode)
1516 size = int_size_in_bytes (type);
1518 size = GET_MODE_SIZE (mode);
1520 /* Figure out the alignment of the object to be passed. */
1523 cum->nbytes = (cum->nbytes + 3) & ~3;
1525 /* Don't pass this arg via a register if all the argument registers
1527 if (cum->nbytes > nregs * UNITS_PER_WORD)
1530 /* Don't pass this arg via a register if it would be split between
1531 registers and memory. */
1532 if (type == NULL_TREE
1533 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1536 switch (cum->nbytes / UNITS_PER_WORD)
1539 result = gen_rtx_REG (mode, 0);
1542 result = gen_rtx_REG (mode, 1);
1551 /* Return the number of bytes of registers to use for an argument passed
1552 partially in registers and partially in memory. */
1555 mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1556 tree type, bool named ATTRIBUTE_UNUSED)
1560 /* We only support using 2 data registers as argument registers. */
1563 /* Figure out the size of the object to be passed. */
1564 if (mode == BLKmode)
1565 size = int_size_in_bytes (type);
1567 size = GET_MODE_SIZE (mode);
1569 /* Figure out the alignment of the object to be passed. */
1572 cum->nbytes = (cum->nbytes + 3) & ~3;
1574 /* Don't pass this arg via a register if all the argument registers
1576 if (cum->nbytes > nregs * UNITS_PER_WORD)
1579 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1582 /* Don't pass this arg via a register if it would be split between
1583 registers and memory. */
1584 if (type == NULL_TREE
1585 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1588 return nregs * UNITS_PER_WORD - cum->nbytes;
1591 /* Return the location of the function's value. This will be either
1592 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1593 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1594 we only return the PARALLEL for outgoing values; we do not want
1595 callers relying on this extra copy. */
1598 mn10300_function_value (const_tree valtype, const_tree func, int outgoing)
1601 enum machine_mode mode = TYPE_MODE (valtype);
1603 if (! POINTER_TYPE_P (valtype))
1604 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1605 else if (! TARGET_PTR_A0D0 || ! outgoing
1606 || current_function_returns_struct)
1607 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1609 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1611 = gen_rtx_EXPR_LIST (VOIDmode,
1612 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1616 = gen_rtx_EXPR_LIST (VOIDmode,
1617 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1622 /* Output a tst insn. */
1624 output_tst (rtx operand, rtx insn)
1629 /* We can save a byte if we can find a register which has the value
1631 temp = PREV_INSN (insn);
1632 while (optimize && temp)
1636 /* We allow the search to go through call insns. We record
1637 the fact that we've past a CALL_INSN and reject matches which
1638 use call clobbered registers. */
1639 if (GET_CODE (temp) == CODE_LABEL
1640 || GET_CODE (temp) == JUMP_INSN
1641 || GET_CODE (temp) == BARRIER)
1644 if (GET_CODE (temp) == CALL_INSN)
1647 if (GET_CODE (temp) == NOTE)
1649 temp = PREV_INSN (temp);
1653 /* It must be an insn, see if it is a simple set. */
1654 set = single_set (temp);
1657 temp = PREV_INSN (temp);
1661 /* Are we setting a data register to zero (this does not win for
1664 If it's a call clobbered register, have we past a call?
1666 Make sure the register we find isn't the same as ourself;
1667 the mn10300 can't encode that.
1669 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1670 so the code to detect calls here isn't doing anything useful. */
1671 if (REG_P (SET_DEST (set))
1672 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1673 && !reg_set_between_p (SET_DEST (set), temp, insn)
1674 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1675 == REGNO_REG_CLASS (REGNO (operand)))
1676 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1677 && REGNO (SET_DEST (set)) != REGNO (operand)
1679 || !call_used_regs[REGNO (SET_DEST (set))]))
1682 xoperands[0] = operand;
1683 xoperands[1] = SET_DEST (set);
1685 output_asm_insn ("cmp %1,%0", xoperands);
1689 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1690 && REG_P (SET_DEST (set))
1691 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1692 && !reg_set_between_p (SET_DEST (set), temp, insn)
1693 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1694 != REGNO_REG_CLASS (REGNO (operand)))
1695 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1696 && REGNO (SET_DEST (set)) != REGNO (operand)
1698 || !call_used_regs[REGNO (SET_DEST (set))]))
1701 xoperands[0] = operand;
1702 xoperands[1] = SET_DEST (set);
1704 output_asm_insn ("cmp %1,%0", xoperands);
1707 temp = PREV_INSN (temp);
1713 impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1715 if (GET_CODE (op) != PLUS)
1718 if (XEXP (op, 0) == stack_pointer_rtx
1719 || XEXP (op, 1) == stack_pointer_rtx)
1725 /* Similarly, but when using a zero_extract pattern for a btst where
1726 the source operand might end up in memory. */
1728 mask_ok_for_mem_btst (int len, int bit)
1730 unsigned int mask = 0;
1739 /* MASK must bit into an 8bit value. */
1740 return (((mask & 0xff) == mask)
1741 || ((mask & 0xff00) == mask)
1742 || ((mask & 0xff0000) == mask)
1743 || ((mask & 0xff000000) == mask));
1746 /* Return 1 if X contains a symbolic expression. We know these
1747 expressions will have one of a few well defined forms, so
1748 we need only check those forms. */
1750 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1752 switch (GET_CODE (op))
1759 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1760 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1761 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1767 /* Try machine dependent ways of modifying an illegitimate address
1768 to be legitimate. If we find one, return the new valid address.
1769 This macro is used in only one place: `memory_address' in explow.c.
1771 OLDX is the address as it was before break_out_memory_refs was called.
1772 In some cases it is useful to look at this to decide what needs to be done.
1774 MODE and WIN are passed so that this macro can use
1775 GO_IF_LEGITIMATE_ADDRESS.
1777 Normally it is always safe for this macro to do nothing. It exists to
1778 recognize opportunities to optimize the output.
1780 But on a few ports with segmented architectures and indexed addressing
1781 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1783 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1784 enum machine_mode mode ATTRIBUTE_UNUSED)
1786 if (flag_pic && ! legitimate_pic_operand_p (x))
1787 x = legitimize_pic_address (oldx, NULL_RTX);
1789 /* Uh-oh. We might have an address for x[n-100000]. This needs
1790 special handling to avoid creating an indexed memory address
1791 with x-100000 as the base. */
1792 if (GET_CODE (x) == PLUS
1793 && symbolic_operand (XEXP (x, 1), VOIDmode))
1795 /* Ugly. We modify things here so that the address offset specified
1796 by the index expression is computed first, then added to x to form
1797 the entire address. */
1799 rtx regx1, regy1, regy2, y;
1801 /* Strip off any CONST. */
1803 if (GET_CODE (y) == CONST)
1806 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1808 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1809 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1810 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1811 regx1 = force_reg (Pmode,
1812 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
1813 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1819 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1820 @GOTOFF in `reg'. */
1822 legitimize_pic_address (rtx orig, rtx reg)
1824 if (GET_CODE (orig) == LABEL_REF
1825 || (GET_CODE (orig) == SYMBOL_REF
1826 && (CONSTANT_POOL_ADDRESS_P (orig)
1827 || ! MN10300_GLOBAL_P (orig))))
1830 reg = gen_reg_rtx (Pmode);
1832 emit_insn (gen_symGOTOFF2reg (reg, orig));
1835 else if (GET_CODE (orig) == SYMBOL_REF)
1838 reg = gen_reg_rtx (Pmode);
1840 emit_insn (gen_symGOT2reg (reg, orig));
1846 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1847 isn't protected by a PIC unspec; nonzero otherwise. */
1849 legitimate_pic_operand_p (rtx x)
1851 register const char *fmt;
1854 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1857 if (GET_CODE (x) == UNSPEC
1858 && (XINT (x, 1) == UNSPEC_PIC
1859 || XINT (x, 1) == UNSPEC_GOT
1860 || XINT (x, 1) == UNSPEC_GOTOFF
1861 || XINT (x, 1) == UNSPEC_PLT))
1864 fmt = GET_RTX_FORMAT (GET_CODE (x));
1865 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1871 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1872 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1875 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1882 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1883 legitimate, and FALSE otherwise. */
1885 legitimate_address_p (enum machine_mode mode, rtx x, int strict)
1887 if (CONSTANT_ADDRESS_P (x)
1888 && (! flag_pic || legitimate_pic_operand_p (x)))
1891 if (RTX_OK_FOR_BASE_P (x, strict))
1895 && GET_CODE (x) == POST_INC
1896 && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1897 && (mode == SImode || mode == SFmode || mode == HImode))
1900 if (GET_CODE (x) == PLUS)
1902 rtx base = 0, index = 0;
1904 if (REG_P (XEXP (x, 0))
1905 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1908 index = XEXP (x, 1);
1911 if (REG_P (XEXP (x, 1))
1912 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1915 index = XEXP (x, 0);
1918 if (base != 0 && index != 0)
1920 if (GET_CODE (index) == CONST_INT)
1922 if (GET_CODE (index) == CONST
1923 && GET_CODE (XEXP (index, 0)) != PLUS
1925 || legitimate_pic_operand_p (index)))
1934 mn10300_address_cost_1 (rtx x, int *unsig)
1936 switch (GET_CODE (x))
1939 switch (REGNO_REG_CLASS (REGNO (x)))
1965 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1966 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1971 return mn10300_address_cost (XEXP (x, 0));
1975 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1978 if (INTVAL (x) == 0)
1980 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1982 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1984 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
2000 mn10300_address_cost (rtx x)
2003 return mn10300_address_cost_1 (x, &s);
2007 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total)
2012 /* Zeros are extremely cheap. */
2013 if (INTVAL (x) == 0 && outer_code == SET)
2015 /* If it fits in 8 bits, then it's still relatively cheap. */
2016 else if (INT_8_BITS (INTVAL (x)))
2018 /* This is the "base" cost, includes constants where either the
2019 upper or lower 16bits are all zeros. */
2020 else if (INT_16_BITS (INTVAL (x))
2021 || (INTVAL (x) & 0xffff) == 0
2022 || (INTVAL (x) & 0xffff0000) == 0)
2031 /* These are more costly than a CONST_INT, but we can relax them,
2032 so they're less costly than a CONST_DOUBLE. */
2037 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2038 so their cost is very high. */
2042 /* ??? This probably needs more work. */
2054 /* Check whether a constant used to initialize a DImode or DFmode can
2055 use a clr instruction. The code here must be kept in sync with
2059 mn10300_wide_const_load_uses_clr (rtx operands[2])
2063 if (GET_CODE (operands[0]) != REG
2064 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2067 switch (GET_CODE (operands[1]))
2072 split_double (operands[1], &low, &high);
2073 val[0] = INTVAL (low);
2074 val[1] = INTVAL (high);
2079 if (GET_MODE (operands[1]) == DFmode)
2083 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2084 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2086 else if (GET_MODE (operands[1]) == VOIDmode
2087 || GET_MODE (operands[1]) == DImode)
2089 val[0] = CONST_DOUBLE_LOW (operands[1]);
2090 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2098 return val[0] == 0 || val[1] == 0;
2100 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2101 may access it using GOTOFF instead of GOT. */
2104 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2108 if (GET_CODE (rtl) != MEM)
2110 symbol = XEXP (rtl, 0);
2111 if (GET_CODE (symbol) != SYMBOL_REF)
2115 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);