1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* This is used by GOTaddr2picreg to uniquely identify
49 int mn10300_unspec_int_label_counter;
51 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
52 names are not prefixed by underscores, to tell whether to prefix a
53 label with a plus sign or not, so that the assembler can tell
54 symbol names from register names. */
55 int mn10300_protect_label;
57 /* The size of the callee register save area. Right now we save everything
58 on entry since it costs us nothing in code size. It does cost us from a
59 speed standpoint, so we want to optimize this sooner or later. */
60 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
61 + 4 * regs_ever_live[3] \
62 + 4 * regs_ever_live[6] \
63 + 4 * regs_ever_live[7] \
64 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
65 || regs_ever_live[16] || regs_ever_live[17]))
68 static int mn10300_address_cost_1 (rtx, int *);
69 static int mn10300_address_cost (rtx);
70 static bool mn10300_rtx_costs (rtx, int, int, int *);
71 static void mn10300_file_start (void);
72 static bool mn10300_return_in_memory (tree, tree);
73 static rtx mn10300_builtin_saveregs (void);
76 /* Initialize the GCC target structure. */
77 #undef TARGET_ASM_ALIGNED_HI_OP
78 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
80 #undef TARGET_RTX_COSTS
81 #define TARGET_RTX_COSTS mn10300_rtx_costs
82 #undef TARGET_ADDRESS_COST
83 #define TARGET_ADDRESS_COST mn10300_address_cost
85 #undef TARGET_ASM_FILE_START
86 #define TARGET_ASM_FILE_START mn10300_file_start
87 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
88 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
90 #undef TARGET_ENCODE_SECTION_INFO
91 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
93 #undef TARGET_PROMOTE_PROTOTYPES
94 #define TARGET_PROMOTE_PROTOTYPES hook_bool_tree_true
96 #undef TARGET_STRUCT_VALUE_RTX
97 #define TARGET_STRUCT_VALUE_RTX hook_rtx_tree_int_null
98 #undef TARGET_RETURN_IN_MEMORY
99 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
101 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
102 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
104 static void mn10300_encode_section_info (tree, rtx, int);
105 struct gcc_target targetm = TARGET_INITIALIZER;
108 mn10300_file_start (void)
110 default_file_start ();
113 fprintf (asm_out_file, "\t.am33_2\n");
114 else if (TARGET_AM33)
115 fprintf (asm_out_file, "\t.am33\n");
119 /* Print operand X using operand code CODE to assembly language output file
123 print_operand (FILE *file, rtx x, int code)
129 if (cc_status.mdep.fpCC)
131 switch (code == 'b' ? GET_CODE (x)
132 : reverse_condition_maybe_unordered (GET_CODE (x)))
135 fprintf (file, "ne");
138 fprintf (file, "eq");
141 fprintf (file, "ge");
144 fprintf (file, "gt");
147 fprintf (file, "le");
150 fprintf (file, "lt");
153 fprintf (file, "lge");
156 fprintf (file, "uo");
159 fprintf (file, "lg");
162 fprintf (file, "ue");
165 fprintf (file, "uge");
168 fprintf (file, "ug");
171 fprintf (file, "ule");
174 fprintf (file, "ul");
181 /* These are normal and reversed branches. */
182 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
185 fprintf (file, "ne");
188 fprintf (file, "eq");
191 fprintf (file, "ge");
194 fprintf (file, "gt");
197 fprintf (file, "le");
200 fprintf (file, "lt");
203 fprintf (file, "cc");
206 fprintf (file, "hi");
209 fprintf (file, "ls");
212 fprintf (file, "cs");
219 /* This is used for the operand to a call instruction;
220 if it's a REG, enclose it in parens, else output
221 the operand normally. */
222 if (GET_CODE (x) == REG)
225 print_operand (file, x, 0);
229 print_operand (file, x, 0);
233 switch (GET_CODE (x))
237 output_address (XEXP (x, 0));
242 fprintf (file, "fd%d", REGNO (x) - 18);
250 /* These are the least significant word in a 64bit value. */
252 switch (GET_CODE (x))
256 output_address (XEXP (x, 0));
261 fprintf (file, "%s", reg_names[REGNO (x)]);
265 fprintf (file, "%s", reg_names[subreg_regno (x)]);
273 switch (GET_MODE (x))
276 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
277 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
278 fprintf (file, "0x%lx", val[0]);
281 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
282 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
283 fprintf (file, "0x%lx", val[0]);
287 print_operand_address (file,
288 GEN_INT (CONST_DOUBLE_LOW (x)));
299 split_double (x, &low, &high);
300 fprintf (file, "%ld", (long)INTVAL (low));
309 /* Similarly, but for the most significant word. */
311 switch (GET_CODE (x))
315 x = adjust_address (x, SImode, 4);
316 output_address (XEXP (x, 0));
321 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
325 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
333 switch (GET_MODE (x))
336 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
337 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
338 fprintf (file, "0x%lx", val[1]);
344 print_operand_address (file,
345 GEN_INT (CONST_DOUBLE_HIGH (x)));
356 split_double (x, &low, &high);
357 fprintf (file, "%ld", (long)INTVAL (high));
368 if (GET_CODE (XEXP (x, 0)) == REG)
369 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
371 output_address (XEXP (x, 0));
376 if (INTVAL (x) < -128 || INTVAL (x) > 255)
378 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
382 if (INTVAL (x) < -128 || INTVAL (x) > 255)
384 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
387 /* For shift counts. The hardware ignores the upper bits of
388 any immediate, but the assembler will flag an out of range
389 shift count as an error. So we mask off the high bits
390 of the immediate here. */
392 if (GET_CODE (x) == CONST_INT)
394 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
400 switch (GET_CODE (x))
404 output_address (XEXP (x, 0));
413 fprintf (file, "%s", reg_names[REGNO (x)]);
417 fprintf (file, "%s", reg_names[subreg_regno (x)]);
420 /* This will only be single precision.... */
426 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
427 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
428 fprintf (file, "0x%lx", val);
438 print_operand_address (file, x);
447 /* Output assembly language output for the address ADDR to FILE. */
450 print_operand_address (FILE *file, rtx addr)
452 switch (GET_CODE (addr))
455 print_operand_address (file, XEXP (addr, 0));
459 print_operand (file, addr, 0);
464 if (REG_P (XEXP (addr, 0))
465 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
466 base = XEXP (addr, 0), index = XEXP (addr, 1);
467 else if (REG_P (XEXP (addr, 1))
468 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
469 base = XEXP (addr, 1), index = XEXP (addr, 0);
472 print_operand (file, index, 0);
474 print_operand (file, base, 0);;
478 output_addr_const (file, addr);
481 output_addr_const (file, addr);
486 /* Count the number of FP registers that have to be saved. */
488 fp_regs_to_save (void)
495 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
496 if (regs_ever_live[i] && ! call_used_regs[i])
502 /* Print a set of registers in the format required by "movm" and "ret".
503 Register K is saved if bit K of MASK is set. The data and address
504 registers can be stored individually, but the extended registers cannot.
505 We assume that the mask alread takes that into account. For instance,
506 bits 14 to 17 must have the same value. */
509 mn10300_print_reg_list (FILE *file, int mask)
517 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
518 if ((mask & (1 << i)) != 0)
522 fputs (reg_names [i], file);
526 if ((mask & 0x3c000) != 0)
528 if ((mask & 0x3c000) != 0x3c000)
532 fputs ("exreg1", file);
540 can_use_return_insn (void)
542 /* size includes the fixed stack space needed for function calls. */
543 int size = get_frame_size () + current_function_outgoing_args_size;
545 /* And space for the return pointer. */
546 size += current_function_outgoing_args_size ? 4 : 0;
548 return (reload_completed
550 && !regs_ever_live[2]
551 && !regs_ever_live[3]
552 && !regs_ever_live[6]
553 && !regs_ever_live[7]
554 && !regs_ever_live[14]
555 && !regs_ever_live[15]
556 && !regs_ever_live[16]
557 && !regs_ever_live[17]
558 && fp_regs_to_save () == 0
559 && !frame_pointer_needed);
562 /* Returns the set of live, callee-saved registers as a bitmask. The
563 callee-saved extended registers cannot be stored individually, so
564 all of them will be included in the mask if any one of them is used. */
567 mn10300_get_live_callee_saved_regs (void)
573 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
574 if (regs_ever_live[i] && ! call_used_regs[i])
576 if ((mask & 0x3c000) != 0)
582 /* Generate an instruction that pushes several registers onto the stack.
583 Register K will be saved if bit K in MASK is set. The function does
584 nothing if MASK is zero.
586 To be compatible with the "movm" instruction, the lowest-numbered
587 register must be stored in the lowest slot. If MASK is the set
588 { R1,...,RN }, where R1...RN are ordered least first, the generated
589 instruction will have the form:
592 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
593 (set (mem:SI (plus:SI (reg:SI 9)
597 (set (mem:SI (plus:SI (reg:SI 9)
602 mn10300_gen_multiple_store (int mask)
611 /* Count how many registers need to be saved. */
613 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
614 if ((mask & (1 << i)) != 0)
617 /* We need one PARALLEL element to update the stack pointer and
618 an additional element for each register that is stored. */
619 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
621 /* Create the instruction that updates the stack pointer. */
623 = gen_rtx_SET (SImode,
625 gen_rtx_PLUS (SImode,
627 GEN_INT (-count * 4)));
629 /* Create each store. */
631 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
632 if ((mask & (1 << i)) != 0)
634 rtx address = gen_rtx_PLUS (SImode,
636 GEN_INT (-pari * 4));
637 XVECEXP(par, 0, pari)
638 = gen_rtx_SET (VOIDmode,
639 gen_rtx_MEM (SImode, address),
640 gen_rtx_REG (SImode, i));
644 par = emit_insn (par);
645 RTX_FRAME_RELATED_P (par) = 1;
650 expand_prologue (void)
654 /* SIZE includes the fixed stack space needed for function calls. */
655 size = get_frame_size () + current_function_outgoing_args_size;
656 size += (current_function_outgoing_args_size ? 4 : 0);
658 /* If we use any of the callee-saved registers, save them now. */
659 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
661 if (TARGET_AM33_2 && fp_regs_to_save ())
663 int num_regs_to_save = fp_regs_to_save (), i;
665 enum { save_sp_merge,
667 save_sp_partial_merge,
669 save_a0_no_merge } strategy;
670 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
674 /* We have several different strategies to save FP registers.
675 We can store them using SP offsets, which is beneficial if
676 there are just a few registers to save, or we can use `a0' in
677 post-increment mode (`a0' is the only call-clobbered address
678 register that is never used to pass information to a
679 function). Furthermore, if we don't need a frame pointer, we
680 can merge the two SP adds into a single one, but this isn't
681 always beneficial; sometimes we can just split the two adds
682 so that we don't exceed a 16-bit constant size. The code
683 below will select which strategy to use, so as to generate
684 smallest code. Ties are broken in favor or shorter sequences
685 (in terms of number of instructions). */
687 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
688 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
689 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
690 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
691 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
692 (((S) >= (L)) ? (SIZE1) * (N) \
693 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
694 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
696 #define SIZE_FMOV_SP_(S,N) \
697 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
698 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
699 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
700 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
702 /* Consider alternative save_sp_merge only if we don't need the
703 frame pointer and size is nonzero. */
704 if (! frame_pointer_needed && size)
706 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
707 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
708 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
709 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
711 if (this_strategy_size < strategy_size)
713 strategy = save_sp_merge;
714 strategy_size = this_strategy_size;
718 /* Consider alternative save_sp_no_merge unconditionally. */
719 /* Insn: add -4 * num_regs_to_save, sp. */
720 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
721 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
722 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
725 /* Insn: add -size, sp. */
726 this_strategy_size += SIZE_ADD_SP (-size);
729 if (this_strategy_size < strategy_size)
731 strategy = save_sp_no_merge;
732 strategy_size = this_strategy_size;
735 /* Consider alternative save_sp_partial_merge only if we don't
736 need a frame pointer and size is reasonably large. */
737 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
739 /* Insn: add -128, sp. */
740 this_strategy_size = SIZE_ADD_SP (-128);
741 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
742 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
746 /* Insn: add 128-size, sp. */
747 this_strategy_size += SIZE_ADD_SP (128 - size);
750 if (this_strategy_size < strategy_size)
752 strategy = save_sp_partial_merge;
753 strategy_size = this_strategy_size;
757 /* Consider alternative save_a0_merge only if we don't need a
758 frame pointer, size is nonzero and the user hasn't
759 changed the calling conventions of a0. */
760 if (! frame_pointer_needed && size
761 && call_used_regs[FIRST_ADDRESS_REGNUM]
762 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
764 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
765 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
766 /* Insn: mov sp, a0. */
767 this_strategy_size++;
770 /* Insn: add size, a0. */
771 this_strategy_size += SIZE_ADD_AX (size);
773 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
774 this_strategy_size += 3 * num_regs_to_save;
776 if (this_strategy_size < strategy_size)
778 strategy = save_a0_merge;
779 strategy_size = this_strategy_size;
783 /* Consider alternative save_a0_no_merge if the user hasn't
784 changed the calling conventions of a0. */
785 if (call_used_regs[FIRST_ADDRESS_REGNUM]
786 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
788 /* Insn: add -4 * num_regs_to_save, sp. */
789 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
790 /* Insn: mov sp, a0. */
791 this_strategy_size++;
792 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
793 this_strategy_size += 3 * num_regs_to_save;
796 /* Insn: add -size, sp. */
797 this_strategy_size += SIZE_ADD_SP (-size);
800 if (this_strategy_size < strategy_size)
802 strategy = save_a0_no_merge;
803 strategy_size = this_strategy_size;
807 /* Emit the initial SP add, common to all strategies. */
810 case save_sp_no_merge:
811 case save_a0_no_merge:
812 emit_insn (gen_addsi3 (stack_pointer_rtx,
814 GEN_INT (-4 * num_regs_to_save)));
818 case save_sp_partial_merge:
819 emit_insn (gen_addsi3 (stack_pointer_rtx,
822 xsize = 128 - 4 * num_regs_to_save;
828 emit_insn (gen_addsi3 (stack_pointer_rtx,
830 GEN_INT (-(size + 4 * num_regs_to_save))));
831 /* We'll have to adjust FP register saves according to the
834 /* Since we've already created the stack frame, don't do it
835 again at the end of the function. */
843 /* Now prepare register a0, if we have decided to use it. */
847 case save_sp_no_merge:
848 case save_sp_partial_merge:
853 case save_a0_no_merge:
854 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
855 emit_insn (gen_movsi (reg, stack_pointer_rtx));
857 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
858 reg = gen_rtx_POST_INC (SImode, reg);
865 /* Now actually save the FP registers. */
866 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
867 if (regs_ever_live[i] && ! call_used_regs[i])
875 /* If we aren't using `a0', use an SP offset. */
878 addr = gen_rtx_PLUS (SImode,
883 addr = stack_pointer_rtx;
888 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
889 gen_rtx_REG (SImode, i)));
891 RTX_FRAME_RELATED_P (insn) = 1;
895 /* Now put the frame pointer into the frame pointer register. */
896 if (frame_pointer_needed)
897 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
899 /* Allocate stack for this frame. */
901 emit_insn (gen_addsi3 (stack_pointer_rtx,
904 if (flag_pic && regs_ever_live[PIC_OFFSET_TABLE_REGNUM])
906 rtx insn = get_last_insn ();
907 rtx last = emit_insn (gen_GOTaddr2picreg ());
909 /* Mark these insns as possibly dead. Sometimes, flow2 may
910 delete all uses of the PIC register. In this case, let it
911 delete the initialization too. */
914 insn = NEXT_INSN (insn);
916 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_MAYBE_DEAD,
920 while (insn != last);
925 expand_epilogue (void)
929 /* SIZE includes the fixed stack space needed for function calls. */
930 size = get_frame_size () + current_function_outgoing_args_size;
931 size += (current_function_outgoing_args_size ? 4 : 0);
933 if (TARGET_AM33_2 && fp_regs_to_save ())
935 int num_regs_to_save = fp_regs_to_save (), i;
938 /* We have several options to restore FP registers. We could
939 load them from SP offsets, but, if there are enough FP
940 registers to restore, we win if we use a post-increment
943 /* If we have a frame pointer, it's the best option, because we
944 already know it has the value we want. */
945 if (frame_pointer_needed)
946 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
947 /* Otherwise, we may use `a1', since it's call-clobbered and
948 it's never used for return values. But only do so if it's
949 smaller than using SP offsets. */
952 enum { restore_sp_post_adjust,
953 restore_sp_pre_adjust,
954 restore_sp_partial_adjust,
955 restore_a1 } strategy;
956 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
958 /* Consider using sp offsets before adjusting sp. */
959 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
960 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
961 /* If size is too large, we'll have to adjust SP with an
963 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
965 /* Insn: add size + 4 * num_regs_to_save, sp. */
966 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
968 /* If we don't have to restore any non-FP registers,
969 we'll be able to save one byte by using rets. */
970 if (! REG_SAVE_BYTES)
971 this_strategy_size--;
973 if (this_strategy_size < strategy_size)
975 strategy = restore_sp_post_adjust;
976 strategy_size = this_strategy_size;
979 /* Consider using sp offsets after adjusting sp. */
980 /* Insn: add size, sp. */
981 this_strategy_size = SIZE_ADD_SP (size);
982 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
983 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
984 /* We're going to use ret to release the FP registers
985 save area, so, no savings. */
987 if (this_strategy_size < strategy_size)
989 strategy = restore_sp_pre_adjust;
990 strategy_size = this_strategy_size;
993 /* Consider using sp offsets after partially adjusting sp.
994 When size is close to 32Kb, we may be able to adjust SP
995 with an imm16 add instruction while still using fmov
997 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
999 /* Insn: add size + 4 * num_regs_to_save
1000 + REG_SAVE_BYTES - 252,sp. */
1001 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1002 + REG_SAVE_BYTES - 252);
1003 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1004 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1005 - 4 * num_regs_to_save,
1007 /* We're going to use ret to release the FP registers
1008 save area, so, no savings. */
1010 if (this_strategy_size < strategy_size)
1012 strategy = restore_sp_partial_adjust;
1013 strategy_size = this_strategy_size;
1017 /* Consider using a1 in post-increment mode, as long as the
1018 user hasn't changed the calling conventions of a1. */
1019 if (call_used_regs[FIRST_ADDRESS_REGNUM+1]
1020 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1022 /* Insn: mov sp,a1. */
1023 this_strategy_size = 1;
1026 /* Insn: add size,a1. */
1027 this_strategy_size += SIZE_ADD_AX (size);
1029 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1030 this_strategy_size += 3 * num_regs_to_save;
1031 /* If size is large enough, we may be able to save a
1033 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1035 /* Insn: mov a1,sp. */
1036 this_strategy_size += 2;
1038 /* If we don't have to restore any non-FP registers,
1039 we'll be able to save one byte by using rets. */
1040 if (! REG_SAVE_BYTES)
1041 this_strategy_size--;
1043 if (this_strategy_size < strategy_size)
1045 strategy = restore_a1;
1046 strategy_size = this_strategy_size;
1052 case restore_sp_post_adjust:
1055 case restore_sp_pre_adjust:
1056 emit_insn (gen_addsi3 (stack_pointer_rtx,
1062 case restore_sp_partial_adjust:
1063 emit_insn (gen_addsi3 (stack_pointer_rtx,
1065 GEN_INT (size + 4 * num_regs_to_save
1066 + REG_SAVE_BYTES - 252)));
1067 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1071 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1072 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1074 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1082 /* Adjust the selected register, if any, for post-increment. */
1084 reg = gen_rtx_POST_INC (SImode, reg);
1086 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1087 if (regs_ever_live[i] && ! call_used_regs[i])
1095 /* If we aren't using a post-increment register, use an
1097 addr = gen_rtx_PLUS (SImode,
1102 addr = stack_pointer_rtx;
1106 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1107 gen_rtx_MEM (SImode, addr)));
1110 /* If we were using the restore_a1 strategy and the number of
1111 bytes to be released won't fit in the `ret' byte, copy `a1'
1112 to `sp', to avoid having to use `add' to adjust it. */
1113 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1115 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1120 /* Maybe cut back the stack, except for the register save area.
1122 If the frame pointer exists, then use the frame pointer to
1125 If the stack size + register save area is more than 255 bytes,
1126 then the stack must be cut back here since the size + register
1127 save size is too big for a ret/retf instruction.
1129 Else leave it alone, it will be cut back as part of the
1130 ret/retf instruction, or there wasn't any stack to begin with.
1132 Under no circumstances should the register save area be
1133 deallocated here, that would leave a window where an interrupt
1134 could occur and trash the register save area. */
1135 if (frame_pointer_needed)
1137 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1140 else if (size + REG_SAVE_BYTES > 255)
1142 emit_insn (gen_addsi3 (stack_pointer_rtx,
1148 /* Adjust the stack and restore callee-saved registers, if any. */
1149 if (size || regs_ever_live[2] || regs_ever_live[3]
1150 || regs_ever_live[6] || regs_ever_live[7]
1151 || regs_ever_live[14] || regs_ever_live[15]
1152 || regs_ever_live[16] || regs_ever_live[17]
1153 || frame_pointer_needed)
1154 emit_jump_insn (gen_return_internal_regs
1155 (GEN_INT (size + REG_SAVE_BYTES)));
1157 emit_jump_insn (gen_return_internal ());
1160 /* Update the condition code from the insn. */
1163 notice_update_cc (rtx body, rtx insn)
1165 switch (get_attr_cc (insn))
1168 /* Insn does not affect CC at all. */
1172 /* Insn does not change CC, but the 0'th operand has been changed. */
1173 if (cc_status.value1 != 0
1174 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1175 cc_status.value1 = 0;
1179 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1180 V,C are unusable. */
1182 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1183 cc_status.value1 = recog_data.operand[0];
1187 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1190 cc_status.flags |= CC_NO_CARRY;
1191 cc_status.value1 = recog_data.operand[0];
1195 /* The insn is a compare instruction. */
1197 cc_status.value1 = SET_SRC (body);
1198 if (GET_CODE (cc_status.value1) == COMPARE
1199 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1200 cc_status.mdep.fpCC = 1;
1204 /* The insn is a compare instruction. */
1206 cc_status.value1 = SET_SRC (body);
1207 cc_status.flags |= CC_INVERTED;
1211 /* Insn doesn't leave CC in a usable state. */
1220 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1221 This function is for MATCH_PARALLEL and so assumes OP is known to be
1222 parallel. If OP is a multiple store, return a mask indicating which
1223 registers it saves. Return 0 otherwise. */
1226 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1234 count = XVECLEN (op, 0);
1238 /* Check that first instruction has the form (set (sp) (plus A B)) */
1239 elt = XVECEXP (op, 0, 0);
1240 if (GET_CODE (elt) != SET
1241 || GET_CODE (SET_DEST (elt)) != REG
1242 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1243 || GET_CODE (SET_SRC (elt)) != PLUS)
1246 /* Check that A is the stack pointer and B is the expected stack size.
1247 For OP to match, each subsequent instruction should push a word onto
1248 the stack. We therefore expect the first instruction to create
1249 COUNT-1 stack slots. */
1250 elt = SET_SRC (elt);
1251 if (GET_CODE (XEXP (elt, 0)) != REG
1252 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1253 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1254 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1257 /* Now go through the rest of the vector elements. They must be
1258 ordered so that the first instruction stores the highest-numbered
1259 register to the highest stack slot and that subsequent instructions
1260 store a lower-numbered register to the slot below.
1262 LAST keeps track of the smallest-numbered register stored so far.
1263 MASK is the set of stored registers. */
1264 last = LAST_EXTENDED_REGNUM + 1;
1266 for (i = 1; i < count; i++)
1268 /* Check that element i is a (set (mem M) R) and that R is valid. */
1269 elt = XVECEXP (op, 0, i);
1270 if (GET_CODE (elt) != SET
1271 || GET_CODE (SET_DEST (elt)) != MEM
1272 || GET_CODE (SET_SRC (elt)) != REG
1273 || REGNO (SET_SRC (elt)) >= last)
1276 /* R was OK, so provisionally add it to MASK. We return 0 in any
1277 case if the rest of the instruction has a flaw. */
1278 last = REGNO (SET_SRC (elt));
1279 mask |= (1 << last);
1281 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1282 elt = XEXP (SET_DEST (elt), 0);
1283 if (GET_CODE (elt) != PLUS
1284 || GET_CODE (XEXP (elt, 0)) != REG
1285 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1286 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1287 || INTVAL (XEXP (elt, 1)) != -i * 4)
1291 /* All or none of the callee-saved extended registers must be in the set. */
1292 if ((mask & 0x3c000) != 0
1293 && (mask & 0x3c000) != 0x3c000)
1299 /* Return true if OP is a valid call operand. */
1302 call_address_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1305 return (EXTRA_CONSTRAINT (op, 'S') || GET_CODE (op) == REG);
1307 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
1310 /* What (if any) secondary registers are needed to move IN with mode
1311 MODE into a register in register class CLASS.
1313 We might be able to simplify this. */
1315 secondary_reload_class (enum reg_class class, enum machine_mode mode, rtx in)
1317 /* Memory loads less than a full word wide can't have an
1318 address or stack pointer destination. They must use
1319 a data register as an intermediate register. */
1320 if ((GET_CODE (in) == MEM
1321 || (GET_CODE (in) == REG
1322 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
1323 || (GET_CODE (in) == SUBREG
1324 && GET_CODE (SUBREG_REG (in)) == REG
1325 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
1326 && (mode == QImode || mode == HImode)
1327 && (class == ADDRESS_REGS || class == SP_REGS
1328 || class == SP_OR_ADDRESS_REGS))
1331 return DATA_OR_EXTENDED_REGS;
1335 /* We can't directly load sp + const_int into a data register;
1336 we must use an address register as an intermediate. */
1337 if (class != SP_REGS
1338 && class != ADDRESS_REGS
1339 && class != SP_OR_ADDRESS_REGS
1340 && class != SP_OR_EXTENDED_REGS
1341 && class != ADDRESS_OR_EXTENDED_REGS
1342 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
1343 && (in == stack_pointer_rtx
1344 || (GET_CODE (in) == PLUS
1345 && (XEXP (in, 0) == stack_pointer_rtx
1346 || XEXP (in, 1) == stack_pointer_rtx))))
1347 return ADDRESS_REGS;
1349 if (GET_CODE (in) == PLUS
1350 && (XEXP (in, 0) == stack_pointer_rtx
1351 || XEXP (in, 1) == stack_pointer_rtx))
1354 return DATA_OR_EXTENDED_REGS;
1358 if (TARGET_AM33_2 && class == FP_REGS
1359 && GET_CODE (in) == MEM && ! OK_FOR_Q (in))
1362 return DATA_OR_EXTENDED_REGS;
1366 /* Otherwise assume no secondary reloads are needed. */
1371 initial_offset (int from, int to)
1373 /* The difference between the argument pointer and the frame pointer
1374 is the size of the callee register save area. */
1375 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1377 if (regs_ever_live[2] || regs_ever_live[3]
1378 || regs_ever_live[6] || regs_ever_live[7]
1379 || regs_ever_live[14] || regs_ever_live[15]
1380 || regs_ever_live[16] || regs_ever_live[17]
1381 || fp_regs_to_save ()
1382 || frame_pointer_needed)
1383 return REG_SAVE_BYTES
1384 + 4 * fp_regs_to_save ();
1389 /* The difference between the argument pointer and the stack pointer is
1390 the sum of the size of this function's frame, the callee register save
1391 area, and the fixed stack space needed for function calls (if any). */
1392 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1394 if (regs_ever_live[2] || regs_ever_live[3]
1395 || regs_ever_live[6] || regs_ever_live[7]
1396 || regs_ever_live[14] || regs_ever_live[15]
1397 || regs_ever_live[16] || regs_ever_live[17]
1398 || fp_regs_to_save ()
1399 || frame_pointer_needed)
1400 return (get_frame_size () + REG_SAVE_BYTES
1401 + 4 * fp_regs_to_save ()
1402 + (current_function_outgoing_args_size
1403 ? current_function_outgoing_args_size + 4 : 0));
1405 return (get_frame_size ()
1406 + (current_function_outgoing_args_size
1407 ? current_function_outgoing_args_size + 4 : 0));
1410 /* The difference between the frame pointer and stack pointer is the sum
1411 of the size of this function's frame and the fixed stack space needed
1412 for function calls (if any). */
1413 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1414 return (get_frame_size ()
1415 + (current_function_outgoing_args_size
1416 ? current_function_outgoing_args_size + 4 : 0));
1421 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1424 mn10300_return_in_memory (tree type, tree fntype ATTRIBUTE_UNUSED)
1426 /* Return values > 8 bytes in length in memory. */
1427 return int_size_in_bytes (type) > 8 || TYPE_MODE (type) == BLKmode;
1430 /* Flush the argument registers to the stack for a stdarg function;
1431 return the new argument pointer. */
1433 mn10300_builtin_saveregs (void)
1436 tree fntype = TREE_TYPE (current_function_decl);
1437 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1438 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1439 != void_type_node)))
1440 ? UNITS_PER_WORD : 0);
1441 int set = get_varargs_alias_set ();
1444 offset = plus_constant (current_function_arg_offset_rtx, argadj);
1446 offset = current_function_arg_offset_rtx;
1448 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
1449 set_mem_alias_set (mem, set);
1450 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1452 mem = gen_rtx_MEM (SImode,
1453 plus_constant (current_function_internal_arg_pointer, 4));
1454 set_mem_alias_set (mem, set);
1455 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1457 return copy_to_reg (expand_binop (Pmode, add_optab,
1458 current_function_internal_arg_pointer,
1459 offset, 0, 0, OPTAB_LIB_WIDEN));
1463 mn10300_va_start (tree valist, rtx nextarg)
1465 nextarg = expand_builtin_saveregs ();
1466 std_expand_builtin_va_start (valist, nextarg);
1470 mn10300_va_arg (tree valist, tree type)
1472 HOST_WIDE_INT align, rsize;
1475 /* Compute the rounded size of the type. */
1476 align = PARM_BOUNDARY / BITS_PER_UNIT;
1477 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
1479 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
1480 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
1481 TREE_SIDE_EFFECTS (t) = 1;
1483 ptr = build_pointer_type (type);
1485 /* "Large" types are passed by reference. */
1488 pptr = build_pointer_type (ptr);
1489 t = build1 (NOP_EXPR, pptr, t);
1490 TREE_SIDE_EFFECTS (t) = 1;
1492 t = build1 (INDIRECT_REF, ptr, t);
1493 TREE_SIDE_EFFECTS (t) = 1;
1497 t = build1 (NOP_EXPR, ptr, t);
1498 TREE_SIDE_EFFECTS (t) = 1;
1502 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
1505 /* Return an RTX to represent where a value with mode MODE will be returned
1506 from a function. If the result is 0, the argument is pushed. */
1509 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1510 tree type, int named ATTRIBUTE_UNUSED)
1515 /* We only support using 2 data registers as argument registers. */
1518 /* Figure out the size of the object to be passed. */
1519 if (mode == BLKmode)
1520 size = int_size_in_bytes (type);
1522 size = GET_MODE_SIZE (mode);
1524 /* Figure out the alignment of the object to be passed. */
1527 cum->nbytes = (cum->nbytes + 3) & ~3;
1529 /* Don't pass this arg via a register if all the argument registers
1531 if (cum->nbytes > nregs * UNITS_PER_WORD)
1534 /* Don't pass this arg via a register if it would be split between
1535 registers and memory. */
1536 if (type == NULL_TREE
1537 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1540 switch (cum->nbytes / UNITS_PER_WORD)
1543 result = gen_rtx_REG (mode, 0);
1546 result = gen_rtx_REG (mode, 1);
1555 /* Return the number of registers to use for an argument passed partially
1556 in registers and partially in memory. */
1559 function_arg_partial_nregs (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1560 tree type, int named ATTRIBUTE_UNUSED)
1564 /* We only support using 2 data registers as argument registers. */
1567 /* Figure out the size of the object to be passed. */
1568 if (mode == BLKmode)
1569 size = int_size_in_bytes (type);
1571 size = GET_MODE_SIZE (mode);
1573 /* Figure out the alignment of the object to be passed. */
1576 cum->nbytes = (cum->nbytes + 3) & ~3;
1578 /* Don't pass this arg via a register if all the argument registers
1580 if (cum->nbytes > nregs * UNITS_PER_WORD)
1583 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1586 /* Don't pass this arg via a register if it would be split between
1587 registers and memory. */
1588 if (type == NULL_TREE
1589 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1592 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1595 /* Output a tst insn. */
1597 output_tst (rtx operand, rtx insn)
1602 /* We can save a byte if we can find a register which has the value
1604 temp = PREV_INSN (insn);
1605 while (optimize && temp)
1609 /* We allow the search to go through call insns. We record
1610 the fact that we've past a CALL_INSN and reject matches which
1611 use call clobbered registers. */
1612 if (GET_CODE (temp) == CODE_LABEL
1613 || GET_CODE (temp) == JUMP_INSN
1614 || GET_CODE (temp) == BARRIER)
1617 if (GET_CODE (temp) == CALL_INSN)
1620 if (GET_CODE (temp) == NOTE)
1622 temp = PREV_INSN (temp);
1626 /* It must be an insn, see if it is a simple set. */
1627 set = single_set (temp);
1630 temp = PREV_INSN (temp);
1634 /* Are we setting a data register to zero (this does not win for
1637 If it's a call clobbered register, have we past a call?
1639 Make sure the register we find isn't the same as ourself;
1640 the mn10300 can't encode that.
1642 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1643 so the code to detect calls here isn't doing anything useful. */
1644 if (REG_P (SET_DEST (set))
1645 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1646 && !reg_set_between_p (SET_DEST (set), temp, insn)
1647 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1648 == REGNO_REG_CLASS (REGNO (operand)))
1649 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1650 && REGNO (SET_DEST (set)) != REGNO (operand)
1652 || !call_used_regs[REGNO (SET_DEST (set))]))
1655 xoperands[0] = operand;
1656 xoperands[1] = SET_DEST (set);
1658 output_asm_insn ("cmp %1,%0", xoperands);
1662 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1663 && REG_P (SET_DEST (set))
1664 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1665 && !reg_set_between_p (SET_DEST (set), temp, insn)
1666 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1667 != REGNO_REG_CLASS (REGNO (operand)))
1668 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1669 && REGNO (SET_DEST (set)) != REGNO (operand)
1671 || !call_used_regs[REGNO (SET_DEST (set))]))
1674 xoperands[0] = operand;
1675 xoperands[1] = SET_DEST (set);
1677 output_asm_insn ("cmp %1,%0", xoperands);
1680 temp = PREV_INSN (temp);
1686 impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1688 if (GET_CODE (op) != PLUS)
1691 if (XEXP (op, 0) == stack_pointer_rtx
1692 || XEXP (op, 1) == stack_pointer_rtx)
1698 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1699 for the btst insn which may examine memory or a register (the memory
1700 variant only allows an unsigned 8 bit integer). */
1702 const_8bit_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1704 return (GET_CODE (op) == CONST_INT
1706 && INTVAL (op) < 256);
1709 /* Return true if the operand is the 1.0f constant. */
1711 const_1f_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1713 return (op == CONST1_RTX (SFmode));
1716 /* Similarly, but when using a zero_extract pattern for a btst where
1717 the source operand might end up in memory. */
1719 mask_ok_for_mem_btst (int len, int bit)
1721 unsigned int mask = 0;
1730 /* MASK must bit into an 8bit value. */
1731 return (((mask & 0xff) == mask)
1732 || ((mask & 0xff00) == mask)
1733 || ((mask & 0xff0000) == mask)
1734 || ((mask & 0xff000000) == mask));
1737 /* Return 1 if X contains a symbolic expression. We know these
1738 expressions will have one of a few well defined forms, so
1739 we need only check those forms. */
1741 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1743 switch (GET_CODE (op))
1750 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1751 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1752 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1758 /* Try machine dependent ways of modifying an illegitimate address
1759 to be legitimate. If we find one, return the new valid address.
1760 This macro is used in only one place: `memory_address' in explow.c.
1762 OLDX is the address as it was before break_out_memory_refs was called.
1763 In some cases it is useful to look at this to decide what needs to be done.
1765 MODE and WIN are passed so that this macro can use
1766 GO_IF_LEGITIMATE_ADDRESS.
1768 Normally it is always safe for this macro to do nothing. It exists to
1769 recognize opportunities to optimize the output.
1771 But on a few ports with segmented architectures and indexed addressing
1772 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1774 legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1775 enum machine_mode mode ATTRIBUTE_UNUSED)
1777 if (flag_pic && ! legitimate_pic_operand_p (x))
1778 x = legitimize_pic_address (oldx, NULL_RTX);
1780 /* Uh-oh. We might have an address for x[n-100000]. This needs
1781 special handling to avoid creating an indexed memory address
1782 with x-100000 as the base. */
1783 if (GET_CODE (x) == PLUS
1784 && symbolic_operand (XEXP (x, 1), VOIDmode))
1786 /* Ugly. We modify things here so that the address offset specified
1787 by the index expression is computed first, then added to x to form
1788 the entire address. */
1790 rtx regx1, regy1, regy2, y;
1792 /* Strip off any CONST. */
1794 if (GET_CODE (y) == CONST)
1797 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1799 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1800 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1801 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1802 regx1 = force_reg (Pmode,
1803 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1804 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1810 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1811 @GOTOFF in `reg'. */
1813 legitimize_pic_address (rtx orig, rtx reg)
1815 if (GET_CODE (orig) == LABEL_REF
1816 || (GET_CODE (orig) == SYMBOL_REF
1817 && (CONSTANT_POOL_ADDRESS_P (orig)
1818 || ! MN10300_GLOBAL_P (orig))))
1821 reg = gen_reg_rtx (Pmode);
1823 emit_insn (gen_symGOTOFF2reg (reg, orig));
1826 else if (GET_CODE (orig) == SYMBOL_REF)
1829 reg = gen_reg_rtx (Pmode);
1831 emit_insn (gen_symGOT2reg (reg, orig));
1837 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1838 isn't protected by a PIC unspec; nonzero otherwise. */
1840 legitimate_pic_operand_p (rtx x)
1842 register const char *fmt;
1845 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1848 if (GET_CODE (x) == UNSPEC
1849 && (XINT (x, 1) == UNSPEC_PIC
1850 || XINT (x, 1) == UNSPEC_GOT
1851 || XINT (x, 1) == UNSPEC_GOTOFF
1852 || XINT (x, 1) == UNSPEC_PLT))
1855 if (GET_CODE (x) == QUEUED)
1856 return legitimate_pic_operand_p (QUEUED_VAR (x));
1858 fmt = GET_RTX_FORMAT (GET_CODE (x));
1859 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1865 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1866 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1869 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1877 mn10300_address_cost_1 (rtx x, int *unsig)
1879 switch (GET_CODE (x))
1882 switch (REGNO_REG_CLASS (REGNO (x)))
1908 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1909 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1914 return mn10300_address_cost (XEXP (x, 0));
1918 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1921 if (INTVAL (x) == 0)
1923 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1925 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1927 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1937 switch (GET_CODE (XEXP (x, 0)))
1940 return mn10300_address_cost (XEXP (x, 0));
1956 mn10300_address_cost (rtx x)
1959 return mn10300_address_cost_1 (x, &s);
1963 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total)
1968 /* Zeros are extremely cheap. */
1969 if (INTVAL (x) == 0 && outer_code == SET)
1971 /* If it fits in 8 bits, then it's still relatively cheap. */
1972 else if (INT_8_BITS (INTVAL (x)))
1974 /* This is the "base" cost, includes constants where either the
1975 upper or lower 16bits are all zeros. */
1976 else if (INT_16_BITS (INTVAL (x))
1977 || (INTVAL (x) & 0xffff) == 0
1978 || (INTVAL (x) & 0xffff0000) == 0)
1987 /* These are more costly than a CONST_INT, but we can relax them,
1988 so they're less costly than a CONST_DOUBLE. */
1993 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
1994 so their cost is very high. */
1998 /* ??? This probably needs more work. */
2010 /* Check whether a constant used to initialize a DImode or DFmode can
2011 use a clr instruction. The code here must be kept in sync with
2015 mn10300_wide_const_load_uses_clr (rtx operands[2])
2019 if (GET_CODE (operands[0]) != REG
2020 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2023 switch (GET_CODE (operands[1]))
2028 split_double (operands[1], &low, &high);
2029 val[0] = INTVAL (low);
2030 val[1] = INTVAL (high);
2035 if (GET_MODE (operands[1]) == DFmode)
2039 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2040 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2042 else if (GET_MODE (operands[1]) == VOIDmode
2043 || GET_MODE (operands[1]) == DImode)
2045 val[0] = CONST_DOUBLE_LOW (operands[1]);
2046 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2054 return val[0] == 0 || val[1] == 0;
2056 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2057 may access it using GOTOFF instead of GOT. */
2060 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2064 if (GET_CODE (rtl) != MEM)
2066 symbol = XEXP (rtl, 0);
2067 if (GET_CODE (symbol) != SYMBOL_REF)
2071 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);