1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
28 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
43 #include "target-def.h"
45 /* The size of the callee register save area. Right now we save everything
46 on entry since it costs us nothing in code size. It does cost us from a
47 speed standpoint, so we want to optimize this sooner or later. */
48 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
49 + 4 * regs_ever_live[3] \
50 + 4 * regs_ever_live[6] \
51 + 4 * regs_ever_live[7] \
52 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
53 || regs_ever_live[16] || regs_ever_live[17]))
55 /* Initialize the GCC target structure. */
56 #undef TARGET_ASM_ALIGNED_HI_OP
57 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
59 struct gcc_target targetm = TARGET_INITIALIZER;
65 fprintf (file, "#\tGCC For the Matsushita MN10300\n");
67 fprintf (file, "# -O%d\n", optimize);
69 fprintf (file, "\n\n");
72 fprintf (file, "\t.am33\n");
73 output_file_directive (file, main_input_filename);
77 /* Print operand X using operand code CODE to assembly language output file
81 print_operand (file, x, code)
90 /* These are normal and reversed branches. */
91 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
100 fprintf (file, "ge");
103 fprintf (file, "gt");
106 fprintf (file, "le");
109 fprintf (file, "lt");
112 fprintf (file, "cc");
115 fprintf (file, "hi");
118 fprintf (file, "ls");
121 fprintf (file, "cs");
128 /* This is used for the operand to a call instruction;
129 if it's a REG, enclose it in parens, else output
130 the operand normally. */
131 if (GET_CODE (x) == REG)
134 print_operand (file, x, 0);
138 print_operand (file, x, 0);
141 /* These are the least significant word in a 64bit value. */
143 switch (GET_CODE (x))
147 output_address (XEXP (x, 0));
152 fprintf (file, "%s", reg_names[REGNO (x)]);
156 fprintf (file, "%s", reg_names[subreg_regno (x)]);
164 switch (GET_MODE (x))
167 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
168 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
169 fprintf (file, "0x%lx", val[0]);
172 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
173 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
174 fprintf (file, "0x%lx", val[0]);
178 print_operand_address (file,
179 GEN_INT (CONST_DOUBLE_LOW (x)));
190 split_double (x, &low, &high);
191 fprintf (file, "%ld", (long)INTVAL (low));
200 /* Similarly, but for the most significant word. */
202 switch (GET_CODE (x))
206 x = adjust_address (x, SImode, 4);
207 output_address (XEXP (x, 0));
212 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
216 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
224 switch (GET_MODE (x))
227 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
228 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
229 fprintf (file, "0x%lx", val[1]);
235 print_operand_address (file,
236 GEN_INT (CONST_DOUBLE_HIGH (x)));
247 split_double (x, &low, &high);
248 fprintf (file, "%ld", (long)INTVAL (high));
259 if (GET_CODE (XEXP (x, 0)) == REG)
260 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
262 output_address (XEXP (x, 0));
267 output_address (GEN_INT ((~INTVAL (x)) & 0xff));
270 /* For shift counts. The hardware ignores the upper bits of
271 any immediate, but the assembler will flag an out of range
272 shift count as an error. So we mask off the high bits
273 of the immediate here. */
275 if (GET_CODE (x) == CONST_INT)
277 fprintf (file, "%d", INTVAL (x) & 0x1f);
283 switch (GET_CODE (x))
287 output_address (XEXP (x, 0));
296 fprintf (file, "%s", reg_names[REGNO (x)]);
300 fprintf (file, "%s", reg_names[subreg_regno (x)]);
303 /* This will only be single precision.... */
309 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
310 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
311 fprintf (file, "0x%lx", val);
320 print_operand_address (file, x);
329 /* Output assembly language output for the address ADDR to FILE. */
332 print_operand_address (file, addr)
336 switch (GET_CODE (addr))
339 print_operand_address (file, XEXP (addr, 0));
343 print_operand (file, addr, 0);
348 if (REG_P (XEXP (addr, 0))
349 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
350 base = XEXP (addr, 0), index = XEXP (addr, 1);
351 else if (REG_P (XEXP (addr, 1))
352 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
353 base = XEXP (addr, 1), index = XEXP (addr, 0);
356 print_operand (file, index, 0);
358 print_operand (file, base, 0);;
362 output_addr_const (file, addr);
365 output_addr_const (file, addr);
370 /* Print a set of registers in the format required by "movm" and "ret".
371 Register K is saved if bit K of MASK is set. The data and address
372 registers can be stored individually, but the extended registers cannot.
373 We assume that the mask alread takes that into account. For instance,
374 bits 14 to 17 must have the same value. */
377 mn10300_print_reg_list (file, mask)
387 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
388 if ((mask & (1 << i)) != 0)
392 fputs (reg_names [i], file);
396 if ((mask & 0x3c000) != 0)
398 if ((mask & 0x3c000) != 0x3c000)
402 fputs ("exreg1", file);
410 can_use_return_insn ()
412 /* size includes the fixed stack space needed for function calls. */
413 int size = get_frame_size () + current_function_outgoing_args_size;
415 /* And space for the return pointer. */
416 size += current_function_outgoing_args_size ? 4 : 0;
418 return (reload_completed
420 && !regs_ever_live[2]
421 && !regs_ever_live[3]
422 && !regs_ever_live[6]
423 && !regs_ever_live[7]
424 && !regs_ever_live[14]
425 && !regs_ever_live[15]
426 && !regs_ever_live[16]
427 && !regs_ever_live[17]
428 && !frame_pointer_needed);
431 /* Returns the set of live, callee-saved registers as a bitmask. The
432 callee-saved extended registers cannot be stored individually, so
433 all of them will be included in the mask if any one of them is used. */
436 mn10300_get_live_callee_saved_regs ()
442 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
443 if (regs_ever_live[i] && ! call_used_regs[i])
445 if ((mask & 0x3c000) != 0)
451 /* Generate an instruction that pushes several registers onto the stack.
452 Register K will be saved if bit K in MASK is set. The function does
453 nothing if MASK is zero.
455 To be compatible with the "movm" instruction, the lowest-numbered
456 register must be stored in the lowest slot. If MASK is the set
457 { R1,...,RN }, where R1...RN are ordered least first, the generated
458 instruction will have the form:
461 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
462 (set (mem:SI (plus:SI (reg:SI 9)
466 (set (mem:SI (plus:SI (reg:SI 9)
471 mn10300_gen_multiple_store (mask)
481 /* Count how many registers need to be saved. */
483 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
484 if ((mask & (1 << i)) != 0)
487 /* We need one PARALLEL element to update the stack pointer and
488 an additional element for each register that is stored. */
489 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
491 /* Create the instruction that updates the stack pointer. */
493 = gen_rtx_SET (SImode,
495 gen_rtx_PLUS (SImode,
497 GEN_INT (-count * 4)));
499 /* Create each store. */
501 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
502 if ((mask & (1 << i)) != 0)
504 rtx address = gen_rtx_PLUS (SImode,
506 GEN_INT (-pari * 4));
507 XVECEXP(par, 0, pari)
508 = gen_rtx_SET (VOIDmode,
509 gen_rtx_MEM (SImode, address),
510 gen_rtx_REG (SImode, i));
514 par = emit_insn (par);
515 RTX_FRAME_RELATED_P (par) = 1;
524 /* SIZE includes the fixed stack space needed for function calls. */
525 size = get_frame_size () + current_function_outgoing_args_size;
526 size += (current_function_outgoing_args_size ? 4 : 0);
528 /* If this is an old-style varargs function, then its arguments
529 need to be flushed back to the stack. */
530 if (current_function_varargs)
532 emit_move_insn (gen_rtx_MEM (SImode,
533 plus_constant (stack_pointer_rtx, 4)),
534 gen_rtx_REG (SImode, 0));
535 emit_move_insn (gen_rtx_MEM (SImode,
536 plus_constant (stack_pointer_rtx, 8)),
537 gen_rtx_REG (SImode, 1));
540 /* If we use any of the callee-saved registers, save them now. */
541 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
543 /* Now put the frame pointer into the frame pointer register. */
544 if (frame_pointer_needed)
545 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
547 /* Allocate stack for this frame. */
549 emit_insn (gen_addsi3 (stack_pointer_rtx,
559 /* SIZE includes the fixed stack space needed for function calls. */
560 size = get_frame_size () + current_function_outgoing_args_size;
561 size += (current_function_outgoing_args_size ? 4 : 0);
563 /* Maybe cut back the stack, except for the register save area.
565 If the frame pointer exists, then use the frame pointer to
568 If the stack size + register save area is more than 255 bytes,
569 then the stack must be cut back here since the size + register
570 save size is too big for a ret/retf instruction.
572 Else leave it alone, it will be cut back as part of the
573 ret/retf instruction, or there wasn't any stack to begin with.
575 Under no circumstanes should the register save area be
576 deallocated here, that would leave a window where an interrupt
577 could occur and trash the register save area. */
578 if (frame_pointer_needed)
580 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
583 else if (size + REG_SAVE_BYTES > 255)
585 emit_insn (gen_addsi3 (stack_pointer_rtx,
591 /* Adjust the stack and restore callee-saved registers, if any. */
592 if (size || regs_ever_live[2] || regs_ever_live[3]
593 || regs_ever_live[6] || regs_ever_live[7]
594 || regs_ever_live[14] || regs_ever_live[15]
595 || regs_ever_live[16] || regs_ever_live[17]
596 || frame_pointer_needed)
597 emit_jump_insn (gen_return_internal_regs
598 (GEN_INT (size + REG_SAVE_BYTES)));
600 emit_jump_insn (gen_return_internal ());
603 /* Update the condition code from the insn. */
606 notice_update_cc (body, insn)
610 switch (get_attr_cc (insn))
613 /* Insn does not affect CC at all. */
617 /* Insn does not change CC, but the 0'th operand has been changed. */
618 if (cc_status.value1 != 0
619 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
620 cc_status.value1 = 0;
624 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
627 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
628 cc_status.value1 = recog_data.operand[0];
632 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
635 cc_status.flags |= CC_NO_CARRY;
636 cc_status.value1 = recog_data.operand[0];
640 /* The insn is a compare instruction. */
642 cc_status.value1 = SET_SRC (body);
646 /* The insn is a compare instruction. */
648 cc_status.value1 = SET_SRC (body);
649 cc_status.flags |= CC_INVERTED;
653 /* Insn doesn't leave CC in a usable state. */
662 /* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store().
663 This function is for MATCH_PARALLEL and so assumes OP is known to be
664 parallel. If OP is a multiple store, return a mask indicating which
665 registers it saves. Return 0 otherwise. */
668 store_multiple_operation (op, mode)
670 enum machine_mode mode ATTRIBUTE_UNUSED;
678 count = XVECLEN (op, 0);
682 /* Check that first instruction has the form (set (sp) (plus A B)) */
683 elt = XVECEXP (op, 0, 0);
684 if (GET_CODE (elt) != SET
685 || GET_CODE (SET_DEST (elt)) != REG
686 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
687 || GET_CODE (SET_SRC (elt)) != PLUS)
690 /* Check that A is the stack pointer and B is the expected stack size.
691 For OP to match, each subsequent instruction should push a word onto
692 the stack. We therefore expect the first instruction to create
693 COUNT-1 stack slots. */
695 if (GET_CODE (XEXP (elt, 0)) != REG
696 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
697 || GET_CODE (XEXP (elt, 1)) != CONST_INT
698 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
701 /* Now go through the rest of the vector elements. They must be
702 ordered so that the first instruction stores the highest-numbered
703 register to the highest stack slot and that subsequent instructions
704 store a lower-numbered register to the slot below.
706 LAST keeps track of the smallest-numbered register stored so far.
707 MASK is the set of stored registers. */
708 last = FIRST_PSEUDO_REGISTER;
710 for (i = 1; i < count; i++)
712 /* Check that element i is a (set (mem M) R) and that R is valid. */
713 elt = XVECEXP (op, 0, i);
714 if (GET_CODE (elt) != SET
715 || GET_CODE (SET_DEST (elt)) != MEM
716 || GET_CODE (SET_SRC (elt)) != REG
717 || REGNO (SET_SRC (elt)) >= last)
720 /* R was OK, so provisionally add it to MASK. We return 0 in any
721 case if the rest of the instruction has a flaw. */
722 last = REGNO (SET_SRC (elt));
725 /* Check that M has the form (plus (sp) (const_int -I*4)) */
726 elt = XEXP (SET_DEST (elt), 0);
727 if (GET_CODE (elt) != PLUS
728 || GET_CODE (XEXP (elt, 0)) != REG
729 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
730 || GET_CODE (XEXP (elt, 1)) != CONST_INT
731 || INTVAL (XEXP (elt, 1)) != -i * 4)
735 /* All or none of the callee-saved extended registers must be in the set. */
736 if ((mask & 0x3c000) != 0
737 && (mask & 0x3c000) != 0x3c000)
743 /* Return true if OP is a valid call operand. */
746 call_address_operand (op, mode)
748 enum machine_mode mode ATTRIBUTE_UNUSED;
750 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
753 /* What (if any) secondary registers are needed to move IN with mode
754 MODE into a register in register class CLASS.
756 We might be able to simplify this. */
758 secondary_reload_class (class, mode, in)
759 enum reg_class class;
760 enum machine_mode mode;
763 /* Memory loads less than a full word wide can't have an
764 address or stack pointer destination. They must use
765 a data register as an intermediate register. */
766 if ((GET_CODE (in) == MEM
767 || (GET_CODE (in) == REG
768 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
769 || (GET_CODE (in) == SUBREG
770 && GET_CODE (SUBREG_REG (in)) == REG
771 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
772 && (mode == QImode || mode == HImode)
773 && (class == ADDRESS_REGS || class == SP_REGS
774 || class == SP_OR_ADDRESS_REGS))
777 return DATA_OR_EXTENDED_REGS;
781 /* We can't directly load sp + const_int into a data register;
782 we must use an address register as an intermediate. */
784 && class != ADDRESS_REGS
785 && class != SP_OR_ADDRESS_REGS
786 && class != SP_OR_EXTENDED_REGS
787 && class != ADDRESS_OR_EXTENDED_REGS
788 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
789 && (in == stack_pointer_rtx
790 || (GET_CODE (in) == PLUS
791 && (XEXP (in, 0) == stack_pointer_rtx
792 || XEXP (in, 1) == stack_pointer_rtx))))
795 if (GET_CODE (in) == PLUS
796 && (XEXP (in, 0) == stack_pointer_rtx
797 || XEXP (in, 1) == stack_pointer_rtx))
800 return DATA_OR_EXTENDED_REGS;
804 /* Otherwise assume no secondary reloads are needed. */
809 initial_offset (from, to)
812 /* The difference between the argument pointer and the frame pointer
813 is the size of the callee register save area. */
814 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
816 if (regs_ever_live[2] || regs_ever_live[3]
817 || regs_ever_live[6] || regs_ever_live[7]
818 || regs_ever_live[14] || regs_ever_live[15]
819 || regs_ever_live[16] || regs_ever_live[17]
820 || frame_pointer_needed)
821 return REG_SAVE_BYTES;
826 /* The difference between the argument pointer and the stack pointer is
827 the sum of the size of this function's frame, the callee register save
828 area, and the fixed stack space needed for function calls (if any). */
829 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
831 if (regs_ever_live[2] || regs_ever_live[3]
832 || regs_ever_live[6] || regs_ever_live[7]
833 || regs_ever_live[14] || regs_ever_live[15]
834 || regs_ever_live[16] || regs_ever_live[17]
835 || frame_pointer_needed)
836 return (get_frame_size () + REG_SAVE_BYTES
837 + (current_function_outgoing_args_size
838 ? current_function_outgoing_args_size + 4 : 0));
840 return (get_frame_size ()
841 + (current_function_outgoing_args_size
842 ? current_function_outgoing_args_size + 4 : 0));
845 /* The difference between the frame pointer and stack pointer is the sum
846 of the size of this function's frame and the fixed stack space needed
847 for function calls (if any). */
848 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
849 return (get_frame_size ()
850 + (current_function_outgoing_args_size
851 ? current_function_outgoing_args_size + 4 : 0));
856 /* Flush the argument registers to the stack for a stdarg function;
857 return the new argument pointer. */
859 mn10300_builtin_saveregs ()
862 tree fntype = TREE_TYPE (current_function_decl);
863 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
864 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
866 ? UNITS_PER_WORD : 0);
867 int set = get_varargs_alias_set ();
870 offset = plus_constant (current_function_arg_offset_rtx, argadj);
872 offset = current_function_arg_offset_rtx;
874 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
875 set_mem_alias_set (mem, set);
876 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
878 mem = gen_rtx_MEM (SImode,
879 plus_constant (current_function_internal_arg_pointer, 4));
880 set_mem_alias_set (mem, set);
881 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
883 return copy_to_reg (expand_binop (Pmode, add_optab,
884 current_function_internal_arg_pointer,
885 offset, 0, 0, OPTAB_LIB_WIDEN));
889 mn10300_va_start (stdarg_p, valist, nextarg)
895 nextarg = expand_builtin_saveregs ();
897 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
901 mn10300_va_arg (valist, type)
904 HOST_WIDE_INT align, rsize;
907 /* Compute the rounded size of the type. */
908 align = PARM_BOUNDARY / BITS_PER_UNIT;
909 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
911 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
912 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
913 TREE_SIDE_EFFECTS (t) = 1;
915 ptr = build_pointer_type (type);
917 /* "Large" types are passed by reference. */
920 pptr = build_pointer_type (ptr);
921 t = build1 (NOP_EXPR, pptr, t);
922 TREE_SIDE_EFFECTS (t) = 1;
924 t = build1 (INDIRECT_REF, ptr, t);
925 TREE_SIDE_EFFECTS (t) = 1;
929 t = build1 (NOP_EXPR, ptr, t);
930 TREE_SIDE_EFFECTS (t) = 1;
934 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
937 /* Return an RTX to represent where a value with mode MODE will be returned
938 from a function. If the result is 0, the argument is pushed. */
941 function_arg (cum, mode, type, named)
942 CUMULATIVE_ARGS *cum;
943 enum machine_mode mode;
945 int named ATTRIBUTE_UNUSED;
950 /* We only support using 2 data registers as argument registers. */
953 /* Figure out the size of the object to be passed. */
955 size = int_size_in_bytes (type);
957 size = GET_MODE_SIZE (mode);
959 /* Figure out the alignment of the object to be passed. */
962 cum->nbytes = (cum->nbytes + 3) & ~3;
964 /* Don't pass this arg via a register if all the argument registers
966 if (cum->nbytes > nregs * UNITS_PER_WORD)
969 /* Don't pass this arg via a register if it would be split between
970 registers and memory. */
971 if (type == NULL_TREE
972 && cum->nbytes + size > nregs * UNITS_PER_WORD)
975 switch (cum->nbytes / UNITS_PER_WORD)
978 result = gen_rtx_REG (mode, 0);
981 result = gen_rtx_REG (mode, 1);
990 /* Return the number of registers to use for an argument passed partially
991 in registers and partially in memory. */
994 function_arg_partial_nregs (cum, mode, type, named)
995 CUMULATIVE_ARGS *cum;
996 enum machine_mode mode;
998 int named ATTRIBUTE_UNUSED;
1002 /* We only support using 2 data registers as argument registers. */
1005 /* Figure out the size of the object to be passed. */
1006 if (mode == BLKmode)
1007 size = int_size_in_bytes (type);
1009 size = GET_MODE_SIZE (mode);
1011 /* Figure out the alignment of the object to be passed. */
1014 cum->nbytes = (cum->nbytes + 3) & ~3;
1016 /* Don't pass this arg via a register if all the argument registers
1018 if (cum->nbytes > nregs * UNITS_PER_WORD)
1021 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1024 /* Don't pass this arg via a register if it would be split between
1025 registers and memory. */
1026 if (type == NULL_TREE
1027 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1030 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1033 /* Output a tst insn. */
1035 output_tst (operand, insn)
1041 /* We can save a byte if we can find a register which has the value
1043 temp = PREV_INSN (insn);
1044 while (optimize && temp)
1048 /* We allow the search to go through call insns. We record
1049 the fact that we've past a CALL_INSN and reject matches which
1050 use call clobbered registers. */
1051 if (GET_CODE (temp) == CODE_LABEL
1052 || GET_CODE (temp) == JUMP_INSN
1053 || GET_CODE (temp) == BARRIER)
1056 if (GET_CODE (temp) == CALL_INSN)
1059 if (GET_CODE (temp) == NOTE)
1061 temp = PREV_INSN (temp);
1065 /* It must be an insn, see if it is a simple set. */
1066 set = single_set (temp);
1069 temp = PREV_INSN (temp);
1073 /* Are we setting a data register to zero (this does not win for
1076 If it's a call clobbered register, have we past a call?
1078 Make sure the register we find isn't the same as ourself;
1079 the mn10300 can't encode that.
1081 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1082 so the code to detect calls here isn't doing anything useful. */
1083 if (REG_P (SET_DEST (set))
1084 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1085 && !reg_set_between_p (SET_DEST (set), temp, insn)
1086 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1087 == REGNO_REG_CLASS (REGNO (operand)))
1088 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1089 && REGNO (SET_DEST (set)) != REGNO (operand)
1091 || !call_used_regs[REGNO (SET_DEST (set))]))
1094 xoperands[0] = operand;
1095 xoperands[1] = SET_DEST (set);
1097 output_asm_insn ("cmp %1,%0", xoperands);
1101 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1102 && REG_P (SET_DEST (set))
1103 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1104 && !reg_set_between_p (SET_DEST (set), temp, insn)
1105 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1106 != REGNO_REG_CLASS (REGNO (operand)))
1107 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1108 && REGNO (SET_DEST (set)) != REGNO (operand)
1110 || !call_used_regs[REGNO (SET_DEST (set))]))
1113 xoperands[0] = operand;
1114 xoperands[1] = SET_DEST (set);
1116 output_asm_insn ("cmp %1,%0", xoperands);
1119 temp = PREV_INSN (temp);
1125 impossible_plus_operand (op, mode)
1127 enum machine_mode mode ATTRIBUTE_UNUSED;
1129 if (GET_CODE (op) != PLUS)
1132 if (XEXP (op, 0) == stack_pointer_rtx
1133 || XEXP (op, 1) == stack_pointer_rtx)
1139 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1140 for the btst insn which may examine memory or a register (the memory
1141 variant only allows an unsigned 8 bit integer). */
1143 const_8bit_operand (op, mode)
1145 enum machine_mode mode ATTRIBUTE_UNUSED;
1147 return (GET_CODE (op) == CONST_INT
1149 && INTVAL (op) < 256);
1152 /* Similarly, but when using a zero_extract pattern for a btst where
1153 the source operand might end up in memory. */
1155 mask_ok_for_mem_btst (len, bit)
1168 /* MASK must bit into an 8bit value. */
1169 return (((mask & 0xff) == mask)
1170 || ((mask & 0xff00) == mask)
1171 || ((mask & 0xff0000) == mask)
1172 || ((mask & 0xff000000) == mask));
1175 /* Return 1 if X contains a symbolic expression. We know these
1176 expressions will have one of a few well defined forms, so
1177 we need only check those forms. */
1179 symbolic_operand (op, mode)
1181 enum machine_mode mode ATTRIBUTE_UNUSED;
1183 switch (GET_CODE (op))
1190 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1191 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1192 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1198 /* Try machine dependent ways of modifying an illegitimate address
1199 to be legitimate. If we find one, return the new valid address.
1200 This macro is used in only one place: `memory_address' in explow.c.
1202 OLDX is the address as it was before break_out_memory_refs was called.
1203 In some cases it is useful to look at this to decide what needs to be done.
1205 MODE and WIN are passed so that this macro can use
1206 GO_IF_LEGITIMATE_ADDRESS.
1208 Normally it is always safe for this macro to do nothing. It exists to
1209 recognize opportunities to optimize the output.
1211 But on a few ports with segmented architectures and indexed addressing
1212 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1214 legitimize_address (x, oldx, mode)
1216 rtx oldx ATTRIBUTE_UNUSED;
1217 enum machine_mode mode ATTRIBUTE_UNUSED;
1219 /* Uh-oh. We might have an address for x[n-100000]. This needs
1220 special handling to avoid creating an indexed memory address
1221 with x-100000 as the base. */
1222 if (GET_CODE (x) == PLUS
1223 && symbolic_operand (XEXP (x, 1), VOIDmode))
1225 /* Ugly. We modify things here so that the address offset specified
1226 by the index expression is computed first, then added to x to form
1227 the entire address. */
1229 rtx regx1, regy1, regy2, y;
1231 /* Strip off any CONST. */
1233 if (GET_CODE (y) == CONST)
1236 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1238 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1239 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1240 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1241 regx1 = force_reg (Pmode,
1242 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1243 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1250 mn10300_address_cost (x, unsig)
1258 switch (GET_CODE (x))
1261 switch (REGNO_REG_CLASS (REGNO (x)))
1286 return (mn10300_address_cost (XEXP (x, 0), unsig)
1287 + mn10300_address_cost (XEXP (x, 1), unsig));
1292 return ADDRESS_COST (XEXP (x, 0));
1296 return mn10300_address_cost (XEXP (x, 0), unsig);
1299 if (INTVAL (x) == 0)
1301 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1303 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1305 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1315 switch (GET_CODE (XEXP (x, 0)))
1318 return ADDRESS_COST (XEXP (x, 0));