gcc/config/mips/sync.md

   1 ;;  Machine Description for MIPS based processor synchronization
   2 ;;  instructions.
   3 ;;  Copyright (C) 2007, 2008
   4 ;;  Free Software Foundation, Inc.
   5
   6 ;; This file is part of GCC.
   7
   8 ;; GCC is free software; you can redistribute it and/or modify
   9 ;; it under the terms of the GNU General Public License as published by
  10 ;; the Free Software Foundation; either version 3, or (at your option)
  11 ;; any later version.
  12
  13 ;; GCC is distributed in the hope that it will be useful,
  14 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 ;; GNU General Public License for more details.
  17
  18 ;; You should have received a copy of the GNU General Public License
  19 ;; along with GCC; see the file COPYING3.  If not see
  20 ;; <http://www.gnu.org/licenses/>.
  21
  22 ;; Atomic fetch bitwise operations.
  23 (define_code_iterator fetchop_bit [ior xor and])
  24
  25 ;; Atomic HI and QI operations
  26 (define_code_iterator atomic_hiqi_op [plus minus ior xor and])
  27
  28 ;; Atomic memory operations.
  29
  30 (define_expand "memory_barrier"
  31   [(set (match_dup 0)
  32         (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
  33   "GENERATE_SYNC"
  34 {
  35   operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
  36   MEM_VOLATILE_P (operands[0]) = 1;
  37 })
  38
  39 (define_insn "*mb_internal"
  40   [(set (match_operand:BLK 0 "" "")
  41         (unspec:BLK [(match_dup 0)] UNSPEC_MEMORY_BARRIER))]
  42   "GENERATE_SYNC"
  43   "%|sync%-")
  44
  45 (define_insn "sync_compare_and_swap<mode>"
  46   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
  47         (match_operand:GPR 1 "memory_operand" "+R,R"))
  48    (set (match_dup 1)
  49         (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "dJ,dJ")
  50                               (match_operand:GPR 3 "arith_operand" "I,d")]
  51          UNSPEC_COMPARE_AND_SWAP))]
  52   "GENERATE_LL_SC"
  53 {
  54   if (which_alternative == 0)
  55     return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "li"));
  56   else
  57     return mips_output_sync_loop (MIPS_COMPARE_AND_SWAP ("<d>", "move"));
  58 }
  59   [(set_attr "length" "32")])
  60
  61 (define_expand "sync_compare_and_swap<mode>"
  62   [(match_operand:SHORT 0 "register_operand")
  63    (match_operand:SHORT 1 "memory_operand")
  64    (match_operand:SHORT 2 "general_operand")
  65    (match_operand:SHORT 3 "general_operand")]
  66   "GENERATE_LL_SC"
  67 {
  68   union mips_gen_fn_ptrs generator;
  69   generator.fn_6 = gen_compare_and_swap_12;
  70   mips_expand_atomic_qihi (generator,
  71                            operands[0], operands[1], operands[2], operands[3]);
  72   DONE;
  73 })
  74
  75 ;; Helper insn for mips_expand_atomic_qihi.
  76 (define_insn "compare_and_swap_12"
  77   [(set (match_operand:SI 0 "register_operand" "=&d,&d")
  78         (match_operand:SI 1 "memory_operand" "+R,R"))
  79    (set (match_dup 1)
  80         (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
  81                              (match_operand:SI 3 "register_operand" "d,d")
  82                              (match_operand:SI 4 "reg_or_0_operand" "dJ,dJ")
  83                              (match_operand:SI 5 "reg_or_0_operand" "d,J")]
  84                             UNSPEC_COMPARE_AND_SWAP_12))]
  85   "GENERATE_LL_SC"
  86 {
  87   if (which_alternative == 0)
  88     return (mips_output_sync_loop
  89             (MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_NONZERO_OP)));
  90   else
  91     return (mips_output_sync_loop
  92             (MIPS_COMPARE_AND_SWAP_12 (MIPS_COMPARE_AND_SWAP_12_ZERO_OP)));
  93 }
  94   [(set_attr "length" "40,36")])
  95
  96 (define_insn "sync_add<mode>"
  97   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
  98         (unspec_volatile:GPR
  99           [(plus:GPR (match_dup 0)
 100                      (match_operand:GPR 1 "arith_operand" "I,d"))]
 101           UNSPEC_SYNC_OLD_OP))]
 102   "GENERATE_LL_SC"
 103 {
 104   if (which_alternative == 0)
 105     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addiu"));
 106   else
 107     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>addu"));
 108 }
 109   [(set_attr "length" "28")])
 110
 111 (define_expand "sync_<optab><mode>"
 112   [(set (match_operand:SHORT 0 "memory_operand")
 113         (unspec_volatile:SHORT
 114           [(atomic_hiqi_op:SHORT (match_dup 0)
 115                                  (match_operand:SHORT 1 "general_operand"))]
 116           UNSPEC_SYNC_OLD_OP))]
 117   "GENERATE_LL_SC"
 118 {
 119   union mips_gen_fn_ptrs generator;
 120   generator.fn_4 = gen_sync_<optab>_12;
 121   mips_expand_atomic_qihi (generator,
 122                            NULL, operands[0], operands[1], NULL);
 123   DONE;
 124 })
 125
 126 ;; Helper insn for sync_<optab><mode>
 127 (define_insn "sync_<optab>_12"
 128   [(set (match_operand:SI 0 "memory_operand" "+R")
 129         (unspec_volatile:SI
 130           [(match_operand:SI 1 "register_operand" "d")
 131            (match_operand:SI 2 "register_operand" "d")
 132            (atomic_hiqi_op:SI (match_dup 0)
 133                               (match_operand:SI 3 "register_operand" "dJ"))]
 134           UNSPEC_SYNC_OLD_OP_12))
 135    (clobber (match_scratch:SI 4 "=&d"))]
 136   "GENERATE_LL_SC"
 137 {
 138     return (mips_output_sync_loop
 139             (MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND)));
 140 }
 141   [(set_attr "length" "40")])
 142
 143 (define_expand "sync_old_<optab><mode>"
 144   [(parallel [
 145      (set (match_operand:SHORT 0 "register_operand")
 146           (match_operand:SHORT 1 "memory_operand"))
 147      (set (match_dup 1)
 148           (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
 149                                     (match_dup 1)
 150                                     (match_operand:SHORT 2 "general_operand"))]
 151             UNSPEC_SYNC_OLD_OP))])]
 152   "GENERATE_LL_SC"
 153 {
 154   union mips_gen_fn_ptrs generator;
 155   generator.fn_5 = gen_sync_old_<optab>_12;
 156   mips_expand_atomic_qihi (generator,
 157                            operands[0], operands[1], operands[2], NULL);
 158   DONE;
 159 })
 160
 161 ;; Helper insn for sync_old_<optab><mode>
 162 (define_insn "sync_old_<optab>_12"
 163   [(set (match_operand:SI 0 "register_operand" "=&d")
 164         (match_operand:SI 1 "memory_operand" "+R"))
 165    (set (match_dup 1)
 166         (unspec_volatile:SI
 167           [(match_operand:SI 2 "register_operand" "d")
 168            (match_operand:SI 3 "register_operand" "d")
 169            (atomic_hiqi_op:SI (match_dup 0)
 170                               (match_operand:SI 4 "register_operand" "dJ"))]
 171           UNSPEC_SYNC_OLD_OP_12))
 172    (clobber (match_scratch:SI 5 "=&d"))]
 173   "GENERATE_LL_SC"
 174 {
 175     return (mips_output_sync_loop
 176             (MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND)));
 177 }
 178   [(set_attr "length" "40")])
 179
 180 (define_expand "sync_new_<optab><mode>"
 181   [(parallel [
 182      (set (match_operand:SHORT 0 "register_operand")
 183           (unspec_volatile:SHORT [(atomic_hiqi_op:SHORT
 184                                     (match_operand:SHORT 1 "memory_operand")
 185                                     (match_operand:SHORT 2 "general_operand"))]
 186             UNSPEC_SYNC_NEW_OP))
 187      (set (match_dup 1)
 188           (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
 189             UNSPEC_SYNC_NEW_OP))])]
 190   "GENERATE_LL_SC"
 191 {
 192   union mips_gen_fn_ptrs generator;
 193   generator.fn_5 = gen_sync_new_<optab>_12;
 194   mips_expand_atomic_qihi (generator,
 195                            operands[0], operands[1], operands[2], NULL);
 196   DONE;
 197 })
 198
 199 ;; Helper insn for sync_new_<optab><mode>
 200 (define_insn "sync_new_<optab>_12"
 201   [(set (match_operand:SI 0 "register_operand" "=&d")
 202         (unspec_volatile:SI
 203           [(match_operand:SI 1 "memory_operand" "+R")
 204            (match_operand:SI 2 "register_operand" "d")
 205            (match_operand:SI 3 "register_operand" "d")
 206            (atomic_hiqi_op:SI (match_dup 0)
 207                               (match_operand:SI 4 "register_operand" "dJ"))]
 208           UNSPEC_SYNC_NEW_OP_12))
 209    (set (match_dup 1)
 210         (unspec_volatile:SI
 211           [(match_dup 1)
 212            (match_dup 2)
 213            (match_dup 3)
 214            (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
 215   "GENERATE_LL_SC"
 216 {
 217     return (mips_output_sync_loop
 218             (MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND)));
 219 }
 220   [(set_attr "length" "40")])
 221
 222 (define_expand "sync_nand<mode>"
 223   [(set (match_operand:SHORT 0 "memory_operand")
 224         (unspec_volatile:SHORT
 225           [(match_dup 0)
 226            (match_operand:SHORT 1 "general_operand")]
 227           UNSPEC_SYNC_OLD_OP))]
 228   "GENERATE_LL_SC"
 229 {
 230   union mips_gen_fn_ptrs generator;
 231   generator.fn_4 = gen_sync_nand_12;
 232   mips_expand_atomic_qihi (generator,
 233                            NULL, operands[0], operands[1], NULL);
 234   DONE;
 235 })
 236
 237 ;; Helper insn for sync_nand<mode>
 238 (define_insn "sync_nand_12"
 239   [(set (match_operand:SI 0 "memory_operand" "+R")
 240         (unspec_volatile:SI
 241           [(match_operand:SI 1 "register_operand" "d")
 242            (match_operand:SI 2 "register_operand" "d")
 243            (match_dup 0)
 244            (match_operand:SI 3 "register_operand" "dJ")]
 245           UNSPEC_SYNC_OLD_OP_12))
 246    (clobber (match_scratch:SI 4 "=&d"))]
 247   "GENERATE_LL_SC"
 248 {
 249     return (mips_output_sync_loop
 250             (MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR)));
 251 }
 252   [(set_attr "length" "40")])
 253
 254 (define_expand "sync_old_nand<mode>"
 255   [(parallel [
 256      (set (match_operand:SHORT 0 "register_operand")
 257           (match_operand:SHORT 1 "memory_operand"))
 258      (set (match_dup 1)
 259           (unspec_volatile:SHORT [(match_dup 1)
 260                                   (match_operand:SHORT 2 "general_operand")]
 261             UNSPEC_SYNC_OLD_OP))])]
 262   "GENERATE_LL_SC"
 263 {
 264   union mips_gen_fn_ptrs generator;
 265   generator.fn_5 = gen_sync_old_nand_12;
 266   mips_expand_atomic_qihi (generator,
 267                            operands[0], operands[1], operands[2], NULL);
 268   DONE;
 269 })
 270
 271 ;; Helper insn for sync_old_nand<mode>
 272 (define_insn "sync_old_nand_12"
 273   [(set (match_operand:SI 0 "register_operand" "=&d")
 274         (match_operand:SI 1 "memory_operand" "+R"))
 275    (set (match_dup 1)
 276         (unspec_volatile:SI
 277           [(match_operand:SI 2 "register_operand" "d")
 278            (match_operand:SI 3 "register_operand" "d")
 279            (match_operand:SI 4 "register_operand" "dJ")]
 280           UNSPEC_SYNC_OLD_OP_12))
 281    (clobber (match_scratch:SI 5 "=&d"))]
 282   "GENERATE_LL_SC"
 283 {
 284     return (mips_output_sync_loop
 285             (MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR)));
 286 }
 287   [(set_attr "length" "40")])
 288
 289 (define_expand "sync_new_nand<mode>"
 290   [(parallel [
 291      (set (match_operand:SHORT 0 "register_operand")
 292           (unspec_volatile:SHORT [(match_operand:SHORT 1 "memory_operand")
 293                                   (match_operand:SHORT 2 "general_operand")]
 294             UNSPEC_SYNC_NEW_OP))
 295      (set (match_dup 1)
 296           (unspec_volatile:SHORT [(match_dup 1) (match_dup 2)]
 297             UNSPEC_SYNC_NEW_OP))])]
 298   "GENERATE_LL_SC"
 299 {
 300   union mips_gen_fn_ptrs generator;
 301   generator.fn_5 = gen_sync_new_nand_12;
 302   mips_expand_atomic_qihi (generator,
 303                            operands[0], operands[1], operands[2], NULL);
 304   DONE;
 305 })
 306
 307 ;; Helper insn for sync_new_nand<mode>
 308 (define_insn "sync_new_nand_12"
 309   [(set (match_operand:SI 0 "register_operand" "=&d")
 310         (unspec_volatile:SI
 311           [(match_operand:SI 1 "memory_operand" "+R")
 312            (match_operand:SI 2 "register_operand" "d")
 313            (match_operand:SI 3 "register_operand" "d")
 314            (match_operand:SI 4 "register_operand" "dJ")]
 315           UNSPEC_SYNC_NEW_OP_12))
 316    (set (match_dup 1)
 317         (unspec_volatile:SI
 318           [(match_dup 1)
 319            (match_dup 2)
 320            (match_dup 3)
 321            (match_dup 4)] UNSPEC_SYNC_NEW_OP_12))]
 322   "GENERATE_LL_SC"
 323 {
 324     return (mips_output_sync_loop
 325             (MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR)));
 326 }
 327   [(set_attr "length" "40")])
 328
 329 (define_insn "sync_sub<mode>"
 330   [(set (match_operand:GPR 0 "memory_operand" "+R")
 331         (unspec_volatile:GPR
 332           [(minus:GPR (match_dup 0)
 333                               (match_operand:GPR 1 "register_operand" "d"))]
 334          UNSPEC_SYNC_OLD_OP))]
 335   "GENERATE_LL_SC"
 336 {
 337   return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<d>subu"));
 338 }
 339   [(set_attr "length" "28")])
 340
 341 (define_insn "sync_old_add<mode>"
 342   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 343         (match_operand:GPR 1 "memory_operand" "+R,R"))
 344    (set (match_dup 1)
 345         (unspec_volatile:GPR
 346           [(plus:GPR (match_dup 1)
 347                      (match_operand:GPR 2 "arith_operand" "I,d"))]
 348          UNSPEC_SYNC_OLD_OP))]
 349   "GENERATE_LL_SC"
 350 {
 351   if (which_alternative == 0)
 352     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addiu"));
 353   else
 354     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>addu"));
 355 }
 356   [(set_attr "length" "28")])
 357
 358 (define_insn "sync_old_sub<mode>"
 359   [(set (match_operand:GPR 0 "register_operand" "=&d")
 360         (match_operand:GPR 1 "memory_operand" "+R"))
 361    (set (match_dup 1)
 362         (unspec_volatile:GPR
 363           [(minus:GPR (match_dup 1)
 364                       (match_operand:GPR 2 "register_operand" "d"))]
 365          UNSPEC_SYNC_OLD_OP))]
 366   "GENERATE_LL_SC"
 367 {
 368   return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<d>subu"));
 369 }
 370   [(set_attr "length" "28")])
 371
 372 (define_insn "sync_new_add<mode>"
 373   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 374         (plus:GPR (match_operand:GPR 1 "memory_operand" "+R,R")
 375                   (match_operand:GPR 2 "arith_operand" "I,d")))
 376    (set (match_dup 1)
 377         (unspec_volatile:GPR
 378           [(plus:GPR (match_dup 1) (match_dup 2))]
 379          UNSPEC_SYNC_NEW_OP))]
 380   "GENERATE_LL_SC"
 381 {
 382   if (which_alternative == 0)
 383     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addiu"));
 384   else
 385     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>addu"));
 386 }
 387   [(set_attr "length" "28")])
 388
 389 (define_insn "sync_new_sub<mode>"
 390   [(set (match_operand:GPR 0 "register_operand" "=&d")
 391         (minus:GPR (match_operand:GPR 1 "memory_operand" "+R")
 392                    (match_operand:GPR 2 "register_operand" "d")))
 393    (set (match_dup 1)
 394         (unspec_volatile:GPR
 395           [(minus:GPR (match_dup 1) (match_dup 2))]
 396          UNSPEC_SYNC_NEW_OP))]
 397   "GENERATE_LL_SC"
 398 {
 399   return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<d>subu"));
 400 }
 401   [(set_attr "length" "28")])
 402
 403 (define_insn "sync_<optab><mode>"
 404   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
 405         (unspec_volatile:GPR
 406           [(fetchop_bit:GPR (match_operand:GPR 1 "uns_arith_operand" "K,d")
 407                               (match_dup 0))]
 408          UNSPEC_SYNC_OLD_OP))]
 409   "GENERATE_LL_SC"
 410 {
 411   if (which_alternative == 0)
 412     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<immediate_insn>"));
 413   else
 414     return mips_output_sync_loop (MIPS_SYNC_OP ("<d>", "<insn>"));
 415 }
 416   [(set_attr "length" "28")])
 417
 418 (define_insn "sync_old_<optab><mode>"
 419   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 420         (match_operand:GPR 1 "memory_operand" "+R,R"))
 421    (set (match_dup 1)
 422         (unspec_volatile:GPR
 423           [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
 424                             (match_dup 1))]
 425          UNSPEC_SYNC_OLD_OP))]
 426   "GENERATE_LL_SC"
 427 {
 428   if (which_alternative == 0)
 429     return (mips_output_sync_loop
 430             (MIPS_SYNC_OLD_OP ("<d>", "<immediate_insn>")));
 431   else
 432     return mips_output_sync_loop (MIPS_SYNC_OLD_OP ("<d>", "<insn>"));
 433 }
 434   [(set_attr "length" "28")])
 435
 436 (define_insn "sync_new_<optab><mode>"
 437   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 438         (match_operand:GPR 1 "memory_operand" "+R,R"))
 439    (set (match_dup 1)
 440         (unspec_volatile:GPR
 441           [(fetchop_bit:GPR (match_operand:GPR 2 "uns_arith_operand" "K,d")
 442                             (match_dup 1))]
 443          UNSPEC_SYNC_NEW_OP))]
 444   "GENERATE_LL_SC"
 445 {
 446   if (which_alternative == 0)
 447     return (mips_output_sync_loop
 448             (MIPS_SYNC_NEW_OP ("<d>", "<immediate_insn>")));
 449   else
 450     return mips_output_sync_loop (MIPS_SYNC_NEW_OP ("<d>", "<insn>"));
 451 }
 452   [(set_attr "length" "28")])
 453
 454 (define_insn "sync_nand<mode>"
 455   [(set (match_operand:GPR 0 "memory_operand" "+R,R")
 456         (unspec_volatile:GPR [(match_operand:GPR 1 "uns_arith_operand" "K,d")]
 457          UNSPEC_SYNC_OLD_OP))]
 458   "GENERATE_LL_SC"
 459 {
 460   if (which_alternative == 0)
 461     return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "andi"));
 462   else
 463     return mips_output_sync_loop (MIPS_SYNC_NAND ("<d>", "and"));
 464 }
 465   [(set_attr "length" "32")])
 466
 467 (define_insn "sync_old_nand<mode>"
 468   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 469         (match_operand:GPR 1 "memory_operand" "+R,R"))
 470    (set (match_dup 1)
 471         (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 472          UNSPEC_SYNC_OLD_OP))]
 473   "GENERATE_LL_SC"
 474 {
 475   if (which_alternative == 0)
 476     return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "andi"));
 477   else
 478     return mips_output_sync_loop (MIPS_SYNC_OLD_NAND ("<d>", "and"));
 479 }
 480   [(set_attr "length" "32")])
 481
 482 (define_insn "sync_new_nand<mode>"
 483   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 484         (match_operand:GPR 1 "memory_operand" "+R,R"))
 485    (set (match_dup 1)
 486         (unspec_volatile:GPR [(match_operand:GPR 2 "uns_arith_operand" "K,d")]
 487          UNSPEC_SYNC_NEW_OP))]
 488   "GENERATE_LL_SC"
 489 {
 490   if (which_alternative == 0)
 491     return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "andi"));
 492   else
 493     return mips_output_sync_loop (MIPS_SYNC_NEW_NAND ("<d>", "and"));
 494 }
 495   [(set_attr "length" "32")])
 496
 497 (define_insn "sync_lock_test_and_set<mode>"
 498   [(set (match_operand:GPR 0 "register_operand" "=&d,&d")
 499         (match_operand:GPR 1 "memory_operand" "+R,R"))
 500    (set (match_dup 1)
 501         (unspec_volatile:GPR [(match_operand:GPR 2 "arith_operand" "I,d")]
 502          UNSPEC_SYNC_EXCHANGE))]
 503   "GENERATE_LL_SC"
 504 {
 505   if (which_alternative == 0)
 506     return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "li"));
 507   else
 508     return mips_output_sync_loop (MIPS_SYNC_EXCHANGE ("<d>", "move"));
 509 }
 510   [(set_attr "length" "24")])
 511
 512 (define_expand "sync_lock_test_and_set<mode>"
 513   [(match_operand:SHORT 0 "register_operand")
 514    (match_operand:SHORT 1 "memory_operand")
 515    (match_operand:SHORT 2 "general_operand")]
 516   "GENERATE_LL_SC"
 517 {
 518   union mips_gen_fn_ptrs generator;
 519   generator.fn_5 = gen_test_and_set_12;
 520   mips_expand_atomic_qihi (generator,
 521                            operands[0], operands[1], operands[2], NULL);
 522   DONE;
 523 })
 524
 525 (define_insn "test_and_set_12"
 526   [(set (match_operand:SI 0 "register_operand" "=&d,&d")
 527         (match_operand:SI 1 "memory_operand" "+R,R"))
 528    (set (match_dup 1)
 529         (unspec_volatile:SI [(match_operand:SI 2 "register_operand" "d,d")
 530                              (match_operand:SI 3 "register_operand" "d,d")
 531                              (match_operand:SI 4 "arith_operand" "d,J")]
 532           UNSPEC_SYNC_EXCHANGE_12))]
 533   "GENERATE_LL_SC"
 534 {
 535   if (which_alternative == 0)
 536     return (mips_output_sync_loop
 537             (MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_NONZERO_OP)));
 538   else
 539     return (mips_output_sync_loop
 540             (MIPS_SYNC_EXCHANGE_12 (MIPS_SYNC_EXCHANGE_12_ZERO_OP)));
 541 }
 542   [(set_attr "length" "28,24")])