1 ;; Mips.md Machine Description for MIPS based processors
2 ;; Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 ;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
4 ;; Contributed by A. Lichnewsky, lich@inria.inria.fr
5 ;; Changes by Michael Meissner, meissner@osf.org
6 ;; 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
7 ;; Brendan Eich, brendan@microunity.com.
9 ;; This file is part of GCC.
11 ;; GCC is free software; you can redistribute it and/or modify
12 ;; it under the terms of the GNU General Public License as published by
13 ;; the Free Software Foundation; either version 2, or (at your option)
16 ;; GCC is distributed in the hope that it will be useful,
17 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
18 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 ;; GNU General Public License for more details.
21 ;; You should have received a copy of the GNU General Public License
22 ;; along with GCC; see the file COPYING. If not, write to
23 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
24 ;; Boston, MA 02111-1307, USA.
27 [(UNSPEC_LOAD_DF_LOW 0)
28 (UNSPEC_LOAD_DF_HIGH 1)
29 (UNSPEC_STORE_DF_HIGH 2)
33 (UNSPEC_EH_RECEIVER 6)
35 (UNSPEC_CONSTTABLE_INT 8)
36 (UNSPEC_CONSTTABLE_FLOAT 9)
40 (UNSPEC_LOAD_RIGHT 19)
41 (UNSPEC_STORE_LEFT 20)
42 (UNSPEC_STORE_RIGHT 21)
49 (UNSPEC_TLS_GET_TP 28)
51 (UNSPEC_ADDRESS_FIRST 100)
55 ;; For MIPS Paired-Singled Floating Point Instructions.
57 (UNSPEC_MOVE_TF_PS 200)
60 ;; MIPS64/MIPS32R2 alnv.ps
63 ;; MIPS-3D instructions
67 (UNSPEC_CVT_PW_PS 205)
68 (UNSPEC_CVT_PS_PW 206)
78 (include "predicates.md")
80 ;; ....................
84 ;; ....................
86 (define_attr "got" "unset,xgot_high,load"
87 (const_string "unset"))
89 ;; For jal instructions, this attribute is DIRECT when the target address
90 ;; is symbolic and INDIRECT when it is a register.
91 (define_attr "jal" "unset,direct,indirect"
92 (const_string "unset"))
94 ;; This attribute is YES if the instruction is a jal macro (not a
95 ;; real jal instruction).
97 ;; jal is always a macro in SVR4 PIC since it includes an instruction to
98 ;; restore $gp. Direct jals are also macros in NewABI PIC since they
99 ;; load the target address into $25.
100 (define_attr "jal_macro" "no,yes"
101 (cond [(eq_attr "jal" "direct")
102 (symbol_ref "TARGET_ABICALLS != 0")
103 (eq_attr "jal" "indirect")
104 (symbol_ref "(TARGET_ABICALLS && !TARGET_NEWABI) != 0")]
105 (const_string "no")))
107 ;; Classification of each insn.
108 ;; branch conditional branch
109 ;; jump unconditional jump
110 ;; call unconditional call
111 ;; load load instruction(s)
112 ;; fpload floating point load
113 ;; fpidxload floating point indexed load
114 ;; store store instruction(s)
115 ;; fpstore floating point store
116 ;; fpidxstore floating point indexed store
117 ;; prefetch memory prefetch (register + offset)
118 ;; prefetchx memory indexed prefetch (register + register)
119 ;; condmove conditional moves
120 ;; xfer transfer to/from coprocessor
121 ;; mthilo transfer to hi/lo registers
122 ;; mfhilo transfer from hi/lo registers
123 ;; const load constant
124 ;; arith integer arithmetic and logical instructions
125 ;; shift integer shift instructions
126 ;; slt set less than instructions
127 ;; clz the clz and clo instructions
128 ;; trap trap if instructions
129 ;; imul integer multiply 2 operands
130 ;; imul3 integer multiply 3 operands
131 ;; imadd integer multiply-add
132 ;; idiv integer divide
133 ;; fmove floating point register move
134 ;; fadd floating point add/subtract
135 ;; fmul floating point multiply
136 ;; fmadd floating point multiply-add
137 ;; fdiv floating point divide
138 ;; frdiv floating point reciprocal divide
139 ;; frdiv1 floating point reciprocal divide step 1
140 ;; frdiv2 floating point reciprocal divide step 2
141 ;; fabs floating point absolute value
142 ;; fneg floating point negation
143 ;; fcmp floating point compare
144 ;; fcvt floating point convert
145 ;; fsqrt floating point square root
146 ;; frsqrt floating point reciprocal square root
147 ;; frsqrt1 floating point reciprocal square root step1
148 ;; frsqrt2 floating point reciprocal square root step2
149 ;; multi multiword sequence (or user asm statements)
152 "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,prefetch,prefetchx,condmove,xfer,mthilo,mfhilo,const,arith,shift,slt,clz,trap,imul,imul3,imadd,idiv,fmove,fadd,fmul,fmadd,fdiv,frdiv,frdiv1,frdiv2,fabs,fneg,fcmp,fcvt,fsqrt,frsqrt,frsqrt1,frsqrt2,multi,nop"
153 (cond [(eq_attr "jal" "!unset") (const_string "call")
154 (eq_attr "got" "load") (const_string "load")]
155 (const_string "unknown")))
157 ;; Main data type used by the insn
158 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
159 (const_string "unknown"))
161 ;; Mode for conversion types (fcvt)
162 ;; I2S integer to float single (SI/DI to SF)
163 ;; I2D integer to float double (SI/DI to DF)
164 ;; S2I float to integer (SF to SI/DI)
165 ;; D2I float to integer (DF to SI/DI)
166 ;; D2S double to float single
167 ;; S2D float single to double
169 (define_attr "cnv_mode" "unknown,I2S,I2D,S2I,D2I,D2S,S2D"
170 (const_string "unknown"))
172 ;; Is this an extended instruction in mips16 mode?
173 (define_attr "extended_mips16" "no,yes"
176 ;; Length of instruction in bytes.
177 (define_attr "length" ""
178 (cond [;; Direct branch instructions have a range of [-0x40000,0x3fffc].
179 ;; If a branch is outside this range, we have a choice of two
180 ;; sequences. For PIC, an out-of-range branch like:
185 ;; becomes the equivalent of:
194 ;; where the load address can be up to three instructions long
197 ;; The non-PIC case is similar except that we use a direct
198 ;; jump instead of an la/jr pair. Since the target of this
199 ;; jump is an absolute 28-bit bit address (the other bits
200 ;; coming from the address of the delay slot) this form cannot
201 ;; cross a 256MB boundary. We could provide the option of
202 ;; using la/jr in this case too, but we do not do so at
205 ;; Note that this value does not account for the delay slot
206 ;; instruction, whose length is added separately. If the RTL
207 ;; pattern has no explicit delay slot, mips_adjust_insn_length
208 ;; will add the length of the implicit nop. The values for
209 ;; forward and backward branches will be different as well.
210 (eq_attr "type" "branch")
211 (cond [(and (le (minus (match_dup 1) (pc)) (const_int 131064))
212 (le (minus (pc) (match_dup 1)) (const_int 131068)))
214 (ne (symbol_ref "flag_pic") (const_int 0))
218 (eq_attr "got" "load")
220 (eq_attr "got" "xgot_high")
223 (eq_attr "type" "const")
224 (symbol_ref "mips_const_insns (operands[1]) * 4")
225 (eq_attr "type" "load,fpload")
226 (symbol_ref "mips_fetch_insns (operands[1]) * 4")
227 (eq_attr "type" "store,fpstore")
228 (symbol_ref "mips_fetch_insns (operands[0]) * 4")
230 ;; In the worst case, a call macro will take 8 instructions:
232 ;; lui $25,%call_hi(FOO)
234 ;; lw $25,%call_lo(FOO)($25)
240 (eq_attr "jal_macro" "yes")
243 (and (eq_attr "extended_mips16" "yes")
244 (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
247 ;; Various VR4120 errata require a nop to be inserted after a macc
248 ;; instruction. The assembler does this for us, so account for
249 ;; the worst-case length here.
250 (and (eq_attr "type" "imadd")
251 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0)))
254 ;; VR4120 errata MD(4): if there are consecutive dmult instructions,
255 ;; the result of the second one is missed. The assembler should work
256 ;; around this by inserting a nop after the first dmult.
257 (and (eq_attr "type" "imul,imul3")
258 (and (eq_attr "mode" "DI")
259 (ne (symbol_ref "TARGET_FIX_VR4120") (const_int 0))))
262 (eq_attr "type" "idiv")
263 (symbol_ref "mips_idiv_insns () * 4")
266 ;; Attribute describing the processor. This attribute must match exactly
267 ;; with the processor_type enumeration in mips.h.
269 "default,4kc,4kp,5kc,20kc,24k,24kx,m4k,r3000,r3900,r6000,r4000,r4100,r4111,r4120,r4130,r4300,r4600,r4650,r5000,r5400,r5500,r7000,r8000,r9000,sb1,sr71000"
270 (const (symbol_ref "mips_tune")))
272 ;; The type of hardware hazard associated with this instruction.
273 ;; DELAY means that the next instruction cannot read the result
274 ;; of this one. HILO means that the next two instructions cannot
275 ;; write to HI or LO.
276 (define_attr "hazard" "none,delay,hilo"
277 (cond [(and (eq_attr "type" "load,fpload,fpidxload")
278 (ne (symbol_ref "ISA_HAS_LOAD_DELAY") (const_int 0)))
279 (const_string "delay")
281 (and (eq_attr "type" "xfer")
282 (ne (symbol_ref "ISA_HAS_XFER_DELAY") (const_int 0)))
283 (const_string "delay")
285 (and (eq_attr "type" "fcmp")
286 (ne (symbol_ref "ISA_HAS_FCMP_DELAY") (const_int 0)))
287 (const_string "delay")
289 ;; The r4000 multiplication patterns include an mflo instruction.
290 (and (eq_attr "type" "imul")
291 (ne (symbol_ref "TARGET_FIX_R4000") (const_int 0)))
292 (const_string "hilo")
294 (and (eq_attr "type" "mfhilo")
295 (eq (symbol_ref "ISA_HAS_HILO_INTERLOCKS") (const_int 0)))
296 (const_string "hilo")]
297 (const_string "none")))
299 ;; Is it a single instruction?
300 (define_attr "single_insn" "no,yes"
301 (symbol_ref "get_attr_length (insn) == (TARGET_MIPS16 ? 2 : 4)"))
303 ;; Can the instruction be put into a delay slot?
304 (define_attr "can_delay" "no,yes"
305 (if_then_else (and (eq_attr "type" "!branch,call,jump")
306 (and (eq_attr "hazard" "none")
307 (eq_attr "single_insn" "yes")))
309 (const_string "no")))
311 ;; Attribute defining whether or not we can use the branch-likely instructions
312 (define_attr "branch_likely" "no,yes"
314 (if_then_else (ne (symbol_ref "GENERATE_BRANCHLIKELY") (const_int 0))
316 (const_string "no"))))
318 ;; True if an instruction might assign to hi or lo when reloaded.
319 ;; This is used by the TUNE_MACC_CHAINS code.
320 (define_attr "may_clobber_hilo" "no,yes"
321 (if_then_else (eq_attr "type" "imul,imul3,imadd,idiv,mthilo")
323 (const_string "no")))
325 ;; Describe a user's asm statement.
326 (define_asm_attributes
327 [(set_attr "type" "multi")
328 (set_attr "can_delay" "no")])
330 ;; This mode macro allows 32-bit and 64-bit GPR patterns to be generated
331 ;; from the same template.
332 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
334 ;; This mode macro allows :P to be used for patterns that operate on
335 ;; pointer-sized quantities. Exactly one of the two alternatives will match.
336 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
338 ;; This mode macro allows :MOVECC to be used anywhere that a
339 ;; conditional-move-type condition is needed.
340 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
342 ;; This mode macro allows the QI and HI extension patterns to be defined from
343 ;; the same template.
344 (define_mode_macro SHORT [QI HI])
346 ;; This mode macro allows :ANYF to be used wherever a scalar or vector
347 ;; floating-point mode is allowed.
348 (define_mode_macro ANYF [(SF "TARGET_HARD_FLOAT")
349 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")
350 (V2SF "TARGET_PAIRED_SINGLE_FLOAT")])
352 ;; Like ANYF, but only applies to scalar modes.
353 (define_mode_macro SCALARF [(SF "TARGET_HARD_FLOAT")
354 (DF "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT")])
356 ;; In GPR templates, a string like "<d>subu" will expand to "subu" in the
357 ;; 32-bit version and "dsubu" in the 64-bit version.
358 (define_mode_attr d [(SI "") (DI "d")])
360 ;; This attribute gives the length suffix for a sign- or zero-extension
362 (define_mode_attr size [(QI "b") (HI "h")])
364 ;; This attributes gives the mode mask of a SHORT.
365 (define_mode_attr mask [(QI "0x00ff") (HI "0xffff")])
367 ;; Mode attributes for GPR loads and stores.
368 (define_mode_attr load [(SI "lw") (DI "ld")])
369 (define_mode_attr store [(SI "sw") (DI "sd")])
371 ;; Similarly for MIPS IV indexed FPR loads and stores.
372 (define_mode_attr loadx [(SF "lwxc1") (DF "ldxc1") (V2SF "ldxc1")])
373 (define_mode_attr storex [(SF "swxc1") (DF "sdxc1") (V2SF "sdxc1")])
375 ;; The unextended ranges of the MIPS16 addiu and daddiu instructions
376 ;; are different. Some forms of unextended addiu have an 8-bit immediate
377 ;; field but the equivalent daddiu has only a 5-bit field.
378 (define_mode_attr si8_di5 [(SI "8") (DI "5")])
380 ;; This attribute gives the best constraint to use for registers of
382 (define_mode_attr reg [(SI "d") (DI "d") (CC "z")])
384 ;; This attribute gives the format suffix for floating-point operations.
385 (define_mode_attr fmt [(SF "s") (DF "d") (V2SF "ps")])
387 ;; This attribute gives the upper-case mode name for one unit of a
388 ;; floating-point mode.
389 (define_mode_attr UNITMODE [(SF "SF") (DF "DF") (V2SF "SF")])
391 ;; This attribute works around the early SB-1 rev2 core "F2" erratum:
393 ;; In certain cases, div.s and div.ps may have a rounding error
394 ;; and/or wrong inexact flag.
396 ;; Therefore, we only allow div.s if not working around SB-1 rev2
397 ;; errata or if a slight loss of precision is OK.
398 (define_mode_attr divide_condition
399 [DF (SF "!TARGET_FIX_SB1 || flag_unsafe_math_optimizations")
400 (V2SF "TARGET_SB1 && (!TARGET_FIX_SB1 || flag_unsafe_math_optimizations)")])
402 ; This attribute gives the condition for which sqrt instructions exist.
403 (define_mode_attr sqrt_condition
404 [(SF "!ISA_MIPS1") (DF "!ISA_MIPS1") (V2SF "TARGET_SB1")])
406 ; This attribute gives the condition for which recip and rsqrt instructions
408 (define_mode_attr recip_condition
409 [(SF "ISA_HAS_FP4") (DF "ISA_HAS_FP4") (V2SF "TARGET_SB1")])
411 ;; This code macro allows all branch instructions to be generated from
412 ;; a single define_expand template.
413 (define_code_macro any_cond [unordered ordered unlt unge uneq ltgt unle ungt
414 eq ne gt ge lt le gtu geu ltu leu])
416 ;; This code macro allows signed and unsigned widening multiplications
417 ;; to use the same template.
418 (define_code_macro any_extend [sign_extend zero_extend])
420 ;; This code macro allows the three shift instructions to be generated
421 ;; from the same template.
422 (define_code_macro any_shift [ashift ashiftrt lshiftrt])
424 ;; This code macro allows all native floating-point comparisons to be
425 ;; generated from the same template.
426 (define_code_macro fcond [unordered uneq unlt unle eq lt le])
428 ;; This code macro is used for comparisons that can be implemented
429 ;; by swapping the operands.
430 (define_code_macro swapped_fcond [ge gt unge ungt])
432 ;; <u> expands to an empty string when doing a signed operation and
433 ;; "u" when doing an unsigned operation.
434 (define_code_attr u [(sign_extend "") (zero_extend "u")])
436 ;; <su> is like <u>, but the signed form expands to "s" rather than "".
437 (define_code_attr su [(sign_extend "s") (zero_extend "u")])
439 ;; <optab> expands to the name of the optab for a particular code.
440 (define_code_attr optab [(ashift "ashl")
444 ;; <insn> expands to the name of the insn that implements a particular code.
445 (define_code_attr insn [(ashift "sll")
449 ;; <fcond> is the c.cond.fmt condition associated with a particular code.
450 (define_code_attr fcond [(unordered "un")
458 ;; Similar, but for swapped conditions.
459 (define_code_attr swapped_fcond [(ge "le")
464 ;; .........................
466 ;; Branch, call and jump delay slots
468 ;; .........................
470 (define_delay (and (eq_attr "type" "branch")
471 (eq (symbol_ref "TARGET_MIPS16") (const_int 0)))
472 [(eq_attr "can_delay" "yes")
474 (and (eq_attr "branch_likely" "yes")
475 (eq_attr "can_delay" "yes"))])
477 (define_delay (eq_attr "type" "jump")
478 [(eq_attr "can_delay" "yes")
482 (define_delay (and (eq_attr "type" "call")
483 (eq_attr "jal_macro" "no"))
484 [(eq_attr "can_delay" "yes")
488 ;; Pipeline descriptions.
490 ;; generic.md provides a fallback for processors without a specific
491 ;; pipeline description. It is derived from the old define_function_unit
492 ;; version and uses the "alu" and "imuldiv" units declared below.
494 ;; Some of the processor-specific files are also derived from old
495 ;; define_function_unit descriptions and simply override the parts of
496 ;; generic.md that don't apply. The other processor-specific files
497 ;; are self-contained.
498 (define_automaton "alu,imuldiv")
500 (define_cpu_unit "alu" "alu")
501 (define_cpu_unit "imuldiv" "imuldiv")
519 (include "generic.md")
522 ;; ....................
526 ;; ....................
530 [(trap_if (const_int 1) (const_int 0))]
533 if (ISA_HAS_COND_TRAP)
535 else if (TARGET_MIPS16)
540 [(set_attr "type" "trap")])
542 (define_expand "conditional_trap"
543 [(trap_if (match_operator 0 "comparison_operator"
544 [(match_dup 2) (match_dup 3)])
545 (match_operand 1 "const_int_operand"))]
548 if (GET_MODE_CLASS (GET_MODE (cmp_operands[0])) == MODE_INT
549 && operands[1] == const0_rtx)
551 mips_gen_conditional_trap (operands);
558 (define_insn "*conditional_trap<mode>"
559 [(trap_if (match_operator:GPR 0 "trap_comparison_operator"
560 [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
561 (match_operand:GPR 2 "arith_operand" "dI")])
565 [(set_attr "type" "trap")])
568 ;; ....................
572 ;; ....................
575 (define_insn "add<mode>3"
576 [(set (match_operand:ANYF 0 "register_operand" "=f")
577 (plus:ANYF (match_operand:ANYF 1 "register_operand" "f")
578 (match_operand:ANYF 2 "register_operand" "f")))]
580 "add.<fmt>\t%0,%1,%2"
581 [(set_attr "type" "fadd")
582 (set_attr "mode" "<UNITMODE>")])
584 (define_expand "add<mode>3"
585 [(set (match_operand:GPR 0 "register_operand")
586 (plus:GPR (match_operand:GPR 1 "register_operand")
587 (match_operand:GPR 2 "arith_operand")))]
590 (define_insn "*add<mode>3"
591 [(set (match_operand:GPR 0 "register_operand" "=d,d")
592 (plus:GPR (match_operand:GPR 1 "register_operand" "d,d")
593 (match_operand:GPR 2 "arith_operand" "d,Q")))]
598 [(set_attr "type" "arith")
599 (set_attr "mode" "<MODE>")])
601 ;; We need to recognize MIPS16 stack pointer additions explicitly, since
602 ;; we don't have a constraint for $sp. These insns will be generated by
603 ;; the save_restore_insns functions.
605 (define_insn "*add<mode>3_sp1"
607 (plus:GPR (reg:GPR 29)
608 (match_operand:GPR 0 "const_arith_operand" "")))]
611 [(set_attr "type" "arith")
612 (set_attr "mode" "<MODE>")
613 (set (attr "length") (if_then_else (match_operand 0 "m16_simm8_8")
617 (define_insn "*add<mode>3_sp2"
618 [(set (match_operand:GPR 0 "register_operand" "=d")
619 (plus:GPR (reg:GPR 29)
620 (match_operand:GPR 1 "const_arith_operand" "")))]
623 [(set_attr "type" "arith")
624 (set_attr "mode" "<MODE>")
625 (set (attr "length") (if_then_else (match_operand 1 "m16_uimm<si8_di5>_4")
629 (define_insn "*add<mode>3_mips16"
630 [(set (match_operand:GPR 0 "register_operand" "=d,d,d")
631 (plus:GPR (match_operand:GPR 1 "register_operand" "0,d,d")
632 (match_operand:GPR 2 "arith_operand" "Q,O,d")))]
638 [(set_attr "type" "arith")
639 (set_attr "mode" "<MODE>")
640 (set_attr_alternative "length"
641 [(if_then_else (match_operand 2 "m16_simm<si8_di5>_1")
644 (if_then_else (match_operand 2 "m16_simm4_1")
650 ;; On the mips16, we can sometimes split an add of a constant which is
651 ;; a 4 byte instruction into two adds which are both 2 byte
652 ;; instructions. There are two cases: one where we are adding a
653 ;; constant plus a register to another register, and one where we are
654 ;; simply adding a constant to a register.
657 [(set (match_operand:SI 0 "register_operand")
658 (plus:SI (match_dup 0)
659 (match_operand:SI 1 "const_int_operand")))]
660 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
661 && REG_P (operands[0])
662 && M16_REG_P (REGNO (operands[0]))
663 && GET_CODE (operands[1]) == CONST_INT
664 && ((INTVAL (operands[1]) > 0x7f
665 && INTVAL (operands[1]) <= 0x7f + 0x7f)
666 || (INTVAL (operands[1]) < - 0x80
667 && INTVAL (operands[1]) >= - 0x80 - 0x80))"
668 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
669 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
671 HOST_WIDE_INT val = INTVAL (operands[1]);
675 operands[1] = GEN_INT (0x7f);
676 operands[2] = GEN_INT (val - 0x7f);
680 operands[1] = GEN_INT (- 0x80);
681 operands[2] = GEN_INT (val + 0x80);
686 [(set (match_operand:SI 0 "register_operand")
687 (plus:SI (match_operand:SI 1 "register_operand")
688 (match_operand:SI 2 "const_int_operand")))]
689 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
690 && REG_P (operands[0])
691 && M16_REG_P (REGNO (operands[0]))
692 && REG_P (operands[1])
693 && M16_REG_P (REGNO (operands[1]))
694 && REGNO (operands[0]) != REGNO (operands[1])
695 && GET_CODE (operands[2]) == CONST_INT
696 && ((INTVAL (operands[2]) > 0x7
697 && INTVAL (operands[2]) <= 0x7 + 0x7f)
698 || (INTVAL (operands[2]) < - 0x8
699 && INTVAL (operands[2]) >= - 0x8 - 0x80))"
700 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))
701 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 3)))]
703 HOST_WIDE_INT val = INTVAL (operands[2]);
707 operands[2] = GEN_INT (0x7);
708 operands[3] = GEN_INT (val - 0x7);
712 operands[2] = GEN_INT (- 0x8);
713 operands[3] = GEN_INT (val + 0x8);
718 [(set (match_operand:DI 0 "register_operand")
719 (plus:DI (match_dup 0)
720 (match_operand:DI 1 "const_int_operand")))]
721 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
722 && REG_P (operands[0])
723 && M16_REG_P (REGNO (operands[0]))
724 && GET_CODE (operands[1]) == CONST_INT
725 && ((INTVAL (operands[1]) > 0xf
726 && INTVAL (operands[1]) <= 0xf + 0xf)
727 || (INTVAL (operands[1]) < - 0x10
728 && INTVAL (operands[1]) >= - 0x10 - 0x10))"
729 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
730 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
732 HOST_WIDE_INT val = INTVAL (operands[1]);
736 operands[1] = GEN_INT (0xf);
737 operands[2] = GEN_INT (val - 0xf);
741 operands[1] = GEN_INT (- 0x10);
742 operands[2] = GEN_INT (val + 0x10);
747 [(set (match_operand:DI 0 "register_operand")
748 (plus:DI (match_operand:DI 1 "register_operand")
749 (match_operand:DI 2 "const_int_operand")))]
750 "TARGET_MIPS16 && TARGET_64BIT && reload_completed && !TARGET_DEBUG_D_MODE
751 && REG_P (operands[0])
752 && M16_REG_P (REGNO (operands[0]))
753 && REG_P (operands[1])
754 && M16_REG_P (REGNO (operands[1]))
755 && REGNO (operands[0]) != REGNO (operands[1])
756 && GET_CODE (operands[2]) == CONST_INT
757 && ((INTVAL (operands[2]) > 0x7
758 && INTVAL (operands[2]) <= 0x7 + 0xf)
759 || (INTVAL (operands[2]) < - 0x8
760 && INTVAL (operands[2]) >= - 0x8 - 0x10))"
761 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))
762 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))]
764 HOST_WIDE_INT val = INTVAL (operands[2]);
768 operands[2] = GEN_INT (0x7);
769 operands[3] = GEN_INT (val - 0x7);
773 operands[2] = GEN_INT (- 0x8);
774 operands[3] = GEN_INT (val + 0x8);
778 (define_insn "*addsi3_extended"
779 [(set (match_operand:DI 0 "register_operand" "=d,d")
781 (plus:SI (match_operand:SI 1 "register_operand" "d,d")
782 (match_operand:SI 2 "arith_operand" "d,Q"))))]
783 "TARGET_64BIT && !TARGET_MIPS16"
787 [(set_attr "type" "arith")
788 (set_attr "mode" "SI")])
790 ;; Split this insn so that the addiu splitters can have a crack at it.
791 ;; Use a conservative length estimate until the split.
792 (define_insn_and_split "*addsi3_extended_mips16"
793 [(set (match_operand:DI 0 "register_operand" "=d,d,d")
795 (plus:SI (match_operand:SI 1 "register_operand" "0,d,d")
796 (match_operand:SI 2 "arith_operand" "Q,O,d"))))]
797 "TARGET_64BIT && TARGET_MIPS16"
799 "&& reload_completed"
800 [(set (match_dup 3) (plus:SI (match_dup 1) (match_dup 2)))]
801 { operands[3] = gen_lowpart (SImode, operands[0]); }
802 [(set_attr "type" "arith")
803 (set_attr "mode" "SI")
804 (set_attr "extended_mips16" "yes")])
807 ;; ....................
811 ;; ....................
814 (define_insn "sub<mode>3"
815 [(set (match_operand:ANYF 0 "register_operand" "=f")
816 (minus:ANYF (match_operand:ANYF 1 "register_operand" "f")
817 (match_operand:ANYF 2 "register_operand" "f")))]
819 "sub.<fmt>\t%0,%1,%2"
820 [(set_attr "type" "fadd")
821 (set_attr "mode" "<UNITMODE>")])
823 (define_insn "sub<mode>3"
824 [(set (match_operand:GPR 0 "register_operand" "=d")
825 (minus:GPR (match_operand:GPR 1 "register_operand" "d")
826 (match_operand:GPR 2 "register_operand" "d")))]
829 [(set_attr "type" "arith")
830 (set_attr "mode" "<MODE>")])
832 (define_insn "*subsi3_extended"
833 [(set (match_operand:DI 0 "register_operand" "=d")
835 (minus:SI (match_operand:SI 1 "register_operand" "d")
836 (match_operand:SI 2 "register_operand" "d"))))]
839 [(set_attr "type" "arith")
840 (set_attr "mode" "DI")])
843 ;; ....................
847 ;; ....................
850 (define_expand "mul<mode>3"
851 [(set (match_operand:SCALARF 0 "register_operand")
852 (mult:SCALARF (match_operand:SCALARF 1 "register_operand")
853 (match_operand:SCALARF 2 "register_operand")))]
857 (define_insn "*mul<mode>3"
858 [(set (match_operand:SCALARF 0 "register_operand" "=f")
859 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
860 (match_operand:SCALARF 2 "register_operand" "f")))]
861 "!TARGET_4300_MUL_FIX"
862 "mul.<fmt>\t%0,%1,%2"
863 [(set_attr "type" "fmul")
864 (set_attr "mode" "<MODE>")])
866 ;; Early VR4300 silicon has a CPU bug where multiplies with certain
867 ;; operands may corrupt immediately following multiplies. This is a
868 ;; simple fix to insert NOPs.
870 (define_insn "*mul<mode>3_r4300"
871 [(set (match_operand:SCALARF 0 "register_operand" "=f")
872 (mult:SCALARF (match_operand:SCALARF 1 "register_operand" "f")
873 (match_operand:SCALARF 2 "register_operand" "f")))]
874 "TARGET_4300_MUL_FIX"
875 "mul.<fmt>\t%0,%1,%2\;nop"
876 [(set_attr "type" "fmul")
877 (set_attr "mode" "<MODE>")
878 (set_attr "length" "8")])
880 (define_insn "mulv2sf3"
881 [(set (match_operand:V2SF 0 "register_operand" "=f")
882 (mult:V2SF (match_operand:V2SF 1 "register_operand" "f")
883 (match_operand:V2SF 2 "register_operand" "f")))]
884 "TARGET_PAIRED_SINGLE_FLOAT"
886 [(set_attr "type" "fmul")
887 (set_attr "mode" "SF")])
889 ;; The original R4000 has a cpu bug. If a double-word or a variable
890 ;; shift executes while an integer multiplication is in progress, the
891 ;; shift may give an incorrect result. Avoid this by keeping the mflo
892 ;; with the mult on the R4000.
894 ;; From "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0"
895 ;; (also valid for MIPS R4000MC processors):
897 ;; "16. R4000PC, R4000SC: Please refer to errata 28 for an update to
898 ;; this errata description.
899 ;; The following code sequence causes the R4000 to incorrectly
900 ;; execute the Double Shift Right Arithmetic 32 (dsra32)
901 ;; instruction. If the dsra32 instruction is executed during an
902 ;; integer multiply, the dsra32 will only shift by the amount in
903 ;; specified in the instruction rather than the amount plus 32
905 ;; instruction 1: mult rs,rt integer multiply
906 ;; instruction 2-12: dsra32 rd,rt,rs doubleword shift
907 ;; right arithmetic + 32
908 ;; Workaround: A dsra32 instruction placed after an integer
909 ;; multiply should not be one of the 11 instructions after the
910 ;; multiply instruction."
914 ;; "28. R4000PC, R4000SC: The text from errata 16 should be replaced by
915 ;; the following description.
916 ;; All extended shifts (shift by n+32) and variable shifts (32 and
917 ;; 64-bit versions) may produce incorrect results under the
918 ;; following conditions:
919 ;; 1) An integer multiply is currently executing
920 ;; 2) These types of shift instructions are executed immediately
921 ;; following an integer divide instruction.
923 ;; 1) Make sure no integer multiply is running wihen these
924 ;; instruction are executed. If this cannot be predicted at
925 ;; compile time, then insert a "mfhi" to R0 instruction
926 ;; immediately after the integer multiply instruction. This
927 ;; will cause the integer multiply to complete before the shift
929 ;; 2) Separate integer divide and these two classes of shift
930 ;; instructions by another instruction or a noop."
932 ;; These processors have PRId values of 0x00004220 and 0x00004300,
935 (define_expand "mul<mode>3"
936 [(set (match_operand:GPR 0 "register_operand")
937 (mult:GPR (match_operand:GPR 1 "register_operand")
938 (match_operand:GPR 2 "register_operand")))]
941 if (GENERATE_MULT3_<MODE>)
942 emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
943 else if (!TARGET_FIX_R4000)
944 emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
947 emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
951 (define_insn "mulsi3_mult3"
952 [(set (match_operand:SI 0 "register_operand" "=d,l")
953 (mult:SI (match_operand:SI 1 "register_operand" "d,d")
954 (match_operand:SI 2 "register_operand" "d,d")))
955 (clobber (match_scratch:SI 3 "=h,h"))
956 (clobber (match_scratch:SI 4 "=l,X"))]
959 if (which_alternative == 1)
960 return "mult\t%1,%2";
969 return "mul\t%0,%1,%2";
970 return "mult\t%0,%1,%2";
972 [(set_attr "type" "imul3,imul")
973 (set_attr "mode" "SI")])
975 (define_insn "muldi3_mult3"
976 [(set (match_operand:DI 0 "register_operand" "=d")
977 (mult:DI (match_operand:DI 1 "register_operand" "d")
978 (match_operand:DI 2 "register_operand" "d")))
979 (clobber (match_scratch:DI 3 "=h"))
980 (clobber (match_scratch:DI 4 "=l"))]
981 "TARGET_64BIT && GENERATE_MULT3_DI"
983 [(set_attr "type" "imul3")
984 (set_attr "mode" "DI")])
986 ;; If a register gets allocated to LO, and we spill to memory, the reload
987 ;; will include a move from LO to a GPR. Merge it into the multiplication
988 ;; if it can set the GPR directly.
991 ;; Operand 1: GPR (1st multiplication operand)
992 ;; Operand 2: GPR (2nd multiplication operand)
994 ;; Operand 4: GPR (destination)
997 [(set (match_operand:SI 0 "register_operand")
998 (mult:SI (match_operand:SI 1 "register_operand")
999 (match_operand:SI 2 "register_operand")))
1000 (clobber (match_operand:SI 3 "register_operand"))
1001 (clobber (scratch:SI))])
1002 (set (match_operand:SI 4 "register_operand")
1003 (unspec [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1004 "GENERATE_MULT3_SI && peep2_reg_dead_p (2, operands[0])"
1007 (mult:SI (match_dup 1)
1009 (clobber (match_dup 3))
1010 (clobber (match_dup 0))])])
1012 (define_insn "mul<mode>3_internal"
1013 [(set (match_operand:GPR 0 "register_operand" "=l")
1014 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1015 (match_operand:GPR 2 "register_operand" "d")))
1016 (clobber (match_scratch:GPR 3 "=h"))]
1019 [(set_attr "type" "imul")
1020 (set_attr "mode" "<MODE>")])
1022 (define_insn "mul<mode>3_r4000"
1023 [(set (match_operand:GPR 0 "register_operand" "=d")
1024 (mult:GPR (match_operand:GPR 1 "register_operand" "d")
1025 (match_operand:GPR 2 "register_operand" "d")))
1026 (clobber (match_scratch:GPR 3 "=h"))
1027 (clobber (match_scratch:GPR 4 "=l"))]
1029 "<d>mult\t%1,%2\;mflo\t%0"
1030 [(set_attr "type" "imul")
1031 (set_attr "mode" "<MODE>")
1032 (set_attr "length" "8")])
1034 ;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
1035 ;; of "mult; mflo". They have the same latency, but the first form gives
1036 ;; us an extra cycle to compute the operands.
1039 ;; Operand 1: GPR (1st multiplication operand)
1040 ;; Operand 2: GPR (2nd multiplication operand)
1042 ;; Operand 4: GPR (destination)
1045 [(set (match_operand:SI 0 "register_operand")
1046 (mult:SI (match_operand:SI 1 "register_operand")
1047 (match_operand:SI 2 "register_operand")))
1048 (clobber (match_operand:SI 3 "register_operand"))])
1049 (set (match_operand:SI 4 "register_operand")
1050 (unspec:SI [(match_dup 0) (match_dup 3)] UNSPEC_MFHILO))]
1051 "ISA_HAS_MACC && !GENERATE_MULT3_SI"
1056 (plus:SI (mult:SI (match_dup 1)
1060 (plus:SI (mult:SI (match_dup 1)
1063 (clobber (match_dup 3))])])
1065 ;; Multiply-accumulate patterns
1067 ;; For processors that can copy the output to a general register:
1069 ;; The all-d alternative is needed because the combiner will find this
1070 ;; pattern and then register alloc/reload will move registers around to
1071 ;; make them fit, and we don't want to trigger unnecessary loads to LO.
1073 ;; The last alternative should be made slightly less desirable, but adding
1074 ;; "?" to the constraint is too strong, and causes values to be loaded into
1075 ;; LO even when that's more costly. For now, using "*d" mostly does the
1077 (define_insn "*mul_acc_si"
1078 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1079 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d,d")
1080 (match_operand:SI 2 "register_operand" "d,d,d"))
1081 (match_operand:SI 3 "register_operand" "0,l,*d")))
1082 (clobber (match_scratch:SI 4 "=h,h,h"))
1083 (clobber (match_scratch:SI 5 "=X,3,l"))
1084 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1086 || ISA_HAS_MADD_MSUB)
1089 static const char *const madd[] = { "madd\t%1,%2", "madd\t%0,%1,%2" };
1090 if (which_alternative == 2)
1092 if (ISA_HAS_MADD_MSUB && which_alternative != 0)
1094 return madd[which_alternative];
1096 [(set_attr "type" "imadd,imadd,multi")
1097 (set_attr "mode" "SI")
1098 (set_attr "length" "4,4,8")])
1100 ;; Split the above insn if we failed to get LO allocated.
1102 [(set (match_operand:SI 0 "register_operand")
1103 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1104 (match_operand:SI 2 "register_operand"))
1105 (match_operand:SI 3 "register_operand")))
1106 (clobber (match_scratch:SI 4))
1107 (clobber (match_scratch:SI 5))
1108 (clobber (match_scratch:SI 6))]
1109 "reload_completed && !TARGET_DEBUG_D_MODE
1110 && GP_REG_P (true_regnum (operands[0]))
1111 && GP_REG_P (true_regnum (operands[3]))"
1112 [(parallel [(set (match_dup 6)
1113 (mult:SI (match_dup 1) (match_dup 2)))
1114 (clobber (match_dup 4))
1115 (clobber (match_dup 5))])
1116 (set (match_dup 0) (plus:SI (match_dup 6) (match_dup 3)))]
1119 ;; Splitter to copy result of MADD to a general register
1121 [(set (match_operand:SI 0 "register_operand")
1122 (plus:SI (mult:SI (match_operand:SI 1 "register_operand")
1123 (match_operand:SI 2 "register_operand"))
1124 (match_operand:SI 3 "register_operand")))
1125 (clobber (match_scratch:SI 4))
1126 (clobber (match_scratch:SI 5))
1127 (clobber (match_scratch:SI 6))]
1128 "reload_completed && !TARGET_DEBUG_D_MODE
1129 && GP_REG_P (true_regnum (operands[0]))
1130 && true_regnum (operands[3]) == LO_REGNUM"
1131 [(parallel [(set (match_dup 3)
1132 (plus:SI (mult:SI (match_dup 1) (match_dup 2))
1134 (clobber (match_dup 4))
1135 (clobber (match_dup 5))
1136 (clobber (match_dup 6))])
1137 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1140 (define_insn "*macc"
1141 [(set (match_operand:SI 0 "register_operand" "=l,d")
1142 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1143 (match_operand:SI 2 "register_operand" "d,d"))
1144 (match_operand:SI 3 "register_operand" "0,l")))
1145 (clobber (match_scratch:SI 4 "=h,h"))
1146 (clobber (match_scratch:SI 5 "=X,3"))]
1149 if (which_alternative == 1)
1150 return "macc\t%0,%1,%2";
1151 else if (TARGET_MIPS5500)
1152 return "madd\t%1,%2";
1154 /* The VR4130 assumes that there is a two-cycle latency between a macc
1155 that "writes" to $0 and an instruction that reads from it. We avoid
1156 this by assigning to $1 instead. */
1157 return "%[macc\t%@,%1,%2%]";
1159 [(set_attr "type" "imadd")
1160 (set_attr "mode" "SI")])
1162 (define_insn "*msac"
1163 [(set (match_operand:SI 0 "register_operand" "=l,d")
1164 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1165 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1166 (match_operand:SI 3 "register_operand" "d,d"))))
1167 (clobber (match_scratch:SI 4 "=h,h"))
1168 (clobber (match_scratch:SI 5 "=X,1"))]
1171 if (which_alternative == 1)
1172 return "msac\t%0,%2,%3";
1173 else if (TARGET_MIPS5500)
1174 return "msub\t%2,%3";
1176 return "msac\t$0,%2,%3";
1178 [(set_attr "type" "imadd")
1179 (set_attr "mode" "SI")])
1181 ;; An msac-like instruction implemented using negation and a macc.
1182 (define_insn_and_split "*msac_using_macc"
1183 [(set (match_operand:SI 0 "register_operand" "=l,d")
1184 (minus:SI (match_operand:SI 1 "register_operand" "0,l")
1185 (mult:SI (match_operand:SI 2 "register_operand" "d,d")
1186 (match_operand:SI 3 "register_operand" "d,d"))))
1187 (clobber (match_scratch:SI 4 "=h,h"))
1188 (clobber (match_scratch:SI 5 "=X,1"))
1189 (clobber (match_scratch:SI 6 "=d,d"))]
1190 "ISA_HAS_MACC && !ISA_HAS_MSAC"
1192 "&& reload_completed"
1194 (neg:SI (match_dup 3)))
1197 (plus:SI (mult:SI (match_dup 2)
1200 (clobber (match_dup 4))
1201 (clobber (match_dup 5))])]
1203 [(set_attr "type" "imadd")
1204 (set_attr "length" "8")])
1206 ;; Patterns generated by the define_peephole2 below.
1208 (define_insn "*macc2"
1209 [(set (match_operand:SI 0 "register_operand" "=l")
1210 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1211 (match_operand:SI 2 "register_operand" "d"))
1213 (set (match_operand:SI 3 "register_operand" "=d")
1214 (plus:SI (mult:SI (match_dup 1)
1217 (clobber (match_scratch:SI 4 "=h"))]
1218 "ISA_HAS_MACC && reload_completed"
1220 [(set_attr "type" "imadd")
1221 (set_attr "mode" "SI")])
1223 (define_insn "*msac2"
1224 [(set (match_operand:SI 0 "register_operand" "=l")
1225 (minus:SI (match_dup 0)
1226 (mult:SI (match_operand:SI 1 "register_operand" "d")
1227 (match_operand:SI 2 "register_operand" "d"))))
1228 (set (match_operand:SI 3 "register_operand" "=d")
1229 (minus:SI (match_dup 0)
1230 (mult:SI (match_dup 1)
1232 (clobber (match_scratch:SI 4 "=h"))]
1233 "ISA_HAS_MSAC && reload_completed"
1235 [(set_attr "type" "imadd")
1236 (set_attr "mode" "SI")])
1238 ;; Convert macc $0,<r1>,<r2> & mflo <r3> into macc <r3>,<r1>,<r2>
1242 ;; Operand 1: macc/msac
1244 ;; Operand 3: GPR (destination)
1247 [(set (match_operand:SI 0 "register_operand")
1248 (match_operand:SI 1 "macc_msac_operand"))
1249 (clobber (match_operand:SI 2 "register_operand"))
1250 (clobber (scratch:SI))])
1251 (set (match_operand:SI 3 "register_operand")
1252 (unspec:SI [(match_dup 0) (match_dup 2)] UNSPEC_MFHILO))]
1254 [(parallel [(set (match_dup 0)
1258 (clobber (match_dup 2))])]
1261 ;; When we have a three-address multiplication instruction, it should
1262 ;; be faster to do a separate multiply and add, rather than moving
1263 ;; something into LO in order to use a macc instruction.
1265 ;; This peephole needs a scratch register to cater for the case when one
1266 ;; of the multiplication operands is the same as the destination.
1268 ;; Operand 0: GPR (scratch)
1270 ;; Operand 2: GPR (addend)
1271 ;; Operand 3: GPR (destination)
1272 ;; Operand 4: macc/msac
1274 ;; Operand 6: new multiplication
1275 ;; Operand 7: new addition/subtraction
1277 [(match_scratch:SI 0 "d")
1278 (set (match_operand:SI 1 "register_operand")
1279 (match_operand:SI 2 "register_operand"))
1282 [(set (match_operand:SI 3 "register_operand")
1283 (match_operand:SI 4 "macc_msac_operand"))
1284 (clobber (match_operand:SI 5 "register_operand"))
1285 (clobber (match_dup 1))])]
1287 && true_regnum (operands[1]) == LO_REGNUM
1288 && peep2_reg_dead_p (2, operands[1])
1289 && GP_REG_P (true_regnum (operands[3]))"
1290 [(parallel [(set (match_dup 0)
1292 (clobber (match_dup 5))
1293 (clobber (match_dup 1))])
1297 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1298 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1299 operands[2], operands[0]);
1302 ;; Same as above, except LO is the initial target of the macc.
1304 ;; Operand 0: GPR (scratch)
1306 ;; Operand 2: GPR (addend)
1307 ;; Operand 3: macc/msac
1309 ;; Operand 5: GPR (destination)
1310 ;; Operand 6: new multiplication
1311 ;; Operand 7: new addition/subtraction
1313 [(match_scratch:SI 0 "d")
1314 (set (match_operand:SI 1 "register_operand")
1315 (match_operand:SI 2 "register_operand"))
1319 (match_operand:SI 3 "macc_msac_operand"))
1320 (clobber (match_operand:SI 4 "register_operand"))
1321 (clobber (scratch:SI))])
1323 (set (match_operand:SI 5 "register_operand")
1324 (unspec:SI [(match_dup 1) (match_dup 4)] UNSPEC_MFHILO))]
1325 "GENERATE_MULT3_SI && peep2_reg_dead_p (3, operands[1])"
1326 [(parallel [(set (match_dup 0)
1328 (clobber (match_dup 4))
1329 (clobber (match_dup 1))])
1333 operands[6] = XEXP (operands[4], GET_CODE (operands[4]) == PLUS ? 0 : 1);
1334 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[4]), SImode,
1335 operands[2], operands[0]);
1338 (define_insn "*mul_sub_si"
1339 [(set (match_operand:SI 0 "register_operand" "=l,*d,*d")
1340 (minus:SI (match_operand:SI 1 "register_operand" "0,l,*d")
1341 (mult:SI (match_operand:SI 2 "register_operand" "d,d,d")
1342 (match_operand:SI 3 "register_operand" "d,d,d"))))
1343 (clobber (match_scratch:SI 4 "=h,h,h"))
1344 (clobber (match_scratch:SI 5 "=X,1,l"))
1345 (clobber (match_scratch:SI 6 "=X,X,&d"))]
1351 [(set_attr "type" "imadd,multi,multi")
1352 (set_attr "mode" "SI")
1353 (set_attr "length" "4,8,8")])
1355 ;; Split the above insn if we failed to get LO allocated.
1357 [(set (match_operand:SI 0 "register_operand")
1358 (minus:SI (match_operand:SI 1 "register_operand")
1359 (mult:SI (match_operand:SI 2 "register_operand")
1360 (match_operand:SI 3 "register_operand"))))
1361 (clobber (match_scratch:SI 4))
1362 (clobber (match_scratch:SI 5))
1363 (clobber (match_scratch:SI 6))]
1364 "reload_completed && !TARGET_DEBUG_D_MODE
1365 && GP_REG_P (true_regnum (operands[0]))
1366 && GP_REG_P (true_regnum (operands[1]))"
1367 [(parallel [(set (match_dup 6)
1368 (mult:SI (match_dup 2) (match_dup 3)))
1369 (clobber (match_dup 4))
1370 (clobber (match_dup 5))])
1371 (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 6)))]
1374 ;; Splitter to copy result of MSUB to a general register
1376 [(set (match_operand:SI 0 "register_operand")
1377 (minus:SI (match_operand:SI 1 "register_operand")
1378 (mult:SI (match_operand:SI 2 "register_operand")
1379 (match_operand:SI 3 "register_operand"))))
1380 (clobber (match_scratch:SI 4))
1381 (clobber (match_scratch:SI 5))
1382 (clobber (match_scratch:SI 6))]
1383 "reload_completed && !TARGET_DEBUG_D_MODE
1384 && GP_REG_P (true_regnum (operands[0]))
1385 && true_regnum (operands[1]) == LO_REGNUM"
1386 [(parallel [(set (match_dup 1)
1387 (minus:SI (match_dup 1)
1388 (mult:SI (match_dup 2) (match_dup 3))))
1389 (clobber (match_dup 4))
1390 (clobber (match_dup 5))
1391 (clobber (match_dup 6))])
1392 (set (match_dup 0) (unspec:SI [(match_dup 5) (match_dup 4)] UNSPEC_MFHILO))]
1395 (define_insn "*muls"
1396 [(set (match_operand:SI 0 "register_operand" "=l,d")
1397 (neg:SI (mult:SI (match_operand:SI 1 "register_operand" "d,d")
1398 (match_operand:SI 2 "register_operand" "d,d"))))
1399 (clobber (match_scratch:SI 3 "=h,h"))
1400 (clobber (match_scratch:SI 4 "=X,l"))]
1405 [(set_attr "type" "imul,imul3")
1406 (set_attr "mode" "SI")])
1408 ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
1410 (define_expand "<u>mulsidi3"
1412 [(set (match_operand:DI 0 "register_operand")
1413 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1414 (any_extend:DI (match_operand:SI 2 "register_operand"))))
1415 (clobber (scratch:DI))
1416 (clobber (scratch:DI))
1417 (clobber (scratch:DI))])]
1418 "!TARGET_64BIT || !TARGET_FIX_R4000"
1422 if (!TARGET_FIX_R4000)
1423 emit_insn (gen_<u>mulsidi3_32bit_internal (operands[0], operands[1],
1426 emit_insn (gen_<u>mulsidi3_32bit_r4000 (operands[0], operands[1],
1432 (define_insn "<u>mulsidi3_32bit_internal"
1433 [(set (match_operand:DI 0 "register_operand" "=x")
1434 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1435 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))]
1436 "!TARGET_64BIT && !TARGET_FIX_R4000"
1438 [(set_attr "type" "imul")
1439 (set_attr "mode" "SI")])
1441 (define_insn "<u>mulsidi3_32bit_r4000"
1442 [(set (match_operand:DI 0 "register_operand" "=d")
1443 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1444 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1445 (clobber (match_scratch:DI 3 "=x"))]
1446 "!TARGET_64BIT && TARGET_FIX_R4000"
1447 "mult<u>\t%1,%2\;mflo\t%L0;mfhi\t%M0"
1448 [(set_attr "type" "imul")
1449 (set_attr "mode" "SI")
1450 (set_attr "length" "12")])
1452 (define_insn_and_split "*<u>mulsidi3_64bit"
1453 [(set (match_operand:DI 0 "register_operand" "=d")
1454 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1455 (any_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1456 (clobber (match_scratch:DI 3 "=l"))
1457 (clobber (match_scratch:DI 4 "=h"))
1458 (clobber (match_scratch:DI 5 "=d"))]
1459 "TARGET_64BIT && !TARGET_FIX_R4000"
1461 "&& reload_completed"
1465 (mult:SI (match_dup 1)
1469 (mult:DI (any_extend:DI (match_dup 1))
1470 (any_extend:DI (match_dup 2)))
1473 ;; OP5 <- LO, OP0 <- HI
1474 (set (match_dup 5) (unspec:DI [(match_dup 3) (match_dup 4)] UNSPEC_MFHILO))
1475 (set (match_dup 0) (unspec:DI [(match_dup 4) (match_dup 3)] UNSPEC_MFHILO))
1479 (ashift:DI (match_dup 5)
1482 (lshiftrt:DI (match_dup 5)
1485 ;; Shift OP0 into place.
1487 (ashift:DI (match_dup 0)
1490 ;; OR the two halves together
1492 (ior:DI (match_dup 0)
1495 [(set_attr "type" "imul")
1496 (set_attr "mode" "SI")
1497 (set_attr "length" "24")])
1499 (define_insn "*<u>mulsidi3_64bit_parts"
1500 [(set (match_operand:DI 0 "register_operand" "=l")
1502 (mult:SI (match_operand:SI 2 "register_operand" "d")
1503 (match_operand:SI 3 "register_operand" "d"))))
1504 (set (match_operand:DI 1 "register_operand" "=h")
1506 (mult:DI (any_extend:DI (match_dup 2))
1507 (any_extend:DI (match_dup 3)))
1509 "TARGET_64BIT && !TARGET_FIX_R4000"
1511 [(set_attr "type" "imul")
1512 (set_attr "mode" "SI")])
1514 ;; Widening multiply with negation.
1515 (define_insn "*muls<u>_di"
1516 [(set (match_operand:DI 0 "register_operand" "=x")
1519 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1520 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1521 "!TARGET_64BIT && ISA_HAS_MULS"
1523 [(set_attr "type" "imul")
1524 (set_attr "mode" "SI")])
1526 (define_insn "*msac<u>_di"
1527 [(set (match_operand:DI 0 "register_operand" "=x")
1529 (match_operand:DI 3 "register_operand" "0")
1531 (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1532 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))))]
1533 "!TARGET_64BIT && ISA_HAS_MSAC"
1535 if (TARGET_MIPS5500)
1536 return "msub<u>\t%1,%2";
1538 return "msac<u>\t$0,%1,%2";
1540 [(set_attr "type" "imadd")
1541 (set_attr "mode" "SI")])
1543 ;; _highpart patterns
1545 (define_expand "<su>mulsi3_highpart"
1546 [(set (match_operand:SI 0 "register_operand")
1549 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand"))
1550 (any_extend:DI (match_operand:SI 2 "register_operand")))
1552 "ISA_HAS_MULHI || !TARGET_FIX_R4000"
1555 emit_insn (gen_<su>mulsi3_highpart_mulhi_internal (operands[0],
1559 emit_insn (gen_<su>mulsi3_highpart_internal (operands[0], operands[1],
1564 (define_insn "<su>mulsi3_highpart_internal"
1565 [(set (match_operand:SI 0 "register_operand" "=h")
1568 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1569 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1571 (clobber (match_scratch:SI 3 "=l"))]
1572 "!ISA_HAS_MULHI && !TARGET_FIX_R4000"
1574 [(set_attr "type" "imul")
1575 (set_attr "mode" "SI")])
1577 (define_insn "<su>mulsi3_highpart_mulhi_internal"
1578 [(set (match_operand:SI 0 "register_operand" "=h,d")
1582 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1583 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d")))
1585 (clobber (match_scratch:SI 3 "=l,l"))
1586 (clobber (match_scratch:SI 4 "=X,h"))]
1591 [(set_attr "type" "imul,imul3")
1592 (set_attr "mode" "SI")])
1594 (define_insn "*<su>mulsi3_highpart_neg_mulhi_internal"
1595 [(set (match_operand:SI 0 "register_operand" "=h,d")
1600 (any_extend:DI (match_operand:SI 1 "register_operand" "d,d"))
1601 (any_extend:DI (match_operand:SI 2 "register_operand" "d,d"))))
1603 (clobber (match_scratch:SI 3 "=l,l"))
1604 (clobber (match_scratch:SI 4 "=X,h"))]
1608 mulshi<u>\t%0,%1,%2"
1609 [(set_attr "type" "imul,imul3")
1610 (set_attr "mode" "SI")])
1612 ;; Disable unsigned multiplication for -mfix-vr4120. This is for VR4120
1613 ;; errata MD(0), which says that dmultu does not always produce the
1615 (define_insn "<su>muldi3_highpart"
1616 [(set (match_operand:DI 0 "register_operand" "=h")
1620 (any_extend:TI (match_operand:DI 1 "register_operand" "d"))
1621 (any_extend:TI (match_operand:DI 2 "register_operand" "d")))
1623 (clobber (match_scratch:DI 3 "=l"))]
1624 "TARGET_64BIT && !TARGET_FIX_R4000
1625 && !(<CODE> == ZERO_EXTEND && TARGET_FIX_VR4120)"
1627 [(set_attr "type" "imul")
1628 (set_attr "mode" "DI")])
1630 ;; The R4650 supports a 32 bit multiply/ 64 bit accumulate
1631 ;; instruction. The HI/LO registers are used as a 64 bit accumulator.
1633 (define_insn "madsi"
1634 [(set (match_operand:SI 0 "register_operand" "+l")
1635 (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d")
1636 (match_operand:SI 2 "register_operand" "d"))
1638 (clobber (match_scratch:SI 3 "=h"))]
1641 [(set_attr "type" "imadd")
1642 (set_attr "mode" "SI")])
1644 (define_insn "*<su>mul_acc_di"
1645 [(set (match_operand:DI 0 "register_operand" "=x")
1647 (mult:DI (any_extend:DI (match_operand:SI 1 "register_operand" "d"))
1648 (any_extend:DI (match_operand:SI 2 "register_operand" "d")))
1649 (match_operand:DI 3 "register_operand" "0")))]
1650 "(TARGET_MAD || ISA_HAS_MACC)
1654 return "mad<u>\t%1,%2";
1655 else if (TARGET_MIPS5500)
1656 return "madd<u>\t%1,%2";
1658 /* See comment in *macc. */
1659 return "%[macc<u>\t%@,%1,%2%]";
1661 [(set_attr "type" "imadd")
1662 (set_attr "mode" "SI")])
1664 ;; Floating point multiply accumulate instructions.
1666 (define_insn "*madd<mode>"
1667 [(set (match_operand:ANYF 0 "register_operand" "=f")
1668 (plus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1669 (match_operand:ANYF 2 "register_operand" "f"))
1670 (match_operand:ANYF 3 "register_operand" "f")))]
1671 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1672 "madd.<fmt>\t%0,%3,%1,%2"
1673 [(set_attr "type" "fmadd")
1674 (set_attr "mode" "<UNITMODE>")])
1676 (define_insn "*msub<mode>"
1677 [(set (match_operand:ANYF 0 "register_operand" "=f")
1678 (minus:ANYF (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1679 (match_operand:ANYF 2 "register_operand" "f"))
1680 (match_operand:ANYF 3 "register_operand" "f")))]
1681 "ISA_HAS_FP4 && TARGET_FUSED_MADD"
1682 "msub.<fmt>\t%0,%3,%1,%2"
1683 [(set_attr "type" "fmadd")
1684 (set_attr "mode" "<UNITMODE>")])
1686 (define_insn "*nmadd<mode>"
1687 [(set (match_operand:ANYF 0 "register_operand" "=f")
1688 (neg:ANYF (plus:ANYF
1689 (mult:ANYF (match_operand:ANYF 1 "register_operand" "f")
1690 (match_operand:ANYF 2 "register_operand" "f"))
1691 (match_operand:ANYF 3 "register_operand" "f"))))]
1692 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1693 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1694 "nmadd.<fmt>\t%0,%3,%1,%2"
1695 [(set_attr "type" "fmadd")
1696 (set_attr "mode" "<UNITMODE>")])
1698 (define_insn "*nmadd<mode>_fastmath"
1699 [(set (match_operand:ANYF 0 "register_operand" "=f")
1701 (mult:ANYF (neg:ANYF (match_operand:ANYF 1 "register_operand" "f"))
1702 (match_operand:ANYF 2 "register_operand" "f"))
1703 (match_operand:ANYF 3 "register_operand" "f")))]
1704 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1705 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1706 "nmadd.<fmt>\t%0,%3,%1,%2"
1707 [(set_attr "type" "fmadd")
1708 (set_attr "mode" "<UNITMODE>")])
1710 (define_insn "*nmsub<mode>"
1711 [(set (match_operand:ANYF 0 "register_operand" "=f")
1712 (neg:ANYF (minus:ANYF
1713 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1714 (match_operand:ANYF 3 "register_operand" "f"))
1715 (match_operand:ANYF 1 "register_operand" "f"))))]
1716 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1717 && HONOR_SIGNED_ZEROS (<MODE>mode)"
1718 "nmsub.<fmt>\t%0,%1,%2,%3"
1719 [(set_attr "type" "fmadd")
1720 (set_attr "mode" "<UNITMODE>")])
1722 (define_insn "*nmsub<mode>_fastmath"
1723 [(set (match_operand:ANYF 0 "register_operand" "=f")
1725 (match_operand:ANYF 1 "register_operand" "f")
1726 (mult:ANYF (match_operand:ANYF 2 "register_operand" "f")
1727 (match_operand:ANYF 3 "register_operand" "f"))))]
1728 "ISA_HAS_NMADD_NMSUB && TARGET_FUSED_MADD
1729 && !HONOR_SIGNED_ZEROS (<MODE>mode)"
1730 "nmsub.<fmt>\t%0,%1,%2,%3"
1731 [(set_attr "type" "fmadd")
1732 (set_attr "mode" "<UNITMODE>")])
1735 ;; ....................
1737 ;; DIVISION and REMAINDER
1739 ;; ....................
1742 (define_expand "div<mode>3"
1743 [(set (match_operand:ANYF 0 "register_operand")
1744 (div:ANYF (match_operand:ANYF 1 "reg_or_1_operand")
1745 (match_operand:ANYF 2 "register_operand")))]
1746 "<divide_condition>"
1748 if (const_1_operand (operands[1], <MODE>mode))
1749 if (!(ISA_HAS_FP4 && flag_unsafe_math_optimizations))
1750 operands[1] = force_reg (<MODE>mode, operands[1]);
1753 ;; These patterns work around the early SB-1 rev2 core "F1" erratum:
1755 ;; If an mfc1 or dmfc1 happens to access the floating point register
1756 ;; file at the same time a long latency operation (div, sqrt, recip,
1757 ;; sqrt) iterates an intermediate result back through the floating
1758 ;; point register file bypass, then instead returning the correct
1759 ;; register value the mfc1 or dmfc1 operation returns the intermediate
1760 ;; result of the long latency operation.
1762 ;; The workaround is to insert an unconditional 'mov' from/to the
1763 ;; long latency op destination register.
1765 (define_insn "*div<mode>3"
1766 [(set (match_operand:ANYF 0 "register_operand" "=f")
1767 (div:ANYF (match_operand:ANYF 1 "register_operand" "f")
1768 (match_operand:ANYF 2 "register_operand" "f")))]
1769 "<divide_condition>"
1772 return "div.<fmt>\t%0,%1,%2\;mov.<fmt>\t%0,%0";
1774 return "div.<fmt>\t%0,%1,%2";
1776 [(set_attr "type" "fdiv")
1777 (set_attr "mode" "<UNITMODE>")
1778 (set (attr "length")
1779 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1783 (define_insn "*recip<mode>3"
1784 [(set (match_operand:ANYF 0 "register_operand" "=f")
1785 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1786 (match_operand:ANYF 2 "register_operand" "f")))]
1787 "<recip_condition> && flag_unsafe_math_optimizations"
1790 return "recip.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1792 return "recip.<fmt>\t%0,%2";
1794 [(set_attr "type" "frdiv")
1795 (set_attr "mode" "<UNITMODE>")
1796 (set (attr "length")
1797 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1801 ;; VR4120 errata MD(A1): signed division instructions do not work correctly
1802 ;; with negative operands. We use special libgcc functions instead.
1803 (define_insn "divmod<mode>4"
1804 [(set (match_operand:GPR 0 "register_operand" "=l")
1805 (div:GPR (match_operand:GPR 1 "register_operand" "d")
1806 (match_operand:GPR 2 "register_operand" "d")))
1807 (set (match_operand:GPR 3 "register_operand" "=h")
1808 (mod:GPR (match_dup 1)
1810 "!TARGET_FIX_VR4120"
1811 { return mips_output_division ("<d>div\t$0,%1,%2", operands); }
1812 [(set_attr "type" "idiv")
1813 (set_attr "mode" "<MODE>")])
1815 (define_insn "udivmod<mode>4"
1816 [(set (match_operand:GPR 0 "register_operand" "=l")
1817 (udiv:GPR (match_operand:GPR 1 "register_operand" "d")
1818 (match_operand:GPR 2 "register_operand" "d")))
1819 (set (match_operand:GPR 3 "register_operand" "=h")
1820 (umod:GPR (match_dup 1)
1823 { return mips_output_division ("<d>divu\t$0,%1,%2", operands); }
1824 [(set_attr "type" "idiv")
1825 (set_attr "mode" "<MODE>")])
1828 ;; ....................
1832 ;; ....................
1834 ;; These patterns work around the early SB-1 rev2 core "F1" erratum (see
1835 ;; "*div[sd]f3" comment for details).
1837 (define_insn "sqrt<mode>2"
1838 [(set (match_operand:ANYF 0 "register_operand" "=f")
1839 (sqrt:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1843 return "sqrt.<fmt>\t%0,%1\;mov.<fmt>\t%0,%0";
1845 return "sqrt.<fmt>\t%0,%1";
1847 [(set_attr "type" "fsqrt")
1848 (set_attr "mode" "<UNITMODE>")
1849 (set (attr "length")
1850 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1854 (define_insn "*rsqrt<mode>a"
1855 [(set (match_operand:ANYF 0 "register_operand" "=f")
1856 (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1857 (sqrt:ANYF (match_operand:ANYF 2 "register_operand" "f"))))]
1858 "<recip_condition> && flag_unsafe_math_optimizations"
1861 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1863 return "rsqrt.<fmt>\t%0,%2";
1865 [(set_attr "type" "frsqrt")
1866 (set_attr "mode" "<UNITMODE>")
1867 (set (attr "length")
1868 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1872 (define_insn "*rsqrt<mode>b"
1873 [(set (match_operand:ANYF 0 "register_operand" "=f")
1874 (sqrt:ANYF (div:ANYF (match_operand:ANYF 1 "const_1_operand" "")
1875 (match_operand:ANYF 2 "register_operand" "f"))))]
1876 "<recip_condition> && flag_unsafe_math_optimizations"
1879 return "rsqrt.<fmt>\t%0,%2\;mov.<fmt>\t%0,%0";
1881 return "rsqrt.<fmt>\t%0,%2";
1883 [(set_attr "type" "frsqrt")
1884 (set_attr "mode" "<UNITMODE>")
1885 (set (attr "length")
1886 (if_then_else (ne (symbol_ref "TARGET_FIX_SB1") (const_int 0))
1891 ;; ....................
1895 ;; ....................
1897 ;; Do not use the integer abs macro instruction, since that signals an
1898 ;; exception on -2147483648 (sigh).
1900 (define_insn "abs<mode>2"
1901 [(set (match_operand:GPR 0 "register_operand" "=d")
1902 (abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
1905 if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
1906 return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
1908 return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
1910 [(set_attr "type" "multi")
1911 (set_attr "mode" "<MODE>")
1912 (set_attr "length" "12")])
1914 (define_insn "abs<mode>2"
1915 [(set (match_operand:ANYF 0 "register_operand" "=f")
1916 (abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
1919 [(set_attr "type" "fabs")
1920 (set_attr "mode" "<UNITMODE>")])
1923 ;; ....................
1925 ;; FIND FIRST BIT INSTRUCTION
1927 ;; ....................
1930 (define_insn "ffs<mode>2"
1931 [(set (match_operand:GPR 0 "register_operand" "=&d")
1932 (ffs:GPR (match_operand:GPR 1 "register_operand" "d")))
1933 (clobber (match_scratch:GPR 2 "=&d"))
1934 (clobber (match_scratch:GPR 3 "=&d"))]
1937 if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1941 %~1:\tand\t%2,%1,0x0001\;\
1951 %~1:\tand\t%2,%3,0x0001\;\
1957 [(set_attr "type" "multi")
1958 (set_attr "mode" "<MODE>")
1959 (set_attr "length" "28")])
1962 ;; ...................
1964 ;; Count leading zeroes.
1966 ;; ...................
1969 (define_insn "clz<mode>2"
1970 [(set (match_operand:GPR 0 "register_operand" "=d")
1971 (clz:GPR (match_operand:GPR 1 "register_operand" "d")))]
1974 [(set_attr "type" "clz")
1975 (set_attr "mode" "<MODE>")])
1978 ;; ....................
1980 ;; NEGATION and ONE'S COMPLEMENT
1982 ;; ....................
1984 (define_insn "negsi2"
1985 [(set (match_operand:SI 0 "register_operand" "=d")
1986 (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1990 return "neg\t%0,%1";
1992 return "subu\t%0,%.,%1";
1994 [(set_attr "type" "arith")
1995 (set_attr "mode" "SI")])
1997 (define_insn "negdi2"
1998 [(set (match_operand:DI 0 "register_operand" "=d")
1999 (neg:DI (match_operand:DI 1 "register_operand" "d")))]
2000 "TARGET_64BIT && !TARGET_MIPS16"
2002 [(set_attr "type" "arith")
2003 (set_attr "mode" "DI")])
2005 (define_insn "neg<mode>2"
2006 [(set (match_operand:ANYF 0 "register_operand" "=f")
2007 (neg:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
2010 [(set_attr "type" "fneg")
2011 (set_attr "mode" "<UNITMODE>")])
2013 (define_insn "one_cmpl<mode>2"
2014 [(set (match_operand:GPR 0 "register_operand" "=d")
2015 (not:GPR (match_operand:GPR 1 "register_operand" "d")))]
2019 return "not\t%0,%1";
2021 return "nor\t%0,%.,%1";
2023 [(set_attr "type" "arith")
2024 (set_attr "mode" "<MODE>")])
2027 ;; ....................
2031 ;; ....................
2034 ;; Many of these instructions use trivial define_expands, because we
2035 ;; want to use a different set of constraints when TARGET_MIPS16.
2037 (define_expand "and<mode>3"
2038 [(set (match_operand:GPR 0 "register_operand")
2039 (and:GPR (match_operand:GPR 1 "register_operand")
2040 (match_operand:GPR 2 "uns_arith_operand")))]
2044 operands[2] = force_reg (<MODE>mode, operands[2]);
2047 (define_insn "*and<mode>3"
2048 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2049 (and:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2050 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2055 [(set_attr "type" "arith")
2056 (set_attr "mode" "<MODE>")])
2058 (define_insn "*and<mode>3_mips16"
2059 [(set (match_operand:GPR 0 "register_operand" "=d")
2060 (and:GPR (match_operand:GPR 1 "register_operand" "%0")
2061 (match_operand:GPR 2 "register_operand" "d")))]
2064 [(set_attr "type" "arith")
2065 (set_attr "mode" "<MODE>")])
2067 (define_expand "ior<mode>3"
2068 [(set (match_operand:GPR 0 "register_operand")
2069 (ior:GPR (match_operand:GPR 1 "register_operand")
2070 (match_operand:GPR 2 "uns_arith_operand")))]
2074 operands[2] = force_reg (<MODE>mode, operands[2]);
2077 (define_insn "*ior<mode>3"
2078 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2079 (ior:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2080 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2085 [(set_attr "type" "arith")
2086 (set_attr "mode" "<MODE>")])
2088 (define_insn "*ior<mode>3_mips16"
2089 [(set (match_operand:GPR 0 "register_operand" "=d")
2090 (ior:GPR (match_operand:GPR 1 "register_operand" "%0")
2091 (match_operand:GPR 2 "register_operand" "d")))]
2094 [(set_attr "type" "arith")
2095 (set_attr "mode" "<MODE>")])
2097 (define_expand "xor<mode>3"
2098 [(set (match_operand:GPR 0 "register_operand")
2099 (xor:GPR (match_operand:GPR 1 "register_operand")
2100 (match_operand:GPR 2 "uns_arith_operand")))]
2105 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2106 (xor:GPR (match_operand:GPR 1 "register_operand" "%d,d")
2107 (match_operand:GPR 2 "uns_arith_operand" "d,K")))]
2112 [(set_attr "type" "arith")
2113 (set_attr "mode" "<MODE>")])
2116 [(set (match_operand:GPR 0 "register_operand" "=d,t,t")
2117 (xor:GPR (match_operand:GPR 1 "register_operand" "%0,d,d")
2118 (match_operand:GPR 2 "uns_arith_operand" "d,K,d")))]
2124 [(set_attr "type" "arith")
2125 (set_attr "mode" "<MODE>")
2126 (set_attr_alternative "length"
2128 (if_then_else (match_operand:VOID 2 "m16_uimm8_1")
2133 (define_insn "*nor<mode>3"
2134 [(set (match_operand:GPR 0 "register_operand" "=d")
2135 (and:GPR (not:GPR (match_operand:GPR 1 "register_operand" "d"))
2136 (not:GPR (match_operand:GPR 2 "register_operand" "d"))))]
2139 [(set_attr "type" "arith")
2140 (set_attr "mode" "<MODE>")])
2143 ;; ....................
2147 ;; ....................
2151 (define_insn "truncdfsf2"
2152 [(set (match_operand:SF 0 "register_operand" "=f")
2153 (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
2154 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2156 [(set_attr "type" "fcvt")
2157 (set_attr "cnv_mode" "D2S")
2158 (set_attr "mode" "SF")])
2160 ;; Integer truncation patterns. Truncating SImode values to smaller
2161 ;; modes is a no-op, as it is for most other GCC ports. Truncating
2162 ;; DImode values to SImode is not a no-op for TARGET_64BIT since we
2163 ;; need to make sure that the lower 32 bits are properly sign-extended
2164 ;; (see TRULY_NOOP_TRUNCATION). Truncating DImode values into modes
2165 ;; smaller than SImode is equivalent to two separate truncations:
2168 ;; DI ---> HI == DI ---> SI ---> HI
2169 ;; DI ---> QI == DI ---> SI ---> QI
2171 ;; Step A needs a real instruction but step B does not.
2173 (define_insn "truncdisi2"
2174 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
2175 (truncate:SI (match_operand:DI 1 "register_operand" "d,d")))]
2180 [(set_attr "type" "shift,store")
2181 (set_attr "mode" "SI")
2182 (set_attr "extended_mips16" "yes,*")])
2184 (define_insn "truncdihi2"
2185 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,m")
2186 (truncate:HI (match_operand:DI 1 "register_operand" "d,d")))]
2191 [(set_attr "type" "shift,store")
2192 (set_attr "mode" "SI")
2193 (set_attr "extended_mips16" "yes,*")])
2195 (define_insn "truncdiqi2"
2196 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,m")
2197 (truncate:QI (match_operand:DI 1 "register_operand" "d,d")))]
2202 [(set_attr "type" "shift,store")
2203 (set_attr "mode" "SI")
2204 (set_attr "extended_mips16" "yes,*")])
2206 ;; Combiner patterns to optimize shift/truncate combinations.
2209 [(set (match_operand:SI 0 "register_operand" "=d")
2211 (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
2212 (match_operand:DI 2 "const_arith_operand" ""))))]
2213 "TARGET_64BIT && !TARGET_MIPS16 && INTVAL (operands[2]) >= 32"
2215 [(set_attr "type" "shift")
2216 (set_attr "mode" "SI")])
2219 [(set (match_operand:SI 0 "register_operand" "=d")
2220 (truncate:SI (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
2222 "TARGET_64BIT && !TARGET_MIPS16"
2224 [(set_attr "type" "shift")
2225 (set_attr "mode" "SI")])
2228 ;; Combiner patterns for truncate/sign_extend combinations. They use
2229 ;; the shift/truncate patterns above.
2231 (define_insn_and_split ""
2232 [(set (match_operand:SI 0 "register_operand" "=d")
2234 (truncate:HI (match_operand:DI 1 "register_operand" "d"))))]
2235 "TARGET_64BIT && !TARGET_MIPS16"
2237 "&& reload_completed"
2239 (ashift:DI (match_dup 1)
2242 (truncate:SI (ashiftrt:DI (match_dup 2)
2244 { operands[2] = gen_lowpart (DImode, operands[0]); })
2246 (define_insn_and_split ""
2247 [(set (match_operand:SI 0 "register_operand" "=d")
2249 (truncate:QI (match_operand:DI 1 "register_operand" "d"))))]
2250 "TARGET_64BIT && !TARGET_MIPS16"
2252 "&& reload_completed"
2254 (ashift:DI (match_dup 1)
2257 (truncate:SI (ashiftrt:DI (match_dup 2)
2259 { operands[2] = gen_lowpart (DImode, operands[0]); })
2262 ;; Combiner patterns to optimize truncate/zero_extend combinations.
2265 [(set (match_operand:SI 0 "register_operand" "=d")
2266 (zero_extend:SI (truncate:HI
2267 (match_operand:DI 1 "register_operand" "d"))))]
2268 "TARGET_64BIT && !TARGET_MIPS16"
2269 "andi\t%0,%1,0xffff"
2270 [(set_attr "type" "arith")
2271 (set_attr "mode" "SI")])
2274 [(set (match_operand:SI 0 "register_operand" "=d")
2275 (zero_extend:SI (truncate:QI
2276 (match_operand:DI 1 "register_operand" "d"))))]
2277 "TARGET_64BIT && !TARGET_MIPS16"
2279 [(set_attr "type" "arith")
2280 (set_attr "mode" "SI")])
2283 [(set (match_operand:HI 0 "register_operand" "=d")
2284 (zero_extend:HI (truncate:QI
2285 (match_operand:DI 1 "register_operand" "d"))))]
2286 "TARGET_64BIT && !TARGET_MIPS16"
2288 [(set_attr "type" "arith")
2289 (set_attr "mode" "HI")])
2292 ;; ....................
2296 ;; ....................
2300 (define_insn_and_split "zero_extendsidi2"
2301 [(set (match_operand:DI 0 "register_operand" "=d,d")
2302 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,W")))]
2307 "&& reload_completed && REG_P (operands[1])"
2309 (ashift:DI (match_dup 1) (const_int 32)))
2311 (lshiftrt:DI (match_dup 0) (const_int 32)))]
2312 { operands[1] = gen_lowpart (DImode, operands[1]); }
2313 [(set_attr "type" "multi,load")
2314 (set_attr "mode" "DI")
2315 (set_attr "length" "8,*")])
2317 (define_expand "zero_extend<SHORT:mode><GPR:mode>2"
2318 [(set (match_operand:GPR 0 "register_operand")
2319 (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2322 if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode))
2324 emit_insn (gen_and<GPR:mode>3 (operands[0],
2325 gen_lowpart (<GPR:MODE>mode, operands[1]),
2326 force_reg (<GPR:MODE>mode,
2327 GEN_INT (<SHORT:mask>))));
2332 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2"
2333 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2335 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2338 andi\t%0,%1,<SHORT:mask>
2339 l<SHORT:size>u\t%0,%1"
2340 [(set_attr "type" "arith,load")
2341 (set_attr "mode" "<GPR:MODE>")])
2343 (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
2344 [(set (match_operand:GPR 0 "register_operand" "=d")
2345 (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
2347 "l<SHORT:size>u\t%0,%1"
2348 [(set_attr "type" "load")
2349 (set_attr "mode" "<GPR:MODE>")])
2351 (define_expand "zero_extendqihi2"
2352 [(set (match_operand:HI 0 "register_operand")
2353 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand")))]
2356 if (TARGET_MIPS16 && !memory_operand (operands[1], QImode))
2358 emit_insn (gen_zero_extendqisi2 (gen_lowpart (SImode, operands[0]),
2364 (define_insn "*zero_extendqihi2"
2365 [(set (match_operand:HI 0 "register_operand" "=d,d")
2366 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2371 [(set_attr "type" "arith,load")
2372 (set_attr "mode" "HI")])
2374 (define_insn "*zero_extendqihi2_mips16"
2375 [(set (match_operand:HI 0 "register_operand" "=d")
2376 (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
2379 [(set_attr "type" "load")
2380 (set_attr "mode" "HI")])
2383 ;; ....................
2387 ;; ....................
2390 ;; Those for integer source operand are ordered widest source type first.
2392 ;; When TARGET_64BIT, all SImode integer registers should already be in
2393 ;; sign-extended form (see TRULY_NOOP_TRUNCATION and truncdisi2). We can
2394 ;; therefore get rid of register->register instructions if we constrain
2395 ;; the source to be in the same register as the destination.
2397 ;; The register alternative has type "arith" so that the pre-reload
2398 ;; scheduler will treat it as a move. This reflects what happens if
2399 ;; the register alternative needs a reload.
2400 (define_insn_and_split "extendsidi2"
2401 [(set (match_operand:DI 0 "register_operand" "=d,d")
2402 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "0,m")))]
2407 "&& reload_completed && register_operand (operands[1], VOIDmode)"
2410 emit_note (NOTE_INSN_DELETED);
2413 [(set_attr "type" "arith,load")
2414 (set_attr "mode" "DI")])
2416 (define_expand "extend<SHORT:mode><GPR:mode>2"
2417 [(set (match_operand:GPR 0 "register_operand")
2418 (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
2421 (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
2422 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2424 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2428 l<SHORT:size>\t%0,%1"
2429 "&& reload_completed && REG_P (operands[1])"
2430 [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2)))
2431 (set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2)))]
2433 operands[1] = gen_lowpart (<GPR:MODE>mode, operands[1]);
2434 operands[2] = GEN_INT (GET_MODE_BITSIZE (<GPR:MODE>mode)
2435 - GET_MODE_BITSIZE (<SHORT:MODE>mode));
2437 [(set_attr "type" "arith,load")
2438 (set_attr "mode" "<GPR:MODE>")
2439 (set_attr "length" "8,*")])
2441 (define_insn "*extend<SHORT:mode><GPR:mode>2_se<SHORT:size>"
2442 [(set (match_operand:GPR 0 "register_operand" "=d,d")
2444 (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
2447 se<SHORT:size>\t%0,%1
2448 l<SHORT:size>\t%0,%1"
2449 [(set_attr "type" "arith,load")
2450 (set_attr "mode" "<GPR:MODE>")])
2452 ;; This pattern generates the same code as extendqisi2; split it into
2453 ;; that form after reload.
2454 (define_insn_and_split "extendqihi2"
2455 [(set (match_operand:HI 0 "register_operand" "=d,d")
2456 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
2460 [(set (match_dup 0) (sign_extend:SI (match_dup 1)))]
2461 { operands[0] = gen_lowpart (SImode, operands[0]); }
2462 [(set_attr "type" "arith,load")
2463 (set_attr "mode" "SI")
2464 (set_attr "length" "8,*")])
2466 (define_insn "extendsfdf2"
2467 [(set (match_operand:DF 0 "register_operand" "=f")
2468 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2469 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2471 [(set_attr "type" "fcvt")
2472 (set_attr "cnv_mode" "S2D")
2473 (set_attr "mode" "DF")])
2476 ;; ....................
2480 ;; ....................
2482 (define_expand "fix_truncdfsi2"
2483 [(set (match_operand:SI 0 "register_operand")
2484 (fix:SI (match_operand:DF 1 "register_operand")))]
2485 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2487 if (!ISA_HAS_TRUNC_W)
2489 emit_insn (gen_fix_truncdfsi2_macro (operands[0], operands[1]));
2494 (define_insn "fix_truncdfsi2_insn"
2495 [(set (match_operand:SI 0 "register_operand" "=f")
2496 (fix:SI (match_operand:DF 1 "register_operand" "f")))]
2497 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && ISA_HAS_TRUNC_W"
2499 [(set_attr "type" "fcvt")
2500 (set_attr "mode" "DF")
2501 (set_attr "cnv_mode" "D2I")
2502 (set_attr "length" "4")])
2504 (define_insn "fix_truncdfsi2_macro"
2505 [(set (match_operand:SI 0 "register_operand" "=f")
2506 (fix:SI (match_operand:DF 1 "register_operand" "f")))
2507 (clobber (match_scratch:DF 2 "=d"))]
2508 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !ISA_HAS_TRUNC_W"
2511 return ".set\tmacro\;trunc.w.d %0,%1,%2\;.set\tnomacro";
2513 return "trunc.w.d %0,%1,%2";
2515 [(set_attr "type" "fcvt")
2516 (set_attr "mode" "DF")
2517 (set_attr "cnv_mode" "D2I")
2518 (set_attr "length" "36")])
2520 (define_expand "fix_truncsfsi2"
2521 [(set (match_operand:SI 0 "register_operand")
2522 (fix:SI (match_operand:SF 1 "register_operand")))]
2525 if (!ISA_HAS_TRUNC_W)
2527 emit_insn (gen_fix_truncsfsi2_macro (operands[0], operands[1]));
2532 (define_insn "fix_truncsfsi2_insn"
2533 [(set (match_operand:SI 0 "register_operand" "=f")
2534 (fix:SI (match_operand:SF 1 "register_operand" "f")))]
2535 "TARGET_HARD_FLOAT && ISA_HAS_TRUNC_W"
2537 [(set_attr "type" "fcvt")
2538 (set_attr "mode" "SF")
2539 (set_attr "cnv_mode" "S2I")
2540 (set_attr "length" "4")])
2542 (define_insn "fix_truncsfsi2_macro"
2543 [(set (match_operand:SI 0 "register_operand" "=f")
2544 (fix:SI (match_operand:SF 1 "register_operand" "f")))
2545 (clobber (match_scratch:SF 2 "=d"))]
2546 "TARGET_HARD_FLOAT && !ISA_HAS_TRUNC_W"
2549 return ".set\tmacro\;trunc.w.s %0,%1,%2\;.set\tnomacro";
2551 return "trunc.w.s %0,%1,%2";
2553 [(set_attr "type" "fcvt")
2554 (set_attr "mode" "SF")
2555 (set_attr "cnv_mode" "S2I")
2556 (set_attr "length" "36")])
2559 (define_insn "fix_truncdfdi2"
2560 [(set (match_operand:DI 0 "register_operand" "=f")
2561 (fix:DI (match_operand:DF 1 "register_operand" "f")))]
2562 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2564 [(set_attr "type" "fcvt")
2565 (set_attr "mode" "DF")
2566 (set_attr "cnv_mode" "D2I")
2567 (set_attr "length" "4")])
2570 (define_insn "fix_truncsfdi2"
2571 [(set (match_operand:DI 0 "register_operand" "=f")
2572 (fix:DI (match_operand:SF 1 "register_operand" "f")))]
2573 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2575 [(set_attr "type" "fcvt")
2576 (set_attr "mode" "SF")
2577 (set_attr "cnv_mode" "S2I")
2578 (set_attr "length" "4")])
2581 (define_insn "floatsidf2"
2582 [(set (match_operand:DF 0 "register_operand" "=f")
2583 (float:DF (match_operand:SI 1 "register_operand" "f")))]
2584 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2586 [(set_attr "type" "fcvt")
2587 (set_attr "mode" "DF")
2588 (set_attr "cnv_mode" "I2D")
2589 (set_attr "length" "4")])
2592 (define_insn "floatdidf2"
2593 [(set (match_operand:DF 0 "register_operand" "=f")
2594 (float:DF (match_operand:DI 1 "register_operand" "f")))]
2595 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2597 [(set_attr "type" "fcvt")
2598 (set_attr "mode" "DF")
2599 (set_attr "cnv_mode" "I2D")
2600 (set_attr "length" "4")])
2603 (define_insn "floatsisf2"
2604 [(set (match_operand:SF 0 "register_operand" "=f")
2605 (float:SF (match_operand:SI 1 "register_operand" "f")))]
2608 [(set_attr "type" "fcvt")
2609 (set_attr "mode" "SF")
2610 (set_attr "cnv_mode" "I2S")
2611 (set_attr "length" "4")])
2614 (define_insn "floatdisf2"
2615 [(set (match_operand:SF 0 "register_operand" "=f")
2616 (float:SF (match_operand:DI 1 "register_operand" "f")))]
2617 "TARGET_HARD_FLOAT && TARGET_FLOAT64 && TARGET_DOUBLE_FLOAT"
2619 [(set_attr "type" "fcvt")
2620 (set_attr "mode" "SF")
2621 (set_attr "cnv_mode" "I2S")
2622 (set_attr "length" "4")])
2625 (define_expand "fixuns_truncdfsi2"
2626 [(set (match_operand:SI 0 "register_operand")
2627 (unsigned_fix:SI (match_operand:DF 1 "register_operand")))]
2628 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
2630 rtx reg1 = gen_reg_rtx (DFmode);
2631 rtx reg2 = gen_reg_rtx (DFmode);
2632 rtx reg3 = gen_reg_rtx (SImode);
2633 rtx label1 = gen_label_rtx ();
2634 rtx label2 = gen_label_rtx ();
2635 REAL_VALUE_TYPE offset;
2637 real_2expN (&offset, 31);
2639 if (reg1) /* Turn off complaints about unreached code. */
2641 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2642 do_pending_stack_adjust ();
2644 emit_insn (gen_cmpdf (operands[1], reg1));
2645 emit_jump_insn (gen_bge (label1));
2647 emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2648 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2649 gen_rtx_LABEL_REF (VOIDmode, label2)));
2652 emit_label (label1);
2653 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2654 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2655 (BITMASK_HIGH, SImode)));
2657 emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2658 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2660 emit_label (label2);
2662 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2663 fields, and can't be used for REG_NOTES anyway). */
2664 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2670 (define_expand "fixuns_truncdfdi2"
2671 [(set (match_operand:DI 0 "register_operand")
2672 (unsigned_fix:DI (match_operand:DF 1 "register_operand")))]
2673 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2675 rtx reg1 = gen_reg_rtx (DFmode);
2676 rtx reg2 = gen_reg_rtx (DFmode);
2677 rtx reg3 = gen_reg_rtx (DImode);
2678 rtx label1 = gen_label_rtx ();
2679 rtx label2 = gen_label_rtx ();
2680 REAL_VALUE_TYPE offset;
2682 real_2expN (&offset, 63);
2684 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, DFmode));
2685 do_pending_stack_adjust ();
2687 emit_insn (gen_cmpdf (operands[1], reg1));
2688 emit_jump_insn (gen_bge (label1));
2690 emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
2691 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2692 gen_rtx_LABEL_REF (VOIDmode, label2)));
2695 emit_label (label1);
2696 emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
2697 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2698 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2700 emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
2701 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2703 emit_label (label2);
2705 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2706 fields, and can't be used for REG_NOTES anyway). */
2707 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2712 (define_expand "fixuns_truncsfsi2"
2713 [(set (match_operand:SI 0 "register_operand")
2714 (unsigned_fix:SI (match_operand:SF 1 "register_operand")))]
2717 rtx reg1 = gen_reg_rtx (SFmode);
2718 rtx reg2 = gen_reg_rtx (SFmode);
2719 rtx reg3 = gen_reg_rtx (SImode);
2720 rtx label1 = gen_label_rtx ();
2721 rtx label2 = gen_label_rtx ();
2722 REAL_VALUE_TYPE offset;
2724 real_2expN (&offset, 31);
2726 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2727 do_pending_stack_adjust ();
2729 emit_insn (gen_cmpsf (operands[1], reg1));
2730 emit_jump_insn (gen_bge (label1));
2732 emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2733 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2734 gen_rtx_LABEL_REF (VOIDmode, label2)));
2737 emit_label (label1);
2738 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2739 emit_move_insn (reg3, GEN_INT (trunc_int_for_mode
2740 (BITMASK_HIGH, SImode)));
2742 emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2743 emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2745 emit_label (label2);
2747 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2748 fields, and can't be used for REG_NOTES anyway). */
2749 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2754 (define_expand "fixuns_truncsfdi2"
2755 [(set (match_operand:DI 0 "register_operand")
2756 (unsigned_fix:DI (match_operand:SF 1 "register_operand")))]
2757 "TARGET_HARD_FLOAT && TARGET_64BIT && TARGET_DOUBLE_FLOAT"
2759 rtx reg1 = gen_reg_rtx (SFmode);
2760 rtx reg2 = gen_reg_rtx (SFmode);
2761 rtx reg3 = gen_reg_rtx (DImode);
2762 rtx label1 = gen_label_rtx ();
2763 rtx label2 = gen_label_rtx ();
2764 REAL_VALUE_TYPE offset;
2766 real_2expN (&offset, 63);
2768 emit_move_insn (reg1, CONST_DOUBLE_FROM_REAL_VALUE (offset, SFmode));
2769 do_pending_stack_adjust ();
2771 emit_insn (gen_cmpsf (operands[1], reg1));
2772 emit_jump_insn (gen_bge (label1));
2774 emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
2775 emit_jump_insn (gen_rtx_SET (VOIDmode, pc_rtx,
2776 gen_rtx_LABEL_REF (VOIDmode, label2)));
2779 emit_label (label1);
2780 emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
2781 emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
2782 emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
2784 emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
2785 emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
2787 emit_label (label2);
2789 /* Allow REG_NOTES to be set on last insn (labels don't have enough
2790 fields, and can't be used for REG_NOTES anyway). */
2791 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
2796 ;; ....................
2800 ;; ....................
2802 ;; Bit field extract patterns which use lwl/lwr or ldl/ldr.
2804 (define_expand "extv"
2805 [(set (match_operand 0 "register_operand")
2806 (sign_extract (match_operand:QI 1 "memory_operand")
2807 (match_operand 2 "immediate_operand")
2808 (match_operand 3 "immediate_operand")))]
2811 if (mips_expand_unaligned_load (operands[0], operands[1],
2812 INTVAL (operands[2]),
2813 INTVAL (operands[3])))
2819 (define_expand "extzv"
2820 [(set (match_operand 0 "register_operand")
2821 (zero_extract (match_operand:QI 1 "memory_operand")
2822 (match_operand 2 "immediate_operand")
2823 (match_operand 3 "immediate_operand")))]
2826 if (mips_expand_unaligned_load (operands[0], operands[1],
2827 INTVAL (operands[2]),
2828 INTVAL (operands[3])))
2834 (define_expand "insv"
2835 [(set (zero_extract (match_operand:QI 0 "memory_operand")
2836 (match_operand 1 "immediate_operand")
2837 (match_operand 2 "immediate_operand"))
2838 (match_operand 3 "reg_or_0_operand"))]
2841 if (mips_expand_unaligned_store (operands[0], operands[3],
2842 INTVAL (operands[1]),
2843 INTVAL (operands[2])))
2849 ;; Unaligned word moves generated by the bit field patterns.
2851 ;; As far as the rtl is concerned, both the left-part and right-part
2852 ;; instructions can access the whole field. However, the real operand
2853 ;; refers to just the first or the last byte (depending on endianness).
2854 ;; We therefore use two memory operands to each instruction, one to
2855 ;; describe the rtl effect and one to use in the assembly output.
2857 ;; Operands 0 and 1 are the rtl-level target and source respectively.
2858 ;; This allows us to use the standard length calculations for the "load"
2859 ;; and "store" type attributes.
2861 (define_insn "mov_<load>l"
2862 [(set (match_operand:GPR 0 "register_operand" "=d")
2863 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2864 (match_operand:QI 2 "memory_operand" "m")]
2868 [(set_attr "type" "load")
2869 (set_attr "mode" "<MODE>")])
2871 (define_insn "mov_<load>r"
2872 [(set (match_operand:GPR 0 "register_operand" "=d")
2873 (unspec:GPR [(match_operand:BLK 1 "memory_operand" "m")
2874 (match_operand:QI 2 "memory_operand" "m")
2875 (match_operand:GPR 3 "register_operand" "0")]
2876 UNSPEC_LOAD_RIGHT))]
2879 [(set_attr "type" "load")
2880 (set_attr "mode" "<MODE>")])
2882 (define_insn "mov_<store>l"
2883 [(set (match_operand:BLK 0 "memory_operand" "=m")
2884 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2885 (match_operand:QI 2 "memory_operand" "m")]
2886 UNSPEC_STORE_LEFT))]
2889 [(set_attr "type" "store")
2890 (set_attr "mode" "<MODE>")])
2892 (define_insn "mov_<store>r"
2893 [(set (match_operand:BLK 0 "memory_operand" "+m")
2894 (unspec:BLK [(match_operand:GPR 1 "reg_or_0_operand" "dJ")
2895 (match_operand:QI 2 "memory_operand" "m")
2897 UNSPEC_STORE_RIGHT))]
2900 [(set_attr "type" "store")
2901 (set_attr "mode" "<MODE>")])
2903 ;; An instruction to calculate the high part of a 64-bit SYMBOL_GENERAL.
2904 ;; The required value is:
2906 ;; (%highest(op1) << 48) + (%higher(op1) << 32) + (%hi(op1) << 16)
2908 ;; which translates to:
2910 ;; lui op0,%highest(op1)
2911 ;; daddiu op0,op0,%higher(op1)
2913 ;; daddiu op0,op0,%hi(op1)
2916 ;; The split is deferred until after flow2 to allow the peephole2 below
2918 (define_insn_and_split "*lea_high64"
2919 [(set (match_operand:DI 0 "register_operand" "=d")
2920 (high:DI (match_operand:DI 1 "general_symbolic_operand" "")))]
2921 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
2923 "&& flow2_completed"
2924 [(set (match_dup 0) (high:DI (match_dup 2)))
2925 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 2)))
2926 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))
2927 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
2928 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 16)))]
2930 operands[2] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
2931 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_MID);
2933 [(set_attr "length" "20")])
2935 ;; Use a scratch register to reduce the latency of the above pattern
2936 ;; on superscalar machines. The optimized sequence is:
2938 ;; lui op1,%highest(op2)
2940 ;; daddiu op1,op1,%higher(op2)
2942 ;; daddu op1,op1,op0
2944 [(set (match_operand:DI 1 "register_operand")
2945 (high:DI (match_operand:DI 2 "general_symbolic_operand")))
2946 (match_scratch:DI 0 "d")]
2947 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS"
2948 [(set (match_dup 1) (high:DI (match_dup 3)))
2949 (set (match_dup 0) (high:DI (match_dup 4)))
2950 (set (match_dup 1) (lo_sum:DI (match_dup 1) (match_dup 3)))
2951 (set (match_dup 1) (ashift:DI (match_dup 1) (const_int 32)))
2952 (set (match_dup 1) (plus:DI (match_dup 1) (match_dup 0)))]
2954 operands[3] = mips_unspec_address (operands[2], SYMBOL_64_HIGH);
2955 operands[4] = mips_unspec_address (operands[2], SYMBOL_64_LOW);
2958 ;; On most targets, the expansion of (lo_sum (high X) X) for a 64-bit
2959 ;; SYMBOL_GENERAL X will take 6 cycles. This next pattern allows combine
2960 ;; to merge the HIGH and LO_SUM parts of a move if the HIGH part is only
2961 ;; used once. We can then use the sequence:
2963 ;; lui op0,%highest(op1)
2965 ;; daddiu op0,op0,%higher(op1)
2966 ;; daddiu op2,op2,%lo(op1)
2968 ;; daddu op0,op0,op2
2970 ;; which takes 4 cycles on most superscalar targets.
2971 (define_insn_and_split "*lea64"
2972 [(set (match_operand:DI 0 "register_operand" "=d")
2973 (match_operand:DI 1 "general_symbolic_operand" ""))
2974 (clobber (match_scratch:DI 2 "=&d"))]
2975 "TARGET_EXPLICIT_RELOCS && ABI_HAS_64BIT_SYMBOLS && cse_not_expected"
2977 "&& reload_completed"
2978 [(set (match_dup 0) (high:DI (match_dup 3)))
2979 (set (match_dup 2) (high:DI (match_dup 4)))
2980 (set (match_dup 0) (lo_sum:DI (match_dup 0) (match_dup 3)))
2981 (set (match_dup 2) (lo_sum:DI (match_dup 2) (match_dup 4)))
2982 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32)))
2983 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2)))]
2985 operands[3] = mips_unspec_address (operands[1], SYMBOL_64_HIGH);
2986 operands[4] = mips_unspec_address (operands[1], SYMBOL_64_LOW);
2988 [(set_attr "length" "24")])
2990 ;; Insns to fetch a global symbol from a big GOT.
2992 (define_insn_and_split "*xgot_hi<mode>"
2993 [(set (match_operand:P 0 "register_operand" "=d")
2994 (high:P (match_operand:P 1 "global_got_operand" "")))]
2995 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
2997 "&& reload_completed"
2998 [(set (match_dup 0) (high:P (match_dup 2)))
2999 (set (match_dup 0) (plus:P (match_dup 0) (match_dup 3)))]
3001 operands[2] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3002 operands[3] = pic_offset_table_rtx;
3004 [(set_attr "got" "xgot_high")
3005 (set_attr "mode" "<MODE>")])
3007 (define_insn_and_split "*xgot_lo<mode>"
3008 [(set (match_operand:P 0 "register_operand" "=d")
3009 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3010 (match_operand:P 2 "global_got_operand" "")))]
3011 "TARGET_EXPLICIT_RELOCS && TARGET_XGOT"
3013 "&& reload_completed"
3015 (unspec:P [(match_dup 1) (match_dup 3)] UNSPEC_LOAD_GOT))]
3016 { operands[3] = mips_unspec_address (operands[2], SYMBOL_GOTOFF_GLOBAL); }
3017 [(set_attr "got" "load")
3018 (set_attr "mode" "<MODE>")])
3020 ;; Insns to fetch a global symbol from a normal GOT.
3022 (define_insn_and_split "*got_disp<mode>"
3023 [(set (match_operand:P 0 "register_operand" "=d")
3024 (match_operand:P 1 "global_got_operand" ""))]
3025 "TARGET_EXPLICIT_RELOCS && !TARGET_XGOT"
3027 "&& reload_completed"
3029 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3031 operands[2] = pic_offset_table_rtx;
3032 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_GLOBAL);
3034 [(set_attr "got" "load")
3035 (set_attr "mode" "<MODE>")])
3037 ;; Insns for loading the high part of a local symbol.
3039 (define_insn_and_split "*got_page<mode>"
3040 [(set (match_operand:P 0 "register_operand" "=d")
3041 (high:P (match_operand:P 1 "local_got_operand" "")))]
3042 "TARGET_EXPLICIT_RELOCS"
3044 "&& reload_completed"
3046 (unspec:P [(match_dup 2) (match_dup 3)] UNSPEC_LOAD_GOT))]
3048 operands[2] = pic_offset_table_rtx;
3049 operands[3] = mips_unspec_address (operands[1], SYMBOL_GOTOFF_PAGE);
3051 [(set_attr "got" "load")
3052 (set_attr "mode" "<MODE>")])
3054 ;; Lower-level instructions for loading an address from the GOT.
3055 ;; We could use MEMs, but an unspec gives more optimization
3058 (define_insn "load_got<mode>"
3059 [(set (match_operand:P 0 "register_operand" "=d")
3060 (unspec:P [(match_operand:P 1 "register_operand" "d")
3061 (match_operand:P 2 "immediate_operand" "")]
3064 "<load>\t%0,%R2(%1)"
3065 [(set_attr "type" "load")
3066 (set_attr "mode" "<MODE>")
3067 (set_attr "length" "4")])
3069 ;; Instructions for adding the low 16 bits of an address to a register.
3070 ;; Operand 2 is the address: print_operand works out which relocation
3071 ;; should be applied.
3073 (define_insn "*low<mode>"
3074 [(set (match_operand:P 0 "register_operand" "=d")
3075 (lo_sum:P (match_operand:P 1 "register_operand" "d")
3076 (match_operand:P 2 "immediate_operand" "")))]
3078 "<d>addiu\t%0,%1,%R2"
3079 [(set_attr "type" "arith")
3080 (set_attr "mode" "<MODE>")])
3082 (define_insn "*low<mode>_mips16"
3083 [(set (match_operand:P 0 "register_operand" "=d")
3084 (lo_sum:P (match_operand:P 1 "register_operand" "0")
3085 (match_operand:P 2 "immediate_operand" "")))]
3088 [(set_attr "type" "arith")
3089 (set_attr "mode" "<MODE>")
3090 (set_attr "length" "8")])
3092 ;; 64-bit integer moves
3094 ;; Unlike most other insns, the move insns can't be split with
3095 ;; different predicates, because register spilling and other parts of
3096 ;; the compiler, have memoized the insn number already.
3098 (define_expand "movdi"
3099 [(set (match_operand:DI 0 "")
3100 (match_operand:DI 1 ""))]
3103 if (mips_legitimize_move (DImode, operands[0], operands[1]))
3107 ;; For mips16, we need a special case to handle storing $31 into
3108 ;; memory, since we don't have a constraint to match $31. This
3109 ;; instruction can be generated by save_restore_insns.
3111 (define_insn "*mov<mode>_ra"
3112 [(set (match_operand:GPR 0 "stack_operand" "=m")
3116 [(set_attr "type" "store")
3117 (set_attr "mode" "<MODE>")])
3119 (define_insn "*movdi_32bit"
3120 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,*x,*d,*B*C*D,*B*C*D,*d,*m")
3121 (match_operand:DI 1 "move_operand" "d,i,m,d,*J*d,*x,*d,*m,*B*C*D,*B*C*D"))]
3122 "!TARGET_64BIT && !TARGET_MIPS16
3123 && (register_operand (operands[0], DImode)
3124 || reg_or_0_operand (operands[1], DImode))"
3125 { return mips_output_move (operands[0], operands[1]); }
3126 [(set_attr "type" "arith,arith,load,store,mthilo,mfhilo,xfer,load,xfer,store")
3127 (set_attr "mode" "DI")
3128 (set_attr "length" "8,16,*,*,8,8,8,*,8,*")])
3130 (define_insn "*movdi_32bit_mips16"
3131 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m,*d")
3132 (match_operand:DI 1 "move_operand" "d,d,y,K,N,m,d,*x"))]
3133 "!TARGET_64BIT && TARGET_MIPS16
3134 && (register_operand (operands[0], DImode)
3135 || register_operand (operands[1], DImode))"
3136 { return mips_output_move (operands[0], operands[1]); }
3137 [(set_attr "type" "arith,arith,arith,arith,arith,load,store,mfhilo")
3138 (set_attr "mode" "DI")
3139 (set_attr "length" "8,8,8,8,12,*,*,8")])
3141 (define_insn "*movdi_64bit"
3142 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*x,*B*C*D,*B*C*D,*d,*m")
3143 (match_operand:DI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3144 "TARGET_64BIT && !TARGET_MIPS16
3145 && (register_operand (operands[0], DImode)
3146 || reg_or_0_operand (operands[1], DImode))"
3147 { return mips_output_move (operands[0], operands[1]); }
3148 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,mthilo,xfer,load,xfer,store")
3149 (set_attr "mode" "DI")
3150 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,8,*,8,*")])
3152 (define_insn "*movdi_64bit_mips16"
3153 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3154 (match_operand:DI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3155 "TARGET_64BIT && TARGET_MIPS16
3156 && (register_operand (operands[0], DImode)
3157 || register_operand (operands[1], DImode))"
3158 { return mips_output_move (operands[0], operands[1]); }
3159 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3160 (set_attr "mode" "DI")
3161 (set_attr_alternative "length"
3165 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3168 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3173 (const_string "*")])])
3176 ;; On the mips16, we can split ld $r,N($r) into an add and a load,
3177 ;; when the original load is a 4 byte instruction but the add and the
3178 ;; load are 2 2 byte instructions.
3181 [(set (match_operand:DI 0 "register_operand")
3182 (mem:DI (plus:DI (match_dup 0)
3183 (match_operand:DI 1 "const_int_operand"))))]
3184 "TARGET_64BIT && TARGET_MIPS16 && reload_completed
3185 && !TARGET_DEBUG_D_MODE
3186 && REG_P (operands[0])
3187 && M16_REG_P (REGNO (operands[0]))
3188 && GET_CODE (operands[1]) == CONST_INT
3189 && ((INTVAL (operands[1]) < 0
3190 && INTVAL (operands[1]) >= -0x10)
3191 || (INTVAL (operands[1]) >= 32 * 8
3192 && INTVAL (operands[1]) <= 31 * 8 + 0x8)
3193 || (INTVAL (operands[1]) >= 0
3194 && INTVAL (operands[1]) < 32 * 8
3195 && (INTVAL (operands[1]) & 7) != 0))"
3196 [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 1)))
3197 (set (match_dup 0) (mem:DI (plus:DI (match_dup 0) (match_dup 2))))]
3199 HOST_WIDE_INT val = INTVAL (operands[1]);
3202 operands[2] = const0_rtx;
3203 else if (val >= 32 * 8)
3207 operands[1] = GEN_INT (0x8 + off);
3208 operands[2] = GEN_INT (val - off - 0x8);
3214 operands[1] = GEN_INT (off);
3215 operands[2] = GEN_INT (val - off);
3219 ;; 32-bit Integer moves
3221 ;; Unlike most other insns, the move insns can't be split with
3222 ;; different predicates, because register spilling and other parts of
3223 ;; the compiler, have memoized the insn number already.
3225 (define_expand "movsi"
3226 [(set (match_operand:SI 0 "")
3227 (match_operand:SI 1 ""))]
3230 if (mips_legitimize_move (SImode, operands[0], operands[1]))
3234 ;; The difference between these two is whether or not ints are allowed
3235 ;; in FP registers (off by default, use -mdebugh to enable).
3237 (define_insn "*movsi_internal"
3238 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*f,*d,*m,*d,*z,*x,*B*C*D,*B*C*D,*d,*m")
3239 (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*f,*d*J,*m,*f,*f,*z,*d,*J*d,*d,*m,*B*C*D,*B*C*D"))]
3241 && (register_operand (operands[0], SImode)
3242 || reg_or_0_operand (operands[1], SImode))"
3243 { return mips_output_move (operands[0], operands[1]); }
3244 [(set_attr "type" "arith,const,const,load,store,fmove,xfer,fpload,xfer,fpstore,xfer,xfer,mthilo,xfer,load,xfer,store")
3245 (set_attr "mode" "SI")
3246 (set_attr "length" "4,*,*,*,*,4,4,*,4,*,4,4,4,4,*,4,*")])
3248 (define_insn "*movsi_mips16"
3249 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,m")
3250 (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,m,d"))]
3252 && (register_operand (operands[0], SImode)
3253 || register_operand (operands[1], SImode))"
3254 { return mips_output_move (operands[0], operands[1]); }
3255 [(set_attr "type" "arith,arith,arith,arith,arith,const,load,store")
3256 (set_attr "mode" "SI")
3257 (set_attr_alternative "length"
3261 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3264 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3269 (const_string "*")])])
3271 ;; On the mips16, we can split lw $r,N($r) into an add and a load,
3272 ;; when the original load is a 4 byte instruction but the add and the
3273 ;; load are 2 2 byte instructions.
3276 [(set (match_operand:SI 0 "register_operand")
3277 (mem:SI (plus:SI (match_dup 0)
3278 (match_operand:SI 1 "const_int_operand"))))]
3279 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3280 && REG_P (operands[0])
3281 && M16_REG_P (REGNO (operands[0]))
3282 && GET_CODE (operands[1]) == CONST_INT
3283 && ((INTVAL (operands[1]) < 0
3284 && INTVAL (operands[1]) >= -0x80)
3285 || (INTVAL (operands[1]) >= 32 * 4
3286 && INTVAL (operands[1]) <= 31 * 4 + 0x7c)
3287 || (INTVAL (operands[1]) >= 0
3288 && INTVAL (operands[1]) < 32 * 4
3289 && (INTVAL (operands[1]) & 3) != 0))"
3290 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3291 (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))]
3293 HOST_WIDE_INT val = INTVAL (operands[1]);
3296 operands[2] = const0_rtx;
3297 else if (val >= 32 * 4)
3301 operands[1] = GEN_INT (0x7c + off);
3302 operands[2] = GEN_INT (val - off - 0x7c);
3308 operands[1] = GEN_INT (off);
3309 operands[2] = GEN_INT (val - off);
3313 ;; On the mips16, we can split a load of certain constants into a load
3314 ;; and an add. This turns a 4 byte instruction into 2 2 byte
3318 [(set (match_operand:SI 0 "register_operand")
3319 (match_operand:SI 1 "const_int_operand"))]
3320 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3321 && REG_P (operands[0])
3322 && M16_REG_P (REGNO (operands[0]))
3323 && GET_CODE (operands[1]) == CONST_INT
3324 && INTVAL (operands[1]) >= 0x100
3325 && INTVAL (operands[1]) <= 0xff + 0x7f"
3326 [(set (match_dup 0) (match_dup 1))
3327 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2)))]
3329 int val = INTVAL (operands[1]);
3331 operands[1] = GEN_INT (0xff);
3332 operands[2] = GEN_INT (val - 0xff);
3335 ;; This insn handles moving CCmode values. It's really just a
3336 ;; slightly simplified copy of movsi_internal2, with additional cases
3337 ;; to move a condition register to a general register and to move
3338 ;; between the general registers and the floating point registers.
3340 (define_insn "movcc"
3341 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,*d,*d,*m,*d,*f,*f,*f,*m")
3342 (match_operand:CC 1 "general_operand" "z,*d,*m,*d,*f,*d,*f,*m,*f"))]
3343 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3344 { return mips_output_move (operands[0], operands[1]); }
3345 [(set_attr "type" "xfer,arith,load,store,xfer,xfer,fmove,fpload,fpstore")
3346 (set_attr "mode" "SI")
3347 (set_attr "length" "8,4,*,*,4,4,4,*,*")])
3349 ;; Reload condition code registers. reload_incc and reload_outcc
3350 ;; both handle moves from arbitrary operands into condition code
3351 ;; registers. reload_incc handles the more common case in which
3352 ;; a source operand is constrained to be in a condition-code
3353 ;; register, but has not been allocated to one.
3355 ;; Sometimes, such as in movcc, we have a CCmode destination whose
3356 ;; constraints do not include 'z'. reload_outcc handles the case
3357 ;; when such an operand is allocated to a condition-code register.
3359 ;; Note that reloads from a condition code register to some
3360 ;; other location can be done using ordinary moves. Moving
3361 ;; into a GPR takes a single movcc, moving elsewhere takes
3362 ;; two. We can leave these cases to the generic reload code.
3363 (define_expand "reload_incc"
3364 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3365 (match_operand:CC 1 "general_operand" ""))
3366 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3367 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3369 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3373 (define_expand "reload_outcc"
3374 [(set (match_operand:CC 0 "fcc_reload_operand" "=z")
3375 (match_operand:CC 1 "register_operand" ""))
3376 (clobber (match_operand:TF 2 "register_operand" "=&f"))]
3377 "ISA_HAS_8CC && TARGET_HARD_FLOAT"
3379 mips_emit_fcc_reload (operands[0], operands[1], operands[2]);
3383 ;; MIPS4 supports loading and storing a floating point register from
3384 ;; the sum of two general registers. We use two versions for each of
3385 ;; these four instructions: one where the two general registers are
3386 ;; SImode, and one where they are DImode. This is because general
3387 ;; registers will be in SImode when they hold 32 bit values, but,
3388 ;; since the 32 bit values are always sign extended, the [ls][wd]xc1
3389 ;; instructions will still work correctly.
3391 ;; ??? Perhaps it would be better to support these instructions by
3392 ;; modifying GO_IF_LEGITIMATE_ADDRESS and friends. However, since
3393 ;; these instructions can only be used to load and store floating
3394 ;; point registers, that would probably cause trouble in reload.
3396 (define_insn "*<ANYF:loadx>_<P:mode>"
3397 [(set (match_operand:ANYF 0 "register_operand" "=f")
3398 (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3399 (match_operand:P 2 "register_operand" "d"))))]
3401 "<ANYF:loadx>\t%0,%1(%2)"
3402 [(set_attr "type" "fpidxload")
3403 (set_attr "mode" "<ANYF:UNITMODE>")])
3405 (define_insn "*<ANYF:storex>_<P:mode>"
3406 [(set (mem:ANYF (plus:P (match_operand:P 1 "register_operand" "d")
3407 (match_operand:P 2 "register_operand" "d")))
3408 (match_operand:ANYF 0 "register_operand" "f"))]
3410 "<ANYF:storex>\t%0,%1(%2)"
3411 [(set_attr "type" "fpidxstore")
3412 (set_attr "mode" "<ANYF:UNITMODE>")])
3414 ;; 16-bit Integer moves
3416 ;; Unlike most other insns, the move insns can't be split with
3417 ;; different predicates, because register spilling and other parts of
3418 ;; the compiler, have memoized the insn number already.
3419 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3421 (define_expand "movhi"
3422 [(set (match_operand:HI 0 "")
3423 (match_operand:HI 1 ""))]
3426 if (mips_legitimize_move (HImode, operands[0], operands[1]))
3430 (define_insn "*movhi_internal"
3431 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3432 (match_operand:HI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3434 && (register_operand (operands[0], HImode)
3435 || reg_or_0_operand (operands[1], HImode))"
3445 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3446 (set_attr "mode" "HI")
3447 (set_attr "length" "4,4,*,*,4,4,4,4")])
3449 (define_insn "*movhi_mips16"
3450 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3451 (match_operand:HI 1 "move_operand" "d,d,y,K,N,m,d"))]
3453 && (register_operand (operands[0], HImode)
3454 || register_operand (operands[1], HImode))"
3463 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3464 (set_attr "mode" "HI")
3465 (set_attr_alternative "length"
3469 (if_then_else (match_operand:VOID 1 "m16_uimm8_1")
3472 (if_then_else (match_operand:VOID 1 "m16_nuimm8_1")
3476 (const_string "*")])])
3479 ;; On the mips16, we can split lh $r,N($r) into an add and a load,
3480 ;; when the original load is a 4 byte instruction but the add and the
3481 ;; load are 2 2 byte instructions.
3484 [(set (match_operand:HI 0 "register_operand")
3485 (mem:HI (plus:SI (match_dup 0)
3486 (match_operand:SI 1 "const_int_operand"))))]
3487 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3488 && REG_P (operands[0])
3489 && M16_REG_P (REGNO (operands[0]))
3490 && GET_CODE (operands[1]) == CONST_INT
3491 && ((INTVAL (operands[1]) < 0
3492 && INTVAL (operands[1]) >= -0x80)
3493 || (INTVAL (operands[1]) >= 32 * 2
3494 && INTVAL (operands[1]) <= 31 * 2 + 0x7e)
3495 || (INTVAL (operands[1]) >= 0
3496 && INTVAL (operands[1]) < 32 * 2
3497 && (INTVAL (operands[1]) & 1) != 0))"
3498 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3499 (set (match_dup 0) (mem:HI (plus:SI (match_dup 0) (match_dup 2))))]
3501 HOST_WIDE_INT val = INTVAL (operands[1]);
3504 operands[2] = const0_rtx;
3505 else if (val >= 32 * 2)
3509 operands[1] = GEN_INT (0x7e + off);
3510 operands[2] = GEN_INT (val - off - 0x7e);
3516 operands[1] = GEN_INT (off);
3517 operands[2] = GEN_INT (val - off);
3521 ;; 8-bit Integer moves
3523 ;; Unlike most other insns, the move insns can't be split with
3524 ;; different predicates, because register spilling and other parts of
3525 ;; the compiler, have memoized the insn number already.
3526 ;; Unsigned loads are used because LOAD_EXTEND_OP returns ZERO_EXTEND.
3528 (define_expand "movqi"
3529 [(set (match_operand:QI 0 "")
3530 (match_operand:QI 1 ""))]
3533 if (mips_legitimize_move (QImode, operands[0], operands[1]))
3537 (define_insn "*movqi_internal"
3538 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,*d,*f,*f,*x")
3539 (match_operand:QI 1 "move_operand" "d,I,m,dJ,*f,*d,*f,*d"))]
3541 && (register_operand (operands[0], QImode)
3542 || reg_or_0_operand (operands[1], QImode))"
3552 [(set_attr "type" "arith,arith,load,store,xfer,xfer,fmove,mthilo")
3553 (set_attr "mode" "QI")
3554 (set_attr "length" "4,4,*,*,4,4,4,4")])
3556 (define_insn "*movqi_mips16"
3557 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,y,d,d,d,d,m")
3558 (match_operand:QI 1 "move_operand" "d,d,y,K,N,m,d"))]
3560 && (register_operand (operands[0], QImode)
3561 || register_operand (operands[1], QImode))"
3570 [(set_attr "type" "arith,arith,arith,arith,arith,load,store")
3571 (set_attr "mode" "QI")
3572 (set_attr "length" "4,4,4,4,8,*,*")])
3574 ;; On the mips16, we can split lb $r,N($r) into an add and a load,
3575 ;; when the original load is a 4 byte instruction but the add and the
3576 ;; load are 2 2 byte instructions.
3579 [(set (match_operand:QI 0 "register_operand")
3580 (mem:QI (plus:SI (match_dup 0)
3581 (match_operand:SI 1 "const_int_operand"))))]
3582 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
3583 && REG_P (operands[0])
3584 && M16_REG_P (REGNO (operands[0]))
3585 && GET_CODE (operands[1]) == CONST_INT
3586 && ((INTVAL (operands[1]) < 0
3587 && INTVAL (operands[1]) >= -0x80)
3588 || (INTVAL (operands[1]) >= 32
3589 && INTVAL (operands[1]) <= 31 + 0x7f))"
3590 [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))
3591 (set (match_dup 0) (mem:QI (plus:SI (match_dup 0) (match_dup 2))))]
3593 HOST_WIDE_INT val = INTVAL (operands[1]);
3596 operands[2] = const0_rtx;
3599 operands[1] = GEN_INT (0x7f);
3600 operands[2] = GEN_INT (val - 0x7f);
3604 ;; 32-bit floating point moves
3606 (define_expand "movsf"
3607 [(set (match_operand:SF 0 "")
3608 (match_operand:SF 1 ""))]
3611 if (mips_legitimize_move (SFmode, operands[0], operands[1]))
3615 (define_insn "*movsf_hardfloat"
3616 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3617 (match_operand:SF 1 "move_operand" "f,G,m,f,G,*d,*f,*G*d,*m,*d"))]
3619 && (register_operand (operands[0], SFmode)
3620 || reg_or_0_operand (operands[1], SFmode))"
3621 { return mips_output_move (operands[0], operands[1]); }
3622 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3623 (set_attr "mode" "SF")
3624 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3626 (define_insn "*movsf_softfloat"
3627 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,m")
3628 (match_operand:SF 1 "move_operand" "Gd,m,d"))]
3629 "TARGET_SOFT_FLOAT && !TARGET_MIPS16
3630 && (register_operand (operands[0], SFmode)
3631 || reg_or_0_operand (operands[1], SFmode))"
3632 { return mips_output_move (operands[0], operands[1]); }
3633 [(set_attr "type" "arith,load,store")
3634 (set_attr "mode" "SF")
3635 (set_attr "length" "4,*,*")])
3637 (define_insn "*movsf_mips16"
3638 [(set (match_operand:SF 0 "nonimmediate_operand" "=d,y,d,d,m")
3639 (match_operand:SF 1 "move_operand" "d,d,y,m,d"))]
3641 && (register_operand (operands[0], SFmode)
3642 || register_operand (operands[1], SFmode))"
3643 { return mips_output_move (operands[0], operands[1]); }
3644 [(set_attr "type" "arith,arith,arith,load,store")
3645 (set_attr "mode" "SF")
3646 (set_attr "length" "4,4,4,*,*")])
3649 ;; 64-bit floating point moves
3651 (define_expand "movdf"
3652 [(set (match_operand:DF 0 "")
3653 (match_operand:DF 1 ""))]
3656 if (mips_legitimize_move (DFmode, operands[0], operands[1]))
3660 (define_insn "*movdf_hardfloat_64bit"
3661 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3662 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3663 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_64BIT
3664 && (register_operand (operands[0], DFmode)
3665 || reg_or_0_operand (operands[1], DFmode))"
3666 { return mips_output_move (operands[0], operands[1]); }
3667 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3668 (set_attr "mode" "DF")
3669 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3671 (define_insn "*movdf_hardfloat_32bit"
3672 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3673 (match_operand:DF 1 "move_operand" "f,G,m,f,G,*d,*f,*d*G,*m,*d"))]
3674 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT
3675 && (register_operand (operands[0], DFmode)
3676 || reg_or_0_operand (operands[1], DFmode))"
3677 { return mips_output_move (operands[0], operands[1]); }
3678 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3679 (set_attr "mode" "DF")
3680 (set_attr "length" "4,8,*,*,*,8,8,8,*,*")])
3682 (define_insn "*movdf_softfloat"
3683 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,m,d,f,f")
3684 (match_operand:DF 1 "move_operand" "dG,m,dG,f,d,f"))]
3685 "(TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT) && !TARGET_MIPS16
3686 && (register_operand (operands[0], DFmode)
3687 || reg_or_0_operand (operands[1], DFmode))"
3688 { return mips_output_move (operands[0], operands[1]); }
3689 [(set_attr "type" "arith,load,store,xfer,xfer,fmove")
3690 (set_attr "mode" "DF")
3691 (set_attr "length" "8,*,*,4,4,4")])
3693 (define_insn "*movdf_mips16"
3694 [(set (match_operand:DF 0 "nonimmediate_operand" "=d,y,d,d,m")
3695 (match_operand:DF 1 "move_operand" "d,d,y,m,d"))]
3697 && (register_operand (operands[0], DFmode)
3698 || register_operand (operands[1], DFmode))"
3699 { return mips_output_move (operands[0], operands[1]); }
3700 [(set_attr "type" "arith,arith,arith,load,store")
3701 (set_attr "mode" "DF")
3702 (set_attr "length" "8,8,8,*,*")])
3705 [(set (match_operand:DI 0 "nonimmediate_operand")
3706 (match_operand:DI 1 "move_operand"))]
3707 "reload_completed && !TARGET_64BIT
3708 && mips_split_64bit_move_p (operands[0], operands[1])"
3711 mips_split_64bit_move (operands[0], operands[1]);
3716 [(set (match_operand:DF 0 "nonimmediate_operand")
3717 (match_operand:DF 1 "move_operand"))]
3718 "reload_completed && !TARGET_64BIT
3719 && mips_split_64bit_move_p (operands[0], operands[1])"
3722 mips_split_64bit_move (operands[0], operands[1]);
3726 ;; When generating mips16 code, split moves of negative constants into
3727 ;; a positive "li" followed by a negation.
3729 [(set (match_operand 0 "register_operand")
3730 (match_operand 1 "const_int_operand"))]
3731 "TARGET_MIPS16 && reload_completed && INTVAL (operands[1]) < 0"
3735 (neg:SI (match_dup 2)))]
3737 operands[2] = gen_lowpart (SImode, operands[0]);
3738 operands[3] = GEN_INT (-INTVAL (operands[1]));
3741 ;; 64-bit paired-single floating point moves
3743 (define_expand "movv2sf"
3744 [(set (match_operand:V2SF 0)
3745 (match_operand:V2SF 1))]
3746 "TARGET_PAIRED_SINGLE_FLOAT"
3748 if (mips_legitimize_move (V2SFmode, operands[0], operands[1]))
3752 (define_insn "movv2sf_hardfloat_64bit"
3753 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=f,f,f,m,m,*f,*d,*d,*d,*m")
3754 (match_operand:V2SF 1 "move_operand" "f,YG,m,f,YG,*d,*f,*d*YG,*m,*d"))]
3755 "TARGET_PAIRED_SINGLE_FLOAT
3757 && (register_operand (operands[0], V2SFmode)
3758 || reg_or_0_operand (operands[1], V2SFmode))"
3759 { return mips_output_move (operands[0], operands[1]); }
3760 [(set_attr "type" "fmove,xfer,fpload,fpstore,store,xfer,xfer,arith,load,store")
3761 (set_attr "mode" "SF")
3762 (set_attr "length" "4,4,*,*,*,4,4,4,*,*")])
3764 ;; The HI and LO registers are not truly independent. If we move an mthi
3765 ;; instruction before an mflo instruction, it will make the result of the
3766 ;; mflo unpredictable. The same goes for mtlo and mfhi.
3768 ;; We cope with this by making the mflo and mfhi patterns use both HI and LO.
3769 ;; Operand 1 is the register we want, operand 2 is the other one.
3771 ;; When generating VR4120 or VR4130 code, we use macc{,hi} and
3772 ;; dmacc{,hi} instead of mfhi and mflo. This avoids both the normal
3773 ;; MIPS III hi/lo hazards and the errata related to -mfix-vr4130.
3775 (define_expand "mfhilo_<mode>"
3776 [(set (match_operand:GPR 0 "register_operand")
3777 (unspec:GPR [(match_operand:GPR 1 "register_operand")
3778 (match_operand:GPR 2 "register_operand")]
3781 (define_insn "*mfhilo_<mode>"
3782 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3783 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3784 (match_operand:GPR 2 "register_operand" "l,h")]
3788 [(set_attr "type" "mfhilo")
3789 (set_attr "mode" "<MODE>")])
3791 (define_insn "*mfhilo_<mode>_macc"
3792 [(set (match_operand:GPR 0 "register_operand" "=d,d")
3793 (unspec:GPR [(match_operand:GPR 1 "register_operand" "h,l")
3794 (match_operand:GPR 2 "register_operand" "l,h")]
3798 if (REGNO (operands[1]) == HI_REGNUM)
3799 return "<d>macchi\t%0,%.,%.";
3801 return "<d>macc\t%0,%.,%.";
3803 [(set_attr "type" "mfhilo")
3804 (set_attr "mode" "<MODE>")])
3806 ;; Patterns for loading or storing part of a paired floating point
3807 ;; register. We need them because odd-numbered floating-point registers
3808 ;; are not fully independent: see mips_split_64bit_move.
3810 ;; Load the low word of operand 0 with operand 1.
3811 (define_insn "load_df_low"
3812 [(set (match_operand:DF 0 "register_operand" "=f,f")
3813 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")]
3814 UNSPEC_LOAD_DF_LOW))]
3815 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3817 operands[0] = mips_subword (operands[0], 0);
3818 return mips_output_move (operands[0], operands[1]);
3820 [(set_attr "type" "xfer,fpload")
3821 (set_attr "mode" "SF")])
3823 ;; Load the high word of operand 0 from operand 1, preserving the value
3825 (define_insn "load_df_high"
3826 [(set (match_operand:DF 0 "register_operand" "=f,f")
3827 (unspec:DF [(match_operand:SI 1 "general_operand" "dJ,m")
3828 (match_operand:DF 2 "register_operand" "0,0")]
3829 UNSPEC_LOAD_DF_HIGH))]
3830 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3832 operands[0] = mips_subword (operands[0], 1);
3833 return mips_output_move (operands[0], operands[1]);
3835 [(set_attr "type" "xfer,fpload")
3836 (set_attr "mode" "SF")])
3838 ;; Store the high word of operand 1 in operand 0. The corresponding
3839 ;; low-word move is done in the normal way.
3840 (define_insn "store_df_high"
3841 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,m")
3842 (unspec:SI [(match_operand:DF 1 "register_operand" "f,f")]
3843 UNSPEC_STORE_DF_HIGH))]
3844 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && !TARGET_64BIT"
3846 operands[1] = mips_subword (operands[1], 1);
3847 return mips_output_move (operands[0], operands[1]);
3849 [(set_attr "type" "xfer,fpstore")
3850 (set_attr "mode" "SF")])
3852 ;; Insn to initialize $gp for n32/n64 abicalls. Operand 0 is the offset
3853 ;; of _gp from the start of this function. Operand 1 is the incoming
3854 ;; function address.
3855 (define_insn_and_split "loadgp"
3856 [(unspec_volatile [(match_operand 0 "" "")
3857 (match_operand 1 "register_operand" "")] UNSPEC_LOADGP)]
3858 "TARGET_ABICALLS && TARGET_NEWABI"
3861 [(set (match_dup 2) (match_dup 3))
3862 (set (match_dup 2) (match_dup 4))
3863 (set (match_dup 2) (match_dup 5))]
3865 operands[2] = pic_offset_table_rtx;
3866 operands[3] = gen_rtx_HIGH (Pmode, operands[0]);
3867 operands[4] = gen_rtx_PLUS (Pmode, operands[2], operands[1]);
3868 operands[5] = gen_rtx_LO_SUM (Pmode, operands[2], operands[0]);
3870 [(set_attr "length" "12")])
3872 ;; The use of gp is hidden when not using explicit relocations.
3873 ;; This blockage instruction prevents the gp load from being
3874 ;; scheduled after an implicit use of gp. It also prevents
3875 ;; the load from being deleted as dead.
3876 (define_insn "loadgp_blockage"
3877 [(unspec_volatile [(reg:DI 28)] UNSPEC_BLOCKAGE)]
3880 [(set_attr "type" "unknown")
3881 (set_attr "mode" "none")
3882 (set_attr "length" "0")])
3884 ;; Emit a .cprestore directive, which normally expands to a single store
3885 ;; instruction. Note that we continue to use .cprestore for explicit reloc
3886 ;; code so that jals inside inline asms will work correctly.
3887 (define_insn "cprestore"
3888 [(unspec_volatile [(match_operand 0 "const_int_operand" "I,i")]
3892 if (set_nomacro && which_alternative == 1)
3893 return ".set\tmacro\;.cprestore\t%0\;.set\tnomacro";
3895 return ".cprestore\t%0";
3897 [(set_attr "type" "store")
3898 (set_attr "length" "4,12")])
3900 ;; Block moves, see mips.c for more details.
3901 ;; Argument 0 is the destination
3902 ;; Argument 1 is the source
3903 ;; Argument 2 is the length
3904 ;; Argument 3 is the alignment
3906 (define_expand "movmemsi"
3907 [(parallel [(set (match_operand:BLK 0 "general_operand")
3908 (match_operand:BLK 1 "general_operand"))
3909 (use (match_operand:SI 2 ""))
3910 (use (match_operand:SI 3 "const_int_operand"))])]
3911 "!TARGET_MIPS16 && !TARGET_MEMCPY"
3913 if (mips_expand_block_move (operands[0], operands[1], operands[2]))
3920 ;; ....................
3924 ;; ....................
3926 (define_expand "<optab><mode>3"
3927 [(set (match_operand:GPR 0 "register_operand")
3928 (any_shift:GPR (match_operand:GPR 1 "register_operand")
3929 (match_operand:SI 2 "arith_operand")))]
3932 /* On the mips16, a shift of more than 8 is a four byte instruction,
3933 so, for a shift between 8 and 16, it is just as fast to do two
3934 shifts of 8 or less. If there is a lot of shifting going on, we
3935 may win in CSE. Otherwise combine will put the shifts back
3936 together again. This can be called by function_arg, so we must
3937 be careful not to allocate a new register if we've reached the
3941 && GET_CODE (operands[2]) == CONST_INT
3942 && INTVAL (operands[2]) > 8
3943 && INTVAL (operands[2]) <= 16
3944 && !reload_in_progress
3945 && !reload_completed)
3947 rtx temp = gen_reg_rtx (<MODE>mode);
3949 emit_insn (gen_<optab><mode>3 (temp, operands[1], GEN_INT (8)));
3950 emit_insn (gen_<optab><mode>3 (operands[0], temp,
3951 GEN_INT (INTVAL (operands[2]) - 8)));
3956 (define_insn "*<optab><mode>3"
3957 [(set (match_operand:GPR 0 "register_operand" "=d")
3958 (any_shift:GPR (match_operand:GPR 1 "register_operand" "d")
3959 (match_operand:SI 2 "arith_operand" "dI")))]
3962 if (GET_CODE (operands[2]) == CONST_INT)
3963 operands[2] = GEN_INT (INTVAL (operands[2])
3964 & (GET_MODE_BITSIZE (<MODE>mode) - 1));
3966 return "<d><insn>\t%0,%1,%2";
3968 [(set_attr "type" "shift")
3969 (set_attr "mode" "<MODE>")])
3971 (define_insn "*<optab>si3_extend"
3972 [(set (match_operand:DI 0 "register_operand" "=d")
3974 (any_shift:SI (match_operand:SI 1 "register_operand" "d")
3975 (match_operand:SI 2 "arith_operand" "dI"))))]
3976 "TARGET_64BIT && !TARGET_MIPS16"
3978 if (GET_CODE (operands[2]) == CONST_INT)
3979 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
3981 return "<insn>\t%0,%1,%2";
3983 [(set_attr "type" "shift")
3984 (set_attr "mode" "SI")])
3986 (define_insn "*<optab>si3_mips16"
3987 [(set (match_operand:SI 0 "register_operand" "=d,d")
3988 (any_shift:SI (match_operand:SI 1 "register_operand" "0,d")
3989 (match_operand:SI 2 "arith_operand" "d,I")))]
3992 if (which_alternative == 0)
3993 return "<insn>\t%0,%2";
3995 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
3996 return "<insn>\t%0,%1,%2";
3998 [(set_attr "type" "shift")
3999 (set_attr "mode" "SI")
4000 (set_attr_alternative "length"
4002 (if_then_else (match_operand 2 "m16_uimm3_b")
4006 ;; We need separate DImode MIPS16 patterns because of the irregularity
4008 (define_insn "*ashldi3_mips16"
4009 [(set (match_operand:DI 0 "register_operand" "=d,d")
4010 (ashift:DI (match_operand:DI 1 "register_operand" "0,d")
4011 (match_operand:SI 2 "arith_operand" "d,I")))]
4012 "TARGET_64BIT && TARGET_MIPS16"
4014 if (which_alternative == 0)
4015 return "dsll\t%0,%2";
4017 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4018 return "dsll\t%0,%1,%2";
4020 [(set_attr "type" "shift")
4021 (set_attr "mode" "DI")
4022 (set_attr_alternative "length"
4024 (if_then_else (match_operand 2 "m16_uimm3_b")
4028 (define_insn "*ashrdi3_mips16"
4029 [(set (match_operand:DI 0 "register_operand" "=d,d")
4030 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4031 (match_operand:SI 2 "arith_operand" "d,I")))]
4032 "TARGET_64BIT && TARGET_MIPS16"
4034 if (GET_CODE (operands[2]) == CONST_INT)
4035 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4037 return "dsra\t%0,%2";
4039 [(set_attr "type" "shift")
4040 (set_attr "mode" "DI")
4041 (set_attr_alternative "length"
4043 (if_then_else (match_operand 2 "m16_uimm3_b")
4047 (define_insn "*lshrdi3_mips16"
4048 [(set (match_operand:DI 0 "register_operand" "=d,d")
4049 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0,0")
4050 (match_operand:SI 2 "arith_operand" "d,I")))]
4051 "TARGET_64BIT && TARGET_MIPS16"
4053 if (GET_CODE (operands[2]) == CONST_INT)
4054 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
4056 return "dsrl\t%0,%2";
4058 [(set_attr "type" "shift")
4059 (set_attr "mode" "DI")
4060 (set_attr_alternative "length"
4062 (if_then_else (match_operand 2 "m16_uimm3_b")
4066 ;; On the mips16, we can split a 4 byte shift into 2 2 byte shifts.
4069 [(set (match_operand:GPR 0 "register_operand")
4070 (any_shift:GPR (match_operand:GPR 1 "register_operand")
4071 (match_operand:GPR 2 "const_int_operand")))]
4072 "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE
4073 && GET_CODE (operands[2]) == CONST_INT
4074 && INTVAL (operands[2]) > 8
4075 && INTVAL (operands[2]) <= 16"
4076 [(set (match_dup 0) (any_shift:GPR (match_dup 1) (const_int 8)))
4077 (set (match_dup 0) (any_shift:GPR (match_dup 0) (match_dup 2)))]
4078 { operands[2] = GEN_INT (INTVAL (operands[2]) - 8); })
4080 ;; If we load a byte on the mips16 as a bitfield, the resulting
4081 ;; sequence of instructions is too complicated for combine, because it
4082 ;; involves four instructions: a load, a shift, a constant load into a
4083 ;; register, and an and (the key problem here is that the mips16 does
4084 ;; not have and immediate). We recognize a shift of a load in order
4085 ;; to make it simple enough for combine to understand.
4087 ;; The length here is the worst case: the length of the split version
4088 ;; will be more accurate.
4089 (define_insn_and_split ""
4090 [(set (match_operand:SI 0 "register_operand" "=d")
4091 (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
4092 (match_operand:SI 2 "immediate_operand" "I")))]
4096 [(set (match_dup 0) (match_dup 1))
4097 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 2)))]
4099 [(set_attr "type" "load")
4100 (set_attr "mode" "SI")
4101 (set_attr "length" "16")])
4103 (define_insn "rotr<mode>3"
4104 [(set (match_operand:GPR 0 "register_operand" "=d")
4105 (rotatert:GPR (match_operand:GPR 1 "register_operand" "d")
4106 (match_operand:SI 2 "arith_operand" "dI")))]
4107 "ISA_HAS_ROTR_<MODE>"
4109 if (GET_CODE (operands[2]) == CONST_INT)
4110 gcc_assert (INTVAL (operands[2]) >= 0
4111 && INTVAL (operands[2]) < GET_MODE_BITSIZE (<MODE>mode));
4113 return "<d>ror\t%0,%1,%2";
4115 [(set_attr "type" "shift")
4116 (set_attr "mode" "<MODE>")])
4119 ;; ....................
4123 ;; ....................
4125 ;; Flow here is rather complex:
4127 ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the arguments
4128 ;; into cmp_operands[] but generates no RTL.
4130 ;; 2) The appropriate branch define_expand is called, which then
4131 ;; creates the appropriate RTL for the comparison and branch.
4132 ;; Different CC modes are used, based on what type of branch is
4133 ;; done, so that we can constrain things appropriately. There
4134 ;; are assumptions in the rest of GCC that break if we fold the
4135 ;; operands into the branches for integer operations, and use cc0
4136 ;; for floating point, so we use the fp status register instead.
4137 ;; If needed, an appropriate temporary is created to hold the
4138 ;; of the integer compare.
4140 (define_expand "cmp<mode>"
4142 (compare:CC (match_operand:GPR 0 "register_operand")
4143 (match_operand:GPR 1 "nonmemory_operand")))]
4146 cmp_operands[0] = operands[0];
4147 cmp_operands[1] = operands[1];
4151 (define_expand "cmp<mode>"
4153 (compare:CC (match_operand:SCALARF 0 "register_operand")
4154 (match_operand:SCALARF 1 "register_operand")))]
4157 cmp_operands[0] = operands[0];
4158 cmp_operands[1] = operands[1];
4163 ;; ....................
4165 ;; CONDITIONAL BRANCHES
4167 ;; ....................
4169 ;; Conditional branches on floating-point equality tests.
4171 (define_insn "branch_fp"
4174 (match_operator:CC 0 "comparison_operator"
4175 [(match_operand:CC 2 "register_operand" "z")
4177 (label_ref (match_operand 1 "" ""))
4181 return mips_output_conditional_branch (insn,
4183 /*two_operands_p=*/0,
4186 get_attr_length (insn));
4188 [(set_attr "type" "branch")
4189 (set_attr "mode" "none")])
4191 (define_insn "branch_fp_inverted"
4194 (match_operator:CC 0 "comparison_operator"
4195 [(match_operand:CC 2 "register_operand" "z")
4198 (label_ref (match_operand 1 "" ""))))]
4201 return mips_output_conditional_branch (insn,
4203 /*two_operands_p=*/0,
4206 get_attr_length (insn));
4208 [(set_attr "type" "branch")
4209 (set_attr "mode" "none")])
4211 ;; Conditional branches on comparisons with zero.
4213 (define_insn "*branch_zero<mode>"
4216 (match_operator:GPR 0 "comparison_operator"
4217 [(match_operand:GPR 2 "register_operand" "d")
4219 (label_ref (match_operand 1 "" ""))
4223 return mips_output_conditional_branch (insn,
4225 /*two_operands_p=*/0,
4228 get_attr_length (insn));
4230 [(set_attr "type" "branch")
4231 (set_attr "mode" "none")])
4233 (define_insn "*branch_zero<mode>_inverted"
4236 (match_operator:GPR 0 "comparison_operator"
4237 [(match_operand:GPR 2 "register_operand" "d")
4240 (label_ref (match_operand 1 "" ""))))]
4243 return mips_output_conditional_branch (insn,
4245 /*two_operands_p=*/0,
4248 get_attr_length (insn));
4250 [(set_attr "type" "branch")
4251 (set_attr "mode" "none")])
4253 ;; Conditional branch on equality comparison.
4255 (define_insn "*branch_equality<mode>"
4258 (match_operator:GPR 0 "equality_operator"
4259 [(match_operand:GPR 2 "register_operand" "d")
4260 (match_operand:GPR 3 "register_operand" "d")])
4261 (label_ref (match_operand 1 "" ""))
4265 return mips_output_conditional_branch (insn,
4267 /*two_operands_p=*/1,
4270 get_attr_length (insn));
4272 [(set_attr "type" "branch")
4273 (set_attr "mode" "none")])
4275 (define_insn "*branch_equality<mode>_inverted"
4278 (match_operator:GPR 0 "equality_operator"
4279 [(match_operand:GPR 2 "register_operand" "d")
4280 (match_operand:GPR 3 "register_operand" "d")])
4282 (label_ref (match_operand 1 "" ""))))]
4285 return mips_output_conditional_branch (insn,
4287 /*two_operands_p=*/1,
4290 get_attr_length (insn));
4292 [(set_attr "type" "branch")
4293 (set_attr "mode" "none")])
4297 (define_insn "*branch_equality<mode>_mips16"
4300 (match_operator:GPR 0 "equality_operator"
4301 [(match_operand:GPR 1 "register_operand" "d,t")
4303 (match_operand 2 "pc_or_label_operand" "")
4304 (match_operand 3 "pc_or_label_operand" "")))]
4307 if (operands[2] != pc_rtx)
4309 if (which_alternative == 0)
4310 return "b%C0z\t%1,%2";
4312 return "bt%C0z\t%2";
4316 if (which_alternative == 0)
4317 return "b%N0z\t%1,%3";
4319 return "bt%N0z\t%3";
4322 [(set_attr "type" "branch")
4323 (set_attr "mode" "none")
4324 (set_attr "length" "8")])
4326 (define_expand "b<code>"
4328 (if_then_else (any_cond:CC (cc0)
4330 (label_ref (match_operand 0 ""))
4334 gen_conditional_branch (operands, <CODE>);
4339 ;; ....................
4341 ;; SETTING A REGISTER FROM A COMPARISON
4343 ;; ....................
4345 (define_expand "seq"
4346 [(set (match_operand:SI 0 "register_operand")
4347 (eq:SI (match_dup 1)
4350 { if (mips_emit_scc (EQ, operands[0])) DONE; else FAIL; })
4352 (define_insn "*seq_<mode>"
4353 [(set (match_operand:GPR 0 "register_operand" "=d")
4354 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4358 [(set_attr "type" "slt")
4359 (set_attr "mode" "<MODE>")])
4361 (define_insn "*seq_<mode>_mips16"
4362 [(set (match_operand:GPR 0 "register_operand" "=t")
4363 (eq:GPR (match_operand:GPR 1 "register_operand" "d")
4367 [(set_attr "type" "slt")
4368 (set_attr "mode" "<MODE>")])
4370 ;; "sne" uses sltu instructions in which the first operand is $0.
4371 ;; This isn't possible in mips16 code.
4373 (define_expand "sne"
4374 [(set (match_operand:SI 0 "register_operand")
4375 (ne:SI (match_dup 1)
4378 { if (mips_emit_scc (NE, operands[0])) DONE; else FAIL; })
4380 (define_insn "*sne_<mode>"
4381 [(set (match_operand:GPR 0 "register_operand" "=d")
4382 (ne:GPR (match_operand:GPR 1 "register_operand" "d")
4386 [(set_attr "type" "slt")
4387 (set_attr "mode" "<MODE>")])
4389 (define_expand "sgt"
4390 [(set (match_operand:SI 0 "register_operand")
4391 (gt:SI (match_dup 1)
4394 { if (mips_emit_scc (GT, operands[0])) DONE; else FAIL; })
4396 (define_insn "*sgt_<mode>"
4397 [(set (match_operand:GPR 0 "register_operand" "=d")
4398 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4399 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4402 [(set_attr "type" "slt")
4403 (set_attr "mode" "<MODE>")])
4405 (define_insn "*sgt_<mode>_mips16"
4406 [(set (match_operand:GPR 0 "register_operand" "=t")
4407 (gt:GPR (match_operand:GPR 1 "register_operand" "d")
4408 (match_operand:GPR 2 "register_operand" "d")))]
4411 [(set_attr "type" "slt")
4412 (set_attr "mode" "<MODE>")])
4414 (define_expand "sge"
4415 [(set (match_operand:SI 0 "register_operand")
4416 (ge:SI (match_dup 1)
4419 { if (mips_emit_scc (GE, operands[0])) DONE; else FAIL; })
4421 (define_insn "*sge_<mode>"
4422 [(set (match_operand:GPR 0 "register_operand" "=d")
4423 (ge:GPR (match_operand:GPR 1 "register_operand" "d")
4427 [(set_attr "type" "slt")
4428 (set_attr "mode" "<MODE>")])
4430 (define_expand "slt"
4431 [(set (match_operand:SI 0 "register_operand")
4432 (lt:SI (match_dup 1)
4435 { if (mips_emit_scc (LT, operands[0])) DONE; else FAIL; })
4437 (define_insn "*slt_<mode>"
4438 [(set (match_operand:GPR 0 "register_operand" "=d")
4439 (lt:GPR (match_operand:GPR 1 "register_operand" "d")
4440 (match_operand:GPR 2 "arith_operand" "dI")))]
4443 [(set_attr "type" "slt")
4444 (set_attr "mode" "<MODE>")])
4446 (define_insn "*slt_<mode>_mips16"
4447 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4448 (lt:GPR (match_operand:GPR 1 "register_operand" "d,d")
4449 (match_operand:GPR 2 "arith_operand" "d,I")))]
4452 [(set_attr "type" "slt")
4453 (set_attr "mode" "<MODE>")
4454 (set_attr_alternative "length"
4456 (if_then_else (match_operand 2 "m16_uimm8_1")
4460 (define_expand "sle"
4461 [(set (match_operand:SI 0 "register_operand")
4462 (le:SI (match_dup 1)
4465 { if (mips_emit_scc (LE, operands[0])) DONE; else FAIL; })
4467 (define_insn "*sle_<mode>"
4468 [(set (match_operand:GPR 0 "register_operand" "=d")
4469 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4470 (match_operand:GPR 2 "sle_operand" "")))]
4473 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4474 return "slt\t%0,%1,%2";
4476 [(set_attr "type" "slt")
4477 (set_attr "mode" "<MODE>")])
4479 (define_insn "*sle_<mode>_mips16"
4480 [(set (match_operand:GPR 0 "register_operand" "=t")
4481 (le:GPR (match_operand:GPR 1 "register_operand" "d")
4482 (match_operand:GPR 2 "sle_operand" "")))]
4485 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4486 return "slt\t%1,%2";
4488 [(set_attr "type" "slt")
4489 (set_attr "mode" "<MODE>")
4490 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4494 (define_expand "sgtu"
4495 [(set (match_operand:SI 0 "register_operand")
4496 (gtu:SI (match_dup 1)
4499 { if (mips_emit_scc (GTU, operands[0])) DONE; else FAIL; })
4501 (define_insn "*sgtu_<mode>"
4502 [(set (match_operand:GPR 0 "register_operand" "=d")
4503 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4504 (match_operand:GPR 2 "reg_or_0_operand" "dJ")))]
4507 [(set_attr "type" "slt")
4508 (set_attr "mode" "<MODE>")])
4510 (define_insn "*sgtu_<mode>_mips16"
4511 [(set (match_operand:GPR 0 "register_operand" "=t")
4512 (gtu:GPR (match_operand:GPR 1 "register_operand" "d")
4513 (match_operand:GPR 2 "register_operand" "d")))]
4516 [(set_attr "type" "slt")
4517 (set_attr "mode" "<MODE>")])
4519 (define_expand "sgeu"
4520 [(set (match_operand:SI 0 "register_operand")
4521 (geu:SI (match_dup 1)
4524 { if (mips_emit_scc (GEU, operands[0])) DONE; else FAIL; })
4526 (define_insn "*sge_<mode>"
4527 [(set (match_operand:GPR 0 "register_operand" "=d")
4528 (geu:GPR (match_operand:GPR 1 "register_operand" "d")
4532 [(set_attr "type" "slt")
4533 (set_attr "mode" "<MODE>")])
4535 (define_expand "sltu"
4536 [(set (match_operand:SI 0 "register_operand")
4537 (ltu:SI (match_dup 1)
4540 { if (mips_emit_scc (LTU, operands[0])) DONE; else FAIL; })
4542 (define_insn "*sltu_<mode>"
4543 [(set (match_operand:GPR 0 "register_operand" "=d")
4544 (ltu:GPR (match_operand:GPR 1 "register_operand" "d")
4545 (match_operand:GPR 2 "arith_operand" "dI")))]
4548 [(set_attr "type" "slt")
4549 (set_attr "mode" "<MODE>")])
4551 (define_insn "*sltu_<mode>_mips16"
4552 [(set (match_operand:GPR 0 "register_operand" "=t,t")
4553 (ltu:GPR (match_operand:GPR 1 "register_operand" "d,d")
4554 (match_operand:GPR 2 "arith_operand" "d,I")))]
4557 [(set_attr "type" "slt")
4558 (set_attr "mode" "<MODE>")
4559 (set_attr_alternative "length"
4561 (if_then_else (match_operand 2 "m16_uimm8_1")
4565 (define_expand "sleu"
4566 [(set (match_operand:SI 0 "register_operand")
4567 (leu:SI (match_dup 1)
4570 { if (mips_emit_scc (LEU, operands[0])) DONE; else FAIL; })
4572 (define_insn "*sleu_<mode>"
4573 [(set (match_operand:GPR 0 "register_operand" "=d")
4574 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4575 (match_operand:GPR 2 "sleu_operand" "")))]
4578 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4579 return "sltu\t%0,%1,%2";
4581 [(set_attr "type" "slt")
4582 (set_attr "mode" "<MODE>")])
4584 (define_insn "*sleu_<mode>_mips16"
4585 [(set (match_operand:GPR 0 "register_operand" "=t")
4586 (leu:GPR (match_operand:GPR 1 "register_operand" "d")
4587 (match_operand:GPR 2 "sleu_operand" "")))]
4590 operands[2] = GEN_INT (INTVAL (operands[2]) + 1);
4591 return "sltu\t%1,%2";
4593 [(set_attr "type" "slt")
4594 (set_attr "mode" "<MODE>")
4595 (set (attr "length") (if_then_else (match_operand 2 "m16_uimm8_m1_1")
4600 ;; ....................
4602 ;; FLOATING POINT COMPARISONS
4604 ;; ....................
4606 (define_insn "s<code>_<mode>"
4607 [(set (match_operand:CC 0 "register_operand" "=z")
4608 (fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4609 (match_operand:SCALARF 2 "register_operand" "f")))]
4611 "c.<fcond>.<fmt>\t%Z0%1,%2"
4612 [(set_attr "type" "fcmp")
4613 (set_attr "mode" "FPSW")])
4615 (define_insn "s<code>_<mode>"
4616 [(set (match_operand:CC 0 "register_operand" "=z")
4617 (swapped_fcond:CC (match_operand:SCALARF 1 "register_operand" "f")
4618 (match_operand:SCALARF 2 "register_operand" "f")))]
4620 "c.<swapped_fcond>.<fmt>\t%Z0%2,%1"
4621 [(set_attr "type" "fcmp")
4622 (set_attr "mode" "FPSW")])
4625 ;; ....................
4627 ;; UNCONDITIONAL BRANCHES
4629 ;; ....................
4631 ;; Unconditional branches.
4635 (label_ref (match_operand 0 "" "")))]
4640 if (get_attr_length (insn) <= 8)
4641 return "%*b\t%l0%/";
4644 output_asm_insn (mips_output_load_label (), operands);
4645 return "%*jr\t%@%/%]";
4649 return "%*j\t%l0%/";
4651 [(set_attr "type" "jump")
4652 (set_attr "mode" "none")
4653 (set (attr "length")
4654 ;; We can't use `j' when emitting PIC. Emit a branch if it's
4655 ;; in range, otherwise load the address of the branch target into
4656 ;; $at and then jump to it.
4658 (ior (eq (symbol_ref "flag_pic") (const_int 0))
4659 (lt (abs (minus (match_dup 0)
4660 (plus (pc) (const_int 4))))
4661 (const_int 131072)))
4662 (const_int 4) (const_int 16)))])
4664 ;; We need a different insn for the mips16, because a mips16 branch
4665 ;; does not have a delay slot.
4669 (label_ref (match_operand 0 "" "")))]
4672 [(set_attr "type" "branch")
4673 (set_attr "mode" "none")
4674 (set_attr "length" "8")])
4676 (define_expand "indirect_jump"
4677 [(set (pc) (match_operand 0 "register_operand"))]
4680 operands[0] = force_reg (Pmode, operands[0]);
4681 if (Pmode == SImode)
4682 emit_jump_insn (gen_indirect_jumpsi (operands[0]));
4684 emit_jump_insn (gen_indirect_jumpdi (operands[0]));
4688 (define_insn "indirect_jump<mode>"
4689 [(set (pc) (match_operand:P 0 "register_operand" "d"))]
4692 [(set_attr "type" "jump")
4693 (set_attr "mode" "none")])
4695 (define_expand "tablejump"
4697 (match_operand 0 "register_operand"))
4698 (use (label_ref (match_operand 1 "")))]
4702 operands[0] = expand_binop (Pmode, add_optab,
4703 convert_to_mode (Pmode, operands[0], false),
4704 gen_rtx_LABEL_REF (Pmode, operands[1]),
4706 else if (TARGET_GPWORD)
4707 operands[0] = expand_binop (Pmode, add_optab, operands[0],
4708 pic_offset_table_rtx, 0, 0, OPTAB_WIDEN);
4710 if (Pmode == SImode)
4711 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1]));
4713 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1]));
4717 (define_insn "tablejump<mode>"
4719 (match_operand:P 0 "register_operand" "d"))
4720 (use (label_ref (match_operand 1 "" "")))]
4723 [(set_attr "type" "jump")
4724 (set_attr "mode" "none")])
4726 ;; For TARGET_ABICALLS, we save the gp in the jmp_buf as well.
4727 ;; While it is possible to either pull it off the stack (in the
4728 ;; o32 case) or recalculate it given t9 and our target label,
4729 ;; it takes 3 or 4 insns to do so.
4731 (define_expand "builtin_setjmp_setup"
4732 [(use (match_operand 0 "register_operand"))]
4737 addr = plus_constant (operands[0], GET_MODE_SIZE (Pmode) * 3);
4738 emit_move_insn (gen_rtx_MEM (Pmode, addr), pic_offset_table_rtx);
4742 ;; Restore the gp that we saved above. Despite the earlier comment, it seems
4743 ;; that older code did recalculate the gp from $25. Continue to jump through
4744 ;; $25 for compatibility (we lose nothing by doing so).
4746 (define_expand "builtin_longjmp"
4747 [(use (match_operand 0 "register_operand"))]
4750 /* The elements of the buffer are, in order: */
4751 int W = GET_MODE_SIZE (Pmode);
4752 rtx fp = gen_rtx_MEM (Pmode, operands[0]);
4753 rtx lab = gen_rtx_MEM (Pmode, plus_constant (operands[0], 1*W));
4754 rtx stack = gen_rtx_MEM (Pmode, plus_constant (operands[0], 2*W));
4755 rtx gpv = gen_rtx_MEM (Pmode, plus_constant (operands[0], 3*W));
4756 rtx pv = gen_rtx_REG (Pmode, PIC_FUNCTION_ADDR_REGNUM);
4757 /* Use gen_raw_REG to avoid being given pic_offset_table_rtx.
4758 The target is bound to be using $28 as the global pointer
4759 but the current function might not be. */
4760 rtx gp = gen_raw_REG (Pmode, GLOBAL_POINTER_REGNUM);
4762 /* This bit is similar to expand_builtin_longjmp except that it
4763 restores $gp as well. */
4764 emit_move_insn (hard_frame_pointer_rtx, fp);
4765 emit_move_insn (pv, lab);
4766 emit_stack_restore (SAVE_NONLOCAL, stack, NULL_RTX);
4767 emit_move_insn (gp, gpv);
4768 emit_insn (gen_rtx_USE (VOIDmode, hard_frame_pointer_rtx));
4769 emit_insn (gen_rtx_USE (VOIDmode, stack_pointer_rtx));
4770 emit_insn (gen_rtx_USE (VOIDmode, gp));
4771 emit_indirect_jump (pv);
4776 ;; ....................
4778 ;; Function prologue/epilogue
4780 ;; ....................
4783 (define_expand "prologue"
4787 mips_expand_prologue ();
4791 ;; Block any insns from being moved before this point, since the
4792 ;; profiling call to mcount can use various registers that aren't
4793 ;; saved or used to pass arguments.
4795 (define_insn "blockage"
4796 [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
4799 [(set_attr "type" "unknown")
4800 (set_attr "mode" "none")
4801 (set_attr "length" "0")])
4803 (define_expand "epilogue"
4807 mips_expand_epilogue (false);
4811 (define_expand "sibcall_epilogue"
4815 mips_expand_epilogue (true);
4819 ;; Trivial return. Make it look like a normal return insn as that
4820 ;; allows jump optimizations to work better.
4822 (define_insn "return"
4824 "mips_can_use_return_insn ()"
4826 [(set_attr "type" "jump")
4827 (set_attr "mode" "none")])
4831 (define_insn "return_internal"
4833 (use (match_operand 0 "pmode_register_operand" ""))]
4836 [(set_attr "type" "jump")
4837 (set_attr "mode" "none")])
4839 ;; This is used in compiling the unwind routines.
4840 (define_expand "eh_return"
4841 [(use (match_operand 0 "general_operand"))]
4844 enum machine_mode gpr_mode = TARGET_64BIT ? DImode : SImode;
4846 if (GET_MODE (operands[0]) != gpr_mode)
4847 operands[0] = convert_to_mode (gpr_mode, operands[0], 0);
4849 emit_insn (gen_eh_set_lr_di (operands[0]));
4851 emit_insn (gen_eh_set_lr_si (operands[0]));
4856 ;; Clobber the return address on the stack. We can't expand this
4857 ;; until we know where it will be put in the stack frame.
4859 (define_insn "eh_set_lr_si"
4860 [(unspec [(match_operand:SI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4861 (clobber (match_scratch:SI 1 "=&d"))]
4865 (define_insn "eh_set_lr_di"
4866 [(unspec [(match_operand:DI 0 "register_operand" "d")] UNSPEC_EH_RETURN)
4867 (clobber (match_scratch:DI 1 "=&d"))]
4872 [(unspec [(match_operand 0 "register_operand")] UNSPEC_EH_RETURN)
4873 (clobber (match_scratch 1))]
4874 "reload_completed && !TARGET_DEBUG_D_MODE"
4877 mips_set_return_address (operands[0], operands[1]);
4881 (define_insn_and_split "exception_receiver"
4883 (unspec_volatile:SI [(const_int 0)] UNSPEC_EH_RECEIVER))]
4884 "TARGET_ABICALLS && TARGET_OLDABI"
4886 "&& reload_completed"
4892 [(set_attr "type" "load")
4893 (set_attr "length" "12")])
4896 ;; ....................
4900 ;; ....................
4902 ;; Instructions to load a call address from the GOT. The address might
4903 ;; point to a function or to a lazy binding stub. In the latter case,
4904 ;; the stub will use the dynamic linker to resolve the function, which
4905 ;; in turn will change the GOT entry to point to the function's real
4908 ;; This means that every call, even pure and constant ones, can
4909 ;; potentially modify the GOT entry. And once a stub has been called,
4910 ;; we must not call it again.
4912 ;; We represent this restriction using an imaginary fixed register that
4913 ;; acts like a GOT version number. By making the register call-clobbered,
4914 ;; we tell the target-independent code that the address could be changed
4915 ;; by any call insn.
4916 (define_insn "load_call<mode>"
4917 [(set (match_operand:P 0 "register_operand" "=c")
4918 (unspec:P [(match_operand:P 1 "register_operand" "r")
4919 (match_operand:P 2 "immediate_operand" "")
4920 (reg:P FAKE_CALL_REGNO)]
4923 "<load>\t%0,%R2(%1)"
4924 [(set_attr "type" "load")
4925 (set_attr "mode" "<MODE>")
4926 (set_attr "length" "4")])
4928 ;; Sibling calls. All these patterns use jump instructions.
4930 ;; If TARGET_SIBCALLS, call_insn_operand will only accept constant
4931 ;; addresses if a direct jump is acceptable. Since the 'S' constraint
4932 ;; is defined in terms of call_insn_operand, the same is true of the
4935 ;; When we use an indirect jump, we need a register that will be
4936 ;; preserved by the epilogue. Since TARGET_ABICALLS forces us to
4937 ;; use $25 for this purpose -- and $25 is never clobbered by the
4938 ;; epilogue -- we might as well use it for !TARGET_ABICALLS as well.
4940 (define_expand "sibcall"
4941 [(parallel [(call (match_operand 0 "")
4942 (match_operand 1 ""))
4943 (use (match_operand 2 "")) ;; next_arg_reg
4944 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
4947 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], true);
4951 (define_insn "sibcall_internal"
4952 [(call (mem:SI (match_operand 0 "call_insn_operand" "j,S"))
4953 (match_operand 1 "" ""))]
4954 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4958 [(set_attr "type" "call")])
4960 (define_expand "sibcall_value"
4961 [(parallel [(set (match_operand 0 "")
4962 (call (match_operand 1 "")
4963 (match_operand 2 "")))
4964 (use (match_operand 3 ""))])] ;; next_arg_reg
4967 mips_expand_call (operands[0], XEXP (operands[1], 0),
4968 operands[2], operands[3], true);
4972 (define_insn "sibcall_value_internal"
4973 [(set (match_operand 0 "register_operand" "=df,df")
4974 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
4975 (match_operand 2 "" "")))]
4976 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4980 [(set_attr "type" "call")])
4982 (define_insn "sibcall_value_multiple_internal"
4983 [(set (match_operand 0 "register_operand" "=df,df")
4984 (call (mem:SI (match_operand 1 "call_insn_operand" "j,S"))
4985 (match_operand 2 "" "")))
4986 (set (match_operand 3 "register_operand" "=df,df")
4987 (call (mem:SI (match_dup 1))
4989 "TARGET_SIBCALLS && SIBLING_CALL_P (insn)"
4993 [(set_attr "type" "call")])
4995 (define_expand "call"
4996 [(parallel [(call (match_operand 0 "")
4997 (match_operand 1 ""))
4998 (use (match_operand 2 "")) ;; next_arg_reg
4999 (use (match_operand 3 ""))])] ;; struct_value_size_rtx
5002 mips_expand_call (0, XEXP (operands[0], 0), operands[1], operands[2], false);
5006 ;; This instruction directly corresponds to an assembly-language "jal".
5007 ;; There are four cases:
5010 ;; Both symbolic and register destinations are OK. The pattern
5011 ;; always expands to a single mips instruction.
5013 ;; - -mabicalls/-mno-explicit-relocs:
5014 ;; Again, both symbolic and register destinations are OK.
5015 ;; The call is treated as a multi-instruction black box.
5017 ;; - -mabicalls/-mexplicit-relocs with n32 or n64:
5018 ;; Only "jal $25" is allowed. This expands to a single "jalr $25"
5021 ;; - -mabicalls/-mexplicit-relocs with o32 or o64:
5022 ;; Only "jal $25" is allowed. The call is actually two instructions:
5023 ;; "jalr $25" followed by an insn to reload $gp.
5025 ;; In the last case, we can generate the individual instructions with
5026 ;; a define_split. There are several things to be wary of:
5028 ;; - We can't expose the load of $gp before reload. If we did,
5029 ;; it might get removed as dead, but reload can introduce new
5030 ;; uses of $gp by rematerializing constants.
5032 ;; - We shouldn't restore $gp after calls that never return.
5033 ;; It isn't valid to insert instructions between a noreturn
5034 ;; call and the following barrier.
5036 ;; - The splitter deliberately changes the liveness of $gp. The unsplit
5037 ;; instruction preserves $gp and so have no effect on its liveness.
5038 ;; But once we generate the separate insns, it becomes obvious that
5039 ;; $gp is not live on entry to the call.
5041 ;; ??? The operands[2] = insn check is a hack to make the original insn
5042 ;; available to the splitter.
5043 (define_insn_and_split "call_internal"
5044 [(call (mem:SI (match_operand 0 "call_insn_operand" "c,S"))
5045 (match_operand 1 "" ""))
5046 (clobber (reg:SI 31))]
5048 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%0%/"; }
5049 "reload_completed && TARGET_SPLIT_CALLS && (operands[2] = insn)"
5052 emit_call_insn (gen_call_split (operands[0], operands[1]));
5053 if (!find_reg_note (operands[2], REG_NORETURN, 0))
5057 [(set_attr "jal" "indirect,direct")
5058 (set_attr "extended_mips16" "no,yes")])
5060 (define_insn "call_split"
5061 [(call (mem:SI (match_operand 0 "call_insn_operand" "c"))
5062 (match_operand 1 "" ""))
5063 (clobber (reg:SI 31))
5064 (clobber (reg:SI 28))]
5065 "TARGET_SPLIT_CALLS"
5067 [(set_attr "type" "call")])
5069 (define_expand "call_value"
5070 [(parallel [(set (match_operand 0 "")
5071 (call (match_operand 1 "")
5072 (match_operand 2 "")))
5073 (use (match_operand 3 ""))])] ;; next_arg_reg
5076 mips_expand_call (operands[0], XEXP (operands[1], 0),
5077 operands[2], operands[3], false);
5081 ;; See comment for call_internal.
5082 (define_insn_and_split "call_value_internal"
5083 [(set (match_operand 0 "register_operand" "=df,df")
5084 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5085 (match_operand 2 "" "")))
5086 (clobber (reg:SI 31))]
5088 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5089 "reload_completed && TARGET_SPLIT_CALLS && (operands[3] = insn)"
5092 emit_call_insn (gen_call_value_split (operands[0], operands[1],
5094 if (!find_reg_note (operands[3], REG_NORETURN, 0))
5098 [(set_attr "jal" "indirect,direct")
5099 (set_attr "extended_mips16" "no,yes")])
5101 (define_insn "call_value_split"
5102 [(set (match_operand 0 "register_operand" "=df")
5103 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5104 (match_operand 2 "" "")))
5105 (clobber (reg:SI 31))
5106 (clobber (reg:SI 28))]
5107 "TARGET_SPLIT_CALLS"
5109 [(set_attr "type" "call")])
5111 ;; See comment for call_internal.
5112 (define_insn_and_split "call_value_multiple_internal"
5113 [(set (match_operand 0 "register_operand" "=df,df")
5114 (call (mem:SI (match_operand 1 "call_insn_operand" "c,S"))
5115 (match_operand 2 "" "")))
5116 (set (match_operand 3 "register_operand" "=df,df")
5117 (call (mem:SI (match_dup 1))
5119 (clobber (reg:SI 31))]
5121 { return TARGET_SPLIT_CALLS ? "#" : "%*jal\t%1%/"; }
5122 "reload_completed && TARGET_SPLIT_CALLS && (operands[4] = insn)"
5125 emit_call_insn (gen_call_value_multiple_split (operands[0], operands[1],
5126 operands[2], operands[3]));
5127 if (!find_reg_note (operands[4], REG_NORETURN, 0))
5131 [(set_attr "jal" "indirect,direct")
5132 (set_attr "extended_mips16" "no,yes")])
5134 (define_insn "call_value_multiple_split"
5135 [(set (match_operand 0 "register_operand" "=df")
5136 (call (mem:SI (match_operand 1 "call_insn_operand" "c"))
5137 (match_operand 2 "" "")))
5138 (set (match_operand 3 "register_operand" "=df")
5139 (call (mem:SI (match_dup 1))
5141 (clobber (reg:SI 31))
5142 (clobber (reg:SI 28))]
5143 "TARGET_SPLIT_CALLS"
5145 [(set_attr "type" "call")])
5147 ;; Call subroutine returning any type.
5149 (define_expand "untyped_call"
5150 [(parallel [(call (match_operand 0 "")
5152 (match_operand 1 "")
5153 (match_operand 2 "")])]
5158 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx));
5160 for (i = 0; i < XVECLEN (operands[2], 0); i++)
5162 rtx set = XVECEXP (operands[2], 0, i);
5163 emit_move_insn (SET_DEST (set), SET_SRC (set));
5166 emit_insn (gen_blockage ());
5171 ;; ....................
5175 ;; ....................
5179 (define_insn "prefetch"
5180 [(prefetch (match_operand:QI 0 "address_operand" "p")
5181 (match_operand 1 "const_int_operand" "n")
5182 (match_operand 2 "const_int_operand" "n"))]
5183 "ISA_HAS_PREFETCH && TARGET_EXPLICIT_RELOCS"
5185 operands[1] = mips_prefetch_cookie (operands[1], operands[2]);
5186 return "pref\t%1,%a0";
5188 [(set_attr "type" "prefetch")])
5190 (define_insn "*prefetch_indexed_<mode>"
5191 [(prefetch (plus:P (match_operand:P 0 "register_operand" "d")
5192 (match_operand:P 1 "register_operand" "d"))
5193 (match_operand 2 "const_int_operand" "n")
5194 (match_operand 3 "const_int_operand" "n"))]
5195 "ISA_HAS_PREFETCHX && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT"
5197 operands[2] = mips_prefetch_cookie (operands[2], operands[3]);
5198 return "prefx\t%2,%1(%0)";
5200 [(set_attr "type" "prefetchx")])
5206 [(set_attr "type" "nop")
5207 (set_attr "mode" "none")])
5209 ;; Like nop, but commented out when outside a .set noreorder block.
5210 (define_insn "hazard_nop"
5219 [(set_attr "type" "nop")])
5221 ;; MIPS4 Conditional move instructions.
5223 (define_insn "*mov<GPR:mode>_on_<MOVECC:mode>"
5224 [(set (match_operand:GPR 0 "register_operand" "=d,d")
5226 (match_operator:MOVECC 4 "equality_operator"
5227 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5229 (match_operand:GPR 2 "reg_or_0_operand" "dJ,0")
5230 (match_operand:GPR 3 "reg_or_0_operand" "0,dJ")))]
5235 [(set_attr "type" "condmove")
5236 (set_attr "mode" "<GPR:MODE>")])
5238 (define_insn "*mov<SCALARF:mode>_on_<MOVECC:mode>"
5239 [(set (match_operand:SCALARF 0 "register_operand" "=f,f")
5240 (if_then_else:SCALARF
5241 (match_operator:MOVECC 4 "equality_operator"
5242 [(match_operand:MOVECC 1 "register_operand" "<MOVECC:reg>,<MOVECC:reg>")
5244 (match_operand:SCALARF 2 "register_operand" "f,0")
5245 (match_operand:SCALARF 3 "register_operand" "0,f")))]
5248 mov%T4.<fmt>\t%0,%2,%1
5249 mov%t4.<fmt>\t%0,%3,%1"
5250 [(set_attr "type" "condmove")
5251 (set_attr "mode" "<SCALARF:MODE>")])
5253 ;; These are the main define_expand's used to make conditional moves.
5255 (define_expand "mov<mode>cc"
5256 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5257 (set (match_operand:GPR 0 "register_operand")
5258 (if_then_else:GPR (match_dup 5)
5259 (match_operand:GPR 2 "reg_or_0_operand")
5260 (match_operand:GPR 3 "reg_or_0_operand")))]
5263 gen_conditional_move (operands);
5267 (define_expand "mov<mode>cc"
5268 [(set (match_dup 4) (match_operand 1 "comparison_operator"))
5269 (set (match_operand:SCALARF 0 "register_operand")
5270 (if_then_else:SCALARF (match_dup 5)
5271 (match_operand:SCALARF 2 "register_operand")
5272 (match_operand:SCALARF 3 "register_operand")))]
5275 gen_conditional_move (operands);
5280 ;; ....................
5282 ;; mips16 inline constant tables
5284 ;; ....................
5287 (define_insn "consttable_int"
5288 [(unspec_volatile [(match_operand 0 "consttable_operand" "")
5289 (match_operand 1 "const_int_operand" "")]
5290 UNSPEC_CONSTTABLE_INT)]
5293 assemble_integer (operands[0], INTVAL (operands[1]),
5294 BITS_PER_UNIT * INTVAL (operands[1]), 1);
5297 [(set (attr "length") (symbol_ref "INTVAL (operands[1])"))])
5299 (define_insn "consttable_float"
5300 [(unspec_volatile [(match_operand 0 "consttable_operand" "")]
5301 UNSPEC_CONSTTABLE_FLOAT)]
5306 gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
5307 REAL_VALUE_FROM_CONST_DOUBLE (d, operands[0]);
5308 assemble_real (d, GET_MODE (operands[0]),
5309 GET_MODE_BITSIZE (GET_MODE (operands[0])));
5312 [(set (attr "length")
5313 (symbol_ref "GET_MODE_SIZE (GET_MODE (operands[0]))"))])
5315 (define_insn "align"
5316 [(unspec_volatile [(match_operand 0 "const_int_operand" "")] UNSPEC_ALIGN)]
5319 [(set (attr "length") (symbol_ref "(1 << INTVAL (operands[0])) - 1"))])
5322 [(match_operand 0 "small_data_pattern")]
5325 { operands[0] = mips_rewrite_small_data (operands[0]); })
5327 ; Thread-Local Storage
5329 ; The TLS base pointer is acessed via "rdhwr $v1, $29". No current
5330 ; MIPS architecture defines this register, and no current
5331 ; implementation provides it; instead, any OS which supports TLS is
5332 ; expected to trap and emulate this instruction. rdhwr is part of the
5333 ; MIPS 32r2 specification, but we use it on any architecture because
5334 ; we expect it to be emulated. Use .set to force the assembler to
5337 (define_insn "tls_get_tp_<mode>"
5338 [(set (match_operand:P 0 "register_operand" "=v")
5339 (unspec:P [(const_int 0)]
5340 UNSPEC_TLS_GET_TP))]
5341 "HAVE_AS_TLS && !TARGET_MIPS16"
5342 ".set\tpush\;.set\tmips32r2\t\;rdhwr\t%0,$29\;.set\tpop"
5343 [(set_attr "type" "unknown")
5344 (set_attr "mode" "<MODE>")])
5346 ; The MIPS Paired-Single Floating Point and MIPS-3D Instructions.
5348 (include "mips-ps-3d.md")