1 /* Definitions of target machine for GNU compiler. MIPS version.
2 Copyright (C) 1989, 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998
3 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
4 Contributed by A. Lichnewsky (lich@inria.inria.fr).
5 Changed by Michael Meissner (meissner@osf.org).
6 64 bit r4000 support by Ian Lance Taylor (ian@cygnus.com) and
7 Brendan Eich (brendan@microunity.com).
9 This file is part of GNU CC.
11 GNU CC is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2, or (at your option)
16 GNU CC is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
21 You should have received a copy of the GNU General Public License
22 along with GNU CC; see the file COPYING. If not, write to
23 the Free Software Foundation, 59 Temple Place - Suite 330,
24 Boston, MA 02111-1307, USA. */
27 /* Standard GCC variables that we reference. */
29 extern char *asm_file_name;
30 extern char call_used_regs[];
31 extern int may_call_alloca;
32 extern char **save_argv;
33 extern int target_flags;
35 /* MIPS external variables defined in mips.c. */
39 CMP_SI, /* compare four byte integers */
40 CMP_DI, /* compare eight byte integers */
41 CMP_SF, /* compare single precision floats */
42 CMP_DF, /* compare double precision floats */
43 CMP_MAX /* max comparison type */
46 /* types of delay slot */
48 DELAY_NONE, /* no delay slot */
49 DELAY_LOAD, /* load from memory delay */
50 DELAY_HILO, /* move from/to hi/lo registers */
51 DELAY_FCMP /* delay after doing c.<xx>.{d,s} */
54 /* Which processor to schedule for. Since there is no difference between
55 a R2000 and R3000 in terms of the scheduler, we collapse them into
56 just an R3000. The elements of the enumeration must match exactly
57 the cpu attribute in the mips.md machine description. */
83 /* Recast the cpu class to be the cpu attribute. */
84 #define mips_cpu_attr ((enum attr_cpu)mips_tune)
86 /* Which ABI to use. ABI_32 (original 32, or o32), ABI_N32 (n32),
87 ABI_64 (n64) are all defined by SGI. ABI_O64 is o32 extended
88 to work on a 64 bit machine. */
95 /* MEABI is gcc's internal name for MIPS' new EABI (defined by MIPS)
96 which is not the same as the above EABI (defined by Cygnus,
97 Greenhills, and Toshiba?). MEABI is not yet complete or published,
98 but at this point it looks like N32 as far as calling conventions go,
99 but allows for either 32 or 64 bit registers.
101 Currently MIPS is calling their EABI "the" MIPS EABI, and Cygnus'
102 EABI the legacy EABI. In the end we may end up calling both ABI's
103 EABI but give them different version numbers, but for now I'm going
104 with different names. */
107 /* Whether to emit abicalls code sequences or not. */
109 enum mips_abicalls_type {
114 /* Recast the abicalls class to be the abicalls attribute. */
115 #define mips_abicalls_attr ((enum attr_abicalls)mips_abicalls)
117 /* Which type of block move to do (whether or not the last store is
118 split out so it can fill a branch delay slot). */
120 enum block_move_type {
121 BLOCK_MOVE_NORMAL, /* generate complete block move */
122 BLOCK_MOVE_NOT_LAST, /* generate all but last store */
123 BLOCK_MOVE_LAST /* generate just the last store */
126 /* Information about one recognized processor. Defined here for the
127 benefit of TARGET_CPU_CPP_BUILTINS. */
128 struct mips_cpu_info {
129 /* The 'canonical' name of the processor as far as GCC is concerned.
130 It's typically a manufacturer's prefix followed by a numerical
131 designation. It should be lower case. */
134 /* The internal processor number that most closely matches this
135 entry. Several processors can have the same value, if there's no
136 difference between them from GCC's point of view. */
137 enum processor_type cpu;
139 /* The ISA level that the processor implements. */
143 extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
144 extern char mips_print_operand_punct[256]; /* print_operand punctuation chars */
145 extern const char *current_function_file; /* filename current function is in */
146 extern int num_source_filenames; /* current .file # */
147 extern int inside_function; /* != 0 if inside of a function */
148 extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
149 extern int file_in_function_warning; /* warning given about .file in func */
150 extern int sdb_label_count; /* block start/end next label # */
151 extern int sdb_begin_function_line; /* Starting Line of current function */
152 extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
153 extern int g_switch_value; /* value of the -G xx switch */
154 extern int g_switch_set; /* whether -G xx was passed. */
155 extern int sym_lineno; /* sgi next label # for each stmt */
156 extern int set_noreorder; /* # of nested .set noreorder's */
157 extern int set_nomacro; /* # of nested .set nomacro's */
158 extern int set_noat; /* # of nested .set noat's */
159 extern int set_volatile; /* # of nested .set volatile's */
160 extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
161 extern int mips_dbx_regno[]; /* Map register # to debug register # */
162 extern GTY(()) rtx branch_cmp[2]; /* operands for compare */
163 extern enum cmp_type branch_type; /* what type of branch to use */
164 extern enum processor_type mips_arch; /* which cpu to codegen for */
165 extern enum processor_type mips_tune; /* which cpu to schedule for */
166 extern enum mips_abicalls_type mips_abicalls;/* for svr4 abi pic calls */
167 extern int mips_isa; /* architectural level */
168 extern int mips16; /* whether generating mips16 code */
169 extern int mips16_hard_float; /* mips16 without -msoft-float */
170 extern int mips_entry; /* generate entry/exit for mips16 */
171 extern const char *mips_arch_string; /* for -march=<xxx> */
172 extern const char *mips_tune_string; /* for -mtune=<xxx> */
173 extern const char *mips_isa_string; /* for -mips{1,2,3,4} */
174 extern const char *mips_abi_string; /* for -mabi={32,n32,64} */
175 extern const char *mips_entry_string; /* for -mentry */
176 extern const char *mips_no_mips16_string;/* for -mno-mips16 */
177 extern const char *mips_cache_flush_func;/* for -mflush-func= and -mno-flush-func */
178 extern int mips_split_addresses; /* perform high/lo_sum support */
179 extern int dslots_load_total; /* total # load related delay slots */
180 extern int dslots_load_filled; /* # filled load delay slots */
181 extern int dslots_jump_total; /* total # jump related delay slots */
182 extern int dslots_jump_filled; /* # filled jump delay slots */
183 extern int dslots_number_nops; /* # of nops needed by previous insn */
184 extern int num_refs[3]; /* # 1/2/3 word references */
185 extern GTY(()) rtx mips_load_reg; /* register to check for load delay */
186 extern GTY(()) rtx mips_load_reg2; /* 2nd reg to check for load delay */
187 extern GTY(()) rtx mips_load_reg3; /* 3rd reg to check for load delay */
188 extern GTY(()) rtx mips_load_reg4; /* 4th reg to check for load delay */
189 extern int mips_string_length; /* length of strings for mips16 */
190 extern const struct mips_cpu_info mips_cpu_info_table[];
191 extern const struct mips_cpu_info *mips_arch_info;
192 extern const struct mips_cpu_info *mips_tune_info;
194 /* Functions to change what output section we are using. */
195 extern void sdata_section PARAMS ((void));
196 extern void sbss_section PARAMS ((void));
198 /* Macros to silence warnings about numbers being signed in traditional
199 C and unsigned in ISO C when compiled on 32-bit hosts. */
201 #define BITMASK_HIGH (((unsigned long)1) << 31) /* 0x80000000 */
202 #define BITMASK_UPPER16 ((unsigned long)0xffff << 16) /* 0xffff0000 */
203 #define BITMASK_LOWER16 ((unsigned long)0xffff) /* 0x0000ffff */
206 /* Run-time compilation parameters selecting different hardware subsets. */
208 /* Macros used in the machine description to test the flags. */
210 /* Bits for real switches */
211 #define MASK_INT64 0x00000001 /* ints are 64 bits */
212 #define MASK_LONG64 0x00000002 /* longs are 64 bits */
213 #define MASK_SPLIT_ADDR 0x00000004 /* Address splitting is enabled. */
214 #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
215 #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
216 #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
217 #define MASK_STATS 0x00000040 /* print statistics to stderr */
218 #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
219 #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
220 #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
221 #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
222 #define MASK_UNUSED1 0x00000800 /* Unused Mask. */
223 #define MASK_LONG_CALLS 0x00001000 /* Always call through a register */
224 #define MASK_64BIT 0x00002000 /* Use 64 bit GP registers and insns */
225 #define MASK_EMBEDDED_PIC 0x00004000 /* Generate embedded PIC code */
226 #define MASK_EMBEDDED_DATA 0x00008000 /* Reduce RAM usage, not fast code */
227 #define MASK_BIG_ENDIAN 0x00010000 /* Generate big endian code */
228 #define MASK_SINGLE_FLOAT 0x00020000 /* Only single precision FPU. */
229 #define MASK_MAD 0x00040000 /* Generate mad/madu as on 4650. */
230 #define MASK_4300_MUL_FIX 0x00080000 /* Work-around early Vr4300 CPU bug */
231 #define MASK_MIPS16 0x00100000 /* Generate mips16 code */
232 #define MASK_NO_CHECK_ZERO_DIV \
233 0x00200000 /* divide by zero checking */
234 #define MASK_CHECK_RANGE_DIV \
235 0x00400000 /* divide result range checking */
236 #define MASK_UNINIT_CONST_IN_RODATA \
237 0x00800000 /* Store uninitialized
239 #define MASK_NO_FUSED_MADD 0x01000000 /* Don't generate floating point
240 multiply-add operations. */
241 #define MASK_BRANCHLIKELY 0x02000000 /* Generate Branch Likely
244 /* Debug switches, not documented */
245 #define MASK_DEBUG 0 /* unused */
246 #define MASK_DEBUG_A 0 /* don't allow <label>($reg) addrs */
247 #define MASK_DEBUG_B 0 /* GO_IF_LEGITIMATE_ADDRESS debug */
248 #define MASK_DEBUG_C 0 /* don't expand seq, etc. */
249 #define MASK_DEBUG_D 0 /* don't do define_split's */
250 #define MASK_DEBUG_E 0 /* function_arg debug */
251 #define MASK_DEBUG_F 0 /* ??? */
252 #define MASK_DEBUG_G 0 /* don't support 64 bit arithmetic */
253 #define MASK_DEBUG_I 0 /* unused */
255 /* Dummy switches used only in specs */
256 #define MASK_MIPS_TFILE 0 /* flag for mips-tfile usage */
258 /* r4000 64 bit sizes */
259 #define TARGET_INT64 (target_flags & MASK_INT64)
260 #define TARGET_LONG64 (target_flags & MASK_LONG64)
261 #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
262 #define TARGET_64BIT (target_flags & MASK_64BIT)
264 /* Mips vs. GNU linker */
265 #define TARGET_SPLIT_ADDRESSES (target_flags & MASK_SPLIT_ADDR)
267 /* Mips vs. GNU assembler */
268 #define TARGET_GAS (target_flags & MASK_GAS)
269 #define TARGET_MIPS_AS (!TARGET_GAS)
272 #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
273 #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
274 #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
275 #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
276 #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
277 #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
278 #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
279 #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
280 #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
282 /* Reg. Naming in .s ($21 vs. $a0) */
283 #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
285 /* Optimize for Sdata/Sbss */
286 #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
288 /* print program statistics */
289 #define TARGET_STATS (target_flags & MASK_STATS)
291 /* call memcpy instead of inline code */
292 #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
294 /* .abicalls, etc from Pyramid V.4 */
295 #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
297 /* software floating point */
298 #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
299 #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
301 /* always call through a register */
302 #define TARGET_LONG_CALLS (target_flags & MASK_LONG_CALLS)
304 /* generate embedded PIC code;
306 #define TARGET_EMBEDDED_PIC (target_flags & MASK_EMBEDDED_PIC)
308 /* for embedded systems, optimize for
309 reduced RAM space instead of for
311 #define TARGET_EMBEDDED_DATA (target_flags & MASK_EMBEDDED_DATA)
313 /* always store uninitialized const
314 variables in rodata, requires
315 TARGET_EMBEDDED_DATA. */
316 #define TARGET_UNINIT_CONST_IN_RODATA (target_flags & MASK_UNINIT_CONST_IN_RODATA)
318 /* generate big endian code. */
319 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN)
321 #define TARGET_SINGLE_FLOAT (target_flags & MASK_SINGLE_FLOAT)
322 #define TARGET_DOUBLE_FLOAT (! TARGET_SINGLE_FLOAT)
324 #define TARGET_MAD (target_flags & MASK_MAD)
326 #define TARGET_FUSED_MADD (! (target_flags & MASK_NO_FUSED_MADD))
328 #define TARGET_4300_MUL_FIX (target_flags & MASK_4300_MUL_FIX)
330 #define TARGET_NO_CHECK_ZERO_DIV (target_flags & MASK_NO_CHECK_ZERO_DIV)
331 #define TARGET_CHECK_RANGE_DIV (target_flags & MASK_CHECK_RANGE_DIV)
333 #define TARGET_BRANCHLIKELY (target_flags & MASK_BRANCHLIKELY)
335 /* This is true if we must enable the assembly language file switching
338 #define TARGET_FILE_SWITCHING \
339 (TARGET_GP_OPT && ! TARGET_GAS && ! TARGET_MIPS16)
341 /* We must disable the function end stabs when doing the file switching trick,
342 because the Lscope stabs end up in the wrong place, making it impossible
343 to debug the resulting code. */
344 #define NO_DBX_FUNCTION_END TARGET_FILE_SWITCHING
346 /* Generate mips16 code */
347 #define TARGET_MIPS16 (target_flags & MASK_MIPS16)
349 /* Generic ISA defines. */
350 #define ISA_MIPS1 (mips_isa == 1)
351 #define ISA_MIPS2 (mips_isa == 2)
352 #define ISA_MIPS3 (mips_isa == 3)
353 #define ISA_MIPS4 (mips_isa == 4)
354 #define ISA_MIPS32 (mips_isa == 32)
355 #define ISA_MIPS64 (mips_isa == 64)
357 /* Architecture target defines. */
358 #define TARGET_MIPS3900 (mips_arch == PROCESSOR_R3900)
359 #define TARGET_MIPS4000 (mips_arch == PROCESSOR_R4000)
360 #define TARGET_MIPS4100 (mips_arch == PROCESSOR_R4100
361 #define TARGET_MIPS4121 (mips_arch == PROCESSOR_R4121)
362 #define TARGET_MIPS4300 (mips_arch == PROCESSOR_R4300)
363 #define TARGET_MIPS4320 (mips_arch == PROCESSOR_R4320)
364 #define TARGET_MIPS4KC (mips_arch == PROCESSOR_R4KC)
365 #define TARGET_MIPS5KC (mips_arch == PROCESSOR_R5KC)
366 #define TARGET_MIPS5400 (mips_arch == PROCESSOR_R5400)
367 #define TARGET_MIPS5500 (mips_arch == PROCESSOR_R5500)
368 #define TARGET_SB1 (mips_arch == PROCESSOR_SB1)
369 #define TARGET_SR71K (mips_arch == PROCESSOR_SR71000)
371 /* Scheduling target defines. */
372 #define TUNE_MIPS3000 (mips_tune == PROCESSOR_R3000)
373 #define TUNE_MIPS3900 (mips_tune == PROCESSOR_R3900)
374 #define TUNE_MIPS4000 (mips_tune == PROCESSOR_R4000)
375 #define TUNE_MIPS5000 (mips_tune == PROCESSOR_R5000)
376 #define TUNE_MIPS5400 (mips_tune == PROCESSOR_R5400)
377 #define TUNE_MIPS5500 (mips_tune == PROCESSOR_R5500)
378 #define TUNE_MIPS6000 (mips_tune == PROCESSOR_R6000)
379 #define TUNE_SB1 (mips_tune == PROCESSOR_SB1)
380 #define TUNE_SR71K (mips_tune == PROCESSOR_SR71000)
382 /* Define preprocessor macros for the -march and -mtune options.
383 PREFIX is either _MIPS_ARCH or _MIPS_TUNE, INFO is the selected
384 processor. If INFO's canonical name is "foo", define PREFIX to
385 be "foo", and define an additional macro PREFIX_FOO. */
386 #define MIPS_CPP_SET_PROCESSOR(PREFIX, INFO) \
391 macro = concat ((PREFIX), "_", (INFO)->name, NULL); \
392 for (p = macro; *p != 0; p++) \
395 builtin_define (macro); \
396 builtin_define_with_value ((PREFIX), (INFO)->name, 1); \
401 /* Target CPU builtins. */
402 #define TARGET_CPU_CPP_BUILTINS() \
405 builtin_assert ("cpu=mips"); \
406 builtin_define ("__mips__"); \
407 builtin_define ("_mips"); \
409 /* We do this here because __mips is defined below \
410 and so we can't use builtin_define_std. */ \
412 builtin_define ("mips"); \
414 /* Treat _R3000 and _R4000 like register-size defines, \
415 which is how they've historically been used. */ \
418 builtin_define ("__mips64"); \
419 builtin_define_std ("R4000"); \
420 builtin_define ("_R4000"); \
424 builtin_define_std ("R3000"); \
425 builtin_define ("_R3000"); \
427 if (TARGET_FLOAT64) \
428 builtin_define ("__mips_fpr=64"); \
430 builtin_define ("__mips_fpr=32"); \
433 builtin_define ("__mips16"); \
435 MIPS_CPP_SET_PROCESSOR ("_MIPS_ARCH", mips_arch_info); \
436 MIPS_CPP_SET_PROCESSOR ("_MIPS_TUNE", mips_tune_info); \
440 builtin_define ("__mips=1"); \
441 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS1"); \
443 else if (ISA_MIPS2) \
445 builtin_define ("__mips=2"); \
446 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS2"); \
448 else if (ISA_MIPS3) \
450 builtin_define ("__mips=3"); \
451 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS3"); \
453 else if (ISA_MIPS4) \
455 builtin_define ("__mips=4"); \
456 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \
458 else if (ISA_MIPS32) \
460 builtin_define ("__mips=32"); \
461 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \
463 else if (ISA_MIPS64) \
465 builtin_define ("__mips=64"); \
466 builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \
469 if (TARGET_HARD_FLOAT) \
470 builtin_define ("__mips_hard_float"); \
471 else if (TARGET_SOFT_FLOAT) \
472 builtin_define ("__mips_soft_float"); \
474 if (TARGET_SINGLE_FLOAT) \
475 builtin_define ("__mips_single_float"); \
477 if (TARGET_BIG_ENDIAN) \
479 builtin_define_std ("MIPSEB"); \
480 builtin_define ("_MIPSEB"); \
484 builtin_define_std ("MIPSEL"); \
485 builtin_define ("_MIPSEL"); \
488 /* Macros dependent on the C dialect. */ \
489 if (preprocessing_asm_p ()) \
491 builtin_define_std ("LANGUAGE_ASSEMBLY"); \
492 builtin_define ("_LANGUAGE_ASSEMBLY"); \
494 else if (c_language == clk_c) \
496 builtin_define_std ("LANGUAGE_C"); \
497 builtin_define ("_LANGUAGE_C"); \
499 else if (c_language == clk_cplusplus) \
501 builtin_define ("_LANGUAGE_C_PLUS_PLUS"); \
502 builtin_define ("__LANGUAGE_C_PLUS_PLUS"); \
503 builtin_define ("__LANGUAGE_C_PLUS_PLUS__"); \
507 builtin_define ("_LANGUAGE_OBJECTIVE_C"); \
508 builtin_define ("__LANGUAGE_OBJECTIVE_C"); \
509 /* Bizzare, but needed at least for Irix. */ \
510 builtin_define_std ("LANGUAGE_C"); \
511 builtin_define ("_LANGUAGE_C"); \
514 if (mips_abi == ABI_EABI) \
515 builtin_define ("__mips_eabi"); \
521 /* Macro to define tables used to set the flags.
522 This is a list in braces of pairs in braces,
523 each pair being { "NAME", VALUE }
524 where VALUE is the bits to set or minus the bits to clear.
525 An empty string NAME is used to identify the default VALUE. */
527 #define TARGET_SWITCHES \
530 N_("No default crt0.o") }, \
531 {"int64", MASK_INT64 | MASK_LONG64, \
532 N_("Use 64-bit int type")}, \
533 {"long64", MASK_LONG64, \
534 N_("Use 64-bit long type")}, \
535 {"long32", -(MASK_LONG64 | MASK_INT64), \
536 N_("Use 32-bit long type")}, \
537 {"split-addresses", MASK_SPLIT_ADDR, \
538 N_("Optimize lui/addiu address loads")}, \
539 {"no-split-addresses", -MASK_SPLIT_ADDR, \
540 N_("Don't optimize lui/addiu address loads")}, \
541 {"mips-as", -MASK_GAS, \
542 N_("Use MIPS as")}, \
545 {"rnames", MASK_NAME_REGS, \
546 N_("Use symbolic register names")}, \
547 {"no-rnames", -MASK_NAME_REGS, \
548 N_("Don't use symbolic register names")}, \
549 {"gpOPT", MASK_GPOPT, \
550 N_("Use GP relative sdata/sbss sections")}, \
551 {"gpopt", MASK_GPOPT, \
552 N_("Use GP relative sdata/sbss sections")}, \
553 {"no-gpOPT", -MASK_GPOPT, \
554 N_("Don't use GP relative sdata/sbss sections")}, \
555 {"no-gpopt", -MASK_GPOPT, \
556 N_("Don't use GP relative sdata/sbss sections")}, \
557 {"stats", MASK_STATS, \
558 N_("Output compiler statistics")}, \
559 {"no-stats", -MASK_STATS, \
560 N_("Don't output compiler statistics")}, \
561 {"memcpy", MASK_MEMCPY, \
562 N_("Don't optimize block moves")}, \
563 {"no-memcpy", -MASK_MEMCPY, \
564 N_("Optimize block moves")}, \
565 {"mips-tfile", MASK_MIPS_TFILE, \
566 N_("Use mips-tfile asm postpass")}, \
567 {"no-mips-tfile", -MASK_MIPS_TFILE, \
568 N_("Don't use mips-tfile asm postpass")}, \
569 {"soft-float", MASK_SOFT_FLOAT, \
570 N_("Use software floating point")}, \
571 {"hard-float", -MASK_SOFT_FLOAT, \
572 N_("Use hardware floating point")}, \
573 {"fp64", MASK_FLOAT64, \
574 N_("Use 64-bit FP registers")}, \
575 {"fp32", -MASK_FLOAT64, \
576 N_("Use 32-bit FP registers")}, \
577 {"gp64", MASK_64BIT, \
578 N_("Use 64-bit general registers")}, \
579 {"gp32", -MASK_64BIT, \
580 N_("Use 32-bit general registers")}, \
581 {"abicalls", MASK_ABICALLS, \
582 N_("Use Irix PIC")}, \
583 {"no-abicalls", -MASK_ABICALLS, \
584 N_("Don't use Irix PIC")}, \
585 {"long-calls", MASK_LONG_CALLS, \
586 N_("Use indirect calls")}, \
587 {"no-long-calls", -MASK_LONG_CALLS, \
588 N_("Don't use indirect calls")}, \
589 {"embedded-pic", MASK_EMBEDDED_PIC, \
590 N_("Use embedded PIC")}, \
591 {"no-embedded-pic", -MASK_EMBEDDED_PIC, \
592 N_("Don't use embedded PIC")}, \
593 {"embedded-data", MASK_EMBEDDED_DATA, \
594 N_("Use ROM instead of RAM")}, \
595 {"no-embedded-data", -MASK_EMBEDDED_DATA, \
596 N_("Don't use ROM instead of RAM")}, \
597 {"uninit-const-in-rodata", MASK_UNINIT_CONST_IN_RODATA, \
598 N_("Put uninitialized constants in ROM (needs -membedded-data)")}, \
599 {"no-uninit-const-in-rodata", -MASK_UNINIT_CONST_IN_RODATA, \
600 N_("Don't put uninitialized constants in ROM")}, \
601 {"eb", MASK_BIG_ENDIAN, \
602 N_("Use big-endian byte order")}, \
603 {"el", -MASK_BIG_ENDIAN, \
604 N_("Use little-endian byte order")}, \
605 {"single-float", MASK_SINGLE_FLOAT, \
606 N_("Use single (32-bit) FP only")}, \
607 {"double-float", -MASK_SINGLE_FLOAT, \
608 N_("Don't use single (32-bit) FP only")}, \
610 N_("Use multiply accumulate")}, \
611 {"no-mad", -MASK_MAD, \
612 N_("Don't use multiply accumulate")}, \
613 {"no-fused-madd", MASK_NO_FUSED_MADD, \
614 N_("Don't generate fused multiply/add instructions")}, \
615 {"fused-madd", -MASK_NO_FUSED_MADD, \
616 N_("Generate fused multiply/add instructions")}, \
617 {"fix4300", MASK_4300_MUL_FIX, \
618 N_("Work around early 4300 hardware bug")}, \
619 {"no-fix4300", -MASK_4300_MUL_FIX, \
620 N_("Don't work around early 4300 hardware bug")}, \
621 {"check-zero-division",-MASK_NO_CHECK_ZERO_DIV, \
622 N_("Trap on integer divide by zero")}, \
623 {"no-check-zero-division", MASK_NO_CHECK_ZERO_DIV, \
624 N_("Don't trap on integer divide by zero")}, \
625 {"check-range-division",MASK_CHECK_RANGE_DIV, \
626 N_("Trap on integer divide overflow")}, \
627 {"no-check-range-division",-MASK_CHECK_RANGE_DIV, \
628 N_("Don't trap on integer divide overflow")}, \
629 { "branch-likely", MASK_BRANCHLIKELY, \
630 N_("Use Branch Likely instructions, overriding default for arch")}, \
631 { "no-branch-likely", -MASK_BRANCHLIKELY, \
632 N_("Don't use Branch Likely instructions, overriding default for arch")}, \
633 {"debug", MASK_DEBUG, \
635 {"debuga", MASK_DEBUG_A, \
637 {"debugb", MASK_DEBUG_B, \
639 {"debugc", MASK_DEBUG_C, \
641 {"debugd", MASK_DEBUG_D, \
643 {"debuge", MASK_DEBUG_E, \
645 {"debugf", MASK_DEBUG_F, \
647 {"debugg", MASK_DEBUG_G, \
649 {"debugi", MASK_DEBUG_I, \
651 {"", (TARGET_DEFAULT \
652 | TARGET_CPU_DEFAULT \
653 | TARGET_ENDIAN_DEFAULT), \
657 /* Default target_flags if no switches are specified */
659 #ifndef TARGET_DEFAULT
660 #define TARGET_DEFAULT 0
663 #ifndef TARGET_CPU_DEFAULT
664 #define TARGET_CPU_DEFAULT 0
667 #ifndef TARGET_ENDIAN_DEFAULT
668 #define TARGET_ENDIAN_DEFAULT MASK_BIG_ENDIAN
671 /* 'from-abi' makes a good default: you get whatever the ABI requires. */
672 #ifndef MIPS_ISA_DEFAULT
673 #ifndef MIPS_CPU_STRING_DEFAULT
674 #define MIPS_CPU_STRING_DEFAULT "from-abi"
680 /* Make this compile time constant for libgcc2 */
682 #define TARGET_64BIT 1
684 #define TARGET_64BIT 0
686 #endif /* IN_LIBGCC2 */
688 #ifndef MULTILIB_ENDIAN_DEFAULT
689 #if TARGET_ENDIAN_DEFAULT == 0
690 #define MULTILIB_ENDIAN_DEFAULT "EL"
692 #define MULTILIB_ENDIAN_DEFAULT "EB"
696 #ifndef MULTILIB_ISA_DEFAULT
697 # if MIPS_ISA_DEFAULT == 1
698 # define MULTILIB_ISA_DEFAULT "mips1"
700 # if MIPS_ISA_DEFAULT == 2
701 # define MULTILIB_ISA_DEFAULT "mips2"
703 # if MIPS_ISA_DEFAULT == 3
704 # define MULTILIB_ISA_DEFAULT "mips3"
706 # if MIPS_ISA_DEFAULT == 4
707 # define MULTILIB_ISA_DEFAULT "mips4"
709 # if MIPS_ISA_DEFAULT == 32
710 # define MULTILIB_ISA_DEFAULT "mips32"
712 # if MIPS_ISA_DEFAULT == 64
713 # define MULTILIB_ISA_DEFAULT "mips64"
715 # define MULTILIB_ISA_DEFAULT "mips1"
724 #ifndef MULTILIB_DEFAULTS
725 #define MULTILIB_DEFAULTS \
726 { MULTILIB_ENDIAN_DEFAULT, MULTILIB_ISA_DEFAULT, MULTILIB_ABI_DEFAULT }
729 /* We must pass -EL to the linker by default for little endian embedded
730 targets using linker scripts with a OUTPUT_FORMAT line. Otherwise, the
731 linker will default to using big-endian output files. The OUTPUT_FORMAT
732 line must be in the linker script, otherwise -EB/-EL will not work. */
735 #if TARGET_ENDIAN_DEFAULT == 0
736 #define ENDIAN_SPEC "%{!EB:%{!meb:-EL}} %{EB|meb:-EB}"
738 #define ENDIAN_SPEC "%{!EL:%{!mel:-EB}} %{EL|mel:-EL}"
742 #define TARGET_OPTIONS \
744 SUBTARGET_TARGET_OPTIONS \
745 { "tune=", &mips_tune_string, \
746 N_("Specify CPU for scheduling purposes")}, \
747 { "arch=", &mips_arch_string, \
748 N_("Specify CPU for code generation purposes")}, \
749 { "abi=", &mips_abi_string, \
750 N_("Specify an ABI")}, \
751 { "ips", &mips_isa_string, \
752 N_("Specify a Standard MIPS ISA")}, \
753 { "entry", &mips_entry_string, \
754 N_("Use mips16 entry/exit psuedo ops")}, \
755 { "no-mips16", &mips_no_mips16_string, \
756 N_("Don't use MIPS16 instructions")}, \
757 { "no-flush-func", &mips_cache_flush_func, \
758 N_("Don't call any cache flush functions")}, \
759 { "flush-func=", &mips_cache_flush_func, \
760 N_("Specify cache flush function")}, \
763 /* This is meant to be redefined in the host dependent files. */
764 #define SUBTARGET_TARGET_OPTIONS
766 #define GENERATE_BRANCHLIKELY (TARGET_BRANCHLIKELY \
770 /* Generate three-operand multiply instructions for SImode. */
771 #define GENERATE_MULT3_SI ((TARGET_MIPS3900 \
779 /* Generate three-operand multiply instructions for DImode. */
780 #define GENERATE_MULT3_DI ((TARGET_MIPS3900) \
783 /* Macros to decide whether certain features are available or not,
784 depending on the instruction set architecture level. */
786 #define HAVE_SQRT_P() (!ISA_MIPS1)
788 /* True if the ABI can only work with 64-bit integer registers. We
789 generally allow ad-hoc variations for TARGET_SINGLE_FLOAT, but
790 otherwise floating-point registers must also be 64-bit. */
791 #define ABI_NEEDS_64BIT_REGS (mips_abi == ABI_64 \
792 || mips_abi == ABI_O64 \
793 || mips_abi == ABI_N32)
795 /* Likewise for 32-bit regs. */
796 #define ABI_NEEDS_32BIT_REGS (mips_abi == ABI_32)
798 /* ISA has instructions for managing 64 bit fp and gp regs (eg. mips3). */
799 #define ISA_HAS_64BIT_REGS (ISA_MIPS3 \
803 /* ISA has branch likely instructions (eg. mips2). */
804 /* Disable branchlikely for tx39 until compare rewrite. They haven't
805 been generated up to this point. */
806 #define ISA_HAS_BRANCHLIKELY (!ISA_MIPS1 \
809 /* ISA has the conditional move instructions introduced in mips4. */
810 #define ISA_HAS_CONDMOVE ((ISA_MIPS4 \
813 && !TARGET_MIPS5500 \
816 /* ISA has just the integer condition move instructions (movn,movz) */
817 #define ISA_HAS_INT_CONDMOVE 0
819 /* ISA has the mips4 FP condition code instructions: FP-compare to CC,
820 branch on CC, and move (both FP and non-FP) on CC. */
821 #define ISA_HAS_8CC (ISA_MIPS4 \
825 /* This is a catch all for the other new mips4 instructions: indexed load and
826 indexed prefetch instructions, the FP madd and msub instructions,
827 and the FP recip and recip sqrt instructions */
828 #define ISA_HAS_FP4 ((ISA_MIPS4 \
832 /* ISA has conditional trap instructions. */
833 #define ISA_HAS_COND_TRAP (!ISA_MIPS1 \
836 /* ISA has integer multiply-accumulate instructions, madd and msub. */
837 #define ISA_HAS_MADD_MSUB ((ISA_MIPS32 \
841 /* ISA has floating-point nmadd and nmsub instructions. */
842 #define ISA_HAS_NMADD_NMSUB ((ISA_MIPS4 \
844 && (!TARGET_MIPS5400 || TARGET_MAD) \
847 /* ISA has count leading zeroes/ones instruction (not implemented). */
848 #define ISA_HAS_CLZ_CLO ((ISA_MIPS32 \
852 /* ISA has double-word count leading zeroes/ones instruction (not
854 #define ISA_HAS_DCLZ_DCLO (ISA_MIPS64 \
857 /* ISA has three operand multiply instructions that put
858 the high part in an accumulator: mulhi or mulhiu. */
859 #define ISA_HAS_MULHI (TARGET_MIPS5400 \
864 /* ISA has three operand multiply instructions that
865 negates the result and puts the result in an accumulator. */
866 #define ISA_HAS_MULS (TARGET_MIPS5400 \
871 /* ISA has three operand multiply instructions that subtracts the
872 result from a 4th operand and puts the result in an accumulator. */
873 #define ISA_HAS_MSAC (TARGET_MIPS5400 \
877 /* ISA has three operand multiply instructions that the result
878 from a 4th operand and puts the result in an accumulator. */
879 #define ISA_HAS_MACC (TARGET_MIPS5400 \
884 /* ISA has 32-bit rotate right instruction. */
885 #define ISA_HAS_ROTR_SI (TARGET_MIPS5400 \
890 /* ISA has 32-bit rotate right instruction. */
891 #define ISA_HAS_ROTR_DI (TARGET_64BIT \
892 && (TARGET_MIPS5400 \
898 /* ISA has data prefetch instruction. */
899 #define ISA_HAS_PREFETCH ((ISA_MIPS4 \
904 /* True if trunc.w.s and trunc.w.d are real (not synthetic)
905 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
906 also requires TARGET_DOUBLE_FLOAT. */
907 #define ISA_HAS_TRUNC_W (!ISA_MIPS1)
909 /* CC1_SPEC causes -mips3 and -mips4 to set -mfp64 and -mgp64; -mips1 or
910 -mips2 sets -mfp32 and -mgp32. This can be overridden by an explicit
911 -mfp32, -mfp64, -mgp32 or -mgp64. -mfp64 sets MASK_FLOAT64 in
912 target_flags, and -mgp64 sets MASK_64BIT.
914 Setting MASK_64BIT in target_flags will cause gcc to assume that
915 registers are 64 bits wide. int, long and void * will be 32 bit;
916 this may be changed with -mint64 or -mlong64.
918 The gen* programs link code that refers to MASK_64BIT. They don't
919 actually use the information in target_flags; they just refer to
922 /* Switch Recognition by gcc.c. Add -G xx support */
924 #undef SWITCH_TAKES_ARG
925 #define SWITCH_TAKES_ARG(CHAR) \
926 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G')
928 /* Sometimes certain combinations of command options do not make sense
929 on a particular target machine. You can define a macro
930 `OVERRIDE_OPTIONS' to take account of this. This macro, if
931 defined, is executed once just after all the command options have
934 On the MIPS, it is used to handle -G. We also use it to set up all
935 of the tables referenced in the other macros. */
937 #define OVERRIDE_OPTIONS override_options ()
939 #define CONDITIONAL_REGISTER_USAGE mips_conditional_register_usage ()
941 /* Show we can debug even without a frame pointer. */
942 #define CAN_DEBUG_WITHOUT_FP
944 /* Tell collect what flags to pass to nm. */
946 #define NM_FLAGS "-Bn"
950 /* Assembler specs. */
952 /* MIPS_AS_ASM_SPEC is passed when using the MIPS assembler rather
955 #define MIPS_AS_ASM_SPEC "\
956 %{!.s:-nocpp} %{.s: %{cpp} %{nocpp}} \
957 %{pipe: %e-pipe is not supported} \
958 %{K} %(subtarget_mips_as_asm_spec)"
960 /* SUBTARGET_MIPS_AS_ASM_SPEC is passed when using the MIPS assembler
961 rather than gas. It may be overridden by subtargets. */
963 #ifndef SUBTARGET_MIPS_AS_ASM_SPEC
964 #define SUBTARGET_MIPS_AS_ASM_SPEC "%{v}"
967 /* GAS_ASM_SPEC is passed when using gas, rather than the MIPS
970 #define GAS_ASM_SPEC "%{mtune=*} %{v}"
975 #ifndef MIPS_ABI_DEFAULT
976 #define MIPS_ABI_DEFAULT ABI_32
979 /* Use the most portable ABI flag for the ASM specs. */
981 #if MIPS_ABI_DEFAULT == ABI_32
982 #define MULTILIB_ABI_DEFAULT "mabi=32"
983 #define ASM_ABI_DEFAULT_SPEC "-32"
986 #if MIPS_ABI_DEFAULT == ABI_O64
987 #define MULTILIB_ABI_DEFAULT "mabi=o64"
988 #define ASM_ABI_DEFAULT_SPEC "-mabi=o64"
991 #if MIPS_ABI_DEFAULT == ABI_N32
992 #define MULTILIB_ABI_DEFAULT "mabi=n32"
993 #define ASM_ABI_DEFAULT_SPEC "-n32"
996 #if MIPS_ABI_DEFAULT == ABI_64
997 #define MULTILIB_ABI_DEFAULT "mabi=64"
998 #define ASM_ABI_DEFAULT_SPEC "-64"
1001 #if MIPS_ABI_DEFAULT == ABI_EABI
1002 #define MULTILIB_ABI_DEFAULT "mabi=eabi"
1003 #define ASM_ABI_DEFAULT_SPEC "-mabi=eabi"
1006 #if MIPS_ABI_DEFAULT == ABI_MEABI
1007 /* Most GAS don't know about MEABI. */
1008 #define MULTILIB_ABI_DEFAULT "mabi=meabi"
1009 #define ASM_ABI_DEFAULT_SPEC ""
1012 /* Only ELF targets can switch the ABI. */
1013 #ifndef OBJECT_FORMAT_ELF
1014 #undef ASM_ABI_DEFAULT_SPEC
1015 #define ASM_ABI_DEFAULT_SPEC ""
1018 /* TARGET_ASM_SPEC is used to select either MIPS_AS_ASM_SPEC or
1019 GAS_ASM_SPEC as the default, depending upon the value of
1022 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1025 #define TARGET_ASM_SPEC "\
1026 %{mmips-as: %(mips_as_asm_spec)} \
1027 %{!mmips-as: %(gas_asm_spec)}"
1031 #define TARGET_ASM_SPEC "\
1032 %{!mgas: %(mips_as_asm_spec)} \
1033 %{mgas: %(gas_asm_spec)}"
1035 #endif /* not GAS */
1037 /* SUBTARGET_ASM_OPTIMIZING_SPEC handles passing optimization options
1038 to the assembler. It may be overridden by subtargets. */
1039 #ifndef SUBTARGET_ASM_OPTIMIZING_SPEC
1040 #define SUBTARGET_ASM_OPTIMIZING_SPEC "\
1042 %{!noasmopt:%{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3}}"
1045 /* SUBTARGET_ASM_DEBUGGING_SPEC handles passing debugging options to
1046 the assembler. It may be overridden by subtargets. */
1047 #ifndef SUBTARGET_ASM_DEBUGGING_SPEC
1048 #define SUBTARGET_ASM_DEBUGGING_SPEC "\
1049 %{g} %{g0} %{g1} %{g2} %{g3} \
1050 %{ggdb:-g} %{ggdb0:-g0} %{ggdb1:-g1} %{ggdb2:-g2} %{ggdb3:-g3} \
1051 %{gstabs:-g} %{gstabs0:-g0} %{gstabs1:-g1} %{gstabs2:-g2} %{gstabs3:-g3} \
1052 %{gstabs+:-g} %{gstabs+0:-g0} %{gstabs+1:-g1} %{gstabs+2:-g2} %{gstabs+3:-g3} \
1053 %{gcoff:-g} %{gcoff0:-g0} %{gcoff1:-g1} %{gcoff2:-g2} %{gcoff3:-g3} \
1054 %{!gdwarf*:-mdebug} %{gdwarf*:-no-mdebug}"
1057 /* SUBTARGET_ASM_SPEC is always passed to the assembler. It may be
1058 overridden by subtargets. */
1060 #ifndef SUBTARGET_ASM_SPEC
1061 #define SUBTARGET_ASM_SPEC ""
1064 /* ASM_SPEC is the set of arguments to pass to the assembler. Note: we
1065 pass -mgp32, -mgp64, -march, -mabi=eabi and -meabi=o64 regardless of
1066 whether we're using GAS. These options can only be used properly
1067 with GAS, and it is better to get an error from a non-GAS assembler
1068 than to silently generate bad code. */
1072 %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64}\
1073 %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
1074 %(subtarget_asm_optimizing_spec) \
1075 %(subtarget_asm_debugging_spec) \
1077 %{mabi=32:-32}%{mabi=n32:-n32}%{mabi=64:-64}%{mabi=n64:-64} \
1078 %{mabi=eabi} %{mabi=o64} %{!mabi*: %(asm_abi_default_spec)} \
1079 %{mgp32} %{mgp64} %{march=*} \
1080 %(target_asm_spec) \
1081 %(subtarget_asm_spec)"
1083 /* Specify to run a post-processor, mips-tfile after the assembler
1084 has run to stuff the mips debug information into the object file.
1085 This is needed because the $#!%^ MIPS assembler provides no way
1086 of specifying such information in the assembly file. If we are
1087 cross compiling, disable mips-tfile unless the user specifies
1090 #ifndef ASM_FINAL_SPEC
1091 #if ((TARGET_CPU_DEFAULT | TARGET_DEFAULT) & MASK_GAS) != 0
1093 #define ASM_FINAL_SPEC "\
1094 %{mmips-as: %{!mno-mips-tfile: \
1095 \n mips-tfile %{v*: -v} \
1097 %{!K: %{save-temps: -I %b.o~}} \
1098 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1099 %{.s:%i} %{!.s:%g.s}}}"
1103 #define ASM_FINAL_SPEC "\
1104 %{!mgas: %{!mno-mips-tfile: \
1105 \n mips-tfile %{v*: -v} \
1107 %{!K: %{save-temps: -I %b.o~}} \
1108 %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %U.o} \
1109 %{.s:%i} %{!.s:%g.s}}}"
1112 #endif /* ASM_FINAL_SPEC */
1114 /* Redefinition of libraries used. Mips doesn't support normal
1115 UNIX style profiling via calling _mcount. It does offer
1116 profiling that samples the PC, so do what we can... */
1119 #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
1122 /* Extra switches sometimes passed to the linker. */
1123 /* ??? The bestGnum will never be passed to the linker, because the gcc driver
1124 will interpret it as a -b option. */
1127 #define LINK_SPEC "\
1129 %{G*} %{mips1} %{mips2} %{mips3} %{mips4} %{mips32} %{mips64} \
1130 %{bestGnum} %{shared} %{non_shared}"
1131 #endif /* LINK_SPEC defined */
1134 /* Specs for the compiler proper */
1136 /* SUBTARGET_CC1_SPEC is passed to the compiler proper. It may be
1137 overridden by subtargets. */
1138 #ifndef SUBTARGET_CC1_SPEC
1139 #define SUBTARGET_CC1_SPEC ""
1142 /* CC1_SPEC is the set of arguments to pass to the compiler proper. */
1143 /* Note, we will need to adjust the following if we ever find a MIPS variant
1144 that has 32-bit GPRs and 64-bit FPRs as well as fix all of the reload bugs
1145 that show up in this case. */
1149 %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
1150 %{G*} %{EB:-meb} %{EL:-mel} %{EB:%{EL:%emay not use both -EB and -EL}} \
1152 %(subtarget_cc1_spec)"
1155 /* Preprocessor specs. */
1157 /* SUBTARGET_CPP_SPEC is passed to the preprocessor. It may be
1158 overridden by subtargets. */
1159 #ifndef SUBTARGET_CPP_SPEC
1160 #define SUBTARGET_CPP_SPEC ""
1163 #define CPP_SPEC "%(subtarget_cpp_spec)"
1165 /* This macro defines names of additional specifications to put in the specs
1166 that can be used in various specifications like CC1_SPEC. Its definition
1167 is an initializer with a subgrouping for each command option.
1169 Each subgrouping contains a string constant, that defines the
1170 specification name, and a string constant that used by the GNU CC driver
1173 Do not define this macro if it does not need to do anything. */
1175 #define EXTRA_SPECS \
1176 { "subtarget_cc1_spec", SUBTARGET_CC1_SPEC }, \
1177 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \
1178 { "mips_as_asm_spec", MIPS_AS_ASM_SPEC }, \
1179 { "gas_asm_spec", GAS_ASM_SPEC }, \
1180 { "target_asm_spec", TARGET_ASM_SPEC }, \
1181 { "subtarget_mips_as_asm_spec", SUBTARGET_MIPS_AS_ASM_SPEC }, \
1182 { "subtarget_asm_optimizing_spec", SUBTARGET_ASM_OPTIMIZING_SPEC }, \
1183 { "subtarget_asm_debugging_spec", SUBTARGET_ASM_DEBUGGING_SPEC }, \
1184 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \
1185 { "asm_abi_default_spec", ASM_ABI_DEFAULT_SPEC }, \
1186 { "endian_spec", ENDIAN_SPEC }, \
1187 SUBTARGET_EXTRA_SPECS
1189 #ifndef SUBTARGET_EXTRA_SPECS
1190 #define SUBTARGET_EXTRA_SPECS
1193 /* If defined, this macro is an additional prefix to try after
1194 `STANDARD_EXEC_PREFIX'. */
1196 #ifndef MD_EXEC_PREFIX
1197 #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc/"
1200 #ifndef MD_STARTFILE_PREFIX
1201 #define MD_STARTFILE_PREFIX "/usr/lib/cmplrs/cc/"
1205 /* Print subsidiary information on the compiler version in use. */
1207 #define MIPS_VERSION "[AL 1.1, MM 40]"
1209 #ifndef MACHINE_TYPE
1210 #define MACHINE_TYPE "BSD Mips"
1213 #ifndef TARGET_VERSION_INTERNAL
1214 #define TARGET_VERSION_INTERNAL(STREAM) \
1215 fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
1218 #ifndef TARGET_VERSION
1219 #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
1223 #define SDB_DEBUGGING_INFO 1 /* generate info for mips-tfile */
1224 #define DBX_DEBUGGING_INFO 1 /* generate stabs (OSF/rose) */
1225 #define MIPS_DEBUGGING_INFO 1 /* MIPS specific debugging info */
1227 #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
1228 #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
1231 /* By default, turn on GDB extensions. */
1232 #define DEFAULT_GDB_EXTENSIONS 1
1234 /* If we are passing smuggling stabs through the MIPS ECOFF object
1235 format, put a comment in front of the .stab<x> operation so
1236 that the MIPS assembler does not choke. The mips-tfile program
1237 will correctly put the stab into the object file. */
1239 #define ASM_STABS_OP ((TARGET_GAS) ? "\t.stabs\t" : " #.stabs\t")
1240 #define ASM_STABN_OP ((TARGET_GAS) ? "\t.stabn\t" : " #.stabn\t")
1241 #define ASM_STABD_OP ((TARGET_GAS) ? "\t.stabd\t" : " #.stabd\t")
1243 /* Local compiler-generated symbols must have a prefix that the assembler
1244 understands. By default, this is $, although some targets (e.g.,
1245 NetBSD-ELF) need to override this. */
1247 #ifndef LOCAL_LABEL_PREFIX
1248 #define LOCAL_LABEL_PREFIX "$"
1251 /* By default on the mips, external symbols do not have an underscore
1252 prepended, but some targets (e.g., NetBSD) require this. */
1254 #ifndef USER_LABEL_PREFIX
1255 #define USER_LABEL_PREFIX ""
1258 /* Forward references to tags are allowed. */
1259 #define SDB_ALLOW_FORWARD_REFERENCES
1261 /* Unknown tags are also allowed. */
1262 #define SDB_ALLOW_UNKNOWN_REFERENCES
1264 /* On Sun 4, this limit is 2048. We use 1500 to be safe,
1265 since the length can run past this up to a continuation point. */
1266 #undef DBX_CONTIN_LENGTH
1267 #define DBX_CONTIN_LENGTH 1500
1269 /* How to renumber registers for dbx and gdb. */
1270 #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
1272 /* The mapping from gcc register number to DWARF 2 CFA column number.
1273 This mapping does not allow for tracking register 0, since SGI's broken
1274 dwarf reader thinks column 0 is used for the frame address, but since
1275 register 0 is fixed this is not a problem. */
1276 #define DWARF_FRAME_REGNUM(REG) \
1277 (REG == GP_REG_FIRST + 31 ? DWARF_FRAME_RETURN_COLUMN : REG)
1279 /* The DWARF 2 CFA column which tracks the return address. */
1280 #define DWARF_FRAME_RETURN_COLUMN (FP_REG_LAST + 1)
1282 /* Before the prologue, RA lives in r31. */
1283 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, GP_REG_FIRST + 31)
1285 /* Describe how we implement __builtin_eh_return. */
1286 #define EH_RETURN_DATA_REGNO(N) ((N) < (TARGET_MIPS16 ? 2 : 4) ? (N) + GP_ARG_FIRST : INVALID_REGNUM)
1287 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 3)
1289 /* Offsets recorded in opcodes are a multiple of this alignment factor.
1290 The default for this in 64-bit mode is 8, which causes problems with
1291 SFmode register saves. */
1292 #define DWARF_CIE_DATA_ALIGNMENT 4
1294 /* Overrides for the COFF debug format. */
1295 #define PUT_SDB_SCL(a) \
1297 extern FILE *asm_out_text_file; \
1298 fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
1301 #define PUT_SDB_INT_VAL(a) \
1303 extern FILE *asm_out_text_file; \
1304 fprintf (asm_out_text_file, "\t.val\t"); \
1305 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1306 fprintf (asm_out_text_file, ";"); \
1309 #define PUT_SDB_VAL(a) \
1311 extern FILE *asm_out_text_file; \
1312 fputs ("\t.val\t", asm_out_text_file); \
1313 output_addr_const (asm_out_text_file, (a)); \
1314 fputc (';', asm_out_text_file); \
1317 #define PUT_SDB_DEF(a) \
1319 extern FILE *asm_out_text_file; \
1320 fprintf (asm_out_text_file, "\t%s.def\t", \
1321 (TARGET_GAS) ? "" : "#"); \
1322 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1323 fputc (';', asm_out_text_file); \
1326 #define PUT_SDB_PLAIN_DEF(a) \
1328 extern FILE *asm_out_text_file; \
1329 fprintf (asm_out_text_file, "\t%s.def\t.%s;", \
1330 (TARGET_GAS) ? "" : "#", (a)); \
1333 #define PUT_SDB_ENDEF \
1335 extern FILE *asm_out_text_file; \
1336 fprintf (asm_out_text_file, "\t.endef\n"); \
1339 #define PUT_SDB_TYPE(a) \
1341 extern FILE *asm_out_text_file; \
1342 fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
1345 #define PUT_SDB_SIZE(a) \
1347 extern FILE *asm_out_text_file; \
1348 fprintf (asm_out_text_file, "\t.size\t"); \
1349 fprintf (asm_out_text_file, HOST_WIDE_INT_PRINT_DEC, (HOST_WIDE_INT)(a)); \
1350 fprintf (asm_out_text_file, ";"); \
1353 #define PUT_SDB_DIM(a) \
1355 extern FILE *asm_out_text_file; \
1356 fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
1359 #ifndef PUT_SDB_START_DIM
1360 #define PUT_SDB_START_DIM \
1362 extern FILE *asm_out_text_file; \
1363 fprintf (asm_out_text_file, "\t.dim\t"); \
1367 #ifndef PUT_SDB_NEXT_DIM
1368 #define PUT_SDB_NEXT_DIM(a) \
1370 extern FILE *asm_out_text_file; \
1371 fprintf (asm_out_text_file, "%d,", a); \
1375 #ifndef PUT_SDB_LAST_DIM
1376 #define PUT_SDB_LAST_DIM(a) \
1378 extern FILE *asm_out_text_file; \
1379 fprintf (asm_out_text_file, "%d;", a); \
1383 #define PUT_SDB_TAG(a) \
1385 extern FILE *asm_out_text_file; \
1386 fprintf (asm_out_text_file, "\t.tag\t"); \
1387 ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
1388 fputc (';', asm_out_text_file); \
1391 /* For block start and end, we create labels, so that
1392 later we can figure out where the correct offset is.
1393 The normal .ent/.end serve well enough for functions,
1394 so those are just commented out. */
1396 #define PUT_SDB_BLOCK_START(LINE) \
1398 extern FILE *asm_out_text_file; \
1399 fprintf (asm_out_text_file, \
1400 "%sLb%d:\n\t%s.begin\t%sLb%d\t%d\n", \
1401 LOCAL_LABEL_PREFIX, \
1403 (TARGET_GAS) ? "" : "#", \
1404 LOCAL_LABEL_PREFIX, \
1407 sdb_label_count++; \
1410 #define PUT_SDB_BLOCK_END(LINE) \
1412 extern FILE *asm_out_text_file; \
1413 fprintf (asm_out_text_file, \
1414 "%sLe%d:\n\t%s.bend\t%sLe%d\t%d\n", \
1415 LOCAL_LABEL_PREFIX, \
1417 (TARGET_GAS) ? "" : "#", \
1418 LOCAL_LABEL_PREFIX, \
1421 sdb_label_count++; \
1424 #define PUT_SDB_FUNCTION_START(LINE)
1426 #define PUT_SDB_FUNCTION_END(LINE) \
1428 extern FILE *asm_out_text_file; \
1429 ASM_OUTPUT_SOURCE_LINE (asm_out_text_file, LINE + sdb_begin_function_line); \
1432 #define PUT_SDB_EPILOGUE_END(NAME)
1434 #define PUT_SDB_SRC_FILE(FILENAME) \
1436 extern FILE *asm_out_text_file; \
1437 output_file_directive (asm_out_text_file, (FILENAME));\
1440 #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
1441 sprintf ((BUFFER), ".%dfake", (NUMBER));
1443 /* Correct the offset of automatic variables and arguments. Note that
1444 the MIPS debug format wants all automatic variables and arguments
1445 to be in terms of the virtual frame pointer (stack pointer before
1446 any adjustment in the function), while the MIPS 3.0 linker wants
1447 the frame pointer to be the stack pointer after the initial
1450 #define DEBUGGER_AUTO_OFFSET(X) \
1451 mips_debugger_offset (X, (HOST_WIDE_INT) 0)
1452 #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
1453 mips_debugger_offset (X, (HOST_WIDE_INT) OFFSET)
1455 /* Tell collect that the object format is ECOFF */
1456 #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
1457 #define EXTENDED_COFF /* ECOFF, not normal coff */
1459 /* Target machine storage layout */
1461 /* Define this if most significant bit is lowest numbered
1462 in instructions that operate on numbered bit-fields.
1464 #define BITS_BIG_ENDIAN 0
1466 /* Define this if most significant byte of a word is the lowest numbered. */
1467 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1469 /* Define this if most significant word of a multiword number is the lowest. */
1470 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
1472 /* Define this to set the endianness to use in libgcc2.c, which can
1473 not depend on target_flags. */
1474 #if !defined(MIPSEL) && !defined(__MIPSEL__)
1475 #define LIBGCC2_WORDS_BIG_ENDIAN 1
1477 #define LIBGCC2_WORDS_BIG_ENDIAN 0
1480 #define MAX_BITS_PER_WORD 64
1482 /* Width of a word, in units (bytes). */
1483 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
1484 #define MIN_UNITS_PER_WORD 4
1486 /* For MIPS, width of a floating point register. */
1487 #define UNITS_PER_FPREG (TARGET_FLOAT64 ? 8 : 4)
1489 /* If register $f0 holds a floating-point value, $f(0 + FP_INC) is
1490 the next available register. */
1491 #define FP_INC (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT ? 1 : 2)
1493 /* The largest size of value that can be held in floating-point registers. */
1494 #define UNITS_PER_FPVALUE (TARGET_SOFT_FLOAT ? 0 : FP_INC * UNITS_PER_FPREG)
1496 /* The number of bytes in a double. */
1497 #define UNITS_PER_DOUBLE (TYPE_PRECISION (double_type_node) / BITS_PER_UNIT)
1499 /* A C expression for the size in bits of the type `int' on the
1500 target machine. If you don't define this, the default is one
1502 #define INT_TYPE_SIZE (TARGET_INT64 ? 64 : 32)
1504 /* Tell the preprocessor the maximum size of wchar_t. */
1505 #ifndef MAX_WCHAR_TYPE_SIZE
1506 #ifndef WCHAR_TYPE_SIZE
1507 #define MAX_WCHAR_TYPE_SIZE 64
1511 /* A C expression for the size in bits of the type `short' on the
1512 target machine. If you don't define this, the default is half a
1513 word. (If this would be less than one storage unit, it is
1514 rounded up to one unit.) */
1515 #define SHORT_TYPE_SIZE 16
1517 /* A C expression for the size in bits of the type `long' on the
1518 target machine. If you don't define this, the default is one
1520 #define LONG_TYPE_SIZE (TARGET_LONG64 ? 64 : 32)
1521 #define MAX_LONG_TYPE_SIZE 64
1523 /* A C expression for the size in bits of the type `long long' on the
1524 target machine. If you don't define this, the default is two
1526 #define LONG_LONG_TYPE_SIZE 64
1528 /* A C expression for the size in bits of the type `float' on the
1529 target machine. If you don't define this, the default is one
1531 #define FLOAT_TYPE_SIZE 32
1533 /* A C expression for the size in bits of the type `double' on the
1534 target machine. If you don't define this, the default is two
1536 #define DOUBLE_TYPE_SIZE 64
1538 /* A C expression for the size in bits of the type `long double' on
1539 the target machine. If you don't define this, the default is two
1541 #define LONG_DOUBLE_TYPE_SIZE 64
1543 /* Width in bits of a pointer.
1544 See also the macro `Pmode' defined below. */
1545 #ifndef POINTER_SIZE
1546 #define POINTER_SIZE (Pmode == DImode ? 64 : 32)
1549 /* Allocation boundary (in *bits*) for storing pointers in memory. */
1550 #define POINTER_BOUNDARY (Pmode == DImode ? 64 : 32)
1552 /* Allocation boundary (in *bits*) for storing arguments in argument list. */
1553 #define PARM_BOUNDARY ((mips_abi == ABI_O64 || mips_abi == ABI_N32 \
1554 || mips_abi == ABI_64 \
1555 || (mips_abi == ABI_EABI && TARGET_64BIT)) ? 64 : 32)
1557 /* Allocation boundary (in *bits*) for the code of a function. */
1558 #define FUNCTION_BOUNDARY 32
1560 /* Alignment of field after `int : 0' in a structure. */
1561 #define EMPTY_FIELD_BOUNDARY 32
1563 /* Every structure's size must be a multiple of this. */
1564 /* 8 is observed right on a DECstation and on riscos 4.02. */
1565 #define STRUCTURE_SIZE_BOUNDARY 8
1567 /* There is no point aligning anything to a rounder boundary than this. */
1568 #define BIGGEST_ALIGNMENT 64
1570 /* Set this nonzero if move instructions will actually fail to work
1571 when given unaligned data. */
1572 #define STRICT_ALIGNMENT 1
1574 /* Define this if you wish to imitate the way many other C compilers
1575 handle alignment of bitfields and the structures that contain
1578 The behavior is that the type written for a bitfield (`int',
1579 `short', or other integer type) imposes an alignment for the
1580 entire structure, as if the structure really did contain an
1581 ordinary field of that type. In addition, the bitfield is placed
1582 within the structure so that it would fit within such a field,
1583 not crossing a boundary for it.
1585 Thus, on most machines, a bitfield whose type is written as `int'
1586 would not cross a four-byte boundary, and would force four-byte
1587 alignment for the whole structure. (The alignment used may not
1588 be four bytes; it is controlled by the other alignment
1591 If the macro is defined, its definition should be a C expression;
1592 a nonzero value for the expression enables this behavior. */
1594 #define PCC_BITFIELD_TYPE_MATTERS 1
1596 /* If defined, a C expression to compute the alignment given to a
1597 constant that is being placed in memory. CONSTANT is the constant
1598 and ALIGN is the alignment that the object would ordinarily have.
1599 The value of this macro is used instead of that alignment to align
1602 If this macro is not defined, then ALIGN is used.
1604 The typical use of this macro is to increase alignment for string
1605 constants to be word aligned so that `strcpy' calls that copy
1606 constants can be done inline. */
1608 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
1609 ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
1610 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
1612 /* If defined, a C expression to compute the alignment for a static
1613 variable. TYPE is the data type, and ALIGN is the alignment that
1614 the object would ordinarily have. The value of this macro is used
1615 instead of that alignment to align the object.
1617 If this macro is not defined, then ALIGN is used.
1619 One use of this macro is to increase alignment of medium-size
1620 data to make it all fit in fewer cache lines. Another is to
1621 cause character arrays to be word-aligned so that `strcpy' calls
1622 that copy constants to character arrays can be done inline. */
1624 #undef DATA_ALIGNMENT
1625 #define DATA_ALIGNMENT(TYPE, ALIGN) \
1626 ((((ALIGN) < BITS_PER_WORD) \
1627 && (TREE_CODE (TYPE) == ARRAY_TYPE \
1628 || TREE_CODE (TYPE) == UNION_TYPE \
1629 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
1632 /* Force right-alignment for small varargs in 32 bit little_endian mode */
1634 #define PAD_VARARGS_DOWN (TARGET_64BIT \
1635 || mips_abi == ABI_MEABI \
1636 ? BYTES_BIG_ENDIAN : !BYTES_BIG_ENDIAN)
1638 /* Define this macro if an argument declared as `char' or `short' in a
1639 prototype should actually be passed as an `int'. In addition to
1640 avoiding errors in certain cases of mismatch, it also makes for
1641 better code on certain machines. */
1643 #define PROMOTE_PROTOTYPES 1
1645 /* Define if operations between registers always perform the operation
1646 on the full register even if a narrower mode is specified. */
1647 #define WORD_REGISTER_OPERATIONS
1649 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1650 will either zero-extend or sign-extend. The value of this macro should
1651 be the code that says which one of the two operations is implicitly
1654 When in 64 bit mode, mips_move_1word will sign extend SImode and CCmode
1655 moves. All other referces are zero extended. */
1656 #define LOAD_EXTEND_OP(MODE) \
1657 (TARGET_64BIT && ((MODE) == SImode || (MODE) == CCmode) \
1658 ? SIGN_EXTEND : ZERO_EXTEND)
1660 /* Define this macro if it is advisable to hold scalars in registers
1661 in a wider mode than that declared by the program. In such cases,
1662 the value is constrained to be within the bounds of the declared
1663 type, but kept valid in the wider mode. The signedness of the
1664 extension may differ from that of the type.
1666 We promote any value smaller than SImode up to SImode. We don't
1667 want to promote to DImode when in 64 bit mode, because that would
1668 prevent us from using the faster SImode multiply and divide
1671 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \
1672 if (GET_MODE_CLASS (MODE) == MODE_INT \
1673 && GET_MODE_SIZE (MODE) < 4) \
1676 /* Define this if function arguments should also be promoted using the above
1679 #define PROMOTE_FUNCTION_ARGS
1681 /* Likewise, if the function return value is promoted. */
1683 #define PROMOTE_FUNCTION_RETURN
1685 /* Standard register usage. */
1687 /* Number of actual hardware registers.
1688 The hardware registers are assigned numbers for the compiler
1689 from 0 to just below FIRST_PSEUDO_REGISTER.
1690 All registers that the compiler knows about must be given numbers,
1691 even those that are not normally considered general registers.
1693 On the Mips, we have 32 integer registers, 32 floating point
1694 registers, 8 condition code registers, and the special registers
1695 hi, lo, hilo, and rap. Afetr that we have 32 COP0 registers, 32
1696 COP2 registers, and 32 COp3 registers. (COP1 is the floating-point
1697 processor.) The 8 condition code registers are only used if
1698 mips_isa >= 4. The hilo register is only used in 64 bit mode. It
1699 represents a 64 bit value stored as two 32 bit values in the hi and
1700 lo registers; this is the result of the mult instruction. rap is a
1701 pointer to the stack where the return address reg ($31) was stored.
1702 This is needed for C++ exception handling. */
1704 #define FIRST_PSEUDO_REGISTER 176
1706 /* 1 for registers that have pervasive standard uses
1707 and are not available for the register allocator.
1709 On the MIPS, see conventions, page D-2 */
1711 /* Regarding coprocessor registers: without evidence to the contrary,
1712 it's best to assume that each coprocessor register has a unique
1713 use. This can be overridden, in, e.g., override_options() or
1714 CONDITIONAL_REGISTER_USAGE should the assumption be inappropriate
1715 for a particular target. */
1717 #define FIXED_REGISTERS \
1719 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1720 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
1721 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1722 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1723 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, \
1724 /* COP0 registers */ \
1725 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1726 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1727 /* COP2 registers */ \
1728 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1729 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1730 /* COP3 registers */ \
1731 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1732 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1736 /* 1 for registers not available across function calls.
1737 These must include the FIXED_REGISTERS and also any
1738 registers that can be used without being saved.
1739 The latter must include the registers where values are returned
1740 and the register where structure-value addresses are passed.
1741 Aside from that, you can include as many other registers as you like. */
1743 #define CALL_USED_REGISTERS \
1745 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1746 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1747 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1748 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1749 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1750 /* COP0 registers */ \
1751 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1752 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1753 /* COP2 registers */ \
1754 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1755 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1756 /* COP3 registers */ \
1757 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1758 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 \
1761 /* Like `CALL_USED_REGISTERS' but used to overcome a historical
1762 problem which makes CALL_USED_REGISTERS *always* include
1763 all the FIXED_REGISTERS. Until this problem has been
1764 resolved this macro can be used to overcome this situation.
1765 In particular, block_propagate() requires this list
1766 be acurate, or we can remove registers which should be live.
1767 This macro is used in regs_invalidated_by_call. */
1770 #define CALL_REALLY_USED_REGISTERS \
1771 { /* General registers. */ \
1772 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1773 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 0, 1, \
1774 /* Floating-point registers. */ \
1775 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1776 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1778 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, \
1779 /* COP0 registers */ \
1780 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1781 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1782 /* COP2 registers */ \
1783 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1784 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1785 /* COP3 registers */ \
1786 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1787 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 \
1790 /* Internal macros to classify a register number as to whether it's a
1791 general purpose register, a floating point register, a
1792 multiply/divide register, or a status register. */
1794 #define GP_REG_FIRST 0
1795 #define GP_REG_LAST 31
1796 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1797 #define GP_DBX_FIRST 0
1799 #define FP_REG_FIRST 32
1800 #define FP_REG_LAST 63
1801 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1802 #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1804 #define MD_REG_FIRST 64
1805 #define MD_REG_LAST 66
1806 #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1808 #define ST_REG_FIRST 67
1809 #define ST_REG_LAST 74
1810 #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1812 #define RAP_REG_NUM 75
1814 #define COP0_REG_FIRST 80
1815 #define COP0_REG_LAST 111
1816 #define COP0_REG_NUM (COP0_REG_LAST - COP0_REG_FIRST + 1)
1818 #define COP2_REG_FIRST 112
1819 #define COP2_REG_LAST 143
1820 #define COP2_REG_NUM (COP2_REG_LAST - COP2_REG_FIRST + 1)
1822 #define COP3_REG_FIRST 144
1823 #define COP3_REG_LAST 175
1824 #define COP3_REG_NUM (COP3_REG_LAST - COP3_REG_FIRST + 1)
1825 /* ALL_COP_REG_NUM assumes that COP0,2,and 3 are numbered consecutively. */
1826 #define ALL_COP_REG_NUM (COP3_REG_LAST - COP0_REG_FIRST + 1)
1828 #define AT_REGNUM (GP_REG_FIRST + 1)
1829 #define HI_REGNUM (MD_REG_FIRST + 0)
1830 #define LO_REGNUM (MD_REG_FIRST + 1)
1831 #define HILO_REGNUM (MD_REG_FIRST + 2)
1833 /* FPSW_REGNUM is the single condition code used if mips_isa < 4. If
1834 mips_isa >= 4, it should not be used, and an arbitrary ST_REG
1835 should be used instead. */
1836 #define FPSW_REGNUM ST_REG_FIRST
1838 #define GP_REG_P(REGNO) \
1839 ((unsigned int) ((int) (REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1840 #define M16_REG_P(REGNO) \
1841 (((REGNO) >= 2 && (REGNO) <= 7) || (REGNO) == 16 || (REGNO) == 17)
1842 #define FP_REG_P(REGNO) \
1843 ((unsigned int) ((int) (REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1844 #define MD_REG_P(REGNO) \
1845 ((unsigned int) ((int) (REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1846 #define ST_REG_P(REGNO) \
1847 ((unsigned int) ((int) (REGNO) - ST_REG_FIRST) < ST_REG_NUM)
1848 #define COP0_REG_P(REGNO) \
1849 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < COP0_REG_NUM)
1850 #define COP2_REG_P(REGNO) \
1851 ((unsigned int) ((int) (REGNO) - COP2_REG_FIRST) < COP2_REG_NUM)
1852 #define COP3_REG_P(REGNO) \
1853 ((unsigned int) ((int) (REGNO) - COP3_REG_FIRST) < COP3_REG_NUM)
1854 #define ALL_COP_REG_P(REGNO) \
1855 ((unsigned int) ((int) (REGNO) - COP0_REG_FIRST) < ALL_COP_REG_NUM)
1857 /* Return coprocessor number from register number. */
1859 #define COPNUM_AS_CHAR_FROM_REGNUM(REGNO) \
1860 (COP0_REG_P (REGNO) ? '0' : COP2_REG_P (REGNO) ? '2' \
1861 : COP3_REG_P (REGNO) ? '3' : '?')
1863 /* Return number of consecutive hard regs needed starting at reg REGNO
1864 to hold something of mode MODE.
1865 This is ordinarily the length in words of a value of mode MODE
1866 but can be less for certain modes in special long registers.
1868 On the MIPS, all general registers are one word long. Except on
1869 the R4000 with the FR bit set, the floating point uses register
1870 pairs, with the second register not being allocable. */
1872 #define HARD_REGNO_NREGS(REGNO, MODE) mips_hard_regno_nregs (REGNO, MODE)
1874 /* Value is 1 if hard register REGNO can hold a value of machine-mode
1875 MODE. In 32 bit mode, require that DImode and DFmode be in even
1876 registers. For DImode, this makes some of the insns easier to
1877 write, since you don't have to worry about a DImode value in
1878 registers 3 & 4, producing a result in 4 & 5.
1880 To make the code simpler HARD_REGNO_MODE_OK now just references an
1881 array built in override_options. Because machmodes.h is not yet
1882 included before this file is processed, the MODE bound can't be
1885 extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1887 #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1888 mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1890 /* Value is 1 if it is a good idea to tie two pseudo registers
1891 when one has mode MODE1 and one has mode MODE2.
1892 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1893 for any hard reg, then this must be 0 for correct output. */
1894 #define MODES_TIEABLE_P(MODE1, MODE2) \
1895 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1896 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1897 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1898 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1900 /* MIPS pc is not overloaded on a register. */
1901 /* #define PC_REGNUM xx */
1903 /* Register to use for pushing function arguments. */
1904 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 29)
1906 /* Offset from the stack pointer to the first available location. Use
1907 the default value zero. */
1908 /* #define STACK_POINTER_OFFSET 0 */
1910 /* Base register for access to local variables of the function. We
1911 pretend that the frame pointer is $1, and then eliminate it to
1912 HARD_FRAME_POINTER_REGNUM. We can get away with this because $1 is
1913 a fixed register, and will not be used for anything else. */
1914 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 1)
1916 /* Temporary scratch register for use by the assembler. */
1917 #define ASSEMBLER_SCRATCH_REGNUM (GP_REG_FIRST + 1)
1919 /* $30 is not available on the mips16, so we use $17 as the frame
1921 #define HARD_FRAME_POINTER_REGNUM \
1922 (TARGET_MIPS16 ? GP_REG_FIRST + 17 : GP_REG_FIRST + 30)
1924 /* Value should be nonzero if functions must have frame pointers.
1925 Zero means the frame pointer need not be set up (and parms
1926 may be accessed via the stack pointer) in functions that seem suitable.
1927 This is computed in `reload', in reload1.c. */
1928 #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1930 /* Base register for access to arguments of the function. */
1931 #define ARG_POINTER_REGNUM GP_REG_FIRST
1933 /* Fake register that holds the address on the stack of the
1934 current function's return address. */
1935 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG_NUM
1937 /* Register in which static-chain is passed to a function. */
1938 #define STATIC_CHAIN_REGNUM (GP_REG_FIRST + 2)
1940 /* If the structure value address is passed in a register, then
1941 `STRUCT_VALUE_REGNUM' should be the number of that register. */
1942 /* #define STRUCT_VALUE_REGNUM (GP_REG_FIRST + 4) */
1944 /* If the structure value address is not passed in a register, define
1945 `STRUCT_VALUE' as an expression returning an RTX for the place
1946 where the address is passed. If it returns 0, the address is
1947 passed as an "invisible" first argument. */
1948 #define STRUCT_VALUE 0
1950 /* Mips registers used in prologue/epilogue code when the stack frame
1951 is larger than 32K bytes. These registers must come from the
1952 scratch register set, and not used for passing and returning
1953 arguments and any other information used in the calling sequence
1954 (such as pic). Must start at 12, since t0/t3 are parameter passing
1955 registers in the 64 bit ABI. */
1957 #define MIPS_TEMP1_REGNUM (GP_REG_FIRST + 12)
1958 #define MIPS_TEMP2_REGNUM (GP_REG_FIRST + 13)
1960 /* Define this macro if it is as good or better to call a constant
1961 function address than to call an address kept in a register. */
1962 #define NO_FUNCTION_CSE 1
1964 /* Define this macro if it is as good or better for a function to
1965 call itself with an explicit address than to call an address
1966 kept in a register. */
1967 #define NO_RECURSIVE_FUNCTION_CSE 1
1969 /* The register number of the register used to address a table of
1970 static data addresses in memory. In some cases this register is
1971 defined by a processor's "application binary interface" (ABI).
1972 When this macro is defined, RTL is generated for this register
1973 once, as with the stack pointer and frame pointer registers. If
1974 this macro is not defined, it is up to the machine-dependent
1975 files to allocate such a register (if necessary). */
1976 #define PIC_OFFSET_TABLE_REGNUM (GP_REG_FIRST + 28)
1978 #define PIC_FUNCTION_ADDR_REGNUM (GP_REG_FIRST + 25)
1980 /* Define the classes of registers for register constraints in the
1981 machine description. Also define ranges of constants.
1983 One of the classes must always be named ALL_REGS and include all hard regs.
1984 If there is more than one class, another class must be named NO_REGS
1985 and contain no registers.
1987 The name GENERAL_REGS must be the name of a class (or an alias for
1988 another name such as ALL_REGS). This is the class of registers
1989 that is allowed by "g" or "r" in a register constraint.
1990 Also, registers outside this class are allocated only when
1991 instructions express preferences for them.
1993 The classes must be numbered in nondecreasing order; that is,
1994 a larger-numbered class must never be contained completely
1995 in a smaller-numbered class.
1997 For any two classes, it is very desirable that there be another
1998 class that represents their union. */
2002 NO_REGS, /* no registers in set */
2003 M16_NA_REGS, /* mips16 regs not used to pass args */
2004 M16_REGS, /* mips16 directly accessible registers */
2005 T_REG, /* mips16 T register ($24) */
2006 M16_T_REGS, /* mips16 registers plus T register */
2007 GR_REGS, /* integer registers */
2008 FP_REGS, /* floating point registers */
2009 HI_REG, /* hi register */
2010 LO_REG, /* lo register */
2011 HILO_REG, /* hilo register pair for 64 bit mode mult */
2012 MD_REGS, /* multiply/divide registers (hi/lo) */
2013 COP0_REGS, /* generic coprocessor classes */
2016 HI_AND_GR_REGS, /* union classes */
2024 ALL_COP_AND_GR_REGS,
2025 ST_REGS, /* status registers (fp status) */
2026 ALL_REGS, /* all registers */
2027 LIM_REG_CLASSES /* max value + 1 */
2030 #define N_REG_CLASSES (int) LIM_REG_CLASSES
2032 #define GENERAL_REGS GR_REGS
2034 /* An initializer containing the names of the register classes as C
2035 string constants. These names are used in writing some of the
2038 #define REG_CLASS_NAMES \
2051 /* coprocessor registers */ \
2057 "HILO_AND_GR_REGS", \
2059 "COP0_AND_GR_REGS", \
2060 "COP2_AND_GR_REGS", \
2061 "COP3_AND_GR_REGS", \
2063 "ALL_COP_AND_GR_REGS", \
2068 /* An initializer containing the contents of the register classes,
2069 as integers which are bit masks. The Nth integer specifies the
2070 contents of class N. The way the integer MASK is interpreted is
2071 that register R is in the class if `MASK & (1 << R)' is 1.
2073 When the machine has more than 32 registers, an integer does not
2074 suffice. Then the integers are replaced by sub-initializers,
2075 braced groupings containing several integers. Each
2076 sub-initializer must be suitable as an initializer for the type
2077 `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
2079 #define REG_CLASS_CONTENTS \
2081 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
2082 { 0x0003000c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 nonarg regs */\
2083 { 0x000300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 registers */ \
2084 { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 T register */ \
2085 { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* mips16 and T regs */ \
2086 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* integer registers */ \
2087 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* floating registers*/ \
2088 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* hi register */ \
2089 { 0x00000000, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, /* lo register */ \
2090 { 0x00000000, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, /* hilo register */ \
2091 { 0x00000000, 0x00000000, 0x00000003, 0x00000000, 0x00000000, 0x00000000 }, /* mul/div registers */ \
2092 { 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, /* cop0 registers */ \
2093 { 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, /* cop2 registers */ \
2094 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, /* cop3 registers */ \
2095 { 0xffffffff, 0x00000000, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, /* union classes */ \
2096 { 0xffffffff, 0x00000000, 0x00000002, 0x00000000, 0x00000000, 0x00000000 }, \
2097 { 0xffffffff, 0x00000000, 0x00000004, 0x00000000, 0x00000000, 0x00000000 }, \
2098 { 0x00000000, 0xffffffff, 0x00000001, 0x00000000, 0x00000000, 0x00000000 }, \
2099 { 0xffffffff, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000, 0x00000000 }, \
2100 { 0xffffffff, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff, 0x00000000 }, \
2101 { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0xffff0000, 0x0000ffff }, \
2102 { 0x00000000, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2103 { 0xffffffff, 0x00000000, 0xffff0000, 0xffffffff, 0xffffffff, 0x0000ffff }, \
2104 { 0x00000000, 0x00000000, 0x000007f8, 0x00000000, 0x00000000, 0x00000000 }, /* status registers */ \
2105 { 0xffffffff, 0xffffffff, 0xffff07ff, 0xffffffff, 0xffffffff, 0x0000ffff } /* all registers */ \
2109 /* A C expression whose value is a register class containing hard
2110 register REGNO. In general there is more that one such class;
2111 choose a class which is "minimal", meaning that no smaller class
2112 also contains the register. */
2114 extern const enum reg_class mips_regno_to_class[];
2116 #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
2118 /* A macro whose definition is the name of the class to which a
2119 valid base register must belong. A base register is one used in
2120 an address which is the register value plus a displacement. */
2122 #define BASE_REG_CLASS (TARGET_MIPS16 ? M16_REGS : GR_REGS)
2124 /* A macro whose definition is the name of the class to which a
2125 valid index register must belong. An index register is one used
2126 in an address where its value is either multiplied by a scale
2127 factor or added to another register (as well as added to a
2130 #define INDEX_REG_CLASS NO_REGS
2132 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows
2133 registers explicitly used in the rtl to be used as spill registers
2134 but prevents the compiler from extending the lifetime of these
2137 #define SMALL_REGISTER_CLASSES (TARGET_MIPS16)
2139 /* This macro is used later on in the file. */
2140 #define GR_REG_CLASS_P(CLASS) \
2141 ((CLASS) == GR_REGS || (CLASS) == M16_REGS || (CLASS) == T_REG \
2142 || (CLASS) == M16_T_REGS || (CLASS) == M16_NA_REGS)
2144 /* This macro is also used later on in the file. */
2145 #define COP_REG_CLASS_P(CLASS) \
2146 ((CLASS) == COP0_REGS || (CLASS) == COP2_REGS || (CLASS) == COP3_REGS)
2148 /* REG_ALLOC_ORDER is to order in which to allocate registers. This
2149 is the default value (allocate the registers in numeric order). We
2150 define it just so that we can override it for the mips16 target in
2151 ORDER_REGS_FOR_LOCAL_ALLOC. */
2153 #define REG_ALLOC_ORDER \
2154 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \
2155 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \
2156 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \
2157 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, \
2158 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
2159 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, \
2160 96, 97, 98, 99, 100,101,102,103,104,105,106,107,108,109,110,111, \
2161 112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127, \
2162 128,129,130,131,132,133,134,135,136,137,138,139,140,141,142,143, \
2163 144,145,146,147,148,149,150,151,152,153,154,155,156,157,158,159, \
2164 160,161,162,163,164,165,166,167,168,169,170,171,172,173,174,175 \
2167 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
2168 to be rearranged based on a particular function. On the mips16, we
2169 want to allocate $24 (T_REG) before other registers for
2170 instructions for which it is possible. */
2172 #define ORDER_REGS_FOR_LOCAL_ALLOC mips_order_regs_for_local_alloc ()
2174 /* REGISTER AND CONSTANT CLASSES */
2176 /* Get reg_class from a letter such as appears in the machine
2179 DEFINED REGISTER CLASSES:
2181 'd' General (aka integer) registers
2182 Normally this is GR_REGS, but in mips16 mode this is M16_REGS
2183 'y' General registers (in both mips16 and non mips16 mode)
2184 'e' mips16 non argument registers (M16_NA_REGS)
2185 't' mips16 temporary register ($24)
2186 'f' Floating point registers
2189 'x' Multiply/divide registers
2191 'z' FP Status register
2195 'b' All registers */
2197 extern enum reg_class mips_char_to_class[256];
2199 #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[(unsigned char)(C)]
2201 /* The letters I, J, K, L, M, N, O, and P in a register constraint
2202 string can be used to stand for particular ranges of immediate
2203 operands. This macro defines what the ranges are. C is the
2204 letter, and VALUE is a constant value. Return 1 if VALUE is
2205 in the range specified by C. */
2209 `I' is used for the range of constants an arithmetic insn can
2210 actually contain (16 bits signed integers).
2212 `J' is used for the range which is just zero (ie, $r0).
2214 `K' is used for the range of constants a logical insn can actually
2215 contain (16 bit zero-extended integers).
2217 `L' is used for the range of constants that be loaded with lui
2218 (ie, the bottom 16 bits are zero).
2220 `M' is used for the range of constants that take two words to load
2221 (ie, not matched by `I', `K', and `L').
2223 `N' is used for negative 16 bit constants other than -65536.
2225 `O' is a 15 bit signed integer.
2227 `P' is used for positive 16 bit constants. */
2229 #define SMALL_INT(X) ((unsigned HOST_WIDE_INT) (INTVAL (X) + 0x8000) < 0x10000)
2230 #define SMALL_INT_UNSIGNED(X) ((unsigned HOST_WIDE_INT) (INTVAL (X)) < 0x10000)
2232 #define CONST_OK_FOR_LETTER_P(VALUE, C) \
2233 ((C) == 'I' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x8000) < 0x10000) \
2234 : (C) == 'J' ? ((VALUE) == 0) \
2235 : (C) == 'K' ? ((unsigned HOST_WIDE_INT) (VALUE) < 0x10000) \
2236 : (C) == 'L' ? (((VALUE) & 0x0000ffff) == 0 \
2237 && (((VALUE) & ~2147483647) == 0 \
2238 || ((VALUE) & ~2147483647) == ~2147483647)) \
2239 : (C) == 'M' ? ((((VALUE) & ~0x0000ffff) != 0) \
2240 && (((VALUE) & ~0x0000ffff) != ~0x0000ffff) \
2241 && (((VALUE) & 0x0000ffff) != 0 \
2242 || (((VALUE) & ~2147483647) != 0 \
2243 && ((VALUE) & ~2147483647) != ~2147483647))) \
2244 : (C) == 'N' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0xffff) < 0xffff) \
2245 : (C) == 'O' ? ((unsigned HOST_WIDE_INT) ((VALUE) + 0x4000) < 0x8000) \
2246 : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & ~0x0000ffff) == 0)) \
2249 /* Similar, but for floating constants, and defining letters G and H.
2250 Here VALUE is the CONST_DOUBLE rtx itself. */
2254 'G' : Floating point 0 */
2256 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
2258 && (VALUE) == CONST0_RTX (GET_MODE (VALUE)))
2260 /* Letters in the range `Q' through `U' may be defined in a
2261 machine-dependent fashion to stand for arbitrary operand types.
2262 The machine description macro `EXTRA_CONSTRAINT' is passed the
2263 operand as its first argument and the constraint letter as its
2266 `Q' is for mips16 GP relative constants
2267 `R' is for memory references which take 1 word for the instruction.
2268 `T' is for memory addresses that can be used to load two words. */
2270 #define EXTRA_CONSTRAINT(OP,CODE) \
2271 (((CODE) == 'T') ? double_memory_operand (OP, GET_MODE (OP)) \
2272 : ((CODE) == 'Q') ? (GET_CODE (OP) == CONST \
2273 && mips16_gp_offset_p (OP)) \
2274 : (GET_CODE (OP) != MEM) ? FALSE \
2275 : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
2278 /* Given an rtx X being reloaded into a reg required to be
2279 in class CLASS, return the class of reg to actually use.
2280 In general this is just CLASS; but on some machines
2281 in some cases it is preferable to use a more restrictive class. */
2283 #define PREFERRED_RELOAD_CLASS(X,CLASS) \
2284 ((CLASS) != ALL_REGS \
2285 ? (! TARGET_MIPS16 \
2287 : ((CLASS) != GR_REGS \
2290 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
2291 || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
2292 ? (TARGET_SOFT_FLOAT \
2293 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2295 : ((GET_MODE_CLASS (GET_MODE (X)) == MODE_INT \
2296 || GET_MODE (X) == VOIDmode) \
2297 ? (TARGET_MIPS16 ? M16_REGS : GR_REGS) \
2300 /* Certain machines have the property that some registers cannot be
2301 copied to some other registers without using memory. Define this
2302 macro on those machines to be a C expression that is nonzero if
2303 objects of mode MODE in registers of CLASS1 can only be copied to
2304 registers of class CLASS2 by storing a register of CLASS1 into
2305 memory and loading that memory location into a register of CLASS2.
2307 Do not define this macro if its value would always be zero. */
2309 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \
2310 ((!TARGET_DEBUG_H_MODE \
2311 && GET_MODE_CLASS (MODE) == MODE_INT \
2312 && ((CLASS1 == FP_REGS && GR_REG_CLASS_P (CLASS2)) \
2313 || (GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS))) \
2314 || (TARGET_FLOAT64 && !TARGET_64BIT && (MODE) == DFmode \
2315 && ((GR_REG_CLASS_P (CLASS1) && CLASS2 == FP_REGS) \
2316 || (GR_REG_CLASS_P (CLASS2) && CLASS1 == FP_REGS))))
2318 /* The HI and LO registers can only be reloaded via the general
2319 registers. Condition code registers can only be loaded to the
2320 general registers, and from the floating point registers. */
2322 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \
2323 mips_secondary_reload_class (CLASS, MODE, X, 1)
2324 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \
2325 mips_secondary_reload_class (CLASS, MODE, X, 0)
2327 /* Return the maximum number of consecutive registers
2328 needed to represent mode MODE in a register of class CLASS. */
2330 #define CLASS_MAX_NREGS(CLASS, MODE) mips_class_max_nregs (CLASS, MODE)
2332 /* If defined, gives a class of registers that cannot be used as the
2333 operand of a SUBREG that changes the mode of the object illegally.
2335 In little-endian mode, the hi-lo registers are numbered backwards,
2336 so (subreg:SI (reg:DI hi) 0) gets the high word instead of the low
2339 Similarly, when using paired floating-point registers, the first
2340 register holds the low word, regardless of endianness. So in big
2341 endian mode, (subreg:SI (reg:DF $f0) 0) does not get the high word
2344 Also, loading a 32-bit value into a 64-bit floating-point register
2345 will not sign-extend the value, despite what LOAD_EXTEND_OP says.
2346 We can't allow 64-bit float registers to change from a 32-bit
2347 mode to a 64-bit mode. */
2349 #define CLASS_CANNOT_CHANGE_MODE \
2350 (TARGET_BIG_ENDIAN ? FP_REGS \
2351 : (TARGET_FLOAT64 ? HI_AND_FP_REGS : HI_REG))
2353 /* Defines illegal mode changes for CLASS_CANNOT_CHANGE_MODE. */
2355 #define CLASS_CANNOT_CHANGE_MODE_P(FROM,TO) \
2356 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO))
2358 /* Stack layout; function entry, exit and calling. */
2360 /* Define this if pushing a word on the stack
2361 makes the stack pointer a smaller address. */
2362 #define STACK_GROWS_DOWNWARD
2364 /* Define this if the nominal address of the stack frame
2365 is at the high-address end of the local variables;
2366 that is, each additional local variable allocated
2367 goes at a more negative offset in the frame. */
2368 /* #define FRAME_GROWS_DOWNWARD */
2370 /* Offset within stack frame to start allocating local variables at.
2371 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
2372 first local allocated. Otherwise, it is the offset to the BEGINNING
2373 of the first local allocated. */
2374 #define STARTING_FRAME_OFFSET \
2375 (current_function_outgoing_args_size \
2376 + (TARGET_ABICALLS ? MIPS_STACK_ALIGN (UNITS_PER_WORD) : 0))
2378 /* Offset from the stack pointer register to an item dynamically
2379 allocated on the stack, e.g., by `alloca'.
2381 The default value for this macro is `STACK_POINTER_OFFSET' plus the
2382 length of the outgoing arguments. The default is correct for most
2383 machines. See `function.c' for details.
2385 The MIPS ABI states that functions which dynamically allocate the
2386 stack must not have 0 for STACK_DYNAMIC_OFFSET, since it looks like
2387 we are trying to create a second frame pointer to the function, so
2388 allocate some stack space to make it happy.
2390 However, the linker currently complains about linking any code that
2391 dynamically allocates stack space, and there seems to be a bug in
2392 STACK_DYNAMIC_OFFSET, so don't define this right now. */
2395 #define STACK_DYNAMIC_OFFSET(FUNDECL) \
2396 ((current_function_outgoing_args_size == 0 && current_function_calls_alloca) \
2397 ? 4*UNITS_PER_WORD \
2398 : current_function_outgoing_args_size)
2401 /* The return address for the current frame is in r31 if this is a leaf
2402 function. Otherwise, it is on the stack. It is at a variable offset
2403 from sp/fp/ap, so we define a fake hard register rap which is a
2404 poiner to the return address on the stack. This always gets eliminated
2405 during reload to be either the frame pointer or the stack pointer plus
2408 /* ??? This definition fails for leaf functions. There is currently no
2409 general solution for this problem. */
2411 /* ??? There appears to be no way to get the return address of any previous
2412 frame except by disassembling instructions in the prologue/epilogue.
2413 So currently we support only the current frame. */
2415 #define RETURN_ADDR_RTX(count, frame) \
2417 ? (leaf_function_p () \
2418 ? gen_rtx_REG (Pmode, GP_REG_FIRST + 31) \
2419 : gen_rtx_MEM (Pmode, gen_rtx_REG (Pmode, \
2420 RETURN_ADDRESS_POINTER_REGNUM))) \
2423 /* Since the mips16 ISA mode is encoded in the least-significant bit
2424 of the address, mask it off return addresses for purposes of
2425 finding exception handling regions. */
2427 #define MASK_RETURN_ADDR GEN_INT (-2)
2429 /* Similarly, don't use the least-significant bit to tell pointers to
2430 code from vtable index. */
2432 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta
2434 /* If defined, this macro specifies a table of register pairs used to
2435 eliminate unneeded registers that point into the stack frame. If
2436 it is not defined, the only elimination attempted by the compiler
2437 is to replace references to the frame pointer with references to
2440 The definition of this macro is a list of structure
2441 initializations, each of which specifies an original and
2442 replacement register.
2444 On some machines, the position of the argument pointer is not
2445 known until the compilation is completed. In such a case, a
2446 separate hard register must be used for the argument pointer.
2447 This register can be eliminated by replacing it with either the
2448 frame pointer or the argument pointer, depending on whether or not
2449 the frame pointer has been eliminated.
2451 In this case, you might specify:
2452 #define ELIMINABLE_REGS \
2453 {{ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2454 {ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \
2455 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}}
2457 Note that the elimination of the argument pointer with the stack
2458 pointer is specified first since that is the preferred elimination.
2460 The eliminations to $17 are only used on the mips16. See the
2461 definition of HARD_FRAME_POINTER_REGNUM. */
2463 #define ELIMINABLE_REGS \
2464 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2465 { ARG_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2466 { ARG_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2467 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2468 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2469 { RETURN_ADDRESS_POINTER_REGNUM, GP_REG_FIRST + 17}, \
2470 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
2471 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 30}, \
2472 { FRAME_POINTER_REGNUM, GP_REG_FIRST + 17}}
2474 /* A C expression that returns nonzero if the compiler is allowed to
2475 try to replace register number FROM-REG with register number
2476 TO-REG. This macro need only be defined if `ELIMINABLE_REGS' is
2477 defined, and will usually be the constant 1, since most of the
2478 cases preventing register elimination are things that the compiler
2479 already knows about.
2481 When not in mips16 and mips64, we can always eliminate to the
2482 frame pointer. We can eliminate to the stack pointer unless
2483 a frame pointer is needed. In mips16 mode, we need a frame
2484 pointer for a large frame; otherwise, reload may be unable
2485 to compute the address of a local variable, since there is
2486 no way to add a large constant to the stack pointer
2487 without using a temporary register.
2489 In mips16, for some instructions (eg lwu), we can't eliminate the
2490 frame pointer for the stack pointer. These instructions are
2491 only generated in TARGET_64BIT mode.
2494 #define CAN_ELIMINATE(FROM, TO) \
2495 (((FROM) == RETURN_ADDRESS_POINTER_REGNUM \
2496 && (((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed) \
2497 || (TO) == HARD_FRAME_POINTER_REGNUM)) \
2498 || ((FROM) != RETURN_ADDRESS_POINTER_REGNUM \
2499 && ((TO) == HARD_FRAME_POINTER_REGNUM \
2500 || ((TO) == STACK_POINTER_REGNUM && ! frame_pointer_needed \
2501 && ! (TARGET_MIPS16 && TARGET_64BIT) \
2502 && (! TARGET_MIPS16 \
2503 || compute_frame_size (get_frame_size ()) < 32768)))))
2505 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
2506 (OFFSET) = mips_initial_elimination_offset ((FROM), (TO))
2508 /* If we generate an insn to push BYTES bytes,
2509 this says how many the stack pointer really advances by.
2510 On the VAX, sp@- in a byte insn really pushes a word. */
2512 /* #define PUSH_ROUNDING(BYTES) 0 */
2514 /* If defined, the maximum amount of space required for outgoing
2515 arguments will be computed and placed into the variable
2516 `current_function_outgoing_args_size'. No space will be pushed
2517 onto the stack for each call; instead, the function prologue
2518 should increase the stack frame size by this amount.
2520 It is not proper to define both `PUSH_ROUNDING' and
2521 `ACCUMULATE_OUTGOING_ARGS'. */
2522 #define ACCUMULATE_OUTGOING_ARGS 1
2524 /* Offset from the argument pointer register to the first argument's
2525 address. On some machines it may depend on the data type of the
2528 If `ARGS_GROW_DOWNWARD', this is the offset to the location above
2529 the first argument's address.
2531 On the MIPS, we must skip the first argument position if we are
2532 returning a structure or a union, to account for its address being
2533 passed in $4. However, at the current time, this produces a compiler
2534 that can't bootstrap, so comment it out for now. */
2537 #define FIRST_PARM_OFFSET(FNDECL) \
2539 && TREE_TYPE (FNDECL) != 0 \
2540 && TREE_TYPE (TREE_TYPE (FNDECL)) != 0 \
2541 && (TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == RECORD_TYPE \
2542 || TREE_CODE (TREE_TYPE (TREE_TYPE (FNDECL))) == UNION_TYPE) \
2546 #define FIRST_PARM_OFFSET(FNDECL) 0
2549 /* When a parameter is passed in a register, stack space is still
2550 allocated for it. For the MIPS, stack space must be allocated, cf
2551 Asm Lang Prog Guide page 7-8.
2553 BEWARE that some space is also allocated for non existing arguments
2554 in register. In case an argument list is of form GF used registers
2555 are a0 (a2,a3), but we should push over a1... */
2557 #define REG_PARM_STACK_SPACE(FNDECL) \
2558 ((mips_abi == ABI_32 || mips_abi == ABI_O64) \
2559 ? (MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD) - FIRST_PARM_OFFSET (FNDECL) \
2562 /* Define this if it is the responsibility of the caller to
2563 allocate the area reserved for arguments passed in registers.
2564 If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
2565 of this macro is to determine whether the space is included in
2566 `current_function_outgoing_args_size'. */
2567 #define OUTGOING_REG_PARM_STACK_SPACE
2569 #define STACK_BOUNDARY \
2570 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2573 /* Make sure 4 words are always allocated on the stack. */
2575 #ifndef STACK_ARGS_ADJUST
2576 #define STACK_ARGS_ADJUST(SIZE) \
2578 if (SIZE.constant < 4 * UNITS_PER_WORD) \
2579 SIZE.constant = 4 * UNITS_PER_WORD; \
2584 /* A C expression that should indicate the number of bytes of its
2585 own arguments that a function pops on returning, or 0
2586 if the function pops no arguments and the caller must therefore
2587 pop them all after the function returns.
2589 FUNDECL is the declaration node of the function (as a tree).
2591 FUNTYPE is a C variable whose value is a tree node that
2592 describes the function in question. Normally it is a node of
2593 type `FUNCTION_TYPE' that describes the data type of the function.
2594 From this it is possible to obtain the data types of the value
2595 and arguments (if known).
2597 When a call to a library function is being considered, FUNTYPE
2598 will contain an identifier node for the library function. Thus,
2599 if you need to distinguish among various library functions, you
2600 can do so by their names. Note that "library function" in this
2601 context means a function used to perform arithmetic, whose name
2602 is known specially in the compiler and was not mentioned in the
2603 C code being compiled.
2605 STACK-SIZE is the number of bytes of arguments passed on the
2606 stack. If a variable number of bytes is passed, it is zero, and
2607 argument popping will always be the responsibility of the
2608 calling function. */
2610 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0
2613 /* Symbolic macros for the registers used to return integer and floating
2616 #define GP_RETURN (GP_REG_FIRST + 2)
2617 #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
2619 #define MAX_ARGS_IN_REGISTERS \
2620 ((mips_abi == ABI_32 || mips_abi == ABI_O64) ? 4 : 8)
2622 /* Largest possible value of MAX_ARGS_IN_REGISTERS. */
2624 #define BIGGEST_MAX_ARGS_IN_REGISTERS 8
2626 /* Symbolic macros for the first/last argument registers. */
2628 #define GP_ARG_FIRST (GP_REG_FIRST + 4)
2629 #define GP_ARG_LAST (GP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2630 #define FP_ARG_FIRST (FP_REG_FIRST + 12)
2631 #define FP_ARG_LAST (FP_ARG_FIRST + MAX_ARGS_IN_REGISTERS - 1)
2633 /* Define how to find the value returned by a library function
2634 assuming the value has mode MODE. Because we define
2635 PROMOTE_FUNCTION_RETURN, we must promote the mode just as
2636 PROMOTE_MODE does. */
2638 #define LIBCALL_VALUE(MODE) \
2639 mips_function_value (NULL_TREE, NULL, (MODE))
2641 /* Define how to find the value returned by a function.
2642 VALTYPE is the data type of the value (as a tree).
2643 If the precise function being called is known, FUNC is its FUNCTION_DECL;
2644 otherwise, FUNC is 0. */
2646 #define FUNCTION_VALUE(VALTYPE, FUNC) \
2647 mips_function_value ((VALTYPE), (FUNC), VOIDmode)
2649 /* 1 if N is a possible register number for a function value.
2650 On the MIPS, R2 R3 and F0 F2 are the only register thus used.
2651 Currently, R2 and F0 are only implemented here (C has no complex type) */
2653 #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
2655 /* 1 if N is a possible register number for function argument passing.
2656 We have no FP argument registers when soft-float. When FP registers
2657 are 32 bits, we can't directly reference the odd numbered ones. */
2659 #define FUNCTION_ARG_REGNO_P(N) \
2660 ((IN_RANGE((N), GP_ARG_FIRST, GP_ARG_LAST) \
2661 || (IN_RANGE((N), FP_ARG_FIRST, FP_ARG_LAST) \
2662 && ((N) % FP_INC == 0) && mips_abi != ABI_O64)) \
2665 /* A C expression which can inhibit the returning of certain function
2666 values in registers, based on the type of value. A nonzero value says
2667 to return the function value in memory, just as large structures are
2668 always returned. Here TYPE will be a C expression of type
2669 `tree', representing the data type of the value.
2671 Note that values of mode `BLKmode' must be explicitly
2672 handled by this macro. Also, the option `-fpcc-struct-return'
2673 takes effect regardless of this macro. On most systems, it is
2674 possible to leave the macro undefined; this causes a default
2675 definition to be used, whose value is the constant 1 for BLKmode
2676 values, and 0 otherwise.
2678 GCC normally converts 1 byte structures into chars, 2 byte
2679 structs into shorts, and 4 byte structs into ints, and returns
2680 them this way. Defining the following macro overrides this,
2681 to give us MIPS cc compatibility. */
2683 #define RETURN_IN_MEMORY(TYPE) \
2684 mips_return_in_memory (TYPE)
2686 #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
2687 (PRETEND_SIZE) = mips_setup_incoming_varargs (&(CUM), (MODE), \
2690 #define STRICT_ARGUMENT_NAMING (mips_abi != ABI_32 && mips_abi != ABI_O64)
2692 /* Define a data type for recording info about an argument list
2693 during the scan of that argument list. This data type should
2694 hold all necessary information about the function itself
2695 and about the args processed so far, enough to enable macros
2696 such as FUNCTION_ARG to determine where the next arg should go.
2698 This structure has to cope with two different argument allocation
2699 schemes. Most MIPS ABIs view the arguments as a struct, of which the
2700 first N words go in registers and the rest go on the stack. If I < N,
2701 the Ith word might go in Ith integer argument register or the
2702 Ith floating-point one. In some cases, it has to go in both (see
2703 function_arg). For these ABIs, we only need to remember the number
2704 of words passed so far.
2706 The EABI instead allocates the integer and floating-point arguments
2707 separately. The first N words of FP arguments go in FP registers,
2708 the rest go on the stack. Likewise, the first N words of the other
2709 arguments go in integer registers, and the rest go on the stack. We
2710 need to maintain three counts: the number of integer registers used,
2711 the number of floating-point registers used, and the number of words
2712 passed on the stack.
2714 We could keep separate information for the two ABIs (a word count for
2715 the standard ABIs, and three separate counts for the EABI). But it
2716 seems simpler to view the standard ABIs as forms of EABI that do not
2717 allocate floating-point registers.
2719 So for the standard ABIs, the first N words are allocated to integer
2720 registers, and function_arg decides on an argument-by-argument basis
2721 whether that argument should really go in an integer register, or in
2722 a floating-point one. */
2724 typedef struct mips_args {
2725 /* Always true for varargs functions. Otherwise true if at least
2726 one argument has been passed in an integer register. */
2729 /* The number of arguments seen so far. */
2730 unsigned int arg_number;
2732 /* For EABI, the number of integer registers used so far. For other
2733 ABIs, the number of words passed in registers (whether integer
2734 or floating-point). */
2735 unsigned int num_gprs;
2737 /* For EABI, the number of floating-point registers used so far. */
2738 unsigned int num_fprs;
2740 /* The number of words passed on the stack. */
2741 unsigned int stack_words;
2743 /* On the mips16, we need to keep track of which floating point
2744 arguments were passed in general registers, but would have been
2745 passed in the FP regs if this were a 32 bit function, so that we
2746 can move them to the FP regs if we wind up calling a 32 bit
2747 function. We record this information in fp_code, encoded in base
2748 four. A zero digit means no floating point argument, a one digit
2749 means an SFmode argument, and a two digit means a DFmode argument,
2750 and a three digit is not used. The low order digit is the first
2751 argument. Thus 6 == 1 * 4 + 2 means a DFmode argument followed by
2752 an SFmode argument. ??? A more sophisticated approach will be
2753 needed if MIPS_ABI != ABI_32. */
2756 /* True if the function has a prototype. */
2759 /* When a structure does not take up a full register, the argument
2760 should sometimes be shifted left so that it occupies the high part
2761 of the register. These two fields describe an array of ashl
2762 patterns for doing this. See function_arg_advance, which creates
2763 the shift patterns, and function_arg, which returns them when given
2764 a VOIDmode argument. */
2765 unsigned int num_adjusts;
2766 rtx adjust[BIGGEST_MAX_ARGS_IN_REGISTERS];
2769 /* Initialize a variable CUM of type CUMULATIVE_ARGS
2770 for a call to a function whose data type is FNTYPE.
2771 For a library call, FNTYPE is 0.
2775 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT) \
2776 init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
2778 /* Update the data in CUM to advance over an argument
2779 of mode MODE and data type TYPE.
2780 (TYPE is null for libcalls where that information may not be available.) */
2782 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
2783 function_arg_advance (&CUM, MODE, TYPE, NAMED)
2785 /* Determine where to put an argument to a function.
2786 Value is zero to push the argument on the stack,
2787 or a hard register in which to store the argument.
2789 MODE is the argument's machine mode.
2790 TYPE is the data type of the argument (as a tree).
2791 This is null for libcalls where that information may
2793 CUM is a variable of type CUMULATIVE_ARGS which gives info about
2794 the preceding args and about the function being called.
2795 NAMED is nonzero if this argument is a named parameter
2796 (otherwise it is an extra parameter matching an ellipsis). */
2798 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
2799 function_arg( &CUM, MODE, TYPE, NAMED)
2801 /* For an arg passed partly in registers and partly in memory,
2802 this is the number of registers used.
2803 For args passed entirely in registers or entirely in memory, zero. */
2805 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
2806 function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
2808 /* If defined, a C expression that gives the alignment boundary, in
2809 bits, of an argument with the specified mode and type. If it is
2810 not defined, `PARM_BOUNDARY' is used for all arguments. */
2812 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
2814 ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
2816 : TYPE_ALIGN(TYPE)) \
2817 : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
2819 : GET_MODE_ALIGNMENT(MODE)))
2821 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \
2822 function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED)
2824 #define FUNCTION_ARG_PADDING(MODE, TYPE) \
2825 (! BYTES_BIG_ENDIAN \
2827 : (((MODE) == BLKmode \
2828 ? ((TYPE) && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2829 && int_size_in_bytes (TYPE) < (PARM_BOUNDARY / BITS_PER_UNIT))\
2830 : (GET_MODE_BITSIZE (MODE) < PARM_BOUNDARY \
2831 && (mips_abi == ABI_32 \
2832 || mips_abi == ABI_O64 \
2833 || mips_abi == ABI_EABI \
2834 || GET_MODE_CLASS (MODE) == MODE_INT))) \
2835 ? downward : upward))
2837 #define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \
2838 (mips_abi == ABI_EABI && (NAMED) \
2839 && FUNCTION_ARG_PASS_BY_REFERENCE (CUM, MODE, TYPE, NAMED))
2841 /* Modified version of the macro in expr.h. */
2842 #define MUST_PASS_IN_STACK(MODE,TYPE) \
2844 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \
2845 || TREE_ADDRESSABLE (TYPE) \
2846 || ((MODE) == BLKmode \
2847 && mips_abi != ABI_32 && mips_abi != ABI_O64 \
2848 && ! ((TYPE) != 0 && TREE_CODE (TYPE_SIZE (TYPE)) == INTEGER_CST \
2849 && 0 == (int_size_in_bytes (TYPE) \
2850 % (PARM_BOUNDARY / BITS_PER_UNIT))) \
2851 && (FUNCTION_ARG_PADDING (MODE, TYPE) \
2852 == (BYTES_BIG_ENDIAN ? upward : downward)))))
2854 /* True if using EABI and varargs can be passed in floating-point
2855 registers. Under these conditions, we need a more complex form
2856 of va_list, which tracks GPR, FPR and stack arguments separately. */
2857 #define EABI_FLOAT_VARARGS_P \
2858 (mips_abi == ABI_EABI && UNITS_PER_FPVALUE >= UNITS_PER_DOUBLE)
2861 /* Tell prologue and epilogue if register REGNO should be saved / restored. */
2863 #define MUST_SAVE_REGISTER(regno) \
2864 ((regs_ever_live[regno] && !call_used_regs[regno]) \
2865 || (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) \
2866 || (regno == (GP_REG_FIRST + 31) && regs_ever_live[GP_REG_FIRST + 31]))
2868 /* Treat LOC as a byte offset from the stack pointer and round it up
2869 to the next fully-aligned offset. */
2870 #define MIPS_STACK_ALIGN(LOC) \
2871 ((mips_abi == ABI_32 || mips_abi == ABI_O64 || mips_abi == ABI_EABI) \
2872 ? ((LOC) + 7) & ~7 \
2873 : ((LOC) + 15) & ~15)
2876 /* Define the `__builtin_va_list' type for the ABI. */
2877 #define BUILD_VA_LIST_TYPE(VALIST) \
2878 (VALIST) = mips_build_va_list ()
2880 /* Implement `va_start' for varargs and stdarg. */
2881 #define EXPAND_BUILTIN_VA_START(valist, nextarg) \
2882 mips_va_start (valist, nextarg)
2884 /* Implement `va_arg'. */
2885 #define EXPAND_BUILTIN_VA_ARG(valist, type) \
2886 mips_va_arg (valist, type)
2888 /* Output assembler code to FILE to increment profiler label # LABELNO
2889 for profiling a function entry. */
2891 #define FUNCTION_PROFILER(FILE, LABELNO) \
2893 if (TARGET_MIPS16) \
2894 sorry ("mips16 function profiling"); \
2895 fprintf (FILE, "\t.set\tnoat\n"); \
2896 fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
2897 reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
2899 "\t%s\t%s,%s,%d\t\t# _mcount pops 2 words from stack\n", \
2900 TARGET_64BIT ? "dsubu" : "subu", \
2901 reg_names[STACK_POINTER_REGNUM], \
2902 reg_names[STACK_POINTER_REGNUM], \
2903 Pmode == DImode ? 16 : 8); \
2904 fprintf (FILE, "\tjal\t_mcount\n"); \
2905 fprintf (FILE, "\t.set\tat\n"); \
2908 /* Define this macro if the code for function profiling should come
2909 before the function prologue. Normally, the profiling code comes
2912 /* #define PROFILE_BEFORE_PROLOGUE */
2914 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
2915 the stack pointer does not matter. The value is tested only in
2916 functions that have frame pointers.
2917 No definition is equivalent to always zero. */
2919 #define EXIT_IGNORE_STACK 1
2922 /* A C statement to output, on the stream FILE, assembler code for a
2923 block of data that contains the constant parts of a trampoline.
2924 This code should not include a label--the label is taken care of
2927 #define TRAMPOLINE_TEMPLATE(STREAM) \
2929 fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
2930 fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
2931 fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
2932 if (Pmode == DImode) \
2934 fprintf (STREAM, "\t.word\t0xdfe30014\t\t# ld $3,20($31)\n"); \
2935 fprintf (STREAM, "\t.word\t0xdfe2001c\t\t# ld $2,28($31)\n"); \
2939 fprintf (STREAM, "\t.word\t0x8fe30014\t\t# lw $3,20($31)\n"); \
2940 fprintf (STREAM, "\t.word\t0x8fe20018\t\t# lw $2,24($31)\n"); \
2942 fprintf (STREAM, "\t.word\t0x0060c821\t\t# move $25,$3 (abicalls)\n"); \
2943 fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
2944 fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
2945 if (Pmode == DImode) \
2947 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <function address>\n"); \
2948 fprintf (STREAM, "\t.dword\t0x00000000\t\t# <static chain value>\n"); \
2952 fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
2953 fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
2957 /* A C expression for the size in bytes of the trampoline, as an
2960 #define TRAMPOLINE_SIZE (32 + (Pmode == DImode ? 16 : 8))
2962 /* Alignment required for trampolines, in bits. */
2964 #define TRAMPOLINE_ALIGNMENT (Pmode == DImode ? 64 : 32)
2966 /* INITIALIZE_TRAMPOLINE calls this library function to flush
2967 program and data caches. */
2969 #ifndef CACHE_FLUSH_FUNC
2970 #define CACHE_FLUSH_FUNC "_flush_cache"
2973 /* A C statement to initialize the variable parts of a trampoline.
2974 ADDR is an RTX for the address of the trampoline; FNADDR is an
2975 RTX for the address of the nested function; STATIC_CHAIN is an
2976 RTX for the static chain value that should be passed to the
2977 function when it is called. */
2979 #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
2982 if (Pmode == DImode) \
2984 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 32)), FUNC); \
2985 emit_move_insn (gen_rtx_MEM (DImode, plus_constant (addr, 40)), CHAIN);\
2989 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 32)), FUNC); \
2990 emit_move_insn (gen_rtx_MEM (SImode, plus_constant (addr, 36)), CHAIN);\
2993 /* Flush both caches. We need to flush the data cache in case \
2994 the system has a write-back cache. */ \
2995 /* ??? Should check the return value for errors. */ \
2996 if (mips_cache_flush_func && mips_cache_flush_func[0]) \
2997 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, mips_cache_flush_func), \
2998 0, VOIDmode, 3, addr, Pmode, \
2999 GEN_INT (TRAMPOLINE_SIZE), TYPE_MODE (integer_type_node),\
3000 GEN_INT (3), TYPE_MODE (integer_type_node)); \
3003 /* Addressing modes, and classification of registers for them. */
3005 /* #define HAVE_POST_INCREMENT 0 */
3006 /* #define HAVE_POST_DECREMENT 0 */
3008 /* #define HAVE_PRE_DECREMENT 0 */
3009 /* #define HAVE_PRE_INCREMENT 0 */
3011 /* These assume that REGNO is a hard or pseudo reg number.
3012 They give nonzero only if REGNO is a hard reg of the suitable class
3013 or a pseudo reg currently allocated to a suitable hard reg.
3014 These definitions are NOT overridden anywhere. */
3016 #define BASE_REG_P(regno, mode) \
3018 ? (M16_REG_P (regno) \
3019 || (regno) == FRAME_POINTER_REGNUM \
3020 || (regno) == ARG_POINTER_REGNUM \
3021 || ((regno) == STACK_POINTER_REGNUM \
3022 && (GET_MODE_SIZE (mode) == 4 \
3023 || GET_MODE_SIZE (mode) == 8))) \
3026 #define GP_REG_OR_PSEUDO_STRICT_P(regno, mode) \
3027 BASE_REG_P((regno < FIRST_PSEUDO_REGISTER) ? (int) regno : reg_renumber[regno], \
3030 #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno, mode) \
3031 (((regno) >= FIRST_PSEUDO_REGISTER) || (BASE_REG_P ((regno), (mode))))
3033 #define REGNO_OK_FOR_INDEX_P(regno) 0
3034 #define REGNO_MODE_OK_FOR_BASE_P(regno, mode) \
3035 GP_REG_OR_PSEUDO_STRICT_P ((regno), (mode))
3037 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
3038 and check its validity for a certain class.
3039 We have two alternate definitions for each of them.
3040 The usual definition accepts all pseudo regs; the other rejects them all.
3041 The symbol REG_OK_STRICT causes the latter definition to be used.
3043 Most source files want to accept pseudo regs in the hope that
3044 they will get allocated to the class that the insn wants them to be in.
3045 Some source files that are used after register allocation
3046 need to be strict. */
3048 #ifndef REG_OK_STRICT
3049 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3050 mips_reg_mode_ok_for_base_p (X, MODE, 0)
3052 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \
3053 mips_reg_mode_ok_for_base_p (X, MODE, 1)
3056 #define REG_OK_FOR_INDEX_P(X) 0
3059 /* Maximum number of registers that can appear in a valid memory address. */
3061 #define MAX_REGS_PER_ADDRESS 1
3063 /* A C compound statement with a conditional `goto LABEL;' executed
3064 if X (an RTX) is a legitimate memory address on the target
3065 machine for a memory operand of mode MODE. */
3068 #define GO_PRINTF(x) fprintf(stderr, (x))
3069 #define GO_PRINTF2(x,y) fprintf(stderr, (x), (y))
3070 #define GO_DEBUG_RTX(x) debug_rtx(x)
3073 #define GO_PRINTF(x)
3074 #define GO_PRINTF2(x,y)
3075 #define GO_DEBUG_RTX(x)
3078 #ifdef REG_OK_STRICT
3079 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3081 if (mips_legitimate_address_p (MODE, X, 1)) \
3085 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
3087 if (mips_legitimate_address_p (MODE, X, 0)) \
3092 /* A C expression that is 1 if the RTX X is a constant which is a
3093 valid address. This is defined to be the same as `CONSTANT_P (X)',
3094 but rejecting CONST_DOUBLE. */
3095 /* When pic, we must reject addresses of the form symbol+large int.
3096 This is because an instruction `sw $4,s+70000' needs to be converted
3097 by the assembler to `lw $at,s($gp);sw $4,70000($at)'. Normally the
3098 assembler would use $at as a temp to load in the large offset. In this
3099 case $at is already in use. We convert such problem addresses to
3100 `la $5,s;sw $4,70000($5)' via LEGITIMIZE_ADDRESS. */
3101 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them
3102 when !TARGET_GAS. */
3103 /* We should be rejecting everything but const addresses. */
3104 #define CONSTANT_ADDRESS_P(X) \
3105 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
3106 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
3107 || (GET_CODE (X) == CONST \
3108 && ! (flag_pic && pic_address_needs_scratch (X)) \
3110 && (mips_abi != ABI_N32 \
3111 && mips_abi != ABI_64)))
3114 /* Define this, so that when PIC, reload won't try to reload invalid
3115 addresses which require two reload registers. */
3117 #define LEGITIMATE_PIC_OPERAND_P(X) (! pic_address_needs_scratch (X))
3119 /* Nonzero if the constant value X is a legitimate general operand.
3120 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
3122 At present, GAS doesn't understand li.[sd], so don't allow it
3123 to be generated at present. Also, the MIPS assembler does not
3124 grok li.d Infinity. */
3126 /* ??? SGI Irix 6 assembler fails for CONST address, so reject them.
3127 Note that the Irix 6 assembler problem may already be fixed.
3128 Note also that the GET_CODE (X) == CONST test catches the mips16
3129 gp pseudo reg (see mips16_gp_pseudo_reg) deciding it is not
3130 a LEGITIMATE_CONSTANT. If we ever want mips16 and ABI_N32 or
3131 ABI_64 to work together, we'll need to fix this. */
3132 #define LEGITIMATE_CONSTANT_P(X) \
3133 ((GET_CODE (X) != CONST_DOUBLE \
3134 || mips_const_double_ok (X, GET_MODE (X))) \
3135 && ! (GET_CODE (X) == CONST \
3137 && (mips_abi == ABI_N32 \
3138 || mips_abi == ABI_64)) \
3139 && (! TARGET_MIPS16 || mips16_constant (X, GET_MODE (X), 0, 0)))
3141 /* A C compound statement that attempts to replace X with a valid
3142 memory address for an operand of mode MODE. WIN will be a C
3143 statement label elsewhere in the code; the macro definition may
3146 GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
3148 to avoid further processing if the address has become legitimate.
3150 X will always be the result of a call to `break_out_memory_refs',
3151 and OLDX will be the operand that was given to that function to
3154 The code generated by this macro should not alter the
3155 substructure of X. If it transforms X into a more legitimate
3156 form, it should assign X (which will always be a C variable) a
3159 It is not necessary for this macro to come up with a legitimate
3160 address. The compiler has standard ways of doing so in all
3161 cases. In fact, it is safe for this macro to do nothing. But
3162 often a machine-dependent strategy can generate better code.
3164 For the MIPS, transform:
3166 memory(X + <large int>)
3170 Y = <large int> & ~0x7fff;
3172 memory (Z + (<large int> & 0x7fff));
3174 This is for CSE to find several similar references, and only use one Z.
3176 When PIC, convert addresses of the form memory (symbol+large int) to
3177 memory (reg+large int). */
3180 #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
3182 register rtx xinsn = (X); \
3184 if (TARGET_DEBUG_B_MODE) \
3186 GO_PRINTF ("\n========== LEGITIMIZE_ADDRESS\n"); \
3187 GO_DEBUG_RTX (xinsn); \
3190 if (mips_split_addresses && mips_check_split (X, MODE)) \
3192 /* ??? Is this ever executed? */ \
3193 X = gen_rtx_LO_SUM (Pmode, \
3194 copy_to_mode_reg (Pmode, \
3195 gen_rtx (HIGH, Pmode, X)), \
3200 if (GET_CODE (xinsn) == CONST \
3201 && ((flag_pic && pic_address_needs_scratch (xinsn)) \
3202 /* ??? SGI's Irix 6 assembler can't handle CONST. */ \
3204 && (mips_abi == ABI_N32 \
3205 || mips_abi == ABI_64)))) \
3207 rtx ptr_reg = gen_reg_rtx (Pmode); \
3208 rtx constant = XEXP (XEXP (xinsn, 0), 1); \
3210 emit_move_insn (ptr_reg, XEXP (XEXP (xinsn, 0), 0)); \
3212 X = gen_rtx_PLUS (Pmode, ptr_reg, constant); \
3213 if (SMALL_INT (constant)) \
3215 /* Otherwise we fall through so the code below will fix the \
3220 if (GET_CODE (xinsn) == PLUS) \
3222 register rtx xplus0 = XEXP (xinsn, 0); \
3223 register rtx xplus1 = XEXP (xinsn, 1); \
3224 register enum rtx_code code0 = GET_CODE (xplus0); \
3225 register enum rtx_code code1 = GET_CODE (xplus1); \
3227 if (code0 != REG && code1 == REG) \
3229 xplus0 = XEXP (xinsn, 1); \
3230 xplus1 = XEXP (xinsn, 0); \
3231 code0 = GET_CODE (xplus0); \
3232 code1 = GET_CODE (xplus1); \
3235 if (code0 == REG && REG_MODE_OK_FOR_BASE_P (xplus0, MODE) \
3236 && code1 == CONST_INT && !SMALL_INT (xplus1)) \
3238 rtx int_reg = gen_reg_rtx (Pmode); \
3239 rtx ptr_reg = gen_reg_rtx (Pmode); \
3241 emit_move_insn (int_reg, \
3242 GEN_INT (INTVAL (xplus1) & ~ 0x7fff)); \
3244 emit_insn (gen_rtx_SET (VOIDmode, \
3246 gen_rtx_PLUS (Pmode, xplus0, int_reg))); \
3248 X = plus_constant (ptr_reg, INTVAL (xplus1) & 0x7fff); \
3253 if (TARGET_DEBUG_B_MODE) \
3254 GO_PRINTF ("LEGITIMIZE_ADDRESS could not fix.\n"); \
3258 /* A C statement or compound statement with a conditional `goto
3259 LABEL;' executed if memory address X (an RTX) can have different
3260 meanings depending on the machine mode of the memory reference it
3263 Autoincrement and autodecrement addresses typically have
3264 mode-dependent effects because the amount of the increment or
3265 decrement is the size of the operand being addressed. Some
3266 machines have other mode-dependent addresses. Many RISC machines
3267 have no mode-dependent addresses.
3269 You may assume that ADDR is a valid address for the machine. */
3271 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
3273 /* This handles the magic '..CURRENT_FUNCTION' symbol, which means
3274 'the start of the function that this code is output in'. */
3276 #define ASM_OUTPUT_LABELREF(FILE,NAME) \
3277 if (strcmp (NAME, "..CURRENT_FUNCTION") == 0) \
3278 asm_fprintf ((FILE), "%U%s", \
3279 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0)); \
3281 asm_fprintf ((FILE), "%U%s", (NAME))
3283 /* The mips16 wants the constant pool to be after the function,
3284 because the PC relative load instructions use unsigned offsets. */
3286 #define CONSTANT_POOL_BEFORE_FUNCTION (! TARGET_MIPS16)
3288 #define ASM_OUTPUT_POOL_EPILOGUE(FILE, FNNAME, FNDECL, SIZE) \
3289 mips_string_length = 0;
3292 /* In mips16 mode, put most string constants after the function. */
3293 #define CONSTANT_AFTER_FUNCTION_P(tree) \
3294 (TARGET_MIPS16 && mips16_constant_after_function_p (tree))
3297 /* Specify the machine mode that this machine uses
3298 for the index in the tablejump instruction.
3299 ??? Using HImode in mips16 mode can cause overflow. However, the
3300 overflow is no more likely than the overflow in a branch
3301 instruction. Large functions can currently break in both ways. */
3302 #define CASE_VECTOR_MODE \
3303 (TARGET_MIPS16 ? HImode : Pmode == DImode ? DImode : SImode)
3305 /* Define as C expression which evaluates to nonzero if the tablejump
3306 instruction expects the table to contain offsets from the address of the
3308 Do not define this if the table should contain absolute addresses. */
3309 #define CASE_VECTOR_PC_RELATIVE (TARGET_MIPS16)
3311 /* Define this as 1 if `char' should by default be signed; else as 0. */
3312 #ifndef DEFAULT_SIGNED_CHAR
3313 #define DEFAULT_SIGNED_CHAR 1
3316 /* Max number of bytes we can move from memory to memory
3317 in one reasonably fast instruction. */
3318 #define MOVE_MAX (TARGET_64BIT ? 8 : 4)
3319 #define MAX_MOVE_MAX 8
3321 /* Define this macro as a C expression which is nonzero if
3322 accessing less than a word of memory (i.e. a `char' or a
3323 `short') is no faster than accessing a word of memory, i.e., if
3324 such access require more than one instruction or if there is no
3325 difference in cost between byte and (aligned) word loads.
3327 On RISC machines, it tends to generate better code to define
3328 this as 1, since it avoids making a QI or HI mode register. */
3329 #define SLOW_BYTE_ACCESS 1
3331 /* We assume that the store-condition-codes instructions store 0 for false
3332 and some other value for true. This is the value stored for true. */
3334 #define STORE_FLAG_VALUE 1
3336 /* Define this to be nonzero if shift instructions ignore all but the low-order
3338 #define SHIFT_COUNT_TRUNCATED 1
3340 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
3341 is done just by pretending it is already truncated. */
3342 /* In 64 bit mode, 32 bit instructions require that register values be properly
3343 sign-extended to 64 bits. As a result, a truncate is not a no-op if it
3344 converts a value >32 bits to a value <32 bits. */
3345 /* ??? This results in inefficient code for 64 bit to 32 conversions.
3346 Something needs to be done about this. Perhaps not use any 32 bit
3347 instructions? Perhaps use PROMOTE_MODE? */
3348 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) \
3349 (TARGET_64BIT ? ((INPREC) <= 32 || (OUTPREC) > 32) : 1)
3351 /* Specify the machine mode that pointers have.
3352 After generation of rtl, the compiler makes no further distinction
3353 between pointers and any other objects of this machine mode.
3355 For MIPS we make pointers are the smaller of longs and gp-registers. */
3358 #define Pmode ((TARGET_LONG64 && TARGET_64BIT) ? DImode : SImode)
3361 /* A function address in a call instruction
3362 is a word address (for indexing purposes)
3363 so give the MEM rtx a words's mode. */
3365 #define FUNCTION_MODE (Pmode == DImode ? DImode : SImode)
3368 /* A part of a C `switch' statement that describes the relative
3369 costs of constant RTL expressions. It must contain `case'
3370 labels for expression codes `const_int', `const', `symbol_ref',
3371 `label_ref' and `const_double'. Each case must ultimately reach
3372 a `return' statement to return the relative cost of the use of
3373 that kind of constant value in an expression. The cost may
3374 depend on the precise value of the constant, which is available
3375 for examination in X.
3377 CODE is the expression code--redundant, since it can be obtained
3378 with `GET_CODE (X)'. */
3380 #define CONST_COSTS(X,CODE,OUTER_CODE) \
3382 if (! TARGET_MIPS16) \
3384 /* Always return 0, since we don't have different sized \
3385 instructions, hence different costs according to Richard \
3389 if ((OUTER_CODE) == SET) \
3391 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3393 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3394 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3395 return COSTS_N_INSNS (1); \
3397 return COSTS_N_INSNS (2); \
3399 /* A PLUS could be an address. We don't want to force an address \
3400 to use a register, so accept any signed 16 bit value without \
3402 if ((OUTER_CODE) == PLUS \
3403 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3405 /* A number between 1 and 8 inclusive is efficient for a shift. \
3406 Otherwise, we will need an extended instruction. */ \
3407 if ((OUTER_CODE) == ASHIFT || (OUTER_CODE) == ASHIFTRT \
3408 || (OUTER_CODE) == LSHIFTRT) \
3410 if (INTVAL (X) >= 1 && INTVAL (X) <= 8) \
3412 return COSTS_N_INSNS (1); \
3414 /* We can use cmpi for an xor with an unsigned 16 bit value. */ \
3415 if ((OUTER_CODE) == XOR \
3416 && INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3418 /* We may be able to use slt or sltu for a comparison with a \
3419 signed 16 bit value. (The boundary conditions aren't quite \
3420 right, but this is just a heuristic anyhow.) */ \
3421 if (((OUTER_CODE) == LT || (OUTER_CODE) == LE \
3422 || (OUTER_CODE) == GE || (OUTER_CODE) == GT \
3423 || (OUTER_CODE) == LTU || (OUTER_CODE) == LEU \
3424 || (OUTER_CODE) == GEU || (OUTER_CODE) == GTU) \
3425 && INTVAL (X) >= -0x8000 && INTVAL (X) < 0x8000) \
3427 /* Equality comparisons with 0 are cheap. */ \
3428 if (((OUTER_CODE) == EQ || (OUTER_CODE) == NE) \
3429 && INTVAL (X) == 0) \
3432 /* Otherwise, work out the cost to load the value into a \
3434 if (INTVAL (X) >= 0 && INTVAL (X) < 0x100) \
3435 return COSTS_N_INSNS (1); \
3436 else if ((INTVAL (X) >= 0 && INTVAL (X) < 0x10000) \
3437 || (INTVAL (X) < 0 && INTVAL (X) > -0x100)) \
3438 return COSTS_N_INSNS (2); \
3440 return COSTS_N_INSNS (3); \
3443 return COSTS_N_INSNS (2); \
3447 rtx offset = const0_rtx; \
3448 rtx symref = eliminate_constant_term (XEXP (X, 0), &offset); \
3450 if (TARGET_MIPS16 && mips16_gp_offset_p (X)) \
3452 /* Treat this like a signed 16 bit CONST_INT. */ \
3453 if ((OUTER_CODE) == PLUS) \
3455 else if ((OUTER_CODE) == SET) \
3456 return COSTS_N_INSNS (1); \
3458 return COSTS_N_INSNS (2); \
3461 if (GET_CODE (symref) == LABEL_REF) \
3462 return COSTS_N_INSNS (2); \
3464 if (GET_CODE (symref) != SYMBOL_REF) \
3465 return COSTS_N_INSNS (4); \
3467 /* let's be paranoid.... */ \
3468 if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767) \
3469 return COSTS_N_INSNS (2); \
3471 return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
3475 return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
3477 case CONST_DOUBLE: \
3480 if (TARGET_MIPS16) \
3481 return COSTS_N_INSNS (4); \
3482 split_double (X, &high, &low); \
3483 return COSTS_N_INSNS ((high == CONST0_RTX (GET_MODE (high)) \
3484 || low == CONST0_RTX (GET_MODE (low))) \
3488 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
3489 This can be used, for example, to indicate how costly a multiply
3490 instruction is. In writing this macro, you can use the construct
3491 `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
3493 This macro is optional; do not define it if the default cost
3494 assumptions are adequate for the target machine.
3496 If -mdebugd is used, change the multiply cost to 2, so multiply by
3497 a constant isn't converted to a series of shifts. This helps
3498 strength reduction, and also makes it easier to identify what the
3499 compiler is doing. */
3501 /* ??? Fix this to be right for the R8000. */
3502 #define RTX_COSTS(X,CODE,OUTER_CODE) \
3505 int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
3506 if (simple_memory_operand (X, GET_MODE (X))) \
3507 return COSTS_N_INSNS (num_words); \
3509 return COSTS_N_INSNS (2*num_words); \
3513 return COSTS_N_INSNS (6); \
3516 return COSTS_N_INSNS ((GET_MODE (X) == DImode && !TARGET_64BIT) ? 2 : 1); \
3521 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3522 return COSTS_N_INSNS (2); \
3529 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3530 return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 4 : 12); \
3536 enum machine_mode xmode = GET_MODE (X); \
3537 if (xmode == SFmode || xmode == DFmode) \
3538 return COSTS_N_INSNS (1); \
3540 return COSTS_N_INSNS (4); \
3546 enum machine_mode xmode = GET_MODE (X); \
3547 if (xmode == SFmode || xmode == DFmode) \
3551 return COSTS_N_INSNS (2); \
3552 else if (TUNE_MIPS6000) \
3553 return COSTS_N_INSNS (3); \
3555 return COSTS_N_INSNS (6); \
3558 if (xmode == DImode && !TARGET_64BIT) \
3559 return COSTS_N_INSNS (4); \
3565 if (GET_MODE (X) == DImode && !TARGET_64BIT) \
3572 enum machine_mode xmode = GET_MODE (X); \
3573 if (xmode == SFmode) \
3578 return COSTS_N_INSNS (4); \
3579 else if (TUNE_MIPS6000 \
3582 return COSTS_N_INSNS (5); \
3584 return COSTS_N_INSNS (7); \
3587 if (xmode == DFmode) \
3592 return COSTS_N_INSNS (5); \
3593 else if (TUNE_MIPS6000 \
3596 return COSTS_N_INSNS (6); \
3598 return COSTS_N_INSNS (8); \
3601 if (TUNE_MIPS3000) \
3602 return COSTS_N_INSNS (12); \
3603 else if (TUNE_MIPS3900) \
3604 return COSTS_N_INSNS (2); \
3605 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3606 return COSTS_N_INSNS ((xmode == DImode) ? 4 : 3); \
3607 else if (TUNE_MIPS6000) \
3608 return COSTS_N_INSNS (17); \
3609 else if (TUNE_MIPS5000) \
3610 return COSTS_N_INSNS (5); \
3612 return COSTS_N_INSNS (10); \
3618 enum machine_mode xmode = GET_MODE (X); \
3619 if (xmode == SFmode) \
3623 return COSTS_N_INSNS (12); \
3624 else if (TUNE_MIPS6000) \
3625 return COSTS_N_INSNS (15); \
3626 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3627 return COSTS_N_INSNS (30); \
3629 return COSTS_N_INSNS (23); \
3632 if (xmode == DFmode) \
3636 return COSTS_N_INSNS (19); \
3637 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3638 return COSTS_N_INSNS (59); \
3639 else if (TUNE_MIPS6000) \
3640 return COSTS_N_INSNS (16); \
3642 return COSTS_N_INSNS (36); \
3645 /* fall through */ \
3651 return COSTS_N_INSNS (35); \
3652 else if (TUNE_MIPS6000) \
3653 return COSTS_N_INSNS (38); \
3654 else if (TUNE_MIPS5000) \
3655 return COSTS_N_INSNS (36); \
3656 else if (TUNE_MIPS5400 || TUNE_MIPS5500) \
3657 return COSTS_N_INSNS ((GET_MODE (X) == SImode) ? 42 : 74); \
3659 return COSTS_N_INSNS (69); \
3662 /* A sign extend from SImode to DImode in 64 bit mode is often \
3663 zero instructions, because the result can often be used \
3664 directly by another instruction; we'll call it one. */ \
3665 if (TARGET_64BIT && GET_MODE (X) == DImode \
3666 && GET_MODE (XEXP (X, 0)) == SImode) \
3667 return COSTS_N_INSNS (1); \
3669 return COSTS_N_INSNS (2); \
3672 if (TARGET_64BIT && GET_MODE (X) == DImode \
3673 && GET_MODE (XEXP (X, 0)) == SImode) \
3674 return COSTS_N_INSNS (2); \
3676 return COSTS_N_INSNS (1);
3678 /* An expression giving the cost of an addressing mode that
3679 contains ADDRESS. If not defined, the cost is computed from the
3680 form of the ADDRESS expression and the `CONST_COSTS' values.
3682 For most CISC machines, the default cost is a good approximation
3683 of the true cost of the addressing mode. However, on RISC
3684 machines, all instructions normally have the same length and
3685 execution time. Hence all addresses will have equal costs.
3687 In cases where more than one form of an address is known, the
3688 form with the lowest cost will be used. If multiple forms have
3689 the same, lowest, cost, the one that is the most complex will be
3692 For example, suppose an address that is equal to the sum of a
3693 register and a constant is used twice in the same basic block.
3694 When this macro is not defined, the address will be computed in
3695 a register and memory references will be indirect through that
3696 register. On machines where the cost of the addressing mode
3697 containing the sum is no higher than that of a simple indirect
3698 reference, this will produce an additional instruction and
3699 possibly require an additional register. Proper specification
3700 of this macro eliminates this overhead for such machines.
3702 Similar use of this macro is made in strength reduction of loops.
3704 ADDRESS need not be valid as an address. In such a case, the
3705 cost is not relevant and can be any value; invalid addresses
3706 need not be assigned a different cost.
3708 On machines where an address involving more than one register is
3709 as cheap as an address computation involving only one register,
3710 defining `ADDRESS_COST' to reflect this can cause two registers
3711 to be live over a region of code where only one would have been
3712 if `ADDRESS_COST' were not defined in that manner. This effect
3713 should be considered in the definition of this macro.
3714 Equivalent costs should probably only be given to addresses with
3715 different numbers of registers on machines with lots of registers.
3717 This macro will normally either not be defined or be defined as
3720 #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
3722 /* A C expression for the cost of moving data from a register in
3723 class FROM to one in class TO. The classes are expressed using
3724 the enumeration values such as `GENERAL_REGS'. A value of 2 is
3725 the default; other values are interpreted relative to that.
3727 It is not required that the cost always equal 2 when FROM is the
3728 same as TO; on some machines it is expensive to move between
3729 registers if they are not general registers.
3731 If reload sees an insn consisting of a single `set' between two
3732 hard registers, and if `REGISTER_MOVE_COST' applied to their
3733 classes returns a value of 2, reload does not check to ensure
3734 that the constraints of the insn are met. Setting a cost of
3735 other than 2 will allow reload to verify that the constraints are
3736 met. You should do this if the `movM' pattern's constraints do
3737 not allow such copying. */
3739 #define REGISTER_MOVE_COST(MODE, FROM, TO) \
3740 mips_register_move_cost (MODE, FROM, TO)
3742 /* ??? Fix this to be right for the R8000. */
3743 #define MEMORY_MOVE_COST(MODE,CLASS,TO_P) \
3744 (((TUNE_MIPS4000 || TUNE_MIPS6000) ? 6 : 4) \
3745 + memory_move_secondary_cost ((MODE), (CLASS), (TO_P)))
3747 /* Define if copies to/from condition code registers should be avoided.
3749 This is needed for the MIPS because reload_outcc is not complete;
3750 it needs to handle cases where the source is a general or another
3751 condition code register. */
3752 #define AVOID_CCMODE_COPIES
3754 /* A C expression for the cost of a branch instruction. A value of
3755 1 is the default; other values are interpreted relative to that. */
3757 /* ??? Fix this to be right for the R8000. */
3758 #define BRANCH_COST \
3760 && (TUNE_MIPS4000 || TUNE_MIPS6000)) \
3763 /* If defined, modifies the length assigned to instruction INSN as a
3764 function of the context in which it is used. LENGTH is an lvalue
3765 that contains the initially computed length of the insn and should
3766 be updated with the correct length of the insn. */
3767 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
3768 ((LENGTH) = mips_adjust_insn_length ((INSN), (LENGTH)))
3771 /* Optionally define this if you have added predicates to
3772 `MACHINE.c'. This macro is called within an initializer of an
3773 array of structures. The first field in the structure is the
3774 name of a predicate and the second field is an array of rtl
3775 codes. For each predicate, list all rtl codes that can be in
3776 expressions matched by the predicate. The list should have a
3777 trailing comma. Here is an example of two entries in the list
3778 for a typical RISC machine:
3780 #define PREDICATE_CODES \
3781 {"gen_reg_rtx_operand", {SUBREG, REG}}, \
3782 {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
3784 Defining this macro does not affect the generated code (however,
3785 incorrect definitions that omit an rtl code that may be matched
3786 by the predicate can cause the compiler to malfunction).
3787 Instead, it allows the table built by `genrecog' to be more
3788 compact and efficient, thus speeding up the compiler. The most
3789 important predicates to include in the list specified by this
3790 macro are thoses used in the most insn patterns. */
3792 #define PREDICATE_CODES \
3793 {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
3794 {"arith_operand", { REG, CONST_INT, SUBREG }}, \
3795 {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
3796 {"reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3797 {"true_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG }}, \
3798 {"small_int", { CONST_INT }}, \
3799 {"large_int", { CONST_INT }}, \
3800 {"mips_const_double_ok", { CONST_DOUBLE }}, \
3801 {"const_float_1_operand", { CONST_DOUBLE }}, \
3802 {"simple_memory_operand", { MEM, SUBREG }}, \
3803 {"equality_op", { EQ, NE }}, \
3804 {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
3806 {"trap_cmp_op", { EQ, NE, GE, GEU, LT, LTU }}, \
3807 {"pc_or_label_operand", { PC, LABEL_REF }}, \
3808 {"call_insn_operand", { CONST_INT, CONST, SYMBOL_REF, REG}}, \
3809 {"move_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3810 SYMBOL_REF, LABEL_REF, SUBREG, \
3812 {"movdi_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3813 SYMBOL_REF, LABEL_REF, SUBREG, REG, \
3814 MEM, SIGN_EXTEND }}, \
3815 {"se_register_operand", { SUBREG, REG, SIGN_EXTEND }}, \
3816 {"se_reg_or_0_operand", { REG, CONST_INT, CONST_DOUBLE, SUBREG, \
3818 {"se_uns_arith_operand", { REG, CONST_INT, SUBREG, \
3820 {"se_arith_operand", { REG, CONST_INT, SUBREG, \
3822 {"se_nonmemory_operand", { CONST_INT, CONST_DOUBLE, CONST, \
3823 SYMBOL_REF, LABEL_REF, SUBREG, \
3824 REG, SIGN_EXTEND }}, \
3825 {"consttable_operand", { LABEL_REF, SYMBOL_REF, CONST_INT, \
3826 CONST_DOUBLE, CONST }}, \
3827 {"extend_operator", { SIGN_EXTEND, ZERO_EXTEND }}, \
3828 {"highpart_shift_operator", { ASHIFTRT, LSHIFTRT, ROTATERT, ROTATE }},
3830 /* A list of predicates that do special things with modes, and so
3831 should not elicit warnings for VOIDmode match_operand. */
3833 #define SPECIAL_MODE_PREDICATES \
3834 "pc_or_label_operand",
3837 /* If defined, a C statement to be executed just prior to the
3838 output of assembler code for INSN, to modify the extracted
3839 operands so they will be output differently.
3841 Here the argument OPVEC is the vector containing the operands
3842 extracted from INSN, and NOPERANDS is the number of elements of
3843 the vector which contain meaningful data for this insn. The
3844 contents of this vector are what will be used to convert the
3845 insn template into assembler code, so you can change the
3846 assembler output by changing the contents of the vector.
3848 We use it to check if the current insn needs a nop in front of it
3849 because of load delays, and also to update the delay slot
3852 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
3853 final_prescan_insn (INSN, OPVEC, NOPERANDS)
3856 /* Control the assembler format that we output. */
3858 /* Output at beginning of assembler file.
3859 If we are optimizing to use the global pointer, create a temporary
3860 file to hold all of the text stuff, and write it out to the end.
3861 This is needed because the MIPS assembler is evidently one pass,
3862 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
3863 declaration when the code is processed, it generates a two
3864 instruction sequence. */
3866 #undef ASM_FILE_START
3867 #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
3869 /* Output to assembler file text saying following lines
3870 may contain character constants, extra white space, comments, etc. */
3873 #define ASM_APP_ON " #APP\n"
3876 /* Output to assembler file text saying following lines
3877 no longer contain unusual constructs. */
3880 #define ASM_APP_OFF " #NO_APP\n"
3883 /* How to refer to registers in assembler output.
3884 This sequence is indexed by compiler's hard-register-number (see above).
3886 In order to support the two different conventions for register names,
3887 we use the name of a table set up in mips.c, which is overwritten
3888 if -mrnames is used. */
3890 #define REGISTER_NAMES \
3892 &mips_reg_names[ 0][0], \
3893 &mips_reg_names[ 1][0], \
3894 &mips_reg_names[ 2][0], \
3895 &mips_reg_names[ 3][0], \
3896 &mips_reg_names[ 4][0], \
3897 &mips_reg_names[ 5][0], \
3898 &mips_reg_names[ 6][0], \
3899 &mips_reg_names[ 7][0], \
3900 &mips_reg_names[ 8][0], \
3901 &mips_reg_names[ 9][0], \
3902 &mips_reg_names[10][0], \
3903 &mips_reg_names[11][0], \
3904 &mips_reg_names[12][0], \
3905 &mips_reg_names[13][0], \
3906 &mips_reg_names[14][0], \
3907 &mips_reg_names[15][0], \
3908 &mips_reg_names[16][0], \
3909 &mips_reg_names[17][0], \
3910 &mips_reg_names[18][0], \
3911 &mips_reg_names[19][0], \
3912 &mips_reg_names[20][0], \
3913 &mips_reg_names[21][0], \
3914 &mips_reg_names[22][0], \
3915 &mips_reg_names[23][0], \
3916 &mips_reg_names[24][0], \
3917 &mips_reg_names[25][0], \
3918 &mips_reg_names[26][0], \
3919 &mips_reg_names[27][0], \
3920 &mips_reg_names[28][0], \
3921 &mips_reg_names[29][0], \
3922 &mips_reg_names[30][0], \
3923 &mips_reg_names[31][0], \
3924 &mips_reg_names[32][0], \
3925 &mips_reg_names[33][0], \
3926 &mips_reg_names[34][0], \
3927 &mips_reg_names[35][0], \
3928 &mips_reg_names[36][0], \
3929 &mips_reg_names[37][0], \
3930 &mips_reg_names[38][0], \
3931 &mips_reg_names[39][0], \
3932 &mips_reg_names[40][0], \
3933 &mips_reg_names[41][0], \
3934 &mips_reg_names[42][0], \
3935 &mips_reg_names[43][0], \
3936 &mips_reg_names[44][0], \
3937 &mips_reg_names[45][0], \
3938 &mips_reg_names[46][0], \
3939 &mips_reg_names[47][0], \
3940 &mips_reg_names[48][0], \
3941 &mips_reg_names[49][0], \
3942 &mips_reg_names[50][0], \
3943 &mips_reg_names[51][0], \
3944 &mips_reg_names[52][0], \
3945 &mips_reg_names[53][0], \
3946 &mips_reg_names[54][0], \
3947 &mips_reg_names[55][0], \
3948 &mips_reg_names[56][0], \
3949 &mips_reg_names[57][0], \
3950 &mips_reg_names[58][0], \
3951 &mips_reg_names[59][0], \
3952 &mips_reg_names[60][0], \
3953 &mips_reg_names[61][0], \
3954 &mips_reg_names[62][0], \
3955 &mips_reg_names[63][0], \
3956 &mips_reg_names[64][0], \
3957 &mips_reg_names[65][0], \
3958 &mips_reg_names[66][0], \
3959 &mips_reg_names[67][0], \
3960 &mips_reg_names[68][0], \
3961 &mips_reg_names[69][0], \
3962 &mips_reg_names[70][0], \
3963 &mips_reg_names[71][0], \
3964 &mips_reg_names[72][0], \
3965 &mips_reg_names[73][0], \
3966 &mips_reg_names[74][0], \
3967 &mips_reg_names[75][0], \
3968 &mips_reg_names[76][0], \
3969 &mips_reg_names[77][0], \
3970 &mips_reg_names[78][0], \
3971 &mips_reg_names[79][0], \
3972 &mips_reg_names[80][0], \
3973 &mips_reg_names[81][0], \
3974 &mips_reg_names[82][0], \
3975 &mips_reg_names[83][0], \
3976 &mips_reg_names[84][0], \
3977 &mips_reg_names[85][0], \
3978 &mips_reg_names[86][0], \
3979 &mips_reg_names[87][0], \
3980 &mips_reg_names[88][0], \
3981 &mips_reg_names[89][0], \
3982 &mips_reg_names[90][0], \
3983 &mips_reg_names[91][0], \
3984 &mips_reg_names[92][0], \
3985 &mips_reg_names[93][0], \
3986 &mips_reg_names[94][0], \
3987 &mips_reg_names[95][0], \
3988 &mips_reg_names[96][0], \
3989 &mips_reg_names[97][0], \
3990 &mips_reg_names[98][0], \
3991 &mips_reg_names[99][0], \
3992 &mips_reg_names[100][0], \
3993 &mips_reg_names[101][0], \
3994 &mips_reg_names[102][0], \
3995 &mips_reg_names[103][0], \
3996 &mips_reg_names[104][0], \
3997 &mips_reg_names[105][0], \
3998 &mips_reg_names[106][0], \
3999 &mips_reg_names[107][0], \
4000 &mips_reg_names[108][0], \
4001 &mips_reg_names[109][0], \
4002 &mips_reg_names[110][0], \
4003 &mips_reg_names[111][0], \
4004 &mips_reg_names[112][0], \
4005 &mips_reg_names[113][0], \
4006 &mips_reg_names[114][0], \
4007 &mips_reg_names[115][0], \
4008 &mips_reg_names[116][0], \
4009 &mips_reg_names[117][0], \
4010 &mips_reg_names[118][0], \
4011 &mips_reg_names[119][0], \
4012 &mips_reg_names[120][0], \
4013 &mips_reg_names[121][0], \
4014 &mips_reg_names[122][0], \
4015 &mips_reg_names[123][0], \
4016 &mips_reg_names[124][0], \
4017 &mips_reg_names[125][0], \
4018 &mips_reg_names[126][0], \
4019 &mips_reg_names[127][0], \
4020 &mips_reg_names[128][0], \
4021 &mips_reg_names[129][0], \
4022 &mips_reg_names[130][0], \
4023 &mips_reg_names[131][0], \
4024 &mips_reg_names[132][0], \
4025 &mips_reg_names[133][0], \
4026 &mips_reg_names[134][0], \
4027 &mips_reg_names[135][0], \
4028 &mips_reg_names[136][0], \
4029 &mips_reg_names[137][0], \
4030 &mips_reg_names[138][0], \
4031 &mips_reg_names[139][0], \
4032 &mips_reg_names[140][0], \
4033 &mips_reg_names[141][0], \
4034 &mips_reg_names[142][0], \
4035 &mips_reg_names[143][0], \
4036 &mips_reg_names[144][0], \
4037 &mips_reg_names[145][0], \
4038 &mips_reg_names[146][0], \
4039 &mips_reg_names[147][0], \
4040 &mips_reg_names[148][0], \
4041 &mips_reg_names[149][0], \
4042 &mips_reg_names[150][0], \
4043 &mips_reg_names[151][0], \
4044 &mips_reg_names[152][0], \
4045 &mips_reg_names[153][0], \
4046 &mips_reg_names[154][0], \
4047 &mips_reg_names[155][0], \
4048 &mips_reg_names[156][0], \
4049 &mips_reg_names[157][0], \
4050 &mips_reg_names[158][0], \
4051 &mips_reg_names[159][0], \
4052 &mips_reg_names[160][0], \
4053 &mips_reg_names[161][0], \
4054 &mips_reg_names[162][0], \
4055 &mips_reg_names[163][0], \
4056 &mips_reg_names[164][0], \
4057 &mips_reg_names[165][0], \
4058 &mips_reg_names[166][0], \
4059 &mips_reg_names[167][0], \
4060 &mips_reg_names[168][0], \
4061 &mips_reg_names[169][0], \
4062 &mips_reg_names[170][0], \
4063 &mips_reg_names[171][0], \
4064 &mips_reg_names[172][0], \
4065 &mips_reg_names[173][0], \
4066 &mips_reg_names[174][0], \
4067 &mips_reg_names[175][0] \
4070 /* print-rtl.c can't use REGISTER_NAMES, since it depends on mips.c.
4071 So define this for it. */
4072 #define DEBUG_REGISTER_NAMES \
4074 "$0", "at", "v0", "v1", "a0", "a1", "a2", "a3", \
4075 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", \
4076 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", \
4077 "t8", "t9", "k0", "k1", "gp", "sp", "$fp", "ra", \
4078 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", \
4079 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", \
4080 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", \
4081 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", \
4082 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", \
4083 "$fcc5","$fcc6","$fcc7","$rap", "", "", "", "", \
4084 "$c0r0", "$c0r1", "$c0r2", "$c0r3", "$c0r4", "$c0r5", "$c0r6", "$c0r7",\
4085 "$c0r8", "$c0r9", "$c0r10","$c0r11","$c0r12","$c0r13","$c0r14","$c0r15",\
4086 "$c0r16","$c0r17","$c0r18","$c0r19","$c0r20","$c0r21","$c0r22","$c0r23",\
4087 "$c0r24","$c0r25","$c0r26","$c0r27","$c0r28","$c0r29","$c0r30","$c0r31",\
4088 "$c2r0", "$c2r1", "$c2r2", "$c2r3", "$c2r4", "$c2r5", "$c2r6", "$c2r7",\
4089 "$c2r8", "$c2r9", "$c2r10","$c2r11","$c2r12","$c2r13","$c2r14","$c2r15",\
4090 "$c2r16","$c2r17","$c2r18","$c2r19","$c2r20","$c2r21","$c2r22","$c2r23",\
4091 "$c2r24","$c2r25","$c2r26","$c2r27","$c2r28","$c2r29","$c2r30","$c2r31",\
4092 "$c3r0", "$c3r1", "$c3r2", "$c3r3", "$c3r4", "$c3r5", "$c3r6", "$c3r7",\
4093 "$c3r8", "$c3r9", "$c3r10","$c3r11","$c3r12","$c3r13","$c3r14","$c3r15",\
4094 "$c3r16","$c3r17","$c3r18","$c3r19","$c3r20","$c3r21","$c3r22","$c3r23",\
4095 "$c3r24","$c3r25","$c3r26","$c3r27","$c3r28","$c3r29","$c3r30","$c3r31"\
4098 /* If defined, a C initializer for an array of structures
4099 containing a name and a register number. This macro defines
4100 additional names for hard registers, thus allowing the `asm'
4101 option in declarations to refer to registers using alternate
4104 We define both names for the integer registers here. */
4106 #define ADDITIONAL_REGISTER_NAMES \
4108 { "$0", 0 + GP_REG_FIRST }, \
4109 { "$1", 1 + GP_REG_FIRST }, \
4110 { "$2", 2 + GP_REG_FIRST }, \
4111 { "$3", 3 + GP_REG_FIRST }, \
4112 { "$4", 4 + GP_REG_FIRST }, \
4113 { "$5", 5 + GP_REG_FIRST }, \
4114 { "$6", 6 + GP_REG_FIRST }, \
4115 { "$7", 7 + GP_REG_FIRST }, \
4116 { "$8", 8 + GP_REG_FIRST }, \
4117 { "$9", 9 + GP_REG_FIRST }, \
4118 { "$10", 10 + GP_REG_FIRST }, \
4119 { "$11", 11 + GP_REG_FIRST }, \
4120 { "$12", 12 + GP_REG_FIRST }, \
4121 { "$13", 13 + GP_REG_FIRST }, \
4122 { "$14", 14 + GP_REG_FIRST }, \
4123 { "$15", 15 + GP_REG_FIRST }, \
4124 { "$16", 16 + GP_REG_FIRST }, \
4125 { "$17", 17 + GP_REG_FIRST }, \
4126 { "$18", 18 + GP_REG_FIRST }, \
4127 { "$19", 19 + GP_REG_FIRST }, \
4128 { "$20", 20 + GP_REG_FIRST }, \
4129 { "$21", 21 + GP_REG_FIRST }, \
4130 { "$22", 22 + GP_REG_FIRST }, \
4131 { "$23", 23 + GP_REG_FIRST }, \
4132 { "$24", 24 + GP_REG_FIRST }, \
4133 { "$25", 25 + GP_REG_FIRST }, \
4134 { "$26", 26 + GP_REG_FIRST }, \
4135 { "$27", 27 + GP_REG_FIRST }, \
4136 { "$28", 28 + GP_REG_FIRST }, \
4137 { "$29", 29 + GP_REG_FIRST }, \
4138 { "$30", 30 + GP_REG_FIRST }, \
4139 { "$31", 31 + GP_REG_FIRST }, \
4140 { "$sp", 29 + GP_REG_FIRST }, \
4141 { "$fp", 30 + GP_REG_FIRST }, \
4142 { "at", 1 + GP_REG_FIRST }, \
4143 { "v0", 2 + GP_REG_FIRST }, \
4144 { "v1", 3 + GP_REG_FIRST }, \
4145 { "a0", 4 + GP_REG_FIRST }, \
4146 { "a1", 5 + GP_REG_FIRST }, \
4147 { "a2", 6 + GP_REG_FIRST }, \
4148 { "a3", 7 + GP_REG_FIRST }, \
4149 { "t0", 8 + GP_REG_FIRST }, \
4150 { "t1", 9 + GP_REG_FIRST }, \
4151 { "t2", 10 + GP_REG_FIRST }, \
4152 { "t3", 11 + GP_REG_FIRST }, \
4153 { "t4", 12 + GP_REG_FIRST }, \
4154 { "t5", 13 + GP_REG_FIRST }, \
4155 { "t6", 14 + GP_REG_FIRST }, \
4156 { "t7", 15 + GP_REG_FIRST }, \
4157 { "s0", 16 + GP_REG_FIRST }, \
4158 { "s1", 17 + GP_REG_FIRST }, \
4159 { "s2", 18 + GP_REG_FIRST }, \
4160 { "s3", 19 + GP_REG_FIRST }, \
4161 { "s4", 20 + GP_REG_FIRST }, \
4162 { "s5", 21 + GP_REG_FIRST }, \
4163 { "s6", 22 + GP_REG_FIRST }, \
4164 { "s7", 23 + GP_REG_FIRST }, \
4165 { "t8", 24 + GP_REG_FIRST }, \
4166 { "t9", 25 + GP_REG_FIRST }, \
4167 { "k0", 26 + GP_REG_FIRST }, \
4168 { "k1", 27 + GP_REG_FIRST }, \
4169 { "gp", 28 + GP_REG_FIRST }, \
4170 { "sp", 29 + GP_REG_FIRST }, \
4171 { "fp", 30 + GP_REG_FIRST }, \
4172 { "ra", 31 + GP_REG_FIRST }, \
4173 { "$sp", 29 + GP_REG_FIRST }, \
4174 { "$fp", 30 + GP_REG_FIRST } \
4175 ALL_COP_ADDITIONAL_REGISTER_NAMES \
4178 /* This is meant to be redefined in the host dependent files. It is a
4179 set of alternative names and regnums for mips coprocessors. */
4181 #define ALL_COP_ADDITIONAL_REGISTER_NAMES
4183 /* A C compound statement to output to stdio stream STREAM the
4184 assembler syntax for an instruction operand X. X is an RTL
4187 CODE is a value that can be used to specify one of several ways
4188 of printing the operand. It is used when identical operands
4189 must be printed differently depending on the context. CODE
4190 comes from the `%' specification that was used to request
4191 printing of the operand. If the specification was just `%DIGIT'
4192 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4193 is the ASCII code for LTR.
4195 If X is a register, this macro should print the register's name.
4196 The names can be found in an array `reg_names' whose type is
4197 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4199 When the machine description has a specification `%PUNCT' (a `%'
4200 followed by a punctuation character), this macro is called with
4201 a null pointer for X and the punctuation character for CODE.
4203 See mips.c for the MIPS specific codes. */
4205 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
4207 /* A C expression which evaluates to true if CODE is a valid
4208 punctuation character for use in the `PRINT_OPERAND' macro. If
4209 `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
4210 punctuation characters (except for the standard one, `%') are
4211 used in this way. */
4213 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
4215 /* A C compound statement to output to stdio stream STREAM the
4216 assembler syntax for an instruction operand that is a memory
4217 reference whose address is ADDR. ADDR is an RTL expression. */
4219 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
4222 /* A C statement, to be executed after all slot-filler instructions
4223 have been output. If necessary, call `dbr_sequence_length' to
4224 determine the number of slots filled in a sequence (zero if not
4225 currently outputting a sequence), to decide how many no-ops to
4226 output, or whatever.
4228 Don't define this macro if it has nothing to do, but it is
4229 helpful in reading assembly output if the extent of the delay
4230 sequence is made explicit (e.g. with white space).
4232 Note that output routines for instructions with delay slots must
4233 be prepared to deal with not being output as part of a sequence
4234 (i.e. when the scheduling pass is not run, or when no slot
4235 fillers could be found.) The variable `final_sequence' is null
4236 when not processing a sequence, otherwise it contains the
4237 `sequence' rtx being output. */
4239 #define DBR_OUTPUT_SEQEND(STREAM) \
4242 if (set_nomacro > 0 && --set_nomacro == 0) \
4243 fputs ("\t.set\tmacro\n", STREAM); \
4245 if (set_noreorder > 0 && --set_noreorder == 0) \
4246 fputs ("\t.set\treorder\n", STREAM); \
4248 dslots_jump_filled++; \
4249 fputs ("\n", STREAM); \
4254 /* How to tell the debugger about changes of source files. Note, the
4255 mips ECOFF format cannot deal with changes of files inside of
4256 functions, which means the output of parser generators like bison
4257 is generally not debuggable without using the -l switch. Lose,
4258 lose, lose. Silicon graphics seems to want all .file's hardwired
4261 #ifndef SET_FILE_NUMBER
4262 #define SET_FILE_NUMBER() ++num_source_filenames
4265 #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
4266 mips_output_filename (STREAM, NAME)
4268 /* This is defined so that it can be overridden in iris6.h. */
4269 #define ASM_OUTPUT_FILENAME(STREAM, NUM_SOURCE_FILENAMES, NAME) \
4272 fprintf (STREAM, "\t.file\t%d ", NUM_SOURCE_FILENAMES); \
4273 output_quoted_string (STREAM, NAME); \
4274 fputs ("\n", STREAM); \
4278 /* This is how to output a note the debugger telling it the line number
4279 to which the following sequence of instructions corresponds.
4280 Silicon graphics puts a label after each .loc. */
4282 #ifndef LABEL_AFTER_LOC
4283 #define LABEL_AFTER_LOC(STREAM)
4286 #ifndef ASM_OUTPUT_SOURCE_LINE
4287 #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
4288 mips_output_lineno (STREAM, LINE)
4291 /* The MIPS implementation uses some labels for its own purpose. The
4292 following lists what labels are created, and are all formed by the
4293 pattern $L[a-z].*. The machine independent portion of GCC creates
4294 labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
4296 LM[0-9]+ Silicon Graphics/ECOFF stabs label before each stmt.
4297 $Lb[0-9]+ Begin blocks for MIPS debug support
4298 $Lc[0-9]+ Label for use in s<xx> operation.
4299 $Le[0-9]+ End blocks for MIPS debug support */
4301 /* A C statement (sans semicolon) to output to the stdio stream
4302 STREAM any text necessary for declaring the name NAME of an
4303 initialized variable which is being defined. This macro must
4304 output the label definition (perhaps using `ASM_OUTPUT_LABEL').
4305 The argument DECL is the `VAR_DECL' tree node representing the
4308 If this macro is not defined, then the variable name is defined
4309 in the usual manner as a label (by means of `ASM_OUTPUT_LABEL'). */
4311 #undef ASM_DECLARE_OBJECT_NAME
4312 #define ASM_DECLARE_OBJECT_NAME(STREAM, NAME, DECL) \
4315 mips_declare_object (STREAM, NAME, "", ":\n", 0); \
4319 /* Globalizing directive for a label. */
4320 #define GLOBAL_ASM_OP "\t.globl\t"
4322 /* This says how to define a global common symbol. */
4324 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGN) \
4326 /* If the target wants uninitialized const declarations in \
4327 .rdata then don't put them in .comm */ \
4328 if (TARGET_EMBEDDED_DATA && TARGET_UNINIT_CONST_IN_RODATA \
4329 && TREE_CODE (DECL) == VAR_DECL && TREE_READONLY (DECL) \
4330 && (DECL_INITIAL (DECL) == 0 \
4331 || DECL_INITIAL (DECL) == error_mark_node)) \
4333 if (TREE_PUBLIC (DECL) && DECL_NAME (DECL)) \
4334 (*targetm.asm_out.globalize_label) (STREAM, NAME); \
4336 readonly_data_section (); \
4337 ASM_OUTPUT_ALIGN (STREAM, floor_log2 (ALIGN / BITS_PER_UNIT)); \
4338 mips_declare_object (STREAM, NAME, "", ":\n\t.space\t%u\n", \
4342 mips_declare_object (STREAM, NAME, "\n\t.comm\t", ",%u\n", \
4347 /* This says how to define a local common symbol (ie, not visible to
4350 #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
4351 mips_declare_object (STREAM, NAME, "\n\t.lcomm\t", ",%u\n", (SIZE))
4354 /* This says how to output an external. It would be possible not to
4355 output anything and let undefined symbol become external. However
4356 the assembler uses length information on externals to allocate in
4357 data/sdata bss/sbss, thereby saving exec time. */
4359 #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
4360 mips_output_external(STREAM,DECL,NAME)
4362 /* This says what to print at the end of the assembly file */
4364 #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
4367 /* Play switch file games if we're optimizing the global pointer. */
4370 #define TEXT_SECTION() \
4372 extern FILE *asm_out_text_file; \
4373 if (TARGET_FILE_SWITCHING) \
4374 asm_out_file = asm_out_text_file; \
4375 fputs (TEXT_SECTION_ASM_OP, asm_out_file); \
4376 fputc ('\n', asm_out_file); \
4380 /* This is how to declare a function name. The actual work of
4381 emitting the label is moved to function_prologue, so that we can
4382 get the line number correctly emitted before the .ent directive,
4383 and after any .file directives. Define as empty so that the function
4384 is not declared before the .ent directive elsewhere. */
4386 #undef ASM_DECLARE_FUNCTION_NAME
4387 #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL)
4390 /* This is how to output an internal numbered label where
4391 PREFIX is the class of label and NUM is the number within the class. */
4393 #undef ASM_OUTPUT_INTERNAL_LABEL
4394 #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
4395 fprintf (STREAM, "%s%s%d:\n", LOCAL_LABEL_PREFIX, PREFIX, NUM)
4397 /* This is how to store into the string LABEL
4398 the symbol_ref name of an internal numbered label where
4399 PREFIX is the class of label and NUM is the number within the class.
4400 This is suitable for output with `assemble_name'. */
4402 #undef ASM_GENERATE_INTERNAL_LABEL
4403 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
4404 sprintf ((LABEL), "*%s%s%ld", (LOCAL_LABEL_PREFIX), (PREFIX), (long)(NUM))
4406 /* This is how to output an element of a case-vector that is absolute. */
4408 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
4409 fprintf (STREAM, "\t%s\t%sL%d\n", \
4410 Pmode == DImode ? ".dword" : ".word", \
4411 LOCAL_LABEL_PREFIX, \
4414 /* This is how to output an element of a case-vector that is relative.
4415 This is used for pc-relative code (e.g. when TARGET_ABICALLS or
4416 TARGET_EMBEDDED_PIC). */
4418 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \
4420 if (TARGET_MIPS16) \
4421 fprintf (STREAM, "\t.half\t%sL%d-%sL%d\n", \
4422 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4423 else if (TARGET_EMBEDDED_PIC) \
4424 fprintf (STREAM, "\t%s\t%sL%d-%sLS%d\n", \
4425 Pmode == DImode ? ".dword" : ".word", \
4426 LOCAL_LABEL_PREFIX, VALUE, LOCAL_LABEL_PREFIX, REL); \
4427 else if (mips_abi == ABI_32 || mips_abi == ABI_O64) \
4428 fprintf (STREAM, "\t%s\t%sL%d\n", \
4429 Pmode == DImode ? ".gpdword" : ".gpword", \
4430 LOCAL_LABEL_PREFIX, VALUE); \
4432 fprintf (STREAM, "\t%s\t%sL%d\n", \
4433 Pmode == DImode ? ".dword" : ".word", \
4434 LOCAL_LABEL_PREFIX, VALUE); \
4437 /* When generating embedded PIC or mips16 code we want to put the jump
4438 table in the .text section. In all other cases, we want to put the
4439 jump table in the .rdata section. Unfortunately, we can't use
4440 JUMP_TABLES_IN_TEXT_SECTION, because it is not conditional.
4441 Instead, we use ASM_OUTPUT_CASE_LABEL to switch back to the .text
4442 section if appropriate. */
4443 #undef ASM_OUTPUT_CASE_LABEL
4444 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, INSN) \
4446 if (TARGET_EMBEDDED_PIC || TARGET_MIPS16) \
4447 function_section (current_function_decl); \
4448 ASM_OUTPUT_INTERNAL_LABEL (FILE, PREFIX, NUM); \
4451 /* This is how to output an assembler line
4452 that says to advance the location counter
4453 to a multiple of 2**LOG bytes. */
4455 #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
4456 fprintf (STREAM, "\t.align\t%d\n", (LOG))
4458 /* This is how to output an assembler line to advance the location
4459 counter by SIZE bytes. */
4461 #undef ASM_OUTPUT_SKIP
4462 #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
4463 fprintf (STREAM, "\t.space\t%u\n", (SIZE))
4465 /* This is how to output a string. */
4466 #undef ASM_OUTPUT_ASCII
4467 #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
4468 mips_output_ascii (STREAM, STRING, LEN)
4470 /* Output #ident as a in the read-only data section. */
4471 #undef ASM_OUTPUT_IDENT
4472 #define ASM_OUTPUT_IDENT(FILE, STRING) \
4474 const char *p = STRING; \
4475 int size = strlen (p) + 1; \
4476 readonly_data_section (); \
4477 assemble_string (p, size); \
4480 /* Default to -G 8 */
4481 #ifndef MIPS_DEFAULT_GVALUE
4482 #define MIPS_DEFAULT_GVALUE 8
4485 /* Define the strings to put out for each section in the object file. */
4486 #define TEXT_SECTION_ASM_OP "\t.text" /* instructions */
4487 #define DATA_SECTION_ASM_OP "\t.data" /* large data */
4488 #define SDATA_SECTION_ASM_OP "\t.sdata" /* small data */
4490 #undef READONLY_DATA_SECTION_ASM_OP
4491 #define READONLY_DATA_SECTION_ASM_OP "\t.rdata" /* read-only data */
4493 #define SMALL_DATA_SECTION sdata_section
4495 /* What other sections we support other than the normal .data/.text. */
4497 #undef EXTRA_SECTIONS
4498 #define EXTRA_SECTIONS in_sdata
4500 /* Define the additional functions to select our additional sections. */
4502 /* on the MIPS it is not a good idea to put constants in the text
4503 section, since this defeats the sdata/data mechanism. This is
4504 especially true when -O is used. In this case an effort is made to
4505 address with faster (gp) register relative addressing, which can
4506 only get at sdata and sbss items (there is no stext !!) However,
4507 if the constant is too large for sdata, and it's readonly, it
4508 will go into the .rdata section. */
4510 #undef EXTRA_SECTION_FUNCTIONS
4511 #define EXTRA_SECTION_FUNCTIONS \
4515 if (in_section != in_sdata) \
4517 fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
4518 in_section = in_sdata; \
4522 /* Given a decl node or constant node, choose the section to output it in
4523 and select that section. */
4525 #undef TARGET_ASM_SELECT_SECTION
4526 #define TARGET_ASM_SELECT_SECTION mips_select_section
4528 /* Store in OUTPUT a string (made with alloca) containing
4529 an assembler-name for a local static variable named NAME.
4530 LABELNO is an integer which is different for each call. */
4532 #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
4533 ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
4534 sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
4536 #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
4539 fprintf (STREAM, "\t%s\t%s,%s,8\n\t%s\t%s,0(%s)\n", \
4540 TARGET_64BIT ? "dsubu" : "subu", \
4541 reg_names[STACK_POINTER_REGNUM], \
4542 reg_names[STACK_POINTER_REGNUM], \
4543 TARGET_64BIT ? "sd" : "sw", \
4545 reg_names[STACK_POINTER_REGNUM]); \
4549 #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
4552 if (! set_noreorder) \
4553 fprintf (STREAM, "\t.set\tnoreorder\n"); \
4555 dslots_load_total++; \
4556 dslots_load_filled++; \
4557 fprintf (STREAM, "\t%s\t%s,0(%s)\n\t%s\t%s,%s,8\n", \
4558 TARGET_64BIT ? "ld" : "lw", \
4560 reg_names[STACK_POINTER_REGNUM], \
4561 TARGET_64BIT ? "daddu" : "addu", \
4562 reg_names[STACK_POINTER_REGNUM], \
4563 reg_names[STACK_POINTER_REGNUM]); \
4565 if (! set_noreorder) \
4566 fprintf (STREAM, "\t.set\treorder\n"); \
4570 /* How to start an assembler comment.
4571 The leading space is important (the mips native assembler requires it). */
4572 #ifndef ASM_COMMENT_START
4573 #define ASM_COMMENT_START " #"
4577 /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
4578 and mips-tdump.c to print them out.
4580 These must match the corresponding definitions in gdb/mipsread.c.
4581 Unfortunately, gcc and gdb do not currently share any directories. */
4583 #define CODE_MASK 0x8F300
4584 #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
4585 #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
4586 #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
4589 /* Default definitions for size_t and ptrdiff_t. */
4592 #define SIZE_TYPE (Pmode == DImode ? "long unsigned int" : "unsigned int")
4595 #ifndef PTRDIFF_TYPE
4596 #define PTRDIFF_TYPE (Pmode == DImode ? "long int" : "int")
4599 /* See mips_expand_prologue's use of loadgp for when this should be
4602 #define DONT_ACCESS_GBLS_AFTER_EPILOGUE (TARGET_ABICALLS \
4603 && mips_abi != ABI_32 \
4604 && mips_abi != ABI_O64)
4606 /* In mips16 mode, we need to look through the function to check for
4607 PC relative loads that are out of range. */
4608 #define MACHINE_DEPENDENT_REORG(X) machine_dependent_reorg (X)
4610 /* We need to use a special set of functions to handle hard floating
4611 point code in mips16 mode. */
4613 #ifndef INIT_SUBTARGET_OPTABS
4614 #define INIT_SUBTARGET_OPTABS
4617 #define INIT_TARGET_OPTABS \
4620 if (! TARGET_MIPS16 || ! mips16_hard_float) \
4621 INIT_SUBTARGET_OPTABS; \
4624 add_optab->handlers[(int) SFmode].libfunc = \
4625 init_one_libfunc ("__mips16_addsf3"); \
4626 sub_optab->handlers[(int) SFmode].libfunc = \
4627 init_one_libfunc ("__mips16_subsf3"); \
4628 smul_optab->handlers[(int) SFmode].libfunc = \
4629 init_one_libfunc ("__mips16_mulsf3"); \
4630 sdiv_optab->handlers[(int) SFmode].libfunc = \
4631 init_one_libfunc ("__mips16_divsf3"); \
4633 eqsf2_libfunc = init_one_libfunc ("__mips16_eqsf2"); \
4634 nesf2_libfunc = init_one_libfunc ("__mips16_nesf2"); \
4635 gtsf2_libfunc = init_one_libfunc ("__mips16_gtsf2"); \
4636 gesf2_libfunc = init_one_libfunc ("__mips16_gesf2"); \
4637 ltsf2_libfunc = init_one_libfunc ("__mips16_ltsf2"); \
4638 lesf2_libfunc = init_one_libfunc ("__mips16_lesf2"); \
4640 floatsisf_libfunc = \
4641 init_one_libfunc ("__mips16_floatsisf"); \
4643 init_one_libfunc ("__mips16_fixsfsi"); \
4645 if (TARGET_DOUBLE_FLOAT) \
4647 add_optab->handlers[(int) DFmode].libfunc = \
4648 init_one_libfunc ("__mips16_adddf3"); \
4649 sub_optab->handlers[(int) DFmode].libfunc = \
4650 init_one_libfunc ("__mips16_subdf3"); \
4651 smul_optab->handlers[(int) DFmode].libfunc = \
4652 init_one_libfunc ("__mips16_muldf3"); \
4653 sdiv_optab->handlers[(int) DFmode].libfunc = \
4654 init_one_libfunc ("__mips16_divdf3"); \
4656 extendsfdf2_libfunc = \
4657 init_one_libfunc ("__mips16_extendsfdf2"); \
4658 truncdfsf2_libfunc = \
4659 init_one_libfunc ("__mips16_truncdfsf2"); \
4662 init_one_libfunc ("__mips16_eqdf2"); \
4664 init_one_libfunc ("__mips16_nedf2"); \
4666 init_one_libfunc ("__mips16_gtdf2"); \
4668 init_one_libfunc ("__mips16_gedf2"); \
4670 init_one_libfunc ("__mips16_ltdf2"); \
4672 init_one_libfunc ("__mips16_ledf2"); \
4674 floatsidf_libfunc = \
4675 init_one_libfunc ("__mips16_floatsidf"); \
4677 init_one_libfunc ("__mips16_fixdfsi"); \
4683 #define DFMODE_NAN \
4684 unsigned short DFbignan[4] = {0x7ff7, 0xffff, 0xffff, 0xffff}; \
4685 unsigned short DFlittlenan[4] = {0xffff, 0xffff, 0xffff, 0xfff7}
4686 #define SFMODE_NAN \
4687 unsigned short SFbignan[2] = {0x7fbf, 0xffff}; \
4688 unsigned short SFlittlenan[2] = {0xffff, 0xffbf}
4690 /* Generate calls to memcpy, etc., not bcopy, etc. */
4691 #define TARGET_MEM_FUNCTIONS